Prepare v2019.07
[project/bcm63xx/u-boot.git] / lib / fdtdec.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 */
5
6 #ifndef USE_HOSTCC
7 #include <common.h>
8 #include <boot_fit.h>
9 #include <dm.h>
10 #include <dm/of_extra.h>
11 #include <errno.h>
12 #include <fdtdec.h>
13 #include <fdt_support.h>
14 #include <mapmem.h>
15 #include <linux/libfdt.h>
16 #include <serial.h>
17 #include <asm/sections.h>
18 #include <linux/ctype.h>
19 #include <linux/lzo.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 /*
24 * Here are the type we know about. One day we might allow drivers to
25 * register. For now we just put them here. The COMPAT macro allows us to
26 * turn this into a sparse list later, and keeps the ID with the name.
27 *
28 * NOTE: This list is basically a TODO list for things that need to be
29 * converted to driver model. So don't add new things here unless there is a
30 * good reason why driver-model conversion is infeasible. Examples include
31 * things which are used before driver model is available.
32 */
33 #define COMPAT(id, name) name
34 static const char * const compat_names[COMPAT_COUNT] = {
35 COMPAT(UNKNOWN, "<none>"),
36 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
37 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
38 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
39 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
40 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
41 COMPAT(SMSC_LAN9215, "smsc,lan9215"),
42 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
43 COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
44 COMPAT(SAMSUNG_EXYNOS5_USB3_PHY, "samsung,exynos5250-usb3-phy"),
45 COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
46 COMPAT(SAMSUNG_EXYNOS_MIPI_DSI, "samsung,exynos-mipi-dsi"),
47 COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"),
48 COMPAT(GENERIC_SPI_FLASH, "jedec,spi-nor"),
49 COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
50 COMPAT(INTEL_MICROCODE, "intel,microcode"),
51 COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
52 COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
53 COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
54 COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
55 COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
56 COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
57 COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
58 COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
59 COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
60 COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
61 COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"),
62 COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"),
63 COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"),
64 COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"),
65 COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"),
66 COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
67 COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
68 COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
69 COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init")
70 };
71
72 const char *fdtdec_get_compatible(enum fdt_compat_id id)
73 {
74 /* We allow reading of the 'unknown' ID for testing purposes */
75 assert(id >= 0 && id < COMPAT_COUNT);
76 return compat_names[id];
77 }
78
79 fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node,
80 const char *prop_name, int index, int na,
81 int ns, fdt_size_t *sizep,
82 bool translate)
83 {
84 const fdt32_t *prop, *prop_end;
85 const fdt32_t *prop_addr, *prop_size, *prop_after_size;
86 int len;
87 fdt_addr_t addr;
88
89 debug("%s: %s: ", __func__, prop_name);
90
91 prop = fdt_getprop(blob, node, prop_name, &len);
92 if (!prop) {
93 debug("(not found)\n");
94 return FDT_ADDR_T_NONE;
95 }
96 prop_end = prop + (len / sizeof(*prop));
97
98 prop_addr = prop + (index * (na + ns));
99 prop_size = prop_addr + na;
100 prop_after_size = prop_size + ns;
101 if (prop_after_size > prop_end) {
102 debug("(not enough data: expected >= %d cells, got %d cells)\n",
103 (u32)(prop_after_size - prop), ((u32)(prop_end - prop)));
104 return FDT_ADDR_T_NONE;
105 }
106
107 #if CONFIG_IS_ENABLED(OF_TRANSLATE)
108 if (translate)
109 addr = fdt_translate_address(blob, node, prop_addr);
110 else
111 #endif
112 addr = fdtdec_get_number(prop_addr, na);
113
114 if (sizep) {
115 *sizep = fdtdec_get_number(prop_size, ns);
116 debug("addr=%08llx, size=%llx\n", (unsigned long long)addr,
117 (unsigned long long)*sizep);
118 } else {
119 debug("addr=%08llx\n", (unsigned long long)addr);
120 }
121
122 return addr;
123 }
124
125 fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent,
126 int node, const char *prop_name,
127 int index, fdt_size_t *sizep,
128 bool translate)
129 {
130 int na, ns;
131
132 debug("%s: ", __func__);
133
134 na = fdt_address_cells(blob, parent);
135 if (na < 1) {
136 debug("(bad #address-cells)\n");
137 return FDT_ADDR_T_NONE;
138 }
139
140 ns = fdt_size_cells(blob, parent);
141 if (ns < 0) {
142 debug("(bad #size-cells)\n");
143 return FDT_ADDR_T_NONE;
144 }
145
146 debug("na=%d, ns=%d, ", na, ns);
147
148 return fdtdec_get_addr_size_fixed(blob, node, prop_name, index, na,
149 ns, sizep, translate);
150 }
151
152 fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node,
153 const char *prop_name, int index,
154 fdt_size_t *sizep,
155 bool translate)
156 {
157 int parent;
158
159 debug("%s: ", __func__);
160
161 parent = fdt_parent_offset(blob, node);
162 if (parent < 0) {
163 debug("(no parent found)\n");
164 return FDT_ADDR_T_NONE;
165 }
166
167 return fdtdec_get_addr_size_auto_parent(blob, parent, node, prop_name,
168 index, sizep, translate);
169 }
170
171 fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
172 const char *prop_name, fdt_size_t *sizep)
173 {
174 int ns = sizep ? (sizeof(fdt_size_t) / sizeof(fdt32_t)) : 0;
175
176 return fdtdec_get_addr_size_fixed(blob, node, prop_name, 0,
177 sizeof(fdt_addr_t) / sizeof(fdt32_t),
178 ns, sizep, false);
179 }
180
181 fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name)
182 {
183 return fdtdec_get_addr_size(blob, node, prop_name, NULL);
184 }
185
186 #if CONFIG_IS_ENABLED(PCI) && defined(CONFIG_DM_PCI)
187 int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type,
188 const char *prop_name, struct fdt_pci_addr *addr)
189 {
190 const u32 *cell;
191 int len;
192 int ret = -ENOENT;
193
194 debug("%s: %s: ", __func__, prop_name);
195
196 /*
197 * If we follow the pci bus bindings strictly, we should check
198 * the value of the node's parent node's #address-cells and
199 * #size-cells. They need to be 3 and 2 accordingly. However,
200 * for simplicity we skip the check here.
201 */
202 cell = fdt_getprop(blob, node, prop_name, &len);
203 if (!cell)
204 goto fail;
205
206 if ((len % FDT_PCI_REG_SIZE) == 0) {
207 int num = len / FDT_PCI_REG_SIZE;
208 int i;
209
210 for (i = 0; i < num; i++) {
211 debug("pci address #%d: %08lx %08lx %08lx\n", i,
212 (ulong)fdt32_to_cpu(cell[0]),
213 (ulong)fdt32_to_cpu(cell[1]),
214 (ulong)fdt32_to_cpu(cell[2]));
215 if ((fdt32_to_cpu(*cell) & type) == type) {
216 addr->phys_hi = fdt32_to_cpu(cell[0]);
217 addr->phys_mid = fdt32_to_cpu(cell[1]);
218 addr->phys_lo = fdt32_to_cpu(cell[1]);
219 break;
220 }
221
222 cell += (FDT_PCI_ADDR_CELLS +
223 FDT_PCI_SIZE_CELLS);
224 }
225
226 if (i == num) {
227 ret = -ENXIO;
228 goto fail;
229 }
230
231 return 0;
232 }
233
234 ret = -EINVAL;
235
236 fail:
237 debug("(not found)\n");
238 return ret;
239 }
240
241 int fdtdec_get_pci_vendev(const void *blob, int node, u16 *vendor, u16 *device)
242 {
243 const char *list, *end;
244 int len;
245
246 list = fdt_getprop(blob, node, "compatible", &len);
247 if (!list)
248 return -ENOENT;
249
250 end = list + len;
251 while (list < end) {
252 len = strlen(list);
253 if (len >= strlen("pciVVVV,DDDD")) {
254 char *s = strstr(list, "pci");
255
256 /*
257 * check if the string is something like pciVVVV,DDDD.RR
258 * or just pciVVVV,DDDD
259 */
260 if (s && s[7] == ',' &&
261 (s[12] == '.' || s[12] == 0)) {
262 s += 3;
263 *vendor = simple_strtol(s, NULL, 16);
264
265 s += 5;
266 *device = simple_strtol(s, NULL, 16);
267
268 return 0;
269 }
270 }
271 list += (len + 1);
272 }
273
274 return -ENOENT;
275 }
276
277 int fdtdec_get_pci_bar32(struct udevice *dev, struct fdt_pci_addr *addr,
278 u32 *bar)
279 {
280 int barnum;
281
282 /* extract the bar number from fdt_pci_addr */
283 barnum = addr->phys_hi & 0xff;
284 if (barnum < PCI_BASE_ADDRESS_0 || barnum > PCI_CARDBUS_CIS)
285 return -EINVAL;
286
287 barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
288 *bar = dm_pci_read_bar32(dev, barnum);
289
290 return 0;
291 }
292 #endif
293
294 uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
295 uint64_t default_val)
296 {
297 const uint64_t *cell64;
298 int length;
299
300 cell64 = fdt_getprop(blob, node, prop_name, &length);
301 if (!cell64 || length < sizeof(*cell64))
302 return default_val;
303
304 return fdt64_to_cpu(*cell64);
305 }
306
307 int fdtdec_get_is_enabled(const void *blob, int node)
308 {
309 const char *cell;
310
311 /*
312 * It should say "okay", so only allow that. Some fdts use "ok" but
313 * this is a bug. Please fix your device tree source file. See here
314 * for discussion:
315 *
316 * http://www.mail-archive.com/u-boot@lists.denx.de/msg71598.html
317 */
318 cell = fdt_getprop(blob, node, "status", NULL);
319 if (cell)
320 return strcmp(cell, "okay") == 0;
321 return 1;
322 }
323
324 enum fdt_compat_id fdtdec_lookup(const void *blob, int node)
325 {
326 enum fdt_compat_id id;
327
328 /* Search our drivers */
329 for (id = COMPAT_UNKNOWN; id < COMPAT_COUNT; id++)
330 if (fdt_node_check_compatible(blob, node,
331 compat_names[id]) == 0)
332 return id;
333 return COMPAT_UNKNOWN;
334 }
335
336 int fdtdec_next_compatible(const void *blob, int node, enum fdt_compat_id id)
337 {
338 return fdt_node_offset_by_compatible(blob, node, compat_names[id]);
339 }
340
341 int fdtdec_next_compatible_subnode(const void *blob, int node,
342 enum fdt_compat_id id, int *depthp)
343 {
344 do {
345 node = fdt_next_node(blob, node, depthp);
346 } while (*depthp > 1);
347
348 /* If this is a direct subnode, and compatible, return it */
349 if (*depthp == 1 && 0 == fdt_node_check_compatible(
350 blob, node, compat_names[id]))
351 return node;
352
353 return -FDT_ERR_NOTFOUND;
354 }
355
356 int fdtdec_next_alias(const void *blob, const char *name, enum fdt_compat_id id,
357 int *upto)
358 {
359 #define MAX_STR_LEN 20
360 char str[MAX_STR_LEN + 20];
361 int node, err;
362
363 /* snprintf() is not available */
364 assert(strlen(name) < MAX_STR_LEN);
365 sprintf(str, "%.*s%d", MAX_STR_LEN, name, *upto);
366 node = fdt_path_offset(blob, str);
367 if (node < 0)
368 return node;
369 err = fdt_node_check_compatible(blob, node, compat_names[id]);
370 if (err < 0)
371 return err;
372 if (err)
373 return -FDT_ERR_NOTFOUND;
374 (*upto)++;
375 return node;
376 }
377
378 int fdtdec_find_aliases_for_id(const void *blob, const char *name,
379 enum fdt_compat_id id, int *node_list,
380 int maxcount)
381 {
382 memset(node_list, '\0', sizeof(*node_list) * maxcount);
383
384 return fdtdec_add_aliases_for_id(blob, name, id, node_list, maxcount);
385 }
386
387 /* TODO: Can we tighten this code up a little? */
388 int fdtdec_add_aliases_for_id(const void *blob, const char *name,
389 enum fdt_compat_id id, int *node_list,
390 int maxcount)
391 {
392 int name_len = strlen(name);
393 int nodes[maxcount];
394 int num_found = 0;
395 int offset, node;
396 int alias_node;
397 int count;
398 int i, j;
399
400 /* find the alias node if present */
401 alias_node = fdt_path_offset(blob, "/aliases");
402
403 /*
404 * start with nothing, and we can assume that the root node can't
405 * match
406 */
407 memset(nodes, '\0', sizeof(nodes));
408
409 /* First find all the compatible nodes */
410 for (node = count = 0; node >= 0 && count < maxcount;) {
411 node = fdtdec_next_compatible(blob, node, id);
412 if (node >= 0)
413 nodes[count++] = node;
414 }
415 if (node >= 0)
416 debug("%s: warning: maxcount exceeded with alias '%s'\n",
417 __func__, name);
418
419 /* Now find all the aliases */
420 for (offset = fdt_first_property_offset(blob, alias_node);
421 offset > 0;
422 offset = fdt_next_property_offset(blob, offset)) {
423 const struct fdt_property *prop;
424 const char *path;
425 int number;
426 int found;
427
428 node = 0;
429 prop = fdt_get_property_by_offset(blob, offset, NULL);
430 path = fdt_string(blob, fdt32_to_cpu(prop->nameoff));
431 if (prop->len && 0 == strncmp(path, name, name_len))
432 node = fdt_path_offset(blob, prop->data);
433 if (node <= 0)
434 continue;
435
436 /* Get the alias number */
437 number = simple_strtoul(path + name_len, NULL, 10);
438 if (number < 0 || number >= maxcount) {
439 debug("%s: warning: alias '%s' is out of range\n",
440 __func__, path);
441 continue;
442 }
443
444 /* Make sure the node we found is actually in our list! */
445 found = -1;
446 for (j = 0; j < count; j++)
447 if (nodes[j] == node) {
448 found = j;
449 break;
450 }
451
452 if (found == -1) {
453 debug("%s: warning: alias '%s' points to a node "
454 "'%s' that is missing or is not compatible "
455 " with '%s'\n", __func__, path,
456 fdt_get_name(blob, node, NULL),
457 compat_names[id]);
458 continue;
459 }
460
461 /*
462 * Add this node to our list in the right place, and mark
463 * it as done.
464 */
465 if (fdtdec_get_is_enabled(blob, node)) {
466 if (node_list[number]) {
467 debug("%s: warning: alias '%s' requires that "
468 "a node be placed in the list in a "
469 "position which is already filled by "
470 "node '%s'\n", __func__, path,
471 fdt_get_name(blob, node, NULL));
472 continue;
473 }
474 node_list[number] = node;
475 if (number >= num_found)
476 num_found = number + 1;
477 }
478 nodes[found] = 0;
479 }
480
481 /* Add any nodes not mentioned by an alias */
482 for (i = j = 0; i < maxcount; i++) {
483 if (!node_list[i]) {
484 for (; j < maxcount; j++)
485 if (nodes[j] &&
486 fdtdec_get_is_enabled(blob, nodes[j]))
487 break;
488
489 /* Have we run out of nodes to add? */
490 if (j == maxcount)
491 break;
492
493 assert(!node_list[i]);
494 node_list[i] = nodes[j++];
495 if (i >= num_found)
496 num_found = i + 1;
497 }
498 }
499
500 return num_found;
501 }
502
503 int fdtdec_get_alias_seq(const void *blob, const char *base, int offset,
504 int *seqp)
505 {
506 int base_len = strlen(base);
507 const char *find_name;
508 int find_namelen;
509 int prop_offset;
510 int aliases;
511
512 find_name = fdt_get_name(blob, offset, &find_namelen);
513 debug("Looking for '%s' at %d, name %s\n", base, offset, find_name);
514
515 aliases = fdt_path_offset(blob, "/aliases");
516 for (prop_offset = fdt_first_property_offset(blob, aliases);
517 prop_offset > 0;
518 prop_offset = fdt_next_property_offset(blob, prop_offset)) {
519 const char *prop;
520 const char *name;
521 const char *slash;
522 int len, val;
523
524 prop = fdt_getprop_by_offset(blob, prop_offset, &name, &len);
525 debug(" - %s, %s\n", name, prop);
526 if (len < find_namelen || *prop != '/' || prop[len - 1] ||
527 strncmp(name, base, base_len))
528 continue;
529
530 slash = strrchr(prop, '/');
531 if (strcmp(slash + 1, find_name))
532 continue;
533 val = trailing_strtol(name);
534 if (val != -1) {
535 *seqp = val;
536 debug("Found seq %d\n", *seqp);
537 return 0;
538 }
539 }
540
541 debug("Not found\n");
542 return -ENOENT;
543 }
544
545 int fdtdec_get_alias_highest_id(const void *blob, const char *base)
546 {
547 int base_len = strlen(base);
548 int prop_offset;
549 int aliases;
550 int max = -1;
551
552 debug("Looking for highest alias id for '%s'\n", base);
553
554 aliases = fdt_path_offset(blob, "/aliases");
555 for (prop_offset = fdt_first_property_offset(blob, aliases);
556 prop_offset > 0;
557 prop_offset = fdt_next_property_offset(blob, prop_offset)) {
558 const char *prop;
559 const char *name;
560 int len, val;
561
562 prop = fdt_getprop_by_offset(blob, prop_offset, &name, &len);
563 debug(" - %s, %s\n", name, prop);
564 if (*prop != '/' || prop[len - 1] ||
565 strncmp(name, base, base_len))
566 continue;
567
568 val = trailing_strtol(name);
569 if (val > max) {
570 debug("Found seq %d\n", val);
571 max = val;
572 }
573 }
574
575 return max;
576 }
577
578 const char *fdtdec_get_chosen_prop(const void *blob, const char *name)
579 {
580 int chosen_node;
581
582 if (!blob)
583 return NULL;
584 chosen_node = fdt_path_offset(blob, "/chosen");
585 return fdt_getprop(blob, chosen_node, name, NULL);
586 }
587
588 int fdtdec_get_chosen_node(const void *blob, const char *name)
589 {
590 const char *prop;
591
592 prop = fdtdec_get_chosen_prop(blob, name);
593 if (!prop)
594 return -FDT_ERR_NOTFOUND;
595 return fdt_path_offset(blob, prop);
596 }
597
598 int fdtdec_check_fdt(void)
599 {
600 /*
601 * We must have an FDT, but we cannot panic() yet since the console
602 * is not ready. So for now, just assert(). Boards which need an early
603 * FDT (prior to console ready) will need to make their own
604 * arrangements and do their own checks.
605 */
606 assert(!fdtdec_prepare_fdt());
607 return 0;
608 }
609
610 /*
611 * This function is a little odd in that it accesses global data. At some
612 * point if the architecture board.c files merge this will make more sense.
613 * Even now, it is common code.
614 */
615 int fdtdec_prepare_fdt(void)
616 {
617 if (!gd->fdt_blob || ((uintptr_t)gd->fdt_blob & 3) ||
618 fdt_check_header(gd->fdt_blob)) {
619 #ifdef CONFIG_SPL_BUILD
620 puts("Missing DTB\n");
621 #else
622 puts("No valid device tree binary found - please append one to U-Boot binary, use u-boot-dtb.bin or define CONFIG_OF_EMBED. For sandbox, use -d <file.dtb>\n");
623 # ifdef DEBUG
624 if (gd->fdt_blob) {
625 printf("fdt_blob=%p\n", gd->fdt_blob);
626 print_buffer((ulong)gd->fdt_blob, gd->fdt_blob, 4,
627 32, 0);
628 }
629 # endif
630 #endif
631 return -1;
632 }
633 return 0;
634 }
635
636 int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name)
637 {
638 const u32 *phandle;
639 int lookup;
640
641 debug("%s: %s\n", __func__, prop_name);
642 phandle = fdt_getprop(blob, node, prop_name, NULL);
643 if (!phandle)
644 return -FDT_ERR_NOTFOUND;
645
646 lookup = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*phandle));
647 return lookup;
648 }
649
650 /**
651 * Look up a property in a node and check that it has a minimum length.
652 *
653 * @param blob FDT blob
654 * @param node node to examine
655 * @param prop_name name of property to find
656 * @param min_len minimum property length in bytes
657 * @param err 0 if ok, or -FDT_ERR_NOTFOUND if the property is not
658 found, or -FDT_ERR_BADLAYOUT if not enough data
659 * @return pointer to cell, which is only valid if err == 0
660 */
661 static const void *get_prop_check_min_len(const void *blob, int node,
662 const char *prop_name, int min_len,
663 int *err)
664 {
665 const void *cell;
666 int len;
667
668 debug("%s: %s\n", __func__, prop_name);
669 cell = fdt_getprop(blob, node, prop_name, &len);
670 if (!cell)
671 *err = -FDT_ERR_NOTFOUND;
672 else if (len < min_len)
673 *err = -FDT_ERR_BADLAYOUT;
674 else
675 *err = 0;
676 return cell;
677 }
678
679 int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
680 u32 *array, int count)
681 {
682 const u32 *cell;
683 int err = 0;
684
685 debug("%s: %s\n", __func__, prop_name);
686 cell = get_prop_check_min_len(blob, node, prop_name,
687 sizeof(u32) * count, &err);
688 if (!err) {
689 int i;
690
691 for (i = 0; i < count; i++)
692 array[i] = fdt32_to_cpu(cell[i]);
693 }
694 return err;
695 }
696
697 int fdtdec_get_int_array_count(const void *blob, int node,
698 const char *prop_name, u32 *array, int count)
699 {
700 const u32 *cell;
701 int len, elems;
702 int i;
703
704 debug("%s: %s\n", __func__, prop_name);
705 cell = fdt_getprop(blob, node, prop_name, &len);
706 if (!cell)
707 return -FDT_ERR_NOTFOUND;
708 elems = len / sizeof(u32);
709 if (count > elems)
710 count = elems;
711 for (i = 0; i < count; i++)
712 array[i] = fdt32_to_cpu(cell[i]);
713
714 return count;
715 }
716
717 const u32 *fdtdec_locate_array(const void *blob, int node,
718 const char *prop_name, int count)
719 {
720 const u32 *cell;
721 int err;
722
723 cell = get_prop_check_min_len(blob, node, prop_name,
724 sizeof(u32) * count, &err);
725 return err ? NULL : cell;
726 }
727
728 int fdtdec_get_bool(const void *blob, int node, const char *prop_name)
729 {
730 const s32 *cell;
731 int len;
732
733 debug("%s: %s\n", __func__, prop_name);
734 cell = fdt_getprop(blob, node, prop_name, &len);
735 return cell != NULL;
736 }
737
738 int fdtdec_parse_phandle_with_args(const void *blob, int src_node,
739 const char *list_name,
740 const char *cells_name,
741 int cell_count, int index,
742 struct fdtdec_phandle_args *out_args)
743 {
744 const __be32 *list, *list_end;
745 int rc = 0, size, cur_index = 0;
746 uint32_t count = 0;
747 int node = -1;
748 int phandle;
749
750 /* Retrieve the phandle list property */
751 list = fdt_getprop(blob, src_node, list_name, &size);
752 if (!list)
753 return -ENOENT;
754 list_end = list + size / sizeof(*list);
755
756 /* Loop over the phandles until all the requested entry is found */
757 while (list < list_end) {
758 rc = -EINVAL;
759 count = 0;
760
761 /*
762 * If phandle is 0, then it is an empty entry with no
763 * arguments. Skip forward to the next entry.
764 */
765 phandle = be32_to_cpup(list++);
766 if (phandle) {
767 /*
768 * Find the provider node and parse the #*-cells
769 * property to determine the argument length.
770 *
771 * This is not needed if the cell count is hard-coded
772 * (i.e. cells_name not set, but cell_count is set),
773 * except when we're going to return the found node
774 * below.
775 */
776 if (cells_name || cur_index == index) {
777 node = fdt_node_offset_by_phandle(blob,
778 phandle);
779 if (!node) {
780 debug("%s: could not find phandle\n",
781 fdt_get_name(blob, src_node,
782 NULL));
783 goto err;
784 }
785 }
786
787 if (cells_name) {
788 count = fdtdec_get_int(blob, node, cells_name,
789 -1);
790 if (count == -1) {
791 debug("%s: could not get %s for %s\n",
792 fdt_get_name(blob, src_node,
793 NULL),
794 cells_name,
795 fdt_get_name(blob, node,
796 NULL));
797 goto err;
798 }
799 } else {
800 count = cell_count;
801 }
802
803 /*
804 * Make sure that the arguments actually fit in the
805 * remaining property data length
806 */
807 if (list + count > list_end) {
808 debug("%s: arguments longer than property\n",
809 fdt_get_name(blob, src_node, NULL));
810 goto err;
811 }
812 }
813
814 /*
815 * All of the error cases above bail out of the loop, so at
816 * this point, the parsing is successful. If the requested
817 * index matches, then fill the out_args structure and return,
818 * or return -ENOENT for an empty entry.
819 */
820 rc = -ENOENT;
821 if (cur_index == index) {
822 if (!phandle)
823 goto err;
824
825 if (out_args) {
826 int i;
827
828 if (count > MAX_PHANDLE_ARGS) {
829 debug("%s: too many arguments %d\n",
830 fdt_get_name(blob, src_node,
831 NULL), count);
832 count = MAX_PHANDLE_ARGS;
833 }
834 out_args->node = node;
835 out_args->args_count = count;
836 for (i = 0; i < count; i++) {
837 out_args->args[i] =
838 be32_to_cpup(list++);
839 }
840 }
841
842 /* Found it! return success */
843 return 0;
844 }
845
846 node = -1;
847 list += count;
848 cur_index++;
849 }
850
851 /*
852 * Result will be one of:
853 * -ENOENT : index is for empty phandle
854 * -EINVAL : parsing error on data
855 * [1..n] : Number of phandle (count mode; when index = -1)
856 */
857 rc = index < 0 ? cur_index : -ENOENT;
858 err:
859 return rc;
860 }
861
862 int fdtdec_get_child_count(const void *blob, int node)
863 {
864 int subnode;
865 int num = 0;
866
867 fdt_for_each_subnode(subnode, blob, node)
868 num++;
869
870 return num;
871 }
872
873 int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
874 u8 *array, int count)
875 {
876 const u8 *cell;
877 int err;
878
879 cell = get_prop_check_min_len(blob, node, prop_name, count, &err);
880 if (!err)
881 memcpy(array, cell, count);
882 return err;
883 }
884
885 const u8 *fdtdec_locate_byte_array(const void *blob, int node,
886 const char *prop_name, int count)
887 {
888 const u8 *cell;
889 int err;
890
891 cell = get_prop_check_min_len(blob, node, prop_name, count, &err);
892 if (err)
893 return NULL;
894 return cell;
895 }
896
897 int fdtdec_get_config_int(const void *blob, const char *prop_name,
898 int default_val)
899 {
900 int config_node;
901
902 debug("%s: %s\n", __func__, prop_name);
903 config_node = fdt_path_offset(blob, "/config");
904 if (config_node < 0)
905 return default_val;
906 return fdtdec_get_int(blob, config_node, prop_name, default_val);
907 }
908
909 int fdtdec_get_config_bool(const void *blob, const char *prop_name)
910 {
911 int config_node;
912 const void *prop;
913
914 debug("%s: %s\n", __func__, prop_name);
915 config_node = fdt_path_offset(blob, "/config");
916 if (config_node < 0)
917 return 0;
918 prop = fdt_get_property(blob, config_node, prop_name, NULL);
919
920 return prop != NULL;
921 }
922
923 char *fdtdec_get_config_string(const void *blob, const char *prop_name)
924 {
925 const char *nodep;
926 int nodeoffset;
927 int len;
928
929 debug("%s: %s\n", __func__, prop_name);
930 nodeoffset = fdt_path_offset(blob, "/config");
931 if (nodeoffset < 0)
932 return NULL;
933
934 nodep = fdt_getprop(blob, nodeoffset, prop_name, &len);
935 if (!nodep)
936 return NULL;
937
938 return (char *)nodep;
939 }
940
941 u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells)
942 {
943 u64 number = 0;
944
945 while (cells--)
946 number = (number << 32) | fdt32_to_cpu(*ptr++);
947
948 return number;
949 }
950
951 int fdt_get_resource(const void *fdt, int node, const char *property,
952 unsigned int index, struct fdt_resource *res)
953 {
954 const fdt32_t *ptr, *end;
955 int na, ns, len, parent;
956 unsigned int i = 0;
957
958 parent = fdt_parent_offset(fdt, node);
959 if (parent < 0)
960 return parent;
961
962 na = fdt_address_cells(fdt, parent);
963 ns = fdt_size_cells(fdt, parent);
964
965 ptr = fdt_getprop(fdt, node, property, &len);
966 if (!ptr)
967 return len;
968
969 end = ptr + len / sizeof(*ptr);
970
971 while (ptr + na + ns <= end) {
972 if (i == index) {
973 res->start = fdtdec_get_number(ptr, na);
974 res->end = res->start;
975 res->end += fdtdec_get_number(&ptr[na], ns) - 1;
976 return 0;
977 }
978
979 ptr += na + ns;
980 i++;
981 }
982
983 return -FDT_ERR_NOTFOUND;
984 }
985
986 int fdt_get_named_resource(const void *fdt, int node, const char *property,
987 const char *prop_names, const char *name,
988 struct fdt_resource *res)
989 {
990 int index;
991
992 index = fdt_stringlist_search(fdt, node, prop_names, name);
993 if (index < 0)
994 return index;
995
996 return fdt_get_resource(fdt, node, property, index, res);
997 }
998
999 static int decode_timing_property(const void *blob, int node, const char *name,
1000 struct timing_entry *result)
1001 {
1002 int length, ret = 0;
1003 const u32 *prop;
1004
1005 prop = fdt_getprop(blob, node, name, &length);
1006 if (!prop) {
1007 debug("%s: could not find property %s\n",
1008 fdt_get_name(blob, node, NULL), name);
1009 return length;
1010 }
1011
1012 if (length == sizeof(u32)) {
1013 result->typ = fdtdec_get_int(blob, node, name, 0);
1014 result->min = result->typ;
1015 result->max = result->typ;
1016 } else {
1017 ret = fdtdec_get_int_array(blob, node, name, &result->min, 3);
1018 }
1019
1020 return ret;
1021 }
1022
1023 int fdtdec_decode_display_timing(const void *blob, int parent, int index,
1024 struct display_timing *dt)
1025 {
1026 int i, node, timings_node;
1027 u32 val = 0;
1028 int ret = 0;
1029
1030 timings_node = fdt_subnode_offset(blob, parent, "display-timings");
1031 if (timings_node < 0)
1032 return timings_node;
1033
1034 for (i = 0, node = fdt_first_subnode(blob, timings_node);
1035 node > 0 && i != index;
1036 node = fdt_next_subnode(blob, node))
1037 i++;
1038
1039 if (node < 0)
1040 return node;
1041
1042 memset(dt, 0, sizeof(*dt));
1043
1044 ret |= decode_timing_property(blob, node, "hback-porch",
1045 &dt->hback_porch);
1046 ret |= decode_timing_property(blob, node, "hfront-porch",
1047 &dt->hfront_porch);
1048 ret |= decode_timing_property(blob, node, "hactive", &dt->hactive);
1049 ret |= decode_timing_property(blob, node, "hsync-len", &dt->hsync_len);
1050 ret |= decode_timing_property(blob, node, "vback-porch",
1051 &dt->vback_porch);
1052 ret |= decode_timing_property(blob, node, "vfront-porch",
1053 &dt->vfront_porch);
1054 ret |= decode_timing_property(blob, node, "vactive", &dt->vactive);
1055 ret |= decode_timing_property(blob, node, "vsync-len", &dt->vsync_len);
1056 ret |= decode_timing_property(blob, node, "clock-frequency",
1057 &dt->pixelclock);
1058
1059 dt->flags = 0;
1060 val = fdtdec_get_int(blob, node, "vsync-active", -1);
1061 if (val != -1) {
1062 dt->flags |= val ? DISPLAY_FLAGS_VSYNC_HIGH :
1063 DISPLAY_FLAGS_VSYNC_LOW;
1064 }
1065 val = fdtdec_get_int(blob, node, "hsync-active", -1);
1066 if (val != -1) {
1067 dt->flags |= val ? DISPLAY_FLAGS_HSYNC_HIGH :
1068 DISPLAY_FLAGS_HSYNC_LOW;
1069 }
1070 val = fdtdec_get_int(blob, node, "de-active", -1);
1071 if (val != -1) {
1072 dt->flags |= val ? DISPLAY_FLAGS_DE_HIGH :
1073 DISPLAY_FLAGS_DE_LOW;
1074 }
1075 val = fdtdec_get_int(blob, node, "pixelclk-active", -1);
1076 if (val != -1) {
1077 dt->flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE :
1078 DISPLAY_FLAGS_PIXDATA_NEGEDGE;
1079 }
1080
1081 if (fdtdec_get_bool(blob, node, "interlaced"))
1082 dt->flags |= DISPLAY_FLAGS_INTERLACED;
1083 if (fdtdec_get_bool(blob, node, "doublescan"))
1084 dt->flags |= DISPLAY_FLAGS_DOUBLESCAN;
1085 if (fdtdec_get_bool(blob, node, "doubleclk"))
1086 dt->flags |= DISPLAY_FLAGS_DOUBLECLK;
1087
1088 return ret;
1089 }
1090
1091 int fdtdec_setup_mem_size_base_fdt(const void *blob)
1092 {
1093 int ret, mem;
1094 struct fdt_resource res;
1095
1096 mem = fdt_path_offset(blob, "/memory");
1097 if (mem < 0) {
1098 debug("%s: Missing /memory node\n", __func__);
1099 return -EINVAL;
1100 }
1101
1102 ret = fdt_get_resource(blob, mem, "reg", 0, &res);
1103 if (ret != 0) {
1104 debug("%s: Unable to decode first memory bank\n", __func__);
1105 return -EINVAL;
1106 }
1107
1108 gd->ram_size = (phys_size_t)(res.end - res.start + 1);
1109 gd->ram_base = (unsigned long)res.start;
1110 debug("%s: Initial DRAM size %llx\n", __func__,
1111 (unsigned long long)gd->ram_size);
1112
1113 return 0;
1114 }
1115
1116 int fdtdec_setup_mem_size_base(void)
1117 {
1118 return fdtdec_setup_mem_size_base_fdt(gd->fdt_blob);
1119 }
1120
1121 #if defined(CONFIG_NR_DRAM_BANKS)
1122
1123 static int get_next_memory_node(const void *blob, int mem)
1124 {
1125 do {
1126 mem = fdt_node_offset_by_prop_value(blob, mem,
1127 "device_type", "memory", 7);
1128 } while (!fdtdec_get_is_enabled(blob, mem));
1129
1130 return mem;
1131 }
1132
1133 int fdtdec_setup_memory_banksize_fdt(const void *blob)
1134 {
1135 int bank, ret, mem, reg = 0;
1136 struct fdt_resource res;
1137
1138 mem = get_next_memory_node(blob, -1);
1139 if (mem < 0) {
1140 debug("%s: Missing /memory node\n", __func__);
1141 return -EINVAL;
1142 }
1143
1144 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
1145 ret = fdt_get_resource(blob, mem, "reg", reg++, &res);
1146 if (ret == -FDT_ERR_NOTFOUND) {
1147 reg = 0;
1148 mem = get_next_memory_node(blob, mem);
1149 if (mem == -FDT_ERR_NOTFOUND)
1150 break;
1151
1152 ret = fdt_get_resource(blob, mem, "reg", reg++, &res);
1153 if (ret == -FDT_ERR_NOTFOUND)
1154 break;
1155 }
1156 if (ret != 0) {
1157 return -EINVAL;
1158 }
1159
1160 gd->bd->bi_dram[bank].start = (phys_addr_t)res.start;
1161 gd->bd->bi_dram[bank].size =
1162 (phys_size_t)(res.end - res.start + 1);
1163
1164 debug("%s: DRAM Bank #%d: start = 0x%llx, size = 0x%llx\n",
1165 __func__, bank,
1166 (unsigned long long)gd->bd->bi_dram[bank].start,
1167 (unsigned long long)gd->bd->bi_dram[bank].size);
1168 }
1169
1170 return 0;
1171 }
1172
1173 int fdtdec_setup_memory_banksize(void)
1174 {
1175 return fdtdec_setup_memory_banksize_fdt(gd->fdt_blob);
1176
1177 }
1178 #endif
1179
1180 #if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
1181 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT_GZIP) ||\
1182 CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO)
1183 static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
1184 {
1185 size_t sz_out = CONFIG_VAL(MULTI_DTB_FIT_UNCOMPRESS_SZ);
1186 bool gzip = 0, lzo = 0;
1187 ulong sz_in = sz_src;
1188 void *dst;
1189 int rc;
1190
1191 if (CONFIG_IS_ENABLED(GZIP))
1192 if (gzip_parse_header(src, sz_in) >= 0)
1193 gzip = 1;
1194 if (CONFIG_IS_ENABLED(LZO))
1195 if (!gzip && lzop_is_valid_header(src))
1196 lzo = 1;
1197
1198 if (!gzip && !lzo)
1199 return -EBADMSG;
1200
1201
1202 if (CONFIG_IS_ENABLED(MULTI_DTB_FIT_DYN_ALLOC)) {
1203 dst = malloc(sz_out);
1204 if (!dst) {
1205 puts("uncompress_blob: Unable to allocate memory\n");
1206 return -ENOMEM;
1207 }
1208 } else {
1209 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT_USER_DEFINED_AREA)
1210 dst = (void *)CONFIG_VAL(MULTI_DTB_FIT_USER_DEF_ADDR);
1211 # else
1212 return -ENOTSUPP;
1213 # endif
1214 }
1215
1216 if (CONFIG_IS_ENABLED(GZIP) && gzip)
1217 rc = gunzip(dst, sz_out, (u8 *)src, &sz_in);
1218 else if (CONFIG_IS_ENABLED(LZO) && lzo)
1219 rc = lzop_decompress(src, sz_in, dst, &sz_out);
1220 else
1221 hang();
1222
1223 if (rc < 0) {
1224 /* not a valid compressed blob */
1225 puts("uncompress_blob: Unable to uncompress\n");
1226 if (CONFIG_IS_ENABLED(MULTI_DTB_FIT_DYN_ALLOC))
1227 free(dst);
1228 return -EBADMSG;
1229 }
1230 *dstp = dst;
1231 return 0;
1232 }
1233 # else
1234 static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
1235 {
1236 *dstp = (void *)src;
1237 return 0;
1238 }
1239 # endif
1240 #endif
1241
1242 #if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
1243 /*
1244 * For CONFIG_OF_SEPARATE, the board may optionally implement this to
1245 * provide and/or fixup the fdt.
1246 */
1247 __weak void *board_fdt_blob_setup(void)
1248 {
1249 void *fdt_blob = NULL;
1250 #ifdef CONFIG_SPL_BUILD
1251 /* FDT is at end of BSS unless it is in a different memory region */
1252 if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
1253 fdt_blob = (ulong *)&_image_binary_end;
1254 else
1255 fdt_blob = (ulong *)&__bss_end;
1256 #else
1257 /* FDT is at end of image */
1258 fdt_blob = (ulong *)&_end;
1259 #endif
1260 return fdt_blob;
1261 }
1262 #endif
1263
1264 int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size)
1265 {
1266 const char *path;
1267 int offset, err;
1268
1269 if (!is_valid_ethaddr(mac))
1270 return -EINVAL;
1271
1272 path = fdt_get_alias(fdt, "ethernet");
1273 if (!path)
1274 return 0;
1275
1276 debug("ethernet alias found: %s\n", path);
1277
1278 offset = fdt_path_offset(fdt, path);
1279 if (offset < 0) {
1280 debug("ethernet alias points to absent node %s\n", path);
1281 return -ENOENT;
1282 }
1283
1284 err = fdt_setprop_inplace(fdt, offset, "local-mac-address", mac, size);
1285 if (err < 0)
1286 return err;
1287
1288 debug("MAC address: %pM\n", mac);
1289
1290 return 0;
1291 }
1292
1293 static int fdtdec_init_reserved_memory(void *blob)
1294 {
1295 int na, ns, node, err;
1296 fdt32_t value;
1297
1298 /* inherit #address-cells and #size-cells from the root node */
1299 na = fdt_address_cells(blob, 0);
1300 ns = fdt_size_cells(blob, 0);
1301
1302 node = fdt_add_subnode(blob, 0, "reserved-memory");
1303 if (node < 0)
1304 return node;
1305
1306 err = fdt_setprop(blob, node, "ranges", NULL, 0);
1307 if (err < 0)
1308 return err;
1309
1310 value = cpu_to_fdt32(ns);
1311
1312 err = fdt_setprop(blob, node, "#size-cells", &value, sizeof(value));
1313 if (err < 0)
1314 return err;
1315
1316 value = cpu_to_fdt32(na);
1317
1318 err = fdt_setprop(blob, node, "#address-cells", &value, sizeof(value));
1319 if (err < 0)
1320 return err;
1321
1322 return node;
1323 }
1324
1325 int fdtdec_add_reserved_memory(void *blob, const char *basename,
1326 const struct fdt_memory *carveout,
1327 uint32_t *phandlep)
1328 {
1329 fdt32_t cells[4] = {}, *ptr = cells;
1330 uint32_t upper, lower, phandle;
1331 int parent, node, na, ns, err;
1332 fdt_size_t size;
1333 char name[64];
1334
1335 /* create an empty /reserved-memory node if one doesn't exist */
1336 parent = fdt_path_offset(blob, "/reserved-memory");
1337 if (parent < 0) {
1338 parent = fdtdec_init_reserved_memory(blob);
1339 if (parent < 0)
1340 return parent;
1341 }
1342
1343 /* only 1 or 2 #address-cells and #size-cells are supported */
1344 na = fdt_address_cells(blob, parent);
1345 if (na < 1 || na > 2)
1346 return -FDT_ERR_BADNCELLS;
1347
1348 ns = fdt_size_cells(blob, parent);
1349 if (ns < 1 || ns > 2)
1350 return -FDT_ERR_BADNCELLS;
1351
1352 /* find a matching node and return the phandle to that */
1353 fdt_for_each_subnode(node, blob, parent) {
1354 const char *name = fdt_get_name(blob, node, NULL);
1355 phys_addr_t addr, size;
1356
1357 addr = fdtdec_get_addr_size(blob, node, "reg", &size);
1358 if (addr == FDT_ADDR_T_NONE) {
1359 debug("failed to read address/size for %s\n", name);
1360 continue;
1361 }
1362
1363 if (addr == carveout->start && (addr + size) == carveout->end) {
1364 *phandlep = fdt_get_phandle(blob, node);
1365 return 0;
1366 }
1367 }
1368
1369 /*
1370 * Unpack the start address and generate the name of the new node
1371 * base on the basename and the unit-address.
1372 */
1373 upper = upper_32_bits(carveout->start);
1374 lower = lower_32_bits(carveout->start);
1375
1376 if (na > 1 && upper > 0)
1377 snprintf(name, sizeof(name), "%s@%x,%x", basename, upper,
1378 lower);
1379 else {
1380 if (upper > 0) {
1381 debug("address %08x:%08x exceeds addressable space\n",
1382 upper, lower);
1383 return -FDT_ERR_BADVALUE;
1384 }
1385
1386 snprintf(name, sizeof(name), "%s@%x", basename, lower);
1387 }
1388
1389 node = fdt_add_subnode(blob, parent, name);
1390 if (node < 0)
1391 return node;
1392
1393 err = fdt_generate_phandle(blob, &phandle);
1394 if (err < 0)
1395 return err;
1396
1397 err = fdtdec_set_phandle(blob, node, phandle);
1398 if (err < 0)
1399 return err;
1400
1401 /* store one or two address cells */
1402 if (na > 1)
1403 *ptr++ = cpu_to_fdt32(upper);
1404
1405 *ptr++ = cpu_to_fdt32(lower);
1406
1407 /* store one or two size cells */
1408 size = carveout->end - carveout->start + 1;
1409 upper = upper_32_bits(size);
1410 lower = lower_32_bits(size);
1411
1412 if (ns > 1)
1413 *ptr++ = cpu_to_fdt32(upper);
1414
1415 *ptr++ = cpu_to_fdt32(lower);
1416
1417 err = fdt_setprop(blob, node, "reg", cells, (na + ns) * sizeof(*cells));
1418 if (err < 0)
1419 return err;
1420
1421 /* return the phandle for the new node for the caller to use */
1422 if (phandlep)
1423 *phandlep = phandle;
1424
1425 return 0;
1426 }
1427
1428 int fdtdec_get_carveout(const void *blob, const char *node, const char *name,
1429 unsigned int index, struct fdt_memory *carveout)
1430 {
1431 const fdt32_t *prop;
1432 uint32_t phandle;
1433 int offset, len;
1434 fdt_size_t size;
1435
1436 offset = fdt_path_offset(blob, node);
1437 if (offset < 0)
1438 return offset;
1439
1440 prop = fdt_getprop(blob, offset, name, &len);
1441 if (!prop) {
1442 debug("failed to get %s for %s\n", name, node);
1443 return -FDT_ERR_NOTFOUND;
1444 }
1445
1446 if ((len % sizeof(phandle)) != 0) {
1447 debug("invalid phandle property\n");
1448 return -FDT_ERR_BADPHANDLE;
1449 }
1450
1451 if (len < (sizeof(phandle) * (index + 1))) {
1452 debug("invalid phandle index\n");
1453 return -FDT_ERR_BADPHANDLE;
1454 }
1455
1456 phandle = fdt32_to_cpu(prop[index]);
1457
1458 offset = fdt_node_offset_by_phandle(blob, phandle);
1459 if (offset < 0) {
1460 debug("failed to find node for phandle %u\n", phandle);
1461 return offset;
1462 }
1463
1464 carveout->start = fdtdec_get_addr_size_auto_noparent(blob, offset,
1465 "reg", 0, &size,
1466 true);
1467 if (carveout->start == FDT_ADDR_T_NONE) {
1468 debug("failed to read address/size from \"reg\" property\n");
1469 return -FDT_ERR_NOTFOUND;
1470 }
1471
1472 carveout->end = carveout->start + size - 1;
1473
1474 return 0;
1475 }
1476
1477 int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
1478 unsigned int index, const char *name,
1479 const struct fdt_memory *carveout)
1480 {
1481 uint32_t phandle;
1482 int err, offset;
1483 fdt32_t value;
1484
1485 /* XXX implement support for multiple phandles */
1486 if (index > 0) {
1487 debug("invalid index %u\n", index);
1488 return -FDT_ERR_BADOFFSET;
1489 }
1490
1491 err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle);
1492 if (err < 0) {
1493 debug("failed to add reserved memory: %d\n", err);
1494 return err;
1495 }
1496
1497 offset = fdt_path_offset(blob, node);
1498 if (offset < 0) {
1499 debug("failed to find offset for node %s: %d\n", node, offset);
1500 return offset;
1501 }
1502
1503 value = cpu_to_fdt32(phandle);
1504
1505 err = fdt_setprop(blob, offset, prop_name, &value, sizeof(value));
1506 if (err < 0) {
1507 debug("failed to set %s property for node %s: %d\n", prop_name,
1508 node, err);
1509 return err;
1510 }
1511
1512 return 0;
1513 }
1514
1515 int fdtdec_setup(void)
1516 {
1517 #if CONFIG_IS_ENABLED(OF_CONTROL)
1518 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
1519 void *fdt_blob;
1520 # endif
1521 # ifdef CONFIG_OF_EMBED
1522 /* Get a pointer to the FDT */
1523 # ifdef CONFIG_SPL_BUILD
1524 gd->fdt_blob = __dtb_dt_spl_begin;
1525 # else
1526 gd->fdt_blob = __dtb_dt_begin;
1527 # endif
1528 # elif defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
1529 /* Allow the board to override the fdt address. */
1530 gd->fdt_blob = board_fdt_blob_setup();
1531 # elif defined(CONFIG_OF_HOSTFILE)
1532 if (sandbox_read_fdt_from_file()) {
1533 puts("Failed to read control FDT\n");
1534 return -1;
1535 }
1536 # endif
1537 # ifndef CONFIG_SPL_BUILD
1538 /* Allow the early environment to override the fdt address */
1539 # if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
1540 gd->fdt_blob = (void *)prior_stage_fdt_address;
1541 # else
1542 gd->fdt_blob = map_sysmem
1543 (env_get_ulong("fdtcontroladdr", 16,
1544 (unsigned long)map_to_sysmem(gd->fdt_blob)), 0);
1545 # endif
1546 # endif
1547
1548 # if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
1549 /*
1550 * Try and uncompress the blob.
1551 * Unfortunately there is no way to know how big the input blob really
1552 * is. So let us set the maximum input size arbitrarily high. 16MB
1553 * ought to be more than enough for packed DTBs.
1554 */
1555 if (uncompress_blob(gd->fdt_blob, 0x1000000, &fdt_blob) == 0)
1556 gd->fdt_blob = fdt_blob;
1557
1558 /*
1559 * Check if blob is a FIT images containings DTBs.
1560 * If so, pick the most relevant
1561 */
1562 fdt_blob = locate_dtb_in_fit(gd->fdt_blob);
1563 if (fdt_blob) {
1564 gd->multi_dtb_fit = gd->fdt_blob;
1565 gd->fdt_blob = fdt_blob;
1566 }
1567
1568 # endif
1569 #endif
1570
1571 return fdtdec_prepare_fdt();
1572 }
1573
1574 #if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
1575 int fdtdec_resetup(int *rescan)
1576 {
1577 void *fdt_blob;
1578
1579 /*
1580 * If the current DTB is part of a compressed FIT image,
1581 * try to locate the best match from the uncompressed
1582 * FIT image stillpresent there. Save the time and space
1583 * required to uncompress it again.
1584 */
1585 if (gd->multi_dtb_fit) {
1586 fdt_blob = locate_dtb_in_fit(gd->multi_dtb_fit);
1587
1588 if (fdt_blob == gd->fdt_blob) {
1589 /*
1590 * The best match did not change. no need to tear down
1591 * the DM and rescan the fdt.
1592 */
1593 *rescan = 0;
1594 return 0;
1595 }
1596
1597 *rescan = 1;
1598 gd->fdt_blob = fdt_blob;
1599 return fdtdec_prepare_fdt();
1600 }
1601
1602 /*
1603 * If multi_dtb_fit is NULL, it means that blob appended to u-boot is
1604 * not a FIT image containings DTB, but a single DTB. There is no need
1605 * to teard down DM and rescan the DT in this case.
1606 */
1607 *rescan = 0;
1608 return 0;
1609 }
1610 #endif
1611
1612 #ifdef CONFIG_NR_DRAM_BANKS
1613 int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
1614 phys_addr_t *basep, phys_size_t *sizep, bd_t *bd)
1615 {
1616 int addr_cells, size_cells;
1617 const u32 *cell, *end;
1618 u64 total_size, size, addr;
1619 int node, child;
1620 bool auto_size;
1621 int bank;
1622 int len;
1623
1624 debug("%s: board_id=%d\n", __func__, board_id);
1625 if (!area)
1626 area = "/memory";
1627 node = fdt_path_offset(blob, area);
1628 if (node < 0) {
1629 debug("No %s node found\n", area);
1630 return -ENOENT;
1631 }
1632
1633 cell = fdt_getprop(blob, node, "reg", &len);
1634 if (!cell) {
1635 debug("No reg property found\n");
1636 return -ENOENT;
1637 }
1638
1639 addr_cells = fdt_address_cells(blob, node);
1640 size_cells = fdt_size_cells(blob, node);
1641
1642 /* Check the board id and mask */
1643 for (child = fdt_first_subnode(blob, node);
1644 child >= 0;
1645 child = fdt_next_subnode(blob, child)) {
1646 int match_mask, match_value;
1647
1648 match_mask = fdtdec_get_int(blob, child, "match-mask", -1);
1649 match_value = fdtdec_get_int(blob, child, "match-value", -1);
1650
1651 if (match_value >= 0 &&
1652 ((board_id & match_mask) == match_value)) {
1653 /* Found matching mask */
1654 debug("Found matching mask %d\n", match_mask);
1655 node = child;
1656 cell = fdt_getprop(blob, node, "reg", &len);
1657 if (!cell) {
1658 debug("No memory-banks property found\n");
1659 return -EINVAL;
1660 }
1661 break;
1662 }
1663 }
1664 /* Note: if no matching subnode was found we use the parent node */
1665
1666 if (bd) {
1667 memset(bd->bi_dram, '\0', sizeof(bd->bi_dram[0]) *
1668 CONFIG_NR_DRAM_BANKS);
1669 }
1670
1671 auto_size = fdtdec_get_bool(blob, node, "auto-size");
1672
1673 total_size = 0;
1674 end = cell + len / 4 - addr_cells - size_cells;
1675 debug("cell at %p, end %p\n", cell, end);
1676 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
1677 if (cell > end)
1678 break;
1679 addr = 0;
1680 if (addr_cells == 2)
1681 addr += (u64)fdt32_to_cpu(*cell++) << 32UL;
1682 addr += fdt32_to_cpu(*cell++);
1683 if (bd)
1684 bd->bi_dram[bank].start = addr;
1685 if (basep && !bank)
1686 *basep = (phys_addr_t)addr;
1687
1688 size = 0;
1689 if (size_cells == 2)
1690 size += (u64)fdt32_to_cpu(*cell++) << 32UL;
1691 size += fdt32_to_cpu(*cell++);
1692
1693 if (auto_size) {
1694 u64 new_size;
1695
1696 debug("Auto-sizing %llx, size %llx: ", addr, size);
1697 new_size = get_ram_size((long *)(uintptr_t)addr, size);
1698 if (new_size == size) {
1699 debug("OK\n");
1700 } else {
1701 debug("sized to %llx\n", new_size);
1702 size = new_size;
1703 }
1704 }
1705
1706 if (bd)
1707 bd->bi_dram[bank].size = size;
1708 total_size += size;
1709 }
1710
1711 debug("Memory size %llu\n", total_size);
1712 if (sizep)
1713 *sizep = (phys_size_t)total_size;
1714
1715 return 0;
1716 }
1717 #endif /* CONFIG_NR_DRAM_BANKS */
1718
1719 #endif /* !USE_HOSTCC */