description: Create a bug report to help us improve
labels:
- bug
+ - bug-report
+ - to-triage
body:
- type: textarea
id: description
---
-blank_issues_enabled: false
+blank_issues_enabled: true
contact_links:
- name: Feature request
url: https://forum.openwrt.org/c/feature-requests
- "package/boot/arm-trusted-firmware-bcm63xx/**"
"target/bmips":
- "target/linux/bmips/**"
+ - "package/boot/uboot-bmips/**"
+"target/d1":
+ - "target/linux/d1/**"
+ - "package/boot/uboot-d1/**"
+ - "package/boot/opensbi/**"
"target/gemini":
- "target/linux/gemini/**"
"target/imx":
"target/omap":
- "target/linux/omap/**"
- "package/boot/uboot-omap/**"
-"target/oxnas":
- - "target/linux/oxnas/**"
- - "package/boot/uboot-oxnas/**"
"target/pistachio":
- "target/linux/pistachio/**"
"target/qoriq":
/*.patch
/llvm-bpf*
key-build*
+private-key.pem
+public-key.pem
*.orig
*.rej
*~
bool "Enable TLS certificate verification during package download"
default y
+ config USE_APK
+ bool "Use APK instead of OPKG to build distribution (EXPERIMENTAL)"
+
comment "General build options"
config TESTING_KERNEL
config STRIP_KERNEL_EXPORTS
bool "Strip unnecessary exports from the kernel image"
+ depends on !LINUX_6_6
help
Reduces kernel size by stripping unused kernel exports from the kernel
image. Note that this might make the kernel incompatible with any kernel
default y
config GRUB_EFI_IMAGES
- bool "Build GRUB EFI images (Linux x86 or x86_64 host only)"
- depends on TARGET_x86 || TARGET_armsr
+ bool "Build GRUB EFI images"
+ depends on TARGET_x86 || TARGET_armsr || TARGET_loongarch64
depends on TARGET_ROOTFS_EXT4FS || TARGET_ROOTFS_JFFS2 || TARGET_ROOTFS_SQUASHFS
select PACKAGE_grub2 if TARGET_x86
select PACKAGE_grub2-efi if TARGET_x86
select PACKAGE_grub2-bios-setup if TARGET_x86
select PACKAGE_grub2-efi-arm if TARGET_armsr
+ select PACKAGE_grub2-efi-loongarch64 if TARGET_loongarch64
select PACKAGE_kmod-fs-vfat
default y
config TARGET_SERIAL
string "Serial port device"
- depends on TARGET_x86 || TARGET_armsr
+ depends on TARGET_x86 || TARGET_armsr || TARGET_loongarch64
default "ttyS0"
config TARGET_IMAGES_GZIP
bool "GZip images"
- depends on TARGET_ROOTFS_EXT4FS || TARGET_x86 || TARGET_armsr || TARGET_malta
+ depends on TARGET_ROOTFS_EXT4FS || TARGET_x86 || TARGET_armsr || TARGET_malta || TARGET_loongarch64
default y
comment "Image Options"
config TARGET_ROOTFS_PARTSIZE
int "Root filesystem partition size (in MiB)"
depends on USES_ROOTFS_PART || TARGET_ROOTFS_EXT4FS
+ default 232 if TARGET_loongarch64
+ default 448 if TARGET_mediatek
default 104
help
Select the root filesystem partition size.
default y if TARGET_armsr_armv8
depends on (arm || aarch64)
+config KERNEL_ARM_PMUV3
+ bool
+ default y if TARGET_armsr_armv8
+ depends on (arm_v7 || aarch64) && LINUX_6_6
+
config KERNEL_RISCV_PMU
bool
select KERNEL_RISCV_PMU_SBI
config KERNEL_PERF_EVENTS
bool "Compile the kernel with performance events and counters"
select KERNEL_ARM_PMU if (arm || aarch64)
+ select KERNEL_ARM_PMUV3 if (arm_v7 || aarch64) && LINUX_6_6
select KERNEL_RISCV_PMU if riscv64
config KERNEL_PROFILING
BPF_HEADERS_DIR:=$(STAGING_DIR)/bpf-headers
BPF_KERNEL_INCLUDE := \
- -nostdinc -isystem $(TOOLCHAIN_INC_DIRS) \
+ -nostdinc $(patsubst %,-isystem %,$(TOOLCHAIN_INC_DIRS)) \
-I$(BPF_HEADERS_DIR)/arch/$(BPF_KARCH)/include \
-I$(BPF_HEADERS_DIR)/arch/$(BPF_KARCH)/include/asm/mach-generic \
-I$(BPF_HEADERS_DIR)/arch/$(BPF_KARCH)/include/generated \
cd $(TMP_DIR)/dl && \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
- cvs -d $(URL) export $(VERSION) $(SUBDIR) && \
+ cvs -d $(URL) export $(SOURCE_VERSION) $(SUBDIR) && \
echo "Packing checkout..." && \
$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \
mv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
( svn help export | grep -q trust-server-cert && \
- svn export --non-interactive --trust-server-cert -r$(VERSION) $(URL) $(SUBDIR) || \
- svn export --non-interactive -r$(VERSION) $(URL) $(SUBDIR) ) && \
+ svn export --non-interactive --trust-server-cert -r$(SOURCE_VERSION) $(URL) $(SUBDIR) || \
+ svn export --non-interactive -r$(SOURCE_VERSION) $(URL) $(SUBDIR) ) && \
echo "Packing checkout..." && \
- export TAR_TIMESTAMP="`svn info -r$(VERSION) --show-item last-changed-date $(URL)`" && \
+ export TAR_TIMESTAMP="`svn info -r$(SOURCE_VERSION) --show-item last-changed-date $(URL)`" && \
$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \
mv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \
rm -rf $(SUBDIR); \
$(SCRIPT_DIR)/dl_github_archive.py \
--dl-dir="$(DL_DIR)" \
--url="$(URL)" \
- --version="$(VERSION)" \
+ --version="$(SOURCE_VERSION)" \
--subdir="$(SUBDIR)" \
--source="$(FILE)" \
--hash="$(MIRROR_HASH)" \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
git clone $(OPTS) $(URL) $(SUBDIR) && \
- (cd $(SUBDIR) && git checkout $(VERSION)) && \
+ (cd $(SUBDIR) && git checkout $(SOURCE_VERSION)) && \
export TAR_TIMESTAMP=`cd $(SUBDIR) && git log -1 --format='@%ct'` && \
echo "Generating formal git archive (apply .gitattributes rules)" && \
(cd $(SUBDIR) && git config core.abbrev 8 && \
cd $(TMP_DIR)/dl && \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
- bzr export --per-file-timestamps -r$(VERSION) $(SUBDIR) $(URL) && \
+ bzr export --per-file-timestamps -r$(SOURCE_VERSION) $(SUBDIR) $(URL) && \
echo "Packing checkout..." && \
export TAR_TIMESTAMP="" && \
$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \
cd $(TMP_DIR)/dl && \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
- hg clone -r $(VERSION) $(URL) $(SUBDIR) && \
+ hg clone -r $(SOURCE_VERSION) $(URL) $(SUBDIR) && \
export TAR_TIMESTAMP=`cd $(SUBDIR) && hg log --template '@{date}' -l 1` && \
find $(SUBDIR) -name .hg | xargs rm -rf && \
echo "Packing checkout..." && \
cd $(TMP_DIR)/dl && \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
- darcs get -t $(VERSION) $(URL) $(SUBDIR) && \
+ darcs get -t $(SOURCE_VERSION) $(URL) $(SUBDIR) && \
export TAR_TIMESTAMP=`cd $(SUBDIR) && LC_ALL=C darcs log --last 1 | sed -ne 's!^Date: \+!!p'` && \
find $(SUBDIR) -name _darcs | xargs rm -rf && \
echo "Packing checkout..." && \
)
endef
-Validate/cvs=VERSION SUBDIR
-Validate/svn=VERSION SUBDIR
-Validate/git=VERSION SUBDIR
-Validate/bzr=VERSION SUBDIR
-Validate/hg=VERSION SUBDIR
-Validate/darcs=VERSION SUBDIR
+Validate/cvs=SOURCE_VERSION SUBDIR
+Validate/svn=SOURCE_VERSION SUBDIR
+Validate/git=SOURCE_VERSION SUBDIR
+Validate/bzr=SOURCE_VERSION SUBDIR
+Validate/hg=SOURCE_VERSION SUBDIR
+Validate/darcs=SOURCE_VERSION SUBDIR
define Download/Defaults
URL:=
MIRROR:=1
MIRROR_HASH=$$(MIRROR_MD5SUM)
MIRROR_MD5SUM:=x
- VERSION:=
+ SOURCE_VERSION:=
OPTS:=
SUBMODULES:=
endef
$(if $(PKG_SOURCE_MIRROR),MIRROR:=$(filter 1,$(PKG_MIRROR)))
$(if $(PKG_MIRROR_MD5SUM),MIRROR_MD5SUM:=$(PKG_MIRROR_MD5SUM))
$(if $(PKG_MIRROR_HASH),MIRROR_HASH:=$(PKG_MIRROR_HASH))
- VERSION:=$(PKG_SOURCE_VERSION)
+ SOURCE_VERSION:=$(PKG_SOURCE_VERSION)
$(if $(PKG_MD5SUM),MD5SUM:=$(PKG_MD5SUM))
$(if $(PKG_HASH),HASH:=$(PKG_HASH))
endef
$(foreach dir,$(PACKAGE_SUBDIRS), \
$(foreach pkg,$(1), $(dir)/$(pkg)_*.ipk)))
+apk_package_files = $(wildcard \
+ $(foreach dir,$(PACKAGE_SUBDIRS), \
+ $(foreach pkg,$(1), $(dir)/$(pkg)_*.apk)))
+
# 1: package name
define FeedPackageDir
$(strip $(if $(CONFIG_PER_FEED_REPO), \
endef
# 1: destination file
-define FeedSourcesAppend
+define FeedSourcesAppendOPKG
( \
echo 'src/gz %d_core %U/targets/%S/packages'; \
$(strip $(if $(CONFIG_PER_FEED_REPO), \
) >> $(1)
endef
+# 1: destination file
+define FeedSourcesAppendAPK
+( \
+ echo '%U/targets/%S/packages/packages.adb'; \
+ $(strip $(if $(CONFIG_PER_FEED_REPO), \
+ echo '%U/packages/%A/base/packages.adb'; \
+ $(if $(filter %SNAPSHOT-y,$(VERSION_NUMBER)-$(CONFIG_BUILDBOT)), \
+ echo '%U/targets/%S/kmods/$(LINUX_VERSION)-$(LINUX_RELEASE)-$(LINUX_VERMAGIC)/packages.adb';) \
+ $(foreach feed,$(FEEDS_AVAILABLE), \
+ $(if $(CONFIG_FEED_$(feed)), \
+ echo '$(if $(filter m,$(CONFIG_FEED_$(feed))),# )%U/packages/%A/$(feed)/packages.adb';)))) \
+) >> $(1)
+endef
+
# 1: package name
define GetABISuffix
$(if $(ABIV_$(1)),$(ABIV_$(1)),$(call FormatABISuffix,$(1),$(foreach v,$(wildcard $(STAGING_DIR)/pkginfo/$(1).version),$(shell cat $(v)))))
HOST_STAMP_BUILT:=$(HOST_BUILD_DIR)/.built
HOST_BUILD_PREFIX?=$(if $(IS_PACKAGE_BUILD),$(STAGING_DIR_HOSTPKG),$(STAGING_DIR_HOST))
HOST_STAMP_INSTALLED:=$(HOST_BUILD_PREFIX)/stamp/.$(PKG_NAME)_installed
-HOST_STAMP_PROGRAMS:=$(foreach program,$(PKG_PROGRAMS),$(subst $(PKG_NAME),$(program),$(HOST_STAMP_INSTALLED)) )
+HOST_STAMP_PROGRAMS:=$(foreach program,$(PKG_PROGRAMS),$(dir $(HOST_STAMP_INSTALLED))$(subst $(PKG_NAME),$(program),$(notdir $(HOST_STAMP_INSTALLED))) )
override MAKEFLAGS=
ifdef IB
define Build/append-image-stage
- dd if=$(STAGING_DIR_IMAGE)/$(BOARD)$(if $(SUBTARGET),-$(SUBTARGET))-$(DEVICE_NAME)-$(1) >> $@
+ dd if=$(STAGING_DIR_IMAGE)/$(BOARD)-$(SUBTARGET)-$(DEVICE_NAME)-$(1) >> $@
endef
else
define Build/append-image-stage
fwtool -s /dev/null -t "$@.stripmeta" || :
fwtool -i /dev/null -t "$@.stripmeta" || :
mkdir -p "$(STAGING_DIR_IMAGE)"
- dd if="$@.stripmeta" of="$(STAGING_DIR_IMAGE)/$(BOARD)$(if $(SUBTARGET),-$(SUBTARGET))-$(DEVICE_NAME)-$(1)"
+ dd if="$@.stripmeta" of="$(STAGING_DIR_IMAGE)/$(BOARD)-$(SUBTARGET)-$(DEVICE_NAME)-$(1)"
dd if="$@.stripmeta" >> "$@"
rm "$@.stripmeta"
endef
IMG_PREFIX_VERNUM:=$(if $(CONFIG_VERSION_FILENAMES),$(call sanitize,$(VERSION_NUMBER))-)
IMG_PREFIX_VERCODE:=$(if $(CONFIG_VERSION_CODE_FILENAMES),$(call sanitize,$(VERSION_CODE))-)
-IMG_PREFIX:=$(VERSION_DIST_SANITIZED)-$(IMG_PREFIX_VERNUM)$(IMG_PREFIX_VERCODE)$(IMG_PREFIX_EXTRA)$(BOARD)$(if $(SUBTARGET),-$(SUBTARGET))
+IMG_PREFIX:=$(VERSION_DIST_SANITIZED)-$(IMG_PREFIX_VERNUM)$(IMG_PREFIX_VERCODE)$(IMG_PREFIX_EXTRA)$(BOARD)-$(SUBTARGET)
IMG_ROOTFS:=$(IMG_PREFIX)-rootfs
IMG_COMBINED:=$(IMG_PREFIX)-combined
ifeq ($(DUMP),)
-I$(DTS_DIR) \
-I$(DTS_DIR)/include \
-I$(LINUX_DIR)/include/ \
+ -I$(LINUX_DIR)/scripts/dtc/include-prefixes \
-undef -D__DTS__ $(3) \
-o $(2).tmp $(1)
$(LINUX_DIR)/scripts/dtc/dtc -O dtb \
endef
define Image/Manifest
- $(call opkg,$(TARGET_DIR_ORIG)) list-installed > \
- $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).manifest
-ifndef IB
- $(if $(CONFIG_JSON_CYCLONEDX_SBOM), \
- $(SCRIPT_DIR)/package-metadata.pl imgcyclonedxsbom \
- $(TMP_DIR)/.packageinfo \
+ $(if $(CONFIG_USE_APK), \
+ $(call apk,$(TARGET_DIR_ORIG)) list --quiet --manifest --no-network | sort | sed 's/ / - /' > \
+ $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).manifest, \
+ $(call opkg,$(TARGET_DIR_ORIG)) list-installed > \
+ $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).manifest \
+ )
+ifneq ($(CONFIG_JSON_CYCLONEDX_SBOM),)
+ $(SCRIPT_DIR)/package-metadata.pl imgcyclonedxsbom \
+ $(if $(IB),$(TOPDIR)/.packageinfo, $(TMP_DIR)/.packageinfo) \
$(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).manifest > \
- $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).bom.cdx.json)
+ $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).bom.cdx.json
endif
endef
$(call opkg,$(mkfs_cur_target_dir)) \
-f $(mkfs_cur_target_dir).conf
+apk_target = $(call apk,$(mkfs_cur_target_dir)) --no-scripts
+
+
target-dir-%: FORCE
+ifneq ($(CONFIG_USE_APK),)
+ rm -rf $(mkfs_cur_target_dir)
+ $(CP) $(TARGET_DIR_ORIG) $(mkfs_cur_target_dir)
+ mv $(mkfs_cur_target_dir)/etc/apk/repositories $(mkfs_cur_target_dir).repositories
+ $(if $(mkfs_packages_remove), \
+ $(apk_target) del $(mkfs_packages_remove))
+ $(if $(mkfs_packages_add), \
+ $(apk_target) add $(mkfs_packages_add))
+ mv $(mkfs_cur_target_dir).repositories $(mkfs_cur_target_dir)/etc/apk/repositories
+else
rm -rf $(mkfs_cur_target_dir) $(mkfs_cur_target_dir).opkg
$(CP) $(TARGET_DIR_ORIG) $(mkfs_cur_target_dir)
-mv $(mkfs_cur_target_dir)/etc/opkg $(mkfs_cur_target_dir).opkg
$(call opkg_package_files,$(mkfs_packages_add)))
-$(CP) -T $(mkfs_cur_target_dir).opkg/ $(mkfs_cur_target_dir)/etc/opkg/
rm -rf $(mkfs_cur_target_dir).opkg $(mkfs_cur_target_dir).conf
+endif
$(call prepare_rootfs,$(mkfs_cur_target_dir),$(TOPDIR)/files)
$(KDIR)/root.%: kernel_prepare
ifdef IB
DEVICE_CHECK_PROFILE = $(filter $(1),DEVICE_$(PROFILE) $(PROFILE))
else
- DEVICE_CHECK_PROFILE = $(CONFIG_TARGET_$(if $(CONFIG_TARGET_MULTI_PROFILE),DEVICE_)$(call target_conf,$(BOARD)$(if $(SUBTARGET),_$(SUBTARGET)))_$(1))
+ DEVICE_CHECK_PROFILE = $(CONFIG_TARGET_$(if $(CONFIG_TARGET_MULTI_PROFILE),DEVICE_)$(call target_conf,$(BOARD)_$(SUBTARGET))_$(1))
endif
-DEVICE_EXTRA_PACKAGES = $(call qstrip,$(CONFIG_TARGET_DEVICE_PACKAGES_$(call target_conf,$(BOARD)$(if $(SUBTARGET),_$(SUBTARGET)))_DEVICE_$(1)))
+DEVICE_EXTRA_PACKAGES = $(call qstrip,$(CONFIG_TARGET_DEVICE_PACKAGES_$(call target_conf,$(BOARD)_$(SUBTARGET))_DEVICE_$(1)))
define merge_packages
$(1) :=
DEVICE_TITLE="$$(DEVICE_TITLE)" \
DEVICE_PACKAGES="$$(DEVICE_PACKAGES)" \
TARGET="$(BOARD)" \
- SUBTARGET="$(if $(SUBTARGET),$(SUBTARGET),generic)" \
+ SUBTARGET="$(SUBTARGET)" \
VERSION_NUMBER="$(VERSION_NUMBER)" \
VERSION_CODE="$(VERSION_CODE)" \
SUPPORTED_DEVICES="$$(SUPPORTED_DEVICES)" \
DEVICE_TITLE="$(DEVICE_TITLE)" \
DEVICE_PACKAGES="$(DEVICE_PACKAGES)" \
TARGET="$(BOARD)" \
- SUBTARGET="$(if $(SUBTARGET),$(SUBTARGET),generic)" \
+ SUBTARGET="$(SUBTARGET)" \
VERSION_NUMBER="$(VERSION_NUMBER)" \
VERSION_CODE="$(VERSION_CODE)" \
SUPPORTED_DEVICES="$(SUPPORTED_DEVICES)" \
DEVICE_TITLE="$(DEVICE_TITLE)" \
DEVICE_PACKAGES="$(DEVICE_PACKAGES)" \
TARGET="$(BOARD)" \
- SUBTARGET="$(if $(SUBTARGET),$(SUBTARGET),generic)" \
+ SUBTARGET="$(SUBTARGET)" \
VERSION_NUMBER="$(VERSION_NUMBER)" \
VERSION_CODE="$(VERSION_CODE)" \
SUPPORTED_DEVICES="$(SUPPORTED_DEVICES)" \
-LINUX_VERSION-5.15 = .153
-LINUX_KERNEL_HASH-5.15.153 = d7ddb1e144a88773b56a5b4a71baea0b241f3996d446be45290537c6997c84bc
+LINUX_VERSION-5.15 = .158
+LINUX_KERNEL_HASH-5.15.158 = f9071c83a4fd8b80af026b48cfc1869bfa25883f9148b92b5dc1e1e1e26dd5c6
-LINUX_VERSION-6.1 = .82
-LINUX_KERNEL_HASH-6.1.82 = d150d2d9d416877668d8b56f75759f166168d192419eefaa942ed67225cbec06
+LINUX_VERSION-6.1 = .89
+LINUX_KERNEL_HASH-6.1.89 = 12bab8e092618d1d4eeaf4201e6e70054c94896198956bd84ff0e908b0264719
-LINUX_VERSION-6.6 = .25
-LINUX_KERNEL_HASH-6.6.25 = 99d210be87908233a55b0fadc0dccd3b95926c0651b6b82e37350b2029de1f44
+LINUX_VERSION-6.6 = .30
+LINUX_KERNEL_HASH-6.6.30 = b66a5b863b0f8669448b74ca83bd641a856f164b29956e539bbcb5fdeeab9cc6
PATCH_DIR ?= $(CURDIR)/patches$(if $(wildcard ./patches-$(KERNEL_PATCHVER)),-$(KERNEL_PATCHVER))
FILES_DIR ?= $(foreach dir,$(wildcard $(CURDIR)/files $(CURDIR)/files-$(KERNEL_PATCHVER)),"$(dir)")
endif
- KERNEL_BUILD_DIR ?= $(BUILD_DIR)/linux-$(BOARD)$(if $(SUBTARGET),_$(SUBTARGET))
+ KERNEL_BUILD_DIR ?= $(BUILD_DIR)/linux-$(BOARD)_$(SUBTARGET)
LINUX_DIR ?= $(KERNEL_BUILD_DIR)/linux-$(LINUX_VERSION)
LINUX_UAPI_DIR=uapi/
LINUX_VERMAGIC:=$(strip $(shell cat $(LINUX_DIR)/.vermagic 2>/dev/null))
LINUX_KARCH := arc
else ifneq (,$(findstring $(ARCH) , armeb ))
LINUX_KARCH := arm
+else ifneq (,$(findstring $(ARCH) , loongarch64 ))
+ LINUX_KARCH := loongarch
else ifneq (,$(findstring $(ARCH) , mipsel mips64 mips64el ))
LINUX_KARCH := mips
else ifneq (,$(findstring $(ARCH) , powerpc64 ))
$(eval $(call KernelPackage/Defaults))
$(eval $(call KernelPackage/$(1)))
$(eval $(call KernelPackage/$(1)/$(BOARD)))
- $(eval $(call KernelPackage/$(1)/$(BOARD)/$(if $(SUBTARGET),$(SUBTARGET),generic)))
+ $(eval $(call KernelPackage/$(1)/$(BOARD)/$(SUBTARGET)))
define Package/kmod-$(1)
TITLE:=$(TITLE)
PKGFLAGS:=$(PKGFLAGS)
$(call KernelPackage/$(1))
$(call KernelPackage/$(1)/$(BOARD))
- $(call KernelPackage/$(1)/$(BOARD)/$(if $(SUBTARGET),$(SUBTARGET),generic))
+ $(call KernelPackage/$(1)/$(BOARD)/$(SUBTARGET))
endef
ifdef KernelPackage/$(1)/conffiles
)$(if $(BUILDONLY),Build-Only: $(BUILDONLY)
)$(if $(HIDDEN),Hidden: $(HIDDEN)
)Description: $(if $(Package/$(1)/description),$(Package/$(1)/description),$(TITLE))
-$(MAINTAINER)
@@
$(if $(Package/$(1)/config),Config:
$(Package/$(1)/config)
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Copyright (C) 2006-2020 OpenWrt.org
-
-ifndef DUMP
- include $(INCLUDE_DIR)/feeds.mk
-endif
-
-IPKG_REMOVE:= \
- $(SCRIPT_DIR)/ipkg-remove
-
-IPKG_STATE_DIR:=$(TARGET_DIR)/usr/lib/opkg
-
-# Generates a make statement to return a wildcard for candidate ipkg files
-# 1: package name
-define gen_ipkg_wildcard
- $(1)$$(if $$(filter -%,$$(ABIV_$(1))),,[^a-z-])*
-endef
-
-# 1: package name
-# 2: candidate ipk files
-define remove_ipkg_files
- $(if $(strip $(2)),$(IPKG_REMOVE) $(1) $(2))
-endef
-
-# 1: package name
-# 2: variable name
-# 3: variable suffix
-# 4: file is a script
-define BuildIPKGVariable
-ifdef Package/$(1)/$(2)
- $$(IPKG_$(1)) : VAR_$(2)$(3)=$$(Package/$(1)/$(2))
- $(call shexport,Package/$(1)/$(2))
- $(1)_COMMANDS += echo "$$$$$$$$$(call shvar,Package/$(1)/$(2))" > $(2)$(3); $(if $(4),chmod 0755 $(2)$(3);)
-endif
-endef
-
-PARENL :=(
-PARENR :=)
-
-dep_split=$(subst :,$(space),$(1))
-dep_rem=$(subst !,,$(subst $(strip $(PARENL)),,$(subst $(strip $(PARENR)),,$(word 1,$(call dep_split,$(1))))))
-dep_and=dep_and_res:=$$(and $(subst $(space),$(comma),$(foreach cond,$(subst &&, ,$(1)),$$(CONFIG_$(cond)))))
-dep_confvar=$(strip $(foreach cond,$(subst ||, ,$(call dep_rem,$(1))),$(eval $(call dep_and,$(cond)))$(dep_and_res)))
-dep_pos=$(if $(call dep_confvar,$(1)),$(call dep_val,$(1)))
-dep_neg=$(if $(call dep_confvar,$(1)),,$(call dep_val,$(1)))
-dep_if=$(if $(findstring !,$(1)),$(call dep_neg,$(1)),$(call dep_pos,$(1)))
-dep_val=$(word 2,$(call dep_split,$(1)))
-strip_deps=$(strip $(subst +,,$(filter-out @%,$(1))))
-filter_deps=$(foreach dep,$(call strip_deps,$(1)),$(if $(findstring :,$(dep)),$(call dep_if,$(dep)),$(dep)))
-
-define AddDependency
- $$(if $(1),$$(if $(2),$$(foreach pkg,$(1),$$(IPKG_$$(pkg))): $$(foreach pkg,$(2),$$(IPKG_$$(pkg)))))
-endef
-
-define FixupReverseDependencies
- DEPS := $$(filter %:$(1),$$(IDEPEND))
- DEPS := $$(patsubst %:$(1),%,$$(DEPS))
- DEPS := $$(filter $$(DEPS),$$(IPKGS))
- $(call AddDependency,$$(DEPS),$(1))
-endef
-
-define FixupDependencies
- DEPS := $$(filter $(1):%,$$(IDEPEND))
- DEPS := $$(patsubst $(1):%,%,$$(DEPS))
- DEPS := $$(filter $$(DEPS),$$(IPKGS))
- $(call AddDependency,$(1),$$(DEPS))
-endef
-
-ifneq ($(PKG_NAME),toolchain)
- define CheckDependencies
- @( \
- rm -f $(PKG_INFO_DIR)/$(1).missing; \
- ( \
- export \
- READELF=$(TARGET_CROSS)readelf \
- OBJCOPY=$(TARGET_CROSS)objcopy \
- XARGS="$(XARGS)"; \
- $(SCRIPT_DIR)/gen-dependencies.sh "$$(IDIR_$(1))"; \
- ) | while read FILE; do \
- grep -qxF "$$$$FILE" $(PKG_INFO_DIR)/$(1).provides || \
- echo "$$$$FILE" >> $(PKG_INFO_DIR)/$(1).missing; \
- done; \
- if [ -f "$(PKG_INFO_DIR)/$(1).missing" ]; then \
- echo "Package $(1) is missing dependencies for the following libraries:" >&2; \
- cat "$(PKG_INFO_DIR)/$(1).missing" >&2; \
- false; \
- fi; \
- )
- endef
-endif
-
-_addsep=$(word 1,$(1))$(foreach w,$(wordlist 2,$(words $(1)),$(1)),$(strip $(2) $(w)))
-_cleansep=$(subst $(space)$(2)$(space),$(2)$(space),$(1))
-mergelist=$(call _cleansep,$(call _addsep,$(1),$(comma)),$(comma))
-addfield=$(if $(strip $(2)),$(1): $(2))
-_define=define
-_endef=endef
-
-ifeq ($(DUMP),)
- define BuildTarget/ipkg
- ABIV_$(1):=$(call FormatABISuffix,$(1),$(ABI_VERSION))
- PDIR_$(1):=$(call FeedPackageDir,$(1))
- IPKG_$(1):=$$(PDIR_$(1))/$(1)$$(ABIV_$(1))_$(VERSION)_$(PKGARCH).ipk
- IDIR_$(1):=$(PKG_BUILD_DIR)/ipkg-$(PKGARCH)/$(1)
- KEEP_$(1):=$(strip $(call Package/$(1)/conffiles))
-
- TARGET_VARIANT:=$$(if $(ALL_VARIANTS),$$(if $$(VARIANT),$$(filter-out *,$$(VARIANT)),$(firstword $(ALL_VARIANTS))))
- ifeq ($(BUILD_VARIANT),$$(if $$(TARGET_VARIANT),$$(TARGET_VARIANT),$(BUILD_VARIANT)))
- do_install=
- ifdef Package/$(1)/install
- do_install=yes
- endif
- ifdef Package/$(1)/install-overlay
- do_install=yes
- endif
- ifdef do_install
- ifneq ($(CONFIG_PACKAGE_$(1))$(DEVELOPER),)
- IPKGS += $(1)
- $(_pkg_target)compile: $$(IPKG_$(1)) $(PKG_INFO_DIR)/$(1).provides $(PKG_BUILD_DIR)/.pkgdir/$(1).installed
- prepare-package-install: $$(IPKG_$(1))
- compile: $(STAGING_DIR_ROOT)/stamp/.$(1)_installed
- else
- $(if $(CONFIG_PACKAGE_$(1)),$$(info WARNING: skipping $(1) -- package not selected))
- endif
-
- .PHONY: $(PKG_INSTALL_STAMP).$(1)
- ifeq ($(CONFIG_PACKAGE_$(1)),y)
- compile: $(PKG_INSTALL_STAMP).$(1)
- endif
- $(PKG_INSTALL_STAMP).$(1): prepare-package-install
- echo "$(1)" >> $(PKG_INSTALL_STAMP)
- else
- $(if $(CONFIG_PACKAGE_$(1)),$$(warning WARNING: skipping $(1) -- package has no install section))
- endif
- endif
-
- DEPENDS:=$(call PKG_FIXUP_DEPENDS,$(1),$(DEPENDS))
- IDEPEND_$(1):=$$(call filter_deps,$$(DEPENDS))
- IDEPEND += $$(patsubst %,$(1):%,$$(IDEPEND_$(1)))
- $(FixupDependencies)
- $(FixupReverseDependencies)
-
- $(eval $(call BuildIPKGVariable,$(1),conffiles))
- $(eval $(call BuildIPKGVariable,$(1),preinst,,1))
- $(eval $(call BuildIPKGVariable,$(1),postinst,-pkg,1))
- $(eval $(call BuildIPKGVariable,$(1),prerm,-pkg,1))
- $(eval $(call BuildIPKGVariable,$(1),postrm,,1))
-
- $(PKG_BUILD_DIR)/.pkgdir/$(1).installed : export PATH=$$(TARGET_PATH_PKG)
- $(PKG_BUILD_DIR)/.pkgdir/$(1).installed: $(STAMP_BUILT)
- rm -rf $$@ $(PKG_BUILD_DIR)/.pkgdir/$(1)
- mkdir -p $(PKG_BUILD_DIR)/.pkgdir/$(1)
- $(call Package/$(1)/install,$(PKG_BUILD_DIR)/.pkgdir/$(1))
- $(call Package/$(1)/install_lib,$(PKG_BUILD_DIR)/.pkgdir/$(1))
- touch $$@
-
- $(STAGING_DIR_ROOT)/stamp/.$(1)_installed: $(PKG_BUILD_DIR)/.pkgdir/$(1).installed
- mkdir -p $(STAGING_DIR_ROOT)/stamp
- $(if $(ABI_VERSION),echo '$(ABI_VERSION)' | cmp -s - $(PKG_INFO_DIR)/$(1).version || { \
- echo '$(ABI_VERSION)' > $(PKG_INFO_DIR)/$(1).version; \
- $(foreach pkg,$(filter-out $(1),$(PROVIDES)), \
- cp $(PKG_INFO_DIR)/$(1).version $(PKG_INFO_DIR)/$(pkg).version; \
- ) \
- } )
- $(call locked,$(CP) $(PKG_BUILD_DIR)/.pkgdir/$(1)/. $(STAGING_DIR_ROOT)/,root-copy)
- touch $$@
-
- Package/$(1)/DEPENDS := $$(call mergelist,$$(foreach dep,$$(filter-out @%,$$(IDEPEND_$(1))),$$(dep)$$(call GetABISuffix,$$(dep))))
- ifneq ($$(EXTRA_DEPENDS),)
- Package/$(1)/DEPENDS := $$(EXTRA_DEPENDS)$$(if $$(Package/$(1)/DEPENDS),$$(comma) $$(Package/$(1)/DEPENDS))
- endif
-
-$(_define) Package/$(1)/CONTROL
-Package: $(1)$$(ABIV_$(1))
-Version: $(VERSION)
-$$(call addfield,Depends,$$(Package/$(1)/DEPENDS)
-)$$(call addfield,Conflicts,$$(call mergelist,$(CONFLICTS))
-)$$(call addfield,Provides,$$(call mergelist,$$(filter-out $(1)$$(ABIV_$(1)),$(PROVIDES)$$(if $$(ABIV_$(1)), $(1) $(foreach provide,$(PROVIDES),$(provide)$$(ABIV_$(1))))))
-)$$(call addfield,Alternatives,$$(call mergelist,$(ALTERNATIVES))
-)$$(call addfield,Source,$(SOURCE)
-)$$(call addfield,SourceName,$(PKG_NAME)
-)$$(call addfield,License,$(LICENSE)
-)$$(call addfield,LicenseFiles,$(LICENSE_FILES)
-)$$(call addfield,Section,$(SECTION)
-)$$(call addfield,Require-User,$(USERID)
-)$$(call addfield,SourceDateEpoch,$(PKG_SOURCE_DATE_EPOCH)
-)$$(call addfield,URL,$(URL)
-)$$(if $$(ABIV_$(1)),ABIVersion: $$(ABIV_$(1))
-)$(if $(PKG_CPE_ID),CPE-ID: $(PKG_CPE_ID)
-)$(if $(filter hold,$(PKG_FLAGS)),Status: unknown hold not-installed
-)$(if $(filter essential,$(PKG_FLAGS)),Essential: yes
-)$(if $(MAINTAINER),Maintainer: $(MAINTAINER)
-)Architecture: $(PKGARCH)
-Installed-Size: 0
-$(_endef)
-
- $$(IPKG_$(1)) : export CONTROL=$$(Package/$(1)/CONTROL)
- $$(IPKG_$(1)) : export DESCRIPTION=$$(Package/$(1)/description)
- $$(IPKG_$(1)) : export PATH=$$(TARGET_PATH_PKG)
- $$(IPKG_$(1)) : export PKG_SOURCE_DATE_EPOCH:=$(PKG_SOURCE_DATE_EPOCH)
- $(PKG_INFO_DIR)/$(1).provides $$(IPKG_$(1)): $(STAMP_BUILT) $(INCLUDE_DIR)/package-ipkg.mk
- @rm -rf $$(IDIR_$(1)); \
- $$(call remove_ipkg_files,$(1),$$(call opkg_package_files,$(call gen_ipkg_wildcard,$(1))))
- mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1))/CONTROL $(PKG_INFO_DIR)
- $(call Package/$(1)/install,$$(IDIR_$(1)))
- $(if $(Package/$(1)/install-overlay),mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1))/rootfs-overlay)
- $(call Package/$(1)/install-overlay,$$(IDIR_$(1))/rootfs-overlay)
- -find $$(IDIR_$(1)) -name 'CVS' -o -name '.svn' -o -name '.#*' -o -name '*~'| $(XARGS) rm -rf
- @( \
- find $$(IDIR_$(1)) -name lib\*.so\* -or -name \*.ko | awk -F/ '{ print $$$$NF }'; \
- for file in $$(patsubst %,$(PKG_INFO_DIR)/%.provides,$$(IDEPEND_$(1))); do \
- if [ -f "$$$$file" ]; then \
- cat $$$$file; \
- fi; \
- done; $(Package/$(1)/extra_provides) \
- ) | sort -u > $(PKG_INFO_DIR)/$(1).provides
- $(if $(PROVIDES),@for pkg in $(filter-out $(1),$(PROVIDES)); do cp $(PKG_INFO_DIR)/$(1).provides $(PKG_INFO_DIR)/$$$$pkg.provides; done)
- $(CheckDependencies)
-
- $(RSTRIP) $$(IDIR_$(1))
-
- ifneq ($$(CONFIG_IPK_FILES_CHECKSUMS),)
- (cd $$(IDIR_$(1)); \
- ( \
- find . -type f \! -path ./CONTROL/\* -exec $(MKHASH) sha256 -n \{\} \; 2> /dev/null | \
- sed 's|\([[:blank:]]\)\./| \1/|' > $$(IDIR_$(1))/CONTROL/files-sha256sum \
- ) || true \
- )
- endif
- (cd $$(IDIR_$(1))/CONTROL; \
- ( \
- echo "$$$$CONTROL"; \
- printf "Description: "; echo "$$$$DESCRIPTION" | sed -e 's,^[[:space:]]*, ,g'; \
- ) > control; \
- chmod 644 control; \
- ( \
- echo "#!/bin/sh"; \
- echo "[ \"\$$$${IPKG_NO_SCRIPT}\" = \"1\" ] && exit 0"; \
- echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
- echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
- echo "default_postinst \$$$$0 \$$$$@"; \
- ) > postinst; \
- ( \
- echo "#!/bin/sh"; \
- echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
- echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
- echo "default_prerm \$$$$0 \$$$$@"; \
- ) > prerm; \
- chmod 0755 postinst prerm; \
- $($(1)_COMMANDS) \
- )
-
- ifneq ($$(KEEP_$(1)),)
- @( \
- keepfiles=""; \
- for x in $$(KEEP_$(1)); do \
- [ -f "$$(IDIR_$(1))/$$$$x" ] || keepfiles="$$$${keepfiles:+$$$$keepfiles }$$$$x"; \
- done; \
- [ -z "$$$$keepfiles" ] || { \
- mkdir -p $$(IDIR_$(1))/lib/upgrade/keep.d; \
- for x in $$$$keepfiles; do echo $$$$x >> $$(IDIR_$(1))/lib/upgrade/keep.d/$(1); done; \
- }; \
- )
- endif
-
- $(INSTALL_DIR) $$(PDIR_$(1))
- $(FAKEROOT) $(STAGING_DIR_HOST)/bin/bash $(SCRIPT_DIR)/ipkg-build -m "$(FILE_MODES)" $$(IDIR_$(1)) $$(PDIR_$(1))
- @[ -f $$(IPKG_$(1)) ]
-
- $(1)-clean:
- $$(call remove_ipkg_files,$(1),$$(call opkg_package_files,$(call gen_ipkg_wildcard,$(1))))
-
- clean: $(1)-clean
-
- endef
-endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2006-2022 OpenWrt.org
+
+ifndef DUMP
+ include $(INCLUDE_DIR)/feeds.mk
+endif
+
+IPKG_STATE_DIR:=$(TARGET_DIR)/usr/lib/opkg
+
+# Generates a make statement to return a wildcard for candidate ipkg files
+# 1: package name
+define gen_package_wildcard
+ $(1)$$(if $$(filter -%,$$(ABIV_$(1))),,[^a-z-])*
+endef
+
+# 1: package name
+# 2: candidate ipk files
+define remove_ipkg_files
+ $(if $(strip $(2)),$(SCRIPT_DIR)/ipkg-remove $(1) $(2))
+endef
+
+# 1: package name
+# 2: variable name
+# 3: variable suffix
+# 4: file is a script
+define BuildPackVariable
+ifdef Package/$(1)/$(2)
+ $$(PACK_$(1)) : VAR_$(2)$(3)=$$(Package/$(1)/$(2))
+ $(call shexport,Package/$(1)/$(2))
+ $(1)_COMMANDS += echo "$$$$$$$$$(call shvar,Package/$(1)/$(2))" > $(2)$(3); $(if $(4),chmod 0755 $(2)$(3);)
+endif
+endef
+
+PARENL :=(
+PARENR :=)
+
+dep_split=$(subst :,$(space),$(1))
+dep_rem=$(subst !,,$(subst $(strip $(PARENL)),,$(subst $(strip $(PARENR)),,$(word 1,$(call dep_split,$(1))))))
+dep_and=dep_and_res:=$$(and $(subst $(space),$(comma),$(foreach cond,$(subst &&, ,$(1)),$$(CONFIG_$(cond)))))
+dep_confvar=$(strip $(foreach cond,$(subst ||, ,$(call dep_rem,$(1))),$(eval $(call dep_and,$(cond)))$(dep_and_res)))
+dep_pos=$(if $(call dep_confvar,$(1)),$(call dep_val,$(1)))
+dep_neg=$(if $(call dep_confvar,$(1)),,$(call dep_val,$(1)))
+dep_if=$(if $(findstring !,$(1)),$(call dep_neg,$(1)),$(call dep_pos,$(1)))
+dep_val=$(word 2,$(call dep_split,$(1)))
+strip_deps=$(strip $(subst +,,$(filter-out @%,$(1))))
+filter_deps=$(foreach dep,$(call strip_deps,$(1)),$(if $(findstring :,$(dep)),$(call dep_if,$(dep)),$(dep)))
+
+define AddDependency
+ $$(if $(1),$$(if $(2),$$(foreach pkg,$(1),$$(PACK_$$(pkg))): $$(foreach pkg,$(2),$$(PACK_$$(pkg)))))
+endef
+
+define FixupReverseDependencies
+ DEPS := $$(filter %:$(1),$$(IDEPEND))
+ DEPS := $$(patsubst %:$(1),%,$$(DEPS))
+ DEPS := $$(filter $$(DEPS),$$(IPKGS))
+ $(call AddDependency,$$(DEPS),$(1))
+endef
+
+define FixupDependencies
+ DEPS := $$(filter $(1):%,$$(IDEPEND))
+ DEPS := $$(patsubst $(1):%,%,$$(DEPS))
+ DEPS := $$(filter $$(DEPS),$$(IPKGS))
+ $(call AddDependency,$(1),$$(DEPS))
+endef
+
+ifneq ($(PKG_NAME),toolchain)
+ define CheckDependencies
+ @( \
+ rm -f $(PKG_INFO_DIR)/$(1).missing; \
+ ( \
+ export \
+ READELF=$(TARGET_CROSS)readelf \
+ OBJCOPY=$(TARGET_CROSS)objcopy \
+ XARGS="$(XARGS)"; \
+ $(SCRIPT_DIR)/gen-dependencies.sh "$$(IDIR_$(1))"; \
+ ) | while read FILE; do \
+ grep -qxF "$$$$FILE" $(PKG_INFO_DIR)/$(1).provides || \
+ echo "$$$$FILE" >> $(PKG_INFO_DIR)/$(1).missing; \
+ done; \
+ if [ -f "$(PKG_INFO_DIR)/$(1).missing" ]; then \
+ echo "Package $(1) is missing dependencies for the following libraries:" >&2; \
+ cat "$(PKG_INFO_DIR)/$(1).missing" >&2; \
+ false; \
+ fi; \
+ )
+ endef
+endif
+
+_addsep=$(word 1,$(1))$(foreach w,$(wordlist 2,$(words $(1)),$(1)),$(strip $(2) $(w)))
+_cleansep=$(subst $(space)$(2)$(space),$(2)$(space),$(1))
+mergelist=$(call _cleansep,$(call _addsep,$(1),$(comma)),$(comma))
+addfield=$(if $(strip $(2)),$(1): $(2))
+_define=define
+_endef=endef
+
+ifeq ($(DUMP),)
+ define BuildTarget/ipkg
+ ABIV_$(1):=$(call FormatABISuffix,$(1),$(ABI_VERSION))
+ PDIR_$(1):=$(call FeedPackageDir,$(1))
+ifeq ($(CONFIG_USE_APK),)
+ PACK_$(1):=$$(PDIR_$(1))/$(1)$$(ABIV_$(1))_$(VERSION)_$(PKGARCH).ipk
+else
+ PACK_$(1):=$$(PDIR_$(1))/$(1)$$(ABIV_$(1))-$(VERSION).apk
+endif
+ IDIR_$(1):=$(PKG_BUILD_DIR)/ipkg-$(PKGARCH)/$(1)
+ ADIR_$(1):=$(PKG_BUILD_DIR)/apk-$(PKGARCH)/$(1)
+ KEEP_$(1):=$(strip $(call Package/$(1)/conffiles))
+
+ TARGET_VARIANT:=$$(if $(ALL_VARIANTS),$$(if $$(VARIANT),$$(filter-out *,$$(VARIANT)),$(firstword $(ALL_VARIANTS))))
+ ifeq ($(BUILD_VARIANT),$$(if $$(TARGET_VARIANT),$$(TARGET_VARIANT),$(BUILD_VARIANT)))
+ do_install=
+ ifdef Package/$(1)/install
+ do_install=yes
+ endif
+ ifdef Package/$(1)/install-overlay
+ do_install=yes
+ endif
+ ifdef do_install
+ ifneq ($(CONFIG_PACKAGE_$(1))$(DEVELOPER),)
+ IPKGS += $(1)
+ $(_pkg_target)compile: $$(PACK_$(1)) $(PKG_INFO_DIR)/$(1).provides $(PKG_BUILD_DIR)/.pkgdir/$(1).installed
+ prepare-package-install: $$(PACK_$(1))
+ compile: $(STAGING_DIR_ROOT)/stamp/.$(1)_installed
+ else
+ $(if $(CONFIG_PACKAGE_$(1)),$$(info WARNING: skipping $(1) -- package not selected))
+ endif
+
+ .PHONY: $(PKG_INSTALL_STAMP).$(1)
+ ifeq ($(CONFIG_PACKAGE_$(1)),y)
+ compile: $(PKG_INSTALL_STAMP).$(1)
+ endif
+ $(PKG_INSTALL_STAMP).$(1): prepare-package-install
+ echo "$(1)" >> $(PKG_INSTALL_STAMP)
+ else
+ $(if $(CONFIG_PACKAGE_$(1)),$$(warning WARNING: skipping $(1) -- package has no install section))
+ endif
+ endif
+
+ DEPENDS:=$(call PKG_FIXUP_DEPENDS,$(1),$(DEPENDS))
+ IDEPEND_$(1):=$$(call filter_deps,$$(DEPENDS))
+ IDEPEND += $$(patsubst %,$(1):%,$$(IDEPEND_$(1)))
+ $(FixupDependencies)
+ $(FixupReverseDependencies)
+
+ $(eval $(call BuildPackVariable,$(1),conffiles))
+ $(eval $(call BuildPackVariable,$(1),preinst,,1))
+ $(eval $(call BuildPackVariable,$(1),postinst,-pkg,1))
+ $(eval $(call BuildPackVariable,$(1),prerm,-pkg,1))
+ $(eval $(call BuildPackVariable,$(1),postrm,,1))
+
+ $(PKG_BUILD_DIR)/.pkgdir/$(1).installed : export PATH=$$(TARGET_PATH_PKG)
+ $(PKG_BUILD_DIR)/.pkgdir/$(1).installed: $(STAMP_BUILT)
+ rm -rf $$@ $(PKG_BUILD_DIR)/.pkgdir/$(1)
+ mkdir -p $(PKG_BUILD_DIR)/.pkgdir/$(1)
+ $(call Package/$(1)/install,$(PKG_BUILD_DIR)/.pkgdir/$(1))
+ $(call Package/$(1)/install_lib,$(PKG_BUILD_DIR)/.pkgdir/$(1))
+ touch $$@
+
+ $(STAGING_DIR_ROOT)/stamp/.$(1)_installed: $(PKG_BUILD_DIR)/.pkgdir/$(1).installed
+ mkdir -p $(STAGING_DIR_ROOT)/stamp
+ $(if $(ABI_VERSION),echo '$(ABI_VERSION)' | cmp -s - $(PKG_INFO_DIR)/$(1).version || { \
+ echo '$(ABI_VERSION)' > $(PKG_INFO_DIR)/$(1).version; \
+ $(foreach pkg,$(filter-out $(1),$(PROVIDES)), \
+ cp $(PKG_INFO_DIR)/$(1).version $(PKG_INFO_DIR)/$(pkg).version; \
+ ) \
+ } )
+ $(call locked,$(CP) $(PKG_BUILD_DIR)/.pkgdir/$(1)/. $(STAGING_DIR_ROOT)/,root-copy)
+ touch $$@
+
+ Package/$(1)/DEPENDS := $$(call mergelist,$$(foreach dep,$$(filter-out @%,$$(IDEPEND_$(1))),$$(dep)$$(call GetABISuffix,$$(dep))))
+ ifneq ($$(EXTRA_DEPENDS),)
+ Package/$(1)/DEPENDS := $$(EXTRA_DEPENDS)$$(if $$(Package/$(1)/DEPENDS),$$(comma) $$(Package/$(1)/DEPENDS))
+ endif
+
+$(_define) Package/$(1)/CONTROL
+Package: $(1)$$(ABIV_$(1))
+Version: $(VERSION)
+$$(call addfield,Depends,$$(Package/$(1)/DEPENDS)
+)$$(call addfield,Conflicts,$$(call mergelist,$(CONFLICTS))
+)$$(call addfield,Provides,$$(call mergelist,$$(filter-out $(1)$$(ABIV_$(1)),$(PROVIDES)$$(if $$(ABIV_$(1)), $(1) $(foreach provide,$(PROVIDES),$(provide)$$(ABIV_$(1))))))
+)$$(call addfield,Alternatives,$$(call mergelist,$(ALTERNATIVES))
+)$$(call addfield,Source,$(SOURCE)
+)$$(call addfield,SourceName,$(PKG_NAME)
+)$$(call addfield,License,$(LICENSE)
+)$$(call addfield,LicenseFiles,$(LICENSE_FILES)
+)$$(call addfield,Section,$(SECTION)
+)$$(call addfield,Require-User,$(USERID)
+)$$(call addfield,SourceDateEpoch,$(PKG_SOURCE_DATE_EPOCH)
+)$$(call addfield,URL,$(URL)
+)$$(if $$(ABIV_$(1)),ABIVersion: $$(ABIV_$(1))
+)$(if $(PKG_CPE_ID),CPE-ID: $(PKG_CPE_ID)
+)$(if $(filter hold,$(PKG_FLAGS)),Status: unknown hold not-installed
+)$(if $(filter essential,$(PKG_FLAGS)),Essential: yes
+)$(if $(MAINTAINER),Maintainer: $(MAINTAINER)
+)Architecture: $(PKGARCH)
+Installed-Size: 0
+$(_endef)
+
+ $$(PACK_$(1)) : export CONTROL=$$(Package/$(1)/CONTROL)
+ $$(PACK_$(1)) : export DESCRIPTION=$$(Package/$(1)/description)
+ $$(PACK_$(1)) : export PATH=$$(TARGET_PATH_PKG)
+ $$(PACK_$(1)) : export PKG_SOURCE_DATE_EPOCH:=$(PKG_SOURCE_DATE_EPOCH)
+ $(PKG_INFO_DIR)/$(1).provides $$(PACK_$(1)): $(STAMP_BUILT) $(INCLUDE_DIR)/package-pack.mk
+ rm -rf $$(IDIR_$(1))
+ifeq ($$(CONFIG_USE_APK),)
+ $$(call remove_ipkg_files,$(1),$$(call opkg_package_files,$(call gen_package_wildcard,$(1))))
+endif
+ mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1)) $(PKG_INFO_DIR)
+ $(call Package/$(1)/install,$$(IDIR_$(1)))
+ $(if $(Package/$(1)/install-overlay),mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1))/rootfs-overlay)
+ $(call Package/$(1)/install-overlay,$$(IDIR_$(1))/rootfs-overlay)
+ -find $$(IDIR_$(1)) -name 'CVS' -o -name '.svn' -o -name '.#*' -o -name '*~'| $(XARGS) rm -rf
+ @( \
+ find $$(IDIR_$(1)) -name lib\*.so\* -or -name \*.ko | awk -F/ '{ print $$$$NF }'; \
+ for file in $$(patsubst %,$(PKG_INFO_DIR)/%.provides,$$(IDEPEND_$(1))); do \
+ if [ -f "$$$$file" ]; then \
+ cat $$$$file; \
+ fi; \
+ done; $(Package/$(1)/extra_provides) \
+ ) | sort -u > $(PKG_INFO_DIR)/$(1).provides
+ $(if $(PROVIDES),@for pkg in $(filter-out $(1),$(PROVIDES)); do cp $(PKG_INFO_DIR)/$(1).provides $(PKG_INFO_DIR)/$$$$pkg.provides; done)
+ $(CheckDependencies)
+
+ $(RSTRIP) $$(IDIR_$(1))
+
+ ifneq ($$(CONFIG_IPK_FILES_CHECKSUMS),)
+ (cd $$(IDIR_$(1)); \
+ ( \
+ find . -type f \! -path ./CONTROL/\* -exec $(MKHASH) sha256 -n \{\} \; 2> /dev/null | \
+ sed 's|\([[:blank:]]\)\./| \1/|' > $$(IDIR_$(1))/CONTROL/files-sha256sum \
+ ) || true \
+ )
+ endif
+
+ ifneq ($$(KEEP_$(1)),)
+ @( \
+ keepfiles=""; \
+ for x in $$(KEEP_$(1)); do \
+ [ -f "$$(IDIR_$(1))/$$$$x" ] || keepfiles="$$$${keepfiles:+$$$$keepfiles }$$$$x"; \
+ done; \
+ [ -z "$$$$keepfiles" ] || { \
+ mkdir -p $$(IDIR_$(1))/lib/upgrade/keep.d; \
+ for x in $$$$keepfiles; do echo $$$$x >> $$(IDIR_$(1))/lib/upgrade/keep.d/$(1); done; \
+ }; \
+ )
+ endif
+
+ $(INSTALL_DIR) $$(PDIR_$(1))/tmp
+
+ifeq ($(CONFIG_USE_APK),)
+ mkdir -p $$(IDIR_$(1))/CONTROL
+ (cd $$(IDIR_$(1))/CONTROL; \
+ ( \
+ echo "$$$$CONTROL"; \
+ printf "Description: "; echo "$$$$DESCRIPTION" | sed -e 's,^[[:space:]]*, ,g'; \
+ ) > control; \
+ chmod 644 control; \
+ ( \
+ echo "#!/bin/sh"; \
+ echo "[ \"\$$$${IPKG_NO_SCRIPT}\" = \"1\" ] && exit 0"; \
+ echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
+ echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
+ echo "default_postinst \$$$$0 \$$$$@"; \
+ ) > postinst; \
+ ( \
+ echo "#!/bin/sh"; \
+ echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
+ echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
+ echo "default_prerm \$$$$0 \$$$$@"; \
+ ) > prerm; \
+ chmod 0755 postinst prerm; \
+ $($(1)_COMMANDS) \
+ )
+
+ $(FAKEROOT) $(STAGING_DIR_HOST)/bin/bash $(SCRIPT_DIR)/ipkg-build -m "$(FILE_MODES)" $$(IDIR_$(1)) $$(PDIR_$(1))
+else
+ mkdir -p $$(ADIR_$(1))/
+ mkdir -p $$(IDIR_$(1))/lib/apk/packages/
+
+ (cd $$(ADIR_$(1)); $($(1)_COMMANDS))
+
+ ( \
+ echo "#!/bin/sh"; \
+ echo "[ \"\$$$${IPKG_NO_SCRIPT}\" = \"1\" ] && exit 0"; \
+ echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
+ echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
+ echo 'export root="$$$${IPKG_INSTROOT}"'; \
+ echo 'export pkgname="$(1)"'; \
+ echo "add_group_and_user"; \
+ [ ! -f $$(ADIR_$(1))/postinst-pkg ] || cat "$$(ADIR_$(1))/postinst-pkg"; \
+ echo "default_postinst"; \
+ ) > $$(ADIR_$(1))/post-install;
+
+ ( \
+ echo "#!/bin/sh"; \
+ echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
+ echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
+ echo 'export root="$$$${IPKG_INSTROOT}"'; \
+ echo 'export pkgname="$(1)"'; \
+ [ ! -f $$(ADIR_$(1))/prerm-pkg ] || cat "$$(ADIR_$(1))/prerm-pkg"; \
+ echo "default_prerm"; \
+ ) > $$(ADIR_$(1))/pre-deinstall;
+
+ if [ -n "$(USERID)" ]; then echo $(USERID) > $$(IDIR_$(1))/lib/apk/packages/$(1).rusers; fi;
+ if [ -n "$(ALTERNATIVES)" ]; then echo $(ALTERNATIVES) > $$(IDIR_$(1))/lib/apk/packages/$(1).alternatives; fi;
+ (cd $$(IDIR_$(1)) && find . -type f,l -printf "/%P\n" > $$(IDIR_$(1))/lib/apk/packages/$(1).list)
+ if [ -f $$(ADIR_$(1))/conffiles ]; then mv $$(ADIR_$(1))/conffiles $$(IDIR_$(1))/lib/apk/packages/$(1).conffiles; fi;
+
+ $(FAKEROOT) $(STAGING_DIR_HOST)/bin/apk mkpkg \
+ --info "name:$(1)$$(ABIV_$(1))" \
+ --info "version:$(VERSION)" \
+ --info "description:" \
+ --info "arch:$(PKGARCH)" \
+ --info "license:$(LICENSE)" \
+ --info "origin:$(SOURCE)" \
+ --info "provides:$$(foreach prov,$$(filter-out $(1)$$(ABIV_$(1)),$(PROVIDES)$$(if $$(ABIV_$(1)), \
+ $(1) $(foreach provide,$(PROVIDES),$(provide)$$(ABIV_$(1))))),$$(prov)=$(VERSION) )" \
+ --script "post-install:$$(ADIR_$(1))/post-install" \
+ --script "pre-deinstall:$$(ADIR_$(1))/pre-deinstall" \
+ --info "depends:$$(foreach depends,$$(subst $$(comma),$$(space),$$(subst $$(space),,$$(subst $$(paren_right),,$$(subst $$(paren_left),,$$(Package/$(1)/DEPENDS))))),$$(depends))" \
+ --files "$$(IDIR_$(1))" \
+ --output "$$(PACK_$(1))" \
+ --sign "$(BUILD_KEY_APK_SEC)"
+endif
+
+ @[ -f $$(PACK_$(1)) ]
+
+ $(1)-clean:
+ifeq ($(CONFIG_USE_APK),)
+ $$(call remove_ipkg_files,$(1),$$(call opkg_package_files,$(call gen_package_wildcard,$(1))))
+else
+ $$(call remove_ipkg_files,$(1),$$(call apk_package_files,$(call gen_package_wildcard,$(1))))
+endif
+
+
+ clean: $(1)-clean
+
+ endef
+endif
include $(INCLUDE_DIR)/package-defaults.mk
include $(INCLUDE_DIR)/package-dumpinfo.mk
-include $(INCLUDE_DIR)/package-ipkg.mk
+include $(INCLUDE_DIR)/package-pack.mk
include $(INCLUDE_DIR)/package-bin.mk
include $(INCLUDE_DIR)/autotools.mk
--add-arch all:100 \
--add-arch $(if $(ARCH_PACKAGES),$(ARCH_PACKAGES),$(BOARD)):200
+apk = \
+ IPKG_INSTROOT=$(1) \
+ $(FAKEROOT) $(STAGING_DIR_HOST)/bin/apk \
+ --root $(1) \
+ --repositories-file /dev/zero \
+ --keys-dir $(TOPDIR) \
+ --no-cache \
+ --no-logfile \
+ --preserve-env \
+ --repository file://$(PACKAGE_DIR_ALL)/packages.adb
+
TARGET_DIR_ORIG := $(TARGET_ROOTFS_DIR)/root.orig-$(BOARD)
ifdef CONFIG_CLEAN_IPKG
@mkdir -p $(1)/var/lock
@( \
cd $(1); \
+ if [ -n "$(CONFIG_USE_APK)" ]; then \
+ $(STAGING_DIR_HOST)/bin/tar -xf ./lib/apk/db/scripts.tar --wildcards "*.post-install" -O > script.sh; \
+ chmod +x script.sh; \
+ IPKG_INSTROOT=$(1) $$(command -v bash) script.sh; \
+ else \
for script in ./usr/lib/opkg/info/*.postinst; do \
IPKG_INSTROOT=$(1) $$(command -v bash) $$script; \
ret=$$?; \
exit 1; \
fi; \
done; \
+ $(if $(IB),,awk -i inplace \
+ '/^Status:/ { \
+ if ($$3 == "user") { $$3 = "ok" } \
+ else { sub(/,\<user\>|\<user\>,/, "", $$3) } \
+ }1' $(1)/usr/lib/opkg/status) ; \
+ $(if $(SOURCE_DATE_EPOCH),sed -i "s/Installed-Time: .*/Installed-Time: $(SOURCE_DATE_EPOCH)/" $(1)/usr/lib/opkg/status ;) \
+ fi; \
for script in ./etc/init.d/*; do \
grep '#!/bin/sh /etc/rc.common' $$script >/dev/null || continue; \
if ! echo " $(3) " | grep -q " $$(basename $$script) "; then \
fi; \
done || true \
)
- awk -i inplace \
- '/^Status:/ { \
- if ($$3 == "user") { $$3 = "ok" } \
- else { sub(/,\<user\>|\<user\>,/, "", $$3) } \
- }1' $(1)/usr/lib/opkg/status
- $(if $(SOURCE_DATE_EPOCH),sed -i "s/Installed-Time: .*/Installed-Time: $(SOURCE_DATE_EPOCH)/" $(1)/usr/lib/opkg/status)
+
@-find $(1) -name CVS -o -name .svn -o -name .git -o -name '.#*' | $(XARGS) rm -rf
rm -rf \
$(1)/boot \
--- /dev/null
+#!/bin/sh
+. $TOPDIR/include/site/linux
+ac_cv_c_littleendian=${ac_cv_c_littleendian=yes}
+ac_cv_c_bigendian=${ac_cv_c_bigendian=no}
+
+ac_cv_sizeof___int64=0
+ac_cv_sizeof_char=1
+ac_cv_sizeof_int=4
+ac_cv_sizeof_int16_t=2
+ac_cv_sizeof_int32_t=4
+ac_cv_sizeof_int64_t=8
+ac_cv_sizeof_long_int=8
+ac_cv_sizeof_long_long=8
+ac_cv_sizeof_long=8
+ac_cv_sizeof_off_t=8
+ac_cv_sizeof_short_int=2
+ac_cv_sizeof_short=2
+ac_cv_sizeof_size_t=8
+ac_cv_sizeof_ssize_t=8
+ac_cv_sizeof_u_int16_t=2
+ac_cv_sizeof_u_int32_t=4
+ac_cv_sizeof_u_int64_t=8
+ac_cv_sizeof_uint16_t=2
+ac_cv_sizeof_uint32_t=4
+ac_cv_sizeof_uint64_t=8
+ac_cv_sizeof_unsigned_int=4
+ac_cv_sizeof_unsigned_long=8
+ac_cv_sizeof_unsigned_long_long=8
+ac_cv_sizeof_unsigned_short=2
+ac_cv_sizeof_void_p=8
logd \
mtd \
netifd \
- opkg \
uci \
uclient-fetch \
urandom-seed \
urngd
+ifdef CONFIG_USE_APK
+DEFAULT_PACKAGES+=apk
+else
+DEFAULT_PACKAGES+=opkg
+endif
+
ifneq ($(CONFIG_SELINUX),)
DEFAULT_PACKAGES+=busybox-selinux procd-selinux
else
CPU_TYPE ?= riscv64
CPU_CFLAGS_riscv64:=-mabi=lp64d -march=rv64imafdc
endif
+ ifeq ($(ARCH),loongarch64)
+ CPU_TYPE ?= generic
+ CPU_CFLAGS := -O2 -pipe
+ CPU_CFLAGS_generic:=-march=loongarch64
+ endif
ifneq ($(CPU_TYPE),)
ifndef CPU_CFLAGS_$(CPU_TYPE)
$(warning CPU_TYPE "$(CPU_TYPE)" doesn't correspond to a known type)
URL:=https://www.trustedfirmware.org/projects/tf-a/
endef
- define Package/trusted-firmware-a-$(1)/install
+ ifndef Package/trusted-firmware-a-$(1)/install
+ define Package/trusted-firmware-a-$(1)/install
$$(Package/trusted-firmware-a/install)
- endef
+ endef
+ endif
endef
define Build/Configure/Trusted-Firmware-A
-e 's,%d,\L$(call sed_escape,$(subst $(space),_,$(VERSION_DIST))),g' \
-e 's,%R,$(call sed_escape,$(REVISION)),g' \
-e 's,%T,$(call sed_escape,$(BOARD)),g' \
- -e 's,%S,$(call sed_escape,$(BOARD)/$(if $(SUBTARGET),$(SUBTARGET),generic)),g' \
+ -e 's,%S,$(call sed_escape,$(BOARD)/$(SUBTARGET)),g' \
-e 's,%A,$(call sed_escape,$(ARCH_PACKAGES)),g' \
-e 's,%t,$(call sed_escape,$(VERSION_TAINTS)),g' \
-e 's,%M,$(call sed_escape,$(VERSION_MANUFACTURER)),g' \
$(curdir)/merge:
rm -rf $(PACKAGE_DIR_ALL)
mkdir -p $(PACKAGE_DIR_ALL)
+ifneq ($(CONFIG_USE_APK),)
+ -$(foreach pdir,$(PACKAGE_SUBDIRS),$(if $(wildcard $(pdir)/*.apk),ln -s $(pdir)/*.apk $(PACKAGE_DIR_ALL);))
+else
-$(foreach pdir,$(PACKAGE_SUBDIRS),$(if $(wildcard $(pdir)/*.ipk),ln -s $(pdir)/*.ipk $(PACKAGE_DIR_ALL);))
+endif
$(curdir)/merge-index: $(curdir)/merge
+ifneq ($(CONFIG_USE_APK),)
+ (cd $(PACKAGE_DIR_ALL) && $(STAGING_DIR_HOST)/bin/apk mkndx \
+ --root $(TOPDIR) \
+ --keys-dir $(TOPDIR) \
+ --sign $(BUILD_KEY_APK_SEC) \
+ --output packages.adb \
+ *.apk; \
+ )
+else
(cd $(PACKAGE_DIR_ALL) && $(SCRIPT_DIR)/ipkg-make-index.sh . 2>&1 > Packages; )
+endif
ifndef SDK
$(curdir)//compile = $(STAGING_DIR)/.prepared $(BIN_DIR)
+ifneq ($(CONFIG_USE_APK),)
+ $(curdir)/compile: $(curdir)/system/apk/host/compile
+else
$(curdir)/compile: $(curdir)/system/opkg/host/compile
endif
+endif
-$(curdir)/install: $(TMP_DIR)/.build $(curdir)/merge $(if $(CONFIG_TARGET_PER_DEVICE_ROOTFS),$(curdir)/merge-index)
+$(curdir)/install: $(TMP_DIR)/.build $(curdir)/merge $(curdir)/merge-index
- find $(STAGING_DIR_ROOT) -type d | $(XARGS) chmod 0755
rm -rf $(TARGET_DIR) $(TARGET_DIR_ORIG)
mkdir -p $(TARGET_DIR)/tmp
+ifneq ($(CONFIG_USE_APK),)
+ $(file >$(TMP_DIR)/apk_install_list,\
+ $(foreach pkg,$(shell cat $(PACKAGE_INSTALL_FILES) 2>/dev/null),$(pkg)$(call GetABISuffix,$(pkg))))
+ $(call apk,$(TARGET_DIR)) add --initdb --no-scripts --arch $(ARCH_PACKAGES) $$(cat $(TMP_DIR)/apk_install_list)
+else
$(file >$(TMP_DIR)/opkg_install_list,\
$(call opkg_package_files,\
$(foreach pkg,$(shell cat $(PACKAGE_INSTALL_FILES) 2>/dev/null),$(pkg)$(call GetABISuffix,$(pkg)))))
$(call opkg,$(TARGET_DIR)) flag $$flag `cat $$file`; \
done; \
done || true
+endif
$(CP) $(TARGET_DIR) $(TARGET_DIR_ORIG)
$(curdir)/index: FORCE
@echo Generating package index...
+ifneq ($(CONFIG_USE_APK),)
+ @for d in $(PACKAGE_SUBDIRS); do \
+ mkdir -p $$d; \
+ cd $$d || continue; \
+ ls *.apk >/dev/null 2>&1 || continue; \
+ $(STAGING_DIR_HOST)/bin/apk mkndx \
+ --root $(TOPDIR) \
+ --keys-dir $(TOPDIR) \
+ --sign $(BUILD_KEY_APK_SEC) \
+ --output packages.adb \
+ *.apk; \
+ done
+else
@for d in $(PACKAGE_SUBDIRS); do ( \
mkdir -p $$d; \
cd $$d || continue; \
$(SCRIPT_DIR)/package-metadata.pl pkgcyclonedxsbom Packages.manifest > Packages.bom.cdx.json || true; \
); done
endif
+endif
$(curdir)/flags-install:= -j1
endef
Build/Compile = $(Build/Compile/Default)
+ifneq ($(CONFIG_USE_APK),)
+ define Build/Configure
+ [ -s $(BUILD_KEY_APK_SEC) -a -s $(BUILD_KEY_APK_PUB) ] || \
+ $(STAGING_DIR_HOST)/bin/openssl ecparam -name prime256v1 -genkey -noout -out $(BUILD_KEY_APK_SEC); \
+ $(STAGING_DIR_HOST)/bin/openssl ec -in $(BUILD_KEY_APK_SEC) -pubout > $(BUILD_KEY_APK_PUB)
+ endef
+
+ifndef CONFIG_BUILDBOT
+ define Package/base-files/install-key
+ mkdir -p $(1)/etc/apk/keys
+ $(CP) $(BUILD_KEY_APK_PUB) $(1)/etc/apk/keys/
+ endef
+endif
+else
ifdef CONFIG_SIGNED_PACKAGES
define Build/Configure
[ -s $(BUILD_KEY) -a -s $(BUILD_KEY).pub ] || \
define Package/base-files/install-key
mkdir -p $(1)/etc/opkg/keys
$(CP) $(BUILD_KEY).pub $(1)/etc/opkg/keys/`$(STAGING_DIR_HOST)/bin/usign -F -p $(BUILD_KEY).pub`
-
endef
endif
endif
+endif
ifeq ($(CONFIG_NAND_SUPPORT),)
define Package/base-files/nand-support
cat $(BIN_DIR)/feeds.buildinfo >>$(1)/etc/build.feeds; \
cat $(BIN_DIR)/version.buildinfo >>$(1)/etc/build.version)
+ $(if $(CONFIG_TARGET_PREINIT_DISABLE_FAILSAFE), \
+ rm -f $(1)/etc/banner.failsafe,)
+
+ifneq ($(CONFIG_USE_APK),)
+ mkdir -p $(1)/etc/apk/
+ $(call FeedSourcesAppendAPK,$(1)/etc/apk/repositories)
+ $(VERSION_SED_SCRIPT) $(1)/etc/apk/repositories
+else
$(if $(CONFIG_CLEAN_IPKG),, \
mkdir -p $(1)/etc/opkg; \
- $(call FeedSourcesAppend,$(1)/etc/opkg/distfeeds.conf); \
+ $(call FeedSourcesAppendOPKG,$(1)/etc/opkg/distfeeds.conf); \
$(VERSION_SED_SCRIPT) $(1)/etc/opkg/distfeeds.conf)
$(if $(CONFIG_IPK_FILES_CHECKSUMS),, \
rm -f $(1)/sbin/pkg_check)
-
- $(if $(CONFIG_TARGET_PREINIT_DISABLE_FAILSAFE), \
- rm -f $(1)/etc/banner.failsafe,)
+endif
endef
ifneq ($(DUMP),1)
[ "$(uci -q get network.globals.ula_prefix)" != "auto" ] && exit 0
-r1=$(dd if=/dev/urandom bs=1 count=1 |hexdump -e '1/1 "%02x"')
-r2=$(dd if=/dev/urandom bs=2 count=1 |hexdump -e '2/1 "%02x"')
-r3=$(dd if=/dev/urandom bs=2 count=1 |hexdump -e '2/1 "%02x"')
-
uci -q batch <<-EOF >/dev/null
- set network.globals.ula_prefix=fd$r1:$r2:$r3::/48
+ set network.globals.ula_prefix="$(hexdump -vn 5 -e '"fd" 1/1 "%02x:" 2/2 "%x:"' /dev/urandom):/48"
commit network
EOF
printf "%0${retlen}x" "$ret"
}
+data_2bin() {
+ local data=$1
+ local len=${#1}
+ local bin_data
+
+ for i in $(seq 0 2 $(($len - 1))); do
+ bin_data="${bin_data}\x${data:i:2}"
+ done
+
+ echo -ne $bin_data
+}
+
+data_2xor_val() {
+ local data=$1
+ local len=${#1}
+ local xor_data
+
+ for i in $(seq 0 4 $(($len - 1))); do
+ xor_data="${xor_data}${data:i:4} "
+ done
+
+ echo -n ${xor_data:0:-1}
+}
+
append() {
local var="$1"
local value="$2"
default_prerm() {
local root="${IPKG_INSTROOT}"
- local pkgname="$(basename ${1%.*})"
+ [ -z "$pkgname" ] && local pkgname="$(basename ${1%.*})"
local ret=0
+ local filelist="${root}/usr/lib/opkg/info/${pkgname}.list"
+ [ -f "$root/lib/apk/packages/${pkgname}.list" ] && filelist="$root/lib/apk/packages/${pkgname}.list"
if [ -f "$root/usr/lib/opkg/info/${pkgname}.prerm-pkg" ]; then
( . "$root/usr/lib/opkg/info/${pkgname}.prerm-pkg" )
fi
local shell="$(command -v bash)"
- for i in $(grep -s "^/etc/init.d/" "$root/usr/lib/opkg/info/${pkgname}.list"); do
+ for i in $(grep -s "^/etc/init.d/" "$filelist"); do
if [ -n "$root" ]; then
${shell:-/bin/sh} "$root/etc/rc.common" "$root$i" disable
else
}
add_group_and_user() {
- local pkgname="$1"
+ [ -z "$pkgname" ] && local pkgname="$(basename ${1%.*})"
local rusers="$(sed -ne 's/^Require-User: *//p' $root/usr/lib/opkg/info/${pkgname}.control 2>/dev/null)"
+ if [ -f "$root/lib/apk/packages/${pkgname}.rusers" ]; then
+ local rusers="$(cat $root/lib/apk/packages/${pkgname}.rusers)"
+ fi
if [ -n "$rusers" ]; then
local tuple oIFS="$IFS"
fi
}
+update_alternatives() {
+ local root="${IPKG_INSTROOT}"
+ local action="$1"
+ local pkgname="$2"
+
+ if [ -f "$root/lib/apk/packages/${pkgname}.alternatives" ]; then
+ for pkg_alt in $(cat $root/lib/apk/packages/${pkgname}.alternatives); do
+ local best_prio=0;
+ local best_src="/bin/busybox";
+ pkg_prio=${pkg_alt%%:*};
+ pkg_target=${pkg_alt#*:};
+ pkg_target=${pkg_target%:*};
+ pkg_src=${pkg_alt##*:};
+
+ if [ -e "$root/$target" ]; then
+ for alts in $root/lib/apk/packages/*.alternatives; do
+ for alt in $(cat $alts); do
+ prio=${alt%%:*};
+ target=${alt#*:};
+ target=${target%:*};
+ src=${alt##*:};
+
+ if [ "$target" = "$pkg_target" ] &&
+ [ "$src" != "$pkg_src" ] &&
+ [ "$best_prio" -lt "$prio" ]; then
+ best_prio=$prio;
+ best_src=$src;
+ fi
+ done
+ done
+ fi
+ case "$action" in
+ install)
+ if [ "$best_prio" -lt "$pkg_prio" ]; then
+ ln -sf "$pkg_src" "$root/$pkg_target"
+ echo "add alternative: $pkg_target -> $pkg_src"
+ fi
+ ;;
+ remove)
+ if [ "$best_prio" -lt "$pkg_prio" ]; then
+ ln -sf "$best_src" "$root/$pkg_target"
+ echo "add alternative: $pkg_target -> $best_src"
+ fi
+ ;;
+ esac
+ done
+ fi
+}
+
default_postinst() {
local root="${IPKG_INSTROOT}"
- local pkgname="$(basename ${1%.*})"
- local filelist="/usr/lib/opkg/info/${pkgname}.list"
+ [ -z "$pkgname" ] && local pkgname="$(basename ${1%.*})"
+ local filelist="${root}/usr/lib/opkg/info/${pkgname}.list"
+ [ -f "$root/lib/apk/packages/${pkgname}.list" ] && filelist="$root/lib/apk/packages/${pkgname}.list"
local ret=0
- add_group_and_user "${pkgname}"
+ if [ -e "${root}/usr/lib/opkg/info/${pkgname}.list" ]; then
+ filelist="${root}/usr/lib/opkg/info/${pkgname}.list"
+ add_group_and_user "${pkgname}"
+ fi
+
+ if [ -e "${root}/lib/apk/packages/${pkgname}.list" ]; then
+ filelist="${root}/lib/apk/packages/${pkgname}.list"
+ update_alternatives install "${pkgname}"
+ fi
if [ -d "$root/rootfs-overlay" ]; then
cp -R $root/rootfs-overlay/. $root/
fi
local shell="$(command -v bash)"
- for i in $(grep -s "^/etc/init.d/" "$root$filelist"); do
+ for i in $(grep -s "^/etc/init.d/" "$filelist"); do
if [ -n "$root" ]; then
${shell:-/bin/sh} "$root/etc/rc.common" "$root$i" enable
else
return
fi
gids=$(cut -d: -f3 ${IPKG_INSTROOT}/etc/group)
- gid=65536
+ gid=32768
while echo "$gids" | grep -q "^$gid$"; do
gid=$((gid + 1))
done
local rc
[ -z "$uid" ] && {
uids=$(cut -d: -f3 ${IPKG_INSTROOT}/etc/passwd)
- uid=65536
+ uid=32768
while echo "$uids" | grep -q "^$uid$"; do
uid=$((uid + 1))
done
local caldata
mtd=$(find_mtd_chardev "$part")
- reversed=$(hexdump -v -s $offset -n $count -e '/1 "%02x "' $mtd)
+ reversed=$(hexdump -v -s $offset -n $count -e '1/1 "%02x "' $mtd)
for byte in $reversed; do
caldata="\x${byte}${caldata}"
return $?
}
-caldata_patch_chksum() {
- local mac=$1
- local mac_offset=$(($2))
+caldata_patch_data() {
+ local data=$1
+ local data_count=$((${#1} / 2))
+ local data_offset=$(($2))
local chksum_offset=$(($3))
local target=$4
- local xor_mac
- local xor_fw_mac
- local xor_fw_chksum
+ local fw_data
+ local fw_chksum
- xor_mac=${mac//:/}
- xor_mac="${xor_mac:0:4} ${xor_mac:4:4} ${xor_mac:8:4}"
+ [ -z "$data" -o -z "$data_offset" ] && return
- xor_fw_mac=$(hexdump -v -n 6 -s $mac_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE)
- xor_fw_mac="${xor_fw_mac:0:4} ${xor_fw_mac:4:4} ${xor_fw_mac:8:4}"
+ [ -n "$target" ] || target=/lib/firmware/$FIRMWARE
- xor_fw_chksum=$(hexdump -v -n 2 -s $chksum_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE)
- xor_fw_chksum=$(xor $xor_fw_chksum $xor_fw_mac $xor_mac)
+ fw_data=$(hexdump -v -n $data_count -s $data_offset -e '1/1 "%02x"' $target)
- printf "%b" "\x${xor_fw_chksum:0:2}\x${xor_fw_chksum:2:2}" | \
- dd of=$target conv=notrunc bs=1 seek=$chksum_offset count=2
-}
+ if [ "$data" != "$fw_data" ]; then
-caldata_patch_mac() {
- local mac=$1
- local mac_offset=$(($2))
- local chksum_offset=$3
- local target=$4
-
- [ -z "$mac" -o -z "$mac_offset" ] && return
+ if [ -n "$chksum_offset" ]; then
+ fw_chksum=$(hexdump -v -n 2 -s $chksum_offset -e '1/1 "%02x"' $target)
+ fw_chksum=$(xor $fw_chksum $(data_2xor_val $fw_data) $(data_2xor_val $data))
- [ -n "$target" ] || target=/lib/firmware/$FIRMWARE
+ data_2bin $fw_chksum | \
+ dd of=$target conv=notrunc bs=1 seek=$chksum_offset count=2 || \
+ caldata_die "failed to write chksum to eeprom file"
+ fi
- [ -n "$chksum_offset" ] && caldata_patch_chksum "$mac" "$mac_offset" "$chksum_offset" "$target"
-
- macaddr_2bin $mac | dd of=$target conv=notrunc oflag=seek_bytes bs=6 seek=$mac_offset count=1 || \
- caldata_die "failed to write MAC address to eeprom file"
+ data_2bin $data | \
+ dd of=$target conv=notrunc bs=1 seek=$data_offset count=$data_count || \
+ caldata_die "failed to write data to eeprom file"
+ fi
}
ath9k_patch_mac() {
local mac=$1
local target=$2
- caldata_patch_mac "$mac" 0x2 "" "$target"
+ caldata_patch_data "${mac//:/}" 0x2 "" "$target"
}
ath9k_patch_mac_crc() {
local chksum_offset=$((mac_offset - 10))
local target=$4
- caldata_patch_mac "$mac" "$mac_offset" "$chksum_offset" "$target"
+ caldata_patch_data "${mac//:/}" "$mac_offset" "$chksum_offset" "$target"
}
ath10k_patch_mac() {
local mac=$1
local target=$2
- caldata_patch_mac "$mac" 0x6 0x2 "$target"
+ caldata_patch_data "${mac//:/}" 0x6 0x2 "$target"
+}
+
+ath11k_patch_mac() {
+ local mac=$1
+ # mac_id from 0 to 5
+ local mac_id=$2
+ local target=$3
+
+ [ -z "$mac_id" ] && return
+
+ caldata_patch_data "${mac//:/}" $(printf "0x%x" $(($mac_id * 0x6 + 0xe))) 0xa "$target"
+}
+
+ath10k_remove_regdomain() {
+ local target=$1
+
+ caldata_patch_data "0000" 0xc 0x2 "$target"
+}
+
+ath11k_remove_regdomain() {
+ local target=$1
+ local regdomain
+ local regdomain_data
+
+ regdomain=$(hexdump -v -n 2 -s 0x34 -e '1/1 "%02x"' $target)
+ caldata_patch_data "0000" 0x34 0xa "$target"
+
+ for offset in 0x450 0x458 0x500 0x5a8; do
+ regdomain_data=$(hexdump -v -n 2 -s $offset -e '1/1 "%02x"' $target)
+
+ if [ "$regdomain" == "$regdomain_data" ]; then
+ caldata_patch_data "0000" $offset 0xa "$target"
+ fi
+ done
+}
+
+ath11k_set_macflag() {
+ local target=$1
+
+ caldata_patch_data "0100" 0x3e 0xa "$target"
}
echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${randsrc}")")"
}
-macaddr_2bin() {
- local mac=$1
-
- echo -ne \\x${mac//:/\\x}
-}
-
macaddr_canonicalize() {
local mac="$1"
local canon=""
NAND_TYPE:=
BOARD_QFN:=
DRAM_USE_COMB:=
+ RAM_BOOT_UART_DL:=
USE_UBI:=
endef
DDR3_FLYBY:=1
endef
+define Trusted-Firmware-A/mt7981-ram-ddr4
+ NAME:=MediaTek MT7981 (RAM, DDR4)
+ BOOT_DEVICE:=ram
+ BUILD_SUBTARGET:=filogic
+ PLAT:=mt7981
+ DDR_TYPE:=ddr4
+ RAM_BOOT_UART_DL:=1
+ HIDDEN:=
+ DEFAULT:=TARGET_mediatek_filogic
+endef
+
define Trusted-Firmware-A/mt7981-emmc-ddr4
NAME:=MediaTek MT7981 (eMMC, DDR4)
BOOT_DEVICE:=emmc
DDR_TYPE:=ddr3
endef
+define Trusted-Firmware-A/mt7981-ram-ddr3
+ NAME:=MediaTek MT7981 (RAM, DDR3)
+ BOOT_DEVICE:=ram
+ BUILD_SUBTARGET:=filogic
+ PLAT:=mt7981
+ DDR_TYPE:=ddr3
+ RAM_BOOT_UART_DL:=1
+ HIDDEN:=
+ DEFAULT:=TARGET_mediatek_filogic
+endef
+
+define Trusted-Firmware-A/mt7981-nor-ddr4
+ NAME:=MediaTek MT7981 (SPI-NOR, DDR4)
+ BOOT_DEVICE:=nor
+ BUILD_SUBTARGET:=filogic
+ PLAT:=mt7981
+ DDR_TYPE:=ddr4
+endef
+
define Trusted-Firmware-A/mt7981-emmc-ddr3
NAME:=MediaTek MT7981 (eMMC, DDR3)
BOOT_DEVICE:=emmc
DDR_TYPE:=ddr3
endef
+define Trusted-Firmware-A/mt7986-ram-ddr4
+ NAME:=MediaTek MT7986 (RAM, DDR4)
+ BOOT_DEVICE:=ram
+ BUILD_SUBTARGET:=filogic
+ PLAT:=mt7986
+ DDR_TYPE:=ddr4
+ RAM_BOOT_UART_DL:=1
+ HIDDEN:=
+ DEFAULT:=TARGET_mediatek_filogic
+endef
+
+define Trusted-Firmware-A/mt7981-spim-nand-ubi-ddr4
+ NAME:=MediaTek MT7981 (SPI-NAND via SPIM, DDR4)
+ BOOT_DEVICE:=spim-nand
+ BUILD_SUBTARGET:=filogic
+ PLAT:=mt7981
+ DDR_TYPE:=ddr4
+ USE_UBI:=1
+endef
+
define Trusted-Firmware-A/mt7986-nor-ddr4
NAME:=MediaTek MT7986 (SPI-NOR, DDR4)
BOOT_DEVICE:=nor
NAND_TYPE:=spim:4k+256
endef
+define Trusted-Firmware-A/mt7986-ram-ddr3
+ NAME:=MediaTek MT7986 (RAM, DDR3)
+ BOOT_DEVICE:=ram
+ BUILD_SUBTARGET:=filogic
+ PLAT:=mt7986
+ DDR_TYPE:=ddr3
+ RAM_BOOT_UART_DL:=1
+ HIDDEN:=
+ DEFAULT:=TARGET_mediatek_filogic
+endef
+
define Trusted-Firmware-A/mt7986-nor-ddr3
NAME:=MediaTek MT7986 (SPI-NOR, DDR3)
BOOT_DEVICE:=nor
DDR_TYPE:=ddr4
endef
+define Trusted-Firmware-A/mt7988-ram-comb
+ NAME:=MediaTek MT7988 (RAM)
+ BOOT_DEVICE:=ram
+ BUILD_SUBTARGET:=filogic
+ PLAT:=mt7988
+ DRAM_USE_COMB:=1
+ RAM_BOOT_UART_DL:=1
+ HIDDEN:=
+ DEFAULT:=TARGET_mediatek_filogic
+endef
+
define Trusted-Firmware-A/mt7988-nor-comb
NAME:=MediaTek MT7988 (SPI-NOR)
BOOT_DEVICE:=nor
mt7622-emmc-2ddr \
mt7622-sdmmc-1ddr \
mt7622-sdmmc-2ddr \
+ mt7981-ram-ddr3 \
mt7981-emmc-ddr3 \
mt7981-nor-ddr3 \
+ mt7981-nor-ddr4 \
mt7981-sdmmc-ddr3 \
mt7981-snand-ddr3 \
mt7981-spim-nand-ddr3 \
+ mt7981-spim-nand-ubi-ddr4 \
+ mt7981-ram-ddr4 \
mt7981-emmc-ddr4 \
mt7981-spim-nand-ddr4 \
+ mt7986-ram-ddr3 \
mt7986-emmc-ddr3 \
mt7986-nor-ddr3 \
mt7986-sdmmc-ddr3 \
mt7986-snand-ddr3 \
mt7986-spim-nand-ddr3 \
+ mt7986-ram-ddr4 \
mt7986-emmc-ddr4 \
mt7986-nor-ddr4 \
mt7986-sdmmc-ddr4 \
mt7988-sdmmc-ddr4 \
mt7988-snand-ddr4 \
mt7988-spim-nand-ddr4 \
+ mt7988-ram-comb \
mt7988-emmc-comb \
mt7988-nor-comb \
mt7988-sdmmc-comb \
HAVE_DRAM_OBJ_FILE=yes \
$(if $(DDR3_FLYBY),DDR3_FLYBY=1) \
$(if $(DRAM_USE_COMB),DRAM_USE_COMB=1) \
+ $(if $(RAM_BOOT_UART_DL),RAM_BOOT_UART_DL=1) \
$(if $(USE_UBI),UBI=1 $(if $(findstring mt7622,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x80000)) \
+ $(if $(USE_UBI),UBI=1 $(if $(findstring mt7981,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x100000)) \
all
+define Package/trusted-firmware-a-ram/install
+ $(INSTALL_DIR) $(STAGING_DIR_IMAGE)
+ $(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl2.bin $(BIN_DIR)/$(BUILD_VARIANT)-bl2.bin
+endef
+Package/trusted-firmware-a-mt7981-ram-ddr3/install = $(Package/trusted-firmware-a-ram/install)
+Package/trusted-firmware-a-mt7981-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install)
+Package/trusted-firmware-a-mt7986-ram-ddr3/install = $(Package/trusted-firmware-a-ram/install)
+Package/trusted-firmware-a-mt7986-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install)
+Package/trusted-firmware-a-mt7988-ram-comb/install = $(Package/trusted-firmware-a-ram/install)
+
define Package/trusted-firmware-a/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl2.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-bl2.img
include $(TOPDIR)/rules.mk
PKG_VERSION:=2.9
-PKG_RELEASE:=1
+PKG_RELEASE:=2
PKG_HASH:=76a66a1de0c01aeb83dfc7b72b51173fe62c6e51d6fca17cc562393117bed08b
PKG_MAINTAINER:=Vladimir Vid <vladimir.vid@sartura.hr>
FILE:=$(A3700_UTILS_SOURCE)
PROTO:=git
URL:=https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
- VERSION:=a3e1c67bb378e1d8a938e1b826cb602af83628d2
+ SOURCE_VERSION:=a3e1c67bb378e1d8a938e1b826cb602af83628d2
MIRROR_HASH:=0e6b8ef6423dcb52a5e282669a8aeebc6eea2d45a7c3a2c9a2fc7a749b3275a7
SUBDIR:=$(A3700_UTILS_NAME)
endef
FILE:=$(CRYPTOPP_SOURCE)
PROTO:=git
URL:=https://github.com/weidai11/cryptopp.git
- VERSION:=4d0cad5401d1a2c998b314bc89288c9620d3021d
- MIRROR_HASH:=74ec9e48ee04b9f2d9a1d8c4f2392ed0ab52780d7af0f70405d7bbb23d1504fa
+ SOURCE_VERSION:=4d0cad5401d1a2c998b314bc89288c9620d3021d
+ MIRROR_HASH:=6c53c8b4dfa07df0c5915a90c20f70c64d150b652cf5ac52e2eae08c5a9cc7cd
SUBDIR:=$(CRYPTOPP_NAME)
endef
FILE:=$(MV_DDR_SOURCE)
PROTO:=git
URL:=https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
- VERSION:=541616bc5d25a0167c9901546255c55973e2c0f0
+ SOURCE_VERSION:=541616bc5d25a0167c9901546255c55973e2c0f0
MIRROR_HASH:=9e86a986c7400ed1a72165a88150b6c494ebd87303b16314b43e5785e3f13068
SUBDIR:=$(MV_DDR_NAME)
endef
PROTO:=git
SUBMODULES:=skip
URL:=https://gitlab.nic.cz/turris/mox-boot-builder.git
- VERSION:=604f8f51d97b4e59fa6d1e579101daa194d6ed2d
+ SOURCE_VERSION:=604f8f51d97b4e59fa6d1e579101daa194d6ed2d
MIRROR_HASH:=b09337a7dde140f57e40133b6e7b7e1eb338e7cea9b15a3af6874824462f15f7
SUBDIR:=$(MOX_BB_NAME)
endef
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=grub
-PKG_VERSION:=2.06
-PKG_RELEASE:=6
+PKG_VERSION:=2.12
+PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNU/grub
-PKG_HASH:=b79ea44af91b93d17cd3fe80bdae6ed43770678a9a5ae192ccea803ebb657ee1
+PKG_HASH:=f3c97391f7c4eaa677a78e090c7e97e6dc47b16f655f04683ebd37bef7fe0faa
PKG_LICENSE:=GPL-3.0-or-later
PKG_CPE_ID:=cpe:/a:gnu:grub2
Package/grub2=$(call Package/grub2/Default,x86,pc)
Package/grub2-efi=$(call Package/grub2/Default,x86,efi)
Package/grub2-efi-arm=$(call Package/grub2/Default,armsr,efi)
+Package/grub2-efi-loongarch64=$(call Package/grub2/Default,loongarch64,efi)
define Package/grub2-editenv
CATEGORY:=Utilities
reboot serial test efi_gop
endef
+define Package/grub2-efi-loongarch64/install
+ $(INSTALL_DIR) $(STAGING_DIR_IMAGE)/grub2
+ cp ./files/grub-early-gpt.cfg $(PKG_BUILD_DIR)/grub-early.cfg
+ $(STAGING_DIR_HOST)/bin/grub-mkimage \
+ -d $(PKG_BUILD_DIR)/grub-core \
+ -p /boot/grub \
+ -O loongarch64-efi \
+ -c $(PKG_BUILD_DIR)/grub-early.cfg \
+ -o $(STAGING_DIR_IMAGE)/grub2/bootloongarch64.efi \
+ boot chain configfile fat linux ls lsefi minicmd part_gpt part_msdos reboot search \
+ search_fs_uuid search_label serial efi_gop all_video gfxterm ext2
+endef
+
define Package/grub2-editenv/install
$(INSTALL_DIR) $(1)/usr/sbin
$(eval $(call BuildPackage,grub2))
$(eval $(call BuildPackage,grub2-efi))
$(eval $(call BuildPackage,grub2-efi-arm))
+$(eval $(call BuildPackage,grub2-efi-loongarch64))
$(eval $(call BuildPackage,grub2-editenv))
$(eval $(call BuildPackage,grub2-bios-setup))
--- /dev/null
+From 4d4dae6a52b1749642261a15f5dcc1e3d4150b36 Mon Sep 17 00:00:00 2001
+From: Julien Olivain <ju.o@free.fr>
+Date: Fri, 22 Dec 2023 19:02:53 +0100
+Subject: [PATCH] Add missing grub-core/extra_deps.lst file in release tarball
+
+A file is missing in the grub-2.12 release tarballs (both .gz and .xz).
+See [1]. The issue was reported in [2] and fixed upstream in [3].
+
+This patch adds the missing file, on top of the release tarball. This
+patch won't apply on upstream git, since the file is present in the
+source repository. Since the issue is fixed upstream in [3], it is
+expected upcoming releases tarballs will include the file.
+
+The file content was fetched from the upstream git repo:
+https://git.savannah.gnu.org/gitweb/?p=grub.git;a=blob_plain;f=grub-core/extra_deps.lst;hb=refs/tags/grub-2.12
+
+[1] https://ftp.gnu.org/gnu/grub/grub-2.12.tar.xz
+[2] https://lists.gnu.org/archive/html/grub-devel/2023-12/msg00054.html
+[3] https://git.savannah.gnu.org/gitweb/?p=grub.git;a=commit;h=b835601c7639ed1890f2d3db91900a8506011a8e
+
+Signed-off-by: Julien Olivain <ju.o@free.fr>
+Upstream: Fixed by: https://git.savannah.gnu.org/gitweb/?p=grub.git;a=commit;h=b835601c7639ed1890f2d3db91900a8506011a8e
+---
+ grub-core/extra_deps.lst | 1 +
+ 1 file changed, 1 insertion(+)
+ create mode 100644 grub-core/extra_deps.lst
+
+--- /dev/null
++++ b/grub-core/extra_deps.lst
+@@ -0,0 +1 @@
++depends bli part_gpt
--- a/include/grub/util/install.h
+++ b/include/grub/util/install.h
-@@ -198,13 +198,13 @@ grub_install_get_image_target (const cha
+@@ -199,13 +199,13 @@ grub_install_get_image_target (const cha
void
grub_util_bios_setup (const char *dir,
const char *boot_file, const char *core_file,
--- a/util/grub-install.c
+++ b/util/grub-install.c
-@@ -1721,7 +1721,7 @@ main (int argc, char *argv[])
+@@ -1770,7 +1770,7 @@ main (int argc, char *argv[])
if (install_bootsector)
{
grub_util_bios_setup (platdir, "boot.img", "core.img",
fs_probe, allow_floppy, add_rs_codes,
!grub_install_is_short_mbrgap_supported ());
-@@ -1752,7 +1752,7 @@ main (int argc, char *argv[])
+@@ -1801,7 +1801,7 @@ main (int argc, char *argv[])
if (install_bootsector)
{
grub_util_sparc_setup (platdir, "boot.img", "core.img",
include $(TOPDIR)/rules.mk
PKG_NAME:=opensbi
-PKG_RELEASE:=1.2
+PKG_RELEASE:=1.4
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/riscv/opensbi
-PKG_SOURCE_DATE:=2022-12-24
-PKG_SOURCE_VERSION:=6b5188ca14e59ce7bf71afe4e7d3d557c3d31bf8
-PKG_MIRROR_HASH:=5939a3225cb37c1dde0b5b9f28f9980c0712533676774ae244d6d84bb09a1439
+PKG_SOURCE_DATE:=2023-12-24
+PKG_SOURCE_VERSION:=a2b255b88918715173942f2c5e1f97ac9e90c877
+PKG_MIRROR_HASH:=a81d7b3622feba80b2a45fe0d38600be73cfbee64a0426be82a71545c10c54d3
PKG_BUILD_DIR=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git
-PKG_SOURCE_DATE:=2023-07-26
-PKG_SOURCE_VERSION:=b4558da0860ca48bf1a571dd33ccba580b9abe23
-PKG_MIRROR_HASH:=7cd2cb8357fa850eb4eef94db49a2c46cf910bfe4e673eff9071413bb002afc9
+PKG_SOURCE_URL:=https://github.com/rockchip-linux/rkbin.git
+PKG_SOURCE_DATE:=2024-02-22
+PKG_SOURCE_VERSION:=a2a0b89b6c8c612dca5ed9ed8a68db8a07f68bc0
+PKG_MIRROR_HASH:=39f15e5f8fac02026065b6747b355b93f4e06202783ae448c43607763211597c
PKG_LICENSE_FILES:=LICENSE
PKG_MAINTAINER:=Tianling Shen <cnsztl@immortalwrt.org>
define Trusted-Firmware-A/rk3566
BUILD_SUBTARGET:=armv8
- ATF:=rk35/rk3568_bl31_v1.43.elf
- TPL:=rk35/rk3566_ddr_1056MHz_v1.18.bin
+ ATF:=rk35/rk3568_bl31_v1.44.elf
+ TPL:=rk35/rk3566_ddr_1056MHz_v1.21.bin
endef
define Trusted-Firmware-A/rk3568
BUILD_SUBTARGET:=armv8
- ATF:=rk35/rk3568_bl31_v1.43.elf
- TPL:=rk35/rk3568_ddr_1560MHz_v1.18.bin
+ ATF:=rk35/rk3568_bl31_v1.44.elf
+ TPL:=rk35/rk3568_ddr_1560MHz_v1.21.bin
endef
TFA_TARGETS:= \
--- /dev/null
+include $(TOPDIR)/rules.mk
+
+PKG_VERSION:=2024.04
+PKG_HASH:=18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a
+PKG_RELEASE:=$(AUTORELEASE)
+
+include $(INCLUDE_DIR)/u-boot.mk
+include $(INCLUDE_DIR)/package.mk
+
+define U-Boot/Default
+ BUILD_TARGET:=bmips
+ BUILD_SUBTARGET:=bcm6328
+ UBOOT_CONFIG:=inteno_xg6846_ram
+ UBOOT_BOARD:=$(1)
+endef
+
+define U-Boot/xg6846
+ NAME:=Inteno XG6846
+ BUILD_DEVICES:=inteno_xg6846
+endef
+
+UBOOT_TARGETS := xg6846
+
+define Build/InstallDev
+ $(INSTALL_DIR) $(STAGING_DIR_IMAGE)
+ $(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-u-boot.bin
+endef
+
+define Package/u-boot/install/default
+endef
+
+$(eval $(call BuildPackage/U-Boot))
define U-Boot/Default
BUILD_TARGET:=d1
+ BUILD_SUBTARGET:=generic
UBOOT_IMAGE:=u-boot-sunxi-with-spl.bin
UENV:=default
DTS_DIR:=arch/riscv/dts
alfa-network,pi-wifi4|\
alfa-network,r36a|\
alfa-network,tube-2hq|\
-allnet,all-wap02860ac|\
araknis,an-300-ap-i-n|\
-araknis,an-500-ap-i-ac|\
-araknis,an-700-ap-i-ac|\
arduino,yun|\
asus,rt-ac59u|\
asus,rt-ac59u-v2|\
asus,zenwifi-cd6r|\
buffalo,bhr-4grv2|\
devolo,magic-2-wifi|\
-engenius,eap1200h|\
-engenius,eap1750h|\
engenius,eap300-v2|\
engenius,eap350-v1|\
engenius,eap600|\
engenius,ecb600|\
engenius,enh202-v1|\
engenius,ens202ext-v1|\
-engenius,enstationac-v1|\
-engenius,ews660ap|\
etactica,eg200|\
glinet,gl-ar750s-nor|\
glinet,gl-ar750s-nor-nand|\
ubnt,rocket-m|\
watchguard,ap100|\
watchguard,ap200|\
-watchguard,ap300|\
yuncore,a770|\
yuncore,a782|\
yuncore,a930|\
linksys,whw01)
ubootenv_add_uci_config "/dev/mtd6" "0x0" "0x40000" "0x10000"
;;
+linksys,whw03)
+ ubootenv_add_uci_config "/dev/mmcblk0p11" "0x0" "0x100000"
+ ;;
linksys,whw03v2)
ubootenv_add_uci_config "/dev/mtd6" "0x0" "0x80000" "0x20000"
;;
;;
bananapi,bpi-r3|\
bananapi,bpi-r3-mini|\
-bananapi,bpi-r4)
+bananapi,bpi-r4|\
+bananapi,bpi-r4-poe|\
+jdcloud,re-cp-03)
. /lib/upgrade/common.sh
bootdev="$(fitblk_get_bootdev)"
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x80000"
;;
cetron,ct3003|\
+edgecore,eap111|\
netgear,wax220|\
zbtlink,zbt-z8102ax|\
zbtlink,zbt-z8103ax)
glinet,gl-mt3000)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x20000"
;;
-jdcloud,re-cp-03)
- local envdev=$(find_mmc_part "ubootenv" "mmcblk0")
- ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
- ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
- ;;
mercusys,mr90x-v1|\
routerich,ax3000)
local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
ubnt,unifi-6-lr-v3-ubootmod)
ubootenv_add_uci_config "/dev/mtd$(find_mtd_index "u-boot-env")" "0x0" "0x4000" "0x1000"
;;
+ubnt,unifi-6-lr-v2)
+ ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x1000" "0x1000" "1"
+ ;;
xiaomi,redmi-router-ax6s)
ubootenv_add_uci_config "/dev/mtd3" "0x0" "0x10000" "0x40000"
;;
;;
linksys,mx4200v1|\
linksys,mx4200v2|\
-linksys,mx5300)
+linksys,mx5300|\
+linksys,mx8500)
idx="$(find_mtd_index u_env)"
[ -n "$idx" ] && \
ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" "2"
[ -n "$idx" ] && \
ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x20000" "0x20000" "1"
;;
+spectrum,sax1v1k)
+ mmcpart="$(find_mmc_part 0:APPSBLENV)"
+ [ -n "$mmcpart" ] && \
+ ubootenv_add_uci_config "$mmcpart" "0x0" "0x40000" "0x40000" "1"
+ ;;
esac
config_load ubootenv
linksys,ea7500-v2|\
linksys,ea8100-v1|\
linksys,ea8100-v2|\
-mts,wg430223)
+mts,wg430223|\
+ubnt,edgerouter-x|\
+ubnt,edgerouter-x-sfp)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x1000" "0x20000"
;;
snr,snr-cpe-me1|\
DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3
endef
+define U-Boot/mt7981_openwrt_one-snand
+ NAME:=OpenWrt One NAND
+ BUILD_SUBTARGET:=filogic
+ BUILD_DEVICES:=openwrt_one
+ UBOOT_CONFIG:=mt7981_openwrt-one-spi-nand
+ UBOOT_IMAGE:=u-boot.fip
+ BL2_BOOTDEV:=spim-nand-ubi
+ BL2_SOC:=mt7981
+ BL2_DDRTYPE:=ddr4
+ DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ubi-ddr4
+endef
+
+define U-Boot/mt7981_openwrt_one-nor
+ NAME:=OpenWrt One NOR
+ BUILD_SUBTARGET:=filogic
+ BUILD_DEVICES:=openwrt_one
+ UBOOT_CONFIG:=mt7981_openwrt-one-nor
+ UBOOT_IMAGE:=u-boot.fip
+ BL2_BOOTDEV:=nor
+ BL2_SOC:=mt7981
+ BL2_DDRTYPE:=ddr4
+ FIP_COMPRESS:=1
+ DEPENDS:=+trusted-firmware-a-mt7981-nor-ddr4
+endef
+
define U-Boot/mt7981_rfb-spim-nand
NAME:=MT7981 Reference Board
BUILD_SUBTARGET:=filogic
DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ubi-comb
endef
+define U-Boot/mt7988_bananapi_bpi-r4-poe-emmc
+ NAME:=BananaPi BPi-R4 2.5GE
+ BUILD_SUBTARGET:=filogic
+ BUILD_DEVICES:=bananapi_bpi-r4-poe
+ UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-poe-emmc
+ UBOOT_IMAGE:=u-boot.fip
+ BL2_BOOTDEV:=emmc
+ BL2_SOC:=mt7988
+ BL2_DDRTYPE:=comb
+ DEPENDS:=+trusted-firmware-a-mt7988-emmc-comb
+endef
+
+define U-Boot/mt7988_bananapi_bpi-r4-poe-sdmmc
+ NAME:=BananaPi BPi-R4 2.5GE
+ BUILD_SUBTARGET:=filogic
+ BUILD_DEVICES:=bananapi_bpi-r4-poe
+ UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-poe-sdmmc
+ UBOOT_IMAGE:=u-boot.fip
+ BL2_BOOTDEV:=sdmmc
+ BL2_SOC:=mt7988
+ BL2_DDRTYPE:=comb
+ DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-comb
+endef
+
+define U-Boot/mt7988_bananapi_bpi-r4-poe-snand
+ NAME:=BananaPi BPi-R4 2.5GE
+ BUILD_SUBTARGET:=filogic
+ BUILD_DEVICES:=bananapi_bpi-r4-poe
+ UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-poe-snand
+ UBOOT_IMAGE:=u-boot.fip
+ BL2_BOOTDEV:=spim-nand-ubi
+ BL2_SOC:=mt7988
+ BL2_DDRTYPE:=comb
+ DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ubi-comb
+endef
+
define U-Boot/mt7988_rfb-spim-nand
NAME:=MT7988 Reference Board
BUILD_SUBTARGET:=filogic
mt7981_cmcc_rax3000m-nand \
mt7981_h3c_magic-nx30-pro \
mt7981_jcg_q30-pro \
+ mt7981_openwrt_one-snand \
+ mt7981_openwrt_one-nor \
mt7981_rfb-spim-nand \
mt7981_rfb-emmc \
mt7981_rfb-nor \
mt7988_bananapi_bpi-r4-emmc \
mt7988_bananapi_bpi-r4-sdmmc \
mt7988_bananapi_bpi-r4-snand \
+ mt7988_bananapi_bpi-r4-poe-emmc \
+ mt7988_bananapi_bpi-r4-poe-sdmmc \
+ mt7988_bananapi_bpi-r4-poe-snand \
mt7988_rfb-spim-nand \
mt7988_rfb-snand \
mt7988_rfb-nor \
CONFIG_MTD=y
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
-@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
+@@ -11,7 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x46000000
CONFIG_DEBUG_UART=y
+-# CONFIG_AUTOBOOT is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_NAND_BOOT=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
- # CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
CONFIG_LOGLEVEL=7
-@@ -22,15 +40,118 @@ CONFIG_SYS_PBSIZE=1049
+ CONFIG_LOG=y
+@@ -22,15 +39,120 @@ CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_EMBED=y
++CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_OVERWRITE=y
-+CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_ENV_OFFSET=0x400000
-+CONFIG_ENV_OFFSET_REDUND=0x440000
-+CONFIG_ENV_SIZE=0x40000
-+CONFIG_ENV_SIZE_REDUND=0x40000
++CONFIG_ENV_IS_IN_UBI=y
++CONFIG_ENV_UBI_PART="ubi"
++CONFIG_ENV_SIZE=0x1f000
++CONFIG_ENV_SIZE_REDUND=0x1f000
++CONFIG_ENV_UBI_VOLUME="ubootenv"
++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
CONFIG_DOS_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
-@@ -46,6 +167,9 @@ CONFIG_PROT_TCP=y
+@@ -46,6 +168,9 @@ CONFIG_PROT_TCP=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
+--- a/arch/arm/dts/mt7988-rfb.dts
++++ b/arch/arm/dts/mt7988-rfb.dts
+@@ -144,6 +144,23 @@
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "bl2";
++ reg = <0x0 0x200000>;
++ };
++
++ partition@200000 {
++ label = "ubi";
++ reg = <0x200000 0x7e00000>;
++ compatible = "linux,ubi";
++ };
++ };
+ };
+ };
+
--- /dev/null
+From cca5775031e4890f195246772e00f7f4ae7438f6 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Mon, 19 Feb 2024 05:52:24 +0100
+Subject: [PATCH 1/2] mt7981.dtsi: add USB nodes
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/dts/mt7981.dtsi | 47 ++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi
+index bda80ac9..6f4e5b9f 100644
+--- a/arch/arm/dts/mt7981.dtsi
++++ b/arch/arm/dts/mt7981.dtsi
+@@ -6,6 +6,7 @@
+
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/clock/mt7981-clk.h>
+ #include <dt-bindings/reset/mt7629-reset.h>
+ #include <dt-bindings/pinctrl/mt65xx.h>
+@@ -342,4 +343,50 @@
+ status = "disabled";
+ };
+
++ xhci: xhci@11200000 {
++ compatible = "mediatek,mt7981-xhci",
++ "mediatek,mtk-xhci";
++ reg = <0x11200000 0x2e00>,
++ <0x11203e00 0x0100>;
++ reg-names = "mac", "ippc";
++ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&u2port0 PHY_TYPE_USB2>,
++ <&u3port0 PHY_TYPE_USB3>;
++ clocks = <&infracfg_ao CK_INFRA_IUSB_SYS_CK>,
++ <&infracfg_ao CK_INFRA_IUSB_CK>,
++ <&infracfg_ao CK_INFRA_IUSB_133_CK>,
++ <&infracfg_ao CK_INFRA_IUSB_66M_CK>,
++ <&topckgen CK_TOP_U2U3_XHCI_SEL>;
++ clock-names = "sys_ck",
++ "ref_ck",
++ "mcu_ck",
++ "dma_ck",
++ "xhci_ck";
++ mediatek,u3p-dis-msk = <0x1>;
++ status = "okay";
++ };
++
++ usbtphy: usb-phy@11e10000 {
++ compatible = "mediatek,mt7981",
++ "mediatek,generic-tphy-v2";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ status = "okay";
++
++ u2port0: usb-phy@11e10000 {
++ reg = <0x11e10000 0x700>;
++ clocks = <&topckgen CK_TOP_USB_FRMCNT_SEL>;
++ clock-names = "ref";
++ #phy-cells = <1>;
++ status = "okay";
++ };
++
++ u3port0: usb-phy@11e10700 {
++ reg = <0x11e10700 0x900>;
++ clocks = <&topckgen CK_TOP_USB3_PHY_SEL>;
++ clock-names = "ref";
++ #phy-cells = <1>;
++ status = "okay";
++ };
++ };
+ };
+--
+2.34.1
+
+reset_factory=eraseenv && reset
+_init_env=setenv _init_env ; saveenv ; saveenv
+_firstboot=setenv _firstboot ; run _switch_to_menu _update_bootdev _init_env boot_first
-+_update_bootdev=setenv _update_bootdev ; setenv bootargs "$console root=/dev/mmcblk0p65"
++_update_bootdev=setenv _update_bootdev ; setenv bootargs "$console root=/dev/fit0 rootwait"
+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title \e[33m$ver\e[0m"
--- a/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts
+serverip=192.168.1.254
+loadaddr=0x46000000
+console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/mmcblk0p65
++bootargs=root=/dev/fit0 rootwait
+bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
+bootconf=config-1
+bootdelay=0
+ non-removable;
+ status = "okay";
+};
+--- /dev/null
++++ b/configs/mt7988a_bananapi_bpi-r4-poe-emmc_defconfig
+@@ -0,0 +1,180 @@
++CONFIG_ARM=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_SYS_PROMPT="MT7988> "
++CONFIG_TARGET_MT7988=y
++CONFIG_DEBUG_UART_BASE=0x11000000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_SYS_LOAD_ADDR=0x50000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4-poe_emmc_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_MTK_AHCI=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
++CONFIG_OF_EMBED=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_ENV_OFFSET=0x400000
++CONFIG_ENV_OFFSET_REDUND=0x440000
++CONFIG_ENV_SIZE=0x40000
++CONFIG_ENV_SIZE_REDUND=0x40000
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_PHY_FIXED=y
++CONFIG_DM_ETH=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
++CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
++++ b/configs/mt7988a_bananapi_bpi-r4-poe-sdmmc_defconfig
+@@ -0,0 +1,180 @@
++CONFIG_ARM=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_SYS_PROMPT="MT7988> "
++CONFIG_TARGET_MT7988=y
++CONFIG_DEBUG_UART_BASE=0x11000000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_SYS_LOAD_ADDR=0x50000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-sd"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4-poe_sdmmc_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-sd.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_MTK_AHCI=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
++CONFIG_OF_EMBED=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_ENV_OFFSET=0x400000
++CONFIG_ENV_OFFSET_REDUND=0x440000
++CONFIG_ENV_SIZE=0x40000
++CONFIG_ENV_SIZE_REDUND=0x40000
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_PHY_FIXED=y
++CONFIG_DM_ETH=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
++CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
++++ b/configs/mt7988a_bananapi_bpi-r4-poe-snand_defconfig
+@@ -0,0 +1,182 @@
++CONFIG_ARM=y
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_ARCH_MEDIATEK=y
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_SYS_PROMPT="MT7988> "
++CONFIG_TARGET_MT7988=y
++CONFIG_DEBUG_UART_BASE=0x11000000
++CONFIG_DEBUG_UART_CLOCK=40000000
++CONFIG_SYS_LOAD_ADDR=0x50000000
++CONFIG_DEBUG_UART=y
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc"
++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4-poe_snand_env"
++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_OF_SYSTEM_SETUP=y
++CONFIG_SMBIOS_PRODUCT_NAME=""
++CONFIG_AUTOBOOT_KEYED=y
++CONFIG_BOOTDELAY=30
++CONFIG_AUTOBOOT_MENU_SHOW=y
++CONFIG_CFB_CONSOLE_ANSI=y
++CONFIG_BOARD_LATE_INIT=y
++CONFIG_BUTTON=y
++CONFIG_BUTTON_GPIO=y
++CONFIG_GPIO_HOG=y
++CONFIG_CMD_ENV_FLAGS=y
++CONFIG_FIT=y
++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
++CONFIG_LED=y
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++CONFIG_LOGLEVEL=7
++CONFIG_LOG=y
++CONFIG_CMD_BOOTMENU=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_CPU=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_DM=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ENV_READMEM=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_EXT4=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++CONFIG_CMD_GPIO=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_HASH=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_LED=y
++CONFIG_CMD_LICENSE=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_MBR is not set
++CONFIG_CMD_MMC=y
++CONFIG_CMD_MTD=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_SF_TEST=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_SMC=y
++CONFIG_CMD_TFTPBOOT=y
++CONFIG_CMD_TFTPSRV=y
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_PART=y
++CONFIG_CMD_RARP=y
++CONFIG_CMD_SETEXPR=y
++CONFIG_CMD_SLEEP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_STRINGS=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_UUID=y
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DM_MMC=y
++CONFIG_DM_MTD=y
++CONFIG_DM_REGULATOR=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_DM_REGULATOR_GPIO=y
++CONFIG_DM_USB=y
++CONFIG_DM_PWM=y
++CONFIG_PWM_MTK=y
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_VERSION_VARIABLE=y
++CONFIG_PARTITION_UUIDS=y
++CONFIG_NETCONSOLE=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_SCSI=y
++CONFIG_AHCI=y
++CONFIG_AHCI_PCI=y
++CONFIG_SCSI_AHCI=y
++CONFIG_SCSI=y
++CONFIG_CMD_SCSI=y
++CONFIG_PHY=y
++CONFIG_PHY_MTK_TPHY=y
++CONFIG_MTK_AHCI=y
++CONFIG_PCI=y
++CONFIG_MTD=y
++CONFIG_MTD_UBI_FASTMAP=y
++CONFIG_DM_PCI=y
++CONFIG_PCIE_MEDIATEK=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_PRE_CONSOLE_BUFFER=y
++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
++CONFIG_RAM=y
++CONFIG_DM_SERIAL=y
++CONFIG_MTK_SERIAL=y
++CONFIG_MMC=y
++CONFIG_MMC_DEFAULT_DEV=1
++CONFIG_MMC_SUPPORTS_TUNING=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_MTK_SPI_NAND=y
++CONFIG_MTK_SPI_NAND_MTD=y
++CONFIG_SYSRESET_WATCHDOG=y
++CONFIG_WDT_MTK=y
++CONFIG_LZO=y
++CONFIG_ZSTD=y
++CONFIG_HEXDUMP=y
++CONFIG_RANDOM_UUID=y
++CONFIG_REGEX=y
++CONFIG_USB=y
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_MTK=y
++CONFIG_USB_STORAGE=y
++CONFIG_OF_EMBED=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_IS_IN_UBI=y
++CONFIG_ENV_UBI_PART="ubi"
++CONFIG_ENV_SIZE=0x1f000
++CONFIG_ENV_SIZE_REDUND=0x1f000
++CONFIG_ENV_UBI_VOLUME="ubootenv"
++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_MMC_MTK=y
++CONFIG_PHY_FIXED=y
++CONFIG_DM_ETH=y
++CONFIG_MEDIATEK_ETH=y
++CONFIG_PINCTRL=y
++CONFIG_PINCONF=y
++CONFIG_PINCTRL_MT7988=y
++CONFIG_POWER_DOMAIN=y
++CONFIG_MTK_POWER_DOMAIN=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MTK_SPIM=y
++#CONFIG_MTK_SNOR=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_NAND_TRIMFFS=y
++CONFIG_LMB_MAX_REGIONS=64
++CONFIG_USE_IPADDR=y
++CONFIG_IPADDR="192.168.1.1"
++CONFIG_USE_SERVERIP=y
++CONFIG_SERVERIP="192.168.1.254"
+--- /dev/null
++++ b/bananapi_bpi-r4-poe_emmc_env
+@@ -0,0 +1,57 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x50000000
++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 rootwait
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
++bootconf=config-mt7988a-bananapi-bpi-r4-poe
++bootconf_base=config-mt7988a-bananapi-bpi-r4-poe
++bootconf_emmc=mt7988a-bananapi-bpi-r4-emmc
++bootconf_extra=
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-initramfs-recovery.itb
++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-emmc-preloader.bin
++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-emmc-bl31-uboot.fip
++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-squashfs-sysupgrade.itb
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title= \e[0;34m( ( ( \e[1;39mOpenWrt\e[0;34m ) ) ) \e[0;36m[eMMC]\e[0m
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=\e[31mLoad BL31+U-Boot FIP via TFTP then write to eMMC.\e[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_7=\e[31mLoad BL2 preloader via TFTP then write to eMMC.\e[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_8=Reboot.=reset
++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; led $bootled_rec off
++boot_emmc=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_emmc ; fi
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
++part_default=production
++part_recovery=recovery
++reset_factory=eraseenv && reset
++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0
++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800
++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title \e[33m$ver\e[0m"
+--- /dev/null
++++ b/bananapi_bpi-r4-poe_sdmmc_env
+@@ -0,0 +1,66 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x50000000
++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 rootwait
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi
++bootconf=config-mt7988a-bananapi-bpi-r4-poe
++bootconf_sd=mt7988a-bananapi-bpi-r4-sd
++bootconf_emmc=mt7988a-bananapi-bpi-r4-emmc
++bootconf_extra=
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-initramfs-recovery.itb
++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-squashfs-sysupgrade.itb
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title= \e[0;34m( ( ( \e[1;39mOpenWrt\e[0;34m ) ) ) \e[0;36m[SD card]\e[0m
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from SD card.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from SD card.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=\e[31mInstall bootloader, recovery and production to NAND.\e[0m=if nand info ; then run ubi_init ; else echo "NAND not detected" ; fi ; run bootmenu_confirm_return
++bootmenu_7=Reboot.=reset
++bootmenu_8=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run sdmmc_read_production && bootm $loadaddr#$bootconf#$bootconf_sd#$bootconf_extra ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run sdmmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_emmc ; led $bootled_rec off
++boot_sdmmc=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run sdmmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_sd#$bootconf_extra ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run sdmmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_sd ; fi
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf#$bootconf_sd
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200
++part_default=production
++part_recovery=recovery
++reset_factory=eraseenv && reset
++sdmmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol
++sdmmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol
++sdmmc_read_snand_bl2=part start mmc 0 install part_addr && mmc read $loadaddr $part_addr 0x400
++sdmmc_read_snand_fip=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x800 && mmc read $loadaddr $offset 0x1000
++sdmmc_read_emmc_install=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x3800 && mmc read $loadaddr $offset 0x4000
++sdmmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
++sdmmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000
++ubi_create_env=ubi create ubootenv 0x100000 dynamic 1 ; ubi create ubootenv2 0x100000 dynamic 2
++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi
++ubi_init=run ubi_format && run ubi_init_bl && run ubi_create_env && run ubi_init_openwrt && run ubi_init_emmc_install
++ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production
++ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run ubi_write_fip
++ubi_init_emmc_install=run sdmmc_read_emmc_install && run ubi_write_emmc_install
++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_emmc_install=ubi check emmc_install && ubi remove emmc_install ; ubi create emmc_install 0x800000 dynamic ; ubi write $loadaddr emmc_install 0x800000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title \e[33m$ver\e[0m"
+--- /dev/null
++++ b/bananapi_bpi-r4-poe_snand_env
+@@ -0,0 +1,67 @@
++ipaddr=192.168.1.1
++serverip=192.168.1.254
++loadaddr=0x50000000
++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 rootwait ubi.block=0,fit
++bootconf=config-mt7988a-bananapi-bpi-r4-poe
++bootconf_extra=mt7988a-bananapi-bpi-r4-emmc
++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-initramfs-recovery.itb
++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-snand-preloader.bin
++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-snand-bl31-uboot.fip
++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-poe-squashfs-sysupgrade.itb
++bootled_pwr=green:status
++bootled_rec=blue:status
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title= \e[0;34m( ( ( \e[1;39mOpenWrt\e[0;34m ) ) ) \e[0;36m[SPI-NAND]\e[0m
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
++bootmenu_6=\e[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.\e[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_7=\e[31mLoad BL2 preloader via TFTP then write to NAND.\e[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_8=\e[31mInstall bootloader, recovery and production to eMMC.\e[0m=if mmc partconf 0 ; then run emmc_init ; else echo "eMMC not detected" ; fi ; run bootmenu_confirm_return
++bootmenu_9=Reboot.=reset
++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf#$bootconf_extra ; led $bootled_pwr off
++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off
++boot_ubi=run boot_production ; run boot_recovery
++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_extra ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++part_default=production
++part_recovery=recovery
++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800
++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000
++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 1 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 2
++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
++ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install
++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size
++emmc_init=mmc dev 0 && mmc bootbus 0 0 0 0 && run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv
++emmc_init_bl=run ubi_read_emmc_install && setenv fileaddr $loadaddr && run emmc_write_bl2 && setexpr fileaddr $loadaddr + 0x100000 && run emmc_write_fip && setexpr fileaddr $loadaddr + 0x500000 && run emmc_write_hdr
++emmc_init_openwrt=run ubi_read_recovery && iminfo $loadaddr && run emmc_write_recovery ; run ubi_read_production && iminfo $loadaddr && run emmc_write_production
++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0
++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800
++emmc_write_hdr=mmc erase 0x0 0x40 && mmc write $fileaddr 0x0 0x40
++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol
++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol
++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title \e[33m$ver\e[0m"
--- /dev/null
+--- /dev/null
++++ b/arch/arm/dts/openwrt-one.dts
+@@ -0,0 +1,203 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2024 John Crispin <john@phrozen.org>
++ */
++
++/dts-v1/;
++#include "mt7981.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++/ {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ model = "OpenWrt One";
++ compatible = "openwrt,one", "mediatek,mt7981";
++ chosen {
++ stdout-path = &uart0;
++ tick-timer = &timer0;
++ };
++
++ memory@40000000 {
++ device_type = "memory";
++ reg = <0x40000000 0x10000000>;
++ };
++
++ keys {
++ compatible = "gpio-keys";
++
++ user {
++ label = "front";
++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
++ linux,code = <BTN_0>;
++ };
++
++ reset {
++ label = "back";
++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
++ linux,code = <BTN_1>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ red {
++ label = "red";
++ gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
++ };
++
++ white {
++ label = "white";
++ gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
++ };
++
++ green {
++ label = "green";
++ gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
++ };
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
++
++ð {
++ status = "okay";
++ mediatek,gmac-id = <1>;
++ phy-mode = "gmii";
++ phy-handle = <&phy0>;
++
++ phy0: eth-phy@0 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0>;
++ };
++};
++
++&pinctrl {
++ spi_flash_pins: spi0-pins-func-1 {
++ mux {
++ function = "flash";
++ groups = "spi0", "spi0_wp_hold";
++ };
++
++ conf-pu {
++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
++ drive-strength = <MTK_DRIVE_8mA>;
++ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
++ };
++
++ conf-pd {
++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
++ drive-strength = <MTK_DRIVE_8mA>;
++ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
++ };
++ };
++
++ spi2_flash_pins: spi2-spi2-pins {
++ mux {
++ function = "spi";
++ groups = "spi2", "spi2_wp_hold";
++ };
++
++ conf-pu {
++ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
++ drive-strength = <MTK_DRIVE_8mA>;
++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
++ };
++
++ conf-pd {
++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
++ drive-strength = <MTK_DRIVE_8mA>;
++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
++ };
++ };
++};
++
++&spi0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi_flash_pins>;
++ status = "okay";
++ must_tx;
++ enhance_timing;
++ dma_ext;
++ ipm_design;
++ support_quad;
++ tick_dly = <2>;
++ sample_sel = <0>;
++
++ spi_nand@0 {
++ compatible = "spi-nand";
++ reg = <0>;
++ spi-max-frequency = <52000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "bl2";
++ reg = <0x0 0x100000>;
++ };
++
++ partition@200000 {
++ label = "ubi";
++ reg = <0x100000 0x7f00000>;
++ };
++ };
++ };
++};
++
++&spi2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi2_flash_pins>;
++ status = "okay";
++ must_tx;
++ enhance_timing;
++ dma_ext;
++ ipm_design;
++ tick_dly = <2>;
++ sample_sel = <0>;
++
++ spi_nor@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <5000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@00000 {
++ label = "bl2-nor";
++ reg = <0x00000 0x0040000>;
++ };
++
++ partition@40000 {
++ label = "factory";
++ reg = <0x40000 0x00C0000>;
++ };
++
++ partition@100000 {
++ label = "fip-nor";
++ reg = <0x100000 0x0080000>;
++ };
++
++ partition@180000 {
++ label = "recovery";
++ reg = <0x180000 0xc80000>;
++ };
++ };
++ };
++};
++
++&watchdog {
++ status = "disabled";
++};
+--- /dev/null
++++ b/configs/mt7981_openwrt-one-nor_defconfig
+@@ -0,0 +1,1811 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# U-Boot 2024.01 Configuration
++#
++
++#
++# Compiler: aarch64-openwrt-linux-musl-gcc (OpenWrt GCC 13.2.0 r26144+12-219018185e) 13.2.0
++#
++CONFIG_CREATE_ARCH_SYMLINK=y
++CONFIG_SYS_CACHE_SHIFT_6=y
++CONFIG_SYS_CACHELINE_SIZE=64
++CONFIG_LINKER_LIST_ALIGN=8
++# CONFIG_ARC is not set
++CONFIG_ARM=y
++# CONFIG_M68K is not set
++# CONFIG_MICROBLAZE is not set
++# CONFIG_MIPS is not set
++# CONFIG_NIOS2 is not set
++# CONFIG_PPC is not set
++# CONFIG_RISCV is not set
++# CONFIG_SANDBOX is not set
++# CONFIG_SH is not set
++# CONFIG_X86 is not set
++# CONFIG_XTENSA is not set
++CONFIG_SYS_ARCH="arm"
++CONFIG_SYS_CPU="armv8"
++CONFIG_SYS_SOC="mediatek"
++CONFIG_SYS_VENDOR="mediatek"
++CONFIG_SYS_BOARD="mt7981"
++CONFIG_SYS_CONFIG_NAME="mt7981"
++
++#
++# Skipping low level initialization functions
++#
++# CONFIG_SKIP_LOWLEVEL_INIT is not set
++# CONFIG_SKIP_LOWLEVEL_INIT_ONLY is not set
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_SYS_NONCACHED_MEMORY=0x100000
++# CONFIG_SYS_ICACHE_OFF is not set
++# CONFIG_SYS_DCACHE_OFF is not set
++
++#
++# ARM architecture
++#
++CONFIG_ARM64=y
++CONFIG_ARM64_CRC32=y
++CONFIG_COUNTER_FREQUENCY=0
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_INIT_SP_RELATIVE=y
++CONFIG_SYS_INIT_SP_BSS_OFFSET=524288
++# CONFIG_GIC_V3_ITS is not set
++CONFIG_STATIC_RELA=y
++CONFIG_DMA_ADDR_T_64BIT=y
++CONFIG_GPIO_EXTRA_HEADER=y
++CONFIG_ARM_ASM_UNIFIED=y
++# CONFIG_SYS_ARM_CACHE_CP15 is not set
++# CONFIG_SYS_ARM_MMU is not set
++# CONFIG_SYS_ARM_MPU is not set
++CONFIG_SYS_ARM_ARCH=8
++CONFIG_SYS_ARM_CACHE_WRITEBACK=y
++# CONFIG_SYS_ARM_CACHE_WRITETHROUGH is not set
++# CONFIG_SYS_ARM_CACHE_WRITEALLOC is not set
++# CONFIG_ARCH_CPU_INIT is not set
++CONFIG_SYS_ARCH_TIMER=y
++CONFIG_ARM_SMCCC=y
++# CONFIG_SYS_L2_PL310 is not set
++# CONFIG_SPL_SYS_L2_PL310 is not set
++# CONFIG_SYS_L2CACHE_OFF is not set
++# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
++# CONFIG_USE_ARCH_MEMCPY is not set
++# CONFIG_USE_ARCH_MEMSET is not set
++CONFIG_ARM64_SUPPORT_AARCH32=y
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_HISTB is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_TARGET_STV0991 is not set
++# CONFIG_ARCH_BCM283X is not set
++# CONFIG_ARCH_BCMSTB is not set
++# CONFIG_ARCH_BCMBCA is not set
++# CONFIG_TARGET_VEXPRESS_CA9X4 is not set
++# CONFIG_TARGET_BCMNS is not set
++# CONFIG_TARGET_BCMNS2 is not set
++# CONFIG_TARGET_BCMNS3 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_S5PC1XX is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_IPQ40XX is not set
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_K3 is not set
++# CONFIG_ARCH_OMAP2PLUS is not set
++# CONFIG_ARCH_MESON is not set
++CONFIG_ARCH_MEDIATEK=y
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_IMX8 is not set
++# CONFIG_ARCH_IMX8M is not set
++# CONFIG_ARCH_IMX8ULP is not set
++# CONFIG_ARCH_IMX9 is not set
++# CONFIG_ARCH_IMXRT is not set
++# CONFIG_ARCH_MX23 is not set
++# CONFIG_ARCH_MX28 is not set
++# CONFIG_ARCH_MX31 is not set
++# CONFIG_ARCH_MX7ULP is not set
++# CONFIG_ARCH_MX7 is not set
++# CONFIG_ARCH_MX6 is not set
++# CONFIG_ARCH_MX5 is not set
++# CONFIG_ARCH_NEXELL is not set
++# CONFIG_ARCH_NPCM is not set
++# CONFIG_ARCH_APPLE is not set
++# CONFIG_ARCH_OWL is not set
++# CONFIG_ARCH_QEMU is not set
++# CONFIG_ARCH_RMOBILE is not set
++# CONFIG_ARCH_SNAPDRAGON is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VERSAL is not set
++# CONFIG_ARCH_VERSAL_NET is not set
++# CONFIG_ARCH_VF610 is not set
++# CONFIG_ARCH_ZYNQ is not set
++# CONFIG_ARCH_ZYNQMP_R5 is not set
++# CONFIG_ARCH_ZYNQMP is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_VEXPRESS64 is not set
++# CONFIG_TARGET_CORSTONE1000 is not set
++# CONFIG_TARGET_TOTAL_COMPUTE is not set
++# CONFIG_TARGET_LS2080A_EMU is not set
++# CONFIG_TARGET_LS1088AQDS is not set
++# CONFIG_TARGET_LS2080AQDS is not set
++# CONFIG_TARGET_LS2080ARDB is not set
++# CONFIG_TARGET_LS2081ARDB is not set
++# CONFIG_TARGET_LX2160ARDB is not set
++# CONFIG_TARGET_LX2160AQDS is not set
++# CONFIG_TARGET_LX2162AQDS is not set
++# CONFIG_TARGET_HIKEY is not set
++# CONFIG_TARGET_HIKEY960 is not set
++# CONFIG_TARGET_POPLAR is not set
++# CONFIG_TARGET_LS1012AQDS is not set
++# CONFIG_TARGET_LS1012ARDB is not set
++# CONFIG_TARGET_LS1012A2G5RDB is not set
++# CONFIG_TARGET_LS1012AFRWY is not set
++# CONFIG_TARGET_LS1012AFRDM is not set
++# CONFIG_TARGET_LS1028AQDS is not set
++# CONFIG_TARGET_LS1028ARDB is not set
++# CONFIG_TARGET_LS1088ARDB is not set
++# CONFIG_TARGET_LS1021AQDS is not set
++# CONFIG_TARGET_LS1021ATWR is not set
++# CONFIG_TARGET_PG_WCOM_SELI8 is not set
++# CONFIG_TARGET_PG_WCOM_EXPU1 is not set
++# CONFIG_TARGET_LS1021ATSN is not set
++# CONFIG_TARGET_LS1021AIOT is not set
++# CONFIG_TARGET_LS1043AQDS is not set
++# CONFIG_TARGET_LS1043ARDB is not set
++# CONFIG_TARGET_LS1046AQDS is not set
++# CONFIG_TARGET_LS1046ARDB is not set
++# CONFIG_TARGET_LS1046AFRWY is not set
++# CONFIG_TARGET_SL28 is not set
++# CONFIG_TARGET_TEN64 is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_SYNQUACER is not set
++# CONFIG_ARCH_STM32 is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_STM32MP is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_OCTEONTX is not set
++# CONFIG_ARCH_OCTEONTX2 is not set
++# CONFIG_TARGET_THUNDERX_88XX is not set
++# CONFIG_ARCH_ASPEED is not set
++# CONFIG_TARGET_DURIAN is not set
++# CONFIG_TARGET_POMELO is not set
++# CONFIG_TARGET_PRESIDIO_ASIC is not set
++# CONFIG_TARGET_XENGUEST_ARM64 is not set
++# CONFIG_ARCH_GXP is not set
++# CONFIG_STATIC_MACH_TYPE is not set
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_LEN=0x400000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_ENV_SOURCE_FILE=""
++CONFIG_SF_DEFAULT_SPEED=1000000
++CONFIG_SF_DEFAULT_MODE=0x0
++CONFIG_ENV_SIZE=0x8000
++CONFIG_DM_GPIO=y
++CONFIG_DEFAULT_DEVICE_TREE="openwrt-one"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x8000
++CONFIG_DM_RESET=y
++CONFIG_SYS_MONITOR_LEN=0
++# CONFIG_MT8512 is not set
++# CONFIG_TARGET_MT7622 is not set
++# CONFIG_TARGET_MT7623 is not set
++# CONFIG_TARGET_MT7629 is not set
++CONFIG_TARGET_MT7981=y
++# CONFIG_TARGET_MT7986 is not set
++# CONFIG_TARGET_MT7988 is not set
++# CONFIG_TARGET_MT8183 is not set
++# CONFIG_TARGET_MT8512 is not set
++# CONFIG_TARGET_MT8516 is not set
++# CONFIG_TARGET_MT8518 is not set
++CONFIG_MTK_BROM_HEADER_INFO="media=snand;nandinfo=2k+64"
++CONFIG_RESET_BUTTON_LABEL="back"
++CONFIG_RESET_BUTTON_SETTLE_DELAY=0
++CONFIG_ERR_PTR_OFFSET=0x0
++# CONFIG_SPL is not set
++CONFIG_BOOTSTAGE_STASH_ADDR=0x0
++CONFIG_DEBUG_UART_BASE=0x11002000
++CONFIG_DEBUG_UART_CLOCK=40000000
++# CONFIG_DEBUG_UART_BOARD_INIT is not set
++CONFIG_IDENT_STRING=""
++CONFIG_SYS_CLK_FREQ=0
++# CONFIG_CHIP_DIP_SCAN is not set
++# CONFIG_CMO_BY_VA_ONLY is not set
++# CONFIG_ARMV8_MULTIENTRY is not set
++# CONFIG_ARMV8_SET_SMPEN is not set
++# CONFIG_ARMV8_SWITCH_TO_EL1 is not set
++
++#
++# ARMv8 secure monitor firmware
++#
++# CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT is not set
++CONFIG_PSCI_RESET=y
++# CONFIG_ARMV8_PSCI is not set
++# CONFIG_ARMV8_EA_EL3_FIRST is not set
++# CONFIG_ARMV8_CRYPTO is not set
++# CONFIG_CMD_DEKBLOB is not set
++# CONFIG_IMX_CAAM_DEK_ENCAP is not set
++# CONFIG_IMX_OPTEE_DEK_ENCAP is not set
++# CONFIG_IMX_SECO_DEK_ENCAP is not set
++# CONFIG_IMX_ELE_DEK_ENCAP is not set
++# CONFIG_CMD_HDMIDETECT is not set
++CONFIG_IMX_DCD_ADDR=0x00910000
++CONFIG_SYS_MEM_TOP_HIDE=0x0
++CONFIG_SYS_LOAD_ADDR=0x46000000
++
++#
++# ARM debug
++#
++CONFIG_BUILD_TARGET=""
++# CONFIG_PCI is not set
++CONFIG_FWU_NUM_BANKS=2
++CONFIG_FWU_NUM_IMAGES_PER_BANK=2
++CONFIG_DEBUG_UART=y
++# CONFIG_AHCI is not set
++# CONFIG_OF_BOARD_FIXUP is not set
++
++#
++# Functionality shared between NXP SoCs
++#
++# CONFIG_NXP_ESBC is not set
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_CC_IS_GCC=y
++CONFIG_GCC_VERSION=130200
++CONFIG_CLANG_VERSION=0
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++# CONFIG_CC_OPTIMIZE_FOR_SPEED is not set
++# CONFIG_CC_OPTIMIZE_FOR_DEBUG is not set
++# CONFIG_OPTIMIZE_INLINING is not set
++CONFIG_ARCH_SUPPORTS_LTO=y
++# CONFIG_LTO is not set
++CONFIG_CC_HAS_ASM_INLINE=y
++# CONFIG_XEN is not set
++# CONFIG_ENV_VARS_UBOOT_CONFIG is not set
++# CONFIG_SYS_BOOT_GET_CMDLINE is not set
++# CONFIG_SYS_BOOT_GET_KBD is not set
++CONFIG_SYS_MALLOC_F=y
++# CONFIG_VALGRIND is not set
++CONFIG_EXPERT=y
++CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
++# CONFIG_SYS_MALLOC_DEFAULT_TO_INIT is not set
++# CONFIG_TOOLS_DEBUG is not set
++CONFIG_PHYS_64BIT=y
++CONFIG_FDT_64BIT=y
++# CONFIG_REMAKE_ELF is not set
++# CONFIG_HAS_BOARD_SIZE_LIMIT is not set
++# CONFIG_SYS_CUSTOM_LDSCRIPT is not set
++CONFIG_PLATFORM_ELFENTRY="_start"
++CONFIG_STACK_SIZE=0x1000000
++CONFIG_SYS_SRAM_BASE=0x0
++CONFIG_SYS_SRAM_SIZE=0x0
++# CONFIG_MP is not set
++CONFIG_HAVE_TEXT_BASE=y
++# CONFIG_HAVE_SYS_UBOOT_START is not set
++CONFIG_SYS_UBOOT_START=0x41e00000
++# CONFIG_DYNAMIC_SYS_CLK_FREQ is not set
++# CONFIG_API is not set
++
++#
++# Boot options
++#
++
++#
++# Boot images
++#
++# CONFIG_ANDROID_BOOT_IMAGE is not set
++# CONFIG_TIMESTAMP is not set
++CONFIG_FIT=y
++CONFIG_FIT_EXTERNAL_OFFSET=0x0
++CONFIG_FIT_FULL_CHECK=y
++# CONFIG_FIT_SIGNATURE is not set
++# CONFIG_FIT_CIPHER is not set
++# CONFIG_FIT_VERBOSE is not set
++# CONFIG_FIT_BEST_MATCH is not set
++CONFIG_FIT_PRINT=y
++# CONFIG_SPL_LOAD_FIT_FULL is not set
++CONFIG_PXE_UTILS=y
++CONFIG_BOOTSTD=y
++# CONFIG_BOOTSTD_FULL is not set
++# CONFIG_BOOTSTD_DEFAULTS is not set
++CONFIG_BOOTSTD_BOOTCOMMAND=y
++CONFIG_BOOTMETH_GLOBAL=y
++# CONFIG_BOOTMETH_CROS is not set
++CONFIG_BOOTMETH_EXTLINUX=y
++CONFIG_BOOTMETH_EXTLINUX_PXE=y
++CONFIG_BOOTMETH_EFILOADER=y
++CONFIG_BOOTMETH_VBE=y
++CONFIG_BOOTMETH_VBE_REQUEST=y
++CONFIG_BOOTMETH_VBE_SIMPLE=y
++CONFIG_BOOTMETH_VBE_SIMPLE_OS=y
++# CONFIG_BOOTMETH_SCRIPT is not set
++CONFIG_LEGACY_IMAGE_FORMAT=y
++# CONFIG_SUPPORT_RAW_INITRD is not set
++# CONFIG_CHROMEOS is not set
++# CONFIG_CHROMEOS_VBOOT is not set
++# CONFIG_RAMBOOT_PBL is not set
++CONFIG_SYS_BOOT_RAMDISK_HIGH=y
++# CONFIG_DISTRO_DEFAULTS is not set
++
++#
++# Boot timing
++#
++# CONFIG_BOOTSTAGE is not set
++CONFIG_BOOTSTAGE_STASH_SIZE=0x1000
++# CONFIG_SHOW_BOOT_PROGRESS is not set
++
++#
++# Boot media
++#
++CONFIG_NAND_BOOT=y
++# CONFIG_ONENAND_BOOT is not set
++# CONFIG_QSPI_BOOT is not set
++# CONFIG_SATA_BOOT is not set
++# CONFIG_SD_BOOT is not set
++# CONFIG_SD_BOOT_QSPI is not set
++CONFIG_SPI_BOOT=y
++
++#
++# Autoboot options
++#
++CONFIG_AUTOBOOT=y
++CONFIG_BOOTDELAY=2
++# CONFIG_AUTOBOOT_KEYED is not set
++# CONFIG_AUTOBOOT_USE_MENUKEY is not set
++CONFIG_AUTOBOOT_MENU_SHOW=y
++# CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE is not set
++# CONFIG_BOOT_RETRY is not set
++
++#
++# Image support
++#
++# CONFIG_IMAGE_PRE_LOAD is not set
++
++#
++# Devicetree fixup
++#
++# CONFIG_OF_BOARD_SETUP is not set
++# CONFIG_OF_SYSTEM_SETUP is not set
++# CONFIG_OF_STDOUT_VIA_ALIAS is not set
++# CONFIG_FDT_FIXUP_PARTITIONS is not set
++# CONFIG_FDT_SIMPLEFB is not set
++CONFIG_ARCH_FIXUP_FDT_MEMORY=y
++# CONFIG_USE_BOOTARGS is not set
++# CONFIG_BOOTARGS_SUBST is not set
++# CONFIG_USE_BOOTCOMMAND is not set
++CONFIG_USE_PREBOOT=y
++CONFIG_DEFAULT_FDT_FILE="openwrt-one"
++# CONFIG_SAVE_PREV_BL_FDT_ADDR is not set
++# CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR is not set
++
++#
++# Configuration editor
++#
++# CONFIG_CEDIT is not set
++
++#
++# Console
++#
++CONFIG_MENU=y
++# CONFIG_CONSOLE_RECORD is not set
++# CONFIG_DISABLE_CONSOLE is not set
++CONFIG_LOGLEVEL=7
++# CONFIG_SILENT_CONSOLE is not set
++# CONFIG_SPL_SILENT_CONSOLE is not set
++# CONFIG_TPL_SILENT_CONSOLE is not set
++# CONFIG_PRE_CONSOLE_BUFFER is not set
++CONFIG_CONSOLE_FLUSH_SUPPORT=y
++# CONFIG_CONSOLE_FLUSH_ON_NEWLINE is not set
++# CONFIG_CONSOLE_MUX is not set
++# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set
++# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set
++# CONFIG_SYS_CONSOLE_INFO_QUIET is not set
++# CONFIG_SYS_STDIO_DEREGISTER is not set
++# CONFIG_SPL_SYS_STDIO_DEREGISTER is not set
++# CONFIG_SYS_DEVICE_NULLDEV is not set
++
++#
++# Logging
++#
++CONFIG_LOG=y
++CONFIG_LOG_MAX_LEVEL=6
++CONFIG_LOG_DEFAULT_LEVEL=6
++CONFIG_LOG_CONSOLE=y
++# CONFIG_LOGF_FILE is not set
++# CONFIG_LOGF_LINE is not set
++# CONFIG_LOGF_FUNC is not set
++CONFIG_LOGF_FUNC_PAD=20
++# CONFIG_LOG_SYSLOG is not set
++# CONFIG_LOG_ERROR_RETURN is not set
++
++#
++# Init options
++#
++# CONFIG_BOARD_TYPES is not set
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DISPLAY_BOARDINFO=y
++# CONFIG_DISPLAY_BOARDINFO_LATE is not set
++
++#
++# Start-up hooks
++#
++# CONFIG_CYCLIC is not set
++CONFIG_EVENT=y
++CONFIG_EVENT_DYNAMIC=y
++# CONFIG_EVENT_DEBUG is not set
++# CONFIG_ARCH_MISC_INIT is not set
++# CONFIG_BOARD_EARLY_INIT_F is not set
++# CONFIG_BOARD_EARLY_INIT_R is not set
++# CONFIG_BOARD_POSTCLK_INIT is not set
++CONFIG_BOARD_LATE_INIT=y
++# CONFIG_CLOCKS is not set
++# CONFIG_HWCONFIG is not set
++CONFIG_LAST_STAGE_INIT=y
++# CONFIG_MISC_INIT_R is not set
++# CONFIG_SYS_MALLOC_BOOTPARAMS is not set
++# CONFIG_ID_EEPROM is not set
++# CONFIG_RESET_PHY_R is not set
++
++#
++# Security support
++#
++CONFIG_HASH=y
++# CONFIG_STACKPROTECTOR is not set
++# CONFIG_BOARD_RNG_SEED is not set
++
++#
++# Update support
++#
++# CONFIG_UPDATE_TFTP is not set
++# CONFIG_ANDROID_AB is not set
++
++#
++# Blob list
++#
++# CONFIG_BLOBLIST is not set
++CONFIG_SUPPORT_SPL=y
++# CONFIG_VPL is not set
++
++#
++# Command line interface
++#
++CONFIG_CMDLINE=y
++CONFIG_HUSH_PARSER=y
++CONFIG_CMDLINE_EDITING=y
++# CONFIG_CMDLINE_PS_SUPPORT is not set
++CONFIG_AUTO_COMPLETE=y
++CONFIG_SYS_LONGHELP=y
++CONFIG_SYS_PROMPT="OpenWrt One> "
++CONFIG_SYS_PROMPT_HUSH_PS2="> "
++CONFIG_SYS_MAXARGS=16
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_SYS_XTRACE=y
++CONFIG_BUILD_BIN2C=y
++
++#
++# Commands
++#
++
++#
++# Info commands
++#
++CONFIG_CMD_BDI=y
++# CONFIG_CMD_BDINFO_EXTRA is not set
++# CONFIG_CMD_CONFIG is not set
++CONFIG_CMD_CONSOLE=y
++CONFIG_CMD_CPU=y
++# CONFIG_CMD_HISTORY is not set
++CONFIG_CMD_LICENSE=y
++# CONFIG_CMD_PMC is not set
++
++#
++# Boot commands
++#
++CONFIG_CMD_BOOTD=y
++CONFIG_CMD_BOOTM=y
++# CONFIG_CMD_BOOTDEV is not set
++CONFIG_CMD_BOOTFLOW=y
++# CONFIG_CMD_BOOTMETH is not set
++CONFIG_BOOTM_EFI=y
++# CONFIG_CMD_BOOTZ is not set
++CONFIG_CMD_BOOTI=y
++CONFIG_BOOTM_LINUX=y
++# CONFIG_BOOTM_NETBSD is not set
++# CONFIG_BOOTM_OPENRTOS is not set
++# CONFIG_BOOTM_OSE is not set
++# CONFIG_BOOTM_PLAN9 is not set
++# CONFIG_BOOTM_RTEMS is not set
++# CONFIG_CMD_VBE is not set
++# CONFIG_BOOTM_VXWORKS is not set
++CONFIG_SYS_BOOTM_LEN=0x4000000
++CONFIG_CMD_BOOTEFI=y
++CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
++# CONFIG_CMD_BOOTEFI_HELLO is not set
++# CONFIG_CMD_BOOTEFI_SELFTEST is not set
++CONFIG_CMD_BOOTMENU=y
++# CONFIG_CMD_ADTIMG is not set
++CONFIG_CMD_ELF=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_GO=y
++CONFIG_CMD_RUN=y
++CONFIG_CMD_IMI=y
++# CONFIG_CMD_IMLS is not set
++CONFIG_CMD_XIMG=y
++# CONFIG_CMD_ZBOOT is not set
++
++#
++# Environment commands
++#
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_EXPORTENV=y
++CONFIG_CMD_IMPORTENV=y
++CONFIG_CMD_EDITENV=y
++# CONFIG_CMD_GREPENV is not set
++CONFIG_CMD_SAVEENV=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_ENV_EXISTS=y
++CONFIG_CMD_ENV_READMEM=y
++# CONFIG_CMD_ENV_CALLBACK is not set
++CONFIG_CMD_ENV_FLAGS=y
++# CONFIG_CMD_NVEDIT_EFI is not set
++# CONFIG_CMD_NVEDIT_INDIRECT is not set
++# CONFIG_CMD_NVEDIT_INFO is not set
++# CONFIG_CMD_NVEDIT_LOAD is not set
++# CONFIG_CMD_NVEDIT_SELECT is not set
++
++#
++# Memory commands
++#
++# CONFIG_CMD_BINOP is not set
++# CONFIG_CMD_BLOBLIST is not set
++CONFIG_CMD_CRC32=y
++# CONFIG_CRC32_VERIFY is not set
++# CONFIG_CMD_EEPROM is not set
++# CONFIG_LOOPW is not set
++# CONFIG_CMD_MD5SUM is not set
++# CONFIG_CMD_MEMINFO is not set
++CONFIG_CMD_MEMORY=y
++# CONFIG_CMD_MEM_SEARCH is not set
++# CONFIG_CMD_MX_CYCLIC is not set
++CONFIG_CMD_RANDOM=y
++# CONFIG_CMD_MEMTEST is not set
++# CONFIG_CMD_SHA1SUM is not set
++CONFIG_CMD_STRINGS=y
++
++#
++# Compression commands
++#
++CONFIG_CMD_LZMADEC=y
++# CONFIG_CMD_UNLZ4 is not set
++# CONFIG_CMD_UNZIP is not set
++# CONFIG_CMD_ZIP is not set
++
++#
++# Device access commands
++#
++# CONFIG_CMD_ARMFLASH is not set
++# CONFIG_CMD_BIND is not set
++# CONFIG_CMD_CLK is not set
++# CONFIG_CMD_DEMO is not set
++# CONFIG_CMD_DFU is not set
++CONFIG_CMD_DM=y
++CONFIG_CMD_FLASH=y
++# CONFIG_CMD_FPGAD is not set
++# CONFIG_CMD_FUSE is not set
++CONFIG_CMD_GPIO=y
++# CONFIG_CMD_GPIO_READ is not set
++CONFIG_CMD_PWM=y
++# CONFIG_CMD_GPT is not set
++# CONFIG_RANDOM_UUID is not set
++# CONFIG_CMD_IDE is not set
++# CONFIG_CMD_IO is not set
++# CONFIG_CMD_IOTRACE is not set
++# CONFIG_CMD_I2C is not set
++CONFIG_CMD_LOADB=y
++# CONFIG_CMD_LOADM is not set
++CONFIG_CMD_LOADS=y
++# CONFIG_LOADS_ECHO is not set
++# CONFIG_CMD_SAVES is not set
++# CONFIG_SYS_LOADS_BAUD_CHANGE is not set
++CONFIG_CMD_LOADXY_TIMEOUT=90
++# CONFIG_CMD_LSBLK is not set
++# CONFIG_CMD_MBR is not set
++# CONFIG_CMD_CLONE is not set
++CONFIG_CMD_MTD=y
++CONFIG_CMD_NAND_EXT=y
++# CONFIG_CMD_ONENAND is not set
++# CONFIG_CMD_OSD is not set
++# CONFIG_CMD_PART is not set
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PINMUX=y
++# CONFIG_CMD_POWEROFF is not set
++# CONFIG_CMD_READ is not set
++# CONFIG_CMD_SATA is not set
++# CONFIG_CMD_SDRAM is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_SF_TEST=y
++# CONFIG_CMD_SPI is not set
++# CONFIG_CMD_TSI148 is not set
++# CONFIG_CMD_UNIVERSE is not set
++CONFIG_CMD_USB=y
++# CONFIG_CMD_USB_SDP is not set
++# CONFIG_CMD_RKMTD is not set
++# CONFIG_CMD_WRITE is not set
++
++#
++# Shell scripting commands
++#
++# CONFIG_CMD_CAT is not set
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_SETEXPR=y
++# CONFIG_CMD_SETEXPR_FMT is not set
++# CONFIG_CMD_XXD is not set
++
++#
++# Android support commands
++#
++CONFIG_CMD_NET=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_DHCP=y
++# CONFIG_BOOTP_MAY_FAIL is not set
++CONFIG_BOOTP_BOOTPATH=y
++# CONFIG_BOOTP_VENDOREX is not set
++# CONFIG_BOOTP_BOOTFILESIZE is not set
++CONFIG_BOOTP_DNS=y
++# CONFIG_BOOTP_DNS2 is not set
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_HOSTNAME=y
++# CONFIG_BOOTP_PREFER_SERVERIP is not set
++CONFIG_BOOTP_SUBNETMASK=y
++# CONFIG_BOOTP_NISDOMAIN is not set
++# CONFIG_BOOTP_NTPSERVER is not set
++# CONFIG_BOOTP_TIMEOFFSET is not set
++# CONFIG_CMD_PCAP is not set
++CONFIG_BOOTP_PXE=y
++CONFIG_BOOTP_PXE_CLIENTARCH=0x16
++# CONFIG_BOOTP_PXE_DHCP_OPTION is not set
++CONFIG_BOOTP_VCI_STRING="U-Boot.armv8"
++CONFIG_CMD_TFTPBOOT=y
++# CONFIG_CMD_TFTPPUT is not set
++CONFIG_CMD_TFTPSRV=y
++CONFIG_NET_TFTP_VARS=y
++CONFIG_CMD_RARP=y
++# CONFIG_CMD_NFS is not set
++# CONFIG_SYS_DISABLE_AUTOLOAD is not set
++# CONFIG_CMD_WGET is not set
++# CONFIG_CMD_MII is not set
++# CONFIG_CMD_MDIO is not set
++CONFIG_CMD_PING=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_ETHSW is not set
++CONFIG_CMD_PXE=y
++# CONFIG_CMD_WOL is not set
++
++#
++# Misc commands
++#
++# CONFIG_CMD_2048 is not set
++# CONFIG_CMD_BSP is not set
++CONFIG_CMD_BLOCK_CACHE=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++# CONFIG_CMD_CONITRACE is not set
++# CONFIG_CMD_CLS is not set
++# CONFIG_CMD_EFIDEBUG is not set
++CONFIG_CMD_EFICONFIG=y
++# CONFIG_CMD_EXCEPTION is not set
++CONFIG_CMD_LED=y
++# CONFIG_CMD_INI is not set
++# CONFIG_CMD_DATE is not set
++# CONFIG_CMD_TIME is not set
++# CONFIG_CMD_GETTIME is not set
++# CONFIG_CMD_PAUSE is not set
++CONFIG_CMD_SLEEP=y
++# CONFIG_CMD_TIMER is not set
++# CONFIG_CMD_SYSBOOT is not set
++# CONFIG_CMD_QFW is not set
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_PSTORE_MEM_SIZE=0x10000
++CONFIG_CMD_PSTORE_RECORD_SIZE=0x1000
++CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x1000
++CONFIG_CMD_PSTORE_FTRACE_SIZE=0x1000
++CONFIG_CMD_PSTORE_PMSG_SIZE=0x1000
++CONFIG_CMD_PSTORE_ECC_SIZE=0
++# CONFIG_CMD_TERMINAL is not set
++CONFIG_CMD_UUID=y
++
++#
++# TI specific command line interface
++#
++
++#
++# Power commands
++#
++
++#
++# Security commands
++#
++# CONFIG_CMD_AES is not set
++# CONFIG_CMD_BLOB is not set
++CONFIG_CMD_HASH=y
++# CONFIG_CMD_HVC is not set
++CONFIG_CMD_SMC=y
++# CONFIG_HASH_VERIFY is not set
++
++#
++# Firmware commands
++#
++
++#
++# Filesystem commands
++#
++# CONFIG_CMD_BTRFS is not set
++# CONFIG_CMD_EROFS is not set
++# CONFIG_CMD_EXT2 is not set
++# CONFIG_CMD_EXT4 is not set
++CONFIG_CMD_FAT=y
++# CONFIG_CMD_SQUASHFS is not set
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++# CONFIG_CMD_JFFS2 is not set
++# CONFIG_CMD_MTDPARTS is not set
++CONFIG_MTDIDS_DEFAULT=""
++CONFIG_MTDPARTS_DEFAULT=""
++# CONFIG_CMD_REISER is not set
++# CONFIG_CMD_ZFS is not set
++
++#
++# Debug commands
++#
++# CONFIG_CMD_DIAG is not set
++# CONFIG_CMD_EVENT is not set
++# CONFIG_CMD_LOG is not set
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITIONS=y
++# CONFIG_MAC_PARTITION is not set
++CONFIG_DOS_PARTITION=y
++# CONFIG_ISO_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++CONFIG_PARTITION_UUIDS=y
++CONFIG_SUPPORT_OF_CONTROL=y
++
++#
++# Device Tree Control
++#
++CONFIG_OF_CONTROL=y
++CONFIG_OF_REAL=y
++# CONFIG_OF_LIVE is not set
++CONFIG_OF_SEPARATE=y
++# CONFIG_OF_EMBED is not set
++# CONFIG_OF_BOARD is not set
++# CONFIG_OF_OMIT_DTB is not set
++CONFIG_DEVICE_TREE_INCLUDES=""
++CONFIG_OF_LIST="openwrt-one"
++# CONFIG_MULTI_DTB_FIT is not set
++CONFIG_OF_TAG_MIGRATE=y
++# CONFIG_OF_DTB_PROPS_REMOVE is not set
++
++#
++# Environment
++#
++CONFIG_ENV_SUPPORT=y
++CONFIG_SAVEENV=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_MIN_ENTRIES=64
++CONFIG_ENV_MAX_ENTRIES=512
++CONFIG_ENV_IS_DEFAULT=y
++CONFIG_ENV_IS_NOWHERE=y
++# CONFIG_ENV_IS_IN_EEPROM is not set
++# CONFIG_ENV_IS_IN_FAT is not set
++# CONFIG_ENV_IS_IN_EXT4 is not set
++# CONFIG_ENV_IS_IN_FLASH is not set
++# CONFIG_ENV_IS_IN_MTD is not set
++# CONFIG_ENV_IS_IN_NAND is not set
++# CONFIG_ENV_IS_IN_NVRAM is not set
++# CONFIG_ENV_IS_IN_ONENAND is not set
++# CONFIG_ENV_IS_IN_REMOTE is not set
++# CONFIG_ENV_IS_IN_SPI_FLASH is not set
++# CONFIG_ENV_IS_IN_UBI is not set
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_DEFAULT_ENV_FILE="openwrt-one-nor_env"
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++# CONFIG_ENV_IMPORT_FDT is not set
++# CONFIG_ENV_APPEND is not set
++# CONFIG_ENV_WRITEABLE_LIST is not set
++# CONFIG_ENV_ACCESS_IGNORE_FORCE is not set
++# CONFIG_USE_BOOTFILE is not set
++# CONFIG_USE_ETHPRIME is not set
++# CONFIG_USE_HOSTNAME is not set
++# CONFIG_VERSION_VARIABLE is not set
++CONFIG_NET=y
++CONFIG_ARP_TIMEOUT=5000
++CONFIG_NET_RETRY_COUNT=5
++CONFIG_PROT_UDP=y
++CONFIG_BOOTDEV_ETH=y
++# CONFIG_BOOTP_SEND_HOSTNAME is not set
++CONFIG_NET_RANDOM_ETHADDR=y
++# CONFIG_NETCONSOLE is not set
++# CONFIG_IP_DEFRAG is not set
++# CONFIG_SYS_FAULT_ECHO_LINK_DOWN is not set
++CONFIG_TFTP_BLOCKSIZE=1468
++# CONFIG_TFTP_PORT is not set
++CONFIG_TFTP_WINDOWSIZE=1
++# CONFIG_TFTP_TSIZE is not set
++# CONFIG_SERVERIP_FROM_PROXYDHCP is not set
++CONFIG_SERVERIP_FROM_PROXYDHCP_DELAY_MS=100
++# CONFIG_KEEP_SERVERADDR is not set
++# CONFIG_UDP_CHECKSUM is not set
++# CONFIG_BOOTP_SERVERIP is not set
++CONFIG_BOOTP_MAX_ROOT_PATH_LEN=64
++# CONFIG_USE_GATEWAYIP is not set
++# CONFIG_USE_IPADDR is not set
++# CONFIG_USE_NETMASK is not set
++# CONFIG_USE_ROOTPATH is not set
++# CONFIG_USE_SERVERIP is not set
++# CONFIG_PROT_TCP is not set
++# CONFIG_IPV6 is not set
++CONFIG_SYS_RX_ETH_BUFFER=4
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_DM=y
++# CONFIG_DM_WARN is not set
++# CONFIG_DM_DEBUG is not set
++# CONFIG_DM_STATS is not set
++CONFIG_DM_DEVICE_REMOVE=y
++CONFIG_DM_EVENT=y
++CONFIG_DM_STDIO=y
++CONFIG_DM_SEQ_ALIAS=y
++# CONFIG_DM_DMA is not set
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++# CONFIG_DEVRES is not set
++CONFIG_SIMPLE_BUS=y
++# CONFIG_SIMPLE_BUS_CORRECT_RANGE is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++CONFIG_OF_TRANSLATE=y
++# CONFIG_TRANSLATION_OFFSET is not set
++CONFIG_DM_DEV_READ_INLINE=y
++# CONFIG_OFNODE_MULTI_TREE is not set
++# CONFIG_BOUNCE_BUFFER is not set
++# CONFIG_ADC is not set
++# CONFIG_ADC_EXYNOS is not set
++# CONFIG_ADC_SANDBOX is not set
++# CONFIG_SARADC_MESON is not set
++# CONFIG_SARADC_ROCKCHIP is not set
++# CONFIG_SATA is not set
++# CONFIG_SCSI_AHCI is not set
++
++#
++# SATA/SCSI device support
++#
++# CONFIG_AXI is not set
++
++#
++# Bus devices
++#
++CONFIG_BLK=y
++CONFIG_BLOCK_CACHE=y
++# CONFIG_BLKMAP is not set
++# CONFIG_EFI_MEDIA is not set
++# CONFIG_IDE is not set
++# CONFIG_LBA48 is not set
++# CONFIG_SYS_64BIT_LBA is not set
++# CONFIG_RKMTD is not set
++# CONFIG_BOOTCOUNT_LIMIT is not set
++
++#
++# Button Support
++#
++CONFIG_BUTTON=y
++# CONFIG_BUTTON_ADC is not set
++CONFIG_BUTTON_GPIO=y
++
++#
++# Cache Controller drivers
++#
++# CONFIG_CACHE is not set
++# CONFIG_L2X0_CACHE is not set
++# CONFIG_V5L2_CACHE is not set
++# CONFIG_NCORE_CACHE is not set
++# CONFIG_SIFIVE_CCACHE is not set
++
++#
++# Clock
++#
++CONFIG_CLK=y
++# CONFIG_CLK_CCF is not set
++# CONFIG_CLK_GPIO is not set
++# CONFIG_CLK_CDCE9XX is not set
++# CONFIG_CLK_ICS8N3QV01 is not set
++# CONFIG_CLK_K210 is not set
++# CONFIG_CLK_MPC83XX is not set
++# CONFIG_CLK_XLNX_CLKWZRD is not set
++# CONFIG_CLK_AT91 is not set
++# CONFIG_CLK_RCAR is not set
++# CONFIG_CLK_RCAR_CPG_LIB is not set
++# CONFIG_CLK_SIFIVE is not set
++# CONFIG_CLK_TI_AM3_DPLL is not set
++# CONFIG_CLK_TI_CTRL is not set
++# CONFIG_CLK_TI_GATE is not set
++# CONFIG_CLK_K3 is not set
++CONFIG_CPU=y
++# CONFIG_CPU_IMX is not set
++
++#
++# Hardware crypto devices
++#
++# CONFIG_DM_HASH is not set
++# CONFIG_FSL_CAAM is not set
++CONFIG_CAAM_64BIT=y
++# CONFIG_SYS_FSL_SEC_BE is not set
++# CONFIG_SYS_FSL_SEC_LE is not set
++# CONFIG_NPCM_AES is not set
++# CONFIG_NPCM_SHA is not set
++# CONFIG_DDR_SPD is not set
++# CONFIG_IMX_SNPS_DDR_PHY is not set
++
++#
++# Demo for driver model
++#
++# CONFIG_DM_DEMO is not set
++
++#
++# DFU support
++#
++
++#
++# DMA Support
++#
++# CONFIG_DMA is not set
++# CONFIG_DMA_LPC32XX is not set
++# CONFIG_TI_EDMA3 is not set
++# CONFIG_DMA_LEGACY is not set
++
++#
++# Extcon Support
++#
++# CONFIG_EXTCON is not set
++
++#
++# Fastboot support
++#
++# CONFIG_UDP_FUNCTION_FASTBOOT is not set
++# CONFIG_TCP_FUNCTION_FASTBOOT is not set
++CONFIG_FIRMWARE=y
++CONFIG_ARM_PSCI_FW=y
++# CONFIG_ZYNQMP_FIRMWARE is not set
++# CONFIG_ARM_SMCCC_FEATURES is not set
++# CONFIG_ARM_FFA_TRANSPORT is not set
++# CONFIG_SCMI_FIRMWARE is not set
++# CONFIG_DM_FUZZING_ENGINE is not set
++
++#
++# FPGA support
++#
++# CONFIG_FPGA_ALTERA is not set
++# CONFIG_FPGA_SOCFPGA is not set
++# CONFIG_FPGA_LATTICE is not set
++# CONFIG_FPGA_XILINX is not set
++# CONFIG_DM_FPGA is not set
++# CONFIG_FWU_MDATA is not set
++CONFIG_GPIO=y
++CONFIG_GPIO_HOG=y
++# CONFIG_DM_GPIO_LOOKUP_LABEL is not set
++# CONFIG_ALTERA_PIO is not set
++# CONFIG_BCM2835_GPIO is not set
++# CONFIG_DWAPB_GPIO is not set
++# CONFIG_AT91_GPIO is not set
++# CONFIG_ATMEL_PIO4 is not set
++# CONFIG_ASPEED_GPIO is not set
++# CONFIG_DA8XX_GPIO is not set
++# CONFIG_HIKEY_GPIO is not set
++# CONFIG_INTEL_BROADWELL_GPIO is not set
++# CONFIG_INTEL_GPIO is not set
++# CONFIG_INTEL_ICH6_GPIO is not set
++# CONFIG_IMX_RGPIO2P is not set
++# CONFIG_IPROC_GPIO is not set
++# CONFIG_HSDK_CREG_GPIO is not set
++# CONFIG_KIRKWOOD_GPIO is not set
++# CONFIG_LPC32XX_GPIO is not set
++# CONFIG_MCP230XX_GPIO is not set
++# CONFIG_MSM_GPIO is not set
++# CONFIG_MXC_GPIO is not set
++# CONFIG_MXS_GPIO is not set
++# CONFIG_NPCM_GPIO is not set
++# CONFIG_CMD_PCA953X is not set
++# CONFIG_ROCKCHIP_GPIO is not set
++# CONFIG_XILINX_GPIO is not set
++# CONFIG_TCA642X is not set
++# CONFIG_TEGRA_GPIO is not set
++# CONFIG_TEGRA186_GPIO is not set
++# CONFIG_VYBRID_GPIO is not set
++# CONFIG_SIFIVE_GPIO is not set
++# CONFIG_ZYNQ_GPIO is not set
++# CONFIG_DM_74X164 is not set
++# CONFIG_PCA953X is not set
++# CONFIG_MPC8XXX_GPIO is not set
++# CONFIG_MPC8XX_GPIO is not set
++# CONFIG_NX_GPIO is not set
++# CONFIG_NOMADIK_GPIO is not set
++# CONFIG_ZYNQMP_GPIO_MODEPIN is not set
++# CONFIG_SLG7XL45106_I2C_GPO is not set
++# CONFIG_TURRIS_OMNIA_MCU is not set
++# CONFIG_FTGPIO010 is not set
++
++#
++# Hardware Spinlock Support
++#
++# CONFIG_DM_HWSPINLOCK is not set
++CONFIG_I2C=y
++# CONFIG_DM_I2C is not set
++# CONFIG_SYS_I2C_LEGACY is not set
++# CONFIG_SPL_SYS_I2C_LEGACY is not set
++# CONFIG_SYS_I2C_FSL is not set
++# CONFIG_SYS_I2C_DW is not set
++# CONFIG_SYS_I2C_IMX_LPI2C is not set
++# CONFIG_SYS_I2C_MTK is not set
++# CONFIG_SYS_I2C_MICROCHIP is not set
++# CONFIG_SYS_I2C_MXC is not set
++# CONFIG_SYS_I2C_NPCM is not set
++# CONFIG_SYS_I2C_SOFT is not set
++# CONFIG_SYS_I2C_MV is not set
++# CONFIG_SYS_I2C_MVTWSI is not set
++CONFIG_INPUT=y
++# CONFIG_DM_KEYBOARD is not set
++# CONFIG_CROS_EC_KEYB is not set
++# CONFIG_TEGRA_KEYBOARD is not set
++# CONFIG_TWL4030_INPUT is not set
++
++#
++# IOMMU device drivers
++#
++# CONFIG_IOMMU is not set
++
++#
++# LED Support
++#
++CONFIG_LED=y
++# CONFIG_LED_PWM is not set
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++# CONFIG_LED_STATUS is not set
++
++#
++# Mailbox Controller Support
++#
++# CONFIG_DM_MAILBOX is not set
++
++#
++# Memory Controller drivers
++#
++# CONFIG_MEMORY is not set
++# CONFIG_ATMEL_EBI is not set
++# CONFIG_MFD_ATMEL_SMC is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MISC is not set
++# CONFIG_NVMEM is not set
++# CONFIG_SPL_NVMEM is not set
++# CONFIG_SMSC_LPC47M is not set
++# CONFIG_SMSC_SIO1007 is not set
++# CONFIG_CROS_EC is not set
++# CONFIG_DS4510 is not set
++# CONFIG_FSL_SEC_MON is not set
++# CONFIG_IRQ is not set
++# CONFIG_NPCM_HOST is not set
++# CONFIG_NUVOTON_NCT6102D is not set
++# CONFIG_PWRSEQ is not set
++# CONFIG_PCA9551_LED is not set
++# CONFIG_TEST_DRV is not set
++# CONFIG_USB_HUB_USB251XB is not set
++# CONFIG_TWL4030_LED is not set
++# CONFIG_WINBOND_W83627 is not set
++# CONFIG_FS_LOADER is not set
++
++#
++# MMC Host controller Support
++#
++# CONFIG_MMC is not set
++# CONFIG_MMC_BROKEN_CD is not set
++# CONFIG_DM_MMC is not set
++# CONFIG_FSL_ESDHC is not set
++# CONFIG_FSL_ESDHC_IMX is not set
++
++#
++# MTD Support
++#
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD=y
++CONFIG_DM_MTD=y
++# CONFIG_MTD_NOR_FLASH is not set
++# CONFIG_MTD_CONCAT is not set
++# CONFIG_SYS_MTDPARTS_RUNTIME is not set
++# CONFIG_FLASH_CFI_DRIVER is not set
++# CONFIG_CFI_FLASH is not set
++# CONFIG_ALTERA_QSPI is not set
++# CONFIG_HBMC_AM654 is not set
++# CONFIG_SAMSUNG_ONENAND is not set
++# CONFIG_USE_SYS_MAX_FLASH_BANKS is not set
++CONFIG_MTD_NAND_CORE=y
++# CONFIG_MTD_RAW_NAND is not set
++CONFIG_MTD_SPI_NAND=y
++
++#
++# SPI Flash Support
++#
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH=y
++CONFIG_SF_DEFAULT_BUS=0
++CONFIG_SF_DEFAULT_CS=0
++# CONFIG_BOOTDEV_SPI_FLASH is not set
++CONFIG_SPI_FLASH_SFDP_SUPPORT=y
++CONFIG_SPI_FLASH_SMART_HWCAPS=y
++# CONFIG_SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT is not set
++# CONFIG_SPI_FLASH_SOFT_RESET is not set
++# CONFIG_SPI_FLASH_BAR is not set
++CONFIG_SPI_FLASH_LOCK=y
++CONFIG_SPI_FLASH_UNLOCK_ALL=y
++# CONFIG_SPI_FLASH_ATMEL is not set
++CONFIG_SPI_FLASH_EON=y
++CONFIG_SPI_FLASH_GIGADEVICE=y
++CONFIG_SPI_FLASH_ISSI=y
++CONFIG_SPI_FLASH_MACRONIX=y
++CONFIG_SPI_FLASH_SPANSION=y
++# CONFIG_SPI_FLASH_S28HX_T is not set
++CONFIG_SPI_FLASH_STMICRO=y
++# CONFIG_SPI_FLASH_MT35XU is not set
++# CONFIG_SPI_FLASH_SST is not set
++CONFIG_SPI_FLASH_WINBOND=y
++CONFIG_SPI_FLASH_XMC=y
++CONFIG_SPI_FLASH_XTX=y
++# CONFIG_SPI_FLASH_ZBIT is not set
++CONFIG_SPI_FLASH_USE_4K_SECTORS=y
++# CONFIG_SPI_FLASH_DATAFLASH is not set
++CONFIG_SPI_FLASH_MTD=y
++
++#
++# UBI support
++#
++CONFIG_UBI_SILENCE_MSG=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_MODULE=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++# CONFIG_NVMXIP is not set
++# CONFIG_NVMXIP_QSPI is not set
++# CONFIG_NMBM is not set
++
++#
++# Multiplexer drivers
++#
++# CONFIG_MULTIPLEXER is not set
++# CONFIG_BITBANGMII is not set
++# CONFIG_MV88E6352_SWITCH is not set
++CONFIG_PHYLIB=y
++# CONFIG_PHY_ADDR_ENABLE is not set
++# CONFIG_B53_SWITCH is not set
++# CONFIG_MV88E61XX_SWITCH is not set
++# CONFIG_PHYLIB_10G is not set
++# CONFIG_PHY_ADIN is not set
++# CONFIG_PHY_AIROHA is not set
++# CONFIG_PHY_AQUANTIA is not set
++# CONFIG_PHY_ATHEROS is not set
++# CONFIG_SPL_PHY_ATHEROS is not set
++# CONFIG_PHY_BROADCOM is not set
++# CONFIG_PHY_CORTINA is not set
++# CONFIG_PHY_DAVICOM is not set
++# CONFIG_PHY_ET1011C is not set
++# CONFIG_PHY_LXT is not set
++# CONFIG_PHY_MARVELL is not set
++# CONFIG_PHY_MARVELL_10G is not set
++# CONFIG_PHY_MESON_GXL is not set
++# CONFIG_PHY_MICREL is not set
++# CONFIG_PHY_MOTORCOMM is not set
++# CONFIG_PHY_MSCC is not set
++# CONFIG_PHY_NATSEMI is not set
++# CONFIG_PHY_NXP_C45_TJA11XX is not set
++# CONFIG_PHY_NXP_TJA11XX is not set
++# CONFIG_PHY_REALTEK is not set
++# CONFIG_PHY_SMSC is not set
++# CONFIG_PHY_TERANETICS is not set
++# CONFIG_PHY_TI is not set
++# CONFIG_PHY_TI_DP83867 is not set
++# CONFIG_PHY_TI_DP83869 is not set
++# CONFIG_PHY_TI_GENERIC is not set
++# CONFIG_PHY_VITESSE is not set
++# CONFIG_PHY_XILINX is not set
++# CONFIG_PHY_XILINX_GMII2RGMII is not set
++# CONFIG_PHY_XWAY is not set
++# CONFIG_PHY_ETHERNET_ID is not set
++CONFIG_PHY_FIXED=y
++# CONFIG_PHY_NCSI is not set
++# CONFIG_FSL_MEMAC is not set
++CONFIG_PHY_RESET_DELAY=0
++# CONFIG_FSL_PFE is not set
++CONFIG_ETH=y
++CONFIG_DM_ETH=y
++# CONFIG_DM_MDIO is not set
++# CONFIG_DM_ETH_PHY is not set
++CONFIG_NETDEVICES=y
++# CONFIG_PHY_GIGE is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_BCM_SF2_ETH is not set
++# CONFIG_BCMGENET is not set
++# CONFIG_BNXT_ETH is not set
++# CONFIG_CALXEDA_XGMAC is not set
++# CONFIG_DRIVER_DM9000 is not set
++# CONFIG_DWC_ETH_QOS is not set
++# CONFIG_EEPRO100 is not set
++# CONFIG_ETH_DESIGNWARE is not set
++# CONFIG_ETH_DESIGNWARE_MESON8B is not set
++# CONFIG_ETHOC is not set
++# CONFIG_FMAN_ENET is not set
++# CONFIG_FTMAC100 is not set
++# CONFIG_FTGMAC100 is not set
++# CONFIG_MCFFEC is not set
++# CONFIG_FSLDMAFEC is not set
++# CONFIG_KS8851_MLL is not set
++# CONFIG_LITEETH is not set
++# CONFIG_MACB is not set
++# CONFIG_NET_NPCM750 is not set
++# CONFIG_PCH_GBE is not set
++# CONFIG_RGMII is not set
++# CONFIG_MII is not set
++# CONFIG_RMII is not set
++# CONFIG_PCNET is not set
++# CONFIG_QE_UEC is not set
++# CONFIG_RTL8139 is not set
++# CONFIG_SMC911X is not set
++# CONFIG_SUN7I_GMAC is not set
++# CONFIG_SUN4I_EMAC is not set
++# CONFIG_SUN8I_EMAC is not set
++# CONFIG_SH_ETHER is not set
++# CONFIG_DRIVER_TI_CPSW is not set
++# CONFIG_DRIVER_TI_EMAC is not set
++# CONFIG_DRIVER_TI_KEYSTONE_NET is not set
++# CONFIG_TULIP is not set
++# CONFIG_XILINX_AXIEMAC is not set
++# CONFIG_VSC7385_ENET is not set
++# CONFIG_XILINX_EMACLITE is not set
++# CONFIG_ZYNQ_GEM is not set
++# CONFIG_SYS_DPAA_QBMAN is not set
++# CONFIG_TSEC_ENET is not set
++CONFIG_MEDIATEK_ETH=y
++# CONFIG_HIFEMAC_ETH is not set
++# CONFIG_HIGMACV300_ETH is not set
++# CONFIG_NVME is not set
++# CONFIG_NVME_APPLE is not set
++
++#
++# PCI Endpoint
++#
++# CONFIG_PCI_ENDPOINT is not set
++# CONFIG_X86_PCH7 is not set
++# CONFIG_X86_PCH9 is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_PHY=y
++# CONFIG_NOP_PHY is not set
++# CONFIG_MIPI_DPHY_HELPERS is not set
++# CONFIG_BCM_SR_PCIE_PHY is not set
++# CONFIG_OMAP_USB2_PHY is not set
++CONFIG_PHY_MTK_TPHY=y
++
++#
++# Rockchip PHY driver
++#
++# CONFIG_PHY_CADENCE_SIERRA is not set
++# CONFIG_PHY_CADENCE_TORRENT is not set
++# CONFIG_MSM8916_USB_PHY is not set
++# CONFIG_MVEBU_COMPHY_SUPPORT is not set
++
++#
++# Pin controllers
++#
++CONFIG_PINCTRL=y
++CONFIG_PINCTRL_FULL=y
++CONFIG_PINCTRL_GENERIC=y
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_PINCONF_RECURSIVE=y
++# CONFIG_PINCTRL_AT91 is not set
++# CONFIG_PINCTRL_AT91PIO4 is not set
++# CONFIG_PINCTRL_INTEL is not set
++# CONFIG_PINCTRL_QE is not set
++# CONFIG_PINCTRL_ROCKCHIP_RV1108 is not set
++# CONFIG_PINCTRL_SINGLE is not set
++# CONFIG_PINCTRL_STM32 is not set
++# CONFIG_PINCTRL_STMFX is not set
++# CONFIG_PINCTRL_K210 is not set
++CONFIG_PINCTRL_MTK=y
++# CONFIG_PINCTRL_MT7622 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT7629 is not set
++CONFIG_PINCTRL_MT7981=y
++# CONFIG_PINCTRL_MT7986 is not set
++# CONFIG_PINCTRL_MT7988 is not set
++# CONFIG_PINCTRL_MT8512 is not set
++# CONFIG_PINCTRL_MT8516 is not set
++# CONFIG_PINCTRL_MT8518 is not set
++CONFIG_POWER=y
++# CONFIG_POWER_LEGACY is not set
++# CONFIG_ACPI_PMC is not set
++
++#
++# Power Domain Support
++#
++CONFIG_POWER_DOMAIN=y
++# CONFIG_APPLE_PMGR_POWER_DOMAIN is not set
++CONFIG_MTK_POWER_DOMAIN=y
++# CONFIG_DM_PMIC is not set
++# CONFIG_PMIC_TPS65217 is not set
++# CONFIG_POWER_TPS65218 is not set
++# CONFIG_POWER_TPS62362 is not set
++# CONFIG_DM_REGULATOR is not set
++# CONFIG_TPS6586X_POWER is not set
++# CONFIG_POWER_MT6323 is not set
++CONFIG_DM_PWM=y
++# CONFIG_PWM_ASPEED is not set
++# CONFIG_PWM_CADENCE_TTC is not set
++# CONFIG_PWM_CROS_EC is not set
++# CONFIG_PWM_EXYNOS is not set
++# CONFIG_PWM_IMX is not set
++# CONFIG_PWM_MESON is not set
++CONFIG_PWM_MTK=y
++# CONFIG_PWM_ROCKCHIP is not set
++# CONFIG_PWM_SANDBOX is not set
++# CONFIG_PWM_SIFIVE is not set
++# CONFIG_PWM_TEGRA is not set
++# CONFIG_PWM_SUNXI is not set
++# CONFIG_U_QE is not set
++# CONFIG_RAM is not set
++
++#
++# Reboot Mode Support
++#
++# CONFIG_DM_REBOOT_MODE is not set
++
++#
++# Remote Processor drivers
++#
++
++#
++# Reset Controller Support
++#
++# CONFIG_RESET_AST2500 is not set
++# CONFIG_RESET_AST2600 is not set
++CONFIG_RESET_MEDIATEK=y
++# CONFIG_RESET_HISILICON is not set
++# CONFIG_RESET_SYSCON is not set
++# CONFIG_RESET_SCMI is not set
++# CONFIG_RESET_DRA7 is not set
++# CONFIG_DM_RNG is not set
++
++#
++# Real Time Clock
++#
++# CONFIG_DM_RTC is not set
++# CONFIG_RTC_ENABLE_32KHZ_OUTPUT is not set
++# CONFIG_RTC_DS1337 is not set
++# CONFIG_RTC_DS1338 is not set
++# CONFIG_RTC_DS1374 is not set
++# CONFIG_RTC_DS3231 is not set
++# CONFIG_RTC_PCF8563 is not set
++# CONFIG_RTC_PT7C4338 is not set
++# CONFIG_RTC_PL031 is not set
++# CONFIG_RTC_S35392A is not set
++# CONFIG_RTC_MC13XXX is not set
++# CONFIG_RTC_MC146818 is not set
++# CONFIG_RTC_M41T62 is not set
++# CONFIG_SCSI is not set
++# CONFIG_DM_SCSI is not set
++CONFIG_SERIAL=y
++CONFIG_BAUDRATE=115200
++# CONFIG_DEFAULT_ENV_IS_RW is not set
++CONFIG_REQUIRE_SERIAL_CONSOLE=y
++# CONFIG_SPECIFY_CONSOLE_INDEX is not set
++CONFIG_SERIAL_PRESENT=y
++CONFIG_DM_SERIAL=y
++# CONFIG_SERIAL_RX_BUFFER is not set
++# CONFIG_SERIAL_PUTS is not set
++# CONFIG_SERIAL_SEARCH_ALL is not set
++# CONFIG_SERIAL_PROBE_ALL is not set
++# CONFIG_VPL_DM_SERIAL is not set
++CONFIG_DEBUG_UART_MTK=y
++CONFIG_DEBUG_UART_SHIFT=0
++# CONFIG_DEBUG_UART_ANNOUNCE is not set
++# CONFIG_DEBUG_UART_SKIP_INIT is not set
++# CONFIG_ALTERA_JTAG_UART is not set
++# CONFIG_ALTERA_UART is not set
++# CONFIG_ARC_SERIAL is not set
++# CONFIG_ARM_DCC is not set
++# CONFIG_ATMEL_USART is not set
++# CONFIG_BCM6345_SERIAL is not set
++# CONFIG_COREBOOT_SERIAL is not set
++# CONFIG_CORTINA_UART is not set
++# CONFIG_FSL_LINFLEXUART is not set
++# CONFIG_FSL_LPUART is not set
++# CONFIG_MVEBU_A3700_UART is not set
++# CONFIG_MCFUART is not set
++# CONFIG_NULLDEV_SERIAL is not set
++# CONFIG_SYS_NS16550 is not set
++# CONFIG_PL01X_SERIAL is not set
++# CONFIG_ROCKCHIP_SERIAL is not set
++# CONFIG_XILINX_UARTLITE is not set
++# CONFIG_MSM_SERIAL is not set
++# CONFIG_MSM_GENI_SERIAL is not set
++# CONFIG_MXS_AUART_SERIAL is not set
++# CONFIG_OMAP_SERIAL is not set
++# CONFIG_SIFIVE_SERIAL is not set
++# CONFIG_ZYNQ_SERIAL is not set
++CONFIG_MTK_SERIAL=y
++# CONFIG_MT7620_SERIAL is not set
++# CONFIG_NPCM_SERIAL is not set
++# CONFIG_SM is not set
++# CONFIG_MESON_SM is not set
++# CONFIG_SMEM is not set
++
++#
++# Sound support
++#
++# CONFIG_SOUND is not set
++
++#
++# SOC (System On Chip) specific Drivers
++#
++# CONFIG_SOC_DEVICE is not set
++# CONFIG_SOC_TI is not set
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_SPI_MEM=y
++# CONFIG_SPI_DIRMAP is not set
++# CONFIG_ALTERA_SPI is not set
++# CONFIG_APPLE_SPI is not set
++# CONFIG_ATCSPI200_SPI is not set
++# CONFIG_ATMEL_SPI is not set
++# CONFIG_BCMSTB_SPI is not set
++# CONFIG_CORTINA_SFLASH is not set
++# CONFIG_CADENCE_QSPI is not set
++# CONFIG_CF_SPI is not set
++# CONFIG_DESIGNWARE_SPI is not set
++# CONFIG_EXYNOS_SPI is not set
++# CONFIG_FSL_DSPI is not set
++# CONFIG_FSL_QSPI is not set
++# CONFIG_GXP_SPI is not set
++# CONFIG_ICH_SPI is not set
++# CONFIG_IPROC_QSPI is not set
++# CONFIG_KIRKWOOD_SPI is not set
++# CONFIG_MICROCHIP_COREQSPI is not set
++# CONFIG_MPC8XXX_SPI is not set
++# CONFIG_MTK_SNOR is not set
++# CONFIG_MTK_SNFI_SPI is not set
++CONFIG_MTK_SPIM=y
++# CONFIG_MVEBU_A3700_SPI is not set
++# CONFIG_MXS_SPI is not set
++# CONFIG_SPI_MXIC is not set
++# CONFIG_NPCM_FIU_SPI is not set
++# CONFIG_NPCM_PSPI is not set
++# CONFIG_NXP_FSPI is not set
++# CONFIG_OMAP3_SPI is not set
++# CONFIG_PL022_SPI is not set
++# CONFIG_ROCKCHIP_SFC is not set
++# CONFIG_ROCKCHIP_SPI is not set
++# CONFIG_SPI_ASPEED_SMC is not set
++# CONFIG_SPI_SIFIVE is not set
++# CONFIG_SOFT_SPI is not set
++# CONFIG_SPI_SN_F_OSPI is not set
++# CONFIG_SPI_SUNXI is not set
++# CONFIG_TEGRA114_SPI is not set
++# CONFIG_TEGRA20_SFLASH is not set
++# CONFIG_TEGRA20_SLINK is not set
++# CONFIG_TEGRA210_QSPI is not set
++# CONFIG_TI_QSPI is not set
++# CONFIG_XILINX_SPI is not set
++# CONFIG_ZYNQ_SPI is not set
++# CONFIG_ZYNQ_QSPI is not set
++# CONFIG_ZYNQMP_GQSPI is not set
++# CONFIG_SH_QSPI is not set
++# CONFIG_MXC_SPI is not set
++
++#
++# SPMI support
++#
++# CONFIG_SPMI is not set
++# CONFIG_SYSINFO is not set
++
++#
++# System reset device drivers
++#
++# CONFIG_SYSRESET is not set
++# CONFIG_TEE is not set
++# CONFIG_DM_THERMAL is not set
++
++#
++# Timer Support
++#
++# CONFIG_TIMER is not set
++
++#
++# TPM support
++#
++CONFIG_USB=y
++CONFIG_DM_USB=y
++# CONFIG_DM_USB_GADGET is not set
++
++#
++# USB Host Controller Drivers
++#
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++# CONFIG_USB_XHCI_DWC3 is not set
++# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set
++CONFIG_USB_XHCI_MTK=y
++# CONFIG_USB_XHCI_FSL is not set
++# CONFIG_USB_XHCI_BRCM is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_ISP1760 is not set
++# CONFIG_USB_CDNS3 is not set
++# CONFIG_USB_DWC3 is not set
++# CONFIG_USB_MTU3 is not set
++
++#
++# Legacy MUSB Support
++#
++# CONFIG_USB_MUSB_HCD is not set
++# CONFIG_USB_MUSB_UDC is not set
++
++#
++# MUSB Controller Driver
++#
++# CONFIG_USB_MUSB_HOST is not set
++# CONFIG_USB_MUSB_PIO_ONLY is not set
++
++#
++# USB Phy
++#
++# CONFIG_TWL4030_USB is not set
++# CONFIG_ROCKCHIP_USB2_PHY is not set
++
++#
++# ULPI drivers
++#
++
++#
++# USB peripherals
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_KEYBOARD is not set
++# CONFIG_USB_ONBOARD_HUB is not set
++CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=1000
++# CONFIG_USB_HOST_ETHER is not set
++# CONFIG_USB_GADGET is not set
++# CONFIG_SPL_USB_GADGET is not set
++
++#
++# UFS Host Controller Support
++#
++# CONFIG_TI_J721E_UFS is not set
++
++#
++# Graphics support
++#
++# CONFIG_VIDEO is not set
++
++#
++# VirtIO Drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# 1-Wire support
++#
++# CONFIG_W1 is not set
++
++#
++# 1-wire EEPROM support
++#
++# CONFIG_W1_EEPROM is not set
++
++#
++# Watchdog Timer Support
++#
++# CONFIG_WATCHDOG is not set
++CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
++# CONFIG_IMX_WATCHDOG is not set
++# CONFIG_ULP_WATCHDOG is not set
++# CONFIG_WDT is not set
++# CONFIG_PHYS_TO_BUS is not set
++
++#
++# File systems
++#
++# CONFIG_FS_BTRFS is not set
++# CONFIG_FS_CBFS is not set
++# CONFIG_FS_EXT4 is not set
++CONFIG_FS_FAT=y
++CONFIG_FAT_WRITE=y
++CONFIG_FS_FAT_MAX_CLUSTSIZE=65536
++# CONFIG_FS_JFFS2 is not set
++CONFIG_UBIFS_SILENCE_MSG=y
++CONFIG_UBIFS_SILENCE_DEBUG_DUMP=y
++# CONFIG_FS_CRAMFS is not set
++# CONFIG_YAFFS2 is not set
++# CONFIG_FS_SQUASHFS is not set
++# CONFIG_FS_EROFS is not set
++
++#
++# Library routines
++#
++# CONFIG_ADDR_MAP is not set
++# CONFIG_SYS_TIMER_COUNTS_DOWN is not set
++# CONFIG_PHYSMEM is not set
++# CONFIG_BCH is not set
++# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
++CONFIG_CHARSET=y
++# CONFIG_DYNAMIC_CRC_TABLE is not set
++CONFIG_LIB_UUID=y
++# CONFIG_SEMIHOSTING is not set
++CONFIG_PRINTF=y
++CONFIG_SPRINTF=y
++CONFIG_STRTO=y
++CONFIG_SYS_HZ=1000
++# CONFIG_PANIC_HANG is not set
++CONFIG_REGEX=y
++CONFIG_LIB_RAND=y
++# CONFIG_LIB_HW_RAND is not set
++CONFIG_SUPPORT_ACPI=y
++# CONFIG_ACPI is not set
++CONFIG_RBTREE=y
++# CONFIG_BITREVERSE is not set
++# CONFIG_TRACE is not set
++# CONFIG_CIRCBUF is not set
++# CONFIG_CMD_DHRYSTONE is not set
++
++#
++# Security support
++#
++# CONFIG_AES is not set
++# CONFIG_ECDSA is not set
++# CONFIG_RSA is not set
++# CONFIG_TPM is not set
++
++#
++# Android Verified Boot
++#
++
++#
++# Hashing Support
++#
++# CONFIG_BLAKE2 is not set
++CONFIG_SHA1=y
++CONFIG_SHA256=y
++# CONFIG_SHA512 is not set
++# CONFIG_SHA384 is not set
++# CONFIG_SHA_HW_ACCEL is not set
++CONFIG_MD5=y
++CONFIG_CRC8=y
++CONFIG_CRC32=y
++
++#
++# Compression Support
++#
++# CONFIG_LZ4 is not set
++CONFIG_LZMA=y
++CONFIG_LZO=y
++CONFIG_GZIP=y
++# CONFIG_ZLIB_UNCOMPRESS is not set
++# CONFIG_BZIP2 is not set
++CONFIG_ZLIB=y
++# CONFIG_ZSTD is not set
++CONFIG_VPL_LZMA=y
++# CONFIG_SPL_GZIP is not set
++# CONFIG_ERRNO_STR is not set
++CONFIG_HEXDUMP=y
++# CONFIG_GETOPT is not set
++CONFIG_OF_LIBFDT=y
++CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
++CONFIG_SYS_FDT_PAD=0x3000
++
++#
++# System tables
++#
++CONFIG_GENERATE_SMBIOS_TABLE=y
++# CONFIG_LIB_RATIONAL is not set
++CONFIG_SMBIOS=y
++# CONFIG_SMBIOS_PARSER is not set
++CONFIG_EFI_LOADER=y
++CONFIG_CMD_BOOTEFI_BOOTMGR=y
++CONFIG_EFI_VARIABLE_FILE_STORE=y
++# CONFIG_EFI_VARIABLE_NO_STORE is not set
++# CONFIG_EFI_VARIABLES_PRESEED is not set
++CONFIG_EFI_VAR_BUF_SIZE=131072
++# CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN is not set
++# CONFIG_EFI_RUNTIME_UPDATE_CAPSULE is not set
++CONFIG_EFI_CAPSULE_MAX=15
++CONFIG_EFI_DEVICE_PATH_TO_TEXT=y
++CONFIG_EFI_DEVICE_PATH_UTIL=y
++CONFIG_EFI_DT_FIXUP=y
++CONFIG_EFI_LOADER_HII=y
++CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y
++CONFIG_EFI_UNICODE_CAPITALIZATION=y
++# CONFIG_EFI_LOADER_BOUNCE_BUFFER is not set
++CONFIG_EFI_PLATFORM_LANG_CODES="en-US"
++CONFIG_EFI_HAVE_RUNTIME_RESET=y
++CONFIG_EFI_LOAD_FILE2_INITRD=y
++CONFIG_EFI_ECPT=y
++CONFIG_EFI_EBBR_2_1_CONFORMANCE=y
++# CONFIG_OPTEE_LIB is not set
++# CONFIG_OPTEE_IMAGE is not set
++# CONFIG_BOOTM_OPTEE is not set
++# CONFIG_TEST_FDTDEC is not set
++CONFIG_LIB_ELF=y
++CONFIG_LMB=y
++CONFIG_LMB_USE_MAX_REGIONS=y
++CONFIG_LMB_MAX_REGIONS=64
++# CONFIG_PHANDLE_CHECK_SEQ is not set
++
++#
++# Testing
++#
++# CONFIG_UNIT_TEST is not set
++# CONFIG_POST is not set
++
++#
++# Tools options
++#
++CONFIG_MKIMAGE_DTC_PATH="dtc"
++CONFIG_TOOLS_CRC32=y
++# CONFIG_TOOLS_LIBCRYPTO is not set
++CONFIG_TOOLS_FIT=y
++CONFIG_TOOLS_FIT_FULL_CHECK=y
++CONFIG_TOOLS_FIT_PRINT=y
++CONFIG_TOOLS_FIT_RSASSA_PSS=y
++CONFIG_TOOLS_FIT_SIGNATURE=y
++CONFIG_TOOLS_FIT_SIGNATURE_MAX_SIZE=0x10000000
++CONFIG_TOOLS_FIT_VERBOSE=y
++CONFIG_TOOLS_MD5=y
++CONFIG_TOOLS_OF_LIBFDT=y
++CONFIG_TOOLS_SHA1=y
++CONFIG_TOOLS_SHA256=y
++CONFIG_TOOLS_SHA384=y
++CONFIG_TOOLS_SHA512=y
++# CONFIG_TOOLS_MKEFICAPSULE is not set
++# CONFIG_FSPI_CONF_HEADER is not set
++# CONFIG_TOOLS_MKFWUMDATA is not set
+--- /dev/null
++++ b/configs/mt7981_openwrt-one-spi-nand_defconfig
+@@ -0,0 +1,1815 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# U-Boot 2024.01 Configuration
++#
++
++#
++# Compiler: aarch64-openwrt-linux-musl-gcc (OpenWrt GCC 12.3.0 r25206+8-d5e2177a6b) 12.3.0
++#
++CONFIG_CREATE_ARCH_SYMLINK=y
++CONFIG_SYS_CACHE_SHIFT_6=y
++CONFIG_SYS_CACHELINE_SIZE=64
++CONFIG_LINKER_LIST_ALIGN=8
++# CONFIG_ARC is not set
++CONFIG_ARM=y
++# CONFIG_M68K is not set
++# CONFIG_MICROBLAZE is not set
++# CONFIG_MIPS is not set
++# CONFIG_NIOS2 is not set
++# CONFIG_PPC is not set
++# CONFIG_RISCV is not set
++# CONFIG_SANDBOX is not set
++# CONFIG_SH is not set
++# CONFIG_X86 is not set
++# CONFIG_XTENSA is not set
++CONFIG_SYS_ARCH="arm"
++CONFIG_SYS_CPU="armv8"
++CONFIG_SYS_SOC="mediatek"
++CONFIG_SYS_VENDOR="mediatek"
++CONFIG_SYS_BOARD="mt7981"
++CONFIG_SYS_CONFIG_NAME="mt7981"
++
++#
++# Skipping low level initialization functions
++#
++# CONFIG_SKIP_LOWLEVEL_INIT is not set
++# CONFIG_SKIP_LOWLEVEL_INIT_ONLY is not set
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_SYS_NONCACHED_MEMORY=0x100000
++# CONFIG_SYS_ICACHE_OFF is not set
++# CONFIG_SYS_DCACHE_OFF is not set
++
++#
++# ARM architecture
++#
++CONFIG_ARM64=y
++CONFIG_ARM64_CRC32=y
++CONFIG_COUNTER_FREQUENCY=0
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_INIT_SP_RELATIVE=y
++CONFIG_SYS_INIT_SP_BSS_OFFSET=524288
++# CONFIG_GIC_V3_ITS is not set
++CONFIG_STATIC_RELA=y
++CONFIG_DMA_ADDR_T_64BIT=y
++CONFIG_GPIO_EXTRA_HEADER=y
++CONFIG_ARM_ASM_UNIFIED=y
++# CONFIG_SYS_ARM_CACHE_CP15 is not set
++# CONFIG_SYS_ARM_MMU is not set
++# CONFIG_SYS_ARM_MPU is not set
++CONFIG_SYS_ARM_ARCH=8
++CONFIG_SYS_ARM_CACHE_WRITEBACK=y
++# CONFIG_SYS_ARM_CACHE_WRITETHROUGH is not set
++# CONFIG_SYS_ARM_CACHE_WRITEALLOC is not set
++# CONFIG_ARCH_CPU_INIT is not set
++CONFIG_SYS_ARCH_TIMER=y
++CONFIG_ARM_SMCCC=y
++# CONFIG_SYS_L2_PL310 is not set
++# CONFIG_SPL_SYS_L2_PL310 is not set
++# CONFIG_SYS_L2CACHE_OFF is not set
++# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
++# CONFIG_USE_ARCH_MEMCPY is not set
++# CONFIG_USE_ARCH_MEMSET is not set
++CONFIG_ARM64_SUPPORT_AARCH32=y
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_HISTB is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_TARGET_STV0991 is not set
++# CONFIG_ARCH_BCM283X is not set
++# CONFIG_ARCH_BCMSTB is not set
++# CONFIG_ARCH_BCMBCA is not set
++# CONFIG_TARGET_VEXPRESS_CA9X4 is not set
++# CONFIG_TARGET_BCMNS is not set
++# CONFIG_TARGET_BCMNS2 is not set
++# CONFIG_TARGET_BCMNS3 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_S5PC1XX is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_IPQ40XX is not set
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_K3 is not set
++# CONFIG_ARCH_OMAP2PLUS is not set
++# CONFIG_ARCH_MESON is not set
++CONFIG_ARCH_MEDIATEK=y
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_IMX8 is not set
++# CONFIG_ARCH_IMX8M is not set
++# CONFIG_ARCH_IMX8ULP is not set
++# CONFIG_ARCH_IMX9 is not set
++# CONFIG_ARCH_IMXRT is not set
++# CONFIG_ARCH_MX23 is not set
++# CONFIG_ARCH_MX28 is not set
++# CONFIG_ARCH_MX31 is not set
++# CONFIG_ARCH_MX7ULP is not set
++# CONFIG_ARCH_MX7 is not set
++# CONFIG_ARCH_MX6 is not set
++# CONFIG_ARCH_MX5 is not set
++# CONFIG_ARCH_NEXELL is not set
++# CONFIG_ARCH_NPCM is not set
++# CONFIG_ARCH_APPLE is not set
++# CONFIG_ARCH_OWL is not set
++# CONFIG_ARCH_QEMU is not set
++# CONFIG_ARCH_RMOBILE is not set
++# CONFIG_ARCH_SNAPDRAGON is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VERSAL is not set
++# CONFIG_ARCH_VERSAL_NET is not set
++# CONFIG_ARCH_VF610 is not set
++# CONFIG_ARCH_ZYNQ is not set
++# CONFIG_ARCH_ZYNQMP_R5 is not set
++# CONFIG_ARCH_ZYNQMP is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_VEXPRESS64 is not set
++# CONFIG_TARGET_CORSTONE1000 is not set
++# CONFIG_TARGET_TOTAL_COMPUTE is not set
++# CONFIG_TARGET_LS2080A_EMU is not set
++# CONFIG_TARGET_LS1088AQDS is not set
++# CONFIG_TARGET_LS2080AQDS is not set
++# CONFIG_TARGET_LS2080ARDB is not set
++# CONFIG_TARGET_LS2081ARDB is not set
++# CONFIG_TARGET_LX2160ARDB is not set
++# CONFIG_TARGET_LX2160AQDS is not set
++# CONFIG_TARGET_LX2162AQDS is not set
++# CONFIG_TARGET_HIKEY is not set
++# CONFIG_TARGET_HIKEY960 is not set
++# CONFIG_TARGET_POPLAR is not set
++# CONFIG_TARGET_LS1012AQDS is not set
++# CONFIG_TARGET_LS1012ARDB is not set
++# CONFIG_TARGET_LS1012A2G5RDB is not set
++# CONFIG_TARGET_LS1012AFRWY is not set
++# CONFIG_TARGET_LS1012AFRDM is not set
++# CONFIG_TARGET_LS1028AQDS is not set
++# CONFIG_TARGET_LS1028ARDB is not set
++# CONFIG_TARGET_LS1088ARDB is not set
++# CONFIG_TARGET_LS1021AQDS is not set
++# CONFIG_TARGET_LS1021ATWR is not set
++# CONFIG_TARGET_PG_WCOM_SELI8 is not set
++# CONFIG_TARGET_PG_WCOM_EXPU1 is not set
++# CONFIG_TARGET_LS1021ATSN is not set
++# CONFIG_TARGET_LS1021AIOT is not set
++# CONFIG_TARGET_LS1043AQDS is not set
++# CONFIG_TARGET_LS1043ARDB is not set
++# CONFIG_TARGET_LS1046AQDS is not set
++# CONFIG_TARGET_LS1046ARDB is not set
++# CONFIG_TARGET_LS1046AFRWY is not set
++# CONFIG_TARGET_SL28 is not set
++# CONFIG_TARGET_TEN64 is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_SYNQUACER is not set
++# CONFIG_ARCH_STM32 is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_STM32MP is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_OCTEONTX is not set
++# CONFIG_ARCH_OCTEONTX2 is not set
++# CONFIG_TARGET_THUNDERX_88XX is not set
++# CONFIG_ARCH_ASPEED is not set
++# CONFIG_TARGET_DURIAN is not set
++# CONFIG_TARGET_POMELO is not set
++# CONFIG_TARGET_PRESIDIO_ASIC is not set
++# CONFIG_TARGET_XENGUEST_ARM64 is not set
++# CONFIG_ARCH_GXP is not set
++# CONFIG_STATIC_MACH_TYPE is not set
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_LEN=0x400000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_ENV_SOURCE_FILE=""
++CONFIG_SF_DEFAULT_SPEED=1000000
++CONFIG_SF_DEFAULT_MODE=0x0
++CONFIG_ENV_SIZE=0x1f000
++CONFIG_DM_GPIO=y
++CONFIG_DEFAULT_DEVICE_TREE="openwrt-one"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x8000
++CONFIG_DM_RESET=y
++CONFIG_SYS_MONITOR_LEN=0
++# CONFIG_MT8512 is not set
++# CONFIG_TARGET_MT7622 is not set
++# CONFIG_TARGET_MT7623 is not set
++# CONFIG_TARGET_MT7629 is not set
++CONFIG_TARGET_MT7981=y
++# CONFIG_TARGET_MT7986 is not set
++# CONFIG_TARGET_MT7988 is not set
++# CONFIG_TARGET_MT8183 is not set
++# CONFIG_TARGET_MT8512 is not set
++# CONFIG_TARGET_MT8516 is not set
++# CONFIG_TARGET_MT8518 is not set
++CONFIG_MTK_BROM_HEADER_INFO="media=snand;nandinfo=2k+64"
++CONFIG_RESET_BUTTON_LABEL="back"
++CONFIG_RESET_BUTTON_SETTLE_DELAY=0
++CONFIG_ERR_PTR_OFFSET=0x0
++# CONFIG_SPL is not set
++CONFIG_BOOTSTAGE_STASH_ADDR=0x0
++CONFIG_DEBUG_UART_BASE=0x11002000
++CONFIG_DEBUG_UART_CLOCK=40000000
++# CONFIG_DEBUG_UART_BOARD_INIT is not set
++CONFIG_IDENT_STRING=""
++CONFIG_SYS_CLK_FREQ=0
++# CONFIG_CHIP_DIP_SCAN is not set
++# CONFIG_CMO_BY_VA_ONLY is not set
++# CONFIG_ARMV8_MULTIENTRY is not set
++# CONFIG_ARMV8_SET_SMPEN is not set
++# CONFIG_ARMV8_SWITCH_TO_EL1 is not set
++
++#
++# ARMv8 secure monitor firmware
++#
++# CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT is not set
++CONFIG_PSCI_RESET=y
++# CONFIG_ARMV8_PSCI is not set
++# CONFIG_ARMV8_EA_EL3_FIRST is not set
++# CONFIG_ARMV8_CRYPTO is not set
++# CONFIG_CMD_DEKBLOB is not set
++# CONFIG_IMX_CAAM_DEK_ENCAP is not set
++# CONFIG_IMX_OPTEE_DEK_ENCAP is not set
++# CONFIG_IMX_SECO_DEK_ENCAP is not set
++# CONFIG_IMX_ELE_DEK_ENCAP is not set
++# CONFIG_CMD_HDMIDETECT is not set
++CONFIG_IMX_DCD_ADDR=0x00910000
++CONFIG_SYS_MEM_TOP_HIDE=0x0
++CONFIG_SYS_LOAD_ADDR=0x46000000
++
++#
++# ARM debug
++#
++CONFIG_BUILD_TARGET=""
++# CONFIG_PCI is not set
++CONFIG_FWU_NUM_BANKS=2
++CONFIG_FWU_NUM_IMAGES_PER_BANK=2
++CONFIG_DEBUG_UART=y
++# CONFIG_AHCI is not set
++# CONFIG_OF_BOARD_FIXUP is not set
++
++#
++# Functionality shared between NXP SoCs
++#
++# CONFIG_NXP_ESBC is not set
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_CC_IS_GCC=y
++CONFIG_GCC_VERSION=120300
++CONFIG_CLANG_VERSION=0
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++# CONFIG_CC_OPTIMIZE_FOR_SPEED is not set
++# CONFIG_CC_OPTIMIZE_FOR_DEBUG is not set
++# CONFIG_OPTIMIZE_INLINING is not set
++CONFIG_ARCH_SUPPORTS_LTO=y
++# CONFIG_LTO is not set
++CONFIG_CC_HAS_ASM_INLINE=y
++# CONFIG_XEN is not set
++# CONFIG_ENV_VARS_UBOOT_CONFIG is not set
++# CONFIG_SYS_BOOT_GET_CMDLINE is not set
++# CONFIG_SYS_BOOT_GET_KBD is not set
++CONFIG_SYS_MALLOC_F=y
++# CONFIG_VALGRIND is not set
++CONFIG_EXPERT=y
++CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
++# CONFIG_SYS_MALLOC_DEFAULT_TO_INIT is not set
++# CONFIG_TOOLS_DEBUG is not set
++CONFIG_PHYS_64BIT=y
++CONFIG_FDT_64BIT=y
++# CONFIG_REMAKE_ELF is not set
++# CONFIG_HAS_BOARD_SIZE_LIMIT is not set
++# CONFIG_SYS_CUSTOM_LDSCRIPT is not set
++CONFIG_PLATFORM_ELFENTRY="_start"
++CONFIG_STACK_SIZE=0x1000000
++CONFIG_SYS_SRAM_BASE=0x0
++CONFIG_SYS_SRAM_SIZE=0x0
++# CONFIG_MP is not set
++CONFIG_HAVE_TEXT_BASE=y
++# CONFIG_HAVE_SYS_UBOOT_START is not set
++CONFIG_SYS_UBOOT_START=0x41e00000
++# CONFIG_DYNAMIC_SYS_CLK_FREQ is not set
++# CONFIG_API is not set
++
++#
++# Boot options
++#
++
++#
++# Boot images
++#
++# CONFIG_ANDROID_BOOT_IMAGE is not set
++# CONFIG_TIMESTAMP is not set
++CONFIG_FIT=y
++CONFIG_FIT_EXTERNAL_OFFSET=0x0
++CONFIG_FIT_FULL_CHECK=y
++# CONFIG_FIT_SIGNATURE is not set
++# CONFIG_FIT_CIPHER is not set
++# CONFIG_FIT_VERBOSE is not set
++# CONFIG_FIT_BEST_MATCH is not set
++CONFIG_FIT_PRINT=y
++# CONFIG_SPL_LOAD_FIT_FULL is not set
++CONFIG_PXE_UTILS=y
++CONFIG_BOOTSTD=y
++# CONFIG_BOOTSTD_FULL is not set
++# CONFIG_BOOTSTD_DEFAULTS is not set
++CONFIG_BOOTSTD_BOOTCOMMAND=y
++CONFIG_BOOTMETH_GLOBAL=y
++# CONFIG_BOOTMETH_CROS is not set
++CONFIG_BOOTMETH_EXTLINUX=y
++CONFIG_BOOTMETH_EXTLINUX_PXE=y
++CONFIG_BOOTMETH_EFILOADER=y
++CONFIG_BOOTMETH_VBE=y
++CONFIG_BOOTMETH_VBE_REQUEST=y
++CONFIG_BOOTMETH_VBE_SIMPLE=y
++CONFIG_BOOTMETH_VBE_SIMPLE_OS=y
++# CONFIG_BOOTMETH_SCRIPT is not set
++CONFIG_LEGACY_IMAGE_FORMAT=y
++# CONFIG_SUPPORT_RAW_INITRD is not set
++# CONFIG_CHROMEOS is not set
++# CONFIG_CHROMEOS_VBOOT is not set
++# CONFIG_RAMBOOT_PBL is not set
++CONFIG_SYS_BOOT_RAMDISK_HIGH=y
++# CONFIG_DISTRO_DEFAULTS is not set
++
++#
++# Boot timing
++#
++# CONFIG_BOOTSTAGE is not set
++CONFIG_BOOTSTAGE_STASH_SIZE=0x1000
++# CONFIG_SHOW_BOOT_PROGRESS is not set
++
++#
++# Boot media
++#
++CONFIG_NAND_BOOT=y
++# CONFIG_ONENAND_BOOT is not set
++# CONFIG_QSPI_BOOT is not set
++# CONFIG_SATA_BOOT is not set
++# CONFIG_SD_BOOT is not set
++# CONFIG_SD_BOOT_QSPI is not set
++CONFIG_SPI_BOOT=y
++
++#
++# Autoboot options
++#
++CONFIG_AUTOBOOT=y
++CONFIG_BOOTDELAY=2
++# CONFIG_AUTOBOOT_KEYED is not set
++# CONFIG_AUTOBOOT_USE_MENUKEY is not set
++CONFIG_AUTOBOOT_MENU_SHOW=y
++# CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE is not set
++# CONFIG_BOOT_RETRY is not set
++
++#
++# Image support
++#
++# CONFIG_IMAGE_PRE_LOAD is not set
++
++#
++# Devicetree fixup
++#
++# CONFIG_OF_BOARD_SETUP is not set
++# CONFIG_OF_SYSTEM_SETUP is not set
++# CONFIG_OF_STDOUT_VIA_ALIAS is not set
++# CONFIG_FDT_FIXUP_PARTITIONS is not set
++# CONFIG_FDT_SIMPLEFB is not set
++CONFIG_ARCH_FIXUP_FDT_MEMORY=y
++# CONFIG_USE_BOOTARGS is not set
++# CONFIG_BOOTARGS_SUBST is not set
++# CONFIG_USE_BOOTCOMMAND is not set
++CONFIG_USE_PREBOOT=y
++CONFIG_DEFAULT_FDT_FILE="openwrt-one"
++# CONFIG_SAVE_PREV_BL_FDT_ADDR is not set
++# CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR is not set
++
++#
++# Configuration editor
++#
++# CONFIG_CEDIT is not set
++
++#
++# Console
++#
++CONFIG_MENU=y
++# CONFIG_CONSOLE_RECORD is not set
++# CONFIG_DISABLE_CONSOLE is not set
++CONFIG_LOGLEVEL=7
++# CONFIG_SILENT_CONSOLE is not set
++# CONFIG_SPL_SILENT_CONSOLE is not set
++# CONFIG_TPL_SILENT_CONSOLE is not set
++# CONFIG_PRE_CONSOLE_BUFFER is not set
++CONFIG_CONSOLE_FLUSH_SUPPORT=y
++# CONFIG_CONSOLE_FLUSH_ON_NEWLINE is not set
++# CONFIG_CONSOLE_MUX is not set
++# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set
++# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set
++# CONFIG_SYS_CONSOLE_INFO_QUIET is not set
++# CONFIG_SYS_STDIO_DEREGISTER is not set
++# CONFIG_SPL_SYS_STDIO_DEREGISTER is not set
++# CONFIG_SYS_DEVICE_NULLDEV is not set
++
++#
++# Logging
++#
++CONFIG_LOG=y
++CONFIG_LOG_MAX_LEVEL=6
++CONFIG_LOG_DEFAULT_LEVEL=6
++CONFIG_LOG_CONSOLE=y
++# CONFIG_LOGF_FILE is not set
++# CONFIG_LOGF_LINE is not set
++# CONFIG_LOGF_FUNC is not set
++CONFIG_LOGF_FUNC_PAD=20
++# CONFIG_LOG_SYSLOG is not set
++# CONFIG_LOG_ERROR_RETURN is not set
++
++#
++# Init options
++#
++# CONFIG_BOARD_TYPES is not set
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DISPLAY_BOARDINFO=y
++# CONFIG_DISPLAY_BOARDINFO_LATE is not set
++
++#
++# Start-up hooks
++#
++# CONFIG_CYCLIC is not set
++CONFIG_EVENT=y
++CONFIG_EVENT_DYNAMIC=y
++# CONFIG_EVENT_DEBUG is not set
++# CONFIG_ARCH_MISC_INIT is not set
++# CONFIG_BOARD_EARLY_INIT_F is not set
++# CONFIG_BOARD_EARLY_INIT_R is not set
++# CONFIG_BOARD_POSTCLK_INIT is not set
++CONFIG_BOARD_LATE_INIT=y
++# CONFIG_CLOCKS is not set
++# CONFIG_HWCONFIG is not set
++CONFIG_LAST_STAGE_INIT=y
++# CONFIG_MISC_INIT_R is not set
++# CONFIG_SYS_MALLOC_BOOTPARAMS is not set
++# CONFIG_ID_EEPROM is not set
++# CONFIG_RESET_PHY_R is not set
++
++#
++# Security support
++#
++CONFIG_HASH=y
++# CONFIG_STACKPROTECTOR is not set
++# CONFIG_BOARD_RNG_SEED is not set
++
++#
++# Update support
++#
++# CONFIG_UPDATE_TFTP is not set
++# CONFIG_ANDROID_AB is not set
++
++#
++# Blob list
++#
++# CONFIG_BLOBLIST is not set
++CONFIG_SUPPORT_SPL=y
++# CONFIG_VPL is not set
++
++#
++# Command line interface
++#
++CONFIG_CMDLINE=y
++CONFIG_HUSH_PARSER=y
++CONFIG_CMDLINE_EDITING=y
++# CONFIG_CMDLINE_PS_SUPPORT is not set
++CONFIG_AUTO_COMPLETE=y
++CONFIG_SYS_LONGHELP=y
++CONFIG_SYS_PROMPT="OpenWrt One> "
++CONFIG_SYS_PROMPT_HUSH_PS2="> "
++CONFIG_SYS_MAXARGS=16
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_SYS_XTRACE=y
++CONFIG_BUILD_BIN2C=y
++
++#
++# Commands
++#
++
++#
++# Info commands
++#
++CONFIG_CMD_BDI=y
++# CONFIG_CMD_BDINFO_EXTRA is not set
++# CONFIG_CMD_CONFIG is not set
++CONFIG_CMD_CONSOLE=y
++CONFIG_CMD_CPU=y
++# CONFIG_CMD_HISTORY is not set
++CONFIG_CMD_LICENSE=y
++# CONFIG_CMD_PMC is not set
++
++#
++# Boot commands
++#
++CONFIG_CMD_BOOTD=y
++CONFIG_CMD_BOOTM=y
++# CONFIG_CMD_BOOTDEV is not set
++CONFIG_CMD_BOOTFLOW=y
++# CONFIG_CMD_BOOTMETH is not set
++CONFIG_BOOTM_EFI=y
++# CONFIG_CMD_BOOTZ is not set
++CONFIG_CMD_BOOTI=y
++CONFIG_BOOTM_LINUX=y
++# CONFIG_BOOTM_NETBSD is not set
++# CONFIG_BOOTM_OPENRTOS is not set
++# CONFIG_BOOTM_OSE is not set
++# CONFIG_BOOTM_PLAN9 is not set
++# CONFIG_BOOTM_RTEMS is not set
++# CONFIG_CMD_VBE is not set
++# CONFIG_BOOTM_VXWORKS is not set
++CONFIG_SYS_BOOTM_LEN=0x4000000
++CONFIG_CMD_BOOTEFI=y
++CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
++# CONFIG_CMD_BOOTEFI_HELLO is not set
++# CONFIG_CMD_BOOTEFI_SELFTEST is not set
++CONFIG_CMD_BOOTMENU=y
++# CONFIG_CMD_ADTIMG is not set
++CONFIG_CMD_ELF=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_GO=y
++CONFIG_CMD_RUN=y
++CONFIG_CMD_IMI=y
++# CONFIG_CMD_IMLS is not set
++CONFIG_CMD_XIMG=y
++# CONFIG_CMD_ZBOOT is not set
++
++#
++# Environment commands
++#
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_EXPORTENV=y
++CONFIG_CMD_IMPORTENV=y
++CONFIG_CMD_EDITENV=y
++# CONFIG_CMD_GREPENV is not set
++CONFIG_CMD_SAVEENV=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_ENV_EXISTS=y
++CONFIG_CMD_ENV_READMEM=y
++# CONFIG_CMD_ENV_CALLBACK is not set
++CONFIG_CMD_ENV_FLAGS=y
++# CONFIG_CMD_NVEDIT_EFI is not set
++# CONFIG_CMD_NVEDIT_INDIRECT is not set
++# CONFIG_CMD_NVEDIT_INFO is not set
++# CONFIG_CMD_NVEDIT_LOAD is not set
++# CONFIG_CMD_NVEDIT_SELECT is not set
++
++#
++# Memory commands
++#
++# CONFIG_CMD_BINOP is not set
++# CONFIG_CMD_BLOBLIST is not set
++CONFIG_CMD_CRC32=y
++# CONFIG_CRC32_VERIFY is not set
++# CONFIG_CMD_EEPROM is not set
++# CONFIG_LOOPW is not set
++# CONFIG_CMD_MD5SUM is not set
++# CONFIG_CMD_MEMINFO is not set
++CONFIG_CMD_MEMORY=y
++# CONFIG_CMD_MEM_SEARCH is not set
++# CONFIG_CMD_MX_CYCLIC is not set
++CONFIG_CMD_RANDOM=y
++# CONFIG_CMD_MEMTEST is not set
++# CONFIG_CMD_SHA1SUM is not set
++CONFIG_CMD_STRINGS=y
++
++#
++# Compression commands
++#
++CONFIG_CMD_LZMADEC=y
++# CONFIG_CMD_UNLZ4 is not set
++# CONFIG_CMD_UNZIP is not set
++# CONFIG_CMD_ZIP is not set
++
++#
++# Device access commands
++#
++# CONFIG_CMD_ARMFLASH is not set
++# CONFIG_CMD_BIND is not set
++# CONFIG_CMD_CLK is not set
++# CONFIG_CMD_DEMO is not set
++# CONFIG_CMD_DFU is not set
++CONFIG_CMD_DM=y
++CONFIG_CMD_FLASH=y
++# CONFIG_CMD_FPGAD is not set
++# CONFIG_CMD_FUSE is not set
++CONFIG_CMD_GPIO=y
++# CONFIG_CMD_GPIO_READ is not set
++CONFIG_CMD_PWM=y
++# CONFIG_CMD_GPT is not set
++# CONFIG_RANDOM_UUID is not set
++# CONFIG_CMD_IDE is not set
++# CONFIG_CMD_IO is not set
++# CONFIG_CMD_IOTRACE is not set
++# CONFIG_CMD_I2C is not set
++CONFIG_CMD_LOADB=y
++# CONFIG_CMD_LOADM is not set
++CONFIG_CMD_LOADS=y
++# CONFIG_LOADS_ECHO is not set
++# CONFIG_CMD_SAVES is not set
++# CONFIG_SYS_LOADS_BAUD_CHANGE is not set
++CONFIG_CMD_LOADXY_TIMEOUT=90
++# CONFIG_CMD_LSBLK is not set
++# CONFIG_CMD_MBR is not set
++# CONFIG_CMD_CLONE is not set
++CONFIG_CMD_MTD=y
++CONFIG_CMD_NAND_EXT=y
++# CONFIG_CMD_ONENAND is not set
++# CONFIG_CMD_OSD is not set
++# CONFIG_CMD_PART is not set
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PINMUX=y
++# CONFIG_CMD_POWEROFF is not set
++# CONFIG_CMD_READ is not set
++# CONFIG_CMD_SATA is not set
++# CONFIG_CMD_SDRAM is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_SF_TEST=y
++# CONFIG_CMD_SPI is not set
++# CONFIG_CMD_TSI148 is not set
++# CONFIG_CMD_UNIVERSE is not set
++CONFIG_CMD_USB=y
++# CONFIG_CMD_USB_SDP is not set
++# CONFIG_CMD_RKMTD is not set
++# CONFIG_CMD_WRITE is not set
++
++#
++# Shell scripting commands
++#
++# CONFIG_CMD_CAT is not set
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_SETEXPR=y
++# CONFIG_CMD_SETEXPR_FMT is not set
++# CONFIG_CMD_XXD is not set
++
++#
++# Android support commands
++#
++CONFIG_CMD_NET=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_DHCP=y
++# CONFIG_BOOTP_MAY_FAIL is not set
++CONFIG_BOOTP_BOOTPATH=y
++# CONFIG_BOOTP_VENDOREX is not set
++# CONFIG_BOOTP_BOOTFILESIZE is not set
++CONFIG_BOOTP_DNS=y
++# CONFIG_BOOTP_DNS2 is not set
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_HOSTNAME=y
++# CONFIG_BOOTP_PREFER_SERVERIP is not set
++CONFIG_BOOTP_SUBNETMASK=y
++# CONFIG_BOOTP_NISDOMAIN is not set
++# CONFIG_BOOTP_NTPSERVER is not set
++# CONFIG_BOOTP_TIMEOFFSET is not set
++# CONFIG_CMD_PCAP is not set
++CONFIG_BOOTP_PXE=y
++CONFIG_BOOTP_PXE_CLIENTARCH=0x16
++# CONFIG_BOOTP_PXE_DHCP_OPTION is not set
++CONFIG_BOOTP_VCI_STRING="U-Boot.armv8"
++CONFIG_CMD_TFTPBOOT=y
++# CONFIG_CMD_TFTPPUT is not set
++CONFIG_CMD_TFTPSRV=y
++CONFIG_NET_TFTP_VARS=y
++CONFIG_CMD_RARP=y
++# CONFIG_CMD_NFS is not set
++# CONFIG_SYS_DISABLE_AUTOLOAD is not set
++# CONFIG_CMD_WGET is not set
++# CONFIG_CMD_MII is not set
++# CONFIG_CMD_MDIO is not set
++CONFIG_CMD_PING=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_ETHSW is not set
++CONFIG_CMD_PXE=y
++# CONFIG_CMD_WOL is not set
++
++#
++# Misc commands
++#
++# CONFIG_CMD_2048 is not set
++# CONFIG_CMD_BSP is not set
++CONFIG_CMD_BLOCK_CACHE=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++# CONFIG_CMD_CONITRACE is not set
++# CONFIG_CMD_CLS is not set
++# CONFIG_CMD_EFIDEBUG is not set
++CONFIG_CMD_EFICONFIG=y
++# CONFIG_CMD_EXCEPTION is not set
++CONFIG_CMD_LED=y
++# CONFIG_CMD_INI is not set
++# CONFIG_CMD_DATE is not set
++# CONFIG_CMD_TIME is not set
++# CONFIG_CMD_GETTIME is not set
++# CONFIG_CMD_PAUSE is not set
++CONFIG_CMD_SLEEP=y
++# CONFIG_CMD_TIMER is not set
++# CONFIG_CMD_SYSBOOT is not set
++# CONFIG_CMD_QFW is not set
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_PSTORE_MEM_SIZE=0x10000
++CONFIG_CMD_PSTORE_RECORD_SIZE=0x1000
++CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x1000
++CONFIG_CMD_PSTORE_FTRACE_SIZE=0x1000
++CONFIG_CMD_PSTORE_PMSG_SIZE=0x1000
++CONFIG_CMD_PSTORE_ECC_SIZE=0
++# CONFIG_CMD_TERMINAL is not set
++CONFIG_CMD_UUID=y
++
++#
++# TI specific command line interface
++#
++
++#
++# Power commands
++#
++
++#
++# Security commands
++#
++# CONFIG_CMD_AES is not set
++# CONFIG_CMD_BLOB is not set
++CONFIG_CMD_HASH=y
++# CONFIG_CMD_HVC is not set
++CONFIG_CMD_SMC=y
++# CONFIG_HASH_VERIFY is not set
++
++#
++# Firmware commands
++#
++
++#
++# Filesystem commands
++#
++# CONFIG_CMD_BTRFS is not set
++# CONFIG_CMD_EROFS is not set
++# CONFIG_CMD_EXT2 is not set
++# CONFIG_CMD_EXT4 is not set
++CONFIG_CMD_FAT=y
++# CONFIG_CMD_SQUASHFS is not set
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++# CONFIG_CMD_JFFS2 is not set
++# CONFIG_CMD_MTDPARTS is not set
++CONFIG_MTDIDS_DEFAULT=""
++CONFIG_MTDPARTS_DEFAULT=""
++# CONFIG_CMD_REISER is not set
++# CONFIG_CMD_ZFS is not set
++
++#
++# Debug commands
++#
++# CONFIG_CMD_DIAG is not set
++# CONFIG_CMD_EVENT is not set
++# CONFIG_CMD_LOG is not set
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITIONS=y
++# CONFIG_MAC_PARTITION is not set
++CONFIG_DOS_PARTITION=y
++# CONFIG_ISO_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++CONFIG_PARTITION_UUIDS=y
++CONFIG_SUPPORT_OF_CONTROL=y
++
++#
++# Device Tree Control
++#
++CONFIG_OF_CONTROL=y
++CONFIG_OF_REAL=y
++# CONFIG_OF_LIVE is not set
++CONFIG_OF_SEPARATE=y
++# CONFIG_OF_EMBED is not set
++# CONFIG_OF_BOARD is not set
++# CONFIG_OF_OMIT_DTB is not set
++CONFIG_DEVICE_TREE_INCLUDES=""
++CONFIG_OF_LIST="openwrt-one"
++# CONFIG_MULTI_DTB_FIT is not set
++CONFIG_OF_TAG_MIGRATE=y
++# CONFIG_OF_DTB_PROPS_REMOVE is not set
++
++#
++# Environment
++#
++CONFIG_ENV_SUPPORT=y
++CONFIG_SAVEENV=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_MIN_ENTRIES=64
++CONFIG_ENV_MAX_ENTRIES=512
++# CONFIG_ENV_IS_NOWHERE is not set
++# CONFIG_ENV_IS_IN_EEPROM is not set
++# CONFIG_ENV_IS_IN_FAT is not set
++# CONFIG_ENV_IS_IN_EXT4 is not set
++# CONFIG_ENV_IS_IN_FLASH is not set
++# CONFIG_ENV_IS_IN_MTD is not set
++# CONFIG_ENV_IS_IN_NAND is not set
++# CONFIG_ENV_IS_IN_NVRAM is not set
++# CONFIG_ENV_IS_IN_ONENAND is not set
++# CONFIG_ENV_IS_IN_REMOTE is not set
++# CONFIG_ENV_IS_IN_SPI_FLASH is not set
++CONFIG_ENV_IS_IN_UBI=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_ENV_UBI_PART="ubi"
++CONFIG_ENV_UBI_VOLUME="ubootenv"
++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
++# CONFIG_ENV_UBI_VOLUME_CREATE is not set
++CONFIG_ENV_UBI_VID_OFFSET=0
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_DEFAULT_ENV_FILE="openwrt-one-spi-nand_env"
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++# CONFIG_ENV_IMPORT_FDT is not set
++# CONFIG_ENV_APPEND is not set
++# CONFIG_ENV_WRITEABLE_LIST is not set
++# CONFIG_ENV_ACCESS_IGNORE_FORCE is not set
++# CONFIG_USE_BOOTFILE is not set
++# CONFIG_USE_ETHPRIME is not set
++# CONFIG_USE_HOSTNAME is not set
++# CONFIG_VERSION_VARIABLE is not set
++CONFIG_NET=y
++CONFIG_ARP_TIMEOUT=5000
++CONFIG_NET_RETRY_COUNT=5
++CONFIG_PROT_UDP=y
++CONFIG_BOOTDEV_ETH=y
++# CONFIG_BOOTP_SEND_HOSTNAME is not set
++CONFIG_NET_RANDOM_ETHADDR=y
++# CONFIG_NETCONSOLE is not set
++# CONFIG_IP_DEFRAG is not set
++# CONFIG_SYS_FAULT_ECHO_LINK_DOWN is not set
++CONFIG_TFTP_BLOCKSIZE=1468
++# CONFIG_TFTP_PORT is not set
++CONFIG_TFTP_WINDOWSIZE=1
++# CONFIG_TFTP_TSIZE is not set
++# CONFIG_SERVERIP_FROM_PROXYDHCP is not set
++CONFIG_SERVERIP_FROM_PROXYDHCP_DELAY_MS=100
++# CONFIG_KEEP_SERVERADDR is not set
++# CONFIG_UDP_CHECKSUM is not set
++# CONFIG_BOOTP_SERVERIP is not set
++CONFIG_BOOTP_MAX_ROOT_PATH_LEN=64
++# CONFIG_USE_GATEWAYIP is not set
++# CONFIG_USE_IPADDR is not set
++# CONFIG_USE_NETMASK is not set
++# CONFIG_USE_ROOTPATH is not set
++# CONFIG_USE_SERVERIP is not set
++# CONFIG_PROT_TCP is not set
++# CONFIG_IPV6 is not set
++CONFIG_SYS_RX_ETH_BUFFER=4
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_DM=y
++# CONFIG_DM_WARN is not set
++# CONFIG_DM_DEBUG is not set
++# CONFIG_DM_STATS is not set
++CONFIG_DM_DEVICE_REMOVE=y
++CONFIG_DM_EVENT=y
++CONFIG_DM_STDIO=y
++CONFIG_DM_SEQ_ALIAS=y
++# CONFIG_DM_DMA is not set
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++# CONFIG_DEVRES is not set
++CONFIG_SIMPLE_BUS=y
++# CONFIG_SIMPLE_BUS_CORRECT_RANGE is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++CONFIG_OF_TRANSLATE=y
++# CONFIG_TRANSLATION_OFFSET is not set
++CONFIG_DM_DEV_READ_INLINE=y
++# CONFIG_OFNODE_MULTI_TREE is not set
++# CONFIG_BOUNCE_BUFFER is not set
++# CONFIG_ADC is not set
++# CONFIG_ADC_EXYNOS is not set
++# CONFIG_ADC_SANDBOX is not set
++# CONFIG_SARADC_MESON is not set
++# CONFIG_SARADC_ROCKCHIP is not set
++# CONFIG_SATA is not set
++# CONFIG_SCSI_AHCI is not set
++
++#
++# SATA/SCSI device support
++#
++# CONFIG_AXI is not set
++
++#
++# Bus devices
++#
++CONFIG_BLK=y
++CONFIG_BLOCK_CACHE=y
++# CONFIG_BLKMAP is not set
++# CONFIG_EFI_MEDIA is not set
++# CONFIG_IDE is not set
++# CONFIG_LBA48 is not set
++# CONFIG_SYS_64BIT_LBA is not set
++# CONFIG_RKMTD is not set
++# CONFIG_BOOTCOUNT_LIMIT is not set
++
++#
++# Button Support
++#
++CONFIG_BUTTON=y
++# CONFIG_BUTTON_ADC is not set
++CONFIG_BUTTON_GPIO=y
++
++#
++# Cache Controller drivers
++#
++# CONFIG_CACHE is not set
++# CONFIG_L2X0_CACHE is not set
++# CONFIG_V5L2_CACHE is not set
++# CONFIG_NCORE_CACHE is not set
++# CONFIG_SIFIVE_CCACHE is not set
++
++#
++# Clock
++#
++CONFIG_CLK=y
++# CONFIG_CLK_CCF is not set
++# CONFIG_CLK_GPIO is not set
++# CONFIG_CLK_CDCE9XX is not set
++# CONFIG_CLK_ICS8N3QV01 is not set
++# CONFIG_CLK_K210 is not set
++# CONFIG_CLK_MPC83XX is not set
++# CONFIG_CLK_XLNX_CLKWZRD is not set
++# CONFIG_CLK_AT91 is not set
++# CONFIG_CLK_RCAR is not set
++# CONFIG_CLK_RCAR_CPG_LIB is not set
++# CONFIG_CLK_SIFIVE is not set
++# CONFIG_CLK_TI_AM3_DPLL is not set
++# CONFIG_CLK_TI_CTRL is not set
++# CONFIG_CLK_TI_GATE is not set
++# CONFIG_CLK_K3 is not set
++CONFIG_CPU=y
++# CONFIG_CPU_IMX is not set
++
++#
++# Hardware crypto devices
++#
++# CONFIG_DM_HASH is not set
++# CONFIG_FSL_CAAM is not set
++CONFIG_CAAM_64BIT=y
++# CONFIG_SYS_FSL_SEC_BE is not set
++# CONFIG_SYS_FSL_SEC_LE is not set
++# CONFIG_NPCM_AES is not set
++# CONFIG_NPCM_SHA is not set
++# CONFIG_DDR_SPD is not set
++# CONFIG_IMX_SNPS_DDR_PHY is not set
++
++#
++# Demo for driver model
++#
++# CONFIG_DM_DEMO is not set
++
++#
++# DFU support
++#
++
++#
++# DMA Support
++#
++# CONFIG_DMA is not set
++# CONFIG_DMA_LPC32XX is not set
++# CONFIG_TI_EDMA3 is not set
++# CONFIG_DMA_LEGACY is not set
++
++#
++# Extcon Support
++#
++# CONFIG_EXTCON is not set
++
++#
++# Fastboot support
++#
++# CONFIG_UDP_FUNCTION_FASTBOOT is not set
++# CONFIG_TCP_FUNCTION_FASTBOOT is not set
++CONFIG_FIRMWARE=y
++CONFIG_ARM_PSCI_FW=y
++# CONFIG_ZYNQMP_FIRMWARE is not set
++# CONFIG_ARM_SMCCC_FEATURES is not set
++# CONFIG_ARM_FFA_TRANSPORT is not set
++# CONFIG_SCMI_FIRMWARE is not set
++# CONFIG_DM_FUZZING_ENGINE is not set
++
++#
++# FPGA support
++#
++# CONFIG_FPGA_ALTERA is not set
++# CONFIG_FPGA_SOCFPGA is not set
++# CONFIG_FPGA_LATTICE is not set
++# CONFIG_FPGA_XILINX is not set
++# CONFIG_DM_FPGA is not set
++# CONFIG_FWU_MDATA is not set
++CONFIG_GPIO=y
++CONFIG_GPIO_HOG=y
++# CONFIG_DM_GPIO_LOOKUP_LABEL is not set
++# CONFIG_ALTERA_PIO is not set
++# CONFIG_BCM2835_GPIO is not set
++# CONFIG_DWAPB_GPIO is not set
++# CONFIG_AT91_GPIO is not set
++# CONFIG_ATMEL_PIO4 is not set
++# CONFIG_ASPEED_GPIO is not set
++# CONFIG_DA8XX_GPIO is not set
++# CONFIG_HIKEY_GPIO is not set
++# CONFIG_INTEL_BROADWELL_GPIO is not set
++# CONFIG_INTEL_GPIO is not set
++# CONFIG_INTEL_ICH6_GPIO is not set
++# CONFIG_IMX_RGPIO2P is not set
++# CONFIG_IPROC_GPIO is not set
++# CONFIG_HSDK_CREG_GPIO is not set
++# CONFIG_KIRKWOOD_GPIO is not set
++# CONFIG_LPC32XX_GPIO is not set
++# CONFIG_MCP230XX_GPIO is not set
++# CONFIG_MSM_GPIO is not set
++# CONFIG_MXC_GPIO is not set
++# CONFIG_MXS_GPIO is not set
++# CONFIG_NPCM_GPIO is not set
++# CONFIG_CMD_PCA953X is not set
++# CONFIG_ROCKCHIP_GPIO is not set
++# CONFIG_XILINX_GPIO is not set
++# CONFIG_TCA642X is not set
++# CONFIG_TEGRA_GPIO is not set
++# CONFIG_TEGRA186_GPIO is not set
++# CONFIG_VYBRID_GPIO is not set
++# CONFIG_SIFIVE_GPIO is not set
++# CONFIG_ZYNQ_GPIO is not set
++# CONFIG_DM_74X164 is not set
++# CONFIG_PCA953X is not set
++# CONFIG_MPC8XXX_GPIO is not set
++# CONFIG_MPC8XX_GPIO is not set
++# CONFIG_NX_GPIO is not set
++# CONFIG_NOMADIK_GPIO is not set
++# CONFIG_ZYNQMP_GPIO_MODEPIN is not set
++# CONFIG_SLG7XL45106_I2C_GPO is not set
++# CONFIG_TURRIS_OMNIA_MCU is not set
++# CONFIG_FTGPIO010 is not set
++
++#
++# Hardware Spinlock Support
++#
++# CONFIG_DM_HWSPINLOCK is not set
++CONFIG_I2C=y
++# CONFIG_DM_I2C is not set
++# CONFIG_SYS_I2C_LEGACY is not set
++# CONFIG_SPL_SYS_I2C_LEGACY is not set
++# CONFIG_SYS_I2C_FSL is not set
++# CONFIG_SYS_I2C_DW is not set
++# CONFIG_SYS_I2C_IMX_LPI2C is not set
++# CONFIG_SYS_I2C_MTK is not set
++# CONFIG_SYS_I2C_MICROCHIP is not set
++# CONFIG_SYS_I2C_MXC is not set
++# CONFIG_SYS_I2C_NPCM is not set
++# CONFIG_SYS_I2C_SOFT is not set
++# CONFIG_SYS_I2C_MV is not set
++# CONFIG_SYS_I2C_MVTWSI is not set
++CONFIG_INPUT=y
++# CONFIG_DM_KEYBOARD is not set
++# CONFIG_CROS_EC_KEYB is not set
++# CONFIG_TEGRA_KEYBOARD is not set
++# CONFIG_TWL4030_INPUT is not set
++
++#
++# IOMMU device drivers
++#
++# CONFIG_IOMMU is not set
++
++#
++# LED Support
++#
++CONFIG_LED=y
++# CONFIG_LED_PWM is not set
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++# CONFIG_LED_STATUS is not set
++
++#
++# Mailbox Controller Support
++#
++# CONFIG_DM_MAILBOX is not set
++
++#
++# Memory Controller drivers
++#
++# CONFIG_MEMORY is not set
++# CONFIG_ATMEL_EBI is not set
++# CONFIG_MFD_ATMEL_SMC is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MISC is not set
++# CONFIG_NVMEM is not set
++# CONFIG_SPL_NVMEM is not set
++# CONFIG_SMSC_LPC47M is not set
++# CONFIG_SMSC_SIO1007 is not set
++# CONFIG_CROS_EC is not set
++# CONFIG_DS4510 is not set
++# CONFIG_FSL_SEC_MON is not set
++# CONFIG_IRQ is not set
++# CONFIG_NPCM_HOST is not set
++# CONFIG_NUVOTON_NCT6102D is not set
++# CONFIG_PWRSEQ is not set
++# CONFIG_PCA9551_LED is not set
++# CONFIG_TEST_DRV is not set
++# CONFIG_USB_HUB_USB251XB is not set
++# CONFIG_TWL4030_LED is not set
++# CONFIG_WINBOND_W83627 is not set
++# CONFIG_FS_LOADER is not set
++
++#
++# MMC Host controller Support
++#
++# CONFIG_MMC is not set
++# CONFIG_MMC_BROKEN_CD is not set
++# CONFIG_DM_MMC is not set
++# CONFIG_FSL_ESDHC is not set
++# CONFIG_FSL_ESDHC_IMX is not set
++
++#
++# MTD Support
++#
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD=y
++CONFIG_DM_MTD=y
++# CONFIG_MTD_NOR_FLASH is not set
++# CONFIG_MTD_CONCAT is not set
++# CONFIG_SYS_MTDPARTS_RUNTIME is not set
++# CONFIG_FLASH_CFI_DRIVER is not set
++# CONFIG_CFI_FLASH is not set
++# CONFIG_ALTERA_QSPI is not set
++# CONFIG_HBMC_AM654 is not set
++# CONFIG_SAMSUNG_ONENAND is not set
++# CONFIG_USE_SYS_MAX_FLASH_BANKS is not set
++CONFIG_MTD_NAND_CORE=y
++# CONFIG_MTD_RAW_NAND is not set
++CONFIG_MTD_SPI_NAND=y
++
++#
++# SPI Flash Support
++#
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH=y
++CONFIG_SF_DEFAULT_BUS=0
++CONFIG_SF_DEFAULT_CS=0
++# CONFIG_BOOTDEV_SPI_FLASH is not set
++CONFIG_SPI_FLASH_SFDP_SUPPORT=y
++CONFIG_SPI_FLASH_SMART_HWCAPS=y
++# CONFIG_SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT is not set
++# CONFIG_SPI_FLASH_SOFT_RESET is not set
++# CONFIG_SPI_FLASH_BAR is not set
++CONFIG_SPI_FLASH_LOCK=y
++CONFIG_SPI_FLASH_UNLOCK_ALL=y
++# CONFIG_SPI_FLASH_ATMEL is not set
++CONFIG_SPI_FLASH_EON=y
++CONFIG_SPI_FLASH_GIGADEVICE=y
++CONFIG_SPI_FLASH_ISSI=y
++CONFIG_SPI_FLASH_MACRONIX=y
++CONFIG_SPI_FLASH_SPANSION=y
++# CONFIG_SPI_FLASH_S28HX_T is not set
++CONFIG_SPI_FLASH_STMICRO=y
++# CONFIG_SPI_FLASH_MT35XU is not set
++# CONFIG_SPI_FLASH_SST is not set
++CONFIG_SPI_FLASH_WINBOND=y
++CONFIG_SPI_FLASH_XMC=y
++CONFIG_SPI_FLASH_XTX=y
++# CONFIG_SPI_FLASH_ZBIT is not set
++CONFIG_SPI_FLASH_USE_4K_SECTORS=y
++# CONFIG_SPI_FLASH_DATAFLASH is not set
++CONFIG_SPI_FLASH_MTD=y
++
++#
++# UBI support
++#
++CONFIG_UBI_SILENCE_MSG=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_MODULE=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++# CONFIG_NVMXIP is not set
++# CONFIG_NVMXIP_QSPI is not set
++# CONFIG_NMBM is not set
++
++#
++# Multiplexer drivers
++#
++# CONFIG_MULTIPLEXER is not set
++# CONFIG_BITBANGMII is not set
++# CONFIG_MV88E6352_SWITCH is not set
++CONFIG_PHYLIB=y
++# CONFIG_PHY_ADDR_ENABLE is not set
++# CONFIG_B53_SWITCH is not set
++# CONFIG_MV88E61XX_SWITCH is not set
++# CONFIG_PHYLIB_10G is not set
++# CONFIG_PHY_ADIN is not set
++# CONFIG_PHY_AIROHA is not set
++# CONFIG_PHY_AQUANTIA is not set
++# CONFIG_PHY_ATHEROS is not set
++# CONFIG_SPL_PHY_ATHEROS is not set
++# CONFIG_PHY_BROADCOM is not set
++# CONFIG_PHY_CORTINA is not set
++# CONFIG_PHY_DAVICOM is not set
++# CONFIG_PHY_ET1011C is not set
++# CONFIG_PHY_LXT is not set
++# CONFIG_PHY_MARVELL is not set
++# CONFIG_PHY_MARVELL_10G is not set
++# CONFIG_PHY_MESON_GXL is not set
++# CONFIG_PHY_MICREL is not set
++# CONFIG_PHY_MOTORCOMM is not set
++# CONFIG_PHY_MSCC is not set
++# CONFIG_PHY_NATSEMI is not set
++# CONFIG_PHY_NXP_C45_TJA11XX is not set
++# CONFIG_PHY_NXP_TJA11XX is not set
++# CONFIG_PHY_REALTEK is not set
++# CONFIG_PHY_SMSC is not set
++# CONFIG_PHY_TERANETICS is not set
++# CONFIG_PHY_TI is not set
++# CONFIG_PHY_TI_DP83867 is not set
++# CONFIG_PHY_TI_DP83869 is not set
++# CONFIG_PHY_TI_GENERIC is not set
++# CONFIG_PHY_VITESSE is not set
++# CONFIG_PHY_XILINX is not set
++# CONFIG_PHY_XILINX_GMII2RGMII is not set
++# CONFIG_PHY_XWAY is not set
++# CONFIG_PHY_ETHERNET_ID is not set
++CONFIG_PHY_FIXED=y
++# CONFIG_PHY_NCSI is not set
++# CONFIG_FSL_MEMAC is not set
++CONFIG_PHY_RESET_DELAY=0
++# CONFIG_FSL_PFE is not set
++CONFIG_ETH=y
++CONFIG_DM_ETH=y
++# CONFIG_DM_MDIO is not set
++# CONFIG_DM_ETH_PHY is not set
++CONFIG_NETDEVICES=y
++# CONFIG_PHY_GIGE is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_BCM_SF2_ETH is not set
++# CONFIG_BCMGENET is not set
++# CONFIG_BNXT_ETH is not set
++# CONFIG_CALXEDA_XGMAC is not set
++# CONFIG_DRIVER_DM9000 is not set
++# CONFIG_DWC_ETH_QOS is not set
++# CONFIG_EEPRO100 is not set
++# CONFIG_ETH_DESIGNWARE is not set
++# CONFIG_ETH_DESIGNWARE_MESON8B is not set
++# CONFIG_ETHOC is not set
++# CONFIG_FMAN_ENET is not set
++# CONFIG_FTMAC100 is not set
++# CONFIG_FTGMAC100 is not set
++# CONFIG_MCFFEC is not set
++# CONFIG_FSLDMAFEC is not set
++# CONFIG_KS8851_MLL is not set
++# CONFIG_LITEETH is not set
++# CONFIG_MACB is not set
++# CONFIG_NET_NPCM750 is not set
++# CONFIG_PCH_GBE is not set
++# CONFIG_RGMII is not set
++# CONFIG_MII is not set
++# CONFIG_RMII is not set
++# CONFIG_PCNET is not set
++# CONFIG_QE_UEC is not set
++# CONFIG_RTL8139 is not set
++# CONFIG_SMC911X is not set
++# CONFIG_SUN7I_GMAC is not set
++# CONFIG_SUN4I_EMAC is not set
++# CONFIG_SUN8I_EMAC is not set
++# CONFIG_SH_ETHER is not set
++# CONFIG_DRIVER_TI_CPSW is not set
++# CONFIG_DRIVER_TI_EMAC is not set
++# CONFIG_DRIVER_TI_KEYSTONE_NET is not set
++# CONFIG_TULIP is not set
++# CONFIG_XILINX_AXIEMAC is not set
++# CONFIG_VSC7385_ENET is not set
++# CONFIG_XILINX_EMACLITE is not set
++# CONFIG_ZYNQ_GEM is not set
++# CONFIG_SYS_DPAA_QBMAN is not set
++# CONFIG_TSEC_ENET is not set
++CONFIG_MEDIATEK_ETH=y
++# CONFIG_HIFEMAC_ETH is not set
++# CONFIG_HIGMACV300_ETH is not set
++# CONFIG_NVME is not set
++# CONFIG_NVME_APPLE is not set
++
++#
++# PCI Endpoint
++#
++# CONFIG_PCI_ENDPOINT is not set
++# CONFIG_X86_PCH7 is not set
++# CONFIG_X86_PCH9 is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_PHY=y
++# CONFIG_NOP_PHY is not set
++# CONFIG_MIPI_DPHY_HELPERS is not set
++# CONFIG_BCM_SR_PCIE_PHY is not set
++# CONFIG_OMAP_USB2_PHY is not set
++CONFIG_PHY_MTK_TPHY=y
++
++#
++# Rockchip PHY driver
++#
++# CONFIG_PHY_CADENCE_SIERRA is not set
++# CONFIG_PHY_CADENCE_TORRENT is not set
++# CONFIG_MSM8916_USB_PHY is not set
++# CONFIG_MVEBU_COMPHY_SUPPORT is not set
++
++#
++# Pin controllers
++#
++CONFIG_PINCTRL=y
++CONFIG_PINCTRL_FULL=y
++CONFIG_PINCTRL_GENERIC=y
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_PINCONF_RECURSIVE=y
++# CONFIG_PINCTRL_AT91 is not set
++# CONFIG_PINCTRL_AT91PIO4 is not set
++# CONFIG_PINCTRL_INTEL is not set
++# CONFIG_PINCTRL_QE is not set
++# CONFIG_PINCTRL_ROCKCHIP_RV1108 is not set
++# CONFIG_PINCTRL_SINGLE is not set
++# CONFIG_PINCTRL_STM32 is not set
++# CONFIG_PINCTRL_STMFX is not set
++# CONFIG_PINCTRL_K210 is not set
++CONFIG_PINCTRL_MTK=y
++# CONFIG_PINCTRL_MT7622 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT7629 is not set
++CONFIG_PINCTRL_MT7981=y
++# CONFIG_PINCTRL_MT7986 is not set
++# CONFIG_PINCTRL_MT7988 is not set
++# CONFIG_PINCTRL_MT8512 is not set
++# CONFIG_PINCTRL_MT8516 is not set
++# CONFIG_PINCTRL_MT8518 is not set
++CONFIG_POWER=y
++# CONFIG_POWER_LEGACY is not set
++# CONFIG_ACPI_PMC is not set
++
++#
++# Power Domain Support
++#
++CONFIG_POWER_DOMAIN=y
++# CONFIG_APPLE_PMGR_POWER_DOMAIN is not set
++CONFIG_MTK_POWER_DOMAIN=y
++# CONFIG_DM_PMIC is not set
++# CONFIG_PMIC_TPS65217 is not set
++# CONFIG_POWER_TPS65218 is not set
++# CONFIG_POWER_TPS62362 is not set
++# CONFIG_DM_REGULATOR is not set
++# CONFIG_TPS6586X_POWER is not set
++# CONFIG_POWER_MT6323 is not set
++CONFIG_DM_PWM=y
++# CONFIG_PWM_ASPEED is not set
++# CONFIG_PWM_CADENCE_TTC is not set
++# CONFIG_PWM_CROS_EC is not set
++# CONFIG_PWM_EXYNOS is not set
++# CONFIG_PWM_IMX is not set
++# CONFIG_PWM_MESON is not set
++CONFIG_PWM_MTK=y
++# CONFIG_PWM_ROCKCHIP is not set
++# CONFIG_PWM_SANDBOX is not set
++# CONFIG_PWM_SIFIVE is not set
++# CONFIG_PWM_TEGRA is not set
++# CONFIG_PWM_SUNXI is not set
++# CONFIG_U_QE is not set
++# CONFIG_RAM is not set
++
++#
++# Reboot Mode Support
++#
++# CONFIG_DM_REBOOT_MODE is not set
++
++#
++# Remote Processor drivers
++#
++
++#
++# Reset Controller Support
++#
++# CONFIG_RESET_AST2500 is not set
++# CONFIG_RESET_AST2600 is not set
++CONFIG_RESET_MEDIATEK=y
++# CONFIG_RESET_HISILICON is not set
++# CONFIG_RESET_SYSCON is not set
++# CONFIG_RESET_SCMI is not set
++# CONFIG_RESET_DRA7 is not set
++# CONFIG_DM_RNG is not set
++
++#
++# Real Time Clock
++#
++# CONFIG_DM_RTC is not set
++# CONFIG_RTC_ENABLE_32KHZ_OUTPUT is not set
++# CONFIG_RTC_DS1337 is not set
++# CONFIG_RTC_DS1338 is not set
++# CONFIG_RTC_DS1374 is not set
++# CONFIG_RTC_DS3231 is not set
++# CONFIG_RTC_PCF8563 is not set
++# CONFIG_RTC_PT7C4338 is not set
++# CONFIG_RTC_PL031 is not set
++# CONFIG_RTC_S35392A is not set
++# CONFIG_RTC_MC13XXX is not set
++# CONFIG_RTC_MC146818 is not set
++# CONFIG_RTC_M41T62 is not set
++# CONFIG_SCSI is not set
++# CONFIG_DM_SCSI is not set
++CONFIG_SERIAL=y
++CONFIG_BAUDRATE=115200
++# CONFIG_DEFAULT_ENV_IS_RW is not set
++CONFIG_REQUIRE_SERIAL_CONSOLE=y
++# CONFIG_SPECIFY_CONSOLE_INDEX is not set
++CONFIG_SERIAL_PRESENT=y
++CONFIG_DM_SERIAL=y
++# CONFIG_SERIAL_RX_BUFFER is not set
++# CONFIG_SERIAL_PUTS is not set
++# CONFIG_SERIAL_SEARCH_ALL is not set
++# CONFIG_SERIAL_PROBE_ALL is not set
++# CONFIG_VPL_DM_SERIAL is not set
++CONFIG_DEBUG_UART_MTK=y
++CONFIG_DEBUG_UART_SHIFT=0
++# CONFIG_DEBUG_UART_ANNOUNCE is not set
++# CONFIG_DEBUG_UART_SKIP_INIT is not set
++# CONFIG_ALTERA_JTAG_UART is not set
++# CONFIG_ALTERA_UART is not set
++# CONFIG_ARC_SERIAL is not set
++# CONFIG_ARM_DCC is not set
++# CONFIG_ATMEL_USART is not set
++# CONFIG_BCM6345_SERIAL is not set
++# CONFIG_COREBOOT_SERIAL is not set
++# CONFIG_CORTINA_UART is not set
++# CONFIG_FSL_LINFLEXUART is not set
++# CONFIG_FSL_LPUART is not set
++# CONFIG_MVEBU_A3700_UART is not set
++# CONFIG_MCFUART is not set
++# CONFIG_NULLDEV_SERIAL is not set
++# CONFIG_SYS_NS16550 is not set
++# CONFIG_PL01X_SERIAL is not set
++# CONFIG_ROCKCHIP_SERIAL is not set
++# CONFIG_XILINX_UARTLITE is not set
++# CONFIG_MSM_SERIAL is not set
++# CONFIG_MSM_GENI_SERIAL is not set
++# CONFIG_MXS_AUART_SERIAL is not set
++# CONFIG_OMAP_SERIAL is not set
++# CONFIG_SIFIVE_SERIAL is not set
++# CONFIG_ZYNQ_SERIAL is not set
++CONFIG_MTK_SERIAL=y
++# CONFIG_MT7620_SERIAL is not set
++# CONFIG_NPCM_SERIAL is not set
++# CONFIG_SM is not set
++# CONFIG_MESON_SM is not set
++# CONFIG_SMEM is not set
++
++#
++# Sound support
++#
++# CONFIG_SOUND is not set
++
++#
++# SOC (System On Chip) specific Drivers
++#
++# CONFIG_SOC_DEVICE is not set
++# CONFIG_SOC_TI is not set
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_SPI_MEM=y
++# CONFIG_SPI_DIRMAP is not set
++# CONFIG_ALTERA_SPI is not set
++# CONFIG_APPLE_SPI is not set
++# CONFIG_ATCSPI200_SPI is not set
++# CONFIG_ATMEL_SPI is not set
++# CONFIG_BCMSTB_SPI is not set
++# CONFIG_CORTINA_SFLASH is not set
++# CONFIG_CADENCE_QSPI is not set
++# CONFIG_CF_SPI is not set
++# CONFIG_DESIGNWARE_SPI is not set
++# CONFIG_EXYNOS_SPI is not set
++# CONFIG_FSL_DSPI is not set
++# CONFIG_FSL_QSPI is not set
++# CONFIG_GXP_SPI is not set
++# CONFIG_ICH_SPI is not set
++# CONFIG_IPROC_QSPI is not set
++# CONFIG_KIRKWOOD_SPI is not set
++# CONFIG_MICROCHIP_COREQSPI is not set
++# CONFIG_MPC8XXX_SPI is not set
++# CONFIG_MTK_SNOR is not set
++# CONFIG_MTK_SNFI_SPI is not set
++CONFIG_MTK_SPIM=y
++# CONFIG_MVEBU_A3700_SPI is not set
++# CONFIG_MXS_SPI is not set
++# CONFIG_SPI_MXIC is not set
++# CONFIG_NPCM_FIU_SPI is not set
++# CONFIG_NPCM_PSPI is not set
++# CONFIG_NXP_FSPI is not set
++# CONFIG_OMAP3_SPI is not set
++# CONFIG_PL022_SPI is not set
++# CONFIG_ROCKCHIP_SFC is not set
++# CONFIG_ROCKCHIP_SPI is not set
++# CONFIG_SPI_ASPEED_SMC is not set
++# CONFIG_SPI_SIFIVE is not set
++# CONFIG_SOFT_SPI is not set
++# CONFIG_SPI_SN_F_OSPI is not set
++# CONFIG_SPI_SUNXI is not set
++# CONFIG_TEGRA114_SPI is not set
++# CONFIG_TEGRA20_SFLASH is not set
++# CONFIG_TEGRA20_SLINK is not set
++# CONFIG_TEGRA210_QSPI is not set
++# CONFIG_TI_QSPI is not set
++# CONFIG_XILINX_SPI is not set
++# CONFIG_ZYNQ_SPI is not set
++# CONFIG_ZYNQ_QSPI is not set
++# CONFIG_ZYNQMP_GQSPI is not set
++# CONFIG_SH_QSPI is not set
++# CONFIG_MXC_SPI is not set
++
++#
++# SPMI support
++#
++# CONFIG_SPMI is not set
++# CONFIG_SYSINFO is not set
++
++#
++# System reset device drivers
++#
++# CONFIG_SYSRESET is not set
++# CONFIG_TEE is not set
++# CONFIG_DM_THERMAL is not set
++
++#
++# Timer Support
++#
++# CONFIG_TIMER is not set
++
++#
++# TPM support
++#
++CONFIG_USB=y
++CONFIG_DM_USB=y
++# CONFIG_DM_USB_GADGET is not set
++
++#
++# USB Host Controller Drivers
++#
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++# CONFIG_USB_XHCI_DWC3 is not set
++# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set
++CONFIG_USB_XHCI_MTK=y
++# CONFIG_USB_XHCI_FSL is not set
++# CONFIG_USB_XHCI_BRCM is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_ISP1760 is not set
++# CONFIG_USB_CDNS3 is not set
++# CONFIG_USB_DWC3 is not set
++# CONFIG_USB_MTU3 is not set
++
++#
++# Legacy MUSB Support
++#
++# CONFIG_USB_MUSB_HCD is not set
++# CONFIG_USB_MUSB_UDC is not set
++
++#
++# MUSB Controller Driver
++#
++# CONFIG_USB_MUSB_HOST is not set
++# CONFIG_USB_MUSB_PIO_ONLY is not set
++
++#
++# USB Phy
++#
++# CONFIG_TWL4030_USB is not set
++# CONFIG_ROCKCHIP_USB2_PHY is not set
++
++#
++# ULPI drivers
++#
++
++#
++# USB peripherals
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_KEYBOARD is not set
++# CONFIG_USB_ONBOARD_HUB is not set
++CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=1000
++# CONFIG_USB_HOST_ETHER is not set
++# CONFIG_USB_GADGET is not set
++# CONFIG_SPL_USB_GADGET is not set
++
++#
++# UFS Host Controller Support
++#
++# CONFIG_TI_J721E_UFS is not set
++
++#
++# Graphics support
++#
++# CONFIG_VIDEO is not set
++
++#
++# VirtIO Drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# 1-Wire support
++#
++# CONFIG_W1 is not set
++
++#
++# 1-wire EEPROM support
++#
++# CONFIG_W1_EEPROM is not set
++
++#
++# Watchdog Timer Support
++#
++# CONFIG_WATCHDOG is not set
++CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
++# CONFIG_IMX_WATCHDOG is not set
++# CONFIG_ULP_WATCHDOG is not set
++# CONFIG_WDT is not set
++# CONFIG_PHYS_TO_BUS is not set
++
++#
++# File systems
++#
++# CONFIG_FS_BTRFS is not set
++# CONFIG_FS_CBFS is not set
++# CONFIG_FS_EXT4 is not set
++CONFIG_FS_FAT=y
++CONFIG_FAT_WRITE=y
++CONFIG_FS_FAT_MAX_CLUSTSIZE=65536
++# CONFIG_FS_JFFS2 is not set
++CONFIG_UBIFS_SILENCE_MSG=y
++CONFIG_UBIFS_SILENCE_DEBUG_DUMP=y
++# CONFIG_FS_CRAMFS is not set
++# CONFIG_YAFFS2 is not set
++# CONFIG_FS_SQUASHFS is not set
++# CONFIG_FS_EROFS is not set
++
++#
++# Library routines
++#
++# CONFIG_ADDR_MAP is not set
++# CONFIG_SYS_TIMER_COUNTS_DOWN is not set
++# CONFIG_PHYSMEM is not set
++# CONFIG_BCH is not set
++# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
++CONFIG_CHARSET=y
++# CONFIG_DYNAMIC_CRC_TABLE is not set
++CONFIG_LIB_UUID=y
++# CONFIG_SEMIHOSTING is not set
++CONFIG_PRINTF=y
++CONFIG_SPRINTF=y
++CONFIG_STRTO=y
++CONFIG_SYS_HZ=1000
++# CONFIG_PANIC_HANG is not set
++CONFIG_REGEX=y
++CONFIG_LIB_RAND=y
++# CONFIG_LIB_HW_RAND is not set
++CONFIG_SUPPORT_ACPI=y
++# CONFIG_ACPI is not set
++CONFIG_RBTREE=y
++# CONFIG_BITREVERSE is not set
++# CONFIG_TRACE is not set
++# CONFIG_CIRCBUF is not set
++# CONFIG_CMD_DHRYSTONE is not set
++
++#
++# Security support
++#
++# CONFIG_AES is not set
++# CONFIG_ECDSA is not set
++# CONFIG_RSA is not set
++# CONFIG_TPM is not set
++
++#
++# Android Verified Boot
++#
++
++#
++# Hashing Support
++#
++# CONFIG_BLAKE2 is not set
++CONFIG_SHA1=y
++CONFIG_SHA256=y
++# CONFIG_SHA512 is not set
++# CONFIG_SHA384 is not set
++# CONFIG_SHA_HW_ACCEL is not set
++CONFIG_MD5=y
++CONFIG_CRC8=y
++CONFIG_CRC32=y
++
++#
++# Compression Support
++#
++# CONFIG_LZ4 is not set
++CONFIG_LZMA=y
++CONFIG_LZO=y
++CONFIG_GZIP=y
++# CONFIG_ZLIB_UNCOMPRESS is not set
++# CONFIG_BZIP2 is not set
++CONFIG_ZLIB=y
++# CONFIG_ZSTD is not set
++CONFIG_VPL_LZMA=y
++# CONFIG_SPL_GZIP is not set
++# CONFIG_ERRNO_STR is not set
++CONFIG_HEXDUMP=y
++# CONFIG_GETOPT is not set
++CONFIG_OF_LIBFDT=y
++CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
++CONFIG_SYS_FDT_PAD=0x3000
++
++#
++# System tables
++#
++CONFIG_GENERATE_SMBIOS_TABLE=y
++# CONFIG_LIB_RATIONAL is not set
++CONFIG_SMBIOS=y
++# CONFIG_SMBIOS_PARSER is not set
++CONFIG_EFI_LOADER=y
++CONFIG_CMD_BOOTEFI_BOOTMGR=y
++CONFIG_EFI_VARIABLE_FILE_STORE=y
++# CONFIG_EFI_VARIABLE_NO_STORE is not set
++# CONFIG_EFI_VARIABLES_PRESEED is not set
++CONFIG_EFI_VAR_BUF_SIZE=131072
++# CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN is not set
++# CONFIG_EFI_RUNTIME_UPDATE_CAPSULE is not set
++CONFIG_EFI_CAPSULE_MAX=15
++CONFIG_EFI_DEVICE_PATH_TO_TEXT=y
++CONFIG_EFI_DEVICE_PATH_UTIL=y
++CONFIG_EFI_DT_FIXUP=y
++CONFIG_EFI_LOADER_HII=y
++CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y
++CONFIG_EFI_UNICODE_CAPITALIZATION=y
++# CONFIG_EFI_LOADER_BOUNCE_BUFFER is not set
++CONFIG_EFI_PLATFORM_LANG_CODES="en-US"
++CONFIG_EFI_HAVE_RUNTIME_RESET=y
++CONFIG_EFI_LOAD_FILE2_INITRD=y
++CONFIG_EFI_ECPT=y
++CONFIG_EFI_EBBR_2_1_CONFORMANCE=y
++# CONFIG_OPTEE_LIB is not set
++# CONFIG_OPTEE_IMAGE is not set
++# CONFIG_BOOTM_OPTEE is not set
++# CONFIG_TEST_FDTDEC is not set
++CONFIG_LIB_ELF=y
++CONFIG_LMB=y
++CONFIG_LMB_USE_MAX_REGIONS=y
++CONFIG_LMB_MAX_REGIONS=64
++# CONFIG_PHANDLE_CHECK_SEQ is not set
++
++#
++# Testing
++#
++# CONFIG_UNIT_TEST is not set
++# CONFIG_POST is not set
++
++#
++# Tools options
++#
++CONFIG_MKIMAGE_DTC_PATH="dtc"
++CONFIG_TOOLS_CRC32=y
++CONFIG_TOOLS_LIBCRYPTO=y
++CONFIG_TOOLS_FIT=y
++CONFIG_TOOLS_FIT_FULL_CHECK=y
++CONFIG_TOOLS_FIT_PRINT=y
++CONFIG_TOOLS_FIT_RSASSA_PSS=y
++CONFIG_TOOLS_FIT_SIGNATURE=y
++CONFIG_TOOLS_FIT_SIGNATURE_MAX_SIZE=0x10000000
++CONFIG_TOOLS_FIT_VERBOSE=y
++CONFIG_TOOLS_MD5=y
++CONFIG_TOOLS_OF_LIBFDT=y
++CONFIG_TOOLS_SHA1=y
++CONFIG_TOOLS_SHA256=y
++CONFIG_TOOLS_SHA384=y
++CONFIG_TOOLS_SHA512=y
++# CONFIG_TOOLS_MKEFICAPSULE is not set
++# CONFIG_FSPI_CONF_HEADER is not set
++# CONFIG_TOOLS_MKFWUMDATA is not set
+--- /dev/null
++++ b/openwrt-one-nor_env
+@@ -0,0 +1,46 @@
++bl2_mtd_write=mtd erase bl2-nor && mtd write bl2-nor $loadaddr 0x0 0x40000
++bl2_tftp_write=tftpboot $loadaddr $bootfile_bl2_nor && run bl2_mtd_write
++bootcmd=run check_button ; run led_start ; mtd read recovery ${loadaddr} ; bootm ; run led_loop_error
++bootconf=config-1
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-openwrt_one-initramfs.itb
++bootfile_bl2_nor=openwrt-mediatek-filogic-openwrt_one-nor-preloader.bin
++bootfile_fip_nor=openwrt-mediatek-filogic-openwrt_one-nor-bl31-uboot.fip
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run bootcmd
++bootmenu_1=Boot system via TFTP.=run tftp_boot ; run bootmenu_confirm_return
++bootmenu_2=\e[31mUnlock NOR. (Make sure the NOR/WP jumper is populated)\e[0m=sf probe 1:0 && sf protect unlock 0x0 0x1000000 ; run bootmenu_confirm_return
++bootmenu_3=\e[31mLoad BL31+U-Boot FIP via TFTP then write to NOR.\e[0m=run fip_tftp_write ; run bootmenu_confirm_return
++bootmenu_4=\e[31mLoad BL2 preloader via TFTP then write to NOR.\e[0m=run bl2_tftp_write ; run bootmenu_confirm_return
++bootmenu_5=\e[31mLoad recovery system via TFTP then write to NOR.\e[0m=run tftp_write ; run bootmenu_confirm_return
++bootmenu_6=\e[31mLock NOR. (Remove jumper afterwards)\e[0m=sf probe 1:0 && sf protect lock 0x0 0x1000000 ; run bootmenu_confirm_return
++bootmenu_7=Reboot.=reset
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title= \e[0;34m( ( ( \e[1;39mOpenWrt\e[0;34m ) ) ) \e[0;36m[SPI-NOR]\e[0m
++check_button=if button front ; then run usb_recovery ; run led_loop_error ; fi
++fip_mtd_write=mtd erase fip-nor && mtd write fip-nor $loadaddr
++fip_tftp_write=tftpboot $loadaddr $bootfile_fip_nor && run fip_mtd_write
++ipaddr=192.168.11.11
++led_done=led green off ; led white on
++led_loop_done=led white off ; led green on ; echo done ; while true ; do sleep 1 ; done
++led_loop_error=led white off ; led green off ; while true ; do led red on ; sleep 1 ; led red off ; sleep 1 ; done
++led_boot=led green on ; led white on ; led red on
++led_start=led green off ; led red off; led white on
++loadaddr=0x46000000
++preboot=run led_boot
++recoverfile_bl2=openwrt-mediatek-filogic-openwrt_one-snand-preloader.bin
++recoverfile_ubi=openwrt-mediatek-filogic-openwrt_one-factory.ubi
++recovery_write_bl2=mtd erase bl2 && for offset in 0x0 0x40000 0x80000; do mtd write bl2 $loadaddr $offset 0x40000 ; done
++recovery_write_ubi=mtd erase ubi && mtd write ubi $loadaddr 0 ${filesize}
++serverip=192.168.11.23
++tftp_boot=run led_start ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++tftp_write=run led_start ; tftpboot $loadaddr $bootfile && mtd erase recovery 0x0 ${filesize} && mtd write recovery $loadaddr 0x0 ${filesize}
++usb_recovery=run led_start ; usb start && run usb_recovery_bl2 && run usb_recovery_ubi && run led_loop_done
++usb_recovery_bl2=fatload usb 0:1 ${loadaddr} ${recoverfile_bl2} && run recovery_write_bl2
++usb_recovery_ubi=fatload usb 0:1 ${loadaddr} ${recoverfile_ubi} && run recovery_write_ubi
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title \e[33m$ver\e[0m"
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; bootmenu
++_init_env=setenv _init_env ; echo Initialize Env ; run ubi_create_env ; saveenv
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
+--- /dev/null
++++ b/openwrt-one-spi-nand_env
+@@ -0,0 +1,59 @@
++ipaddr=192.168.11.11
++serverip=192.168.11.23
++loadaddr=0x46000000
++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
++bootcmd=run check_buttons ; run led_start ; run boot_calibration ; run boot_production ; run boot_recovery
++bootconf=config-1
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-openwrt_one-initramfs.itb
++bootfile_bl2=openwrt-mediatek-filogic-openwrt_one-snand-preloader.bin
++bootfile_fip=openwrt-mediatek-filogic-openwrt_one-snand-bl31-uboot.fip
++bootfile_upg=openwrt-mediatek-filogic-openwrt_one-squashfs-sysupgrade.itb
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; run led_boot ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title= \e[0;34m( ( ( \e[1;39mOpenWrt\e[0;34m ) ) ) \e[0;36m[SPI-NAND]\e[0m
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to NAND.=noboot=1 ; replacevol=1 ; run boot_tftp_production ; noboot= ; replacevol= ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to NAND.=noboot=1 ; replacevol=1 ; run boot_tftp_recovery ; noboot= ; replacevol= ; run bootmenu_confirm_return
++bootmenu_6=\e[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.\e[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_7=\e[31mLoad BL2 preloader via TFTP then write to NAND.\e[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_8=Reboot.=reset
++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_default=run bootcmd ; run boot_recovery ; replacevol=1 ; run boot_tftp_forever
++boot_calibration=ubi read $loadaddr calibration && bootm $loadaddr#$bootconf
++boot_production=led white on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led white off
++boot_recovery=led green on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led green off
++boot_tftp=run led_start ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++boot_tftp_forever=led green off ; led white off ; led red on ; while true ; do run boot_tftp_recovery ; led red off ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && test $replacevol = 1 && iminfo $loadaddr && run ubi_write_production ; if test $noboot = 1 ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && test $replacevol = 1 && iminfo $loadaddr && run ubi_write_recovery ; if test $noboot = 1 ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++check_buttons=if button front ; then run boot_recovery ; run boot_tftp ; run led_loop_error ; else if button back ; then ; run usb_recover ; run led_loop_error ; fi ; fi
++led_boot=led green on ; led white on ; led red on
++led_done=led green on ; led white off ; led red off
++led_loop_error=led white off ; led green off ; while true ; do led red on ; sleep 1 ; led red off ; sleep 1 ; done
++led_start=led white on ; led green off ; led red off
++preboot=run led_boot
++reset_factory=mw $loadaddr 0xff 0x1f000 ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data
++snand_write_bl2=mtd erase bl2 && for offset in 0x0 0x40000 0x80000 0xc0000 ; do mtd write bl2 $loadaddr $offset 0x40000 ; done
++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x1f000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x1f000 dynamic
++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++usb_recover=run led_start ; usb start && run usb_recover_production && run led_loop_done
++usb_recover_production=fatload usb 0:1 ${loadaddr} ${bootfile_upg} && iminfo $loadaddr && run ubi_write_production
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip $filesize static && ubi write $loadaddr fip $filesize
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; bootmenu
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title \e[33m$ver\e[0m"
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
-PKG_VERSION:=2023.07.02
+PKG_VERSION:=2024.04
PKG_RELEASE:=1
-PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
+PKG_HASH:=18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
+++ /dev/null
-From 8621f6d22a9589651c6f25742294dd19a26db430 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Thu, 3 Aug 2023 13:34:13 +0200
-Subject: [PATCH 1/3] arm: mvebu: Espressobin: move FDT fixup into a separate
- function
-
-Currently, Esspresobin FDT is being fixed up directly in ft_board_setup()
-which makes it hard to add support for any other board to be fixed up.
-
-So, lets just move the FDT fixup code to a separate function and call it
-if compatible matches, there should be no functional change.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- board/Marvell/mvebu_armada-37xx/board.c | 14 +++++++++-----
- 1 file changed, 9 insertions(+), 5 deletions(-)
-
---- a/board/Marvell/mvebu_armada-37xx/board.c
-+++ b/board/Marvell/mvebu_armada-37xx/board.c
-@@ -359,18 +359,14 @@ int last_stage_init(void)
- #endif
-
- #ifdef CONFIG_OF_BOARD_SETUP
--int ft_board_setup(void *blob, struct bd_info *bd)
-+static int espressobin_fdt_setup(void *blob)
- {
--#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
- int ret;
- int spi_off;
- int parts_off;
- int part_off;
-
- /* Fill SPI MTD partitions for Linux kernel on Espressobin */
-- if (!of_machine_is_compatible("globalscale,espressobin"))
-- return 0;
--
- spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
- if (spi_off < 0)
- return 0;
-@@ -455,6 +451,14 @@ int ft_board_setup(void *blob, struct bd
- return 0;
- }
-
-+ return 0;
-+}
-+
-+int ft_board_setup(void *blob, struct bd_info *bd)
-+{
-+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-+ if (of_machine_is_compatible("globalscale,espressobin"))
-+ return espressobin_fdt_setup(blob);
- #endif
- return 0;
- }
--- /dev/null
+From ca4ecdce4cdcfab7df101b5df6ddad43d2f549e1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
+Date: Thu, 4 Apr 2024 09:50:50 +0200
+Subject: [PATCH] arm: mvebu: turris_omnia: Enable LTO by default on Turris
+ Omnia
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+U-Boot builds for Turris Omnia are approaching the limit of 0xf0000
+bytes, which is the size of the U-Boot partition on Omnia.
+
+Enable LTO to get more size optimized binaries.
+
+Signed-off-by: Marek Behún <kabel@kernel.org>
+Reviewed-by: Stefan Roese <sr@denx.de>
+---
+ configs/turris_omnia_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/configs/turris_omnia_defconfig
++++ b/configs/turris_omnia_defconfig
+@@ -31,6 +31,7 @@ CONFIG_AHCI=y
+ CONFIG_OF_BOARD_FIXUP=y
+ CONFIG_SYS_MEMTEST_START=0x00800000
+ CONFIG_SYS_MEMTEST_END=0x00ffffff
++CONFIG_LTO=y
+ CONFIG_HAS_BOARD_SIZE_LIMIT=y
+ CONFIG_BOARD_SIZE_LIMIT=983040
+ CONFIG_FIT=y
+++ /dev/null
-From 3f8c18894a50fd45b81a807f217893f289500bc6 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Thu, 3 Aug 2023 14:24:31 +0200
-Subject: [PATCH 2/3] arm: mvebu: Espressobin: move network setup into a
- separate function
-
-Currently, Esspresobin switch is being setup directly in last_stage_init()
-which makes it hard to add support for any other board to be setup.
-
-So, lets just move the switch setup code to a separate function and call it
-if compatible matches, there should be no functional change.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- board/Marvell/mvebu_armada-37xx/board.c | 16 +++++++++++-----
- 1 file changed, 11 insertions(+), 5 deletions(-)
-
---- a/board/Marvell/mvebu_armada-37xx/board.c
-+++ b/board/Marvell/mvebu_armada-37xx/board.c
-@@ -300,15 +300,11 @@ static int mii_multi_chip_mode_write(str
- return 0;
- }
-
--/* Bring-up board-specific network stuff */
--int last_stage_init(void)
-+static int espressobin_last_stage_init(void)
- {
- struct udevice *bus;
- ofnode node;
-
-- if (!of_machine_is_compatible("globalscale,espressobin"))
-- return 0;
--
- node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
- if (!ofnode_valid(node) ||
- uclass_get_device_by_ofnode(UCLASS_MDIO, node, &bus) ||
-@@ -356,6 +352,16 @@ int last_stage_init(void)
-
- return 0;
- }
-+
-+/* Bring-up board-specific network stuff */
-+int last_stage_init(void)
-+{
-+
-+ if (of_machine_is_compatible("globalscale,espressobin"))
-+ return espressobin_last_stage_init();
-+
-+ return 0;
-+}
- #endif
-
- #ifdef CONFIG_OF_BOARD_SETUP
+++ /dev/null
-From 83c00ee665b8dde813458b2b07cf97ce8409248d Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Fri, 4 Aug 2023 22:39:06 +0200
-Subject: [PATCH 3/3] arm: mvebu: eDPU: support new board revision
-
-There is a new eDPU revision that uses Marvell 88E6361 switch onboard.
-We can rely on detecting the switch to enable and fixup the Linux DTS
-so a single DTS can be used.
-
-There is currently no support for the 88E6361 switch and thus no working
-networking in U-Boot, so we disable both ports.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- arch/arm/dts/armada-3720-eDPU-u-boot.dtsi | 13 ++-
- arch/arm/dts/armada-3720-eDPU.dts | 47 ++++++++
- board/Marvell/mvebu_armada-37xx/board.c | 125 ++++++++++++++++++++++
- configs/eDPU_defconfig | 2 +
- 4 files changed, 182 insertions(+), 5 deletions(-)
-
---- a/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
-+++ b/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
-@@ -32,14 +32,17 @@
- bootph-all;
- };
-
--ð0 {
-- /* G.hn does not work without additional configuration */
-- status = "disabled";
--};
--
- ð1 {
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-+
-+/*
-+ * eDPU v2 has a MV88E6361 switch on the MDIO bus and U-boot is used
-+ * to patch the Linux DTS if its found so enable MDIO by default.
-+ */
-+&mdio {
-+ status = "okay";
-+};
---- a/arch/arm/dts/armada-3720-eDPU.dts
-+++ b/arch/arm/dts/armada-3720-eDPU.dts
-@@ -12,3 +12,50 @@
- ð0 {
- phy-mode = "2500base-x";
- };
-+
-+/*
-+ * External MV88E6361 switch is only available on v2 of the board.
-+ * U-Boot will enable the MDIO bus and switch nodes.
-+ */
-+&mdio {
-+ status = "disabled";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&smi_pins>;
-+
-+ /* Actual device is MV88E6361 */
-+ switch: switch@0 {
-+ compatible = "marvell,mv88e6190";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0>;
-+ status = "disabled";
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ port@0 {
-+ reg = <0>;
-+ label = "cpu";
-+ phy-mode = "2500base-x";
-+ managed = "in-band-status";
-+ ethernet = <ð0>;
-+ };
-+
-+ port@9 {
-+ reg = <9>;
-+ label = "downlink";
-+ phy-mode = "2500base-x";
-+ managed = "in-band-status";
-+ };
-+
-+ port@a {
-+ reg = <10>;
-+ label = "uplink";
-+ phy-mode = "2500base-x";
-+ managed = "in-band-status";
-+ sfp = <&sfp_eth1>;
-+ };
-+ };
-+ };
-+};
---- a/board/Marvell/mvebu_armada-37xx/board.c
-+++ b/board/Marvell/mvebu_armada-37xx/board.c
-@@ -13,6 +13,7 @@
- #include <mmc.h>
- #include <miiphy.h>
- #include <phy.h>
-+#include <fdt_support.h>
- #include <asm/global_data.h>
- #include <asm/io.h>
- #include <asm/arch/cpu.h>
-@@ -49,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
- /* Single-chip mode */
- /* Switch Port Registers */
- #define MVEBU_SW_LINK_CTRL_REG (1)
-+#define MVEBU_SW_PORT_SWITCH_ID (3)
- #define MVEBU_SW_PORT_CTRL_REG (4)
- #define MVEBU_SW_PORT_BASE_VLAN (6)
-
-@@ -56,6 +58,8 @@ DECLARE_GLOBAL_DATA_PTR;
- #define MVEBU_G2_SMI_PHY_CMD_REG (24)
- #define MVEBU_G2_SMI_PHY_DATA_REG (25)
-
-+#define SWITCH_88E6361_PRODUCT_NUMBER 0x2610
-+
- /*
- * Memory Controller Registers
- *
-@@ -72,6 +76,27 @@ DECLARE_GLOBAL_DATA_PTR;
- #define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
- #define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
-
-+static bool is_edpu_plus(void)
-+{
-+ struct udevice *bus;
-+ ofnode node;
-+ int val;
-+
-+ node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
-+ if (!ofnode_valid(node) ||
-+ uclass_get_device_by_ofnode(UCLASS_MDIO, node, &bus) ||
-+ device_probe(bus)) {
-+ printf("Cannot find MDIO bus\n");
-+ return -ENODEV;
-+ }
-+
-+ val = dm_mdio_read(bus, 0x0, MDIO_DEVAD_NONE, MVEBU_SW_PORT_SWITCH_ID);
-+ if (val == SWITCH_88E6361_PRODUCT_NUMBER)
-+ return true;
-+ else
-+ return false;
-+}
-+
- int board_early_init_f(void)
- {
- return 0;
-@@ -353,6 +378,41 @@ static int espressobin_last_stage_init(v
- return 0;
- }
-
-+static int edpu_plus_last_stage_init(void)
-+{
-+ struct udevice *dev;
-+ int ret;
-+
-+ if (is_edpu_plus()) {
-+ ret = uclass_get_device_by_name(UCLASS_ETH,
-+ "ethernet@40000",
-+ &dev);
-+ if (!ret) {
-+ device_remove(dev, DM_REMOVE_NORMAL);
-+ device_unbind(dev);
-+ }
-+
-+ /* Currently no networking support on the eDPU+ board */
-+ ret = uclass_get_device_by_name(UCLASS_ETH,
-+ "ethernet@30000",
-+ &dev);
-+ if (!ret) {
-+ device_remove(dev, DM_REMOVE_NORMAL);
-+ device_unbind(dev);
-+ }
-+ } else {
-+ ret = uclass_get_device_by_name(UCLASS_ETH,
-+ "ethernet@30000",
-+ &dev);
-+ if (!ret) {
-+ device_remove(dev, DM_REMOVE_NORMAL);
-+ device_unbind(dev);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
- /* Bring-up board-specific network stuff */
- int last_stage_init(void)
- {
-@@ -360,6 +420,9 @@ int last_stage_init(void)
- if (of_machine_is_compatible("globalscale,espressobin"))
- return espressobin_last_stage_init();
-
-+ if (of_machine_is_compatible("methode,edpu"))
-+ return edpu_plus_last_stage_init();
-+
- return 0;
- }
- #endif
-@@ -460,12 +523,74 @@ static int espressobin_fdt_setup(void *b
- return 0;
- }
-
-+static int edpu_plus_fdt_setup(void *blob)
-+{
-+ const char *ports[] = { "downlink", "uplink" };
-+ uint8_t mac[ETH_ALEN];
-+ const char *path;
-+ int i, ret;
-+
-+ if (is_edpu_plus()) {
-+ ret = fdt_set_status_by_compatible(blob,
-+ "marvell,orion-mdio",
-+ FDT_STATUS_OKAY);
-+ if (ret)
-+ printf("Failed to enable MDIO!\n");
-+
-+ ret = fdt_set_status_by_alias(blob,
-+ "ethernet1",
-+ FDT_STATUS_DISABLED);
-+ if (ret)
-+ printf("Failed to disable ethernet1!\n");
-+
-+ path = fdt_get_alias(blob, "ethernet0");
-+ if (path)
-+ do_fixup_by_path_string(blob, path, "phy-mode", "2500base-x");
-+ else
-+ printf("Failed to update ethernet0 phy-mode to 2500base-x!\n");
-+
-+ ret = fdt_set_status_by_compatible(blob,
-+ "marvell,mv88e6190",
-+ FDT_STATUS_OKAY);
-+ if (ret)
-+ printf("Failed to enable MV88E6361!\n");
-+
-+ /*
-+ * MAC-s for Uplink and Downlink ports are stored under
-+ * non standard variable names, so lets manually fixup the
-+ * switch port nodes to have the desired MAC-s.
-+ */
-+ for (i = 0; i < 2; i++) {
-+ if (eth_env_get_enetaddr(ports[i], mac)) {
-+ do_fixup_by_prop(blob,
-+ "label",
-+ ports[i],
-+ strlen(ports[i]) + 1,
-+ "mac-address",
-+ mac, ARP_HLEN, 1);
-+
-+ do_fixup_by_prop(blob,
-+ "label",
-+ ports[i],
-+ strlen(ports[i]) + 1,
-+ "local-mac-address",
-+ mac, ARP_HLEN, 1);
-+ }
-+ }
-+ }
-+
-+ return 0;
-+}
-+
- int ft_board_setup(void *blob, struct bd_info *bd)
- {
- #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
- if (of_machine_is_compatible("globalscale,espressobin"))
- return espressobin_fdt_setup(blob);
- #endif
-+ if (of_machine_is_compatible("methode,edpu"))
-+ return edpu_plus_fdt_setup(blob);
-+
- return 0;
- }
- #endif
---- a/configs/eDPU_defconfig
-+++ b/configs/eDPU_defconfig
-@@ -17,12 +17,14 @@ CONFIG_DEBUG_UART=y
- # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
- CONFIG_FIT=y
- CONFIG_FIT_VERBOSE=y
-+CONFIG_OF_BOARD_SETUP=y
- CONFIG_DISTRO_DEFAULTS=y
- CONFIG_USE_PREBOOT=y
- # CONFIG_DISPLAY_CPUINFO is not set
- # CONFIG_DISPLAY_BOARDINFO is not set
- CONFIG_DISPLAY_BOARDINFO_LATE=y
- CONFIG_BOARD_EARLY_INIT_F=y
-+CONFIG_LAST_STAGE_INIT=y
- CONFIG_SYS_MAXARGS=32
- CONFIG_SYS_PBSIZE=1048
- # CONFIG_CMD_ELF is not set
+++ /dev/null
-From 1dbc6d3739869af38e6157cd8b9bc4314ca3c9fe Mon Sep 17 00:00:00 2001
-From: Josua Mayer <josua@solid-run.com>
-Date: Mon, 18 Jul 2022 20:04:54 +0300
-Subject: [PATCH 1/2] arm: mvebu: clearfog: read number of ddr channels from
- tlv data
-
-Extend the existing tlv vendor extension used for ram size by one byte to
-also store the number of ddr channels.
-The length of the tlv entry can indicate whether the new information is
-present. If not default to single channel.
-
-Signed-off-by: Josua Mayer <josua@solid-run.com>
----
- board/solidrun/clearfog/clearfog.c | 14 +++++++++++++-
- board/solidrun/common/tlv_data.c | 7 ++++++-
- board/solidrun/common/tlv_data.h | 1 +
- 3 files changed, 20 insertions(+), 2 deletions(-)
-
-diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
-index 6edb4221551..4f4532b537e 100644
---- a/board/solidrun/clearfog/clearfog.c
-+++ b/board/solidrun/clearfog/clearfog.c
-@@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR;
- #define BOARD_GPP_POL_LOW 0x0
- #define BOARD_GPP_POL_MID 0x0
-
--static struct tlv_data cf_tlv_data;
-+static struct tlv_data cf_tlv_data = { 0 };
-
- static void cf_read_tlv_data(void)
- {
-@@ -168,6 +168,18 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
- break;
- }
-
-+ switch (cf_tlv_data.ram_channels) {
-+ default:
-+ case 1:
-+ for (uint8_t i = 0; i < 5; i++)
-+ ifp->as_bus_params[i].cs_bitmask = 0x1;
-+ break;
-+ case 2:
-+ for (uint8_t i = 0; i < 5; i++)
-+ ifp->as_bus_params[i].cs_bitmask = 0x3;
-+ break;
-+ }
-+
- /* Return the board topology as defined in the board code */
- return &board_topology_map;
- }
-diff --git a/board/solidrun/common/tlv_data.c b/board/solidrun/common/tlv_data.c
-index 11d6e4a1380..cf5824886c3 100644
---- a/board/solidrun/common/tlv_data.c
-+++ b/board/solidrun/common/tlv_data.c
-@@ -45,9 +45,14 @@ static void parse_tlv_vendor_ext(struct tlvinfo_tlv *tlv_entry,
-
- if (val[4] != SR_TLV_CODE_RAM_SIZE)
- return;
-- if (tlv_entry->length != 6)
-+ if (tlv_entry->length < 6)
- return;
- td->ram_size = val[5];
-+
-+ /* extension with additional data field for number of ddr channels */
-+ if (tlv_entry->length >= 7) {
-+ td->ram_channels = val[6];
-+ }
- }
-
- static void parse_tlv_data(u8 *eeprom, struct tlvinfo_header *hdr,
-diff --git a/board/solidrun/common/tlv_data.h b/board/solidrun/common/tlv_data.h
-index a1432e4b8e1..be3f782ac4a 100644
---- a/board/solidrun/common/tlv_data.h
-+++ b/board/solidrun/common/tlv_data.h
-@@ -10,6 +10,7 @@ struct tlv_data {
- /* Store product name of both SOM and carrier */
- char tlv_product_name[2][32];
- unsigned int ram_size;
-+ uint8_t ram_channels;
- };
-
- void read_tlv_data(struct tlv_data *td);
---
-2.35.3
-
+++ /dev/null
-From b1b4941c2e3e16a21dc15604220725cf7f2de7c5 Mon Sep 17 00:00:00 2001
-From: Josua Mayer <josua@solid-run.com>
-Date: Wed, 20 Jul 2022 19:10:56 +0300
-Subject: [PATCH 2/2] arm: mvebu: clearfog: support 512MB memory size from tlv
- eeprom
-
-Handle 2GBit memory size value "2" from tlv eeprom on ddr
-initialisation, to support SoMs with 512MB ddr memory.
-
-Signed-off-by: Josua Mayer <josua@solid-run.com>
----
- board/solidrun/clearfog/clearfog.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
-index 4f4532b537e..6fa2fe5fe3e 100644
---- a/board/solidrun/clearfog/clearfog.c
-+++ b/board/solidrun/clearfog/clearfog.c
-@@ -159,6 +159,9 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
- cf_read_tlv_data();
-
- switch (cf_tlv_data.ram_size) {
-+ case 2:
-+ ifp->memory_size = MV_DDR_DIE_CAP_2GBIT;
-+ break;
- case 4:
- default:
- ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
---
-2.35.3
-
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_VERSION:=2014.10
-PKG_RELEASE:=16
-
-PKG_HASH:=d3b132a7a9b3f3182b7aad71c2dfbd4fc15bea83e12c76134eb3ffefc07d1c71
-
-include $(INCLUDE_DIR)/u-boot.mk
-include $(INCLUDE_DIR)/package.mk
-
-define U-Boot/Default
- BUILD_TARGET:=oxnas
- BUILD_DEVICES:=Default
- HIDDEN:=y
-endef
-
-define U-Boot/ox820
- NAME:=Oxford/PLX NAS7820
-endef
-
-UBOOT_TARGETS:=ox820
-
-define Build/InstallDev
- $(INSTALL_DIR) $(STAGING_DIR_IMAGE)
- $(CP) $(PKG_BUILD_DIR)/u-boot.bin $(STAGING_DIR_IMAGE)/u-boot.bin
-endef
-
-$(eval $(call BuildPackage/U-Boot))
+++ /dev/null
-From df9fb90120423c4c55b66a5dc09af23f605a406b Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 1 Dec 2014 21:37:25 +0100
-Subject: [PATCH] disk/part.c: use unsigned format when printing capacity
-To: u-boot@lists.denx.de
-
-Large disks otherwise produce highly unplausible output such as
- Capacity: 1907729.0 MB = 1863.0 GB (-387938128 x 512)
-
-As supposedly all size-related decimals are unsigned, use unsigned
-format in printf statement, resulting in a correct capacity being
-displayed:
- Capacity: 1907729.0 MB = 1863.0 GB (3907029168 x 512)
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- disk/part.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/disk/part.c
-+++ b/disk/part.c
-@@ -229,13 +229,13 @@ void dev_print (block_dev_desc_t *dev_de
- printf (" Supports 48-bit addressing\n");
- #endif
- #if defined(CONFIG_SYS_64BIT_LBA)
-- printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%Ld x %ld)\n",
-+ printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%Lu x %lu)\n",
- mb_quot, mb_rem,
- gb_quot, gb_rem,
- lba,
- dev_desc->blksz);
- #else
-- printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\n",
-+ printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%lu x %lu)\n",
- mb_quot, mb_rem,
- gb_quot, gb_rem,
- (ulong)lba,
+++ /dev/null
---- a/tools/socfpgaimage.c
-+++ b/tools/socfpgaimage.c
-@@ -74,12 +74,12 @@ static uint16_t hdr_checksum(struct socf
- static void build_header(uint8_t *buf, uint8_t version, uint8_t flags,
- uint16_t length_bytes)
- {
-- header.validation = htole32(VALIDATION_WORD);
-+ header.validation = cpu_to_le32(VALIDATION_WORD);
- header.version = version;
- header.flags = flags;
-- header.length_u32 = htole16(length_bytes/4);
-+ header.length_u32 = cpu_to_le16(length_bytes/4);
- header.zero = 0;
-- header.checksum = htole16(hdr_checksum(&header));
-+ header.checksum = cpu_to_le16(hdr_checksum(&header));
-
- memcpy(buf, &header, sizeof(header));
- }
-@@ -92,12 +92,12 @@ static int verify_header(const uint8_t *
- {
- memcpy(&header, buf, sizeof(header));
-
-- if (le32toh(header.validation) != VALIDATION_WORD)
-+ if (le32_to_cpu(header.validation) != VALIDATION_WORD)
- return -1;
-- if (le16toh(header.checksum) != hdr_checksum(&header))
-+ if (le16_to_cpu(header.checksum) != hdr_checksum(&header))
- return -1;
-
-- return le16toh(header.length_u32) * 4;
-+ return le16_to_cpu(header.length_u32) * 4;
- }
-
- /* Sign the buffer and return the signed buffer size */
-@@ -116,7 +116,7 @@ static int sign_buffer(uint8_t *buf,
- /* Calculate and apply the CRC */
- calc_crc = ~pbl_crc32(0, (char *)buf, len);
-
-- *((uint32_t *)(buf + len)) = htole32(calc_crc);
-+ *((uint32_t *)(buf + len)) = cpu_to_le32(calc_crc);
-
- if (!pad_64k)
- return len + 4;
-@@ -150,7 +150,7 @@ static int verify_buffer(const uint8_t *
-
- calc_crc = ~pbl_crc32(0, (const char *)buf, len);
-
-- buf_crc = le32toh(*((uint32_t *)(buf + len)));
-+ buf_crc = le32_to_cpu(*((uint32_t *)(buf + len)));
-
- if (buf_crc != calc_crc) {
- fprintf(stderr, "CRC32 does not match (%08x != %08x)\n",
+++ /dev/null
---- a/common/spl/Makefile
-+++ b/common/spl/Makefile
-@@ -19,4 +19,5 @@ obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc
- obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
- obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
- obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
-+obj-$(CONFIG_SPL_BLOCK_SUPPORT) += spl_block.o
- endif
---- a/common/spl/spl.c
-+++ b/common/spl/spl.c
-@@ -191,6 +191,14 @@ void board_init_r(gd_t *dummy1, ulong du
- spl_spi_load_image();
- break;
- #endif
-+#ifdef CONFIG_SPL_BLOCK_SUPPORT
-+ case BOOT_DEVICE_BLOCK:
-+ {
-+ extern void spl_block_load_image(void);
-+ spl_block_load_image();
-+ break;
-+ }
-+#endif
- #ifdef CONFIG_SPL_ETH_SUPPORT
- case BOOT_DEVICE_CPGMAC:
- #ifdef CONFIG_SPL_ETH_DEVICE
---- a/common/cmd_nvedit.c
-+++ b/common/cmd_nvedit.c
-@@ -49,6 +49,7 @@ DECLARE_GLOBAL_DATA_PTR;
- !defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \
- !defined(CONFIG_ENV_IS_IN_REMOTE) && \
- !defined(CONFIG_ENV_IS_IN_UBI) && \
-+ !defined(CONFIG_ENV_IS_IN_EXT4) && \
- !defined(CONFIG_ENV_IS_NOWHERE)
- # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
- SPI_FLASH|NVRAM|MMC|FAT|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
---- a/common/Makefile
-+++ b/common/Makefile
-@@ -63,6 +63,7 @@ obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_o
- obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
- obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
- obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
-+obj-$(CONFIG_ENV_IS_IN_EXT4) += env_ext4.o
- obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
-
- # command
-@@ -213,6 +214,8 @@ obj-$(CONFIG_UPDATE_TFTP) += update.o
- obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
- obj-$(CONFIG_CMD_DFU) += cmd_dfu.o
- obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
-+else
-+obj-$(CONFIG_SPL_BLOCK_SUPPORT) += cmd_ide.o
- endif
-
- ifdef CONFIG_SPL_BUILD
+++ /dev/null
-From e719404ee1241af679a51879eaad291bc27e4817 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 2 Dec 2014 14:46:05 +0100
-Subject: [PATCH] net/phy: add back icplus driver
-
-IC+ phy driver was removed due to the lack of users some time ago.
-Add it back, so we can use it.
----
- drivers/net/phy/Makefile | 1 +
- drivers/net/phy/icplus.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++
- drivers/net/phy/phy.c | 3 ++
- 3 files changed, 84 insertions(+)
- create mode 100644 drivers/net/phy/icplus.c
-
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_ATHEROS) += atheros.o
- obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
- obj-$(CONFIG_PHY_DAVICOM) += davicom.o
- obj-$(CONFIG_PHY_ET1011C) += et1011c.o
-+obj-$(CONFIG_PHY_ICPLUS) += icplus.o
- obj-$(CONFIG_PHY_LXT) += lxt.o
- obj-$(CONFIG_PHY_MARVELL) += marvell.o
- obj-$(CONFIG_PHY_MICREL) += micrel.o
---- /dev/null
-+++ b/drivers/net/phy/icplus.c
-@@ -0,0 +1,93 @@
-+/*
-+ * ICPlus PHY drivers
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ *
-+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
-+ */
-+#include <phy.h>
-+
-+/* IP101A/G - IP1001 */
-+#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
-+#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
-+#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
-+#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
-+#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
-+#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
-+#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
-+#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
-+#define IP1001LF_DRIVE_MASK (15 << 5)
-+#define IP1001LF_RXCLKDRIVE_HI (2 << 5)
-+#define IP1001LF_RXDDRIVE_HI (2 << 7)
-+#define IP1001LF_RXCLKDRIVE_M (1 << 5)
-+#define IP1001LF_RXDDRIVE_M (1 << 7)
-+#define IP1001LF_RXCLKDRIVE_L (0 << 5)
-+#define IP1001LF_RXDDRIVE_L (0 << 7)
-+#define IP1001LF_RXCLKDRIVE_VL (3 << 5)
-+#define IP1001LF_RXDDRIVE_VL (3 << 7)
-+
-+static int ip1001_config(struct phy_device *phydev)
-+{
-+ int c;
-+
-+ /* Enable Auto Power Saving mode */
-+ c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2);
-+ if (c < 0)
-+ return c;
-+ c |= IP1001_APS_ON;
-+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c);
-+ if (c < 0)
-+ return c;
-+
-+ /* INTR pin used: speed/link/duplex will cause an interrupt */
-+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS,
-+ IP101A_G_IRQ_DEFAULT);
-+ if (c < 0)
-+ return c;
-+
-+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
-+ /*
-+ * Additional delay (2ns) used to adjust RX clock phase
-+ * at RGMII interface
-+ */
-+ c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS);
-+ if (c < 0)
-+ return c;
-+
-+ c |= IP1001_PHASE_SEL_MASK;
-+ /* adjust digtial drive strength */
-+ c &= ~IP1001LF_DRIVE_MASK;
-+ c |= IP1001LF_RXCLKDRIVE_M;
-+ c |= IP1001LF_RXDDRIVE_M;
-+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS,
-+ c);
-+ if (c < 0)
-+ return c;
-+ }
-+
-+ return 0;
-+}
-+
-+static int ip1001_startup(struct phy_device *phydev)
-+{
-+ genphy_update_link(phydev);
-+ genphy_parse_link(phydev);
-+
-+ return 0;
-+}
-+static struct phy_driver IP1001_driver = {
-+ .name = "ICPlus IP1001",
-+ .uid = 0x02430d90,
-+ .mask = 0x0ffffff0,
-+ .features = PHY_GBIT_FEATURES,
-+ .config = &ip1001_config,
-+ .startup = &ip1001_startup,
-+ .shutdown = &genphy_shutdown,
-+};
-+
-+int phy_icplus_init(void)
-+{
-+ phy_register(&IP1001_driver);
-+
-+ return 0;
-+}
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -454,6 +454,9 @@ int phy_init(void)
- #ifdef CONFIG_PHY_ET1011C
- phy_et1011c_init();
- #endif
-+#ifdef CONFIG_PHY_ICPLUS
-+ phy_icplus_init();
-+#endif
- #ifdef CONFIG_PHY_LXT
- phy_lxt_init();
- #endif
---- a/include/phy.h
-+++ b/include/phy.h
-@@ -225,6 +225,7 @@ int phy_atheros_init(void);
- int phy_broadcom_init(void);
- int phy_davicom_init(void);
- int phy_et1011c_init(void);
-+int phy_icplus_init(void);
- int phy_lxt_init(void);
- int phy_marvell_init(void);
- int phy_micrel_init(void);
+++ /dev/null
---- a/arch/arm/include/asm/mach-types.h
-+++ b/arch/arm/include/asm/mach-types.h
-@@ -212,6 +212,7 @@ extern unsigned int __machine_arch_type;
- #define MACH_TYPE_EDB9307A 1128
- #define MACH_TYPE_OMAP_3430SDP 1138
- #define MACH_TYPE_VSTMS 1140
-+#define MACH_TYPE_OXNAS 1152
- #define MACH_TYPE_MICRO9M 1169
- #define MACH_TYPE_BUG 1179
- #define MACH_TYPE_AT91SAM9263EK 1202
---- a/drivers/block/Makefile
-+++ b/drivers/block/Makefile
-@@ -21,3 +21,4 @@ obj-$(CONFIG_IDE_SIL680) += sil680.o
- obj-$(CONFIG_SANDBOX) += sandbox.o
- obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
- obj-$(CONFIG_SYSTEMACE) += systemace.o
-+obj-$(CONFIG_IDE_PLX) += plxsata_ide.o
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
- obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
- obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
- obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
-+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o
- obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
- obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
- obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
---- a/tools/.gitignore
-+++ b/tools/.gitignore
-@@ -9,6 +9,7 @@
- /mkenvimage
- /mkimage
- /mkexynosspl
-+/mkox820crc
- /mpc86x_clk
- /mxsboot
- /mksunxiboot
---- a/tools/Makefile
-+++ b/tools/Makefile
-@@ -143,6 +143,12 @@ hostprogs-$(CONFIG_KIRKWOOD) += kwboot
- hostprogs-y += proftool
- hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
-
-+
-+hostprogs-$(CONFIG_OX820) += mkox820crc$(SFX)
-+
-+mkox820crc$(SFX)-objs := mkox820crc.o lib/crc32.o
-+
-+
- # We build some files with extra pedantic flags to try to minimize things
- # that won't build on some weird host compiler -- though there are lots of
- # exceptions for files that aren't complaint.
---- a/drivers/serial/ns16550.c
-+++ b/drivers/serial/ns16550.c
-@@ -118,6 +118,14 @@ int ns16550_calc_divisor(NS16550_t port,
- }
- port->osc_12m_sel = 0; /* clear if previsouly set */
- #endif
-+#ifdef CONFIG_OX820
-+ {
-+ /* with additional 3 bit fractional */
-+ u32 div = (CONFIG_SYS_NS16550_CLK + baudrate) / (baudrate * 2);
-+ port->reg9 = (div & 7) << 5;
-+ return (div >> 3);
-+ }
-+#endif
-
- return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
- }
---- a/scripts/Makefile.spl
-+++ b/scripts/Makefile.spl
-@@ -202,6 +202,9 @@ OBJCOPYFLAGS_$(SPL_BIN).bin = $(SPL_OBJC
-
- $(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN) FORCE
- $(call if_changed,objcopy)
-+ifdef CONFIG_OX820
-+ $(OBJTREE)/tools/mkox820crc $@
-+endif
-
- LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
- ifneq ($(CONFIG_SPL_TEXT_BASE),)
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -488,6 +488,9 @@ config TARGET_BALLOON3
- config TARGET_H2200
- bool "Support h2200"
-
-+config TARGET_OX820
-+ bool "Support ox820"
-+
- config TARGET_PALMLD
- bool "Support palmld"
-
-@@ -650,6 +653,7 @@ source "board/logicpd/imx27lite/Kconfig"
- source "board/logicpd/imx31_litekit/Kconfig"
- source "board/mpl/vcma9/Kconfig"
- source "board/olimex/mx23_olinuxino/Kconfig"
-+source "board/ox820/Kconfig"
- source "board/palmld/Kconfig"
- source "board/palmtc/Kconfig"
- source "board/palmtreo680/Kconfig"
+++ /dev/null
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 7 Feb 2015 21:52:40 +0000 (+0100)
-Subject: Add linux/compiler-gcc5.h to fix builds with gcc5
-X-Git-Tag: v2015.04-rc2~31
-X-Git-Url: http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=478b02f1a7043b673565075ea5016376f3293b23
-
-Add linux/compiler-gcc5.h to fix builds with gcc5
-
-Add linux/compiler-gcc5/h from the kernel sources at:
-
-commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b
-Author: Steven Noonan <steven@uplinklabs.net>
-Date: Sat Oct 25 15:09:42 2014 -0700
-
- compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
-
---- /dev/null
-+++ b/include/linux/compiler-gcc5.h
-@@ -0,0 +1,65 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+#define __used __attribute__((__used__))
-+#define __must_check __attribute__((warn_unused_result))
-+#define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
-+
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+ to them will be unlikely. This means a lot of manual unlikely()s
-+ are unnecessary now for any paths leading to the usual suspects
-+ like BUG(), printk(), panic() etc. [but let's keep them for now for
-+ older compilers]
-+
-+ Early snapshots of gcc 4.3 don't support this and we can't detect this
-+ in the preprocessor, but we can live with this because they're unreleased.
-+ Maketime probing would be overkill here.
-+
-+ gcc also has a __attribute__((__hot__)) to move hot functions into
-+ a special section, but I don't see any sense in this right now in
-+ the kernel context */
-+#define __cold __attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+
-+/*
-+ * Mark a position in code as unreachable. This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased. Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone __attribute__((__noclone__))
-+
-+/*
-+ * Tell the optimizer that something else uses this function or variable.
-+ */
-+#define __visible __attribute__((externally_visible))
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
+++ /dev/null
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 7 Feb 2015 21:52:40 +0000 (+0100)
-Subject: Add linux/compiler-gcc6.h to fix builds with gcc6
-X-Git-Tag: v2015.04-rc2~31
-X-Git-Url: http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=478b02f1a7043b673565075ea5016376f3293b23
-
-Add linux/compiler-gcc6.h to fix builds with gcc6
-
-Add linux/compiler-gcc6/h from the kernel sources at:
-
-commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b
-Author: Steven Noonan <steven@uplinklabs.net>
-Date: Sat Oct 25 15:09:42 2014 -0700
-
- compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
-
---- /dev/null
-+++ b/include/linux/compiler-gcc6.h
-@@ -0,0 +1,284 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+/*
-+ * Common definitions for all gcc versions go here.
-+ */
-+#define GCC_VERSION (__GNUC__ * 10000 \
-+ + __GNUC_MINOR__ * 100 \
-+ + __GNUC_PATCHLEVEL__)
-+
-+/* Optimization barrier */
-+
-+/* The "volatile" is due to gcc bugs */
-+#define barrier() __asm__ __volatile__("": : :"memory")
-+/*
-+ * This version is i.e. to prevent dead stores elimination on @ptr
-+ * where gcc and llvm may behave differently when otherwise using
-+ * normal barrier(): while gcc behavior gets along with a normal
-+ * barrier(), llvm needs an explicit input variable to be assumed
-+ * clobbered. The issue is as follows: while the inline asm might
-+ * access any memory it wants, the compiler could have fit all of
-+ * @ptr into memory registers instead, and since @ptr never escaped
-+ * from that, it proofed that the inline asm wasn't touching any of
-+ * it. This version works well with both compilers, i.e. we're telling
-+ * the compiler that the inline asm absolutely may see the contents
-+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
-+ */
-+#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
-+
-+/*
-+ * This macro obfuscates arithmetic on a variable address so that gcc
-+ * shouldn't recognize the original var, and make assumptions about it.
-+ *
-+ * This is needed because the C standard makes it undefined to do
-+ * pointer arithmetic on "objects" outside their boundaries and the
-+ * gcc optimizers assume this is the case. In particular they
-+ * assume such arithmetic does not wrap.
-+ *
-+ * A miscompilation has been observed because of this on PPC.
-+ * To work around it we hide the relationship of the pointer and the object
-+ * using this macro.
-+ *
-+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
-+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
-+ * the inline assembly constraint from =g to =r, in this particular
-+ * case either is valid.
-+ */
-+#define RELOC_HIDE(ptr, off) \
-+({ \
-+ unsigned long __ptr; \
-+ __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \
-+ (typeof(ptr)) (__ptr + (off)); \
-+})
-+
-+/* Make the optimizer believe the variable can be manipulated arbitrarily. */
-+#define OPTIMIZER_HIDE_VAR(var) \
-+ __asm__ ("" : "=r" (var) : "0" (var))
-+
-+#ifdef __CHECKER__
-+#define __must_be_array(a) 0
-+#else
-+/* &a[0] degrades to a pointer: a different type from an array */
-+#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
-+#endif
-+
-+/*
-+ * Force always-inline if the user requests it so via the .config,
-+ * or if gcc is too old:
-+ */
-+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
-+ !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-+#define inline inline __attribute__((always_inline)) notrace
-+#define __inline__ __inline__ __attribute__((always_inline)) notrace
-+#define __inline __inline __attribute__((always_inline)) notrace
-+#else
-+/* A lot of inline functions can cause havoc with function tracing */
-+#define inline inline notrace
-+#define __inline__ __inline__ notrace
-+#define __inline __inline notrace
-+#endif
-+
-+#define __always_inline inline __attribute__((always_inline))
-+#define noinline __attribute__((noinline))
-+
-+#define __deprecated __attribute__((deprecated))
-+#define __packed __attribute__((packed))
-+#define __weak __attribute__((weak))
-+#define __alias(symbol) __attribute__((alias(#symbol)))
-+
-+/*
-+ * it doesn't make sense on ARM (currently the only user of __naked)
-+ * to trace naked functions because then mcount is called without
-+ * stack and frame pointer being set up and there is no chance to
-+ * restore the lr register to the value before mcount was called.
-+ *
-+ * The asm() bodies of naked functions often depend on standard calling
-+ * conventions, therefore they must be noinline and noclone.
-+ *
-+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.
-+ * See GCC PR44290.
-+ */
-+#define __naked __attribute__((naked)) noinline __noclone notrace
-+
-+#define __noreturn __attribute__((noreturn))
-+
-+/*
-+ * From the GCC manual:
-+ *
-+ * Many functions have no effects except the return value and their
-+ * return value depends only on the parameters and/or global
-+ * variables. Such a function can be subject to common subexpression
-+ * elimination and loop optimization just as an arithmetic operator
-+ * would be.
-+ * [...]
-+ */
-+#define __pure __attribute__((pure))
-+#define __aligned(x) __attribute__((aligned(x)))
-+#define __printf(a, b) __attribute__((format(printf, a, b)))
-+#define __scanf(a, b) __attribute__((format(scanf, a, b)))
-+#define __attribute_const__ __attribute__((__const__))
-+#define __maybe_unused __attribute__((unused))
-+#define __always_unused __attribute__((unused))
-+
-+/* gcc version specific checks */
-+
-+#if GCC_VERSION < 30200
-+# error Sorry, your compiler is too old - please upgrade it.
-+#endif
-+
-+#if GCC_VERSION < 30300
-+# define __used __attribute__((__unused__))
-+#else
-+# define __used __attribute__((__used__))
-+#endif
-+
-+#ifdef CONFIG_GCOV_KERNEL
-+# if GCC_VERSION < 30400
-+# error "GCOV profiling support for gcc versions below 3.4 not included"
-+# endif /* __GNUC_MINOR__ */
-+#endif /* CONFIG_GCOV_KERNEL */
-+
-+#if GCC_VERSION >= 30400
-+#define __must_check __attribute__((warn_unused_result))
-+#define __malloc __attribute__((__malloc__))
-+#endif
-+
-+#if GCC_VERSION >= 40000
-+
-+/* GCC 4.1.[01] miscompiles __weak */
-+#ifdef __KERNEL__
-+# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101
-+# error Your version of gcc miscompiles the __weak directive
-+# endif
-+#endif
-+
-+#define __used __attribute__((__used__))
-+#define __compiler_offsetof(a, b) \
-+ __builtin_offsetof(a, b)
-+
-+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
-+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-+#endif
-+
-+#if GCC_VERSION >= 40300
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+ * to them will be unlikely. This means a lot of manual unlikely()s
-+ * are unnecessary now for any paths leading to the usual suspects
-+ * like BUG(), printk(), panic() etc. [but let's keep them for now for
-+ * older compilers]
-+ *
-+ * Early snapshots of gcc 4.3 don't support this and we can't detect this
-+ * in the preprocessor, but we can live with this because they're unreleased.
-+ * Maketime probing would be overkill here.
-+ *
-+ * gcc also has a __attribute__((__hot__)) to move hot functions into
-+ * a special section, but I don't see any sense in this right now in
-+ * the kernel context
-+ */
-+#define __cold __attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+#endif /* GCC_VERSION >= 40300 */
-+
-+#if GCC_VERSION >= 40500
-+/*
-+ * Mark a position in code as unreachable. This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased. Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone __attribute__((__noclone__, __optimize__("no-tracer")))
-+
-+#endif /* GCC_VERSION >= 40500 */
-+
-+#if GCC_VERSION >= 40600
-+/*
-+ * When used with Link Time Optimization, gcc can optimize away C functions or
-+ * variables which are referenced only from assembly code. __visible tells the
-+ * optimizer that something else uses this function or variable, thus preventing
-+ * this.
-+ */
-+#define __visible __attribute__((externally_visible))
-+#endif
-+
-+
-+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)
-+/*
-+ * __assume_aligned(n, k): Tell the optimizer that the returned
-+ * pointer can be assumed to be k modulo n. The second argument is
-+ * optional (default 0), so we use a variadic macro to make the
-+ * shorthand.
-+ *
-+ * Beware: Do not apply this to functions which may return
-+ * ERR_PTRs. Also, it is probably unwise to apply it to functions
-+ * returning extra information in the low bits (but in that case the
-+ * compiler should see some alignment anyway, when the return value is
-+ * massaged by 'flags = ptr & 3; ptr &= ~3;').
-+ */
-+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
-+#endif
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#if GCC_VERSION >= 40400
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#endif
-+#if GCC_VERSION >= 40800
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
-+
-+#if GCC_VERSION >= 50000
-+#define KASAN_ABI_VERSION 4
-+#elif GCC_VERSION >= 40902
-+#define KASAN_ABI_VERSION 3
-+#endif
-+
-+#if GCC_VERSION >= 40902
-+/*
-+ * Tell the compiler that address safety instrumentation (KASAN)
-+ * should not be applied to that function.
-+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
-+ */
-+#define __no_sanitize_address __attribute__((no_sanitize_address))
-+#endif
-+
-+#endif /* gcc version >= 40000 specific checks */
-+
-+#if !defined(__noclone)
-+#define __noclone /* not needed */
-+#endif
-+
-+#if !defined(__no_sanitize_address)
-+#define __no_sanitize_address
-+#endif
-+
-+/*
-+ * A trick to suppress uninitialized variable warning without generating any
-+ * code
-+ */
-+#define uninitialized_var(x) x = x
+++ /dev/null
---- /dev/null
-+++ b/include/linux/compiler-gcc7.h
-@@ -0,0 +1,284 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+/*
-+ * Common definitions for all gcc versions go here.
-+ */
-+#define GCC_VERSION (__GNUC__ * 10000 \
-+ + __GNUC_MINOR__ * 100 \
-+ + __GNUC_PATCHLEVEL__)
-+
-+/* Optimization barrier */
-+
-+/* The "volatile" is due to gcc bugs */
-+#define barrier() __asm__ __volatile__("": : :"memory")
-+/*
-+ * This version is i.e. to prevent dead stores elimination on @ptr
-+ * where gcc and llvm may behave differently when otherwise using
-+ * normal barrier(): while gcc behavior gets along with a normal
-+ * barrier(), llvm needs an explicit input variable to be assumed
-+ * clobbered. The issue is as follows: while the inline asm might
-+ * access any memory it wants, the compiler could have fit all of
-+ * @ptr into memory registers instead, and since @ptr never escaped
-+ * from that, it proofed that the inline asm wasn't touching any of
-+ * it. This version works well with both compilers, i.e. we're telling
-+ * the compiler that the inline asm absolutely may see the contents
-+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
-+ */
-+#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
-+
-+/*
-+ * This macro obfuscates arithmetic on a variable address so that gcc
-+ * shouldn't recognize the original var, and make assumptions about it.
-+ *
-+ * This is needed because the C standard makes it undefined to do
-+ * pointer arithmetic on "objects" outside their boundaries and the
-+ * gcc optimizers assume this is the case. In particular they
-+ * assume such arithmetic does not wrap.
-+ *
-+ * A miscompilation has been observed because of this on PPC.
-+ * To work around it we hide the relationship of the pointer and the object
-+ * using this macro.
-+ *
-+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
-+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
-+ * the inline assembly constraint from =g to =r, in this particular
-+ * case either is valid.
-+ */
-+#define RELOC_HIDE(ptr, off) \
-+({ \
-+ unsigned long __ptr; \
-+ __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \
-+ (typeof(ptr)) (__ptr + (off)); \
-+})
-+
-+/* Make the optimizer believe the variable can be manipulated arbitrarily. */
-+#define OPTIMIZER_HIDE_VAR(var) \
-+ __asm__ ("" : "=r" (var) : "0" (var))
-+
-+#ifdef __CHECKER__
-+#define __must_be_array(a) 0
-+#else
-+/* &a[0] degrades to a pointer: a different type from an array */
-+#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
-+#endif
-+
-+/*
-+ * Force always-inline if the user requests it so via the .config,
-+ * or if gcc is too old:
-+ */
-+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
-+ !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-+#define inline inline __attribute__((always_inline)) notrace
-+#define __inline__ __inline__ __attribute__((always_inline)) notrace
-+#define __inline __inline __attribute__((always_inline)) notrace
-+#else
-+/* A lot of inline functions can cause havoc with function tracing */
-+#define inline inline notrace
-+#define __inline__ __inline__ notrace
-+#define __inline __inline notrace
-+#endif
-+
-+#define __always_inline inline __attribute__((always_inline))
-+#define noinline __attribute__((noinline))
-+
-+#define __deprecated __attribute__((deprecated))
-+#define __packed __attribute__((packed))
-+#define __weak __attribute__((weak))
-+#define __alias(symbol) __attribute__((alias(#symbol)))
-+
-+/*
-+ * it doesn't make sense on ARM (currently the only user of __naked)
-+ * to trace naked functions because then mcount is called without
-+ * stack and frame pointer being set up and there is no chance to
-+ * restore the lr register to the value before mcount was called.
-+ *
-+ * The asm() bodies of naked functions often depend on standard calling
-+ * conventions, therefore they must be noinline and noclone.
-+ *
-+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.
-+ * See GCC PR44290.
-+ */
-+#define __naked __attribute__((naked)) noinline __noclone notrace
-+
-+#define __noreturn __attribute__((noreturn))
-+
-+/*
-+ * From the GCC manual:
-+ *
-+ * Many functions have no effects except the return value and their
-+ * return value depends only on the parameters and/or global
-+ * variables. Such a function can be subject to common subexpression
-+ * elimination and loop optimization just as an arithmetic operator
-+ * would be.
-+ * [...]
-+ */
-+#define __pure __attribute__((pure))
-+#define __aligned(x) __attribute__((aligned(x)))
-+#define __printf(a, b) __attribute__((format(printf, a, b)))
-+#define __scanf(a, b) __attribute__((format(scanf, a, b)))
-+#define __attribute_const__ __attribute__((__const__))
-+#define __maybe_unused __attribute__((unused))
-+#define __always_unused __attribute__((unused))
-+
-+/* gcc version specific checks */
-+
-+#if GCC_VERSION < 30200
-+# error Sorry, your compiler is too old - please upgrade it.
-+#endif
-+
-+#if GCC_VERSION < 30300
-+# define __used __attribute__((__unused__))
-+#else
-+# define __used __attribute__((__used__))
-+#endif
-+
-+#ifdef CONFIG_GCOV_KERNEL
-+# if GCC_VERSION < 30400
-+# error "GCOV profiling support for gcc versions below 3.4 not included"
-+# endif /* __GNUC_MINOR__ */
-+#endif /* CONFIG_GCOV_KERNEL */
-+
-+#if GCC_VERSION >= 30400
-+#define __must_check __attribute__((warn_unused_result))
-+#define __malloc __attribute__((__malloc__))
-+#endif
-+
-+#if GCC_VERSION >= 40000
-+
-+/* GCC 4.1.[01] miscompiles __weak */
-+#ifdef __KERNEL__
-+# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101
-+# error Your version of gcc miscompiles the __weak directive
-+# endif
-+#endif
-+
-+#define __used __attribute__((__used__))
-+#define __compiler_offsetof(a, b) \
-+ __builtin_offsetof(a, b)
-+
-+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
-+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-+#endif
-+
-+#if GCC_VERSION >= 40300
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+ * to them will be unlikely. This means a lot of manual unlikely()s
-+ * are unnecessary now for any paths leading to the usual suspects
-+ * like BUG(), printk(), panic() etc. [but let's keep them for now for
-+ * older compilers]
-+ *
-+ * Early snapshots of gcc 4.3 don't support this and we can't detect this
-+ * in the preprocessor, but we can live with this because they're unreleased.
-+ * Maketime probing would be overkill here.
-+ *
-+ * gcc also has a __attribute__((__hot__)) to move hot functions into
-+ * a special section, but I don't see any sense in this right now in
-+ * the kernel context
-+ */
-+#define __cold __attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+#endif /* GCC_VERSION >= 40300 */
-+
-+#if GCC_VERSION >= 40500
-+/*
-+ * Mark a position in code as unreachable. This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased. Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone __attribute__((__noclone__, __optimize__("no-tracer")))
-+
-+#endif /* GCC_VERSION >= 40500 */
-+
-+#if GCC_VERSION >= 40600
-+/*
-+ * When used with Link Time Optimization, gcc can optimize away C functions or
-+ * variables which are referenced only from assembly code. __visible tells the
-+ * optimizer that something else uses this function or variable, thus preventing
-+ * this.
-+ */
-+#define __visible __attribute__((externally_visible))
-+#endif
-+
-+
-+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)
-+/*
-+ * __assume_aligned(n, k): Tell the optimizer that the returned
-+ * pointer can be assumed to be k modulo n. The second argument is
-+ * optional (default 0), so we use a variadic macro to make the
-+ * shorthand.
-+ *
-+ * Beware: Do not apply this to functions which may return
-+ * ERR_PTRs. Also, it is probably unwise to apply it to functions
-+ * returning extra information in the low bits (but in that case the
-+ * compiler should see some alignment anyway, when the return value is
-+ * massaged by 'flags = ptr & 3; ptr &= ~3;').
-+ */
-+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
-+#endif
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#if GCC_VERSION >= 40400
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#endif
-+#if GCC_VERSION >= 40800
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
-+
-+#if GCC_VERSION >= 50000
-+#define KASAN_ABI_VERSION 4
-+#elif GCC_VERSION >= 40902
-+#define KASAN_ABI_VERSION 3
-+#endif
-+
-+#if GCC_VERSION >= 40902
-+/*
-+ * Tell the compiler that address safety instrumentation (KASAN)
-+ * should not be applied to that function.
-+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
-+ */
-+#define __no_sanitize_address __attribute__((no_sanitize_address))
-+#endif
-+
-+#endif /* gcc version >= 40000 specific checks */
-+
-+#if !defined(__noclone)
-+#define __noclone /* not needed */
-+#endif
-+
-+#if !defined(__no_sanitize_address)
-+#define __no_sanitize_address
-+#endif
-+
-+/*
-+ * A trick to suppress uninitialized variable warning without generating any
-+ * code
-+ */
-+#define uninitialized_var(x) x = x
+++ /dev/null
---- a/common/cmd_bootm.c
-+++ b/common/cmd_bootm.c
-@@ -77,7 +77,7 @@ static int do_bootm_subcommand(cmd_tbl_t
- return CMD_RET_USAGE;
- }
-
-- if (state != BOOTM_STATE_START && images.state >= state) {
-+ if (!(state & BOOTM_STATE_START) && images.state >= state) {
- printf("Trying to execute a command out of order\n");
- return CMD_RET_USAGE;
- }
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += reset.o
-obj-y += timer.o
-obj-y += clock.o
-obj-y += pinmux.o
+++ /dev/null
-#include <common.h>
-#include <asm/arch/sysctl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-
-typedef struct {
- unsigned short mhz;
- unsigned char refdiv;
- unsigned char outdiv;
- unsigned int fbdiv;
- unsigned short bwadj;
- unsigned short sfreq;
- unsigned int sslope;
-} PLL_CONFIG;
-
-const PLL_CONFIG C_PLL_CONFIG[] = {
- { 500, 1, 2, 3932160, 119, 208, 189 }, // 500 MHz
- { 525, 2, 1, 4128768, 125, 139, 297 }, // 525 MHz
- { 550, 2, 1, 4325376, 131, 139, 311 }, // 550 MHz
- { 575, 2, 1, 4521984, 137, 139, 326 }, // 575 MHz
- { 600, 2, 1, 4718592, 143, 138, 339 }, // 600 MHz
- { 625, 1, 1, 3276800, 99, 208, 157 }, // 625 MHz
- { 650, 1, 1, 3407872, 103, 208, 164 }, // 650 MHz
- { 675, 1, 1, 3538944, 107, 208, 170 }, // 675 MHz
- { 700, 0, 0, 917504, 27, 416, 22 }, // 700 MHz
- { 725, 1, 1, 3801088, 115, 208, 182 }, // 725 MHz
- { 750, 0, 0, 983040, 29, 416, 23 }, // 750 MHz
- { 775, 3, 0, 4063232, 123, 104, 390 }, // 775 MHz
- { 800, 3, 0, 4194304, 127, 104, 403 }, // 800 MHz
- { 825, 3, 0, 4325376, 131, 104, 415 }, // 825 MHz
- { 850, 2, 0, 3342336, 101, 139, 241 }, // 850 MHz
- { 875, 2, 0, 3440640, 104, 139, 248 }, // 875 MHz
- { 900, 2, 0, 3538944, 107, 139, 255 }, // 900 MHz
- { 925, 2, 0, 3637248, 110, 139, 262 }, // 925 MHz
- { 950, 2, 0, 3735552, 113, 139, 269 }, // 950 MHz
- { 975, 2, 0, 3833856, 116, 139, 276 }, // 975 MHz
- { 1000, 2, 0, 3932160, 119, 139, 283 }, // 1000 MHz
-};
-
-#define PLL_BYPASS (1<<1)
-#define SAT_ENABLE (1<<3)
-
-#define PLL_OUTDIV_SHIFT 4
-#define PLL_REFDIV_SHIFT 8
-#define PLL_BWADJ_SHIFT 16
-
-#define PLL_LOW_FREQ 500
-#define PLL_FREQ_STEP 25
-static void plla_configure(int outdiv, int refdiv, int fbdiv, int bwadj,
- int sfreq, int sslope)
-{
- setbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS);
- udelay(10);
- reset_block(SYS_CTRL_RST_PLLA, 1);
- udelay(10);
-
- writel((refdiv << PLL_REFDIV_SHIFT) | (outdiv << PLL_OUTDIV_SHIFT) |
- SAT_ENABLE | PLL_BYPASS,
- SYS_CTRL_PLLA_CTRL0);
-
- writel(fbdiv, SYS_CTRL_PLLA_CTRL1);
- writel((bwadj << PLL_BWADJ_SHIFT) | sfreq, SYS_CTRL_PLLA_CTRL2);
- writel(sslope, SYS_CTRL_PLLA_CTRL3);
-
- udelay(10); // 5us delay required (from TCI datasheet), use 10us
-
- reset_block(SYS_CTRL_RST_PLLA, 0);
-
- udelay(100); // Delay for PLL to lock
-
- printf(" plla_ctrl0 : %08x\n", readl(SYS_CTRL_PLLA_CTRL0));
- printf(" plla_ctrl1 : %08x\n", readl(SYS_CTRL_PLLA_CTRL1));
- printf(" plla_ctrl2 : %08x\n", readl(SYS_CTRL_PLLA_CTRL2));
- printf(" plla_ctrl3 : %08x\n", readl(SYS_CTRL_PLLA_CTRL3));
-
- clrbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS); // Take PLL out of bypass
- puts("\nPLLA Set\n");
-}
-
-int plla_set_config(int mhz)
-{
- int index = (mhz - PLL_LOW_FREQ) / PLL_FREQ_STEP;
- const PLL_CONFIG *cfg;
-
- if (index < 0 || index > ARRAY_SIZE(C_PLL_CONFIG)) {
- debug("Freq %d MHz out of range, default to lowest\n", mhz);
- index = 0;
- }
- cfg = &C_PLL_CONFIG[index];
-
- printf("Attempting to set PLLA to %d MHz ...\n", (unsigned) cfg->mhz);
- plla_configure(cfg->outdiv, cfg->refdiv, cfg->fbdiv, cfg->bwadj,
- cfg->sfreq, cfg->sslope);
-
- return cfg->mhz;
-}
-
+++ /dev/null
-#include <common.h>
-#include <asm/arch/pinmux.h>
-
-void pinmux_set(int bank, int pin, int func)
-{
- u32 reg;
- u32 base;
- /* TODO: check parameters */
-
- if (bank == PINMUX_BANK_MFA)
- base = SYS_CONTROL_BASE;
- else
- base = SEC_CONTROL_BASE;
-
- clrbits_le32(base + PINMUX_SECONDARY_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_TERTIARY_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_QUATERNARY_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_DEBUG_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_ALTERNATIVE_SEL, BIT(pin));
-
- switch (func) {
- case PINMUX_GPIO:
- default:
- return;
- break;
- case PINMUX_2:
- reg = base + PINMUX_SECONDARY_SEL;
- break;
- case PINMUX_3:
- reg = base + PINMUX_TERTIARY_SEL;
- break;
- case PINMUX_4:
- reg = base + PINMUX_QUATERNARY_SEL;
- break;
- case PINMUX_DEBUG:
- reg = base + PINMUX_DEBUG_SEL;
- break;
- case PINMUX_ALT:
- reg = base + PINMUX_ALTERNATIVE_SEL;
- break;
- }
- setbits_le32(reg, BIT(pin));
-}
+++ /dev/null
-#include <common.h>
-#include <asm/arch/sysctl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/clock.h>
-
-void reset_cpu(ulong addr)
-{
- u32 value;
-
- // Assert reset to cores as per power on defaults
- // Don't touch the DDR interface as things will come to an impromptu stop
- // NB Possibly should be asserting reset for PLLB, but there are timing
- // concerns here according to the docs
-
- value =
- BIT(SYS_CTRL_RST_COPRO ) |
- BIT(SYS_CTRL_RST_USBHS ) |
- BIT(SYS_CTRL_RST_USBHSPHYA ) |
- BIT(SYS_CTRL_RST_MACA ) |
- BIT(SYS_CTRL_RST_PCIEA ) |
- BIT(SYS_CTRL_RST_SGDMA ) |
- BIT(SYS_CTRL_RST_CIPHER ) |
- BIT(SYS_CTRL_RST_SATA ) |
- BIT(SYS_CTRL_RST_SATA_LINK ) |
- BIT(SYS_CTRL_RST_SATA_PHY ) |
- BIT(SYS_CTRL_RST_PCIEPHY ) |
- BIT(SYS_CTRL_RST_STATIC ) |
- BIT(SYS_CTRL_RST_UART1 ) |
- BIT(SYS_CTRL_RST_UART2 ) |
- BIT(SYS_CTRL_RST_MISC ) |
- BIT(SYS_CTRL_RST_I2S ) |
- BIT(SYS_CTRL_RST_SD ) |
- BIT(SYS_CTRL_RST_MACB ) |
- BIT(SYS_CTRL_RST_PCIEB ) |
- BIT(SYS_CTRL_RST_VIDEO ) |
- BIT(SYS_CTRL_RST_USBHSPHYB ) |
- BIT(SYS_CTRL_RST_USBDEV );
-
- writel(value, SYS_CTRL_RST_SET_CTRL);
-
- // Release reset to cores as per power on defaults
- writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
-
- // Disable clocks to cores as per power-on defaults - must leave DDR
- // related clocks enabled otherwise we'll stop rather abruptly.
- value =
- BIT(SYS_CTRL_CLK_COPRO) |
- BIT(SYS_CTRL_CLK_DMA) |
- BIT(SYS_CTRL_CLK_CIPHER) |
- BIT(SYS_CTRL_CLK_SD) |
- BIT(SYS_CTRL_CLK_SATA) |
- BIT(SYS_CTRL_CLK_I2S) |
- BIT(SYS_CTRL_CLK_USBHS) |
- BIT(SYS_CTRL_CLK_MAC) |
- BIT(SYS_CTRL_CLK_PCIEA) |
- BIT(SYS_CTRL_CLK_STATIC) |
- BIT(SYS_CTRL_CLK_MACB) |
- BIT(SYS_CTRL_CLK_PCIEB) |
- BIT(SYS_CTRL_CLK_REF600) |
- BIT(SYS_CTRL_CLK_USBDEV);
-
- writel(value, SYS_CTRL_CLK_CLR_CTRL);
-
- // Enable clocks to cores as per power-on defaults
-
- // Set sys-control pin mux'ing as per power-on defaults
-
- writel(0, SYS_CONTROL_BASE + PINMUX_SECONDARY_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_TERTIARY_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_DEBUG_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_PULLUP_SEL);
-
- writel(0, SEC_CONTROL_BASE + PINMUX_SECONDARY_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_TERTIARY_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_DEBUG_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_PULLUP_SEL);
-
- // No need to save any state, as the ROM loader can determine whether reset
- // is due to power cycling or programatic action, just hit the (self-
- // clearing) CPU reset bit of the block reset register
- value =
- BIT(SYS_CTRL_RST_SCU) |
- BIT(SYS_CTRL_RST_ARM0) |
- BIT(SYS_CTRL_RST_ARM1);
-
- writel(value, SYS_CTRL_RST_SET_CTRL);
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (1 << (CONFIG_TIMER_PRESCALE * 4)))
-#define TIMER_LOAD_VAL 0xFFFFFF
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR)) \
- / (TIMER_CLOCK / CONFIG_SYS_HZ)
-
-#define READ_TIMER_HW (TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR))
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int timer_init (void)
-{
- int32_t val;
-
- /* Start the counter ticking up */
- writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + TIMER_LOAD); /* reload value on overflow*/
-
- val = (CONFIG_TIMER_PRESCALE << TIMER_PRESCALE_SHIFT) |
- (TIMER_MODE_PERIODIC << TIMER_MODE_SHIFT) |
- (TIMER_ENABLE << TIMER_ENABLE_SHIFT); /* mask to enable timer*/
- writel(val, CONFIG_SYS_TIMERBASE + TIMER_CTRL); /* start timer */
-
- /* reset time */
- gd->arch.lastinc = READ_TIMER; /* capture current incrementer value */
- gd->arch.tbl = 0; /* start "advancing" time stamp */
-
- return(0);
-}
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
- return get_timer_masked () - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
- ulong tmo, tmp;
-
- if (usec > 100000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
-
- tmp = get_timer (0); /* get current timestamp */
- while (get_timer (tmp) < tmo)/* loop till event */
- /*NOP*/;
- } else { /* else small number, convert to hw ticks */
- tmo = usec * (TIMER_CLOCK / 1000) / 1000;
- /* timeout is no more than 0.1s, and the hw timer will roll over at most once */
- tmp = READ_TIMER_HW;
- while (((READ_TIMER_HW -tmp) & TIMER_LOAD_VAL) < tmo)/* loop till event */
- /*NOP*/;
- }
-}
-
-ulong get_timer_masked (void)
-{
- ulong now = READ_TIMER; /* current tick value */
-
- if (now >= gd->arch.lastinc) { /* normal mode (non roll) */
- /* move stamp fordward with absoulte diff ticks */
- gd->arch.tbl += (now - gd->arch.lastinc);
- } else {
- /* we have rollover of incrementer */
- gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
- - gd->arch.lastinc) + now;
- }
- gd->arch.lastinc = now;
- return gd->arch.tbl;
-}
-
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- ulong tbclk;
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
-}
+++ /dev/null
-#ifndef _NAS782X_CLOCK_H
-#define _NAS782X_CLOCK_H
-
-#include <asm/arch/sysctl.h>
-#include <asm/arch/cpu.h>
-
-/* bit numbers of clock control register */
-#define SYS_CTRL_CLK_COPRO 0
-#define SYS_CTRL_CLK_DMA 1
-#define SYS_CTRL_CLK_CIPHER 2
-#define SYS_CTRL_CLK_SD 3
-#define SYS_CTRL_CLK_SATA 4
-#define SYS_CTRL_CLK_I2S 5
-#define SYS_CTRL_CLK_USBHS 6
-#define SYS_CTRL_CLK_MACA 7
-#define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA
-#define SYS_CTRL_CLK_PCIEA 8
-#define SYS_CTRL_CLK_STATIC 9
-#define SYS_CTRL_CLK_MACB 10
-#define SYS_CTRL_CLK_PCIEB 11
-#define SYS_CTRL_CLK_REF600 12
-#define SYS_CTRL_CLK_USBDEV 13
-#define SYS_CTRL_CLK_DDR 14
-#define SYS_CTRL_CLK_DDRPHY 15
-#define SYS_CTRL_CLK_DDRCK 16
-
-/* bit numbers of reset control register */
-#define SYS_CTRL_RST_SCU 0
-#define SYS_CTRL_RST_COPRO 1
-#define SYS_CTRL_RST_ARM0 2
-#define SYS_CTRL_RST_ARM1 3
-#define SYS_CTRL_RST_USBHS 4
-#define SYS_CTRL_RST_USBHSPHYA 5
-#define SYS_CTRL_RST_MACA 6
-#define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA
-#define SYS_CTRL_RST_PCIEA 7
-#define SYS_CTRL_RST_SGDMA 8
-#define SYS_CTRL_RST_CIPHER 9
-#define SYS_CTRL_RST_DDR 10
-#define SYS_CTRL_RST_SATA 11
-#define SYS_CTRL_RST_SATA_LINK 12
-#define SYS_CTRL_RST_SATA_PHY 13
-#define SYS_CTRL_RST_PCIEPHY 14
-#define SYS_CTRL_RST_STATIC 15
-#define SYS_CTRL_RST_GPIO 16
-#define SYS_CTRL_RST_UART1 17
-#define SYS_CTRL_RST_UART2 18
-#define SYS_CTRL_RST_MISC 19
-#define SYS_CTRL_RST_I2S 20
-#define SYS_CTRL_RST_SD 21
-#define SYS_CTRL_RST_MACB 22
-#define SYS_CTRL_RST_PCIEB 23
-#define SYS_CTRL_RST_VIDEO 24
-#define SYS_CTRL_RST_DDR_PHY 25
-#define SYS_CTRL_RST_USBHSPHYB 26
-#define SYS_CTRL_RST_USBDEV 27
-#define SYS_CTRL_RST_ARMDBG 29
-#define SYS_CTRL_RST_PLLA 30
-#define SYS_CTRL_RST_PLLB 31
-
-static inline void reset_block(int block, int reset)
-{
- u32 reg;
- if (reset)
- reg = SYS_CTRL_RST_SET_CTRL;
- else
- reg = SYS_CTRL_RST_CLR_CTRL;
-
- writel(BIT(block), reg);
-}
-
-static inline void enable_clock(int block)
-{
- writel(BIT(block), SYS_CTRL_CLK_SET_CTRL);
-}
-
-static inline void disable_clock(int block)
-{
- writel(BIT(block), SYS_CTRL_CLK_CLR_CTRL);
-}
-
-int plla_set_config(int idx);
-
-#endif /* _NAS782X_CLOCK_H */
+++ /dev/null
-#ifndef _NAS782X_CPU_H
-#define _NAS782X_CPU_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#include <asm/io.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/timer.h>
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-
-#define BIT(x) (1 << (x))
-
-/* fix "implicit declaration of function" warnning */
-void *memalign(size_t alignment, size_t bytes);
-void free(void* mem);
-void *malloc(size_t bytes);
-void *calloc(size_t n, size_t elem_size);
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#endif /* _NAS782X_CPU_H */
+++ /dev/null
-#ifndef _NAS782X_HARDWARE_H
-#define _NAS782X_HARDWARE_H
-
-/* Core addresses */
-#define USB_HOST_BASE 0x40200000
-#define MACA_BASE 0x40400000
-#define MACB_BASE 0x40800000
-#define MAC_BASE MACA_BASE
-#define STATIC_CS0_BASE 0x41000000
-#define STATIC_CS1_BASE 0x41400000
-#define STATIC_CONTROL_BASE 0x41C00000
-#define SATA_DATA_BASE 0x42000000 /* non-functional, DMA just needs an address */
-#define GPIO_1_BASE 0x44000000
-#define GPIO_2_BASE 0x44100000
-#define UART_1_BASE 0x44200000
-#define UART_2_BASE 0x44300000
-#define SYS_CONTROL_BASE 0x44e00000
-#define SEC_CONTROL_BASE 0x44f00000
-#define RPSA_BASE 0x44400000
-#define RPSC_BASE 0x44500000
-#define DDR_BASE 0x44700000
-
-#define SATA_BASE 0x45900000
-#define SATA_0_REGS_BASE 0x45900000
-#define SATA_1_REGS_BASE 0x45910000
-#define SATA_DMA_REGS_BASE 0x459a0000
-#define SATA_SGDMA_REGS_BASE 0x459b0000
-#define SATA_HOST_REGS_BASE 0x459e0000
-
-#endif /* _NAS782X_HARDWARE_H */
+++ /dev/null
-#ifndef _NAS782X_PINMUX_H
-#define _NAS782X_PINMUX_H
-
-#include <asm/arch/cpu.h>
-
-#define PINMUX_GPIO 0
-#define PINMUX_2 1
-#define PINMUX_3 2
-#define PINMUX_4 3
-#define PINMUX_DEBUG 4
-#define PINMUX_ALT 5
-
-#define PINMUX_BANK_MFA 0
-#define PINMUX_BANK_MFB 1
-
-/* System control multi-function pin function selection */
-#define PINMUX_SECONDARY_SEL 0x14
-#define PINMUX_TERTIARY_SEL 0x8c
-#define PINMUX_QUATERNARY_SEL 0x94
-#define PINMUX_DEBUG_SEL 0x9c
-#define PINMUX_ALTERNATIVE_SEL 0xa4
-#define PINMUX_PULLUP_SEL 0xac
-
-#define PINMUX_UARTA_SIN PINMUX_ALT
-#define PINMUX_UARTA_SOUT PINMUX_ALT
-
-#define PINMUX_STATIC_DATA0 PINMUX_2
-#define PINMUX_STATIC_DATA1 PINMUX_2
-#define PINMUX_STATIC_DATA2 PINMUX_2
-#define PINMUX_STATIC_DATA3 PINMUX_2
-#define PINMUX_STATIC_DATA4 PINMUX_2
-#define PINMUX_STATIC_DATA5 PINMUX_2
-#define PINMUX_STATIC_DATA6 PINMUX_2
-#define PINMUX_STATIC_DATA7 PINMUX_2
-#define PINMUX_STATIC_NWE PINMUX_2
-#define PINMUX_STATIC_NOE PINMUX_2
-#define PINMUX_STATIC_NCS PINMUX_2
-#define PINMUX_STATIC_ADDR18 PINMUX_2
-#define PINMUX_STATIC_ADDR19 PINMUX_2
-
-#define PINMUX_MACA_MDC PINMUX_2
-#define PINMUX_MACA_MDIO PINMUX_2
-
-extern void pinmux_set(int bank, int pin, int func);
-
-#endif /* _NAS782X_PINMUX_H */
+++ /dev/null
-#ifndef _NAS782X_SPL_H
-#define _NAS782X_SPL_H
-
-#include <asm/arch/cpu.h>
-
-#endif /* _NAS782X_SPL_H */
+++ /dev/null
-#ifndef _NAS782X_SYSCTL_H
-#define _NAS782X_SYSCTL_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#include <asm/arch/hardware.h>
-
-/**
- * System block reset and clock control
- */
-#define SYS_CTRL_PCI_STAT (SYS_CONTROL_BASE + 0x20)
-#define SYS_CTRL_CLK_SET_CTRL (SYS_CONTROL_BASE + 0x2C)
-#define SYS_CTRL_CLK_CLR_CTRL (SYS_CONTROL_BASE + 0x30)
-#define SYS_CTRL_RST_SET_CTRL (SYS_CONTROL_BASE + 0x34)
-#define SYS_CTRL_RST_CLR_CTRL (SYS_CONTROL_BASE + 0x38)
-#define SYS_CTRL_PLLSYS_CTRL (SYS_CONTROL_BASE + 0x48)
-#define SYS_CTRL_PLLSYS_KEY_CTRL (SYS_CONTROL_BASE + 0x6C)
-#define SYS_CTRL_GMAC_CTRL (SYS_CONTROL_BASE + 0x78)
-
-/* Scratch registers */
-#define SYS_CTRL_SCRATCHWORD0 (SYS_CONTROL_BASE + 0xc4)
-#define SYS_CTRL_SCRATCHWORD1 (SYS_CONTROL_BASE + 0xc8)
-#define SYS_CTRL_SCRATCHWORD2 (SYS_CONTROL_BASE + 0xcc)
-#define SYS_CTRL_SCRATCHWORD3 (SYS_CONTROL_BASE + 0xd0)
-
-#define SYS_CTRL_PLLA_CTRL0 (SYS_CONTROL_BASE + 0x1F0)
-#define SYS_CTRL_PLLA_CTRL1 (SYS_CONTROL_BASE + 0x1F4)
-#define SYS_CTRL_PLLA_CTRL2 (SYS_CONTROL_BASE + 0x1F8)
-#define SYS_CTRL_PLLA_CTRL3 (SYS_CONTROL_BASE + 0x1FC)
-
-#define SYS_CTRL_GMAC_AUTOSPEED 3
-#define SYS_CTRL_GMAC_RGMII 2
-#define SYS_CTRL_GMAC_SIMPLE_MUX 1
-#define SYS_CTRL_GMAC_CKEN_GTX 0
-
-#define SYS_CTRL_CKCTRL_CTRL_ADDR (SYS_CONTROL_BASE + 0x64)
-
-#define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0
-#define SYS_CTRL_CKCTRL_SLOW_BIT 8
-
-
-#define SYS_CTRL_USBHSMPH_CTRL (SYS_CONTROL_BASE + 0x40)
-#define SYS_CTRL_USBHSMPH_STAT (SYS_CONTROL_BASE + 0x44)
-#define SYS_CTRL_REF300_DIV (SYS_CONTROL_BASE + 0xF8)
-#define SYS_CTRL_USBHSPHY_CTRL (SYS_CONTROL_BASE + 0x84)
-#define SYS_CTRL_USB_CTRL (SYS_CONTROL_BASE + 0x90)
-
-/* System control multi-function pin function selection */
-#define SYS_CTRL_SECONDARY_SEL (SYS_CONTROL_BASE + 0x14)
-#define SYS_CTRL_TERTIARY_SEL (SYS_CONTROL_BASE + 0x8c)
-#define SYS_CTRL_QUATERNARY_SEL (SYS_CONTROL_BASE + 0x94)
-#define SYS_CTRL_DEBUG_SEL (SYS_CONTROL_BASE + 0x9c)
-#define SYS_CTRL_ALTERNATIVE_SEL (SYS_CONTROL_BASE + 0xa4)
-#define SYS_CTRL_PULLUP_SEL (SYS_CONTROL_BASE + 0xac)
-
-/* Secure control multi-function pin function selection */
-#define SEC_CTRL_SECONDARY_SEL (SEC_CONTROL_BASE + 0x14)
-#define SEC_CTRL_TERTIARY_SEL (SEC_CONTROL_BASE + 0x8c)
-#define SEC_CTRL_QUATERNARY_SEL (SEC_CONTROL_BASE + 0x94)
-#define SEC_CTRL_DEBUG_SEL (SEC_CONTROL_BASE + 0x9c)
-#define SEC_CTRL_ALTERNATIVE_SEL (SEC_CONTROL_BASE + 0xa4)
-#define SEC_CTRL_PULLUP_SEL (SEC_CONTROL_BASE + 0xac)
-
-#define SEC_CTRL_COPRO_CTRL (SEC_CONTROL_BASE + 0x68)
-#define SEC_CTRL_SECURE_CTRL (SEC_CONTROL_BASE + 0x98)
-#define SEC_CTRL_LEON_DEBUG (SEC_CONTROL_BASE + 0xF0)
-#define SEC_CTRL_PLLB_DIV_CTRL (SEC_CONTROL_BASE + 0xF8)
-#define SEC_CTRL_PLLB_CTRL0 (SEC_CONTROL_BASE + 0x1F0)
-#define SEC_CTRL_PLLB_CTRL1 (SEC_CONTROL_BASE + 0x1F4)
-#define SEC_CTRL_PLLB_CTRL8 (SEC_CONTROL_BASE + 0x1F4)
-
-#define REF300_DIV_INT_SHIFT 8
-#define REF300_DIV_FRAC_SHIFT 0
-#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
-#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
-
-#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16
-#define USBHSPHY_SUSPENDM_MANUAL_STATE 15
-#define USBHSPHY_ATE_ESET 14
-#define USBHSPHY_TEST_DIN 6
-#define USBHSPHY_TEST_ADD 2
-#define USBHSPHY_TEST_DOUT_SEL 1
-#define USBHSPHY_TEST_CLK 0
-
-#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5
-#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-
-#define USBAMUX_DEVICE BIT(4)
-
-#define USBPHY_REFCLKDIV_SHIFT 2
-#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT)
-
-#define USB_CTRL_USB_CKO_SEL_BIT 0
-
-#define USB_INT_CLK_XTAL 0
-#define USB_INT_CLK_REF300 2
-#define USB_INT_CLK_PLLB 3
-
-#define SYS_CTRL_GMAC_AUTOSPEED 3
-#define SYS_CTRL_GMAC_RGMII 2
-#define SYS_CTRL_GMAC_SIMPLE_MUX 1
-#define SYS_CTRL_GMAC_CKEN_GTX 0
-
-
-#define PLLB_ENSAT 3
-#define PLLB_OUTDIV 4
-#define PLLB_REFDIV 8
-#define PLLB_DIV_INT_SHIFT 8
-#define PLLB_DIV_FRAC_SHIFT 0
-#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
-#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#endif /* _NAS782X_SYSCTL_H */
+++ /dev/null
-#ifndef _NAS782X_TIMER_H
-#define _NAS782X_TIMER_H
-
-#define TIMER1_BASE (RPSA_BASE + 0x200)
-#define TIMER2_BASE (RPSA_BASE + 0x220)
-
-#define TIMER_LOAD 0
-#define TIMER_CURR 4
-#define TIMER_CTRL 8
-#define TIMER_INTR 0x0C
-
-#define TIMER_PRESCALE_SHIFT 2
-#define TIMER_PRESCALE_1 0
-#define TIMER_PRESCALE_16 1
-#define TIMER_PRESCALE_256 2
-#define TIMER_MODE_SHIFT 6
-#define TIMER_MODE_FREE_RUNNING 0
-#define TIMER_MODE_PERIODIC 1
-#define TIMER_ENABLE_SHIFT 7
-#define TIMER_DISABLE 0
-#define TIMER_ENABLE 1
-
-#endif /* _NAS782X_TIMER_H */
+++ /dev/null
-if TARGET_OX820
-
-config SYS_CPU
- default "arm1136"
-
-config SYS_SOC
- default "nas782x"
-
-config SYS_BOARD
- default "ox820"
-
-config SYS_CONFIG_NAME
- default "ox820"
-
-endif
+++ /dev/null
-SHEEVAPLUG BOARD
-M: Daniel Golle <daniel@makrotopia.org>
-S: Maintained
-F: board/ox820/
-F: include/configs/ox820.h
-F: configs/ox820_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ox820.o
-obj-y += lowlevel_init.o
-
-obj-$(CONFIG_SPL_BUILD) += spl_start.o
-obj-$(CONFIG_SPL_BUILD) += ddr.o
-
+++ /dev/null
-/*******************************************************************
- *
- * File: ddr_oxsemi.c
- *
- * Description: Declarations for DDR routines and data objects
- *
- * Author: Julien Margetts
- *
- * Copyright: Oxford Semiconductor Ltd, 2009
- */
-#include <common.h>
-#include <asm/arch/clock.h>
-
-#include "ddr.h"
-
-typedef unsigned int UINT;
-
-// DDR TIMING PARAMETERS
-typedef struct {
- unsigned int holdoff_cmd_A;
- unsigned int holdoff_cmd_ARW;
- unsigned int holdoff_cmd_N;
- unsigned int holdoff_cmd_LM;
- unsigned int holdoff_cmd_R;
- unsigned int holdoff_cmd_W;
- unsigned int holdoff_cmd_PC;
- unsigned int holdoff_cmd_RF;
- unsigned int holdoff_bank_R;
- unsigned int holdoff_bank_W;
- unsigned int holdoff_dir_RW;
- unsigned int holdoff_dir_WR;
- unsigned int holdoff_FAW;
- unsigned int latency_CAS;
- unsigned int latency_WL;
- unsigned int recovery_WR;
- unsigned int width_update;
- unsigned int odt_offset;
- unsigned int odt_drive_all;
- unsigned int use_fixed_re;
- unsigned int delay_wr_to_re;
- unsigned int wr_slave_ratio;
- unsigned int rd_slave_ratio0;
- unsigned int rd_slave_ratio1;
-} T_DDR_TIMING_PARAMETERS;
-
-// DDR CONFIG PARAMETERS
-
-typedef struct {
- unsigned int ddr_mode;
- unsigned int width;
- unsigned int blocs;
- unsigned int banks8;
- unsigned int rams;
- unsigned int asize;
- unsigned int speed;
- unsigned int cmd_mode_wr_cl_bl;
-} T_DDR_CONFIG_PARAMETERS;
-
-//cmd_mode_wr_cl_bl
-//when SDR : cmd_mode_wr_cl_bl = 0x80200002 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
-//else cmd_mode_wr_cl_bl = 0x80200003 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
-
-// cmd_ bank_ dir_ lat_ rec_ width_ odt_ odt_ fix delay ratio
-// A F C update offset all re re_to_we w r0 r1
-// R L P R R W A A W W
-//Timing Parameters A W N M R W C F R W W R W S L R
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_1GB = { 4, 5, 0, 2, 4, 4,
- 5, 51, 23, 24, 9, 11, 18, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; //elida device.
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_2GB = { 4, 5, 0, 2, 4, 4,
- 5, 79, 22, 24, 9, 11, 20, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 };
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25_CL6_1GB = { 4, 5, 0, 2, 4, 4,
- 4, 51, 22, 26, 10, 12, 18, 6, 5, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; // 400MHz, Speedgrade 25 timings (1Gb parts)
-
-// D B B R A S
-// D W L K A S P
-//Config Parameters R D C 8 M Z D CMD_MODE
-//static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2,16, 1, 0, 1, 32,25,0x80200A53}; // 64 MByte
-static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2, 16, 1, 1, 1, 64,
- 25, 0x80200A53 }; // 128 MByte
-static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25_CL6 = { 2, 16, 1, 1, 1, 128,
- 25, 0x80200A63 }; // 256 MByte
-
-static void ddr_phy_poll_until_locked(void)
-{
- volatile UINT reg_tmp = 0;
- volatile UINT locked = 0;
-
- //Extra read to put in delay before starting to poll...
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
-
- //POLL C_DDR_PHY2_REG register until clock and flock
- //!!! Ideally have a timeout on this.
- while (locked == 0) {
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
-
- //locked when bits 30 and 31 are set
- if (reg_tmp & 0xC0000000) {
- locked = 1;
- }
- }
-}
-
-static void ddr_poll_until_not_busy(void)
-{
- volatile UINT reg_tmp = 0;
- volatile UINT busy = 1;
-
- //Extra read to put in delay before starting to poll...
- reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read
-
- //POLL DDR_STAT register until no longer busy
- //!!! Ideally have a timeout on this.
- while (busy == 1) {
- reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read
-
- //when bit 31 is clear - core is no longer busy
- if ((reg_tmp & 0x80000000) == 0x00000000) {
- busy = 0;
- }
- }
-}
-
-static void ddr_issue_command(int commmand)
-{
- *(volatile UINT *) C_DDR_CMD_REG = commmand;
- ddr_poll_until_not_busy();
-}
-
-static void ddr_timing_initialisation(
- const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters)
-{
- volatile UINT reg_tmp = 0;
- /* update the DDR controller registers for timing parameters */
- reg_tmp = (ddr_timing_parameters->holdoff_cmd_A << 0);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_ARW << 4);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_N << 8);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_LM << 12);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_R << 16);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_W << 20);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_PC << 24);
- *(volatile UINT *) C_DDR_REG_TIMING0 = reg_tmp;
-
- reg_tmp = (ddr_timing_parameters->holdoff_cmd_RF << 0);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_R << 8);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_W << 16);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_RW << 24);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_WR << 28);
- *(volatile UINT *) C_DDR_REG_TIMING1 = reg_tmp;
-
- reg_tmp = (ddr_timing_parameters->latency_CAS << 0);
- reg_tmp = reg_tmp + (ddr_timing_parameters->latency_WL << 4);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_FAW << 8);
- reg_tmp = reg_tmp + (ddr_timing_parameters->width_update << 16);
- reg_tmp = reg_tmp + (ddr_timing_parameters->odt_offset << 21);
- reg_tmp = reg_tmp + (ddr_timing_parameters->odt_drive_all << 24);
-
- *(volatile UINT *) C_DDR_REG_TIMING2 = reg_tmp;
-
- /* Program the timing parameters in the PHY too */
- reg_tmp = (ddr_timing_parameters->use_fixed_re << 16)
- | (ddr_timing_parameters->delay_wr_to_re << 8)
- | (ddr_timing_parameters->latency_WL << 4)
- | (ddr_timing_parameters->latency_CAS << 0);
-
- *(volatile UINT *) C_DDR_REG_PHY_TIMING = reg_tmp;
-
- reg_tmp = ddr_timing_parameters->wr_slave_ratio;
-
- *(volatile UINT *) C_DDR_REG_PHY_WR_RATIO = reg_tmp;
-
- reg_tmp = ddr_timing_parameters->rd_slave_ratio0;
- reg_tmp += ddr_timing_parameters->rd_slave_ratio1 << 8;
-
- *(volatile UINT *) C_DDR_REG_PHY_RD_RATIO = reg_tmp;
-
-}
-
-static void ddr_normal_initialisation(
- const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters, int mhz)
-{
- int i;
- volatile UINT tmp = 0;
- volatile UINT reg_tmp = 0;
- volatile UINT emr_cmd = 0;
- UINT refresh;
-
- //Total size of memory in Mbits...
- tmp = ddr_config_parameters->rams * ddr_config_parameters->asize
- * ddr_config_parameters->width;
- //Deduce value to program into DDR_CFG register...
- switch (tmp) {
- case 16:
- reg_tmp = 0x00020000 * 1;
- break;
- case 32:
- reg_tmp = 0x00020000 * 2;
- break;
- case 64:
- reg_tmp = 0x00020000 * 3;
- break;
- case 128:
- reg_tmp = 0x00020000 * 4;
- break;
- case 256:
- reg_tmp = 0x00020000 * 5;
- break;
- case 512:
- reg_tmp = 0x00020000 * 6;
- break;
- case 1024:
- reg_tmp = 0x00020000 * 7;
- break;
- case 2048:
- reg_tmp = 0x00020000 * 8;
- break;
- default:
- reg_tmp = 0; //forces sims not to work if badly configured
- }
-
- //Memory width
- tmp = ddr_config_parameters->rams * ddr_config_parameters->width;
- switch (tmp) {
- case 8:
- reg_tmp = reg_tmp + 0x00400000;
- break;
- case 16:
- reg_tmp = reg_tmp + 0x00200000;
- break;
- case 32:
- reg_tmp = reg_tmp + 0x00000000;
- break;
- default:
- reg_tmp = 0; //forces sims not to work if badly configured
- }
-
- //Setup DDR Mode
- switch (ddr_config_parameters->ddr_mode) {
- case 0:
- reg_tmp = reg_tmp + 0x00000000;
- break; //SDR
- case 1:
- reg_tmp = reg_tmp + 0x40000000;
- break; //DDR
- case 2:
- reg_tmp = reg_tmp + 0x80000000;
- break; //DDR2
- default:
- reg_tmp = 0; //forces sims not to work if badly configured
- }
-
- //Setup Banks
- if (ddr_config_parameters->banks8 == 1) {
- reg_tmp = reg_tmp + 0x00800000;
- }
-
- //Program DDR_CFG register...
- *(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
-
- //Configure PHY0 reg - se_mode is bit 1,
- //needs to be 1 for DDR (single_ended drive)
- switch (ddr_config_parameters->ddr_mode) {
- case 0:
- reg_tmp = 2 + (0 << 4);
- break; //SDR
- case 1:
- reg_tmp = 2 + (4 << 4);
- break; //DDR
- case 2:
- reg_tmp = 0 + (4 << 4);
- break; //DDR2
- default:
- reg_tmp = 0;
- }
-
- //Program DDR_PHY0 register...
- *(volatile UINT *) C_DDR_REG_PHY0 = reg_tmp;
-
- //Read DDR_PHY* registers to exercise paths for vcd
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY3;
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY1;
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY0;
-
- //Start up sequences - Different dependant on DDR mode
- switch (ddr_config_parameters->ddr_mode) {
- case 2: //DDR2
- //Start-up sequence: follows procedure described in Micron datasheet.
- //start up DDR PHY DLL
- reg_tmp = 0x00022828; // dll on, start point and inc = h28
- *(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
-
- reg_tmp = 0x00032828; // start on, dll on, start point and inc = h28
- *(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
-
- ddr_phy_poll_until_locked();
-
- udelay(200); //200us
-
- //Startup SDRAM...
- //!!! Software: CK should be running for 200us before wake-up
- ddr_issue_command( C_CMD_WAKE_UP);
- ddr_issue_command( C_CMD_NOP);
- ddr_issue_command( C_CMD_PRECHARGE_ALL);
- ddr_issue_command( C_CMD_DDR2_EMR2);
- ddr_issue_command( C_CMD_DDR2_EMR3);
-
- emr_cmd = C_CMD_DDR2_EMR1 + C_CMD_ODT_75 + C_CMD_REDUCED_DRIVE
- + C_CMD_ENABLE_DLL;
-
- ddr_issue_command(emr_cmd);
- //Sets CL=3; BL=8 but also reset DLL to trigger a DLL initialisation...
- udelay(1); //1us
- ddr_issue_command(
- ddr_config_parameters->cmd_mode_wr_cl_bl
- + C_CMD_RESET_DLL);
- udelay(1); //1us
-
- //!!! Software: Wait 200 CK cycles before...
- //for(i=1; i<=2; i++) {
- ddr_issue_command(C_CMD_PRECHARGE_ALL);
- // !!! Software: Wait here at least 8 CK cycles
- //}
- //need a wait here to ensure PHY DLL lock before the refresh is issued
- udelay(1); //1us
- for (i = 1; i <= 2; i++) {
- ddr_issue_command( C_CMD_AUTO_REFRESH);
- //!!! Software: Wait here at least 8 CK cycles to satify tRFC
- udelay(1); //1us
- }
- //As before but without 'RESET_DLL' bit set...
- ddr_issue_command(ddr_config_parameters->cmd_mode_wr_cl_bl);
- udelay(1); //1us
- // OCD commands
- ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_DFLT);
- ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_EXIT);
- break;
-
- default:
- break; //Do nothing
- }
-
- //Enable auto-refresh
-
- // 8192 Refreshes required every 64ms, so maximum refresh period is 7.8125 us
- // We have a 400 MHz DDR clock (2.5ns period) so max period is 3125 cycles
- // Our core now does 8 refreshes in a go, so we multiply this period by 8
-
- refresh = (64000 * mhz) / 8192; // Refresh period in clocks
-
- reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read
-#ifdef BURST_REFRESH_ENABLE
- reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 8);
- reg_tmp |= C_CFG_BURST_REFRESH_ENABLE;
-#else
- reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 1);
- reg_tmp &= ~C_CFG_BURST_REFRESH_ENABLE;
-#endif
- *(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
-
- //Verify register contents
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
- //printf("Warning XXXXXXXXXXXXXXXXXXXXXX - get bad read data from C_DDR_PHY2_REG, though it looks OK on bus XXXXXXXXXXXXXXXXXX");
- //TBD Check_data (read_data, dll_reg, "Error: bad C_DDR_PHY2_REG read", tb_pass);
- reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read
- //TBD Check_data (read_data, cfg_reg, "Error: bad DDR_CFG read", tb_pass);
-
- //disable optimised wrapping
- if (ddr_config_parameters->ddr_mode == 2) {
- reg_tmp = 0xFFFF0000;
- *(volatile UINT *) C_DDR_REG_IGNORE = reg_tmp;
- }
-
- //enable midbuffer followon
- reg_tmp = *(volatile UINT *) C_DDR_ARB_REG; // read
- reg_tmp = 0xFFFF0000 | reg_tmp;
- *(volatile UINT *) C_DDR_ARB_REG = reg_tmp;
-
- // Enable write behind coherency checking for all clients
-
- reg_tmp = 0xFFFF0000;
- *(volatile UINT *) C_DDR_AHB4_REG = reg_tmp;
-
- //Wait for 200 clock cycles for SDRAM DLL to lock...
- udelay(1); //1us
-}
-
-// Function used to Setup DDR core
-
-void ddr_setup(int mhz)
-{
- static const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters =
- &C_TP_DDR2_25_CL6_1GB;
- static const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters =
- &C_CP_DDR2_25_CL6;
-
- //Bring core out of Reset
- *(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON;
-
- //DDR TIMING INITIALISTION
- ddr_timing_initialisation(ddr_timing_parameters);
-
- //DDR NORMAL INITIALISATION
- ddr_normal_initialisation(ddr_config_parameters, mhz);
-
- // route all writes through one client
- *(volatile UINT *) C_DDR_TRANSACTION_ROUTING = (0
- << DDR_ROUTE_CPU0_INSTR_SHIFT)
- | (1 << DDR_ROUTE_CPU0_RDDATA_SHIFT)
- | (3 << DDR_ROUTE_CPU0_WRDATA_SHIFT)
- | (2 << DDR_ROUTE_CPU1_INSTR_SHIFT)
- | (3 << DDR_ROUTE_CPU1_RDDATA_SHIFT)
- | (3 << DDR_ROUTE_CPU1_WRDATA_SHIFT);
-
- //Bring all clients out of reset
- *(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON + 0x0000FFFF;
-
-}
-
-void set_ddr_timing(unsigned int w, unsigned int i)
-{
- unsigned int reg;
- unsigned int wnow = 16;
- unsigned int inow = 32;
-
- /* reset all timing controls to known value (31) */
- writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST | DDR_PHY_TIMING_CK,
- DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
-
- /* step up or down read delay to the requested value */
- while (wnow != w) {
- if (wnow < w) {
- reg = DDR_PHY_TIMING_INC;
- wnow++;
- } else {
- reg = 0;
- wnow--;
- }
- writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_W_CE | reg,
- DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
- }
-
- /* now write delay */
- while (inow != i) {
- if (inow < i) {
- reg = DDR_PHY_TIMING_INC;
- inow++;
- } else {
- reg = 0;
- inow--;
- }
- writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_I_CE | reg,
- DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
- }
-}
-
-//Function used to Setup SDRAM in DDR/SDR mode
-void init_ddr(int mhz)
-{
- /* start clocks */
- enable_clock(SYS_CTRL_CLK_DDRPHY);
- enable_clock(SYS_CTRL_CLK_DDR);
- enable_clock(SYS_CTRL_CLK_DDRCK);
-
- /* bring phy and core out of reset */
- reset_block(SYS_CTRL_RST_DDR_PHY, 0);
- reset_block(SYS_CTRL_RST_DDR, 0);
-
- /* DDR runs at half the speed of the CPU */
- ddr_setup(mhz >> 1);
- return;
-}
+++ /dev/null
-/*******************************************************************
-*
-* File: ddr_oxsemi.h
-*
-* Description: Declarations for DDR routines and data objects
-*
-* Author: Julien Margetts
-*
-* Copyright: Oxford Semiconductor Ltd, 2009
-*/
-
-void ddr_oxsemi_setup(int mhz);
-
-/* define to refresh in bursts of 8 */
-#define BURST_REFRESH_ENABLE
-
-#define DDR_BASE 0x44700000
-
-#define C_DDR_CFG_REG (DDR_BASE + 0x00)
-#define C_CFG_DDR 0x80000000
-#define C_CFG_SDR 0x00000000
-#define C_CFG_WIDTH8 0x00200000
-#define C_CFG_WIDTH16 0x00100000
-#define C_CFG_WIDTH32 0x00000000
-#define C_CFG_SIZE_FACTOR 0x00020000
-#define C_CFG_REFRESH_ENABLE 0x00010000
-#define C_CFG_BURST_REFRESH_ENABLE 0x01000000
-#define C_CFG_SIZE(x) (x << 17)
-#define CFG_SIZE_2MB 1
-#define CFG_SIZE_4MB 2
-#define CFG_SIZE_8MB 3
-#define CFG_SIZE_16MB 4
-#define CFG_SIZE_32MB 5
-#define CFG_SIZE_64MB 6
-#define CFG_SIZE_128MB 7
-
-#define C_DDR_BLKEN_REG (DDR_BASE + 0x04)
-#define C_BLKEN_DDR_ON 0x80000000
-
-#define C_DDR_STAT_REG (DDR_BASE + 0x08)
-
-#define C_DDR_CMD_REG (DDR_BASE + 0x0C)
-#define C_CMD_SEND_COMMAND (1UL << 31) | (1 << 21) // RAS/CAS/WE/CS all low(active), CKE High, indicates
-#define C_CMD_WAKE_UP 0x80FC0000 // Asserts CKE
-#define C_CMD_MODE_SDR 0x80200022 // Sets CL=2 BL=4
-#define C_CMD_MODE_DDR 0x80200063 // Sets CL=2.5 BL=8
-#define C_CMD_RESET_DLL 0x00000100 // A8=1 Use in conjunction with C_CMD_MODE_DDR
-#define C_CMD_PRECHARGE_ALL 0x80280400
-#define C_CMD_AUTO_REFRESH 0x80240000
-#define C_CMD_SELF_REFRESH 0x80040000 // As AUTO-REFRESH but with CKE low
-#define C_CMD_NOP 0x803C0000 // NOP just to insert guaranteed delay
-#define C_CMD_DDR2_EMR1 0x80210000 // Load extended mode register 1 with zeros (for init), CKE still set
-//#define C_CMD_DDR2_EMR1 0x80210400 // Load extended mode register 1 with zeros (for init), CKE still set
-#define C_CMD_ENABLE_DLL 0x00000000 // Values used in conjuction with C_CMD_DDR2_EMR1
-#define C_CMD_DISABLE_DLL 0x00000001
-#define C_CMD_REDUCED_DRIVE 0x00000002
-#define C_CMD_ODT_DISABLED 0x00000000
-#define C_CMD_ODT_50 0x00000044
-#define C_CMD_ODT_75 0x00000004
-#define C_CMD_ODT_150 0x00000040
-#define C_CMD_MODE_DDR2_OCD_DFLT 0x00000380
-#define C_CMD_MODE_DDR2_OCD_EXIT 0x00000000
-
-#define C_CMD_DDR2_EMR2 0x80220000 // Load extended mode register 2 with zeros (for init), CKE still set
-#define C_CMD_DDR2_EMR3 0x80230000 // Load extended mode register 3 with zeros (for init), CKE still set
-
-#define C_DDR_AHB_REG (DDR_BASE + 0x10)
-#define C_AHB_NO_RCACHES 0xFFFF0000
-#define C_AHB_FLUSH_ALL_RCACHES 0x0000FFFF
-#define C_AHB_FLUSH_AHB0_RCACHE 0x00000001
-#define C_AHB_FLUSH_AHB1_RCACHE 0x00000002
-
-#define C_DDR_DLL_REG (DDR_BASE + 0x14)
-#define C_DLL_DISABLED 0x00000000
-#define C_DLL_MANUAL 0x80000000
-#define C_DLL_AUTO_OFFSET 0xA0000000
-#define C_DLL_AUTO_IN_REFRESH 0xC0000000
-#define C_DLL_AUTOMATIC 0xE0000000
-
-#define C_DDR_MON_REG (DDR_BASE + 0x18)
-#define C_MON_ALL 0x00000010
-#define C_MON_CLIENT 0x00000000
-
-#define C_DDR_DIAG_REG (DDR_BASE + 0x1C)
-#define C_DDR_DIAG2_REG (DDR_BASE + 0x20)
-
-#define C_DDR_IOC_REG (DDR_BASE + 0x24)
-#define C_DDR_IOC_PWR_DWN (1 << 10)
-#define C_DDR_IOC_SEL_SSTL (1 << 9)
-#define C_DDR_IOC_CK_DRIVE(x) ((x) << 6)
-#define C_DDR_IOC_DQ_DRIVE(x) ((x) << 3)
-#define C_DDR_IOC_XX_DRIVE(x) ((x) << 0)
-
-#define C_DDR_ARB_REG (DDR_BASE + 0x28)
-#define C_DDR_ARB_MIDBUF (1 << 4)
-#define C_DDR_ARB_LRUBANK (1 << 3)
-#define C_DDR_ARB_REQAGE (1 << 2)
-#define C_DDR_ARB_DATDIR (1 << 1)
-#define C_DDR_ARB_DATDIR_NC (1 << 0)
-
-#define C_TOP_ADDRESS_BIT_TEST 22
-#define C_MEM_BASE C_SDRAM_BASE
-
-#define C_MEM_TEST_BASE 0
-#define C_MEM_TEST_LEN 1920
-#define C_MAX_RAND_ACCESS_LEN 16
-
-#define C_DDR_REG_IGNORE (DDR_BASE + 0x2C)
-#define C_DDR_AHB4_REG (DDR_BASE + 0x44)
-
-#define C_DDR_REG_TIMING0 (DDR_BASE + 0x34)
-#define C_DDR_REG_TIMING1 (DDR_BASE + 0x38)
-#define C_DDR_REG_TIMING2 (DDR_BASE + 0x3C)
-
-#define C_DDR_REG_PHY0 (DDR_BASE + 0x48)
-#define C_DDR_REG_PHY1 (DDR_BASE + 0x4C)
-#define C_DDR_REG_PHY2 (DDR_BASE + 0x50)
-#define C_DDR_REG_PHY3 (DDR_BASE + 0x54)
-
-#define C_DDR_REG_GENERIC (DDR_BASE + 0x60)
-
-#define C_OXSEMI_DDRC_SIGNATURE 0x054415AA
-
-#define DDR_PHY_BASE (DDR_BASE + 0x80000)
-#define DDR_PHY_TIMING (DDR_PHY_BASE + 0x48)
-#define DDR_PHY_TIMING_CK (1 << 12)
-#define DDR_PHY_TIMING_INC (1 << 13)
-#define DDR_PHY_TIMING_W_CE (1 << 14)
-#define DDR_PHY_TIMING_W_RST (1 << 15)
-#define DDR_PHY_TIMING_I_CE (1 << 16)
-#define DDR_PHY_TIMING_I_RST (1 << 17)
-
-#define C_DDR_REG_PHY_TIMING (DDR_PHY_BASE + 0x50)
-#define C_DDR_REG_PHY_WR_RATIO (DDR_PHY_BASE + 0x74)
-#define C_DDR_REG_PHY_RD_RATIO (DDR_PHY_BASE + 0x78)
-
-#define C_DDR_TRANSACTION_ROUTING (DDR_PHY_BASE + 0xC8)
-#define DDR_ROUTE_CPU0_INSTR_SHIFT 0
-#define DDR_ROUTE_CPU0_RDDATA_SHIFT 4
-#define DDR_ROUTE_CPU0_WRDATA_SHIFT 6
-#define DDR_ROUTE_CPU1_INSTR_SHIFT 8
-#define DDR_ROUTE_CPU1_RDDATA_SHIFT 12
-#define DDR_ROUTE_CPU1_WRDATA_SHIFT 14
-
-unsigned int ddrc_signature(void);
-void set_ddr_timing(unsigned int w, unsigned int i);
-int pause(unsigned int us);
-void set_ddr_sel(int val);
+++ /dev/null
-#include <config.h>
-#ifndef CONFIG_SPL_BUILD
-
-.globl lowlevel_init
-lowlevel_init:
- /*
- * Copy exception table to relocated address in internal SRAM
- */
- ldr r0, src /* Address of exception table in flash */
- ldr r1, dest /* Relocated address of exception table */
- ldmia r0!, {r3-r10} /* Copy exception table and jump values from */
- stmia r1!, {r3-r10} /* FLASH to relocated address */
- ldmia r0!, {r3-r10}
- stmia r1!, {r3-r10}
- mov pc, lr
-
-src: .word CONFIG_SYS_TEXT_BASE
-dest: .word CONFIG_SRAM_BASE
-
-#endif
\ No newline at end of file
+++ /dev/null
-#include <common.h>
-#include <spl.h>
-#include <phy.h>
-#include <netdev.h>
-#include <ide.h>
-#include <nand.h>
-#include <asm/arch/spl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sysctl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SPL_BUILD
-
-#ifdef DEBUG
-#define DILIGENCE (1048576/4)
-static int test_memory(u32 memory)
-{
- volatile u32 *read;
- volatile u32 *write;
- const u32 INIT_PATTERN = 0xAA55AA55;
- const u32 INC_PATTERN = 0x01030507;
- u32 pattern;
- int check;
- int i;
-
- check = 0;
- read = write = (volatile u32 *) memory;
- pattern = INIT_PATTERN;
- for (i = 0; i < DILIGENCE; i++) {
- *write++ = pattern;
- pattern += INC_PATTERN;
- }
- puts("testing\n");
- pattern = INIT_PATTERN;
- for (i = 0; i < DILIGENCE; i++) {
- check += (pattern == *read++) ? 1 : 0;
- pattern += INC_PATTERN;
- }
- return (check == DILIGENCE) ? 0 : -1;
-}
-#endif
-
-void uart_init(void)
-{
- /* Reset UART1 */
- reset_block(SYS_CTRL_RST_UART1, 1);
- udelay(100);
- reset_block(SYS_CTRL_RST_UART1, 0);
- udelay(100);
-
- /* Setup pin mux'ing for UART1 */
- pinmux_set(PINMUX_BANK_MFA, 30, PINMUX_UARTA_SIN);
- pinmux_set(PINMUX_BANK_MFA, 31, PINMUX_UARTA_SOUT);
-}
-
-extern void init_ddr(int mhz);
-
-void board_inithw(void)
-{
- int plla_freq;
-#ifdef DEBUG
- int i;
-#endif /* DEBUG */
-
- timer_init();
- uart_init();
- preloader_console_init();
-
- plla_freq = plla_set_config(CONFIG_PLLA_FREQ_MHZ);
- init_ddr(plla_freq);
-
-#ifdef DEBUG
- if(test_memory(CONFIG_SYS_SDRAM_BASE)) {
- puts("memory test failed\n");
- } else {
- puts("memory test done\n");
- }
-#endif /* DEBUG */
-#ifdef CONFIG_SPL_BSS_DRAM_START
- extern char __bss_dram_start[];
- extern char __bss_dram_end[];
- memset(&__bss_dram_start, 0, __bss_dram_end - __bss_dram_start);
-#endif
-}
-
-void board_init_f(ulong dummy)
-{
- /* Set the stack pointer. */
- asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* Set global data pointer. */
- gd = &gdata;
-
- board_inithw();
-
- board_init_r(NULL, 0);
-}
-
-u32 spl_boot_device(void)
-{
- return CONFIG_SPL_BOOT_DEVICE;
-}
-
-#ifdef CONFIG_SPL_BLOCK_SUPPORT
-void spl_block_device_init(void)
-{
- ide_init();
-}
-#endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- return (serial_tstc() && serial_getc() == 'c');
-}
-#endif
-
-void spl_display_print(void)
-{
- /* print a hint, so that we will not use the wrong SPL by mistake */
- puts(" Boot device: " BOOT_DEVICE_TYPE "\n" );
-}
-
-void lowlevel_init(void)
-{
-}
-
-#ifdef USE_DL_PREFIX
-/* quick and dirty memory allocation */
-static ulong next_mem = CONFIG_SPL_MALLOC_START;
-
-void *memalign(size_t alignment, size_t bytes)
-{
- ulong mem = ALIGN(next_mem, alignment);
-
- next_mem = mem + bytes;
-
- if (next_mem > CONFIG_SYS_SDRAM_BASE + CONFIG_MIN_SDRAM_SIZE) {
- printf("spl: out of memory\n");
- hang();
- }
-
- return (void *)mem;
-}
-
-void free(void* mem)
-{
-}
-#endif
-
-#endif /* CONFIG_SPL_BUILD */
-
-int board_early_init_f(void)
-{
- return 0;
-}
-
-#define STATIC_CTL_BANK0 (STATIC_CONTROL_BASE + 4)
-#define STATIC_READ_CYCLE_SHIFT 0
-#define STATIC_DELAYED_OE (1 << 7)
-#define STATIC_WRITE_CYCLE_SHIFT 8
-#define STATIC_WRITE_PULSE_SHIFT 16
-#define STATIC_WRITE_BURST_EN (1 << 23)
-#define STATIC_TURN_AROUND_SHIFT 24
-#define STATIC_BUFFER_PRESENT (1 << 28)
-#define STATIC_READ_BURST_EN (1 << 29)
-#define STATIC_BUS_WIDTH8 (0 << 30)
-#define STATIC_BUS_WIDTH16 (1 << 30)
-#define STATIC_BUS_WIDTH32 (2 << 30)
-
-void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
- unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- nandaddr &= ~(BIT(NAND_ALE_ADDR_PIN) | BIT(NAND_CLE_ADDR_PIN));
- if (ctrl & NAND_CLE)
- nandaddr |= BIT(NAND_CLE_ADDR_PIN);
- else if (ctrl & NAND_ALE)
- nandaddr |= BIT(NAND_ALE_ADDR_PIN);
- this->IO_ADDR_W = (void __iomem *) nandaddr;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, (void __iomem *) nandaddr);
-}
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOOT_FROM_NAND)
-
-int nand_dev_ready(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
-
- udelay(chip->chip_delay);
-
- return 1;
-}
-
-void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
-
- for (i = 0; i < len; i++)
- buf[i] = readb(chip->IO_ADDR_R);
-}
-
-void nand_dev_reset(struct nand_chip *chip)
-{
- writeb(NAND_CMD_RESET, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
- udelay(chip->chip_delay);
- writeb(NAND_CMD_STATUS, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
- while (!(readb(chip->IO_ADDR_R) & NAND_STATUS_READY)) {
- ;
- }
-}
-
-#else
-
-#define nand_dev_reset(chip) /* framework will reset the chip anyway */
-#define nand_read_buf NULL /* framework will provide a default one */
-#define nand_dev_ready NULL /* dev_ready is optional */
-
-#endif
-
-int board_nand_init(struct nand_chip *chip)
-{
- /* Block reset Static core */
- reset_block(SYS_CTRL_RST_STATIC, 1);
- reset_block(SYS_CTRL_RST_STATIC, 0);
-
- /* Enable clock to Static core */
- enable_clock(SYS_CTRL_CLK_STATIC);
-
- /* enable flash support on static bus.
- * Enable static bus onto GPIOs, only CS0 */
- pinmux_set(PINMUX_BANK_MFA, 12, PINMUX_STATIC_DATA0);
- pinmux_set(PINMUX_BANK_MFA, 13, PINMUX_STATIC_DATA1);
- pinmux_set(PINMUX_BANK_MFA, 14, PINMUX_STATIC_DATA2);
- pinmux_set(PINMUX_BANK_MFA, 15, PINMUX_STATIC_DATA3);
- pinmux_set(PINMUX_BANK_MFA, 16, PINMUX_STATIC_DATA4);
- pinmux_set(PINMUX_BANK_MFA, 17, PINMUX_STATIC_DATA5);
- pinmux_set(PINMUX_BANK_MFA, 18, PINMUX_STATIC_DATA6);
- pinmux_set(PINMUX_BANK_MFA, 19, PINMUX_STATIC_DATA7);
-
- pinmux_set(PINMUX_BANK_MFA, 20, PINMUX_STATIC_NWE);
- pinmux_set(PINMUX_BANK_MFA, 21, PINMUX_STATIC_NOE);
- pinmux_set(PINMUX_BANK_MFA, 22, PINMUX_STATIC_NCS);
- pinmux_set(PINMUX_BANK_MFA, 23, PINMUX_STATIC_ADDR18);
- pinmux_set(PINMUX_BANK_MFA, 24, PINMUX_STATIC_ADDR19);
-
- /* Setup the static bus CS0 to access FLASH */
-
- writel((0x3f << STATIC_READ_CYCLE_SHIFT)
- | (0x3f << STATIC_WRITE_CYCLE_SHIFT)
- | (0x1f << STATIC_WRITE_PULSE_SHIFT)
- | (0x03 << STATIC_TURN_AROUND_SHIFT) |
- STATIC_BUS_WIDTH16,
- STATIC_CTL_BANK0);
-
- chip->cmd_ctrl = nand_hwcontrol;
- chip->ecc.mode = NAND_ECC_SOFT;
- chip->chip_delay = 30;
- chip->dev_ready = nand_dev_ready;
- chip->read_buf = nand_read_buf;
-
- nand_dev_reset(chip);
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- gd->bd->bi_arch_number = MACH_TYPE_OXNAS;
-
- /* assume uart is already initialized by SPL */
-
-#if defined(CONFIG_START_IDE)
- puts("IDE: ");
- ide_init();
-#endif
-
- return 0;
-}
-
-/* copied from board/evb64260/sdram_init.c */
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-static long int dram_size (long int *base, long int maxsize)
-{
- volatile long int *addr, *b = base;
- long int cnt, val, save1, save2;
-
-#define STARTVAL (CONFIG_MIN_SDRAM_SIZE / 2) /* start test at half size */
- for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
- cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save1 = *addr; /* save contents of addr */
- save2 = *b; /* save contents of base */
-
- *addr = cnt; /* write cnt to addr */
- *b = 0; /* put null at base */
-
- /* check at base address */
- if ((*b) != 0) {
- *addr = save1; /* restore *addr */
- *b = save2; /* restore *b */
- return (0);
- }
- val = *addr; /* read *addr */
-
- *addr = save1;
- *b = save2;
-
- if (val != cnt) {
- /* fix boundary condition.. STARTVAL means zero */
- if (cnt == STARTVAL / sizeof (long))
- cnt = 0;
- return (cnt * sizeof (long));
- }
- }
- return maxsize;
-}
-
-int dram_init(void)
-{
- gd->ram_size = dram_size((long int *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_MAX_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- u32 value;
-
- /* set the pin multiplexers to enable talking to Ethernent Phys */
- pinmux_set(PINMUX_BANK_MFA, 3, PINMUX_MACA_MDC);
- pinmux_set(PINMUX_BANK_MFA, 4, PINMUX_MACA_MDIO);
-
- // Ensure the MAC block is properly reset
- reset_block(SYS_CTRL_RST_MAC, 1);
- udelay(10);
- reset_block(SYS_CTRL_RST_MAC, 0);
-
- // Enable the clock to the MAC block
- enable_clock(SYS_CTRL_CLK_MAC);
-
- value = readl(SYS_CTRL_GMAC_CTRL);
- /* Use simple mux for 25/125 Mhz clock switching */
- value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);
- /* Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY */
- value |= BIT(SYS_CTRL_GMAC_CKEN_GTX);
- /* set auto tx speed */
- value |= BIT(SYS_CTRL_GMAC_AUTOSPEED);
-
- writel(value, SYS_CTRL_GMAC_CTRL);
-
- return designware_initialize(MAC_BASE, PHY_INTERFACE_MODE_RGMII);
-}
-
+++ /dev/null
-.section .init
-.globl _spl_start
-_spl_start:
- b _start
- b _start+0x4
- b _start+0x8
- b _start+0xc
- b _start+0x10
- b _start+0x14
- b _start+0x18
- b _start+0x1c
- .space 0x30 - (. - _spl_start)
- .ascii "BOOT" /* 0x30 signature*/
- .word 0x50 /* 0x34 header size itself */
- .word 0 /* 0x38 */
- .word 0x5000f000 /* boot report location */
- .word _start /* 0x40 */
-
-main_crc_size: .word code_size /* 0x44 filled by linker */
-main_crc: .word 0 /* 0x48 fill later */
-header_crc: .word 0 /* 0x4C header crc*/
+++ /dev/null
-/*
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-MEMORY
-{
- sram (rwx) : ORIGIN = CONFIG_SPL_TEXT_BASE, LENGTH = CONFIG_SPL_MAX_SIZE
- dram : ORIGIN = CONFIG_SPL_BSS_DRAM_START, LENGTH = CONFIG_SPL_BSS_DRAM_SIZE
-}
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_spl_start)
-SECTIONS
-{
- .text.0 :
- {
- *(.init*)
- }
-
-
- /* Start of the rest of the SPL */
- code_start = . ;
-
- .text.1 :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- __image_copy_end = .;
- code_size = . - code_start;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- . = ALIGN(0x800);
-
- _end = .;
-
- .bss.sram __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss.stdio_devices)
- *(.bss.serial_current)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- .bss : {
- __bss_dram_start = .;
- *(.bss*)
- __bss_dram_end = .;
- } > dram
-
- /DISCARD/ : { *(.bss*) }
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynsym*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.hash*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-/*
- * (c) Copyright 2011 by Tigris Elektronik GmbH
- *
- * Author:
- * Maximilian Schwerin <mvs@tigris.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include <command.h>
-#include <environment.h>
-#include <linux/stddef.h>
-#include <malloc.h>
-#include <search.h>
-#include <errno.h>
-#include <ext4fs.h>
-
-char *env_name_spec = "EXT4";
-
-env_t *env_ptr;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int env_init(void)
-{
- /* use default */
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 1;
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_SAVEENV
-int saveenv(void)
-{
- env_t env_new;
- ssize_t len;
- char *res;
- block_dev_desc_t *dev_desc = NULL;
- int dev = EXT4_ENV_DEVICE;
- int part = EXT4_ENV_PART;
- int err;
-
- res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
- if (len < 0) {
- error("Cannot export environment: errno = %d\n", errno);
- return 1;
- }
-
- dev_desc = get_dev(EXT4_ENV_INTERFACE, dev);
- if (dev_desc == NULL) {
- printf("Failed to find %s%d\n",
- EXT4_ENV_INTERFACE, dev);
- return 1;
- }
-
- err = ext4_register_device(dev_desc, part);
- if (err) {
- printf("Failed to register %s%d:%d\n",
- EXT4_ENV_INTERFACE, dev, part);
- return 1;
- }
-
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
- err = ext4fs_write(EXT4_ENV_FILE, (void *)&env_new, sizeof(env_t));
- ext4fs_close();
- if (err == -1) {
- printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
- EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
- return 1;
- }
-
- puts("done\n");
- return 0;
-}
-#endif /* CONFIG_CMD_SAVEENV */
-
-void env_relocate_spec(void)
-{
- char buf[CONFIG_ENV_SIZE];
- block_dev_desc_t *dev_desc = NULL;
- int dev = EXT4_ENV_DEVICE;
- int part = EXT4_ENV_PART;
- int err;
-
- dev_desc = get_dev(EXT4_ENV_INTERFACE, dev);
- if (dev_desc == NULL) {
- printf("Failed to find %s%d\n",
- EXT4_ENV_INTERFACE, dev);
- set_default_env(NULL);
- return;
- }
-
- err = ext4_register_device(dev_desc, part);
- if (err) {
- printf("Failed to register %s%d:%d\n",
- EXT4_ENV_INTERFACE, dev, part);
- set_default_env(NULL);
- return;
- }
-
- err = ext4_read_file(EXT4_ENV_FILE, (uchar *)&buf, 0, CONFIG_ENV_SIZE);
- ext4fs_close();
-
- if (err == -1) {
- printf("\n** Unable to read \"%s\" from %s%d:%d **\n",
- EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
- set_default_env(NULL);
- return;
- }
-
- env_import(buf, 1);
-}
+++ /dev/null
-/*
- * (C) Copyright 2013
- *
- * Ma Haijun <mahaijuns@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <spl.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-#include <version.h>
-#include <part.h>
-#include <fat.h>
-#include <ext4fs.h>
-
-/* should be implemented by board */
-extern void spl_block_device_init(void);
-
-block_dev_desc_t * spl_get_block_device(void)
-{
- block_dev_desc_t * device;
-
- spl_block_device_init();
-
- device = get_dev(CONFIG_SPL_BLOCKDEV_INTERFACE, CONFIG_SPL_BLOCKDEV_ID);
- if (!device) {
- printf("blk device %s%d not exists\n",
- CONFIG_SPL_BLOCKDEV_INTERFACE,
- CONFIG_SPL_BLOCKDEV_ID);
- hang();
- }
-
- return device;
-}
-
-#ifdef CONFIG_SPL_FAT_SUPPORT
-static int block_load_image_fat(const char *filename)
-{
- int err;
- struct image_header *header;
-
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
-
- err = file_fat_read(filename, header, sizeof(struct image_header));
- if (err <= 0)
- goto end;
-
- spl_parse_image_header(header);
-
- err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
-
-end:
- if (err <= 0)
- printf("spl: error reading image %s, err - %d\n",
- filename, err);
-
- return (err <= 0);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_fat_os(void)
-{
- int err;
-
- err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,
- (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
- if (err <= 0) {
- return -1;
- }
-
- return block_load_image_fat(CONFIG_SPL_FAT_LOAD_KERNEL_NAME);
-}
-#endif
-
-void spl_block_load_image(void)
-{
- int err;
- block_dev_desc_t * device;
-
- device = spl_get_block_device();
- err = fat_register_device(device, CONFIG_BLOCKDEV_FAT_BOOT_PARTITION);
- if (err) {
- printf("spl: fat register err - %d\n", err);
- hang();
- }
-#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || block_load_image_fat_os())
-#endif
- {
- err = block_load_image_fat(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
- if (err)
- hang();
- }
-}
-#elif defined(CONFIG_SPL_EXT4_SUPPORT) /* end CONFIG_SPL_FAT_SUPPORT */
-static int block_load_image_ext4(const char *filename)
-{
- int err;
- struct image_header *header;
-
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
-
- err = ext4_read_file(filename, header, 0, sizeof(struct image_header));
- if (err <= 0)
- goto end;
-
- spl_parse_image_header(header);
-
- err = ext4_read_file(filename, (u8 *)spl_image.load_addr, 0, 0);
-
-end:
- return (err <= 0);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_ext4_os(void)
-{
- int err;
-
- err = ext4_read_file(CONFIG_SPL_EXT4_LOAD_ARGS_NAME,
- (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, 0);
- if (err <= 0) {
- return -1;
- }
-
- return block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_KERNEL_NAME);
-}
-#endif
-
-void spl_block_load_image(void)
-{
- int err;
- block_dev_desc_t * device;
-
- device = spl_get_block_device();
- err = ext4_register_device(device, CONFIG_BLOCKDEV_EXT4_BOOT_PARTITION);
- if (err) {
- hang();
- }
-#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || block_load_image_ext4_os())
-#endif
- {
- err = block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_PAYLOAD_NAME);
- if (err)
- hang();
- }
-}
-#else /* end CONFIG_SPL_EXT4_SUPPORT */
-static int block_load_image_raw(block_dev_desc_t * device, lbaint_t sector)
-{
- int n;
- u32 image_size_sectors;
- struct image_header *header;
-
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
-
- /* read image header to find the image size & load address */
- n = device->block_read(device->dev, sector, 1, header);
-
- if (n != 1) {
- printf("spl: blk read err\n");
- return 1;
- }
-
- spl_parse_image_header(header);
-
- /* convert size to sectors - round up */
- image_size_sectors = (spl_image.size + 512 - 1) / 512;
- n = device->block_read(device->dev, sector, image_size_sectors,
- (void *)spl_image.load_addr);
-
- if (n != image_size_sectors) {
- printf("spl: blk read err\n");
- return 1;
- }
- return 0;
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_raw_os(block_dev_desc_t * device)
-{
- int n;
-
- n = device->block_read(device->dev, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTOR,
- CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS,
- (u32 *)CONFIG_SYS_SPL_ARGS_ADDR);
- /* flush cache after read */
- flush_cache(addr, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS * 512);
-
- if (n != CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS) {
- printf("args blk read error\n");
- return -1;
- }
-
- return block_load_image_raw(device, CONFIG_SYS_BLOCK_RAW_MODE_KERNEL_SECTOR);
-}
-#endif
-
-void spl_block_load_image(void)
-{
- int err;
- block_dev_desc_t * device;
-
- device = spl_get_block_device();
-#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || block_load_image_raw_os(device))
-#endif
- {
- err = block_load_image_raw(device,
- CONFIG_SYS_BLOCK_RAW_MODE_U_BOOT_SECTOR);
- if (err)
- hang();
- }
-}
-#endif /* CONFIG_SPL_FAT_SUPPORT */
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_OX820=y
-CONFIG_TARGET_OX820=y
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Oxford Semiconductor Ltd
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,`
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/clock.h>
-
-/**
- * SATA related definitions
- */
-#define ATA_PORT_CTL 0
-#define ATA_PORT_FEATURE 1
-#define ATA_PORT_NSECT 2
-#define ATA_PORT_LBAL 3
-#define ATA_PORT_LBAM 4
-#define ATA_PORT_LBAH 5
-#define ATA_PORT_DEVICE 6
-#define ATA_PORT_COMMAND 7
-
-/* The offsets to the SATA registers */
-#define SATA_ORB1_OFF 0
-#define SATA_ORB2_OFF 1
-#define SATA_ORB3_OFF 2
-#define SATA_ORB4_OFF 3
-#define SATA_ORB5_OFF 4
-
-#define SATA_FIS_ACCESS 11
-#define SATA_INT_STATUS_OFF 12 /* Read only */
-#define SATA_INT_CLR_OFF 12 /* Write only */
-#define SATA_INT_ENABLE_OFF 13 /* Read only */
-#define SATA_INT_ENABLE_SET_OFF 13 /* Write only */
-#define SATA_INT_ENABLE_CLR_OFF 14 /* Write only */
-#define SATA_VERSION_OFF 15
-#define SATA_CONTROL_OFF 23
-#define SATA_COMMAND_OFF 24
-#define SATA_PORT_CONTROL_OFF 25
-#define SATA_DRIVE_CONTROL_OFF 26
-
-/* The offsets to the link registers that are access in an asynchronous manner */
-#define SATA_LINK_DATA 28
-#define SATA_LINK_RD_ADDR 29
-#define SATA_LINK_WR_ADDR 30
-#define SATA_LINK_CONTROL 31
-
-/* SATA interrupt status register fields */
-#define SATA_INT_STATUS_EOC_RAW_BIT ( 0 + 16)
-#define SATA_INT_STATUS_ERROR_BIT ( 2 + 16)
-#define SATA_INT_STATUS_EOADT_RAW_BIT ( 1 + 16)
-
-/* SATA core command register commands */
-#define SATA_CMD_WRITE_TO_ORB_REGS 2
-#define SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND 4
-
-#define SATA_CMD_BUSY_BIT 7
-
-#define SATA_SCTL_CLR_ERR 0x00000316UL
-
-#define SATA_LBAL_BIT 0
-#define SATA_LBAM_BIT 8
-#define SATA_LBAH_BIT 16
-#define SATA_HOB_LBAH_BIT 24
-#define SATA_DEVICE_BIT 24
-#define SATA_NSECT_BIT 0
-#define SATA_HOB_NSECT_BIT 8
-#define SATA_LBA32_BIT 0
-#define SATA_LBA40_BIT 8
-#define SATA_FEATURE_BIT 16
-#define SATA_COMMAND_BIT 24
-#define SATA_CTL_BIT 24
-
-/* ATA status (7) register field definitions */
-#define ATA_STATUS_BSY_BIT 7
-#define ATA_STATUS_DRDY_BIT 6
-#define ATA_STATUS_DF_BIT 5
-#define ATA_STATUS_DRQ_BIT 3
-#define ATA_STATUS_ERR_BIT 0
-
-/* ATA device (6) register field definitions */
-#define ATA_DEVICE_FIXED_MASK 0xA0
-#define ATA_DEVICE_DRV_BIT 4
-#define ATA_DEVICE_DRV_NUM_BITS 1
-#define ATA_DEVICE_LBA_BIT 6
-
-/* ATA Command register initiated commands */
-#define ATA_CMD_INIT 0x91
-#define ATA_CMD_IDENT 0xEC
-
-#define SATA_STD_ASYNC_REGS_OFF 0x20
-#define SATA_SCR_STATUS 0
-#define SATA_SCR_ERROR 1
-#define SATA_SCR_CONTROL 2
-#define SATA_SCR_ACTIVE 3
-#define SATA_SCR_NOTIFICAION 4
-
-#define SATA_BURST_BUF_FORCE_EOT_BIT 0
-#define SATA_BURST_BUF_DATA_INJ_ENABLE_BIT 1
-#define SATA_BURST_BUF_DIR_BIT 2
-#define SATA_BURST_BUF_DATA_INJ_END_BIT 3
-#define SATA_BURST_BUF_FIFO_DIS_BIT 4
-#define SATA_BURST_BUF_DIS_DREQ_BIT 5
-#define SATA_BURST_BUF_DREQ_BIT 6
-
-#define SATA_OPCODE_MASK 0x3
-
-#define SATA_DMA_CHANNEL 0
-
-#define DMA_CTRL_STATUS (0x0)
-#define DMA_BASE_SRC_ADR (0x4)
-#define DMA_BASE_DST_ADR (0x8)
-#define DMA_BYTE_CNT (0xC)
-#define DMA_CURRENT_SRC_ADR (0x10)
-#define DMA_CURRENT_DST_ADR (0x14)
-#define DMA_CURRENT_BYTE_CNT (0x18)
-#define DMA_INTR_ID (0x1C)
-#define DMA_INTR_CLEAR_REG (DMA_CURRENT_SRC_ADR)
-
-#define DMA_CALC_REG_ADR(channel, register) ((volatile u32*)(DMA_BASE + ((channel) << 5) + (register)))
-
-#define DMA_CTRL_STATUS_FAIR_SHARE_ARB (1 << 0)
-#define DMA_CTRL_STATUS_IN_PROGRESS (1 << 1)
-#define DMA_CTRL_STATUS_SRC_DREQ_MASK (0x0000003C)
-#define DMA_CTRL_STATUS_SRC_DREQ_SHIFT (2)
-#define DMA_CTRL_STATUS_DEST_DREQ_MASK (0x000003C0)
-#define DMA_CTRL_STATUS_DEST_DREQ_SHIFT (6)
-#define DMA_CTRL_STATUS_INTR (1 << 10)
-#define DMA_CTRL_STATUS_NXT_FREE (1 << 11)
-#define DMA_CTRL_STATUS_RESET (1 << 12)
-#define DMA_CTRL_STATUS_DIR_MASK (0x00006000)
-#define DMA_CTRL_STATUS_DIR_SHIFT (13)
-#define DMA_CTRL_STATUS_SRC_ADR_MODE (1 << 15)
-#define DMA_CTRL_STATUS_DEST_ADR_MODE (1 << 16)
-#define DMA_CTRL_STATUS_TRANSFER_MODE_A (1 << 17)
-#define DMA_CTRL_STATUS_TRANSFER_MODE_B (1 << 18)
-#define DMA_CTRL_STATUS_SRC_WIDTH_MASK (0x00380000)
-#define DMA_CTRL_STATUS_SRC_WIDTH_SHIFT (19)
-#define DMA_CTRL_STATUS_DEST_WIDTH_MASK (0x01C00000)
-#define DMA_CTRL_STATUS_DEST_WIDTH_SHIFT (22)
-#define DMA_CTRL_STATUS_PAUSE (1 << 25)
-#define DMA_CTRL_STATUS_INTERRUPT_ENABLE (1 << 26)
-#define DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED (1 << 27)
-#define DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED (1 << 28)
-#define DMA_CTRL_STATUS_STARVE_LOW_PRIORITY (1 << 29)
-#define DMA_CTRL_STATUS_INTR_CLEAR_ENABLE (1 << 30)
-
-#define DMA_BYTE_CNT_MASK ((1 << 21) - 1)
-#define DMA_BYTE_CNT_WR_EOT_MASK (1 << 30)
-#define DMA_BYTE_CNT_RD_EOT_MASK (1 << 31)
-#define DMA_BYTE_CNT_BURST_MASK (1 << 28)
-
-#define MAKE_FIELD(value, num_bits, bit_num) (((value) & ((1 << (num_bits)) - 1)) << (bit_num))
-
-typedef enum oxnas_dma_mode {
- OXNAS_DMA_MODE_FIXED, OXNAS_DMA_MODE_INC
-} oxnas_dma_mode_t;
-
-typedef enum oxnas_dma_direction {
- OXNAS_DMA_TO_DEVICE, OXNAS_DMA_FROM_DEVICE
-} oxnas_dma_direction_t;
-
-/* The available buses to which the DMA controller is attached */
-typedef enum oxnas_dma_transfer_bus {
- OXNAS_DMA_SIDE_A, OXNAS_DMA_SIDE_B
-} oxnas_dma_transfer_bus_t;
-
-/* Direction of data flow between the DMA controller's pair of interfaces */
-typedef enum oxnas_dma_transfer_direction {
- OXNAS_DMA_A_TO_A, OXNAS_DMA_B_TO_A, OXNAS_DMA_A_TO_B, OXNAS_DMA_B_TO_B
-} oxnas_dma_transfer_direction_t;
-
-/* The available data widths */
-typedef enum oxnas_dma_transfer_width {
- OXNAS_DMA_TRANSFER_WIDTH_8BITS,
- OXNAS_DMA_TRANSFER_WIDTH_16BITS,
- OXNAS_DMA_TRANSFER_WIDTH_32BITS
-} oxnas_dma_transfer_width_t;
-
-/* The mode of the DMA transfer */
-typedef enum oxnas_dma_transfer_mode {
- OXNAS_DMA_TRANSFER_MODE_SINGLE, OXNAS_DMA_TRANSFER_MODE_BURST
-} oxnas_dma_transfer_mode_t;
-
-/* The available transfer targets */
-typedef enum oxnas_dma_dreq {
- OXNAS_DMA_DREQ_SATA = 0, OXNAS_DMA_DREQ_MEMORY = 15
-} oxnas_dma_dreq_t;
-
-typedef struct oxnas_dma_device_settings {
- unsigned long address_;
- unsigned fifo_size_; // Chained transfers must take account of FIFO offset at end of previous transfer
- unsigned char dreq_;
- unsigned read_eot_ :1;
- unsigned read_final_eot_ :1;
- unsigned write_eot_ :1;
- unsigned write_final_eot_ :1;
- unsigned bus_ :1;
- unsigned width_ :2;
- unsigned transfer_mode_ :1;
- unsigned address_mode_ :1;
- unsigned address_really_fixed_ :1;
-} oxnas_dma_device_settings_t;
-
-static const int MAX_NO_ERROR_LOOPS = 100000; /* 1 second in units of 10uS */
-static const int MAX_DMA_XFER_LOOPS = 300000; /* 30 seconds in units of 100uS */
-static const int MAX_DMA_ABORT_LOOPS = 10000; /* 0.1 second in units of 10uS */
-static const int MAX_SRC_READ_LOOPS = 10000; /* 0.1 second in units of 10uS */
-static const int MAX_SRC_WRITE_LOOPS = 10000; /* 0.1 second in units of 10uS */
-static const int MAX_NOT_BUSY_LOOPS = 10000; /* 1 second in units of 100uS */
-
-/* The internal SATA drive on which we should attempt to find partitions */
-static volatile u32* sata_regs_base[2] = { (volatile u32*) SATA_0_REGS_BASE,
- (volatile u32*) SATA_1_REGS_BASE,
-
-};
-static u32 wr_sata_orb1[2] = { 0, 0 };
-static u32 wr_sata_orb2[2] = { 0, 0 };
-static u32 wr_sata_orb3[2] = { 0, 0 };
-static u32 wr_sata_orb4[2] = { 0, 0 };
-
-#ifdef CONFIG_LBA48
-/* need keeping a record of NSECT LBAL LBAM LBAH ide_outb values for lba48 support */
-#define OUT_HISTORY_BASE ATA_PORT_NSECT
-#define OUT_HISTORY_MAX ATA_PORT_LBAH
-static unsigned char out_history[2][OUT_HISTORY_MAX - OUT_HISTORY_BASE + 1] = {};
-#endif
-
-static oxnas_dma_device_settings_t oxnas_sata_dma_settings = { .address_ =
- SATA_DATA_BASE, .fifo_size_ = 16, .dreq_ = OXNAS_DMA_DREQ_SATA,
- .read_eot_ = 0, .read_final_eot_ = 1, .write_eot_ = 0,
- .write_final_eot_ = 1, .bus_ = OXNAS_DMA_SIDE_B, .width_ =
- OXNAS_DMA_TRANSFER_WIDTH_32BITS, .transfer_mode_ =
- OXNAS_DMA_TRANSFER_MODE_BURST, .address_mode_ =
- OXNAS_DMA_MODE_FIXED, .address_really_fixed_ = 0 };
-
-oxnas_dma_device_settings_t oxnas_ram_dma_settings = { .address_ = 0,
- .fifo_size_ = 0, .dreq_ = OXNAS_DMA_DREQ_MEMORY, .read_eot_ = 1,
- .read_final_eot_ = 1, .write_eot_ = 1, .write_final_eot_ = 1,
- .bus_ = OXNAS_DMA_SIDE_A, .width_ =
- OXNAS_DMA_TRANSFER_WIDTH_32BITS, .transfer_mode_ =
- OXNAS_DMA_TRANSFER_MODE_BURST, .address_mode_ =
- OXNAS_DMA_MODE_FIXED, .address_really_fixed_ = 1 };
-
-static void xfer_wr_shadow_to_orbs(int device)
-{
- *(sata_regs_base[device] + SATA_ORB1_OFF) = wr_sata_orb1[device];
- *(sata_regs_base[device] + SATA_ORB2_OFF) = wr_sata_orb2[device];
- *(sata_regs_base[device] + SATA_ORB3_OFF) = wr_sata_orb3[device];
- *(sata_regs_base[device] + SATA_ORB4_OFF) = wr_sata_orb4[device];
-}
-
-static inline void device_select(int device)
-{
- /* master/slave has no meaning to SATA core */
-}
-
-static int disk_present[CONFIG_SYS_IDE_MAXDEVICE];
-
-#include <ata.h>
-
-unsigned char ide_inb(int device, int port)
-{
- unsigned char val = 0;
-
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return ATA_STAT_FAULT;
- }
-
- device_select(device);
-
- switch (port) {
- case ATA_PORT_CTL:
- val = (*(sata_regs_base[device] + SATA_ORB4_OFF)
- & (0xFFUL << SATA_CTL_BIT)) >> SATA_CTL_BIT;
- break;
- case ATA_PORT_FEATURE:
- val = (*(sata_regs_base[device] + SATA_ORB2_OFF)
- & (0xFFUL << SATA_FEATURE_BIT)) >> SATA_FEATURE_BIT;
- break;
- case ATA_PORT_NSECT:
- val = (*(sata_regs_base[device] + SATA_ORB2_OFF)
- & (0xFFUL << SATA_NSECT_BIT)) >> SATA_NSECT_BIT;
- break;
- case ATA_PORT_LBAL:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_LBAL_BIT)) >> SATA_LBAL_BIT;
- break;
- case ATA_PORT_LBAM:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_LBAM_BIT)) >> SATA_LBAM_BIT;
- break;
- case ATA_PORT_LBAH:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_LBAH_BIT)) >> SATA_LBAH_BIT;
- break;
- case ATA_PORT_DEVICE:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_HOB_LBAH_BIT)) >> SATA_HOB_LBAH_BIT;
- val |= (*(sata_regs_base[device] + SATA_ORB1_OFF)
- & (0xFFUL << SATA_DEVICE_BIT)) >> SATA_DEVICE_BIT;
- break;
- case ATA_PORT_COMMAND:
- val = (*(sata_regs_base[device] + SATA_ORB2_OFF)
- & (0xFFUL << SATA_COMMAND_BIT)) >> SATA_COMMAND_BIT;
- val |= ATA_STAT_DRQ;
- break;
- default:
- printf("ide_inb() Unknown port = %d\n", port);
- break;
- }
-
- // printf("inb: %d:%01x => %02x\n", device, port, val);
-
- return val;
-}
-
-/**
- * Possible that ATA status will not become no-error, so must have timeout
- * @returns An int which is zero on error
- */
-static inline int wait_no_error(int device)
-{
- int status = 0;
-
- /* Check for ATA core error */
- if (*(sata_regs_base[device] + SATA_INT_STATUS_OFF)
- & (1 << SATA_INT_STATUS_ERROR_BIT)) {
- printf("wait_no_error() SATA core flagged error\n");
- } else {
- int loops = MAX_NO_ERROR_LOOPS;
- do {
- /* Check for ATA device error */
- if (!(ide_inb(device, ATA_PORT_COMMAND)
- & (1 << ATA_STATUS_ERR_BIT))) {
- status = 1;
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("wait_no_error() Timed out of wait for SATA no-error condition\n");
- }
- }
-
- return status;
-}
-
-/**
- * Expect SATA command to always finish, perhaps with error
- * @returns An int which is zero on error
- */
-static inline int wait_sata_command_not_busy(int device)
-{
- /* Wait for data to be available */
- int status = 0;
- int loops = MAX_NOT_BUSY_LOOPS;
- do {
- if (!(*(sata_regs_base[device] + SATA_COMMAND_OFF)
- & (1 << SATA_CMD_BUSY_BIT))) {
- status = 1;
- break;
- }
- udelay(100);
- } while (--loops);
-
- if (!loops) {
- printf("wait_sata_command_not_busy() Timed out of wait for SATA command to finish\n");
- }
-
- return status;
-}
-
-void ide_outb(int device, int port, unsigned char val)
-{
- typedef enum send_method {
- SEND_NONE, SEND_SIMPLE, SEND_CMD, SEND_CTL,
- } send_method_t;
-
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return;
- }
-
- // printf("outb: %d:%01x <= %02x\n", device, port, val);
-
- device_select(device);
-
-#ifdef CONFIG_LBA48
- if (port >= OUT_HISTORY_BASE && port <= OUT_HISTORY_MAX) {
- out_history[0][port - OUT_HISTORY_BASE] =
- out_history[1][port - OUT_HISTORY_BASE];
- out_history[1][port - OUT_HISTORY_BASE] = val;
- }
-#endif
- send_method_t send_regs = SEND_NONE;
- switch (port) {
- case ATA_PORT_CTL:
- wr_sata_orb4[device] &= ~(0xFFUL << SATA_CTL_BIT);
- wr_sata_orb4[device] |= (val << SATA_CTL_BIT);
- send_regs = SEND_CTL;
- break;
- case ATA_PORT_FEATURE:
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_FEATURE_BIT);
- wr_sata_orb2[device] |= (val << SATA_FEATURE_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_NSECT:
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_NSECT_BIT);
- wr_sata_orb2[device] |= (val << SATA_NSECT_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_LBAL:
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAL_BIT);
- wr_sata_orb3[device] |= (val << SATA_LBAL_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_LBAM:
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAM_BIT);
- wr_sata_orb3[device] |= (val << SATA_LBAM_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_LBAH:
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAH_BIT);
- wr_sata_orb3[device] |= (val << SATA_LBAH_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_DEVICE:
- wr_sata_orb1[device] &= ~(0xFFUL << SATA_DEVICE_BIT);
- wr_sata_orb1[device] |= (val << SATA_DEVICE_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_COMMAND:
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_COMMAND_BIT);
- wr_sata_orb2[device] |= (val << SATA_COMMAND_BIT);
- send_regs = SEND_CMD;
-#ifdef CONFIG_LBA48
- if (val == ATA_CMD_READ_EXT || val == ATA_CMD_WRITE_EXT)
- {
- /* fill high bytes of LBA48 && NSECT */
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_HOB_NSECT_BIT);
- wr_sata_orb2[device] |=
- (out_history[0][ATA_PORT_NSECT - OUT_HISTORY_BASE] << SATA_HOB_NSECT_BIT);
-
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_HOB_LBAH_BIT);
- wr_sata_orb3[device] |=
- (out_history[0][ATA_PORT_LBAL - OUT_HISTORY_BASE] << SATA_HOB_LBAH_BIT);
-
- wr_sata_orb4[device] &= ~(0xFFUL << SATA_LBA32_BIT);
- wr_sata_orb4[device] |=
- (out_history[0][ATA_PORT_LBAM - OUT_HISTORY_BASE] << SATA_LBA32_BIT);
-
- wr_sata_orb4[device] &= ~(0xFFUL << SATA_LBA40_BIT);
- wr_sata_orb4[device] |=
- (out_history[0][ATA_PORT_LBAH - OUT_HISTORY_BASE] << SATA_LBA40_BIT);
- }
-#endif
- break;
- default:
- printf("ide_outb() Unknown port = %d\n", port);
- }
-
- u32 command;
- switch (send_regs) {
- case SEND_CMD:
- wait_sata_command_not_busy(device);
- command = *(sata_regs_base[device] + SATA_COMMAND_OFF);
- command &= ~SATA_OPCODE_MASK;
- command |= SATA_CMD_WRITE_TO_ORB_REGS;
- xfer_wr_shadow_to_orbs(device);
- wait_sata_command_not_busy(device);
- *(sata_regs_base[device] + SATA_COMMAND_OFF) = command;
- if (!wait_no_error(device)) {
- printf("ide_outb() Wait for ATA no-error timed-out\n");
- }
- break;
- case SEND_CTL:
- wait_sata_command_not_busy(device);
- command = *(sata_regs_base[device] + SATA_COMMAND_OFF);
- command &= ~SATA_OPCODE_MASK;
- command |= SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- xfer_wr_shadow_to_orbs(device);
- wait_sata_command_not_busy(device);
- *(sata_regs_base[device] + SATA_COMMAND_OFF) = command;
- if (!wait_no_error(device)) {
- printf("ide_outb() Wait for ATA no-error timed-out\n");
- }
- break;
- default:
- break;
- }
-}
-
-static u32 encode_start(u32 ctrl_status)
-{
- return ctrl_status & ~DMA_CTRL_STATUS_PAUSE;
-}
-
-/* start a paused DMA transfer in channel 0 of the SATA DMA core */
-static void dma_start(void)
-{
- unsigned int reg;
- reg = readl(SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
- reg = encode_start(reg);
- writel(reg, SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
-}
-
-static unsigned long encode_control_status(
- oxnas_dma_device_settings_t* src_settings,
- oxnas_dma_device_settings_t* dst_settings)
-{
- unsigned long ctrl_status;
- oxnas_dma_transfer_direction_t direction;
-
- ctrl_status = DMA_CTRL_STATUS_PAUSE; // Paused
- ctrl_status |= DMA_CTRL_STATUS_FAIR_SHARE_ARB; // High priority
- ctrl_status |= (src_settings->dreq_ << DMA_CTRL_STATUS_SRC_DREQ_SHIFT); // Dreq
- ctrl_status |= (dst_settings->dreq_ << DMA_CTRL_STATUS_DEST_DREQ_SHIFT); // Dreq
- ctrl_status &= ~DMA_CTRL_STATUS_RESET; // !RESET
-
- // Use new interrupt clearing register
- ctrl_status |= DMA_CTRL_STATUS_INTR_CLEAR_ENABLE;
-
- // Setup the transfer direction and burst/single mode for the two DMA busses
- if (src_settings->bus_ == OXNAS_DMA_SIDE_A) {
- // Set the burst/single mode for bus A based on src device's settings
- if (src_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A;
- }
-
- if (dst_settings->bus_ == OXNAS_DMA_SIDE_A) {
- direction = OXNAS_DMA_A_TO_A;
- } else {
- direction = OXNAS_DMA_A_TO_B;
-
- // Set the burst/single mode for bus B based on dst device's settings
- if (dst_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B;
- }
- }
- } else {
- // Set the burst/single mode for bus B based on src device's settings
- if (src_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B;
- }
-
- if (dst_settings->bus_ == OXNAS_DMA_SIDE_A) {
- direction = OXNAS_DMA_B_TO_A;
-
- // Set the burst/single mode for bus A based on dst device's settings
- if (dst_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A;
- }
- } else {
- direction = OXNAS_DMA_B_TO_B;
- }
- }
- ctrl_status |= (direction << DMA_CTRL_STATUS_DIR_SHIFT);
-
- // Setup source address mode fixed or increment
- if (src_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) {
- // Fixed address
- ctrl_status &= ~(DMA_CTRL_STATUS_SRC_ADR_MODE);
-
- // Set up whether fixed address is _really_ fixed
- if (src_settings->address_really_fixed_) {
- ctrl_status |= DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
- }
- } else {
- // Incrementing address
- ctrl_status |= DMA_CTRL_STATUS_SRC_ADR_MODE;
- ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
- }
-
- // Setup destination address mode fixed or increment
- if (dst_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) {
- // Fixed address
- ctrl_status &= ~(DMA_CTRL_STATUS_DEST_ADR_MODE);
-
- // Set up whether fixed address is _really_ fixed
- if (dst_settings->address_really_fixed_) {
- ctrl_status |=
- DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
- } else {
- ctrl_status &=
- ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
- }
- } else {
- // Incrementing address
- ctrl_status |= DMA_CTRL_STATUS_DEST_ADR_MODE;
- ctrl_status &= ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
- }
-
- // Set up the width of the transfers on the DMA buses
- ctrl_status |=
- (src_settings->width_ << DMA_CTRL_STATUS_SRC_WIDTH_SHIFT);
- ctrl_status |=
- (dst_settings->width_ << DMA_CTRL_STATUS_DEST_WIDTH_SHIFT);
-
- // Setup the priority arbitration scheme
- ctrl_status &= ~DMA_CTRL_STATUS_STARVE_LOW_PRIORITY; // !Starve low priority
-
- return ctrl_status;
-}
-
-static u32 encode_final_eot(oxnas_dma_device_settings_t* src_settings,
- oxnas_dma_device_settings_t* dst_settings,
- unsigned long length)
-{
- // Write the length, with EOT configuration for a final transfer
- unsigned long encoded = length;
- if (dst_settings->write_final_eot_) {
- encoded |= DMA_BYTE_CNT_WR_EOT_MASK;
- } else {
- encoded &= ~DMA_BYTE_CNT_WR_EOT_MASK;
- }
- if (src_settings->read_final_eot_) {
- encoded |= DMA_BYTE_CNT_RD_EOT_MASK;
- } else {
- encoded &= ~DMA_BYTE_CNT_RD_EOT_MASK;
- }
- /* if((src_settings->transfer_mode_) ||
- (src_settings->transfer_mode_)) {
- encoded |= DMA_BYTE_CNT_BURST_MASK;
- } else {
- encoded &= ~DMA_BYTE_CNT_BURST_MASK;
- }*/
- return encoded;
-}
-
-static void dma_start_write(const ulong* buffer, int num_bytes)
-{
- // Assemble complete memory settings
- oxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings;
- mem_settings.address_ = (unsigned long) buffer;
- mem_settings.address_mode_ = OXNAS_DMA_MODE_INC;
-
- writel(encode_control_status(&mem_settings, &oxnas_sata_dma_settings),
- SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
- writel(mem_settings.address_, SATA_DMA_REGS_BASE + DMA_BASE_SRC_ADR);
- writel(oxnas_sata_dma_settings.address_,
- SATA_DMA_REGS_BASE + DMA_BASE_DST_ADR);
- writel(encode_final_eot(&mem_settings, &oxnas_sata_dma_settings,
- num_bytes),
- SATA_DMA_REGS_BASE + DMA_BYTE_CNT);
-
- dma_start();
-}
-
-static void dma_start_read(ulong* buffer, int num_bytes)
-{
- // Assemble complete memory settings
- oxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings;
- mem_settings.address_ = (unsigned long) buffer;
- mem_settings.address_mode_ = OXNAS_DMA_MODE_INC;
-
- writel(encode_control_status(&oxnas_sata_dma_settings, &mem_settings),
- SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
- writel(oxnas_sata_dma_settings.address_,
- SATA_DMA_REGS_BASE + DMA_BASE_SRC_ADR);
- writel(mem_settings.address_, SATA_DMA_REGS_BASE + DMA_BASE_DST_ADR);
- writel(encode_final_eot(&oxnas_sata_dma_settings, &mem_settings,
- num_bytes),
- SATA_DMA_REGS_BASE + DMA_BYTE_CNT);
-
- dma_start();
-}
-
-static inline int dma_busy(void)
-{
- return readl(SATA_DMA_REGS_BASE + DMA_CTRL_STATUS)
- & DMA_CTRL_STATUS_IN_PROGRESS;
-}
-
-static int wait_dma_not_busy(int device)
-{
- unsigned int cleanup_required = 0;
-
- /* Poll for DMA completion */
- int loops = MAX_DMA_XFER_LOOPS;
- do {
- if (!dma_busy()) {
- break;
- }
- udelay(100);
- } while (--loops);
-
- if (!loops) {
- printf("wait_dma_not_busy() Timed out of wait for DMA not busy\n");
- cleanup_required = 1;
- }
-
- if (cleanup_required) {
- /* Abort DMA to make sure it has finished. */
- unsigned int ctrl_status = readl(
- SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
- ctrl_status |= DMA_CTRL_STATUS_RESET;
- writel(ctrl_status, SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
-
- // Wait for the channel to become idle - should be quick as should
- // finish after the next AHB single or burst transfer
- loops = MAX_DMA_ABORT_LOOPS;
- do {
- if (!dma_busy()) {
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("wait_dma_not_busy() Timed out of wait for DMA channel abort\n");
- } else {
- /* Successfully cleanup the DMA channel */
- cleanup_required = 0;
- }
-
- // Deassert reset for the channel
- ctrl_status = readl(SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
- ctrl_status &= ~DMA_CTRL_STATUS_RESET;
- writel(ctrl_status, SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
- }
-
- return !cleanup_required;
-}
-
-/**
- * Possible that ATA status will not become not-busy, so must have timeout
- */
-static unsigned int wait_not_busy(int device, unsigned long timeout_secs)
-{
- int busy = 1;
- unsigned long loops = (timeout_secs * 1000) / 50;
- do {
- // Test the ATA status register BUSY flag
- if (!((*(sata_regs_base[device] + SATA_ORB2_OFF)
- >> SATA_COMMAND_BIT) & (1UL << ATA_STATUS_BSY_BIT))) {
- /* Not busy, so stop polling */
- busy = 0;
- break;
- }
-
- // Wait for 50mS before sampling ATA status register again
- udelay(50000);
- } while (--loops);
-
- return busy;
-}
-
-void ide_output_data(int device, const ulong *sect_buf, int words)
-{
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return;
- }
-
- /* Select the required internal SATA drive */
- device_select(device);
-
- /* Start the DMA channel sending data from the passed buffer to the SATA core */
- dma_start_write(sect_buf, words << 2);
-
- /* Don't know why we need this delay, but without it the wait for DMA not
- busy times soemtimes out, e.g. when saving environment to second disk */
- udelay(1000);
-
- /* Wait for DMA to finish */
- if (!wait_dma_not_busy(device)) {
- printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n",
- device);
- }
-
- /* Sata core should finish after DMA */
- if (wait_not_busy(device, 30)) {
- printf("Timed out of wait for SATA device %d to have BUSY clear\n",
- device);
- }
- if (!wait_no_error(device)) {
- printf("oxnas_sata_output_data() Wait for ATA no-error timed-out\n");
- }
-}
-
-
-#define SATA_DM_DBG1 (SATA_HOST_REGS_BASE + 0)
-#define SATA_DATACOUNT_PORT0 (SATA_HOST_REGS_BASE + 0x10)
-#define SATA_DATACOUNT_PORT1 (SATA_HOST_REGS_BASE + 0x14)
-#define SATA_DATA_MUX_RAM0 (SATA_HOST_REGS_BASE + 0x8000)
-#define SATA_DATA_MUX_RAM1 (SATA_HOST_REGS_BASE + 0xA000)
-/* Sata core debug1 register bits */
-#define SATA_CORE_PORT0_DATA_DIR_BIT 20
-#define SATA_CORE_PORT1_DATA_DIR_BIT 21
-#define SATA_CORE_PORT0_DATA_DIR (1 << SATA_CORE_PORT0_DATA_DIR_BIT)
-#define SATA_CORE_PORT1_DATA_DIR (1 << SATA_CORE_PORT1_DATA_DIR_BIT)
-
-/**
- * Ref bug-6320
- *
- * This code is a work around for a DMA hardware bug that will repeat the
- * penultimate 8-bytes on some reads. This code will check that the amount
- * of data transferred is a multiple of 512 bytes, if not the in it will
- * fetch the correct data from a buffer in the SATA core and copy it into
- * memory.
- *
- */
-static void sata_bug_6320_workaround(int port, ulong *candidate)
-{
- int is_read;
- int quads_transferred;
- int remainder;
- int sector_quads_remaining;
-
- /* Only want to apply fix to reads */
- is_read = !(*((unsigned long*) SATA_DM_DBG1)
- & (port ? SATA_CORE_PORT1_DATA_DIR : SATA_CORE_PORT0_DATA_DIR));
-
- /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
- transferred (datacount_port register counts quads transferred) */
- quads_transferred = *((unsigned long*) (
- port ? SATA_DATACOUNT_PORT1 : SATA_DATACOUNT_PORT0));
-
- remainder = quads_transferred & 0x7f;
- sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
-
- if (is_read && (sector_quads_remaining == 2)) {
- debug("SATA read fixup, only transfered %d quads, "
- "sector_quads_remaining %d, port %d\n",
- quads_transferred, sector_quads_remaining, port);
-
- int total_len = ATA_SECT_SIZE;
- ulong *sata_data_ptr = (void*) (
- port ? SATA_DATA_MUX_RAM1 : SATA_DATA_MUX_RAM0)
- + ((total_len - 8) % 2048);
-
- *candidate = *sata_data_ptr;
- *(candidate + 1) = *(sata_data_ptr + 1);
- }
-}
-
-
-void ide_input_data(int device, ulong *sect_buf, int words)
-{
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return;
- }
-
- /* Select the required internal SATA drive */
- device_select(device);
-
- /* Start the DMA channel receiving data from the SATA core into the passed buffer */
- dma_start_read(sect_buf, words << 2);
-
- /* Sata core should finish before DMA */
- if (wait_not_busy(device, 30)) {
- printf("Timed out of wait for SATA device %d to have BUSY clear\n",
- device);
- }
- if (!wait_no_error(device)) {
- printf("oxnas_sata_output_data() Wait for ATA no-error timed-out\n");
- }
-
- /* Wait for DMA to finish */
- if (!wait_dma_not_busy(device)) {
- printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n",
- device);
- }
-
- if (words == ATA_SECTORWORDS)
- sata_bug_6320_workaround(device, sect_buf + words - 2);
-}
-
-static u32 scr_read(int device, unsigned int sc_reg)
-{
- /* Setup adr of required register. std regs start eight into async region */
- *(sata_regs_base[device] + SATA_LINK_RD_ADDR) = sc_reg
- * 4+ SATA_STD_ASYNC_REGS_OFF;
-
- /* Wait for data to be available */
- int loops = MAX_SRC_READ_LOOPS;
- do {
- if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) {
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("scr_read() Timed out of wait for read completion\n");
- }
-
- /* Read the data from the async register */
- return *(sata_regs_base[device] + SATA_LINK_DATA);
-}
-
-static void scr_write(int device, unsigned int sc_reg, u32 val)
-{
- /* Setup the data for the write */
- *(sata_regs_base[device] + SATA_LINK_DATA) = val;
-
- /* Setup adr of required register. std regs start eight into async region */
- *(sata_regs_base[device] + SATA_LINK_WR_ADDR) = sc_reg
- * 4+ SATA_STD_ASYNC_REGS_OFF;
-
- /* Wait for data to be written */
- int loops = MAX_SRC_WRITE_LOOPS;
- do {
- if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) {
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("scr_write() Timed out of wait for write completion\n");
- }
-}
-extern void workaround5458(void);
-
-#define PHY_LOOP_COUNT 25 /* Wait for upto 5 seconds for PHY to be found */
-#define LOS_AND_TX_LVL 0x2988
-#define TX_ATTEN 0x55629
-
-static int phy_reset(int device)
-{
- int phy_status = 0;
- int loops = 0;
-
- scr_write(device, (0x60 - SATA_STD_ASYNC_REGS_OFF) / 4, LOS_AND_TX_LVL);
- scr_write(device, (0x70 - SATA_STD_ASYNC_REGS_OFF) / 4, TX_ATTEN);
-
- /* limit it to Gen-1 SATA (1.5G) */
- scr_write(device, SATA_SCR_CONTROL, 0x311); /* Issue phy wake & core reset */
- scr_read(device, SATA_SCR_STATUS); /* Dummy read; flush */
- udelay(1000);
- scr_write(device, SATA_SCR_CONTROL, 0x310); /* Issue phy wake & clear core reset */
-
- /* Wait for upto 5 seconds for PHY to become ready */
- do {
- udelay(200000);
- if ((scr_read(device, SATA_SCR_STATUS) & 0xf) == 3) {
- scr_write(device, SATA_SCR_ERROR, ~0);
- phy_status = 1;
- break;
- }
- //printf("No SATA PHY found status:0x%x\n", scr_read(device, SATA_SCR_STATUS));
- } while (++loops < PHY_LOOP_COUNT);
-
- if (phy_status) {
- udelay(500000); /* wait half a second */
- }
-
- return phy_status;
-}
-
-#define FIS_LOOP_COUNT 25 /* Wait for upto 5 seconds for FIS to be received */
-static int wait_FIS(int device)
-{
- int status = 0;
- int loops = 0;
-
- do {
- udelay(200000);
- if (ide_inb(device, ATA_PORT_NSECT) > 0) {
- status = 1;
- break;
- }
- } while (++loops < FIS_LOOP_COUNT);
-
- return status;
-}
-
-
-#define SATA_PHY_ASIC_STAT (0x44900000)
-#define SATA_PHY_ASIC_DATA (0x44900004)
-
-/**
- * initialise functions and macros for ASIC implementation
- */
-#define PH_GAIN 2
-#define FR_GAIN 3
-#define PH_GAIN_OFFSET 6
-#define FR_GAIN_OFFSET 8
-#define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
-#define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
-#define USE_INT_SETTING (1<<5)
-
-#define CR_READ_ENABLE (1<<16)
-#define CR_WRITE_ENABLE (1<<17)
-#define CR_CAP_DATA (1<<18)
-
-static void wait_cr_ack(void)
-{
- while ((readl(SATA_PHY_ASIC_STAT) >> 16) & 0x1f)
- /* wait for an ack bit to be set */;
-}
-
-static unsigned short read_cr(unsigned short address)
-{
- writel(address, SATA_PHY_ASIC_STAT);
- wait_cr_ack();
- writel(CR_READ_ENABLE, SATA_PHY_ASIC_DATA);
- wait_cr_ack();
- return readl(SATA_PHY_ASIC_STAT);
-}
-
-static void write_cr(unsigned short data, unsigned short address)
-{
- writel(address, SATA_PHY_ASIC_STAT);
- wait_cr_ack();
- writel((data | CR_CAP_DATA), SATA_PHY_ASIC_DATA);
- wait_cr_ack();
- writel(CR_WRITE_ENABLE, SATA_PHY_ASIC_DATA);
- wait_cr_ack();
- return;
-}
-
-void workaround5458(void)
-{
- unsigned i;
-
- for (i = 0; i < 2; i++) {
- unsigned short rx_control = read_cr(0x201d + (i << 8));
- rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
- rx_control |= PH_GAIN << PH_GAIN_OFFSET;
- rx_control |= FR_GAIN << FR_GAIN_OFFSET;
- rx_control |= USE_INT_SETTING;
- write_cr(rx_control, 0x201d + (i << 8));
- }
-}
-
-int ide_preinit(void)
-{
- int num_disks_found = 0;
-
- /* Initialise records of which disks are present to all present */
- int i;
- for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; i++) {
- disk_present[i] = 1;
- }
-
- /* Block reset SATA and DMA cores */
- reset_block(SYS_CTRL_RST_SATA, 1);
- reset_block(SYS_CTRL_RST_SATA_LINK, 1);
- reset_block(SYS_CTRL_RST_SATA_PHY, 1);
- reset_block(SYS_CTRL_RST_SGDMA, 1);
-
- /* Enable clocks to SATA and DMA cores */
- enable_clock(SYS_CTRL_CLK_SATA);
- enable_clock(SYS_CTRL_CLK_DMA);
-
- udelay(5000);
- reset_block(SYS_CTRL_RST_SATA_PHY, 0);
- udelay(50);
- reset_block(SYS_CTRL_RST_SATA, 0);
- reset_block(SYS_CTRL_RST_SATA_LINK, 0);
- udelay(50);
- reset_block(SYS_CTRL_RST_SGDMA, 0);
- udelay(100);
- /* Apply the Synopsis SATA PHY workarounds */
- workaround5458();
- udelay(10000);
-
- /* disable and clear core interrupts */
- *((unsigned long*) SATA_HOST_REGS_BASE + SATA_INT_ENABLE_CLR_OFF) =
- ~0UL;
- *((unsigned long*) SATA_HOST_REGS_BASE + SATA_INT_CLR_OFF) = ~0UL;
-
- int device;
- for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) {
- int found = 0;
- int retries = 1;
-
- /* Disable SATA interrupts */
- *(sata_regs_base[device] + SATA_INT_ENABLE_CLR_OFF) = ~0UL;
-
- /* Clear any pending SATA interrupts */
- *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL;
-
- do {
- /* clear sector count register for FIS detection */
- ide_outb(device, ATA_PORT_NSECT, 0);
-
- /* Get the PHY working */
- if (!phy_reset(device)) {
- printf("SATA PHY not ready for device %d\n",
- device);
- break;
- }
-
- if (!wait_FIS(device)) {
- printf("No FIS received from device %d\n",
- device);
- } else {
- if ((scr_read(device, SATA_SCR_STATUS) & 0xf)
- == 0x3) {
- if (wait_not_busy(device, 30)) {
- printf("Timed out of wait for SATA device %d to have BUSY clear\n",
- device);
- } else {
- ++num_disks_found;
- found = 1;
- }
- } else {
- printf("No SATA device %d found, PHY status = 0x%08x\n",
- device,
- scr_read(
- device,
- SATA_SCR_STATUS));
- }
- break;
- }
- } while (retries--);
-
- /* Record whether disk is present, so won't attempt to access it later */
- disk_present[device] = found;
- }
-
- /* post disk detection clean-up */
- for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) {
- if (disk_present[device]) {
- /* set as ata-5 (28-bit) */
- *(sata_regs_base[device] + SATA_DRIVE_CONTROL_OFF) =
- 0UL;
-
- /* clear phy/link errors */
- scr_write(device, SATA_SCR_ERROR, ~0);
-
- /* clear host errors */
- *(sata_regs_base[device] + SATA_CONTROL_OFF) |=
- SATA_SCTL_CLR_ERR;
-
- /* clear interrupt register as this clears the error bit in the IDE
- status register */
- *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL;
- }
- }
-
- return !num_disks_found;
-}
-
+++ /dev/null
-/*
- * drivers/usb/host/ehci-oxnas.c
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sysctl.h>
-#include <asm/arch/clock.h>
-
-#include "ehci.h"
-
-static struct ehci_hcor *ghcor;
-
-static int start_oxnas_usb_ehci(void)
-{
-#ifdef CONFIG_USB_PLLB_CLK
- reset_block(SYS_CTRL_RST_PLLB, 0);
- enable_clock(SYS_CTRL_CLK_REF600);
-
- writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV),
- SEC_CTRL_PLLB_CTRL0);
- /* 600MHz pllb divider for 12MHz */
- writel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0), SEC_CTRL_PLLB_DIV_CTRL);
-#else
- /* ref 300 divider for 12MHz */
- writel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0), SYS_CTRL_REF300_DIV);
-#endif
-
- /* Ensure the USB block is properly reset */
- reset_block(SYS_CTRL_RST_USBHS, 1);
- reset_block(SYS_CTRL_RST_USBHS, 0);
-
- reset_block(SYS_CTRL_RST_USBHSPHYA, 1);
- reset_block(SYS_CTRL_RST_USBHSPHYA, 0);
-
- reset_block(SYS_CTRL_RST_USBHSPHYB, 1);
- reset_block(SYS_CTRL_RST_USBHSPHYB, 0);
-
- /* Force the high speed clock to be generated all the time, via serial
- programming of the USB HS PHY */
- writel((2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
- writel((1UL << USBHSPHY_TEST_CLK) |
- (2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
- writel((0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
- writel((1UL << USBHSPHY_TEST_CLK) |
- (0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
-#ifdef CONFIG_USB_PLLB_CLK /* use pllb clock */
- writel(USB_CLK_INTERNAL | USB_INT_CLK_PLLB, SYS_CTRL_USB_CTRL);
-#else /* use ref300 derived clock */
- writel(USB_CLK_INTERNAL | USB_INT_CLK_REF300, SYS_CTRL_USB_CTRL);
-#endif
- /* Enable the clock to the USB block */
- enable_clock(SYS_CTRL_CLK_USBHS);
-
- return 0;
-}
-int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
- struct ehci_hcor **hcor)
-{
- start_oxnas_usb_ehci();
- *hccr = (struct ehci_hccr *)(USB_HOST_BASE + 0x100);
- *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
- HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
- ghcor = *hcor;
- return 0;
-}
-
-int ehci_hcd_stop(int index)
-{
- reset_block(SYS_CTRL_RST_USBHS, 1);
- disable_clock(SYS_CTRL_CLK_USBHS);
- return 0;
-}
-
-extern void __ehci_set_usbmode(int index);
-void ehci_set_usbmode(int index)
-{
- #define or_txttfill_tuning _reserved_1_[0]
- u32 tmp;
-
- __ehci_set_usbmode(index);
-
- tmp = ehci_readl(&ghcor->or_txfilltuning);
- tmp &= ~0x00ff0000;
- tmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes) */
- tmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/
- ehci_writel(&ghcor->or_txfilltuning, tmp);
-
- tmp = ehci_readl(&ghcor->or_txttfill_tuning);
- tmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */
- ehci_writel(&ghcor->or_txttfill_tuning, tmp);
-}
+++ /dev/null
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_ARM1136
-#define CONFIG_OX820
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-
-/* make cmd_ide.c quiet when compile */
-#define __io
-
-/*#define CONFIG_ARCH_CPU_INIT*/
-/*#define CONFIG_DISPLAY_CPUINFO*/
-/*#define CONFIG_DISPLAY_BOARDINFO*/
-/*#define CONFIG_BOARD_EARLY_INIT_F*/
-/*#define CONFIG_SKIP_LOWLEVEL_INIT*/
-
-/* mem */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_MIN_SDRAM_SIZE (128 * 1024 * 1024) /* 128 MB */
-#define CONFIG_MAX_SDRAM_SIZE (512 * 1024 * 1024) /* 512 MB */
-#define CONFIG_SRAM_BASE 0x50000000
-#define CONFIG_SRAM_SIZE (64 * 1024)
-
-/* need do dma so better keep dcache off */
-#define CONFIG_SYS_DCACHE_OFF
-
-/* clock */
-#define CONFIG_PLLA_FREQ_MHZ 800
-#define CONFIG_RPSCLK 6250000
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_CLK_FREQ CONFIG_RPSCLK
-#define CONFIG_SYS_TIMERBASE TIMER1_BASE
-#define CONFIG_TIMER_PRESCALE TIMER_PRESCALE_16
-
-/* serial */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK CONFIG_RPSCLK
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_NS16550_COM1 UART_1_BASE
-#define CONFIG_CONS_INDEX 1
-
-/* ide */
-#define CONFIG_SYS_ATA_BASE_ADDR 0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0
-#define CONFIG_IDE_PLX
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_IDE_PREINIT
-#define CONFIG_LBA48
-
-/* nand */
-#define CONFIG_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE STATIC_CS0_BASE
-#define NAND_CLE_ADDR_PIN 19
-#define NAND_ALE_ADDR_PIN 18
-#define MTDPARTS_DEFAULT "mtdparts=41000000.nand:" \
- "14m(boot)," \
- "-(ubi)"
-#define MTDIDS_DEFAULT "nand0=41000000.nand"
-#define UBIPART_DEFAULT "ubi"
-
-/* net */
-#define CONFIG_DESIGNWARE_ETH
-#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_MII
-#define CONFIG_CMD_MII
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_ICPLUS
-
-/* spl */
-#ifdef CONFIG_SPL_BUILD
-#define USE_DL_PREFIX /* rename malloc free etc, so we can override them */
-#endif
-
-#if defined(CONFIG_BOOT_FROM_NAND) || defined(CONFIG_BOOT_FROM_SATA)
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_TEXT_BASE 0x50000000
-#define CONFIG_SPL_STACK (CONFIG_SRAM_BASE + (48 * 1024))
-#define CONFIG_SPL_DISPLAY_PRINT
-#define CONFIG_SPL_BSS_DRAM_START 0x65000000
-#define CONFIG_SPL_BSS_DRAM_SIZE 0x01000000
-#define CONFIG_SPL_MALLOC_START 0x66000000
-#endif
-
-#if defined(CONFIG_BOOT_FROM_NAND)
-#define CONFIG_SPL_NAND_SUPPORT
-#define BOOT_DEVICE_TYPE "NAND"
-#define BOOT_DEVICE_NAND 0xfeedbacc
-#define CONFIG_SPL_BOOT_DEVICE BOOT_DEVICE_NAND
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_NAND_SOFTECC
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 6
-#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
- 48, 49, 50, 51, 52, 53, 54, 55, \
- 56, 57, 58, 59, 60, 61, 62, 63}
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-/* pages per erase block */
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
-/* nand spl use 1 erase block, and use bit to byte encode for reliability */
-#define CONFIG_SPL_MAX_SIZE (128 * 1024 / 8)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
-/* spl kernel load is not enabled */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
-#define CONFIG_CMD_SPL_NAND_OFS 0
-#define CONFIG_CMD_SPL_WRITE_SIZE 1024
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-/* CONFIG_BOOT_FROM_NAND end */
-
-#elif defined(CONFIG_BOOT_FROM_SATA)
-#define CONFIG_SPL_BLOCK_SUPPORT
-#define BOOT_DEVICE_TYPE "SATA"
-#define BOOT_DEVICE_BLOCK 860202
-#define CONFIG_SPL_BOOT_DEVICE BOOT_DEVICE_BLOCK
-#define CONFIG_SPL_MAX_SIZE (36 * 1024)
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_BLOCKDEV_INTERFACE "ide"
-#define CONFIG_SPL_BLOCKDEV_ID 0
-
-#ifdef CONFIG_BOOT_FROM_FAT /* u-boot in fat partition */
-
-#define CONFIG_SPL_FAT_SUPPORT
-
-#define CONFIG_BLOCKDEV_FAT_BOOT_PARTITION 1 /* first partition */
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" /* u-boot file name */
-/* enable U-Boot Falcon Mode */
-#define CONFIG_CMD_SPL
-#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "bootargs.bin" /* boot parameters */
-#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "falcon.img" /* kernel */
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-
-#elif CONFIG_BOOT_FROM_EXT4
-
-#define CONFIG_SPL_EXT4_SUPPORT
-#define CONFIG_BLOCKDEV_EXT4_BOOT_PARTITION 1 /* first partition */
-#define CONFIG_SPL_EXT4_LOAD_PAYLOAD_NAME "/boot/u-boot.img" /* u-boot file name */
-/* enable U-Boot Falcon Mode */
-#define CONFIG_CMD_SPL
-#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_EXT4_LOAD_ARGS_NAME "/boot/bootargs.bin" /* boot parameters */
-#define CONFIG_SPL_EXT4_LOAD_KERNEL_NAME "/boot/falcon.img" /* kernel */
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-
-#else /* u-boot in raw sectors */
-
-#define CONFIG_SYS_BLOCK_RAW_MODE_U_BOOT_SECTOR 1024
-/* spl kernel load is not enabled */
-#define CONFIG_SYS_BLOCK_RAW_MODE_KERNEL_SECTOR 4096
-#define CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTOR 0
-#define CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS (1024 / 512)
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-
-#endif /* CONFIG_BOOT_FROM_FAT */
-/* CONFIG_BOOT_FROM_SATA end */
-
-#else
-/* generic, no spl support */
-#endif
-
-/* boot */
-#define CONFIG_IDENT_STRING " for OXNAS"
-#define CONFIG_MACH_TYPE MACH_TYPE_OXNAS
-#ifndef CONFIG_SPL_BUILD
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-#endif
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_DEFAULT_CONSOLE_PARM "console=ttyS0,115200n8 earlyprintk=serial"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_AUTOLOAD "no"
-
-#define CONFIG_DEFAULT_CONSOLE CONFIG_DEFAULT_CONSOLE_PARM "\0"
-#define CONFIG_BOOTARGS CONFIG_DEFAULT_CONSOLE_PARM
-#define CONFIG_BOOTCOMMAND "run nandboot"
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_RESET_TO_RETRY 60
-
-#define CONFIG_NETCONSOLE
-#define CONFIG_IPADDR 192.168.50.100
-#define CONFIG_SERVERIP 192.168.50.59
-
-/* A sane default configuration...
- * When booting without a valid environment in ubi, first to loading and booting
- * the kernel image directly above U-Boot, maybe both were loaded there by
- * another bootloader.
- * Also use that same offset (0x90000) to load the rescue image later on (by
- * adding it onto the flash address where U-Boot is supposed to be stored by
- * the legacy loader, 0x440000, resulting in offset 0x4d0000 on the flash).
- * When coming up with a valid environment in ubi, first try to load the
- * kernel from a ubi volume kernel, if that fails, fallback to the rescue
- * image stored in boot partition. As a last resort try booting via
- * DHCP/TFTP.
- * In case there is no valid environment, first probe for a uimage in ram left
- * behind by the first bootloader on a tftp boot.
- * If that fails, switch to normal boot order and save environment.
- * The loader is supposed to be written to flash at offset 0x440000 and loaded to
- * RAM at 0x64000000
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "load_kernel_ubi=ubi readvol 0x62000000 kernel;\0" \
- "load_kernel_rescue=nand read 0x62000000 0x4e0000 0x400000;\0" \
- "load_kernel_dhcp=dhcp 0x62000000 oxnas-rescue.bin;\0" \
- "boot_kernel=bootm 0x62000000;\0" \
- "boot_ubi=run load_kernel_ubi && run boot_kernel;\0" \
- "boot_rescue=run load_kernel_rescue && run boot_kernel;\0" \
- "boot_dhcp=run load_kernel_dhcp && run boot_kernel;\0" \
- "normalboot=run boot_ubi; run boot_rescue; run boot_dhcp;\0" \
- "firstboot=bootm 0x640a0000; setenv bootcmd run normalboot; " \
- "setenv firstboot; saveenv; run bootcmd; \0" \
- "bootcmd=run firstboot; \0" \
- "console=" CONFIG_DEFAULT_CONSOLE \
- "bootargs=" CONFIG_BOOTARGS "\0" \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
-
-/* env */
-#if defined(CONFIG_BOOT_FROM_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x000C0000
-#define CONFIG_ENV_SIZE 0x00020000
-#define CONFIG_ENV_OFFSET_REDUND 0x00100000
-#define CONFIG_ENV_SIZE_REDUND 0x00020000
-#define CONFIG_ENV_RANGE (CONFIG_ENV_SIZE * 2)
-/* CONFIG_BOOT_FROM_NAND end */
-
-#elif defined(CONFIG_BOOT_FROM_SATA)
-#ifdef CONFIG_BOOT_FROM_EXT4
-#define CONFIG_ENV_IS_IN_EXT4
-#define CONFIG_START_IDE
-#define EXT4_ENV_INTERFACE "ide"
-#define EXT4_ENV_DEVICE 0
-#define EXT4_ENV_PART 1
-#define EXT4_ENV_FILE "/boot/u-boot.env"
-#define CONFIG_ENV_SIZE (16 * 1024)
-#else
-#define CONFIG_ENV_IS_IN_FAT
-#define CONFIG_START_IDE
-#define FAT_ENV_INTERFACE "ide"
-#define FAT_ENV_DEVICE 0
-#define FAT_ENV_PART 1
-#define FAT_ENV_FILE "u-boot.env"
-#define CONFIG_ENV_SIZE (16 * 1024)
-#endif
-/* CONFIG_BOOT_FROM_SATA end */
-#elif defined(CONFIG_BOOT_FROM_SATA)
-
-#else
-/* generic */
-#define CONFIG_ENV_IS_IN_UBI 1
-#define CONFIG_ENV_UBI_PART UBIPART_DEFAULT
-#define CONFIG_ENV_UBI_VOLUME "ubootenv"
-#define CONFIG_ENV_UBI_VOLUME_REDUND "ubootenv2"
-#define CONFIG_ENV_SIZE (16 * 1024)
-#endif
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_TEXT_BASE 0x64000000
-#define CONFIG_SYS_INIT_SP_ADDR 0x65000000
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "OX820 # "
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size*/
-#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE
-
-/* usb */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_USB_EHCI
-#define CONFIG_EHCI_IS_TDI
-/* #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x3F */
-#define CONFIG_USB_PLLB_CLK
-#define CONFIG_USB_EHCI_OXNAS
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_USB_STORAGE
-#endif
-#define CONFIG_CMD_USB
-
-/* cmds */
-#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_ENV_FLAGS
-
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PXE
-
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_EXT4_WRITE
-#endif
-
-#define CONFIG_CMD_ZIP
-#define CONFIG_CMD_UNZIP
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_HASH
-#define CONFIG_CMD_INI
-#define CONFIG_CMD_GETTIME
-#define CONFIG_CMD_BOOTMENU
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_BOOTZ
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
-/* for CONFIG_CMD_MTDPARTS */
-#define CONFIG_MTD_DEVICE
-/* for CONFIG_CMD_UBI */
-#define CONFIG_MTD_PARTITIONS
-/* for CONFIG_CMD_UBI */
-#define CONFIG_RBTREE
-
-/* optional, for CONFIG_CMD_BOOTM & required by CONFIG_CMD_UBIFS */
-#define CONFIG_LZO
-#define CONFIG_LZMA
-#define CONFIG_BZIP2
-
-/* for CONFIG_CMD_ZIP */
-#define CONFIG_GZIP_COMPRESSED
-/* for CONFIG_CMD_MD5SUM */
-#define CONFIG_MD5
-#define CONFIG_MD5SUM_VERIFY
-/* enable CONFIG_CMD_HASH's verification feature */
-#define CONFIG_HASH_VERIFY
-#define CONFIG_REGEX
-/* for CONFIG_CMD_BOOTMENU & CONFIG_CMD_PXE */
-#define CONFIG_MENU
-
-/* for new FIT uImage format generated in OpenWrt */
-#define CONFIG_FIT
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* J J Larworthy 27 September 2006 */
-
-/* file to read the boot sector of a dis and the loaded image and report
- * if the boot rom would accept the data as intact and suitable for use
- */
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/errno.h>
-
-#include <fcntl.h>
-#include <unistd.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
-
-extern uint32_t crc32(uint32_t, const unsigned char *, unsigned int);
-
-#define NUMBER_VECTORS 12
-struct {
- unsigned int start_vector[NUMBER_VECTORS];
- char code[4];
- unsigned int header_length;
- unsigned int reserved[3];
- unsigned int length;
- unsigned int img_CRC;
- unsigned int CRC;
-} img_header;
-
-void print_usage(void)
-{
- printf("update_header file.bin\n");
-}
-
-void print_header(void)
-{
- int i;
-
- printf("vectors in header\n");
- for (i = 0; i < NUMBER_VECTORS; i++) {
- printf("%d:0x%08x\n", i, img_header.start_vector[i]);
- }
- printf("length:%8x\nimg_CRC:0x%08x\nHeader CRC:0x%08x\n",
- img_header.length, img_header.img_CRC, img_header.CRC);
-}
-
-int main(int argc, char **argv)
-{
- int in_file;
- int status;
- int unsigned crc;
- int file_length;
- int len;
-
- struct stat file_stat;
-
- void *executable;
-
- in_file = open(argv[1], O_RDWR);
-
- if (in_file < 0) {
- printf("failed to open file:%s\n", argv[optind]);
- return -ENOENT;
- }
-
- status = fstat(in_file, &file_stat);
-
- /* read header and obtain size of image */
- status = read(in_file, &img_header, sizeof(img_header));
-
- file_length = file_stat.st_size - sizeof(img_header);
-
- if (img_header.length != file_length) {
- printf("size in header:%d, size of file: %d\n",
- img_header.length, file_length);
- }
- img_header.length = file_length;
-
- /* read working image and CRC */
- executable = malloc(file_length);
-
- status = read(in_file, executable, file_length);
-
- if (status != file_length) {
- printf("Failed to load image\n");
- free(executable);
- return -ENOENT;
- }
-
- /* verify image CRC */
- crc = crc32(0, (const unsigned char *) executable, img_header.length);
-
- if (crc != img_header.img_CRC) {
- printf("New Image CRC:0x%08x, hdr:0x%08x\n", crc,
- img_header.img_CRC);
- img_header.img_CRC = crc;
- }
- memcpy(img_header.code, "BOOT", 4);
- img_header.header_length = sizeof(img_header);
-
- /* check header CRC */
- crc = crc32(0, (const unsigned char *) &img_header,
- sizeof(img_header) - sizeof(unsigned int));
- if (crc != img_header.CRC) {
- printf("New header CRC - crc:0x%08x hdr:0x%08x\n", crc,
- img_header.CRC);
- img_header.CRC = crc;
- }
-
- /* re-write the file */
- status = lseek(in_file, 0, SEEK_SET);
- if (status != 0) {
- printf("failed to rewind\n");
- free(executable);
- return 1;
- }
- len = write(in_file, &img_header, sizeof(img_header));
- assert(len == sizeof(img_header));
- len = write(in_file, executable, file_length);
- assert(len == file_length);
- close(in_file);
- free(executable);
-
- return 0;
-}
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
-PKG_VERSION:=2024.01
+PKG_VERSION:=2024.04
PKG_RELEASE:=1
-PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
+PKG_HASH:=18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a
PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
define U-Boot/rk3566/Default
BUILD_SUBTARGET:=armv8
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3566
- ATF:=rk3568_bl31_v1.43.elf
- TPL:=rk3566_ddr_1056MHz_v1.18.bin
+ ATF:=rk3568_bl31_v1.44.elf
+ TPL:=rk3566_ddr_1056MHz_v1.21.bin
endef
define U-Boot/radxa-cm3-io-rk3566
define U-Boot/rk3568/Default
BUILD_SUBTARGET:=armv8
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3568
- ATF:=rk3568_bl31_v1.43.elf
- TPL:=rk3568_ddr_1560MHz_v1.18.bin
+ ATF:=rk3568_bl31_v1.44.elf
+ TPL:=rk3568_ddr_1560MHz_v1.21.bin
+endef
+
+define U-Boot/bpi-r2-pro-rk3568
+ $(U-Boot/rk3568/Default)
+ NAME:=Bananapi-R2 Pro
+ BUILD_DEVICES:= \
+ sinovoip_bpi-r2-pro
endef
define U-Boot/nanopi-r5c-rk3568
rock64-rk3328 \
rock-pi-e-rk3328 \
radxa-cm3-io-rk3566 \
+ bpi-r2-pro-rk3568 \
nanopi-r5c-rk3568 \
nanopi-r5s-rk3568 \
radxa-e25-rk3568
+++ /dev/null
-From 0bc16c6a8744a1c0293a31253020205b312895d3 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 23 Dec 2023 12:00:07 +0800
-Subject: [PATCH] board: rockchip: Add support for FriendlyARM NanoPi R2C Plus
-
-The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
-eMMC flash (8G) included.
-
-The device tree is taken from the kernel v6.5.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
----
- arch/arm/dts/Makefile | 1 +
- .../dts/rk3328-nanopi-r2c-plus-u-boot.dtsi | 9 ++
- arch/arm/dts/rk3328-nanopi-r2c-plus.dts | 33 +++++
- board/rockchip/evb_rk3328/MAINTAINERS | 6 +
- configs/nanopi-r2c-plus-rk3328_defconfig | 114 ++++++++++++++++++
- 5 files changed, 163 insertions(+)
- create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
- create mode 100644 arch/arm/dts/rk3328-nanopi-r2c-plus.dts
- create mode 100644 configs/nanopi-r2c-plus-rk3328_defconfig
-
---- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -126,6 +126,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
- dtb-$(CONFIG_ROCKCHIP_RK3328) += \
- rk3328-evb.dtb \
- rk3328-nanopi-r2c.dtb \
-+ rk3328-nanopi-r2c-plus.dtb \
- rk3328-nanopi-r2s.dtb \
- rk3328-orangepi-r1-plus.dtb \
- rk3328-orangepi-r1-plus-lts.dtb \
---- /dev/null
-+++ b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
-@@ -0,0 +1,9 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later
-+
-+#include "rk3328-nanopi-r2c-u-boot.dtsi"
-+
-+/ {
-+ chosen {
-+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
-+ };
-+};
---- /dev/null
-+++ b/arch/arm/dts/rk3328-nanopi-r2c-plus.dts
-@@ -0,0 +1,33 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3328-nanopi-r2c.dts"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R2C Plus";
-+ compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
-+
-+ aliases {
-+ mmc1 = &emmc;
-+ };
-+};
-+
-+&emmc {
-+ bus-width = <8>;
-+ cap-mmc-highspeed;
-+ max-frequency = <150000000>;
-+ mmc-ddr-1_8v;
-+ mmc-hs200-1_8v;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-+ vmmc-supply = <&vcc_io_33>;
-+ vqmmc-supply = <&vcc18_emmc>;
-+ status = "okay";
-+};
---- a/board/rockchip/evb_rk3328/MAINTAINERS
-+++ b/board/rockchip/evb_rk3328/MAINTAINERS
-@@ -11,6 +11,12 @@ S: Maintained
- F: configs/nanopi-r2c-rk3328_defconfig
- F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
-
-+NANOPI-R2C-PLUS-RK3328
-+M: Tianling Shen <cnsztl@gmail.com>
-+S: Maintained
-+F: configs/nanopi-r2c-plus-rk3328_defconfig
-+F: arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
-+
- NANOPI-R2S-RK3328
- M: David Bauer <mail@david-bauer.net>
- S: Maintained
---- /dev/null
-+++ b/configs/nanopi-r2c-plus-rk3328_defconfig
-@@ -0,0 +1,114 @@
-+CONFIG_ARM=y
-+CONFIG_SKIP_LOWLEVEL_INIT=y
-+CONFIG_COUNTER_FREQUENCY=24000000
-+CONFIG_ARCH_ROCKCHIP=y
-+CONFIG_TEXT_BASE=0x00200000
-+CONFIG_SPL_GPIO=y
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
-+CONFIG_SF_DEFAULT_SPEED=20000000
-+CONFIG_ENV_OFFSET=0x3F8000
-+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus"
-+CONFIG_DM_RESET=y
-+CONFIG_ROCKCHIP_RK3328=y
-+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-+CONFIG_TPL_LIBCOMMON_SUPPORT=y
-+CONFIG_TPL_LIBGENERIC_SUPPORT=y
-+CONFIG_SPL_DRIVERS_MISC=y
-+CONFIG_SPL_STACK_R_ADDR=0x600000
-+CONFIG_SPL_STACK=0x400000
-+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-+CONFIG_DEBUG_UART_BASE=0xFF130000
-+CONFIG_DEBUG_UART_CLOCK=24000000
-+CONFIG_SYS_LOAD_ADDR=0x800800
-+CONFIG_DEBUG_UART=y
-+# CONFIG_ANDROID_BOOT_IMAGE is not set
-+CONFIG_FIT=y
-+CONFIG_FIT_VERBOSE=y
-+CONFIG_SPL_LOAD_FIT=y
-+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb"
-+# CONFIG_DISPLAY_CPUINFO is not set
-+CONFIG_DISPLAY_BOARDINFO_LATE=y
-+CONFIG_MISC_INIT_R=y
-+CONFIG_SPL_MAX_SIZE=0x40000
-+CONFIG_SPL_PAD_TO=0x7f8000
-+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-+CONFIG_SPL_BSS_START_ADDR=0x2000000
-+CONFIG_SPL_BSS_MAX_SIZE=0x2000
-+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-+CONFIG_SPL_STACK_R=y
-+CONFIG_SPL_I2C=y
-+CONFIG_SPL_POWER=y
-+CONFIG_SPL_ATF=y
-+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
-+CONFIG_CMD_BOOTZ=y
-+CONFIG_CMD_GPT=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_USB=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_TIME=y
-+CONFIG_SPL_OF_CONTROL=y
-+CONFIG_TPL_OF_CONTROL=y
-+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-+CONFIG_TPL_OF_PLATDATA=y
-+CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-+CONFIG_SYS_MMC_ENV_DEV=1
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_TPL_DM=y
-+CONFIG_REGMAP=y
-+CONFIG_SPL_REGMAP=y
-+CONFIG_TPL_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_SPL_SYSCON=y
-+CONFIG_TPL_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_SPL_CLK=y
-+CONFIG_FASTBOOT_BUF_ADDR=0x800800
-+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-+CONFIG_ROCKCHIP_GPIO=y
-+CONFIG_SYS_I2C_ROCKCHIP=y
-+CONFIG_MISC=y
-+CONFIG_MMC_DW=y
-+CONFIG_MMC_DW_ROCKCHIP=y
-+CONFIG_ETH_DESIGNWARE=y
-+CONFIG_GMAC_ROCKCHIP=y
-+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-+CONFIG_PINCTRL=y
-+CONFIG_SPL_PINCTRL=y
-+CONFIG_DM_PMIC=y
-+CONFIG_PMIC_RK8XX=y
-+CONFIG_SPL_PMIC_RK8XX=y
-+CONFIG_SPL_DM_REGULATOR=y
-+CONFIG_REGULATOR_PWM=y
-+CONFIG_DM_REGULATOR_FIXED=y
-+CONFIG_SPL_DM_REGULATOR_FIXED=y
-+CONFIG_REGULATOR_RK8XX=y
-+CONFIG_PWM_ROCKCHIP=y
-+CONFIG_RAM=y
-+CONFIG_SPL_RAM=y
-+CONFIG_TPL_RAM=y
-+CONFIG_BAUDRATE=1500000
-+CONFIG_DEBUG_UART_SHIFT=2
-+CONFIG_SYS_NS16550_MEM32=y
-+CONFIG_SYSINFO=y
-+CONFIG_SYSRESET=y
-+# CONFIG_TPL_SYSRESET is not set
-+CONFIG_USB=y
-+CONFIG_USB_XHCI_HCD=y
-+CONFIG_USB_EHCI_HCD=y
-+CONFIG_USB_EHCI_GENERIC=y
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_USB_OHCI_GENERIC=y
-+CONFIG_USB_DWC2=y
-+CONFIG_USB_DWC3=y
-+# CONFIG_USB_DWC3_GADGET is not set
-+CONFIG_USB_DWC3_GENERIC=y
-+CONFIG_USB_GADGET=y
-+CONFIG_USB_GADGET_DWC2_OTG=y
-+CONFIG_SPL_TINY_MEMSET=y
-+CONFIG_TPL_TINY_MEMSET=y
-+CONFIG_ERRNO_STR=y
BUILD_DEVICES:=linksprite_a10-pcduino
endef
+define U-Boot/LicheePi_Zero
+ BUILD_SUBTARGET:=cortexa7
+ NAME:=Lichee Pi Zero V3s
+ BUILD_DEVICES:=licheepi_licheepi-zero-dock
+endef
+
define U-Boot/Linksprite_pcDuino3
BUILD_SUBTARGET:=cortexa7
NAME:=Linksprite pcDuino3
Marsboard_A10 \
Mele_M9 \
OLIMEX_A13_SOM \
+ LicheePi_Zero \
Linksprite_pcDuino \
Linksprite_pcDuino3 \
Linksprite_pcDuino3_Nano \
#
include $(TOPDIR)/rules.mk
-PKG_VERSION := 2020.04
-PKG_RELEASE:=3
+PKG_VERSION := 2024.04
+PKG_RELEASE:=1
-PKG_HASH := fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372
+PKG_HASH := 18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a
PKG_MAINTAINER := Tomasz Maciej Nowak <tmn505@gmail.com>
)
endef
-define Build/Configure
- sed '/select BINMAN/d' -i $(PKG_BUILD_DIR)/arch/arm/mach-tegra/Kconfig
- $(call Build/Configure/U-Boot)
-endef
-
define Build/Compile
$(call Build/Compile/U-Boot)
$(call Build/bct-image)
HOST_CPPFLAGS:=-I$(HOST_BUILD_DIR)/lib -I$(HOST_BUILD_DIR)/src $(HOST_CPPFLAGS)
TARGET_CPPFLAGS:=-I$(PKG_BUILD_DIR)/lib -I$(PKG_BUILD_DIR)/src $(TARGET_CPPFLAGS)
+HOST_CXXFLAGS += -std=c++11
+
define Package/gperf
SECTION:=devel
CATEGORY:=Development
PKG_RELEASE:=1
PKG_MAINTAINER:=Tony Ambardar <itugrok@yahoo.com>
-PKG_BUILD_FLAGS:=gc-sections lto
+PKG_BUILD_FLAGS:=no-lto
PKG_BUILD_PARALLEL:=1
PKG_FLAGS:=nonshared
define Package/kselftests-bpf
SECTION:=devel
CATEGORY:=Development
- DEPENDS:= +libelf +zlib +libpthread +librt @!IN_SDK \
- @KERNEL_DEBUG_FS @KERNEL_DEBUG_INFO_BTF @KERNEL_BPF_EVENTS
+ DEPENDS:= \
+ +libelf +zlib +libpthread +librt @!IN_SDK \
+ @KERNEL_DEBUG_FS @KERNEL_DEBUG_INFO_BTF @KERNEL_BPF_EVENTS
TITLE:=Linux Kernel Selftests (BPF)
URL:=http://www.kernel.org
endef
kselftests-bpf is the Linux kernel BPF test suite
endef
-TEST_TARGET = test_verifier
+EXE_TARGETS = test_verifier
+
+MOD_TARGETS = $(if $(call kernel_patchver_ge,6.4),bpf_testmod.ko)
MAKE_PATH:=tools/testing/selftests/bpf
MAKE_VARS = \
ARCH="$(LINUX_KARCH)" \
CROSS_COMPILE="$(TARGET_CROSS)" \
- SAN_CFLAGS="$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)" \
+ EXTRA_CFLAGS="$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)" \
LDLIBS="$(TARGET_LDFLAGS)" \
TOOLCHAIN_INCLUDE="$(TOOLCHAIN_INC_DIRS)" \
- VMLINUX_BTF="$(LINUX_DIR)/vmlinux"
+ KBUILD_OUTPUT="$(LINUX_DIR)"
MAKE_FLAGS = \
$(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='') \
- O=$(PKG_BUILD_DIR)
+ OUTPUT=$(PKG_BUILD_DIR)
define Build/Compile
+$(MAKE_VARS) \
$(MAKE) $(PKG_JOBS) -C $(LINUX_DIR)/$(MAKE_PATH) \
- $(MAKE_FLAGS) $(TEST_TARGET) ;
+ $(MAKE_FLAGS) $(EXE_TARGETS) $(MOD_TARGETS) ;
endef
define Package/kselftests-bpf/install
- $(INSTALL_DIR) $(1)/usr/bin
- $(INSTALL_BIN) $(PKG_BUILD_DIR)/$(TEST_TARGET) $(1)/usr/bin/
+ $(INSTALL_DIR) $(1)/usr/libexec/$(PKG_NAME)
+ $(foreach tgt,$(MOD_TARGETS), \
+ $(INSTALL_DATA) \
+ $(PKG_BUILD_DIR)/$(tgt) $(1)/usr/libexec/$(PKG_NAME); \
+ )
+ $(foreach tgt,$(EXE_TARGETS), \
+ $(INSTALL_BIN) \
+ $(PKG_BUILD_DIR)/$(tgt) $(1)/usr/libexec/$(PKG_NAME); \
+)
endef
$(eval $(call BuildPackage,kselftests-bpf))
O=$(PKG_BUILD_DIR) \
prefix=/usr
+ifeq ($(LINUX_KARCH),powerpc)
+ MAKE_FLAGS += NO_AUXTRACE=1
+endif
+
define Build/Compile
+$(MAKE) $(PKG_JOBS) $(MAKE_FLAGS) \
--no-print-directory \
include $(INCLUDE_DIR)/version.mk
PKG_NAME:=ipq-wifi
-PKG_RELEASE:=2
+PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/firmware/qca-wireless.git
-PKG_SOURCE_DATE:=2024-03-20
-PKG_SOURCE_VERSION:=87717baa8a7c922942f4202a0ec3de3cb5643941
-PKG_MIRROR_HASH:=a88124db0cd9a386d2cbd905e48408e7131f057240bcc7da93f7c5fc10ea4892
+PKG_SOURCE_DATE:=2024-04-26
+PKG_SOURCE_VERSION:=644ba9ea2e6685e420561ef098cb6fbaaf136cbf
+PKG_MIRROR_HASH:=3b913fd6fb0fac404b16e67c66d36c10315dba5459a8d495d870afcb1e2c33cd
PKG_FLAGS:=nonshared
include $(INCLUDE_DIR)/package.mk
edimax_cax1800 \
linksys_mx4200 \
linksys_mx5300 \
+ linksys_mx8500 \
netgear_lbr20 \
netgear_rax120v2 \
netgear_wax214 \
prpl_haze \
qnap_301w \
redmi_ax6 \
+ spectrum_sax1v1k \
wallys_dr40x9 \
xiaomi_ax3600 \
xiaomi_ax9000 \
yyets_le1 \
yuncore_ax880 \
yuncore_fap650 \
+ zbtlink_zbt-z800ax \
zte_mf269 \
zte_mf287 \
zte_mf287plus \
$(eval $(call generate-ipq-wifi-package,edimax_cax1800,Edimax CAX1800))
$(eval $(call generate-ipq-wifi-package,linksys_mx4200,Linksys MX4200))
$(eval $(call generate-ipq-wifi-package,linksys_mx5300,Linksys MX5300))
+$(eval $(call generate-ipq-wifi-package,linksys_mx8500,Linksys MX8500))
$(eval $(call generate-ipq-wifi-package,netgear_lbr20,Netgear LBR20))
$(eval $(call generate-ipq-wifi-package,netgear_rax120v2,Netgear RAX120v2))
$(eval $(call generate-ipq-wifi-package,netgear_wax214,Netgear WAX214))
$(eval $(call generate-ipq-wifi-package,qnap_301w,QNAP 301w))
$(eval $(call generate-ipq-wifi-package,prpl_haze,prpl Haze))
$(eval $(call generate-ipq-wifi-package,redmi_ax6,Redmi AX6))
+$(eval $(call generate-ipq-wifi-package,spectrum_sax1v1k,Spectrum SAX1V1K))
$(eval $(call generate-ipq-wifi-package,wallys_dr40x9,Wallys DR40X9))
$(eval $(call generate-ipq-wifi-package,xiaomi_ax3600,Xiaomi AX3600))
$(eval $(call generate-ipq-wifi-package,xiaomi_ax9000,Xiaomi AX9000))
$(eval $(call generate-ipq-wifi-package,yyets_le1,YYeTs LE1))
$(eval $(call generate-ipq-wifi-package,yuncore_ax880,Yuncore AX880))
$(eval $(call generate-ipq-wifi-package,yuncore_fap650,Yuncore FAP650))
+$(eval $(call generate-ipq-wifi-package,zbtlink_zbt-z800ax,Zbtlink ZBT-Z800AX))
$(eval $(call generate-ipq-wifi-package,zte_mf269,ZTE MF269))
$(eval $(call generate-ipq-wifi-package,zte_mf287,ZTE MF287))
$(eval $(call generate-ipq-wifi-package,zte_mf287plus,ZTE MF287Plus))
endef
$(eval $(call BuildPackage,rtl8723au-firmware))
+Package/rtl8723be-firmware = $(call Package/firmware-default,RealTek RTL8723BE firmware,,LICENCE.rtlwifi_firmware.txt)
+define Package/rtl8723be-firmware/install
+ $(INSTALL_DIR) $(1)/lib/firmware/rtlwifi
+ $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8723befw_36.bin $(1)/lib/firmware/rtlwifi
+ $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8723befw.bin $(1)/lib/firmware/rtlwifi
+endef
+$(eval $(call BuildPackage,rtl8723be-firmware))
+
Package/rtl8723bu-firmware = $(call Package/firmware-default,RealTek RTL8723BU firmware,,LICENCE.rtlwifi_firmware.txt)
define Package/rtl8723bu-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi
Package/rtl8821ae-firmware = $(call Package/firmware-default,RealTek RTL8821AE firmware,,LICENCE.rtlwifi_firmware.txt)
define Package/rtl8821ae-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi
- $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8821aefw.bin $(1)/lib/firmware/rtlwifi
+ $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8821aefw_29.bin $(1)/lib/firmware/rtlwifi
$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8821aefw_wowlan.bin $(1)/lib/firmware/rtlwifi
endef
$(eval $(call BuildPackage,rtl8821ae-firmware))
include $(TOPDIR)/rules.mk
PKG_NAME:=wireless-regdb
-PKG_VERSION:=2024.01.23
+PKG_VERSION:=2024.05.08
PKG_RELEASE:=1
PKG_LICENSE:=ISC
PKG_LICENSE_FILES:=LICENSE
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@KERNEL/software/network/wireless-regdb/
-PKG_HASH:=c8a61c9acf76fa7eb4239e89f640dee3e87098d9f69b4d3518c9c60fc6d20c55
+PKG_HASH:=9aee1d86ebebb363b714bec941b2820f31e3b7f1a485ddc9fcbd9985c7d3e7c4
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_SOURCE_URL:=https://github.com/greearb/ath10k-ct.git
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2023-06-05
-PKG_SOURCE_VERSION:=fadd0768cbd22248a60efbb219ccefc9d86cd78c
-PKG_MIRROR_HASH:=caaa373ae2cc6e443e8a31e43e5e2caca4f4ba2b9614efd3e5c9df401056d307
+PKG_SOURCE_DATE:=2024-03-02
+PKG_SOURCE_VERSION:=eb3f488a200fafc46140fd51b5e21f737ee50f24
+PKG_MIRROR_HASH:=bb1a92b2861a19c16e7edf046c54ebf681b6a3274601b7fb567877ccd9872a8c
# Build the 6.4 ath10k-ct driver version.
# Probably this should match as closely as
# possible to whatever mac80211 backports version is being used.
-CT_KVER="-6.4"
+CT_KVER="-6.7"
PKG_MAINTAINER:=Ben Greear <greearb@candelatech.com>
PKG_BUILD_PARALLEL:=1
+++ /dev/null
-From a227621b46df8a7a5c276131b245f40eac7513fb Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 3 Nov 2023 04:03:08 +0100
-Subject: [PATCH] ath10k-ct: port compilation warning for debug level to kernel
- 6.4
-
-Port compilation warning for debug level previously fixed in other
-kernel to kernel version 6.4.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- ath10k-6.4/debug.c | 85 ++++++++++++++++++++++++++--------------------
- 1 file changed, 48 insertions(+), 37 deletions(-)
-
---- a/ath10k-6.4/debug.c
-+++ b/ath10k-6.4/debug.c
-@@ -1345,47 +1345,58 @@ static const struct file_operations fops
- .llseek = default_llseek,
- };
-
-+static const char debug_level_buf[] =
-+ "To change debug level, set value adding up desired flags:\n"
-+ "PCI: 0x1\n"
-+ "WMI: 0x2\n"
-+ "HTC: 0x4\n"
-+ "HTT: 0x8\n"
-+ "MAC: 0x10\n"
-+ "BOOT: 0x20\n"
-+ "PCI-DUMP: 0x40\n"
-+ "HTT-DUMP: 0x80\n"
-+ "MGMT: 0x100\n"
-+ "DATA: 0x200\n"
-+ "BMI: 0x400\n"
-+ "REGULATORY: 0x800\n"
-+ "TESTMODE: 0x1000\n"
-+ "WMI-PRINT: 0x2000\n"
-+ "PCI-PS: 0x4000\n"
-+ "AHB: 0x8000\n"
-+ "SDIO: 0x10000\n"
-+ "SDIO_DUMP: 0x20000\n"
-+ "USB: 0x40000\n"
-+ "USB_BULK: 0x80000\n"
-+ "SNOC: 0x100000\n"
-+ "QMI: 0x200000\n"
-+ "BEACONS: 0x8000000\n"
-+ "NO-FW-DBGLOG:0x10000000\n"
-+ "MAC2: 0x20000000\n"
-+ "INFO-AS-DBG: 0x40000000\n"
-+ "FW: 0x80000000\n"
-+ "ALL: 0xEFFFFFFF\n";
-+
-+#define READ_DEBUG_LEVEL_SIZE sizeof(debug_level_buf) + 60
-+
- static ssize_t ath10k_read_debug_level(struct file *file,
- char __user *user_buf,
- size_t count, loff_t *ppos)
- {
-- int sz;
-- const char buf[] =
-- "To change debug level, set value adding up desired flags:\n"
-- "PCI: 0x1\n"
-- "WMI: 0x2\n"
-- "HTC: 0x4\n"
-- "HTT: 0x8\n"
-- "MAC: 0x10\n"
-- "BOOT: 0x20\n"
-- "PCI-DUMP: 0x40\n"
-- "HTT-DUMP: 0x80\n"
-- "MGMT: 0x100\n"
-- "DATA: 0x200\n"
-- "BMI: 0x400\n"
-- "REGULATORY: 0x800\n"
-- "TESTMODE: 0x1000\n"
-- "WMI-PRINT: 0x2000\n"
-- "PCI-PS: 0x4000\n"
-- "AHB: 0x8000\n"
-- "SDIO: 0x10000\n"
-- "SDIO_DUMP: 0x20000\n"
-- "USB: 0x40000\n"
-- "USB_BULK: 0x80000\n"
-- "SNOC: 0x100000\n"
-- "QMI: 0x200000\n"
-- "BEACONS: 0x8000000\n"
-- "NO-FW-DBGLOG:0x10000000\n"
-- "MAC2: 0x20000000\n"
-- "INFO-AS-DBG: 0x40000000\n"
-- "FW: 0x80000000\n"
-- "ALL: 0xEFFFFFFF\n";
-- char wbuf[sizeof(buf) + 60];
-- sz = snprintf(wbuf, sizeof(wbuf), "Current debug level: 0x%x\n\n%s",
-- ath10k_debug_mask, buf);
-- wbuf[sizeof(wbuf) - 1] = 0;
-+ int sz, ret;
-+ char *wbuf;
-+
-+ wbuf = kcalloc(READ_DEBUG_LEVEL_SIZE, sizeof(char), GFP_KERNEL);
-+ if (!wbuf)
-+ return -ENOMEM;
-+
-+ sz = snprintf(wbuf, READ_DEBUG_LEVEL_SIZE,
-+ "Current debug level: 0x%x\n\n%s",
-+ ath10k_debug_mask, debug_level_buf);
-+
-+ ret = simple_read_from_buffer(user_buf, count, ppos, wbuf, sz);
-+ kfree(wbuf);
-
-- return simple_read_from_buffer(user_buf, count, ppos, wbuf, sz);
-+ return ret;
- }
-
- /* Set logging level.
Signed-off-by: Vincent Tremblay <vincent@vtremblay.dev>
---- a/ath10k-6.4/core.c
-+++ b/ath10k-6.4/core.c
+--- a/ath10k-6.7/core.c
++++ b/ath10k-6.7/core.c
@@ -2869,14 +2869,14 @@ done:
static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar)
{
* cleanup includes
- ath10k-6.4/Kconfig | 10 +++
- ath10k-6.4/Makefile | 1 +
- ath10k-6.4/core.c | 22 +++++++
- ath10k-6.4/core.h | 9 ++-
- ath10k-6.4/hw.h | 1 +
- ath10k-6.4/leds.c | 103 ++++++++++++++++++++++++++++++
- ath10k-6.4/leds.h | 45 +++++++++++++
- ath10k-6.4/mac.c | 1 +
- ath10k-6.4/wmi-ops.h | 32 ++++++++++
- ath10k-6.4/wmi-tlv.c | 2 +
- ath10k-6.4/wmi.c | 54 ++++++++++++++++
- ath10k-6.4/wmi.h | 35 ++++++++++
+ ath10k-6.7/Kconfig | 10 +++
+ ath10k-6.7/Makefile | 1 +
+ ath10k-6.7/core.c | 22 +++++++
+ ath10k-6.7/core.h | 9 ++-
+ ath10k-6.7/hw.h | 1 +
+ ath10k-6.7/leds.c | 103 ++++++++++++++++++++++++++++++
+ ath10k-6.7/leds.h | 45 +++++++++++++
+ ath10k-6.7/mac.c | 1 +
+ ath10k-6.7/wmi-ops.h | 32 ++++++++++
+ ath10k-6.7/wmi-tlv.c | 2 +
+ ath10k-6.7/wmi.c | 54 ++++++++++++++++
+ ath10k-6.7/wmi.h | 35 ++++++++++
12 files changed, 314 insertions(+), 1 deletion(-)
- create mode 100644 ath10k-6.4/leds.c
- create mode 100644 ath10k-6.4/leds.h
+ create mode 100644 ath10k-6.7/leds.c
+ create mode 100644 ath10k-6.7/leds.h
---- a/ath10k-6.4/Kconfig
-+++ b/ath10k-6.4/Kconfig
+--- a/ath10k-6.7/Kconfig
++++ b/ath10k-6.7/Kconfig
@@ -67,6 +67,16 @@ config ATH10K_DEBUGFS
If unsure, say Y to make it easier to debug problems.
config ATH10K_SPECTRAL
bool "Atheros ath10k spectral scan support"
depends on ATH10K_DEBUGFS
---- a/ath10k-6.4/Makefile
-+++ b/ath10k-6.4/Makefile
+--- a/ath10k-6.7/Makefile
++++ b/ath10k-6.7/Makefile
@@ -20,6 +20,7 @@ ath10k_core-$(CONFIG_ATH10K_SPECTRAL) +=
ath10k_core-$(CONFIG_NL80211_TESTMODE) += testmode.o
ath10k_core-$(CONFIG_ATH10K_TRACING) += trace.o
ath10k_core-$(CONFIG_MAC80211_DEBUGFS) += debugfs_sta.o
ath10k_core-$(CONFIG_PM) += wow.o
ath10k_core-$(CONFIG_ATH10K_CE) += ce.o
---- a/ath10k-6.4/core.c
-+++ b/ath10k-6.4/core.c
+--- a/ath10k-6.7/core.c
++++ b/ath10k-6.7/core.c
@@ -28,6 +28,7 @@
#include "testmode.h"
#include "wmi-ops.h"
.patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
.uart_pin = 7,
.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
-@@ -4080,6 +4086,10 @@ int ath10k_core_start(struct ath10k *ar,
+@@ -4071,6 +4077,10 @@ int ath10k_core_start(struct ath10k *ar,
ath10k_wmi_check_apply_board_power_ctl_table(ar);
}
return 0;
err_hif_stop:
-@@ -4341,9 +4351,18 @@ static void ath10k_core_register_work(st
+@@ -4332,9 +4342,18 @@ static void ath10k_core_register_work(st
goto err_spectral_destroy;
}
err_spectral_destroy:
ath10k_spectral_destroy(ar);
err_debug_destroy:
-@@ -4403,6 +4422,8 @@ void ath10k_core_unregister(struct ath10
+@@ -4394,6 +4413,8 @@ void ath10k_core_unregister(struct ath10
if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
return;
ath10k_thermal_unregister(ar);
/* Stop spectral before unregistering from mac80211 to remove the
* relayfs debugfs file cleanly. Otherwise the parent debugfs tree
---- a/ath10k-6.4/core.h
-+++ b/ath10k-6.4/core.h
+--- a/ath10k-6.7/core.h
++++ b/ath10k-6.7/core.h
@@ -14,6 +14,7 @@
#include <linux/pci.h>
#include <linux/uuid.h>
#include "htt.h"
#include "htc.h"
-@@ -1586,6 +1587,13 @@ struct ath10k {
+@@ -1589,6 +1590,13 @@ struct ath10k {
} testmode;
struct {
/* protected by data_lock */
u32 rx_crc_err_drop;
u32 fw_crash_counter;
---- a/ath10k-6.4/hw.h
-+++ b/ath10k-6.4/hw.h
+--- a/ath10k-6.7/hw.h
++++ b/ath10k-6.7/hw.h
@@ -523,6 +523,7 @@ struct ath10k_hw_params {
const char *name;
u32 patch_load_addr;
/* Type of hw cycle counter wraparound logic, for more info
--- /dev/null
-+++ b/ath10k-6.4/leds.c
++++ b/ath10k-6.7/leds.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2005-2011 Atheros Communications Inc.
+}
+
--- /dev/null
-+++ b/ath10k-6.4/leds.h
++++ b/ath10k-6.7/leds.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#endif
+#endif /* _LEDS_H_ */
---- a/ath10k-6.4/mac.c
-+++ b/ath10k-6.4/mac.c
+--- a/ath10k-6.7/mac.c
++++ b/ath10k-6.7/mac.c
@@ -25,6 +25,7 @@
#include "wmi-tlv.h"
#include "wmi-ops.h"
/*********/
/* Rates */
---- a/ath10k-6.4/wmi-ops.h
-+++ b/ath10k-6.4/wmi-ops.h
+--- a/ath10k-6.7/wmi-ops.h
++++ b/ath10k-6.7/wmi-ops.h
@@ -228,7 +228,10 @@ struct wmi_ops {
const struct wmi_bb_timing_cfg_arg *arg);
struct sk_buff *(*gen_per_peer_per_tid_cfg)(struct ath10k *ar,
static inline int
ath10k_wmi_dbglog_cfg(struct ath10k *ar, u64 module_enable, u32 log_level)
{
---- a/ath10k-6.4/wmi-tlv.c
-+++ b/ath10k-6.4/wmi-tlv.c
+--- a/ath10k-6.7/wmi-tlv.c
++++ b/ath10k-6.7/wmi-tlv.c
@@ -4601,6 +4601,8 @@ static const struct wmi_ops wmi_tlv_ops
.gen_echo = ath10k_wmi_tlv_op_gen_echo,
.gen_vdev_spectral_conf = ath10k_wmi_tlv_op_gen_vdev_spectral_conf,
};
static const struct wmi_peer_flags_map wmi_tlv_peer_flags_map = {
---- a/ath10k-6.4/wmi.c
-+++ b/ath10k-6.4/wmi.c
-@@ -8438,6 +8438,49 @@ ath10k_wmi_op_gen_peer_set_param(struct
+--- a/ath10k-6.7/wmi.c
++++ b/ath10k-6.7/wmi.c
+@@ -8446,6 +8446,49 @@ ath10k_wmi_op_gen_peer_set_param(struct
return skb;
}
static struct sk_buff *
ath10k_wmi_op_gen_set_psmode(struct ath10k *ar, u32 vdev_id,
enum wmi_sta_ps_mode psmode)
-@@ -10269,6 +10312,9 @@ static const struct wmi_ops wmi_ops = {
+@@ -10255,6 +10298,9 @@ static const struct wmi_ops wmi_ops = {
.fw_stats_fill = ath10k_wmi_main_op_fw_stats_fill,
.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,
.gen_echo = ath10k_wmi_op_gen_echo,
/* .gen_bcn_tmpl not implemented */
/* .gen_prb_tmpl not implemented */
/* .gen_p2p_go_bcn_ie not implemented */
-@@ -10339,6 +10385,8 @@ static const struct wmi_ops wmi_10_1_ops
+@@ -10325,6 +10371,8 @@ static const struct wmi_ops wmi_10_1_ops
.fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill,
.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,
.gen_echo = ath10k_wmi_op_gen_echo,
/* .gen_bcn_tmpl not implemented */
/* .gen_prb_tmpl not implemented */
/* .gen_p2p_go_bcn_ie not implemented */
-@@ -10418,6 +10466,8 @@ static const struct wmi_ops wmi_10_2_ops
+@@ -10404,6 +10452,8 @@ static const struct wmi_ops wmi_10_2_ops
.gen_delba_send = ath10k_wmi_op_gen_delba_send,
.fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill,
.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,
/* .gen_pdev_enable_adaptive_cca not implemented */
};
-@@ -10489,6 +10539,8 @@ static const struct wmi_ops wmi_10_2_4_o
+@@ -10475,6 +10525,8 @@ static const struct wmi_ops wmi_10_2_4_o
ath10k_wmi_op_gen_pdev_enable_adaptive_cca,
.get_vdev_subtype = ath10k_wmi_10_2_4_op_get_vdev_subtype,
.gen_bb_timing = ath10k_wmi_10_2_4_op_gen_bb_timing,
/* .gen_bcn_tmpl not implemented */
/* .gen_prb_tmpl not implemented */
/* .gen_p2p_go_bcn_ie not implemented */
-@@ -10571,6 +10623,8 @@ static const struct wmi_ops wmi_10_4_ops
+@@ -10557,6 +10609,8 @@ static const struct wmi_ops wmi_10_4_ops
.gen_pdev_bss_chan_info_req = ath10k_wmi_10_2_op_gen_pdev_bss_chan_info,
.gen_echo = ath10k_wmi_op_gen_echo,
.gen_pdev_get_tpc_config = ath10k_wmi_10_2_4_op_gen_pdev_get_tpc_config,
};
int ath10k_wmi_attach(struct ath10k *ar)
---- a/ath10k-6.4/wmi.h
-+++ b/ath10k-6.4/wmi.h
+--- a/ath10k-6.7/wmi.h
++++ b/ath10k-6.7/wmi.h
@@ -3133,6 +3133,41 @@ enum wmi_10_4_feature_mask {
};
Signed-off-by: Mathias Kresin <dev@kresin.me>
---
- ath10k-6.4/core.h | 4 ++++
- ath10k-6.4/leds.c | 4 +---
- ath10k-6.4/mac.c | 2 +-
+ ath10k-6.7/core.h | 4 ++++
+ ath10k-6.7/leds.c | 4 +---
+ ath10k-6.7/mac.c | 2 +-
3 files changed, 6 insertions(+), 4 deletions(-)
---- a/ath10k-6.4/core.h
-+++ b/ath10k-6.4/core.h
-@@ -1701,6 +1701,10 @@ struct ath10k {
+--- a/ath10k-6.7/core.h
++++ b/ath10k-6.7/core.h
+@@ -1704,6 +1704,10 @@ struct ath10k {
u8 csi_data[4096];
u16 csi_data_len;
/* must be last */
u8 drv_priv[] __aligned(sizeof(void *));
};
---- a/ath10k-6.4/leds.c
-+++ b/ath10k-6.4/leds.c
+--- a/ath10k-6.7/leds.c
++++ b/ath10k-6.7/leds.c
@@ -81,9 +81,7 @@ int ath10k_leds_register(struct ath10k *
ar->leds.cdev.name = ar->leds.label;
ret = led_classdev_register(wiphy_dev(ar->hw->wiphy), &ar->leds.cdev);
if (ret)
---- a/ath10k-6.4/mac.c
-+++ b/ath10k-6.4/mac.c
-@@ -11616,7 +11616,7 @@ int ath10k_mac_register(struct ath10k *a
+--- a/ath10k-6.7/mac.c
++++ b/ath10k-6.7/mac.c
+@@ -11622,7 +11622,7 @@ int ath10k_mac_register(struct ath10k *a
ar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER;
#ifdef CPTCFG_MAC80211_LEDS
---- a/ath10k-6.4/wmi.h
-+++ b/ath10k-6.4/wmi.h
+--- a/ath10k-6.7/wmi.h
++++ b/ath10k-6.7/wmi.h
@@ -6341,7 +6341,7 @@ struct qca9880_set_ctl_table_cmd {
__le32 ctl_len; /* in bytes. This may be ignored in firmware,
* make sure ctl_info data is sizeof(qca9880_power_ctl) */
---- a/ath10k-6.4/htt.h
-+++ b/ath10k-6.4/htt.h
+--- a/ath10k-6.7/htt.h
++++ b/ath10k-6.7/htt.h
@@ -237,7 +237,11 @@ enum htt_rx_ring_flags {
};
---- a/ath10k-6.4/pci.c
-+++ b/ath10k-6.4/pci.c
+--- a/ath10k-6.7/pci.c
++++ b/ath10k-6.7/pci.c
@@ -131,7 +131,11 @@ static const struct ce_attr pci_host_ce_
.flags = CE_ATTR_FLAGS,
.src_nentries = 0,
+++ /dev/null
---- a/ath10k-5.15/core.c
-+++ b/ath10k-5.15/core.c
-@@ -2970,7 +2970,7 @@ static void ath10k_core_set_coverage_cla
- set_coverage_class_work);
-
- if (ar->hw_params.hw_ops->set_coverage_class)
-- ar->hw_params.hw_ops->set_coverage_class(ar, -1);
-+ ar->hw_params.hw_ops->set_coverage_class(ar, ar->fw_coverage.coverage_class);
- }
-
- static int ath10k_core_init_firmware_features(struct ath10k *ar)
---- a/ath10k-5.15/hw.c
-+++ b/ath10k-5.15/hw.c
-@@ -584,6 +584,56 @@ void ath10k_hw_fill_survey_time(struct a
- survey->time_busy = CCNT_TO_MSEC(ar, rcc);
- }
-
-+/* Wireless firmware version 10.4 supports setting Coverage Class by
-++ * setting via wmi tx_ack_timeout; chipsets a.o. ipq40xx, qca99xx
-++*/
-+static void ath10k_hw_qca99xx_set_coverage_class(struct ath10k *ar,
-+ s16 value)
-+{
-+ u32 timeout;
-+ int ret;
-+
-+ mutex_lock(&ar->conf_mutex);
-+
-+ /* Only execute if the core is started. */
-+ if ((ar->state != ATH10K_STATE_ON) &&
-+ (ar->state != ATH10K_STATE_RESTARTED)) {
-+ ath10k_warn(ar, "ath10k core not yet started");
-+ goto unlock;
-+ }
-+
-+ if (value < 0)
-+ value = ar->fw_coverage.coverage_class;
-+
-+ /* WIP: it appears that one wmi timeout unit accounts for 3 C.Class units
-+ * so we need an integer divide by three; feedback welcome for distances
-+ * 10-20 km; tested at 7 km */
-+ if (value > 0) {
-+ timeout = 0x40 + (value / 3) + 0x01;
-+
-+ /* Limit to 0xff as the destination register is u8 */
-+ if (timeout > 0xff)
-+ timeout = 0xff;
-+ }
-+ else
-+ timeout = 0x40;
-+
-+ /* set Coverage Class via wmi */
-+ ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->tx_ack_timeout,
-+ timeout);
-+ if (ret) {
-+ ath10k_warn(ar, "failed to set tx-acktimeout: %d, timeout: 0x%x\n"
-+ , ret, timeout);
-+ }
-+
-+unlock:
-+ spin_lock_bh(&ar->data_lock);
-+ ar->fw_coverage.coverage_class = value;
-+ spin_unlock_bh(&ar->data_lock);
-+
-+ mutex_unlock(&ar->conf_mutex);
-+}
-+
- /* The stock firmware does not support setting the coverage class. Instead this
- * function monitors and modifies the corresponding MAC registers.
- */
-@@ -1172,6 +1222,7 @@ static bool ath10k_qca99x0_rx_desc_msdu_
- }
-
- const struct ath10k_hw_ops qca99x0_ops = {
-+ .set_coverage_class = ath10k_hw_qca99xx_set_coverage_class,
- .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
- .rx_desc_get_msdu_limit_error = ath10k_qca99x0_rx_desc_msdu_limit_error,
- .is_rssi_enable = ath10k_htt_tx_rssi_enable,
---- a/ath10k-5.15/wmi.c
-+++ b/ath10k-5.15/wmi.c
-@@ -1164,6 +1164,7 @@ static struct wmi_pdev_param_map wmi_pde
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
-@@ -1260,6 +1261,7 @@ static struct wmi_pdev_param_map wmi_10x
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = {
-@@ -1357,6 +1359,7 @@ static struct wmi_pdev_param_map wmi_10_
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- /* firmware 10.2 specific mappings */
-@@ -1617,6 +1620,7 @@ static struct wmi_pdev_param_map wmi_10_
- .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
- .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
- .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
-+ .tx_ack_timeout = WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT,
- };
-
- static const u8 wmi_key_cipher_suites[] = {
---- a/ath10k-5.15/wmi.h
-+++ b/ath10k-5.15/wmi.h
-@@ -3937,6 +3937,7 @@ struct wmi_pdev_param_map {
- u32 rfkill_config;
- u32 rfkill_enable;
- u32 peer_stats_info_enable;
-+ u32 tx_ack_timeout;
- };
-
- #define WMI_PDEV_PARAM_UNSUPPORTED 0
-@@ -4257,6 +4258,8 @@ enum wmi_10_4_pdev_param {
- WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
- WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
- WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
-+ /* TX acknowledge timeout. Advised range: 0x40 - 0xFF microsec. */
-+ WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT = 0x68,
- };
-
- struct wmi_pdev_set_param_cmd {
---- a/ath10k-5.17/core.c
-+++ b/ath10k-5.17/core.c
-@@ -3035,7 +3035,7 @@ static void ath10k_core_set_coverage_cla
- set_coverage_class_work);
-
- if (ar->hw_params.hw_ops->set_coverage_class)
-- ar->hw_params.hw_ops->set_coverage_class(ar, -1);
-+ ar->hw_params.hw_ops->set_coverage_class(ar, ar->fw_coverage.coverage_class);
- }
-
- static int ath10k_core_init_firmware_features(struct ath10k *ar)
---- a/ath10k-5.17/hw.c
-+++ b/ath10k-5.17/hw.c
-@@ -584,6 +584,56 @@ void ath10k_hw_fill_survey_time(struct a
- survey->time_busy = CCNT_TO_MSEC(ar, rcc);
- }
-
-+/* Wireless firmware version 10.4 supports setting Coverage Class by
-++ * setting via wmi tx_ack_timeout; chipsets a.o. ipq40xx, qca99xx
-++*/
-+static void ath10k_hw_qca99xx_set_coverage_class(struct ath10k *ar,
-+ s16 value)
-+{
-+ u32 timeout;
-+ int ret;
-+
-+ mutex_lock(&ar->conf_mutex);
-+
-+ /* Only execute if the core is started. */
-+ if ((ar->state != ATH10K_STATE_ON) &&
-+ (ar->state != ATH10K_STATE_RESTARTED)) {
-+ ath10k_warn(ar, "ath10k core not yet started");
-+ goto unlock;
-+ }
-+
-+ if (value < 0)
-+ value = ar->fw_coverage.coverage_class;
-+
-+ /* WIP: it appears that one wmi timeout unit accounts for 3 C.Class units
-+ * so we need an integer divide by three; feedback welcome for distances
-+ * 10-20 km; tested at 7 km */
-+ if (value > 0) {
-+ timeout = 0x40 + (value / 3) + 0x01;
-+
-+ /* Limit to 0xff as the destination register is u8 */
-+ if (timeout > 0xff)
-+ timeout = 0xff;
-+ }
-+ else
-+ timeout = 0x40;
-+
-+ /* set Coverage Class via wmi */
-+ ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->tx_ack_timeout,
-+ timeout);
-+ if (ret) {
-+ ath10k_warn(ar, "failed to set tx-acktimeout: %d, timeout: 0x%x\n"
-+ , ret, timeout);
-+ }
-+
-+unlock:
-+ spin_lock_bh(&ar->data_lock);
-+ ar->fw_coverage.coverage_class = value;
-+ spin_unlock_bh(&ar->data_lock);
-+
-+ mutex_unlock(&ar->conf_mutex);
-+}
-+
- /* The stock firmware does not support setting the coverage class. Instead this
- * function monitors and modifies the corresponding MAC registers.
- */
-@@ -1172,6 +1222,7 @@ static bool ath10k_qca99x0_rx_desc_msdu_
- }
-
- const struct ath10k_hw_ops qca99x0_ops = {
-+ .set_coverage_class = ath10k_hw_qca99xx_set_coverage_class,
- .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
- .rx_desc_get_msdu_limit_error = ath10k_qca99x0_rx_desc_msdu_limit_error,
- .is_rssi_enable = ath10k_htt_tx_rssi_enable,
---- a/ath10k-5.17/wmi.c
-+++ b/ath10k-5.17/wmi.c
-@@ -1164,6 +1164,7 @@ static struct wmi_pdev_param_map wmi_pde
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
-@@ -1260,6 +1261,7 @@ static struct wmi_pdev_param_map wmi_10x
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = {
-@@ -1357,6 +1359,7 @@ static struct wmi_pdev_param_map wmi_10_
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- /* firmware 10.2 specific mappings */
-@@ -1617,6 +1620,7 @@ static struct wmi_pdev_param_map wmi_10_
- .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
- .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
- .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
-+ .tx_ack_timeout = WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT,
- };
-
- static const u8 wmi_key_cipher_suites[] = {
---- a/ath10k-5.17/wmi.h
-+++ b/ath10k-5.17/wmi.h
-@@ -3939,6 +3939,7 @@ struct wmi_pdev_param_map {
- u32 rfkill_config;
- u32 rfkill_enable;
- u32 peer_stats_info_enable;
-+ u32 tx_ack_timeout;
- };
-
- #define WMI_PDEV_PARAM_UNSUPPORTED 0
-@@ -4259,6 +4260,8 @@ enum wmi_10_4_pdev_param {
- WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
- WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
- WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
-+ /* TX acknowledge timeout. Advised range: 0x40 - 0xFF microsec. */
-+ WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT = 0x68,
- };
-
- struct wmi_pdev_set_param_cmd {
---- a/ath10k-5.19/core.c
-+++ b/ath10k-5.19/core.c
-@@ -3091,7 +3091,7 @@ static void ath10k_core_set_coverage_cla
- set_coverage_class_work);
-
- if (ar->hw_params.hw_ops->set_coverage_class)
-- ar->hw_params.hw_ops->set_coverage_class(ar, -1);
-+ ar->hw_params.hw_ops->set_coverage_class(ar, ar->fw_coverage.coverage_class);
- }
-
- static int ath10k_core_init_firmware_features(struct ath10k *ar)
---- a/ath10k-5.19/hw.c
-+++ b/ath10k-5.19/hw.c
-@@ -585,6 +585,56 @@ void ath10k_hw_fill_survey_time(struct a
- survey->time_busy = CCNT_TO_MSEC(ar, rcc);
- }
-
-+/* Wireless firmware version 10.4 supports setting Coverage Class by
-++ * setting via wmi tx_ack_timeout; chipsets a.o. ipq40xx, qca99xx
-++*/
-+static void ath10k_hw_qca99xx_set_coverage_class(struct ath10k *ar,
-+ s16 value)
-+{
-+ u32 timeout;
-+ int ret;
-+
-+ mutex_lock(&ar->conf_mutex);
-+
-+ /* Only execute if the core is started. */
-+ if ((ar->state != ATH10K_STATE_ON) &&
-+ (ar->state != ATH10K_STATE_RESTARTED)) {
-+ ath10k_warn(ar, "ath10k core not yet started");
-+ goto unlock;
-+ }
-+
-+ if (value < 0)
-+ value = ar->fw_coverage.coverage_class;
-+
-+ /* WIP: it appears that one wmi timeout unit accounts for 3 C.Class units
-+ * so we need an integer divide by three; feedback welcome for distances
-+ * 10-20 km; tested at 7 km */
-+ if (value > 0) {
-+ timeout = 0x40 + (value / 3) + 0x01;
-+
-+ /* Limit to 0xff as the destination register is u8 */
-+ if (timeout > 0xff)
-+ timeout = 0xff;
-+ }
-+ else
-+ timeout = 0x40;
-+
-+ /* set Coverage Class via wmi */
-+ ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->tx_ack_timeout,
-+ timeout);
-+ if (ret) {
-+ ath10k_warn(ar, "failed to set tx-acktimeout: %d, timeout: 0x%x\n"
-+ , ret, timeout);
-+ }
-+
-+unlock:
-+ spin_lock_bh(&ar->data_lock);
-+ ar->fw_coverage.coverage_class = value;
-+ spin_unlock_bh(&ar->data_lock);
-+
-+ mutex_unlock(&ar->conf_mutex);
-+}
-+
- /* The stock firmware does not support setting the coverage class. Instead this
- * function monitors and modifies the corresponding MAC registers.
- */
-@@ -1161,6 +1211,7 @@ const struct ath10k_hw_ops qca988x_ops =
- };
-
- const struct ath10k_hw_ops qca99x0_ops = {
-+ .set_coverage_class = ath10k_hw_qca99xx_set_coverage_class,
- .is_rssi_enable = ath10k_htt_tx_rssi_enable,
- };
-
---- a/ath10k-5.19/wmi.c
-+++ b/ath10k-5.19/wmi.c
-@@ -1164,6 +1164,7 @@ static struct wmi_pdev_param_map wmi_pde
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
-@@ -1260,6 +1261,7 @@ static struct wmi_pdev_param_map wmi_10x
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = {
-@@ -1357,6 +1359,7 @@ static struct wmi_pdev_param_map wmi_10_
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- /* firmware 10.2 specific mappings */
-@@ -1617,6 +1620,7 @@ static struct wmi_pdev_param_map wmi_10_
- .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
- .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
- .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
-+ .tx_ack_timeout = WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT,
- };
-
- static const u8 wmi_key_cipher_suites[] = {
---- a/ath10k-5.19/wmi.h
-+++ b/ath10k-5.19/wmi.h
-@@ -3939,6 +3939,7 @@ struct wmi_pdev_param_map {
- u32 rfkill_config;
- u32 rfkill_enable;
- u32 peer_stats_info_enable;
-+ u32 tx_ack_timeout;
- };
-
- #define WMI_PDEV_PARAM_UNSUPPORTED 0
-@@ -4259,6 +4260,8 @@ enum wmi_10_4_pdev_param {
- WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
- WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
- WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
-+ /* TX acknowledge timeout. Advised range: 0x40 - 0xFF microsec. */
-+ WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT = 0x68,
- };
-
- struct wmi_pdev_set_param_cmd {
---- a/ath10k-6.2/core.c
-+++ b/ath10k-6.2/core.c
-@@ -3116,7 +3116,7 @@ static void ath10k_core_set_coverage_cla
- set_coverage_class_work);
-
- if (ar->hw_params.hw_ops->set_coverage_class)
-- ar->hw_params.hw_ops->set_coverage_class(ar, -1);
-+ ar->hw_params.hw_ops->set_coverage_class(ar, ar->fw_coverage.coverage_class);
- }
-
- static int ath10k_core_init_firmware_features(struct ath10k *ar)
---- a/ath10k-6.2/hw.c
-+++ b/ath10k-6.2/hw.c
-@@ -585,6 +585,56 @@ void ath10k_hw_fill_survey_time(struct a
- survey->time_busy = CCNT_TO_MSEC(ar, rcc);
- }
-
-+/* Wireless firmware version 10.4 supports setting Coverage Class by
-++ * setting via wmi tx_ack_timeout; chipsets a.o. ipq40xx, qca99xx
-++*/
-+static void ath10k_hw_qca99xx_set_coverage_class(struct ath10k *ar,
-+ s16 value)
-+{
-+ u32 timeout;
-+ int ret;
-+
-+ mutex_lock(&ar->conf_mutex);
-+
-+ /* Only execute if the core is started. */
-+ if ((ar->state != ATH10K_STATE_ON) &&
-+ (ar->state != ATH10K_STATE_RESTARTED)) {
-+ ath10k_warn(ar, "ath10k core not yet started");
-+ goto unlock;
-+ }
-+
-+ if (value < 0)
-+ value = ar->fw_coverage.coverage_class;
-+
-+ /* WIP: it appears that one wmi timeout unit accounts for 3 C.Class units
-+ * so we need an integer divide by three; feedback welcome for distances
-+ * 10-20 km; tested at 7 km */
-+ if (value > 0) {
-+ timeout = 0x40 + (value / 3) + 0x01;
-+
-+ /* Limit to 0xff as the destination register is u8 */
-+ if (timeout > 0xff)
-+ timeout = 0xff;
-+ }
-+ else
-+ timeout = 0x40;
-+
-+ /* set Coverage Class via wmi */
-+ ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->tx_ack_timeout,
-+ timeout);
-+ if (ret) {
-+ ath10k_warn(ar, "failed to set tx-acktimeout: %d, timeout: 0x%x\n"
-+ , ret, timeout);
-+ }
-+
-+unlock:
-+ spin_lock_bh(&ar->data_lock);
-+ ar->fw_coverage.coverage_class = value;
-+ spin_unlock_bh(&ar->data_lock);
-+
-+ mutex_unlock(&ar->conf_mutex);
-+}
-+
- /* The stock firmware does not support setting the coverage class. Instead this
- * function monitors and modifies the corresponding MAC registers.
- */
-@@ -1161,6 +1211,7 @@ const struct ath10k_hw_ops qca988x_ops =
- };
-
- const struct ath10k_hw_ops qca99x0_ops = {
-+ .set_coverage_class = ath10k_hw_qca99xx_set_coverage_class,
- .is_rssi_enable = ath10k_htt_tx_rssi_enable,
- };
-
---- a/ath10k-6.2/wmi.c
-+++ b/ath10k-6.2/wmi.c
-@@ -1164,6 +1164,7 @@ static struct wmi_pdev_param_map wmi_pde
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
-@@ -1260,6 +1261,7 @@ static struct wmi_pdev_param_map wmi_10x
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = {
-@@ -1357,6 +1359,7 @@ static struct wmi_pdev_param_map wmi_10_
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- /* firmware 10.2 specific mappings */
-@@ -1617,6 +1620,7 @@ static struct wmi_pdev_param_map wmi_10_
- .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
- .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
- .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
-+ .tx_ack_timeout = WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT,
- };
-
- static const u8 wmi_key_cipher_suites[] = {
---- a/ath10k-6.2/wmi.h
-+++ b/ath10k-6.2/wmi.h
-@@ -3974,6 +3974,7 @@ struct wmi_pdev_param_map {
- u32 rfkill_config;
- u32 rfkill_enable;
- u32 peer_stats_info_enable;
-+ u32 tx_ack_timeout;
- };
-
- #define WMI_PDEV_PARAM_UNSUPPORTED 0
-@@ -4294,6 +4295,8 @@ enum wmi_10_4_pdev_param {
- WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
- WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
- WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
-+ /* TX acknowledge timeout. Advised range: 0x40 - 0xFF microsec. */
-+ WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT = 0x68,
- };
-
- struct wmi_pdev_set_param_cmd {
---- a/ath10k-6.4/core.c
-+++ b/ath10k-6.4/core.c
-@@ -3110,7 +3110,7 @@ static void ath10k_core_set_coverage_cla
- set_coverage_class_work);
-
- if (ar->hw_params.hw_ops->set_coverage_class)
-- ar->hw_params.hw_ops->set_coverage_class(ar, -1);
-+ ar->hw_params.hw_ops->set_coverage_class(ar, ar->fw_coverage.coverage_class);
- }
-
- static int ath10k_core_init_firmware_features(struct ath10k *ar)
---- a/ath10k-6.4/hw.c
-+++ b/ath10k-6.4/hw.c
-@@ -585,6 +585,56 @@ void ath10k_hw_fill_survey_time(struct a
- survey->time_busy = CCNT_TO_MSEC(ar, rcc);
- }
-
-+/* Wireless firmware version 10.4 supports setting Coverage Class by
-++ * setting via wmi tx_ack_timeout; chipsets a.o. ipq40xx, qca99xx
-++*/
-+static void ath10k_hw_qca99xx_set_coverage_class(struct ath10k *ar,
-+ s16 value)
-+{
-+ u32 timeout;
-+ int ret;
-+
-+ mutex_lock(&ar->conf_mutex);
-+
-+ /* Only execute if the core is started. */
-+ if ((ar->state != ATH10K_STATE_ON) &&
-+ (ar->state != ATH10K_STATE_RESTARTED)) {
-+ ath10k_warn(ar, "ath10k core not yet started");
-+ goto unlock;
-+ }
-+
-+ if (value < 0)
-+ value = ar->fw_coverage.coverage_class;
-+
-+ /* WIP: it appears that one wmi timeout unit accounts for 3 C.Class units
-+ * so we need an integer divide by three; feedback welcome for distances
-+ * 10-20 km; tested at 7 km */
-+ if (value > 0) {
-+ timeout = 0x40 + (value / 3) + 0x01;
-+
-+ /* Limit to 0xff as the destination register is u8 */
-+ if (timeout > 0xff)
-+ timeout = 0xff;
-+ }
-+ else
-+ timeout = 0x40;
-+
-+ /* set Coverage Class via wmi */
-+ ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->tx_ack_timeout,
-+ timeout);
-+ if (ret) {
-+ ath10k_warn(ar, "failed to set tx-acktimeout: %d, timeout: 0x%x\n"
-+ , ret, timeout);
-+ }
-+
-+unlock:
-+ spin_lock_bh(&ar->data_lock);
-+ ar->fw_coverage.coverage_class = value;
-+ spin_unlock_bh(&ar->data_lock);
-+
-+ mutex_unlock(&ar->conf_mutex);
-+}
-+
- /* The stock firmware does not support setting the coverage class. Instead this
- * function monitors and modifies the corresponding MAC registers.
- */
-@@ -1161,6 +1211,7 @@ const struct ath10k_hw_ops qca988x_ops =
- };
-
- const struct ath10k_hw_ops qca99x0_ops = {
-+ .set_coverage_class = ath10k_hw_qca99xx_set_coverage_class,
- .is_rssi_enable = ath10k_htt_tx_rssi_enable,
- };
-
---- a/ath10k-6.4/wmi.c
-+++ b/ath10k-6.4/wmi.c
-@@ -1164,6 +1164,7 @@ static struct wmi_pdev_param_map wmi_pde
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
-@@ -1260,6 +1261,7 @@ static struct wmi_pdev_param_map wmi_10x
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = {
-@@ -1357,6 +1359,7 @@ static struct wmi_pdev_param_map wmi_10_
- .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
- .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
-+ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
- };
-
- /* firmware 10.2 specific mappings */
-@@ -1617,6 +1620,7 @@ static struct wmi_pdev_param_map wmi_10_
- .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
- .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
- .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
-+ .tx_ack_timeout = WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT,
- };
-
- static const u8 wmi_key_cipher_suites[] = {
---- a/ath10k-6.4/wmi.h
-+++ b/ath10k-6.4/wmi.h
-@@ -3939,6 +3939,7 @@ struct wmi_pdev_param_map {
- u32 rfkill_config;
- u32 rfkill_enable;
- u32 peer_stats_info_enable;
-+ u32 tx_ack_timeout;
- };
-
- #define WMI_PDEV_PARAM_UNSUPPORTED 0
-@@ -4259,6 +4260,8 @@ enum wmi_10_4_pdev_param {
- WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
- WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
- WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
-+ /* TX acknowledge timeout. Advised range: 0x40 - 0xFF microsec. */
-+ WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT = 0x68,
- };
-
- struct wmi_pdev_set_param_cmd {
Signed-off-by: David Bauer <mail@david-bauer.net>
---
- ath10k-6.4/mac.c | 1 -
+ ath10k-6.7/mac.c | 1 -
1 file changed, 1 deletion(-)
---- a/ath10k-6.4/mac.c
-+++ b/ath10k-6.4/mac.c
-@@ -11305,7 +11305,6 @@ int ath10k_mac_register(struct ath10k *a
+--- a/ath10k-6.7/mac.c
++++ b/ath10k-6.7/mac.c
+@@ -11311,7 +11311,6 @@ int ath10k_mac_register(struct ath10k *a
ieee80211_hw_set(ar->hw, CHANCTX_STA_CSA);
ieee80211_hw_set(ar->hw, QUEUE_CONTROL);
ieee80211_hw_set(ar->hw, SUPPORTS_TX_FRAG);
--- /dev/null
+--- a/ath10k-5.15/core.c
++++ b/ath10k-5.15/core.c
+@@ -2970,7 +2970,7 @@ static void ath10k_core_set_coverage_cla
+ set_coverage_class_work);
+
+ if (ar->hw_params.hw_ops->set_coverage_class)
+- ar->hw_params.hw_ops->set_coverage_class(ar, -1);
++ ar->hw_params.hw_ops->set_coverage_class(ar, ar->fw_coverage.coverage_class);
+ }
+
+ static int ath10k_core_init_firmware_features(struct ath10k *ar)
+--- a/ath10k-5.15/hw.c
++++ b/ath10k-5.15/hw.c
+@@ -584,6 +584,56 @@ void ath10k_hw_fill_survey_time(struct a
+ survey->time_busy = CCNT_TO_MSEC(ar, rcc);
+ }
+
++/* Wireless firmware version 10.4 supports setting Coverage Class by
+++ * setting via wmi tx_ack_timeout; chipsets a.o. ipq40xx, qca99xx
+++*/
++static void ath10k_hw_qca99xx_set_coverage_class(struct ath10k *ar,
++ s16 value)
++{
++ u32 timeout;
++ int ret;
++
++ mutex_lock(&ar->conf_mutex);
++
++ /* Only execute if the core is started. */
++ if ((ar->state != ATH10K_STATE_ON) &&
++ (ar->state != ATH10K_STATE_RESTARTED)) {
++ ath10k_warn(ar, "ath10k core not yet started");
++ goto unlock;
++ }
++
++ if (value < 0)
++ value = ar->fw_coverage.coverage_class;
++
++ /* WIP: it appears that one wmi timeout unit accounts for 3 C.Class units
++ * so we need an integer divide by three; feedback welcome for distances
++ * 10-20 km; tested at 7 km */
++ if (value > 0) {
++ timeout = 0x40 + (value / 3) + 0x01;
++
++ /* Limit to 0xff as the destination register is u8 */
++ if (timeout > 0xff)
++ timeout = 0xff;
++ }
++ else
++ timeout = 0x40;
++
++ /* set Coverage Class via wmi */
++ ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->tx_ack_timeout,
++ timeout);
++ if (ret) {
++ ath10k_warn(ar, "failed to set tx-acktimeout: %d, timeout: 0x%x\n"
++ , ret, timeout);
++ }
++
++unlock:
++ spin_lock_bh(&ar->data_lock);
++ ar->fw_coverage.coverage_class = value;
++ spin_unlock_bh(&ar->data_lock);
++
++ mutex_unlock(&ar->conf_mutex);
++}
++
+ /* The stock firmware does not support setting the coverage class. Instead this
+ * function monitors and modifies the corresponding MAC registers.
+ */
+@@ -1172,6 +1222,7 @@ static bool ath10k_qca99x0_rx_desc_msdu_
+ }
+
+ const struct ath10k_hw_ops qca99x0_ops = {
++ .set_coverage_class = ath10k_hw_qca99xx_set_coverage_class,
+ .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
+ .rx_desc_get_msdu_limit_error = ath10k_qca99x0_rx_desc_msdu_limit_error,
+ .is_rssi_enable = ath10k_htt_tx_rssi_enable,
+--- a/ath10k-5.15/wmi.c
++++ b/ath10k-5.15/wmi.c
+@@ -1164,6 +1164,7 @@ static struct wmi_pdev_param_map wmi_pde
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
+@@ -1260,6 +1261,7 @@ static struct wmi_pdev_param_map wmi_10x
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = {
+@@ -1357,6 +1359,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ /* firmware 10.2 specific mappings */
+@@ -1617,6 +1620,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
+ .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
+ .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ .tx_ack_timeout = WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT,
+ };
+
+ static const u8 wmi_key_cipher_suites[] = {
+--- a/ath10k-5.15/wmi.h
++++ b/ath10k-5.15/wmi.h
+@@ -3937,6 +3937,7 @@ struct wmi_pdev_param_map {
+ u32 rfkill_config;
+ u32 rfkill_enable;
+ u32 peer_stats_info_enable;
++ u32 tx_ack_timeout;
+ };
+
+ #define WMI_PDEV_PARAM_UNSUPPORTED 0
+@@ -4257,6 +4258,8 @@ enum wmi_10_4_pdev_param {
+ WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
+ WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
+ WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ /* TX acknowledge timeout. Advised range: 0x40 - 0xFF microsec. */
++ WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT = 0x68,
+ };
+
+ struct wmi_pdev_set_param_cmd {
+--- a/ath10k-5.17/core.c
++++ b/ath10k-5.17/core.c
+@@ -3035,7 +3035,7 @@ static void ath10k_core_set_coverage_cla
+ set_coverage_class_work);
+
+ if (ar->hw_params.hw_ops->set_coverage_class)
+- ar->hw_params.hw_ops->set_coverage_class(ar, -1);
++ ar->hw_params.hw_ops->set_coverage_class(ar, ar->fw_coverage.coverage_class);
+ }
+
+ static int ath10k_core_init_firmware_features(struct ath10k *ar)
+--- a/ath10k-5.17/hw.c
++++ b/ath10k-5.17/hw.c
+@@ -584,6 +584,56 @@ void ath10k_hw_fill_survey_time(struct a
+ survey->time_busy = CCNT_TO_MSEC(ar, rcc);
+ }
+
++/* Wireless firmware version 10.4 supports setting Coverage Class by
+++ * setting via wmi tx_ack_timeout; chipsets a.o. ipq40xx, qca99xx
+++*/
++static void ath10k_hw_qca99xx_set_coverage_class(struct ath10k *ar,
++ s16 value)
++{
++ u32 timeout;
++ int ret;
++
++ mutex_lock(&ar->conf_mutex);
++
++ /* Only execute if the core is started. */
++ if ((ar->state != ATH10K_STATE_ON) &&
++ (ar->state != ATH10K_STATE_RESTARTED)) {
++ ath10k_warn(ar, "ath10k core not yet started");
++ goto unlock;
++ }
++
++ if (value < 0)
++ value = ar->fw_coverage.coverage_class;
++
++ /* WIP: it appears that one wmi timeout unit accounts for 3 C.Class units
++ * so we need an integer divide by three; feedback welcome for distances
++ * 10-20 km; tested at 7 km */
++ if (value > 0) {
++ timeout = 0x40 + (value / 3) + 0x01;
++
++ /* Limit to 0xff as the destination register is u8 */
++ if (timeout > 0xff)
++ timeout = 0xff;
++ }
++ else
++ timeout = 0x40;
++
++ /* set Coverage Class via wmi */
++ ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->tx_ack_timeout,
++ timeout);
++ if (ret) {
++ ath10k_warn(ar, "failed to set tx-acktimeout: %d, timeout: 0x%x\n"
++ , ret, timeout);
++ }
++
++unlock:
++ spin_lock_bh(&ar->data_lock);
++ ar->fw_coverage.coverage_class = value;
++ spin_unlock_bh(&ar->data_lock);
++
++ mutex_unlock(&ar->conf_mutex);
++}
++
+ /* The stock firmware does not support setting the coverage class. Instead this
+ * function monitors and modifies the corresponding MAC registers.
+ */
+@@ -1172,6 +1222,7 @@ static bool ath10k_qca99x0_rx_desc_msdu_
+ }
+
+ const struct ath10k_hw_ops qca99x0_ops = {
++ .set_coverage_class = ath10k_hw_qca99xx_set_coverage_class,
+ .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
+ .rx_desc_get_msdu_limit_error = ath10k_qca99x0_rx_desc_msdu_limit_error,
+ .is_rssi_enable = ath10k_htt_tx_rssi_enable,
+--- a/ath10k-5.17/wmi.c
++++ b/ath10k-5.17/wmi.c
+@@ -1164,6 +1164,7 @@ static struct wmi_pdev_param_map wmi_pde
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
+@@ -1260,6 +1261,7 @@ static struct wmi_pdev_param_map wmi_10x
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = {
+@@ -1357,6 +1359,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ /* firmware 10.2 specific mappings */
+@@ -1617,6 +1620,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
+ .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
+ .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ .tx_ack_timeout = WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT,
+ };
+
+ static const u8 wmi_key_cipher_suites[] = {
+--- a/ath10k-5.17/wmi.h
++++ b/ath10k-5.17/wmi.h
+@@ -3939,6 +3939,7 @@ struct wmi_pdev_param_map {
+ u32 rfkill_config;
+ u32 rfkill_enable;
+ u32 peer_stats_info_enable;
++ u32 tx_ack_timeout;
+ };
+
+ #define WMI_PDEV_PARAM_UNSUPPORTED 0
+@@ -4259,6 +4260,8 @@ enum wmi_10_4_pdev_param {
+ WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
+ WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
+ WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ /* TX acknowledge timeout. Advised range: 0x40 - 0xFF microsec. */
++ WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT = 0x68,
+ };
+
+ struct wmi_pdev_set_param_cmd {
+--- a/ath10k-5.19/core.c
++++ b/ath10k-5.19/core.c
+@@ -3091,7 +3091,7 @@ static void ath10k_core_set_coverage_cla
+ set_coverage_class_work);
+
+ if (ar->hw_params.hw_ops->set_coverage_class)
+- ar->hw_params.hw_ops->set_coverage_class(ar, -1);
++ ar->hw_params.hw_ops->set_coverage_class(ar, ar->fw_coverage.coverage_class);
+ }
+
+ static int ath10k_core_init_firmware_features(struct ath10k *ar)
+--- a/ath10k-5.19/hw.c
++++ b/ath10k-5.19/hw.c
+@@ -585,6 +585,56 @@ void ath10k_hw_fill_survey_time(struct a
+ survey->time_busy = CCNT_TO_MSEC(ar, rcc);
+ }
+
++/* Wireless firmware version 10.4 supports setting Coverage Class by
+++ * setting via wmi tx_ack_timeout; chipsets a.o. ipq40xx, qca99xx
+++*/
++static void ath10k_hw_qca99xx_set_coverage_class(struct ath10k *ar,
++ s16 value)
++{
++ u32 timeout;
++ int ret;
++
++ mutex_lock(&ar->conf_mutex);
++
++ /* Only execute if the core is started. */
++ if ((ar->state != ATH10K_STATE_ON) &&
++ (ar->state != ATH10K_STATE_RESTARTED)) {
++ ath10k_warn(ar, "ath10k core not yet started");
++ goto unlock;
++ }
++
++ if (value < 0)
++ value = ar->fw_coverage.coverage_class;
++
++ /* WIP: it appears that one wmi timeout unit accounts for 3 C.Class units
++ * so we need an integer divide by three; feedback welcome for distances
++ * 10-20 km; tested at 7 km */
++ if (value > 0) {
++ timeout = 0x40 + (value / 3) + 0x01;
++
++ /* Limit to 0xff as the destination register is u8 */
++ if (timeout > 0xff)
++ timeout = 0xff;
++ }
++ else
++ timeout = 0x40;
++
++ /* set Coverage Class via wmi */
++ ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->tx_ack_timeout,
++ timeout);
++ if (ret) {
++ ath10k_warn(ar, "failed to set tx-acktimeout: %d, timeout: 0x%x\n"
++ , ret, timeout);
++ }
++
++unlock:
++ spin_lock_bh(&ar->data_lock);
++ ar->fw_coverage.coverage_class = value;
++ spin_unlock_bh(&ar->data_lock);
++
++ mutex_unlock(&ar->conf_mutex);
++}
++
+ /* The stock firmware does not support setting the coverage class. Instead this
+ * function monitors and modifies the corresponding MAC registers.
+ */
+@@ -1161,6 +1211,7 @@ const struct ath10k_hw_ops qca988x_ops =
+ };
+
+ const struct ath10k_hw_ops qca99x0_ops = {
++ .set_coverage_class = ath10k_hw_qca99xx_set_coverage_class,
+ .is_rssi_enable = ath10k_htt_tx_rssi_enable,
+ };
+
+--- a/ath10k-5.19/wmi.c
++++ b/ath10k-5.19/wmi.c
+@@ -1164,6 +1164,7 @@ static struct wmi_pdev_param_map wmi_pde
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
+@@ -1260,6 +1261,7 @@ static struct wmi_pdev_param_map wmi_10x
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = {
+@@ -1357,6 +1359,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ /* firmware 10.2 specific mappings */
+@@ -1617,6 +1620,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
+ .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
+ .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ .tx_ack_timeout = WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT,
+ };
+
+ static const u8 wmi_key_cipher_suites[] = {
+--- a/ath10k-5.19/wmi.h
++++ b/ath10k-5.19/wmi.h
+@@ -3939,6 +3939,7 @@ struct wmi_pdev_param_map {
+ u32 rfkill_config;
+ u32 rfkill_enable;
+ u32 peer_stats_info_enable;
++ u32 tx_ack_timeout;
+ };
+
+ #define WMI_PDEV_PARAM_UNSUPPORTED 0
+@@ -4259,6 +4260,8 @@ enum wmi_10_4_pdev_param {
+ WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
+ WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
+ WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ /* TX acknowledge timeout. Advised range: 0x40 - 0xFF microsec. */
++ WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT = 0x68,
+ };
+
+ struct wmi_pdev_set_param_cmd {
+--- a/ath10k-6.2/core.c
++++ b/ath10k-6.2/core.c
+@@ -3110,7 +3110,7 @@ static void ath10k_core_set_coverage_cla
+ set_coverage_class_work);
+
+ if (ar->hw_params.hw_ops->set_coverage_class)
+- ar->hw_params.hw_ops->set_coverage_class(ar, -1);
++ ar->hw_params.hw_ops->set_coverage_class(ar, ar->fw_coverage.coverage_class);
+ }
+
+ static int ath10k_core_init_firmware_features(struct ath10k *ar)
+--- a/ath10k-6.2/hw.c
++++ b/ath10k-6.2/hw.c
+@@ -585,6 +585,56 @@ void ath10k_hw_fill_survey_time(struct a
+ survey->time_busy = CCNT_TO_MSEC(ar, rcc);
+ }
+
++/* Wireless firmware version 10.4 supports setting Coverage Class by
+++ * setting via wmi tx_ack_timeout; chipsets a.o. ipq40xx, qca99xx
+++*/
++static void ath10k_hw_qca99xx_set_coverage_class(struct ath10k *ar,
++ s16 value)
++{
++ u32 timeout;
++ int ret;
++
++ mutex_lock(&ar->conf_mutex);
++
++ /* Only execute if the core is started. */
++ if ((ar->state != ATH10K_STATE_ON) &&
++ (ar->state != ATH10K_STATE_RESTARTED)) {
++ ath10k_warn(ar, "ath10k core not yet started");
++ goto unlock;
++ }
++
++ if (value < 0)
++ value = ar->fw_coverage.coverage_class;
++
++ /* WIP: it appears that one wmi timeout unit accounts for 3 C.Class units
++ * so we need an integer divide by three; feedback welcome for distances
++ * 10-20 km; tested at 7 km */
++ if (value > 0) {
++ timeout = 0x40 + (value / 3) + 0x01;
++
++ /* Limit to 0xff as the destination register is u8 */
++ if (timeout > 0xff)
++ timeout = 0xff;
++ }
++ else
++ timeout = 0x40;
++
++ /* set Coverage Class via wmi */
++ ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->tx_ack_timeout,
++ timeout);
++ if (ret) {
++ ath10k_warn(ar, "failed to set tx-acktimeout: %d, timeout: 0x%x\n"
++ , ret, timeout);
++ }
++
++unlock:
++ spin_lock_bh(&ar->data_lock);
++ ar->fw_coverage.coverage_class = value;
++ spin_unlock_bh(&ar->data_lock);
++
++ mutex_unlock(&ar->conf_mutex);
++}
++
+ /* The stock firmware does not support setting the coverage class. Instead this
+ * function monitors and modifies the corresponding MAC registers.
+ */
+@@ -1161,6 +1211,7 @@ const struct ath10k_hw_ops qca988x_ops =
+ };
+
+ const struct ath10k_hw_ops qca99x0_ops = {
++ .set_coverage_class = ath10k_hw_qca99xx_set_coverage_class,
+ .is_rssi_enable = ath10k_htt_tx_rssi_enable,
+ };
+
+--- a/ath10k-6.2/wmi.c
++++ b/ath10k-6.2/wmi.c
+@@ -1164,6 +1164,7 @@ static struct wmi_pdev_param_map wmi_pde
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
+@@ -1260,6 +1261,7 @@ static struct wmi_pdev_param_map wmi_10x
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = {
+@@ -1357,6 +1359,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ /* firmware 10.2 specific mappings */
+@@ -1617,6 +1620,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
+ .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
+ .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ .tx_ack_timeout = WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT,
+ };
+
+ static const u8 wmi_key_cipher_suites[] = {
+--- a/ath10k-6.2/wmi.h
++++ b/ath10k-6.2/wmi.h
+@@ -3939,6 +3939,7 @@ struct wmi_pdev_param_map {
+ u32 rfkill_config;
+ u32 rfkill_enable;
+ u32 peer_stats_info_enable;
++ u32 tx_ack_timeout;
+ };
+
+ #define WMI_PDEV_PARAM_UNSUPPORTED 0
+@@ -4259,6 +4260,8 @@ enum wmi_10_4_pdev_param {
+ WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
+ WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
+ WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ /* TX acknowledge timeout. Advised range: 0x40 - 0xFF microsec. */
++ WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT = 0x68,
+ };
+
+ struct wmi_pdev_set_param_cmd {
+--- a/ath10k-6.4/core.c
++++ b/ath10k-6.4/core.c
+@@ -3110,7 +3110,7 @@ static void ath10k_core_set_coverage_cla
+ set_coverage_class_work);
+
+ if (ar->hw_params.hw_ops->set_coverage_class)
+- ar->hw_params.hw_ops->set_coverage_class(ar, -1);
++ ar->hw_params.hw_ops->set_coverage_class(ar, ar->fw_coverage.coverage_class);
+ }
+
+ static int ath10k_core_init_firmware_features(struct ath10k *ar)
+--- a/ath10k-6.4/hw.c
++++ b/ath10k-6.4/hw.c
+@@ -585,6 +585,56 @@ void ath10k_hw_fill_survey_time(struct a
+ survey->time_busy = CCNT_TO_MSEC(ar, rcc);
+ }
+
++/* Wireless firmware version 10.4 supports setting Coverage Class by
+++ * setting via wmi tx_ack_timeout; chipsets a.o. ipq40xx, qca99xx
+++*/
++static void ath10k_hw_qca99xx_set_coverage_class(struct ath10k *ar,
++ s16 value)
++{
++ u32 timeout;
++ int ret;
++
++ mutex_lock(&ar->conf_mutex);
++
++ /* Only execute if the core is started. */
++ if ((ar->state != ATH10K_STATE_ON) &&
++ (ar->state != ATH10K_STATE_RESTARTED)) {
++ ath10k_warn(ar, "ath10k core not yet started");
++ goto unlock;
++ }
++
++ if (value < 0)
++ value = ar->fw_coverage.coverage_class;
++
++ /* WIP: it appears that one wmi timeout unit accounts for 3 C.Class units
++ * so we need an integer divide by three; feedback welcome for distances
++ * 10-20 km; tested at 7 km */
++ if (value > 0) {
++ timeout = 0x40 + (value / 3) + 0x01;
++
++ /* Limit to 0xff as the destination register is u8 */
++ if (timeout > 0xff)
++ timeout = 0xff;
++ }
++ else
++ timeout = 0x40;
++
++ /* set Coverage Class via wmi */
++ ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->tx_ack_timeout,
++ timeout);
++ if (ret) {
++ ath10k_warn(ar, "failed to set tx-acktimeout: %d, timeout: 0x%x\n"
++ , ret, timeout);
++ }
++
++unlock:
++ spin_lock_bh(&ar->data_lock);
++ ar->fw_coverage.coverage_class = value;
++ spin_unlock_bh(&ar->data_lock);
++
++ mutex_unlock(&ar->conf_mutex);
++}
++
+ /* The stock firmware does not support setting the coverage class. Instead this
+ * function monitors and modifies the corresponding MAC registers.
+ */
+@@ -1161,6 +1211,7 @@ const struct ath10k_hw_ops qca988x_ops =
+ };
+
+ const struct ath10k_hw_ops qca99x0_ops = {
++ .set_coverage_class = ath10k_hw_qca99xx_set_coverage_class,
+ .is_rssi_enable = ath10k_htt_tx_rssi_enable,
+ };
+
+--- a/ath10k-6.4/wmi.c
++++ b/ath10k-6.4/wmi.c
+@@ -1164,6 +1164,7 @@ static struct wmi_pdev_param_map wmi_pde
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
+@@ -1260,6 +1261,7 @@ static struct wmi_pdev_param_map wmi_10x
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = {
+@@ -1357,6 +1359,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ /* firmware 10.2 specific mappings */
+@@ -1617,6 +1620,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
+ .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
+ .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ .tx_ack_timeout = WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT,
+ };
+
+ static const u8 wmi_key_cipher_suites[] = {
+--- a/ath10k-6.4/wmi.h
++++ b/ath10k-6.4/wmi.h
+@@ -3939,6 +3939,7 @@ struct wmi_pdev_param_map {
+ u32 rfkill_config;
+ u32 rfkill_enable;
+ u32 peer_stats_info_enable;
++ u32 tx_ack_timeout;
+ };
+
+ #define WMI_PDEV_PARAM_UNSUPPORTED 0
+@@ -4259,6 +4260,8 @@ enum wmi_10_4_pdev_param {
+ WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
+ WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
+ WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ /* TX acknowledge timeout. Advised range: 0x40 - 0xFF microsec. */
++ WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT = 0x68,
+ };
+
+ struct wmi_pdev_set_param_cmd {
+--- a/ath10k-6.7/core.c
++++ b/ath10k-6.7/core.c
+@@ -3107,7 +3107,7 @@ static void ath10k_core_set_coverage_cla
+ set_coverage_class_work);
+
+ if (ar->hw_params.hw_ops->set_coverage_class)
+- ar->hw_params.hw_ops->set_coverage_class(ar, -1);
++ ar->hw_params.hw_ops->set_coverage_class(ar, ar->fw_coverage.coverage_class);
+ }
+
+ static int ath10k_core_init_firmware_features(struct ath10k *ar)
+--- a/ath10k-6.7/hw.c
++++ b/ath10k-6.7/hw.c
+@@ -585,6 +585,56 @@ void ath10k_hw_fill_survey_time(struct a
+ survey->time_busy = CCNT_TO_MSEC(ar, rcc);
+ }
+
++/* Wireless firmware version 10.4 supports setting Coverage Class by
+++ * setting via wmi tx_ack_timeout; chipsets a.o. ipq40xx, qca99xx
+++*/
++static void ath10k_hw_qca99xx_set_coverage_class(struct ath10k *ar,
++ s16 value)
++{
++ u32 timeout;
++ int ret;
++
++ mutex_lock(&ar->conf_mutex);
++
++ /* Only execute if the core is started. */
++ if ((ar->state != ATH10K_STATE_ON) &&
++ (ar->state != ATH10K_STATE_RESTARTED)) {
++ ath10k_warn(ar, "ath10k core not yet started");
++ goto unlock;
++ }
++
++ if (value < 0)
++ value = ar->fw_coverage.coverage_class;
++
++ /* WIP: it appears that one wmi timeout unit accounts for 3 C.Class units
++ * so we need an integer divide by three; feedback welcome for distances
++ * 10-20 km; tested at 7 km */
++ if (value > 0) {
++ timeout = 0x40 + (value / 3) + 0x01;
++
++ /* Limit to 0xff as the destination register is u8 */
++ if (timeout > 0xff)
++ timeout = 0xff;
++ }
++ else
++ timeout = 0x40;
++
++ /* set Coverage Class via wmi */
++ ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->tx_ack_timeout,
++ timeout);
++ if (ret) {
++ ath10k_warn(ar, "failed to set tx-acktimeout: %d, timeout: 0x%x\n"
++ , ret, timeout);
++ }
++
++unlock:
++ spin_lock_bh(&ar->data_lock);
++ ar->fw_coverage.coverage_class = value;
++ spin_unlock_bh(&ar->data_lock);
++
++ mutex_unlock(&ar->conf_mutex);
++}
++
+ /* The stock firmware does not support setting the coverage class. Instead this
+ * function monitors and modifies the corresponding MAC registers.
+ */
+@@ -1161,6 +1211,7 @@ const struct ath10k_hw_ops qca988x_ops =
+ };
+
+ const struct ath10k_hw_ops qca99x0_ops = {
++ .set_coverage_class = ath10k_hw_qca99xx_set_coverage_class,
+ .is_rssi_enable = ath10k_htt_tx_rssi_enable,
+ };
+
+--- a/ath10k-6.7/wmi.c
++++ b/ath10k-6.7/wmi.c
+@@ -1164,6 +1164,7 @@ static struct wmi_pdev_param_map wmi_pde
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
+@@ -1260,6 +1261,7 @@ static struct wmi_pdev_param_map wmi_10x
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ static struct wmi_pdev_param_map wmi_10_2_4_pdev_param_map = {
+@@ -1357,6 +1359,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .arp_dstaddr = WMI_PDEV_PARAM_UNSUPPORTED,
+ .enable_btcoex = WMI_PDEV_PARAM_UNSUPPORTED,
++ .tx_ack_timeout = WMI_PDEV_PARAM_UNSUPPORTED,
+ };
+
+ /* firmware 10.2 specific mappings */
+@@ -1617,6 +1620,7 @@ static struct wmi_pdev_param_map wmi_10_
+ .arp_srcaddr = WMI_10_4_PDEV_PARAM_ARP_SRCADDR,
+ .arp_dstaddr = WMI_10_4_PDEV_PARAM_ARP_DSTADDR,
+ .enable_btcoex = WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ .tx_ack_timeout = WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT,
+ };
+
+ static const u8 wmi_key_cipher_suites[] = {
+--- a/ath10k-6.7/wmi.h
++++ b/ath10k-6.7/wmi.h
+@@ -3974,6 +3974,7 @@ struct wmi_pdev_param_map {
+ u32 rfkill_config;
+ u32 rfkill_enable;
+ u32 peer_stats_info_enable;
++ u32 tx_ack_timeout;
+ };
+
+ #define WMI_PDEV_PARAM_UNSUPPORTED 0
+@@ -4294,6 +4295,8 @@ enum wmi_10_4_pdev_param {
+ WMI_10_4_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
+ WMI_10_4_PDEV_PARAM_ATF_SSID_GROUP_POLICY,
+ WMI_10_4_PDEV_PARAM_ENABLE_BTCOEX,
++ /* TX acknowledge timeout. Advised range: 0x40 - 0xFF microsec. */
++ WMI_10_4_PDEV_PARAM_TX_ACK_TIMEOUT = 0x68,
+ };
+
+ struct wmi_pdev_set_param_cmd {
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=bcm27xx-gpu-fw
-PKG_VERSION:=2024-01-11
-PKG_RELEASE:=0968de28716a9b1f106b8492646d0ed0a2800152
+PKG_VERSION:=2024-04-24
+PKG_RELEASE:=969420b4121b522ab33c5001074cc4c2547dafaf
PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)/rpi-firmware-$(PKG_RELEASE)
FILE:=$(RPI_FIRMWARE_FILE)-fixup.dat
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=fixup.dat
- HASH:=c28ea955e672e374016dca61d63afa026490f0473a98115908586ab48e324aeb
+ HASH:=94ae3ff8363a6a2832f173241597b6500cf67044d34155a1251fe58671dd6ce7
endef
$(eval $(call Download,fixup_dat))
FILE:=$(RPI_FIRMWARE_FILE)-fixup_cd.dat
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=fixup_cd.dat
- HASH:=3cf1aef5f596ca106203ed5dac9ad45e85929ec55ce44c813588645e174442ec
+ HASH:=2d7c19e46780ef29867f8ed200a94bb77a7982f5bc41219afe864d2303ba3084
endef
$(eval $(call Download,fixup_cd_dat))
FILE:=$(RPI_FIRMWARE_FILE)-fixup_x.dat
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=fixup_x.dat
- HASH:=56525c8feabde1ab86f36bb09bc55171659b2993f94132cf81ffc4293d62269d
+ HASH:=692393562d0650f7d1891ba0143ad0500ccf07129947d386d56350e7ca204d16
endef
$(eval $(call Download,fixup_x_dat))
FILE:=$(RPI_FIRMWARE_FILE)-fixup4.dat
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=fixup4.dat
- HASH:=615f8595801bf52373039f73ad5ad9513f83400d355eb1b2c075c7ae907e927c
+ HASH:=63a4a8f356e2b8ed2850d68b9adf21008ef1dfa7743b22ddc26987e4d3171302
endef
$(eval $(call Download,fixup4_dat))
FILE:=$(RPI_FIRMWARE_FILE)-fixup4cd.dat
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=fixup4cd.dat
- HASH:=3cf1aef5f596ca106203ed5dac9ad45e85929ec55ce44c813588645e174442ec
+ HASH:=2d7c19e46780ef29867f8ed200a94bb77a7982f5bc41219afe864d2303ba3084
endef
$(eval $(call Download,fixup4cd_dat))
FILE:=$(RPI_FIRMWARE_FILE)-fixup4x.dat
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=fixup4x.dat
- HASH:=6d27a4b8ecb78cef9e1f03751b4aaec5ce8749d36988f381145a8a41dbf164ae
+ HASH:=41328f6587c0cd47ae7fa7edab4bf62730dda54caf52ffaa3bfb24ff93b8348b
endef
$(eval $(call Download,fixup4x_dat))
FILE:=$(RPI_FIRMWARE_FILE)-start.elf
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=start.elf
- HASH:=e8348e88522e7a1d0e2b0944ab66d7d8f4f30da98f326e2b3c123522e45f71b2
+ HASH:=8637fb847ff62f69fbb8b98b1beff685b47cf4095580e830724f6a27fb20fee0
endef
$(eval $(call Download,start_elf))
FILE:=$(RPI_FIRMWARE_FILE)-start_cd.elf
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=start_cd.elf
- HASH:=c9b4de3f12bec7808868b898c49f656b5378ddc315f12ccab83d6519bad51680
+ HASH:=6832f57236f6c453cd72eac1f0ab53e265037fb75fc41301448fedb8d505f2b3
endef
$(eval $(call Download,start_cd_elf))
FILE:=$(RPI_FIRMWARE_FILE)-start_x.elf
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=start_x.elf
- HASH:=0b5c06c109984361eeed0ab14d146f686d8aa8da2025689b887e9cb098636db9
+ HASH:=6f72a3fda8cbdacb340676e18a8468b9edd89458173b5ecf3c12b00c147dce40
endef
$(eval $(call Download,start_x_elf))
FILE:=$(RPI_FIRMWARE_FILE)-start4.elf
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=start4.elf
- HASH:=fedc4ecd72c9d21018e210240dcd2e41a8bb5f936fb5674c3351f2a447a22203
+ HASH:=badf4cd8822d1b85ad56ddb9e32e9b4220c88099c8cc0c3e70ae77190571c8ef
endef
$(eval $(call Download,start4_elf))
FILE:=$(RPI_FIRMWARE_FILE)-start4cd.elf
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=start4cd.elf
- HASH:=ea22282a77666801378137a651e7e0b17cc186f63cdbdc8b9bb98749cd12b256
+ HASH:=7d3f13c8412c6b0efdbd3b53439776f3552621cc28ee887caaac539fb063ad8a
endef
$(eval $(call Download,start4cd_elf))
FILE:=$(RPI_FIRMWARE_FILE)-start4x.elf
URL:=$(RPI_FIRMWARE_URL)
URL_FILE:=start4x.elf
- HASH:=c509e73a9cba7af3223dea885f58294bd04845e822aa3d6278500fa4dcdb112f
+ HASH:=c30fbdfedad7180245ff567ccdea953fc1816d0da3ff4701b15071c6f8b47a89
endef
$(eval $(call Download,start4x_elf))
--- /dev/null
+From 7ed95633bff19950069c348b94c9c13164a57a2a Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 18 Jan 2023 20:20:39 +0100
+Subject: [PATCH] linux/netlink: drop NL_SET_ERR_MSG for kernel modules
+
+We don't need NL_SET_ERR_MSG_MOD for bpf modules and we can drop it to
+solve missing KBUILD_MODNAME define.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ include/linux/netlink.h | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/include/linux/netlink.h b/include/linux/netlink.h
+index 61b1c7f..93561fb 100644
+--- a/include/linux/netlink.h
++++ b/include/linux/netlink.h
+@@ -98,9 +98,6 @@ struct netlink_ext_ack {
+ __extack->_msg = __msg; \
+ } while (0)
+
+-#define NL_SET_ERR_MSG_MOD(extack, msg) \
+- NL_SET_ERR_MSG((extack), KBUILD_MODNAME ": " msg)
+-
+ #define NL_SET_BAD_ATTR_POLICY(extack, attr, pol) do { \
+ if ((extack)) { \
+ (extack)->bad_attr = (attr); \
+--
+2.38.1
+
--- /dev/null
+From 6e7cd9c0abffea55e39a4160949bc6fba972d161 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 19 Jan 2023 13:37:46 +0100
+Subject: [PATCH] net/flow_offload: use NL_SET_ERR_MSG instead of
+ NL_SET_ERR_MSG_MOD
+
+Use NL_SET_ERR_MSG instead of NL_SET_ERR_MSG_MOD for bpf modules as
+kernel modules are not supported.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ include/net/flow_offload.h | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
+index 7a2b022..f17c485 100644
+--- a/include/net/flow_offload.h
++++ b/include/net/flow_offload.h
+@@ -321,7 +321,7 @@ flow_action_mixed_hw_stats_check(const struct flow_action *action,
+
+ flow_action_for_each(i, action_entry, action) {
+ if (i && action_entry->hw_stats != last_hw_stats) {
+- NL_SET_ERR_MSG_MOD(extack, "Mixing HW stats types for actions is not supported");
++ NL_SET_ERR_MSG(extack, "Mixing HW stats types for actions is not supported");
+ return false;
+ }
+ last_hw_stats = action_entry->hw_stats;
+@@ -356,11 +356,11 @@ __flow_action_hw_stats_check(const struct flow_action *action,
+
+ if (!check_allow_bit &&
+ ~action_entry->hw_stats & FLOW_ACTION_HW_STATS_ANY) {
+- NL_SET_ERR_MSG_MOD(extack, "Driver supports only default HW stats type \"any\"");
++ NL_SET_ERR_MSG(extack, "Driver supports only default HW stats type \"any\"");
+ return false;
+ } else if (check_allow_bit &&
+ !(action_entry->hw_stats & BIT(allow_bit))) {
+- NL_SET_ERR_MSG_MOD(extack, "Driver does not support selected HW stats type");
++ NL_SET_ERR_MSG(extack, "Driver does not support selected HW stats type");
+ return false;
+ }
+ return true;
+--
+2.38.1
+
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
-#include <linux/gpio.h>
+#include <linux/gpio/driver.h>
#include <linux/version.h>
#include <linux/dmi.h>
#include <linux/string.h>
#define IFXMIPS_FUSE_BASE_ADDR IFX_FUSE_BASE_ADDR
#define IFXMIPS_ICU_IM0_IER IFX_ICU_IM0_IER
#define IFXMIPS_ICU_IM2_IER IFX_ICU_IM2_IER
-#define LTQ_MEI_INT IFX_MEI_INT
-#define LTQ_MEI_DYING_GASP_INT IFX_MEI_DYING_GASP_INT
#define LTQ_MEI_BASE_ADDR IFX_MEI_SPACE_ACCESS
#define IFXMIPS_PMU_PWDCR IFX_PMU_PWDCR
#define IFXMIPS_MPS_CHIPID IFX_MPS_CHIPID
#define LTQ_PMU_BASE_ADDR 0x1F102000
-#ifdef CONFIG_DANUBE
-# define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
-# define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
-# define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
-#endif
-
-#ifdef CONFIG_AMAZON_SE
-# define LTQ_MEI_INT (INT_NUM_IM2_IRL0 + 9)
-# define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM2_IRL0 + 11)
-# define LTQ_USB_OC_INT (INT_NUM_IM2_IRL0 + 20)
-#endif
-
-#ifdef CONFIG_AR9
-# define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
-# define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
-# define LTQ_USB_OC_INT (INT_NUM_IM1_IRL0 + 28)
-#endif
-
-#ifndef LTQ_MEI_INT
-#error "Unknown Lantiq ARCH!"
-#endif
-
#define LTQ_RCU_RST_REQ_DFE (1 << 7)
#define LTQ_RCU_RST_REQ_AFE (1 << 11)
im2_register = (*LTQ_ICU_IM2_IER) & (1 << 20);
/* Turn off irq */
- disable_irq (LTQ_USB_OC_INT);
+ disable_irq (pDev->nIrq[IFX_USB_OC]);
disable_irq (pDev->nIrq[IFX_DYING_GASP]);
IFX_MEI_RunArc (pDev);
MEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready, 1000);
- MEI_MASK_AND_ACK_IRQ (LTQ_USB_OC_INT);
+ MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_USB_OC]);
MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]);
/* Re-enable irq */
sizeof (smmu_mem_info_t) * MAX_BAR_REGISTERS);
if (num == 0) {
- pDev->nIrq[IFX_DFEIR] = LTQ_MEI_INT;
- pDev->nIrq[IFX_DYING_GASP] = LTQ_MEI_DYING_GASP_INT;
pDev->base_address = KSEG1 + LTQ_MEI_BASE_ADDR;
/* Power up MEI */
{
int i = 0;
static struct class *dsl_class;
+ DSL_DEV_Device_t *pDev;
pr_info("IFX MEI Version %ld.%02ld.%02ld\n", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);
for (i = 0; i < BSP_MAX_DEVICES; i++) {
+ pDev = &dsl_devices[i];
+
+ pDev->nIrq[IFX_DFEIR] = platform_get_irq(pdev, 0);
+ if (pDev->nIrq[IFX_DFEIR] < 0) {
+ IFX_MEI_EMSG("Failed to get DFEIR irq!\n");
+ return pDev->nIrq[IFX_DFEIR];
+ }
+
+ pDev->nIrq[IFX_DYING_GASP] = platform_get_irq(pdev, 1);
+ if (pDev->nIrq[IFX_DYING_GASP] < 0) {
+ IFX_MEI_EMSG("Failed to get DYING_GASP irq!\n");
+ return pDev->nIrq[IFX_DYING_GASP];
+ }
+
+ pDev->nIrq[IFX_USB_OC] = platform_get_irq(pdev, 2);
+ if (pDev->nIrq[IFX_USB_OC] < 0) {
+ IFX_MEI_EMSG("Failed to get USB_OC irq!\n");
+ return pDev->nIrq[IFX_USB_OC];
+ }
+
if (IFX_MEI_InitDevice (i) != 0) {
IFX_MEI_EMSG("Init device fail!\n");
return -EIO;
DSL_int_t nInUse; /* modem state, update by bsp driver, */
DSL_void_t *pPriv;
DSL_uint32_t base_address; /* mei base address */
- DSL_int_t nIrq[2]; /* irq number */
+ DSL_int_t nIrq[3]; /* irq number */
#define IFX_DFEIR 0
#define IFX_DYING_GASP 1
+#define IFX_USB_OC 2
DSL_DEV_MeiDebug_t lop_debugwr; /* dying gasp */
struct module *owner;
} DSL_DEV_Device_t; /* ifx_adsl_device_t */
nErrCode = DSL_DRV_PM_HistoryDelete(pContext, EpData.pHistShowtime );
--- a/src/device/drv_dsl_cpe_device_danube.c
+++ b/src/device/drv_dsl_cpe_device_danube.c
-@@ -3193,7 +3193,7 @@ DSL_Error_t DSL_DRV_DEV_AutobootHandleTraining(
+@@ -3193,7 +3193,7 @@ DSL_Error_t DSL_DRV_DEV_AutobootHandleTr
DSL_DEV_NUM(pContext)));
}
#endif /* INCLUDE_DSL_DELT*/
--- a/src/g997/drv_dsl_cpe_api_g997_danube.c
+++ b/src/g997/drv_dsl_cpe_api_g997_danube.c
-@@ -1984,41 +1984,53 @@ DSL_Error_t DSL_DRV_DEV_G997_DeltHlogGet(
+@@ -1984,41 +1984,53 @@ DSL_Error_t DSL_DRV_DEV_G997_DeltHlogGet
{
if (nDirection == DSL_DOWNSTREAM)
{
--- a/src/g997/drv_dsl_cpe_api_g997_danube.c
+++ b/src/g997/drv_dsl_cpe_api_g997_danube.c
-@@ -2512,6 +2524,7 @@ DSL_Error_t DSL_DRV_DEV_G997_PowerManagementStateForcedTrigger(
+@@ -2524,6 +2524,7 @@ DSL_Error_t DSL_DRV_DEV_G997_PowerManage
else
{
/* read L3 request failure reason */
nErrCode = DSL_DRV_DANUBE_CmvRead(pContext, DSL_CMV_GROUP_STAT,
DSL_CMV_ADDRESS_STAT_L3_FAILURE_REASON, 0, 1, &nVal);
DSL_DEBUG(DSL_DBG_MSG,
-@@ -2525,11 +2538,13 @@ DSL_Error_t DSL_DRV_DEV_G997_PowerManagementStateForcedTrigger(
+@@ -2537,11 +2538,13 @@ DSL_Error_t DSL_DRV_DEV_G997_PowerManage
nErrCode = DSL_ERR_MSG_EXCHANGE;
break;
}
--- /dev/null
+--- a/src/common/drv_dsl_cpe_os_linux.c
++++ b/src/common/drv_dsl_cpe_os_linux.c
+@@ -556,7 +556,11 @@ static int DSL_DRV_KernelThreadStartup(v
+ retVal = pThrCntrl->pThrFct(&pThrCntrl->thrParams);
+ pThrCntrl->thrParams.bRunning = 0;
+
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,17,0))
+ complete_and_exit(&pThrCntrl->thrCompletion, (long)retVal);
++#else
++ kthread_complete_and_exit(&pThrCntrl->thrCompletion, (long)retVal);
++#endif
+
+ DSL_DEBUG( DSL_DBG_MSG,
+ (DSL_NULL, "EXIT - Kernel Thread Startup <%s>" DSL_DRV_CRLF,
#define IFXMIPS_ATM_CORE_H
-#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24)
-#define INT_NUM_IM2_IRL13 (INT_NUM_IM2_IRL0 + 13)
#define CONFIG_IFXMIPS_DSL_CPE_MEI
#define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r))
#define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r))
void *oam_buf_base;
void *tx_desc_base;
void *tx_skb_base;
+
+ int irq;
};
#include "ifxmips_atm_ppe_common.h"
#define EMA_ALIGNMENT 4
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL13
-
#endif // IFXMIPS_ATM_PPE_AMAZON_SE_H
#define EMA_ALIGNMENT 4
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
-
#endif // IFXMIPS_ATM_PPE_AR9_H
#define EMA_ALIGNMENT 4
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
-
#endif // IFXMIPS_ATM_PPE_DANUBE_H
#define PDMA_ALIGNMENT 4
#define EMA_ALIGNMENT PDMA_ALIGNMENT
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
-
#endif // IFXMIPS_ATM_PPE_VR9_H
*MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
*MBOX_IGU1_IER = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
- enable_irq(PPE_MAILBOX_IGU1_INT);
+ enable_irq(g_atm_priv_data.irq);
}
/* set port */
/* disable irq */
if ( g_atm_priv_data.conn_table == 0 )
- disable_irq(PPE_MAILBOX_IGU1_INT);
+ disable_irq(g_atm_priv_data.irq);
/* release bandwidth */
switch ( vcc->qos.txtp.traffic_class )
else if (*MBOX_IGU1_ISR >> (FIRST_QSB_QID + 16)) /* TX queue */
tasklet_schedule(&g_dma_tasklet);
else
- enable_irq(PPE_MAILBOX_IGU1_INT);
+ enable_irq(g_atm_priv_data.irq);
}
static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
if ( !*MBOX_IGU1_ISR )
return IRQ_HANDLED;
- disable_irq_nosync(PPE_MAILBOX_IGU1_INT);
+ disable_irq_nosync(g_atm_priv_data.irq);
tasklet_schedule(&g_dma_tasklet);
return IRQ_HANDLED;
}
}
+ g_atm_priv_data.irq = platform_get_irq(pdev, 0);
+ if (g_atm_priv_data.irq < 0) {
+ pr_err("platform_get_irq fail");
+ goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
+ }
+
/* register interrupt handler */
- ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data);
+ ret = request_irq(g_atm_priv_data.irq, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data);
if ( ret ) {
if ( ret == -EBUSY ) {
pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
} else {
- pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT);
+ pr_err("request_irq fail irq:%d\n", g_atm_priv_data.irq);
}
goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
}
- disable_irq(PPE_MAILBOX_IGU1_INT);
+ disable_irq(g_atm_priv_data.irq);
ret = ops->start(0);
return 0;
PP32_START_FAIL:
- free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
+ free_irq(g_atm_priv_data.irq, &g_atm_priv_data);
REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
ATM_DEV_REGISTER_FAIL:
while ( port_num-- > 0 )
ops->stop(0);
- free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
+ free_irq(g_atm_priv_data.irq, &g_atm_priv_data);
for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
--- a/ifxmips_ptm_adsl.c
+++ b/ifxmips_ptm_adsl.c
-@@ -180,7 +180,7 @@ static int proc_read_version(char *, char **, off_t, int, int *, void *);
+@@ -180,7 +180,7 @@ static int proc_read_version(char *, cha
static int proc_read_wanmib(char *, char **, off_t, int, int *, void *);
static int proc_write_wanmib(struct file *, const char *, unsigned long, void *);
#endif
static int proc_read_genconf(char *, char **, off_t, int, int *, void *);
#endif
#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
-@@ -191,8 +191,8 @@ static int proc_write_wanmib(struct file *, const char *, unsigned long, void *)
+@@ -191,8 +191,8 @@ static int proc_write_wanmib(struct file
/*
* Proc Help Functions
*/
static INLINE int strincmp(const char *, const char *, int);
#endif
static INLINE int ifx_ptm_version(char *);
-@@ -1159,8 +1159,6 @@ static int proc_write_dbg(struct file *file, const char *buf, unsigned long coun
+@@ -1159,8 +1159,6 @@ static int proc_write_dbg(struct file *f
return count;
}
static INLINE int stricmp(const char *p1, const char *p2)
{
int c1, c2;
-@@ -1178,7 +1176,6 @@ static INLINE int stricmp(const char *p1, const char *p2)
+@@ -1178,7 +1176,6 @@ static INLINE int stricmp(const char *p1
return *p1 - *p2;
}
static void ptm_setup(struct net_device *dev, int ndev)
{
+ u8 addr[ETH_ALEN];
+
#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
netif_carrier_off(dev);
#endif
dev->netdev_ops = &g_ptm_netdev_ops;
/* Allow up to 1508 bytes, for RFC4638 */
dev->max_mtu = ETH_DATA_LEN + 8;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,19,0))
netif_napi_add(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 25);
+#else
+ netif_napi_add_weight(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 25);
+#endif
dev->watchdog_timeo = ETH_WATCHDOG_TIMEOUT;
- dev->dev_addr[0] = 0x00;
- dev->dev_addr[1] = 0x20;
- dev->dev_addr[2] = 0xda;
- dev->dev_addr[3] = 0x86;
- dev->dev_addr[4] = 0x23;
- dev->dev_addr[5] = 0x75 + ndev;
+ addr[0] = 0x00;
+ addr[1] = 0x20;
+ addr[2] = 0xda;
+ addr[3] = 0x86;
+ addr[4] = 0x23;
+ addr[5] = 0x75 + ndev;
+ eth_hw_addr_set(dev, addr);
}
static struct net_device_stats *ptm_get_stats(struct net_device *dev)
goto REGISTER_NETDEV_FAIL;
}
+ g_ptm_priv_data.irq = platform_get_irq(pdev, 0);
+ if (g_ptm_priv_data.irq < 0) {
+ err("platform_get_irq fail");
+ goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
+ }
+
/* register interrupt handler */
- ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
+ ret = request_irq(g_ptm_priv_data.irq, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
if ( ret ) {
if ( ret == -EBUSY ) {
err("IRQ may be occupied by other driver, please reconfig to disable it.");
}
goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
}
- disable_irq(PPE_MAILBOX_IGU1_INT);
+ disable_irq(g_ptm_priv_data.irq);
ret = ifx_pp32_start(0);
if ( ret ) {
IFX_REG_W32(0, MBOX_IGU1_IER);
IFX_REG_W32(~0, MBOX_IGU1_ISRC);
- enable_irq(PPE_MAILBOX_IGU1_INT);
+ enable_irq(g_ptm_priv_data.irq);
proc_file_create();
return 0;
PP32_START_FAIL:
- free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
+ free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
i = ARRAY_SIZE(g_net_dev);
REGISTER_NETDEV_FAIL:
ifx_pp32_stop(0);
- free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
+ free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
unregister_netdev(g_net_dev[i]);
#include "ifxmips_ptm_fw_regs_adsl.h"
#define CONFIG_IFXMIPS_DSL_CPE_MEI
-#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24)
#define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r))
#define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r))
struct ptm_priv_data {
struct ptm_itf itf[MAX_ITF_NUMBER];
+ int irq;
void *rx_desc_base;
void *tx_desc_base;
#define EMA_ALIGNMENT 4
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL13
-
#endif // IFXMIPS_PTM_PPE_AMAZON_SE_H
#define SW_P2_CTL SW_REG(0x00C)
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
-
-
#endif // IFXMIPS_PTM_PPE_AR9_H
#define EMA_ALIGNMENT 4
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
-
#endif // IFXMIPS_PTM_PPE_DANUBE_H
#define PDMA_ALIGNMENT 32 // same as Central DMA because of descriptor swap
#define EMA_ALIGNMENT PDMA_ALIGNMENT
-/*
- * Mailbox IGU1 Interrupt
- */
-#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
-
#endif // IFXMIPS_PTM_PPE_VR9_H
dev->netdev_ops = &g_ptm_netdev_ops;
/* Allow up to 1508 bytes, for RFC4638 */
dev->max_mtu = ETH_DATA_LEN + 8;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,19,0))
netif_napi_add(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 16);
+#else
+ netif_napi_add_weight(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 16);
+#endif
dev->watchdog_timeo = ETH_WATCHDOG_TIMEOUT;
addr[0] = 0x00;
goto REGISTER_NETDEV_FAIL;
}
+ g_ptm_priv_data.irq = platform_get_irq(pdev, 0);
+ if (g_ptm_priv_data.irq < 0) {
+ err("platform_get_irq fail");
+ goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
+ }
+
/* register interrupt handler */
- ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
+ ret = request_irq(g_ptm_priv_data.irq, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
if ( ret ) {
if ( ret == -EBUSY ) {
err("IRQ may be occupied by other driver, please reconfig to disable it.");
}
goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
}
- disable_irq(PPE_MAILBOX_IGU1_INT);
+ disable_irq(g_ptm_priv_data.irq);
ret = ifx_pp32_start(0);
if ( ret ) {
IFX_REG_W32(1 << 16, MBOX_IGU1_IER); // enable SWAP interrupt
IFX_REG_W32(~0, MBOX_IGU1_ISRC);
- enable_irq(PPE_MAILBOX_IGU1_INT);
+ enable_irq(g_ptm_priv_data.irq);
ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
if ( g_showtime ) {
return 0;
PP32_START_FAIL:
- free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
+ free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
i = ARRAY_SIZE(g_net_dev);
REGISTER_NETDEV_FAIL:
ifx_pp32_stop(0);
- free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
+ free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
unregister_netdev(g_net_dev[i]);
#include "ifxmips_ptm_ppe_common.h"
#include "ifxmips_ptm_fw_regs_vdsl.h"
-#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24)
-
#define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r))
#define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r))
#define IFX_REG_W32_MASK(_clr, _set, _r) IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r))
struct ptm_priv_data {
struct ptm_itf itf[MAX_ITF_NUMBER];
+ int irq;
};
#endif
/* add MEI CPE debug/printout part */
-@@ -1718,8 +1718,8 @@ static void MEI_MeminfoProcPerDevGet(struct seq_file *s)
+@@ -1718,8 +1718,8 @@ static void MEI_MeminfoProcPerDevGet(str
", CRC = 0x%08X"
#endif
MEI_DRV_CRLF,
#if (MEI_SUPPORT_OPTIMIZED_FW_DL == 1)
--- a/src/drv_mei_cpe_download_vrx.c
+++ b/src/drv_mei_cpe_download_vrx.c
-@@ -3139,9 +3139,9 @@ IFX_int32_t MEI_DEV_IoctlFirmwareDownload(
+@@ -3139,9 +3139,9 @@ IFX_int32_t MEI_DEV_IoctlFirmwareDownloa
{
IFX_int32_t ret = 0;
MEI_DEV_T *pMeiDev = pMeiDynCntrl->pMeiDev;
--- /dev/null
+--- a/src/drv_mei_cpe_linux.c
++++ b/src/drv_mei_cpe_linux.c
+@@ -1873,7 +1873,11 @@ static int mei_seq_single_show(struct se
+
+ static int mei_proc_single_open(struct inode *inode, struct file *file)
+ {
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,17,0))
+ return single_open(file, mei_seq_single_show, PDE_DATA(inode));
++#else
++ return single_open(file, mei_seq_single_show, pde_data(inode));
++#endif
+ }
+
+ static void mei_proc_entry_create(struct proc_dir_entry *parent_node,
+--- a/src/drv_mei_cpe_linux_proc_config.c
++++ b/src/drv_mei_cpe_linux_proc_config.c
+@@ -1036,7 +1036,11 @@ static int mei_seq_single_show(struct se
+
+ static int mei_proc_single_open(struct inode *inode, struct file *file)
+ {
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,17,0))
+ return single_open(file, mei_seq_single_show, PDE_DATA(inode));
++#else
++ return single_open(file, mei_seq_single_show, pde_data(inode));
++#endif
+ }
+
+ #if (LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0))
--- /dev/null
+--- a/src/drv_mei_cpe_msg_process.c
++++ b/src/drv_mei_cpe_msg_process.c
+@@ -3524,7 +3524,12 @@ IFX_int32_t MEI_IoctlCmdMsgWrite(
+ {
+ if (bInternCall)
+ {
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,19,0))
+ memcpy(pDestPtr, pUserMsg->pPayload, pUserMsg->paylSize_byte);
++#else
++ unsafe_memcpy(pDestPtr, pUserMsg->pPayload, pUserMsg->paylSize_byte,
++ /* field-spanning writing is used here intentionally */);
++#endif
+ }
+ else
+ {
--- /dev/null
+--- a/src/drv_vmmc_api.h
++++ b/src/drv_vmmc_api.h
+@@ -149,17 +149,6 @@ DECLARE_TRACE_GROUP(VMMC);
+ return code; \
+ }while(0)
+
+-/*******************************************************************************
+-Description:
+- always returns the absolute value of argument given
+-Arguments:
+- x - argument
+-Return:
+- absolute value of x
+-*******************************************************************************/
+-/* define ABS */
+-#define ABS(x) (((x) < 0) ? -(x) : (x))
+-
+ /* regular format macros */
+ /*******************************************************************************
+ Description:
--- /dev/null
+--- a/src/drv_vmmc_init.c
++++ b/src/drv_vmmc_init.c
+@@ -202,11 +202,20 @@ IFX_int32_t VMMC_GetDevice (IFX_uint16_t
+ /**
+ Wrapper for the voice buffer get function that sets the FW as owner.
+ */
+-static IFX_void_t* vmmc_WrapperVoiceBufferGet (IFX_void_t)
++static IFX_void_t* vmmc_WrapperVoiceBufferGet (IFX_size_t size,
++ IFX_int32_t priority)
+ {
+ return IFX_TAPI_VoiceBufferGetWithOwnerId (IFX_TAPI_BUFFER_OWNER_FW);
+ }
+
++/**
++ Wrapper for the voice buffer get function that sets the FW as owner.
++*/
++static IFX_void_t vmmc_WrapperVoiceBufferPut (const IFX_void_t *ptr)
++{
++ IFX_TAPI_VoiceBufferPut ((IFX_void_t *)ptr);
++}
++
+
+ /**
+ Wrapper for the voice buffer free all function freeing all buffers that
+@@ -263,10 +272,8 @@ IFX_int32_t VMMC_ChipAccessInit(VMMC_DEV
+
+ /* Register the buffer handler. */
+ #ifdef USE_BUFFERPOOL
+- ifx_mps_bufman_register((IFX_void_t* (*)(IFX_size_t, IFX_int32_t))
+- vmmc_WrapperVoiceBufferGet,
+- (IFX_void_t (*)(const IFX_void_t*))
+- IFX_TAPI_VoiceBufferPut,
++ ifx_mps_bufman_register(vmmc_WrapperVoiceBufferGet,
++ vmmc_WrapperVoiceBufferPut,
+ sizeof(PACKET), POBX_BUFFER_THRESHOLD);
+ ifx_mps_register_bufman_freeall_callback (vmmc_WrapperVoiceBufferFreeAll);
+ #else
--- /dev/null
+--- a/src/drv_vmmc_fw_commands.h
++++ b/src/drv_vmmc_fw_commands.h
+@@ -4628,26 +4628,28 @@ struct RES_DTMFATG_COEF
+ struct CDM_RES_DTMFATG_DATA
+ {
+ CMD_HEAD_BE;
+- /** Frequency 1 1st Tone or Dual Tone Control Word 1 */
+- IFX_uint16_t FREQ11_DTC1;
+- /** Frequency 2 1st Tone or Dual Tone Control Word 2 */
+- IFX_uint16_t FREQ21_DTC2;
+- /** Frequency 1 2nd Tone */
+- IFX_uint16_t FREQ12_DTC3;
+- /** Frequency 2 2nd Tone */
+- IFX_uint16_t FREQ22_DTC4;
+- /** Frequency 1 3rd Tone */
+- IFX_uint16_t FREQ13_DTC5;
+- /** Frequency 2 3nd Tone */
+- IFX_uint16_t FREQ23_DTC6;
+- /** Frequency 1 4th Tone */
+- IFX_uint16_t FREQ14_DTC7;
+- /** Frequency 2 4th Tone */
+- IFX_uint16_t FREQ24_DTC8;
+- /** Frequency 1 5th Tone */
+- IFX_uint16_t FREQ15_DTC9;
+- /** Frequency 2 5th Tone */
+- IFX_uint16_t FREQ25_DTC10;
++ struct_group(FREQS,
++ /** Frequency 1 1st Tone or Dual Tone Control Word 1 */
++ IFX_uint16_t FREQ11_DTC1;
++ /** Frequency 2 1st Tone or Dual Tone Control Word 2 */
++ IFX_uint16_t FREQ21_DTC2;
++ /** Frequency 1 2nd Tone */
++ IFX_uint16_t FREQ12_DTC3;
++ /** Frequency 2 2nd Tone */
++ IFX_uint16_t FREQ22_DTC4;
++ /** Frequency 1 3rd Tone */
++ IFX_uint16_t FREQ13_DTC5;
++ /** Frequency 2 3nd Tone */
++ IFX_uint16_t FREQ23_DTC6;
++ /** Frequency 1 4th Tone */
++ IFX_uint16_t FREQ14_DTC7;
++ /** Frequency 2 4th Tone */
++ IFX_uint16_t FREQ24_DTC8;
++ /** Frequency 1 5th Tone */
++ IFX_uint16_t FREQ15_DTC9;
++ /** Frequency 2 5th Tone */
++ IFX_uint16_t FREQ25_DTC10;
++ );
+ } __PACKED__ ;
+
+
+--- a/src/drv_vmmc_sig_dtmfg.c
++++ b/src/drv_vmmc_sig_dtmfg.c
+@@ -742,10 +742,8 @@ IFX_int32_t irq_VMMC_SIG_DtmfOnRequest(V
+ /* Get a pointer to the data area which is behind the header of the cmd */
+ pAtgCmd = &pDtmfAtgData->FREQ11_DTC1;
+
+- /* Wipe the data area in the command. The size of this area is
+- command size - header size. */
+- /*lint -e(419) */
+- memset (pAtgCmd, 0x00, sizeof(CDM_RES_DTMFATG_DATA_t) - CMD_HDR_CNT);
++ /* Wipe the data area in the command. */
++ memset (&pDtmfAtgData->FREQS, 0x00, sizeof(pDtmfAtgData->FREQS));
+
+ /* Fill the data area */
+ if (pDtmf->bByteMode == IFX_TRUE)
--- /dev/null
+--- a/src/mps/drv_mps_vmmc_linux.c
++++ b/src/mps/drv_mps_vmmc_linux.c
+@@ -104,6 +104,10 @@ extern irqreturn_t ifx_mps_vc_irq (IFX_i
+ extern IFX_void_t ifx_mps_shutdown (IFX_void_t);
+ extern IFX_int32_t ifx_mps_event_activation_poll (mps_devices type,
+ MbxEventRegs_s * act);
++extern unsigned int ltq_get_mps_ad0_irq(void);
++extern unsigned int ltq_get_mps_ad1_irq(void);
++extern unsigned int ltq_get_mps_vc_irq(int idx);
++
+ mps_mbx_dev *ifx_mps_get_device (mps_devices type);
+
+ #ifdef CONFIG_PROC_FS
+@@ -2260,7 +2264,7 @@ IFX_int32_t __init ifx_mps_init_module (
+ /* reset the device before initializing the device driver */
+ ifx_mps_reset ();
+
+- result = request_irq (INT_NUM_IM4_IRL18,
++ result = request_irq (ltq_get_mps_ad0_irq(),
+ #ifdef LINUX_2_6
+ ifx_mps_ad0_irq, 0x0
+ #else /* */
+@@ -2270,7 +2274,7 @@ IFX_int32_t __init ifx_mps_init_module (
+ , "mps_mbx ad0", &ifx_mps_dev);
+ if (result)
+ return result;
+- result = request_irq (INT_NUM_IM4_IRL19,
++ result = request_irq (ltq_get_mps_ad1_irq(),
+ #ifdef LINUX_2_6
+ ifx_mps_ad1_irq, 0x0
+ #else /* */
+@@ -2285,7 +2289,7 @@ IFX_int32_t __init ifx_mps_init_module (
+ for (i = 0; i < 4; ++i)
+ {
+ sprintf (&voice_channel_int_name[i][0], "mps_mbx vc%d", i);
+- result = request_irq (INT_NUM_IM4_IRL14 + i,
++ result = request_irq (ltq_get_mps_vc_irq(i),
+ #ifdef LINUX_2_6
+ ifx_mps_vc_irq, 0x0
+ #else /* */
+@@ -2446,13 +2450,13 @@ ifx_mps_cleanup_module (IFX_void_t)
+ ifx_mps_release_structures (&ifx_mps_dev);
+
+ /* release all interrupts at the system */
+- free_irq (INT_NUM_IM4_IRL18, &ifx_mps_dev);
+- free_irq (INT_NUM_IM4_IRL19, &ifx_mps_dev);
++ free_irq (ltq_get_mps_ad0_irq(), &ifx_mps_dev);
++ free_irq (ltq_get_mps_ad1_irq(), &ifx_mps_dev);
+
+ /* register status interrupts for voice channels */
+ for (i = 0; i < 4; ++i)
+ {
+- free_irq (INT_NUM_IM4_IRL14 + i, &ifx_mps_dev);
++ free_irq (ltq_get_mps_vc_irq(i), &ifx_mps_dev);
+ }
+ #ifdef CONFIG_PROC_FS
+ #if CONFIG_MPS_HISTORY_SIZE > 0
+--- a/src/mps/drv_mps_vmmc_common.c
++++ b/src/mps/drv_mps_vmmc_common.c
+@@ -134,6 +134,8 @@ extern IFX_void_t mask_and_ack_danube_ir
+
+ #endif /* */
+
++extern unsigned int ltq_get_mps_vc_irq(int idx);
++
+ extern void sys_hw_setup (void);
+
+ extern IFXOS_event_t fw_ready_evt;
+@@ -2979,7 +2981,7 @@ irqreturn_t ifx_mps_ad1_irq (IFX_int32_t
+ */
+ irqreturn_t ifx_mps_vc_irq (IFX_int32_t irq, mps_comm_dev * pDev)
+ {
+- IFX_uint32_t chan = irq - INT_NUM_IM4_IRL14;
++ IFX_uint32_t chan = irq - ltq_get_mps_vc_irq(0);
+ mps_mbx_dev *mbx_dev = (mps_mbx_dev *) & (pMPSDev->voice_mb[chan]);
+ MPS_VCStatReg_u MPS_VCStatusReg;
+ MbxEventRegs_s events;
+--- a/src/mps/drv_mps_vmmc_device.h
++++ b/src/mps/drv_mps_vmmc_device.h
+@@ -69,9 +69,6 @@
+ # define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
+ # define IFX_MPS_SAD0SR IFXMIPS_MPS_SAD0SR
+ /* interrupt vectors */
+-# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
+-# define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18)
+-# define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19)
+ # define IFX_ICU_IM4_IER IFXMIPS_ICU_IM4_IER
+
+ /* ============================= */
return 0;
}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0)
+static int gca230718_probe(struct i2c_client *client)
+#else
static int gca230718_probe(struct i2c_client *client, const struct i2c_device_id *id)
+#endif
{
int status = 0;
struct gca230718_private* gca230718_privateData;
$(eval $(call KernelPackage,ata-artop))
+define KernelPackage/ata-ahci-dwc
+ TITLE:=Synopsys DWC AHCI SATA
+ KCONFIG:= \
+ CONFIG_AHCI_DWC \
+ CONFIG_SATA_HOST=y
+ FILES:=$(LINUX_DIR)/drivers/ata/ahci_dwc.ko
+ DEPENDS:=+kmod-ata-ahci-platform
+ AUTOLOAD:=$(call AutoLoad,41,ahci_dwc,1)
+ $(call AddDepends/ata,@TARGET_rockchip)
+endef
+
+$(eval $(call KernelPackage,ata-ahci-dwc))
define KernelPackage/ata-nvidia-sata
TITLE:=Nvidia Serial ATA support
ALGAPI2=crypto_algapi \
BLKCIPHER2=crypto_blkcipher
-CRYPTO_TARGET = $(BOARD)/$(if $(SUBTARGET),$(SUBTARGET),generic)
+CRYPTO_TARGET = $(BOARD)/$(SUBTARGET)
crypto_confvar=CONFIG_CRYPTO_$(word 1,$(subst =,$(space),$(1)))
crypto_file=$(LINUX_DIR)/crypto/$(word 2,$(subst =,$(space),$(1))).ko
KCONFIG:= \
CONFIG_CRYPTO_HW=y \
CONFIG_CRYPTO_DEV_IXP4XX
- FILES:=$(LINUX_DIR)/drivers/crypto/ixp4xx_crypto.ko
+ FILES:=$(LINUX_DIR)/drivers/crypto/intel/ixp4xx/ixp4xx_crypto.ko
AUTOLOAD:=$(call AutoProbe,ixp4xx_crypto)
$(call AddDepends/crypto)
endef
$(eval $(call KernelPackage,hwmon-drivetemp))
+define KernelPackage/hwmon-emc2305
+ TITLE:=Microchip EMC2301/2/3/5 fan controller
+ KCONFIG:=CONFIG_SENSORS_EMC2305
+ FILES:=$(LINUX_DIR)/drivers/hwmon/emc2305.ko
+ AUTOLOAD:=$(call AutoProbe,emc2305)
+ $(call AddDepends/hwmon,+kmod-i2c-core +PACKAGE_kmod-thermal:kmod-thermal +kmod-regmap-i2c @LINUX_6_1||LINUX_6_6)
+endef
+
+define KernelPackage/hwmon-emc2305/description
+ Kernel module for Microchip EMC2301/EMC2302/EMC2303/EMC2305 fan controllers
+endef
+
+$(eval $(call KernelPackage,hwmon-emc2305))
+
+
define KernelPackage/hwmon-gsc
TITLE:=Gateworks System Controller support
KCONFIG:=CONFIG_MFD_GATEWORKS_GSC \
define KernelPackage/mdio-devres
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Supports MDIO device registration
- DEPENDS:=+kmod-libphy +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_malta||TARGET_tegra):kmod-of-mdio
+ DEPENDS:=+kmod-libphy +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_loongarch64||TARGET_malta||TARGET_tegra):kmod-of-mdio
KCONFIG:=CONFIG_MDIO_DEVRES
HIDDEN:=1
FILES:=$(LINUX_DIR)/drivers/net/phy/mdio_devres.ko
define KernelPackage/mdio-gpio
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:= Supports GPIO lib-based MDIO busses
- DEPENDS:=+kmod-libphy @GPIO_SUPPORT +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_malta||TARGET_tegra):kmod-of-mdio
+ DEPENDS:=+kmod-libphy @GPIO_SUPPORT +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_loongarch64||TARGET_malta||TARGET_tegra):kmod-of-mdio
KCONFIG:= \
CONFIG_MDIO_BITBANG \
CONFIG_MDIO_GPIO
$(eval $(call KernelPackage,phy-aquantia))
+define KernelPackage/dsa-tag-dsa
+ SUBMENU:=$(NETWORK_DEVICES_MENU)
+ TITLE:=Marvell DSA type DSA and EDSA taggers
+ KCONFIG:= CONFIG_NET_DSA_TAG_DSA_COMMON \
+ CONFIG_NET_DSA_TAG_DSA \
+ CONFIG_NET_DSA_TAG_EDSA \
+ CONFIG_NET_DSA=y
+ FILES:=$(LINUX_DIR)/net/dsa/tag_dsa.ko
+ AUTOLOAD:=$(call AutoLoad,40,tag_dsa,1)
+endef
+
+define KernelPackage/dsa-tag-dsa/description
+ Kernel modules for Marvell DSA and EDSA tagging
+endef
+
+$(eval $(call KernelPackage,dsa-tag-dsa))
+
+define KernelPackage/dsa-mv88e6xxx
+ SUBMENU:=$(NETWORK_DEVICES_MENU)
+ TITLE:=Marvell MV88E6XXX DSA Switch
+ DEPENDS:=+kmod-ptp +kmod-phy-marvell +kmod-dsa-tag-dsa
+ KCONFIG:=CONFIG_NET_DSA_MV88E6XXX \
+ CONFIG_NET_DSA_MV88E6XXX_PTP=y \
+ CONFIG_NET_DSA=y
+ FILES:=$(LINUX_DIR)/drivers/net/dsa/mv88e6xxx/mv88e6xxx.ko
+ AUTOLOAD:=$(call AutoLoad,41,mv88e6xxx,1)
+endef
+
+define KernelPackage/dsa-mv88e6xxx/description
+ Kernel modules for MV88E6XXX DSA switches
+endef
+
+$(eval $(call KernelPackage,dsa-mv88e6xxx))
+
define KernelPackage/swconfig
SUBMENU:=$(NETWORK_DEVICES_MENU)
define KernelPackage/switch-rtl8366-smi
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Realtek RTL8366 SMI switch interface support
- DEPENDS:=@GPIO_SUPPORT +kmod-swconfig +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_malta||TARGET_tegra):kmod-of-mdio
+ DEPENDS:=@GPIO_SUPPORT +kmod-swconfig +(TARGET_armsr||TARGET_bcm27xx_bcm2708||TARGET_loongarch64||TARGET_malta||TARGET_tegra):kmod-of-mdio
KCONFIG:=CONFIG_RTL8366_SMI
FILES:=$(LINUX_DIR)/drivers/net/phy/rtl8366_smi.ko
AUTOLOAD:=$(call AutoLoad,42,rtl8366_smi,1)
define KernelPackage/acpi-video
SUBMENU:=$(VIDEO_MENU)
TITLE:=ACPI Extensions For Display Adapters
- DEPENDS:=@TARGET_x86 +kmod-backlight
+ DEPENDS:=@TARGET_x86||TARGET_loongarch64 +kmod-backlight
HIDDEN:=1
- KCONFIG:=CONFIG_ACPI_VIDEO \
- CONFIG_ACPI_WMI
- FILES:=$(LINUX_DIR)/drivers/acpi/video.ko \
- $(LINUX_DIR)/drivers/platform/x86/wmi.ko
- AUTOLOAD:=$(call AutoProbe,wmi video)
+ KCONFIG:=CONFIG_ACPI_VIDEO
+ FILES:=$(LINUX_DIR)/drivers/acpi/video.ko
+ AUTOLOAD:=$(call AutoProbe,video)
endef
define KernelPackage/acpi-video/description
Kernel support for integrated graphics devices.
endef
+define KernelPackage/acpi-video/x86
+ KCONFIG+=CONFIG_ACPI_WMI
+ FILES+=$(LINUX_DIR)/drivers/platform/x86/wmi.ko
+ AUTOLOAD:=$(call AutoProbe,wmi video)
+endef
+
$(eval $(call KernelPackage,acpi-video))
define KernelPackage/backlight
define KernelPackage/drm-amdgpu
SUBMENU:=$(VIDEO_MENU)
TITLE:=AMDGPU DRM support
- DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-ttm \
+ DEPENDS:=@TARGET_x86||TARGET_loongarch64 @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-ttm \
+kmod-drm-ttm-helper +kmod-drm-kms-helper +kmod-i2c-algo-bit +amdgpu-firmware \
+kmod-drm-display-helper +kmod-drm-buddy +kmod-acpi-video \
+LINUX_6_6:kmod-drm-exec +LINUX_6_6:kmod-drm-suballoc-helper
Direct Rendering Manager (DRM) support for AMDGPU Cards
endef
+define KernelPackage/drm-amdgpu/loongarch64
+ KCONFIG+=CONFIG_DRM_AMDGPU_USERPTR=y \
+ CONFIG_DRM_AMD_DC=y \
+ CONFIG_DRM_AMD_DC_FP=y \
+ CONFIG_DRM_AMD_DC_SI=y
+endef
+
$(eval $(call KernelPackage,drm-amdgpu))
--- /dev/null
+From 1338da257f299d35b4d954b9fda2cc7e0a54a69d Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@gmail.com>
+Date: Sun, 11 Jun 2023 14:37:32 +0200
+Subject: [PATCH] wifi: ath11k: add support DT ieee80211-freq-limit
+
+The common DT property can be used to limit the available
+channels/frequencies. But ath11k has to manually call
+wiphy_read_of_freq_limits().
+
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ drivers/net/wireless/ath/ath11k/mac.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/net/wireless/ath/ath11k/mac.c
++++ b/drivers/net/wireless/ath/ath11k/mac.c
+@@ -9455,6 +9455,7 @@ static int __ath11k_mac_register(struct
+ if (ret)
+ goto err;
+
++ wiphy_read_of_freq_limits(ar->hw->wiphy);
+ ath11k_mac_setup_ht_vht_cap(ar, cap, &ht_cap);
+ ath11k_mac_setup_he_cap(ar, cap);
+
+++ /dev/null
-From dd3b9c59cfa1e9e0b73a575f4646be905691eaef Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 16 Oct 2021 19:34:10 +0200
-Subject: [PATCH 241/241] ath11k: Disable coldboot calibration for IPQ8074
-
-There is a bug with the remoteproc reset after coldboot calibration,
-so until that is resolved disabled it to allow using the radio.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/net/wireless/ath/ath11k/core.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/net/wireless/ath/ath11k/core.c
-+++ b/drivers/net/wireless/ath/ath11k/core.c
-@@ -86,8 +86,8 @@ static const struct ath11k_hw_params ath
- .supports_shadow_regs = false,
- .idle_ps = false,
- .supports_sta_ps = false,
-- .coldboot_cal_mm = true,
-- .coldboot_cal_ftm = true,
-+ .coldboot_cal_mm = false,
-+ .coldboot_cal_ftm = false,
- .cbcal_restart_fw = true,
- .fw_mem_mode = 0,
- .num_vdevs = 16 + 1,
--- a/net/mac80211/mesh.h
+++ b/net/mac80211/mesh.h
-@@ -134,9 +134,33 @@ struct mesh_path {
+@@ -134,9 +134,38 @@ struct mesh_path {
#define MESH_FAST_TX_CACHE_TIMEOUT 8000 /* msecs */
/**
+ * @MESH_FAST_TX_TYPE_LOCAL: tx from the local vif address as SA
+ * @MESH_FAST_TX_TYPE_PROXIED: local tx with a different SA (e.g. bridged)
+ * @MESH_FAST_TX_TYPE_FORWARDED: forwarded from a different mesh point
++ * @NUM_MESH_FAST_TX_TYPE: number of entry types
+ */
+enum ieee80211_mesh_fast_tx_type {
+ MESH_FAST_TX_TYPE_LOCAL,
+ MESH_FAST_TX_TYPE_PROXIED,
+ MESH_FAST_TX_TYPE_FORWARDED,
++
++ /* must be last */
++ NUM_MESH_FAST_TX_TYPE
+};
+
++
+/**
+ * struct ieee80211_mesh_fast_tx_key - cached mesh fast tx entry key
+ *
+ */
+struct ieee80211_mesh_fast_tx_key {
+ u8 addr[ETH_ALEN] __aligned(2);
-+ enum ieee80211_mesh_fast_tx_type type;
++ u16 type;
+};
+
+/**
* @fast_tx: base fast_tx data
* @hdr: cached mesh and rfc1042 headers
* @hdrlen: length of mesh + rfc1042
-@@ -147,7 +171,7 @@ struct mesh_path {
+@@ -147,7 +176,7 @@ struct mesh_path {
*/
struct ieee80211_mesh_fast_tx {
struct rhash_head rhash;
struct ieee80211_fast_tx fast_tx;
u8 hdr[sizeof(struct ieee80211s_hdr) + sizeof(rfc1042_header)];
-@@ -333,7 +357,8 @@ void mesh_path_tx_root_frame(struct ieee
+@@ -333,7 +362,8 @@ void mesh_path_tx_root_frame(struct ieee
bool mesh_action_is_path_sel(struct ieee80211_mgmt *mgmt);
struct ieee80211_mesh_fast_tx *
- entry = rhashtable_lookup_fast(&cache->rht, addr, fast_tx_rht_params);
- if (entry)
- mesh_fast_tx_entry_free(cache, entry);
-+ for (i = MESH_FAST_TX_TYPE_LOCAL; i < MESH_FAST_TX_TYPE_FORWARDED; i++) {
++ for (i = 0; i < NUM_MESH_FAST_TX_TYPE; i++) {
+ key.type = i;
+ entry = rhashtable_lookup_fast(&cache->rht, &key, fast_tx_rht_params);
+ if (entry)
--- a/net/mac80211/sta_info.c
+++ b/net/mac80211/sta_info.c
-@@ -914,6 +914,7 @@ static int sta_info_insert_finish(struct
+@@ -918,6 +918,7 @@ static int sta_info_insert_finish(struct
if (ieee80211_vif_is_mesh(&sdata->vif))
mesh_accept_plinks_update(sdata);
PKG_DRIVERS += \
rtlwifi rtlwifi-pci rtlwifi-btcoexist rtlwifi-usb rtl8192c-common \
- rtl8192ce rtl8192se rtl8192de rtl8192cu rtl8723bs rtl8821ae \
+ rtl8192ce rtl8192se rtl8192de rtl8192cu rtl8723-common rtl8723be rtl8723bs rtl8821ae \
rtl8xxxu rtw88 rtw88-pci rtw88-usb rtw88-8821c rtw88-8822b rtw88-8822c \
rtw88-8723d rtw88-8821ce rtw88-8821cu rtw88-8822be rtw88-8822bu \
rtw88-8822ce rtw88-8822cu rtw88-8723de
config-$(call config_package,rtl8xxxu) += RTL8XXXU
config-y += RTL8XXXU_UNTESTED
+config-$(call config_package,rtl8723-common) += RTL8723_COMMON
+config-$(call config_package,rtl8723be) += RTL8723BE
+
config-$(call config_package,rtl8723bs) += RTL8723BS
config-y += STAGING
AUTOLOAD:=$(call AutoProbe,rtw88_8723)
endef
+define KernelPackage/rtl8723-common
+ $(call KernelPackage/mac80211/Default)
+ TITLE:=Realtek RTL8723AE/RTL8723BE common support module
+ DEPENDS+= +kmod-rtlwifi
+ FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8723com/rtl8723-common.ko
+ HIDDEN:=1
+endef
+
+define KernelPackage/rtl8723be
+ $(call KernelPackage/mac80211/Default)
+ TITLE:=Realtek RTL8723AE/RTL8723BE support
+ DEPENDS+= +kmod-rtlwifi-btcoexist +kmod-rtlwifi-pci +kmod-rtl8723-common +rtl8723be-firmware
+ FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8723be/rtl8723be.ko
+ AUTOLOAD:=$(call AutoProbe,rtl8723be)
+endef
+
define KernelPackage/rtl8723bs
$(call KernelPackage/mac80211/Default)
TITLE:=Realtek RTL8723BS SDIO Wireless LAN NIC driver (staging)
PKG_SOURCE_URL:=https://github.com/openwrt/mt76
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2024-04-03
-PKG_SOURCE_VERSION:=1e336a8582dce2ef32ddd440d423e9afef961e71
-PKG_MIRROR_HASH:=276613540603dc6ece9d2474ae1899b6aaa6ca93bd27824056c9689c725f5890
+PKG_SOURCE_DATE:=2024-05-17
+PKG_SOURCE_VERSION:=513c131c6309712a51502870b041f45b4bd6a6d4
+PKG_MIRROR_HASH:=3e5d8ee6b8b122cc4e32668fdde0552a9fa23819b7ebdc758ecb63b5f761683a
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_USE_NINJA:=0
$(INSTALL_BIN) $(PKG_BUILD_DIR)/tools/mt76-test $(1)/usr/sbin
endef
+define Build/InstallDev
+ mkdir -p $(STAGING_DIR_IMAGE)
+ $(CP) $(PKG_BUILD_DIR)/firmware/mt7981_eeprom_mt7976_dbdc.bin $(STAGING_DIR_IMAGE)/
+endef
+
$(eval $(call KernelPackage,mt76-core))
$(eval $(call KernelPackage,mt76-usb))
$(eval $(call KernelPackage,mt76x02-usb))
PKG_SOURCE_URL:=https://github.com/kaloz/mwlwifi
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2023-11-29
-PKG_SOURCE_VERSION:=ebf3167445f108346dcff9a31a708534c0bd7cc5
-PKG_MIRROR_HASH:=6dffc08208305366b9c25133b74693d5c2e544c1076b7b4ed846628c66be56c1
+PKG_SOURCE_DATE:=2024-04-19
+PKG_SOURCE_VERSION:=a737d348ef4fe00434b2bc44b2b6a68ea833d95b
+PKG_MIRROR_HASH:=d55f69c2fa48d02ba535b72b108fc77f5f13a52b29130a631489a053f1670d2c
PKG_MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
PKG_BUILD_PARALLEL:=1
include $(TOPDIR)/rules.mk
PKG_NAME:=qca-nss-dp
-PKG_RELEASE:=2
+PKG_RELEASE:=1
PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/nss-dp.git
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2023-06-06
-PKG_SOURCE_VERSION:=fa67464466f69f00967cc373d1bdd6025f57eb89
-PKG_MIRROR_HASH:=39329770042c85b32780cd12eef2aad2c5df79f34d1b7081e5ba1e1cc0b1b161
+PKG_SOURCE_DATE:=2024-04-16
+PKG_SOURCE_VERSION:=5bf8b91e9fc209f175f9a58723b03055ace3d581
+PKG_MIRROR_HASH:=e86b04ea674c18fb69cd09a45ccab50317b85117e40d76c8457052c2e55d7c18
PKG_BUILD_PARALLEL:=1
PKG_FLAGS:=nonshared
--- a/include/nss_dp_dev.h
+++ b/include/nss_dp_dev.h
-@@ -202,13 +202,10 @@ struct nss_dp_dev {
+@@ -225,13 +225,10 @@ struct nss_dp_dev {
unsigned long drv_flags; /* Driver specific feature flags */
/* Phy related stuff */
--- a/nss_dp_main.c
+++ b/nss_dp_main.c
-@@ -418,7 +418,7 @@ static int nss_dp_open(struct net_device
+@@ -436,7 +436,7 @@ static int nss_dp_open(struct net_device
netif_start_queue(netdev);
/* Notify data plane link is up */
if (dp_priv->data_plane_ops->link_state(dp_priv->dpc, 1)) {
netdev_dbg(netdev, "Data plane set link failed\n");
-@@ -615,6 +615,12 @@ static int32_t nss_dp_of_get_pdata(struc
+@@ -633,6 +633,12 @@ static int32_t nss_dp_of_get_pdata(struc
return -EFAULT;
}
if (of_property_read_u32(np, "qcom,mactype", &hal_pdata->mactype)) {
pr_err("%s: error reading mactype\n", np->name);
return -EFAULT;
-@@ -635,18 +641,6 @@ static int32_t nss_dp_of_get_pdata(struc
+@@ -653,18 +659,6 @@ static int32_t nss_dp_of_get_pdata(struc
return -EFAULT;
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
maddr = (uint8_t *)of_get_mac_address(np);
#if (LINUX_VERSION_CODE > KERNEL_VERSION(5, 4, 0))
-@@ -695,56 +689,6 @@ static int32_t nss_dp_of_get_pdata(struc
+@@ -753,56 +747,6 @@ static int32_t nss_dp_of_get_pdata(struc
return 0;
}
#ifdef CONFIG_NET_SWITCHDEV
/*
* nss_dp_is_phy_dev()
-@@ -803,7 +747,6 @@ static int32_t nss_dp_probe(struct platf
+@@ -861,7 +805,6 @@ static int32_t nss_dp_probe(struct platf
struct device_node *np = pdev->dev.of_node;
struct nss_gmac_hal_platform_data gmac_hal_pdata;
int32_t ret = 0;
#if defined(NSS_DP_PPE_SUPPORT)
uint32_t vsi_id;
fal_port_t port_id;
-@@ -880,22 +823,14 @@ static int32_t nss_dp_probe(struct platf
+@@ -940,22 +883,16 @@ static int32_t nss_dp_probe(struct platf
dp_priv->drv_flags |= NSS_DP_PRIV_FLAG(INIT_DONE);
- }
- snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
- dp_priv->miibus->id, dp_priv->phy_mdio_addr);
--
+ if (dp_priv->phy_node) {
- SET_NETDEV_DEV(netdev, &pdev->dev);
- dp_priv->phydev = phy_connect(netdev, phy_id,
- &nss_dp_adjust_link,
- dp_priv->phy_mii_type);
- if (IS_ERR(dp_priv->phydev)) {
- netdev_dbg(netdev, "failed to connect to phy device\n");
+- goto phy_setup_fail;
+- }
+ dp_priv->phydev = of_phy_connect(netdev, dp_priv->phy_node,
-+ &nss_dp_adjust_link, 0,
-+ dp_priv->phy_mii_type);
++ &nss_dp_adjust_link, 0,
++ dp_priv->phy_mii_type);
+ if (!(dp_priv->phydev)) {
+ netdev_err(netdev, "failed to connect to phy device\n");
- goto phy_setup_fail;
- }
++ goto phy_setup_fail;
++ }
++ phy_attached_info(dp_priv->phydev);
}
+
+ #if defined(NSS_DP_PPE_SUPPORT)
--- a/nss_dp_main.c
+++ b/nss_dp_main.c
-@@ -746,18 +746,29 @@ static int32_t nss_dp_probe(struct platf
+@@ -804,18 +804,29 @@ static int32_t nss_dp_probe(struct platf
struct nss_dp_dev *dp_priv;
struct device_node *np = pdev->dev.of_node;
struct nss_gmac_hal_platform_data gmac_hal_pdata;
#define NSS_DP_SWITCH_ID 0
#define NSS_DP_SW_ETHTYPE_PID 0 /* PPE ethtype profile ID for slow protocols */
-@@ -521,7 +523,76 @@ static struct notifier_block *nss_dp_sw_
+@@ -534,7 +536,76 @@ static struct notifier_block *nss_dp_sw_
#else
+++ /dev/null
-From 01ec275bd0942ddc6b80e1d3671cdc66be670f57 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 1 Sep 2023 12:23:58 +0200
-Subject: [PATCH] nss-dp: include <net/netdev_rx_queue.h>
-
-Since 6.5 netdev_rx_queue was moved out of netdevice.h so include the new
-header since that is where it lives now.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- nss_dp_main.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/nss_dp_main.c
-+++ b/nss_dp_main.c
-@@ -34,6 +34,9 @@
- #if defined(NSS_DP_MAC_POLL_SUPPORT)
- #include <init/ssdk_init.h>
- #endif
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 5, 0))
-+#include <net/netdev_rx_queue.h>
-+#endif
-
- #include "nss_dp_hal.h"
-
--- /dev/null
+From c318c90b824c59539bf2e33618e381293398616c Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 15:02:49 +0200
+Subject: [PATCH 1/6] edma_v1: rework hw_reset logic to permit rmmod and insmod
+
+Rework hw_reset logic for edma v1 to permit rmmod and insmod by using
+get_exclusive_released variant (assuming the reset control was released)
+and manually acquire and release it.
+
+This permits rmmod and insmod without triggering warning or receiving
+-EBUSY errors.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ hal/dp_ops/edma_dp/edma_v1/edma_cfg.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c
++++ b/hal/dp_ops/edma_dp/edma_v1/edma_cfg.c
+@@ -719,18 +719,22 @@ int edma_hw_reset(struct edma_hw *ehw)
+ struct reset_control *rst;
+ struct platform_device *pdev = ehw->pdev;
+
+- rst = devm_reset_control_get(&pdev->dev, EDMA_HW_RESET_ID);
++ rst = devm_reset_control_get_exclusive_released(&pdev->dev, EDMA_HW_RESET_ID);
+ if (IS_ERR(rst)) {
+ pr_warn("DTS Node: %s does not exist\n", EDMA_HW_RESET_ID);
+ return -EINVAL;
+ }
+
++ reset_control_acquire(rst);
++
+ reset_control_assert(rst);
+ udelay(100);
+
+ reset_control_deassert(rst);
+ udelay(100);
+
++ reset_control_release(rst);
++
+ pr_info("EDMA HW Reset completed succesfully\n");
+
+ return 0;
--- /dev/null
+From 079bfe441b274a8c06474be82e4ccc88599a5e0e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 16:08:46 +0200
+Subject: [PATCH 2/6] nss_dp_switchdev: correctly unregister notifier on
+ dp_remove
+
+Correctly unregister notifier on dp_remove to fix kernel panic on system
+reboot.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ include/nss_dp_dev.h | 1 +
+ nss_dp_main.c | 4 ++++
+ nss_dp_switchdev.c | 13 +++++++++++++
+ 3 files changed, 18 insertions(+)
+
+--- a/include/nss_dp_dev.h
++++ b/include/nss_dp_dev.h
+@@ -349,6 +349,7 @@ void nss_dp_set_ethtool_ops(struct net_d
+ */
+ #ifdef CONFIG_NET_SWITCHDEV
+ void nss_dp_switchdev_setup(struct net_device *dev);
++void nss_dp_switchdev_remove(struct net_device *dev);
+ bool nss_dp_is_phy_dev(struct net_device *dev);
+ #endif
+
+--- a/nss_dp_main.c
++++ b/nss_dp_main.c
+@@ -970,6 +970,10 @@ static int nss_dp_remove(struct platform
+ if (!dp_priv)
+ continue;
+
++ #ifdef CONFIG_NET_SWITCHDEV
++ nss_dp_switchdev_remove(dp_priv->netdev);
++ #endif
++
+ dp_ops = dp_priv->data_plane_ops;
+ hal_ops = dp_priv->gmac_hal_ops;
+
+--- a/nss_dp_switchdev.c
++++ b/nss_dp_switchdev.c
+@@ -648,4 +648,17 @@ void nss_dp_switchdev_setup(struct net_d
+
+ switch_init_done = true;
+ }
++
++void nss_dp_switchdev_remove(struct net_device *dev)
++{
++ if (!switch_init_done)
++ return;
++
++ if (nss_dp_sw_ev_nb)
++ unregister_switchdev_notifier(nss_dp_sw_ev_nb);
++
++ unregister_switchdev_blocking_notifier(&nss_dp_switchdev_notifier);
++
++ switch_init_done = false;
++}
+ #endif
--- /dev/null
+From ab7b1a361d51157118e1a61ce6530a59bcef4b61 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 16:10:09 +0200
+Subject: [PATCH 3/6] nss_dp_main: swap dp_exit function call
+
+First unregister nss_dp platform devices then cleanup the HAL.
+
+This is to fix kernel panic by cleaning data that needs to be used by
+platform driver unregister functions.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ nss_dp_main.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/nss_dp_main.c
++++ b/nss_dp_main.c
+@@ -1161,6 +1161,8 @@ int __init nss_dp_init(void)
+ */
+ void __exit nss_dp_exit(void)
+ {
++ platform_driver_unregister(&nss_dp_drv);
++
+ /*
+ * TODO Move this to soc_ops
+ */
+@@ -1168,8 +1170,6 @@ void __exit nss_dp_exit(void)
+ nss_dp_hal_cleanup();
+ dp_global_ctx.common_init_done = false;
+ }
+-
+- platform_driver_unregister(&nss_dp_drv);
+ }
+
+ module_init(nss_dp_init);
--- /dev/null
+From 33dd3aa6d0f9cd240d63f53a49157ae44ebccf87 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 16:12:11 +0200
+Subject: [PATCH 4/6] nss_dp_main: call unregister_netdev first in dp_remove
+ and carrifer_off
+
+In dp_remove move unregister_netdev up before calling exit and deinit
+and first call netif_carrier_off to stop any traffic from happening and
+prevent kernel panics for napi in the middle of transfer.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ nss_dp_main.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/nss_dp_main.c
++++ b/nss_dp_main.c
+@@ -977,6 +977,9 @@ static int nss_dp_remove(struct platform
+ dp_ops = dp_priv->data_plane_ops;
+ hal_ops = dp_priv->gmac_hal_ops;
+
++ netif_carrier_off(dp_priv->netdev);
++ unregister_netdev(dp_priv->netdev);
++
+ if (dp_priv->phydev)
+ phy_disconnect(dp_priv->phydev);
+
+@@ -988,7 +991,6 @@ static int nss_dp_remove(struct platform
+ #endif
+ hal_ops->exit(dp_priv->gmac_hal_ctx);
+ dp_ops->deinit(dp_priv->dpc);
+- unregister_netdev(dp_priv->netdev);
+ free_netdev(dp_priv->netdev);
+ dp_global_ctx.nss_dp[i] = NULL;
+ }
--- /dev/null
+From 655b07b701271bc00952fe64aeb14f993a48a50e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 16:17:36 +0200
+Subject: [PATCH 5/6] nss_dp_main: use phy_detach instead of disconnect in
+ dp_remove
+
+Use phy_detach instead of disconnect in dp_remove. On Module remove, phy
+are already disconnected but they need to be detached to be correctly
+reattached later with an insmod.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ nss_dp_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/nss_dp_main.c
++++ b/nss_dp_main.c
+@@ -981,7 +981,7 @@ static int nss_dp_remove(struct platform
+ unregister_netdev(dp_priv->netdev);
+
+ if (dp_priv->phydev)
+- phy_disconnect(dp_priv->phydev);
++ phy_detach(dp_priv->phydev);
+
+ #if defined(NSS_DP_PPE_SUPPORT)
+ /*
--- /dev/null
+From c7c59c6097d94dbab8fc68dae798017bdbc5b3b9 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 16:22:32 +0200
+Subject: [PATCH 6/6] edma_v1: skip edma_disable_port in edma_cleanup
+ subsequent run
+
+Skip edma_disable_port in edma_cleanup subsequent run as it will cause
+the kernel panic as the regs are already freed by previous run of
+edma_cleanup. It's use it's not clear but the call is already done in
+the first run of edma_cleanup. Maybe an oversight never dropped?
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+--- a/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
++++ b/hal/dp_ops/edma_dp/edma_v1/edma_data_plane.c
+@@ -326,9 +326,15 @@ void edma_cleanup(bool is_dp_override)
+ * Disable EDMA only at module exit time, since NSS firmware
+ * depends on this setting.
+ */
+- if (!is_dp_override) {
+- edma_disable_port();
+- }
++ /* This call will make the kernel panic as reg used by
++ * edma_disable_port are already freed by previous call of
++ * edma_cleanup. Logic is not clear of WHY this is called.
++ * Keep this here for reference if someone EVER wants
++ * to investigate.
++ */
++ // if (!is_dp_override) {
++ // edma_disable_port();
++ // }
+ return;
+ }
+
include $(TOPDIR)/rules.mk
PKG_NAME:=qca-ssdk
-PKG_RELEASE:=6
+PKG_RELEASE:=2
PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2023-10-04
-PKG_SOURCE_VERSION:=23a5aa4a4d5834da7a07efb58baebfbee91786b0
-PKG_MIRROR_HASH:=53fb201053b3aca004c4da07b06a0608b0b3322a2062b1f7ab3b3a7871ddabcb
+PKG_SOURCE_DATE:=2024-04-17
+PKG_SOURCE_VERSION:=3d060f7ad70d087f6b0452abe79ab6d042e8cd53
+PKG_MIRROR_HASH:=6f5e390b294e699491584094f5d7eb941de6237ad8c5320191e9e306fbcd8eb5
PKG_FLAGS:=nonshared
PKG_BUILD_PARALLEL:=1
GCC_VERSION=$(GCC_VERSION) \
EXTRA_CFLAGS="-fno-stack-protector -I$(STAGING_DIR)/usr/include" \
SoC=$(CONFIG_TARGET_SUBTARGET) \
+ SHELL="$(BASH)" \
PTP_FEATURE=disable SWCONFIG_FEATURE=disable \
ISISC_ENABLE=disable IN_QCA803X_PHY=FALSE \
IN_QCA808X_PHY=FALSE IN_MALIBU_PHY=FALSE \
+++ /dev/null
-From f6c0115daaac586740e873a3b8145c5370a73dce Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 17 Feb 2024 13:02:31 +0100
-Subject: [PATCH] config: identify kernel 6.6
-
-Identify kernel 6.6 so it can be compiled against.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- config | 5 +++++
- make/linux_opt.mk | 4 ++--
- 2 files changed, 7 insertions(+), 2 deletions(-)
-
---- a/config
-+++ b/config
-@@ -27,6 +27,11 @@ endif
- ifeq ($(KVER),$(filter 6.1%,$(KVER)))
- OS_VER=6_1
- endif
-+
-+ifeq ($(KVER),$(filter 6.6%,$(KVER)))
-+ OS_VER=6_6
-+endif
-+
- ifeq ($(KVER), 3.4.0)
- OS_VER=3_4
- endif
---- a/make/linux_opt.mk
-+++ b/make/linux_opt.mk
-@@ -450,7 +450,7 @@ ifeq (KSLIB, $(MODULE_TYPE))
- KASAN_SHADOW_SCALE_SHIFT := 3
- endif
-
-- ifeq ($(OS_VER),$(filter 5_4 6_1, $(OS_VER)))
-+ ifeq ($(OS_VER),$(filter 5_4 6_1 6_6, $(OS_VER)))
- ifeq ($(ARCH), arm64)
- KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT)
- endif
-@@ -481,7 +481,7 @@ ifeq (KSLIB, $(MODULE_TYPE))
-
- endif
-
-- ifeq ($(OS_VER),$(filter 4_4 5_4 6_1, $(OS_VER)))
-+ ifeq ($(OS_VER),$(filter 4_4 5_4 6_1 6_6, $(OS_VER)))
- MODULE_CFLAG += -DKVER34
- MODULE_CFLAG += -DKVER32
- MODULE_CFLAG += -DLNX26_22
--- a/src/hsl/phy/hsl_phy.c
+++ b/src/hsl/phy/hsl_phy.c
-@@ -1335,6 +1335,9 @@ hsl_port_phydev_interface_mode_status_ge
+@@ -1322,6 +1322,9 @@ hsl_port_phydev_interface_mode_status_ge
case PHY_INTERFACE_MODE_10GKR:
*interface_mode_status = PORT_10GBASE_R;
break;
--- a/include/init/ssdk_dts.h
+++ b/include/init/ssdk_dts.h
-@@ -101,6 +101,7 @@ typedef struct
+@@ -99,6 +99,7 @@ typedef struct
a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/
a_uint32_t clk_mode;
a_uint32_t pcie_hw_base;
+ a_uint32_t port3_pcs_channel;
+ led_ctrl_pattern_t source_pattern[SSDK_MAX_PORT_NUM][PORT_LED_SOURCE_MAX];
} ssdk_dt_cfg;
- #define SSDK_MAX_NR_ETH 6
-@@ -162,6 +163,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t
+@@ -161,6 +162,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t
struct device_node *ssdk_dts_node_get(a_uint32_t dev_id);
struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id);
struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id);
cppe_port_mux_ctrl.bf.port4_pcs_sel =
--- a/src/adpt/hppe/adpt_hppe_uniphy.c
+++ b/src/adpt/hppe/adpt_hppe_uniphy.c
-@@ -1122,9 +1122,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
+@@ -1160,9 +1160,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
{
a_uint32_t i;
sw_error_t rv = SW_OK;
union uniphy_mode_ctrl_u uniphy_mode_ctrl;
-@@ -1134,9 +1131,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
+@@ -1172,9 +1169,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index);
#if defined(CPPE)
if (adpt_ppe_type_get(dev_id) == CPPE_TYPE) {
+a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id)
+{
+ ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
-+
++
+ return cfg->port3_pcs_channel;
+}
+
- #ifndef BOARD_AR71XX
#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id,
-@@ -306,6 +313,25 @@ static void ssdk_dt_parse_mac_mode(a_uin
+ struct device_node *switch_node, ssdk_init_cfg *cfg)
+@@ -305,6 +312,25 @@ static void ssdk_dt_parse_mac_mode(a_uin
return;
}
+{
+ const __be32 *port3_pcs_channel;
+ a_uint32_t len = 0;
-+
++
+ port3_pcs_channel = of_get_property(switch_node, "port3_pcs_channel", &len);
+ if (!port3_pcs_channel) {
+ ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel = 2;
#ifdef IN_UNIPHY
static void ssdk_dt_parse_uniphy(a_uint32_t dev_id)
{
-@@ -1292,6 +1318,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg *
+@@ -1347,6 +1373,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg *
rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv);
SW_RTN_ON_ERROR(rv);
ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg);
--- /dev/null
+From ab3b663842f66d0ed290696cee9edb9070a36e8f Mon Sep 17 00:00:00 2001
+From: Paweł Owoc <frut3k7@gmail.com>
+Date: Wed, 7 May 2024 10:37:44 +0100
+Subject: [PATCH] hsl_phy: add support for AQR114C-B0 PHY
+
+Add support for AQR114C-B0 PHY.
+
+Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
+---
+ include/hsl/phy/hsl_phy.h | 1 +
+ src/hsl/phy/hsl_phy.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/include/hsl/phy/hsl_phy.h
++++ b/include/hsl/phy/hsl_phy.h
+@@ -612,6 +612,7 @@ typedef struct {
+ #define AQUANTIA_PHY_113C_B0 0x31c31C12
+ #define AQUANTIA_PHY_113C_B1 0x31c31C13
+ #define AQUANTIA_PHY_112C 0x03a1b792
++#define AQUANTIA_PHY_114C_B0 0x31c31c22
+ #define MVL_PHY_X3410 0x31c31DD3
+
+ #define PHY_805XV2 0x004DD082
+--- a/src/hsl/phy/hsl_phy.c
++++ b/src/hsl/phy/hsl_phy.c
+@@ -271,6 +271,7 @@ phy_type_t hsl_phytype_get_by_phyid(a_uint32_t dev_id, a_uint32_t phy_id)
+ case AQUANTIA_PHY_113C_B0:
+ case AQUANTIA_PHY_113C_B1:
+ case AQUANTIA_PHY_112C:
++ case AQUANTIA_PHY_114C_B0:
+ case MVL_PHY_X3410:
+ phytype = AQUANTIA_PHY_CHIP;
+ break;
+++ /dev/null
-From bdae481e89cbe551068a99028bb57119b59f5ff4 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 26 Mar 2024 12:19:49 +0100
-Subject: [PATCH] mdio: adapt to C22 and C45 read/write split
-
-Kernel 6.3 has introduced separate C45 read/write operations, and thus
-split them out of the C22 operations completely so the old way of marking
-C45 reads and writes via the register value does not work anymore.
-
-This is causing SSDK to fail and find C45 only PHY-s such as Aquantia ones:
-[ 22.187877] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 8, phy_id = 0x0 phytype doesn't match
-[ 22.209924] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 0, phy_id = 0x0 phytype doesn't match
-
-This in turn causes USXGMII MAC autoneg bit to not get set and then UNIPHY
-autoneg will time out, causing the 10G ports not to work:
-[ 37.292784] uniphy autoneg time out!
-
-So, lets detect C45 reads and writes by the magic BIT(30) in the register
-argument and if so call separate C45 mdiobus read/write functions.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- include/init/ssdk_plat.h | 7 +++++++
- src/init/ssdk_plat.c | 30 ++++++++++++++++++++++++++++++
- 2 files changed, 37 insertions(+)
-
---- a/include/init/ssdk_plat.h
-+++ b/include/init/ssdk_plat.h
-@@ -505,3 +505,10 @@ void ssdk_plat_exit(a_uint32_t dev_id);
-
- #endif
- /*qca808x_end*/
-+
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
-+#define MII_ADDR_C45 (1<<30)
-+#define MII_DEVADDR_C45_SHIFT 16
-+#define MII_DEVADDR_C45_MASK GENMASK(20, 16)
-+#define MII_REGADDR_C45_MASK GENMASK(15, 0)
-+#endif
---- a/src/init/ssdk_plat.c
-+++ b/src/init/ssdk_plat.c
-@@ -356,6 +356,18 @@ phy_addr_validation_check(a_uint32_t phy
- return A_TRUE;
- }
-
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
-+static inline u16 mdiobus_c45_regad(u32 regnum)
-+{
-+ return FIELD_GET(MII_REGADDR_C45_MASK, regnum);
-+}
-+
-+static inline u16 mdiobus_c45_devad(u32 regnum)
-+{
-+ return FIELD_GET(MII_DEVADDR_C45_MASK, regnum);
-+}
-+#endif
-+
- sw_error_t
- qca_ar8327_phy_read(a_uint32_t dev_id, a_uint32_t phy_addr,
- a_uint32_t reg, a_uint16_t* data)
-@@ -371,9 +383,18 @@ qca_ar8327_phy_read(a_uint32_t dev_id, a
- if (!bus)
- return SW_NOT_SUPPORTED;
- phy_addr = TO_PHY_ADDR(phy_addr);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
-+ mutex_lock(&bus->mdio_lock);
-+ if (reg & MII_ADDR_C45)
-+ *data = __mdiobus_c45_read(bus, phy_addr, mdiobus_c45_devad(reg), mdiobus_c45_regad(reg));
-+ else
-+ *data = __mdiobus_read(bus, phy_addr, reg);
-+ mutex_unlock(&bus->mdio_lock);
-+#else
- mutex_lock(&bus->mdio_lock);
- *data = __mdiobus_read(bus, phy_addr, reg);
- mutex_unlock(&bus->mdio_lock);
-+#endif
-
- return 0;
- }
-@@ -393,9 +414,18 @@ qca_ar8327_phy_write(a_uint32_t dev_id,
- if (!bus)
- return SW_NOT_SUPPORTED;
- phy_addr = TO_PHY_ADDR(phy_addr);
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
-+ mutex_lock(&bus->mdio_lock);
-+ if (reg & MII_ADDR_C45)
-+ __mdiobus_c45_write(bus, phy_addr, mdiobus_c45_devad(reg), mdiobus_c45_regad(reg), data);
-+ else
-+ __mdiobus_write(bus, phy_addr, reg, data);
-+ mutex_unlock(&bus->mdio_lock);
-+#else
- mutex_lock(&bus->mdio_lock);
- __mdiobus_write(bus, phy_addr, reg, data);
- mutex_unlock(&bus->mdio_lock);
-+#endif
-
- return 0;
- }
kslib_c:
--- a/make/linux_opt.mk
+++ b/make/linux_opt.mk
-@@ -777,6 +777,6 @@ LOCAL_CFLAGS += $(CPU_CFLAG) -D"KBUILD_M
+@@ -778,6 +778,6 @@ LOCAL_CFLAGS += $(CPU_CFLAG) -D"KBUILD_M
####################################################################
# cflags for LNX Modules-Style Makefile
####################################################################
--- /dev/null
+--- a/src/fal/fal_port_ctrl.c
++++ b/src/fal/fal_port_ctrl.c
+@@ -2089,7 +2089,7 @@ fal_port_hibernate_get (a_uint32_t dev_i
+ */
+ sw_error_t
+ fal_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+- a_uint32_t * cable_status, a_uint32_t * cable_len)
++ fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+ {
+ sw_error_t rv;
+
+--- a/src/fal/fal_portvlan.c
++++ b/src/fal/fal_portvlan.c
+@@ -2173,7 +2173,7 @@ fal_netisolate_get(a_uint32_t dev_id, a_
+ * @return SW_OK or error code
+ */
+ sw_error_t
+-fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable)
++fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable)
+ {
+ sw_error_t rv;
+
+@@ -2190,7 +2190,7 @@ fal_eg_trans_filter_bypass_en_set(a_uint
+ * @return SW_OK or error code
+ */
+ sw_error_t
+-fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t* enable)
++fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t* enable)
+ {
+ sw_error_t rv;
+
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/gpio/consumer.h>
-#include <linux/version.h>
/**
* Driver for the Ubiquiti RGB LED controller (LEDBAR).
return ret;
}
-
-static int ubnt_ledbar_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
+static int ubnt_ledbar_probe(struct i2c_client *client)
{
struct device_node *np = client->dev.of_node;
struct ubnt_ledbar *ledbar;
return ubnt_ledbar_apply_state(ledbar);
}
-#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)
-static int ubnt_ledbar_remove(struct i2c_client *client)
-#else
static void ubnt_ledbar_remove(struct i2c_client *client)
-#endif
{
struct ubnt_ledbar *ledbar = i2c_get_clientdata(client);
mutex_destroy(&ledbar->lock);
-
-#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0)
- return 0;
-#endif
}
static const struct i2c_device_id ubnt_ledbar_id[] = {
include $(TOPDIR)/rules.mk
PKG_NAME:=elfutils
-PKG_VERSION:=0.189
+PKG_VERSION:=0.191
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://sourceware.org/$(PKG_NAME)/ftp/$(PKG_VERSION)
-PKG_HASH:=39bd8f1a338e2b7cd4abc3ff11a0eddc6e690f69578a57478d8179b4148708c8
+PKG_HASH:=df76db71366d1d708365fc7a6c60ca48398f14367eb2b8954efc8897147ad871
PKG_MAINTAINER:=Luiz Angelo Daros de Luca <luizluca@gmail.com>
PKG_LICENSE:=GPL-3.0-or-later
- libasm debuginfod src po doc tests
+ libasm
- EXTRA_DIST = elfutils.spec GPG-KEY NOTES CONTRIBUTING \
+ EXTRA_DIST = elfutils.spec GPG-KEY NOTES CONTRIBUTING SECURITY \
COPYING COPYING-GPLV2 COPYING-LGPLV3
include $(TOPDIR)/rules.mk
PKG_NAME:=gettext-full
-PKG_VERSION:=0.21.1
-PKG_RELEASE:=2
+PKG_VERSION:=0.22.5
+PKG_RELEASE:=1
PKG_SOURCE:=gettext-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNU/gettext
-PKG_HASH:=50dbc8f39797950aa2c98e939947c527e5ac9ebd2c1b99dd7b06ba33a6767ae6
+PKG_HASH:=fe10c37353213d78a5b83d48af231e005c4da84db5ce88037d88355938259640
PKG_BUILD_DIR:=$(BUILD_DIR)/gettext-$(PKG_VERSION)
HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/gettext-$(PKG_VERSION)
--- a/autogen.sh
+++ b/autogen.sh
-@@ -78,6 +78,7 @@ if ! $skip_gnulib; then
+@@ -81,6 +81,7 @@ if ! $skip_gnulib; then
getopt-gnu
gettext-h
havelib
progname
--- a/gettext-runtime/src/Makefile.am
+++ b/gettext-runtime/src/Makefile.am
-@@ -40,7 +40,7 @@ envsubst_SOURCES = envsubst.c
+@@ -43,7 +43,7 @@ envsubst_SOURCES = envsubst.c
# Link dependencies.
# Need @LTLIBICONV@ because striconv.c uses iconv().
+++ /dev/null
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-
-PKG_NAME:=libaudit
-PKG_VERSION:=2.8.5
-PKG_RELEASE:=1
-
-PKG_SOURCE_NAME:=audit
-PKG_SOURCE:=$(PKG_SOURCE_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_URL:=https://people.redhat.com/sgrubb/audit
-PKG_HASH:=0e5d4103646e00f8d1981e1cd2faea7a2ae28e854c31a803e907a383c5e2ecb7
-PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_SOURCE_NAME)-$(PKG_VERSION)
-HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_SOURCE_NAME)-$(PKG_VERSION)
-PKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>
-PKG_LICENSE:=GPL-2.0
-PKG_LICENSE_FILES:=COPYING
-PKG_CPE_ID:=cpe:/a:linux_audit_project:linux_audit
-
-PKG_FIXUP:=autoreconf
-
-PKG_BUILD_FLAGS:=no-mips16
-PKG_INSTALL:=1
-
-include $(INCLUDE_DIR)/package.mk
-include $(INCLUDE_DIR)/host-build.mk
-
-define Package/libaudit
- CATEGORY:=Libraries
- TITLE:=Linux Auditing Framework (shared library)
- URL:=http://people.redhat.com/sgrubb/audit/
-endef
-
-define Package/libaudit/description
- This package contains the audit shared library.
-endef
-
-CONFIGURE_VARS += \
- LDFLAGS_FOR_BUILD="$(HOST_LDFLAGS)" \
- CPPFLAGS_FOR_BUILD="$(HOST_CPPFLAGS)" \
- CFLAGS_FOR_BUILD="$(HOST_CFLAGS)" \
- CC_FOR_BUILD="$(HOSTCC)"
-
-CONFIGURE_ARGS += \
- --without-libcap-ng \
- --disable-systemd \
- --without-python \
- --without-python3 \
- --disable-zos-remote
-
-ifeq ($(ARCH),aarch64)
-CONFIGURE_ARGS += --with-aarch64
-else ifeq ($(ARCH),arm)
-CONFIGURE_ARGS += --with-arm
-endif
-
-HOST_CONFIGURE_ARGS += \
- --without-libcap-ng \
- --disable-systemd \
- --without-python \
- --without-python3 \
- --disable-zos-remote
-
-MAKE_PATH:=lib
-
-# Host/Compile/default doesn't include $(MAKE_PATH), override to use,
-# so we avoid building and installing unnecessary parts on the host.
-define Host/Compile
- +$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/$(MAKE_PATH) $(HOST_MAKE_FLAGS) all
-endef
-
-define Host/Install
- +$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/lib $(HOST_MAKE_FLAGS) install
- +$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/init.d $(HOST_MAKE_FLAGS) install
-endef
-
-# We can't use the default, as the default passes $(MAKE_ARGS), which
-# overrides CC, CFLAGS, etc. and defeats the *_FOR_BUILD definitions
-# passed in CONFIGURE_VARS
-define Build/Compile
- $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/$(MAKE_PATH)
-endef
-
-define Build/Install
- $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/lib $(MAKE_INSTALL_FLAGS) install
- $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/init.d $(MAKE_INSTALL_FLAGS) install
-endef
-
-define Build/InstallDev
- $(INSTALL_DIR) $(1)/usr/include
- $(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/
- $(INSTALL_DIR) $(1)/usr/lib/pkgconfig
- $(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/*.pc $(1)/usr/lib/pkgconfig/
- $(INSTALL_DIR) $(1)/usr/lib
- $(CP) $(PKG_INSTALL_DIR)/usr/lib/* $(1)/usr/lib/
-endef
-
-define Package/libaudit/install
- $(INSTALL_DIR) $(1)/usr/lib
- $(CP) $(PKG_INSTALL_DIR)/usr/lib/*.so.* $(1)/usr/lib/
- $(INSTALL_DIR) $(1)/etc
- $(CP) $(PKG_INSTALL_DIR)/etc/libaudit.conf $(1)/etc/
-endef
-
-$(eval $(call HostBuild))
-$(eval $(call BuildPackage,libaudit))
+++ /dev/null
-From c39a071e7c021f6ff3554aca2758e97b47a9777c Mon Sep 17 00:00:00 2001
-From: Steve Grubb <sgrubb@redhat.com>
-Date: Tue, 26 Feb 2019 18:33:33 -0500
-Subject: [PATCH] Add substitue functions for strndupa & rawmemchr
-
-(cherry picked from commit d579a08bb1cde71f939c13ac6b2261052ae9f77e)
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
----
- auparse/auparse.c | 12 +++++++++++-
- auparse/interpret.c | 9 ++++++++-
- configure.ac | 14 +++++++++++++-
- src/ausearch-lol.c | 12 +++++++++++-
- 4 files changed, 43 insertions(+), 4 deletions(-)
-
-diff --git a/auparse/auparse.c b/auparse/auparse.c
-index 650db02..2e1c737 100644
---- a/auparse/auparse.c
-+++ b/auparse/auparse.c
-@@ -1,5 +1,5 @@
- /* auparse.c --
-- * Copyright 2006-08,2012-17 Red Hat Inc., Durham, North Carolina.
-+ * Copyright 2006-08,2012-19 Red Hat Inc., Durham, North Carolina.
- * All Rights Reserved.
- *
- * This library is free software; you can redistribute it and/or
-@@ -1118,6 +1118,16 @@ static int str2event(char *s, au_event_t *e)
- return 0;
- }
-
-+#ifndef HAVE_STRNDUPA
-+static inline char *strndupa(const char *old, size_t n)
-+{
-+ size_t len = strnlen(old, n);
-+ char *tmp = alloca(len + 1);
-+ tmp[len] = 0;
-+ return memcpy(tmp, old, len);
-+}
-+#endif
-+
- /* Returns 0 on success and 1 on error */
- static int extract_timestamp(const char *b, au_event_t *e)
- {
-diff --git a/auparse/interpret.c b/auparse/interpret.c
-index 51c4a5e..67b7b77 100644
---- a/auparse/interpret.c
-+++ b/auparse/interpret.c
-@@ -853,6 +853,13 @@ err_out:
- return print_escaped(id->val);
- }
-
-+// rawmemchr is faster. Let's use it if we have it.
-+#ifdef HAVE_RAWMEMCHR
-+#define STRCHR rawmemchr
-+#else
-+#define STRCHR strchr
-+#endif
-+
- static const char *print_proctitle(const char *val)
- {
- char *out = (char *)print_escaped(val);
-@@ -863,7 +870,7 @@ static const char *print_proctitle(const char *val)
- // Proctitle has arguments separated by NUL bytes
- // We need to write over the NUL bytes with a space
- // so that we can see the arguments
-- while ((ptr = rawmemchr(ptr, '\0'))) {
-+ while ((ptr = STRCHR(ptr, '\0'))) {
- if (ptr >= end)
- break;
- *ptr = ' ';
-diff --git a/configure.ac b/configure.ac
-index 6e345f1..6f3007e 100644
---- a/configure.ac
-+++ b/configure.ac
-@@ -1,7 +1,7 @@
- dnl
- define([AC_INIT_NOTICE],
- [### Generated automatically using autoconf version] AC_ACVERSION [
--### Copyright 2005-18 Steve Grubb <sgrubb@redhat.com>
-+### Copyright 2005-19 Steve Grubb <sgrubb@redhat.com>
- ###
- ### Permission is hereby granted, free of charge, to any person obtaining a
- ### copy of this software and associated documentation files (the "Software"),
-@@ -72,6 +72,18 @@ dnl; posix_fallocate is used in audisp-remote
- AC_CHECK_FUNCS([posix_fallocate])
- dnl; signalfd is needed for libev
- AC_CHECK_FUNC([signalfd], [], [ AC_MSG_ERROR([The signalfd system call is necessary for auditd]) ])
-+dnl; check if rawmemchr is available
-+AC_CHECK_FUNCS([rawmemchr])
-+dnl; check if strndupa is available
-+AC_LINK_IFELSE(
-+ [AC_LANG_SOURCE(
-+ [[
-+ #define _GNU_SOURCE
-+ #include <string.h>
-+ int main() { (void) strndupa("test", 10); return 0; }]])],
-+ [AC_DEFINE(HAVE_STRNDUPA, 1, [Let us know if we have it or not])],
-+ []
-+)
-
- ALLWARNS=""
- ALLDEBUG="-g"
-diff --git a/src/ausearch-lol.c b/src/ausearch-lol.c
-index 5d17a72..758c33e 100644
---- a/src/ausearch-lol.c
-+++ b/src/ausearch-lol.c
-@@ -1,6 +1,6 @@
- /*
- * ausearch-lol.c - linked list of linked lists library
--* Copyright (c) 2008,2010,2014,2016 Red Hat Inc., Durham, North Carolina.
-+* Copyright (c) 2008,2010,2014,2016,2019 Red Hat Inc., Durham, North Carolina.
- * All Rights Reserved.
- *
- * This software may be freely redistributed and/or modified under the
-@@ -152,6 +152,16 @@ static int compare_event_time(event *e1, event *e2)
- return 0;
- }
-
-+#ifndef HAVE_STRNDUPA
-+static inline char *strndupa(const char *old, size_t n)
-+{
-+ size_t len = strnlen(old, n);
-+ char *tmp = alloca(len + 1);
-+ tmp[len] = 0;
-+ return memcpy(tmp, old, len);
-+}
-+#endif
-+
- /*
- * This function will look at the line and pick out pieces of it.
- */
---
-2.21.0
-
+++ /dev/null
-From 017e6c6ab95df55f34e339d2139def83e5dada1f Mon Sep 17 00:00:00 2001
-From: Steve Grubb <sgrubb@redhat.com>
-Date: Fri, 10 Jan 2020 21:13:50 -0500
-Subject: [PATCH 01/30] Header definitions need to be external when building
- with -fno-common (which is default in GCC 10) - Tony Jones
-
----
- src/ausearch-common.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/ausearch-common.h b/src/ausearch-common.h
-index 6669203..3040547 100644
---- a/src/ausearch-common.h
-+++ b/src/ausearch-common.h
-@@ -50,7 +50,7 @@ extern pid_t event_pid;
- extern int event_exact_match;
- extern uid_t event_uid, event_euid, event_loginuid;
- extern const char *event_tuid, *event_teuid, *event_tauid;
--slist *event_node_list;
-+extern slist *event_node_list;
- extern const char *event_comm;
- extern const char *event_filename;
- extern const char *event_hostname;
---
-2.26.2
-
#
-# Copyright (C) 2020-2023 Tony Ambardar <itugrok@yahoo.com>
+# Copyright (C) 2020-2024 Tony Ambardar <itugrok@yahoo.com>
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
include $(TOPDIR)/rules.mk
PKG_NAME:=libbpf
-PKG_VERSION:=1.3.0
+PKG_VERSION:=1.4.2
PKG_RELEASE:=1
PKG_SOURCE_URL:=https://github.com/libbpf/libbpf
-PKG_MIRROR_HASH:=669d8db696f86f640f86edc358bffa2af8dda656b8e787b095de3578bd8d94ff
+PKG_MIRROR_HASH:=eaf56a8d4297a1dfb477d91b4fb7c7c5ad6b6df73e0f7ac3c8fd93f2664c2e85
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_VERSION:=v1.3.0
+PKG_SOURCE_VERSION:=v1.4.2
PKG_ABI_VERSION:=$(firstword $(subst .,$(space),$(PKG_VERSION)))
PKG_MAINTAINER:=Tony Ambardar <itugrok@yahoo.com>
PKG_CPE_ID:=cpe:/a:libbpf_project:libbpf
-PKG_BUILD_FLAGS:=no-mips16
+PKG_BUILD_FLAGS:=no-mips16 no-gc-sections no-lto
PKG_BUILD_PARALLEL:=1
PKG_INSTALL:=1
libbpf is a library for loading eBPF programs and reading and manipulating eBPF objects from user-space.
endef
-MAKE_VARS = \
- EXTRA_CFLAGS="$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)" \
- LDFLAGS="$(TARGET_LDFLAGS)"
-
MAKE_FLAGS += \
$(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='') \
LIBSUBDIR=lib
+++ /dev/null
---- a/src/Makefile
-+++ b/src/Makefile
-@@ -34,6 +34,7 @@ ALL_CFLAGS := $(INCLUDES)
-
- SHARED_CFLAGS += -fPIC -fvisibility=hidden -DSHARED
-
-+CFLAGS = $(EXTRA_CFLAGS)
- CFLAGS ?= -g -O2 -Werror -Wall -std=gnu89
- ALL_CFLAGS += $(CFLAGS) \
- -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 \
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_LICENSE:=MIT
PKG_LICENSE_FILES:=COPYING
-PKG_CPE_ID:=cpe:/a:json-c_project:json-c
+PKG_CPE_ID:=cpe:/a:json-c:json-c
HOST_BUILD_PREFIX:=$(STAGING_DIR_HOST)
PKG_CPE_ID:=cpe:/a:selinuxproject:libsemanage
-HOST_BUILD_DEPENDS:=libaudit/host libselinux/host bzip2/host
+HOST_BUILD_DEPENDS:=audit/host libselinux/host bzip2/host
include $(INCLUDE_DIR)/package.mk
include $(TOPDIR)/rules.mk
PKG_NAME:=libunwind
-PKG_VERSION:=1.6.2
+PKG_VERSION:=1.8.1
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_URL:=@SAVANNAH/$(PKG_NAME)
-PKG_HASH:=4a6aec666991fb45d0889c44aede8ad6eb108071c3554fcdff671f9c94794976
+PKG_SOURCE_URL:=https://github.com/$(PKG_NAME)/$(PKG_NAME)/releases/download/v$(PKG_VERSION)/
+PKG_HASH:=ddf0e32dd5fafe5283198d37e4bf9decf7ba1770b6e7e006c33e6df79e6a6157
PKG_MAINTAINER:=Yousong Zhou <yszhou4tech@gmail.com>
PKG_LICENSE:=X11
CATEGORY:=Libraries
TITLE:=The libunwind project
URL:=http://www.nongnu.org/libunwind/
- DEPENDS:=@((mips||mipsel||mips64||powerpc64||x86_64||arm||aarch64)||(USE_GLIBC&&(powerpc||i386))) +zlib
+ DEPENDS:=@((mips||mipsel||mips64||powerpc64||x86_64||arm||aarch64||loongarch64)||(USE_GLIBC&&(powerpc||i386))) +zlib
ABI_VERSION:=8
endef
--- a/include/libunwind-mips.h
+++ b/include/libunwind-mips.h
-@@ -114,6 +114,42 @@ typedef enum
+@@ -121,6 +121,42 @@ typedef enum
}
mips_regnum_t;
--- a/include/libunwind-ppc32.h
+++ b/include/libunwind-ppc32.h
-@@ -74,6 +74,88 @@ typedef int64_t unw_sword_t;
+@@ -81,6 +81,88 @@ typedef int64_t unw_sword_t;
typedef long double unw_tdep_fpreg_t;
UNW_PPC32_R0,
--- a/include/libunwind-ppc64.h
+++ b/include/libunwind-ppc64.h
-@@ -81,6 +81,88 @@ typedef struct {
+@@ -88,6 +88,88 @@ typedef struct {
uint64_t halves[2];
} unw_tdep_vreg_t;
UNW_PPC64_R0,
--- a/src/ppc32/Ginit.c
+++ b/src/ppc32/Ginit.c
-@@ -46,14 +46,19 @@ static void *
+@@ -46,10 +46,15 @@ static void *
uc_addr (ucontext_t *uc, int reg)
{
void *addr;
+#endif
if ((unsigned) (reg - UNW_PPC32_R0) < 32)
+ #if defined(__linux__)
- addr = &uc->uc_mcontext.uc_regs->gregs[reg - UNW_PPC32_R0];
+ addr = &mc->gregs[reg - UNW_PPC32_R0];
-
- else
+ #elif defined(__FreeBSD__)
+ addr = &uc->uc_mcontext.mc_gpr[reg - UNW_PPC32_R0];
+ #endif
+@@ -58,7 +63,7 @@ uc_addr (ucontext_t *uc, int reg)
if ( ((unsigned) (reg - UNW_PPC32_F0) < 32) &&
((unsigned) (reg - UNW_PPC32_F0) >= 0) )
+ #if defined(__linux__)
- addr = &uc->uc_mcontext.uc_regs->fpregs.fpregs[reg - UNW_PPC32_F0];
+ addr = &mc->fpregs.fpregs[reg - UNW_PPC32_F0];
-
- else
- {
-@@ -76,7 +81,7 @@ uc_addr (ucontext_t *uc, int reg)
- default:
+ #elif defined(__FreeBSD__)
+ addr = &uc->uc_mcontext.mc_fpreg[reg - UNW_PPC32_F0];
+ #endif
+@@ -85,7 +90,7 @@ uc_addr (ucontext_t *uc, int reg)
return NULL;
}
+ #if defined(__linux__)
- addr = &uc->uc_mcontext.uc_regs->gregs[gregs_idx];
+ addr = &mc->gregs[gregs_idx];
- }
- return addr;
- }
+ #elif defined(__FreeBSD__)
+ addr = &uc->uc_mcontext.mc_gpr[gregs_idx];
+ #endif
--- a/src/ppc32/ucontext_i.h
+++ b/src/ppc32/ucontext_i.h
-@@ -46,83 +46,89 @@ WITH THE SOFTWARE OR THE USE OR OTHER DE
- various structure members. */
- static ucontext_t dmy_ctxt UNUSED;
+@@ -44,8 +44,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DE
+ //#define MQ_IDX 36
+ #define LINK_IDX 36
--#define UC_MCONTEXT_GREGS_R0 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[0] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R1 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[1] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R2 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[2] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R3 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[3] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R4 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[4] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R5 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[5] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R6 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[6] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R7 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[7] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R8 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[8] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R9 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[9] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R10 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[10] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R11 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[11] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R12 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[12] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R13 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[13] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R14 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[14] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R15 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[15] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R16 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[16] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R17 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[17] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R18 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[18] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R19 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[19] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R20 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[20] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R21 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[21] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R22 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[22] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R23 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[23] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R24 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[24] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R25 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[25] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R26 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[26] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R27 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[27] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R28 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[28] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R29 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[29] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R30 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[30] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R31 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[31] - (void *)&dmy_ctxt)
+#ifdef __GLIBC__
-+#define UC_MCONTEXT_OFFSET(field) ((void *)&dmy_ctxt.uc_mcontext.uc_regs->field - (void *)&dmy_ctxt)
+ #define _UC_MCONTEXT_GPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[x] - (void *)&dmy_ctxt) )
+ #define _UC_MCONTEXT_FPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[x] - (void *)&dmy_ctxt) )
+#else
-+#define UC_MCONTEXT_OFFSET(field) ((void *)&dmy_ctxt.uc_mcontext.field - (void *)&dmy_ctxt)
++#define _UC_MCONTEXT_GPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.gregs[x] - (void *)&dmy_ctxt) )
++#define _UC_MCONTEXT_FPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.fpregs.fpregs[x] - (void *)&dmy_ctxt) )
+#endif
-+
-+#define UC_MCONTEXT_GREGS_R0 UC_MCONTEXT_OFFSET(gregs[0])
-+#define UC_MCONTEXT_GREGS_R1 UC_MCONTEXT_OFFSET(gregs[1])
-+#define UC_MCONTEXT_GREGS_R2 UC_MCONTEXT_OFFSET(gregs[2])
-+#define UC_MCONTEXT_GREGS_R3 UC_MCONTEXT_OFFSET(gregs[3])
-+#define UC_MCONTEXT_GREGS_R4 UC_MCONTEXT_OFFSET(gregs[4])
-+#define UC_MCONTEXT_GREGS_R5 UC_MCONTEXT_OFFSET(gregs[5])
-+#define UC_MCONTEXT_GREGS_R6 UC_MCONTEXT_OFFSET(gregs[6])
-+#define UC_MCONTEXT_GREGS_R7 UC_MCONTEXT_OFFSET(gregs[7])
-+#define UC_MCONTEXT_GREGS_R8 UC_MCONTEXT_OFFSET(gregs[8])
-+#define UC_MCONTEXT_GREGS_R9 UC_MCONTEXT_OFFSET(gregs[9])
-+#define UC_MCONTEXT_GREGS_R10 UC_MCONTEXT_OFFSET(gregs[10])
-+#define UC_MCONTEXT_GREGS_R11 UC_MCONTEXT_OFFSET(gregs[11])
-+#define UC_MCONTEXT_GREGS_R12 UC_MCONTEXT_OFFSET(gregs[12])
-+#define UC_MCONTEXT_GREGS_R13 UC_MCONTEXT_OFFSET(gregs[13])
-+#define UC_MCONTEXT_GREGS_R14 UC_MCONTEXT_OFFSET(gregs[14])
-+#define UC_MCONTEXT_GREGS_R15 UC_MCONTEXT_OFFSET(gregs[15])
-+#define UC_MCONTEXT_GREGS_R16 UC_MCONTEXT_OFFSET(gregs[16])
-+#define UC_MCONTEXT_GREGS_R17 UC_MCONTEXT_OFFSET(gregs[17])
-+#define UC_MCONTEXT_GREGS_R18 UC_MCONTEXT_OFFSET(gregs[18])
-+#define UC_MCONTEXT_GREGS_R19 UC_MCONTEXT_OFFSET(gregs[19])
-+#define UC_MCONTEXT_GREGS_R20 UC_MCONTEXT_OFFSET(gregs[20])
-+#define UC_MCONTEXT_GREGS_R21 UC_MCONTEXT_OFFSET(gregs[21])
-+#define UC_MCONTEXT_GREGS_R22 UC_MCONTEXT_OFFSET(gregs[22])
-+#define UC_MCONTEXT_GREGS_R23 UC_MCONTEXT_OFFSET(gregs[23])
-+#define UC_MCONTEXT_GREGS_R24 UC_MCONTEXT_OFFSET(gregs[24])
-+#define UC_MCONTEXT_GREGS_R25 UC_MCONTEXT_OFFSET(gregs[25])
-+#define UC_MCONTEXT_GREGS_R26 UC_MCONTEXT_OFFSET(gregs[26])
-+#define UC_MCONTEXT_GREGS_R27 UC_MCONTEXT_OFFSET(gregs[27])
-+#define UC_MCONTEXT_GREGS_R28 UC_MCONTEXT_OFFSET(gregs[28])
-+#define UC_MCONTEXT_GREGS_R29 UC_MCONTEXT_OFFSET(gregs[29])
-+#define UC_MCONTEXT_GREGS_R30 UC_MCONTEXT_OFFSET(gregs[30])
-+#define UC_MCONTEXT_GREGS_R31 UC_MCONTEXT_OFFSET(gregs[31])
-
--#define UC_MCONTEXT_GREGS_MSR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[MSR_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_ORIG_GPR3 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[ORIG_GPR3_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_CTR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[CTR_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_LINK ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[LINK_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_XER ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[XER_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_CCR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[CCR_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_SOFTE ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[SOFTE_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_TRAP ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[TRAP_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_DAR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[DAR_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_DSISR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[DSISR_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_RESULT ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[RESULT_IDX] - (void *)&dmy_ctxt)
-+#define UC_MCONTEXT_GREGS_MSR UC_MCONTEXT_OFFSET(gregs[MSR_IDX])
-+#define UC_MCONTEXT_GREGS_ORIG_GPR3 UC_MCONTEXT_OFFSET(gregs[ORIG_GPR3_IDX])
-+#define UC_MCONTEXT_GREGS_CTR UC_MCONTEXT_OFFSET(gregs[CTR_IDX])
-+#define UC_MCONTEXT_GREGS_LINK UC_MCONTEXT_OFFSET(gregs[LINK_IDX])
-+#define UC_MCONTEXT_GREGS_XER UC_MCONTEXT_OFFSET(gregs[XER_IDX])
-+#define UC_MCONTEXT_GREGS_CCR UC_MCONTEXT_OFFSET(gregs[CCR_IDX])
-+#define UC_MCONTEXT_GREGS_SOFTE UC_MCONTEXT_OFFSET(gregs[SOFTE_IDX])
-+#define UC_MCONTEXT_GREGS_TRAP UC_MCONTEXT_OFFSET(gregs[TRAP_IDX])
-+#define UC_MCONTEXT_GREGS_DAR UC_MCONTEXT_OFFSET(gregs[DAR_IDX])
-+#define UC_MCONTEXT_GREGS_DSISR UC_MCONTEXT_OFFSET(gregs[DSISR_IDX])
-+#define UC_MCONTEXT_GREGS_RESULT UC_MCONTEXT_OFFSET(gregs[RESULT_IDX])
-
--#define UC_MCONTEXT_FREGS_R0 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[0] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R1 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[1] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R2 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[2] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R3 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[3] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R4 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[4] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R5 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[5] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R6 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[6] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R7 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[7] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R8 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[8] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R9 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[9] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R10 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[10] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R11 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[11] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R12 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[12] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R13 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[13] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R14 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[14] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R15 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[15] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R16 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[16] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R17 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[17] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R18 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[18] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R19 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[19] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R20 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[20] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R21 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[21] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R22 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[22] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R23 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[23] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R24 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[24] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R25 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[25] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R26 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[26] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R27 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[27] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R28 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[28] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R29 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[29] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R30 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[30] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R31 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[31] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_FPSCR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[32] - (void *)&dmy_ctxt)
-+#define UC_MCONTEXT_FREGS_R0 UC_MCONTEXT_OFFSET(fpregs.fpregs[0])
-+#define UC_MCONTEXT_FREGS_R1 UC_MCONTEXT_OFFSET(fpregs.fpregs[1])
-+#define UC_MCONTEXT_FREGS_R2 UC_MCONTEXT_OFFSET(fpregs.fpregs[2])
-+#define UC_MCONTEXT_FREGS_R3 UC_MCONTEXT_OFFSET(fpregs.fpregs[3])
-+#define UC_MCONTEXT_FREGS_R4 UC_MCONTEXT_OFFSET(fpregs.fpregs[4])
-+#define UC_MCONTEXT_FREGS_R5 UC_MCONTEXT_OFFSET(fpregs.fpregs[5])
-+#define UC_MCONTEXT_FREGS_R6 UC_MCONTEXT_OFFSET(fpregs.fpregs[6])
-+#define UC_MCONTEXT_FREGS_R7 UC_MCONTEXT_OFFSET(fpregs.fpregs[7])
-+#define UC_MCONTEXT_FREGS_R8 UC_MCONTEXT_OFFSET(fpregs.fpregs[8])
-+#define UC_MCONTEXT_FREGS_R9 UC_MCONTEXT_OFFSET(fpregs.fpregs[9])
-+#define UC_MCONTEXT_FREGS_R10 UC_MCONTEXT_OFFSET(fpregs.fpregs[10])
-+#define UC_MCONTEXT_FREGS_R11 UC_MCONTEXT_OFFSET(fpregs.fpregs[11])
-+#define UC_MCONTEXT_FREGS_R12 UC_MCONTEXT_OFFSET(fpregs.fpregs[12])
-+#define UC_MCONTEXT_FREGS_R13 UC_MCONTEXT_OFFSET(fpregs.fpregs[13])
-+#define UC_MCONTEXT_FREGS_R14 UC_MCONTEXT_OFFSET(fpregs.fpregs[14])
-+#define UC_MCONTEXT_FREGS_R15 UC_MCONTEXT_OFFSET(fpregs.fpregs[15])
-+#define UC_MCONTEXT_FREGS_R16 UC_MCONTEXT_OFFSET(fpregs.fpregs[16])
-+#define UC_MCONTEXT_FREGS_R17 UC_MCONTEXT_OFFSET(fpregs.fpregs[17])
-+#define UC_MCONTEXT_FREGS_R18 UC_MCONTEXT_OFFSET(fpregs.fpregs[18])
-+#define UC_MCONTEXT_FREGS_R19 UC_MCONTEXT_OFFSET(fpregs.fpregs[19])
-+#define UC_MCONTEXT_FREGS_R20 UC_MCONTEXT_OFFSET(fpregs.fpregs[20])
-+#define UC_MCONTEXT_FREGS_R21 UC_MCONTEXT_OFFSET(fpregs.fpregs[21])
-+#define UC_MCONTEXT_FREGS_R22 UC_MCONTEXT_OFFSET(fpregs.fpregs[22])
-+#define UC_MCONTEXT_FREGS_R23 UC_MCONTEXT_OFFSET(fpregs.fpregs[23])
-+#define UC_MCONTEXT_FREGS_R24 UC_MCONTEXT_OFFSET(fpregs.fpregs[24])
-+#define UC_MCONTEXT_FREGS_R25 UC_MCONTEXT_OFFSET(fpregs.fpregs[25])
-+#define UC_MCONTEXT_FREGS_R26 UC_MCONTEXT_OFFSET(fpregs.fpregs[26])
-+#define UC_MCONTEXT_FREGS_R27 UC_MCONTEXT_OFFSET(fpregs.fpregs[27])
-+#define UC_MCONTEXT_FREGS_R28 UC_MCONTEXT_OFFSET(fpregs.fpregs[28])
-+#define UC_MCONTEXT_FREGS_R29 UC_MCONTEXT_OFFSET(fpregs.fpregs[29])
-+#define UC_MCONTEXT_FREGS_R30 UC_MCONTEXT_OFFSET(fpregs.fpregs[30])
-+#define UC_MCONTEXT_FREGS_R31 UC_MCONTEXT_OFFSET(fpregs.fpregs[31])
-+#define UC_MCONTEXT_FREGS_FPSCR UC_MCONTEXT_OFFSET(fpregs.fpregs[32])
- #endif
+ /* These are dummy structures used only for obtaining the offsets of the
+ various structure members. */
--- /dev/null
+--- a/src/loongarch64/getcontext.S
++++ b/src/loongarch64/getcontext.S
+@@ -25,7 +25,9 @@ OF CONTRACT, TORT OR OTHERWISE, ARISING
+ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+ #include "offsets.h"
++#ifdef __GLIBC__
+ #include <endian.h>
++#endif
+ .text
+
+ #define SREG(X) st.d $r##X, $r4, (LINUX_UC_MCONTEXT_GREGS + 8 * X)
include $(TOPDIR)/rules.mk
PKG_NAME:=libxml2
-PKG_VERSION:=2.12.5
+PKG_VERSION:=2.12.6
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNOME/libxml2/$(basename $(PKG_VERSION))
-PKG_HASH:=a972796696afd38073e0f59c283c3a2f5a560b5268b4babc391b286166526b21
+PKG_HASH:=889c593a881a3db5fdd96cc9318c87df34eb648edfc458272ad46fd607353fbb
PKG_LICENSE:=MIT
PKG_LICENSE_FILES:=COPYING
bool "MBEDTLS_RIPEMD160_C"
default n
-config MBEDTLS_XTEA_C
- bool "MBEDTLS_XTEA_C"
- default n
-
config MBEDTLS_RSA_NO_CRT
bool "MBEDTLS_RSA_NO_CRT"
default y
comment "Build Options - unselect features to reduce binary size"
-config MBEDTLS_CERTS_C
- bool "MBEDTLS_CERTS_C"
- default n
-
config MBEDTLS_CIPHER_MODE_OFB
bool "MBEDTLS_CIPHER_MODE_OFB"
default n
bool "MBEDTLS_SELF_TEST"
default n
-config MBEDTLS_SSL_TRUNCATED_HMAC
- bool "MBEDTLS_SSL_TRUNCATED_HMAC"
- default n
-
config MBEDTLS_THREADING_C
bool "MBEDTLS_THREADING_C"
default y
bool "MBEDTLS_VERSION_FEATURES"
default n
+config MBEDTLS_PSA_CRYPTO_CLIENT
+ bool "MBEDTLS_PSA_CRYPTO_CLIENT"
+
+config MBEDTLS_DEPRECATED_WARNING
+ bool "MBEDTLS_DEPRECATED_WARNING"
+ default n
+
+config MBEDTLS_SSL_PROTO_TLS1_2
+ bool "MBEDTLS_SSL_PROTO_TLS1_2"
+ default y
+
+config MBEDTLS_SSL_PROTO_TLS1_3
+ bool "MBEDTLS_SSL_PROTO_TLS1_3"
+ select MBEDTLS_PSA_CRYPTO_CLIENT
+ select MBEDTLS_HKDF_C
+ default y
+
+config MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE
+ bool "MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE"
+ depends on MBEDTLS_SSL_PROTO_TLS1_3
+ default y
+
+config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED
+ bool "MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED"
+ depends on MBEDTLS_SSL_PROTO_TLS1_3
+ default y
+
+config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED
+ bool "MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED"
+ depends on MBEDTLS_SSL_PROTO_TLS1_3
+ default y
+
+config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED
+ bool "MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED"
+ depends on MBEDTLS_SSL_PROTO_TLS1_3
+ default y
+
comment "Build Options"
config MBEDTLS_ENTROPY_FORCE_SHA256
config MBEDTLS_SSL_RENEGOTIATION
bool "MBEDTLS_SSL_RENEGOTIATION"
+ depends on MBEDTLS_SSL_PROTO_TLS1_2
default n
endif
include $(TOPDIR)/rules.mk
PKG_NAME:=mbedtls
-PKG_VERSION:=2.28.7
-PKG_RELEASE:=2
+PKG_VERSION:=3.6.0
+PKG_RELEASE:=1
PKG_BUILD_FLAGS:=no-mips16 gc-sections no-lto
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_URL:=https://codeload.github.com/ARMmbed/mbedtls/tar.gz/v$(PKG_VERSION)?
-PKG_HASH:=1df6073f0cf6a4e1953890bf5e0de2a8c7e6be50d6d6c69fa9fefcb1d14e981a
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_URL=https://github.com/Mbed-TLS/mbedtls.git
+PKG_SOURCE_VERSION:=2ca6c285a0dd3f33982dd57299012dacab1ff206
+PKG_MIRROR_HASH:=a684012126590b4e0b6ab41e244cc2af0d2bcfc4b6c94bf42fc37d2d08f0553e
PKG_LICENSE:=GPL-2.0-or-later
PKG_LICENSE_FILES:=gpl-2.0.txt
CONFIG_MBEDTLS_NIST_KW_C \
CONFIG_MBEDTLS_RIPEMD160_C \
CONFIG_MBEDTLS_RSA_NO_CRT \
- CONFIG_MBEDTLS_XTEA_C
+ CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED \
+ CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED \
+ CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED
MBEDTLS_BUILD_OPTS= \
$(MBEDTLS_BUILD_OPTS_CURVES) \
$(MBEDTLS_BUILD_OPTS_CIPHERS) \
- CONFIG_MBEDTLS_CERTS_C \
CONFIG_MBEDTLS_CIPHER_MODE_OFB \
CONFIG_MBEDTLS_CIPHER_MODE_XTS \
CONFIG_MBEDTLS_DEBUG_C \
CONFIG_MBEDTLS_PLATFORM_C \
CONFIG_MBEDTLS_SELF_TEST \
CONFIG_MBEDTLS_SSL_RENEGOTIATION \
- CONFIG_MBEDTLS_SSL_TRUNCATED_HMAC \
CONFIG_MBEDTLS_THREADING_C \
CONFIG_MBEDTLS_THREADING_PTHREAD \
CONFIG_MBEDTLS_VERSION_C \
- CONFIG_MBEDTLS_VERSION_FEATURES
+ CONFIG_MBEDTLS_VERSION_FEATURES \
+ CONFIG_MBEDTLS_PSA_CRYPTO_CLIENT \
+ CONFIG_MBEDTLS_DEPRECATED_WARNING \
+ CONFIG_MBEDTLS_SSL_PROTO_TLS1_2 \
+ CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 \
+ CONFIG_MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE
PKG_CONFIG_DEPENDS := $(MBEDTLS_BUILD_OPTS)
CATEGORY:=Libraries
SUBMENU:=SSL
TITLE+= (library)
- ABI_VERSION:=13
+ ABI_VERSION:=21
MENU:=1
endef
$(if $(strip $(foreach opt,$(MBEDTLS_BUILD_OPTS),$($(opt)))),
$(foreach opt,$(MBEDTLS_BUILD_OPTS),
$(PKG_BUILD_DIR)/scripts/config.py \
- -f $(PKG_BUILD_DIR)/include/mbedtls/config.h \
+ -f $(PKG_BUILD_DIR)/include/mbedtls/mbedtls_config.h \
$(if $($(opt)),set,unset) $(patsubst CONFIG_%,%,$(opt))),)
endef
$(INSTALL_DIR) $(1)/usr/lib
$(CP) $(PKG_INSTALL_DIR)/usr/lib/lib*.so* $(1)/usr/lib/
$(CP) $(PKG_INSTALL_DIR)/usr/lib/lib*.a $(1)/usr/lib/
+ $(CP) $(PKG_INSTALL_DIR)/usr/lib/cmake $(1)/usr/lib/
+ $(INSTALL_DIR) $(1)/usr/lib/pkgconfig
+ $(CP) \
+ $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/mbedcrypto.pc \
+ $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/mbedtls.pc \
+ $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/mbedx509.pc \
+ $(1)/usr/lib/pkgconfig/
endef
define Package/libmbedtls/install
+++ /dev/null
-From eb9d4fdf1846e688d51d86a9a50f0312aca2af25 Mon Sep 17 00:00:00 2001
-From: Glenn Strauss <gstrauss@gluelogic.com>
-Date: Sun, 23 Oct 2022 19:48:18 -0400
-Subject: [PATCH] x509 crt verify SAN iPAddress
-
-Signed-off-by: Glenn Strauss <gstrauss@gluelogic.com>
----
- include/mbedtls/x509_crt.h | 2 +-
- library/x509_crt.c | 126 ++++++++++++++++++++++++++++++-------
- 2 files changed, 103 insertions(+), 25 deletions(-)
-
---- a/include/mbedtls/x509_crt.h
-+++ b/include/mbedtls/x509_crt.h
-@@ -608,7 +608,7 @@ int mbedtls_x509_crt_verify_info(char *b
- * \param cn The expected Common Name. This will be checked to be
- * present in the certificate's subjectAltNames extension or,
- * if this extension is absent, as a CN component in its
-- * Subject name. Currently only DNS names are supported. This
-+ * Subject name. DNS names and IP addresses are supported. This
- * may be \c NULL if the CN need not be verified.
- * \param flags The address at which to store the result of the verification.
- * If the verification couldn't be completed, the flag value is
---- a/library/x509_crt.c
-+++ b/library/x509_crt.c
-@@ -57,6 +57,10 @@
-
- #if defined(MBEDTLS_HAVE_TIME)
- #if defined(_WIN32) && !defined(EFIX64) && !defined(EFI32)
-+#define WIN32_LEAN_AND_MEAN
-+#ifndef _WIN32_WINNT
-+#define _WIN32_WINNT 0x0600
-+#endif
- #include <windows.h>
- #else
- #include <time.h>
-@@ -3002,6 +3006,61 @@ find_parent:
- }
- }
-
-+#ifdef _WIN32
-+#ifdef _MSC_VER
-+#pragma comment(lib, "ws2_32.lib")
-+#include <winsock2.h>
-+#include <ws2tcpip.h>
-+#elif (defined(__MINGW32__) || defined(__MINGW64__)) && _WIN32_WINNT >= 0x0600
-+#include <winsock2.h>
-+#include <ws2tcpip.h>
-+#endif
-+#elif defined(__sun)
-+/* Solaris requires -lsocket -lnsl for inet_pton() */
-+#elif defined(__has_include)
-+#if __has_include(<sys/socket.h>)
-+#include <sys/socket.h>
-+#endif
-+#if __has_include(<arpa/inet.h>)
-+#include <arpa/inet.h>
-+#endif
-+#endif
-+
-+/* Use whether or not AF_INET6 is defined to indicate whether or not to use
-+ * the platform inet_pton() or a local implementation (below). The local
-+ * implementation may be used even in cases where the platform provides
-+ * inet_pton(), e.g. when there are different includes required and/or the
-+ * platform implementation requires dependencies on additional libraries.
-+ * Specifically, Windows requires custom includes and additional link
-+ * dependencies, and Solaris requires additional link dependencies.
-+ * Also, as a coarse heuristic, use the local implementation if the compiler
-+ * does not support __has_include(), or if the definition of AF_INET6 is not
-+ * provided by headers included (or not) via __has_include() above. */
-+#ifndef AF_INET6
-+
-+#define x509_cn_inet_pton(cn, dst) (0)
-+
-+#else
-+
-+static int x509_inet_pton_ipv6(const char *src, void *dst)
-+{
-+ return inet_pton(AF_INET6, src, dst) == 1 ? 0 : -1;
-+}
-+
-+static int x509_inet_pton_ipv4(const char *src, void *dst)
-+{
-+ return inet_pton(AF_INET, src, dst) == 1 ? 0 : -1;
-+}
-+
-+#endif /* AF_INET6 */
-+
-+static size_t x509_cn_inet_pton(const char *cn, void *dst)
-+{
-+ return strchr(cn, ':') == NULL
-+ ? x509_inet_pton_ipv4(cn, dst) == 0 ? 4 : 0
-+ : x509_inet_pton_ipv6(cn, dst) == 0 ? 16 : 0;
-+}
-+
- /*
- * Check for CN match
- */
-@@ -3022,24 +3081,51 @@ static int x509_crt_check_cn(const mbedt
- return -1;
- }
-
-+static int x509_crt_check_san_ip(const mbedtls_x509_sequence *san,
-+ const char *cn, size_t cn_len)
-+{
-+ uint32_t ip[4];
-+ cn_len = x509_cn_inet_pton(cn, ip);
-+ if (cn_len == 0) {
-+ return -1;
-+ }
-+
-+ for (const mbedtls_x509_sequence *cur = san; cur != NULL; cur = cur->next) {
-+ const unsigned char san_type = (unsigned char) cur->buf.tag &
-+ MBEDTLS_ASN1_TAG_VALUE_MASK;
-+ if (san_type == MBEDTLS_X509_SAN_IP_ADDRESS &&
-+ cur->buf.len == cn_len && memcmp(cur->buf.p, ip, cn_len) == 0) {
-+ return 0;
-+ }
-+ }
-+
-+ return -1;
-+}
-+
- /*
- * Check for SAN match, see RFC 5280 Section 4.2.1.6
- */
--static int x509_crt_check_san(const mbedtls_x509_buf *name,
-+static int x509_crt_check_san(const mbedtls_x509_sequence *san,
- const char *cn, size_t cn_len)
- {
-- const unsigned char san_type = (unsigned char) name->tag &
-- MBEDTLS_ASN1_TAG_VALUE_MASK;
--
-- /* dNSName */
-- if (san_type == MBEDTLS_X509_SAN_DNS_NAME) {
-- return x509_crt_check_cn(name, cn, cn_len);
-+ int san_ip = 0;
-+ for (const mbedtls_x509_sequence *cur = san; cur != NULL; cur = cur->next) {
-+ switch ((unsigned char) cur->buf.tag & MBEDTLS_ASN1_TAG_VALUE_MASK) {
-+ case MBEDTLS_X509_SAN_DNS_NAME: /* dNSName */
-+ if (x509_crt_check_cn(&cur->buf, cn, cn_len) == 0) {
-+ return 0;
-+ }
-+ break;
-+ case MBEDTLS_X509_SAN_IP_ADDRESS: /* iPAddress */
-+ san_ip = 1;
-+ break;
-+ /* (We may handle other types here later.) */
-+ default: /* Unrecognized type */
-+ break;
-+ }
- }
-
-- /* (We may handle other types here later.) */
--
-- /* Unrecognized type */
-- return -1;
-+ return san_ip ? x509_crt_check_san_ip(san, cn, cn_len) : -1;
- }
-
- /*
-@@ -3050,31 +3136,23 @@ static void x509_crt_verify_name(const m
- uint32_t *flags)
- {
- const mbedtls_x509_name *name;
-- const mbedtls_x509_sequence *cur;
- size_t cn_len = strlen(cn);
-
- if (crt->ext_types & MBEDTLS_X509_EXT_SUBJECT_ALT_NAME) {
-- for (cur = &crt->subject_alt_names; cur != NULL; cur = cur->next) {
-- if (x509_crt_check_san(&cur->buf, cn, cn_len) == 0) {
-- break;
-- }
-- }
--
-- if (cur == NULL) {
-- *flags |= MBEDTLS_X509_BADCERT_CN_MISMATCH;
-+ if (x509_crt_check_san(&crt->subject_alt_names, cn, cn_len) == 0) {
-+ return;
- }
- } else {
- for (name = &crt->subject; name != NULL; name = name->next) {
- if (MBEDTLS_OID_CMP(MBEDTLS_OID_AT_CN, &name->oid) == 0 &&
- x509_crt_check_cn(&name->val, cn, cn_len) == 0) {
-- break;
-+ return;
- }
- }
-
-- if (name == NULL) {
-- *flags |= MBEDTLS_X509_BADCERT_CN_MISMATCH;
-- }
- }
-+
-+ *flags |= MBEDTLS_X509_BADCERT_CN_MISMATCH;
- }
-
- /*
--- a/programs/CMakeLists.txt
+++ b/programs/CMakeLists.txt
-@@ -1,12 +1,8 @@
+@@ -1,13 +1,9 @@
add_subdirectory(aes)
+ add_subdirectory(cipher)
-if (NOT WIN32)
- add_subdirectory(fuzz)
-endif()
--- /dev/null
+++ b/Configurations/25-openwrt.conf
-@@ -0,0 +1,56 @@
+@@ -0,0 +1,59 @@
+## Openwrt "CONFIG_ARCH" matching targets.
+
+# The targets need to end in '-openwrt' for the AFALG patch to work
+ "linux-i386-openwrt" => {
+ inherit_from => [ "linux-x86", "openwrt" ],
+ },
++ "linux-loongarch64-openwrt" => {
++ inherit_from => [ "linux64-loongarch64", "openwrt" ],
++ },
+ "linux-mips-openwrt" => {
+ inherit_from => [ "linux-mips32", "openwrt" ],
+ },
PKG_MAINTAINER:=Shane Peelar <lookatyouhacker@gmail.com>
PKG_LICENSE:=BSD-3-Clause
PKG_LICENSE_FILES:=LICENCE
-PKG_CPE_ID:=cpe:/a:pcre:pcre
+PKG_CPE_ID:=cpe:/a:pcre:pcre2
PKG_CONFIG_DEPENDS:=\
CONFIG_PACKAGE_libpcre2-16 \
$(call Package/gcc/Default)
NAME:=libtsan
TITLE:=Runtime library for ThreadSanitizer in GCC
- DEPENDS:=@USE_GLIBC +librt +libstdcpp @!mips @!mipsel @!mips64 @!mips64el @!arc
+ DEPENDS:=@USE_GLIBC +librt +libstdcpp @!loongarch64 @!mips @!mipsel @!mips64 @!mips64el @!arc
ABI_VERSION:=0
endef
$(call Package/gcc/Default)
NAME:=liblsan
TITLE:=Runtime library for LeakSanitizer in GCC
- DEPENDS:=@USE_GLIBC +librt +libstdcpp @!mips @!mipsel @!mips64 @!mips64el @!arc
+ DEPENDS:=@USE_GLIBC +librt +libstdcpp @!loongarch64 @!mips @!mipsel @!mips64 @!mips64el @!arc
ABI_VERSION:=0
endef
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/uclient.git
-PKG_MIRROR_HASH:=21c95854c60757007edacc579ce874999d2d536f682b0e636a8d19bc75e70da5
-PKG_SOURCE_DATE:=2024-04-05
-PKG_SOURCE_VERSION:=6c16331e4bf542fbb538d62a6b5bf3d286ecbf2c
+PKG_MIRROR_HASH:=0a0ea0752d534db87f2a13342d1b1b33fb94e43b934bdd015f96f19c635aa08c
+PKG_SOURCE_DATE:=2024-04-19
+PKG_SOURCE_VERSION:=e8780fa7792aaa2d68af21c0df91cd9c05e1f73a
CMAKE_INSTALL:=1
PKG_BUILD_DEPENDS:=ustream-ssl
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/ustream-ssl.git
-PKG_SOURCE_DATE:=2024-04-07
-PKG_SOURCE_VERSION:=d61493a4420417cbf9931ffee8c862faf04f2967
-PKG_MIRROR_HASH:=a420d775ad4928836e33e0d9423486fe4904555dbbfff283cd96370a49cf9659
+PKG_SOURCE_DATE:=2024-04-19
+PKG_SOURCE_VERSION:=524a76e5af78fa577c46e0d24bdedd4254e07cd4
+PKG_MIRROR_HASH:=638a3143013c7b60faa0e92f466a4245c635b72a7a61baa84dc9fca000991999
CMAKE_INSTALL:=1
PKG_LICENSE:=ISC
include $(TOPDIR)/rules.mk
PKG_NAME:=wolfssl
-PKG_VERSION:=5.6.6-stable
+PKG_VERSION:=5.7.0-stable
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/wolfSSL/wolfssl/archive/v$(PKG_VERSION)
-PKG_HASH:=3d2ca672d41c2c2fa667885a80d6fa03c3e91f0f4f72f87aef2bc947e8c87237
+PKG_HASH:=2de93e8af588ee856fe67a6d7fce23fc1b226b74d710b0e3946bc8061f6aa18f
PKG_FIXUP:=libtool libtool-abiver
PKG_INSTALL:=1
--- a/wolfssl/wolfcrypt/settings.h
+++ b/wolfssl/wolfcrypt/settings.h
-@@ -2774,7 +2774,7 @@ extern void uITRON4_free(void *p) ;
+@@ -2945,7 +2945,7 @@ extern void uITRON4_free(void *p) ;
/* warning for not using harden build options (default with ./configure) */
/* do not warn if big integer support is disabled */
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/firewall4.git
-PKG_SOURCE_DATE:=2023-11-03
-PKG_SOURCE_VERSION:=698a53354fd280aae097efe08803c0c9a10c14c2
-PKG_MIRROR_HASH:=736b3d03cf0db1170242de20776b0095cc37d260108e4313f84eafb46b1be711
+PKG_SOURCE_DATE:=2024-05-21
+PKG_SOURCE_VERSION:=4c01d1ebf99e8ecfa69758a9b4f450ecef7b93cd
+PKG_MIRROR_HASH:=bbc5622bc03e3b43116fcc86e3fa2d2372bfc07b3a00d2b3a6efac4f7454a403
PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
PKG_LICENSE:=ISC
define Package/netifd
SECTION:=base
CATEGORY:=Base system
- DEPENDS:=+libuci +libnl-tiny +libubus +ubus +ubusd +jshn +libubox +libudebug
+ DEPENDS:=+libuci +libnl-tiny +libubus +ubus +ubusd +jshn +libubox +libudebug +ucode +ucode-mod-fs
TITLE:=OpenWrt Network Interface Configuration Daemon
endef
}
reload_service() {
- /usr/libexec/network/packet-steering.sh
+ packet_steering="$(uci -q get "network.@globals[0].packet_steering")"
+ steering_flows="$(uci -q get "network.@globals[0].steering_flows")"
+ [ "${steering_flows:-0}" -gt 0 ] && opts="-l $steering_flows"
+ if [ -e "/usr/libexec/platform/packet-steering.sh" ]; then
+ /usr/libexec/platform/packet-steering.sh "$packet_steering"
+ else
+ /usr/libexec/network/packet-steering.uc $opts "$packet_steering"
+ fi
}
+++ /dev/null
-#!/bin/sh
-NPROCS="$(grep -c "^processor.*:" /proc/cpuinfo)"
-[ "$NPROCS" -gt 1 ] || exit
-
-PROC_MASK="$(( (1 << $NPROCS) - 1 ))"
-
-find_irq_cpu() {
- local dev="$1"
- local match="$(grep -m 1 "$dev\$" /proc/interrupts)"
- local cpu=0
-
- [ -n "$match" ] && {
- set -- $match
- shift
- for cur in $(seq 1 $NPROCS); do
- [ "$1" -gt 0 ] && {
- cpu=$(($cur - 1))
- break
- }
- shift
- done
- }
-
- echo "$cpu"
-}
-
-set_hex_val() {
- local file="$1"
- local val="$2"
- val="$(printf %x "$val")"
- [ -n "$DEBUG" ] && echo "$file = $val"
- echo "$val" > "$file"
-}
-
-packet_steering="$(uci get "network.@globals[0].packet_steering")"
-[ "$packet_steering" != 1 ] && exit 0
-
-exec 512>/var/lock/smp_tune.lock
-flock 512 || exit 1
-
-[ -e "/usr/libexec/platform/packet-steering.sh" ] && {
- /usr/libexec/platform/packet-steering.sh
- exit 0
-}
-
-for dev in /sys/class/net/*; do
- [ -d "$dev" ] || continue
-
- # ignore virtual interfaces
- [ -n "$(ls "${dev}/" | grep '^lower_')" ] && continue
- [ -d "${dev}/device" ] || continue
-
- device="$(readlink "${dev}/device")"
- device="$(basename "$device")"
- irq_cpu="$(find_irq_cpu "$device")"
- irq_cpu_mask="$((1 << $irq_cpu))"
-
- for q in ${dev}/queues/tx-*; do
- set_hex_val "$q/xps_cpus" "$PROC_MASK"
- done
-
- # ignore dsa slave ports for RPS
- subsys="$(readlink "${dev}/device/subsystem")"
- subsys="$(basename "$subsys")"
- [ "$subsys" = "mdio_bus" ] && continue
-
- for q in ${dev}/queues/rx-*; do
- set_hex_val "$q/rps_cpus" "$PROC_MASK"
- done
-done
--- /dev/null
+#!/usr/bin/env ucode
+'use strict';
+import { glob, basename, dirname, readlink, readfile, realpath, writefile, error, open } from "fs";
+
+let napi_weight = 1.0;
+let cpu_thread_weight = 0.75;
+let rx_weight = 0.75;
+let eth_bias = 2.0;
+let debug = 0, do_nothing = 0;
+let disable;
+let cpus;
+let all_cpus;
+let local_flows = 0;
+
+while (length(ARGV) > 0) {
+ let arg = shift(ARGV);
+ switch (arg) {
+ case "-d":
+ debug++;
+ break;
+ case "-n":
+ do_nothing++;
+ break;
+ case '0':
+ disable = true;
+ break;
+ case '2':
+ all_cpus = true;
+ break;
+ case '-l':
+ local_flows = +shift(ARGV);
+ break;
+ }
+}
+
+function task_name(pid)
+{
+ let stat = open(`/proc/${pid}/status`, "r");
+ if (!stat)
+ return;
+ let line = stat.read("line");
+ stat.close();
+ return trim(split(line, "\t", 2)[1]);
+}
+
+function set_task_cpu(pid, cpu) {
+ if (disable)
+ cpu = join(",", map(cpus, (cpu) => cpu.id));
+ let name = task_name(pid);
+ if (!name)
+ return;
+ if (debug || do_nothing)
+ warn(`taskset -p -c ${cpu} ${name}\n`);
+ if (!do_nothing)
+ system(`taskset -p -c ${cpu} ${pid}`);
+}
+
+function cpu_mask(cpu)
+{
+ let mask;
+ if (cpu < 0)
+ mask = (1 << length(cpus)) - 1;
+ else
+ mask = (1 << int(cpu));
+ return sprintf("%x", mask);
+}
+
+function set_netdev_cpu(dev, cpu) {
+ let queues = glob(`/sys/class/net/${dev}/queues/rx-*/rps_cpus`);
+ let val = cpu_mask(cpu);
+ if (disable)
+ val = 0;
+ for (let queue in queues) {
+ if (debug || do_nothing)
+ warn(`echo ${val} > ${queue}\n`);
+ if (!do_nothing)
+ writefile(queue, `${val}`);
+ }
+ queues = glob(`/sys/class/net/${dev}/queues/rx-*/rps_flow_cnt`);
+ for (let queue in queues) {
+ if (debug || do_nothing)
+ warn(`echo ${local_flows} > ${queue}\n`);
+ if (!do_nothing)
+ writefile(queue, `${local_flows}`);
+ }
+}
+
+function task_device_match(name, device)
+{
+ let napi_match = match(name, /napi\/([^-+])-\d+/);
+ if (!napi_match)
+ napi_match = match(name, /mt76-tx (phy\d+)/);
+ if (napi_match &&
+ (index(device.phy, napi_match[1]) >= 0 ||
+ index(device.netdev, napi_match[1]) >= 0))
+ return true;
+
+ if (device.driver == "mtk_soc_eth" && match(name, /napi\/mtk_eth-/))
+ return true;
+
+ return false;
+}
+
+cpus = map(glob("/sys/bus/cpu/devices/*"), (path) => {
+ return {
+ id: int(match(path, /.*cpu(\d+)/)[1]),
+ core: int(trim(readfile(`${path}/topology/core_id`))),
+ load: 0.0,
+ };
+});
+
+cpus = slice(cpus, 0, 64);
+if (length(cpus) < 2)
+ exit(0);
+
+function cpu_add_weight(cpu_id, weight)
+{
+ let cpu = cpus[cpu_id];
+ cpu.load += weight;
+ for (let sibling in cpus) {
+ if (sibling == cpu || sibling.core != cpu.core)
+ continue;
+ sibling.load += weight * cpu_thread_weight;
+ }
+}
+
+function get_next_cpu(weight, prev_cpu)
+{
+ if (disable)
+ return 0;
+
+ let sort_cpus = sort(slice(cpus), (a, b) => a.load - b.load);
+ let idx = 0;
+
+ if (prev_cpu != null && sort_cpus[idx].id == prev_cpu)
+ idx++;
+
+ let cpu = sort_cpus[idx].id;
+ cpu_add_weight(cpu, weight);
+ return cpu;
+}
+
+let phys_devs = {};
+let netdev_phys = {};
+let netdevs = map(glob("/sys/class/net/*"), (dev) => basename(dev));
+
+for (let dev in netdevs) {
+ let pdev_path = realpath(`/sys/class/net/${dev}/device`);
+ if (!pdev_path)
+ continue;
+
+ if (length(glob(`/sys/class/net/${dev}/lower_*`)) > 0)
+ continue;
+
+ let pdev = phys_devs[pdev_path];
+ if (!pdev) {
+ pdev = phys_devs[pdev_path] = {
+ path: pdev_path,
+ driver: basename(readlink(`${pdev_path}/driver`)),
+ netdev: [],
+ phy: [],
+ tasks: [],
+ };
+ }
+
+ let phyidx = trim(readfile(`/sys/class/net/${dev}/phy80211/index`));
+ if (phyidx != null) {
+ let phy = `phy${phyidx}`;
+ if (index(pdev.phy, phy) < 0)
+ push(pdev.phy, phy);
+ }
+
+ push(pdev.netdev, dev);
+ netdev_phys[dev] = pdev;
+}
+
+for (let path in glob("/proc/*/exe")) {
+ readlink(path);
+ if (error() != "No such file or directory")
+ continue;
+
+ let pid = basename(dirname(path));
+ let name = task_name(pid);
+ for (let devname in phys_devs) {
+ let dev = phys_devs[devname];
+ if (!task_device_match(name, dev))
+ continue;
+
+ push(dev.tasks, pid);
+ break;
+ }
+}
+
+function assign_dev_cpu(dev) {
+ if (length(dev.tasks) > 0) {
+ let cpu = dev.napi_cpu = get_next_cpu(napi_weight);
+ for (let task in dev.tasks)
+ set_task_cpu(task, cpu);
+ }
+
+ if (length(dev.netdev) > 0) {
+ let cpu;
+ if (all_cpus)
+ cpu = -1;
+ else
+ cpu = get_next_cpu(rx_weight, dev.napi_cpu);
+ dev.rx_cpu = cpu;
+ for (let netdev in dev.netdev)
+ set_netdev_cpu(netdev, cpu);
+ }
+}
+
+// Assign ethernet devices first
+for (let devname in phys_devs) {
+ let dev = phys_devs[devname];
+ if (!length(dev.phy))
+ assign_dev_cpu(dev);
+}
+
+// Add bias to avoid assigning other tasks to CPUs with ethernet NAPI
+for (let devname in phys_devs) {
+ let dev = phys_devs[devname];
+ if (!length(dev.tasks) || dev.napi_cpu == null)
+ continue;
+ cpu_add_weight(dev.napi_cpu, eth_bias);
+}
+
+// Assign WLAN devices
+for (let devname in phys_devs) {
+ let dev = phys_devs[devname];
+ if (length(dev.phy) > 0)
+ assign_dev_cpu(dev);
+}
+
+if (debug > 1)
+ warn(sprintf("devices: %.J\ncpus: %.J\n", phys_devs, cpus));
PKG_NAME:=bridger
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/nbd168/bridger
-PKG_SOURCE_DATE:=2023-05-12
-PKG_SOURCE_VERSION:=d0f79a16c749ad310d79e1c31f593860619f99eb
-PKG_MIRROR_HASH:=dde6613662ad53ba6622e669400560a534426edfa4f42c91d156fbd7ccafd15c
+PKG_SOURCE_DATE:=2024-04-22
+PKG_SOURCE_VERSION:=40b1c5b6be4e73a6749cf2997c664520eb20055d
+PKG_MIRROR_HASH:=b3ba2ab5ffa1af55f8da2cae5a90df486474b97ed4c359ec40c986aa6e82c300
PKG_LICENSE:=GPL-2.0
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
config defaults
+ # handle bridge local rx/tx
+ option bridge_local_tx 1
+ option bridge_local_rx 0
+
# example for blacklisting individual devices or bridges
# list blacklist eth0
USE_PROCD=1
PROG=/usr/sbin/bridger
-add_blacklist() {
+get_defaults() {
cfg="$1"
config_get blacklist "$cfg" blacklist
+ json_add_array blacklist
for i in $blacklist; do
json_add_string "" "$i"
done
+ json_close_array
+
+ config_get_bool bridge_local_tx "$cfg" bridge_local_tx 1
+ json_add_boolean bridge_local_tx "$bridge_local_tx"
+
+ config_get_bool bridge_local_rx "$cfg" bridge_local_rx 0
+ json_add_boolean bridge_local_rx "$bridge_local_rx"
}
reload_service() {
config_load bridger
json_init
- json_add_string name "config"
- json_add_array devices
- config_foreach add_blacklist defaults
- json_close_array
+ config_foreach get_defaults defaults
- ubus call bridger set_blacklist "$(json_dump)"
+ ubus call bridger set_config "$(json_dump)"
}
service_triggers() {
and disables:
- AES
- RSA
- - SHA1
Reduces binary size by about 64 kB (MIPS) from default
configuration.
include $(TOPDIR)/rules.mk
PKG_NAME:=dropbear
-PKG_VERSION:=2022.83
+PKG_VERSION:=2024.85
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:= \
https://matt.ucc.asn.au/dropbear/releases/ \
https://dropbear.nl/mirror/releases/
-PKG_HASH:=bc5a121ffbc94b5171ad5ebe01be42746d50aa797c9549a4639894a16749443b
+PKG_HASH:=86b036c433a69d89ce51ebae335d65c47738ccf90d13e5eb0fea832e556da502
PKG_LICENSE:=MIT
PKG_LICENSE_FILES:=LICENSE libtomcrypt/LICENSE libtommath/LICENSE
-PKG_CPE_ID:=cpe:/a:matt_johnston:dropbear_ssh_server
+PKG_CPE_ID:=cpe:/a:dropbear_ssh_project:dropbear_ssh
PKG_BUILD_PARALLEL:=1
PKG_ASLR_PIE_REGULAR:=1
CATEGORY:=Base system
TITLE:=Small SSH2 client/server
DEPENDS:= +DROPBEAR_ZLIB:zlib
- ALTERNATIVES:=
+ ALTERNATIVES:=100:/usr/bin/ssh-keygen:/usr/sbin/dropbear
$(if $(CONFIG_DROPBEAR_SCP),ALTERNATIVES+= \
100:/usr/bin/scp:/usr/sbin/dropbear,)
$(if $(CONFIG_DROPBEAR_DBCLIENT),ALTERNATIVES+= \
##############################################################################
#
# option,value - add option to localoptions.h
-# !!option,value - replace option in sysoptions.h
+# !!option,value - replace option in src/sysoptions.h
#
##############################################################################
##############################################################################
#
# option,config,enabled,disabled = add option to localoptions.h
-# !!option,config,enabled,disabled = replace option in sysoptions.h
+# !!option,config,enabled,disabled = replace option in src/sysoptions.h
#
# option := (config) ? enabled : disabled
#
xsedx:=$(shell printf '\027')
db_opt_add =echo '\#define $(1) $(2)' >> $(PKG_BUILD_DIR)/localoptions.h
-db_opt_replace =$(ESED) '/^\#define $(1) .*$$$$/{h;:a;$$$$!n;/^\#.+$$$$/bb;/^$$$$/bb;H;ba;:b;x;s$(xsedx)^.+$$$$$(xsedx)\#define $(1) $(2)$(xsedx)p;x};p' -n $(PKG_BUILD_DIR)/sysoptions.h
+db_opt_replace =$(ESED) '/^\#define $(1) .*$$$$/{h;:a;$$$$!n;/^\#.+$$$$/bb;/^$$$$/bb;H;ba;:b;x;s$(xsedx)^.+$$$$$(xsedx)\#define $(1) $(2)$(xsedx)p;x};p' -n $(PKG_BUILD_DIR)/src/sysoptions.h
define Build/Configure/dropbear_headers
$(strip $(foreach s,$(DB_OPT_COMMON), \
esac
local c=0
- # sysoptions.h
+ # src/sysoptions.h
local DROPBEAR_MAX_PORTS=10
local a n if_ipaddrs
# ref: validate_section_dropbear()
# default receive window size is 24576 (DEFAULT_RECV_WINDOW in default_options.h)
- # sysoptions.h
+ # src/sysoptions.h
local MAX_RECV_WINDOW=10485760
if [ "${RecvWindowSize}" -gt ${MAX_RECV_WINDOW} ] ; then
# separate logging is required because syslog misses dropbear's message
+++ /dev/null
-From 36a03132634a17c667c0fac0a8e1519b3d1b71c6 Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Mon, 28 Nov 2022 21:12:23 +0800
-Subject: Add #if DROPBEAR_RSA guards
-
-Fixes building with DROPBEAR_RSA disabled.
-Closes #197
----
- signkey.c | 8 +++++++-
- signkey.h | 2 ++
- sysoptions.h | 5 +----
- 3 files changed, 10 insertions(+), 5 deletions(-)
-
---- a/signkey.c
-+++ b/signkey.c
-@@ -120,6 +120,7 @@ enum signkey_type signkey_type_from_name
- /* Special case for rsa-sha2-256. This could be generalised if more
- signature names are added that aren't 1-1 with public key names */
- const char* signature_name_from_type(enum signature_type type, unsigned int *namelen) {
-+#if DROPBEAR_RSA
- #if DROPBEAR_RSA_SHA256
- if (type == DROPBEAR_SIGNATURE_RSA_SHA256) {
- if (namelen) {
-@@ -136,11 +137,13 @@ const char* signature_name_from_type(enu
- return SSH_SIGNKEY_RSA;
- }
- #endif
-+#endif /* DROPBEAR_RSA */
- return signkey_name_from_type((enum signkey_type)type, namelen);
- }
-
- /* Returns DROPBEAR_SIGNATURE_NONE if none match */
- enum signature_type signature_type_from_name(const char* name, unsigned int namelen) {
-+#if DROPBEAR_RSA
- #if DROPBEAR_RSA_SHA256
- if (namelen == strlen(SSH_SIGNATURE_RSA_SHA256)
- && memcmp(name, SSH_SIGNATURE_RSA_SHA256, namelen) == 0) {
-@@ -153,10 +156,11 @@ enum signature_type signature_type_from_
- return DROPBEAR_SIGNATURE_RSA_SHA1;
- }
- #endif
-+#endif /* DROPBEAR_RSA */
- return (enum signature_type)signkey_type_from_name(name, namelen);
- }
-
--/* Returns the signature type from a key type. Must not be called
-+/* Returns the signature type from a key type. Must not be called
- with RSA keytype */
- enum signature_type signature_type_from_signkey(enum signkey_type keytype) {
- #if DROPBEAR_RSA
-@@ -167,6 +171,7 @@ enum signature_type signature_type_from_
- }
-
- enum signkey_type signkey_type_from_signature(enum signature_type sigtype) {
-+#if DROPBEAR_RSA
- #if DROPBEAR_RSA_SHA256
- if (sigtype == DROPBEAR_SIGNATURE_RSA_SHA256) {
- return DROPBEAR_SIGNKEY_RSA;
-@@ -177,6 +182,7 @@ enum signkey_type signkey_type_from_sign
- return DROPBEAR_SIGNKEY_RSA;
- }
- #endif
-+#endif /* DROPBEAR_RSA */
- assert((int)sigtype < (int)DROPBEAR_SIGNKEY_NUM_NAMED);
- return (enum signkey_type)sigtype;
- }
---- a/signkey.h
-+++ b/signkey.h
-@@ -79,12 +79,14 @@ enum signature_type {
- DROPBEAR_SIGNATURE_SK_ED25519 = DROPBEAR_SIGNKEY_SK_ED25519,
- #endif
- #endif
-+#if DROPBEAR_RSA
- #if DROPBEAR_RSA_SHA1
- DROPBEAR_SIGNATURE_RSA_SHA1 = 100, /* ssh-rsa signature (sha1) */
- #endif
- #if DROPBEAR_RSA_SHA256
- DROPBEAR_SIGNATURE_RSA_SHA256 = 101, /* rsa-sha2-256 signature. has a ssh-rsa key */
- #endif
-+#endif /* DROPBEAR_RSA */
- DROPBEAR_SIGNATURE_NONE = DROPBEAR_SIGNKEY_NONE,
- };
-
---- a/sysoptions.h
-+++ b/sysoptions.h
-@@ -137,7 +137,7 @@
-
- /* Debian doesn't define this in system headers */
- #if !defined(LTM_DESC) && (DROPBEAR_ECC)
--#define LTM_DESC
-+#define LTM_DESC
- #endif
-
- #define DROPBEAR_ECC_256 (DROPBEAR_ECC)
-@@ -151,9 +151,6 @@
- * signing operations slightly slower. */
- #define DROPBEAR_RSA_BLINDING 1
-
--#ifndef DROPBEAR_RSA_SHA1
--#define DROPBEAR_RSA_SHA1 DROPBEAR_RSA
--#endif
- #ifndef DROPBEAR_RSA_SHA256
- #define DROPBEAR_RSA_SHA256 DROPBEAR_RSA
- #endif
+++ /dev/null
-From ec2215726cffb976019d08ebf569edd2229e9dba Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Thu, 1 Dec 2022 11:34:43 +0800
-Subject: Fix y2038 issues with time_t conversion
-
-These changes were identified by building with and without
--D_TIME_BITS=64 -D_FILE_OFFSET_BITS=64
-on 32-bit arm, logging warnings to files.
--Wconversion was added to CFLAGS in both builds.
-
-Then a "diff -I Wconversion log1 log2" shows new warnings that appear
-with the 64-bit time_t. There are a few false positives that have been
-fixed for quietness.
-
-struct logininfo and struct wtmp are still problematic, those will
-need to be handled by libc.
----
- common-session.c | 43 +++++++++++++++++++++++++++----------------
- dbutil.c | 2 +-
- loginrec.c | 2 ++
- loginrec.h | 4 ++--
- runopts.h | 4 ++--
- svr-auth.c | 2 +-
- 6 files changed, 35 insertions(+), 22 deletions(-)
-
---- a/common-session.c
-+++ b/common-session.c
-@@ -519,15 +519,24 @@ static void send_msg_keepalive() {
- ses.last_packet_time_idle = old_time_idle;
- }
-
-+/* Returns the difference in seconds, clamped to LONG_MAX */
-+static long elapsed(time_t now, time_t prev) {
-+ time_t del = now - prev;
-+ if (del > LONG_MAX) {
-+ return LONG_MAX;
-+ }
-+ return (long)del;
-+}
-+
- /* Check all timeouts which are required. Currently these are the time for
- * user authentication, and the automatic rekeying. */
- static void checktimeouts() {
-
- time_t now;
- now = monotonic_now();
--
-+
- if (IS_DROPBEAR_SERVER && ses.connect_time != 0
-- && now - ses.connect_time >= AUTH_TIMEOUT) {
-+ && elapsed(now, ses.connect_time) >= AUTH_TIMEOUT) {
- dropbear_close("Timeout before auth");
- }
-
-@@ -537,45 +546,47 @@ static void checktimeouts() {
- }
-
- if (!ses.kexstate.sentkexinit
-- && (now - ses.kexstate.lastkextime >= KEX_REKEY_TIMEOUT
-+ && (elapsed(now, ses.kexstate.lastkextime) >= KEX_REKEY_TIMEOUT
- || ses.kexstate.datarecv+ses.kexstate.datatrans >= KEX_REKEY_DATA)) {
- TRACE(("rekeying after timeout or max data reached"))
- send_msg_kexinit();
- }
--
-+
- if (opts.keepalive_secs > 0 && ses.authstate.authdone) {
- /* Avoid sending keepalives prior to auth - those are
- not valid pre-auth packet types */
-
- /* Send keepalives if we've been idle */
-- if (now - ses.last_packet_time_any_sent >= opts.keepalive_secs) {
-+ if (elapsed(now, ses.last_packet_time_any_sent) >= opts.keepalive_secs) {
- send_msg_keepalive();
- }
-
- /* Also send an explicit keepalive message to trigger a response
- if the remote end hasn't sent us anything */
-- if (now - ses.last_packet_time_keepalive_recv >= opts.keepalive_secs
-- && now - ses.last_packet_time_keepalive_sent >= opts.keepalive_secs) {
-+ if (elapsed(now, ses.last_packet_time_keepalive_recv) >= opts.keepalive_secs
-+ && elapsed(now, ses.last_packet_time_keepalive_sent) >= opts.keepalive_secs) {
- send_msg_keepalive();
- }
-
-- if (now - ses.last_packet_time_keepalive_recv
-+ if (elapsed(now, ses.last_packet_time_keepalive_recv)
- >= opts.keepalive_secs * DEFAULT_KEEPALIVE_LIMIT) {
- dropbear_exit("Keepalive timeout");
- }
- }
-
-- if (opts.idle_timeout_secs > 0
-- && now - ses.last_packet_time_idle >= opts.idle_timeout_secs) {
-+ if (opts.idle_timeout_secs > 0
-+ && elapsed(now, ses.last_packet_time_idle) >= opts.idle_timeout_secs) {
- dropbear_close("Idle timeout");
- }
- }
-
--static void update_timeout(long limit, long now, long last_event, long * timeout) {
-- TRACE2(("update_timeout limit %ld, now %ld, last %ld, timeout %ld",
-- limit, now, last_event, *timeout))
-+static void update_timeout(long limit, time_t now, time_t last_event, long * timeout) {
-+ TRACE2(("update_timeout limit %ld, now %llu, last %llu, timeout %ld",
-+ limit,
-+ (unsigned long long)now,
-+ (unsigned long long)last_event, *timeout))
- if (last_event > 0 && limit > 0) {
-- *timeout = MIN(*timeout, last_event+limit-now);
-+ *timeout = MIN(*timeout, elapsed(now, last_event) + limit);
- TRACE2(("new timeout %ld", *timeout))
- }
- }
-@@ -584,7 +595,7 @@ static long select_timeout() {
- /* determine the minimum timeout that might be required, so
- as to avoid waking when unneccessary */
- long timeout = KEX_REKEY_TIMEOUT;
-- long now = monotonic_now();
-+ time_t now = monotonic_now();
-
- if (!ses.kexstate.sentkexinit) {
- update_timeout(KEX_REKEY_TIMEOUT, now, ses.kexstate.lastkextime, &timeout);
-@@ -596,7 +607,7 @@ static long select_timeout() {
- }
-
- if (ses.authstate.authdone) {
-- update_timeout(opts.keepalive_secs, now,
-+ update_timeout(opts.keepalive_secs, now,
- MAX(ses.last_packet_time_keepalive_recv, ses.last_packet_time_keepalive_sent),
- &timeout);
- }
---- a/dbutil.c
-+++ b/dbutil.c
-@@ -724,7 +724,7 @@ void gettime_wrapper(struct timespec *no
- /* Fallback for everything else - this will sometimes go backwards */
- gettimeofday(&tv, NULL);
- now->tv_sec = tv.tv_sec;
-- now->tv_nsec = 1000*tv.tv_usec;
-+ now->tv_nsec = 1000*(long)tv.tv_usec;
- }
-
- /* second-resolution monotonic timestamp */
---- a/loginrec.c
-+++ b/loginrec.c
-@@ -459,6 +459,7 @@ line_abbrevname(char *dst, const char *s
- void
- set_utmp_time(struct logininfo *li, struct utmp *ut)
- {
-+ /* struct utmp in glibc isn't y2038 safe yet */
- # ifdef HAVE_STRUCT_UTMP_UT_TV
- ut->ut_tv.tv_sec = li->tv_sec;
- ut->ut_tv.tv_usec = li->tv_usec;
-@@ -1272,6 +1273,7 @@ lastlog_construct(struct logininfo *li,
- (void)line_stripname(last->ll_line, li->line, sizeof(last->ll_line));
- strlcpy(last->ll_host, li->hostname,
- MIN_SIZEOF(last->ll_host, li->hostname));
-+ /* struct lastlog in glibc isn't y2038 safe yet */
- last->ll_time = li->tv_sec;
- }
-
---- a/loginrec.h
-+++ b/loginrec.h
-@@ -139,8 +139,8 @@ struct logininfo {
- /* struct timeval (sys/time.h) isn't always available, if it isn't we'll
- * use time_t's value as tv_sec and set tv_usec to 0
- */
-- unsigned int tv_sec;
-- unsigned int tv_usec;
-+ time_t tv_sec;
-+ suseconds_t tv_usec;
- union login_netinfo hostaddr; /* caller's host address(es) */
- }; /* struct logininfo */
-
---- a/runopts.h
-+++ b/runopts.h
-@@ -39,8 +39,8 @@ typedef struct runopts {
- int listen_fwd_all;
- #endif
- unsigned int recv_window;
-- time_t keepalive_secs; /* Time between sending keepalives. 0 is off */
-- time_t idle_timeout_secs; /* Exit if no traffic is sent/received in this time */
-+ long keepalive_secs; /* Time between sending keepalives. 0 is off */
-+ long idle_timeout_secs; /* Exit if no traffic is sent/received in this time */
- int usingsyslog;
-
- #ifndef DISABLE_ZLIB
---- a/svr-auth.c
-+++ b/svr-auth.c
-@@ -389,7 +389,7 @@ void send_msg_userauth_failure(int parti
- Beware of integer overflow if increasing these values */
- const unsigned int mindelay = 250000000;
- const unsigned int vardelay = 100000000;
-- unsigned int rand_delay;
-+ suseconds_t rand_delay;
- struct timespec delay;
-
- gettime_wrapper(&delay);
+++ /dev/null
-From c043efb47c3173072fa636ca0da0d19875d4511f Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Tue, 6 Dec 2022 22:34:11 +0800
-Subject: Fix so DROPBEAR_DSS is only forced for fuzzing
-
-Regression from 787391ea3b5af2acf5e3c83372510f0c79477ad7,
-was missing fuzzing conditional
----
- sysoptions.h | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/sysoptions.h
-+++ b/sysoptions.h
-@@ -380,9 +380,11 @@
- #endif
-
- /* Fuzzing expects all key types to be enabled */
-+#if DROPBEAR_FUZZ
- #if defined(DROPBEAR_DSS)
- #undef DROPBEAR_DSS
- #endif
- #define DROPBEAR_DSS 1
-+#endif
-
- /* no include guard for this file */
+++ /dev/null
-From 860721558837441ab45019858e710a2625ffa46e Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Wed, 7 Dec 2022 13:04:10 +0800
-Subject: Allow users's own gid in pty permission check
-
-This allows non-root Dropbear to work even without devpts gid=5 mount
-option on Linux.
----
- sshpty.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/sshpty.c
-+++ b/sshpty.c
-@@ -380,7 +380,9 @@ pty_setowner(struct passwd *pw, const ch
- tty_name, strerror(errno));
- }
-
-- if (st.st_uid != pw->pw_uid || st.st_gid != gid) {
-+ /* Allow either "tty" gid or user's own gid. On Linux with openpty()
-+ * this varies depending on the devpts mount options */
-+ if (st.st_uid != pw->pw_uid || !(st.st_gid == gid || st.st_gid == pw->pw_gid)) {
- if (chown(tty_name, pw->pw_uid, gid) < 0) {
- if (errno == EROFS &&
- (st.st_uid == pw->pw_uid || st.st_uid == 0)) {
+++ /dev/null
-From 01415ef8269e594a647f67ea0729ca8b590679de Mon Sep 17 00:00:00 2001
-From: Francois Perrad <francois.perrad@gadz.org>
-Date: Thu, 22 Dec 2022 10:19:54 +0100
-Subject: const parameter mp_int
-
----
- bignum.c | 2 +-
- bignum.h | 2 +-
- buffer.c | 2 +-
- buffer.h | 2 +-
- dbrandom.c | 2 +-
- dbrandom.h | 2 +-
- dbutil.c | 2 +-
- dbutil.h | 2 +-
- genrsa.c | 4 ++--
- 9 files changed, 10 insertions(+), 10 deletions(-)
-
---- a/bignum.c
-+++ b/bignum.c
-@@ -93,7 +93,7 @@ void bytes_to_mp(mp_int *mp, const unsig
-
- /* hash the ssh representation of the mp_int mp */
- void hash_process_mp(const struct ltc_hash_descriptor *hash_desc,
-- hash_state *hs, mp_int *mp) {
-+ hash_state *hs, const mp_int *mp) {
- buffer * buf;
-
- buf = buf_new(512 + 20); /* max buffer is a 4096 bit key,
---- a/bignum.h
-+++ b/bignum.h
-@@ -33,6 +33,6 @@ void m_mp_alloc_init_multi(mp_int **mp,
- void m_mp_free_multi(mp_int **mp, ...) ATTRIB_SENTINEL;
- void bytes_to_mp(mp_int *mp, const unsigned char* bytes, unsigned int len);
- void hash_process_mp(const struct ltc_hash_descriptor *hash_desc,
-- hash_state *hs, mp_int *mp);
-+ hash_state *hs, const mp_int *mp);
-
- #endif /* DROPBEAR_BIGNUM_H_ */
---- a/buffer.c
-+++ b/buffer.c
-@@ -299,7 +299,7 @@ void buf_putbytes(buffer *buf, const uns
-
- /* for our purposes we only need positive (or 0) numbers, so will
- * fail if we get negative numbers */
--void buf_putmpint(buffer* buf, mp_int * mp) {
-+void buf_putmpint(buffer* buf, const mp_int * mp) {
- size_t written;
- unsigned int len, pad = 0;
- TRACE2(("enter buf_putmpint"))
---- a/buffer.h
-+++ b/buffer.h
-@@ -65,7 +65,7 @@ void buf_putint(buffer* buf, unsigned in
- void buf_putstring(buffer* buf, const char* str, unsigned int len);
- void buf_putbufstring(buffer *buf, const buffer* buf_str);
- void buf_putbytes(buffer *buf, const unsigned char *bytes, unsigned int len);
--void buf_putmpint(buffer* buf, mp_int * mp);
-+void buf_putmpint(buffer* buf, const mp_int * mp);
- int buf_getmpint(buffer* buf, mp_int* mp);
- unsigned int buf_getint(buffer* buf);
-
---- a/dbrandom.c
-+++ b/dbrandom.c
-@@ -347,7 +347,7 @@ void genrandom(unsigned char* buf, unsig
- * rand must be an initialised *mp_int for the result.
- * the result rand satisfies: 0 < rand < max
- * */
--void gen_random_mpint(mp_int *max, mp_int *rand) {
-+void gen_random_mpint(const mp_int *max, mp_int *rand) {
-
- unsigned char *randbuf = NULL;
- unsigned int len = 0;
---- a/dbrandom.h
-+++ b/dbrandom.h
-@@ -30,6 +30,6 @@
- void seedrandom(void);
- void genrandom(unsigned char* buf, unsigned int len);
- void addrandom(const unsigned char * buf, unsigned int len);
--void gen_random_mpint(mp_int *max, mp_int *rand);
-+void gen_random_mpint(const mp_int *max, mp_int *rand);
-
- #endif /* DROPBEAR_RANDOM_H_ */
---- a/dbutil.c
-+++ b/dbutil.c
-@@ -442,7 +442,7 @@ void printhex(const char * label, const
- }
- }
-
--void printmpint(const char *label, mp_int *mp) {
-+void printmpint(const char *label, const mp_int *mp) {
- buffer *buf = buf_new(1000);
- buf_putmpint(buf, mp);
- fprintf(stderr, "%d bits ", mp_count_bits(mp));
---- a/dbutil.h
-+++ b/dbutil.h
-@@ -53,7 +53,7 @@ void dropbear_trace3(const char* format,
- void dropbear_trace4(const char* format, ...) ATTRIB_PRINTF(1,2);
- void dropbear_trace5(const char* format, ...) ATTRIB_PRINTF(1,2);
- void printhex(const char * label, const unsigned char * buf, int len);
--void printmpint(const char *label, mp_int *mp);
-+void printmpint(const char *label, const mp_int *mp);
- void debug_start_net(void);
- extern int debug_trace;
- #endif
---- a/genrsa.c
-+++ b/genrsa.c
-@@ -34,7 +34,7 @@
- #if DROPBEAR_RSA
-
- static void getrsaprime(mp_int* prime, mp_int *primeminus,
-- mp_int* rsa_e, unsigned int size_bytes);
-+ const mp_int* rsa_e, unsigned int size_bytes);
-
- /* mostly taken from libtomcrypt's rsa key generation routine */
- dropbear_rsa_key * gen_rsa_priv_key(unsigned int size) {
-@@ -89,7 +89,7 @@ dropbear_rsa_key * gen_rsa_priv_key(unsi
-
- /* return a prime suitable for p or q */
- static void getrsaprime(mp_int* prime, mp_int *primeminus,
-- mp_int* rsa_e, unsigned int size_bytes) {
-+ const mp_int* rsa_e, unsigned int size_bytes) {
-
- unsigned char *buf;
- int trials;
+++ /dev/null
-From 39d955c49f31fc155e885447ee2be61c869d8c2d Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Tue, 3 Jan 2023 22:05:14 +0800
-Subject: Add missing break in switch
-
-Has no effect on execution, the fallthrough does nothing
-Closes #208
----
- dropbearkey.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/dropbearkey.c
-+++ b/dropbearkey.c
-@@ -139,6 +139,7 @@ static void check_signkey_bits(enum sign
- dropbear_exit("DSS keys have a fixed size of 1024 bits\n");
- exit(EXIT_FAILURE);
- }
-+ break;
- #endif
- default:
- (void)0; /* quiet, compiler. ecdsa handles checks itself */
+++ /dev/null
-From 7a53c7f0f4b3eb23e002819553cb45558642c01d Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Wed, 4 Jan 2023 20:32:23 +0800
-Subject: Fix building only client or server
-
-Regressed when -Wundef was added
-
-Fixes #210
----
- sysoptions.h | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/sysoptions.h
-+++ b/sysoptions.h
-@@ -10,6 +10,14 @@
- #define LOCAL_IDENT "SSH-2.0-dropbear_" DROPBEAR_VERSION
- #define PROGNAME "dropbear"
-
-+#ifndef DROPBEAR_CLIENT
-+#define DROPBEAR_CLIENT 0
-+#endif
-+
-+#ifndef DROPBEAR_SERVER
-+#define DROPBEAR_SERVER 0
-+#endif
-+
- /* Spec recommends after one hour or 1 gigabyte of data. One hour
- * is a bit too verbose, so we try 8 hours */
- #ifndef KEX_REKEY_TIMEOUT
+++ /dev/null
-From a113381c12a2da3c9b7bd594f47a1b2657bdfdf2 Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Sun, 12 Feb 2023 22:44:32 +0800
-Subject: Disable rsa signatures when no rsa hostkey
-
-Otherwise Dropbear will offer RSA as a hostkey signature option, but the
-session will exit with an assertion or NULL pointer dereference once
-that algorithm is negotiated.
-
-This likely regressed in 2020.79 when signature vs key type enums were
-split, for rsa-sha256.
-
-Fixes #219 on github
----
- svr-runopts.c | 21 +++++++++++----------
- 1 file changed, 11 insertions(+), 10 deletions(-)
-
---- a/svr-runopts.c
-+++ b/svr-runopts.c
-@@ -505,11 +505,11 @@ static void addportandaddress(const char
- svr_opts.portcount++;
- }
-
--static void disablekey(int type) {
-+static void disablekey(enum signature_type type) {
- int i;
- TRACE(("Disabling key type %d", type))
- for (i = 0; sigalgs[i].name != NULL; i++) {
-- if (sigalgs[i].val == type) {
-+ if ((int)sigalgs[i].val == (int)type) {
- sigalgs[i].usable = 0;
- break;
- }
-@@ -624,7 +624,8 @@ void load_all_hostkeys() {
-
- #if DROPBEAR_RSA
- if (!svr_opts.delay_hostkey && !svr_opts.hostkey->rsakey) {
-- disablekey(DROPBEAR_SIGNKEY_RSA);
-+ disablekey(DROPBEAR_SIGNATURE_RSA_SHA256);
-+ disablekey(DROPBEAR_SIGNATURE_RSA_SHA1);
- } else {
- any_keys = 1;
- }
-@@ -632,7 +633,7 @@ void load_all_hostkeys() {
-
- #if DROPBEAR_DSS
- if (!svr_opts.delay_hostkey && !svr_opts.hostkey->dsskey) {
-- disablekey(DROPBEAR_SIGNKEY_DSS);
-+ disablekey(DROPBEAR_SIGNATURE_DSS);
- } else {
- any_keys = 1;
- }
-@@ -666,35 +667,35 @@ void load_all_hostkeys() {
- #if DROPBEAR_ECC_256
- if (!svr_opts.hostkey->ecckey256
- && (!svr_opts.delay_hostkey || loaded_any_ecdsa || ECDSA_DEFAULT_SIZE != 256 )) {
-- disablekey(DROPBEAR_SIGNKEY_ECDSA_NISTP256);
-+ disablekey(DROPBEAR_SIGNATURE_ECDSA_NISTP256);
- }
- #endif
- #if DROPBEAR_ECC_384
- if (!svr_opts.hostkey->ecckey384
- && (!svr_opts.delay_hostkey || loaded_any_ecdsa || ECDSA_DEFAULT_SIZE != 384 )) {
-- disablekey(DROPBEAR_SIGNKEY_ECDSA_NISTP384);
-+ disablekey(DROPBEAR_SIGNATURE_ECDSA_NISTP384);
- }
- #endif
- #if DROPBEAR_ECC_521
- if (!svr_opts.hostkey->ecckey521
- && (!svr_opts.delay_hostkey || loaded_any_ecdsa || ECDSA_DEFAULT_SIZE != 521 )) {
-- disablekey(DROPBEAR_SIGNKEY_ECDSA_NISTP521);
-+ disablekey(DROPBEAR_SIGNATURE_ECDSA_NISTP521);
- }
- #endif
- #endif /* DROPBEAR_ECDSA */
-
- #if DROPBEAR_ED25519
- if (!svr_opts.delay_hostkey && !svr_opts.hostkey->ed25519key) {
-- disablekey(DROPBEAR_SIGNKEY_ED25519);
-+ disablekey(DROPBEAR_SIGNATURE_ED25519);
- } else {
- any_keys = 1;
- }
- #endif
- #if DROPBEAR_SK_ECDSA
-- disablekey(DROPBEAR_SIGNKEY_SK_ECDSA_NISTP256);
-+ disablekey(DROPBEAR_SIGNATURE_SK_ECDSA_NISTP256);
- #endif
- #if DROPBEAR_SK_ED25519
-- disablekey(DROPBEAR_SIGNKEY_SK_ED25519);
-+ disablekey(DROPBEAR_SIGNATURE_SK_ED25519);
- #endif
-
- if (!any_keys) {
+++ /dev/null
-From 3292b8c6f1e5fcc405fa0f7a20e90a60f74037b2 Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Sun, 12 Feb 2023 23:00:00 +0800
-Subject: Use write() rather than fprintf() in segv handler
-
-fprintf isn't guaranteed safe (though hasn't had any problems reported).
----
- svr-main.c | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
---- a/svr-main.c
-+++ b/svr-main.c
-@@ -420,8 +420,12 @@ static void sigchld_handler(int UNUSED(u
-
- /* catch any segvs */
- static void sigsegv_handler(int UNUSED(unused)) {
-- fprintf(stderr, "Aiee, segfault! You should probably report "
-- "this as a bug to the developer\n");
-+ int i;
-+ const char *msg = "Aiee, segfault! You should probably report "
-+ "this as a bug to the developer\n";
-+ i = write(STDERR_FILENO, msg, strlen(msg));
-+ /* ignore short writes */
-+ (void)i;
- _exit(EXIT_FAILURE);
- }
-
+++ /dev/null
-From 5040f21cb4ee6ade966e60c6d5a3c270d03de1f1 Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Mon, 1 May 2023 22:05:43 +0800
-Subject: Remove SO_LINGER
-
-It could cause channels to take up to 5 seconds to close(), which would block
-the entire process. On busy TCP forwarding sessions this would result in
-channels seeming stuck and new connections not being accepted.
-
-We don't need to monitor for flushing failures since we can't report errors, so
-SO_LINGER wasn't useful.
-
-Thanks to GektorUA for reporting and testing
-
-Fixes #230
----
- netio.c | 4 ----
- 1 file changed, 4 deletions(-)
-
---- a/netio.c
-+++ b/netio.c
-@@ -472,7 +472,6 @@ int dropbear_listen(const char* address,
- struct addrinfo hints, *res = NULL, *res0 = NULL;
- int err;
- unsigned int nsock;
-- struct linger linger;
- int val;
- int sock;
- uint16_t *allocated_lport_p = NULL;
-@@ -551,9 +550,6 @@ int dropbear_listen(const char* address,
- val = 1;
- /* set to reuse, quick timeout */
- setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (void*) &val, sizeof(val));
-- linger.l_onoff = 1;
-- linger.l_linger = 5;
-- setsockopt(sock, SOL_SOCKET, SO_LINGER, (void*)&linger, sizeof(linger));
-
- #if defined(IPPROTO_IPV6) && defined(IPV6_V6ONLY)
- if (res->ai_family == AF_INET6) {
+++ /dev/null
-From fb64db9eac3fdc6434f2dc7b5ea407fe5df76e6f Mon Sep 17 00:00:00 2001
-From: Diederik De Coninck <diederik.deconinck_ext@softathome.com>
-Date: Tue, 11 Apr 2023 15:38:04 +0200
-Subject: Add option to bind to interface
-
----
- netio.c | 13 +++++++++++--
- netio.h | 2 +-
- runopts.h | 1 +
- svr-main.c | 2 +-
- svr-runopts.c | 9 +++++++++
- svr-tcpfwd.c | 1 +
- tcp-accept.c | 2 +-
- tcpfwd.h | 1 +
- 8 files changed, 26 insertions(+), 5 deletions(-)
-
---- a/netio.c
-+++ b/netio.c
-@@ -467,7 +467,7 @@ int get_sock_port(int sock) {
- * failure, if errstring wasn't NULL, it'll be a newly malloced error
- * string.*/
- int dropbear_listen(const char* address, const char* port,
-- int *socks, unsigned int sockcount, char **errstring, int *maxfd) {
-+ int *socks, unsigned int sockcount, char **errstring, int *maxfd, const char* interface) {
-
- struct addrinfo hints, *res = NULL, *res0 = NULL;
- int err;
-@@ -497,7 +497,11 @@ int dropbear_listen(const char* address,
- TRACE(("dropbear_listen: local loopback"))
- } else {
- if (address[0] == '\0') {
-- TRACE(("dropbear_listen: all interfaces"))
-+ if (interface) {
-+ TRACE(("dropbear_listen: %s", interface))
-+ } else {
-+ TRACE(("dropbear_listen: all interfaces"))
-+ }
- address = NULL;
- }
- hints.ai_flags = AI_PASSIVE;
-@@ -551,6 +555,11 @@ int dropbear_listen(const char* address,
- /* set to reuse, quick timeout */
- setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (void*) &val, sizeof(val));
-
-+ if(interface && setsockopt(sock, SOL_SOCKET, SO_BINDTODEVICE, interface, strlen(interface)) < 0) {
-+ dropbear_log(LOG_WARNING, "Couldn't set SO_BINDTODEVICE");
-+ TRACE(("Failed setsockopt with errno failure, %d %s", errno, strerror(errno)))
-+ }
-+
- #if defined(IPPROTO_IPV6) && defined(IPV6_V6ONLY)
- if (res->ai_family == AF_INET6) {
- int on = 1;
---- a/netio.h
-+++ b/netio.h
-@@ -19,7 +19,7 @@ void get_socket_address(int fd, char **l
- void getaddrstring(struct sockaddr_storage* addr,
- char **ret_host, char **ret_port, int host_lookup);
- int dropbear_listen(const char* address, const char* port,
-- int *socks, unsigned int sockcount, char **errstring, int *maxfd);
-+ int *socks, unsigned int sockcount, char **errstring, int *maxfd, const char* interface);
-
- struct dropbear_progress_connection;
-
---- a/runopts.h
-+++ b/runopts.h
-@@ -128,6 +128,7 @@ typedef struct svr_runopts {
- char * pidfile;
-
- char * forced_command;
-+ char* interface;
-
- #if DROPBEAR_PLUGIN
- /* malloced */
---- a/svr-main.c
-+++ b/svr-main.c
-@@ -488,7 +488,7 @@ static size_t listensockets(int *socks,
-
- nsock = dropbear_listen(svr_opts.addresses[i], svr_opts.ports[i], &socks[sockpos],
- sockcount - sockpos,
-- &errstring, maxfd);
-+ &errstring, maxfd, svr_opts.interface);
-
- if (nsock < 0) {
- dropbear_log(LOG_WARNING, "Failed listening on '%s': %s",
---- a/svr-runopts.c
-+++ b/svr-runopts.c
-@@ -98,6 +98,8 @@ static void printhelp(const char * progn
- " (default port is %s if none specified)\n"
- "-P PidFile Create pid file PidFile\n"
- " (default %s)\n"
-+ "-l <interface>\n"
-+ " interface to bind on\n"
- #if INETD_MODE
- "-i Start for inetd\n"
- #endif
-@@ -265,6 +267,9 @@ void svr_getopts(int argc, char ** argv)
- case 'P':
- next = &svr_opts.pidfile;
- break;
-+ case 'l':
-+ next = &svr_opts.interface;
-+ break;
- #if DO_MOTD
- /* motd is displayed by default, -m turns it off */
- case 'm':
-@@ -438,6 +443,10 @@ void svr_getopts(int argc, char ** argv)
- dropbear_log(LOG_INFO, "Forced command set to '%s'", svr_opts.forced_command);
- }
-
-+ if (svr_opts.interface) {
-+ dropbear_log(LOG_INFO, "Binding to interface '%s'", svr_opts.interface);
-+ }
-+
- if (reexec_fd_arg) {
- if (m_str_to_uint(reexec_fd_arg, &svr_opts.reexec_childpipe) == DROPBEAR_FAILURE
- || svr_opts.reexec_childpipe < 0) {
---- a/svr-tcpfwd.c
-+++ b/svr-tcpfwd.c
-@@ -205,6 +205,7 @@ static int svr_remotetcpreq(int *allocat
- tcpinfo->listenport = port;
- tcpinfo->chantype = &svr_chan_tcpremote;
- tcpinfo->tcp_type = forwarded;
-+ tcpinfo->interface = svr_opts.interface;
-
- tcpinfo->request_listenaddr = request_addr;
- if (!opts.listen_fwd_all || (strcmp(request_addr, "localhost") == 0) ) {
---- a/tcp-accept.c
-+++ b/tcp-accept.c
-@@ -117,7 +117,7 @@ int listen_tcpfwd(struct TCPListener* tc
- snprintf(portstring, sizeof(portstring), "%u", tcpinfo->listenport);
-
- nsocks = dropbear_listen(tcpinfo->listenaddr, portstring, socks,
-- DROPBEAR_MAX_SOCKS, &errstring, &ses.maxfd);
-+ DROPBEAR_MAX_SOCKS, &errstring, &ses.maxfd, tcpinfo->interface);
- if (nsocks < 0) {
- dropbear_log(LOG_INFO, "TCP forward failed: %s", errstring);
- m_free(errstring);
---- a/tcpfwd.h
-+++ b/tcpfwd.h
-@@ -42,6 +42,7 @@ struct TCPListener {
- unsigned int listenport;
- /* The address that the remote host asked to listen on */
- char *request_listenaddr;
-+ char* interface;
-
- const struct ChanType *chantype;
- enum {direct, forwarded} tcp_type;
+++ /dev/null
-From 031d09b47912b2401f4934667c0b6f857ede61ee Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Tue, 18 Jul 2023 23:20:16 +0800
-Subject: Add ifdef guards for SO_BINDTODEVICE
-
----
- netio.c | 2 ++
- svr-runopts.c | 4 ++++
- 2 files changed, 6 insertions(+)
-
---- a/netio.c
-+++ b/netio.c
-@@ -555,10 +555,12 @@ int dropbear_listen(const char* address,
- /* set to reuse, quick timeout */
- setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (void*) &val, sizeof(val));
-
-+#ifdef SO_BINDTODEVICE
- if(interface && setsockopt(sock, SOL_SOCKET, SO_BINDTODEVICE, interface, strlen(interface)) < 0) {
- dropbear_log(LOG_WARNING, "Couldn't set SO_BINDTODEVICE");
- TRACE(("Failed setsockopt with errno failure, %d %s", errno, strerror(errno)))
- }
-+#endif
-
- #if defined(IPPROTO_IPV6) && defined(IPV6_V6ONLY)
- if (res->ai_family == AF_INET6) {
---- a/svr-runopts.c
-+++ b/svr-runopts.c
-@@ -98,8 +98,10 @@ static void printhelp(const char * progn
- " (default port is %s if none specified)\n"
- "-P PidFile Create pid file PidFile\n"
- " (default %s)\n"
-+#ifdef SO_BINDTODEVICE
- "-l <interface>\n"
- " interface to bind on\n"
-+#endif
- #if INETD_MODE
- "-i Start for inetd\n"
- #endif
-@@ -267,9 +269,11 @@ void svr_getopts(int argc, char ** argv)
- case 'P':
- next = &svr_opts.pidfile;
- break;
-+#ifdef SO_BINDTODEVICE
- case 'l':
- next = &svr_opts.interface;
- break;
-+#endif
- #if DO_MOTD
- /* motd is displayed by default, -m turns it off */
- case 'm':
+++ /dev/null
-From 62a06cd95f58060a59359f8769c3f35cd680d4fd Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Sun, 23 Jul 2023 21:01:48 +0800
-Subject: Make banner reading failure non-fatal
-
----
- svr-runopts.c | 45 ++++++++++++++++++++++++++++-----------------
- 1 file changed, 28 insertions(+), 17 deletions(-)
-
---- a/svr-runopts.c
-+++ b/svr-runopts.c
-@@ -38,6 +38,7 @@ static void printhelp(const char * progn
- static void addportandaddress(const char* spec);
- static void loadhostkey(const char *keyfile, int fatal_duplicate);
- static void addhostkey(const char *keyfile);
-+static void load_banner();
-
- static void printhelp(const char * progname) {
-
-@@ -382,23 +383,7 @@ void svr_getopts(int argc, char ** argv)
- }
-
- if (svr_opts.bannerfile) {
-- struct stat buf;
-- if (stat(svr_opts.bannerfile, &buf) != 0) {
-- dropbear_exit("Error opening banner file '%s'",
-- svr_opts.bannerfile);
-- }
--
-- if (buf.st_size > MAX_BANNER_SIZE) {
-- dropbear_exit("Banner file too large, max is %d bytes",
-- MAX_BANNER_SIZE);
-- }
--
-- svr_opts.banner = buf_new(buf.st_size);
-- if (buf_readfile(svr_opts.banner, svr_opts.bannerfile)!=DROPBEAR_SUCCESS) {
-- dropbear_exit("Error reading banner file '%s'",
-- svr_opts.bannerfile);
-- }
-- buf_setpos(svr_opts.banner, 0);
-+ load_banner();
- }
-
- #ifdef HAVE_GETGROUPLIST
-@@ -715,3 +700,29 @@ void load_all_hostkeys() {
- dropbear_exit("No hostkeys available. 'dropbear -R' may be useful or run dropbearkey.");
- }
- }
-+
-+static void load_banner() {
-+ struct stat buf;
-+ if (stat(svr_opts.bannerfile, &buf) != 0) {
-+ dropbear_log(LOG_WARNING, "Error opening banner file '%s'",
-+ svr_opts.bannerfile);
-+ return;
-+ }
-+
-+ if (buf.st_size > MAX_BANNER_SIZE) {
-+ dropbear_log(LOG_WARNING, "Banner file too large, max is %d bytes",
-+ MAX_BANNER_SIZE);
-+ return;
-+ }
-+
-+ svr_opts.banner = buf_new(buf.st_size);
-+ if (buf_readfile(svr_opts.banner, svr_opts.bannerfile) != DROPBEAR_SUCCESS) {
-+ dropbear_log(LOG_WARNING, "Error reading banner file '%s'",
-+ svr_opts.bannerfile);
-+ buf_free(svr_opts.banner);
-+ svr_opts.banner = NULL;
-+ return;
-+ }
-+ buf_setpos(svr_opts.banner, 0);
-+
-+}
+++ /dev/null
-From ec26975d442163b66d1646a48e022bc8c2f1607a Mon Sep 17 00:00:00 2001
-From: Sergey Ponomarev <stokito@gmail.com>
-Date: Sun, 27 Aug 2023 00:07:05 +0300
-Subject: dropbearkey.c Ignore unsupported command line options
-
-To generate non interactively a key with OpenSSH the simplest command is:
-
-ssh-keygen -t ed25519 -q -N '' -f ~/.ssh/id_ed25519
-
-The command has two options -q quiet and -N passphrase which aren't supported by the dropbearkey.
-
-To improve interoperability add explicit ignoring of the -q and -N with empty passphrase.
-Also ignore the -v even if the DEBUG_TRACE is not set.
-
-Signed-off-by: Sergey Ponomarev <stokito@gmail.com>
----
- dropbearkey.c | 15 +++++++++++++--
- 1 file changed, 13 insertions(+), 2 deletions(-)
-
---- a/dropbearkey.c
-+++ b/dropbearkey.c
-@@ -159,6 +159,7 @@ int main(int argc, char ** argv) {
- enum signkey_type keytype = DROPBEAR_SIGNKEY_NONE;
- char * typetext = NULL;
- char * sizetext = NULL;
-+ char * passphrase = NULL;
- unsigned int bits = 0, genbits;
- int printpub = 0;
-
-@@ -194,11 +195,16 @@ int main(int argc, char ** argv) {
- printhelp(argv[0]);
- exit(EXIT_SUCCESS);
- break;
--#if DEBUG_TRACE
- case 'v':
-+#if DEBUG_TRACE
- debug_trace = DROPBEAR_VERBOSE_LEVEL;
-- break;
- #endif
-+ break;
-+ case 'q':
-+ break; /* quiet is default */
-+ case 'N':
-+ next = &passphrase;
-+ break;
- default:
- fprintf(stderr, "Unknown argument %s\n", argv[i]);
- printhelp(argv[0]);
-@@ -266,6 +272,11 @@ int main(int argc, char ** argv) {
- check_signkey_bits(keytype, bits);;
- }
-
-+ if (passphrase && *passphrase != '\0') {
-+ fprintf(stderr, "Only empty passphrase is supported\n");
-+ exit(EXIT_FAILURE);
-+ }
-+
- genbits = signkey_generate_get_bits(keytype, bits);
- fprintf(stderr, "Generating %u bit %s key, this may take a while...\n", genbits, typetext);
- if (signkey_generate(keytype, bits, filename, 0) == DROPBEAR_FAILURE)
+++ /dev/null
-From 3b576d95dcf791d7b945e75f639da8f89c1685a2 Mon Sep 17 00:00:00 2001
-From: czurnieden <czurnieden@gmx.de>
-Date: Tue, 9 May 2023 17:17:12 +0200
-Subject: Fix possible integer overflow
-
----
- libtommath/bn_mp_2expt.c | 4 ++++
- libtommath/bn_mp_grow.c | 4 ++++
- libtommath/bn_mp_init_size.c | 5 +++++
- libtommath/bn_mp_mul_2d.c | 4 ++++
- libtommath/bn_s_mp_mul_digs.c | 4 ++++
- libtommath/bn_s_mp_mul_digs_fast.c | 4 ++++
- libtommath/bn_s_mp_mul_high_digs.c | 4 ++++
- libtommath/bn_s_mp_mul_high_digs_fast.c | 4 ++++
- 8 files changed, 33 insertions(+)
-
---- a/libtommath/bn_mp_2expt.c
-+++ b/libtommath/bn_mp_2expt.c
-@@ -12,6 +12,10 @@ mp_err mp_2expt(mp_int *a, int b)
- {
- mp_err err;
-
-+ if (b < 0) {
-+ return MP_VAL;
-+ }
-+
- /* zero a as per default */
- mp_zero(a);
-
---- a/libtommath/bn_mp_grow.c
-+++ b/libtommath/bn_mp_grow.c
-@@ -9,6 +9,10 @@ mp_err mp_grow(mp_int *a, int size)
- int i;
- mp_digit *tmp;
-
-+ if (size < 0) {
-+ return MP_VAL;
-+ }
-+
- /* if the alloc size is smaller alloc more ram */
- if (a->alloc < size) {
- /* reallocate the array a->dp
---- a/libtommath/bn_mp_init_size.c
-+++ b/libtommath/bn_mp_init_size.c
-@@ -6,6 +6,11 @@
- /* init an mp_init for a given size */
- mp_err mp_init_size(mp_int *a, int size)
- {
-+
-+ if (size < 0) {
-+ return MP_VAL;
-+ }
-+
- size = MP_MAX(MP_MIN_PREC, size);
-
- /* alloc mem */
---- a/libtommath/bn_mp_mul_2d.c
-+++ b/libtommath/bn_mp_mul_2d.c
-@@ -9,6 +9,10 @@ mp_err mp_mul_2d(const mp_int *a, int b,
- mp_digit d;
- mp_err err;
-
-+ if (b < 0) {
-+ return MP_VAL;
-+ }
-+
- /* copy */
- if (a != c) {
- if ((err = mp_copy(a, c)) != MP_OKAY) {
---- a/libtommath/bn_s_mp_mul_digs.c
-+++ b/libtommath/bn_s_mp_mul_digs.c
-@@ -16,6 +16,10 @@ mp_err s_mp_mul_digs(const mp_int *a, co
- mp_word r;
- mp_digit tmpx, *tmpt, *tmpy;
-
-+ if (digs < 0) {
-+ return MP_VAL;
-+ }
-+
- /* can we use the fast multiplier? */
- if ((digs < MP_WARRAY) &&
- (MP_MIN(a->used, b->used) < MP_MAXFAST)) {
---- a/libtommath/bn_s_mp_mul_digs_fast.c
-+++ b/libtommath/bn_s_mp_mul_digs_fast.c
-@@ -26,6 +26,10 @@ mp_err s_mp_mul_digs_fast(const mp_int *
- mp_digit W[MP_WARRAY];
- mp_word _W;
-
-+ if (digs < 0) {
-+ return MP_VAL;
-+ }
-+
- /* grow the destination as required */
- if (c->alloc < digs) {
- if ((err = mp_grow(c, digs)) != MP_OKAY) {
---- a/libtommath/bn_s_mp_mul_high_digs.c
-+++ b/libtommath/bn_s_mp_mul_high_digs.c
-@@ -15,6 +15,10 @@ mp_err s_mp_mul_high_digs(const mp_int *
- mp_word r;
- mp_digit tmpx, *tmpt, *tmpy;
-
-+ if (digs < 0) {
-+ return MP_VAL;
-+ }
-+
- /* can we use the fast multiplier? */
- if (MP_HAS(S_MP_MUL_HIGH_DIGS_FAST)
- && ((a->used + b->used + 1) < MP_WARRAY)
---- a/libtommath/bn_s_mp_mul_high_digs_fast.c
-+++ b/libtommath/bn_s_mp_mul_high_digs_fast.c
-@@ -19,6 +19,10 @@ mp_err s_mp_mul_high_digs_fast(const mp_
- mp_digit W[MP_WARRAY];
- mp_word _W;
-
-+ if (digs < 0) {
-+ return MP_VAL;
-+ }
-+
- /* grow the destination as required */
- pa = a->used + b->used;
- if (c->alloc < pa) {
+++ /dev/null
-From 3cf8344769eda55e26eee53c1898b2c66544f188 Mon Sep 17 00:00:00 2001
-From: Justin Chen <justin.chen@broadcom.com>
-Date: Fri, 8 Sep 2023 11:35:18 -0700
-Subject: src: svr-tcpfwd: Fix noremotetcp behavior
-
-If noremotetcp is set, we should still reply with
-send_msg_request_failed. This matches the behavior
-of !DROPBEAR_SVR_REMOTETCPFWD.
-
-We were seeing keepalive packets being ignored when
-the "-k" option was used.
----
- svr-tcpfwd.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/svr-tcpfwd.c
-+++ b/svr-tcpfwd.c
-@@ -79,14 +79,14 @@ void recv_msg_global_request_remotetcp()
-
- TRACE(("enter recv_msg_global_request_remotetcp"))
-
-+ reqname = buf_getstring(ses.payload, &namelen);
-+ wantreply = buf_getbool(ses.payload);
-+
- if (svr_opts.noremotetcp || !svr_pubkey_allows_tcpfwd()) {
- TRACE(("leave recv_msg_global_request_remotetcp: remote tcp forwarding disabled"))
- goto out;
- }
-
-- reqname = buf_getstring(ses.payload, &namelen);
-- wantreply = buf_getbool(ses.payload);
--
- if (namelen > MAX_NAME_LEN) {
- TRACE(("name len is wrong: %d", namelen))
- goto out;
+++ /dev/null
-From e28ba1b9975eab48799aa3ed77d3cd91627d7b27 Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Sat, 9 Dec 2023 23:10:41 +0800
-Subject: Don't try to shutdown() a pty
-
-shutdown() of a pty doesn't work (ENOTSOCK), so we should close
-it instead.
-
-This will ensure that PTY controlling terminals are closed when a
-session exits, including when multiple sessions run over a single SSH
-connection. In the normal case of a single session, the PTY controlling
-terminal would be closed when the Dropbear server process exits anyway.
-
-This possibly fixes #264 on github
-
-It is possible that there could be subtle changes to PTY flushing
-behaviour, though nothing caught by tests at present.
----
- svr-chansession.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/svr-chansession.c
-+++ b/svr-chansession.c
-@@ -910,7 +910,7 @@ static int ptycommand(struct Channel *ch
- channel->readfd = chansess->master;
- /* don't need to set stderr here */
- ses.maxfd = MAX(ses.maxfd, chansess->master);
-- channel->bidir_fd = 1;
-+ channel->bidir_fd = 0;
-
- setnonblocking(chansess->master);
-
+++ /dev/null
-From 806586b585806cbe32013bcd3af3847278972060 Mon Sep 17 00:00:00 2001
-From: Sergey Ponomarev <stokito@gmail.com>
-Date: Sun, 10 Dec 2023 10:31:56 +0200
-Subject: dropbearkey: add alias to ssh-keygen
-
-The dropbearkey is partially compatible with ssh-keygen and can be used as an alias.
-
-Closes: #263
----
- dbmulti.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/dbmulti.c
-+++ b/dbmulti.c
-@@ -41,7 +41,8 @@ static int runprog(const char *multipath
- }
- #endif
- #ifdef DBMULTI_dropbearkey
-- if (strcmp(progname, "dropbearkey") == 0) {
-+ if (strcmp(progname, "dropbearkey") == 0
-+ || strcmp(progname, "ssh-keygen") == 0) {
- return dropbearkey_main(argc, argv);
- }
- #endif
-@@ -88,7 +89,7 @@ int main(int argc, char ** argv) {
- "'dbclient' or 'ssh' - the Dropbear client\n"
- #endif
- #ifdef DBMULTI_dropbearkey
-- "'dropbearkey' - the key generator\n"
-+ "'dropbearkey' or 'ssh-keygen' - the key generator\n"
- #endif
- #ifdef DBMULTI_dropbearconvert
- "'dropbearconvert' - the key converter\n"
+++ /dev/null
-From 383cc8c97a9420aad9cf93d88e77ec636b183a9d Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Mon, 11 Dec 2023 23:18:09 +0800
-Subject: Allow inetd with non-syslog
-
-An inetd-alike should be able to distinguish stdout and stderr, so
-it's a valid configuration.
-
-Fixes #218 on github
----
- svr-runopts.c | 12 ------------
- 1 file changed, 12 deletions(-)
-
---- a/svr-runopts.c
-+++ b/svr-runopts.c
-@@ -443,18 +443,6 @@ void svr_getopts(int argc, char ** argv)
- }
- }
-
--#if INETD_MODE
-- if (svr_opts.inetdmode && (
-- opts.usingsyslog == 0
--#if DEBUG_TRACE
-- || debug_trace
--#endif
-- )) {
-- /* log output goes to stderr which would get sent over the inetd network socket */
-- dropbear_exit("Dropbear inetd mode is incompatible with debug -v or non-syslog");
-- }
--#endif
--
- if (svr_opts.multiauthmethod && svr_opts.noauthpass) {
- dropbear_exit("-t and -s are incompatible");
- }
+++ /dev/null
-From 9ac650401ffc2fb05c9328d26e76a5e7ae39152a Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Mon, 11 Dec 2023 23:31:22 +0800
-Subject: Fix test for multiuser kernels
-
-getuid() succeeds even on non-multiuser kernels. Instead
-getgroups() is a valid test.
-
-Fixes #214 on github
----
- common-session.c | 11 +++++++----
- 1 file changed, 7 insertions(+), 4 deletions(-)
-
---- a/common-session.c
-+++ b/common-session.c
-@@ -71,10 +71,13 @@ void common_session_init(int sock_in, in
- #if !DROPBEAR_SVR_MULTIUSER
- /* A sanity check to prevent an accidental configuration option
- leaving multiuser systems exposed */
-- errno = 0;
-- getuid();
-- if (errno != ENOSYS) {
-- dropbear_exit("Non-multiuser Dropbear requires a non-multiuser kernel");
-+ {
-+ int ret;
-+ errno = 0;
-+ ret = getgroups(0, NULL);
-+ if (!(ret == -1 && errno == ENOSYS)) {
-+ dropbear_exit("Non-multiuser Dropbear requires a non-multiuser kernel");
-+ }
- }
- #endif
-
+++ /dev/null
-From 6e43be5c7b99dbee49dc72b6f989f29fdd7e9356 Mon Sep 17 00:00:00 2001
-From: Matt Johnston <matt@ucc.asn.au>
-Date: Mon, 20 Nov 2023 14:02:47 +0800
-Subject: Implement Strict KEX mode
-
-As specified by OpenSSH with kex-strict-c-v00@openssh.com and
-kex-strict-s-v00@openssh.com.
----
- cli-session.c | 11 +++++++++++
- common-algo.c | 6 ++++++
- common-kex.c | 26 +++++++++++++++++++++++++-
- kex.h | 3 +++
- process-packet.c | 34 +++++++++++++++++++---------------
- ssh.h | 4 ++++
- svr-session.c | 3 +++
- 7 files changed, 71 insertions(+), 16 deletions(-)
-
---- a/cli-session.c
-+++ b/cli-session.c
-@@ -46,6 +46,7 @@ static void cli_finished(void) ATTRIB_NO
- static void recv_msg_service_accept(void);
- static void cli_session_cleanup(void);
- static void recv_msg_global_request_cli(void);
-+static void cli_algos_initialise(void);
-
- struct clientsession cli_ses; /* GLOBAL */
-
-@@ -117,6 +118,7 @@ void cli_session(int sock_in, int sock_o
- }
-
- chaninitialise(cli_chantypes);
-+ cli_algos_initialise();
-
- /* Set up cli_ses vars */
- cli_session_init(proxy_cmd_pid);
-@@ -487,3 +489,12 @@ void cli_dropbear_log(int priority, cons
- fflush(stderr);
- }
-
-+static void cli_algos_initialise(void) {
-+ algo_type *algo;
-+ for (algo = sshkex; algo->name; algo++) {
-+ if (strcmp(algo->name, SSH_STRICT_KEX_S) == 0) {
-+ algo->usable = 0;
-+ }
-+ }
-+}
-+
---- a/common-algo.c
-+++ b/common-algo.c
-@@ -308,6 +308,12 @@ algo_type sshkex[] = {
- {SSH_EXT_INFO_C, 0, NULL, 1, NULL},
- #endif
- #endif
-+#if DROPBEAR_CLIENT
-+ {SSH_STRICT_KEX_C, 0, NULL, 1, NULL},
-+#endif
-+#if DROPBEAR_SERVER
-+ {SSH_STRICT_KEX_S, 0, NULL, 1, NULL},
-+#endif
- {NULL, 0, NULL, 0, NULL}
- };
-
---- a/common-kex.c
-+++ b/common-kex.c
-@@ -183,6 +183,10 @@ void send_msg_newkeys() {
- gen_new_keys();
- switch_keys();
-
-+ if (ses.kexstate.strict_kex) {
-+ ses.transseq = 0;
-+ }
-+
- TRACE(("leave send_msg_newkeys"))
- }
-
-@@ -193,7 +197,11 @@ void recv_msg_newkeys() {
-
- ses.kexstate.recvnewkeys = 1;
- switch_keys();
--
-+
-+ if (ses.kexstate.strict_kex) {
-+ ses.recvseq = 0;
-+ }
-+
- TRACE(("leave recv_msg_newkeys"))
- }
-
-@@ -550,6 +558,10 @@ void recv_msg_kexinit() {
-
- ses.kexstate.recvkexinit = 1;
-
-+ if (ses.kexstate.strict_kex && !ses.kexstate.donefirstkex && ses.recvseq != 1) {
-+ dropbear_exit("First packet wasn't kexinit");
-+ }
-+
- TRACE(("leave recv_msg_kexinit"))
- }
-
-@@ -859,6 +871,18 @@ static void read_kex_algos() {
- }
- #endif
-
-+ if (!ses.kexstate.donefirstkex) {
-+ const char* strict_name;
-+ if (IS_DROPBEAR_CLIENT) {
-+ strict_name = SSH_STRICT_KEX_S;
-+ } else {
-+ strict_name = SSH_STRICT_KEX_C;
-+ }
-+ if (buf_has_algo(ses.payload, strict_name) == DROPBEAR_SUCCESS) {
-+ ses.kexstate.strict_kex = 1;
-+ }
-+ }
-+
- algo = buf_match_algo(ses.payload, sshkex, kexguess2, &goodguess);
- allgood &= goodguess;
- if (algo == NULL || algo->data == NULL) {
---- a/kex.h
-+++ b/kex.h
-@@ -83,6 +83,9 @@ struct KEXState {
-
- unsigned our_first_follows_matches : 1;
-
-+ /* Boolean indicating that strict kex mode is in use */
-+ unsigned int strict_kex;
-+
- time_t lastkextime; /* time of the last kex */
- unsigned int datatrans; /* data transmitted since last kex */
- unsigned int datarecv; /* data received since last kex */
---- a/process-packet.c
-+++ b/process-packet.c
-@@ -44,6 +44,7 @@ void process_packet() {
-
- unsigned char type;
- unsigned int i;
-+ unsigned int first_strict_kex = ses.kexstate.strict_kex && !ses.kexstate.donefirstkex;
- time_t now;
-
- TRACE2(("enter process_packet"))
-@@ -54,22 +55,24 @@ void process_packet() {
- now = monotonic_now();
- ses.last_packet_time_keepalive_recv = now;
-
-- /* These packets we can receive at any time */
-- switch(type) {
-
-- case SSH_MSG_IGNORE:
-- goto out;
-- case SSH_MSG_DEBUG:
-- goto out;
--
-- case SSH_MSG_UNIMPLEMENTED:
-- /* debugging XXX */
-- TRACE(("SSH_MSG_UNIMPLEMENTED"))
-- goto out;
--
-- case SSH_MSG_DISCONNECT:
-- /* TODO cleanup? */
-- dropbear_close("Disconnect received");
-+ if (type == SSH_MSG_DISCONNECT) {
-+ /* Allowed at any time */
-+ dropbear_close("Disconnect received");
-+ }
-+
-+ /* These packets may be received at any time,
-+ except during first kex with strict kex */
-+ if (!first_strict_kex) {
-+ switch(type) {
-+ case SSH_MSG_IGNORE:
-+ goto out;
-+ case SSH_MSG_DEBUG:
-+ goto out;
-+ case SSH_MSG_UNIMPLEMENTED:
-+ TRACE(("SSH_MSG_UNIMPLEMENTED"))
-+ goto out;
-+ }
- }
-
- /* Ignore these packet types so that keepalives don't interfere with
-@@ -98,7 +101,8 @@ void process_packet() {
- if (type >= 1 && type <= 49
- && type != SSH_MSG_SERVICE_REQUEST
- && type != SSH_MSG_SERVICE_ACCEPT
-- && type != SSH_MSG_KEXINIT)
-+ && type != SSH_MSG_KEXINIT
-+ && !first_strict_kex)
- {
- TRACE(("unknown allowed packet during kexinit"))
- recv_unimplemented();
---- a/ssh.h
-+++ b/ssh.h
-@@ -100,6 +100,10 @@
- #define SSH_EXT_INFO_C "ext-info-c"
- #define SSH_SERVER_SIG_ALGS "server-sig-algs"
-
-+/* OpenSSH strict KEX feature */
-+#define SSH_STRICT_KEX_S "kex-strict-s-v00@openssh.com"
-+#define SSH_STRICT_KEX_C "kex-strict-c-v00@openssh.com"
-+
- /* service types */
- #define SSH_SERVICE_USERAUTH "ssh-userauth"
- #define SSH_SERVICE_USERAUTH_LEN 12
---- a/svr-session.c
-+++ b/svr-session.c
-@@ -370,6 +370,9 @@ static void svr_algos_initialise(void) {
- algo->usable = 0;
- }
- #endif
-+ if (strcmp(algo->name, SSH_STRICT_KEX_C) == 0) {
-+ algo->usable = 0;
-+ }
- }
- }
-
---- a/svr-authpubkey.c
-+++ b/svr-authpubkey.c
+--- a/src/svr-authpubkey.c
++++ b/src/svr-authpubkey.c
@@ -78,6 +78,13 @@ static void send_msg_userauth_pk_ok(cons
const unsigned char* keyblob, unsigned int keybloblen);
static int checkfileperm(char * filename);
---- a/svr-chansession.c
-+++ b/svr-chansession.c
-@@ -985,12 +985,12 @@ static void execchild(const void *user_d
+--- a/src/svr-chansession.c
++++ b/src/svr-chansession.c
+@@ -987,12 +987,12 @@ static void execchild(const void *user_d
/* We can only change uid/gid as root ... */
if (getuid() == 0) {
---- a/cli-runopts.c
-+++ b/cli-runopts.c
-@@ -329,6 +329,10 @@ void cli_getopts(int argc, char ** argv)
+--- a/src/cli-runopts.c
++++ b/src/cli-runopts.c
+@@ -340,6 +340,10 @@ void cli_getopts(int argc, char ** argv)
case 'z':
opts.disable_ip_tos = 1;
break;
---- a/dbutil.h
-+++ b/dbutil.h
+--- a/src/dbutil.h
++++ b/src/dbutil.h
@@ -80,7 +80,11 @@ int m_snprintf(char *str, size_t size, c
#define DEF_MP_INT(X) mp_int X = {0, 0, 0, NULL}
--- a/Makefile.in
+++ b/Makefile.in
-@@ -200,17 +200,17 @@ dropbearkey: $(dropbearkeyobjs)
+@@ -220,17 +220,17 @@ dropbearkey: $(dropbearkeyobjs)
dropbearconvert: $(dropbearconvertobjs)
dropbear: $(HEADERS) $(LIBTOM_DEPS) Makefile
# multi-binary compilation.
-@@ -221,7 +221,7 @@ ifeq ($(MULTI),1)
+@@ -241,7 +241,7 @@ ifeq ($(MULTI),1)
endif
dropbearmulti$(EXEEXT): $(HEADERS) $(MULTIOBJS) $(LIBTOM_DEPS) Makefile
---- a/svr-auth.c
-+++ b/svr-auth.c
+--- a/src/svr-auth.c
++++ b/src/svr-auth.c
@@ -124,7 +124,7 @@ void recv_msg_userauth_request() {
AUTH_METHOD_NONE_LEN) == 0) {
TRACE(("recv_msg_userauth_request: 'none' request"))
--- a/configure.ac
+++ b/configure.ac
-@@ -87,54 +87,6 @@ AC_ARG_ENABLE(harden,
+@@ -86,54 +86,6 @@ AC_ARG_ENABLE(harden,
if test "$hardenbuild" -eq 1; then
AC_MSG_NOTICE(Checking for available hardened build flags:)
--- a/configure.ac
+++ b/configure.ac
-@@ -45,11 +45,8 @@ fi
+@@ -44,11 +44,8 @@ fi
# LTM_CFLAGS is given to ./configure by the user,
# DROPBEAR_LTM_CFLAGS is substituted in the LTM Makefile.in
DROPBEAR_LTM_CFLAGS="$LTM_CFLAGS"
signkey.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
---- a/signkey.c
-+++ b/signkey.c
+--- a/src/signkey.c
++++ b/src/signkey.c
@@ -652,10 +652,18 @@ int buf_verify(buffer * buf, sign_key *k
sigtype = signature_type_from_name(type_name, type_name_len);
m_free(type_name);
PKG_SOURCE_URL:=https://w1.fi/hostap.git
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2024-03-09
-PKG_SOURCE_VERSION:=695277a5b3da08b9a8a4e7117b933deb8b4950a7
-PKG_MIRROR_HASH:=57b8e64d24707e37e0df3359cee15dd5184b824b8622568833a5b8a0cae163ae
+PKG_SOURCE_DATE:=2024-05-10
+PKG_SOURCE_VERSION:=7566370a96a8da92638ea5a826c8dc89a927aac9
+PKG_MIRROR_HASH:=6cac442fd35bc669926082eeea62bd90cbb365535f3f1769ce007f2745daf85d
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_LICENSE:=BSD-3-Clause
# Driver interface for no driver (e.g., RADIUS server only)
#CONFIG_DRIVER_NONE=y
-# IEEE 802.11F/IAPP
-#CONFIG_IAPP=y
-
# WPA2/IEEE 802.11i RSN pre-authentication
CONFIG_RSN_PREAUTH=y
-# IEEE 802.11w (management frame protection)
-#CONFIG_IEEE80211W=y
-
# Support Operating Channel Validation
CONFIG_OCV=y
# the IEEE 802.11 Management capability (e.g., FreeBSD/net80211)
#CONFIG_DRIVER_RADIUS_ACL=y
-# IEEE 802.11n (High Throughput) support
-CONFIG_IEEE80211N=y
-
# Wireless Network Management (IEEE Std 802.11v-2011)
# Note: This is experimental and not complete implementation.
#CONFIG_WNM=y
CONFIG_IEEE80211AC=y
# IEEE 802.11ax HE support
+#CONFIG_IEEE80211AX=y
+
+# IEEE 802.11be EHT support
+# CONFIG_IEEE80211AX is mandatory for setting CONFIG_IEEE80211BE.
# Note: This is experimental and work in progress. The definitions are still
# subject to change and this should not be expected to interoperate with the
-# final IEEE 802.11ax version.
-#CONFIG_IEEE80211AX=y
+# final IEEE 802.11be version.
+#CONFIG_IEEE80211BE=y
+
+# Simultaneous Authentication of Equals (SAE), WPA3-Personal
+#CONFIG_SAE=y
+
+# SAE Public Key, WPA3-Personal
+#CONFIG_SAE_PK=y
# Remove debugging code that is printing out debug messages to stdout.
# This can be used to reduce the size of the hostapd considerably if debugging
# * ath10k
#
# For more details refer to:
-# http://wireless.kernel.org/en/users/Documentation/acs
+# https://wireless.wiki.kernel.org/en/users/documentation/acs
#
#CONFIG_ACS=y
# Multiband Operation support
-# These extentions facilitate efficient use of multiple frequency bands
+# These extensions facilitate efficient use of multiple frequency bands
# available to the AP and the devices that may associate with it.
#CONFIG_MBO=y
# Airtime policy support
CONFIG_AIRTIME_POLICY=y
-# Proxy ARP support
-#CONFIG_PROXYARP=y
-
# Override default value for the wpa_disable_eapol_key_retries configuration
# parameter. See that parameter in hostapd.conf for more details.
#CFLAGS += -DDEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES=1
+# Wired equivalent privacy (WEP)
+# WEP is an obsolete cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used for anything anymore. The
+# functionality needed to use WEP is available in the current hostapd
+# release under this optional build parameter. This functionality is subject to
+# be completely removed in a future release.
+#CONFIG_WEP=y
+
+# Remove all TKIP functionality
+# TKIP is an old cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used anymore. For now, the default hostapd
+# build includes this to allow mixed mode WPA+WPA2 networks to be enabled, but
+# that functionality is subject to be removed in the future.
+#CONFIG_NO_TKIP=y
+
+# Pre-Association Security Negotiation (PASN)
+# Experimental implementation based on IEEE P802.11z/D2.6 and the protocol
+# design is still subject to change. As such, this should not yet be enabled in
+# production use.
+#CONFIG_PASN=y
+
+# Device Provisioning Protocol (DPP) (also known as Wi-Fi Easy Connect)
+#CONFIG_DPP=y
+# DPP version 2 support
+#CONFIG_DPP2=y
+# DPP version 3 support (experimental and still changing; do not enable for
+# production use)
+#CONFIG_DPP3=y
+
# uBus IPC/RPC System
# Services can connect to the bus and provide methods
# that can be called by other services or clients.
# Driver interface for no driver (e.g., RADIUS server only)
#CONFIG_DRIVER_NONE=y
-# IEEE 802.11F/IAPP
-CONFIG_IAPP=y
-
# WPA2/IEEE 802.11i RSN pre-authentication
CONFIG_RSN_PREAUTH=y
-# IEEE 802.11w (management frame protection)
-#CONFIG_IEEE80211W=y
-
# Support Operating Channel Validation
CONFIG_OCV=y
# the IEEE 802.11 Management capability (e.g., FreeBSD/net80211)
#CONFIG_DRIVER_RADIUS_ACL=y
-# IEEE 802.11n (High Throughput) support
-CONFIG_IEEE80211N=y
-
# Wireless Network Management (IEEE Std 802.11v-2011)
# Note: This is experimental and not complete implementation.
CONFIG_WNM=y
CONFIG_IEEE80211AC=y
# IEEE 802.11ax HE support
+#CONFIG_IEEE80211AX=y
+
+# IEEE 802.11be EHT support
+# CONFIG_IEEE80211AX is mandatory for setting CONFIG_IEEE80211BE.
# Note: This is experimental and work in progress. The definitions are still
# subject to change and this should not be expected to interoperate with the
-# final IEEE 802.11ax version.
-#CONFIG_IEEE80211AX=y
+# final IEEE 802.11be version.
+#CONFIG_IEEE80211BE=y
+
+# Simultaneous Authentication of Equals (SAE), WPA3-Personal
+#CONFIG_SAE=y
+
+# SAE Public Key, WPA3-Personal
+#CONFIG_SAE_PK=y
# Remove debugging code that is printing out debug messages to stdout.
# This can be used to reduce the size of the hostapd considerably if debugging
# * ath10k
#
# For more details refer to:
-# http://wireless.kernel.org/en/users/Documentation/acs
+# https://wireless.wiki.kernel.org/en/users/documentation/acs
#
#CONFIG_ACS=y
# Multiband Operation support
-# These extentions facilitate efficient use of multiple frequency bands
+# These extensions facilitate efficient use of multiple frequency bands
# available to the AP and the devices that may associate with it.
#CONFIG_MBO=y
# Airtime policy support
CONFIG_AIRTIME_POLICY=y
-# Proxy ARP support
-CONFIG_PROXYARP=y
-
# Override default value for the wpa_disable_eapol_key_retries configuration
# parameter. See that parameter in hostapd.conf for more details.
#CFLAGS += -DDEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES=1
+# Wired equivalent privacy (WEP)
+# WEP is an obsolete cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used for anything anymore. The
+# functionality needed to use WEP is available in the current hostapd
+# release under this optional build parameter. This functionality is subject to
+# be completely removed in a future release.
+#CONFIG_WEP=y
+
+# Remove all TKIP functionality
+# TKIP is an old cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used anymore. For now, the default hostapd
+# build includes this to allow mixed mode WPA+WPA2 networks to be enabled, but
+# that functionality is subject to be removed in the future.
+#CONFIG_NO_TKIP=y
+
+# Pre-Association Security Negotiation (PASN)
+# Experimental implementation based on IEEE P802.11z/D2.6 and the protocol
+# design is still subject to change. As such, this should not yet be enabled in
+# production use.
+#CONFIG_PASN=y
+
+# Device Provisioning Protocol (DPP) (also known as Wi-Fi Easy Connect)
+#CONFIG_DPP=y
+# DPP version 2 support
+#CONFIG_DPP2=y
+# DPP version 3 support (experimental and still changing; do not enable for
+# production use)
+#CONFIG_DPP3=y
+
# uBus IPC/RPC System
# Services can connect to the bus and provide methods
# that can be called by other services or clients.
# Driver interface for no driver (e.g., RADIUS server only)
#CONFIG_DRIVER_NONE=y
-# IEEE 802.11F/IAPP
-#CONFIG_IAPP=y
-
# WPA2/IEEE 802.11i RSN pre-authentication
CONFIG_RSN_PREAUTH=y
-# IEEE 802.11w (management frame protection)
-#CONFIG_IEEE80211W=y
-
# Support Operating Channel Validation
#CONFIG_OCV=y
# the IEEE 802.11 Management capability (e.g., FreeBSD/net80211)
#CONFIG_DRIVER_RADIUS_ACL=y
-# IEEE 802.11n (High Throughput) support
-CONFIG_IEEE80211N=y
-
# Wireless Network Management (IEEE Std 802.11v-2011)
# Note: This is experimental and not complete implementation.
#CONFIG_WNM=y
CONFIG_IEEE80211AC=y
# IEEE 802.11ax HE support
+#CONFIG_IEEE80211AX=y
+
+# IEEE 802.11be EHT support
+# CONFIG_IEEE80211AX is mandatory for setting CONFIG_IEEE80211BE.
# Note: This is experimental and work in progress. The definitions are still
# subject to change and this should not be expected to interoperate with the
-# final IEEE 802.11ax version.
-#CONFIG_IEEE80211AX=y
+# final IEEE 802.11be version.
+#CONFIG_IEEE80211BE=y
+
+# Simultaneous Authentication of Equals (SAE), WPA3-Personal
+#CONFIG_SAE=y
+
+# SAE Public Key, WPA3-Personal
+#CONFIG_SAE_PK=y
# Remove debugging code that is printing out debug messages to stdout.
# This can be used to reduce the size of the hostapd considerably if debugging
# * ath10k
#
# For more details refer to:
-# http://wireless.kernel.org/en/users/Documentation/acs
+# https://wireless.wiki.kernel.org/en/users/documentation/acs
#
#CONFIG_ACS=y
# Multiband Operation support
-# These extentions facilitate efficient use of multiple frequency bands
+# These extensions facilitate efficient use of multiple frequency bands
# available to the AP and the devices that may associate with it.
#CONFIG_MBO=y
# Airtime policy support
#CONFIG_AIRTIME_POLICY=y
-# Proxy ARP support
-#CONFIG_PROXYARP=y
-
# Override default value for the wpa_disable_eapol_key_retries configuration
# parameter. See that parameter in hostapd.conf for more details.
#CFLAGS += -DDEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES=1
+# Wired equivalent privacy (WEP)
+# WEP is an obsolete cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used for anything anymore. The
+# functionality needed to use WEP is available in the current hostapd
+# release under this optional build parameter. This functionality is subject to
+# be completely removed in a future release.
+#CONFIG_WEP=y
+
+# Remove all TKIP functionality
+# TKIP is an old cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used anymore. For now, the default hostapd
+# build includes this to allow mixed mode WPA+WPA2 networks to be enabled, but
+# that functionality is subject to be removed in the future.
+#CONFIG_NO_TKIP=y
+
+# Pre-Association Security Negotiation (PASN)
+# Experimental implementation based on IEEE P802.11z/D2.6 and the protocol
+# design is still subject to change. As such, this should not yet be enabled in
+# production use.
+#CONFIG_PASN=y
+
+# Device Provisioning Protocol (DPP) (also known as Wi-Fi Easy Connect)
+#CONFIG_DPP=y
+# DPP version 2 support
+#CONFIG_DPP2=y
+# DPP version 3 support (experimental and still changing; do not enable for
+# production use)
+#CONFIG_DPP3=y
+
# uBus IPC/RPC System
# Services can connect to the bus and provide methods
# that can be called by other services or clients.
# EAP-TLS
#CONFIG_EAP_TLS=y
+# Enable EAP-TLSv1.3 support by default (currently disabled unless explicitly
+# enabled in network configuration)
+#CONFIG_EAP_TLSV1_3=y
# EAL-PEAP
#CONFIG_EAP_PEAP=y
# Support VHT overrides (disable VHT, mask MCS rates, etc.)
CONFIG_VHT_OVERRIDES=y
+# Support HE overrides
+CONFIG_HE_OVERRIDES=y
+
# Development testing
#CONFIG_EAPOL_TEST=y
# Simultaneous Authentication of Equals (SAE), WPA3-Personal
#CONFIG_SAE=y
-# Disable scan result processing (ap_mode=1) to save code size by about 1 kB.
+# SAE Public Key, WPA3-Personal
+#CONFIG_SAE_PK=y
+
+# Disable scan result processing (ap_scan=1) to save code size by about 1 kB.
# This can be used if ap_scan=1 mode is never enabled.
#CONFIG_NO_SCAN_PROCESSING=y
# bridge interfaces (commit 'bridge: respect RFC2863 operational state')').
CONFIG_NO_LINUX_PACKET_SOCKET_WAR=y
-# IEEE 802.11w (management frame protection), also known as PMF
-# Driver support is also needed for IEEE 802.11w.
-#CONFIG_IEEE80211W=y
-
# Support Operating Channel Validation
CONFIG_OCV=y
#PLATFORMSDKLIB="/opt/Program Files/Microsoft Platform SDK/Lib"
# Add support for new DBus control interface
-# (fi.w1.hostap.wpa_supplicant1)
+# (fi.w1.wpa_supplicant1)
#CONFIG_CTRL_IFACE_DBUS_NEW=y
# Add introspection support for new DBus control interface
# Requires glibc 2.25 to build, falls back to /dev/random if unavailable.
CONFIG_GETRANDOM=y
-# IEEE 802.11n (High Throughput) support (mainly for AP mode)
-#CONFIG_IEEE80211N=y
-
# IEEE 802.11ac (Very High Throughput) support (mainly for AP mode)
-# (depends on CONFIG_IEEE80211N)
#CONFIG_IEEE80211AC=y
+# IEEE 802.11ax HE support (mainly for AP mode)
+#CONFIG_IEEE80211AX=y
+
+# IEEE 802.11be EHT support (mainly for AP mode)
+# CONFIG_IEEE80211AX is mandatory for setting CONFIG_IEEE80211BE.
+# Note: This is experimental and work in progress. The definitions are still
+# subject to change and this should not be expected to interoperate with the
+# final IEEE 802.11be version.
+#CONFIG_IEEE80211BE=y
+
# Wireless Network Management (IEEE Std 802.11v-2011)
# Note: This is experimental and not complete implementation.
#CONFIG_WNM=y
#
# External password backend for testing purposes (developer use)
#CONFIG_EXT_PASSWORD_TEST=y
+# File-based backend to read passwords from an external file.
+#CONFIG_EXT_PASSWORD_FILE=y
# Enable Fast Session Transfer (FST)
#CONFIG_FST=y
# Experimental implementation of draft-harkins-owe-07.txt
#CONFIG_OWE=y
-# Device Provisioning Protocol (DPP)
-# This requires CONFIG_IEEE80211W=y to be enabled, too. (see
-# wpa_supplicant/README-DPP for details)
+# Device Provisioning Protocol (DPP) (also known as Wi-Fi Easy Connect)
#CONFIG_DPP=y
+# DPP version 2 support
+#CONFIG_DPP2=y
+# DPP version 3 support (experimental and still changing; do not enable for
+# production use)
+#CONFIG_DPP3=y
+
+# Wired equivalent privacy (WEP)
+# WEP is an obsolete cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used for anything anymore. The
+# functionality needed to use WEP is available in the current wpa_supplicant
+# release under this optional build parameter. This functionality is subject to
+# be completely removed in a future release.
+#CONFIG_WEP=y
+
+# Remove all TKIP functionality
+# TKIP is an old cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used anymore for anything else than a
+# backwards compatibility option as a group cipher when connecting to APs that
+# use WPA+WPA2 mixed mode. For now, the default wpa_supplicant build includes
+# support for this by default, but that functionality is subject to be removed
+# in the future.
+#CONFIG_NO_TKIP=y
+
+# Pre-Association Security Negotiation (PASN)
+# Experimental implementation based on IEEE P802.11z/D2.6 and the protocol
+# design is still subject to change. As such, this should not yet be enabled in
+# production use.
+#CONFIG_PASN=y
# uBus IPC/RPC System
# Services can connect to the bus and provide methods
# EAP-TLS
CONFIG_EAP_TLS=y
+# Enable EAP-TLSv1.3 support by default (currently disabled unless explicitly
+# enabled in network configuration)
+#CONFIG_EAP_TLSV1_3=y
# EAL-PEAP
CONFIG_EAP_PEAP=y
# Support VHT overrides (disable VHT, mask MCS rates, etc.)
CONFIG_VHT_OVERRIDES=y
+# Support HE overrides
+CONFIG_HE_OVERRIDES=y
+
# Development testing
#CONFIG_EAPOL_TEST=y
# Simultaneous Authentication of Equals (SAE), WPA3-Personal
#CONFIG_SAE=y
-# Disable scan result processing (ap_mode=1) to save code size by about 1 kB.
+# SAE Public Key, WPA3-Personal
+#CONFIG_SAE_PK=y
+
+# Disable scan result processing (ap_scan=1) to save code size by about 1 kB.
# This can be used if ap_scan=1 mode is never enabled.
#CONFIG_NO_SCAN_PROCESSING=y
# bridge interfaces (commit 'bridge: respect RFC2863 operational state')').
CONFIG_NO_LINUX_PACKET_SOCKET_WAR=y
-# IEEE 802.11w (management frame protection), also known as PMF
-# Driver support is also needed for IEEE 802.11w.
-#CONFIG_IEEE80211W=y
-
# Support Operating Channel Validation
CONFIG_OCV=y
#PLATFORMSDKLIB="/opt/Program Files/Microsoft Platform SDK/Lib"
# Add support for new DBus control interface
-# (fi.w1.hostap.wpa_supplicant1)
+# (fi.w1.wpa_supplicant1)
#CONFIG_CTRL_IFACE_DBUS_NEW=y
# Add introspection support for new DBus control interface
# Requires glibc 2.25 to build, falls back to /dev/random if unavailable.
CONFIG_GETRANDOM=y
-# IEEE 802.11n (High Throughput) support (mainly for AP mode)
-#CONFIG_IEEE80211N=y
-
# IEEE 802.11ac (Very High Throughput) support (mainly for AP mode)
-# (depends on CONFIG_IEEE80211N)
#CONFIG_IEEE80211AC=y
+# IEEE 802.11ax HE support (mainly for AP mode)
+#CONFIG_IEEE80211AX=y
+
+# IEEE 802.11be EHT support (mainly for AP mode)
+# CONFIG_IEEE80211AX is mandatory for setting CONFIG_IEEE80211BE.
+# Note: This is experimental and work in progress. The definitions are still
+# subject to change and this should not be expected to interoperate with the
+# final IEEE 802.11be version.
+#CONFIG_IEEE80211BE=y
+
# Wireless Network Management (IEEE Std 802.11v-2011)
# Note: This is experimental and not complete implementation.
CONFIG_WNM=y
#
# External password backend for testing purposes (developer use)
#CONFIG_EXT_PASSWORD_TEST=y
+# File-based backend to read passwords from an external file.
+#CONFIG_EXT_PASSWORD_FILE=y
# Enable Fast Session Transfer (FST)
#CONFIG_FST=y
# Experimental implementation of draft-harkins-owe-07.txt
#CONFIG_OWE=y
-# Device Provisioning Protocol (DPP)
-# This requires CONFIG_IEEE80211W=y to be enabled, too. (see
-# wpa_supplicant/README-DPP for details)
+# Device Provisioning Protocol (DPP) (also known as Wi-Fi Easy Connect)
#CONFIG_DPP=y
+# DPP version 2 support
+#CONFIG_DPP2=y
+# DPP version 3 support (experimental and still changing; do not enable for
+# production use)
+#CONFIG_DPP3=y
+
+# Wired equivalent privacy (WEP)
+# WEP is an obsolete cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used for anything anymore. The
+# functionality needed to use WEP is available in the current wpa_supplicant
+# release under this optional build parameter. This functionality is subject to
+# be completely removed in a future release.
+#CONFIG_WEP=y
+
+# Remove all TKIP functionality
+# TKIP is an old cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used anymore for anything else than a
+# backwards compatibility option as a group cipher when connecting to APs that
+# use WPA+WPA2 mixed mode. For now, the default wpa_supplicant build includes
+# support for this by default, but that functionality is subject to be removed
+# in the future.
+#CONFIG_NO_TKIP=y
+
+# Pre-Association Security Negotiation (PASN)
+# Experimental implementation based on IEEE P802.11z/D2.6 and the protocol
+# design is still subject to change. As such, this should not yet be enabled in
+# production use.
+#CONFIG_PASN=y
# uBus IPC/RPC System
# Services can connect to the bus and provide methods
# EAP-TLS
#CONFIG_EAP_TLS=y
+# Enable EAP-TLSv1.3 support by default (currently disabled unless explicitly
+# enabled in network configuration)
+#CONFIG_EAP_TLSV1_3=y
# EAL-PEAP
#CONFIG_EAP_PEAP=y
# Support VHT overrides (disable VHT, mask MCS rates, etc.)
CONFIG_VHT_OVERRIDES=y
+# Support HE overrides
+CONFIG_HE_OVERRIDES=y
+
# Development testing
#CONFIG_EAPOL_TEST=y
# Simultaneous Authentication of Equals (SAE), WPA3-Personal
#CONFIG_SAE=y
-# Disable scan result processing (ap_mode=1) to save code size by about 1 kB.
+# SAE Public Key, WPA3-Personal
+#CONFIG_SAE_PK=y
+
+# Disable scan result processing (ap_scan=1) to save code size by about 1 kB.
# This can be used if ap_scan=1 mode is never enabled.
#CONFIG_NO_SCAN_PROCESSING=y
# bridge interfaces (commit 'bridge: respect RFC2863 operational state')').
CONFIG_NO_LINUX_PACKET_SOCKET_WAR=y
-# IEEE 802.11w (management frame protection), also known as PMF
-# Driver support is also needed for IEEE 802.11w.
-#CONFIG_IEEE80211W=y
-
# Support Operating Channel Validation
-#CONFIG_OCV=y
+CONFIG_OCV=y
# Select TLS implementation
# openssl = OpenSSL (default)
#PLATFORMSDKLIB="/opt/Program Files/Microsoft Platform SDK/Lib"
# Add support for new DBus control interface
-# (fi.w1.hostap.wpa_supplicant1)
+# (fi.w1.wpa_supplicant1)
#CONFIG_CTRL_IFACE_DBUS_NEW=y
# Add introspection support for new DBus control interface
# Requires glibc 2.25 to build, falls back to /dev/random if unavailable.
CONFIG_GETRANDOM=y
-# IEEE 802.11n (High Throughput) support (mainly for AP mode)
-#CONFIG_IEEE80211N=y
-
# IEEE 802.11ac (Very High Throughput) support (mainly for AP mode)
-# (depends on CONFIG_IEEE80211N)
#CONFIG_IEEE80211AC=y
+# IEEE 802.11ax HE support (mainly for AP mode)
+#CONFIG_IEEE80211AX=y
+
+# IEEE 802.11be EHT support (mainly for AP mode)
+# CONFIG_IEEE80211AX is mandatory for setting CONFIG_IEEE80211BE.
+# Note: This is experimental and work in progress. The definitions are still
+# subject to change and this should not be expected to interoperate with the
+# final IEEE 802.11be version.
+#CONFIG_IEEE80211BE=y
+
# Wireless Network Management (IEEE Std 802.11v-2011)
# Note: This is experimental and not complete implementation.
#CONFIG_WNM=y
#
# External password backend for testing purposes (developer use)
#CONFIG_EXT_PASSWORD_TEST=y
+# File-based backend to read passwords from an external file.
+#CONFIG_EXT_PASSWORD_FILE=y
# Enable Fast Session Transfer (FST)
#CONFIG_FST=y
# Experimental implementation of draft-harkins-owe-07.txt
#CONFIG_OWE=y
-# Device Provisioning Protocol (DPP)
-# This requires CONFIG_IEEE80211W=y to be enabled, too. (see
-# wpa_supplicant/README-DPP for details)
+# Device Provisioning Protocol (DPP) (also known as Wi-Fi Easy Connect)
#CONFIG_DPP=y
+# DPP version 2 support
+#CONFIG_DPP2=y
+# DPP version 3 support (experimental and still changing; do not enable for
+# production use)
+#CONFIG_DPP3=y
+
+# Wired equivalent privacy (WEP)
+# WEP is an obsolete cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used for anything anymore. The
+# functionality needed to use WEP is available in the current wpa_supplicant
+# release under this optional build parameter. This functionality is subject to
+# be completely removed in a future release.
+#CONFIG_WEP=y
+
+# Remove all TKIP functionality
+# TKIP is an old cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used anymore for anything else than a
+# backwards compatibility option as a group cipher when connecting to APs that
+# use WPA+WPA2 mixed mode. For now, the default wpa_supplicant build includes
+# support for this by default, but that functionality is subject to be removed
+# in the future.
+#CONFIG_NO_TKIP=y
+
+# Pre-Association Security Negotiation (PASN)
+# Experimental implementation based on IEEE P802.11z/D2.6 and the protocol
+# design is still subject to change. As such, this should not yet be enabled in
+# production use.
+#CONFIG_PASN=y
# uBus IPC/RPC System
# Services can connect to the bus and provide methods
# EAP-TLS
CONFIG_EAP_TLS=y
+# Enable EAP-TLSv1.3 support by default (currently disabled unless explicitly
+# enabled in network configuration)
+#CONFIG_EAP_TLSV1_3=y
# EAL-PEAP
CONFIG_EAP_PEAP=y
# Support VHT overrides (disable VHT, mask MCS rates, etc.)
CONFIG_VHT_OVERRIDES=y
+# Support HE overrides
+CONFIG_HE_OVERRIDES=y
+
# Development testing
#CONFIG_EAPOL_TEST=y
# Simultaneous Authentication of Equals (SAE), WPA3-Personal
#CONFIG_SAE=y
-# Disable scan result processing (ap_mode=1) to save code size by about 1 kB.
+# SAE Public Key, WPA3-Personal
+#CONFIG_SAE_PK=y
+
+# Disable scan result processing (ap_scan=1) to save code size by about 1 kB.
# This can be used if ap_scan=1 mode is never enabled.
#CONFIG_NO_SCAN_PROCESSING=y
# bridge interfaces (commit 'bridge: respect RFC2863 operational state')').
CONFIG_NO_LINUX_PACKET_SOCKET_WAR=y
-# IEEE 802.11w (management frame protection), also known as PMF
-# Driver support is also needed for IEEE 802.11w.
-CONFIG_IEEE80211W=y
-
# Support Operating Channel Validation
#CONFIG_OCV=y
#PLATFORMSDKLIB="/opt/Program Files/Microsoft Platform SDK/Lib"
# Add support for new DBus control interface
-# (fi.w1.hostap.wpa_supplicant1)
+# (fi.w1.wpa_supplicant1)
#CONFIG_CTRL_IFACE_DBUS_NEW=y
# Add introspection support for new DBus control interface
# Requires glibc 2.25 to build, falls back to /dev/random if unavailable.
CONFIG_GETRANDOM=y
-# IEEE 802.11n (High Throughput) support (mainly for AP mode)
-#CONFIG_IEEE80211N=y
-
# IEEE 802.11ac (Very High Throughput) support (mainly for AP mode)
-# (depends on CONFIG_IEEE80211N)
#CONFIG_IEEE80211AC=y
+# IEEE 802.11ax HE support (mainly for AP mode)
+#CONFIG_IEEE80211AX=y
+
+# IEEE 802.11be EHT support (mainly for AP mode)
+# CONFIG_IEEE80211AX is mandatory for setting CONFIG_IEEE80211BE.
+# Note: This is experimental and work in progress. The definitions are still
+# subject to change and this should not be expected to interoperate with the
+# final IEEE 802.11be version.
+#CONFIG_IEEE80211BE=y
+
# Wireless Network Management (IEEE Std 802.11v-2011)
# Note: This is experimental and not complete implementation.
#CONFIG_WNM=y
#
# External password backend for testing purposes (developer use)
#CONFIG_EXT_PASSWORD_TEST=y
+# File-based backend to read passwords from an external file.
+#CONFIG_EXT_PASSWORD_FILE=y
# Enable Fast Session Transfer (FST)
#CONFIG_FST=y
# Experimental implementation of draft-harkins-owe-07.txt
#CONFIG_OWE=y
-# Device Provisioning Protocol (DPP)
-# This requires CONFIG_IEEE80211W=y to be enabled, too. (see
-# wpa_supplicant/README-DPP for details)
+# Device Provisioning Protocol (DPP) (also known as Wi-Fi Easy Connect)
#CONFIG_DPP=y
+# DPP version 2 support
+#CONFIG_DPP2=y
+# DPP version 3 support (experimental and still changing; do not enable for
+# production use)
+#CONFIG_DPP3=y
+
+# Wired equivalent privacy (WEP)
+# WEP is an obsolete cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used for anything anymore. The
+# functionality needed to use WEP is available in the current wpa_supplicant
+# release under this optional build parameter. This functionality is subject to
+# be completely removed in a future release.
+#CONFIG_WEP=y
+
+# Remove all TKIP functionality
+# TKIP is an old cryptographic data confidentiality algorithm that is not
+# considered secure. It should not be used anymore for anything else than a
+# backwards compatibility option as a group cipher when connecting to APs that
+# use WPA+WPA2 mixed mode. For now, the default wpa_supplicant build includes
+# support for this by default, but that functionality is subject to be removed
+# in the future.
+#CONFIG_NO_TKIP=y
+
+# Pre-Association Security Negotiation (PASN)
+# Experimental implementation based on IEEE P802.11z/D2.6 and the protocol
+# design is still subject to change. As such, this should not yet be enabled in
+# production use.
+#CONFIG_PASN=y
# uBus IPC/RPC System
# Services can connect to the bus and provide methods
if (ht40 == -1) {
if (!(pri_chan->flag & HOSTAPD_CHAN_HT40MINUS))
-@@ -2940,7 +2949,7 @@ static bool ibss_mesh_select_80_160mhz(s
+@@ -2941,7 +2950,7 @@ static bool ibss_mesh_select_80_160mhz(s
const struct wpa_ssid *ssid,
struct hostapd_hw_modes *mode,
struct hostapd_freq_params *freq,
static const int bw80[] = {
5180, 5260, 5500, 5580, 5660, 5745, 5825,
5955, 6035, 6115, 6195, 6275, 6355, 6435,
-@@ -2985,7 +2994,7 @@ static bool ibss_mesh_select_80_160mhz(s
+@@ -2986,7 +2995,7 @@ static bool ibss_mesh_select_80_160mhz(s
goto skip_80mhz;
/* Use 40 MHz if channel not usable */
goto skip_80mhz;
chwidth = CONF_OPER_CHWIDTH_80MHZ;
-@@ -2999,7 +3008,7 @@ static bool ibss_mesh_select_80_160mhz(s
+@@ -3000,7 +3009,7 @@ static bool ibss_mesh_select_80_160mhz(s
if ((mode->he_capab[ieee80211_mode].phy_cap[
HE_PHYCAP_CHANNEL_WIDTH_SET_IDX] &
HE_PHYCAP_CHANNEL_WIDTH_SET_160MHZ_IN_5G) && is_6ghz &&
for (j = 0; j < ARRAY_SIZE(bw160); j++) {
if (freq->freq == bw160[j]) {
chwidth = CONF_OPER_CHWIDTH_160MHZ;
-@@ -3027,10 +3036,12 @@ static bool ibss_mesh_select_80_160mhz(s
+@@ -3028,10 +3037,12 @@ static bool ibss_mesh_select_80_160mhz(s
if (!chan)
continue;
/* Found a suitable second segment for 80+80 */
chwidth = CONF_OPER_CHWIDTH_80P80MHZ;
-@@ -3085,6 +3096,7 @@ void ibss_mesh_setup_freq(struct wpa_sup
+@@ -3086,6 +3097,7 @@ void ibss_mesh_setup_freq(struct wpa_sup
int i, obss_scan = 1;
u8 channel;
bool is_6ghz, is_24ghz;
freq->freq = ssid->frequency;
-@@ -3133,9 +3145,9 @@ void ibss_mesh_setup_freq(struct wpa_sup
+@@ -3134,9 +3146,9 @@ void ibss_mesh_setup_freq(struct wpa_sup
freq->channel = channel;
/* Setup higher BW only for 5 GHz */
if (mode->mode == HOSTAPD_MODE_IEEE80211A) {
--- a/src/ap/dfs.c
+++ b/src/ap/dfs.c
-@@ -17,6 +17,7 @@
+@@ -18,6 +18,7 @@
#include "ap_drv_ops.h"
#include "drivers/driver.h"
#include "dfs.h"
enum dfs_channel_type {
-@@ -526,9 +527,14 @@ dfs_get_valid_channel(struct hostapd_ifa
+@@ -527,9 +528,14 @@ dfs_get_valid_channel(struct hostapd_ifa
int num_available_chandefs;
int chan_idx, chan_idx2;
int sec_chan_idx_80p80 = -1;
wpa_printf(MSG_DEBUG, "DFS: Selecting random channel");
*secondary_channel = 0;
*oper_centr_freq_seg0_idx = 0;
-@@ -548,8 +554,20 @@ dfs_get_valid_channel(struct hostapd_ifa
+@@ -549,8 +555,20 @@ dfs_get_valid_channel(struct hostapd_ifa
if (num_available_chandefs == 0)
return NULL;
chan_idx, num_available_chandefs);
--- a/src/drivers/driver_nl80211.c
+++ b/src/drivers/driver_nl80211.c
-@@ -11195,6 +11195,10 @@ static int nl80211_switch_channel(void *
+@@ -11289,6 +11289,10 @@ static int nl80211_switch_channel(void *
if (ret)
goto error;
--- a/src/ap/ieee802_11.c
+++ b/src/ap/ieee802_11.c
-@@ -4659,6 +4659,13 @@ static int add_associated_sta(struct hos
+@@ -4670,6 +4670,13 @@ static int add_associated_sta(struct hos
* drivers to accept the STA parameter configuration. Since this is
* after a new FT-over-DS exchange, a new TK has been derived, so key
* reinstallation is not a concern for this case.
*/
wpa_printf(MSG_DEBUG, "Add associated STA " MACSTR
" (added_unassoc=%d auth_alg=%u ft_over_ds=%u reassoc=%d authorized=%d ft_tk=%d fils_tk=%d)",
-@@ -4672,7 +4679,8 @@ static int add_associated_sta(struct hos
+@@ -4683,7 +4690,8 @@ static int add_associated_sta(struct hos
(!(sta->flags & WLAN_STA_AUTHORIZED) ||
(reassoc && sta->ft_over_ds && sta->auth_alg == WLAN_AUTH_FT) ||
(!wpa_auth_sta_ft_tk_already_set(sta->wpa_sm) &&
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Wed, 28 Jul 2021 05:43:29 +0200
-Subject: [PATCH] ndisc_snoop: call dl_list_del before freeing ipv6 addresses
-
-Fixes a segmentation fault on sta disconnect
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/src/ap/ndisc_snoop.c
-+++ b/src/ap/ndisc_snoop.c
-@@ -61,6 +61,7 @@ void sta_ip6addr_del(struct hostapd_data
- dl_list_for_each_safe(ip6addr, prev, &sta->ip6addr, struct ip6addr,
- list) {
- hostapd_drv_br_delete_ip_neigh(hapd, 6, (u8 *) &ip6addr->addr);
-+ dl_list_del(&ip6addr->list);
- os_free(ip6addr);
- }
- }
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Wed, 28 Jul 2021 05:49:46 +0200
-Subject: [PATCH] driver_nl80211: rewrite neigh code to not depend on
- libnl3-route
-
-Removes an unnecessary dependency and also makes the code smaller
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/src/drivers/driver_nl80211.c
-+++ b/src/drivers/driver_nl80211.c
-@@ -18,9 +18,6 @@
- #include <netlink/genl/genl.h>
- #include <netlink/genl/ctrl.h>
- #include <netlink/genl/family.h>
--#ifdef CONFIG_LIBNL3_ROUTE
--#include <netlink/route/neighbour.h>
--#endif /* CONFIG_LIBNL3_ROUTE */
- #include <linux/rtnetlink.h>
- #include <netpacket/packet.h>
- #include <linux/errqueue.h>
-@@ -5859,26 +5856,29 @@ fail:
-
- static void rtnl_neigh_delete_fdb_entry(struct i802_bss *bss, const u8 *addr)
- {
--#ifdef CONFIG_LIBNL3_ROUTE
- struct wpa_driver_nl80211_data *drv = bss->drv;
-- struct rtnl_neigh *rn;
-- struct nl_addr *nl_addr;
-+ struct ndmsg nhdr = {
-+ .ndm_state = NUD_PERMANENT,
-+ .ndm_ifindex = bss->ifindex,
-+ .ndm_family = AF_BRIDGE,
-+ };
-+ struct nl_msg *msg;
- int err;
-
-- rn = rtnl_neigh_alloc();
-- if (!rn)
-+ msg = nlmsg_alloc_simple(RTM_DELNEIGH, NLM_F_CREATE);
-+ if (!msg)
- return;
-
-- rtnl_neigh_set_family(rn, AF_BRIDGE);
-- rtnl_neigh_set_ifindex(rn, bss->ifindex);
-- nl_addr = nl_addr_build(AF_BRIDGE, (void *) addr, ETH_ALEN);
-- if (!nl_addr) {
-- rtnl_neigh_put(rn);
-- return;
-- }
-- rtnl_neigh_set_lladdr(rn, nl_addr);
-+ if (nlmsg_append(msg, &nhdr, sizeof(nhdr), NLMSG_ALIGNTO) < 0)
-+ goto errout;
-+
-+ if (nla_put(msg, NDA_LLADDR, ETH_ALEN, (void *)addr))
-+ goto errout;
-+
-+ if (nl_send_auto_complete(drv->rtnl_sk, msg) < 0)
-+ goto errout;
-
-- err = rtnl_neigh_delete(drv->rtnl_sk, rn, 0);
-+ err = nl_wait_for_ack(drv->rtnl_sk);
- if (err < 0) {
- wpa_printf(MSG_DEBUG, "nl80211: bridge FDB entry delete for "
- MACSTR " ifindex=%d failed: %s", MAC2STR(addr),
-@@ -5888,9 +5888,8 @@ static void rtnl_neigh_delete_fdb_entry(
- MACSTR, MAC2STR(addr));
- }
-
-- nl_addr_put(nl_addr);
-- rtnl_neigh_put(rn);
--#endif /* CONFIG_LIBNL3_ROUTE */
-+errout:
-+ nlmsg_free(msg);
- }
-
-
-@@ -8615,7 +8614,6 @@ static void *i802_init(struct hostapd_da
- (params->num_bridge == 0 || !params->bridge[0]))
- add_ifidx(drv, br_ifindex, drv->ifindex);
-
--#ifdef CONFIG_LIBNL3_ROUTE
- if (bss->added_if_into_bridge || bss->already_in_bridge) {
- int err;
-
-@@ -8632,7 +8630,6 @@ static void *i802_init(struct hostapd_da
- goto failed;
- }
- }
--#endif /* CONFIG_LIBNL3_ROUTE */
-
- if (drv->capa.flags2 & WPA_DRIVER_FLAGS2_CONTROL_PORT_RX) {
- wpa_printf(MSG_DEBUG,
-@@ -12071,13 +12068,14 @@ static int wpa_driver_br_add_ip_neigh(vo
- const u8 *ipaddr, int prefixlen,
- const u8 *addr)
- {
--#ifdef CONFIG_LIBNL3_ROUTE
- struct i802_bss *bss = priv;
- struct wpa_driver_nl80211_data *drv = bss->drv;
-- struct rtnl_neigh *rn;
-- struct nl_addr *nl_ipaddr = NULL;
-- struct nl_addr *nl_lladdr = NULL;
-- int family, addrsize;
-+ struct ndmsg nhdr = {
-+ .ndm_state = NUD_PERMANENT,
-+ .ndm_ifindex = bss->br_ifindex,
-+ };
-+ struct nl_msg *msg;
-+ int addrsize;
- int res;
-
- if (!ipaddr || prefixlen == 0 || !addr)
-@@ -12096,85 +12094,66 @@ static int wpa_driver_br_add_ip_neigh(vo
- }
-
- if (version == 4) {
-- family = AF_INET;
-+ nhdr.ndm_family = AF_INET;
- addrsize = 4;
- } else if (version == 6) {
-- family = AF_INET6;
-+ nhdr.ndm_family = AF_INET6;
- addrsize = 16;
- } else {
- return -EINVAL;
- }
-
-- rn = rtnl_neigh_alloc();
-- if (rn == NULL)
-+ msg = nlmsg_alloc_simple(RTM_NEWNEIGH, NLM_F_CREATE);
-+ if (!msg)
- return -ENOMEM;
-
-- /* set the destination ip address for neigh */
-- nl_ipaddr = nl_addr_build(family, (void *) ipaddr, addrsize);
-- if (nl_ipaddr == NULL) {
-- wpa_printf(MSG_DEBUG, "nl80211: nl_ipaddr build failed");
-- res = -ENOMEM;
-+ res = -ENOMEM;
-+ if (nlmsg_append(msg, &nhdr, sizeof(nhdr), NLMSG_ALIGNTO) < 0)
- goto errout;
-- }
-- nl_addr_set_prefixlen(nl_ipaddr, prefixlen);
-- res = rtnl_neigh_set_dst(rn, nl_ipaddr);
-- if (res) {
-- wpa_printf(MSG_DEBUG,
-- "nl80211: neigh set destination addr failed");
-+
-+ if (nla_put(msg, NDA_DST, addrsize, (void *)ipaddr))
- goto errout;
-- }
-
-- /* set the corresponding lladdr for neigh */
-- nl_lladdr = nl_addr_build(AF_BRIDGE, (u8 *) addr, ETH_ALEN);
-- if (nl_lladdr == NULL) {
-- wpa_printf(MSG_DEBUG, "nl80211: neigh set lladdr failed");
-- res = -ENOMEM;
-+ if (nla_put(msg, NDA_LLADDR, ETH_ALEN, (void *)addr))
- goto errout;
-- }
-- rtnl_neigh_set_lladdr(rn, nl_lladdr);
-
-- rtnl_neigh_set_ifindex(rn, bss->br_ifindex);
-- rtnl_neigh_set_state(rn, NUD_PERMANENT);
-+ res = nl_send_auto_complete(drv->rtnl_sk, msg);
-+ if (res < 0)
-+ goto errout;
-
-- res = rtnl_neigh_add(drv->rtnl_sk, rn, NLM_F_CREATE);
-+ res = nl_wait_for_ack(drv->rtnl_sk);
- if (res) {
- wpa_printf(MSG_DEBUG,
- "nl80211: Adding bridge ip neigh failed: %s",
- nl_geterror(res));
- }
- errout:
-- if (nl_lladdr)
-- nl_addr_put(nl_lladdr);
-- if (nl_ipaddr)
-- nl_addr_put(nl_ipaddr);
-- if (rn)
-- rtnl_neigh_put(rn);
-+ nlmsg_free(msg);
- return res;
--#else /* CONFIG_LIBNL3_ROUTE */
-- return -1;
--#endif /* CONFIG_LIBNL3_ROUTE */
- }
-
-
- static int wpa_driver_br_delete_ip_neigh(void *priv, u8 version,
- const u8 *ipaddr)
- {
--#ifdef CONFIG_LIBNL3_ROUTE
- struct i802_bss *bss = priv;
- struct wpa_driver_nl80211_data *drv = bss->drv;
-- struct rtnl_neigh *rn;
-- struct nl_addr *nl_ipaddr;
-- int family, addrsize;
-+ struct ndmsg nhdr = {
-+ .ndm_state = NUD_PERMANENT,
-+ .ndm_ifindex = bss->br_ifindex,
-+ };
-+ struct nl_msg *msg;
-+ int addrsize;
- int res;
-
- if (!ipaddr)
- return -EINVAL;
-
- if (version == 4) {
-- family = AF_INET;
-+ nhdr.ndm_family = AF_INET;
- addrsize = 4;
- } else if (version == 6) {
-- family = AF_INET6;
-+ nhdr.ndm_family = AF_INET6;
- addrsize = 16;
- } else {
- return -EINVAL;
-@@ -12192,41 +12171,30 @@ static int wpa_driver_br_delete_ip_neigh
- return -1;
- }
-
-- rn = rtnl_neigh_alloc();
-- if (rn == NULL)
-+ msg = nlmsg_alloc_simple(RTM_DELNEIGH, NLM_F_CREATE);
-+ if (!msg)
- return -ENOMEM;
-
-- /* set the destination ip address for neigh */
-- nl_ipaddr = nl_addr_build(family, (void *) ipaddr, addrsize);
-- if (nl_ipaddr == NULL) {
-- wpa_printf(MSG_DEBUG, "nl80211: nl_ipaddr build failed");
-- res = -ENOMEM;
-+ res = -ENOMEM;
-+ if (nlmsg_append(msg, &nhdr, sizeof(nhdr), NLMSG_ALIGNTO) < 0)
- goto errout;
-- }
-- res = rtnl_neigh_set_dst(rn, nl_ipaddr);
-- if (res) {
-- wpa_printf(MSG_DEBUG,
-- "nl80211: neigh set destination addr failed");
-+
-+ if (nla_put(msg, NDA_DST, addrsize, (void *)ipaddr))
- goto errout;
-- }
-
-- rtnl_neigh_set_ifindex(rn, bss->br_ifindex);
-+ res = nl_send_auto_complete(drv->rtnl_sk, msg);
-+ if (res < 0)
-+ goto errout;
-
-- res = rtnl_neigh_delete(drv->rtnl_sk, rn, 0);
-+ res = nl_wait_for_ack(drv->rtnl_sk);
- if (res) {
- wpa_printf(MSG_DEBUG,
- "nl80211: Deleting bridge ip neigh failed: %s",
- nl_geterror(res));
- }
- errout:
-- if (nl_ipaddr)
-- nl_addr_put(nl_ipaddr);
-- if (rn)
-- rtnl_neigh_put(rn);
-+ nlmsg_free(msg);
- return res;
--#else /* CONFIG_LIBNL3_ROUTE */
-- return -1;
--#endif /* CONFIG_LIBNL3_ROUTE */
- }
-
-
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Mon, 18 Feb 2019 12:57:11 +0100
-Subject: [PATCH] mesh: allow processing authentication frames in blocked state
-
-If authentication fails repeatedly e.g. because of a weak signal, the link
-can end up in blocked state. If one of the nodes tries to establish a link
-again before it is unblocked on the other side, it will block the link to
-that other side. The same happens on the other side when it unblocks the
-link. In that scenario, the link never recovers on its own.
-
-To fix this, allow restarting authentication even if the link is in blocked
-state, but don't initiate the attempt until the blocked period is over.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/src/ap/ieee802_11.c
-+++ b/src/ap/ieee802_11.c
-@@ -3032,15 +3032,6 @@ static void handle_auth(struct hostapd_d
- seq_ctrl);
- return;
- }
--#ifdef CONFIG_MESH
-- if ((hapd->conf->mesh & MESH_ENABLED) &&
-- sta->plink_state == PLINK_BLOCKED) {
-- wpa_printf(MSG_DEBUG, "Mesh peer " MACSTR
-- " is blocked - drop Authentication frame",
-- MAC2STR(sa));
-- return;
-- }
--#endif /* CONFIG_MESH */
- #ifdef CONFIG_PASN
- if (auth_alg == WLAN_AUTH_PASN &&
- (sta->flags & WLAN_STA_ASSOC)) {
--- a/src/ap/hostapd.c
+++ b/src/ap/hostapd.c
-@@ -3646,6 +3646,8 @@ int hostapd_remove_iface(struct hapd_int
+@@ -3960,6 +3960,8 @@ int hostapd_remove_iface(struct hapd_int
void hostapd_new_assoc_sta(struct hostapd_data *hapd, struct sta_info *sta,
int reassoc)
{
if (hapd->tkip_countermeasures) {
hostapd_drv_sta_deauth(hapd, sta->addr,
WLAN_REASON_MICHAEL_MIC_FAILURE);
-@@ -3653,10 +3655,16 @@ void hostapd_new_assoc_sta(struct hostap
+@@ -3967,10 +3969,16 @@ void hostapd_new_assoc_sta(struct hostap
}
#ifdef CONFIG_IEEE80211BE
sta->post_csa_sa_query = 0;
--- a/src/ap/sta_info.c
+++ b/src/ap/sta_info.c
-@@ -1412,9 +1412,6 @@ bool ap_sta_set_authorized_flag(struct h
+@@ -1477,9 +1477,6 @@ bool ap_sta_set_authorized_flag(struct h
mld_assoc_link_id = -2;
}
#endif /* CONFIG_IEEE80211BE */
--- a/src/drivers/driver.h
+++ b/src/drivers/driver.h
-@@ -2340,6 +2340,9 @@ struct wpa_driver_capa {
+@@ -2355,6 +2355,9 @@ struct wpa_driver_capa {
/** Maximum number of iterations in a single scan plan */
u32 max_sched_scan_plan_iterations;
--- a/src/drivers/driver_nl80211_capa.c
+++ b/src/drivers/driver_nl80211_capa.c
-@@ -972,6 +972,10 @@ static int wiphy_info_handler(struct nl_
+@@ -976,6 +976,10 @@ static int wiphy_info_handler(struct nl_
nla_get_u32(tb[NL80211_ATTR_MAX_SCAN_PLAN_ITERATIONS]);
}
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 1 May 2024 18:55:24 +0200
+Subject: [PATCH] AP: add missing null pointer check in hostapd_free_hapd_data
+
+When called from wpa_supplicant, iface->interfaces can be NULL
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/src/ap/hostapd.c
++++ b/src/ap/hostapd.c
+@@ -485,7 +485,7 @@ void hostapd_free_hapd_data(struct hosta
+ struct hapd_interfaces *ifaces = hapd->iface->interfaces;
+ size_t i;
+
+- for (i = 0; i < ifaces->count; i++) {
++ for (i = 0; ifaces && i < ifaces->count; i++) {
+ struct hostapd_iface *iface = ifaces->iface[i];
+ size_t j;
+
ifdef CONFIG_RADIUS_SERVER
CFLAGS += -DRADIUS_SERVER
-@@ -1341,7 +1426,9 @@ NOBJS += ../src/utils/trace.o
+@@ -1342,7 +1427,9 @@ NOBJS += ../src/utils/trace.o
endif
HOBJS += hlr_auc_gw.o ../src/utils/common.o ../src/utils/wpa_debug.o ../src/utils/os_$(CONFIG_OS).o ../src/utils/wpabuf.o ../src/crypto/milenage.o
ifdef CONFIG_INTERNAL_AES
HOBJS += ../src/crypto/aes-internal.o
HOBJS += ../src/crypto/aes-internal-enc.o
-@@ -1364,13 +1451,17 @@ SOBJS += ../src/common/sae.o
+@@ -1365,13 +1452,17 @@ SOBJS += ../src/common/sae.o
SOBJS += ../src/common/sae_pk.o
SOBJS += ../src/common/dragonfly.o
SOBJS += $(AESOBJS)
+{
+ #if !defined(MBEDTLS_USE_PSA_CRYPTO) /* XXX: (not extracted for PSA crypto) */
+ #if defined(MBEDTLS_SSL_PROTO_TLS1_3)
-+ if (tls_version == MBEDTLS_SSL_VERSION_TLS1_3)
++ if (mbedtls_ssl_get_version_number(ssl) == MBEDTLS_SSL_VERSION_TLS1_3)
+ return 0; /* (calculation not extracted) */
+ #endif /* MBEDTLS_SSL_PROTO_TLS1_3 */
+
CONFIG_SIM_SIMULATOR=y
--- a/wpa_supplicant/Makefile
+++ b/wpa_supplicant/Makefile
-@@ -1229,6 +1229,29 @@ endif
+@@ -1230,6 +1230,29 @@ endif
CFLAGS += -DTLS_DEFAULT_CIPHERS=\"$(CONFIG_TLS_DEFAULT_CIPHERS)\"
endif
ifeq ($(CONFIG_TLS), gnutls)
ifndef CONFIG_CRYPTO
# default to libgcrypt
-@@ -1421,9 +1444,11 @@ endif
+@@ -1422,9 +1445,11 @@ endif
ifneq ($(CONFIG_TLS), openssl)
ifneq ($(CONFIG_TLS), wolfssl)
ifdef CONFIG_OPENSSL_INTERNAL_AES_WRAP
# Seems to be needed at least with BoringSSL
NEED_INTERNAL_AES_WRAP=y
-@@ -1437,9 +1462,11 @@ endif
+@@ -1438,9 +1463,11 @@ endif
ifdef NEED_INTERNAL_AES_WRAP
ifneq ($(CONFIG_TLS), linux)
ifdef NEED_AES_EAX
AESOBJS += ../src/crypto/aes-eax.o
NEED_AES_CTR=y
-@@ -1449,35 +1476,45 @@ AESOBJS += ../src/crypto/aes-siv.o
+@@ -1450,35 +1477,45 @@ AESOBJS += ../src/crypto/aes-siv.o
NEED_AES_CTR=y
endif
ifdef NEED_AES_CTR
ifdef NEED_AES_ENC
ifdef CONFIG_INTERNAL_AES
AESOBJS += ../src/crypto/aes-internal-enc.o
-@@ -1492,12 +1529,16 @@ ifneq ($(CONFIG_TLS), openssl)
+@@ -1493,12 +1530,16 @@ ifneq ($(CONFIG_TLS), openssl)
ifneq ($(CONFIG_TLS), linux)
ifneq ($(CONFIG_TLS), gnutls)
ifneq ($(CONFIG_TLS), wolfssl)
ifdef CONFIG_INTERNAL_SHA1
SHA1OBJS += ../src/crypto/sha1-internal.o
ifdef NEED_FIPS186_2_PRF
-@@ -1509,29 +1550,37 @@ CFLAGS += -DCONFIG_NO_PBKDF2
+@@ -1510,29 +1551,37 @@ CFLAGS += -DCONFIG_NO_PBKDF2
else
ifneq ($(CONFIG_TLS), openssl)
ifneq ($(CONFIG_TLS), wolfssl)
ifdef NEED_MD5
ifdef CONFIG_INTERNAL_MD5
MD5OBJS += ../src/crypto/md5-internal.o
-@@ -1586,12 +1635,17 @@ ifneq ($(CONFIG_TLS), openssl)
+@@ -1587,12 +1636,17 @@ ifneq ($(CONFIG_TLS), openssl)
ifneq ($(CONFIG_TLS), linux)
ifneq ($(CONFIG_TLS), gnutls)
ifneq ($(CONFIG_TLS), wolfssl)
ifdef CONFIG_INTERNAL_SHA256
SHA256OBJS += ../src/crypto/sha256-internal.o
endif
-@@ -1604,50 +1658,68 @@ CFLAGS += -DCONFIG_INTERNAL_SHA512
+@@ -1605,50 +1659,68 @@ CFLAGS += -DCONFIG_INTERNAL_SHA512
SHA256OBJS += ../src/crypto/sha512-internal.o
endif
ifdef NEED_TLS_PRF_SHA256
ifdef NEED_ASN1
OBJS += ../src/tls/asn1.o
-@@ -1822,10 +1894,12 @@ ifdef CONFIG_FIPS
+@@ -1823,10 +1895,12 @@ ifdef CONFIG_FIPS
CFLAGS += -DCONFIG_FIPS
ifneq ($(CONFIG_TLS), openssl)
ifneq ($(CONFIG_TLS), wolfssl)
--- a/wpa_supplicant/Makefile
+++ b/wpa_supplicant/Makefile
-@@ -1240,10 +1240,6 @@ endif
+@@ -1241,10 +1241,6 @@ endif
OBJS += ../src/crypto/crypto_$(CONFIG_CRYPTO).o
OBJS_p += ../src/crypto/crypto_$(CONFIG_CRYPTO).o
OBJS_priv += ../src/crypto/crypto_$(CONFIG_CRYPTO).o
+ if tls.startswith("mbed TLS"):
+ raise HwsimSkip("TLS v1.3 not supported")
ok = ['run=OpenSSL 1.1.1', 'run=OpenSSL 3.0', 'run=OpenSSL 3.1',
- 'run=OpenSSL 3.2', 'wolfSSL']
+ 'run=OpenSSL 3.2', 'run=OpenSSL 3.3', 'wolfSSL']
for s in ok:
@@ -122,11 +161,15 @@ def check_pkcs12_support(dev):
# raise HwsimSkip("PKCS#12 not supported with this TLS library: " + tls)
ca_cert="auth_serv/rsa3072-ca.pem",
--- a/tests/hwsim/test_wpas_ctrl.py
+++ b/tests/hwsim/test_wpas_ctrl.py
-@@ -1842,7 +1842,7 @@ def _test_wpas_ctrl_oom(dev):
+@@ -1856,7 +1856,7 @@ def _test_wpas_ctrl_oom(dev):
tls = dev[0].request("GET tls_library")
if not tls.startswith("internal"):
tests.append(('NFC_GET_HANDOVER_SEL NDEF P2P-CR-TAG', 'FAIL',
if (need_more_data) {
--- a/wpa_supplicant/Makefile
+++ b/wpa_supplicant/Makefile
-@@ -1188,6 +1188,7 @@ TLS_FUNCS=y
+@@ -1189,6 +1189,7 @@ TLS_FUNCS=y
endif
ifeq ($(CONFIG_TLS), wolfssl)
ifdef TLS_FUNCS
CFLAGS += -DWOLFSSL_DER_LOAD
OBJS += ../src/crypto/tls_wolfssl.o
-@@ -1203,6 +1204,7 @@ LIBS_p += -lwolfssl -lm
+@@ -1204,6 +1205,7 @@ LIBS_p += -lwolfssl -lm
endif
ifeq ($(CONFIG_TLS), openssl)
CFLAGS += -DCRYPTO_RSA_OAEP_SHA256
ifdef TLS_FUNCS
CFLAGS += -DEAP_TLS_OPENSSL
-@@ -1230,6 +1232,7 @@ CFLAGS += -DTLS_DEFAULT_CIPHERS=\"$(CONF
+@@ -1231,6 +1233,7 @@ CFLAGS += -DTLS_DEFAULT_CIPHERS=\"$(CONF
endif
ifeq ($(CONFIG_TLS), mbedtls)
ifndef CONFIG_CRYPTO
CONFIG_CRYPTO=mbedtls
endif
-@@ -1249,6 +1252,7 @@ endif
+@@ -1250,6 +1253,7 @@ endif
endif
ifeq ($(CONFIG_TLS), gnutls)
ifndef CONFIG_CRYPTO
# default to libgcrypt
CONFIG_CRYPTO=gnutls
-@@ -1279,6 +1283,7 @@ endif
+@@ -1280,6 +1284,7 @@ endif
endif
ifeq ($(CONFIG_TLS), internal)
ifndef CONFIG_CRYPTO
CONFIG_CRYPTO=internal
endif
-@@ -1359,6 +1364,7 @@ endif
+@@ -1360,6 +1365,7 @@ endif
endif
ifeq ($(CONFIG_TLS), linux)
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 14 Sep 2023 11:28:03 +0200
-Subject: [PATCH] driver_nl80211: update drv->ifindex on removing the first
- BSS
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/src/drivers/driver_nl80211.c
-+++ b/src/drivers/driver_nl80211.c
-@@ -8985,6 +8985,7 @@ static int wpa_driver_nl80211_if_remove(
- if (drv->first_bss->next) {
- drv->first_bss = drv->first_bss->next;
- drv->ctx = drv->first_bss->ctx;
-+ drv->ifindex = drv->first_bss->ifindex;
- os_free(bss);
- } else {
- wpa_printf(MSG_DEBUG, "nl80211: No second BSS to reassign context to");
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Mon, 18 Sep 2023 16:47:41 +0200
-Subject: [PATCH] nl80211: move nl80211_put_freq_params call outside of
- 802.11ax #ifdef
-
-The relevance of this call is not specific to 802.11ax, so it should be done
-even with CONFIG_IEEE80211AX disabled.
-
-Fixes: b3921db426ea ("nl80211: Add frequency info in start AP command")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/src/drivers/driver_nl80211.c
-+++ b/src/drivers/driver_nl80211.c
-@@ -5315,6 +5315,9 @@ static int wpa_driver_nl80211_set_ap(voi
- nla_nest_end(msg, ftm);
- }
-
-+ if (params->freq && nl80211_put_freq_params(msg, params->freq) < 0)
-+ goto fail;
-+
- #ifdef CONFIG_IEEE80211AX
- if (params->he_spr_ctrl) {
- struct nlattr *spr;
-@@ -5349,9 +5352,6 @@ static int wpa_driver_nl80211_set_ap(voi
- nla_nest_end(msg, spr);
- }
-
-- if (params->freq && nl80211_put_freq_params(msg, params->freq) < 0)
-- goto fail;
--
- if (params->freq && params->freq->he_enabled &&
- nl80211_attr_supported(drv, NL80211_ATTR_HE_BSS_COLOR)) {
- struct nlattr *bss_color;
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Wed, 20 Sep 2023 13:41:10 +0200
-Subject: [PATCH] hostapd: cancel channel_list_update_timeout in
- hostapd_cleanup_iface_partial
-
-Fixes a crash when disabling an interface during channel list update
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/src/ap/hostapd.c
-+++ b/src/ap/hostapd.c
-@@ -656,6 +656,7 @@ static void sta_track_deinit(struct host
- void hostapd_cleanup_iface_partial(struct hostapd_iface *iface)
- {
- wpa_printf(MSG_DEBUG, "%s(%p)", __func__, iface);
-+ eloop_cancel_timeout(channel_list_update_timeout, iface, NULL);
- #ifdef NEED_AP_MLME
- hostapd_stop_setup_timers(iface);
- #endif /* NEED_AP_MLME */
-@@ -685,7 +686,6 @@ void hostapd_cleanup_iface_partial(struc
- static void hostapd_cleanup_iface(struct hostapd_iface *iface)
- {
- wpa_printf(MSG_DEBUG, "%s(%p)", __func__, iface);
-- eloop_cancel_timeout(channel_list_update_timeout, iface, NULL);
- eloop_cancel_timeout(hostapd_interface_setup_failure_handler, iface,
- NULL);
-
include ../src/build.rules
ifdef LIBS
-@@ -199,7 +200,8 @@ endif
+@@ -200,7 +201,8 @@ endif
ifdef CONFIG_NO_VLAN
CFLAGS += -DCONFIG_NO_VLAN
OBJS += ../src/ap/vlan_init.o
OBJS += ../src/ap/vlan_ifconfig.o
OBJS += ../src/ap/vlan.o
-@@ -358,10 +360,14 @@ CFLAGS += -DCONFIG_MBO
+@@ -359,10 +361,14 @@ CFLAGS += -DCONFIG_MBO
OBJS += ../src/ap/mbo_ap.o
endif
LIBS += $(DRV_AP_LIBS)
ifdef CONFIG_L2_PACKET
-@@ -1392,6 +1398,12 @@ install: $(addprefix $(DESTDIR)$(BINDIR)
+@@ -1393,6 +1399,12 @@ install: $(addprefix $(DESTDIR)$(BINDIR)
_OBJS_VAR := OBJS
include ../src/objs.mk
hostapd: $(OBJS)
$(Q)$(CC) $(LDFLAGS) -o hostapd $(OBJS) $(LIBS)
@$(E) " LD " $@
-@@ -1472,6 +1484,12 @@ include ../src/objs.mk
+@@ -1473,6 +1485,12 @@ include ../src/objs.mk
_OBJS_VAR := SOBJS
include ../src/objs.mk
@$(E) " LD " $@
--- a/hostapd/main.c
+++ b/hostapd/main.c
-@@ -705,6 +705,11 @@ fail:
+@@ -692,6 +692,11 @@ fail:
return -1;
}
#ifdef CONFIG_WPS
static int gen_uuid(const char *txt_addr)
-@@ -798,6 +803,8 @@ int main(int argc, char *argv[])
+@@ -808,6 +813,8 @@ int main(int argc, char *argv[])
return -1;
#endif /* CONFIG_DPP */
if (c < 0)
--- a/src/ap/drv_callbacks.c
+++ b/src/ap/drv_callbacks.c
-@@ -2341,8 +2341,8 @@ err:
- #endif /* CONFIG_OWE */
+@@ -2383,8 +2383,8 @@ static void hostapd_eapol_tx_status(stru
+ #endif /* NEED_AP_MLME */
-void wpa_supplicant_event(void *ctx, enum wpa_event_type event,
{
struct hostapd_data *hapd = ctx;
struct sta_info *sta;
-@@ -2674,7 +2674,7 @@ void wpa_supplicant_event(void *ctx, enu
+@@ -2737,7 +2737,7 @@ void wpa_supplicant_event(void *ctx, enu
}
struct hapd_interfaces *interfaces = ctx;
--- a/src/drivers/driver.h
+++ b/src/drivers/driver.h
-@@ -6763,8 +6763,8 @@ union wpa_event_data {
+@@ -6843,8 +6843,8 @@ union wpa_event_data {
* Driver wrapper code should call this function whenever an event is received
* from the driver.
*/
/**
* wpa_supplicant_event_global - Report a driver event for wpa_supplicant
-@@ -6776,7 +6776,7 @@ void wpa_supplicant_event(void *ctx, enu
+@@ -6856,7 +6856,7 @@ void wpa_supplicant_event(void *ctx, enu
* Same as wpa_supplicant_event(), but we search for the interface in
* wpa_global.
*/
include ../src/build.rules
ifdef CONFIG_BUILD_PASN_SO
-@@ -388,7 +389,9 @@ endif
+@@ -389,7 +390,9 @@ endif
ifdef CONFIG_IBSS_RSN
NEED_RSN_AUTHENTICATOR=y
CFLAGS += -DCONFIG_IBSS_RSN
OBJS += ibss_rsn.o
endif
-@@ -980,6 +983,10 @@ ifdef CONFIG_DYNAMIC_EAP_METHODS
+@@ -981,6 +984,10 @@ ifdef CONFIG_DYNAMIC_EAP_METHODS
CFLAGS += -DCONFIG_DYNAMIC_EAP_METHODS
LIBS += -ldl -rdynamic
endif
endif
ifdef CONFIG_AP
-@@ -987,9 +994,11 @@ NEED_EAP_COMMON=y
+@@ -988,9 +995,11 @@ NEED_EAP_COMMON=y
NEED_RSN_AUTHENTICATOR=y
CFLAGS += -DCONFIG_AP
OBJS += ap.o
OBJS += ../src/ap/hostapd.o
OBJS += ../src/ap/wpa_auth_glue.o
OBJS += ../src/ap/utils.o
-@@ -1080,6 +1089,12 @@ endif
+@@ -1081,6 +1090,12 @@ endif
ifdef CONFIG_HS20
OBJS += ../src/ap/hs20.o
endif
endif
ifdef CONFIG_MBO
-@@ -1089,7 +1104,9 @@ NEED_GAS=y
+@@ -1090,7 +1105,9 @@ NEED_GAS=y
endif
ifdef NEED_RSN_AUTHENTICATOR
NEED_AES_WRAP=y
OBJS += ../src/ap/wpa_auth.o
OBJS += ../src/ap/wpa_auth_ie.o
-@@ -2079,6 +2096,12 @@ wpa_priv: $(BCHECK) $(OBJS_priv)
+@@ -2080,6 +2097,12 @@ wpa_priv: $(BCHECK) $(OBJS_priv)
_OBJS_VAR := OBJS
include ../src/objs.mk
wpa_supplicant: $(BCHECK) $(OBJS) $(EXTRA_progs)
$(Q)$(LDO) $(LDFLAGS) -o wpa_supplicant $(OBJS) $(LIBS) $(EXTRALIBS)
@$(E) " LD " $@
-@@ -2211,6 +2234,12 @@ eap_gpsk.so: $(SRC_EAP_GPSK)
+@@ -2212,6 +2235,12 @@ eap_gpsk.so: $(SRC_EAP_GPSK)
$(Q)sed -e 's|\@BINDIR\@|$(BINDIR)|g' $< >$@
@$(E) " sed" $<
os_memset(&eapol_test, 0, sizeof(eapol_test));
--- a/wpa_supplicant/events.c
+++ b/wpa_supplicant/events.c
-@@ -5919,8 +5919,8 @@ static void wpas_link_reconfig(struct wp
+@@ -5929,8 +5929,8 @@ static void wpas_link_reconfig(struct wp
}
{
struct wpa_supplicant *wpa_s = ctx;
int resched;
-@@ -6872,7 +6872,7 @@ void wpa_supplicant_event(void *ctx, enu
+@@ -6882,7 +6882,7 @@ void wpa_supplicant_event(void *ctx, enu
}
struct wpa_supplicant *wpa_s;
--- a/wpa_supplicant/wpa_priv.c
+++ b/wpa_supplicant/wpa_priv.c
-@@ -1039,8 +1039,8 @@ static void wpa_priv_send_ft_response(st
+@@ -1042,8 +1042,8 @@ static void wpa_priv_send_ft_response(st
}
{
struct wpa_priv_interface *iface = ctx;
-@@ -1103,7 +1103,7 @@ void wpa_supplicant_event(void *ctx, enu
+@@ -1106,7 +1106,7 @@ void wpa_supplicant_event(void *ctx, enu
}
union wpa_event_data *data)
{
struct wpa_priv_global *global = ctx;
-@@ -1217,6 +1217,8 @@ int main(int argc, char *argv[])
+@@ -1220,6 +1220,8 @@ int main(int argc, char *argv[])
if (os_program_init())
return -1;
os_memset(&global, 0, sizeof(global));
--- a/wpa_supplicant/wpa_supplicant.c
+++ b/wpa_supplicant/wpa_supplicant.c
-@@ -7583,7 +7583,6 @@ struct wpa_interface * wpa_supplicant_ma
+@@ -7596,7 +7596,6 @@ struct wpa_interface * wpa_supplicant_ma
return NULL;
}
/**
* wpa_supplicant_match_existing - Match existing interfaces
* @global: Pointer to global data from wpa_supplicant_init()
-@@ -7618,6 +7617,11 @@ static int wpa_supplicant_match_existing
+@@ -7631,6 +7630,11 @@ static int wpa_supplicant_match_existing
#endif /* CONFIG_MATCH_IFACE */
/**
* wpa_supplicant_add_iface - Add a new network interface
-@@ -7874,6 +7878,8 @@ struct wpa_global * wpa_supplicant_init(
+@@ -7887,6 +7891,8 @@ struct wpa_global * wpa_supplicant_init(
#ifndef CONFIG_NO_WPA_MSG
wpa_msg_register_ifname_cb(wpa_supplicant_msg_ifname_cb);
#endif /* CONFIG_NO_WPA_MSG */
--- a/hostapd/Makefile
+++ b/hostapd/Makefile
-@@ -1405,7 +1405,7 @@ hostapd_multi.a: $(BCHECK) $(OBJS)
+@@ -1406,7 +1406,7 @@ hostapd_multi.a: $(BCHECK) $(OBJS)
@$(AR) cr $@ hostapd_multi.o $(OBJS)
hostapd: $(OBJS)
@$(E) " LD " $@
ifdef CONFIG_WPA_TRACE
-@@ -1416,7 +1416,7 @@ _OBJS_VAR := OBJS_c
+@@ -1417,7 +1417,7 @@ _OBJS_VAR := OBJS_c
include ../src/objs.mk
hostapd_cli: $(OBJS_c)
NOBJS = nt_password_hash.o ../src/crypto/ms_funcs.o $(SHA1OBJS)
--- a/wpa_supplicant/Makefile
+++ b/wpa_supplicant/Makefile
-@@ -2103,31 +2103,31 @@ wpa_supplicant_multi.a: .config $(BCHECK
+@@ -2104,31 +2104,31 @@ wpa_supplicant_multi.a: .config $(BCHECK
@$(AR) cr $@ wpa_supplicant_multi.o $(OBJS)
wpa_supplicant: $(BCHECK) $(OBJS) $(EXTRA_progs)
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 4 Apr 2024 12:59:41 +0200
-Subject: [PATCH] build: de-duplicate _DIRS before calling mkdir
-
-If the build path is long, the contents of the _DIRS variable can be very long,
-since it repeats the same directories very often.
-In some cases, this has triggered an "Argument list too long" build error.
-
-Suggested-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/src/build.rules
-+++ b/src/build.rules
-@@ -80,7 +80,7 @@ endif
- _DIRS := $(BUILDDIR)/$(PROJ)
- .PHONY: _make_dirs
- _make_dirs:
-- @mkdir -p $(_DIRS)
-+ @mkdir -p $(sort $(_DIRS))
-
- $(BUILDDIR)/$(PROJ)/src/%.o: $(ROOTDIR)src/%.c $(CONFIG_FILE) | _make_dirs
- $(Q)$(CC) -c -o $@ $(CFLAGS) $<
struct hapd_global {
void **drv_priv;
-@@ -806,7 +806,7 @@ int main(int argc, char *argv[])
+@@ -816,7 +816,7 @@ int main(int argc, char *argv[])
wpa_supplicant_event = hostapd_wpa_event;
wpa_supplicant_event_global = hostapd_wpa_event_global;
for (;;) {
if (c < 0)
break;
switch (c) {
-@@ -843,6 +843,8 @@ int main(int argc, char *argv[])
+@@ -853,6 +853,8 @@ int main(int argc, char *argv[])
break;
#endif /* CONFIG_DEBUG_LINUX_TRACING */
case 'v':
static int hostapd_cli_cmd_disassoc_imminent(struct wpa_ctrl *ctrl, int argc,
-@@ -1670,13 +1666,10 @@ static const struct hostapd_cli_cmd host
+@@ -1677,13 +1673,10 @@ static const struct hostapd_cli_cmd host
{ "disassociate", hostapd_cli_cmd_disassociate,
hostapd_complete_stations,
"<addr> = disassociate a station" },
{ "wps_pin", hostapd_cli_cmd_wps_pin, NULL,
"<uuid> <pin> [timeout] [addr] = add WPS Enrollee PIN" },
{ "wps_check_pin", hostapd_cli_cmd_wps_check_pin, NULL,
-@@ -1701,7 +1694,6 @@ static const struct hostapd_cli_cmd host
+@@ -1708,7 +1701,6 @@ static const struct hostapd_cli_cmd host
"<SSID> <auth> <encr> <key> = configure AP" },
{ "wps_get_status", hostapd_cli_cmd_wps_get_status, NULL,
"= show current WPS status" },
--- a/hostapd/Makefile
+++ b/hostapd/Makefile
-@@ -221,6 +221,9 @@ endif
+@@ -222,6 +222,9 @@ endif
ifdef CONFIG_NO_CTRL_IFACE
CFLAGS += -DCONFIG_NO_CTRL_IFACE
else
static int hostapd_ctrl_iface_sta_mib(struct hostapd_data *hapd,
struct sta_info *sta,
char *buf, size_t buflen)
-@@ -539,6 +539,7 @@ int hostapd_ctrl_iface_sta_next(struct h
+@@ -554,6 +554,7 @@ int hostapd_ctrl_iface_sta_next(struct h
return hostapd_ctrl_iface_sta_mib(hapd, sta->next, buf, buflen);
}
#ifdef CONFIG_P2P_MANAGER
static int p2p_manager_disconnect(struct hostapd_data *hapd, u16 stype,
-@@ -951,12 +952,12 @@ int hostapd_ctrl_iface_status(struct hos
+@@ -1002,12 +1003,12 @@ int hostapd_ctrl_iface_status(struct hos
return len;
len += ret;
}
if (os_snprintf_error(buflen - len, ret))
--- a/src/ap/ieee802_1x.c
+++ b/src/ap/ieee802_1x.c
-@@ -2837,6 +2837,7 @@ static const char * bool_txt(bool val)
+@@ -2845,6 +2845,7 @@ static const char * bool_txt(bool val)
return val ? "TRUE" : "FALSE";
}
int ieee802_1x_get_mib(struct hostapd_data *hapd, char *buf, size_t buflen)
{
-@@ -3023,6 +3024,7 @@ int ieee802_1x_get_mib_sta(struct hostap
+@@ -3031,6 +3032,7 @@ int ieee802_1x_get_mib_sta(struct hostap
return len;
}
static void ieee802_1x_wnm_notif_send(void *eloop_ctx, void *timeout_ctx)
--- a/src/ap/wpa_auth.c
+++ b/src/ap/wpa_auth.c
-@@ -5583,6 +5583,7 @@ static const char * wpa_bool_txt(int val
+@@ -5911,6 +5911,7 @@ static const char * wpa_bool_txt(int val
return val ? "TRUE" : "FALSE";
}
#define RSN_SUITE "%02x-%02x-%02x-%d"
#define RSN_SUITE_ARG(s) \
-@@ -5735,7 +5736,7 @@ int wpa_get_mib_sta(struct wpa_state_mac
+@@ -6063,7 +6064,7 @@ int wpa_get_mib_sta(struct wpa_state_mac
return len;
}
--- a/wpa_supplicant/Makefile
+++ b/wpa_supplicant/Makefile
-@@ -1038,6 +1038,9 @@ ifdef CONFIG_FILS
+@@ -1039,6 +1039,9 @@ ifdef CONFIG_FILS
OBJS += ../src/ap/fils_hlp.o
endif
ifdef CONFIG_CTRL_IFACE
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 4 Nov 2021 11:45:18 +0100
-Subject: [PATCH] hostapd: support qos_map_set without CONFIG_INTERWORKING
-
-This feature is useful on its own even without full interworking support
-
---- a/hostapd/config_file.c
-+++ b/hostapd/config_file.c
-@@ -1680,6 +1680,8 @@ static int parse_anqp_elem(struct hostap
- return 0;
- }
-
-+#endif /* CONFIG_INTERWORKING */
-+
-
- static int parse_qos_map_set(struct hostapd_bss_config *bss,
- char *buf, int line)
-@@ -1721,8 +1723,6 @@ static int parse_qos_map_set(struct host
- return 0;
- }
-
--#endif /* CONFIG_INTERWORKING */
--
-
- #ifdef CONFIG_HS20
- static int hs20_parse_conn_capab(struct hostapd_bss_config *bss, char *buf,
-@@ -4260,10 +4260,10 @@ static int hostapd_config_fill(struct ho
- bss->gas_frag_limit = val;
- } else if (os_strcmp(buf, "gas_comeback_delay") == 0) {
- bss->gas_comeback_delay = atoi(pos);
-+#endif /* CONFIG_INTERWORKING */
- } else if (os_strcmp(buf, "qos_map_set") == 0) {
- if (parse_qos_map_set(bss, pos, line) < 0)
- return 1;
--#endif /* CONFIG_INTERWORKING */
- #ifdef CONFIG_RADIUS_TEST
- } else if (os_strcmp(buf, "dump_msk_file") == 0) {
- os_free(bss->dump_msk_file);
---- a/src/ap/hostapd.c
-+++ b/src/ap/hostapd.c
-@@ -1548,6 +1548,7 @@ static int hostapd_setup_bss(struct host
- wpa_printf(MSG_ERROR, "GAS server initialization failed");
- return -1;
- }
-+#endif /* CONFIG_INTERWORKING */
-
- if (conf->qos_map_set_len &&
- hostapd_drv_set_qos_map(hapd, conf->qos_map_set,
-@@ -1555,7 +1556,6 @@ static int hostapd_setup_bss(struct host
- wpa_printf(MSG_ERROR, "Failed to initialize QoS Map");
- return -1;
- }
--#endif /* CONFIG_INTERWORKING */
-
- if (conf->bss_load_update_period && bss_load_update_init(hapd)) {
- wpa_printf(MSG_ERROR, "BSS Load initialization failed");
---- a/src/ap/ieee802_11_shared.c
-+++ b/src/ap/ieee802_11_shared.c
-@@ -1138,13 +1138,11 @@ u8 * hostapd_eid_rsnxe(struct hostapd_da
- u16 check_ext_capab(struct hostapd_data *hapd, struct sta_info *sta,
- const u8 *ext_capab_ie, size_t ext_capab_ie_len)
- {
--#ifdef CONFIG_INTERWORKING
- /* check for QoS Map support */
- if (ext_capab_ie_len >= 5) {
- if (ext_capab_ie[4] & 0x01)
- sta->qos_map_enabled = 1;
- }
--#endif /* CONFIG_INTERWORKING */
-
- if (ext_capab_ie_len > 0) {
- sta->ecsa_supported = !!(ext_capab_ie[0] & BIT(2));
---- a/wpa_supplicant/events.c
-+++ b/wpa_supplicant/events.c
-@@ -2935,8 +2935,6 @@ void wnm_bss_keep_alive_deinit(struct wp
- }
-
-
--#ifdef CONFIG_INTERWORKING
--
- static int wpas_qos_map_set(struct wpa_supplicant *wpa_s, const u8 *qos_map,
- size_t len)
- {
-@@ -2969,8 +2967,6 @@ static void interworking_process_assoc_r
- }
- }
-
--#endif /* CONFIG_INTERWORKING */
--
-
- static void wpa_supplicant_set_4addr_mode(struct wpa_supplicant *wpa_s)
- {
-@@ -3350,10 +3346,8 @@ static int wpa_supplicant_event_associnf
- wnm_process_assoc_resp(wpa_s, data->assoc_info.resp_ies,
- data->assoc_info.resp_ies_len);
- #endif /* CONFIG_WNM */
--#ifdef CONFIG_INTERWORKING
- interworking_process_assoc_resp(wpa_s, data->assoc_info.resp_ies,
- data->assoc_info.resp_ies_len);
--#endif /* CONFIG_INTERWORKING */
- if (wpa_s->hw_capab == CAPAB_VHT &&
- get_ie(data->assoc_info.resp_ies,
- data->assoc_info.resp_ies_len, WLAN_EID_VHT_CAP))
} else if (os_strcmp(buf, "ht_capab") == 0) {
--- a/src/ap/ap_config.h
+++ b/src/ap/ap_config.h
-@@ -1093,6 +1093,8 @@ struct hostapd_config {
+@@ -1102,6 +1102,8 @@ struct hostapd_config {
int ht_op_mode_fixed;
u16 ht_capab;
int no_pri_sec_switch;
--- a/src/ap/hw_features.c
+++ b/src/ap/hw_features.c
-@@ -544,7 +544,8 @@ static int ieee80211n_check_40mhz(struct
+@@ -551,7 +551,8 @@ static int ieee80211n_check_40mhz(struct
int ret;
/* Check that HT40 is used and PRI / SEC switch is allowed */
149, 157, 165, 173, 184, 192
};
int ht40 = -1;
-@@ -3093,7 +3093,7 @@ void ibss_mesh_setup_freq(struct wpa_sup
+@@ -3094,7 +3094,7 @@ void ibss_mesh_setup_freq(struct wpa_sup
int ieee80211_mode = wpas_mode_to_ieee80211_mode(ssid->mode);
enum hostapd_hw_mode hw_mode;
struct hostapd_hw_modes *mode = NULL;
u8 channel;
bool is_6ghz, is_24ghz;
bool dfs_enabled = wpa_s->conf->country[0] && (wpa_s->drv_flags & WPA_DRIVER_FLAGS_RADAR);
-@@ -3143,6 +3143,8 @@ void ibss_mesh_setup_freq(struct wpa_sup
+@@ -3144,6 +3144,8 @@ void ibss_mesh_setup_freq(struct wpa_sup
freq->he_enabled = ibss_mesh_can_use_he(wpa_s, ssid, mode,
ieee80211_mode);
freq->channel = channel;
--- a/wpa_supplicant/wpa_supplicant.c
+++ b/wpa_supplicant/wpa_supplicant.c
-@@ -5870,7 +5870,7 @@ wpa_supplicant_alloc(struct wpa_supplica
+@@ -5883,7 +5883,7 @@ wpa_supplicant_alloc(struct wpa_supplica
if (wpa_s == NULL)
return NULL;
wpa_s->scan_req = INITIAL_SCAN_REQ;
--- a/src/drivers/driver_nl80211.c
+++ b/src/drivers/driver_nl80211.c
-@@ -5483,7 +5483,7 @@ static int nl80211_set_channel(struct i8
+@@ -5482,7 +5482,7 @@ static int nl80211_set_channel(struct i8
freq->he_enabled, freq->eht_enabled, freq->bandwidth,
freq->center_freq1, freq->center_freq2);
--- a/src/drivers/driver_nl80211.c
+++ b/src/drivers/driver_nl80211.c
-@@ -3075,12 +3075,12 @@ static int wpa_driver_nl80211_del_beacon
- return 0;
-
- wpa_printf(MSG_DEBUG, "nl80211: Remove beacon (ifindex=%d)",
-- drv->ifindex);
-+ bss->ifindex);
- link->beacon_set = 0;
- link->freq = 0;
-
- nl80211_put_wiphy_data_ap(bss);
-- msg = nl80211_drv_msg(drv, 0, NL80211_CMD_DEL_BEACON);
-+ msg = nl80211_bss_msg(bss, 0, NL80211_CMD_DEL_BEACON);
- if (!msg)
- return -ENOBUFS;
-
-@@ -6176,8 +6176,7 @@ static void nl80211_teardown_ap(struct i
+@@ -6171,8 +6171,7 @@ static void nl80211_teardown_ap(struct i
nl80211_mgmt_unsubscribe(bss, "AP teardown");
nl80211_put_wiphy_data_ap(bss);
}
-@@ -8977,8 +8976,6 @@ static int wpa_driver_nl80211_if_remove(
- } else {
- wpa_printf(MSG_DEBUG, "nl80211: First BSS - reassign context");
- nl80211_teardown_ap(bss);
-- if (!bss->added_if && !drv->first_bss->next)
-- wpa_driver_nl80211_del_beacon_all(bss);
- nl80211_destroy_bss(bss);
- if (!bss->added_if)
- i802_set_iface_flags(bss, 0);
--- a/src/drivers/driver.h
+++ b/src/drivers/driver.h
-@@ -971,6 +971,9 @@ struct wpa_driver_associate_params {
+@@ -979,6 +979,9 @@ struct wpa_driver_associate_params {
* responsible for selecting with which BSS to associate. */
const u8 *bssid;
* macsec_policy - Determines the policy for MACsec secure session
--- a/wpa_supplicant/wpa_supplicant.c
+++ b/wpa_supplicant/wpa_supplicant.c
-@@ -4249,6 +4249,12 @@ static void wpas_start_assoc_cb(struct w
+@@ -4254,6 +4254,12 @@ static void wpas_start_assoc_cb(struct w
params.beacon_int = ssid->beacon_int;
else
params.beacon_int = wpa_s->conf->beacon_int;
--- a/src/drivers/driver.h
+++ b/src/drivers/driver.h
-@@ -1876,6 +1876,7 @@ struct wpa_driver_mesh_join_params {
+@@ -1889,6 +1889,7 @@ struct wpa_driver_mesh_join_params {
#define WPA_DRIVER_MESH_FLAG_AMPE 0x00000008
unsigned int flags;
bool handle_dfs;
struct wpa_driver_set_key_params {
--- a/src/drivers/driver_nl80211.c
+++ b/src/drivers/driver_nl80211.c
-@@ -11850,6 +11850,18 @@ static int nl80211_put_mesh_id(struct nl
+@@ -11952,6 +11952,18 @@ static int nl80211_put_mesh_id(struct nl
}
static int nl80211_put_mesh_config(struct nl_msg *msg,
struct wpa_driver_mesh_bss_params *params)
{
-@@ -11911,6 +11923,7 @@ static int nl80211_join_mesh(struct i802
+@@ -12013,6 +12025,7 @@ static int nl80211_join_mesh(struct i802
nl80211_put_basic_rates(msg, params->basic_rates) ||
nl80211_put_mesh_id(msg, params->meshid, params->meshid_len) ||
nl80211_put_beacon_int(msg, params->beacon_int) ||
--- a/wpa_supplicant/wpa_supplicant.c
+++ b/wpa_supplicant/wpa_supplicant.c
-@@ -3100,6 +3100,10 @@ void ibss_mesh_setup_freq(struct wpa_sup
+@@ -3101,6 +3101,10 @@ void ibss_mesh_setup_freq(struct wpa_sup
freq->freq = ssid->frequency;
--- a/hostapd/config_file.c
+++ b/hostapd/config_file.c
-@@ -3708,6 +3708,8 @@ static int hostapd_config_fill(struct ho
+@@ -3710,6 +3710,8 @@ static int hostapd_config_fill(struct ho
} else if (os_strcmp(buf, "he_bss_color") == 0) {
conf->he_op.he_bss_color = atoi(pos) & 0x3f;
conf->he_op.he_bss_color_disabled = 0;
--- a/src/ap/hostapd.h
+++ b/src/ap/hostapd.h
-@@ -163,6 +163,21 @@ struct hostapd_sae_commit_queue {
+@@ -168,6 +168,21 @@ struct hostapd_sae_commit_queue {
};
/**
* struct hostapd_data - hostapd per-BSS data structure
*/
struct hostapd_data {
-@@ -182,6 +197,9 @@ struct hostapd_data {
+@@ -181,6 +196,9 @@ struct hostapd_data {
- struct hostapd_data *mld_first_bss;
+ u8 own_addr[ETH_ALEN];
+ /* OpenWrt specific statistics */
+ struct hostapd_openwrt_stats openwrt_stats;
--- a/hostapd/Makefile
+++ b/hostapd/Makefile
-@@ -166,6 +166,12 @@ OBJS += ../src/common/hw_features_common
+@@ -167,6 +167,12 @@ OBJS += ../src/common/hw_features_common
OBJS += ../src/eapol_auth/eapol_auth_sm.o
}
--- a/src/ap/beacon.c
+++ b/src/ap/beacon.c
-@@ -1351,6 +1351,12 @@ void handle_probe_req(struct hostapd_dat
+@@ -1357,6 +1357,12 @@ void handle_probe_req(struct hostapd_dat
int mld_id;
u16 links;
#endif /* CONFIG_IEEE80211BE */
if (hapd->iconf->rssi_ignore_probe_request && ssi_signal &&
ssi_signal < hapd->iconf->rssi_ignore_probe_request)
-@@ -1537,6 +1543,12 @@ void handle_probe_req(struct hostapd_dat
+@@ -1543,6 +1549,12 @@ void handle_probe_req(struct hostapd_dat
}
#endif /* CONFIG_P2P */
--- a/src/ap/dfs.c
+++ b/src/ap/dfs.c
-@@ -1225,6 +1225,8 @@ int hostapd_dfs_pre_cac_expired(struct h
+@@ -1236,6 +1236,8 @@ int hostapd_dfs_pre_cac_expired(struct h
"freq=%d ht_enabled=%d chan_offset=%d chan_width=%d cf1=%d cf2=%d",
freq, ht_enabled, chan_offset, chan_width, cf1, cf2);
wpabuf_free(sta->p2p_ie);
--- a/src/ap/hostapd.c
+++ b/src/ap/hostapd.c
-@@ -493,6 +493,7 @@ void hostapd_free_hapd_data(struct hosta
+@@ -475,6 +475,7 @@ void hostapd_free_hapd_data(struct hosta
hapd->beacon_set_done = 0;
wpa_printf(MSG_DEBUG, "%s(%s)", __func__, hapd->conf->iface);
accounting_deinit(hapd);
hostapd_deinit_wpa(hapd);
vlan_deinit(hapd);
-@@ -1274,6 +1275,8 @@ static int hostapd_start_beacon(struct h
+@@ -1303,6 +1304,8 @@ static int hostapd_start_beacon(struct h
if (hapd->driver && hapd->driver->set_operstate)
hapd->driver->set_operstate(hapd->drv_priv, 1);
return 0;
}
-@@ -2367,6 +2370,7 @@ static int hostapd_setup_interface_compl
+@@ -2448,6 +2451,7 @@ static int hostapd_setup_interface_compl
if (err)
goto fail;
wpa_printf(MSG_DEBUG, "Completing interface initialization");
if (iface->freq) {
#ifdef NEED_AP_MLME
-@@ -2586,6 +2590,7 @@ dfs_offload:
+@@ -2667,6 +2671,7 @@ dfs_offload:
fail:
wpa_printf(MSG_ERROR, "Interface initialization failed");
if (iface->is_no_ir) {
hostapd_set_state(iface, HAPD_IFACE_NO_IR);
-@@ -3076,6 +3081,7 @@ void hostapd_interface_deinit_free(struc
+@@ -3383,6 +3388,7 @@ void hostapd_interface_deinit_free(struc
(unsigned int) iface->conf->num_bss);
driver = iface->bss[0]->driver;
drv_priv = iface->bss[0]->drv_priv;
#define OCE_STA_CFON_ENABLED(hapd) \
((hapd->conf->oce & OCE_STA_CFON) && \
-@@ -184,6 +185,7 @@ struct hostapd_data {
+@@ -189,6 +190,7 @@ struct hostapd_data {
struct hostapd_iface *iface;
struct hostapd_config *iconf;
struct hostapd_bss_config *conf;
int interface_added; /* virtual interface added for this BSS */
unsigned int started:1;
unsigned int disabled:1;
-@@ -707,6 +709,7 @@ hostapd_alloc_bss_data(struct hostapd_if
+@@ -742,6 +744,7 @@ hostapd_alloc_bss_data(struct hostapd_if
struct hostapd_bss_config *bss);
int hostapd_setup_interface(struct hostapd_iface *iface);
int hostapd_setup_interface_complete(struct hostapd_iface *iface, int err);
struct hostapd_iface * hostapd_alloc_iface(void);
--- a/src/ap/ieee802_11.c
+++ b/src/ap/ieee802_11.c
-@@ -2798,7 +2798,7 @@ static void handle_auth(struct hostapd_d
+@@ -2808,7 +2808,7 @@ static void handle_auth(struct hostapd_d
u16 auth_alg, auth_transaction, status_code;
u16 resp = WLAN_STATUS_SUCCESS;
struct sta_info *sta = NULL;
u16 fc;
const u8 *challenge = NULL;
u8 resp_ies[2 + WLAN_AUTH_CHALLENGE_LEN];
-@@ -2807,6 +2807,11 @@ static void handle_auth(struct hostapd_d
- struct radius_sta rad_info;
- const u8 *dst, *sa, *bssid;
+@@ -2819,6 +2819,11 @@ static void handle_auth(struct hostapd_d
+ #ifdef CONFIG_IEEE80211BE
bool mld_sta = false;
+ #endif /* CONFIG_IEEE80211BE */
+ struct hostapd_ubus_request req = {
+ .type = HOSTAPD_UBUS_AUTH_REQ,
+ .mgmt_frame = mgmt,
if (len < IEEE80211_HDRLEN + sizeof(mgmt->u.auth)) {
wpa_printf(MSG_INFO, "handle_auth - too short payload (len=%lu)",
-@@ -2998,6 +3003,13 @@ static void handle_auth(struct hostapd_d
+@@ -3012,6 +3017,13 @@ static void handle_auth(struct hostapd_d
resp = WLAN_STATUS_UNSPECIFIED_FAILURE;
goto fail;
}
if (res == HOSTAPD_ACL_PENDING)
return;
-@@ -5242,7 +5254,7 @@ static void handle_assoc(struct hostapd_
+@@ -5252,7 +5264,7 @@ static void handle_assoc(struct hostapd_
int resp = WLAN_STATUS_SUCCESS;
u16 reply_res = WLAN_STATUS_UNSPECIFIED_FAILURE;
const u8 *pos;
struct sta_info *sta;
u8 *tmp = NULL;
#ifdef CONFIG_FILS
-@@ -5484,6 +5496,11 @@ static void handle_assoc(struct hostapd_
+@@ -5494,6 +5506,11 @@ static void handle_assoc(struct hostapd_
left = res;
}
#endif /* CONFIG_FILS */
/* followed by SSID and Supported rates; and HT capabilities if 802.11n
* is used */
-@@ -5586,6 +5603,13 @@ static void handle_assoc(struct hostapd_
+@@ -5596,6 +5613,13 @@ static void handle_assoc(struct hostapd_
if (set_beacon)
ieee802_11_set_beacons(hapd->iface);
fail:
/*
-@@ -5836,6 +5860,7 @@ static void handle_disassoc(struct hosta
+@@ -5825,6 +5849,7 @@ static void handle_disassoc(struct hosta
(unsigned long) len);
return;
}
sta = ap_get_sta(hapd, mgmt->sa);
if (!sta) {
-@@ -5867,6 +5892,8 @@ static void handle_deauth(struct hostapd
+@@ -5856,6 +5881,8 @@ static void handle_deauth(struct hostapd
/* Clear the PTKSA cache entries for PASN */
ptksa_cache_flush(hapd->ptksa, mgmt->sa, WPA_CIPHER_NONE);
}
-@@ -352,6 +355,9 @@ void hostapd_handle_radio_measurement(st
- mgmt->u.action.u.rrm.action, MAC2STR(mgmt->sa));
-
+@@ -401,6 +404,7 @@ void hostapd_handle_radio_measurement(st
switch (mgmt->u.action.u.rrm.action) {
-+ case WLAN_RRM_LINK_MEASUREMENT_REPORT:
-+ hostapd_ubus_handle_link_measurement(hapd, buf, len);
-+ break;
case WLAN_RRM_RADIO_MEASUREMENT_REPORT:
hostapd_handle_radio_msmt_report(hapd, buf, len);
++ hostapd_ubus_handle_link_measurement(hapd, buf, len);
break;
+ case WLAN_RRM_NEIGHBOR_REPORT_REQUEST:
+ hostapd_handle_nei_report_req(hapd, buf, len);
--- a/src/ap/sta_info.c
+++ b/src/ap/sta_info.c
-@@ -476,6 +476,7 @@ void ap_handle_timer(void *eloop_ctx, vo
+@@ -540,6 +540,7 @@ void ap_handle_timer(void *eloop_ctx, vo
hostapd_logger(hapd, sta->addr, HOSTAPD_MODULE_IEEE80211,
HOSTAPD_LEVEL_INFO, "deauthenticated due to "
"local deauth request");
ap_free_sta(hapd, sta);
return;
}
-@@ -631,6 +632,7 @@ skip_poll:
+@@ -695,6 +696,7 @@ skip_poll:
mlme_deauthenticate_indication(
hapd, sta,
WLAN_REASON_PREV_AUTH_NOT_VALID);
ap_free_sta(hapd, sta);
break;
}
-@@ -1448,15 +1450,28 @@ void ap_sta_set_authorized_event(struct
+@@ -1513,15 +1515,28 @@ void ap_sta_set_authorized_event(struct
os_snprintf(buf, sizeof(buf), MACSTR, MAC2STR(sta->addr));
if (authorized) {
#ifdef CONFIG_P2P
if (wpa_auth_get_ip_addr(sta->wpa_sm, ip_addr_buf) == 0) {
os_snprintf(ip_addr, sizeof(ip_addr),
-@@ -1467,6 +1482,13 @@ void ap_sta_set_authorized_event(struct
+@@ -1532,6 +1547,13 @@ void ap_sta_set_authorized_event(struct
}
#endif /* CONFIG_P2P */
keyid = ap_sta_wpa_get_keyid(hapd, sta);
if (keyid) {
os_snprintf(keyid_buf, sizeof(keyid_buf),
-@@ -1485,17 +1507,19 @@ void ap_sta_set_authorized_event(struct
+@@ -1550,17 +1572,19 @@ void ap_sta_set_authorized_event(struct
dpp_pkhash, SHA256_MAC_LEN);
}
hapd->msg_ctx_parent != hapd->msg_ctx)
--- a/src/ap/sta_info.h
+++ b/src/ap/sta_info.h
-@@ -319,6 +319,7 @@ struct sta_info {
+@@ -317,6 +317,7 @@ struct sta_info {
#endif /* CONFIG_TESTING_OPTIONS */
#ifdef CONFIG_AIRTIME_POLICY
unsigned int airtime_weight;
+}
--- a/wpa_supplicant/Makefile
+++ b/wpa_supplicant/Makefile
-@@ -189,6 +189,13 @@ ifdef CONFIG_EAPOL_TEST
+@@ -191,6 +191,13 @@ ifdef CONFIG_EAPOL_TEST
CFLAGS += -Werror -DEAPOL_TEST
endif
ifdef CONFIG_CODE_COVERAGE
CFLAGS += -O0 -fprofile-arcs -ftest-coverage -U_FORTIFY_SOURCE
LIBS += -lgcov
-@@ -1042,6 +1049,9 @@ ifdef CONFIG_CTRL_IFACE_MIB
+@@ -1043,6 +1050,9 @@ ifdef CONFIG_CTRL_IFACE_MIB
CFLAGS += -DCONFIG_CTRL_IFACE_MIB
endif
OBJS += ../src/ap/ctrl_iface_ap.o
break;
--- a/wpa_supplicant/wpa_supplicant.c
+++ b/wpa_supplicant/wpa_supplicant.c
-@@ -7716,6 +7716,8 @@ struct wpa_supplicant * wpa_supplicant_a
+@@ -7729,6 +7729,8 @@ struct wpa_supplicant * wpa_supplicant_a
}
#endif /* CONFIG_P2P */
return wpa_s;
}
-@@ -7742,6 +7744,8 @@ int wpa_supplicant_remove_iface(struct w
+@@ -7755,6 +7757,8 @@ int wpa_supplicant_remove_iface(struct w
struct wpa_supplicant *parent = wpa_s->parent;
#endif /* CONFIG_MESH */
/* Remove interface from the global list of interfaces */
prev = global->ifaces;
if (prev == wpa_s) {
-@@ -8088,8 +8092,12 @@ int wpa_supplicant_run(struct wpa_global
+@@ -8101,8 +8105,12 @@ int wpa_supplicant_run(struct wpa_global
eloop_register_signal_terminate(wpa_supplicant_terminate, global);
eloop_register_signal_reconfig(wpa_supplicant_reconfig, global);
--- a/hostapd/Makefile
+++ b/hostapd/Makefile
-@@ -168,9 +168,21 @@ OBJS += ../src/eapol_auth/eapol_auth_sm.
+@@ -169,9 +169,21 @@ OBJS += ../src/eapol_auth/eapol_auth_sm.
ifdef CONFIG_UBUS
CFLAGS += -DUBUS_SUPPORT
ifdef CONFIG_CODE_COVERAGE
--- a/hostapd/ctrl_iface.c
+++ b/hostapd/ctrl_iface.c
-@@ -5487,6 +5487,7 @@ try_again:
+@@ -5490,6 +5490,7 @@ try_again:
return -1;
}
wpa_msg_register_cb(hostapd_ctrl_iface_msg_cb);
return 0;
-@@ -5588,6 +5589,7 @@ fail:
+@@ -5591,6 +5592,7 @@ fail:
os_free(fname);
interface->global_ctrl_sock = s;
--- a/hostapd/main.c
+++ b/hostapd/main.c
-@@ -1014,6 +1014,7 @@ int main(int argc, char *argv[])
+@@ -1024,6 +1024,7 @@ int main(int argc, char *argv[])
}
hostapd_global_ctrl_iface_init(&interfaces);
if (hostapd_global_run(&interfaces, daemonize, pid_file)) {
wpa_printf(MSG_ERROR, "Failed to start eloop");
-@@ -1023,6 +1024,7 @@ int main(int argc, char *argv[])
+@@ -1033,6 +1034,7 @@ int main(int argc, char *argv[])
ret = 0;
out:
for (i = 0; i < interfaces.count; i++) {
--- a/src/ap/ap_drv_ops.h
+++ b/src/ap/ap_drv_ops.h
-@@ -399,6 +399,23 @@ static inline int hostapd_drv_stop_ap(st
+@@ -404,6 +404,23 @@ static inline int hostapd_drv_stop_ap(st
return hapd->driver->stop_ap(hapd->drv_priv, link_id);
}
if (iface->config_fname == NULL) {
/* Only in-memory config in use - assume it has been updated */
hostapd_clear_old(iface);
-@@ -493,6 +495,7 @@ void hostapd_free_hapd_data(struct hosta
+@@ -475,6 +477,7 @@ void hostapd_free_hapd_data(struct hosta
hapd->beacon_set_done = 0;
wpa_printf(MSG_DEBUG, "%s(%s)", __func__, hapd->conf->iface);
hostapd_ubus_free_bss(hapd);
accounting_deinit(hapd);
hostapd_deinit_wpa(hapd);
-@@ -687,6 +690,7 @@ void hostapd_cleanup_iface_partial(struc
+@@ -716,6 +719,7 @@ void hostapd_cleanup_iface_partial(struc
static void hostapd_cleanup_iface(struct hostapd_iface *iface)
{
wpa_printf(MSG_DEBUG, "%s(%p)", __func__, iface);
eloop_cancel_timeout(hostapd_interface_setup_failure_handler, iface,
NULL);
-@@ -1276,6 +1280,7 @@ static int hostapd_start_beacon(struct h
+@@ -1305,6 +1309,7 @@ static int hostapd_start_beacon(struct h
hapd->driver->set_operstate(hapd->drv_priv, 1);
hostapd_ubus_add_bss(hapd);
return 0;
}
-@@ -1298,8 +1303,7 @@ static int hostapd_start_beacon(struct h
+@@ -1327,8 +1332,7 @@ static int hostapd_start_beacon(struct h
* initialized. Most of the modules that are initialized here will be
* deinitialized in hostapd_cleanup().
*/
{
struct hostapd_bss_config *conf = hapd->conf;
u8 ssid[SSID_MAX_LEN + 1];
-@@ -2790,7 +2794,7 @@ hostapd_alloc_bss_data(struct hostapd_if
+@@ -2871,7 +2875,7 @@ hostapd_alloc_bss_data(struct hostapd_if
}
{
if (!hapd)
return;
-@@ -3608,7 +3612,8 @@ int hostapd_remove_iface(struct hapd_int
+@@ -3920,7 +3924,8 @@ int hostapd_remove_iface(struct hapd_int
hapd_iface = interfaces->iface[i];
if (hapd_iface == NULL)
return -1;
#define OCE_STA_CFON_ENABLED(hapd) \
((hapd->conf->oce & OCE_STA_CFON) && \
-@@ -51,6 +52,10 @@ struct hapd_interfaces {
+@@ -52,6 +53,10 @@ struct hapd_interfaces {
struct hostapd_config * (*config_read_cb)(const char *config_fname);
int (*ctrl_iface_init)(struct hostapd_data *hapd);
void (*ctrl_iface_deinit)(struct hostapd_data *hapd);
int (*for_each_interface)(struct hapd_interfaces *interfaces,
int (*cb)(struct hostapd_iface *iface,
void *ctx), void *ctx);
-@@ -186,6 +191,7 @@ struct hostapd_data {
+@@ -191,6 +196,7 @@ struct hostapd_data {
struct hostapd_config *iconf;
struct hostapd_bss_config *conf;
struct hostapd_ubus_bss ubus;
int interface_added; /* virtual interface added for this BSS */
unsigned int started:1;
unsigned int disabled:1;
-@@ -518,6 +524,7 @@ struct hostapd_sta_info {
+@@ -548,6 +554,7 @@ struct hostapd_mld {
*/
struct hostapd_iface {
struct hapd_interfaces *interfaces;
void *owner;
char *config_fname;
struct hostapd_config *conf;
-@@ -718,6 +725,8 @@ struct hostapd_iface * hostapd_init(stru
+@@ -753,6 +760,8 @@ struct hostapd_iface * hostapd_init(stru
struct hostapd_iface *
hostapd_interface_init_bss(struct hapd_interfaces *interfaces, const char *phy,
const char *config_fname, int debug);
void hostapd_interface_deinit_free(struct hostapd_iface *iface);
--- a/src/drivers/driver.h
+++ b/src/drivers/driver.h
-@@ -3856,6 +3856,25 @@ struct wpa_driver_ops {
+@@ -3890,6 +3890,25 @@ struct wpa_driver_ops {
const char *ifname);
/**
* set_sta_vlan - Bind a station into a specific interface (AP only)
* @priv: Private driver interface data
* @ifname: Interface (main or virtual BSS or VLAN)
-@@ -6510,6 +6529,7 @@ union wpa_event_data {
+@@ -6590,6 +6609,7 @@ union wpa_event_data {
/**
* struct ch_switch
* @freq: Frequency of new channel in MHz
* @ht_enabled: Whether this is an HT channel
* @ch_offset: Secondary channel offset
-@@ -6520,6 +6540,7 @@ union wpa_event_data {
+@@ -6600,6 +6620,7 @@ union wpa_event_data {
* @punct_bitmap: Puncturing bitmap
*/
struct ch_switch {
nl_cb_set(bss->nl_cb, NL_CB_SEQ_CHECK, NL_CB_CUSTOM,
no_seq_check, NULL);
nl_cb_set(bss->nl_cb, NL_CB_VALID, NL_CB_CUSTOM,
-@@ -8554,6 +8575,7 @@ static void *i802_init(struct hostapd_da
+@@ -8561,6 +8582,7 @@ static void *i802_init(struct hostapd_da
char master_ifname[IFNAMSIZ];
int ifindex, br_ifindex = 0;
int br_added = 0;
bss = wpa_driver_nl80211_drv_init(hapd, params->ifname,
params->global_priv, 1,
-@@ -8613,21 +8635,17 @@ static void *i802_init(struct hostapd_da
+@@ -8620,21 +8642,17 @@ static void *i802_init(struct hostapd_da
(params->num_bridge == 0 || !params->bridge[0]))
add_ifidx(drv, br_ifindex, drv->ifindex);
}
if (drv->capa.flags2 & WPA_DRIVER_FLAGS2_CONTROL_PORT_RX) {
-@@ -8992,6 +9010,50 @@ static int wpa_driver_nl80211_if_remove(
+@@ -9003,6 +9021,50 @@ static int wpa_driver_nl80211_if_remove(
return 0;
}
static int cookie_handler(struct nl_msg *msg, void *arg)
{
-@@ -10688,6 +10750,37 @@ static int driver_nl80211_if_remove(void
- }
+@@ -10786,6 +10848,37 @@ static bool nl80211_is_drv_shared(void *
+ #endif /* CONFIG_IEEE80211BE */
+static int driver_nl80211_if_rename(void *priv, enum wpa_driver_if_type type,
static int driver_nl80211_send_mlme(void *priv, const u8 *data,
size_t data_len, int noack,
unsigned int freq,
-@@ -13881,6 +13974,8 @@ const struct wpa_driver_ops wpa_driver_n
+@@ -14009,6 +14102,8 @@ const struct wpa_driver_ops wpa_driver_n
.set_acl = wpa_driver_nl80211_set_acl,
.if_add = wpa_driver_nl80211_if_add,
.if_remove = driver_nl80211_if_remove,
+ if (count)
+ data.ch_switch.count = nla_get_u32(count);
- if (finished)
- bss->flink->freq = data.ch_switch.freq;
-@@ -3961,6 +3964,7 @@ static void do_process_drv_event(struct
+ if (link)
+ data.ch_switch.link_id = nla_get_u8(link);
+@@ -3985,6 +3988,7 @@ static void do_process_drv_event(struct
tb[NL80211_ATTR_CENTER_FREQ1],
tb[NL80211_ATTR_CENTER_FREQ2],
tb[NL80211_ATTR_PUNCT_BITMAP],
0);
break;
case NL80211_CMD_CH_SWITCH_NOTIFY:
-@@ -3973,6 +3977,7 @@ static void do_process_drv_event(struct
+@@ -3997,6 +4001,7 @@ static void do_process_drv_event(struct
tb[NL80211_ATTR_CENTER_FREQ1],
tb[NL80211_ATTR_CENTER_FREQ2],
tb[NL80211_ATTR_PUNCT_BITMAP],
extern int wpa_debug_timestamp;
--- a/wpa_supplicant/Makefile
+++ b/wpa_supplicant/Makefile
-@@ -192,8 +192,20 @@ endif
+@@ -194,8 +194,20 @@ endif
ifdef CONFIG_UBUS
CFLAGS += -DUBUS_SUPPORT
OBJS += ubus.o
endif
ifdef CONFIG_CODE_COVERAGE
-@@ -1052,6 +1064,9 @@ OBJS += ../src/ap/ctrl_iface_ap.o
+@@ -1053,6 +1065,9 @@ OBJS += ../src/ap/ctrl_iface_ap.o
ifdef CONFIG_UBUS
OBJS += ../src/ap/ubus.o
endif
CFLAGS += -DEAP_SERVER -DEAP_SERVER_IDENTITY
--- a/wpa_supplicant/events.c
+++ b/wpa_supplicant/events.c
-@@ -5949,6 +5949,7 @@ void supplicant_event(void *ctx, enum wp
+@@ -5965,6 +5965,7 @@ void supplicant_event(void *ctx, enum wp
event_to_string(event), event);
#endif /* CONFIG_NO_STDOUT_DEBUG */
#ifdef CONFIG_BGSCAN
if (state == WPA_COMPLETED && wpa_s->current_ssid != wpa_s->bgscan_ssid)
-@@ -7717,6 +7718,7 @@ struct wpa_supplicant * wpa_supplicant_a
+@@ -7730,6 +7731,7 @@ struct wpa_supplicant * wpa_supplicant_a
#endif /* CONFIG_P2P */
wpas_ubus_add_bss(wpa_s);
return wpa_s;
}
-@@ -7744,6 +7746,7 @@ int wpa_supplicant_remove_iface(struct w
+@@ -7757,6 +7759,7 @@ int wpa_supplicant_remove_iface(struct w
struct wpa_supplicant *parent = wpa_s->parent;
#endif /* CONFIG_MESH */
wpas_ubus_free_bss(wpa_s);
/* Remove interface from the global list of interfaces */
-@@ -8054,6 +8057,7 @@ struct wpa_global * wpa_supplicant_init(
+@@ -8067,6 +8070,7 @@ struct wpa_global * wpa_supplicant_init(
eloop_register_timeout(WPA_SUPPLICANT_CLEANUP_INTERVAL, 0,
wpas_periodic, global, NULL);
return global;
}
-@@ -8092,12 +8096,8 @@ int wpa_supplicant_run(struct wpa_global
+@@ -8105,12 +8109,8 @@ int wpa_supplicant_run(struct wpa_global
eloop_register_signal_terminate(wpa_supplicant_terminate, global);
eloop_register_signal_reconfig(wpa_supplicant_reconfig, global);
return 0;
}
-@@ -8130,6 +8130,8 @@ void wpa_supplicant_deinit(struct wpa_gl
+@@ -8143,6 +8143,8 @@ void wpa_supplicant_deinit(struct wpa_gl
wpas_notify_supplicant_deinitialized(global);
--- a/hostapd/config_file.c
+++ b/hostapd/config_file.c
-@@ -5065,7 +5065,12 @@ struct hostapd_config * hostapd_config_r
+@@ -5102,7 +5102,12 @@ struct hostapd_config * hostapd_config_r
int errors = 0;
size_t i;
} else if (os_strcmp(buf, "vlan_bridge") == 0) {
--- a/src/ap/ap_drv_ops.c
+++ b/src/ap/ap_drv_ops.c
-@@ -387,8 +387,6 @@ int hostapd_set_wds_sta(struct hostapd_d
+@@ -390,8 +390,6 @@ int hostapd_set_wds_sta(struct hostapd_d
return -1;
if (hapd->conf->wds_bridge[0])
bridge = hapd->conf->wds_bridge;
} else if (os_strcmp(buf, "extended_key_id") == 0) {
--- a/src/ap/ap_config.h
+++ b/src/ap/ap_config.h
-@@ -1057,6 +1057,8 @@ struct hostapd_config {
+@@ -1066,6 +1066,8 @@ struct hostapd_config {
unsigned int track_sta_max_num;
unsigned int track_sta_max_age;
* ' ' (ascii 32): all environments
--- a/src/ap/beacon.c
+++ b/src/ap/beacon.c
-@@ -1567,7 +1567,7 @@ void handle_probe_req(struct hostapd_dat
+@@ -1573,7 +1573,7 @@ void handle_probe_req(struct hostapd_dat
if (hapd->conf->no_probe_resp_if_max_sta &&
is_multicast_ether_addr(mgmt->da) &&
is_multicast_ether_addr(mgmt->bssid) &&
{
--- a/src/ap/hostapd.h
+++ b/src/ap/hostapd.h
-@@ -754,6 +754,7 @@ void hostapd_cleanup_cs_params(struct ho
+@@ -789,6 +789,7 @@ void hostapd_cleanup_cs_params(struct ho
void hostapd_periodic_iface(struct hostapd_iface *iface);
int hostapd_owe_trans_get_info(struct hostapd_data *hapd);
void hostapd_ocv_check_csa_sa_query(void *eloop_ctx, void *timeout_ctx);
int bridge_hairpin; /* hairpin_mode on bridge members */
--- a/src/ap/wpa_auth_glue.c
+++ b/src/ap/wpa_auth_glue.c
-@@ -1777,8 +1777,12 @@ int hostapd_setup_wpa(struct hostapd_dat
+@@ -1759,8 +1759,12 @@ int hostapd_setup_wpa(struct hostapd_dat
wpa_key_mgmt_ft(hapd->conf->wpa_key_mgmt)) {
const char *ft_iface;
int bridge_hairpin; /* hairpin_mode on bridge members */
--- a/src/ap/ap_drv_ops.h
+++ b/src/ap/ap_drv_ops.h
-@@ -366,12 +366,12 @@ static inline int hostapd_drv_br_port_se
+@@ -371,12 +371,12 @@ static inline int hostapd_drv_br_port_se
static inline int hostapd_drv_br_set_net_param(struct hostapd_data *hapd,
enum drv_br_net_param param,
hapd->x_snoop_initialized = false;
--- a/src/drivers/driver.h
+++ b/src/drivers/driver.h
-@@ -4278,7 +4278,7 @@ struct wpa_driver_ops {
+@@ -4312,7 +4312,7 @@ struct wpa_driver_ops {
* Returns: 0 on success, negative (<0) on failure
*/
int (*br_set_net_param)(void *priv, enum drv_br_net_param param,
* get_wowlan - Get wake-on-wireless status
--- a/src/drivers/driver_nl80211.c
+++ b/src/drivers/driver_nl80211.c
-@@ -12376,7 +12376,7 @@ static const char * drv_br_net_param_str
+@@ -12472,7 +12472,7 @@ static const char * drv_br_net_param_str
static int wpa_driver_br_set_net_param(void *priv, enum drv_br_net_param param,
{
struct i802_bss *bss = priv;
char path[128];
-@@ -12402,8 +12402,11 @@ static int wpa_driver_br_set_net_param(v
+@@ -12498,8 +12498,11 @@ static int wpa_driver_br_set_net_param(v
return -EINVAL;
}
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 23 Dec 2021 19:18:33 +0100
-Subject: [PATCH] hostapd: only attempt to set qos map if supported by the
- driver
-
-Fixes issues with brcmfmac
-
---- a/src/ap/ap_drv_ops.c
-+++ b/src/ap/ap_drv_ops.c
-@@ -998,7 +998,8 @@ int hostapd_start_dfs_cac(struct hostapd
- int hostapd_drv_set_qos_map(struct hostapd_data *hapd,
- const u8 *qos_map_set, u8 qos_map_set_len)
- {
-- if (!hapd->driver || !hapd->driver->set_qos_map || !hapd->drv_priv)
-+ if (!hapd->driver || !hapd->driver->set_qos_map || !hapd->drv_priv ||
-+ !(hapd->iface->drv_flags & WPA_DRIVER_FLAGS_QOS_MAPPING))
- return 0;
- return hapd->driver->set_qos_map(hapd->drv_priv, qos_map_set,
- qos_map_set_len);
int acct_interim_interval;
--- a/src/ap/ieee802_1x.c
+++ b/src/ap/ieee802_1x.c
-@@ -601,6 +601,10 @@ int add_common_radius_attr(struct hostap
+@@ -600,6 +600,10 @@ int add_common_radius_attr(struct hostap
struct hostapd_radius_attr *attr;
int len;
--- a/src/ap/hostapd.c
+++ b/src/ap/hostapd.c
-@@ -1510,6 +1510,7 @@ int hostapd_setup_bss(struct hostapd_dat
+@@ -1582,6 +1582,7 @@ setup_mld:
os_memset(&das_conf, 0, sizeof(das_conf));
das_conf.port = conf->radius_das_port;
#ifndef CONFIG_NO_HOSTAPD_LOGGER
static void hostapd_logger_cb(void *ctx, const u8 *addr, unsigned int module,
-@@ -778,6 +779,11 @@ int main(int argc, char *argv[])
+@@ -788,6 +789,11 @@ int main(int argc, char *argv[])
if (os_program_init())
return -1;
int i;
list = ucv_array_new(vm);
- for (i = 0; i < iface->num_bss; i++) {
+ for (i = 0; iface->bss && i < iface->num_bss; i++) {
struct hostapd_data *hapd = iface->bss[i];
uc_value_t *val = hostapd_ucode_bss_get_uval(hapd);
PKG_NAME:=lldpd
PKG_VERSION:=1.0.17
-PKG_RELEASE:=3
+PKG_RELEASE:=5
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/lldpd/lldpd/releases/download/$(PKG_VERSION)/
config_get _ifaces 'config' "$2"
local _iface _ifnames=""
+ # Set noglob to prevent '*' capturing diverse file names in the for ... in
+ set -o noglob
for _iface in $_ifaces; do
- local _ifname=""
- if network_get_device _ifname "$_iface" || [ -e "/sys/class/net/$_iface" ]; then
- append _ifnames "${_ifname:-$_iface}" ","
+
+ local _l2device=""
+ if network_get_physdev _l2device "$_iface" || [ -e "/sys/class/net/$_iface" ]; then
+ append _ifnames "${_l2device:-$_iface}" ","
+ else
+ # Glob case (interface is e.g. '!eth1' or 'eth*' or '*')
+ append _ifnames "$_iface" ","
fi
done
+ # Turn noglob off i.e. enable glob again
+ set +o noglob
export -n "${1}=$_ifnames"
}
local lldp_mgmt_ip
config_get lldp_mgmt_ip 'config' 'lldp_mgmt_ip'
+ # Configurable capabilities in lldpd >= v1.0.15: defaults to 'unconfigured' i.e. kernel info
local lldp_syscapabilities
config_get lldp_syscapabilities 'config' 'lldp_syscapabilities'
+ # Configurable capabilities in lldpd >= v1.0.15: defaults to on in lldpd
+ local lldp_capability_advertisements
+ config_get_bool lldp_capability_advertisements 'config' 'lldp_capability_advertisements' 1
+
+ # Broadcast management address in lldpd >= 0.7.15: defaults to on in lldpd
+ local lldp_mgmt_addr_advertisements
+ config_get_bool lldp_mgmt_addr_advertisements 'config' 'lldp_mgmt_addr_advertisements' 1
+
if [ "$CONFIG_LLDPD_WITH_LLDPMED" = "y" ]; then
local lldpmed_fast_start
config_get_bool lldpmed_fast_start 'config' 'lldpmed_fast_start' 0
[ -n "$lldp_hostname" ] && echo "configure system hostname" "\"$lldp_hostname\"" >> "$LLDPD_CONF"
[ -n "$lldp_mgmt_ip" ] && echo "configure system ip management pattern" "\"$lldp_mgmt_ip\"" >> "$LLDPD_CONF"
[ -n "$lldp_syscapabilities" ] && echo "configure system capabilities enabled $lldp_syscapabilities" >> "$LLDPD_CONF"
+
if [ "$CONFIG_LLDPD_WITH_LLDPMED" = "y" ] && [ "$lldpmed_fast_start" -gt 0 ]; then
if [ "$lldpmed_fast_start_tx_interval" -gt 0 ]; then
echo "configure med fast-start tx-interval $lldpmed_fast_start_tx_interval" >> "$LLDPD_CONF"
[ -n "$lldp_platform" ] && echo "configure system platform" "\"$lldp_platform\"" >> "$LLDPD_CONF"
[ -n "$lldp_tx_interval" ] && echo "configure lldp tx-interval $lldp_tx_interval" >> "$LLDPD_CONF"
[ "$lldp_tx_hold" -gt 0 ] && echo "configure lldp tx-hold $lldp_tx_hold" >> "$LLDPD_CONF"
+ [ "$lldp_capability_advertisements" -gt 0 ] && echo "configure lldp capabilities-advertisements" >> "$LLDPD_CONF" ||\
+ echo "unconfigure lldp capabilities-advertisements" >> "$LLDPD_CONF"
+ [ "$lldp_mgmt_addr_advertisements" -gt 0 ] && echo "configure lldp management-addresses-advertisements" >> "$LLDPD_CONF" ||\
+ echo "unconfigure lldp management-addresses-advertisements" >> "$LLDPD_CONF"
# Since lldpd's sysconfdir is /tmp, we'll symlink /etc/lldpd.d to /tmp/$LLDPD_CONFS_DIR
[ -e "$LLDPD_CONFS_DIR" ] || ln -s /etc/lldpd.d "$LLDPD_CONFS_DIR"
return 0
fi
- $LLDPCLI -u "$LLDPSOCKET" 2>&1 /dev/null <<-EOF
+ $LLDPCLI -u "$LLDPSOCKET" >/dev/null 2>&1 <<-EOF
pause
unconfigure lldp custom-tlv
+ unconfigure lldp capabilities-advertisements
+ unconfigure lldp management-addresses-advertisements
+ # unconfigures user-configured system capabilities, and instead uses the kernel information:
+ unconfigure system capabilities enabled
unconfigure system interface pattern
unconfigure system description
unconfigure system hostname
unconfigure system platform
EOF
if [ "$CONFIG_LLDPD_WITH_LLDPMED" = "y" ]; then
- $LLDPCLI -u "$LLDPSOCKET" 2>&1 /dev/null <<-EOF
+ $LLDPCLI -u "$LLDPSOCKET" >/dev/null 2>&1 <<-EOF
unconfigure med fast-start
EOF
# Rewrite lldpd.conf
# If something changed it should be included by the lldpcli call
write_lldpd_conf
- $LLDPCLI -u "$LLDPSOCKET" -c "$LLDPD_CONF" -c "$LLDPD_CONFS_DIR" 2>&1 /dev/null
+ $LLDPCLI -u "$LLDPSOCKET" -c "$LLDPD_CONF" -c "$LLDPD_CONFS_DIR" >/dev/null 2>&1
# Broadcast update over the wire
- $LLDPCLI -u "$LLDPSOCKET" 2>&1 /dev/null <<-EOF
+ $LLDPCLI -u "$LLDPSOCKET" >/dev/null 2>&1 <<-EOF
resume
update
EOF
}
stop_service() {
- rm -rf ${LLDPD_RUN} "$LLDPSOCKET" 2> /dev/null
+ rm -rf ${LLDPD_RUN} "$LLDPSOCKET" >/dev/null 2>&1
}
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/odhcpd.git
-PKG_MIRROR_HASH:=08fddf4294929d1713e0c3f7b258f8c7bf4abe731d5f34fceb797faa411f7a58
-PKG_SOURCE_DATE:=2023-10-24
-PKG_SOURCE_VERSION:=d8118f6e76e5519881f9a37137c3a06b3cb60fd2
+PKG_MIRROR_HASH:=f6e1c18551a00e01229fa12caa7b3fe33ad82785150fedcbe615fcc651ba2876
+PKG_SOURCE_DATE:=2024-05-08
+PKG_SOURCE_VERSION:=a29882318a4ccb3ae26f7cc0145e06ad4ead224b
PKG_MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>
PKG_LICENSE:=GPL-2.0
[ -n "$EXTENDPREFIX" ] && json_add_string extendprefix 1
[ -n "$IP6TABLE" ] && json_add_string ip6table $IP6TABLE
[ -n "$PEERDNS" ] && json_add_boolean peerdns $PEERDNS
+ [ "$NOSOURCEFILTER" = "1" ] && json_add_boolean sourcefilter "0"
json_close_object
ubus call network add_dynamic "$(json_dump)"
fi
proto_config_add_boolean persist
proto_config_add_int maxfail
proto_config_add_int holdoff
+ proto_config_add_boolean sourcefilter
}
ppp_generic_setup() {
local config="$1"; shift
local localip
- json_get_vars ip6table demand keepalive keepalive_adaptive username password pppd_options pppname unnumbered persist maxfail holdoff peerdns
+ json_get_vars ip6table demand keepalive keepalive_adaptive username password pppd_options pppname unnumbered persist maxfail holdoff peerdns sourcefilter
[ ! -e /proc/sys/net/ipv6 ] && ipv6=0 || json_get_var ipv6 ipv6
[ "${keepalive_adaptive:-1}" -lt 1 ] && lcp_adaptive=""
[ -n "$connect" ] || json_get_var connect connect
[ -n "$disconnect" ] || json_get_var disconnect disconnect
+ [ "$sourcefilter" = "0" ] || sourcefilter=""
proto_run_command "$config" /usr/sbin/pppd \
nodetach ipparam "$config" \
${autoipv6:+set AUTOIPV6=1} \
${ip6table:+set IP6TABLE=$ip6table} \
${peerdns:+set PEERDNS=$peerdns} \
+ ${sourcefilter:+set NOSOURCEFILTER=1} \
nodefaultroute \
usepeerdns \
$demand $persist maxfail $maxfail \
PKG_SOURCE_URL=$(PROJECT_GIT)/project/ustp.git
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2021-09-21
-PKG_SOURCE_VERSION:=462b3a491347e452c15220861949b1d6371fa59e
-PKG_MIRROR_HASH:=c3373b369b127c26d4a79425631cb5db83ef479ab21d164da879b35942539dfb
+PKG_SOURCE_DATE:=2023-05-29
+PKG_SOURCE_VERSION:=a85a5bc83bde5b485319ca12b6e32c4b7f0b120f
+PKG_MIRROR_HASH:=b907b91989320eb8916e719ced9bdce96b8c5db6abefcee35e25fb112ad5b27f
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_LICENSE:=GPL-2.0
#
-# Copyright (C) 2020-2023 Tony Ambardar <itugrok@yahoo.com>
+# Copyright (C) 2020-2024 Tony Ambardar <itugrok@yahoo.com>
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
include $(TOPDIR)/rules.mk
-PKG_NAME:=bpftools
-PKG_VERSION:=7.3.0
+PKG_NAME:=bpftool
+PKG_VERSION:=7.4.0
PKG_RELEASE:=1
PKG_SOURCE_URL:=https://github.com/libbpf/bpftool
-PKG_MIRROR_HASH:=42030a007714aa075fbd402ccb0196e4892344fb7215b4f51a99b633cc5104fa
+PKG_MIRROR_HASH:=18e22f72e67ff402b5ecaf314445f25c40bfe23299cb783b5834a496297c51ed
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_VERSION:=v7.3.0
+PKG_SOURCE_VERSION:=v7.4.0
PKG_MAINTAINER:=Tony Ambardar <itugrok@yahoo.com>
-PKG_BUILD_FLAGS:=no-mips16
+PKG_BUILD_FLAGS:=no-mips16 gc-sections lto
PKG_BUILD_PARALLEL:=1
PKG_INSTALL:=1
eBPF programs and jited code.
endef
-TARGET_CFLAGS += -ffunction-sections -fdata-sections -flto
-TARGET_LDFLAGS += -Wl,--gc-sections -flto
-
ifeq ($(BUILD_VARIANT),full)
full:=1
else
full:=0
endif
-MAKE_VARS = \
- EXTRA_CFLAGS="$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)" \
- LDFLAGS="$(TARGET_LDFLAGS)"
-
MAKE_FLAGS += \
OUTPUT="$(PKG_BUILD_DIR)/" \
prefix="/usr" \
+++ /dev/null
---- a/libbpf/src/Makefile
-+++ b/libbpf/src/Makefile
-@@ -34,6 +34,7 @@ ALL_CFLAGS := $(INCLUDES)
-
- SHARED_CFLAGS += -fPIC -fvisibility=hidden -DSHARED
-
-+CFLAGS = $(EXTRA_CFLAGS)
- CFLAGS ?= -g -O2 -Werror -Wall -std=gnu89
- ALL_CFLAGS += $(CFLAGS) \
- -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 \
---- a/libbpf/include/linux/list.h
-+++ b/libbpf/include/linux/list.h
-@@ -3,6 +3,8 @@
- #ifndef __LINUX_LIST_H
- #define __LINUX_LIST_H
-
-+#include <linux/types.h>
-+
- #define LIST_HEAD_INIT(name) { &(name), &(name) }
- #define LIST_HEAD(name) \
- struct list_head name = LIST_HEAD_INIT(name)
--- a/src/Makefile
+++ b/src/Makefile
@@ -73,10 +73,10 @@ CFLAGS += -W -Wall -Wextra -Wno-unused-p
proto_config_add_string delay
proto_config_add_string mode
proto_config_add_string pdptype
+ proto_config_add_boolean sourcefilter
proto_config_add_int profile
proto_config_add_defaults
}
local manufacturer initialize setmode connect finalize devname devpath ifpath
local device ifname apn auth username password pincode delay mode pdptype profile $PROTO_DEFAULT_OPTIONS
- json_get_vars device ifname apn auth username password pincode delay mode pdptype profile $PROTO_DEFAULT_OPTIONS
+ json_get_vars device ifname apn auth username password pincode delay mode pdptype sourcefilter profile $PROTO_DEFAULT_OPTIONS
local context_type
json_add_string ifname "@$interface"
json_add_string proto "dhcpv6"
json_add_string extendprefix 1
+ [ "$sourcefilter" = "0" ] && json_add_boolean sourcefilter "0"
proto_add_dynamic_defaults
[ -n "$zone" ] && {
json_add_string zone "$zone"
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=ipset
-PKG_VERSION:=7.17
+PKG_VERSION:=7.21
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://ipset.netfilter.org
-PKG_HASH:=be49c9ff489dd6610cad6541e743c3384eac96e9f24707da7b3929d8f2ac64d8
+PKG_HASH:=e2c6ce4fcf3acb3893ca5d35c86935f80ad76fc5ccae601185842df760e0bc69
PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
PKG_LICENSE:=GPL-2.0
--- /dev/null
+--- a/src/ipset.c
++++ b/src/ipset.c
+@@ -6,8 +6,8 @@
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+-#define _GNU_SOURCE
+ #include <assert.h> /* assert */
++#include <libgen.h> /* basename */
+ #include <stdio.h> /* fprintf */
+ #include <stdlib.h> /* exit */
+ #include <string.h> /* strcmp */
PKG_BUILD_FLAGS:=gc-sections no-lto
PKG_BUILD_PARALLEL:=1
PKG_LICENSE:=GPL-2.0
-PKG_CPE_ID:=cpe:/a:netfilter_core_team:iptables
+PKG_CPE_ID:=cpe:/a:netfilter:iptables
include $(INCLUDE_DIR)/package.mk
ifeq ($(DUMP),)
[ -e /proc/sys/net/ipv6 ] && proto_config_add_string ipv6
proto_config_add_string dhcp
proto_config_add_string dhcpv6
+ proto_config_add_boolean sourcefilter
proto_config_add_string pdptype
proto_config_add_int mtu
proto_config_add_defaults
local device apn pincode delay auth username password allow_roaming allow_partner
local dhcp dhcpv6 pdptype ip4table ip6table mtu $PROTO_DEFAULT_OPTIONS
json_get_vars device apn pincode delay auth username password allow_roaming allow_partner
- json_get_vars dhcp dhcpv6 pdptype ip4table ip6table mtu $PROTO_DEFAULT_OPTIONS
+ json_get_vars dhcp dhcpv6 sourcefilter pdptype ip4table ip6table mtu $PROTO_DEFAULT_OPTIONS
[ ! -e /proc/sys/net/ipv6 ] && ipv6=0 || json_get_var ipv6 ipv6
echo "mbim[$$]" "Starting DHCPv6 on $ifname"
json_add_string proto "dhcpv6"
json_add_string extendprefix 1
+ [ "$sourcefilter" = "0" ] && json_add_boolean sourcefilter "0"
fi
[ "$peerdns" = 0 -a "$dhcpv6" != 1 ] || {
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/uqmi.git
-PKG_SOURCE_DATE:=2024-01-16
-PKG_SOURCE_VERSION:=c3488b831ce6285c8107704156b9b8ed7d59deb3
-PKG_MIRROR_HASH:=1aa576e46dfb6528ef12f5fd1b626585d565bbcf9119cde302cc34d732c75076
+PKG_SOURCE_DATE:=2024-04-24
+PKG_SOURCE_VERSION:=e7207bec95f02f2f7a98254d642186a082af838d
+PKG_MIRROR_HASH:=53e83720472f07cb9bb3e2b68ea6c379fc8c43ed8f93227bcb3d06c94a32a669
PKG_MAINTAINER:=Matti Laakso <malaakso@elisanet.fi>
PKG_LICENSE:=GPL-2.0
TARGET_CFLAGS += \
-I$(STAGING_DIR)/usr/include \
- -Wno-error=dangling-pointer \
-Wno-error=maybe-uninitialized
CMAKE_OPTIONS += \
define Package/uqmi/install
$(INSTALL_DIR) $(1)/sbin
- $(INSTALL_BIN) $(PKG_BUILD_DIR)/uqmi $(1)/sbin/
+ $(INSTALL_BIN) $(PKG_BUILD_DIR)/uqmi/uqmi $(1)/sbin/
$(CP) ./files/* $(1)/
endef
proto_config_add_int v6profile
proto_config_add_boolean dhcp
proto_config_add_boolean dhcpv6
+ proto_config_add_boolean sourcefilter
proto_config_add_boolean autoconnect
proto_config_add_int plmn
proto_config_add_int timeout
local profile_pdptype
json_get_vars device apn v6apn auth username password pincode delay modes
- json_get_vars pdptype profile v6profile dhcp dhcpv6 autoconnect plmn ip4table
+ json_get_vars pdptype profile v6profile dhcp dhcpv6 sourcefilter autoconnect plmn ip4table
json_get_vars ip6table timeout mtu $PROTO_DEFAULT_OPTIONS
[ "$timeout" = "" ] && timeout="10"
proto_add_dynamic_defaults
# RFC 7278: Extend an IPv6 /64 Prefix to LAN
json_add_string extendprefix 1
+ [ "$sourcefilter" = "0" ] && json_add_boolean sourcefilter "0"
[ -n "$zone" ] && json_add_string zone "$zone"
json_close_object
ubus call network add_dynamic "$(json_dump)"
CFLAGS="$(TARGET_CFLAGS)" \
LDFLAGS="$(TARGET_LDFLAGS)" \
CLANG="$(CLANG)" \
- BPF_TARGET="$(BPF_TARGET)" \
- LLC="$(LLVM_LLC)"
+ BPF_TARGET="$(BPF_ARCH)-linux-gnu" \
+ LLC="$(LLVM_LLC)" \
+ BPF_LDFLAGS="-march=$(BPF_TARGET) -mcpu=v3"
+
+ifneq ($(findstring s,$(OPENWRT_VERBOSE)),)
+ MAKE_FLAGS+=V=1
+endif
MAKE_VARS += \
PREFIX=/usr \
define Build/Configure
$(call Build/Configure/Default)
- echo "BPF_CFLAGS += -I$(BPF_HEADERS_DIR)/tools/lib -fno-stack-protector" >> $(PKG_BUILD_DIR)/config.mk
+ echo "BPF_CFLAGS += $(BPF_CFLAGS) -Wno-error -fno-stack-protector" >> $(PKG_BUILD_DIR)/config.mk
endef
define Build/InstallDev
--- /dev/null
+From 1f160c287c14b4300c4248752e20da5981c9763e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 18 Jan 2023 19:00:54 +0100
+Subject: [PATCH] libxdp: Use __noinline__ reserved attribute for XDP
+ dispatcher
+
+The use of noinline is wrong as noline is not a reserved attribute and
+with gcc12 this became an error. Use the reserved __noinline__ attribute
+to fix compilation error.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+[a.heider: adapt lib/libxdp/protocol.org too]
+Signed-off-by: Andre Heider <a.heider@gmail.com>
+---
+ lib/libxdp/protocol.org | 2 +-
+ lib/libxdp/xdp-dispatcher.c.in | 4 ++--
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+--- a/lib/libxdp/protocol.org
++++ b/lib/libxdp/protocol.org
+@@ -54,7 +54,7 @@ static volatile const struct xdp_dispatc
+ /* The volatile return value prevents the compiler from assuming it knows the
+ * return value and optimising based on that.
+ */
+-__attribute__ ((noinline))
++__attribute__ ((__noinline__))
+ int prog0(struct xdp_md *ctx) {
+ volatile int ret = XDP_DISPATCHER_RETVAL;
+
+--- a/lib/libxdp/xdp-dispatcher.c.in
++++ b/lib/libxdp/xdp-dispatcher.c.in
+@@ -30,7 +30,7 @@ static volatile const struct xdp_dispatc
+ * return value and optimising based on that.
+ */
+ forloop(`i', `0', NUM_PROGS,
+-`__attribute__ ((noinline))
++`__attribute__ ((__noinline__))
+ int format(`prog%d', i)(struct xdp_md *ctx) {
+ volatile int ret = XDP_DISPATCHER_RETVAL;
+
+@@ -40,7 +40,7 @@ int format(`prog%d', i)(struct xdp_md *c
+ }
+ ')
+
+-__attribute__ ((noinline))
++__attribute__ ((__noinline__))
+ int compat_test(struct xdp_md *ctx) {
+ volatile int ret = XDP_DISPATCHER_RETVAL;
+
--- /dev/null
+From bc2a11227b5bed29d33926d5ff7e707228db9e87 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 18 Jan 2023 20:07:58 +0100
+Subject: [PATCH] headers: xdp: drop vlan_hdr as already defined
+
+Drop vlan_hdr as already defined by bpf headers.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ headers/xdp/parsing_helpers.h | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+--- a/headers/xdp/parsing_helpers.h
++++ b/headers/xdp/parsing_helpers.h
+@@ -33,16 +33,6 @@ struct hdr_cursor {
+ };
+
+ /*
+- * struct vlan_hdr - vlan header
+- * @h_vlan_TCI: priority and VLAN ID
+- * @h_vlan_encapsulated_proto: packet type ID or len
+- */
+-struct vlan_hdr {
+- __be16 h_vlan_TCI;
+- __be16 h_vlan_encapsulated_proto;
+-};
+-
+-/*
+ * Struct icmphdr_common represents the common part of the icmphdr and icmp6hdr
+ * structures.
+ */
--- /dev/null
+From 0388d7447de027e0d2369d6b8a9c58ea0f8f027c Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 18 Jan 2023 20:37:12 +0100
+Subject: [PATCH] xdp-dump: add missing perf_event include for bpf and xdp
+
+Add missing perf_event include needed for struct perf_event_header for
+bpf and xdp.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ xdp-dump/xdpdump_bpf.c | 1 +
+ xdp-dump/xdpdump_xdp.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/xdp-dump/xdpdump_bpf.c
++++ b/xdp-dump/xdpdump_bpf.c
+@@ -4,6 +4,7 @@
+ * Include files
+ *****************************************************************************/
+ #include <stdbool.h>
++#include <linux/perf_event.h>
+ #include <linux/bpf.h>
+ #include <bpf/bpf_helpers.h>
+ #include <bpf/bpf_trace_helpers.h>
+--- a/xdp-dump/xdpdump_xdp.c
++++ b/xdp-dump/xdpdump_xdp.c
+@@ -4,6 +4,7 @@
+ * Include files
+ *****************************************************************************/
+ #include <stdbool.h>
++#include <linux/perf_event.h>
+ #include <linux/bpf.h>
+ #include <bpf/bpf_helpers.h>
+ #include <bpf/bpf_trace_helpers.h>
--- /dev/null
+From cb1ef3322671a67e2050a3eee18b49cdb4ed4bed Mon Sep 17 00:00:00 2001
+From: Andre Heider <a.heider@gmail.com>
+Date: Wed, 18 Jan 2023 20:54:41 +0100
+Subject: [PATCH] libxdp: fix compilation on multiarch systems
+
+Multiarch systems require an additional include path, which is covered
+by ARCH_INCLUDES here. Just as lib/util, add it to BPF_CFLAGS.
+
+Fixes compilation on debian:
+
+In file included from xdp-dispatcher.c:3:
+In file included from ../../headers/linux/bpf.h:11:
+/usr/include/linux/types.h:5:10: fatal error: 'asm/types.h' file not found
+
+Signed-off-by: Andre Heider <a.heider@gmail.com>
+---
+ lib/libxdp/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/lib/libxdp/Makefile
++++ b/lib/libxdp/Makefile
+@@ -30,7 +30,7 @@ PC_FILE := $(OBJDIR)/libxdp.pc
+ TEMPLATED_SOURCES := xdp-dispatcher.c
+
+ CFLAGS += -I$(HEADER_DIR)
+-BPF_CFLAGS += -I$(HEADER_DIR)
++BPF_CFLAGS += -I$(HEADER_DIR) $(ARCH_INCLUDES)
+
+
+ ifndef BUILD_STATIC_ONLY
--- /dev/null
+From e2d8eae9477f6ba41ab75ad77202f235e34c04f7 Mon Sep 17 00:00:00 2001
+From: Andre Heider <a.heider@gmail.com>
+Date: Wed, 18 Jan 2023 22:30:23 +0100
+Subject: [PATCH] lib: allow overwriting -W* flags via BPF_CFLAGS
+
+The bpf header file situation is a mess, and the default warning
+compiler flags may not be suitable everywhere, especially with -Werror
+in the mix.
+
+Move BPF_CFLAGS further down, so these can be overwritten by builders.
+
+Signed-off-by: Andre Heider <a.heider@gmail.com>
+---
+ lib/common.mk | 2 +-
+ lib/libxdp/Makefile | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/lib/common.mk
++++ b/lib/common.mk
+@@ -108,12 +108,12 @@ $(XDP_OBJ): %.o: %.c $(KERN_USER_H) $(EX
+ $(QUIET_CLANG)$(CLANG) -S \
+ -target $(BPF_TARGET) \
+ -D __BPF_TRACING__ \
+- $(BPF_CFLAGS) \
+ -Wall \
+ -Wno-unused-value \
+ -Wno-pointer-sign \
+ -Wno-compare-distinct-pointer-types \
+ -Werror \
++ $(BPF_CFLAGS) \
+ -O2 -emit-llvm -c -g -o ${@:.o=.ll} $<
+ $(QUIET_LLC)$(LLC) -march=$(BPF_TARGET) -filetype=obj -o $@ ${@:.o=.ll}
+
+--- a/lib/libxdp/Makefile
++++ b/lib/libxdp/Makefile
+@@ -139,12 +139,12 @@ $(XDP_OBJS): %.o: %.c $(BPF_HEADERS) $(L
+ $(QUIET_CLANG)$(CLANG) -S \
+ -target $(BPF_TARGET) \
+ -D __BPF_TRACING__ \
+- $(BPF_CFLAGS) \
+ -Wall \
+ -Wno-unused-value \
+ -Wno-pointer-sign \
+ -Wno-compare-distinct-pointer-types \
+ -Werror \
++ $(BPF_CFLAGS) \
+ -O2 -emit-llvm -c -g -o ${@:.o=.ll} $<
+ $(QUIET_LLC)$(LLC) -march=$(BPF_TARGET) -filetype=obj -o $@ ${@:.o=.ll}
+
--- /dev/null
+From 7b00d4a90af1d7bff50833ffe1216cf59592353a Mon Sep 17 00:00:00 2001
+From: Andre Heider <a.heider@gmail.com>
+Date: Wed, 18 Jan 2023 22:42:28 +0100
+Subject: [PATCH] Add BPF_LDFLAGS to allow overwriting llc's -march argument
+
+The argument to clang's -target isn't necessarily the same as to
+llc's -march.
+
+Analogue to BPF_CFLAGS, introduce BPF_LDFLAGS to allow e.g.:
+BPF_TARGET="mipsel-linux-gnu" BPF_LDFLAGS="-march=bpfel -mcpu=v3"
+
+Signed-off-by: Andre Heider <a.heider@gmail.com>
+---
+ configure | 2 ++
+ lib/common.mk | 2 +-
+ lib/libxdp/Makefile | 2 +-
+ 3 files changed, 4 insertions(+), 2 deletions(-)
+
+--- a/configure
++++ b/configure
+@@ -17,10 +17,12 @@ check_opts()
+ : ${DYNAMIC_LIBXDP:=0}
+ : ${MAX_DISPATCHER_ACTIONS:=10}
+ : ${BPF_TARGET:=bpf}
++ : ${BPF_LDFLAGS:=-march=$(BPF_TARGET)}
+ echo "PRODUCTION:=${PRODUCTION}" >>$CONFIG
+ echo "DYNAMIC_LIBXDP:=${DYNAMIC_LIBXDP}" >>$CONFIG
+ echo "MAX_DISPATCHER_ACTIONS:=${MAX_DISPATCHER_ACTIONS}" >>$CONFIG
+ echo "BPF_TARGET:=${BPF_TARGET}" >>$CONFIG
++ echo "BPF_LDFLAGS:=${BPF_LDFLAGS}" >>$CONFIG
+ }
+
+ find_tool()
+--- a/lib/common.mk
++++ b/lib/common.mk
+@@ -115,7 +115,7 @@ $(XDP_OBJ): %.o: %.c $(KERN_USER_H) $(EX
+ -Werror \
+ $(BPF_CFLAGS) \
+ -O2 -emit-llvm -c -g -o ${@:.o=.ll} $<
+- $(QUIET_LLC)$(LLC) -march=$(BPF_TARGET) -filetype=obj -o $@ ${@:.o=.ll}
++ $(QUIET_LLC)$(LLC) $(BPF_LDFLAGS) -filetype=obj -o $@ ${@:.o=.ll}
+
+ .PHONY: man
+ ifeq ($(EMACS),)
+--- a/lib/libxdp/Makefile
++++ b/lib/libxdp/Makefile
+@@ -146,7 +146,7 @@ $(XDP_OBJS): %.o: %.c $(BPF_HEADERS) $(L
+ -Werror \
+ $(BPF_CFLAGS) \
+ -O2 -emit-llvm -c -g -o ${@:.o=.ll} $<
+- $(QUIET_LLC)$(LLC) -march=$(BPF_TARGET) -filetype=obj -o $@ ${@:.o=.ll}
++ $(QUIET_LLC)$(LLC) $(BPF_LDFLAGS) -filetype=obj -o $@ ${@:.o=.ll}
+
+ .PHONY: man
+ ifeq ($(EMACS),)
--- /dev/null
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=apk
+PKG_RELEASE:=1
+
+PKG_SOURCE_URL=https://gitlab.alpinelinux.org/alpine/apk-tools.git
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_DATE:=2024-05-19
+PKG_SOURCE_VERSION:=825681118d05ca5801c6b3852a70a42499e57def
+PKG_MIRROR_HASH:=adc07e3320e8d780bbbd3d95d3c6c6ce259f3dbf97ab0a4ff9dc4853af21e04f
+
+PKG_VERSION=3.0.0_pre$(subst -,,$(PKG_SOURCE_DATE))
+
+PKG_MAINTAINER:=Paul Spooren <mail@aparcar.org>
+PKG_LICENSE:=GPL-2.0-only
+PKG_LICENSE_FILES:=LICENSE
+PKG_INSTALL:=1
+
+HOST_BUILD_PREFIX:=$(STAGING_DIR_HOST)
+PKG_BUILD_DEPENDS:=lua/host
+
+include $(INCLUDE_DIR)/package.mk
+include $(INCLUDE_DIR)/host-build.mk
+include $(INCLUDE_DIR)/meson.mk
+
+define Package/apk/default
+ SECTION:=base
+ CATEGORY:=Base system
+ TITLE:=apk package manager
+ DEPENDS:=+zlib
+ URL:=$(PKG_SOURCE_URL)
+ PROVIDES:=apk
+endef
+
+define Package/apk-mbedtls
+ $(Package/apk/default)
+ TITLE += (mbedtls)
+ DEPENDS +=+libmbedtls
+ VARIANT:=mbedtls
+ DEFAULT_VARIANT:=1
+ CONFLICTS:=apk-openssl
+endef
+
+define Package/apk-openssl
+ $(Package/apk/default)
+ TITLE += (openssl)
+ DEPENDS +=+libopenssl
+ VARIANT:=openssl
+endef
+
+MESON_HOST_VARS+=VERSION=$(PKG_VERSION)
+MESON_VARS+=VERSION=$(PKG_VERSION)
+
+MESON_HOST_ARGS += \
+ -Dhelp=disabled \
+ -Dcompressed-help=false \
+ -Ddocs=disabled \
+ -Dcrypto_backend=openssl \
+ -Dzstd=false
+
+MESON_ARGS += \
+ -Dlua_version=5.1 \
+ -Dcompressed-help=false \
+ -Ddocs=disabled \
+ -Durl_backend=wget \
+ -Dcrypto_backend=$(BUILD_VARIANT) \
+ -Dzstd=false
+
+HOST_LDFLAGS += \
+ -Wl,-rpath $(STAGING_DIR_HOST)/lib
+
+define Package/apk/default/install
+ $(INSTALL_DIR) $(1)/lib/apk/db
+
+ $(INSTALL_DIR) $(1)/usr/bin
+ $(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/apk $(1)/usr/bin/apk
+
+ $(INSTALL_DIR) $(1)/usr/lib
+ $(CP) $(PKG_INSTALL_DIR)/usr/lib/libapk.so.* $(1)/usr/lib/
+endef
+
+Package/apk-mbedtls/install = $(Package/apk/default/install)
+Package/apk-openssl/install = $(Package/apk/default/install)
+
+$(eval $(call BuildPackage,apk-mbedtls))
+$(eval $(call BuildPackage,apk-openssl))
+$(eval $(call HostBuild))
--- /dev/null
+From 9918c683fcc2f148328332d58d030ec5750a1473 Mon Sep 17 00:00:00 2001
+From: Paul Spooren <mail@aparcar.org>
+Date: Sat, 19 Feb 2022 17:20:37 +0100
+Subject: [PATCH 1/4] openwrt: move layer db to temp folder
+
+Signed-off-by: Paul Spooren <mail@aparcar.org>
+---
+ src/database.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/src/database.c
++++ b/src/database.c
+@@ -1604,7 +1604,7 @@ const char *apk_db_layer_name(int layer)
+ {
+ switch (layer) {
+ case APK_DB_LAYER_ROOT: return "lib/apk/db";
+- case APK_DB_LAYER_UVOL: return "lib/apk/db-uvol";
++ case APK_DB_LAYER_UVOL: return "tmp/run/uvol/.meta/apk";
+ default:
+ assert("invalid layer");
+ return 0;
#include <endian.h>
#include <string.h>
#include <errno.h>
+#include <netinet/in.h>
#include <sys/ioctl.h>
#include <mtd/mtd-user.h>
size_t block_offset;
if (quiet < 2)
- fprintf(stderr, "Trying to fix trx header in %s at 0x%x...\n", mtd, offset);
+ fprintf(stderr, "Trying to fix trx header in %s at 0x%zx...\n", mtd, offset);
fd = mtd_check_open(mtd);
if(fd < 0) {
trx->crc32 = STORE32_LE(crc32buf(buf, data_size));
if (mtd_erase_block(fd, block_offset)) {
- fprintf(stderr, "Can't erease block at 0x%x (%s)\n", block_offset, strerror(errno));
+ fprintf(stderr, "Can't erease block at 0x%zx (%s)\n", block_offset, strerror(errno));
exit(1);
}
#!/bin/sh
-[ -f /etc/opkg.conf ] && grep -q "src\/" /etc/opkg.conf || exit 0
+[ -f /etc/opkg.conf ] && grep -q "src/" /etc/opkg.conf || exit 0
echo -e "# Old feeds from previous image\n# Uncomment to reenable\n" >> /etc/opkg/customfeeds.conf
sed -n "s/.*\(src\/.*\)/# \1/p" /etc/opkg.conf >> /etc/opkg/customfeeds.conf
}
procd_add_mdns_service() {
- local service proto port
+ local service proto port txt_count=0
service=$1; shift
proto=$1; shift
port=$1; shift
json_add_object "${service}_$port"
json_add_string "service" "_$service._$proto.local"
json_add_int port "$port"
- [ -n "$1" ] && {
- json_add_array txt
- for txt in "$@"; do json_add_string "" "$txt"; done
- json_select ..
- }
+ for txt in "$@"; do
+ [ -z "$txt" ] && continue
+ txt_count=$((txt_count+1))
+ [ $txt_count -eq 1 ] && json_add_array txt
+ json_add_string "" "$txt"
+ done
+ [ $txt_count -gt 0 ] && json_select ..
+
json_select ..
}
$(eval $(call BuildPackage,rpcd))
$(eval $(call BuildPlugin,file,,Provides ubus calls for file and directory operations.))
$(eval $(call BuildPlugin,rpcsys,,Provides ubus calls for sysupgrade and password changing.))
-$(eval $(call BuildPlugin,iwinfo,+libiwinfo,Provides ubus calls for accessing iwinfo data.,libiwinfo (>= 2023-01-21)))
+$(eval $(call BuildPlugin,iwinfo,+libiwinfo,Provides ubus calls for accessing iwinfo data.,libiwinfo (>=2023.01.21)))
$(eval $(call BuildPlugin,ucode,+libucode,Allows implementing plugins using ucode scripts.))
include $(TOPDIR)/rules.mk
PKG_NAME:=ubox
-PKG_RELEASE:=2
+PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/ubox.git
-PKG_SOURCE_DATE:=2024-01-24
-PKG_SOURCE_VERSION:=2c5887cb46883a28d69071c4349c3dabbbe3972c
-PKG_MIRROR_HASH:=5b7b00c358cc53b842c25e6f6dd21bf429d4913204a8186a72b13447658927cf
+PKG_SOURCE_DATE:=2024-04-26
+PKG_SOURCE_VERSION:=85f1053019caf4cd333795760950235ee4529ba7
+PKG_MIRROR_HASH:=9e3fb6ab94854405fb91626a673b0547a061582c552ce719691be1bc8818da6c
CMAKE_INSTALL:=1
PKG_LICENSE:=GPL-2.0
--- /dev/null
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=audit-userspace
+PKG_VERSION:=3.1.4
+PKG_RELEASE:=2
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
+PKG_SOURCE_URL:=https://github.com/linux-audit/audit-userspace/archive/refs/tags/v$(PKG_VERSION).tar.gz?
+PKG_HASH:=aec501760acd13ebbe00e78b9b59f795d16a430b1d673628e346cd18905c594b
+PKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>
+PKG_LICENSE:=GPL-2.0-or-later
+PKG_LICENSE_FILES:=COPYING
+PKG_CPE_ID:=cpe:/a:linux_audit_project:linux_audit
+
+PKG_CONFIG_DEPENDS:=CONFIG_KERNEL_IO_URING
+PKG_FIXUP:=autoreconf
+
+PKG_BUILD_FLAGS:=no-mips16
+PKG_INSTALL:=1
+
+include $(INCLUDE_DIR)/package.mk
+include $(INCLUDE_DIR)/host-build.mk
+
+define Package/audit/Default
+ TITLE:=Audit
+ URL:=https://github.com/linux-audit/
+endef
+
+define Package/audit/Default/description
+ The audit package contains the user space utilities for
+ storing and searching the audit records generated by
+ the audit subsystem in the kernel.
+endef
+
+define Package/libaudit
+$(call Package/audit/Default)
+ SECTION:=libs
+ CATEGORY:=Libraries
+ TITLE+= (libaudit)
+endef
+
+define Package/libaudit/description
+$(call Package/audit/Default/description)
+ This package contains the audit shared library.
+endef
+
+define Package/libauparse
+$(call Package/audit/Default)
+ SECTION:=libs
+ CATEGORY:=Libraries
+ TITLE+= (libauparse)
+ DEPENDS:= +libaudit
+endef
+
+define Package/libauparse/description
+$(call Package/audit/Default/description)
+ This package contains the audit parsing shared library.
+endef
+
+define Package/audit-utils
+$(call Package/audit/Default)
+ SECTION:=admin
+ CATEGORY:=Administration
+ TITLE+= (utilities)
+ DEPENDS:= +libaudit +libauparse
+endef
+
+define Package/audit-utils/description
+$(call Package/audit/Default/description)
+ This package contains the audit utilities.
+endef
+
+define Package/auditd
+$(call Package/audit/Default)
+ SECTION:=admin
+ CATEGORY:=Administration
+ TITLE+= (daemon)
+ DEPENDS:= +libaudit +libauparse +audit-utils +libev
+endef
+
+define Package/auditd/description
+$(call Package/audit/Default/description)
+ This package contains the audit daemon.
+endef
+
+CONFIGURE_VARS += \
+ LDFLAGS_FOR_BUILD="$(HOST_LDFLAGS)" \
+ CPPFLAGS_FOR_BUILD="$(HOST_CPPFLAGS)" \
+ CFLAGS_FOR_BUILD="$(HOST_CFLAGS)" \
+ CC_FOR_BUILD="$(HOSTCC)"
+
+CONFIGURE_ARGS += \
+ --with-debug \
+ --disable-systemd \
+ --disable-zos-remote \
+ --disable-gssapi-krb5 \
+ --without-libcap-ng \
+ --without-python \
+ --without-python3 \
+ --without-golang
+
+ifeq ($(ARCH),aarch64)
+CONFIGURE_ARGS += --with-aarch64
+else ifeq ($(ARCH),arm)
+CONFIGURE_ARGS += --with-arm
+endif
+
+HOST_CONFIGURE_ARGS += \
+ --disable-systemd \
+ --disable-zos-remote \
+ --disable-gssapi-krb5 \
+ --without-libcap-ng \
+ --without-python \
+ --without-python3 \
+ --without-golang
+
+define Host/Install
+ +$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/lib $(HOST_MAKE_FLAGS) install
+ +$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/init.d $(HOST_MAKE_FLAGS) install
+endef
+
+# We can't use the default, as the default passes $(MAKE_ARGS), which
+# overrides CC, CFLAGS, etc. and defeats the *_FOR_BUILD definitions
+# passed in CONFIGURE_VARS
+define Build/Compile
+ $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/$(MAKE_PATH)
+endef
+
+define Build/Install
+ $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/lib $(MAKE_INSTALL_FLAGS) install
+ $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/init.d $(MAKE_INSTALL_FLAGS) install
+ $(call Build/Install/Default,install)
+endef
+
+define Build/InstallDev
+ $(INSTALL_DIR) $(1)/usr/include
+ $(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/
+ $(INSTALL_DIR) $(1)/usr/lib/pkgconfig
+ $(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/*.pc $(1)/usr/lib/pkgconfig/
+ $(INSTALL_DIR) $(1)/usr/lib
+ $(CP) $(PKG_INSTALL_DIR)/usr/lib/* $(1)/usr/lib/
+endef
+
+define Package/libaudit/install
+ $(INSTALL_DIR) $(1)/usr/lib
+ $(CP) $(PKG_INSTALL_DIR)/usr/lib/libaudit.so* $(1)/usr/lib/
+ $(INSTALL_DIR) $(1)/etc
+ $(CP) $(PKG_INSTALL_DIR)/etc/libaudit.conf $(1)/etc/
+endef
+
+define Package/libauparse/install
+ $(INSTALL_DIR) $(1)/usr/lib
+ $(CP) $(PKG_INSTALL_DIR)/usr/lib/libauparse.so* $(1)/usr/lib/
+endef
+
+define Package/audit-utils/install
+ $(INSTALL_DIR) $(1)/usr/bin
+ $(CP) $(PKG_INSTALL_DIR)/usr/bin/* $(1)/usr/bin/
+ $(INSTALL_DIR) $(1)/usr/sbin
+ $(CP) \
+ $(PKG_INSTALL_DIR)/usr/sbin/{audisp-remote,audisp-syslog,auditctl,augenrules,aureport,ausearch,autrace} \
+ $(1)/usr/sbin/
+endef
+
+define Package/auditd/install
+ $(INSTALL_DIR) $(1)/etc/audit
+ $(CP) $(PKG_INSTALL_DIR)/etc/audit/* $(1)/etc/audit/
+ # af_unix plugin is not installed. Remove it's .conf.
+ if [[ -f $(1)/etc/audit/plugins.d/af_unix.conf ]] ; then rm $(1)/etc/audit/plugins.d/af_unix.conf ; fi
+ $(INSTALL_DIR) $(1)/etc/init.d
+ $(INSTALL_BIN) ./files/audit.init $(1)/etc/init.d/audit
+ $(INSTALL_DIR) $(1)/usr/sbin
+ $(CP) $(PKG_INSTALL_DIR)/usr/sbin/auditd $(1)/usr/sbin/
+endef
+
+$(eval $(call HostBuild))
+$(eval $(call BuildPackage,libaudit))
+$(eval $(call BuildPackage,libauparse))
+$(eval $(call BuildPackage,audit-utils))
+$(eval $(call BuildPackage,auditd))
--- /dev/null
+#!/bin/sh /etc/rc.common
+# Copyright (c) 2014 OpenWrt.org
+
+START=11
+
+USE_PROCD=1
+PROG=/usr/sbin/auditd
+
+start_service() {
+ mkdir -p /var/log/audit
+ procd_open_instance
+ procd_set_param command "$PROG" -n
+ procd_set_param respawn
+ procd_close_instance
+ test -f /etc/audit/rules.d/audit.rules && /usr/sbin/auditctl -R /etc/audit/rules.d/audit.rules
+}
--- /dev/null
+From 429d031edd52566eeba03c3b3af32ad6e103fd94 Mon Sep 17 00:00:00 2001
+From: Steve Grubb <ausearch.1@gmail.com>
+Date: Fri, 3 May 2024 17:33:39 -0400
+Subject: [PATCH] Implicit builtin functions
+
+Correct a number of places where printf is being used without a prototype.
+All cases are in libraries which should not be using printf. Change them
+to return an error rather than communicate the problem.
+
+This is a backport of 8c7eaa7
+---
+ audisp/audispd-llist.c | 10 +++++-----
+ audisp/audispd-llist.h | 4 ++--
+ auparse/normalize-llist.c | 12 ++++++------
+ auparse/normalize-llist.h | 4 ++--
+ auparse/normalize.c | 14 +++++++++-----
+ src/auditctl-llist.c | 18 +++++++++---------
+ src/auditctl-llist.h | 4 ++--
+ src/ausearch-avc.c | 16 ++++++++--------
+ src/ausearch-avc.h | 4 ++--
+ src/ausearch-int.c | 12 ++++++------
+ src/ausearch-int.h | 4 ++--
+ src/ausearch-llist.c | 14 +++++++-------
+ src/ausearch-llist.h | 2 +-
+ src/ausearch-nvpair.c | 12 ++++++------
+ src/ausearch-nvpair.h | 4 ++--
+ src/ausearch-string.c | 10 +++++-----
+ src/ausearch-string.h | 2 +-
+ tools/aulastlog/aulastlog-llist.c | 18 +++++++++---------
+ tools/aulastlog/aulastlog-llist.h | 4 ++--
+ 19 files changed, 86 insertions(+), 82 deletions(-)
+
+--- a/audisp/audispd-llist.c
++++ b/audisp/audispd-llist.c
+@@ -69,15 +69,13 @@ unsigned int plist_count_active(const co
+ return cnt;
+ }
+
+-void plist_append(conf_llist *l, plugin_conf_t *p)
++int plist_append(conf_llist *l, plugin_conf_t *p)
+ {
+ lnode* newnode;
+
+ newnode = malloc(sizeof(lnode));
+- if (newnode == NULL) {
+- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__);
+- return;
+- }
++ if (newnode == NULL)
++ return 1;
+
+ if (p) {
+ void *pp = malloc(sizeof(struct plugin_conf));
+@@ -98,6 +96,8 @@ void plist_append(conf_llist *l, plugin_
+ // make newnode current
+ l->cur = newnode;
+ l->cnt++;
++
++ return 0;
+ }
+
+ void plist_clear(conf_llist* l)
+--- a/audisp/audispd-llist.h
++++ b/audisp/audispd-llist.h
+@@ -1,6 +1,6 @@
+ /*
+ * audispd-llist.h - Header file for ausearch-conf_llist.c
+-* Copyright (c) 2007,2013 Red Hat Inc., Durham, North Carolina.
++* Copyright (c) 2007,2013 Red Hat Inc.
+ * All Rights Reserved.
+ *
+ * This software may be freely redistributed and/or modified under the
+@@ -51,7 +51,7 @@ unsigned int plist_count_active(const co
+ void plist_last(conf_llist *l);
+ lnode *plist_next(conf_llist *l);
+ static inline lnode *plist_get_cur(conf_llist *l) { return l->cur; }
+-void plist_append(conf_llist *l, plugin_conf_t *p);
++int plist_append(conf_llist *l, plugin_conf_t *p);
+ void plist_clear(conf_llist* l);
+ void plist_mark_all_unchecked(conf_llist* l);
+ lnode *plist_find_unchecked(conf_llist* l);
+--- a/auparse/normalize-llist.c
++++ b/auparse/normalize-llist.c
+@@ -1,6 +1,6 @@
+ /*
+ * normalize-llist.c - Minimal linked list library
+- * Copyright (c) 2016-17 Red Hat Inc., Durham, North Carolina.
++ * Copyright (c) 2016-17 Red Hat Inc.
+ * All Rights Reserved.
+ *
+ * This library is free software; you can redistribute it and/or
+@@ -61,15 +61,14 @@ data_node *cllist_next(cllist *l)
+ return l->cur;
+ }
+
+-void cllist_append(cllist *l, uint32_t num, void *data)
++// Returns 0 on success and 1 on error
++int cllist_append(cllist *l, uint32_t num, void *data)
+ {
+ data_node *newnode;
+
+ newnode = malloc(sizeof(data_node));
+- if (newnode == NULL) {
+- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__);
+- return;
+- }
++ if (newnode == NULL)
++ return 1;
+
+ newnode->num = num;
+ newnode->data = data;
+@@ -84,5 +83,6 @@ void cllist_append(cllist *l, uint32_t n
+ // make newnode current
+ l->cur = newnode;
+ l->cnt++;
++ return 0;
+ }
+
+--- a/auparse/normalize-llist.h
++++ b/auparse/normalize-llist.h
+@@ -1,6 +1,6 @@
+ /*
+ * normalize-llist.h - Header file for normalize-llist.c
+- * Copyright (c) 2016-17 Red Hat Inc., Durham, North Carolina.
++ * Copyright (c) 2016-17 Red Hat Inc.
+ * All Rights Reserved.
+ *
+ * This library is free software; you can redistribute it and/or
+@@ -53,7 +53,7 @@ AUDIT_HIDDEN_START
+ void cllist_create(cllist *l, void (*cleanup)(void *));
+ void cllist_clear(cllist* l);
+ data_node *cllist_next(cllist *l);
+-void cllist_append(cllist *l, uint32_t num, void *data);
++int cllist_append(cllist *l, uint32_t num, void *data);
+
+ AUDIT_HIDDEN_END
+
+--- a/auparse/normalize.c
++++ b/auparse/normalize.c
+@@ -179,7 +179,8 @@ static unsigned int add_subj_attr(aupars
+ if ((auparse_find_field(au, str))) {
+ attr = set_record(0, rnum);
+ attr = set_field(attr, auparse_get_field_num(au));
+- cllist_append(&D.actor.attr, attr, NULL);
++ if (cllist_append(&D.actor.attr, attr, NULL))
++ return 1;
+ return 0;
+ } else
+ auparse_goto_record_num(au, rnum);
+@@ -224,7 +225,8 @@ static unsigned int add_obj_attr(auparse
+ if ((auparse_find_field(au, str))) {
+ attr = set_record(0, rnum);
+ attr = set_field(attr, auparse_get_field_num(au));
+- cllist_append(&D.thing.attr, attr, NULL);
++ if (cllist_append(&D.thing.attr, attr, NULL))
++ return 1;
+ return 0;
+ } else
+ auparse_goto_record_num(au, rnum);
+@@ -360,21 +362,23 @@ static void collect_id_obj2(auparse_stat
+ }
+ }
+
+-static void collect_path_attrs(auparse_state_t *au)
++static int collect_path_attrs(auparse_state_t *au)
+ {
+ value_t attr;
+ unsigned int rnum = auparse_get_record_num(au);
+
+ auparse_first_field(au);
+ if (add_obj_attr(au, "mode", rnum))
+- return; // Failed opens don't have anything else
++ return 1; // Failed opens don't have anything else
+
+ // All the rest of the fields matter
+ while ((auparse_next_field(au))) {
+ attr = set_record(0, rnum);
+ attr = set_field(attr, auparse_get_field_num(au));
+- cllist_append(&D.thing.attr, attr, NULL);
++ if (cllist_append(&D.thing.attr, attr, NULL))
++ return 1;
+ }
++ return 0;
+ }
+
+ static void collect_cwd_attrs(auparse_state_t *au)
+--- a/src/auditctl-llist.c
++++ b/src/auditctl-llist.c
+@@ -1,7 +1,7 @@
+ /*
+ * ausearch-llist.c - Minimal linked list library
+-* Copyright (c) 2005 Red Hat Inc., Durham, North Carolina.
+-* All Rights Reserved.
++* Copyright (c) 2005 Red Hat Inc.
++* All Rights Reserved.
+ *
+ * This software may be freely redistributed and/or modified under the
+ * terms of the GNU General Public License as published by the Free
+@@ -15,7 +15,7 @@
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING. If not, write to the
+-* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor
++* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor
+ * Boston, MA 02110-1335, USA.
+ *
+ * Authors:
+@@ -59,19 +59,17 @@ lnode *list_next(llist *l)
+ return l->cur;
+ }
+
+-void list_append(llist *l, struct audit_rule_data *r, size_t sz)
++int list_append(llist *l, struct audit_rule_data *r, size_t sz)
+ {
+ lnode* newnode;
+
+ newnode = malloc(sizeof(lnode));
+- if (newnode == NULL) {
+- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__);
+- return;
+- }
++ if (newnode == NULL)
++ return 1;
+
+ if (r) {
+ void *rr = malloc(sz);
+- if (rr)
++ if (rr)
+ memcpy(rr, r, sz);
+ newnode->r = rr;
+ } else
+@@ -89,6 +87,8 @@ void list_append(llist *l, struct audit_
+ // make newnode current
+ l->cur = newnode;
+ l->cnt++;
++
++ return 0;
+ }
+
+ void list_clear(llist* l)
+--- a/src/auditctl-llist.h
++++ b/src/auditctl-llist.h
+@@ -1,6 +1,6 @@
+ /*
+ * auditctl-llist.h - Header file for ausearch-llist.c
+-* Copyright (c) 2005 Red Hat Inc., Durham, North Carolina.
++* Copyright (c) 2005 Red Hat Inc.
+ * All Rights Reserved.
+ *
+ * This software may be freely redistributed and/or modified under the
+@@ -50,7 +50,7 @@ void list_first(llist *l);
+ void list_last(llist *l);
+ lnode *list_next(llist *l);
+ static inline lnode *list_get_cur(llist *l) { return l->cur; }
+-void list_append(llist *l, struct audit_rule_data *r, size_t sz);
++int list_append(llist *l, struct audit_rule_data *r, size_t sz);
+ void list_clear(llist* l);
+
+ #endif
+--- a/src/ausearch-avc.c
++++ b/src/ausearch-avc.c
+@@ -1,7 +1,7 @@
+ /*
+ * ausearch-avc.c - Minimal linked list library for avcs
+-* Copyright (c) 2006,2008,2014 Red Hat Inc., Durham, North Carolina.
+-* All Rights Reserved.
++* Copyright (c) 2006,2008,2014 Red Hat Inc.
++* All Rights Reserved.
+ *
+ * This software may be freely redistributed and/or modified under the
+ * terms of the GNU General Public License as published by the Free
+@@ -15,7 +15,7 @@
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING. If not, write to the
+-* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor
++* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor
+ * Boston, MA 02110-1335, USA.
+ *
+ * Authors:
+@@ -62,15 +62,13 @@ static void alist_last(alist *l)
+ l->cur = cur;
+ }
+
+-void alist_append(alist *l, anode *node)
++int alist_append(alist *l, anode *node)
+ {
+ anode* newnode;
+
+ newnode = malloc(sizeof(anode));
+- if (newnode == NULL) {
+- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__);
+- return;
+- }
++ if (newnode == NULL)
++ return 1;
+
+ if (node->scontext)
+ newnode->scontext = node->scontext;
+@@ -108,6 +106,8 @@ void alist_append(alist *l, anode *node)
+ // make newnode current
+ l->cur = newnode;
+ l->cnt++;
++
++ return 0;
+ }
+
+ int alist_find_subj(alist *l)
+--- a/src/ausearch-avc.h
++++ b/src/ausearch-avc.h
+@@ -1,6 +1,6 @@
+ /*
+ * ausearch-avc.h - Header file for ausearch-string.c
+-* Copyright (c) 2006,2008 Red Hat Inc., Durham, North Carolina.
++* Copyright (c) 2006,2008 Red Hat Inc.
+ * All Rights Reserved.
+ *
+ * This software may be freely redistributed and/or modified under the
+@@ -54,7 +54,7 @@ void alist_create(alist *l);
+ static inline void alist_first(alist *l) { l->cur = l->head; }
+ anode *alist_next(alist *l);
+ static inline anode *alist_get_cur(alist *l) { return l->cur; }
+-void alist_append(alist *l, anode *node);
++int alist_append(alist *l, anode *node);
+ void anode_init(anode *an);
+ void anode_clear(anode *an);
+ void alist_clear(alist* l);
+--- a/src/ausearch-int.c
++++ b/src/ausearch-int.c
+@@ -1,6 +1,6 @@
+ /*
+ * ausearch-int.c - Minimal linked list library for integers
+-* Copyright (c) 2005,2008 Red Hat Inc., Durham, North Carolina.
++* Copyright (c) 2005,2008 Red Hat Inc.
+ * All Rights Reserved.
+ *
+ * This software may be freely redistributed and/or modified under the
+@@ -41,15 +41,13 @@ int_node *ilist_next(ilist *l)
+ return l->cur;
+ }
+
+-void ilist_append(ilist *l, int num, unsigned int hits, int aux)
++int ilist_append(ilist *l, int num, unsigned int hits, int aux)
+ {
+ int_node* newnode;
+
+ newnode = malloc(sizeof(int_node));
+- if (newnode == NULL) {
+- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__);
+- return;
+- }
++ if (newnode == NULL)
++ return 1;
+
+ newnode->num = num;
+ newnode->hits = hits;
+@@ -65,6 +63,8 @@ void ilist_append(ilist *l, int num, uns
+ // make newnode current
+ l->cur = newnode;
+ l->cnt++;
++
++ return 0;
+ }
+
+ void ilist_clear(ilist* l)
+--- a/src/ausearch-int.h
++++ b/src/ausearch-int.h
+@@ -1,6 +1,6 @@
+ /*
+ * ausearch-int.h - Header file for ausearch-int.c
+-* Copyright (c) 2005,2008 Red Hat Inc., Durham, North Carolina.
++* Copyright (c) 2005,2008 Red Hat Inc.
+ * All Rights Reserved.
+ *
+ * This software may be freely redistributed and/or modified under the
+@@ -48,7 +48,7 @@ void ilist_create(ilist *l);
+ static inline void ilist_first(ilist *l) { l->cur = l->head; }
+ int_node *ilist_next(ilist *l);
+ static inline int_node *ilist_get_cur(ilist *l) { return l->cur; }
+-void ilist_append(ilist *l, int num, unsigned int hits, int aux);
++int ilist_append(ilist *l, int num, unsigned int hits, int aux);
+ void ilist_clear(ilist* l);
+
+ /* append a number if its not already on the list */
+--- a/src/ausearch-llist.c
++++ b/src/ausearch-llist.c
+@@ -1,6 +1,6 @@
+ /*
+ * ausearch-llist.c - Minimal linked list library
+-* Copyright (c) 2005-2008,2011,2016 Red Hat Inc., Durham, North Carolina.
++* Copyright (c) 2005-2008,2011,2016 Red Hat Inc.
+ * Copyright (c) 2011 IBM Corp.
+ * All Rights Reserved.
+ *
+@@ -102,15 +102,13 @@ lnode *list_prev(llist *l)
+ return l->cur;
+ }
+
+-void list_append(llist *l, lnode *node)
++int list_append(llist *l, lnode *node)
+ {
+ lnode* newnode;
+
+ newnode = malloc(sizeof(lnode));
+- if (newnode == NULL) {
+- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__);
+- return;
+- }
++ if (newnode == NULL)
++ return 1;
+
+ if (node->message)
+ newnode->message = node->message;
+@@ -123,7 +121,7 @@ void list_append(llist *l, lnode *node)
+ newnode->type = node->type;
+ newnode->a0 = node->a0;
+ newnode->a1 = node->a1;
+- newnode->item = l->cnt;
++ newnode->item = l->cnt;
+ newnode->next = NULL;
+
+ // if we are at top, fix this up
+@@ -135,6 +133,8 @@ void list_append(llist *l, lnode *node)
+ // make newnode current
+ l->cur = newnode;
+ l->cnt++;
++
++ return 0;
+ }
+
+ int list_find_item(llist *l, unsigned int i)
+--- a/src/ausearch-llist.h
++++ b/src/ausearch-llist.h
+@@ -107,7 +107,7 @@ void list_last(llist *l);
+ lnode *list_next(llist *l);
+ lnode *list_prev(llist *l);
+ static inline lnode *list_get_cur(llist *l) { return l->cur; }
+-void list_append(llist *l, lnode *node);
++int list_append(llist *l, lnode *node);
+ void list_clear(llist* l);
+ int list_get_event(llist* l, event *e);
+
+--- a/src/ausearch-nvpair.c
++++ b/src/ausearch-nvpair.c
+@@ -1,6 +1,6 @@
+ /*
+ * ausearch-nvpair.c - Minimal linked list library for name-value pairs
+-* Copyright (c) 2006-08 Red Hat Inc., Durham, North Carolina.
++* Copyright (c) 2006-08 Red Hat Inc.
+ * All Rights Reserved.
+ *
+ * This software may be freely redistributed and/or modified under the
+@@ -42,13 +42,11 @@ nvnode *search_list_next(nvlist *l)
+ return l->cur;
+ }
+
+-void search_list_append(nvlist *l, nvnode *node)
++int search_list_append(nvlist *l, nvnode *node)
+ {
+ nvnode* newnode = malloc(sizeof(nvnode));
+- if (newnode == NULL) {
+- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__);
+- return;
+- }
++ if (newnode == NULL)
++ return 1;
+
+ newnode->name = node->name;
+ newnode->val = node->val;
+@@ -66,6 +64,8 @@ void search_list_append(nvlist *l, nvnod
+ // make newnode current
+ l->cur = newnode;
+ l->cnt++;
++
++ return 0;
+ }
+
+ int search_list_find_val(nvlist *l, long val)
+--- a/src/ausearch-nvpair.h
++++ b/src/ausearch-nvpair.h
+@@ -1,6 +1,6 @@
+ /*
+ * ausearch-nvpair.h - Header file for ausearch-nvpair.c
+-* Copyright (c) 2006-08 Red Hat Inc., Durham, North Carolina.
++* Copyright (c) 2006-08 Red Hat Inc.
+ * All Rights Reserved.
+ *
+ * This software may be freely redistributed and/or modified under the
+@@ -48,7 +48,7 @@ void search_list_create(nvlist *l);
+ static inline void search_list_first(nvlist *l) { l->cur = l->head; }
+ nvnode *search_list_next(nvlist *l);
+ static inline nvnode *search_list_get_cur(nvlist *l) { return l->cur; }
+-void search_list_append(nvlist *l, nvnode *node);
++int search_list_append(nvlist *l, nvnode *node);
+ void search_list_clear(nvlist* l);
+
+ /* Given a numeric index, find that record. */
+--- a/src/ausearch-string.c
++++ b/src/ausearch-string.c
+@@ -44,15 +44,13 @@ snode *slist_next(slist *l)
+ return l->cur;
+ }
+
+-void slist_append(slist *l, snode *node)
++int slist_append(slist *l, snode *node)
+ {
+ snode* newnode;
+
+ newnode = malloc(sizeof(snode));
+- if (newnode == NULL) {
+- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__);
+- return;
+- }
++ if (newnode == NULL)
++ return 1;
+
+ if (node->str)
+ newnode->str = node->str;
+@@ -79,6 +77,8 @@ void slist_append(slist *l, snode *node)
+ // make newnode current
+ l->cur = newnode;
+ l->cnt++;
++
++ return 0;
+ }
+
+ void slist_clear(slist* l)
+--- a/src/ausearch-string.h
++++ b/src/ausearch-string.h
+@@ -49,7 +49,7 @@ void slist_create(slist *l);
+ static inline void slist_first(slist *l) { l->cur = l->head; }
+ snode *slist_next(slist *l);
+ static inline snode *slist_get_cur(slist *l) { return l->cur; }
+-void slist_append(slist *l, snode *node);
++int slist_append(slist *l, snode *node);
+ void slist_clear(slist* l);
+
+ /* append a string if its not already on the list */
+--- a/tools/aulastlog/aulastlog-llist.c
++++ b/tools/aulastlog/aulastlog-llist.c
+@@ -1,7 +1,7 @@
+ /*
+ * aulastlog-llist.c - Minimal linked list library
+-* Copyright (c) 2008 Red Hat Inc., Durham, North Carolina.
+-* All Rights Reserved.
++* Copyright (c) 2008 Red Hat Inc..
++* All Rights Reserved.
+ *
+ * This software may be freely redistributed and/or modified under the
+ * terms of the GNU General Public License as published by the Free
+@@ -15,7 +15,7 @@
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING. If not, write to the
+-* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor
++* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor
+ * Boston, MA 02110-1335, USA.
+ *
+ * Authors:
+@@ -41,15 +41,13 @@ lnode *list_next(llist *l)
+ return l->cur;
+ }
+
+-void list_append(llist *l, lnode *node)
++int list_append(llist *l, lnode *node)
+ {
+ lnode* newnode;
+
+ newnode = malloc(sizeof(lnode));
+- if (newnode == NULL) {
+- printf("Out of memory. Check %s file, %d line", __FILE__, __LINE__);
+- return;
+- }
++ if (newnode == NULL)
++ return 1;
+
+ newnode->sec = node->sec;
+ newnode->uid = node->uid;
+@@ -62,7 +60,7 @@ void list_append(llist *l, lnode *node)
+ newnode->term = strdup(node->term);
+ else
+ newnode->term = NULL;
+- newnode->item = l->cnt;
++ newnode->item = l->cnt;
+ newnode->next = NULL;
+
+ // if we are at top, fix this up
+@@ -74,6 +72,8 @@ void list_append(llist *l, lnode *node)
+ // make newnode current
+ l->cur = newnode;
+ l->cnt++;
++
++ return 0;
+ }
+
+ void list_clear(llist* l)
+--- a/tools/aulastlog/aulastlog-llist.h
++++ b/tools/aulastlog/aulastlog-llist.h
+@@ -1,6 +1,6 @@
+ /*
+ * aulastlog-llist.h - Header file for aulastlog-llist.c
+-* Copyright (c) 2008 Red Hat Inc., Durham, North Carolina.
++* Copyright (c) 2008 Red Hat Inc.
+ * All Rights Reserved.
+ *
+ * This software may be freely redistributed and/or modified under the
+@@ -53,7 +53,7 @@ static inline void list_first(llist *l)
+ lnode *list_next(llist *l);
+ static inline lnode *list_get_cur(llist *l) { return l->cur; }
+ static inline unsigned int list_get_cnt(llist *l) { return l->cnt; }
+-void list_append(llist *l, lnode *node);
++int list_append(llist *l, lnode *node);
+ void list_clear(llist* l);
+ int list_update_login(llist* l, time_t t);
+ int list_update_host(llist* l, const char *h);
include $(TOPDIR)/rules.mk
PKG_NAME:=bcm27xx-utils
-PKG_VERSION:=2024-01-18
+PKG_VERSION:=2024-04-24
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/raspberrypi/utils.git
-PKG_SOURCE_VERSION:=e65f5ec102e74218cda7da9fdc8b1caa0fd1127d
-PKG_MIRROR_HASH:=ea946fc4a86875c5d1efc35b2bc80f6b5482afc3d1ea13853b69abc2b4a2eee6
+PKG_SOURCE_VERSION:=451b9881b72cb994c102724b5a7d9b93f97dc315
+PKG_MIRROR_HASH:=b453976171187e0ffe7cacfdcab36cec6b5d02db8b6d978cb9afbbcafcfcff9d
PKG_FLAGS:=nonshared
PKG_BUILD_FLAGS:=no-lto
PKG_NAME:=mtd-utils
PKG_VERSION:=2.1.6
-PKG_RELEASE:=1
+PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://infraroot.at/pub/mtd/
MAKE_FLAGS += LDLIBS+="$(LIBGCC_S)"
CONFIGURE_ARGS += \
- --disable-tests \
+ --enable-tests \
--without-crypto \
--without-xattr \
--without-zstd \
define Package/nand-utils/install
$(INSTALL_DIR) $(1)/usr/sbin
$(INSTALL_BIN) \
- $(PKG_INSTALL_DIR)/usr/sbin/{flash_erase,nanddump,nandwrite,nandtest,mtdinfo} $(1)/usr/sbin/
+ $(PKG_INSTALL_DIR)/usr/sbin/{flash_erase,nanddump,nandwrite,nandtest,mtdinfo} \
+ $(PKG_INSTALL_DIR)/usr/lib/mtd-utils/nandbiterrs $(1)/usr/sbin/
endef
$(eval $(call BuildPackage,ubi-utils))
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/jow-/ucode.git
-PKG_SOURCE_DATE:=2024-02-21
-PKG_SOURCE_VERSION:=ba3855ae3775197f3594fc2615cac539075bd2fb
-PKG_MIRROR_HASH:=f585447ebbb5ef56ada3a9f8dbe71d5310cc8185d0e90676b512849eaf60f77c
+PKG_SOURCE_DATE:=2024-05-09
+PKG_SOURCE_VERSION:=0d823e702bfe5f2bb5be694030a98afedf34aa6b
+PKG_MIRROR_HASH:=c52d499d2490e958e36ed80c32e8fd6d94cacf3b43b9d14c45c68a25bc44d536
PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
PKG_LICENSE:=ISC
rtnl, RTNL_SUPPORT, +libnl-tiny +libubox, \
The rtnl plugin provides access to the Linux routing netlink API.))
+$(eval $(call UcodeModule, \
+ socket, SOCKET_SUPPORT, , \
+ The socket plugin provides access to IPv4, IPv6, Unix and packet socket APIs.))
+
$(eval $(call UcodeModule, \
struct, STRUCT_SUPPORT, , \
The struct plugin implements Python 3 compatible struct.pack/unpack functionality.))
#include <unistd.h>
#include "uencrypt.h"
+#if MBEDTLS_VERSION_NUMBER < 0x03010000 /* mbedtls 3.1.0 */
+static inline mbedtls_cipher_mode_t mbedtls_cipher_info_get_mode(
+ const mbedtls_cipher_info_t *info)
+{
+ if (info == NULL) {
+ return MBEDTLS_MODE_NONE;
+ } else {
+ return info->mode;
+ }
+}
+
+static inline size_t mbedtls_cipher_info_get_key_bitlen(
+ const mbedtls_cipher_info_t *info)
+{
+ if (info == NULL) {
+ return 0;
+ } else {
+ return info->key_bitlen;
+ }
+}
+
+static inline const char *mbedtls_cipher_info_get_name(
+ const mbedtls_cipher_info_t *info)
+{
+ if (info == NULL) {
+ return NULL;
+ } else {
+ return info->name;
+ }
+}
+
+static inline size_t mbedtls_cipher_info_get_iv_size(
+ const mbedtls_cipher_info_t *info)
+{
+ if (info == NULL) {
+ return 0;
+ }
+
+ return info->iv_size;
+}
+
+static inline size_t mbedtls_cipher_info_get_block_size(
+ const mbedtls_cipher_info_t *info)
+{
+ if (info == NULL) {
+ return 0;
+ }
+
+ return info->block_size;
+}
+#endif
+
unsigned char *hexstr2buf(const char *str, long *len)
{
unsigned char *buf;
cipher = mbedtls_cipher_info_from_type(*list);
if (!cipher)
continue;
- fprintf(stderr, "\t%s\n", cipher->name);
+ fprintf(stderr, "\t%s\n", mbedtls_cipher_info_get_name(cipher));
}
return NULL;
}
{
const mbedtls_cipher_info_t *c = cipher;
- return c->iv_size;
+ return mbedtls_cipher_info_get_iv_size(c);
}
int get_cipher_keysize(const cipher_t *cipher)
{
const mbedtls_cipher_info_t *c = cipher;
- return c->key_bitlen >> 3;
+ return mbedtls_cipher_info_get_key_bitlen(c) >> 3;
}
ctx_t *create_ctx(const cipher_t *cipher, const unsigned char *key,
}
}
- if (cipher_info->mode == MBEDTLS_MODE_CBC) {
+ if (mbedtls_cipher_info_get_mode(cipher_info) == MBEDTLS_MODE_CBC) {
ret = mbedtls_cipher_set_padding_mode(ctx, padding ?
MBEDTLS_PADDING_PKCS7 :
MBEDTLS_PADDING_NONE);
goto abort;
}
} else {
- if (cipher_info->block_size > 1 && padding) {
+ if (mbedtls_cipher_info_get_block_size(cipher_info) > 1 && padding) {
fprintf(stderr,
"Error: mbedTLS only allows padding with CBC ciphers.\n");
goto abort;
}
}
if (ivlen != get_cipher_ivsize(cipher)) {
- fprintf(stderr, "Error: IV must be %d bytes; given IV is %zd bytes.\n",
+ fprintf(stderr, "Error: IV must be %d bytes; given IV is %ld bytes.\n",
get_cipher_ivsize(cipher), ivlen);
exit(EXIT_FAILURE);
}
if (keylen != get_cipher_keysize(cipher)) {
- fprintf(stderr, "Error: key must be %d bytes; given key is %zd bytes.\n",
+ fprintf(stderr, "Error: key must be %d bytes; given key is %ld bytes.\n",
get_cipher_keysize(cipher), keylen);
exit(EXIT_FAILURE);
}
endif
else
ifeq ($(CONFIG_NATIVE_TOOLCHAIN),)
+ -include $(TOOLCHAIN_DIR)/info.mk
TARGET_CROSS:=$(call qstrip,$(CONFIG_TOOLCHAIN_PREFIX))
TOOLCHAIN_ROOT_DIR:=$(call qstrip,$(CONFIG_TOOLCHAIN_ROOT))
TOOLCHAIN_BIN_DIRS:=$(patsubst ./%,$(TOOLCHAIN_ROOT_DIR)/%,$(call qstrip,$(CONFIG_TOOLCHAIN_BIN_PATH)))
HOST_LDFLAGS:=-L$(STAGING_DIR_HOST)/lib $(if $(IS_PACKAGE_BUILD),-L$(STAGING_DIR_HOSTPKG)/lib -L$(STAGING_DIR)/host/lib)
BUILD_KEY=$(TOPDIR)/key-build
+BUILD_KEY_APK_SEC=$(TOPDIR)/private-key.pem
+BUILD_KEY_APK_PUB=$(TOPDIR)/public-key.pem
FAKEROOT:=$(STAGING_DIR_HOST)/bin/fakeroot
if ts is not None:
args.append('--mtime=@%d' % ts)
if into.endswith('.zst'):
- envs['ZSTD_CLEVEL'] = '20'
- envs['ZSTD_NBTHREADS'] = '0'
- args.append('--zstd')
+ args.append('-I zstd -T0 --ultra -20')
elif into.endswith('.xz'):
envs['XZ_OPT'] = '-7e'
args.append('-J')
printf "\t\tdepends on PER_FEED_REPO\n";
printf "\t\tdefault y\n" if $installed;
printf "\t\thelp\n";
- printf "\t\t Enable the \\\"%s\\\" feed in opkg distfeeds.conf.\n", $feed->[1];
+ printf "\t\t Enable the \\\"%s\\\" feed in opkg distfeeds.conf and apk repositories.\n", $feed->[1];
printf "\t\t Say M to add the feed commented out.\n";
printf "\n";
}
-s : List of feed names and their URL.
-r <feedname>: List packages of specified feed.
-d <delimiter>: Use specified delimiter to distinguish rows (default: spaces)
- -f : List feeds in feeds.conf compatible format (when using -s).
+ -f : List feeds in opkg feeds.conf compatible format (when using -s).
install [options] <package>: Install a package
Options:
exit
git
printf
+ sed
set
shift
+ sort
'
_msg()
{
echo "Usage: ${0}"
echo 'Helper script to bump the target kernel version, whilst keeping history.'
+ echo ' -c Migrate config files (e.g. subtargets) only.'
echo " -p Optional Platform name (e.g. 'ath79' [PLATFORM_NAME]"
+ echo " -r Optional comma separated list of sub-targets (e.g. 'rtl930x' [SUBTARGET_NAMES]"
echo " -s Source version of kernel (e.g. 'v6.1' [SOURCE_VERSION])"
echo " -t Target version of kernel (e.g. 'v6.6' [TARGET_VERSION]')"
echo
echo 'All options can also be passed in environment variables (listed between [BRACKETS]).'
+ echo 'Note that this script must be run from within the OpenWrt git repository.'
echo 'Example: scripts/kernel_bump.sh -p realtek -s v6.1 -t v6.6'
}
init()
{
+ src_file="$(readlink -f "${0}")"
+ src_dir="${src_file%%"${src_file##*'/'}"}"
initial_branch="$(git rev-parse --abbrev-ref HEAD)"
initial_commitish="$(git rev-parse HEAD)"
- trap cleanup EXIT HUP INT QUIT ABRT ALRM TERM
-}
+ if [ -n "$(git status --porcelain | grep -v '^?? .*')" ]; then
+ echo 'Git respository not in a clean state, will not continue.'
+ exit 1
+ fi
-do_source_target()
-{
- _target_dir="${1:?Missing argument to function}"
- _op="${2:?Missing argument to function}"
+ if [ -n "${src_dir##*'/scripts/'}" ]; then
+ echo "This script '${src_file}' is not in the scripts subdirectory, this is unexpected, cannot continue."
+ exit 1
+ fi
+
+ source_version="${source_version#v}"
+ target_version="${target_version#v}"
+ trap cleanup EXIT HUP INT QUIT ABRT ALRM TERM
}
bump_kernel()
{
- platform_name="${platform_name##*'/'}"
-
- if [ -z "${platform_name:-}" ]; then
- platform_name="${PWD##*'/'}"
+ if [ -z "${platform_name}" ] || \
+ [ -d "${PWD}/image" ]; then
+ platform_name="${PWD}"
fi
+ platform_name="${platform_name##*'/'}"
- if [ "${PWD##*'/'}" = "${platform_name}" ]; then
- _target_dir='./'
- else
- _target_dir="target/linux/${platform_name}"
- fi
+ _target_dir="${src_dir}/../target/linux/${platform_name}"
if [ ! -d "${_target_dir}/image" ]; then
- e_err 'Cannot find target linux directory.'
+ e_err "Cannot find target linux directory '${_target_dir:-not defined}'. Not in a platform directory, or -p not set."
exit 1
fi
git switch --force-create '__openwrt_kernel_files_mover'
- for _path in "${_target_dir}/"*; do
- if [ ! -s "${_path}" ] || \
- [ "${_path}" = "${_path%%"-${source_version}"}" ]; then
+ if [ "${config_only:-false}" != 'true' ]; then
+ for _path in $(git ls-tree -d -r --name-only '__openwrt_kernel_files_mover' "${_target_dir}" |
+ sed -n "s|^\(.*-${source_version}\).*|\1|p" |
+ sort -u); do
+ if [ ! -e "${_path}" ] || \
+ [ "${_path}" = "${_path%%"-${source_version}"}" ]; then
+ continue
+ fi
+
+ _target_path="${_path%%"-${source_version}"}-${target_version}"
+ if [ -e "${_target_path}" ]; then
+ e_err "Target '${_target_path}' already exists!"
+ exit 1
+ fi
+
+ git mv \
+ "${_path}" \
+ "${_target_path}"
+ done
+ fi
+
+ for _config in $(git ls-files "${_target_dir}" |
+ sed -n "s|^\(.*config-${source_version}\).*|\1|p" |
+ sort -u); do
+ if [ ! -e "${_config}" ]; then
continue
fi
- _target_path="${_path%%"-${source_version}"}-${target_version}"
- if [ -s "${_target_path}" ]; then
- e_err "Target '${_target_path}' already exists!"
- exit 1
+ _subtarget="${_config%%"/config-${source_version}"}"
+ if [ -n "${subtarget_names:-}" ]; then
+ echo "${subtarget_names:-}" | while IFS=',' read -r _subtarget_name; do
+ if [ "${_subtarget_name}" = "${_subtarget##*'/'}" ]; then
+ git mv "${_config}" "${_subtarget}/config-${target_version}"
+ fi
+ done
+ else
+ git mv "${_config}" "${_subtarget}/config-${target_version}"
fi
-
- git mv \
- "${_path}" \
- "${_target_path}"
- done
-
- find "${_target_dir}" -iname "config-${source_version}" | while read -r _config; do
- _path="${_config%%"/config-${source_version}"}"
- git mv "${_config}" "${_path}/config-${target_version}"
done
git commit \
--signoff \
--message "kernel/${platform_name}: Create kernel files for v${target_version} (from v${source_version})" \
--message 'This is an automatically generated commit.' \
- --message 'During a `git bisect` session, `git bisect --skip` is recommended.'
+ --message 'When doing `git bisect`, consider `git bisect --skip`.'
git checkout 'HEAD~' "${_target_dir}"
git commit \
--signoff \
--message "kernel/${platform_name}: Restore kernel files for v${source_version}" \
- --message "$(printf "This is an automatically generated commit which aids following Kernel patch history,\nas git will see the move and copy as a rename thus defeating the purpose.\n\nSee: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html\nfor the original discussion.")"
+ --message "$(printf "This is an automatically generated commit which aids following Kernel patch\nhistory, as git will see the move and copy as a rename thus defeating the\npurpose.\n\nFor the original discussion see:\nhttps://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html")"
git switch "${initial_branch:?Unable to switch back to original branch. Quitting.}"
GIT_EDITOR=true git merge --no-ff '__openwrt_kernel_files_mover'
git branch --delete '__openwrt_kernel_files_mover'
+ echo "Deleting merge commit ($(git rev-parse HEAD))."
+ git rebase HEAD~1
echo "Original commitish was '${initial_commitish}'."
echo 'Kernel bump complete. Remember to use `git log --follow`.'
main()
{
- while getopts 'hp:s:t:' _options; do
+ while getopts 'chp:r:s:t:' _options; do
case "${_options}" in
+ 'c')
+ config_only='true'
+ ;;
'h')
usage
exit 0
'p')
platform_name="${OPTARG}"
;;
+ 'r')
+ subtarget_names="${OPTARG}"
+ ;;
's')
- source_version="${OPTARG#v}"
+ source_version="${OPTARG}"
;;
't')
- target_version="${OPTARG#v}"
+ target_version="${OPTARG}"
;;
':')
e_err "Option -${OPTARG} requires an argument."
shift "$((OPTIND - 1))"
platform_name="${platform_name:-${PLATFORM_NAME:-}}"
+ subtarget_names="${subtarget_names:-${SUBTARGET_NAMES:-}}"
source_version="${source_version:-${SOURCE_VERSION:-}}"
target_version="${target_version:-${TARGET_VERSION:-}}"
if [ -z "${source_version:-}" ] || [ -z "${target_version:-}" ]; then
- e_err "Source (${source_version}) and target (${target_version}) versions need to be defined."
+ e_err "Source (${source_version:-missing source version}) and target (${target_version:-missing target version}) versions need to be defined."
+ echo
+ usage
exit 1
fi
sub gen_condition ($) {
my $condition = shift;
- # remove '!()', just as include/package-ipkg.mk does
+ # remove '!()', just as include/package-pack.mk does
$condition =~ s/[()!]//g;
return join("", map(and_condition($_), split('\|\|', $condition)));
}
rootsize="$( round_up "$( stat -c%s "$2" )" 1024 )"
;;
esac
- ubivol $vol_id rootfs "$2" "$autoresize" "$rootsize" dynamic
+ ubivol $vol_id rootfs "$2" "$autoresize" "$rootsize"
vol_id=$(( vol_id + 1 ))
- [ "$rootfs_type" = "ubifs" ] || ubivol $vol_id rootfs_data "" 1 dymamic
+ [ "$rootfs_type" = "ubifs" ] || ubivol $vol_id rootfs_data "" 1
fi
}
config i686
bool
+config loongarch64
+ select ARCH_64BIT
+ bool
+
config m68k
bool
default "armeb" if armeb
default "i386" if i386
default "i686" if i686
+ default "loongarch64" if loongarch64
default "m68k" if m68k
default "mips" if mips
default "mipsel" if mipsel
override MAKEFLAGS=
-IB_NAME:=$(VERSION_DIST_SANITIZED)-imagebuilder-$(if $(CONFIG_VERSION_FILENAMES),$(VERSION_NUMBER)-)$(BOARD)$(if $(SUBTARGET),-$(SUBTARGET)).$(HOST_OS)-$(HOST_ARCH)
+IB_NAME:=$(VERSION_DIST_SANITIZED)-imagebuilder-$(if $(CONFIG_VERSION_FILENAMES),$(VERSION_NUMBER)-)$(BOARD)-$(SUBTARGET).$(HOST_OS)-$(HOST_ARCH)
PKG_BUILD_DIR:=$(BUILD_DIR)/$(IB_NAME)
IB_KDIR:=$(patsubst $(TOPDIR)/%,$(PKG_BUILD_DIR)/%,$(KERNEL_BUILD_DIR))
IB_LDIR:=$(patsubst $(TOPDIR)/%,$(PKG_BUILD_DIR)/%,$(LINUX_DIR))
BUNDLER_PATH := $(subst $(space),:,$(filter-out $(TOPDIR)/%,$(subst :,$(space),$(PATH))))
BUNDLER_COMMAND := PATH=$(BUNDLER_PATH) $(XARGS) $(SCRIPT_DIR)/bundle-libraries.sh $(PKG_BUILD_DIR)/staging_dir/host
+PACKAGE_SUFFIX:=$(if $(CONFIG_USE_APK),apk,ipk)
+
all: compile
-$(BIN_DIR)/$(IB_NAME).tar.xz: clean
+$(BIN_DIR)/$(IB_NAME).tar.zst: clean
rm -rf $(PKG_BUILD_DIR)
mkdir -p $(IB_KDIR) $(IB_LDIR) $(PKG_BUILD_DIR)/staging_dir/host/lib \
$(PKG_BUILD_DIR)/target/linux $(PKG_BUILD_DIR)/scripts $(IB_DTSDIR)
$(INCLUDE_DIR) $(SCRIPT_DIR) \
$(TOPDIR)/rules.mk \
./files/Makefile \
- ./files/repositories.conf \
$(TMP_DIR)/.targetinfo \
$(TMP_DIR)/.packageinfo \
$(PKG_BUILD_DIR)/
+ $(INSTALL_DIR) $(PKG_BUILD_DIR)/packages
+
ifeq ($(CONFIG_IB_STANDALONE),)
+ifneq ($(CONFIG_USE_APK),)
+ $(call FeedSourcesAppendAPK,$(PKG_BUILD_DIR)/repositories)
+ $(VERSION_SED_SCRIPT) $(PKG_BUILD_DIR)/repositories
+else
echo '## Remote package repositories' >> $(PKG_BUILD_DIR)/repositories.conf
- $(call FeedSourcesAppend,$(PKG_BUILD_DIR)/repositories.conf)
+ $(call FeedSourcesAppendOPKG,$(PKG_BUILD_DIR)/repositories.conf)
$(VERSION_SED_SCRIPT) $(PKG_BUILD_DIR)/repositories.conf
-endif
- $(INSTALL_DIR) $(PKG_BUILD_DIR)/packages
# create an empty package index so `opkg` doesn't report an error
touch $(PKG_BUILD_DIR)/packages/Packages
$(INSTALL_DATA) ./files/README.md $(PKG_BUILD_DIR)/packages/
echo '' >> $(PKG_BUILD_DIR)/repositories.conf
echo '## This is the local package repository, do not remove!' >> $(PKG_BUILD_DIR)/repositories.conf
echo 'src imagebuilder file:packages' >> $(PKG_BUILD_DIR)/repositories.conf
+endif
+endif
ifeq ($(CONFIG_BUILDBOT),)
ifeq ($(CONFIG_IB_STANDALONE),)
$(FIND) $(call FeedPackageDir,libc) -type f \
- \( -name 'libc_*.ipk' -or -name 'kernel_*.ipk' -or -name 'kmod-*.ipk' \) \
+ \( -name 'libc_*.$(PACKAGE_SUFFIX)' -or -name 'kernel_*.$(PACKAGE_SUFFIX)' -or -name 'kmod-*.$(PACKAGE_SUFFIX)' \) \
-exec $(CP) -t $(PKG_BUILD_DIR)/packages {} +
else
- $(FIND) $(wildcard $(PACKAGE_SUBDIRS)) -type f -name '*.ipk' \
+ $(FIND) $(wildcard $(PACKAGE_SUBDIRS)) -type f -name '*.$(PACKAGE_SUFFIX)' \
-exec $(CP) -t $(PKG_BUILD_DIR)/packages/ {} +
endif
else
$(FIND) $(call FeedPackageDir,libc) -type f \
- \( -name 'libc_*.ipk' -or -name 'kernel_*.ipk' \) \
+ \( -name 'libc_*.$(PACKAGE_SUFFIX)' -or -name 'kernel_*.$(PACKAGE_SUFFIX)' \) \
-exec $(CP) -t $(IB_LDIR)/ {} +
endif
+ifneq ($(CONFIG_USE_APK),y)
ifneq ($(CONFIG_SIGNATURE_CHECK),)
echo '' >> $(PKG_BUILD_DIR)/repositories.conf
echo 'option check_signature' >> $(PKG_BUILD_DIR)/repositories.conf
$(INSTALL_DIR) $(PKG_BUILD_DIR)/keys
$(CP) -L $(STAGING_DIR_ROOT)/etc/opkg/keys/ $(PKG_BUILD_DIR)/
$(CP) -L $(STAGING_DIR_ROOT)/usr/sbin/opkg-key $(PKG_BUILD_DIR)/scripts/
+endif
endif
$(CP) -L $(TOPDIR)/target/linux/Makefile $(PKG_BUILD_DIR)/target/linux
$(BUNDLER_COMMAND))
$(CP) $(TOPDIR)/staging_dir/host/lib/libfakeroot* $(PKG_BUILD_DIR)/staging_dir/host/lib
STRIP=$(STAGING_DIR_HOST)/bin/sstrip $(SCRIPT_DIR)/rstrip.sh $(PKG_BUILD_DIR)/staging_dir/host/bin/
+
(cd $(BUILD_DIR); \
- tar -I '$(STAGING_DIR_HOST)/bin/xz -7e -T$(if $(filter 1,$(NPROC)),2,0)' -cf $@ $(IB_NAME) \
+ tar -I '$(STAGING_DIR_HOST)/bin/zstd -T0 --ultra -20' -cf $@ $(IB_NAME) \
--mtime="$(shell date --date=@$(SOURCE_DATE_EPOCH))"; \
)
download:
prepare:
-compile: $(BIN_DIR)/$(IB_NAME).tar.xz
+compile: $(BIN_DIR)/$(IB_NAME).tar.zst
install: compile
clean: FORCE
- rm -rf $(PKG_BUILD_DIR) $(BIN_DIR)/$(IB_NAME).tar.xz
+ rm -rf $(PKG_BUILD_DIR) $(BIN_DIR)/$(IB_NAME).tar.zst
# override variables from rules.mk
PACKAGE_DIR:=$(TOPDIR)/packages
LISTS_DIR:=$(subst $(space),/,$(patsubst %,..,$(subst /,$(space),$(TARGET_DIR))))$(DL_DIR)
+PACKAGE_DIR_ALL:=$(TOPDIR)/packages
+
export OPKG_KEYS:=$(TOPDIR)/keys
OPKG:=$(call opkg,$(TARGET_DIR)) \
-f $(TOPDIR)/repositories.conf \
--cache $(DL_DIR) \
--lists-dir $(LISTS_DIR)
+APK:=$(call apk,$(TARGET_DIR)) \
+ --cache-dir $(DL_DIR) \
+ --allow-untrusted
+
+
include $(INCLUDE_DIR)/target.mk
-include .profiles.mk
.profiles.mk: .targetinfo
- @$(SCRIPT_DIR)/target-metadata.pl profile_mk $< '$(BOARD)$(if $(SUBTARGET),/$(SUBTARGET))' > $@
+ @$(SCRIPT_DIR)/target-metadata.pl profile_mk $< '$(BOARD)/$(SUBTARGET)' > $@
staging_dir/host/.prereq-build: include/prereq-build.mk
mkdir -p tmp
mkdir -p $(TARGET_DIR) $(BIN_DIR) $(TMP_DIR) $(DL_DIR)
$(MAKE) package_reload >/dev/null
$(MAKE) package_install >/dev/null
+ifeq ($(CONFIG_USE_APK),)
$(OPKG) list-installed $(if $(STRIP_ABI),--strip-abi)
+else
+ $(APK) list --quiet --manifest --no-network
+endif
package_index: FORCE
@echo >&2
@echo Building package index... >&2
@mkdir -p $(TMP_DIR) $(TARGET_DIR)/tmp
+ifeq ($(CONFIG_USE_APK),)
(cd $(PACKAGE_DIR); $(SCRIPT_DIR)/ipkg-make-index.sh . > Packages && \
gzip -9nc Packages > Packages.gz; \
$(if $(CONFIG_SIGNATURE_CHECK), \
$(STAGING_DIR_HOST)/bin/usign -S -m Packages -s $(BUILD_KEY)) \
) >/dev/null 2>/dev/null
$(OPKG) update >&2 || true
+else
+ (cd $(PACKAGE_DIR); $(APK) mkndx --output packages.adb *.apk) >&2
+endif
package_reload:
+ifeq ($(CONFIG_USE_APK),)
if [ -d "$(PACKAGE_DIR)" ] && ( \
[ ! -f "$(PACKAGE_DIR)/Packages" ] || \
[ ! -f "$(PACKAGE_DIR)/Packages.gz" ] || \
mkdir -p $(TARGET_DIR)/tmp; \
$(OPKG) update >&2 || true; \
fi
+else
+ if [ -d "$(PACKAGE_DIR)" ] && ( \
+ [ ! -f "$(PACKAGE_DIR)/packages.adb" ] || \
+ [ "`find $(PACKAGE_DIR) -cnewer $(PACKAGE_DIR)/packages.adb`" ] ); then \
+ echo "Package list missing or not up-to-date, generating it." >&2 ;\
+ $(MAKE) package_index; \
+ else \
+ mkdir -p $(TARGET_DIR)/tmp; \
+ $(APK) update >&2 || true; \
+ fi
+endif
package_list: FORCE
@$(MAKE) -s package_reload
+ifeq ($(CONFIG_USE_APK),)
@$(OPKG) list --size 2>/dev/null
+else
+ @$(APK) list --size 2>/dev/null
+endif
package_install: FORCE
@echo
@echo Installing packages...
+ifeq ($(CONFIG_USE_APK),)
$(OPKG) install $(firstword $(wildcard $(LINUX_DIR)/libc_*.ipk $(PACKAGE_DIR)/libc_*.ipk))
$(OPKG) install $(firstword $(wildcard $(LINUX_DIR)/kernel_*.ipk $(PACKAGE_DIR)/kernel_*.ipk))
$(OPKG) install $(BUILD_PACKAGES)
+else
+ $(APK) add --initdb --no-scripts $(firstword $(wildcard $(LINUX_DIR)/libc-*.apk $(PACKAGE_DIR)/libc_*.apk))
+ $(APK) add --no-scripts $(firstword $(wildcard $(LINUX_DIR)/kernel-*.apk $(PACKAGE_DIR)/kernel_*.apk))
+ $(APK) add --no-scripts $(BUILD_PACKAGES)
+endif
prepare_rootfs: FORCE
@echo
@echo Finalizing root filesystem...
$(CP) $(TARGET_DIR) $(TARGET_DIR_ORIG)
+ifeq ($(CONFIG_USE_APK),)
$(if $(CONFIG_SIGNATURE_CHECK), \
$(if $(ADD_LOCAL_KEY), \
OPKG_KEYS=$(TARGET_DIR)/etc/opkg/keys/ \
$(SCRIPT_DIR)/opkg-key add $(BUILD_KEY).pub \
) \
)
+endif
$(call prepare_rootfs,$(TARGET_DIR),$(USER_FILES),$(DISABLED_SERVICES))
build_image: FORCE
endif
_check_keys: FORCE
+ifeq ($(CONFIG_USE_APK),)
ifneq ($(CONFIG_SIGNATURE_CHECK),)
@if [ ! -s $(BUILD_KEY) -o ! -s $(BUILD_KEY).pub ]; then \
echo Generate local signing keys... >&2; \
-s $(BUILD_KEY); \
fi
endif
+else
+ # TODO
+endif
image:
$(MAKE) -s _check_profile
@exit 1
endif
@$(MAKE) -s package_reload
- @$(OPKG) whatdepends -A $(PACKAGE)
+ifeq ($(CONFIG_USE_APK),)
+ @$(OPKG) list --depends $(PACKAGE)
+else
+ @$(APK) list --depends $(PACKAGE)
+endif
package_depends: FORCE
ifeq ($(PACKAGE),)
@exit 1
endif
@$(MAKE) -s package_reload
+ifeq ($(CONFIG_USE_APK),)
@$(OPKG) depends -A $(PACKAGE)
-
+else
+ @$(OPKG) whatdepends -A $(PACKAGE)
+endif
.SILENT: help info image manifest package_whatdepends package_depends
FEATURES:=dt squashfs nand ramdisk gpio source-only
KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_AIROHA=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_EN7523=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MISC=y
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_EN7523=y
+CONFIG_GPIO_GENERIC=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IOMMUFD is not set
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PINCTRL=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_AIROHA_EN7523=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_STACKTRACE=y
+# CONFIG_SWAP is not set
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_USE_OF=y
+# CONFIG_VFP is not set
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -353,6 +353,12 @@ config SPI_DLN2
+ This driver can also be built as a module. If so, the module
+ will be called spi-dln2.
+
++config SPI_AIROHA_EN7523
++ bool "Airoha EN7523 SPI controller support"
++ depends on ARCH_AIROHA
++ help
++ This enables SPI controller support for the Airoha EN7523 SoC.
++
+ config SPI_EP93XX
+ tristate "Cirrus Logic EP93xx SPI controller"
+ depends on ARCH_EP93XX || COMPILE_TEST
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -50,6 +50,7 @@ obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1.
+ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
+ obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o
+ obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
++obj-$(CONFIG_SPI_AIROHA_EN7523) += spi-en7523.o
+ obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
+ obj-$(CONFIG_SPI_FSI) += spi-fsi.o
+ obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o
+--- /dev/null
++++ b/drivers/spi/spi-en7523.c
+@@ -0,0 +1,313 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/mod_devicetable.h>
++#include <linux/spi/spi.h>
++
++
++#define ENSPI_READ_IDLE_EN 0x0004
++#define ENSPI_MTX_MODE_TOG 0x0014
++#define ENSPI_RDCTL_FSM 0x0018
++#define ENSPI_MANUAL_EN 0x0020
++#define ENSPI_MANUAL_OPFIFO_EMPTY 0x0024
++#define ENSPI_MANUAL_OPFIFO_WDATA 0x0028
++#define ENSPI_MANUAL_OPFIFO_FULL 0x002C
++#define ENSPI_MANUAL_OPFIFO_WR 0x0030
++#define ENSPI_MANUAL_DFIFO_FULL 0x0034
++#define ENSPI_MANUAL_DFIFO_WDATA 0x0038
++#define ENSPI_MANUAL_DFIFO_EMPTY 0x003C
++#define ENSPI_MANUAL_DFIFO_RD 0x0040
++#define ENSPI_MANUAL_DFIFO_RDATA 0x0044
++#define ENSPI_IER 0x0090
++#define ENSPI_NFI2SPI_EN 0x0130
++
++// TODO not in spi block
++#define ENSPI_CLOCK_DIVIDER ((void __iomem *)0x1fa201c4)
++
++#define OP_CSH 0x00
++#define OP_CSL 0x01
++#define OP_CK 0x02
++#define OP_OUTS 0x08
++#define OP_OUTD 0x09
++#define OP_OUTQ 0x0A
++#define OP_INS 0x0C
++#define OP_INS0 0x0D
++#define OP_IND 0x0E
++#define OP_INQ 0x0F
++#define OP_OS2IS 0x10
++#define OP_OS2ID 0x11
++#define OP_OS2IQ 0x12
++#define OP_OD2IS 0x13
++#define OP_OD2ID 0x14
++#define OP_OD2IQ 0x15
++#define OP_OQ2IS 0x16
++#define OP_OQ2ID 0x17
++#define OP_OQ2IQ 0x18
++#define OP_OSNIS 0x19
++#define OP_ODNID 0x1A
++
++#define MATRIX_MODE_AUTO 1
++#define CONF_MTX_MODE_AUTO 0
++#define MANUALEN_AUTO 0
++#define MATRIX_MODE_MANUAL 0
++#define CONF_MTX_MODE_MANUAL 9
++#define MANUALEN_MANUAL 1
++
++#define _ENSPI_MAX_XFER 0x1ff
++
++#define REG(x) (iobase + x)
++
++
++static void __iomem *iobase;
++
++
++static void opfifo_write(u32 cmd, u32 len)
++{
++ u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff);
++
++ writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA));
++
++ /* Wait for room in OPFIFO */
++ while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL)))
++ ;
++
++ /* Shift command into OPFIFO */
++ writel(1, REG(ENSPI_MANUAL_OPFIFO_WR));
++
++ /* Wait for command to finish */
++ while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY)))
++ ;
++}
++
++static void set_cs(int state)
++{
++ if (state)
++ opfifo_write(OP_CSH, 1);
++ else
++ opfifo_write(OP_CSL, 1);
++}
++
++static void manual_begin_cmd(void)
++{
++ /* Disable read idle state */
++ writel(0, REG(ENSPI_READ_IDLE_EN));
++
++ /* Wait for FSM to reach idle state */
++ while (readl(REG(ENSPI_RDCTL_FSM)))
++ ;
++
++ /* Set SPI core to manual mode */
++ writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG));
++ writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN));
++}
++
++static void manual_end_cmd(void)
++{
++ /* Set SPI core to auto mode */
++ writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG));
++ writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN));
++
++ /* Enable read idle state */
++ writel(1, REG(ENSPI_READ_IDLE_EN));
++}
++
++static void dfifo_read(u8 *buf, int len)
++{
++ int i;
++
++ for (i = 0; i < len; i++) {
++ /* Wait for requested data to show up in DFIFO */
++ while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY)))
++ ;
++ buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA));
++ /* Queue up next byte */
++ writel(1, REG(ENSPI_MANUAL_DFIFO_RD));
++ }
++}
++
++static void dfifo_write(const u8 *buf, int len)
++{
++ int i;
++
++ for (i = 0; i < len; i++) {
++ /* Wait for room in DFIFO */
++ while (readl(REG(ENSPI_MANUAL_DFIFO_FULL)))
++ ;
++ writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA));
++ }
++}
++
++#if 0
++static void set_spi_clock_speed(int freq_mhz)
++{
++ u32 tmp, val;
++
++ tmp = readl(ENSPI_CLOCK_DIVIDER);
++ tmp &= 0xffff0000;
++ writel(tmp, ENSPI_CLOCK_DIVIDER);
++
++ val = (400 / (freq_mhz * 2));
++ tmp |= (val << 8) | 1;
++ writel(tmp, ENSPI_CLOCK_DIVIDER);
++}
++#endif
++
++static void init_hw(void)
++{
++ /* Disable manual/auto mode clash interrupt */
++ writel(0, REG(ENSPI_IER));
++
++ // TODO via clk framework
++ // set_spi_clock_speed(50);
++
++ /* Disable DMA */
++ writel(0, REG(ENSPI_NFI2SPI_EN));
++}
++
++static int xfer_read(struct spi_transfer *xfer)
++{
++ int opcode;
++ uint8_t *buf = xfer->rx_buf;
++
++ switch (xfer->rx_nbits) {
++ case SPI_NBITS_SINGLE:
++ opcode = OP_INS;
++ break;
++ case SPI_NBITS_DUAL:
++ opcode = OP_IND;
++ break;
++ case SPI_NBITS_QUAD:
++ opcode = OP_INQ;
++ break;
++ }
++
++ opfifo_write(opcode, xfer->len);
++ dfifo_read(buf, xfer->len);
++
++ return xfer->len;
++}
++
++static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx)
++{
++ int opcode;
++ const uint8_t *buf = xfer->tx_buf;
++
++ if (next_xfer_is_rx) {
++ /* need to use Ox2Ix opcode to set the core to input afterwards */
++ switch (xfer->tx_nbits) {
++ case SPI_NBITS_SINGLE:
++ opcode = OP_OS2IS;
++ break;
++ case SPI_NBITS_DUAL:
++ opcode = OP_OS2ID;
++ break;
++ case SPI_NBITS_QUAD:
++ opcode = OP_OS2IQ;
++ break;
++ }
++ } else {
++ switch (xfer->tx_nbits) {
++ case SPI_NBITS_SINGLE:
++ opcode = OP_OUTS;
++ break;
++ case SPI_NBITS_DUAL:
++ opcode = OP_OUTD;
++ break;
++ case SPI_NBITS_QUAD:
++ opcode = OP_OUTQ;
++ break;
++ }
++ }
++
++ opfifo_write(opcode, xfer->len);
++ dfifo_write(buf, xfer->len);
++
++ return xfer->len;
++}
++
++size_t max_transfer_size(struct spi_device *spi)
++{
++ return _ENSPI_MAX_XFER;
++}
++
++int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg)
++{
++ struct spi_transfer *xfer;
++ int next_xfer_is_rx = 0;
++
++ manual_begin_cmd();
++ set_cs(0);
++ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++ if (xfer->tx_buf) {
++ if (!list_is_last(&xfer->transfer_list, &msg->transfers)
++ && list_next_entry(xfer, transfer_list)->rx_buf != NULL)
++ next_xfer_is_rx = 1;
++ else
++ next_xfer_is_rx = 0;
++ msg->actual_length += xfer_write(xfer, next_xfer_is_rx);
++ } else if (xfer->rx_buf) {
++ msg->actual_length += xfer_read(xfer);
++ }
++ }
++ set_cs(1);
++ manual_end_cmd();
++
++ msg->status = 0;
++ spi_finalize_current_message(ctrl);
++
++ return 0;
++}
++
++static int spi_probe(struct platform_device *pdev)
++{
++ struct spi_controller *ctrl;
++ int err;
++
++ ctrl = devm_spi_alloc_master(&pdev->dev, 0);
++ if (!ctrl) {
++ dev_err(&pdev->dev, "Error allocating SPI controller\n");
++ return -ENOMEM;
++ }
++
++ iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
++ if (IS_ERR(iobase)) {
++ dev_err(&pdev->dev, "Could not map SPI register address");
++ return -ENOMEM;
++ }
++
++ init_hw();
++
++ ctrl->dev.of_node = pdev->dev.of_node;
++ ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
++ ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL;
++ ctrl->max_transfer_size = max_transfer_size;
++ ctrl->transfer_one_message = transfer_one_message;
++ err = devm_spi_register_controller(&pdev->dev, ctrl);
++ if (err) {
++ dev_err(&pdev->dev, "Could not register SPI controller\n");
++ return -ENODEV;
++ }
++
++ return 0;
++}
++
++static const struct of_device_id spi_of_ids[] = {
++ { .compatible = "airoha,en7523-spi" },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, spi_of_ids);
++
++static struct platform_driver spi_driver = {
++ .probe = spi_probe,
++ .driver = {
++ .name = "airoha-en7523-spi",
++ .of_match_table = spi_of_ids,
++ },
++};
++
++module_platform_driver(spi_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
++MODULE_DESCRIPTION("Airoha EN7523 SPI driver");
FEATURES+=cpiogz ext4 ramdisk squashfs targz vmdk
KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MMAP_RND_BITS=8
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_V4 is not set
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_VIRT=y
+CONFIG_ARM=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_CACHE_L2X0=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMA_OPS=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HAVE_SMP=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_NEON=y
+CONFIG_NR_CPUS=4
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYS_OFFSET=0
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+# CONFIG_UNWINDER_FRAME_POINTER is not set
+CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
--- /dev/null
+CONFIG_64BIT=y
+CONFIG_ACPI_APEI=y
+# CONFIG_ACPI_FFH is not set
+# CONFIG_ACPI_FPDT is not set
+CONFIG_ACPI_HMAT=y
+CONFIG_ACPI_PCC=y
+CONFIG_AHCI_IMX=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM2835=y
+# CONFIG_ARCH_BCMBCA is not set
+CONFIG_ARCH_BCM_IPROC=y
+CONFIG_ARCH_BRCMSTB=y
+CONFIG_ARCH_HISI=y
+CONFIG_ARCH_INTEL_SOCFPGA=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_MVEBU=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NXP=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_R8A774A1=y
+CONFIG_ARCH_R8A774B1=y
+CONFIG_ARCH_R8A774C0=y
+CONFIG_ARCH_R8A774E1=y
+# CONFIG_ARCH_R8A77950 is not set
+# CONFIG_ARCH_R8A77951 is not set
+# CONFIG_ARCH_R8A77960 is not set
+# CONFIG_ARCH_R8A77961 is not set
+# CONFIG_ARCH_R8A77965 is not set
+# CONFIG_ARCH_R8A77970 is not set
+# CONFIG_ARCH_R8A77980 is not set
+# CONFIG_ARCH_R8A77990 is not set
+# CONFIG_ARCH_R8A77995 is not set
+# CONFIG_ARCH_R8A779A0 is not set
+# CONFIG_ARCH_R8A779F0 is not set
+# CONFIG_ARCH_R8A779G0 is not set
+CONFIG_ARCH_R9A07G043=y
+CONFIG_ARCH_R9A07G044=y
+CONFIG_ARCH_R9A07G054=y
+CONFIG_ARCH_R9A09G011=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SYNQUACER=y
+CONFIG_ARCH_THUNDER=y
+CONFIG_ARCH_THUNDER2=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_AMU_EXTN=y
+CONFIG_ARM64_BTI=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_E0PD=y
+CONFIG_ARM64_EPAN=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_1319367=y
+CONFIG_ARM64_ERRATUM_1418040=y
+CONFIG_ARM64_ERRATUM_1463225=y
+CONFIG_ARM64_ERRATUM_1508412=y
+CONFIG_ARM64_ERRATUM_1530923=y
+CONFIG_ARM64_ERRATUM_1542419=y
+CONFIG_ARM64_ERRATUM_1742098=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2441007=y
+CONFIG_ARM64_ERRATUM_2441009=y
+CONFIG_ARM64_ERRATUM_2457168=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_834220=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_MTE=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_TLB_RANGE=y
+CONFIG_ARM64_VA_BITS=48
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+# CONFIG_ARMADA_37XX_RWTM_MBOX is not set
+CONFIG_ARMADA_37XX_WATCHDOG=y
+CONFIG_ARMADA_THERMAL=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+# CONFIG_ARM_DMC620_PMU is not set
+# CONFIG_ARM_MHU_V2 is not set
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_SBSA_WATCHDOG=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SMCCC_SOC_ID=y
+CONFIG_ARM_SMC_WATCHDOG=y
+CONFIG_ARM_SMMU=y
+# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_PMU is not set
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_ATOMIC64_SELFTEST=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+# CONFIG_AXI_DMAC is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BCM2711_THERMAL is not set
+CONFIG_BCM2835_MBOX=y
+CONFIG_BCM2835_POWER=y
+# CONFIG_BCM2835_THERMAL is not set
+# CONFIG_BCM2835_VCHIQ is not set
+CONFIG_BCM2835_WDT=y
+# CONFIG_BCMASP is not set
+# CONFIG_BCMGENET is not set
+# CONFIG_BCM_CYGNUS_PHY is not set
+# CONFIG_BCM_FLEXRM_MBOX is not set
+# CONFIG_BCM_NS_THERMAL is not set
+# CONFIG_BCM_PDC_MBOX is not set
+# CONFIG_BCM_SR_THERMAL is not set
+CONFIG_BCM_VIDEOCORE=y
+# CONFIG_BGMAC_PLATFORM is not set
+CONFIG_BLK_PM=y
+# CONFIG_BRCMSTB_PM is not set
+# CONFIG_BRCMSTB_THERMAL is not set
+CONFIG_BRCM_USB_PINMAP=y
+CONFIG_CAVIUM_ERRATUM_22375=y
+CONFIG_CAVIUM_ERRATUM_23144=y
+CONFIG_CAVIUM_ERRATUM_23154=y
+CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CAVIUM_ERRATUM_30115=y
+CONFIG_CAVIUM_TX2_ERRATUM_219=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CLK_BCM2711_DVP=y
+CONFIG_CLK_BCM2835=y
+CONFIG_CLK_BCM_NS2=y
+CONFIG_CLK_BCM_SR=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MQ=y
+CONFIG_CLK_IMX8QXP=y
+CONFIG_CLK_IMX8ULP=y
+CONFIG_CLK_IMX93=y
+CONFIG_CLK_INTEL_SOCFPGA=y
+CONFIG_CLK_INTEL_SOCFPGA64=y
+CONFIG_CLK_LS1028A_PLLDIG=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_QORIQ=y
+CONFIG_CLK_RASPBERRYPI=y
+CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
+CONFIG_CLK_RENESAS=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3568=y
+CONFIG_CLK_RK3588=y
+CONFIG_CLK_SP810=y
+CONFIG_CLK_SUNXI=y
+CONFIG_CLK_SUNXI_CLOCKS=y
+# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set
+# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set
+# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
+CONFIG_CLK_VEXPRESS_OSC=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=19
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=32
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+# CONFIG_COMMON_CLK_FSL_FLEXSPI is not set
+# CONFIG_COMMON_CLK_FSL_SAI is not set
+CONFIG_COMMON_CLK_HI3516CV300=y
+CONFIG_COMMON_CLK_HI3519=y
+CONFIG_COMMON_CLK_HI3559A=y
+CONFIG_COMMON_CLK_HI3660=y
+CONFIG_COMMON_CLK_HI3670=y
+CONFIG_COMMON_CLK_HI3798CV200=y
+CONFIG_COMMON_CLK_HI6220=y
+CONFIG_COMMON_CLK_HI655X=y
+CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMMON_CLK_ZYNQMP=y
+CONFIG_COMMON_RESET_HI3660=y
+CONFIG_COMMON_RESET_HI6220=y
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PM=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_BS=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_CHACHA20=y
+CONFIG_CRYPTO_CHACHA20_NEON=y
+CONFIG_CRYPTO_CRYPTD=y
+# CONFIG_CRYPTO_DEV_ALLWINNER is not set
+# CONFIG_CRYPTO_DEV_BCM_SPU is not set
+# CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM is not set
+# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
+# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
+# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
+# CONFIG_CRYPTO_DEV_OCTEONTX2_CPT is not set
+# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
+# CONFIG_CRYPTO_DEV_ZYNQMP_AES is not set
+# CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 is not set
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64=y
+CONFIG_CRYPTO_SIMD=y
+# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set
+# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
+# CONFIG_DEV_DAX_HMEM is not set
+CONFIG_DMA_BCM2835=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DIRECT_REMAP=y
+# CONFIG_DMA_NUMA_CMA is not set
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_SUN6I=y
+CONFIG_DRM=y
+CONFIG_DRM_BOCHS=y
+CONFIG_DRM_BRIDGE=y
+# CONFIG_DRM_FSL_LDB is not set
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+# CONFIG_DRM_IMX8QM_LDB is not set
+# CONFIG_DRM_IMX8QXP_LDB is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_LINK is not set
+# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set
+# CONFIG_DRM_IMX_DCSS is not set
+# CONFIG_DRM_IMX_LCDC is not set
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
+# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
+# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
+# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set
+# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set
+# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
+CONFIG_DRM_QXL=y
+# CONFIG_DRM_RCAR_DU is not set
+# CONFIG_DRM_ROCKCHIP is not set
+# CONFIG_DRM_RZG2L_MIPI_DSI is not set
+# CONFIG_DRM_SHMOBILE is not set
+CONFIG_DRM_TTM=y
+CONFIG_DRM_TTM_HELPER=y
+# CONFIG_DRM_V3D is not set
+CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_DRM_VIRTIO_GPU_KMS=y
+CONFIG_DRM_VRAM_HELPER=y
+# CONFIG_DWMAC_SUN8I is not set
+# CONFIG_DWMAC_SUNXI is not set
+CONFIG_DW_WATCHDOG=y
+CONFIG_EFI_CAPSULE_LOADER=y
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+CONFIG_EFI_SOFT_RESERVE=y
+CONFIG_EFI_VARS_PSTORE=y
+# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_MX3=y
+# CONFIG_FB_SH_MOBILE_LCDC is not set
+# CONFIG_FB_XILINX is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_FSL_DPAA is not set
+# CONFIG_FSL_DPAA2_QDMA is not set
+CONFIG_FSL_ERRATUM_A008585=y
+# CONFIG_FSL_IMX8_DDR_PMU is not set
+# CONFIG_FSL_PQ_MDIO is not set
+CONFIG_FUJITSU_ERRATUM_010001=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+# CONFIG_GIANFAR is not set
+CONFIG_GPIO_BCM_XGS_IPROC=y
+CONFIG_GPIO_BRCMSTB=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_RASPBERRYPI_EXP=y
+CONFIG_GPIO_ROCKCHIP=y
+CONFIG_GPIO_THUNDERX=y
+CONFIG_GPIO_XLP=y
+CONFIG_GPIO_ZYNQ=y
+CONFIG_GPIO_ZYNQMP_MODEPIN=y
+CONFIG_HDMI=y
+CONFIG_HI3660_MBOX=y
+CONFIG_HI6220_MBOX=y
+CONFIG_HISILICON_ERRATUM_161600802=y
+CONFIG_HISILICON_LPC=y
+CONFIG_HISI_PMU=y
+CONFIG_HISI_THERMAL=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
+# CONFIG_HW_RANDOM_HISI is not set
+# CONFIG_HW_RANDOM_HISTB is not set
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_ALTERA=y
+# CONFIG_I2C_BCM2835 is not set
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_HIX5HD2 is not set
+CONFIG_I2C_IMX=y
+CONFIG_I2C_IMX_LPI2C=y
+CONFIG_I2C_RIIC=y
+# CONFIG_I2C_RZV2M is not set
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_I2C_SYNQUACER=y
+CONFIG_I2C_THUNDERX=y
+# CONFIG_I2C_XLP9XX is not set
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+# CONFIG_IMX2_WDT is not set
+# CONFIG_IMX8MM_THERMAL is not set
+# CONFIG_IMX8QXP_ADC is not set
+# CONFIG_IMX93_ADC is not set
+# CONFIG_IMX_DMA is not set
+# CONFIG_IMX_DSP is not set
+CONFIG_IMX_INTMUX=y
+CONFIG_IMX_IRQSTEER=y
+CONFIG_IMX_MBOX=y
+# CONFIG_IMX_MU_MSI is not set
+CONFIG_IMX_SCU=y
+CONFIG_IMX_SCU_PD=y
+# CONFIG_IMX_SC_THERMAL is not set
+# CONFIG_IMX_SC_WDT is not set
+# CONFIG_IMX_SDMA is not set
+# CONFIG_IMX_WEIM is not set
+# CONFIG_INPUT_BBNSM_PWRKEY is not set
+# CONFIG_INPUT_HISI_POWERKEY is not set
+# CONFIG_INPUT_IBM_PANEL is not set
+# CONFIG_INTEL_STRATIX10_RSU is not set
+# CONFIG_INTEL_STRATIX10_SERVICE is not set
+CONFIG_INTERCONNECT=y
+CONFIG_INTERCONNECT_IMX=y
+CONFIG_INTERCONNECT_IMX8MM=y
+CONFIG_INTERCONNECT_IMX8MN=y
+CONFIG_INTERCONNECT_IMX8MP=y
+CONFIG_INTERCONNECT_IMX8MQ=y
+# CONFIG_IOMMUFD is not set
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_DART is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IPMMU_VMSA is not set
+# CONFIG_K3_DMA is not set
+CONFIG_KCMP=y
+# CONFIG_KEYBOARD_IMX_SC_KEY is not set
+# CONFIG_KEYBOARD_SUN4I_LRADC is not set
+CONFIG_KSM=y
+# CONFIG_KUNPENG_HCCS is not set
+CONFIG_KVM=y
+CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MARVELL_10G_PHY=y
+# CONFIG_MARVELL_CN10K_DDR_PMU is not set
+# CONFIG_MARVELL_CN10K_TAD_PMU is not set
+# CONFIG_MARVELL_GTI_WDT is not set
+CONFIG_MDIO_BCM_IPROC=y
+CONFIG_MDIO_BUS_MUX_BCM_IPROC=y
+CONFIG_MDIO_SUN4I=y
+# CONFIG_MFD_ALTERA_A10SR is not set
+CONFIG_MFD_ALTERA_SYSMGR=y
+# CONFIG_MFD_AXP20X_RSB is not set
+CONFIG_MFD_CORE=y
+CONFIG_MFD_HI655X_PMIC=y
+# CONFIG_MFD_KHADAS_MCU is not set
+CONFIG_MFD_SUN4I_GPADC=y
+# CONFIG_MFD_SUN6I_PRCM is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_BCM2835=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CAVIUM_THUNDERX=y
+CONFIG_MMC_DW=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_ROCKCHIP=y
+# CONFIG_MMC_MXC is not set
+CONFIG_MMC_RICOH_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SDHCI_IPROC=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+CONFIG_MMC_SDHCI_PCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SDHI_INTERNAL_DMAC=y
+# CONFIG_MMC_SDHI_SYS_DMAC is not set
+# CONFIG_MMC_SH_MMCIF is not set
+CONFIG_MMC_SUNXI=y
+CONFIG_MODULES_USE_ELF_RELA=y
+# CONFIG_MVNETA is not set
+# CONFIG_MVPP2 is not set
+# CONFIG_MV_XOR is not set
+# CONFIG_MX3_IPU is not set
+CONFIG_MXC_CLK=y
+CONFIG_MXC_CLK_SCU=y
+# CONFIG_MXS_DMA is not set
+CONFIG_NEED_SG_DMA_LENGTH=y
+# CONFIG_NET_VENDOR_ALLWINNER is not set
+CONFIG_NODES_SHIFT=4
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=256
+CONFIG_NUMA=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+# CONFIG_NVHE_EL2_DEBUG is not set
+CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
+# CONFIG_NVMEM_IMX_IIM is not set
+# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
+CONFIG_NVMEM_IMX_OCOTP_SCU=y
+# CONFIG_NVMEM_LAYERSCAPE_SFP is not set
+CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+# CONFIG_NVMEM_ROCKCHIP_OTP is not set
+# CONFIG_NVMEM_SNVS_LPGPR is not set
+# CONFIG_NVMEM_SUNXI_SID is not set
+# CONFIG_NVMEM_ZYNQMP is not set
+CONFIG_PCC=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_ARMADA_8K=y
+CONFIG_PCIE_BRCMSTB=y
+CONFIG_PCIE_HISI_STB=y
+CONFIG_PCIE_IPROC_MSI=y
+CONFIG_PCIE_IPROC_PLATFORM=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_PCIE_MOBIVEIL_PLAT=y
+# CONFIG_PCIE_RCAR_EP is not set
+CONFIG_PCIE_RCAR_HOST=y
+CONFIG_PCIE_ROCKCHIP=y
+# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set
+CONFIG_PCIE_ROCKCHIP_HOST=y
+CONFIG_PCIE_XILINX_CPM=y
+CONFIG_PCIE_XILINX_NWL=y
+CONFIG_PCI_AARDVARK=y
+CONFIG_PCI_HISI=y
+CONFIG_PCI_HOST_THUNDER_ECAM=y
+CONFIG_PCI_HOST_THUNDER_PEM=y
+CONFIG_PCI_IMX6=y
+CONFIG_PCI_IMX6_HOST=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_PASID=y
+# CONFIG_PCI_RCAR_GEN2 is not set
+CONFIG_PHY_BCM_SR_PCIE=y
+CONFIG_PHY_BCM_SR_USB=y
+CONFIG_PHY_BRCM_SATA=y
+CONFIG_PHY_BRCM_USB=y
+CONFIG_PHY_FSL_IMX8M_PCIE=y
+# CONFIG_PHY_FSL_LYNX_28G is not set
+CONFIG_PHY_HI3660_USB=y
+CONFIG_PHY_HI3670_PCIE=y
+CONFIG_PHY_HI3670_USB=y
+CONFIG_PHY_HI6220_USB=y
+CONFIG_PHY_HISI_INNO_USB2=y
+# CONFIG_PHY_HISTB_COMBPHY is not set
+# CONFIG_PHY_MIXEL_LVDS_PHY is not set
+CONFIG_PHY_MVEBU_A3700_COMPHY=y
+CONFIG_PHY_MVEBU_A3700_UTMI=y
+CONFIG_PHY_MVEBU_A38X_COMPHY=y
+CONFIG_PHY_MVEBU_CP110_COMPHY=y
+CONFIG_PHY_NS2_PCIE=y
+CONFIG_PHY_NS2_USB_DRD=y
+# CONFIG_PHY_R8A779F0_ETHERNET_SERDES is not set
+# CONFIG_PHY_RCAR_GEN2 is not set
+CONFIG_PHY_RCAR_GEN3_PCIE=y
+CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_RCAR_GEN3_USB3=y
+# CONFIG_PHY_ROCKCHIP_DP is not set
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
+CONFIG_PHY_ROCKCHIP_EMMC=y
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set
+CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+# CONFIG_PHY_ROCKCHIP_USB is not set
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_SUN50I_USB3=y
+# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
+CONFIG_PHY_SUN9I_USB=y
+# CONFIG_PHY_XILINX_ZYNQMP is not set
+CONFIG_PINCTRL_IMX=y
+CONFIG_PINCTRL_IMX8DXL=y
+CONFIG_PINCTRL_IMX8MM=y
+CONFIG_PINCTRL_IMX8MN=y
+CONFIG_PINCTRL_IMX8MP=y
+CONFIG_PINCTRL_IMX8MQ=y
+CONFIG_PINCTRL_IMX8QM=y
+CONFIG_PINCTRL_IMX8QXP=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_PINCTRL_IMX93=y
+# CONFIG_PINCTRL_IMXRT1050 is not set
+# CONFIG_PINCTRL_IMXRT1170 is not set
+CONFIG_PINCTRL_IMX_SCU=y
+CONFIG_PINCTRL_IPROC_GPIO=y
+CONFIG_PINCTRL_NS2_MUX=y
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SUN20I_D1 is not set
+CONFIG_PINCTRL_SUN4I_A10=y
+CONFIG_PINCTRL_SUN50I_A100=y
+CONFIG_PINCTRL_SUN50I_A100_R=y
+CONFIG_PINCTRL_SUN50I_A64=y
+CONFIG_PINCTRL_SUN50I_A64_R=y
+CONFIG_PINCTRL_SUN50I_H5=y
+CONFIG_PINCTRL_SUN50I_H6=y
+CONFIG_PINCTRL_SUN50I_H616=y
+CONFIG_PINCTRL_SUN50I_H616_R=y
+CONFIG_PINCTRL_SUN50I_H6_R=y
+CONFIG_PINCTRL_SUN5I=y
+# CONFIG_PINCTRL_SUN6I_A31 is not set
+# CONFIG_PINCTRL_SUN6I_A31_R is not set
+# CONFIG_PINCTRL_SUN8I_A23 is not set
+# CONFIG_PINCTRL_SUN8I_A23_R is not set
+# CONFIG_PINCTRL_SUN8I_A33 is not set
+# CONFIG_PINCTRL_SUN8I_A83T is not set
+# CONFIG_PINCTRL_SUN8I_A83T_R is not set
+# CONFIG_PINCTRL_SUN8I_H3 is not set
+# CONFIG_PINCTRL_SUN8I_H3_R is not set
+# CONFIG_PINCTRL_SUN8I_V3S is not set
+# CONFIG_PINCTRL_SUN9I_A80 is not set
+# CONFIG_PINCTRL_SUN9I_A80_R is not set
+CONFIG_PINCTRL_ZYNQMP=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_HISI=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_PTP_1588_CLOCK_DTE is not set
+# CONFIG_PWM_BCM2835 is not set
+CONFIG_QCOM_FALKOR_ERRATUM_1003=y
+CONFIG_QCOM_FALKOR_ERRATUM_1009=y
+CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
+CONFIG_QCOM_QDF2400_ERRATUM_0065=y
+CONFIG_QORIQ_THERMAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RASPBERRYPI_FIRMWARE=y
+CONFIG_RASPBERRYPI_POWER=y
+# CONFIG_RAVB is not set
+CONFIG_RCAR_DMAC=y
+# CONFIG_RCAR_GEN3_THERMAL is not set
+# CONFIG_RCAR_THERMAL is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_HI655X=y
+CONFIG_REGULATOR_PFUZE100=y
+# CONFIG_REGULATOR_VEXPRESS is not set
+CONFIG_RELOCATABLE=y
+# CONFIG_RENESAS_ETHER_SWITCH is not set
+CONFIG_RENESAS_OSTM=y
+# CONFIG_RENESAS_RZAWDT is not set
+# CONFIG_RENESAS_RZG2LWDT is not set
+# CONFIG_RENESAS_RZN1WDT is not set
+CONFIG_RENESAS_USB_DMAC=y
+# CONFIG_RENESAS_WDT is not set
+# CONFIG_RESET_BRCMSTB is not set
+CONFIG_RESET_IMX7=y
+# CONFIG_RESET_RASPBERRYPI is not set
+CONFIG_RESET_RZG2L_USBPHY_CTRL=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_IOMMU=y
+# CONFIG_ROCKCHIP_MBOX is not set
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_ROCKCHIP_SARADC is not set
+# CONFIG_ROCKCHIP_THERMAL is not set
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+# CONFIG_RTC_DRV_BBNSM is not set
+# CONFIG_RTC_DRV_BRCMSTB is not set
+# CONFIG_RTC_DRV_FSL_FTM_ALARM is not set
+# CONFIG_RTC_DRV_IMXDI is not set
+# CONFIG_RTC_DRV_IMX_SC is not set
+CONFIG_RTC_DRV_MV=y
+# CONFIG_RTC_DRV_MXC is not set
+# CONFIG_RTC_DRV_MXC_V2 is not set
+# CONFIG_RTC_DRV_SH is not set
+CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RZG2L_ADC is not set
+# CONFIG_RZG2L_THERMAL is not set
+CONFIG_RZ_DMAC=y
+CONFIG_RZ_MTU3=y
+CONFIG_SATA_SIL24=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+# CONFIG_SENSORS_ARM_SCPI is not set
+CONFIG_SERIAL_8250_BCM2835AUX=y
+CONFIG_SERIAL_8250_BCM7271=y
+# CONFIG_SERIAL_8250_EXAR is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_FSL_LINFLEXUART=y
+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_IMX_EARLYCON=y
+CONFIG_SERIAL_MVEBU_CONSOLE=y
+CONFIG_SERIAL_MVEBU_UART=y
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_SH_SCI_DMA=y
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=18
+# CONFIG_SMC91X is not set
+# CONFIG_SND_SOC_RCAR is not set
+# CONFIG_SND_SOC_RZ is not set
+# CONFIG_SND_SOC_SH4_FSI is not set
+# CONFIG_SND_SUN4I_I2S is not set
+# CONFIG_SND_SUN50I_CODEC_ANALOG is not set
+# CONFIG_SND_SUN50I_DMIC is not set
+# CONFIG_SND_SUN8I_CODEC is not set
+# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
+# CONFIG_SNI_NETSEC is not set
+CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
+CONFIG_SOC_IMX8M=y
+CONFIG_SOC_IMX9=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPI_ARMADA_3700=y
+# CONFIG_SPI_BCM2835 is not set
+CONFIG_SPI_FSL_LPSPI=y
+# CONFIG_SPI_FSL_QUADSPI is not set
+# CONFIG_SPI_HISI_KUNPENG is not set
+# CONFIG_SPI_HISI_SFC is not set
+# CONFIG_SPI_HISI_SFC_V3XX is not set
+CONFIG_SPI_IMX=y
+# CONFIG_SPI_ROCKCHIP_SFC is not set
+# CONFIG_SPI_RSPI is not set
+# CONFIG_SPI_RZV2M_CSI is not set
+# CONFIG_SPI_SH_HSPI is not set
+# CONFIG_SPI_SH_MSIOF is not set
+# CONFIG_SPI_SUN4I is not set
+# CONFIG_SPI_SUN6I is not set
+# CONFIG_SPI_SYNQUACER is not set
+CONFIG_SPI_THUNDERX=y
+# CONFIG_SPI_XLP is not set
+# CONFIG_SSIF_IPMI_BMC is not set
+CONFIG_STUB_CLK_HI3660=y
+CONFIG_STUB_CLK_HI6220=y
+# CONFIG_SUN20I_GPADC is not set
+# CONFIG_SUN20I_PPU is not set
+CONFIG_SUN50I_A100_CCU=y
+CONFIG_SUN50I_A100_R_CCU=y
+CONFIG_SUN50I_A64_CCU=y
+CONFIG_SUN50I_H616_CCU=y
+CONFIG_SUN50I_H6_CCU=y
+CONFIG_SUN50I_H6_R_CCU=y
+CONFIG_SUN50I_IOMMU=y
+CONFIG_SUN6I_MSGBOX=y
+CONFIG_SUN6I_RTC_CCU=y
+# CONFIG_SUN8I_A83T_CCU is not set
+CONFIG_SUN8I_DE2_CCU=y
+# CONFIG_SUN8I_H3_CCU is not set
+CONFIG_SUN8I_R_CCU=y
+CONFIG_SUN8I_THERMAL=y
+CONFIG_SUNXI_CCU=y
+CONFIG_SUNXI_RSB=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+# CONFIG_TCG_TIS_SYNQUACER is not set
+CONFIG_THREAD_INFO_IN_TASK=y
+# CONFIG_THUNDERX2_PMU is not set
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+# CONFIG_TURRIS_MOX_RWTM is not set
+CONFIG_TYPEC=y
+# CONFIG_TYPEC_ANX7411 is not set
+# CONFIG_TYPEC_DP_ALTMODE is not set
+# CONFIG_TYPEC_FUSB302 is not set
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_MUX_FSA4480 is not set
+# CONFIG_TYPEC_MUX_GPIO_SBU is not set
+# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# CONFIG_TYPEC_RT1711H is not set
+# CONFIG_TYPEC_RT1719 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+CONFIG_TYPEC_TCPCI=y
+# CONFIG_TYPEC_TCPCI_MAXIM is not set
+CONFIG_TYPEC_TCPM=y
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_TYPEC_WUSB3801 is not set
+# CONFIG_UACCE is not set
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+# CONFIG_USB_BRCMSTB is not set
+# CONFIG_USB_CDNS2_UDC is not set
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_GENERIC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_IMX=y
+CONFIG_USB_CHIPIDEA_PCI=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_DUAL_ROLE=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_DWC3_HAPS=y
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_IMX8MP=y
+# CONFIG_USB_DWC3_OF_SIMPLE is not set
+CONFIG_USB_DWC3_PCI=y
+# CONFIG_USB_DWC3_ULPI is not set
+CONFIG_USB_DWC3_XILINX=y
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_ORION=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_EMXX is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_OHCI_EXYNOS=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_RENESAS_USB3=y
+CONFIG_USB_RENESAS_USBF=y
+CONFIG_USB_RENESAS_USBHS=y
+CONFIG_USB_RENESAS_USBHS_HCD=y
+CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_USB_RZV2M_USB3DRD=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_HISTB=y
+CONFIG_USB_XHCI_MVEBU=y
+CONFIG_USB_XHCI_PLATFORM=y
+# CONFIG_USB_XHCI_RCAR is not set
+CONFIG_USB_XHCI_RZV2M=y
+CONFIG_VEXPRESS_CONFIG=y
+# CONFIG_VFIO_AMBA is not set
+CONFIG_VIDEOMODE_HELPERS=y
+# CONFIG_VIDEO_IMX7_CSI is not set
+# CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 is not set
+# CONFIG_VIDEO_IMX8_ISI is not set
+# CONFIG_VIDEO_RZG2L_CRU is not set
+# CONFIG_VIDEO_RZG2L_CSI2 is not set
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
+# CONFIG_VIRTIO_IOMMU is not set
+CONFIG_VIRTUALIZATION=y
+CONFIG_VMAP_STACK=y
+CONFIG_WDAT_WDT=y
+# CONFIG_XILINX_AMS is not set
+# CONFIG_XILINX_INTC is not set
+CONFIG_XLNX_EVENT_MANAGER=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZYNQMP_FIRMWARE=y
+# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
+CONFIG_ZYNQMP_PM_DOMAINS=y
+CONFIG_ZYNQMP_POWER=y
. /lib/functions/uci-defaults.sh
+KERNEL_MAJOR=$(uname -r | awk -F '.' '{print $1}')
+KERNEL_MINOR=$(uname -r | awk -F '.' '{print $2}')
+
board_config_update
board=$(board_name)
case "$board" in
traverse,ten64)
- ucidef_add_gpio_switch "lte_reset" "Cell Modem Reset" "376"
- ucidef_add_gpio_switch "lte_power" "Cell Modem Power" "377"
- ucidef_add_gpio_switch "lte_disable" "Cell Modem Airplane mode" "378"
- ucidef_add_gpio_switch "gnss_disable" "Cell Modem Disable GNSS receiver" "379"
- ucidef_add_gpio_switch "lower_sfp_txidsable" "Lower SFP+ TX Disable" "369"
- ucidef_add_gpio_switch "upper_sfp_txdisable" "Upper SFP+ TX Disable" "373"
+ if [ "${KERNEL_MAJOR}" -ge "6" ] && [ "${KERNEL_MINOR}" -ge "6" ]; then
+ I2C_GPIO_BASE=640
+ else
+ I2C_GPIO_BASE=368
+ fi
+ ucidef_add_gpio_switch "lte_reset" "Cell Modem Reset" "$(($I2C_GPIO_BASE + 8))"
+ ucidef_add_gpio_switch "lte_power" "Cell Modem Power" "$(($I2C_GPIO_BASE + 9))"
+ ucidef_add_gpio_switch "lte_disable" "Cell Modem Airplane mode" "$((I2C_GPIO_BASE + 10))"
+ ucidef_add_gpio_switch "gnss_disable" "Cell Modem Disable GNSS receiver" "$(($I2C_GPIO_BASE + 11))"
+ ucidef_add_gpio_switch "lower_sfp_txidsable" "Lower SFP+ TX Disable" "$(($I2C_GPIO_BASE + 1))"
+ ucidef_add_gpio_switch "upper_sfp_txdisable" "Upper SFP+ TX Disable" "$(($I2C_GPIO_BASE + 5))"
;;
esac
--- /dev/null
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This script migrates GPIO switch pin numbers
+# from kernel versions prior to 6.6
+# See https://lists.openwrt.org/pipermail/openwrt-devel/2024-March/042448.html
+
+. /lib/functions.sh
+
+ten64_update_gpioswitch_num() {
+ local section="$1"
+ config_get gpio_pin "${section}" gpio_pin
+ config_get gpio_name "${section}" name
+ if [ -z "${gpio_pin}" ]; then
+ return
+ fi
+ local this_pin_name=$(uci get "system.${section}.name")
+ if [ "${gpio_pin}" -lt 640 ]; then
+ new_pin_value=$(( $gpio_pin + 272 ))
+ uci set "system.${section}.gpio_pin=${new_pin_value}"
+ fi
+}
+
+board=$(board_name)
+if [ "${board}" != "traverse,ten64" ]; then
+ exit 0
+fi
+
+KERNEL_MINOR=$(uname -r | awk -F '.' '{print $2}')
+if [ "${KERNEL_MINOR}" -lt "6" ]; then
+ exit 0
+fi
+
+config_load system
+config_foreach ten64_update_gpioswitch_num gpio_switch
+
+exit 0
\ No newline at end of file
--- /dev/null
+CONFIG_64BIT=y
+CONFIG_9P_FS=y
+# CONFIG_9P_FS_POSIX_ACL is not set
+# CONFIG_9P_FS_SECURITY is not set
+# CONFIG_A64FX_DIAG is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_EINJ=y
+# CONFIG_ACPI_APEI_ERST_DEBUG is not set
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_PCIEAER=y
+CONFIG_ACPI_BATTERY=y
+# CONFIG_ACPI_BGRT is not set
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_CCA_REQUIRED=y
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_CPPC_CPUFREQ=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_GTDT=y
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_IORT=y
+CONFIG_ACPI_MCFG=y
+# CONFIG_ACPI_PCI_SLOT is not set
+# CONFIG_ACPI_PFRUT is not set
+CONFIG_ACPI_PPTT=y
+CONFIG_ACPI_PRMT=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_THERMAL=y
+# CONFIG_ACPI_TINY_POWER_BUTTON is not set
+# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_SMMU_V3_PMU is not set
+CONFIG_ATA=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMI=y
+CONFIG_DMIID=y
+CONFIG_DMI_SYSFS=y
+CONFIG_DTC=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=y
+CONFIG_EFI_ARMSTUB_DTB_LOADER=y
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_COCO_SECRET is not set
+# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+# CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER is not set
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_ZBOOT is not set
+CONFIG_EXT4_FS=y
+CONFIG_F2FS_FS=y
+CONFIG_FAILOVER=y
+CONFIG_FB_EFI=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_AUTOSELECT=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_CDEV=y
+# CONFIG_GPIO_HISI is not set
+CONFIG_GPIO_PL061=y
+# CONFIG_GPIO_VF610 is not set
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HZ_PERIODIC=y
+# CONFIG_I2C_AMD_MP2 is not set
+CONFIG_I2C_HID_ACPI=y
+# CONFIG_I2C_HISI is not set
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISCSI_IBFT is not set
+CONFIG_JBD2=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_BALLOON=y
+CONFIG_MIGRATION=y
+# CONFIG_MLXBF_GIGE is not set
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MVMDIO=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_9P=y
+# CONFIG_NET_9P_DEBUG is not set
+# CONFIG_NET_9P_FD is not set
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=256
+CONFIG_NVMEM=y
+CONFIG_NVME_CORE=y
+# CONFIG_NVME_MULTIPATH is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_PADATA=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+# CONFIG_PCIE_HISI_ERR is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RATIONAL=y
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_HOST=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI_VIRTIO=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SRCU=y
+# CONFIG_SURFACE_PLATFORMS is not set
+CONFIG_SWIOTLB=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFB=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_ACPI=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+# CONFIG_UACCE is not set
+CONFIG_UCS2_STRING=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB=y
+CONFIG_USB_HID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VMAP_STACK=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_ZONE_DMA32=y
CONFIG_FSL_ENETC_QOS=y
FILES:= \
$(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc.ko \
+ $(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-core.ko@ge6.3 \
$(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-vf.ko \
$(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-mdio.ko \
$(LINUX_DIR)/drivers/net/ethernet/freescale/enetc/fsl-enetc-ierb.ko
--- /dev/null
+From b77c0ecdc7915e5c5c515da1aa6cfaf6f4eb8351 Mon Sep 17 00:00:00 2001
+From: Mathew McBride <matt@traverse.com.au>
+Date: Wed, 28 Sep 2022 16:39:31 +1000
+Subject: [PATCH] arm: disable code size reduction measures
+ (gc-sections,-f*-sections)
+
+This interferes with the EFI boot stub on armv7l.
+
+Signed-off-by: Mathew McBride <matt@traverse.com.au>
+---
+ arch/arm/Kconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -128,7 +128,6 @@ config ARM
+ select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
+ select IRQ_FORCED_THREADING
+ select LOCK_MM_AND_FIND_VMA
+- select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
+ select MODULES_USE_ELF_REL
+ select NEED_DMA_MAP_STATE
+ select OF_EARLY_FLATTREE if OF
FEATURES:=ext4 squashfs targz usbgadget ubifs
SUBTARGETS:=sama7 sama5 sam9x
-KERNEL_PATCHVER:=5.15
+KERNEL_PATCHVER:=6.1
include $(INCLUDE_DIR)/target.mk
+++ /dev/null
-From 65bb4687b2a5c6f02f44345540c3389d6e7523e7 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:05 +0300
-Subject: [PATCH 234/247] clk: at91: re-factor clocks suspend/resume
-
-SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where
-most of the SoC's components are powered off (including PMC). Resuming
-from this mode is done with the help of bootloader. Peripherals are not
-aware of the power saving mode thus most of them are disabling clocks in
-proper suspend API and re-enable them in resume API without taking into
-account the previously setup rate. Moreover some of the peripherals are
-acting as wakeup sources and are not disabling the clocks in this
-scenario, when suspending. Since backup mode cuts the power for
-peripherals, in resume part these clocks needs to be re-configured.
-
-The initial PMC suspend/resume code was designed only for SAMA5D2's PMC
-(as it was the only one supporting backup mode). SAMA7G supports also
-backup mode and its PMC is different (few new functionalities, different
-registers offsets, different offsets in registers for each
-functionalities). To address both SAMA5D2 and SAMA7G5 PMC add
-.save_context()/.resume_context() support to each clocks driver and call
-this from PMC driver.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-generated.c | 46 +++++--
- drivers/clk/at91/clk-main.c | 66 ++++++++++
- drivers/clk/at91/clk-master.c | 194 ++++++++++++++++++++++++++--
- drivers/clk/at91/clk-peripheral.c | 40 +++++-
- drivers/clk/at91/clk-pll.c | 39 ++++++
- drivers/clk/at91/clk-programmable.c | 29 ++++-
- drivers/clk/at91/clk-sam9x60-pll.c | 68 +++++++++-
- drivers/clk/at91/clk-system.c | 20 +++
- drivers/clk/at91/clk-usb.c | 27 ++++
- drivers/clk/at91/clk-utmi.c | 39 ++++++
- drivers/clk/at91/pmc.c | 147 +--------------------
- drivers/clk/at91/pmc.h | 24 ++--
- 12 files changed, 558 insertions(+), 181 deletions(-)
-
---- a/drivers/clk/at91/clk-generated.c
-+++ b/drivers/clk/at91/clk-generated.c
-@@ -27,6 +27,7 @@ struct clk_generated {
- u32 id;
- u32 gckdiv;
- const struct clk_pcr_layout *layout;
-+ struct at91_clk_pms pms;
- u8 parent_id;
- int chg_pid;
- };
-@@ -34,25 +35,35 @@ struct clk_generated {
- #define to_clk_generated(hw) \
- container_of(hw, struct clk_generated, hw)
-
--static int clk_generated_enable(struct clk_hw *hw)
-+static int clk_generated_set(struct clk_generated *gck, int status)
- {
-- struct clk_generated *gck = to_clk_generated(hw);
- unsigned long flags;
--
-- pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
-- __func__, gck->gckdiv, gck->parent_id);
-+ unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0;
-
- spin_lock_irqsave(gck->lock, flags);
- regmap_write(gck->regmap, gck->layout->offset,
- (gck->id & gck->layout->pid_mask));
- regmap_update_bits(gck->regmap, gck->layout->offset,
- AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
-- gck->layout->cmd | AT91_PMC_PCR_GCKEN,
-+ gck->layout->cmd | enable,
- field_prep(gck->layout->gckcss_mask, gck->parent_id) |
- gck->layout->cmd |
- FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
-- AT91_PMC_PCR_GCKEN);
-+ enable);
- spin_unlock_irqrestore(gck->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int clk_generated_enable(struct clk_hw *hw)
-+{
-+ struct clk_generated *gck = to_clk_generated(hw);
-+
-+ pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
-+ __func__, gck->gckdiv, gck->parent_id);
-+
-+ clk_generated_set(gck, 1);
-+
- return 0;
- }
-
-@@ -249,6 +260,23 @@ static int clk_generated_set_rate(struct
- return 0;
- }
-
-+static int clk_generated_save_context(struct clk_hw *hw)
-+{
-+ struct clk_generated *gck = to_clk_generated(hw);
-+
-+ gck->pms.status = clk_generated_is_enabled(&gck->hw);
-+
-+ return 0;
-+}
-+
-+static void clk_generated_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_generated *gck = to_clk_generated(hw);
-+
-+ if (gck->pms.status)
-+ clk_generated_set(gck, gck->pms.status);
-+}
-+
- static const struct clk_ops generated_ops = {
- .enable = clk_generated_enable,
- .disable = clk_generated_disable,
-@@ -258,6 +286,8 @@ static const struct clk_ops generated_op
- .get_parent = clk_generated_get_parent,
- .set_parent = clk_generated_set_parent,
- .set_rate = clk_generated_set_rate,
-+ .save_context = clk_generated_save_context,
-+ .restore_context = clk_generated_restore_context,
- };
-
- /**
-@@ -324,8 +354,6 @@ at91_clk_register_generated(struct regma
- if (ret) {
- kfree(gck);
- hw = ERR_PTR(ret);
-- } else {
-- pmc_register_id(id);
- }
-
- return hw;
---- a/drivers/clk/at91/clk-main.c
-+++ b/drivers/clk/at91/clk-main.c
-@@ -28,6 +28,7 @@
- struct clk_main_osc {
- struct clk_hw hw;
- struct regmap *regmap;
-+ struct at91_clk_pms pms;
- };
-
- #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
-@@ -37,6 +38,7 @@ struct clk_main_rc_osc {
- struct regmap *regmap;
- unsigned long frequency;
- unsigned long accuracy;
-+ struct at91_clk_pms pms;
- };
-
- #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
-@@ -51,6 +53,7 @@ struct clk_rm9200_main {
- struct clk_sam9x5_main {
- struct clk_hw hw;
- struct regmap *regmap;
-+ struct at91_clk_pms pms;
- u8 parent;
- };
-
-@@ -120,10 +123,29 @@ static int clk_main_osc_is_prepared(stru
- return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
- }
-
-+static int clk_main_osc_save_context(struct clk_hw *hw)
-+{
-+ struct clk_main_osc *osc = to_clk_main_osc(hw);
-+
-+ osc->pms.status = clk_main_osc_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_main_osc_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_main_osc *osc = to_clk_main_osc(hw);
-+
-+ if (osc->pms.status)
-+ clk_main_osc_prepare(hw);
-+}
-+
- static const struct clk_ops main_osc_ops = {
- .prepare = clk_main_osc_prepare,
- .unprepare = clk_main_osc_unprepare,
- .is_prepared = clk_main_osc_is_prepared,
-+ .save_context = clk_main_osc_save_context,
-+ .restore_context = clk_main_osc_restore_context,
- };
-
- struct clk_hw * __init
-@@ -240,12 +262,31 @@ static unsigned long clk_main_rc_osc_rec
- return osc->accuracy;
- }
-
-+static int clk_main_rc_osc_save_context(struct clk_hw *hw)
-+{
-+ struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
-+
-+ osc->pms.status = clk_main_rc_osc_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_main_rc_osc_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
-+
-+ if (osc->pms.status)
-+ clk_main_rc_osc_prepare(hw);
-+}
-+
- static const struct clk_ops main_rc_osc_ops = {
- .prepare = clk_main_rc_osc_prepare,
- .unprepare = clk_main_rc_osc_unprepare,
- .is_prepared = clk_main_rc_osc_is_prepared,
- .recalc_rate = clk_main_rc_osc_recalc_rate,
- .recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
-+ .save_context = clk_main_rc_osc_save_context,
-+ .restore_context = clk_main_rc_osc_restore_context,
- };
-
- struct clk_hw * __init
-@@ -465,12 +506,37 @@ static u8 clk_sam9x5_main_get_parent(str
- return clk_main_parent_select(status);
- }
-
-+static int clk_sam9x5_main_save_context(struct clk_hw *hw)
-+{
-+ struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
-+
-+ clkmain->pms.status = clk_main_rc_osc_is_prepared(&clkmain->hw);
-+ clkmain->pms.parent = clk_sam9x5_main_get_parent(&clkmain->hw);
-+
-+ return 0;
-+}
-+
-+static void clk_sam9x5_main_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
-+ int ret;
-+
-+ ret = clk_sam9x5_main_set_parent(hw, clkmain->pms.parent);
-+ if (ret)
-+ return;
-+
-+ if (clkmain->pms.status)
-+ clk_sam9x5_main_prepare(hw);
-+}
-+
- static const struct clk_ops sam9x5_main_ops = {
- .prepare = clk_sam9x5_main_prepare,
- .is_prepared = clk_sam9x5_main_is_prepared,
- .recalc_rate = clk_sam9x5_main_recalc_rate,
- .set_parent = clk_sam9x5_main_set_parent,
- .get_parent = clk_sam9x5_main_get_parent,
-+ .save_context = clk_sam9x5_main_save_context,
-+ .restore_context = clk_sam9x5_main_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -37,6 +37,7 @@ struct clk_master {
- spinlock_t *lock;
- const struct clk_master_layout *layout;
- const struct clk_master_characteristics *characteristics;
-+ struct at91_clk_pms pms;
- u32 *mux_table;
- u32 mckr;
- int chg_pid;
-@@ -112,10 +113,52 @@ static unsigned long clk_master_div_reca
- return rate;
- }
-
-+static int clk_master_div_save_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+ unsigned long flags;
-+ unsigned int mckr, div;
-+
-+ spin_lock_irqsave(master->lock, flags);
-+ regmap_read(master->regmap, master->layout->offset, &mckr);
-+ spin_unlock_irqrestore(master->lock, flags);
-+
-+ mckr &= master->layout->mask;
-+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ div = master->characteristics->divisors[div];
-+
-+ master->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+ master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div);
-+
-+ return 0;
-+}
-+
-+static void clk_master_div_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+ unsigned long flags;
-+ unsigned int mckr;
-+ u8 div;
-+
-+ spin_lock_irqsave(master->lock, flags);
-+ regmap_read(master->regmap, master->layout->offset, &mckr);
-+ spin_unlock_irqrestore(master->lock, flags);
-+
-+ mckr &= master->layout->mask;
-+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ div = master->characteristics->divisors[div];
-+
-+ if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate))
-+ pr_warn("MCKR DIV not configured properly by firmware!\n");
-+}
-+
- static const struct clk_ops master_div_ops = {
- .prepare = clk_master_prepare,
- .is_prepared = clk_master_is_prepared,
- .recalc_rate = clk_master_div_recalc_rate,
-+ .save_context = clk_master_div_save_context,
-+ .restore_context = clk_master_div_restore_context,
- };
-
- static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,
-@@ -125,7 +168,9 @@ static int clk_master_div_set_rate(struc
- const struct clk_master_characteristics *characteristics =
- master->characteristics;
- unsigned long flags;
-+ unsigned int mckr, tmp;
- int div, i;
-+ int ret;
-
- div = DIV_ROUND_CLOSEST(parent_rate, rate);
- if (div > ARRAY_SIZE(characteristics->divisors))
-@@ -145,11 +190,24 @@ static int clk_master_div_set_rate(struc
- return -EINVAL;
-
- spin_lock_irqsave(master->lock, flags);
-- regmap_update_bits(master->regmap, master->layout->offset,
-- (MASTER_DIV_MASK << MASTER_DIV_SHIFT),
-- (div << MASTER_DIV_SHIFT));
-+ ret = regmap_read(master->regmap, master->layout->offset, &mckr);
-+ if (ret)
-+ goto unlock;
-+
-+ tmp = mckr & master->layout->mask;
-+ tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ if (tmp == div)
-+ goto unlock;
-+
-+ mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT);
-+ mckr |= (div << MASTER_DIV_SHIFT);
-+ ret = regmap_write(master->regmap, master->layout->offset, mckr);
-+ if (ret)
-+ goto unlock;
-+
- while (!clk_master_ready(master))
- cpu_relax();
-+unlock:
- spin_unlock_irqrestore(master->lock, flags);
-
- return 0;
-@@ -197,12 +255,25 @@ static int clk_master_div_determine_rate
- return 0;
- }
-
-+static void clk_master_div_restore_context_chg(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+ int ret;
-+
-+ ret = clk_master_div_set_rate(hw, master->pms.rate,
-+ master->pms.parent_rate);
-+ if (ret)
-+ pr_warn("Failed to restore MCK DIV clock\n");
-+}
-+
- static const struct clk_ops master_div_ops_chg = {
- .prepare = clk_master_prepare,
- .is_prepared = clk_master_is_prepared,
- .recalc_rate = clk_master_div_recalc_rate,
- .determine_rate = clk_master_div_determine_rate,
- .set_rate = clk_master_div_set_rate,
-+ .save_context = clk_master_div_save_context,
-+ .restore_context = clk_master_div_restore_context_chg,
- };
-
- static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
-@@ -272,7 +343,8 @@ static int clk_master_pres_set_rate(stru
- {
- struct clk_master *master = to_clk_master(hw);
- unsigned long flags;
-- unsigned int pres;
-+ unsigned int pres, mckr, tmp;
-+ int ret;
-
- pres = DIV_ROUND_CLOSEST(parent_rate, rate);
- if (pres > MASTER_PRES_MAX)
-@@ -284,15 +356,27 @@ static int clk_master_pres_set_rate(stru
- pres = ffs(pres) - 1;
-
- spin_lock_irqsave(master->lock, flags);
-- regmap_update_bits(master->regmap, master->layout->offset,
-- (MASTER_PRES_MASK << master->layout->pres_shift),
-- (pres << master->layout->pres_shift));
-+ ret = regmap_read(master->regmap, master->layout->offset, &mckr);
-+ if (ret)
-+ goto unlock;
-+
-+ mckr &= master->layout->mask;
-+ tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK;
-+ if (pres == tmp)
-+ goto unlock;
-+
-+ mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift);
-+ mckr |= (pres << master->layout->pres_shift);
-+ ret = regmap_write(master->regmap, master->layout->offset, mckr);
-+ if (ret)
-+ goto unlock;
-
- while (!clk_master_ready(master))
- cpu_relax();
-+unlock:
- spin_unlock_irqrestore(master->lock, flags);
-
-- return 0;
-+ return ret;
- }
-
- static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
-@@ -330,11 +414,68 @@ static u8 clk_master_pres_get_parent(str
- return mckr & AT91_PMC_CSS;
- }
-
-+static int clk_master_pres_save_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+ unsigned long flags;
-+ unsigned int val, pres;
-+
-+ spin_lock_irqsave(master->lock, flags);
-+ regmap_read(master->regmap, master->layout->offset, &val);
-+ spin_unlock_irqrestore(master->lock, flags);
-+
-+ val &= master->layout->mask;
-+ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
-+ if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)
-+ pres = 3;
-+ else
-+ pres = (1 << pres);
-+
-+ master->pms.parent = val & AT91_PMC_CSS;
-+ master->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+ master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres);
-+
-+ return 0;
-+}
-+
-+static void clk_master_pres_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+ unsigned long flags;
-+ unsigned int val, pres;
-+
-+ spin_lock_irqsave(master->lock, flags);
-+ regmap_read(master->regmap, master->layout->offset, &val);
-+ spin_unlock_irqrestore(master->lock, flags);
-+
-+ val &= master->layout->mask;
-+ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
-+ if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)
-+ pres = 3;
-+ else
-+ pres = (1 << pres);
-+
-+ if (master->pms.rate !=
-+ DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) ||
-+ (master->pms.parent != (val & AT91_PMC_CSS)))
-+ pr_warn("MCKR PRES was not configured properly by firmware!\n");
-+}
-+
-+static void clk_master_pres_restore_context_chg(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+
-+ clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate);
-+}
-+
- static const struct clk_ops master_pres_ops = {
- .prepare = clk_master_prepare,
- .is_prepared = clk_master_is_prepared,
- .recalc_rate = clk_master_pres_recalc_rate,
- .get_parent = clk_master_pres_get_parent,
-+ .save_context = clk_master_pres_save_context,
-+ .restore_context = clk_master_pres_restore_context,
- };
-
- static const struct clk_ops master_pres_ops_chg = {
-@@ -344,6 +485,8 @@ static const struct clk_ops master_pres_
- .recalc_rate = clk_master_pres_recalc_rate,
- .get_parent = clk_master_pres_get_parent,
- .set_rate = clk_master_pres_set_rate,
-+ .save_context = clk_master_pres_save_context,
-+ .restore_context = clk_master_pres_restore_context_chg,
- };
-
- static struct clk_hw * __init
-@@ -539,20 +682,21 @@ static int clk_sama7g5_master_set_parent
- return 0;
- }
-
--static int clk_sama7g5_master_enable(struct clk_hw *hw)
-+static void clk_sama7g5_master_set(struct clk_master *master,
-+ unsigned int status)
- {
-- struct clk_master *master = to_clk_master(hw);
- unsigned long flags;
- unsigned int val, cparent;
-+ unsigned int enable = status ? PMC_MCR_EN : 0;
-
- spin_lock_irqsave(master->lock, flags);
-
- regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));
- regmap_read(master->regmap, PMC_MCR, &val);
- regmap_update_bits(master->regmap, PMC_MCR,
-- PMC_MCR_EN | PMC_MCR_CSS | PMC_MCR_DIV |
-+ enable | PMC_MCR_CSS | PMC_MCR_DIV |
- PMC_MCR_CMD | PMC_MCR_ID_MSK,
-- PMC_MCR_EN | (master->parent << PMC_MCR_CSS_SHIFT) |
-+ enable | (master->parent << PMC_MCR_CSS_SHIFT) |
- (master->div << MASTER_DIV_SHIFT) |
- PMC_MCR_CMD | PMC_MCR_ID(master->id));
-
-@@ -563,6 +707,13 @@ static int clk_sama7g5_master_enable(str
- cpu_relax();
-
- spin_unlock_irqrestore(master->lock, flags);
-+}
-+
-+static int clk_sama7g5_master_enable(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+
-+ clk_sama7g5_master_set(master, 1);
-
- return 0;
- }
-@@ -620,6 +771,23 @@ static int clk_sama7g5_master_set_rate(s
- return 0;
- }
-
-+static int clk_sama7g5_master_save_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+
-+ master->pms.status = clk_sama7g5_master_is_enabled(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_sama7g5_master_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+
-+ if (master->pms.status)
-+ clk_sama7g5_master_set(master, master->pms.status);
-+}
-+
- static const struct clk_ops sama7g5_master_ops = {
- .enable = clk_sama7g5_master_enable,
- .disable = clk_sama7g5_master_disable,
-@@ -629,6 +797,8 @@ static const struct clk_ops sama7g5_mast
- .set_rate = clk_sama7g5_master_set_rate,
- .get_parent = clk_sama7g5_master_get_parent,
- .set_parent = clk_sama7g5_master_set_parent,
-+ .save_context = clk_sama7g5_master_save_context,
-+ .restore_context = clk_sama7g5_master_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-peripheral.c
-+++ b/drivers/clk/at91/clk-peripheral.c
-@@ -37,6 +37,7 @@ struct clk_sam9x5_peripheral {
- u32 id;
- u32 div;
- const struct clk_pcr_layout *layout;
-+ struct at91_clk_pms pms;
- bool auto_div;
- int chg_pid;
- };
-@@ -155,10 +156,11 @@ static void clk_sam9x5_peripheral_autodi
- periph->div = shift;
- }
-
--static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
-+static int clk_sam9x5_peripheral_set(struct clk_sam9x5_peripheral *periph,
-+ unsigned int status)
- {
-- struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
- unsigned long flags;
-+ unsigned int enable = status ? AT91_PMC_PCR_EN : 0;
-
- if (periph->id < PERIPHERAL_ID_MIN)
- return 0;
-@@ -168,15 +170,21 @@ static int clk_sam9x5_peripheral_enable(
- (periph->id & periph->layout->pid_mask));
- regmap_update_bits(periph->regmap, periph->layout->offset,
- periph->layout->div_mask | periph->layout->cmd |
-- AT91_PMC_PCR_EN,
-+ enable,
- field_prep(periph->layout->div_mask, periph->div) |
-- periph->layout->cmd |
-- AT91_PMC_PCR_EN);
-+ periph->layout->cmd | enable);
- spin_unlock_irqrestore(periph->lock, flags);
-
- return 0;
- }
-
-+static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
-+{
-+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-+
-+ return clk_sam9x5_peripheral_set(periph, 1);
-+}
-+
- static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
- {
- struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-@@ -393,6 +401,23 @@ static int clk_sam9x5_peripheral_set_rat
- return -EINVAL;
- }
-
-+static int clk_sam9x5_peripheral_save_context(struct clk_hw *hw)
-+{
-+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-+
-+ periph->pms.status = clk_sam9x5_peripheral_is_enabled(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_sam9x5_peripheral_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-+
-+ if (periph->pms.status)
-+ clk_sam9x5_peripheral_set(periph, periph->pms.status);
-+}
-+
- static const struct clk_ops sam9x5_peripheral_ops = {
- .enable = clk_sam9x5_peripheral_enable,
- .disable = clk_sam9x5_peripheral_disable,
-@@ -400,6 +425,8 @@ static const struct clk_ops sam9x5_perip
- .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
- .round_rate = clk_sam9x5_peripheral_round_rate,
- .set_rate = clk_sam9x5_peripheral_set_rate,
-+ .save_context = clk_sam9x5_peripheral_save_context,
-+ .restore_context = clk_sam9x5_peripheral_restore_context,
- };
-
- static const struct clk_ops sam9x5_peripheral_chg_ops = {
-@@ -409,6 +436,8 @@ static const struct clk_ops sam9x5_perip
- .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
- .determine_rate = clk_sam9x5_peripheral_determine_rate,
- .set_rate = clk_sam9x5_peripheral_set_rate,
-+ .save_context = clk_sam9x5_peripheral_save_context,
-+ .restore_context = clk_sam9x5_peripheral_restore_context,
- };
-
- struct clk_hw * __init
-@@ -460,7 +489,6 @@ at91_clk_register_sam9x5_peripheral(stru
- hw = ERR_PTR(ret);
- } else {
- clk_sam9x5_peripheral_autodiv(periph);
-- pmc_register_id(id);
- }
-
- return hw;
---- a/drivers/clk/at91/clk-pll.c
-+++ b/drivers/clk/at91/clk-pll.c
-@@ -40,6 +40,7 @@ struct clk_pll {
- u16 mul;
- const struct clk_pll_layout *layout;
- const struct clk_pll_characteristics *characteristics;
-+ struct at91_clk_pms pms;
- };
-
- static inline bool clk_pll_ready(struct regmap *regmap, int id)
-@@ -260,6 +261,42 @@ static int clk_pll_set_rate(struct clk_h
- return 0;
- }
-
-+static int clk_pll_save_context(struct clk_hw *hw)
-+{
-+ struct clk_pll *pll = to_clk_pll(hw);
-+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+
-+ pll->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+ pll->pms.rate = clk_pll_recalc_rate(&pll->hw, pll->pms.parent_rate);
-+ pll->pms.status = clk_pll_ready(pll->regmap, PLL_REG(pll->id));
-+
-+ return 0;
-+}
-+
-+static void clk_pll_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_pll *pll = to_clk_pll(hw);
-+ unsigned long calc_rate;
-+ unsigned int pllr, pllr_out, pllr_count;
-+ u8 out = 0;
-+
-+ if (pll->characteristics->out)
-+ out = pll->characteristics->out[pll->range];
-+
-+ regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
-+
-+ calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) *
-+ (PLL_MUL(pllr, pll->layout) + 1);
-+ pllr_count = (pllr >> PLL_COUNT_SHIFT) & PLL_MAX_COUNT;
-+ pllr_out = (pllr >> PLL_OUT_SHIFT) & out;
-+
-+ if (pll->pms.rate != calc_rate ||
-+ pll->pms.status != clk_pll_ready(pll->regmap, PLL_REG(pll->id)) ||
-+ pllr_count != PLL_MAX_COUNT ||
-+ (out && pllr_out != out))
-+ pr_warn("PLLAR was not configured properly by firmware\n");
-+}
-+
- static const struct clk_ops pll_ops = {
- .prepare = clk_pll_prepare,
- .unprepare = clk_pll_unprepare,
-@@ -267,6 +304,8 @@ static const struct clk_ops pll_ops = {
- .recalc_rate = clk_pll_recalc_rate,
- .round_rate = clk_pll_round_rate,
- .set_rate = clk_pll_set_rate,
-+ .save_context = clk_pll_save_context,
-+ .restore_context = clk_pll_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-programmable.c
-+++ b/drivers/clk/at91/clk-programmable.c
-@@ -24,6 +24,7 @@ struct clk_programmable {
- u32 *mux_table;
- u8 id;
- const struct clk_programmable_layout *layout;
-+ struct at91_clk_pms pms;
- };
-
- #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
-@@ -177,12 +178,38 @@ static int clk_programmable_set_rate(str
- return 0;
- }
-
-+static int clk_programmable_save_context(struct clk_hw *hw)
-+{
-+ struct clk_programmable *prog = to_clk_programmable(hw);
-+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+
-+ prog->pms.parent = clk_programmable_get_parent(hw);
-+ prog->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+ prog->pms.rate = clk_programmable_recalc_rate(hw, prog->pms.parent_rate);
-+
-+ return 0;
-+}
-+
-+static void clk_programmable_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_programmable *prog = to_clk_programmable(hw);
-+ int ret;
-+
-+ ret = clk_programmable_set_parent(hw, prog->pms.parent);
-+ if (ret)
-+ return;
-+
-+ clk_programmable_set_rate(hw, prog->pms.rate, prog->pms.parent_rate);
-+}
-+
- static const struct clk_ops programmable_ops = {
- .recalc_rate = clk_programmable_recalc_rate,
- .determine_rate = clk_programmable_determine_rate,
- .get_parent = clk_programmable_get_parent,
- .set_parent = clk_programmable_set_parent,
- .set_rate = clk_programmable_set_rate,
-+ .save_context = clk_programmable_save_context,
-+ .restore_context = clk_programmable_restore_context,
- };
-
- struct clk_hw * __init
-@@ -221,8 +248,6 @@ at91_clk_register_programmable(struct re
- if (ret) {
- kfree(prog);
- hw = ERR_PTR(ret);
-- } else {
-- pmc_register_pck(id);
- }
-
- return hw;
---- a/drivers/clk/at91/clk-sam9x60-pll.c
-+++ b/drivers/clk/at91/clk-sam9x60-pll.c
-@@ -38,12 +38,14 @@ struct sam9x60_pll_core {
-
- struct sam9x60_frac {
- struct sam9x60_pll_core core;
-+ struct at91_clk_pms pms;
- u32 frac;
- u16 mul;
- };
-
- struct sam9x60_div {
- struct sam9x60_pll_core core;
-+ struct at91_clk_pms pms;
- u8 div;
- };
-
-@@ -75,9 +77,8 @@ static unsigned long sam9x60_frac_pll_re
- DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
- }
-
--static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
-+static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
- {
-- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
- struct sam9x60_frac *frac = to_sam9x60_frac(core);
- struct regmap *regmap = core->regmap;
- unsigned int val, cfrac, cmul;
-@@ -141,6 +142,13 @@ unlock:
- return 0;
- }
-
-+static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+
-+ return sam9x60_frac_pll_set(core);
-+}
-+
- static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
- {
- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-@@ -280,6 +288,25 @@ unlock:
- return ret;
- }
-
-+static int sam9x60_frac_pll_save_context(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+ struct sam9x60_frac *frac = to_sam9x60_frac(core);
-+
-+ frac->pms.status = sam9x60_pll_ready(core->regmap, core->id);
-+
-+ return 0;
-+}
-+
-+static void sam9x60_frac_pll_restore_context(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+ struct sam9x60_frac *frac = to_sam9x60_frac(core);
-+
-+ if (frac->pms.status)
-+ sam9x60_frac_pll_set(core);
-+}
-+
- static const struct clk_ops sam9x60_frac_pll_ops = {
- .prepare = sam9x60_frac_pll_prepare,
- .unprepare = sam9x60_frac_pll_unprepare,
-@@ -287,6 +314,8 @@ static const struct clk_ops sam9x60_frac
- .recalc_rate = sam9x60_frac_pll_recalc_rate,
- .round_rate = sam9x60_frac_pll_round_rate,
- .set_rate = sam9x60_frac_pll_set_rate,
-+ .save_context = sam9x60_frac_pll_save_context,
-+ .restore_context = sam9x60_frac_pll_restore_context,
- };
-
- static const struct clk_ops sam9x60_frac_pll_ops_chg = {
-@@ -296,11 +325,12 @@ static const struct clk_ops sam9x60_frac
- .recalc_rate = sam9x60_frac_pll_recalc_rate,
- .round_rate = sam9x60_frac_pll_round_rate,
- .set_rate = sam9x60_frac_pll_set_rate_chg,
-+ .save_context = sam9x60_frac_pll_save_context,
-+ .restore_context = sam9x60_frac_pll_restore_context,
- };
-
--static int sam9x60_div_pll_prepare(struct clk_hw *hw)
-+static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
- {
-- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
- struct sam9x60_div *div = to_sam9x60_div(core);
- struct regmap *regmap = core->regmap;
- unsigned long flags;
-@@ -334,6 +364,13 @@ unlock:
- return 0;
- }
-
-+static int sam9x60_div_pll_prepare(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+
-+ return sam9x60_div_pll_set(core);
-+}
-+
- static void sam9x60_div_pll_unprepare(struct clk_hw *hw)
- {
- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-@@ -482,6 +519,25 @@ unlock:
- return 0;
- }
-
-+static int sam9x60_div_pll_save_context(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+ struct sam9x60_div *div = to_sam9x60_div(core);
-+
-+ div->pms.status = sam9x60_div_pll_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void sam9x60_div_pll_restore_context(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+ struct sam9x60_div *div = to_sam9x60_div(core);
-+
-+ if (div->pms.status)
-+ sam9x60_div_pll_set(core);
-+}
-+
- static const struct clk_ops sam9x60_div_pll_ops = {
- .prepare = sam9x60_div_pll_prepare,
- .unprepare = sam9x60_div_pll_unprepare,
-@@ -489,6 +545,8 @@ static const struct clk_ops sam9x60_div_
- .recalc_rate = sam9x60_div_pll_recalc_rate,
- .round_rate = sam9x60_div_pll_round_rate,
- .set_rate = sam9x60_div_pll_set_rate,
-+ .save_context = sam9x60_div_pll_save_context,
-+ .restore_context = sam9x60_div_pll_restore_context,
- };
-
- static const struct clk_ops sam9x60_div_pll_ops_chg = {
-@@ -498,6 +556,8 @@ static const struct clk_ops sam9x60_div_
- .recalc_rate = sam9x60_div_pll_recalc_rate,
- .round_rate = sam9x60_div_pll_round_rate,
- .set_rate = sam9x60_div_pll_set_rate_chg,
-+ .save_context = sam9x60_div_pll_save_context,
-+ .restore_context = sam9x60_div_pll_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-system.c
-+++ b/drivers/clk/at91/clk-system.c
-@@ -20,6 +20,7 @@
- struct clk_system {
- struct clk_hw hw;
- struct regmap *regmap;
-+ struct at91_clk_pms pms;
- u8 id;
- };
-
-@@ -77,10 +78,29 @@ static int clk_system_is_prepared(struct
- return !!(status & (1 << sys->id));
- }
-
-+static int clk_system_save_context(struct clk_hw *hw)
-+{
-+ struct clk_system *sys = to_clk_system(hw);
-+
-+ sys->pms.status = clk_system_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_system_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_system *sys = to_clk_system(hw);
-+
-+ if (sys->pms.status)
-+ clk_system_prepare(&sys->hw);
-+}
-+
- static const struct clk_ops system_ops = {
- .prepare = clk_system_prepare,
- .unprepare = clk_system_unprepare,
- .is_prepared = clk_system_is_prepared,
-+ .save_context = clk_system_save_context,
-+ .restore_context = clk_system_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-usb.c
-+++ b/drivers/clk/at91/clk-usb.c
-@@ -24,6 +24,7 @@
- struct at91sam9x5_clk_usb {
- struct clk_hw hw;
- struct regmap *regmap;
-+ struct at91_clk_pms pms;
- u32 usbs_mask;
- u8 num_parents;
- };
-@@ -148,12 +149,38 @@ static int at91sam9x5_clk_usb_set_rate(s
- return 0;
- }
-
-+static int at91sam9x5_usb_save_context(struct clk_hw *hw)
-+{
-+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
-+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+
-+ usb->pms.parent = at91sam9x5_clk_usb_get_parent(hw);
-+ usb->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+ usb->pms.rate = at91sam9x5_clk_usb_recalc_rate(hw, usb->pms.parent_rate);
-+
-+ return 0;
-+}
-+
-+static void at91sam9x5_usb_restore_context(struct clk_hw *hw)
-+{
-+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
-+ int ret;
-+
-+ ret = at91sam9x5_clk_usb_set_parent(hw, usb->pms.parent);
-+ if (ret)
-+ return;
-+
-+ at91sam9x5_clk_usb_set_rate(hw, usb->pms.rate, usb->pms.parent_rate);
-+}
-+
- static const struct clk_ops at91sam9x5_usb_ops = {
- .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
- .determine_rate = at91sam9x5_clk_usb_determine_rate,
- .get_parent = at91sam9x5_clk_usb_get_parent,
- .set_parent = at91sam9x5_clk_usb_set_parent,
- .set_rate = at91sam9x5_clk_usb_set_rate,
-+ .save_context = at91sam9x5_usb_save_context,
-+ .restore_context = at91sam9x5_usb_restore_context,
- };
-
- static int at91sam9n12_clk_usb_enable(struct clk_hw *hw)
---- a/drivers/clk/at91/clk-utmi.c
-+++ b/drivers/clk/at91/clk-utmi.c
-@@ -23,6 +23,7 @@ struct clk_utmi {
- struct clk_hw hw;
- struct regmap *regmap_pmc;
- struct regmap *regmap_sfr;
-+ struct at91_clk_pms pms;
- };
-
- #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
-@@ -113,11 +114,30 @@ static unsigned long clk_utmi_recalc_rat
- return UTMI_RATE;
- }
-
-+static int clk_utmi_save_context(struct clk_hw *hw)
-+{
-+ struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+ utmi->pms.status = clk_utmi_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_utmi_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+ if (utmi->pms.status)
-+ clk_utmi_prepare(hw);
-+}
-+
- static const struct clk_ops utmi_ops = {
- .prepare = clk_utmi_prepare,
- .unprepare = clk_utmi_unprepare,
- .is_prepared = clk_utmi_is_prepared,
- .recalc_rate = clk_utmi_recalc_rate,
-+ .save_context = clk_utmi_save_context,
-+ .restore_context = clk_utmi_restore_context,
- };
-
- static struct clk_hw * __init
-@@ -232,10 +252,29 @@ static int clk_utmi_sama7g5_is_prepared(
- return 0;
- }
-
-+static int clk_utmi_sama7g5_save_context(struct clk_hw *hw)
-+{
-+ struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+ utmi->pms.status = clk_utmi_sama7g5_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+ if (utmi->pms.status)
-+ clk_utmi_sama7g5_prepare(hw);
-+}
-+
- static const struct clk_ops sama7g5_utmi_ops = {
- .prepare = clk_utmi_sama7g5_prepare,
- .is_prepared = clk_utmi_sama7g5_is_prepared,
- .recalc_rate = clk_utmi_recalc_rate,
-+ .save_context = clk_utmi_sama7g5_save_context,
-+ .restore_context = clk_utmi_sama7g5_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/pmc.c
-+++ b/drivers/clk/at91/pmc.c
-@@ -3,6 +3,7 @@
- * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- */
-
-+#include <linux/clk.h>
- #include <linux/clk-provider.h>
- #include <linux/clkdev.h>
- #include <linux/clk/at91_pmc.h>
-@@ -14,8 +15,6 @@
-
- #include <asm/proc-fns.h>
-
--#include <dt-bindings/clock/at91.h>
--
- #include "pmc.h"
-
- #define PMC_MAX_IDS 128
-@@ -111,147 +110,19 @@ struct pmc_data *pmc_data_allocate(unsig
- }
-
- #ifdef CONFIG_PM
--static struct regmap *pmcreg;
--
--static u8 registered_ids[PMC_MAX_IDS];
--static u8 registered_pcks[PMC_MAX_PCKS];
--
--static struct
--{
-- u32 scsr;
-- u32 pcsr0;
-- u32 uckr;
-- u32 mor;
-- u32 mcfr;
-- u32 pllar;
-- u32 mckr;
-- u32 usb;
-- u32 imr;
-- u32 pcsr1;
-- u32 pcr[PMC_MAX_IDS];
-- u32 audio_pll0;
-- u32 audio_pll1;
-- u32 pckr[PMC_MAX_PCKS];
--} pmc_cache;
--
--/*
-- * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored
-- * without alteration in the table, and 0 is for unused clocks.
-- */
--void pmc_register_id(u8 id)
-+static int at91_pmc_suspend(void)
- {
-- int i;
--
-- for (i = 0; i < PMC_MAX_IDS; i++) {
-- if (registered_ids[i] == 0) {
-- registered_ids[i] = id;
-- break;
-- }
-- if (registered_ids[i] == id)
-- break;
-- }
-+ return clk_save_context();
- }
-
--/*
-- * As Programmable Clock 0 is valid on AT91 chips, there is an offset
-- * of 1 between the stored value and the real clock ID.
-- */
--void pmc_register_pck(u8 pck)
-+static void at91_pmc_resume(void)
- {
-- int i;
--
-- for (i = 0; i < PMC_MAX_PCKS; i++) {
-- if (registered_pcks[i] == 0) {
-- registered_pcks[i] = pck + 1;
-- break;
-- }
-- if (registered_pcks[i] == (pck + 1))
-- break;
-- }
--}
--
--static int pmc_suspend(void)
--{
-- int i;
-- u8 num;
--
-- regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);
-- regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);
-- regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);
-- regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
-- regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr);
-- regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar);
-- regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr);
-- regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb);
-- regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr);
-- regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1);
--
-- for (i = 0; registered_ids[i]; i++) {
-- regmap_write(pmcreg, AT91_PMC_PCR,
-- (registered_ids[i] & AT91_PMC_PCR_PID_MASK));
-- regmap_read(pmcreg, AT91_PMC_PCR,
-- &pmc_cache.pcr[registered_ids[i]]);
-- }
-- for (i = 0; registered_pcks[i]; i++) {
-- num = registered_pcks[i] - 1;
-- regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);
-- }
--
-- return 0;
--}
--
--static bool pmc_ready(unsigned int mask)
--{
-- unsigned int status;
--
-- regmap_read(pmcreg, AT91_PMC_SR, &status);
--
-- return ((status & mask) == mask) ? 1 : 0;
--}
--
--static void pmc_resume(void)
--{
-- int i;
-- u8 num;
-- u32 tmp;
-- u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;
--
-- regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);
-- if (pmc_cache.mckr != tmp)
-- pr_warn("MCKR was not configured properly by the firmware\n");
-- regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp);
-- if (pmc_cache.pllar != tmp)
-- pr_warn("PLLAR was not configured properly by the firmware\n");
--
-- regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);
-- regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);
-- regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);
-- regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
-- regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr);
-- regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb);
-- regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr);
-- regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1);
--
-- for (i = 0; registered_ids[i]; i++) {
-- regmap_write(pmcreg, AT91_PMC_PCR,
-- pmc_cache.pcr[registered_ids[i]] |
-- AT91_PMC_PCR_CMD);
-- }
-- for (i = 0; registered_pcks[i]; i++) {
-- num = registered_pcks[i] - 1;
-- regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);
-- }
--
-- if (pmc_cache.uckr & AT91_PMC_UPLLEN)
-- mask |= AT91_PMC_LOCKU;
--
-- while (!pmc_ready(mask))
-- cpu_relax();
-+ clk_restore_context();
- }
-
- static struct syscore_ops pmc_syscore_ops = {
-- .suspend = pmc_suspend,
-- .resume = pmc_resume,
-+ .suspend = at91_pmc_suspend,
-+ .resume = at91_pmc_resume,
- };
-
- static const struct of_device_id sama5d2_pmc_dt_ids[] = {
-@@ -271,11 +142,7 @@ static int __init pmc_register_ops(void)
- of_node_put(np);
- return -ENODEV;
- }
--
-- pmcreg = device_node_to_regmap(np);
- of_node_put(np);
-- if (IS_ERR(pmcreg))
-- return PTR_ERR(pmcreg);
-
- register_syscore_ops(&pmc_syscore_ops);
-
---- a/drivers/clk/at91/pmc.h
-+++ b/drivers/clk/at91/pmc.h
-@@ -13,6 +13,8 @@
- #include <linux/regmap.h>
- #include <linux/spinlock.h>
-
-+#include <dt-bindings/clock/at91.h>
-+
- extern spinlock_t pmc_pcr_lock;
-
- struct pmc_data {
-@@ -98,6 +100,20 @@ struct clk_pcr_layout {
- u32 pid_mask;
- };
-
-+/**
-+ * struct at91_clk_pms - Power management state for AT91 clock
-+ * @rate: clock rate
-+ * @parent_rate: clock parent rate
-+ * @status: clock status (enabled or disabled)
-+ * @parent: clock parent index
-+ */
-+struct at91_clk_pms {
-+ unsigned long rate;
-+ unsigned long parent_rate;
-+ unsigned int status;
-+ unsigned int parent;
-+};
-+
- #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
- #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
-
-@@ -248,12 +264,4 @@ struct clk_hw * __init
- at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,
- const char *parent_name);
-
--#ifdef CONFIG_PM
--void pmc_register_id(u8 id);
--void pmc_register_pck(u8 pck);
--#else
--static inline void pmc_register_id(u8 id) {}
--static inline void pmc_register_pck(u8 pck) {}
--#endif
--
- #endif /* __PMC_H_ */
+++ /dev/null
-From 63a0c32028148e91ea91cfbf95841c4ecd69d21b Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:06 +0300
-Subject: [PATCH 235/247] clk: at91: pmc: execute suspend/resume only for
- backup mode
-
-Before going to backup mode architecture specific PM code sets the first
-word in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()).
-Thus take this into account when suspending/resuming clocks. This will
-avoid executing unnecessary instructions when suspending to non backup
-modes.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-3-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/pmc.c | 39 +++++++++++++++++++++++++++++++++++++++
- 1 file changed, 39 insertions(+)
-
---- a/drivers/clk/at91/pmc.c
-+++ b/drivers/clk/at91/pmc.c
-@@ -8,6 +8,7 @@
- #include <linux/clkdev.h>
- #include <linux/clk/at91_pmc.h>
- #include <linux/of.h>
-+#include <linux/of_address.h>
- #include <linux/mfd/syscon.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
-@@ -110,13 +111,35 @@ struct pmc_data *pmc_data_allocate(unsig
- }
-
- #ifdef CONFIG_PM
-+
-+/* Address in SECURAM that say if we suspend to backup mode. */
-+static void __iomem *at91_pmc_backup_suspend;
-+
- static int at91_pmc_suspend(void)
- {
-+ unsigned int backup;
-+
-+ if (!at91_pmc_backup_suspend)
-+ return 0;
-+
-+ backup = readl_relaxed(at91_pmc_backup_suspend);
-+ if (!backup)
-+ return 0;
-+
- return clk_save_context();
- }
-
- static void at91_pmc_resume(void)
- {
-+ unsigned int backup;
-+
-+ if (!at91_pmc_backup_suspend)
-+ return;
-+
-+ backup = readl_relaxed(at91_pmc_backup_suspend);
-+ if (!backup)
-+ return;
-+
- clk_restore_context();
- }
-
-@@ -144,6 +167,22 @@ static int __init pmc_register_ops(void)
- }
- of_node_put(np);
-
-+ np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
-+ if (!np)
-+ return -ENODEV;
-+
-+ if (!of_device_is_available(np)) {
-+ of_node_put(np);
-+ return -ENODEV;
-+ }
-+ of_node_put(np);
-+
-+ at91_pmc_backup_suspend = of_iomap(np, 0);
-+ if (!at91_pmc_backup_suspend) {
-+ pr_warn("%s(): unable to map securam\n", __func__);
-+ return -ENOMEM;
-+ }
-+
- register_syscore_ops(&pmc_syscore_ops);
-
- return 0;
+++ /dev/null
-From c716562753d1e51a1c53647aa77a332f97187d15 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:08 +0300
-Subject: [PATCH 237/247] clk: at91: clk-master: add register definition for
- sama7g5's master clock
-
-SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the
-register at offset 0x30 (relative to PMC). In the last/first phase of
-suspend/resume procedure (which is architecture specific) the parent
-of master clocks are changed (via assembly code) for more power saving
-(see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable
-and at91_mckx_ps_restore). Thus the macros corresponding to register
-at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S.
-commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's
-master clock") introduced the proper macros but didn't adapted the
-clk-master.c as well. Thus, this commit adapt the clk-master.c to use
-the macros introduced in commit ec03f18cc222 ("clk: at91: add register
-definition for sama7g5's master clock").
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-master.c | 50 ++++++++++++++++-------------------
- 1 file changed, 23 insertions(+), 27 deletions(-)
-
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -17,15 +17,7 @@
- #define MASTER_DIV_SHIFT 8
- #define MASTER_DIV_MASK 0x7
-
--#define PMC_MCR 0x30
--#define PMC_MCR_ID_MSK GENMASK(3, 0)
--#define PMC_MCR_CMD BIT(7)
--#define PMC_MCR_DIV GENMASK(10, 8)
--#define PMC_MCR_CSS GENMASK(20, 16)
- #define PMC_MCR_CSS_SHIFT (16)
--#define PMC_MCR_EN BIT(28)
--
--#define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK)
-
- #define MASTER_MAX_ID 4
-
-@@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struc
- {
- unsigned long flags;
- unsigned int val, cparent;
-- unsigned int enable = status ? PMC_MCR_EN : 0;
-+ unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;
-
- spin_lock_irqsave(master->lock, flags);
-
-- regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));
-- regmap_read(master->regmap, PMC_MCR, &val);
-- regmap_update_bits(master->regmap, PMC_MCR,
-- enable | PMC_MCR_CSS | PMC_MCR_DIV |
-- PMC_MCR_CMD | PMC_MCR_ID_MSK,
-+ regmap_write(master->regmap, AT91_PMC_MCR_V2,
-+ AT91_PMC_MCR_V2_ID(master->id));
-+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
-+ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
-+ enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |
-+ AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,
- enable | (master->parent << PMC_MCR_CSS_SHIFT) |
- (master->div << MASTER_DIV_SHIFT) |
-- PMC_MCR_CMD | PMC_MCR_ID(master->id));
-+ AT91_PMC_MCR_V2_CMD |
-+ AT91_PMC_MCR_V2_ID(master->id));
-
-- cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
-+ cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
-
- /* Wait here only if parent is being changed. */
- while ((cparent != master->parent) && !clk_master_ready(master))
-@@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(s
-
- spin_lock_irqsave(master->lock, flags);
-
-- regmap_write(master->regmap, PMC_MCR, master->id);
-- regmap_update_bits(master->regmap, PMC_MCR,
-- PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK,
-- PMC_MCR_CMD | PMC_MCR_ID(master->id));
-+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
-+ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
-+ AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD |
-+ AT91_PMC_MCR_V2_ID_MSK,
-+ AT91_PMC_MCR_V2_CMD |
-+ AT91_PMC_MCR_V2_ID(master->id));
-
- spin_unlock_irqrestore(master->lock, flags);
- }
-@@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled
-
- spin_lock_irqsave(master->lock, flags);
-
-- regmap_write(master->regmap, PMC_MCR, master->id);
-- regmap_read(master->regmap, PMC_MCR, &val);
-+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
-+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
-
- spin_unlock_irqrestore(master->lock, flags);
-
-- return !!(val & PMC_MCR_EN);
-+ return !!(val & AT91_PMC_MCR_V2_EN);
- }
-
- static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,
-@@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct
- master->mux_table = mux_table;
-
- spin_lock_irqsave(master->lock, flags);
-- regmap_write(master->regmap, PMC_MCR, master->id);
-- regmap_read(master->regmap, PMC_MCR, &val);
-- master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
-- master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT;
-+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
-+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
-+ master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
-+ master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT;
- spin_unlock_irqrestore(master->lock, flags);
-
- hw = &master->hw;
+++ /dev/null
-From 17b53ad1574cb5f41789993289d3d94f7a50f0ce Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:09 +0300
-Subject: [PATCH 238/247] clk: at91: clk-master: improve readability by using
- local variables
-
-Improve readability in clk_sama7g5_master_set() by using local
-variables.
-
-Suggested-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-6-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-master.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -680,6 +680,8 @@ static void clk_sama7g5_master_set(struc
- unsigned long flags;
- unsigned int val, cparent;
- unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;
-+ unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT;
-+ unsigned int div = master->div << MASTER_DIV_SHIFT;
-
- spin_lock_irqsave(master->lock, flags);
-
-@@ -689,9 +691,7 @@ static void clk_sama7g5_master_set(struc
- regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
- enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |
- AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,
-- enable | (master->parent << PMC_MCR_CSS_SHIFT) |
-- (master->div << MASTER_DIV_SHIFT) |
-- AT91_PMC_MCR_V2_CMD |
-+ enable | parent | div | AT91_PMC_MCR_V2_CMD |
- AT91_PMC_MCR_V2_ID(master->id));
-
- cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
+++ /dev/null
-From 8a38e0dda46c9d941a61d8b2e6c14704531b7871 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:10 +0300
-Subject: [PATCH 239/247] clk: at91: pmc: add sama7g5 to the list of available
- pmcs
-
-Add SAMA7G5 to the list of available PMCs such that the suspend/resume
-code for clocks to be used on backup mode.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-7-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/pmc.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/at91/pmc.c
-+++ b/drivers/clk/at91/pmc.c
-@@ -148,8 +148,9 @@ static struct syscore_ops pmc_syscore_op
- .resume = at91_pmc_resume,
- };
-
--static const struct of_device_id sama5d2_pmc_dt_ids[] = {
-+static const struct of_device_id pmc_dt_ids[] = {
- { .compatible = "atmel,sama5d2-pmc" },
-+ { .compatible = "microchip,sama7g5-pmc", },
- { /* sentinel */ }
- };
-
-@@ -157,7 +158,7 @@ static int __init pmc_register_ops(void)
- {
- struct device_node *np;
-
-- np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);
-+ np = of_find_matching_node(NULL, pmc_dt_ids);
- if (!np)
- return -ENODEV;
-
+++ /dev/null
-From 27c11c09346b7b9f67eeb39db1b943f4a9742ff3 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:13 +0300
-Subject: [PATCH 241/247] clk: at91: clk-master: mask mckr against layout->mask
-
-Mask values read/written from/to MCKR against layout->mask as this
-mask may be different b/w PMC versions.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-10-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-master.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -186,8 +186,8 @@ static int clk_master_div_set_rate(struc
- if (ret)
- goto unlock;
-
-- tmp = mckr & master->layout->mask;
-- tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ mckr &= master->layout->mask;
-+ tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
- if (tmp == div)
- goto unlock;
-
-@@ -384,6 +384,7 @@ static unsigned long clk_master_pres_rec
- regmap_read(master->regmap, master->layout->offset, &val);
- spin_unlock_irqrestore(master->lock, flags);
-
-+ val &= master->layout->mask;
- pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
- if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)
- pres = 3;
-@@ -403,6 +404,8 @@ static u8 clk_master_pres_get_parent(str
- regmap_read(master->regmap, master->layout->offset, &mckr);
- spin_unlock_irqrestore(master->lock, flags);
-
-+ mckr &= master->layout->mask;
-+
- return mckr & AT91_PMC_CSS;
- }
-
+++ /dev/null
-From e76d2af5009f52aa02d3db7ae32d150ad66398f9 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:15 +0300
-Subject: [PATCH 243/247] clk: at91: clk-sam9x60-pll: add notifier for div part
- of PLL
-
-SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts:
-one fractional part and one divider. On SAMA7G5 the CPU PLL could be
-changed at run-time to implement DVFS. The hardware clock tree on
-SAMA7G5 for CPU PLL is as follows:
-
- +---- div1 ----------------> cpuck
- |
-FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0
-
-The div1 block is not implemented in Linux; on prescaler block it has
-been discovered a bug on some scenarios and will be removed from Linux
-in next commits. Thus, the final clock tree that will be used in Linux
-will be as follows:
-
- +-----------> cpuck
- |
-FRAC PLL ---> DIV PLL -+-> div0 ---> mck0
-
-It has been proposed in [1] to not introduce a new CPUFreq driver but
-to overload the proper clock drivers with proper operation such that
-cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement
-clock notifiers which applies safe dividers before FRAC PLL is changed.
-The current commit treats only the DIV PLL by adding a notifier that
-sets a safe divider on PRE_RATE_CHANGE events. The safe divider is
-provided by initialization clock code (sama7g5.c). The div0 is treated
-in next commits (to keep the changes as clean as possible).
-
-[1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++++++++++++++-------
- drivers/clk/at91/pmc.h | 3 +-
- drivers/clk/at91/sam9x60.c | 6 +-
- drivers/clk/at91/sama7g5.c | 13 +++-
- 4 files changed, 95 insertions(+), 29 deletions(-)
-
---- a/drivers/clk/at91/clk-sam9x60-pll.c
-+++ b/drivers/clk/at91/clk-sam9x60-pll.c
-@@ -5,6 +5,7 @@
- */
-
- #include <linux/bitfield.h>
-+#include <linux/clk.h>
- #include <linux/clk-provider.h>
- #include <linux/clkdev.h>
- #include <linux/clk/at91_pmc.h>
-@@ -47,12 +48,15 @@ struct sam9x60_div {
- struct sam9x60_pll_core core;
- struct at91_clk_pms pms;
- u8 div;
-+ u8 safe_div;
- };
-
- #define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw)
- #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core)
- #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core)
-
-+static struct sam9x60_div *notifier_div;
-+
- static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
- {
- unsigned int status;
-@@ -329,6 +333,26 @@ static const struct clk_ops sam9x60_frac
- .restore_context = sam9x60_frac_pll_restore_context,
- };
-
-+/* This function should be called with spinlock acquired. */
-+static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
-+ bool enable)
-+{
-+ struct regmap *regmap = core->regmap;
-+ u32 ena_msk = enable ? core->layout->endiv_mask : 0;
-+ u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0;
-+
-+ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
-+ core->layout->div_mask | ena_msk,
-+ (div << core->layout->div_shift) | ena_val);
-+
-+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
-+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
-+ AT91_PMC_PLL_UPDT_UPDATE | core->id);
-+
-+ while (!sam9x60_pll_ready(regmap, core->id))
-+ cpu_relax();
-+}
-+
- static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
- {
- struct sam9x60_div *div = to_sam9x60_div(core);
-@@ -346,17 +370,7 @@ static int sam9x60_div_pll_set(struct sa
- if (!!(val & core->layout->endiv_mask) && cdiv == div->div)
- goto unlock;
-
-- regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
-- core->layout->div_mask | core->layout->endiv_mask,
-- (div->div << core->layout->div_shift) |
-- (1 << core->layout->endiv_shift));
--
-- regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
-- AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
-- AT91_PMC_PLL_UPDT_UPDATE | core->id);
--
-- while (!sam9x60_pll_ready(regmap, core->id))
-- cpu_relax();
-+ sam9x60_div_pll_set_div(core, div->div, 1);
-
- unlock:
- spin_unlock_irqrestore(core->lock, flags);
-@@ -502,16 +516,7 @@ static int sam9x60_div_pll_set_rate_chg(
- if (cdiv == div->div)
- goto unlock;
-
-- regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
-- core->layout->div_mask,
-- (div->div << core->layout->div_shift));
--
-- regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
-- AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
-- AT91_PMC_PLL_UPDT_UPDATE | core->id);
--
-- while (!sam9x60_pll_ready(regmap, core->id))
-- cpu_relax();
-+ sam9x60_div_pll_set_div(core, div->div, 0);
-
- unlock:
- spin_unlock_irqrestore(core->lock, irqflags);
-@@ -538,6 +543,48 @@ static void sam9x60_div_pll_restore_cont
- sam9x60_div_pll_set(core);
- }
-
-+static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier,
-+ unsigned long code, void *data)
-+{
-+ struct sam9x60_div *div = notifier_div;
-+ struct sam9x60_pll_core core = div->core;
-+ struct regmap *regmap = core.regmap;
-+ unsigned long irqflags;
-+ u32 val, cdiv;
-+ int ret = NOTIFY_DONE;
-+
-+ if (code != PRE_RATE_CHANGE)
-+ return ret;
-+
-+ /*
-+ * We switch to safe divider to avoid overclocking of other domains
-+ * feed by us while the frac PLL (our parent) is changed.
-+ */
-+ div->div = div->safe_div;
-+
-+ spin_lock_irqsave(core.lock, irqflags);
-+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
-+ core.id);
-+ regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
-+ cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
-+
-+ /* Stop if nothing changed. */
-+ if (cdiv == div->safe_div)
-+ goto unlock;
-+
-+ sam9x60_div_pll_set_div(&core, div->div, 0);
-+ ret = NOTIFY_OK;
-+
-+unlock:
-+ spin_unlock_irqrestore(core.lock, irqflags);
-+
-+ return ret;
-+}
-+
-+static struct notifier_block sam9x60_div_pll_notifier = {
-+ .notifier_call = sam9x60_div_pll_notifier_fn,
-+};
-+
- static const struct clk_ops sam9x60_div_pll_ops = {
- .prepare = sam9x60_div_pll_prepare,
- .unprepare = sam9x60_div_pll_unprepare,
-@@ -647,7 +694,8 @@ struct clk_hw * __init
- sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
- const char *name, const char *parent_name, u8 id,
- const struct clk_pll_characteristics *characteristics,
-- const struct clk_pll_layout *layout, u32 flags)
-+ const struct clk_pll_layout *layout, u32 flags,
-+ u32 safe_div)
- {
- struct sam9x60_div *div;
- struct clk_hw *hw;
-@@ -656,9 +704,13 @@ sam9x60_clk_register_div_pll(struct regm
- unsigned int val;
- int ret;
-
-- if (id > PLL_MAX_ID || !lock)
-+ /* We only support one changeable PLL. */
-+ if (id > PLL_MAX_ID || !lock || (safe_div && notifier_div))
- return ERR_PTR(-EINVAL);
-
-+ if (safe_div >= PLL_DIV_MAX)
-+ safe_div = PLL_DIV_MAX - 1;
-+
- div = kzalloc(sizeof(*div), GFP_KERNEL);
- if (!div)
- return ERR_PTR(-ENOMEM);
-@@ -678,6 +730,7 @@ sam9x60_clk_register_div_pll(struct regm
- div->core.layout = layout;
- div->core.regmap = regmap;
- div->core.lock = lock;
-+ div->safe_div = safe_div;
-
- spin_lock_irqsave(div->core.lock, irqflags);
-
-@@ -693,6 +746,9 @@ sam9x60_clk_register_div_pll(struct regm
- if (ret) {
- kfree(div);
- hw = ERR_PTR(ret);
-+ } else if (div->safe_div) {
-+ notifier_div = div;
-+ clk_notifier_register(hw->clk, &sam9x60_div_pll_notifier);
- }
-
- return hw;
---- a/drivers/clk/at91/pmc.h
-+++ b/drivers/clk/at91/pmc.h
-@@ -214,7 +214,8 @@ struct clk_hw * __init
- sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
- const char *name, const char *parent_name, u8 id,
- const struct clk_pll_characteristics *characteristics,
-- const struct clk_pll_layout *layout, u32 flags);
-+ const struct clk_pll_layout *layout, u32 flags,
-+ u32 safe_div);
-
- struct clk_hw * __init
- sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
---- a/drivers/clk/at91/sam9x60.c
-+++ b/drivers/clk/at91/sam9x60.c
-@@ -242,7 +242,7 @@ static void __init sam9x60_pmc_setup(str
- * This feeds CPU. It should not
- * be disabled.
- */
-- CLK_IS_CRITICAL | CLK_SET_RATE_GATE);
-+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
-@@ -260,7 +260,7 @@ static void __init sam9x60_pmc_setup(str
- &pll_div_layout,
- CLK_SET_RATE_GATE |
- CLK_SET_PARENT_GATE |
-- CLK_SET_RATE_PARENT);
-+ CLK_SET_RATE_PARENT, 0);
- if (IS_ERR(hw))
- goto err_free;
-
-@@ -279,7 +279,7 @@ static void __init sam9x60_pmc_setup(str
- hw = at91_clk_register_master_div(regmap, "masterck_div",
- "masterck_pres", &sam9x60_master_layout,
- &mck_characteristics, &mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/sama7g5.c
-+++ b/drivers/clk/at91/sama7g5.c
-@@ -127,6 +127,8 @@ static const struct clk_pll_characterist
- * @t: clock type
- * @f: clock flags
- * @eid: export index in sama7g5->chws[] array
-+ * @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE
-+ * notification
- */
- static const struct {
- const char *n;
-@@ -136,6 +138,7 @@ static const struct {
- unsigned long f;
- u8 t;
- u8 eid;
-+ u8 safe_div;
- } sama7g5_plls[][PLL_ID_MAX] = {
- [PLL_ID_CPU] = {
- { .n = "cpupll_fracck",
-@@ -156,7 +159,12 @@ static const struct {
- .t = PLL_TYPE_DIV,
- /* This feeds CPU. It should not be disabled. */
- .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-- .eid = PMC_CPUPLL, },
-+ .eid = PMC_CPUPLL,
-+ /*
-+ * Safe div=15 should be safe even for switching b/w 1GHz and
-+ * 90MHz (frac pll might go up to 1.2GHz).
-+ */
-+ .safe_div = 15, },
- },
-
- [PLL_ID_SYS] = {
-@@ -966,7 +974,8 @@ static void __init sama7g5_pmc_setup(str
- sama7g5_plls[i][j].p, i,
- sama7g5_plls[i][j].c,
- sama7g5_plls[i][j].l,
-- sama7g5_plls[i][j].f);
-+ sama7g5_plls[i][j].f,
-+ sama7g5_plls[i][j].safe_div);
- break;
-
- default:
+++ /dev/null
-From 75d5d1d584ae73ba0c36d1d7255db6153ca4d3f3 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:16 +0300
-Subject: [PATCH 244/247] clk: at91: clk-master: add notifier for divider
-
-SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same
-parent with cpuck as seen in the following clock tree:
-
- +----------> cpuck
- |
-FRAC PLL ---> DIV PLL -+-> DIV ---> mck0
-
-mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking
-while changing FRAC PLL or DIV PLL the commit implements a notifier for
-mck0 which applies a safe divider to register (maximum value of the divider
-which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not
-overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE
-events.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/at91rm9200.c | 2 +-
- drivers/clk/at91/at91sam9260.c | 2 +-
- drivers/clk/at91/at91sam9g45.c | 2 +-
- drivers/clk/at91/at91sam9n12.c | 2 +-
- drivers/clk/at91/at91sam9rl.c | 2 +-
- drivers/clk/at91/at91sam9x5.c | 2 +-
- drivers/clk/at91/clk-master.c | 244 +++++++++++++++++++++++----------
- drivers/clk/at91/dt-compat.c | 2 +-
- drivers/clk/at91/pmc.h | 2 +-
- drivers/clk/at91/sama5d2.c | 2 +-
- drivers/clk/at91/sama5d3.c | 2 +-
- drivers/clk/at91/sama5d4.c | 2 +-
- drivers/clk/at91/sama7g5.c | 2 +-
- 13 files changed, 186 insertions(+), 82 deletions(-)
-
---- a/drivers/clk/at91/at91rm9200.c
-+++ b/drivers/clk/at91/at91rm9200.c
-@@ -152,7 +152,7 @@ static void __init at91rm9200_pmc_setup(
- "masterck_pres",
- &at91rm9200_master_layout,
- &rm9200_mck_characteristics,
-- &rm9200_mck_lock, CLK_SET_RATE_GATE);
-+ &rm9200_mck_lock, CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/at91sam9260.c
-+++ b/drivers/clk/at91/at91sam9260.c
-@@ -429,7 +429,7 @@ static void __init at91sam926x_pmc_setup
- &at91rm9200_master_layout,
- data->mck_characteristics,
- &at91sam9260_mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/at91sam9g45.c
-+++ b/drivers/clk/at91/at91sam9g45.c
-@@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup
- &at91rm9200_master_layout,
- &mck_characteristics,
- &at91sam9g45_mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/at91sam9n12.c
-+++ b/drivers/clk/at91/at91sam9n12.c
-@@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup
- &at91sam9x5_master_layout,
- &mck_characteristics,
- &at91sam9n12_mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/at91sam9rl.c
-+++ b/drivers/clk/at91/at91sam9rl.c
-@@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup(
- "masterck_pres",
- &at91rm9200_master_layout,
- &sam9rl_mck_characteristics,
-- &sam9rl_mck_lock, CLK_SET_RATE_GATE);
-+ &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/at91sam9x5.c
-+++ b/drivers/clk/at91/at91sam9x5.c
-@@ -210,7 +210,7 @@ static void __init at91sam9x5_pmc_setup(
- "masterck_pres",
- &at91sam9x5_master_layout,
- &mck_characteristics, &mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -5,6 +5,7 @@
-
- #include <linux/clk-provider.h>
- #include <linux/clkdev.h>
-+#include <linux/clk.h>
- #include <linux/clk/at91_pmc.h>
- #include <linux/of.h>
- #include <linux/mfd/syscon.h>
-@@ -36,8 +37,12 @@ struct clk_master {
- u8 id;
- u8 parent;
- u8 div;
-+ u32 safe_div;
- };
-
-+/* MCK div reference to be used by notifier. */
-+static struct clk_master *master_div;
-+
- static inline bool clk_master_ready(struct clk_master *master)
- {
- unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;
-@@ -153,107 +158,81 @@ static const struct clk_ops master_div_o
- .restore_context = clk_master_div_restore_context,
- };
-
--static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,
-- unsigned long parent_rate)
-+/* This function must be called with lock acquired. */
-+static int clk_master_div_set(struct clk_master *master,
-+ unsigned long parent_rate, int div)
- {
-- struct clk_master *master = to_clk_master(hw);
- const struct clk_master_characteristics *characteristics =
- master->characteristics;
-- unsigned long flags;
-- unsigned int mckr, tmp;
-- int div, i;
-+ unsigned long rate = parent_rate;
-+ unsigned int max_div = 0, div_index = 0, max_div_index = 0;
-+ unsigned int i, mckr, tmp;
- int ret;
-
-- div = DIV_ROUND_CLOSEST(parent_rate, rate);
-- if (div > ARRAY_SIZE(characteristics->divisors))
-- return -EINVAL;
--
- for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
- if (!characteristics->divisors[i])
- break;
-
-- if (div == characteristics->divisors[i]) {
-- div = i;
-- break;
-+ if (div == characteristics->divisors[i])
-+ div_index = i;
-+
-+ if (max_div < characteristics->divisors[i]) {
-+ max_div = characteristics->divisors[i];
-+ max_div_index = i;
- }
- }
-
-- if (i == ARRAY_SIZE(characteristics->divisors))
-- return -EINVAL;
-+ if (div > max_div)
-+ div_index = max_div_index;
-
-- spin_lock_irqsave(master->lock, flags);
- ret = regmap_read(master->regmap, master->layout->offset, &mckr);
- if (ret)
-- goto unlock;
-+ return ret;
-
- mckr &= master->layout->mask;
- tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-- if (tmp == div)
-- goto unlock;
-+ if (tmp == div_index)
-+ return 0;
-+
-+ rate /= characteristics->divisors[div_index];
-+ if (rate < characteristics->output.min)
-+ pr_warn("master clk div is underclocked");
-+ else if (rate > characteristics->output.max)
-+ pr_warn("master clk div is overclocked");
-
- mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT);
-- mckr |= (div << MASTER_DIV_SHIFT);
-+ mckr |= (div_index << MASTER_DIV_SHIFT);
- ret = regmap_write(master->regmap, master->layout->offset, mckr);
- if (ret)
-- goto unlock;
-+ return ret;
-
- while (!clk_master_ready(master))
- cpu_relax();
--unlock:
-- spin_unlock_irqrestore(master->lock, flags);
-+
-+ master->div = characteristics->divisors[div_index];
-
- return 0;
- }
-
--static int clk_master_div_determine_rate(struct clk_hw *hw,
-- struct clk_rate_request *req)
-+static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw,
-+ unsigned long parent_rate)
- {
- struct clk_master *master = to_clk_master(hw);
-- const struct clk_master_characteristics *characteristics =
-- master->characteristics;
-- struct clk_hw *parent;
-- unsigned long parent_rate, tmp_rate, best_rate = 0;
-- int i, best_diff = INT_MIN, tmp_diff;
--
-- parent = clk_hw_get_parent(hw);
-- if (!parent)
-- return -EINVAL;
--
-- parent_rate = clk_hw_get_rate(parent);
-- if (!parent_rate)
-- return -EINVAL;
-
-- for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
-- if (!characteristics->divisors[i])
-- break;
--
-- tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate,
-- characteristics->divisors[i]);
-- tmp_diff = abs(tmp_rate - req->rate);
--
-- if (!best_rate || best_diff > tmp_diff) {
-- best_diff = tmp_diff;
-- best_rate = tmp_rate;
-- }
--
-- if (!best_diff)
-- break;
-- }
--
-- req->best_parent_rate = best_rate;
-- req->best_parent_hw = parent;
-- req->rate = best_rate;
--
-- return 0;
-+ return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div);
- }
-
- static void clk_master_div_restore_context_chg(struct clk_hw *hw)
- {
- struct clk_master *master = to_clk_master(hw);
-+ unsigned long flags;
- int ret;
-
-- ret = clk_master_div_set_rate(hw, master->pms.rate,
-- master->pms.parent_rate);
-+ spin_lock_irqsave(master->lock, flags);
-+ ret = clk_master_div_set(master, master->pms.parent_rate,
-+ DIV_ROUND_CLOSEST(master->pms.parent_rate,
-+ master->pms.rate));
-+ spin_unlock_irqrestore(master->lock, flags);
- if (ret)
- pr_warn("Failed to restore MCK DIV clock\n");
- }
-@@ -261,13 +240,116 @@ static void clk_master_div_restore_conte
- static const struct clk_ops master_div_ops_chg = {
- .prepare = clk_master_prepare,
- .is_prepared = clk_master_is_prepared,
-- .recalc_rate = clk_master_div_recalc_rate,
-- .determine_rate = clk_master_div_determine_rate,
-- .set_rate = clk_master_div_set_rate,
-+ .recalc_rate = clk_master_div_recalc_rate_chg,
- .save_context = clk_master_div_save_context,
- .restore_context = clk_master_div_restore_context_chg,
- };
-
-+static int clk_master_div_notifier_fn(struct notifier_block *notifier,
-+ unsigned long code, void *data)
-+{
-+ const struct clk_master_characteristics *characteristics =
-+ master_div->characteristics;
-+ struct clk_notifier_data *cnd = data;
-+ unsigned long flags, new_parent_rate, new_rate;
-+ unsigned int mckr, div, new_div = 0;
-+ int ret, i;
-+ long tmp_diff;
-+ long best_diff = -1;
-+
-+ spin_lock_irqsave(master_div->lock, flags);
-+ switch (code) {
-+ case PRE_RATE_CHANGE:
-+ /*
-+ * We want to avoid any overclocking of MCK DIV domain. To do
-+ * this we set a safe divider (the underclocking is not of
-+ * interest as we can go as low as 32KHz). The relation
-+ * b/w this clock and its parents are as follows:
-+ *
-+ * FRAC PLL -> DIV PLL -> MCK DIV
-+ *
-+ * With the proper safe divider we should be good even with FRAC
-+ * PLL at its maximum value.
-+ */
-+ ret = regmap_read(master_div->regmap, master_div->layout->offset,
-+ &mckr);
-+ if (ret) {
-+ ret = NOTIFY_STOP_MASK;
-+ goto unlock;
-+ }
-+
-+ mckr &= master_div->layout->mask;
-+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+
-+ /* Switch to safe divider. */
-+ clk_master_div_set(master_div,
-+ cnd->old_rate * characteristics->divisors[div],
-+ master_div->safe_div);
-+ break;
-+
-+ case POST_RATE_CHANGE:
-+ /*
-+ * At this point we want to restore MCK DIV domain to its maximum
-+ * allowed rate.
-+ */
-+ ret = regmap_read(master_div->regmap, master_div->layout->offset,
-+ &mckr);
-+ if (ret) {
-+ ret = NOTIFY_STOP_MASK;
-+ goto unlock;
-+ }
-+
-+ mckr &= master_div->layout->mask;
-+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ new_parent_rate = cnd->new_rate * characteristics->divisors[div];
-+
-+ for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
-+ if (!characteristics->divisors[i])
-+ break;
-+
-+ new_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate,
-+ characteristics->divisors[i]);
-+
-+ tmp_diff = characteristics->output.max - new_rate;
-+ if (tmp_diff < 0)
-+ continue;
-+
-+ if (best_diff < 0 || best_diff > tmp_diff) {
-+ new_div = characteristics->divisors[i];
-+ best_diff = tmp_diff;
-+ }
-+
-+ if (!tmp_diff)
-+ break;
-+ }
-+
-+ if (!new_div) {
-+ ret = NOTIFY_STOP_MASK;
-+ goto unlock;
-+ }
-+
-+ /* Update the div to preserve MCK DIV clock rate. */
-+ clk_master_div_set(master_div, new_parent_rate,
-+ new_div);
-+
-+ ret = NOTIFY_OK;
-+ break;
-+
-+ default:
-+ ret = NOTIFY_DONE;
-+ break;
-+ }
-+
-+unlock:
-+ spin_unlock_irqrestore(master_div->lock, flags);
-+
-+ return ret;
-+}
-+
-+static struct notifier_block clk_master_div_notifier = {
-+ .notifier_call = clk_master_div_notifier_fn,
-+};
-+
- static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
- struct clk_hw *parent,
- unsigned long parent_rate,
-@@ -496,6 +578,8 @@ at91_clk_register_master_internal(struct
- struct clk_master *master;
- struct clk_init_data init;
- struct clk_hw *hw;
-+ unsigned int mckr;
-+ unsigned long irqflags;
- int ret;
-
- if (!name || !num_parents || !parent_names || !lock)
-@@ -518,6 +602,16 @@ at91_clk_register_master_internal(struct
- master->chg_pid = chg_pid;
- master->lock = lock;
-
-+ if (ops == &master_div_ops_chg) {
-+ spin_lock_irqsave(master->lock, irqflags);
-+ regmap_read(master->regmap, master->layout->offset, &mckr);
-+ spin_unlock_irqrestore(master->lock, irqflags);
-+
-+ mckr &= layout->mask;
-+ mckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ master->div = characteristics->divisors[mckr];
-+ }
-+
- hw = &master->hw;
- ret = clk_hw_register(NULL, &master->hw);
- if (ret) {
-@@ -554,19 +648,29 @@ at91_clk_register_master_div(struct regm
- const char *name, const char *parent_name,
- const struct clk_master_layout *layout,
- const struct clk_master_characteristics *characteristics,
-- spinlock_t *lock, u32 flags)
-+ spinlock_t *lock, u32 flags, u32 safe_div)
- {
- const struct clk_ops *ops;
-+ struct clk_hw *hw;
-
- if (flags & CLK_SET_RATE_GATE)
- ops = &master_div_ops;
- else
- ops = &master_div_ops_chg;
-
-- return at91_clk_register_master_internal(regmap, name, 1,
-- &parent_name, layout,
-- characteristics, ops,
-- lock, flags, -EINVAL);
-+ hw = at91_clk_register_master_internal(regmap, name, 1,
-+ &parent_name, layout,
-+ characteristics, ops,
-+ lock, flags, -EINVAL);
-+
-+ if (!IS_ERR(hw) && safe_div) {
-+ master_div = to_clk_master(hw);
-+ master_div->safe_div = safe_div;
-+ clk_notifier_register(hw->clk,
-+ &clk_master_div_notifier);
-+ }
-+
-+ return hw;
- }
-
- static unsigned long
---- a/drivers/clk/at91/dt-compat.c
-+++ b/drivers/clk/at91/dt-compat.c
-@@ -399,7 +399,7 @@ of_at91_clk_master_setup(struct device_n
-
- hw = at91_clk_register_master_div(regmap, name, "masterck_pres",
- layout, characteristics,
-- &mck_lock, CLK_SET_RATE_GATE);
-+ &mck_lock, CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto out_free_characteristics;
-
---- a/drivers/clk/at91/pmc.h
-+++ b/drivers/clk/at91/pmc.h
-@@ -182,7 +182,7 @@ at91_clk_register_master_div(struct regm
- const char *parent_names,
- const struct clk_master_layout *layout,
- const struct clk_master_characteristics *characteristics,
-- spinlock_t *lock, u32 flags);
-+ spinlock_t *lock, u32 flags, u32 safe_div);
-
- struct clk_hw * __init
- at91_clk_sama7g5_register_master(struct regmap *regmap,
---- a/drivers/clk/at91/sama5d2.c
-+++ b/drivers/clk/at91/sama5d2.c
-@@ -249,7 +249,7 @@ static void __init sama5d2_pmc_setup(str
- "masterck_pres",
- &at91sam9x5_master_layout,
- &mck_characteristics, &mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/sama5d3.c
-+++ b/drivers/clk/at91/sama5d3.c
-@@ -184,7 +184,7 @@ static void __init sama5d3_pmc_setup(str
- "masterck_pres",
- &at91sam9x5_master_layout,
- &mck_characteristics, &mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/sama5d4.c
-+++ b/drivers/clk/at91/sama5d4.c
-@@ -199,7 +199,7 @@ static void __init sama5d4_pmc_setup(str
- "masterck_pres",
- &at91sam9x5_master_layout,
- &mck_characteristics, &mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/sama7g5.c
-+++ b/drivers/clk/at91/sama7g5.c
-@@ -993,7 +993,7 @@ static void __init sama7g5_pmc_setup(str
- parent_names[0] = "cpupll_divpmcck";
- hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck",
- &mck0_layout, &mck0_characteristics,
-- &pmc_mck0_lock, 0);
-+ &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
- if (IS_ERR(hw))
- goto err_free;
-
+++ /dev/null
-From 9fd5a49f6da9de5da83f4a53eccefad647ab15ed Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:18 +0300
-Subject: [PATCH 246/247] clk: at91: sama7g5: set low limit for mck0 at 32KHz
-
-MCK0 could go as low as 32KHz. Set this limit.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-15-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/sama7g5.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/at91/sama7g5.c
-+++ b/drivers/clk/at91/sama7g5.c
-@@ -849,7 +849,7 @@ static const struct {
-
- /* MCK0 characteristics. */
- static const struct clk_master_characteristics mck0_characteristics = {
-- .output = { .min = 50000000, .max = 200000000 },
-+ .output = { .min = 32768, .max = 200000000 },
- .divisors = { 1, 2, 4, 3, 5 },
- .have_div3_pres = 1,
- };
+++ /dev/null
-From fe07791494a78d5a4be1363385e6ba7940740644 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:19 +0300
-Subject: [PATCH 247/247] clk: use clk_core_get_rate_recalc() in clk_rate_get()
-
-In case clock flags contains CLK_GET_RATE_NOCACHE the clk_rate_get()
-will return the cached rate. Thus, use clk_core_get_rate_recalc() which
-takes proper action when clock flags contains CLK_GET_RATE_NOCACHE.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-16-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-[sboyd@kernel.org: Grab prepare lock around operation]
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/clk.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/clk.c
-+++ b/drivers/clk/clk.c
-@@ -3145,7 +3145,10 @@ static int clk_rate_get(void *data, u64
- {
- struct clk_core *core = data;
-
-- *val = core->rate;
-+ clk_prepare_lock();
-+ *val = clk_core_get_rate_recalc(core);
-+ clk_prepare_unlock();
-+
- return 0;
- }
-
--- /dev/null
+From 5d8ae2928f71f0f9c2c3f8f13d00ecec35649ad3 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Thu, 15 Dec 2022 17:42:54 +0100
+Subject: [PATCH] pinctrl: at91: convert to NOIRQ_SYSTEM_SLEEP_PM_OPS
+
+With the old SET_NOIRQ_SYSTEM_SLEEP_PM_OPS, some configs result in a
+build warning:
+
+drivers/pinctrl/pinctrl-at91.c:1668:12: error: 'at91_gpio_resume' defined but not used [-Werror=unused-function]
+ 1668 | static int at91_gpio_resume(struct device *dev)
+ | ^~~~~~~~~~~~~~~~
+drivers/pinctrl/pinctrl-at91.c:1650:12: error: 'at91_gpio_suspend' defined but not used [-Werror=unused-function]
+ 1650 | static int at91_gpio_suspend(struct device *dev)
+ | ^~~~~~~~~~~~~~~~~
+
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Ryan Wanner <Ryan.Wanner@microchip.com>
+Link: https://lore.kernel.org/r/20221215164301.934805-1-arnd@kernel.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-at91.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/pinctrl-at91.c
++++ b/drivers/pinctrl/pinctrl-at91.c
+@@ -1921,7 +1921,7 @@ err:
+ }
+
+ static const struct dev_pm_ops at91_gpio_pm_ops = {
+- SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(at91_gpio_suspend, at91_gpio_resume)
++ NOIRQ_SYSTEM_SLEEP_PM_OPS(at91_gpio_suspend, at91_gpio_resume)
+ };
+
+ static struct platform_driver at91_gpio_driver = {
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_V4 is not set
-CONFIG_ARCH_MULTI_V4T=y
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-# CONFIG_AT91RM9200_WATCHDOG is not set
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_AT91_ADC is not set
-CONFIG_AT91_SAMA5D2_ADC=y
-CONFIG_AT91_SOC_ID=y
-# CONFIG_AT91_SOC_SFR is not set
-CONFIG_ATMEL_AIC5_IRQ=y
-CONFIG_ATMEL_AIC_IRQ=y
-CONFIG_ATMEL_CLOCKSOURCE_PIT=y
-CONFIG_ATMEL_CLOCKSOURCE_TCB=y
-CONFIG_ATMEL_EBI=y
-CONFIG_ATMEL_PIT=y
-CONFIG_ATMEL_PM=y
-CONFIG_ATMEL_SDRAMC=y
-CONFIG_ATMEL_SSC=y
-CONFIG_ATMEL_ST=y
-CONFIG_ATMEL_TCB_CLKSRC=y
-CONFIG_AT_HDMAC=y
-CONFIG_AT_XDMAC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_PM=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_AT91=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CPU_32v4T=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV4T=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM920T=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_V4WT=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_NO_EFFICIENT_FFS=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRC16=y
-CONFIG_CRC7=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EXT4_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_ATMEL=y
-CONFIG_HZ=128
-CONFIG_HZ_FIXED=128
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_AT91=y
-# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_GPIO=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACB=y
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MFD_AT91_USART=y
-CONFIG_MFD_ATMEL_FLEXCOM=y
-CONFIG_MFD_ATMEL_HLCDC=y
-CONFIG_MFD_ATMEL_SMC=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICREL_PHY=y
-CONFIG_MICROCHIP_PIT64B=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_AT91=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_DATAFLASH=y
-# CONFIG_MTD_DATAFLASH_OTP is not set
-# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_BLOCK is not set
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MICROCHIP_OTPC is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AT91=y
-# CONFIG_PINCTRL_AT91PIO4 is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_AT91_POWEROFF=y
-CONFIG_POWER_RESET_AT91_RESET=y
-CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_PWM_ATMEL_HLCDC_PWM=y
-CONFIG_PWM_ATMEL_TCB=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SAMA5D4_WATCHDOG=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_SERIAL_ATMEL_PDC=y
-# CONFIG_SERIAL_ATMEL_TTYAT is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SOC_AT91RM9200=y
-CONFIG_SOC_AT91SAM9=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_SAM9X60=y
-CONFIG_SOC_SAM_V4_V5=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_AT91_USART is not set
-CONFIG_SPI_ATMEL=y
-CONFIG_SPI_ATMEL_QUADSPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_ACM=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_AT91 is not set
-# CONFIG_USB_ATMEL_USBA is not set
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_AT91=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_AT91=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XXHASH=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_AT91=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_V4 is not set
+CONFIG_ARCH_MULTI_V4T=y
+CONFIG_ARCH_MULTI_V4_V5=y
+CONFIG_ARCH_MULTI_V5=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_AT91RM9200_WATCHDOG is not set
+CONFIG_AT91SAM9X_WATCHDOG=y
+# CONFIG_AT91_ADC is not set
+CONFIG_AT91_SAMA5D2_ADC=y
+CONFIG_AT91_SOC_ID=y
+# CONFIG_AT91_SOC_SFR is not set
+CONFIG_ATMEL_AIC5_IRQ=y
+CONFIG_ATMEL_AIC_IRQ=y
+CONFIG_ATMEL_CLOCKSOURCE_PIT=y
+CONFIG_ATMEL_CLOCKSOURCE_TCB=y
+CONFIG_ATMEL_EBI=y
+CONFIG_ATMEL_PIT=y
+CONFIG_ATMEL_PM=y
+CONFIG_ATMEL_SDRAMC=y
+CONFIG_ATMEL_SSC=y
+CONFIG_ATMEL_ST=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_AT_HDMAC=y
+CONFIG_AT_XDMAC=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_PM=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_AT91=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_ARM926T=y
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CRC16=y
+CONFIG_CRC7=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_ATMEL=y
+CONFIG_HZ=128
+CONFIG_HZ_FIXED=128
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_AT91=y
+# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_GPIO=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACB=y
+CONFIG_MACB_USE_HWSTAMP=y
+# CONFIG_MCHP_EIC is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MFD_AT91_USART=y
+CONFIG_MFD_ATMEL_FLEXCOM=y
+CONFIG_MFD_ATMEL_HLCDC=y
+CONFIG_MFD_ATMEL_SMC=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MICREL_PHY=y
+CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
+CONFIG_MICROCHIP_PIT64B=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_AT91=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_BLOCK is not set
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NLS=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_MICROCHIP_OTPC is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+# CONFIG_PINCTRL_AT91PIO4 is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_SLEEP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_AT91_POWEROFF=y
+CONFIG_POWER_RESET_AT91_RESET=y
+CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_ATMEL=y
+CONFIG_PWM_ATMEL_HLCDC_PWM=y
+CONFIG_PWM_ATMEL_TCB=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_SAMA5D4_WATCHDOG=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SOC_AT91RM9200=y
+CONFIG_SOC_AT91SAM9=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_SAM9X60=y
+CONFIG_SOC_SAM_V4_V5=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+# CONFIG_SPI_AT91_USART is not set
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_ATMEL_QUADSPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SRCU=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWPHY=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_ACM=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_AT91 is not set
+# CONFIG_USB_ATMEL_USBA is not set
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_AT91=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_AT91=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+# CONFIG_VFP is not set
+# CONFIG_VIDEO_ATMEL_XISC is not set
+# CONFIG_VIDEO_MICROCHIP_CSI2DC is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XXHASH=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AT91_CPUIDLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-CONFIG_AT91_ADC=y
-CONFIG_AT91_SAMA5D2_ADC=y
-CONFIG_AT91_SOC_ID=y
-# CONFIG_AT91_SOC_SFR is not set
-CONFIG_ATMEL_AIC5_IRQ=y
-# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
-CONFIG_ATMEL_CLOCKSOURCE_TCB=y
-CONFIG_ATMEL_EBI=y
-CONFIG_ATMEL_PM=y
-CONFIG_ATMEL_SDRAMC=y
-CONFIG_ATMEL_SSC=y
-CONFIG_ATMEL_TCB_CLKSRC=y
-CONFIG_AT_HDMAC=y
-CONFIG_AT_XDMAC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BATTERY_ACT8945A=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=4
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_PM=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_AT91=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRASH_DUMP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DEBUG_USER=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DNOTIFY=y
-CONFIG_DRM=y
-CONFIG_DRM_ATMEL_HLCDC=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_DP_AUX_BUS=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_PANEL_SIMPLE=y
-CONFIG_DTC=y
-CONFIG_DVB_CORE=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_ELF_CORE=y
-CONFIG_EXT4_FS=y
-CONFIG_FAT_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FORCE_MAX_ZONEORDER=15
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HDMI=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_ATMEL=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_AT91=y
-# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_LEDS=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-# CONFIG_JFFS2_FS is not set
-CONFIG_KCMP=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_QT1070=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACB=y
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_ATTACH=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_TEST_SUPPORT=y
-CONFIG_MEDIA_TUNER=y
-CONFIG_MEDIA_USB_SUPPORT=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_ACT8945A=y
-CONFIG_MFD_AT91_USART=y
-CONFIG_MFD_ATMEL_FLEXCOM=y
-CONFIG_MFD_ATMEL_HLCDC=y
-CONFIG_MFD_ATMEL_SMC=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICREL_PHY=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_AT91=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_BLOCK is not set
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-# CONFIG_NEON is not set
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MICROCHIP_OTPC is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AT91=y
-CONFIG_PINCTRL_AT91PIO4=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_AT91_POWEROFF=y
-CONFIG_POWER_RESET_AT91_RESET=y
-CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_PROC_VMCORE=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_PWM_ATMEL_HLCDC_PWM=y
-CONFIG_PWM_ATMEL_TCB=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ACT8865=y
-CONFIG_REGULATOR_ACT8945A=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-# CONFIG_RTC_DRV_AT91SAM9 is not set
-# CONFIG_RTC_DRV_CMOS is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_SAMA5D4_WATCHDOG=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_SERIAL_ATMEL_PDC=y
-# CONFIG_SERIAL_ATMEL_TTYAT is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SND=y
-CONFIG_SND_ARM=y
-# CONFIG_SND_AT73C213 is not set
-# CONFIG_SND_AT91_SOC_SAM9G20_WM8731 is not set
-# CONFIG_SND_AT91_SOC_SAM9X5_WM8731 is not set
-CONFIG_SND_ATMEL_SOC=y
-CONFIG_SND_ATMEL_SOC_CLASSD=y
-CONFIG_SND_ATMEL_SOC_DMA=y
-CONFIG_SND_ATMEL_SOC_I2S=y
-CONFIG_SND_ATMEL_SOC_PDC=y
-# CONFIG_SND_ATMEL_SOC_PDMIC is not set
-CONFIG_SND_ATMEL_SOC_SSC=y
-CONFIG_SND_ATMEL_SOC_SSC_DMA=y
-# CONFIG_SND_ATMEL_SOC_SSC_PDC is not set
-# CONFIG_SND_ATMEL_SOC_TSE850_PCM5142 is not set
-CONFIG_SND_ATMEL_SOC_WM8904=y
-# CONFIG_SND_COMPRESS_OFFLOAD is not set
-CONFIG_SND_DMAENGINE_PCM=y
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-# CONFIG_SND_MCHP_SOC_I2S_MCC is not set
-# CONFIG_SND_MCHP_SOC_SPDIFRX is not set
-# CONFIG_SND_MCHP_SOC_SPDIFTX is not set
-CONFIG_SND_PCM=y
-CONFIG_SND_PCM_TIMER=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-CONFIG_SND_SOC_MIKROE_PROTO=y
-CONFIG_SND_SOC_WM8731=y
-CONFIG_SND_SOC_WM8904=y
-CONFIG_SND_SPI=y
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_TIMER=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_SAMA5=y
-CONFIG_SOC_SAMA5D2=y
-CONFIG_SOC_SAMA5D3=y
-CONFIG_SOC_SAMA5D4=y
-# CONFIG_SOC_SAMA7G5 is not set
-CONFIG_SOC_SAM_V7=y
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_AT91_USART is not set
-CONFIG_SPI_ATMEL=y
-CONFIG_SPI_ATMEL_QUADSPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SQUASHFS is not set
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-# CONFIG_STANDALONE is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_SYNC_FILE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_TOUCHSCREEN_ATMEL_MXT=y
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_ACM=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_AT91 is not set
-# CONFIG_USB_ATMEL_USBA is not set
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_AT91=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_HID=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_AT91=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-# CONFIG_USB_PWC is not set
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VIDEOMODE_HELPERS=y
-# CONFIG_VIDEO_CPIA2 is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XXHASH=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_AT91=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AT91_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AT91SAM9X_WATCHDOG=y
+CONFIG_AT91_ADC=y
+CONFIG_AT91_SAMA5D2_ADC=y
+CONFIG_AT91_SOC_ID=y
+# CONFIG_AT91_SOC_SFR is not set
+CONFIG_ATMEL_AIC5_IRQ=y
+# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
+CONFIG_ATMEL_CLOCKSOURCE_TCB=y
+CONFIG_ATMEL_EBI=y
+CONFIG_ATMEL_PM=y
+CONFIG_ATMEL_SDRAMC=y
+# CONFIG_ATMEL_SECURE_PM is not set
+CONFIG_ATMEL_SSC=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_AT_HDMAC=y
+CONFIG_AT_XDMAC=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BATTERY_ACT8945A=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_PM=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_AT91=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_USER=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DRM=y
+CONFIG_DRM_ATMEL_HLCDC=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_GEM_DMA_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_NOMODESET=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DTC=y
+CONFIG_DVB_CORE=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_ELF_CORE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_ATMEL=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_AT91=y
+# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_KCMP=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_QT1070=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACB=y
+CONFIG_MACB_USE_HWSTAMP=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MCHP_EIC is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_TEST_SUPPORT=y
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_ACT8945A=y
+CONFIG_MFD_AT91_USART=y
+CONFIG_MFD_ATMEL_FLEXCOM=y
+CONFIG_MFD_ATMEL_HLCDC=y
+CONFIG_MFD_ATMEL_SMC=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MICREL_PHY=y
+# CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B is not set
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_AT91=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_BLOCK is not set
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_NEON is not set
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_MICROCHIP_OTPC is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_PINCTRL_AT91PIO4=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_SLEEP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_AT91_POWEROFF=y
+CONFIG_POWER_RESET_AT91_RESET=y
+CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_ATMEL=y
+CONFIG_PWM_ATMEL_HLCDC_PWM=y
+CONFIG_PWM_ATMEL_TCB=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ACT8865=y
+CONFIG_REGULATOR_ACT8945A=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_SAMA5D4_WATCHDOG=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SND=y
+CONFIG_SND_ARM=y
+# CONFIG_SND_AT73C213 is not set
+# CONFIG_SND_AT91_SOC_SAM9G20_WM8731 is not set
+# CONFIG_SND_AT91_SOC_SAM9X5_WM8731 is not set
+CONFIG_SND_ATMEL_SOC=y
+CONFIG_SND_ATMEL_SOC_CLASSD=y
+CONFIG_SND_ATMEL_SOC_DMA=y
+CONFIG_SND_ATMEL_SOC_I2S=y
+CONFIG_SND_ATMEL_SOC_PDC=y
+# CONFIG_SND_ATMEL_SOC_PDMIC is not set
+CONFIG_SND_ATMEL_SOC_SSC=y
+CONFIG_SND_ATMEL_SOC_SSC_DMA=y
+# CONFIG_SND_ATMEL_SOC_SSC_PDC is not set
+# CONFIG_SND_ATMEL_SOC_TSE850_PCM5142 is not set
+CONFIG_SND_ATMEL_SOC_WM8904=y
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+CONFIG_SND_DMAENGINE_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+# CONFIG_SND_MCHP_SOC_I2S_MCC is not set
+# CONFIG_SND_MCHP_SOC_PDMC is not set
+# CONFIG_SND_MCHP_SOC_SPDIFRX is not set
+# CONFIG_SND_MCHP_SOC_SPDIFTX is not set
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_MIKROE_PROTO=y
+CONFIG_SND_SOC_WM8731=y
+CONFIG_SND_SOC_WM8904=y
+CONFIG_SND_SPI=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_TIMER=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_LAN966 is not set
+CONFIG_SOC_SAMA5=y
+CONFIG_SOC_SAMA5D2=y
+CONFIG_SOC_SAMA5D3=y
+CONFIG_SOC_SAMA5D4=y
+# CONFIG_SOC_SAMA7G5 is not set
+CONFIG_SOC_SAM_V7=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+# CONFIG_SPI_AT91_USART is not set
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_ATMEL_QUADSPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SQUASHFS is not set
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SRCU=y
+# CONFIG_STANDALONE is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWPHY=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SYNC_FILE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_UBIFS_FS=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_ACM=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_AT91 is not set
+# CONFIG_USB_ATMEL_USBA is not set
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_AT91=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_HID=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_AT91=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+# CONFIG_USB_PWC is not set
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_VIDEO_ATMEL_XISC is not set
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIDEO_DEV=y
+# CONFIG_VIDEO_MICROCHIP_CSI2DC is not set
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XXHASH=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_ALLOW_DEV_COREDUMP is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_PATCH_IDIV is not set
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-# CONFIG_AT91SAM9X_WATCHDOG is not set
-# CONFIG_AT91_ADC is not set
-CONFIG_AT91_SAMA5D2_ADC=y
-CONFIG_AT91_SOC_ID=y
-# CONFIG_AT91_SOC_SFR is not set
-CONFIG_ATMEL_CLOCKSOURCE_TCB=y
-# CONFIG_ATMEL_EBI is not set
-CONFIG_ATMEL_SDRAMC=y
-CONFIG_ATMEL_TCB_CLKSRC=y
-# CONFIG_AT_HDMAC is not set
-CONFIG_AT_XDMAC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CAN=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=9
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=256
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk nocache ignore_loglevel"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_AT91=y
-# CONFIG_COMPACTION is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_SPECTRE=y
-# CONFIG_CPU_SW_DOMAIN_PAN is not set
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_AT91_SAMA7G5_FLEXCOM3=y
-CONFIG_DEBUG_AT91_UART=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/at91.S"
-CONFIG_DEBUG_UART_PHYS=0xe1824200
-CONFIG_DEBUG_UART_VIRT=0xe0824200
-# CONFIG_DEBUG_UNCOMPRESS is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-# CONFIG_EFI_PARTITION is not set
-CONFIG_EXT4_FS=y
-CONFIG_FANOTIFY=y
-CONFIG_FAT_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FORCE_MAX_ZONEORDER=15
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRACE_PERIOD=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_AT91=y
-# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_CONFIGFS=y
-# CONFIG_IIO_HRTIMER_TRIGGER is not set
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_SW_TRIGGER=y
-# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_BOOTP is not set
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_RARP is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCKD=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_LSM="N"
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACB=y
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_SUPPORT_FILTER=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_AT91_USART=y
-CONFIG_MFD_ATMEL_FLEXCOM=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICREL_PHY=y
-CONFIG_MICROCHIP_PIT64B=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-# CONFIG_MMC_ATMELMCI is not set
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_AT91=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEON=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NFS_FS=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MICROCHIP_OTPC is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCCARD=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AT91=y
-CONFIG_PINCTRL_AT91PIO4=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_AT91_POWEROFF is not set
-CONFIG_POWER_RESET_AT91_RESET=y
-CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
-CONFIG_PPS=y
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MCP16502=y
-CONFIG_ROOT_NFS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_SAMA5D4_WATCHDOG=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_SERIAL_ATMEL_PDC=y
-# CONFIG_SERIAL_ATMEL_TTYAT is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SND=y
-CONFIG_SND_ATMEL_SOC=y
-# CONFIG_SND_ATMEL_SOC_CLASSD is not set
-# CONFIG_SND_ATMEL_SOC_I2S is not set
-# CONFIG_SND_ATMEL_SOC_PDMIC is not set
-# CONFIG_SND_COMPRESS_OFFLOAD is not set
-CONFIG_SND_DMAENGINE_PCM=y
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_MCHP_SOC_I2S_MCC=y
-CONFIG_SND_MCHP_SOC_SPDIFRX=y
-CONFIG_SND_MCHP_SOC_SPDIFTX=y
-CONFIG_SND_PCM=y
-CONFIG_SND_SIMPLE_CARD=y
-CONFIG_SND_SIMPLE_CARD_UTILS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_MIKROE_PROTO is not set
-CONFIG_SND_SOC_PCM5102A=y
-CONFIG_SND_SOC_SPDIF=y
-CONFIG_SOC_BUS=y
-# CONFIG_SOC_SAMA5D2 is not set
-# CONFIG_SOC_SAMA5D3 is not set
-# CONFIG_SOC_SAMA5D4 is not set
-CONFIG_SOC_SAMA7=y
-CONFIG_SOC_SAMA7G5=y
-CONFIG_SOC_SAM_V7=y
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_AT91_USART is not set
-CONFIG_SPI_ATMEL=y
-# CONFIG_SPI_ATMEL_QUADSPI is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-# CONFIG_STANDALONE is not set
-CONFIG_SUNRPC=y
-# CONFIG_SWAP is not set
-CONFIG_SWPHY=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USE_OF=y
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-# CONFIG_VIDEO_ATMEL_XISC is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_AT91=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_PATCH_IDIV is not set
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+# CONFIG_AT91SAM9X_WATCHDOG is not set
+# CONFIG_AT91_ADC is not set
+CONFIG_AT91_SAMA5D2_ADC=y
+CONFIG_AT91_SOC_ID=y
+# CONFIG_AT91_SOC_SFR is not set
+CONFIG_ATMEL_CLOCKSOURCE_TCB=y
+# CONFIG_ATMEL_EBI is not set
+CONFIG_ATMEL_SDRAMC=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+# CONFIG_AT_HDMAC is not set
+CONFIG_AT_XDMAC=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CAN=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=9
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=256
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk nocache ignore_loglevel"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_AT91=y
+# CONFIG_COMPACTION is not set
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_SPECTRE=y
+# CONFIG_CPU_SW_DOMAIN_PAN is not set
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECC=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_AT91_SAMA7G5_FLEXCOM3=y
+CONFIG_DEBUG_AT91_UART=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="debug/at91.S"
+CONFIG_DEBUG_UART_PHYS=0xe1824200
+CONFIG_DEBUG_UART_VIRT=0xe0824200
+CONFIG_DEBUG_USER=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMATEST=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ENGINE_RAID=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_FAT_FS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GRACE_PERIOD=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_AT91=y
+# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_CONFIGFS=y
+# CONFIG_IIO_HRTIMER_TRIGGER is not set
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_SW_TRIGGER=y
+# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_BOOTP is not set
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCKD=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_LSM="N"
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACB=y
+CONFIG_MACB_USE_HWSTAMP=y
+# CONFIG_MCHP_EIC is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
+CONFIG_MFD_AT91_USART=y
+CONFIG_MFD_ATMEL_FLEXCOM=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MICREL_PHY=y
+CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
+CONFIG_MICROCHIP_PIT64B=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+# CONFIG_MMC_ATMELMCI is not set
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_AT91=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NEON=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NFS_FS=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_MICROCHIP_OTPC is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCCARD=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_AT91_POWEROFF is not set
+CONFIG_POWER_RESET_AT91_RESET=y
+CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_ATMEL=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_MCP16502=y
+CONFIG_ROOT_NFS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_SAMA5D4_WATCHDOG=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SND=y
+CONFIG_SND_ATMEL_SOC=y
+# CONFIG_SND_ATMEL_SOC_CLASSD is not set
+# CONFIG_SND_ATMEL_SOC_I2S is not set
+# CONFIG_SND_ATMEL_SOC_PDMIC is not set
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+CONFIG_SND_DMAENGINE_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_MCHP_SOC_I2S_MCC=y
+# CONFIG_SND_MCHP_SOC_PDMC is not set
+CONFIG_SND_MCHP_SOC_SPDIFRX=y
+CONFIG_SND_MCHP_SOC_SPDIFTX=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SIMPLE_CARD_UTILS=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_MIKROE_PROTO is not set
+CONFIG_SND_SOC_PCM5102A=y
+CONFIG_SND_SOC_SPDIF=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_LAN966 is not set
+# CONFIG_SOC_SAMA5D2 is not set
+# CONFIG_SOC_SAMA5D3 is not set
+# CONFIG_SOC_SAMA5D4 is not set
+CONFIG_SOC_SAMA7=y
+CONFIG_SOC_SAMA7G5=y
+CONFIG_SOC_SAM_V7=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+# CONFIG_SPI_AT91_USART is not set
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_ATMEL_QUADSPI is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SRCU=y
+CONFIG_STACKTRACE=y
+# CONFIG_STANDALONE is not set
+CONFIG_SUNRPC=y
+# CONFIG_SWAP is not set
+CONFIG_SWPHY=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USE_OF=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_VIDEO_ATMEL_XISC is not set
+CONFIG_VIDEO_DEV=y
+# CONFIG_VIDEO_MICROCHIP_CSI2DC is not set
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
FEATURES:=ramdisk squashfs usbgadget
KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
CONFIG_GPIO_ATH79=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_GENERIC=y
-# CONFIG_GPIO_LATCH is not set
+# CONFIG_GPIO_LATCH_MIKROTIK is not set
# CONFIG_GPIO_RB91X_KEY is not set
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
--- /dev/null
+CONFIG_AG71XX=y
+# CONFIG_AG71XX_DEBUG is not set
+CONFIG_AG71XX_DEBUG_FS=y
+CONFIG_AR8216_PHY=y
+CONFIG_AR8216_PHY_LEDS=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_AT803X_PHY=y
+CONFIG_ATH79=y
+CONFIG_ATH79_WDT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_74X164=y
+CONFIG_GPIO_ATH79=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+# CONFIG_GPIO_LATCH_MIKROTIK is not set
+# CONFIG_GPIO_RB91X_KEY is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_RESET is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=y
+# CONFIG_MFD_RB4XX_CPLD is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+CONFIG_MTD_PARSER_CYBERTAN=y
+# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_ELF_FW=y
+CONFIG_MTD_SPLIT_LZMA_FW=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_SPLIT_WRGG_FW=y
+CONFIG_MTD_VIRT_CONCAT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCI_AR71XX=y
+CONFIG_PCI_AR724X=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_AR7100_USB is not set
+# CONFIG_PHY_AR7200_USB is not set
+# CONFIG_PHY_ATH79_USB is not set
+CONFIG_PINCTRL=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_RESET_ATH79=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_AR933X=y
+CONFIG_SERIAL_AR933X_CONSOLE=y
+CONFIG_SERIAL_AR933X_NR_UARTS=2
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_AR934X=y
+CONFIG_SPI_ATH79=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_RB4XX is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
};
gpio_latch: gpio_latch {
- compatible = "gpio-latch";
+ compatible = "gpio-latch-mikrotik";
gpio-controller;
#gpio-cells = <2>;
gpios = <&gpio 0 GPIO_ACTIVE_HIGH>,
interrupts = <4>;
phy-mode = "mii";
+ syscon-no-reset;
mdio0: mdio {
status = "disabled";
interrupts = <5>;
phy-mode = "mii";
+ syscon-no-reset;
mdio1: mdio {
status = "disabled";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca953x.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "comfast,cf-ew71-v2", "qca,qca9531";
+ model = "COMFAST CF-EW71 v2";
+
+ aliases {
+ serial0 = &uart;
+ led-boot = &led_wan;
+ led-failsafe = &led_wan;
+ led-upgrade = &led_wan;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&jtag_disable_pins>;
+
+ lan {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ };
+
+ led_wan: wan {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+ };
+
+ wlan {
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy0tpt";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+ debounce-interval = <60>;
+ };
+ };
+
+ watchdog {
+ compatible = "linux,wdt-gpio";
+
+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+ hw_algo = "toggle";
+ hw_margin_ms = <1200>;
+ always-running;
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&spi {
+ status = "okay";
+
+ flash@0 {
+ compatible = "winbond,w25q128", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x000000 0x010000>;
+ read-only;
+ };
+
+ art: partition@10000 {
+ label = "art";
+ reg = <0x010000 0x010000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_art_0: macaddr@0 {
+ compatible = "mac-base";
+ reg = <0x0 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ partition@20000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x020000 0xfd0000>;
+ };
+
+ partition@ff0000 {
+ label = "nvram";
+ reg = <0xff0000 0x010000>;
+ read-only;
+ };
+ };
+ };
+};
+
+ð0 {
+ status = "okay";
+
+ phy-handle = <&swphy4>;
+
+ nvmem-cells = <&macaddr_art_0 1>;
+ nvmem-cell-names = "mac-address";
+};
+
+ð1 {
+ nvmem-cells = <&macaddr_art_0 0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&wmac {
+ status = "okay";
+
+ mtd-cal-data = <&art 0x1000>;
+ nvmem-cells = <&macaddr_art_0 3>;
+ nvmem-cell-names = "mac-address";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca955x_senao_loader.dtsi"
+
+&partitions {
+ partition@ff0000 {
+ label = "art";
+ reg = <0xff0000 0x010000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_art_0: macaddr@0 {
+ compatible = "mac-base";
+ reg = <0x0 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ calibration_art_1000: calibration@1000 {
+ reg = <0x1000 0x440>;
+ };
+
+ calibration_art_5000: calibration@5000 {
+ reg = <0x5000 0x844>;
+ };
+ };
+ };
+};
+
+&mdio0 {
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ eee-broken-100tx;
+ eee-broken-1000t;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ eee-broken-100tx;
+ eee-broken-1000t;
+ at803x-override-sgmii-link-check;
+ };
+};
+
+ð0 {
+ status = "okay";
+
+ nvmem-cells = <&macaddr_art_0 0>;
+ nvmem-cell-names = "mac-address";
+
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+
+ pll-data = <0x82000000 0x80000101 0x80001313>;
+};
+
+ð1 {
+ status = "okay";
+
+ nvmem-cells = <&macaddr_art_0 1>;
+ nvmem-cell-names = "mac-address";
+
+ phy-handle = <&phy2>;
+
+ pll-data = <0x03000000 0x00000101 0x00001313>;
+
+ qca955x-sgmii-fixup;
+};
+
+&wmac {
+ status = "okay";
+
+ nvmem-cells = <&macaddr_art_0 2>, <&calibration_art_1000>;
+ nvmem-cell-names = "mac-address", "calibration";
+};
+
+&ath10k_1 {
+ nvmem-cells = <&macaddr_art_0 3>, <&calibration_art_5000>;
+ nvmem-cell-names = "mac-address", "calibration";
+};
+
+&pcie1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca9558_engenius_dual_ap.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "engenius,ens1750", "qca,qca9558";
+ model = "EnGenius ENS1750";
+
+ aliases {
+ label-mac-device = ð0;
+ led-boot = &led_wifi5g;
+ led-failsafe = &led_wifi5g;
+ led-upgrade = &led_wifi5g;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
+ debounce-interval = <60>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ wifi2g {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_2GHZ;
+ gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy1tpt";
+ };
+
+ led_wifi5g: wifi5g {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_5GHZ;
+ gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy0tpt";
+ };
+ };
+};
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include "qca955x_senao_loader.dtsi"
+#include "qca9558_engenius_dual_ap.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
/ {
compatible = "engenius,ews660ap", "qca,qca9558";
compatible = "gpio-leds";
wifi2g {
- label = "green:wifi2g";
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_2GHZ;
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
led_wifi5g: wifi5g {
- label = "green:wifi5g";
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_5GHZ;
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
};
};
-
-&partitions {
- partition@ff0000 {
- label = "art";
- reg = <0xff0000 0x010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- calibration_art_1000: calibration@1000 {
- reg = <0x1000 0x440>;
- };
-
- calibration_art_5000: calibration@5000 {
- reg = <0x5000 0x844>;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- eee-broken-100tx;
- eee-broken-1000t;
- };
-
- phy2: ethernet-phy@2 {
- reg = <2>;
- eee-broken-100tx;
- eee-broken-1000t;
- at803x-override-sgmii-link-check;
- };
-};
-
-ð0 {
- status = "okay";
-
- nvmem-cells = <&macaddr_art_0 0>;
- nvmem-cell-names = "mac-address";
-
- phy-handle = <&phy1>;
- phy-mode = "rgmii-id";
-
- pll-data = <0x82000000 0x80000101 0x80001313>;
-};
-
-ð1 {
- status = "okay";
-
- nvmem-cells = <&macaddr_art_0 1>;
- nvmem-cell-names = "mac-address";
-
- phy-handle = <&phy2>;
-
- pll-data = <0x03000000 0x00000101 0x00001313>;
-
- qca955x-sgmii-fixup;
-};
-
-&wmac {
- status = "okay";
-
- nvmem-cells = <&macaddr_art_0 2>, <&calibration_art_1000>;
- nvmem-cell-names = "mac-address", "calibration";
-};
-
-&ath10k_1 {
- status = "okay";
-
- nvmem-cells = <&macaddr_art_0 3>, <&calibration_art_5000>;
- nvmem-cell-names = "mac-address", "calibration";
-};
-
-&pcie1 {
- status = "okay";
-};
};
partition@40000 {
+ compatible = "u-boot,env";
label = "u-boot-env";
reg = <0x040000 0x010000>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * GPIO latch driver
+ *
+ * Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/gpio/consumer.h>
+#include <linux/gpio/driver.h>
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
+
+#define GPIO_LATCH_DRIVER_NAME "gpio-latch-mikrotik"
+#define GPIO_LATCH_LINES 9
+
+struct gpio_latch_chip {
+ struct gpio_chip gc;
+ struct mutex mutex;
+ struct mutex latch_mutex;
+ bool latch_enabled;
+ int le_gpio;
+ bool le_active_low;
+ struct gpio_desc *gpios[GPIO_LATCH_LINES];
+};
+
+static inline struct gpio_latch_chip *to_gpio_latch_chip(struct gpio_chip *gc)
+{
+ return container_of(gc, struct gpio_latch_chip, gc);
+}
+
+static void gpio_latch_lock(struct gpio_latch_chip *glc, bool enable)
+{
+ mutex_lock(&glc->mutex);
+
+ if (enable)
+ glc->latch_enabled = true;
+
+ if (glc->latch_enabled)
+ mutex_lock(&glc->latch_mutex);
+}
+
+static void gpio_latch_unlock(struct gpio_latch_chip *glc, bool disable)
+{
+ if (glc->latch_enabled)
+ mutex_unlock(&glc->latch_mutex);
+
+ if (disable)
+ glc->latch_enabled = true;
+
+ mutex_unlock(&glc->mutex);
+}
+
+static int
+gpio_latch_get(struct gpio_chip *gc, unsigned offset)
+{
+ struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
+ int ret;
+
+ gpio_latch_lock(glc, false);
+ ret = gpiod_get_raw_value_cansleep(glc->gpios[offset]);
+ gpio_latch_unlock(glc, false);
+
+ return ret;
+}
+
+static void
+gpio_latch_set(struct gpio_chip *gc, unsigned offset, int value)
+{
+ struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
+ bool enable_latch = false;
+ bool disable_latch = false;
+
+ if (offset == glc->le_gpio) {
+ enable_latch = value ^ glc->le_active_low;
+ disable_latch = !enable_latch;
+ }
+
+ gpio_latch_lock(glc, enable_latch);
+ gpiod_set_raw_value_cansleep(glc->gpios[offset], value);
+ gpio_latch_unlock(glc, disable_latch);
+}
+
+static int
+gpio_latch_direction_output(struct gpio_chip *gc, unsigned offset, int value)
+{
+ struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
+ bool enable_latch = false;
+ bool disable_latch = false;
+ int ret;
+
+ if (offset == glc->le_gpio) {
+ enable_latch = value ^ glc->le_active_low;
+ disable_latch = !enable_latch;
+ }
+
+ gpio_latch_lock(glc, enable_latch);
+ ret = gpiod_direction_output_raw(glc->gpios[offset], value);
+ gpio_latch_unlock(glc, disable_latch);
+
+ return ret;
+}
+
+static int gpio_latch_probe(struct platform_device *pdev)
+{
+ struct gpio_latch_chip *glc;
+ struct gpio_chip *gc;
+ struct device *dev = &pdev->dev;
+ struct fwnode_handle *fwnode = dev->fwnode;
+ int i, n;
+
+ glc = devm_kzalloc(dev, sizeof(*glc), GFP_KERNEL);
+ if (!glc)
+ return -ENOMEM;
+
+ mutex_init(&glc->mutex);
+ mutex_init(&glc->latch_mutex);
+
+ n = gpiod_count(dev, NULL);
+ if (n <= 0) {
+ dev_err(dev, "failed to get gpios: %d\n", n);
+ return n;
+ } else if (n != GPIO_LATCH_LINES) {
+ dev_err(dev, "expected %d gpios\n", GPIO_LATCH_LINES);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < n; i++) {
+ glc->gpios[i] = devm_gpiod_get_index_optional(dev, NULL, i,
+ GPIOD_OUT_LOW);
+ if (IS_ERR(glc->gpios[i])) {
+ if (PTR_ERR(glc->gpios[i]) != -EPROBE_DEFER) {
+ dev_err(dev, "failed to get gpio %d: %ld\n", i,
+ PTR_ERR(glc->gpios[i]));
+ }
+ return PTR_ERR(glc->gpios[i]);
+ }
+ }
+
+ glc->le_gpio = 8;
+ glc->le_active_low = gpiod_is_active_low(glc->gpios[glc->le_gpio]);
+
+ if (!glc->gpios[glc->le_gpio]) {
+ dev_err(dev, "missing required latch-enable gpio %d\n",
+ glc->le_gpio);
+ return -EINVAL;
+ }
+
+ gc = &glc->gc;
+ gc->label = GPIO_LATCH_DRIVER_NAME;
+ gc->can_sleep = true;
+ gc->base = -1;
+ gc->ngpio = GPIO_LATCH_LINES;
+ gc->get = gpio_latch_get;
+ gc->set = gpio_latch_set;
+ gc->direction_output = gpio_latch_direction_output;
+ gc->fwnode = fwnode;
+
+ platform_set_drvdata(pdev, glc);
+
+ i = gpiochip_add(&glc->gc);
+ if (i) {
+ dev_err(dev, "gpiochip_add() failed: %d\n", i);
+ return i;
+ }
+
+ return 0;
+}
+
+static int gpio_latch_remove(struct platform_device *pdev)
+{
+ struct gpio_latch_chip *glc = platform_get_drvdata(pdev);
+
+ gpiochip_remove(&glc->gc);
+ return 0;
+}
+
+static const struct of_device_id gpio_latch_match[] = {
+ { .compatible = GPIO_LATCH_DRIVER_NAME },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, gpio_latch_match);
+
+static struct platform_driver gpio_latch_driver = {
+ .probe = gpio_latch_probe,
+ .remove = gpio_latch_remove,
+ .driver = {
+ .name = GPIO_LATCH_DRIVER_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = gpio_latch_match,
+ },
+};
+
+module_platform_driver(gpio_latch_driver);
+
+MODULE_DESCRIPTION("GPIO latch driver");
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_AUTHOR("Denis Kalashnikov <denis281089@gmail.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" GPIO_LATCH_DRIVER_NAME);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * GPIO latch driver
- *
- * Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/gpio/consumer.h>
-#include <linux/gpio/driver.h>
-#include <linux/platform_device.h>
-#include <linux/of_platform.h>
-#include <linux/of_gpio.h>
-
-#define GPIO_LATCH_DRIVER_NAME "gpio-latch"
-#define GPIO_LATCH_LINES 9
-
-struct gpio_latch_chip {
- struct gpio_chip gc;
- struct mutex mutex;
- struct mutex latch_mutex;
- bool latch_enabled;
- int le_gpio;
- bool le_active_low;
- struct gpio_desc *gpios[GPIO_LATCH_LINES];
-};
-
-static inline struct gpio_latch_chip *to_gpio_latch_chip(struct gpio_chip *gc)
-{
- return container_of(gc, struct gpio_latch_chip, gc);
-}
-
-static void gpio_latch_lock(struct gpio_latch_chip *glc, bool enable)
-{
- mutex_lock(&glc->mutex);
-
- if (enable)
- glc->latch_enabled = true;
-
- if (glc->latch_enabled)
- mutex_lock(&glc->latch_mutex);
-}
-
-static void gpio_latch_unlock(struct gpio_latch_chip *glc, bool disable)
-{
- if (glc->latch_enabled)
- mutex_unlock(&glc->latch_mutex);
-
- if (disable)
- glc->latch_enabled = true;
-
- mutex_unlock(&glc->mutex);
-}
-
-static int
-gpio_latch_get(struct gpio_chip *gc, unsigned offset)
-{
- struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
- int ret;
-
- gpio_latch_lock(glc, false);
- ret = gpiod_get_raw_value_cansleep(glc->gpios[offset]);
- gpio_latch_unlock(glc, false);
-
- return ret;
-}
-
-static void
-gpio_latch_set(struct gpio_chip *gc, unsigned offset, int value)
-{
- struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
- bool enable_latch = false;
- bool disable_latch = false;
-
- if (offset == glc->le_gpio) {
- enable_latch = value ^ glc->le_active_low;
- disable_latch = !enable_latch;
- }
-
- gpio_latch_lock(glc, enable_latch);
- gpiod_set_raw_value_cansleep(glc->gpios[offset], value);
- gpio_latch_unlock(glc, disable_latch);
-}
-
-static int
-gpio_latch_direction_output(struct gpio_chip *gc, unsigned offset, int value)
-{
- struct gpio_latch_chip *glc = to_gpio_latch_chip(gc);
- bool enable_latch = false;
- bool disable_latch = false;
- int ret;
-
- if (offset == glc->le_gpio) {
- enable_latch = value ^ glc->le_active_low;
- disable_latch = !enable_latch;
- }
-
- gpio_latch_lock(glc, enable_latch);
- ret = gpiod_direction_output_raw(glc->gpios[offset], value);
- gpio_latch_unlock(glc, disable_latch);
-
- return ret;
-}
-
-static int gpio_latch_probe(struct platform_device *pdev)
-{
- struct gpio_latch_chip *glc;
- struct gpio_chip *gc;
- struct device *dev = &pdev->dev;
- struct device_node *of_node = dev->of_node;
- int i, n;
-
- glc = devm_kzalloc(dev, sizeof(*glc), GFP_KERNEL);
- if (!glc)
- return -ENOMEM;
-
- mutex_init(&glc->mutex);
- mutex_init(&glc->latch_mutex);
-
- n = gpiod_count(dev, NULL);
- if (n <= 0) {
- dev_err(dev, "failed to get gpios: %d\n", n);
- return n;
- } else if (n != GPIO_LATCH_LINES) {
- dev_err(dev, "expected %d gpios\n", GPIO_LATCH_LINES);
- return -EINVAL;
- }
-
- for (i = 0; i < n; i++) {
- glc->gpios[i] = devm_gpiod_get_index_optional(dev, NULL, i,
- GPIOD_OUT_LOW);
- if (IS_ERR(glc->gpios[i])) {
- if (PTR_ERR(glc->gpios[i]) != -EPROBE_DEFER) {
- dev_err(dev, "failed to get gpio %d: %ld\n", i,
- PTR_ERR(glc->gpios[i]));
- }
- return PTR_ERR(glc->gpios[i]);
- }
- }
-
- glc->le_gpio = 8;
- glc->le_active_low = gpiod_is_active_low(glc->gpios[glc->le_gpio]);
-
- if (!glc->gpios[glc->le_gpio]) {
- dev_err(dev, "missing required latch-enable gpio %d\n",
- glc->le_gpio);
- return -EINVAL;
- }
-
- gc = &glc->gc;
- gc->label = GPIO_LATCH_DRIVER_NAME;
- gc->can_sleep = true;
- gc->base = -1;
- gc->ngpio = GPIO_LATCH_LINES;
- gc->get = gpio_latch_get;
- gc->set = gpio_latch_set;
- gc->direction_output = gpio_latch_direction_output;
- gc->of_node = of_node;
-
- platform_set_drvdata(pdev, glc);
-
- i = gpiochip_add(&glc->gc);
- if (i) {
- dev_err(dev, "gpiochip_add() failed: %d\n", i);
- return i;
- }
-
- return 0;
-}
-
-static int gpio_latch_remove(struct platform_device *pdev)
-{
- struct gpio_latch_chip *glc = platform_get_drvdata(pdev);
-
- gpiochip_remove(&glc->gc);
- return 0;
-}
-
-static const struct of_device_id gpio_latch_match[] = {
- { .compatible = GPIO_LATCH_DRIVER_NAME },
- {},
-};
-
-MODULE_DEVICE_TABLE(of, gpio_latch_match);
-
-static struct platform_driver gpio_latch_driver = {
- .probe = gpio_latch_probe,
- .remove = gpio_latch_remove,
- .driver = {
- .name = GPIO_LATCH_DRIVER_NAME,
- .owner = THIS_MODULE,
- .of_match_table = gpio_latch_match,
- },
-};
-
-module_platform_driver(gpio_latch_driver);
-
-MODULE_DESCRIPTION("GPIO latch driver");
-MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-MODULE_AUTHOR("Denis Kalashnikov <denis281089@gmail.com>");
-MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:" GPIO_LATCH_DRIVER_NAME);
struct gpio_rb91x_key *drvdata;
struct gpio_chip *gc;
struct device *dev = &pdev->dev;
- struct device_node *of_node = dev->of_node;
+ struct fwnode_handle *fwnode = dev->fwnode;
int r;
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
gc->set = gpio_rb91x_key_set;
gc->direction_output = gpio_rb91x_key_direction_output;
gc->direction_input = gpio_rb91x_key_direction_input;
- gc->of_node = of_node;
+ gc->fwnode = fwnode;
platform_set_drvdata(pdev, drvdata);
int ring_mask = BIT(ring->order) - 1;
int ring_size = BIT(ring->order);
struct list_head rx_list;
- struct sk_buff *next;
struct sk_buff *skb;
int done = 0;
ag71xx_ring_rx_refill(ag);
- list_for_each_entry_safe(skb, next, &rx_list, list)
+ list_for_each_entry(skb, &rx_list, list)
skb->protocol = eth_type_trans(skb, dev);
netif_receive_skb_list(&rx_list);
ucidef_set_led_switch "lan3" "LAN3" "blue:lan3" "switch0" "0x08"
ucidef_set_led_switch "lan4" "LAN4" "blue:lan4" "switch0" "0x10"
;;
+comfast,cf-ew71-v2|\
comfast,cf-ew72|\
openmesh,om2p-v2|\
openmesh,om2p-hs-v1|\
elecom,wab-i1750-ps|\
elecom,wab-s1167-ps|\
elecom,wab-s600-ps|\
+ engenius,ens1750|\
engenius,enstationac-v1|\
engenius,ews511ap|\
engenius,ews660ap|\
engenius,eap300-v2|\
engenius,eap600|\
engenius,ecb600|\
+ engenius,ens1750|\
engenius,ens202ext-v1|\
engenius,enstationac-v1|\
engenius,ews660ap|\
endef
TARGET_DEVICES += comfast_cf-e560ac
+define Device/comfast_cf-ew71-v2
+ SOC := qca9531
+ DEVICE_VENDOR := COMFAST
+ DEVICE_MODEL := CF-EW71
+ DEVICE_VARIANT := v2
+ DEVICE_PACKAGES := kmod-usb2 -uboot-envtools -swconfig
+ IMAGE_SIZE := 16192k
+endef
+TARGET_DEVICES += comfast_cf-ew71-v2
+
define Device/comfast_cf-ew72
SOC := qca9531
DEVICE_VENDOR := COMFAST
endef
TARGET_DEVICES += engenius_ews511ap
-define Device/engenius_ews660ap
+define Device/engenius_ews_dual_ap
$(Device/senao_loader_okli)
SOC := qca9558
DEVICE_VENDOR := EnGenius
- DEVICE_MODEL := EWS660AP
DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct
IMAGE_SIZE := 11584k
LOADER_FLASH_OFFS := 0x220000
+endef
+
+define Device/engenius_ews660ap
+ $(Device/engenius_ews_dual_ap)
+ DEVICE_MODEL := EWS660AP
SENAO_IMGNAME := ar71xx-generic-ews660ap
endef
TARGET_DEVICES += engenius_ews660ap
+define Device/engenius_ens1750
+ $(Device/engenius_ews_dual_ap)
+ DEVICE_MODEL := ENS1750
+ SENAO_IMGNAME := ar71xx-generic-ens1750
+endef
+TARGET_DEVICES += engenius_ens1750
+
define Device/enterasys_ws-ap3705i
SOC := ar9344
DEVICE_VENDOR := Enterasys
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_ZSTD=y
-CONFIG_GPIO_LATCH=y
+CONFIG_GPIO_LATCH_MIKROTIK=y
CONFIG_GPIO_RB4XX=y
CONFIG_GPIO_RB91X_KEY=y
CONFIG_GPIO_WATCHDOG=y
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
-@@ -2942,12 +2942,19 @@ static void spi_nor_set_mtd_info(struct
+@@ -2964,12 +2964,19 @@ static void spi_nor_set_mtd_info(struct
{
struct mtd_info *mtd = &nor->mtd;
struct device *dev = nor->dev;
goto next_ht;
--- a/net/ipv6/ip6_offload.c
+++ b/net/ipv6/ip6_offload.c
-@@ -259,7 +259,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
+@@ -290,7 +290,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
continue;
iph2 = (struct ipv6hdr *)(p->data + off);
--- a/net/ipv4/tcp_offload.c
+++ b/net/ipv4/tcp_offload.c
-@@ -220,7 +220,7 @@ struct sk_buff *tcp_gro_receive(struct l
+@@ -62,7 +62,7 @@ static struct sk_buff *__tcpv4_gso_segme
+ th2 = tcp_hdr(seg->next);
+ iph2 = ip_hdr(seg->next);
- th2 = tcp_hdr(p);
+- if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++ if (!(net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) &&
+ iph->daddr == iph2->daddr && iph->saddr == iph2->saddr)
+ return segs;
+
+@@ -254,7 +254,7 @@ struct sk_buff *tcp_gro_lookup(struct li
+ continue;
+ th2 = tcp_hdr(p);
- if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
+ if (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) {
NAPI_GRO_CB(p)->same_flow = 0;
continue;
}
-@@ -238,8 +238,8 @@ found:
+@@ -320,8 +320,8 @@ struct sk_buff *tcp_gro_receive(struct l
~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH));
flush |= (__force int)(th->ack_seq ^ th2->ack_seq);
for (i = sizeof(*th); i < thlen; i += 4)
obj-$(CONFIG_MFD_INTEL_M10_BMC) += intel-m10-bmc.o
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
-@@ -1593,6 +1593,12 @@ config GPIO_SODAVILLE
+@@ -1594,6 +1594,12 @@ config GPIO_SODAVILLE
help
Say Y here to support Intel Sodaville GPIO.
If unsure, say N.
-+config GPIO_LATCH
++config GPIO_LATCH_MIKROTIK
+ tristate "MikroTik RouterBOARD GPIO latch support"
+ depends on ATH79
+ help
obj-$(CONFIG_GPIO_IXP4XX) += gpio-ixp4xx.o
obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o
obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o
-+obj-$(CONFIG_GPIO_LATCH) += gpio-latch.o
++obj-$(CONFIG_GPIO_LATCH_MIKROTIK) += gpio-latch-mikrotik.o
obj-$(CONFIG_GPIO_LOGICVC) += gpio-logicvc.o
obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o
obj-$(CONFIG_GPIO_LOONGSON) += gpio-loongson.o
--- /dev/null
+From 661edfc3dab943a67c8821353b63cc23057f7ce9 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Tue, 9 Jan 2024 20:48:46 +0100
+Subject: [PATCH] reset: ath79: read back reset register
+
+Read back the reset register in order to flush the cache. This fixes
+spurious reboot hangs on TP-Link TL-WDR3600 and TL-WDR4300 with Zentel
+DRAM chips.
+
+This issue was fixed in the past, but switching to the reset-driver
+specific implementation removed the old fix.
+
+Link: https://github.com/freifunk-gluon/gluon/issues/2904
+Link: https://github.com/openwrt/openwrt/issues/13043
+Link: https://dev.archive.openwrt.org/ticket/17839
+Link: f8a7bfe1cb2c ("MIPS: ath79: fix system restart")
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/reset/reset-ath79.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/reset/reset-ath79.c
++++ b/drivers/reset/reset-ath79.c
+@@ -37,6 +37,8 @@ static int ath79_reset_update(struct res
+ else
+ val &= ~BIT(id);
+ writel(val, ath79_reset->base);
++ /* Flush cache */
++ readl(ath79_reset->base);
+ spin_unlock_irqrestore(&ath79_reset->lock, flags);
+
+ return 0;
--- /dev/null
+From f3eacff2310a60348a755c50a8da6fc251fc8587 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 6 Mar 2018 09:55:13 +0100
+Subject: [PATCH 07/33] irqchip/irq-ath79-intc: add irq cascade driver for
+ QCA9556 SoCs
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/irqchip/Makefile | 1 +
+ drivers/irqchip/irq-ath79-intc.c | 142 +++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 143 insertions(+)
+ create mode 100644 drivers/irqchip/irq-ath79-intc.c
+
+--- a/drivers/irqchip/Makefile
++++ b/drivers/irqchip/Makefile
+@@ -4,6 +4,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
+ obj-$(CONFIG_AL_FIC) += irq-al-fic.o
+ obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
+ obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
++obj-$(CONFIG_ATH79) += irq-ath79-intc.o
+ obj-$(CONFIG_ATH79) += irq-ath79-misc.o
+ obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
+ obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
+--- /dev/null
++++ b/drivers/irqchip/irq-ath79-intc.c
+@@ -0,0 +1,142 @@
++/*
++ * Atheros AR71xx/AR724x/AR913x specific interrupt handling
++ *
++ * Copyright (C) 2018 John Crispin <john@phrozen.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/interrupt.h>
++#include <linux/irqchip.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/irqdomain.h>
++
++#include <asm/irq_cpu.h>
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#define ATH79_MAX_INTC_CASCADE 3
++
++struct ath79_intc {
++ struct irq_chip chip;
++ u32 irq;
++ u32 pending_mask;
++ u32 int_status;
++ u32 irq_mask[ATH79_MAX_INTC_CASCADE];
++ u32 irq_wb_chan[ATH79_MAX_INTC_CASCADE];
++};
++
++static void ath79_intc_irq_handler(struct irq_desc *desc)
++{
++ struct irq_domain *domain = irq_desc_get_handler_data(desc);
++ struct ath79_intc *intc = domain->host_data;
++ u32 pending;
++
++ pending = ath79_reset_rr(intc->int_status);
++ pending &= intc->pending_mask;
++
++ if (pending) {
++ int i;
++
++ for (i = 0; i < domain->hwirq_max; i++)
++ if (pending & intc->irq_mask[i]) {
++ if (intc->irq_wb_chan[i] != 0xffffffff)
++ ath79_ddr_wb_flush(intc->irq_wb_chan[i]);
++ generic_handle_irq(irq_find_mapping(domain, i));
++ }
++ } else {
++ spurious_interrupt();
++ }
++}
++
++static void ath79_intc_irq_enable(struct irq_data *d)
++{
++ struct ath79_intc *intc = d->domain->host_data;
++ enable_irq(intc->irq);
++}
++
++static void ath79_intc_irq_disable(struct irq_data *d)
++{
++ struct ath79_intc *intc = d->domain->host_data;
++ disable_irq(intc->irq);
++}
++
++static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
++{
++ struct ath79_intc *intc = d->host_data;
++
++ irq_set_chip_and_handler(irq, &intc->chip, handle_level_irq);
++
++ return 0;
++}
++
++static const struct irq_domain_ops ath79_irq_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = ath79_intc_map,
++};
++
++static int __init ath79_intc_of_init(
++ struct device_node *node, struct device_node *parent)
++{
++ struct irq_domain *domain;
++ struct ath79_intc *intc;
++ int cnt, cntwb, i, err;
++
++ cnt = of_property_count_u32_elems(node, "qca,pending-bits");
++ if (cnt > ATH79_MAX_INTC_CASCADE)
++ panic("Too many INTC pending bits\n");
++
++ intc = kzalloc(sizeof(*intc), GFP_KERNEL);
++ if (!intc)
++ panic("Failed to allocate INTC memory\n");
++ intc->chip = dummy_irq_chip;
++ intc->chip.name = "INTC";
++ intc->chip.irq_disable = ath79_intc_irq_disable;
++ intc->chip.irq_enable = ath79_intc_irq_enable;
++
++ if (of_property_read_u32(node, "qca,int-status-addr", &intc->int_status) < 0) {
++ panic("Missing address of interrupt status register\n");
++ }
++
++ of_property_read_u32_array(node, "qca,pending-bits", intc->irq_mask, cnt);
++ for (i = 0; i < cnt; i++) {
++ intc->pending_mask |= intc->irq_mask[i];
++ intc->irq_wb_chan[i] = 0xffffffff;
++ }
++
++ cntwb = of_count_phandle_with_args(
++ node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
++
++ for (i = 0; i < cntwb; i++) {
++ struct of_phandle_args args;
++ u32 irq = i;
++
++ of_property_read_u32_index(
++ node, "qca,ddr-wb-channel-interrupts", i, &irq);
++ if (irq >= ATH79_MAX_INTC_CASCADE)
++ continue;
++
++ err = of_parse_phandle_with_args(
++ node, "qca,ddr-wb-channels",
++ "#qca,ddr-wb-channel-cells",
++ i, &args);
++ if (err)
++ return err;
++
++ intc->irq_wb_chan[irq] = args.args[0];
++ }
++
++ intc->irq = irq_of_parse_and_map(node, 0);
++ if (!intc->irq)
++ panic("Failed to get INTC IRQ");
++
++ domain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc);
++ irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain);
++
++ return 0;
++}
++IRQCHIP_DECLARE(ath79_intc, "qca,ar9340-intc",
++ ath79_intc_of_init);
--- /dev/null
+From e029f998594f151008ecbfa024e2957edd2a5189 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 6 Mar 2018 09:58:19 +0100
+Subject: [PATCH 08/33] irqchip/irq-ath79-cpu: drop !OF init helper
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/irqchip/irq-ath79-cpu.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+--- a/drivers/irqchip/irq-ath79-cpu.c
++++ b/drivers/irqchip/irq-ath79-cpu.c
+@@ -85,10 +85,3 @@ static int __init ar79_cpu_intc_of_init(
+ }
+ IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
+ ar79_cpu_intc_of_init);
+-
+-void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3)
+-{
+- irq_wb_chan[2] = irq_wb_chan2;
+- irq_wb_chan[3] = irq_wb_chan3;
+- mips_cpu_irq_init();
+-}
--- /dev/null
+From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Mon, 25 Jun 2018 15:52:10 +0200
+Subject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc
+
+With the driver being converted from platform_data to pure OF, we need to
+also add some docs.
+
+Cc: Rob Herring <robh+dt@kernel.org>
+Cc: devicetree@vger.kernel.org
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
+@@ -0,0 +1,38 @@
++* Qualcomm Atheros AR7100 PCI express root complex
++
++Required properties:
++- compatible: should contain "qcom,ar7100-pci" to identify the core.
++- reg: Should contain the register ranges as listed in the reg-names property.
++- reg-names: Definition: Must include the following entries
++ - "cfg_base" IO Memory
++- #address-cells: set to <3>
++- #size-cells: set to <2>
++- ranges: ranges for the PCI memory and I/O regions
++- interrupt-map-mask and interrupt-map: standard PCI
++ properties to define the mapping of the PCIe interface to interrupt
++ numbers.
++- #interrupt-cells: set to <1>
++- interrupt-controller: define to enable the builtin IRQ cascade.
++
++Optional properties:
++- interrupt-parent: phandle to the MIPS IRQ controller
++
++* Example for ar7100
++ pcie@180c0000 {
++ compatible = "qca,ar7100-pci";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ bus-range = <0x0 0x0>;
++ reg = <0x17010000 0x100>;
++ reg-names = "cfg_base";
++ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000
++ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
++ interrupt-parent = <&cpuintc>;
++ interrupts = <2>;
++
++ interrupt-controller;
++ #interrupt-cells = <1>;
++
++ interrupt-map-mask = <0 0 0 1>;
++ interrupt-map = <0 0 0 0 &pcie0 0>;
++ };
--- /dev/null
+From 1855ab6b1d27f5b38a648baf57ff6a534afec26d Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:07:23 +0200
+Subject: [PATCH 18/33] MIPS: pci-ar71xx: convert to OF
+
+With the ath79 target getting converted to pure OF, we can drop all the
+platform data code and add the missing OF bits to the driver. We also add
+a irq domain for the PCI/e controllers cascade, thus making it usable from
+dts files.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/pci/pci-ar71xx.c | 82 +++++++++++++++++++++++-----------------------
+ 1 file changed, 41 insertions(+), 41 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -15,8 +15,11 @@
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
+ #include <linux/interrupt.h>
++#include <linux/irqchip/chained_irq.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
+
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+@@ -46,12 +49,13 @@
+ #define AR71XX_PCI_IRQ_COUNT 5
+
+ struct ar71xx_pci_controller {
++ struct device_node *np;
+ void __iomem *cfg_base;
+ int irq;
+- int irq_base;
+ struct pci_controller pci_ctrl;
+ struct resource io_res;
+ struct resource mem_res;
++ struct irq_domain *domain;
+ };
+
+ /* Byte lane enable bits */
+@@ -225,29 +229,30 @@ static struct pci_ops ar71xx_pci_ops = {
+
+ static void ar71xx_pci_irq_handler(struct irq_desc *desc)
+ {
+- struct ar71xx_pci_controller *apc;
+ void __iomem *base = ath79_reset_base;
++ struct irq_chip *chip = irq_desc_get_chip(desc);
++ struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
+ u32 pending;
+
+- apc = irq_desc_get_handler_data(desc);
+-
++ chained_irq_enter(chip, desc);
+ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+
+ if (pending & AR71XX_PCI_INT_DEV0)
+- generic_handle_irq(apc->irq_base + 0);
++ generic_handle_irq(irq_linear_revmap(apc->domain, 1));
+
+ else if (pending & AR71XX_PCI_INT_DEV1)
+- generic_handle_irq(apc->irq_base + 1);
++ generic_handle_irq(irq_linear_revmap(apc->domain, 2));
+
+ else if (pending & AR71XX_PCI_INT_DEV2)
+- generic_handle_irq(apc->irq_base + 2);
++ generic_handle_irq(irq_linear_revmap(apc->domain, 3));
+
+ else if (pending & AR71XX_PCI_INT_CORE)
+- generic_handle_irq(apc->irq_base + 4);
++ generic_handle_irq(irq_linear_revmap(apc->domain, 4));
+
+ else
+ spurious_interrupt();
++ chained_irq_exit(chip, desc);
+ }
+
+ static void ar71xx_pci_irq_unmask(struct irq_data *d)
+@@ -258,7 +263,7 @@ static void ar71xx_pci_irq_unmask(struct
+ u32 t;
+
+ apc = irq_data_get_irq_chip_data(d);
+- irq = d->irq - apc->irq_base;
++ irq = irq_linear_revmap(apc->domain, d->irq);
+
+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+@@ -275,7 +280,7 @@ static void ar71xx_pci_irq_mask(struct i
+ u32 t;
+
+ apc = irq_data_get_irq_chip_data(d);
+- irq = d->irq - apc->irq_base;
++ irq = irq_linear_revmap(apc->domain, d->irq);
+
+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+@@ -291,24 +296,31 @@ static struct irq_chip ar71xx_pci_irq_ch
+ .irq_mask_ack = ar71xx_pci_irq_mask,
+ };
+
++static int ar71xx_pci_irq_map(struct irq_domain *d,
++ unsigned int irq, irq_hw_number_t hw)
++{
++ struct ar71xx_pci_controller *apc = d->host_data;
++
++ irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
++ irq_set_chip_data(irq, apc);
++
++ return 0;
++}
++
++static const struct irq_domain_ops ar71xx_pci_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = ar71xx_pci_irq_map,
++};
++
+ static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
+ {
+ void __iomem *base = ath79_reset_base;
+- int i;
+
+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
+
+- BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
+-
+- apc->irq_base = ATH79_PCI_IRQ_BASE;
+- for (i = apc->irq_base;
+- i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
+- irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
+- handle_level_irq);
+- irq_set_chip_data(i, apc);
+- }
+-
++ apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
++ &ar71xx_pci_domain_ops, apc);
+ irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
+ apc);
+ }
+@@ -325,10 +337,14 @@ static void ar71xx_pci_reset(void)
+ mdelay(100);
+ }
+
++static const struct of_device_id ar71xx_pci_ids[] = {
++ { .compatible = "qca,ar7100-pci" },
++ {},
++};
++
+ static int ar71xx_pci_probe(struct platform_device *pdev)
+ {
+ struct ar71xx_pci_controller *apc;
+- struct resource *res;
+ u32 t;
+
+ apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
+@@ -345,26 +361,6 @@ static int ar71xx_pci_probe(struct platf
+ if (apc->irq < 0)
+ return -EINVAL;
+
+- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
+- if (!res)
+- return -EINVAL;
+-
+- apc->io_res.parent = res;
+- apc->io_res.name = "PCI IO space";
+- apc->io_res.start = res->start;
+- apc->io_res.end = res->end;
+- apc->io_res.flags = IORESOURCE_IO;
+-
+- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
+- if (!res)
+- return -EINVAL;
+-
+- apc->mem_res.parent = res;
+- apc->mem_res.name = "PCI memory space";
+- apc->mem_res.start = res->start;
+- apc->mem_res.end = res->end;
+- apc->mem_res.flags = IORESOURCE_MEM;
+-
+ ar71xx_pci_reset();
+
+ /* setup COMMAND register */
+@@ -377,9 +373,11 @@ static int ar71xx_pci_probe(struct platf
+
+ ar71xx_pci_irq_init(apc);
+
++ apc->np = pdev->dev.of_node;
+ apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
+ apc->pci_ctrl.mem_resource = &apc->mem_res;
+ apc->pci_ctrl.io_resource = &apc->io_res;
++ pci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node);
+
+ register_pci_controller(&apc->pci_ctrl);
+
+@@ -390,6 +388,7 @@ static struct platform_driver ar71xx_pci
+ .probe = ar71xx_pci_probe,
+ .driver = {
+ .name = "ar71xx-pci",
++ .of_match_table = of_match_ptr(ar71xx_pci_ids),
+ },
+ };
+
--- /dev/null
+From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Mon, 25 Jun 2018 15:52:02 +0200
+Subject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc
+
+With the driver being converted from platform_data to pure OF, we need to
+also add some docs.
+
+Cc: Rob Herring <robh+dt@kernel.org>
+Cc: devicetree@vger.kernel.org
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ .../devicetree/bindings/pci/qcom,ar7240-pci.txt | 42 ++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
+@@ -0,0 +1,42 @@
++* Qualcomm Atheros AR724X PCI express root complex
++
++Required properties:
++- compatible: should contain "qcom,ar7240-pci" to identify the core.
++- reg: Should contain the register ranges as listed in the reg-names property.
++- reg-names: Definition: Must include the following entries
++ - "crp_base" Configuration registers
++ - "ctrl_base" Control registers
++ - "cfg_base" IO Memory
++- #address-cells: set to <3>
++- #size-cells: set to <2>
++- ranges: ranges for the PCI memory and I/O regions
++- interrupt-map-mask and interrupt-map: standard PCI
++ properties to define the mapping of the PCIe interface to interrupt
++ numbers.
++- #interrupt-cells: set to <1>
++- interrupt-parent: phandle to the MIPS IRQ controller
++
++Optional properties:
++- interrupt-controller: define to enable the builtin IRQ cascade.
++
++* Example for qca9557
++ pcie@180c0000 {
++ compatible = "qcom,ar7240-pci";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ bus-range = <0x0 0x0>;
++ reg = <0x180c0000 0x1000>,
++ <0x180f0000 0x100>,
++ <0x14000000 0x1000>;
++ reg-names = "crp_base", "ctrl_base", "cfg_base";
++ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000
++ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
++ interrupt-parent = <&intc2>;
++ interrupts = <1>;
++
++ interrupt-controller;
++ #interrupt-cells = <1>;
++
++ interrupt-map-mask = <0 0 0 1>;
++ interrupt-map = <0 0 0 0 &pcie0 0>;
++ };
--- /dev/null
+From a522ee0199d5d3ea114ca2e211f6ac398d3e8e0b Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:07:37 +0200
+Subject: [PATCH 20/33] MIPS: pci-ar724x: convert to OF
+
+With the ath79 target getting converted to pure OF, we can drop all the
+platform data code and add the missing OF bits to the driver. We also add
+a irq domain for the PCI/e controllers cascade, thus making it usable from
+dts files.
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/pci/pci-ar724x.c | 88 ++++++++++++++++++++++------------------------
+ 1 file changed, 42 insertions(+), 46 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -11,8 +11,11 @@
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/platform_device.h>
++#include <linux/irqchip/chained_irq.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
+
+ #define AR724X_PCI_REG_APP 0x00
+ #define AR724X_PCI_REG_RESET 0x18
+@@ -42,17 +45,20 @@ struct ar724x_pci_controller {
+ void __iomem *crp_base;
+
+ int irq;
+- int irq_base;
+
+ bool link_up;
+ bool bar0_is_cached;
+ u32 bar0_value;
+
++ struct device_node *np;
+ struct pci_controller pci_controller;
++ struct irq_domain *domain;
+ struct resource io_res;
+ struct resource mem_res;
+ };
+
++static struct irq_chip ar724x_pci_irq_chip;
++
+ static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
+ {
+ u32 reset;
+@@ -228,35 +234,31 @@ static struct pci_ops ar724x_pci_ops = {
+
+ static void ar724x_pci_irq_handler(struct irq_desc *desc)
+ {
+- struct ar724x_pci_controller *apc;
+- void __iomem *base;
++ struct irq_chip *chip = irq_desc_get_chip(desc);
++ struct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc);
+ u32 pending;
+
+- apc = irq_desc_get_handler_data(desc);
+- base = apc->ctrl_base;
+-
+- pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
+- __raw_readl(base + AR724X_PCI_REG_INT_MASK);
++ chained_irq_enter(chip, desc);
++ pending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) &
++ __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK);
+
+ if (pending & AR724X_PCI_INT_DEV0)
+- generic_handle_irq(apc->irq_base + 0);
+-
++ generic_handle_irq(irq_linear_revmap(apc->domain, 1));
+ else
+ spurious_interrupt();
++ chained_irq_exit(chip, desc);
+ }
+
+ static void ar724x_pci_irq_unmask(struct irq_data *d)
+ {
+ struct ar724x_pci_controller *apc;
+ void __iomem *base;
+- int offset;
+ u32 t;
+
+ apc = irq_data_get_irq_chip_data(d);
+ base = apc->ctrl_base;
+- offset = apc->irq_base - d->irq;
+
+- switch (offset) {
++ switch (irq_linear_revmap(apc->domain, d->irq)) {
+ case 0:
+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ __raw_writel(t | AR724X_PCI_INT_DEV0,
+@@ -270,14 +272,12 @@ static void ar724x_pci_irq_mask(struct i
+ {
+ struct ar724x_pci_controller *apc;
+ void __iomem *base;
+- int offset;
+ u32 t;
+
+ apc = irq_data_get_irq_chip_data(d);
+ base = apc->ctrl_base;
+- offset = apc->irq_base - d->irq;
+
+- switch (offset) {
++ switch (irq_linear_revmap(apc->domain, d->irq)) {
+ case 0:
+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
+ __raw_writel(t & ~AR724X_PCI_INT_DEV0,
+@@ -302,26 +302,34 @@ static struct irq_chip ar724x_pci_irq_ch
+ .irq_mask_ack = ar724x_pci_irq_mask,
+ };
+
++static int ar724x_pci_irq_map(struct irq_domain *d,
++ unsigned int irq, irq_hw_number_t hw)
++{
++ struct ar724x_pci_controller *apc = d->host_data;
++
++ irq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq);
++ irq_set_chip_data(irq, apc);
++
++ return 0;
++}
++
++static const struct irq_domain_ops ar724x_pci_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = ar724x_pci_irq_map,
++};
++
+ static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
+ int id)
+ {
+ void __iomem *base;
+- int i;
+
+ base = apc->ctrl_base;
+
+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
+
+- apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
+-
+- for (i = apc->irq_base;
+- i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
+- irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
+- handle_level_irq);
+- irq_set_chip_data(i, apc);
+- }
+-
++ apc->domain = irq_domain_add_linear(apc->np, 2,
++ &ar724x_pci_domain_ops, apc);
+ irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,
+ apc);
+ }
+@@ -360,7 +368,6 @@ static void ar724x_pci_hw_init(struct ar
+ static int ar724x_pci_probe(struct platform_device *pdev)
+ {
+ struct ar724x_pci_controller *apc;
+- struct resource *res;
+ int id;
+
+ id = pdev->id;
+@@ -388,29 +395,11 @@ static int ar724x_pci_probe(struct platf
+ if (apc->irq < 0)
+ return -EINVAL;
+
+- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
+- if (!res)
+- return -EINVAL;
+-
+- apc->io_res.parent = res;
+- apc->io_res.name = "PCI IO space";
+- apc->io_res.start = res->start;
+- apc->io_res.end = res->end;
+- apc->io_res.flags = IORESOURCE_IO;
+-
+- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
+- if (!res)
+- return -EINVAL;
+-
+- apc->mem_res.parent = res;
+- apc->mem_res.name = "PCI memory space";
+- apc->mem_res.start = res->start;
+- apc->mem_res.end = res->end;
+- apc->mem_res.flags = IORESOURCE_MEM;
+-
++ apc->np = pdev->dev.of_node;
+ apc->pci_controller.pci_ops = &ar724x_pci_ops;
+ apc->pci_controller.io_resource = &apc->io_res;
+ apc->pci_controller.mem_resource = &apc->mem_res;
++ pci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node);
+
+ /*
+ * Do the full PCIE Root Complex Initialization Sequence if the PCIe
+@@ -432,10 +421,16 @@ static int ar724x_pci_probe(struct platf
+ return 0;
+ }
+
++static const struct of_device_id ar724x_pci_ids[] = {
++ { .compatible = "qcom,ar7240-pci" },
++ {},
++};
++
+ static struct platform_driver ar724x_pci_driver = {
+ .probe = ar724x_pci_probe,
+ .driver = {
+ .name = "ar724x-pci",
++ .of_match_table = of_match_ptr(ar724x_pci_ids),
+ },
+ };
+
--- /dev/null
+From: John Crispin <john@phrozen.org>
+Subject: ath79: fix remove irq code from pci driver patch
+
+This patch got mangled in the void while rebasing it.
+
+Submitted-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/pci/pci-ar71xx.c | 107 ------------------
+ 1 file changed, 141 deletions(-)
+
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -51,11 +51,9 @@
+ struct ar71xx_pci_controller {
+ struct device_node *np;
+ void __iomem *cfg_base;
+- int irq;
+ struct pci_controller pci_ctrl;
+ struct resource io_res;
+ struct resource mem_res;
+- struct irq_domain *domain;
+ };
+
+ /* Byte lane enable bits */
+@@ -227,104 +225,6 @@ static struct pci_ops ar71xx_pci_ops = {
+ .write = ar71xx_pci_write_config,
+ };
+
+-static void ar71xx_pci_irq_handler(struct irq_desc *desc)
+-{
+- void __iomem *base = ath79_reset_base;
+- struct irq_chip *chip = irq_desc_get_chip(desc);
+- struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);
+- u32 pending;
+-
+- chained_irq_enter(chip, desc);
+- pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
+- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-
+- if (pending & AR71XX_PCI_INT_DEV0)
+- generic_handle_irq(irq_linear_revmap(apc->domain, 1));
+-
+- else if (pending & AR71XX_PCI_INT_DEV1)
+- generic_handle_irq(irq_linear_revmap(apc->domain, 2));
+-
+- else if (pending & AR71XX_PCI_INT_DEV2)
+- generic_handle_irq(irq_linear_revmap(apc->domain, 3));
+-
+- else if (pending & AR71XX_PCI_INT_CORE)
+- generic_handle_irq(irq_linear_revmap(apc->domain, 4));
+-
+- else
+- spurious_interrupt();
+- chained_irq_exit(chip, desc);
+-}
+-
+-static void ar71xx_pci_irq_unmask(struct irq_data *d)
+-{
+- struct ar71xx_pci_controller *apc;
+- unsigned int irq;
+- void __iomem *base = ath79_reset_base;
+- u32 t;
+-
+- apc = irq_data_get_irq_chip_data(d);
+- irq = irq_linear_revmap(apc->domain, d->irq);
+-
+- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+- __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-
+- /* flush write */
+- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-}
+-
+-static void ar71xx_pci_irq_mask(struct irq_data *d)
+-{
+- struct ar71xx_pci_controller *apc;
+- unsigned int irq;
+- void __iomem *base = ath79_reset_base;
+- u32 t;
+-
+- apc = irq_data_get_irq_chip_data(d);
+- irq = irq_linear_revmap(apc->domain, d->irq);
+-
+- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+- __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-
+- /* flush write */
+- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+-}
+-
+-static struct irq_chip ar71xx_pci_irq_chip = {
+- .name = "AR71XX PCI",
+- .irq_mask = ar71xx_pci_irq_mask,
+- .irq_unmask = ar71xx_pci_irq_unmask,
+- .irq_mask_ack = ar71xx_pci_irq_mask,
+-};
+-
+-static int ar71xx_pci_irq_map(struct irq_domain *d,
+- unsigned int irq, irq_hw_number_t hw)
+-{
+- struct ar71xx_pci_controller *apc = d->host_data;
+-
+- irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);
+- irq_set_chip_data(irq, apc);
+-
+- return 0;
+-}
+-
+-static const struct irq_domain_ops ar71xx_pci_domain_ops = {
+- .xlate = irq_domain_xlate_onecell,
+- .map = ar71xx_pci_irq_map,
+-};
+-
+-static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
+-{
+- void __iomem *base = ath79_reset_base;
+-
+- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
+-
+- apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,
+- &ar71xx_pci_domain_ops, apc);
+- irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
+- apc);
+-}
+-
+ static void ar71xx_pci_reset(void)
+ {
+ ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
+@@ -357,10 +257,6 @@ static int ar71xx_pci_probe(struct platf
+ if (IS_ERR(apc->cfg_base))
+ return PTR_ERR(apc->cfg_base);
+
+- apc->irq = platform_get_irq(pdev, 0);
+- if (apc->irq < 0)
+- return -EINVAL;
+-
+ ar71xx_pci_reset();
+
+ /* setup COMMAND register */
+@@ -371,8 +267,6 @@ static int ar71xx_pci_probe(struct platf
+ /* clear bus errors */
+ ar71xx_pci_check_error(apc, 1);
+
+- ar71xx_pci_irq_init(apc);
+-
+ apc->np = pdev->dev.of_node;
+ apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
+ apc->pci_ctrl.mem_resource = &apc->mem_res;
--- /dev/null
+From: David Bauer <mail@david-bauer.net>
+Date: Sat, 11 Apr 2020 14:03:12 +0200
+Subject: MIPS: pci-ar724x: add QCA9550 reset sequence
+
+The QCA9550 family of SoCs have a slightly different reset
+sequence compared to older chips.
+
+Normally the bootloader performs this sequence, however
+some bootloader implementation expect the operating system
+to clear the reset.
+
+Also get the resets from OF to support handling of the second
+PCIe root-complex on the QCA9558.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -390,6 +390,7 @@
+ #define QCA955X_PLL_CPU_CONFIG_REG 0x00
+ #define QCA955X_PLL_DDR_CONFIG_REG 0x04
+ #define QCA955X_PLL_CLK_CTRL_REG 0x08
++#define QCA955X_PLL_PCIE_CONFIG_REG 0x0c
+ #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
+ #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
+ #define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
+@@ -475,6 +476,9 @@
+ #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
+ #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
++#define QCA955X_PLL_PCIE_CONFIG_PLL_PWD BIT(30)
++#define QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS BIT(16)
++
+ #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5)
+ #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6)
+ #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7)
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -8,6 +8,7 @@
+
+ #include <linux/irq.h>
+ #include <linux/pci.h>
++#include <linux/reset.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/platform_device.h>
+@@ -55,6 +56,9 @@ struct ar724x_pci_controller {
+ struct irq_domain *domain;
+ struct resource io_res;
+ struct resource mem_res;
++
++ struct reset_control *hc_reset;
++ struct reset_control *phy_reset;
+ };
+
+ static struct irq_chip ar724x_pci_irq_chip;
+@@ -340,18 +344,30 @@ static void ar724x_pci_hw_init(struct ar
+ int wait = 0;
+
+ /* deassert PCIe host controller and PCIe PHY reset */
+- ath79_device_reset_clear(AR724X_RESET_PCIE);
+- ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
++ reset_control_deassert(apc->hc_reset);
++ reset_control_deassert(apc->phy_reset);
+
+- /* remove the reset of the PCIE PLL */
+- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
+- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
+-
+- /* deassert bypass for the PCIE PLL */
+- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
+- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++ if (of_device_is_compatible(apc->np, "qcom,qca9550-pci")) {
++ /* remove the reset of the PCIE PLL */
++ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
++ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_PWD;
++ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
++
++ /* deassert bypass for the PCIE PLL */
++ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
++ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS;
++ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
++ } else {
++ /* remove the reset of the PCIE PLL */
++ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
++ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
++ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++
++ /* deassert bypass for the PCIE PLL */
++ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
++ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
++ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++ }
+
+ /* set PCIE Application Control to ready */
+ app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
+@@ -395,6 +411,14 @@ static int ar724x_pci_probe(struct platf
+ if (apc->irq < 0)
+ return -EINVAL;
+
++ apc->hc_reset = devm_reset_control_get_exclusive(&pdev->dev, "hc");
++ if (IS_ERR(apc->hc_reset))
++ return PTR_ERR(apc->hc_reset);
++
++ apc->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, "phy");
++ if (IS_ERR(apc->phy_reset))
++ return PTR_ERR(apc->phy_reset);
++
+ apc->np = pdev->dev.of_node;
+ apc->pci_controller.pci_ops = &ar724x_pci_ops;
+ apc->pci_controller.io_resource = &apc->io_res;
+@@ -405,7 +429,7 @@ static int ar724x_pci_probe(struct platf
+ * Do the full PCIE Root Complex Initialization Sequence if the PCIe
+ * host controller is in reset.
+ */
+- if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
++ if (reset_control_status(apc->hc_reset))
+ ar724x_pci_hw_init(apc);
+
+ apc->link_up = ar724x_pci_check_link(apc);
+@@ -423,6 +447,7 @@ static int ar724x_pci_probe(struct platf
+
+ static const struct of_device_id ar724x_pci_ids[] = {
+ { .compatible = "qcom,ar7240-pci" },
++ { .compatible = "qcom,qca9550-pci" },
+ {},
+ };
+
--- /dev/null
+From: Gabor Juhos <juhosg@openwrt.org>
+Subject: [PATCH] ar71xx: swizzle address for PCI byte/word access on AR71xx
+
+Closes #11683.
+
+SVN-Revision: 32639
+---
+ .../mips/include/asm/mach-ath79/mangle-port.h | 111 ++++++++++++++++++
+ 1 file changed, 111 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-ath79/mangle-port.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
+@@ -0,0 +1,37 @@
++/*
++ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
++ * Copyright (C) 2003, 2004 Ralf Baechle
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
++#define __ASM_MACH_ATH79_MANGLE_PORT_H
++
++#ifdef CONFIG_PCI_AR71XX
++extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
++extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
++#else
++#define ath79_pci_swizzle_b(port) (port)
++#define ath79_pci_swizzle_w(port) (port)
++#endif
++
++#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port)
++#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port)
++#define __swizzle_addr_l(port) (port)
++#define __swizzle_addr_q(port) (port)
++
++# define ioswabb(a, x) (x)
++# define __mem_ioswabb(a, x) (x)
++# define ioswabw(a, x) (x)
++# define __mem_ioswabw(a, x) cpu_to_le16(x)
++# define ioswabl(a, x) (x)
++# define __mem_ioswabl(a, x) cpu_to_le32(x)
++# define ioswabq(a, x) (x)
++# define __mem_ioswabq(a, x) cpu_to_le64(x)
++
++#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
+--- a/arch/mips/pci/pci-ar71xx.c
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -68,6 +68,45 @@ static const u32 ar71xx_pci_read_mask[8]
+ 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
+ };
+
++static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
++static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
++
++static inline bool ar71xx_is_pci_addr(unsigned long port)
++{
++ unsigned long phys = CPHYSADDR(port);
++
++ return (phys >= AR71XX_PCI_MEM_BASE &&
++ phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
++}
++
++static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
++{
++ return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
++}
++
++static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
++{
++ return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
++}
++
++unsigned long ath79_pci_swizzle_b(unsigned long port)
++{
++ if (__ath79_pci_swizzle_b)
++ return __ath79_pci_swizzle_b(port);
++
++ return port;
++}
++EXPORT_SYMBOL(ath79_pci_swizzle_b);
++
++unsigned long ath79_pci_swizzle_w(unsigned long port)
++{
++ if (__ath79_pci_swizzle_w)
++ return __ath79_pci_swizzle_w(port);
++
++ return port;
++}
++EXPORT_SYMBOL(ath79_pci_swizzle_w);
++
+ static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
+ {
+ u32 t;
+@@ -275,6 +314,9 @@ static int ar71xx_pci_probe(struct platf
+
+ register_pci_controller(&apc->pci_ctrl);
+
++ __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
++ __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
++
+ return 0;
+ }
+
--- /dev/null
+From: Christian Lamparter <chunkeey@gmail.com>
+Subject: [PATCH] ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for
+
+ ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344
+
+ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1231,6 +1231,10 @@
+ #define AR934X_ETH_CFG_RDV_DELAY BIT(16)
+ #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
+ #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
++#define AR934X_ETH_CFG_TXD_DELAY_MASK 0x3
++#define AR934X_ETH_CFG_TXD_DELAY_SHIFT 18
++#define AR934X_ETH_CFG_TXE_DELAY_MASK 0x3
++#define AR934X_ETH_CFG_TXE_DELAY_SHIFT 20
+
+ /*
+ * QCA953X GMAC Interface
--- /dev/null
+From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Mon, 18 Mar 2019 00:54:06 +0100
+Subject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers
+
+This adds missing GMAC register definitions for the Qualcomm Atheros
+QCA955X series MIPS SoCs.
+
+They originate from the platforms U-Boot code and the AVM FRITZ!WLAN
+Repeater 450E's GPL tarball.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ .../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++
+ 1 file changed, 54 insertions(+)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1251,7 +1251,12 @@
+ */
+
+ #define QCA955X_GMAC_REG_ETH_CFG 0x00
++#define QCA955X_GMAC_REG_SGMII_RESET 0x14
+ #define QCA955X_GMAC_REG_SGMII_SERDES 0x18
++#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c
++#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20
++#define QCA955X_GMAC_REG_SGMII_CONFIG 0x34
++#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58
+
+ #define QCA955X_ETH_CFG_RGMII_EN BIT(0)
+ #define QCA955X_ETH_CFG_MII_GE0 BIT(1)
+@@ -1273,9 +1278,58 @@
+ #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
+ #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
+
++#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0
++#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0)
++#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1)
++#define QCA955X_SGMII_RESET_RX_125M_N BIT(2)
++#define QCA955X_SGMII_RESET_TX_125M_N BIT(3)
++#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4)
++
+ #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
+ #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
+ #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
++
++#define QCA955X_MR_AN_CONTROL_SPEED_SEL1 BIT(6)
++#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE BIT(8)
++#define QCA955X_MR_AN_CONTROL_RESTART_AN BIT(9)
++#define QCA955X_MR_AN_CONTROL_POWER_DOWN BIT(11)
++#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12)
++#define QCA955X_MR_AN_CONTROL_SPEED_SEL0 BIT(13)
++#define QCA955X_MR_AN_CONTROL_LOOPBACK BIT(14)
++#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15)
++
++#define QCA955X_MR_AN_STATUS_EXT_CAP BIT(0)
++#define QCA955X_MR_AN_STATUS_LINK_UP BIT(2)
++#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3)
++#define QCA955X_MR_AN_STATUS_REMOTE_FAULT BIT(4)
++#define QCA955X_MR_AN_STATUS_AN_COMPLETE BIT(5)
++#define QCA955X_MR_AN_STATUS_NO_PREAMBLE BIT(6)
++#define QCA955X_MR_AN_STATUS_BASE_PAGE BIT(7)
++
++#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
++#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
++#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3)
++#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4)
++#define QCA955X_SGMII_CONFIG_FORCE_SPEED BIT(5)
++#define QCA955X_SGMII_CONFIG_SPEED_SHIFT 6
++#define QCA955X_SGMII_CONFIG_SPEED_MASK 0xc0
++#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8)
++#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9)
++#define QCA955X_SGMII_CONFIG_MDIO_ENABLE BIT(10)
++#define QCA955X_SGMII_CONFIG_MDIO_PULSE BIT(11)
++#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE BIT(12)
++#define QCA955X_SGMII_CONFIG_PRBS_ENABLE BIT(13)
++#define QCA955X_SGMII_CONFIG_BERT_ENABLE BIT(14)
++
++#define QCA955X_SGMII_DEBUG_TX_STATE_MASK 0xff
++#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT 0
++#define QCA955X_SGMII_DEBUG_RX_STATE_MASK 0xff00
++#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT 8
++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff0000
++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16
++#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK 0xf000000
++#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT 24
++
+ /*
+ * QCA956X GMAC Interface
+ */
--- /dev/null
+From: David Bauer <mail@david-bauer.net>
+Subject: [PATCH] ath79: force SGMII SerDes mode to MAC operation
+
+The mode on the SGMII SerDes on the QCA9563 is 1000 Base-X by default.
+This only allows for 1000 Mbit/s links, however when used with an SGMII
+PHY in 100 Mbit/s link mode, the link remains dead.
+
+This strictly has nothing to do with the SerDes calibration, however it
+is done at the same point in the QCA reference U-Boot which is the
+blueprint for everything happening here. As the current state is more or
+less a hack, this should be fine.
+
+This fixes the issues outlined above on a TP-Link EAP-225 Outdoor.
+
+Reported-by: Tom Herbers <freifunk@tomherbers.de>
+Tested-by: Tom Herbers <freifunk@tomherbers.de>
+Submitted-by: David Bauer <mail@david-bauer.net>
+---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
+ 1 files changed, 1 insertion(+)
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1380,5 +1380,6 @@
+
+ #define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
+ #define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
++#define QCA956X_SGMII_CONFIG_MODE_CTRL_SGMII_MAC 0x2
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
--- /dev/null
+From: John Crispin <john@phrozen.org>
+Subject: ath79: Register GPIO driver earlier
+
+HACK: register the GPIO driver earlier to ensure that gpio_request calls
+from mach files succeed.
+
+Submitted-by: John Crispin <john@phrozen.org>
+---
+ drivers/gpio/gpio-ath79.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpio/gpio-ath79.c
++++ b/drivers/gpio/gpio-ath79.c
+@@ -302,7 +302,11 @@ static struct platform_driver ath79_gpio
+ .probe = ath79_gpio_probe,
+ };
+
+-module_platform_driver(ath79_gpio_driver);
++static int __init ath79_gpio_init(void)
++{
++ return platform_driver_register(&ath79_gpio_driver);
++}
++postcore_initcall(ath79_gpio_init);
+
+ MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
+ MODULE_LICENSE("GPL v2");
--- /dev/null
+From: John Crispin <john@phrozen.org>
+Subject: [PATCH] ath79: make ahb wifi work
+
+Submitted-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/ath79/common.c | 3 +++
+ mips/include/asm/mach-ath79/ath79.h | 1+
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -31,11 +31,13 @@ EXPORT_SYMBOL_GPL(ath79_ddr_freq);
+
+ enum ath79_soc_type ath79_soc;
+ unsigned int ath79_soc_rev;
++EXPORT_SYMBOL_GPL(ath79_soc_rev);
+
+ void __iomem *ath79_pll_base;
+ void __iomem *ath79_reset_base;
+ EXPORT_SYMBOL_GPL(ath79_reset_base);
+-static void __iomem *ath79_ddr_base;
++void __iomem *ath79_ddr_base;
++EXPORT_SYMBOL_GPL(ath79_ddr_base);
+ static void __iomem *ath79_ddr_wb_flush_base;
+ static void __iomem *ath79_ddr_pci_win_base;
+
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -149,6 +149,7 @@ void ath79_ddr_wb_flush(unsigned int reg
+ void ath79_ddr_set_pci_windows(void);
+
+ extern void __iomem *ath79_pll_base;
++extern void __iomem *ath79_ddr_base;
+ extern void __iomem *ath79_reset_base;
+
+ static inline void ath79_pll_wr(unsigned reg, u32 val)
--- /dev/null
+From: Luiz Angelo Daros de Luca <luizluca@gmail.com>
+Subject: [PATCH] ath79: export ath79_pll_base
+
+This symbol is declared as extern but nobody exported it.
+Any module including arch/mips/include/asm/mach-ath79/ath79.h
+will not build. Without this export, ag71xx.ko will not build
+as a module and the build will fail like this:
+
+ERROR: modpost: "ath79_pll_base" [drivers/net/ethernet/atheros/ag71xx/ag71xx.ko] undefined!
+
+The ath79_pll_base symbol is accessed in the ath79_pll_wr() inline function.
+
+---
+ arch/mips/ath79/common.c | 1 +
+ 1 file changed, 1 insertions(+)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -34,6 +34,7 @@ unsigned int ath79_soc_rev;
+ EXPORT_SYMBOL_GPL(ath79_soc_rev);
+
+ void __iomem *ath79_pll_base;
++EXPORT_SYMBOL_GPL(ath79_pll_base);
+ void __iomem *ath79_reset_base;
+ EXPORT_SYMBOL_GPL(ath79_reset_base);
+ void __iomem *ath79_ddr_base;
--- /dev/null
+From: Daniel Golle <daniel@makrotopia.org>
+Subject: [PATCH] ath79: add support for Atheros AR934x HS UART
+
+AR934x chips also got the 'old' qca,ar9330-uart in addition to the
+'new' ns16550a compatible one. Add support for UART1 clock selector as
+well as device-tree bindings in ar934x.dtsi to make use of that uart.
+
+Reported-by: Piotr Dymacz <pepe2k@gmail.com>
+Submitted-by: Daniel Golle <daniel@makrotopia.org>
+---
+ arch/mips/ath79/clock.c | 7 +++++++
+ .../mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
+ include/dt-bindings/clock/ath79-clk.h | 3 ++-
+ 3 files changed, 10 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -40,6 +40,7 @@ static const char * const clk_names[ATH7
+ [ATH79_CLK_AHB] = "ahb",
+ [ATH79_CLK_REF] = "ref",
+ [ATH79_CLK_MDIO] = "mdio",
++ [ATH79_CLK_UART1] = "uart1",
+ };
+
+ static const char * __init ath79_clk_name(int type)
+@@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo
+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
+ ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
+
++ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)
++ ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);
++
+ iounmap(dpll_base);
+ }
+
+@@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt(
+ if (!clks[ATH79_CLK_MDIO])
+ clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
+
++ if (!clks[ATH79_CLK_UART1])
++ clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];
++
+ if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
+ pr_err("%pOF: could not register clk provider\n", np);
+ goto err_iounmap;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -348,6 +348,7 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+ #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL BIT(7)
+
+ #define QCA953X_PLL_CPU_CONFIG_REG 0x00
+ #define QCA953X_PLL_DDR_CONFIG_REG 0x04
+--- a/include/dt-bindings/clock/ath79-clk.h
++++ b/include/dt-bindings/clock/ath79-clk.h
+@@ -11,7 +11,8 @@
+ #define ATH79_CLK_AHB 2
+ #define ATH79_CLK_REF 3
+ #define ATH79_CLK_MDIO 4
++#define ATH79_CLK_UART1 5
+
+-#define ATH79_CLK_END 5
++#define ATH79_CLK_END 6
+
+ #endif /* __DT_BINDINGS_ATH79_CLK_H */
--- /dev/null
+From 3fc8585cf76022dba7496627074d42af88c30718 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 23 Jun 2018 15:16:55 +0200
+Subject: [PATCH 32/33] MIPS: ath79: sanitize symbols
+
+We no longer need to select which SoCs are supported as the whole arch
+code is always built. So lets drop all the SoC symbols
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/Kconfig | 2 ++
+ arch/mips/ath79/Kconfig | 44 +++++---------------------------------------
+ arch/mips/pci/Makefile | 2 +-
+ 3 files changed, 8 insertions(+), 40 deletions(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -255,6 +255,8 @@ config ATH79
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_MIPS16
+ select SYS_SUPPORTS_ZBOOT_UART_PROM
++ select HAVE_PCI
++ select USB_ARCH_HAS_EHCI
+ select USE_OF
+ select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM
+ help
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -1,32 +1,14 @@
+ # SPDX-License-Identifier: GPL-2.0
+ if ATH79
+
+-config SOC_AR71XX
+- select HAVE_PCI
+- def_bool n
+-
+-config SOC_AR724X
+- select HAVE_PCI
+- select PCI_AR724X if PCI
+- def_bool n
+-
+-config SOC_AR913X
+- def_bool n
+-
+-config SOC_AR933X
+- def_bool n
+-
+-config SOC_AR934X
+- select HAVE_PCI
+- select PCI_AR724X if PCI
+- def_bool n
+-
+-config SOC_QCA955X
+- select HAVE_PCI
+- select PCI_AR724X if PCI
++config PCI_AR71XX
++ bool "PCI support for AR7100 type SoCs"
++ depends on PCI
+ def_bool n
+
+ config PCI_AR724X
++ bool "PCI support for AR724x type SoCs"
++ depends on PCI
+ def_bool n
+
+ endif
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -19,7 +19,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o
+ ops-bcm63xx.o
+ obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
+ obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
+-obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
++obj-$(CONFIG_PCI_AR71XX) += pci-ar71xx.o
+ obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
+ obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xtalk-bridge.o
+ #
--- /dev/null
+From f32bc2aa01edcba2f2ed5db151cf183eac9ef919 Mon Sep 17 00:00:00 2001
+From: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>
+Date: Sat, 25 Feb 2017 16:42:50 +0000
+Subject: mtd: nor: support mtd name from device tree
+
+Signed-off-by: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>
+---
+ drivers/mtd/spi-nor/spi-nor.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -3420,12 +3420,19 @@ static void spi_nor_set_mtd_info(struct
+ {
+ struct mtd_info *mtd = &nor->mtd;
+ struct device *dev = nor->dev;
++ struct device_node *np = spi_nor_get_flash_node(nor);
++ const char __maybe_unused *of_mtd_name = NULL;
+
+ spi_nor_set_mtd_locking_ops(nor);
+ spi_nor_set_mtd_otp_ops(nor);
+
+ mtd->dev.parent = dev;
+- if (!mtd->name)
++#ifdef CONFIG_MTD_OF_PARTS
++ of_property_read_string(np, "linux,mtd-name", &of_mtd_name);
++#endif
++ if (of_mtd_name)
++ mtd->name = of_mtd_name;
++ else if (!mtd->name)
+ mtd->name = dev_name(dev);
+ mtd->type = MTD_NORFLASH;
+ mtd->flags = MTD_CAP_NORFLASH;
+--- a/drivers/mtd/mtdcore.c
++++ b/drivers/mtd/mtdcore.c
+@@ -870,6 +870,17 @@ out_error:
+ */
+ static void mtd_set_dev_defaults(struct mtd_info *mtd)
+ {
++#ifdef CONFIG_MTD_OF_PARTS
++ const char __maybe_unused *of_mtd_name = NULL;
++ struct device_node *np;
++
++ np = mtd_get_of_node(mtd);
++ if (np && !mtd->name) {
++ of_property_read_string(np, "linux,mtd-name", &of_mtd_name);
++ if (of_mtd_name)
++ mtd->name = of_mtd_name;
++ } else
++#endif
+ if (mtd->dev.parent) {
+ if (!mtd->owner && mtd->dev.parent->driver)
+ mtd->owner = mtd->dev.parent->driver->owner;
--- /dev/null
+From: Christian Lamparter <chunkeey@gmail.com>
+Subject: [PATCH] ath79: port cybertan_part from ar71xx
+
+This patch ports the cybertan_part code from ar71xx and converts the
+driver to a DT-supported mtd parser. As a result, it will no longer
+add the u-boot, nvram and art partitions, which were never part of
+the special Cybertan header.
+
+Instead these partitions have to be specified in the DT, which has the
+upside of making it possible to add properties (i.e.: read-only), labels
+and references to these important partitions.
+
+Submitted-by: Christian Lamparter <chunkeey@gmail.com>
+---
+ drivers/mtd/parsers/Makefile | 1 +
+ drivers/mtd/parsers/Kconfig | 8 ++++++++
+ 2 files changed, 9 insertions(+)
+
+--- a/drivers/mtd/parsers/Makefile
++++ b/drivers/mtd/parsers/Makefile
+@@ -9,6 +9,7 @@ obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
+ ofpart-y += ofpart_core.o
+ ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908) += ofpart_bcm4908.o
+ ofpart-$(CONFIG_MTD_OF_PARTS_LINKSYS_NS)+= ofpart_linksys_ns.o
++obj-$(CONFIG_MTD_PARSER_CYBERTAN) += parser_cybertan.o
+ obj-$(CONFIG_MTD_PARSER_IMAGETAG) += parser_imagetag.o
+ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
+ obj-$(CONFIG_MTD_PARSER_TPLINK_SAFELOADER) += tplink_safeloader.o
+--- a/drivers/mtd/parsers/Kconfig
++++ b/drivers/mtd/parsers/Kconfig
+@@ -112,6 +112,14 @@ config MTD_OF_PARTS_LINKSYS_NS
+ two "firmware" partitions. Currently used firmware has to be detected
+ using CFE environment variable.
+
++config MTD_PARSER_CYBERTAN
++ tristate "Parser for Cybertan format partitions"
++ depends on MTD && (ATH79 || COMPILE_TEST)
++ help
++ Cybertan has a proprietory header than encompasses a Broadcom trx
++ header. This driver will parse the header and take care of the
++ special offsets that result in the extra headers.
++
+ config MTD_PARSER_IMAGETAG
+ tristate "Parser for BCM963XX Image Tag format partitions"
+ depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST
--- /dev/null
+From: Gabor Juhos <juhosg@openwrt.org>
+Subject: [PATCH] ar71xx: Link SPI before MTD
+
+SVN-Revision: 22863
+---
+ drivers/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -87,8 +87,8 @@ obj-y += scsi/
+ obj-y += nvme/
+ obj-$(CONFIG_ATA) += ata/
+ obj-$(CONFIG_TARGET_CORE) += target/
+-obj-$(CONFIG_MTD) += mtd/
+ obj-$(CONFIG_SPI) += spi/
++obj-$(CONFIG_MTD) += mtd/
+ obj-$(CONFIG_SPMI) += spmi/
+ obj-$(CONFIG_HSI) += hsi/
+ obj-$(CONFIG_SLIMBUS) += slimbus/
--- /dev/null
+From: Gabor Juhos <juhosg@openwrt.org>
+Subject: ar71xx: ar934x_nfc: experimental NAND Flash Controller driver for AR934x
+
+SVN-Revision: 33385
+---
+ drivers/mtd/nand/raw/Kconfig | 8 ++++++++
+ drivers/mtd/nand/raw/Makefile | 1 +
+ 2 files changed, 9 insertions(+)
+
+--- a/drivers/mtd/nand/raw/Kconfig
++++ b/drivers/mtd/nand/raw/Kconfig
+@@ -543,4 +543,12 @@ config MTD_NAND_DISKONCHIP_BBTWRITE
+ load time (assuming you build diskonchip as a module) with the module
+ parameter "inftl_bbt_write=1".
+
++config MTD_NAND_AR934X
++ tristate "Support for NAND controller on Qualcomm Atheros AR934x/QCA955x SoCs"
++ depends on ATH79 || COMPILE_TEST
++ depends on HAS_IOMEM
++ help
++ Enables support for NAND controller on Qualcomm Atheros SoCs.
++ This controller is found on AR934x and QCA955x SoCs.
++
+ endif # MTD_RAW_NAND
+--- a/drivers/mtd/nand/raw/Makefile
++++ b/drivers/mtd/nand/raw/Makefile
+@@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_INTEL_LGM) += inte
+ obj-$(CONFIG_MTD_NAND_ROCKCHIP) += rockchip-nand-controller.o
+ obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o
+ obj-$(CONFIG_MTD_NAND_RENESAS) += renesas-nand-controller.o
++obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nand.o
+
+ nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
+ nand-objs += nand_onfi.o
--- /dev/null
+From 08c9d6ceef01893678a5d2e8a15517c745417f21 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 6 Mar 2018 10:04:05 +0100
+Subject: [PATCH 04/27] phy: add ath79 usb phys
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/phy/Kconfig | 16 ++++++
+ drivers/phy/Makefile | 2 +
+ drivers/phy/phy-ar7100-usb.c | 124 +++++++++++++++++++++++++++++++++++++++++++
+ drivers/phy/phy-ar7200-usb.c | 108 +++++++++++++++++++++++++++++++++++++
+ 4 files changed, 250 insertions(+)
+ create mode 100644 drivers/phy/phy-ar7100-usb.c
+ create mode 100644 drivers/phy/phy-ar7200-usb.c
+
+--- a/drivers/phy/Kconfig
++++ b/drivers/phy/Kconfig
+@@ -25,6 +25,22 @@ config GENERIC_PHY_MIPI_DPHY
+ Provides a number of helpers a core functions for MIPI D-PHY
+ drivers to us.
+
++config PHY_AR7100_USB
++ tristate "Atheros AR7100 USB PHY driver"
++ depends on ATH79 || COMPILE_TEST
++ default y if USB_EHCI_HCD_PLATFORM
++ select GENERIC_PHY
++ help
++ Enable this to support the USB PHY on Atheros AR7100 SoCs.
++
++config PHY_AR7200_USB
++ tristate "Atheros AR7200 USB PHY driver"
++ depends on ATH79 || COMPILE_TEST
++ default y if USB_EHCI_HCD_PLATFORM
++ select GENERIC_PHY
++ help
++ Enable this to support the USB PHY on Atheros AR7200 SoCs.
++
+ config PHY_LPC18XX_USB_OTG
+ tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver"
+ depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
+--- a/drivers/phy/Makefile
++++ b/drivers/phy/Makefile
+@@ -4,6 +4,8 @@
+ #
+
+ obj-$(CONFIG_GENERIC_PHY) += phy-core.o
++obj-$(CONFIG_PHY_AR7100_USB) += phy-ar7100-usb.o
++obj-$(CONFIG_PHY_AR7200_USB) += phy-ar7200-usb.o
+ obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
+ obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
+ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
+--- /dev/null
++++ b/drivers/phy/phy-ar7100-usb.c
+@@ -0,0 +1,140 @@
++/*
++ * Copyright (C) 2018 John Crispin <john@phrozen.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/phy/phy.h>
++#include <linux/delay.h>
++#include <linux/reset.h>
++#include <linux/of_gpio.h>
++
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++struct ar7100_usb_phy {
++ struct reset_control *rst_phy;
++ struct reset_control *rst_host;
++ struct reset_control *rst_ohci_dll;
++ void __iomem *io_base;
++ struct phy *phy;
++ int gpio;
++};
++
++static int ar7100_usb_phy_power_off(struct phy *phy)
++{
++ struct ar7100_usb_phy *priv = phy_get_drvdata(phy);
++ int err = 0;
++
++ err |= reset_control_assert(priv->rst_host);
++ err |= reset_control_assert(priv->rst_phy);
++ err |= reset_control_assert(priv->rst_ohci_dll);
++
++ return err;
++}
++
++static int ar7100_usb_phy_power_on(struct phy *phy)
++{
++ struct ar7100_usb_phy *priv = phy_get_drvdata(phy);
++ int err = 0;
++
++ err |= ar7100_usb_phy_power_off(phy);
++ mdelay(100);
++ err |= reset_control_deassert(priv->rst_ohci_dll);
++ err |= reset_control_deassert(priv->rst_phy);
++ err |= reset_control_deassert(priv->rst_host);
++ mdelay(500);
++ iowrite32(0xf0000, priv->io_base + AR71XX_USB_CTRL_REG_CONFIG);
++ iowrite32(0x20c00, priv->io_base + AR71XX_USB_CTRL_REG_FLADJ);
++
++ return err;
++}
++
++static const struct phy_ops ar7100_usb_phy_ops = {
++ .power_on = ar7100_usb_phy_power_on,
++ .power_off = ar7100_usb_phy_power_off,
++ .owner = THIS_MODULE,
++};
++
++static int ar7100_usb_phy_probe(struct platform_device *pdev)
++{
++ struct phy_provider *phy_provider;
++ struct resource *res;
++ struct ar7100_usb_phy *priv;
++
++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ priv->io_base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(priv->io_base))
++ return PTR_ERR(priv->io_base);
++
++ priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy");
++ if (IS_ERR(priv->rst_phy)) {
++ dev_err(&pdev->dev, "phy reset is missing\n");
++ return PTR_ERR(priv->rst_phy);
++ }
++
++ priv->rst_host = devm_reset_control_get(&pdev->dev, "usb-host");
++ if (IS_ERR(priv->rst_host)) {
++ dev_err(&pdev->dev, "host reset is missing\n");
++ return PTR_ERR(priv->rst_host);
++ }
++
++ priv->rst_ohci_dll = devm_reset_control_get(&pdev->dev, "usb-ohci-dll");
++ if (IS_ERR(priv->rst_ohci_dll)) {
++ dev_err(&pdev->dev, "ohci-dll reset is missing\n");
++ return PTR_ERR(priv->rst_host);
++ }
++
++ priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7100_usb_phy_ops);
++ if (IS_ERR(priv->phy)) {
++ dev_err(&pdev->dev, "failed to create PHY\n");
++ return PTR_ERR(priv->phy);
++ }
++
++ priv->gpio = of_get_named_gpio(pdev->dev.of_node, "gpios", 0);
++ if (gpio_is_valid(priv->gpio)) {
++ int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));
++
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request gpio\n");
++ return ret;
++ }
++ gpio_export_with_name(gpio_to_desc(priv->gpio), 0, dev_name(&pdev->dev));
++ gpio_set_value(priv->gpio, 1);
++ }
++
++ phy_set_drvdata(priv->phy, priv);
++
++ phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
++
++
++ return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static const struct of_device_id ar7100_usb_phy_of_match[] = {
++ { .compatible = "qca,ar7100-usb-phy" },
++ {}
++};
++MODULE_DEVICE_TABLE(of, ar7100_usb_phy_of_match);
++
++static struct platform_driver ar7100_usb_phy_driver = {
++ .probe = ar7100_usb_phy_probe,
++ .driver = {
++ .of_match_table = ar7100_usb_phy_of_match,
++ .name = "ar7100-usb-phy",
++ }
++};
++module_platform_driver(ar7100_usb_phy_driver);
++
++MODULE_DESCRIPTION("ATH79 USB PHY driver");
++MODULE_AUTHOR("Alban Bedel <albeu@free.fr>");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/phy/phy-ar7200-usb.c
+@@ -0,0 +1,136 @@
++/*
++ * Copyright (C) 2015 Alban Bedel <albeu@free.fr>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/phy/phy.h>
++#include <linux/reset.h>
++#include <linux/of_gpio.h>
++
++struct ar7200_usb_phy {
++ struct reset_control *rst_phy;
++ struct reset_control *rst_phy_analog;
++ struct reset_control *suspend_override;
++ struct phy *phy;
++ int gpio;
++};
++
++static int ar7200_usb_phy_power_on(struct phy *phy)
++{
++ struct ar7200_usb_phy *priv = phy_get_drvdata(phy);
++ int err = 0;
++
++ if (priv->suspend_override)
++ err = reset_control_assert(priv->suspend_override);
++ if (priv->rst_phy)
++ err |= reset_control_deassert(priv->rst_phy);
++ if (priv->rst_phy_analog)
++ err |= reset_control_deassert(priv->rst_phy_analog);
++
++ return err;
++}
++
++static int ar7200_usb_phy_power_off(struct phy *phy)
++{
++ struct ar7200_usb_phy *priv = phy_get_drvdata(phy);
++ int err = 0;
++
++ if (priv->suspend_override)
++ err = reset_control_deassert(priv->suspend_override);
++ if (priv->rst_phy)
++ err |= reset_control_assert(priv->rst_phy);
++ if (priv->rst_phy_analog)
++ err |= reset_control_assert(priv->rst_phy_analog);
++
++ return err;
++}
++
++static const struct phy_ops ar7200_usb_phy_ops = {
++ .power_on = ar7200_usb_phy_power_on,
++ .power_off = ar7200_usb_phy_power_off,
++ .owner = THIS_MODULE,
++};
++
++static int ar7200_usb_phy_probe(struct platform_device *pdev)
++{
++ struct phy_provider *phy_provider;
++ struct ar7200_usb_phy *priv;
++
++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy");
++ if (IS_ERR(priv->rst_phy)) {
++ if (PTR_ERR(priv->rst_phy) != -EPROBE_DEFER)
++ dev_err(&pdev->dev, "phy reset is missing\n");
++ return PTR_ERR(priv->rst_phy);
++ }
++
++ priv->rst_phy_analog = devm_reset_control_get_optional(
++ &pdev->dev, "usb-phy-analog");
++ if (IS_ERR(priv->rst_phy_analog)) {
++ if (PTR_ERR(priv->rst_phy_analog) == -ENOENT)
++ priv->rst_phy_analog = NULL;
++ else
++ return PTR_ERR(priv->rst_phy_analog);
++ }
++
++ priv->suspend_override = devm_reset_control_get_optional(
++ &pdev->dev, "usb-suspend-override");
++ if (IS_ERR(priv->suspend_override)) {
++ if (PTR_ERR(priv->suspend_override) == -ENOENT)
++ priv->suspend_override = NULL;
++ else
++ return PTR_ERR(priv->suspend_override);
++ }
++
++ priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7200_usb_phy_ops);
++ if (IS_ERR(priv->phy)) {
++ dev_err(&pdev->dev, "failed to create PHY\n");
++ return PTR_ERR(priv->phy);
++ }
++
++ priv->gpio = of_get_named_gpio(pdev->dev.of_node, "gpios", 0);
++ if (gpio_is_valid(priv->gpio)) {
++ int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));
++
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request gpio\n");
++ return ret;
++ }
++ gpio_export_with_name(gpio_to_desc(priv->gpio), 0, dev_name(&pdev->dev));
++ gpio_set_value(priv->gpio, 1);
++ }
++
++ phy_set_drvdata(priv->phy, priv);
++
++ phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
++
++ return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static const struct of_device_id ar7200_usb_phy_of_match[] = {
++ { .compatible = "qca,ar7200-usb-phy" },
++ {}
++};
++MODULE_DEVICE_TABLE(of, ar7200_usb_phy_of_match);
++
++static struct platform_driver ar7200_usb_phy_driver = {
++ .probe = ar7200_usb_phy_probe,
++ .driver = {
++ .of_match_table = ar7200_usb_phy_of_match,
++ .name = "ar7200-usb-phy",
++ }
++};
++module_platform_driver(ar7200_usb_phy_driver);
++
++MODULE_DESCRIPTION("ATH79 USB PHY driver");
++MODULE_AUTHOR("Alban Bedel <albeu@free.fr>");
++MODULE_LICENSE("GPL");
--- /dev/null
+From 2201818e5bd33f389beceb3943fdfcf5a698fc5b Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 6 Mar 2018 10:01:43 +0100
+Subject: [PATCH 05/27] usb: add more OF/quirk properties
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/usb/host/ehci-platform.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/usb/host/ehci-platform.c
++++ b/drivers/usb/host/ehci-platform.c
+@@ -274,6 +274,11 @@ static int ehci_platform_probe(struct pl
+ ehci = hcd_to_ehci(hcd);
+
+ if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
++ of_property_read_u32(dev->dev.of_node, "caps-offset", &pdata->caps_offset);
++
++ if (of_property_read_bool(dev->dev.of_node, "has-synopsys-hc-bug"))
++ pdata->has_synopsys_hc_bug = 1;
++
+ if (of_property_read_bool(dev->dev.of_node, "big-endian-regs"))
+ ehci->big_endian_mmio = 1;
+
--- /dev/null
+From: John Crispin <john@phrozen.org>
+Subject: [PATCH] ath79: add new OF only target for QCA MIPS silicon
+
+This target aims to replace ar71xx mid-term. The big part that is still
+missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik
+subtargets will follow.
+
+Submitted-by: John Crispin <john@phrozen.org>
+---
+ drivers/net/ethernet/atheros/Kconfig | 8 +-------
+ drivers/net/ethernet/atheros/Makefile | 2 +-
+ 2 files changed, 2 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/ethernet/atheros/Kconfig
++++ b/drivers/net/ethernet/atheros/Kconfig
+@@ -17,14 +17,7 @@ config NET_VENDOR_ATHEROS
+
+ if NET_VENDOR_ATHEROS
+
+-config AG71XX
+- tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
+- depends on ATH79
+- select PHYLINK
+- imply NET_SELFTESTS
+- help
+- If you wish to compile a kernel for AR7XXX/91XXX and enable
+- ethernet support, then you should always answer Y to this.
++source "drivers/net/ethernet/atheros/ag71xx/Kconfig"
+
+ config ATL2
+ tristate "Atheros L2 Fast Ethernet support"
+--- a/drivers/net/ethernet/atheros/Makefile
++++ b/drivers/net/ethernet/atheros/Makefile
+@@ -3,7 +3,7 @@
+ # Makefile for the Atheros network device drivers.
+ #
+
+-obj-$(CONFIG_AG71XX) += ag71xx.o
++obj-$(CONFIG_AG71XX) += ag71xx/
+ obj-$(CONFIG_ATL1) += atlx/
+ obj-$(CONFIG_ATL2) += atlx/
+ obj-$(CONFIG_ATL1E) += atl1e/
--- /dev/null
+From: Jonas Gorski <jogo@openwrt.org>
+Subject: ar71xx: add a workaround for ar8316 not always driving the TA bit to low
+
+AR8316 behind a GPIO bitbanged MDIO bus fails to drive the turnaround bit
+to low despite returning a valid value. Ignore it and just use the
+returned value anyway.
+
+SVN-Revision: 28422
+---
+ drivers/net/mdio/mdio-bitbang.c | 16 ++-----------------
+ 1 file changed, 2 insertions(+), 14 deletions(-)
+
+--- a/drivers/net/mdio/mdio-bitbang.c
++++ b/drivers/net/mdio/mdio-bitbang.c
+@@ -148,23 +148,11 @@ static void mdiobb_cmd_addr(struct mdiob
+ static int mdiobb_read_common(struct mii_bus *bus, int phy)
+ {
+ struct mdiobb_ctrl *ctrl = bus->priv;
+- int ret, i;
++ int ret;
+
+ ctrl->ops->set_mdio_dir(ctrl, 0);
+
+- /* check the turnaround bit: the PHY should be driving it to zero, if this
+- * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that
+- */
+- if (mdiobb_get_bit(ctrl) != 0 &&
+- !(bus->phy_ignore_ta_mask & (1 << phy))) {
+- /* PHY didn't drive TA low -- flush any bits it
+- * may be trying to send.
+- */
+- for (i = 0; i < 32; i++)
+- mdiobb_get_bit(ctrl);
+-
+- return 0xffff;
+- }
++ mdiobb_get_bit(ctrl);
+
+ ret = mdiobb_get_num(ctrl, 16);
+ mdiobb_get_bit(ctrl);
--- /dev/null
+From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Tue, 16 Jun 2015 13:15:08 +0200
+Subject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command
+
+It seems some phys have some maximum timings for accessing the MDIO line,
+resulting in bit errors under cpu stress. Prevent this from happening by
+disabling interrupts when sending commands.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/net/mdio/mdio-bitbang.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/drivers/net/mdio/mdio-bitbang.c
++++ b/drivers/net/mdio/mdio-bitbang.c
+@@ -14,6 +14,7 @@
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ */
+
++#include <linux/irqflags.h>
+ #include <linux/delay.h>
+ #include <linux/mdio-bitbang.h>
+ #include <linux/module.h>
+@@ -161,22 +162,32 @@ static int mdiobb_read_common(struct mii
+
+ int mdiobb_read_c22(struct mii_bus *bus, int phy, int reg)
+ {
++ int ret;
++ unsigned long flags;
+ struct mdiobb_ctrl *ctrl = bus->priv;
+
++ local_irq_save(flags);
+ mdiobb_cmd(ctrl, ctrl->op_c22_read, phy, reg);
+
+- return mdiobb_read_common(bus, phy);
++ ret = mdiobb_read_common(bus, phy);
++ local_irq_restore(flags);
++ return ret;
+ }
+ EXPORT_SYMBOL(mdiobb_read_c22);
+
+ int mdiobb_read_c45(struct mii_bus *bus, int phy, int devad, int reg)
+ {
++ int ret;
++ unsigned long flags;
+ struct mdiobb_ctrl *ctrl = bus->priv;
+
++ local_irq_save(flags);
+ mdiobb_cmd_addr(ctrl, phy, devad, reg);
+ mdiobb_cmd(ctrl, MDIO_C45_READ, phy, devad);
+
+- return mdiobb_read_common(bus, phy);
++ ret = mdiobb_read_common(bus, phy);
++ local_irq_restore(flags);
++ return ret;
+ }
+ EXPORT_SYMBOL(mdiobb_read_c45);
+
+@@ -197,22 +208,32 @@ static int mdiobb_write_common(struct mi
+
+ int mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, u16 val)
+ {
++ int ret;
++ unsigned long flags;
+ struct mdiobb_ctrl *ctrl = bus->priv;
+
++ local_irq_save(flags);
+ mdiobb_cmd(ctrl, ctrl->op_c22_write, phy, reg);
+
+- return mdiobb_write_common(bus, val);
++ ret = mdiobb_write_common(bus, val);
++ local_irq_restore(flags);
++ return ret;
+ }
+ EXPORT_SYMBOL(mdiobb_write_c22);
+
+ int mdiobb_write_c45(struct mii_bus *bus, int phy, int devad, int reg, u16 val)
+ {
++ int ret;
++ unsigned long flags;
+ struct mdiobb_ctrl *ctrl = bus->priv;
+
++ local_irq_save(flags);
+ mdiobb_cmd_addr(ctrl, phy, devad, reg);
+ mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, devad);
+
+- return mdiobb_write_common(bus, val);
++ ret = mdiobb_write_common(bus, val);
++ local_irq_restore(flags);
++ return ret;
+ }
+ EXPORT_SYMBOL(mdiobb_write_c45);
+
--- /dev/null
+From b3797d1a92afe97c173b00fdb7824cedba24eef0 Mon Sep 17 00:00:00 2001
+From: Chuanhong Guo <gch981213@gmail.com>
+Date: Sun, 20 Sep 2020 01:00:45 +0800
+Subject: [PATCH] ath79: ar8216: make switch register access atomic
+
+due to some unknown reason these register accesses sometimes fail
+on the integrated switch without this patch.
+
+THIS ONLY WORKS ON ATH79 AND MAY BREAK THE DRIVER ON OTHER PLATFORMS!
+The mdio bus on ath79 works in polling mode and doesn't rely on
+any interrupt. This patch breaks the driver on any mdio master
+with interrupts used.
+
+---
+--- a/drivers/net/phy/ar8216.c
++++ b/drivers/net/phy/ar8216.c
+@@ -252,6 +252,7 @@ ar8xxx_mii_write32(struct ar8xxx_priv *p
+ u32
+ ar8xxx_read(struct ar8xxx_priv *priv, int reg)
+ {
++ unsigned long flags;
+ struct mii_bus *bus = priv->mii_bus;
+ u16 r1, r2, page;
+ u32 val;
+@@ -259,11 +260,13 @@ ar8xxx_read(struct ar8xxx_priv *priv, in
+ split_addr((u32) reg, &r1, &r2, &page);
+
+ mutex_lock(&bus->mdio_lock);
++ local_irq_save(flags);
+
+ bus->write(bus, 0x18, 0, page);
+ wait_for_page_switch();
+ val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
+
++ local_irq_restore(flags);
+ mutex_unlock(&bus->mdio_lock);
+
+ return val;
+@@ -272,17 +275,20 @@ ar8xxx_read(struct ar8xxx_priv *priv, in
+ void
+ ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
+ {
++ unsigned long flags;
+ struct mii_bus *bus = priv->mii_bus;
+ u16 r1, r2, page;
+
+ split_addr((u32) reg, &r1, &r2, &page);
+
+ mutex_lock(&bus->mdio_lock);
++ local_irq_save(flags);
+
+ bus->write(bus, 0x18, 0, page);
+ wait_for_page_switch();
+ ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
+
++ local_irq_restore(flags);
+ mutex_unlock(&bus->mdio_lock);
+ }
+
--- /dev/null
+From ecbd9c87f073f097d9fe56390353e64e963e866a Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 6 Mar 2018 10:03:03 +0100
+Subject: [PATCH 03/27] leds: add reset-controller based driver
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/leds/Kconfig | 11 ++++
+ drivers/leds/Makefile | 1 +
+ drivers/leds/leds-reset.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 149 insertions(+)
+ create mode 100644 drivers/leds/leds-reset.c
+
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -901,6 +901,17 @@ source "drivers/leds/flash/Kconfig"
+ comment "RGB LED drivers"
+ source "drivers/leds/rgb/Kconfig"
+
++config LEDS_RESET
++ tristate "LED support for reset-controller API"
++ depends on LEDS_CLASS
++ depends on RESET_CONTROLLER
++ help
++ This option enables support for LEDs connected to pins driven by reset
++ controllers. Yes, DNI actual built HW like that.
++
++ To compile this driver as a module, choose M here: the module
++ will be called leds-reset.
++
+ comment "LED Triggers"
+ source "drivers/leds/trigger/Kconfig"
+
+--- /dev/null
++++ b/drivers/leds/leds-reset.c
+@@ -0,0 +1,140 @@
++/*
++ * Copyright (C) 2018 John Crispin <john@phrozen.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++#include <linux/err.h>
++#include <linux/reset.h>
++#include <linux/kernel.h>
++#include <linux/leds.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/reset.h>
++
++struct reset_led_data {
++ struct led_classdev cdev;
++ struct reset_control *rst;
++};
++
++static inline struct reset_led_data *
++ cdev_to_reset_led_data(struct led_classdev *led_cdev)
++{
++ return container_of(led_cdev, struct reset_led_data, cdev);
++}
++
++static void reset_led_set(struct led_classdev *led_cdev,
++ enum led_brightness value)
++{
++ struct reset_led_data *led_dat = cdev_to_reset_led_data(led_cdev);
++
++ if (value == LED_OFF)
++ reset_control_assert(led_dat->rst);
++ else
++ reset_control_deassert(led_dat->rst);
++}
++
++struct reset_leds_priv {
++ int num_leds;
++ struct reset_led_data leds[];
++};
++
++static inline int sizeof_reset_leds_priv(int num_leds)
++{
++ return sizeof(struct reset_leds_priv) +
++ (sizeof(struct reset_led_data) * num_leds);
++}
++
++static struct reset_leds_priv *reset_leds_create(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct fwnode_handle *child;
++ struct reset_leds_priv *priv;
++ int count, ret;
++
++ count = device_get_child_node_count(dev);
++ if (!count)
++ return ERR_PTR(-ENODEV);
++
++ priv = devm_kzalloc(dev, sizeof_reset_leds_priv(count), GFP_KERNEL);
++ if (!priv)
++ return ERR_PTR(-ENOMEM);
++
++ device_for_each_child_node(dev, child) {
++ struct reset_led_data *led = &priv->leds[priv->num_leds];
++ struct device_node *np = to_of_node(child);
++
++ ret = fwnode_property_read_string(child, "label", &led->cdev.name);
++ if (!led->cdev.name) {
++ fwnode_handle_put(child);
++ return ERR_PTR(-EINVAL);
++ }
++ led->rst = __of_reset_control_get(np, NULL, 0, 0, 0, true);
++ if (IS_ERR(led->rst))
++ return ERR_PTR(-EINVAL);
++
++ fwnode_property_read_string(child, "linux,default-trigger",
++ &led->cdev.default_trigger);
++
++ led->cdev.brightness_set = reset_led_set;
++ ret = devm_led_classdev_register(&pdev->dev, &led->cdev);
++ if (ret < 0)
++ return ERR_PTR(ret);
++ led->cdev.dev->of_node = np;
++ priv->num_leds++;
++ }
++
++ return priv;
++}
++
++static const struct of_device_id of_reset_leds_match[] = {
++ { .compatible = "reset-leds", },
++ {},
++};
++
++MODULE_DEVICE_TABLE(of, of_reset_leds_match);
++
++static int reset_led_probe(struct platform_device *pdev)
++{
++ struct reset_leds_priv *priv;
++
++ priv = reset_leds_create(pdev);
++ if (IS_ERR(priv))
++ return PTR_ERR(priv);
++
++ platform_set_drvdata(pdev, priv);
++
++ return 0;
++}
++
++static void reset_led_shutdown(struct platform_device *pdev)
++{
++ struct reset_leds_priv *priv = platform_get_drvdata(pdev);
++ int i;
++
++ for (i = 0; i < priv->num_leds; i++) {
++ struct reset_led_data *led = &priv->leds[i];
++
++ if (!(led->cdev.flags & LED_RETAIN_AT_SHUTDOWN))
++ reset_led_set(&led->cdev, LED_OFF);
++ }
++}
++
++static struct platform_driver reset_led_driver = {
++ .probe = reset_led_probe,
++ .shutdown = reset_led_shutdown,
++ .driver = {
++ .name = "leds-reset",
++ .of_match_table = of_reset_leds_match,
++ },
++};
++
++module_platform_driver(reset_led_driver);
++
++MODULE_AUTHOR("John Crispin <john@phrozen.org>");
++MODULE_DESCRIPTION("reset controller LED driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:leds-reset");
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -88,6 +88,7 @@ obj-$(CONFIG_LEDS_TURRIS_OMNIA) += leds
+ obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o
+ obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o
+ obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o
++obj-$(CONFIG_LEDS_RESET) += leds-reset.o
+
+ # LED SPI Drivers
+ obj-$(CONFIG_LEDS_CR0014114) += leds-cr0014114.o
--- /dev/null
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Wed, 31 May 2023 00:15:23 +0000
+Subject: [PATCH] ath79: ignore the abused interrupt-map on pcie node
+
+ath79 PCIe interrupt controller has stopped working correctly. This
+is because the DT exposing a non-sensical interrupt-map property,
+and their drivers relying on the kernel ignoring this property[1].
+
+This patch fix the pcie init error:
+ath9k 0000:00:00.0: of_irq_parse_pci: failed with rc=-14
+
+Notice:
+This is just a workaround, not a fix. PCIe driver and related dts
+node need to be rewritten.
+
+[1] https://lore.kernel.org/all/20211201114102.13446-1-maz@kernel.org/
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/of/irq.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/of/irq.c
++++ b/drivers/of/irq.c
+@@ -86,6 +86,8 @@ EXPORT_SYMBOL_GPL(of_irq_find_parent);
+ * drawing board.
+ */
+ static const char * const of_irq_imap_abusers[] = {
++ "qca,ar7100-pci",
++ "qcom,ar7240-pci",
+ "CBEA,platform-spider-pic",
+ "sti,platform-spider-pic",
+ "realtek,rtl-intc",
--- /dev/null
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Wed, 13 Mar 2024 22:36:31 +0800
+Subject: [PATCH] mfd: syscon: support skip reset control for syscon devices
+
+Some platform device drivers(e.g. ag71xx) expect exclusive reset
+control. Fetching reset controller for syscon[1] will break these
+drivers. This patch introduces a new property 'syscon-no-reset'
+to skip it.
+
+[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit?id=7d1e3bd94828ad9fc86f55253cd6fec8edd65394
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/mfd/syscon.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/mfd/syscon.c
++++ b/drivers/mfd/syscon.c
+@@ -52,7 +52,7 @@ static struct syscon *of_syscon_register
+ int ret;
+ struct regmap_config syscon_config = syscon_regmap_config;
+ struct resource res;
+- struct reset_control *reset;
++ struct reset_control *reset = NULL;
+
+ syscon = kzalloc(sizeof(*syscon), GFP_KERNEL);
+ if (!syscon)
+@@ -134,7 +134,8 @@ static struct syscon *of_syscon_register
+ goto err_attach_clk;
+ }
+
+- reset = of_reset_control_get_optional_exclusive(np, NULL);
++ if (!of_property_read_bool(np, "syscon-no-reset"))
++ reset = of_reset_control_get_optional_exclusive(np, NULL);
+ if (IS_ERR(reset)) {
+ ret = PTR_ERR(reset);
+ goto err_attach_clk;
--- /dev/null
+From: Felix Fietkau <nbd@openwrt.org>
+Subject: [PATCH] ar71xx: fix unaligned access in a few more places
+
+SVN-Revision: 35130
+---
+ arch/mips/include/asm/checksum.h | 83 +++---------------
+ include/uapi/linux/ip.h | 2 +-
+ include/uapi/linux/ipv6.h | 2 +-
+ include/uapi/linux/tcp.h | 4 ++--
+ include/uapi/linux/udp.h | 2 +-
+ net/netfilter/nf_conntrack_core.c | 4 ++--
+ include/uapi/linux/icmp.h | 2 +-
+ include/uapi/linux/in6.h | 2 +-
+ net/ipv6/tcp_ipv6.c | 9 +++--
+ net/ipv6/datagram.c | 6 ++--
+ net/ipv6/exthdrs.c | 2 +-
+ include/linux/types.h | 5 +++
+ net/ipv4/af_inet.c | 4 ++--
+ net/ipv4/tcp_output.c | 69 +++++++++--------
+ include/uapi/linux/igmp.h | 8 +++---
+ net/core/flow_dissector.c | 2 +-
+ include/uapi/linux/icmpv6.h | 2 +-
+ include/net/ndisc.h | 10 ++++----
+ net/sched/cls_u32.c | 6 +++---
+ net/ipv6/ip6_offload.c | 2 +-
+ include/net/addrconf.h | 2 +-
+ include/net/inet_ecn.h | 4 ++--
+ include/net/ipv6.h | 23 +++++----
+ include/net/secure_seq.h | 1 +
+ include/uapi/linux/in.h | 2 +-
+ net/ipv6/ip6_fib.h | 2 +-
+ net/netfilter/nf_conntrack_proto_tcp.c | 2 +-
+ net/xfrm/xfrm_input.c | 4 ++--
+ net/ipv4/tcp_input.c | 12 ++++---
+ include/uapi/linux/if_pppox.h | 1 +
+ net/ipv6/netfilter/nf_log_ipv6.c | 4 ++--
+ include/net/neighbour.h | 6 +++--
+ include/uapi/linux/netfilter_arp/arp_tables.h | 2 +-
+ net/core/utils.c | 10 +++++--
+ include/linux/etherdevice.h | 11 ++++---
+ net/ipv4/tcp_offload.c | 6 +++---
+ net/ipv6/netfilter/ip6table_mangle.c | 4 ++--
+ 37 file changed, 171 insertions(+), 141 deletions(-)
+
+--- a/arch/mips/include/asm/checksum.h
++++ b/arch/mips/include/asm/checksum.h
+@@ -100,26 +100,30 @@ static inline __sum16 ip_fast_csum(const
+ const unsigned int *stop = word + ihl;
+ unsigned int csum;
+ int carry;
++ unsigned int w;
+
+- csum = word[0];
+- csum += word[1];
+- carry = (csum < word[1]);
++ csum = net_hdr_word(word++);
++
++ w = net_hdr_word(word++);
++ csum += w;
++ carry = (csum < w);
+ csum += carry;
+
+- csum += word[2];
+- carry = (csum < word[2]);
++ w = net_hdr_word(word++);
++ csum += w;
++ carry = (csum < w);
+ csum += carry;
+
+- csum += word[3];
+- carry = (csum < word[3]);
++ w = net_hdr_word(word++);
++ csum += w;
++ carry = (csum < w);
+ csum += carry;
+
+- word += 4;
+ do {
+- csum += *word;
+- carry = (csum < *word);
++ w = net_hdr_word(word++);
++ csum += w;
++ carry = (csum < w);
+ csum += carry;
+- word++;
+ } while (word != stop);
+
+ return csum_fold(csum);
+@@ -179,74 +183,6 @@ static inline __sum16 ip_compute_csum(co
+ return csum_fold(csum_partial(buff, len, 0));
+ }
+
+-#define _HAVE_ARCH_IPV6_CSUM
+-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
+- const struct in6_addr *daddr,
+- __u32 len, __u8 proto,
+- __wsum sum)
+-{
+- __wsum tmp;
+-
+- __asm__(
+- " .set push # csum_ipv6_magic\n"
+- " .set noreorder \n"
+- " .set noat \n"
+- " addu %0, %5 # proto (long in network byte order)\n"
+- " sltu $1, %0, %5 \n"
+- " addu %0, $1 \n"
+-
+- " addu %0, %6 # csum\n"
+- " sltu $1, %0, %6 \n"
+- " lw %1, 0(%2) # four words source address\n"
+- " addu %0, $1 \n"
+- " addu %0, %1 \n"
+- " sltu $1, %0, %1 \n"
+-
+- " lw %1, 4(%2) \n"
+- " addu %0, $1 \n"
+- " addu %0, %1 \n"
+- " sltu $1, %0, %1 \n"
+-
+- " lw %1, 8(%2) \n"
+- " addu %0, $1 \n"
+- " addu %0, %1 \n"
+- " sltu $1, %0, %1 \n"
+-
+- " lw %1, 12(%2) \n"
+- " addu %0, $1 \n"
+- " addu %0, %1 \n"
+- " sltu $1, %0, %1 \n"
+-
+- " lw %1, 0(%3) \n"
+- " addu %0, $1 \n"
+- " addu %0, %1 \n"
+- " sltu $1, %0, %1 \n"
+-
+- " lw %1, 4(%3) \n"
+- " addu %0, $1 \n"
+- " addu %0, %1 \n"
+- " sltu $1, %0, %1 \n"
+-
+- " lw %1, 8(%3) \n"
+- " addu %0, $1 \n"
+- " addu %0, %1 \n"
+- " sltu $1, %0, %1 \n"
+-
+- " lw %1, 12(%3) \n"
+- " addu %0, $1 \n"
+- " addu %0, %1 \n"
+- " sltu $1, %0, %1 \n"
+-
+- " addu %0, $1 # Add final carry\n"
+- " .set pop"
+- : "=&r" (sum), "=&r" (tmp)
+- : "r" (saddr), "r" (daddr),
+- "0" (htonl(len)), "r" (htonl(proto)), "r" (sum)
+- : "memory");
+-
+- return csum_fold(sum);
+-}
+-
+ #include <asm-generic/checksum.h>
+ #endif /* CONFIG_GENERIC_CSUM */
+
+--- a/include/uapi/linux/ip.h
++++ b/include/uapi/linux/ip.h
+@@ -106,7 +106,7 @@ struct iphdr {
+ __be32 daddr;
+ );
+ /*The options start here. */
+-};
++} __attribute__((packed, aligned(2)));
+
+
+ struct ip_auth_hdr {
+--- a/include/uapi/linux/ipv6.h
++++ b/include/uapi/linux/ipv6.h
+@@ -135,7 +135,7 @@ struct ipv6hdr {
+ struct in6_addr saddr;
+ struct in6_addr daddr;
+ );
+-};
++} __attribute__((packed, aligned(2)));
+
+
+ /* index values for the variables in ipv6_devconf */
+--- a/include/uapi/linux/tcp.h
++++ b/include/uapi/linux/tcp.h
+@@ -55,7 +55,7 @@ struct tcphdr {
+ __be16 window;
+ __sum16 check;
+ __be16 urg_ptr;
+-};
++} __attribute__((packed, aligned(2)));
+
+ /*
+ * The union cast uses a gcc extension to avoid aliasing problems
+@@ -65,7 +65,7 @@ struct tcphdr {
+ union tcp_word_hdr {
+ struct tcphdr hdr;
+ __be32 words[5];
+-};
++} __attribute__((packed, aligned(2)));
+
+ #define tcp_flag_word(tp) (((union tcp_word_hdr *)(tp))->words[3])
+
+--- a/include/uapi/linux/udp.h
++++ b/include/uapi/linux/udp.h
+@@ -25,7 +25,7 @@ struct udphdr {
+ __be16 dest;
+ __be16 len;
+ __sum16 check;
+-};
++} __attribute__((packed, aligned(2)));
+
+ /* UDP socket options */
+ #define UDP_CORK 1 /* Never send partially complete segments */
+--- a/net/netfilter/nf_conntrack_core.c
++++ b/net/netfilter/nf_conntrack_core.c
+@@ -298,8 +298,8 @@ nf_ct_get_tuple(const struct sk_buff *sk
+
+ switch (l3num) {
+ case NFPROTO_IPV4:
+- tuple->src.u3.ip = ap[0];
+- tuple->dst.u3.ip = ap[1];
++ tuple->src.u3.ip = net_hdr_word(ap++);
++ tuple->dst.u3.ip = net_hdr_word(ap);
+ break;
+ case NFPROTO_IPV6:
+ memcpy(tuple->src.u3.ip6, ap, sizeof(tuple->src.u3.ip6));
+--- a/include/uapi/linux/icmp.h
++++ b/include/uapi/linux/icmp.h
+@@ -102,7 +102,7 @@ struct icmphdr {
+ } frag;
+ __u8 reserved[4];
+ } un;
+-};
++} __attribute__((packed, aligned(2)));
+
+
+ /*
+--- a/include/uapi/linux/in6.h
++++ b/include/uapi/linux/in6.h
+@@ -43,7 +43,7 @@ struct in6_addr {
+ #define s6_addr16 in6_u.u6_addr16
+ #define s6_addr32 in6_u.u6_addr32
+ #endif
+-};
++} __attribute__((packed, aligned(2)));
+ #endif /* __UAPI_DEF_IN6_ADDR */
+
+ #if __UAPI_DEF_SOCKADDR_IN6
+--- a/net/ipv6/tcp_ipv6.c
++++ b/net/ipv6/tcp_ipv6.c
+@@ -35,6 +35,7 @@
+ #include <linux/ipsec.h>
+ #include <linux/times.h>
+ #include <linux/slab.h>
++#include <asm/unaligned.h>
+ #include <linux/uaccess.h>
+ #include <linux/ipv6.h>
+ #include <linux/icmpv6.h>
+@@ -897,10 +898,10 @@ static void tcp_v6_send_response(const s
+ topt = (__be32 *)(t1 + 1);
+
+ if (tsecr) {
+- *topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
+- (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP);
+- *topt++ = htonl(tsval);
+- *topt++ = htonl(tsecr);
++ put_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
++ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++);
++ put_unaligned_be32(tsval, topt++);
++ put_unaligned_be32(tsecr, topt++);
+ }
+
+ if (mrst)
+--- a/include/linux/ipv6.h
++++ b/include/linux/ipv6.h
+@@ -6,6 +6,7 @@
+
+ #define ipv6_optlen(p) (((p)->hdrlen+1) << 3)
+ #define ipv6_authlen(p) (((p)->hdrlen+2) << 2)
++
+ /*
+ * This structure contains configuration options per IPv6 link.
+ */
+--- a/net/ipv6/datagram.c
++++ b/net/ipv6/datagram.c
+@@ -499,7 +499,7 @@ int ipv6_recv_error(struct sock *sk, str
+ ipv6_iface_scope_id(&sin->sin6_addr,
+ IP6CB(skb)->iif);
+ } else {
+- ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset),
++ ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset),
+ &sin->sin6_addr);
+ sin->sin6_scope_id = 0;
+ }
+@@ -853,12 +853,12 @@ int ip6_datagram_send_ctl(struct net *ne
+ }
+
+ if (fl6->flowlabel&IPV6_FLOWINFO_MASK) {
+- if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) {
++ if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) {
+ err = -EINVAL;
+ goto exit_f;
+ }
+ }
+- fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg);
++ fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg));
+ break;
+
+ case IPV6_2292HOPOPTS:
+--- a/net/ipv6/exthdrs.c
++++ b/net/ipv6/exthdrs.c
+@@ -982,7 +982,7 @@ static bool ipv6_hop_jumbo(struct sk_buf
+ goto drop;
+ }
+
+- pkt_len = ntohl(*(__be32 *)(nh + optoff + 2));
++ pkt_len = ntohl(net_hdr_word(nh + optoff + 2));
+ if (pkt_len <= IPV6_MAXPLEN) {
+ icmpv6_param_prob_reason(skb, ICMPV6_HDR_FIELD, optoff + 2,
+ SKB_DROP_REASON_IP_INHDR);
+--- a/include/linux/types.h
++++ b/include/linux/types.h
+@@ -244,5 +244,11 @@ typedef void (*swap_func_t)(void *a, voi
+ typedef int (*cmp_r_func_t)(const void *a, const void *b, const void *priv);
+ typedef int (*cmp_func_t)(const void *a, const void *b);
+
++struct net_hdr_word {
++ u32 words[1];
++} __attribute__((packed, aligned(2)));
++
++#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0])
++
+ #endif /* __ASSEMBLY__ */
+ #endif /* _LINUX_TYPES_H */
+--- a/net/ipv4/af_inet.c
++++ b/net/ipv4/af_inet.c
+@@ -1506,8 +1506,8 @@ struct sk_buff *inet_gro_receive(struct
+ goto out;
+
+ NAPI_GRO_CB(skb)->proto = proto;
+- id = ntohl(*(__be32 *)&iph->id);
+- flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF));
++ id = ntohl(net_hdr_word(&iph->id));
++ flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF));
+ id >>= 16;
+
+ list_for_each_entry(p, head, list) {
+--- a/net/ipv4/tcp_output.c
++++ b/net/ipv4/tcp_output.c
+@@ -620,48 +620,53 @@ static void tcp_options_write(struct tcp
+ u16 options = opts->options; /* mungable copy */
+
+ if (unlikely(OPTION_MD5 & options)) {
+- *ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
+- (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
++ net_hdr_word(ptr++) =
++ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
++ (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);
+ /* overload cookie hash location */
+ opts->hash_location = (__u8 *)ptr;
+ ptr += 4;
+ }
+
+ if (unlikely(opts->mss)) {
+- *ptr++ = htonl((TCPOPT_MSS << 24) |
+- (TCPOLEN_MSS << 16) |
+- opts->mss);
++ net_hdr_word(ptr++) =
++ htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) |
++ opts->mss);
+ }
+
+ if (likely(OPTION_TS & options)) {
+ if (unlikely(OPTION_SACK_ADVERTISE & options)) {
+- *ptr++ = htonl((TCPOPT_SACK_PERM << 24) |
+- (TCPOLEN_SACK_PERM << 16) |
+- (TCPOPT_TIMESTAMP << 8) |
+- TCPOLEN_TIMESTAMP);
++ net_hdr_word(ptr++) =
++ htonl((TCPOPT_SACK_PERM << 24) |
++ (TCPOLEN_SACK_PERM << 16) |
++ (TCPOPT_TIMESTAMP << 8) |
++ TCPOLEN_TIMESTAMP);
+ options &= ~OPTION_SACK_ADVERTISE;
+ } else {
+- *ptr++ = htonl((TCPOPT_NOP << 24) |
+- (TCPOPT_NOP << 16) |
+- (TCPOPT_TIMESTAMP << 8) |
+- TCPOLEN_TIMESTAMP);
++ net_hdr_word(ptr++) =
++ htonl((TCPOPT_NOP << 24) |
++ (TCPOPT_NOP << 16) |
++ (TCPOPT_TIMESTAMP << 8) |
++ TCPOLEN_TIMESTAMP);
+ }
+- *ptr++ = htonl(opts->tsval);
+- *ptr++ = htonl(opts->tsecr);
++ net_hdr_word(ptr++) = htonl(opts->tsval);
++ net_hdr_word(ptr++) = htonl(opts->tsecr);
+ }
+
+ if (unlikely(OPTION_SACK_ADVERTISE & options)) {
+- *ptr++ = htonl((TCPOPT_NOP << 24) |
+- (TCPOPT_NOP << 16) |
+- (TCPOPT_SACK_PERM << 8) |
+- TCPOLEN_SACK_PERM);
++ net_hdr_word(ptr++) =
++ htonl((TCPOPT_NOP << 24) |
++ (TCPOPT_NOP << 16) |
++ (TCPOPT_SACK_PERM << 8) |
++ TCPOLEN_SACK_PERM);
+ }
+
+ if (unlikely(OPTION_WSCALE & options)) {
+- *ptr++ = htonl((TCPOPT_NOP << 24) |
+- (TCPOPT_WINDOW << 16) |
+- (TCPOLEN_WINDOW << 8) |
+- opts->ws);
++ net_hdr_word(ptr++) =
++ htonl((TCPOPT_NOP << 24) |
++ (TCPOPT_WINDOW << 16) |
++ (TCPOLEN_WINDOW << 8) |
++ opts->ws);
+ }
+
+ if (unlikely(opts->num_sack_blocks)) {
+@@ -669,16 +674,17 @@ static void tcp_options_write(struct tcp
+ tp->duplicate_sack : tp->selective_acks;
+ int this_sack;
+
+- *ptr++ = htonl((TCPOPT_NOP << 24) |
+- (TCPOPT_NOP << 16) |
+- (TCPOPT_SACK << 8) |
+- (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
++ net_hdr_word(ptr++) =
++ htonl((TCPOPT_NOP << 24) |
++ (TCPOPT_NOP << 16) |
++ (TCPOPT_SACK << 8) |
++ (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *
+ TCPOLEN_SACK_PERBLOCK)));
+
+ for (this_sack = 0; this_sack < opts->num_sack_blocks;
+ ++this_sack) {
+- *ptr++ = htonl(sp[this_sack].start_seq);
+- *ptr++ = htonl(sp[this_sack].end_seq);
++ net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq);
++ net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq);
+ }
+
+ tp->rx_opt.dsack = 0;
+@@ -691,13 +697,14 @@ static void tcp_options_write(struct tcp
+
+ if (foc->exp) {
+ len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;
+- *ptr = htonl((TCPOPT_EXP << 24) | (len << 16) |
++ net_hdr_word(ptr) =
++ htonl((TCPOPT_EXP << 24) | (len << 16) |
+ TCPOPT_FASTOPEN_MAGIC);
+ p += TCPOLEN_EXP_FASTOPEN_BASE;
+ } else {
+ len = TCPOLEN_FASTOPEN_BASE + foc->len;
+- *p++ = TCPOPT_FASTOPEN;
+- *p++ = len;
++ net_hdr_word(p++) = TCPOPT_FASTOPEN;
++ net_hdr_word(p++) = len;
+ }
+
+ memcpy(p, foc->val, foc->len);
+--- a/include/uapi/linux/igmp.h
++++ b/include/uapi/linux/igmp.h
+@@ -33,7 +33,7 @@ struct igmphdr {
+ __u8 code; /* For newer IGMP */
+ __sum16 csum;
+ __be32 group;
+-};
++} __attribute__((packed, aligned(2)));
+
+ /* V3 group record types [grec_type] */
+ #define IGMPV3_MODE_IS_INCLUDE 1
+@@ -49,7 +49,7 @@ struct igmpv3_grec {
+ __be16 grec_nsrcs;
+ __be32 grec_mca;
+ __be32 grec_src[];
+-};
++} __attribute__((packed, aligned(2)));
+
+ struct igmpv3_report {
+ __u8 type;
+@@ -58,7 +58,7 @@ struct igmpv3_report {
+ __be16 resv2;
+ __be16 ngrec;
+ struct igmpv3_grec grec[];
+-};
++} __attribute__((packed, aligned(2)));
+
+ struct igmpv3_query {
+ __u8 type;
+@@ -79,7 +79,7 @@ struct igmpv3_query {
+ __u8 qqic;
+ __be16 nsrcs;
+ __be32 srcs[];
+-};
++} __attribute__((packed, aligned(2)));
+
+ #define IGMP_HOST_MEMBERSHIP_QUERY 0x11 /* From RFC1112 */
+ #define IGMP_HOST_MEMBERSHIP_REPORT 0x12 /* Ditto */
+--- a/net/core/flow_dissector.c
++++ b/net/core/flow_dissector.c
+@@ -132,7 +132,7 @@ __be32 __skb_flow_get_ports(const struct
+ ports = __skb_header_pointer(skb, thoff + poff,
+ sizeof(_ports), data, hlen, &_ports);
+ if (ports)
+- return *ports;
++ return (__be32)net_hdr_word(ports);
+ }
+
+ return 0;
+--- a/include/uapi/linux/icmpv6.h
++++ b/include/uapi/linux/icmpv6.h
+@@ -78,7 +78,7 @@ struct icmp6hdr {
+ #define icmp6_addrconf_other icmp6_dataun.u_nd_ra.other
+ #define icmp6_rt_lifetime icmp6_dataun.u_nd_ra.rt_lifetime
+ #define icmp6_router_pref icmp6_dataun.u_nd_ra.router_pref
+-};
++} __attribute__((packed, aligned(2)));
+
+
+ #define ICMPV6_ROUTER_PREF_LOW 0x3
+--- a/include/net/ndisc.h
++++ b/include/net/ndisc.h
+@@ -93,7 +93,7 @@ struct ra_msg {
+ struct icmp6hdr icmph;
+ __be32 reachable_time;
+ __be32 retrans_timer;
+-};
++} __attribute__((packed, aligned(2)));
+
+ struct rd_msg {
+ struct icmp6hdr icmph;
+@@ -372,10 +372,10 @@ static inline u32 ndisc_hashfn(const voi
+ {
+ const u32 *p32 = pkey;
+
+- return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) +
+- (p32[1] * hash_rnd[1]) +
+- (p32[2] * hash_rnd[2]) +
+- (p32[3] * hash_rnd[3]));
++ return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) +
++ (net_hdr_word(&p32[1]) * hash_rnd[1]) +
++ (net_hdr_word(&p32[2]) * hash_rnd[2]) +
++ (net_hdr_word(&p32[3]) * hash_rnd[3]));
+ }
+
+ static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey)
+--- a/net/sched/cls_u32.c
++++ b/net/sched/cls_u32.c
+@@ -157,7 +157,7 @@ next_knode:
+ data = skb_header_pointer(skb, toff, 4, &hdata);
+ if (!data)
+ goto out;
+- if ((*data ^ key->val) & key->mask) {
++ if ((net_hdr_word(data) ^ key->val) & key->mask) {
+ n = rcu_dereference_bh(n->next);
+ goto next_knode;
+ }
+@@ -208,8 +208,8 @@ check_terminal:
+ &hdata);
+ if (!data)
+ goto out;
+- sel = ht->divisor & u32_hash_fold(*data, &n->sel,
+- n->fshift);
++ sel = ht->divisor & u32_hash_fold(net_hdr_word(data),
++ &n->sel, n->fshift);
+ }
+ if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT)))
+ goto next_ht;
+--- a/net/ipv6/ip6_offload.c
++++ b/net/ipv6/ip6_offload.c
+@@ -273,7 +273,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
+ continue;
+
+ iph2 = (struct ipv6hdr *)(p->data + off);
+- first_word = *(__be32 *)iph ^ *(__be32 *)iph2;
++ first_word = net_hdr_word(iph) ^ net_hdr_word(iph2);
+
+ /* All fields must match except length and Traffic Class.
+ * XXX skbs on the gro_list have all been parsed and pulled
+--- a/include/net/addrconf.h
++++ b/include/net/addrconf.h
+@@ -52,7 +52,7 @@ struct prefix_info {
+ __be32 reserved2;
+
+ struct in6_addr prefix;
+-};
++} __attribute__((packed, aligned(2)));
+
+ /* rfc4861 4.6.2: IPv6 PIO is 32 bytes in size */
+ static_assert(sizeof(struct prefix_info) == 32);
+--- a/include/net/inet_ecn.h
++++ b/include/net/inet_ecn.h
+@@ -138,9 +138,9 @@ static inline int IP6_ECN_set_ce(struct
+ if (INET_ECN_is_not_ect(ipv6_get_dsfield(iph)))
+ return 0;
+
+- from = *(__be32 *)iph;
++ from = net_hdr_word(iph);
+ to = from | htonl(INET_ECN_CE << 20);
+- *(__be32 *)iph = to;
++ net_hdr_word(iph) = to;
+ if (skb->ip_summed == CHECKSUM_COMPLETE)
+ skb->csum = csum_add(csum_sub(skb->csum, (__force __wsum)from),
+ (__force __wsum)to);
+--- a/include/net/ipv6.h
++++ b/include/net/ipv6.h
+@@ -149,7 +149,7 @@ struct frag_hdr {
+ __u8 reserved;
+ __be16 frag_off;
+ __be32 identification;
+-};
++} __attribute__((packed, aligned(2)));
+
+ /*
+ * Jumbo payload option, as described in RFC 2675 2.
+@@ -649,8 +649,8 @@ static inline void __ipv6_addr_set_half(
+ }
+ #endif
+ #endif
+- addr[0] = wh;
+- addr[1] = wl;
++ net_hdr_word(&addr[0]) = wh;
++ net_hdr_word(&addr[1]) = wl;
+ }
+
+ static inline void ipv6_addr_set(struct in6_addr *addr,
+@@ -709,6 +709,8 @@ static inline bool ipv6_prefix_equal(con
+ const __be32 *a1 = addr1->s6_addr32;
+ const __be32 *a2 = addr2->s6_addr32;
+ unsigned int pdw, pbi;
++ /* Used for last <32-bit fraction of prefix */
++ u32 pbia1, pbia2;
+
+ /* check complete u32 in prefix */
+ pdw = prefixlen >> 5;
+@@ -717,7 +719,9 @@ static inline bool ipv6_prefix_equal(con
+
+ /* check incomplete u32 in prefix */
+ pbi = prefixlen & 0x1f;
+- if (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi))))
++ pbia1 = net_hdr_word(&a1[pdw]);
++ pbia2 = net_hdr_word(&a2[pdw]);
++ if (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi))))
+ return false;
+
+ return true;
+@@ -839,13 +843,13 @@ static inline void ipv6_addr_set_v4mappe
+ */
+ static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen)
+ {
+- const __be32 *a1 = token1, *a2 = token2;
++ const struct in6_addr *a1 = token1, *a2 = token2;
+ int i;
+
+ addrlen >>= 2;
+
+ for (i = 0; i < addrlen; i++) {
+- __be32 xb = a1[i] ^ a2[i];
++ __be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i];
+ if (xb)
+ return i * 32 + 31 - __fls(ntohl(xb));
+ }
+@@ -1040,17 +1044,18 @@ static inline u32 ip6_multipath_hash_fie
+ static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass,
+ __be32 flowlabel)
+ {
+- *(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel;
++ net_hdr_word((__be32 *)hdr) =
++ htonl(0x60000000 | (tclass << 20)) | flowlabel;
+ }
+
+ static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr)
+ {
+- return *(__be32 *)hdr & IPV6_FLOWINFO_MASK;
++ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK;
+ }
+
+ static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr)
+ {
+- return *(__be32 *)hdr & IPV6_FLOWLABEL_MASK;
++ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK;
+ }
+
+ static inline u8 ip6_tclass(__be32 flowinfo)
+--- a/include/net/secure_seq.h
++++ b/include/net/secure_seq.h
+@@ -3,6 +3,7 @@
+ #define _NET_SECURE_SEQ
+
+ #include <linux/types.h>
++#include <linux/in6.h>
+
+ struct net;
+
+--- a/include/uapi/linux/in.h
++++ b/include/uapi/linux/in.h
+@@ -91,7 +91,7 @@ enum {
+ /* Internet address. */
+ struct in_addr {
+ __be32 s_addr;
+-};
++} __attribute__((packed, aligned(2)));
+ #endif
+
+ #define IP_TOS 1
+--- a/net/ipv6/ip6_fib.c
++++ b/net/ipv6/ip6_fib.c
+@@ -141,7 +141,7 @@ static __be32 addr_bit_set(const void *t
+ * See include/asm-generic/bitops/le.h.
+ */
+ return (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) &
+- addr[fn_bit >> 5];
++ net_hdr_word(&addr[fn_bit >> 5]);
+ }
+
+ struct fib6_info *fib6_info_alloc(gfp_t gfp_flags, bool with_fib6_nh)
+--- a/net/netfilter/nf_conntrack_proto_tcp.c
++++ b/net/netfilter/nf_conntrack_proto_tcp.c
+@@ -406,7 +406,7 @@ static void tcp_sack(const struct sk_buf
+
+ /* Fast path for timestamp-only option */
+ if (length == TCPOLEN_TSTAMP_ALIGNED
+- && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24)
++ && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24)
+ | (TCPOPT_NOP << 16)
+ | (TCPOPT_TIMESTAMP << 8)
+ | TCPOLEN_TIMESTAMP))
+--- a/net/xfrm/xfrm_input.c
++++ b/net/xfrm/xfrm_input.c
+@@ -168,8 +168,8 @@ int xfrm_parse_spi(struct sk_buff *skb,
+ if (!pskb_may_pull(skb, hlen))
+ return -EINVAL;
+
+- *spi = *(__be32 *)(skb_transport_header(skb) + offset);
+- *seq = *(__be32 *)(skb_transport_header(skb) + offset_seq);
++ *spi = net_hdr_word(skb_transport_header(skb) + offset);
++ *seq = net_hdr_word(skb_transport_header(skb) + offset_seq);
+ return 0;
+ }
+ EXPORT_SYMBOL(xfrm_parse_spi);
+--- a/net/ipv4/tcp_input.c
++++ b/net/ipv4/tcp_input.c
+@@ -4188,14 +4188,16 @@ static bool tcp_parse_aligned_timestamp(
+ {
+ const __be32 *ptr = (const __be32 *)(th + 1);
+
+- if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16)
+- | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
++ if (net_hdr_word(ptr) ==
++ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |
++ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {
+ tp->rx_opt.saw_tstamp = 1;
+ ++ptr;
+- tp->rx_opt.rcv_tsval = ntohl(*ptr);
++ tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr);
+ ++ptr;
+- if (*ptr)
+- tp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset;
++ if (net_hdr_word(ptr))
++ tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) -
++ tp->tsoffset;
+ else
+ tp->rx_opt.rcv_tsecr = 0;
+ return true;
+--- a/include/uapi/linux/if_pppox.h
++++ b/include/uapi/linux/if_pppox.h
+@@ -51,6 +51,7 @@ struct pppoe_addr {
+ */
+ struct pptp_addr {
+ __u16 call_id;
++ __u16 pad;
+ struct in_addr sin_addr;
+ };
+
+--- a/include/net/neighbour.h
++++ b/include/net/neighbour.h
+@@ -286,8 +286,10 @@ static inline bool neigh_key_eq128(const
+ const u32 *n32 = (const u32 *)n->primary_key;
+ const u32 *p32 = pkey;
+
+- return ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) |
+- (n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0;
++ return ((n32[0] ^ net_hdr_word(&p32[0])) |
++ (n32[1] ^ net_hdr_word(&p32[1])) |
++ (n32[2] ^ net_hdr_word(&p32[2])) |
++ (n32[3] ^ net_hdr_word(&p32[3]))) == 0;
+ }
+
+ static inline struct neighbour *___neigh_lookup_noref(
+--- a/include/uapi/linux/netfilter_arp/arp_tables.h
++++ b/include/uapi/linux/netfilter_arp/arp_tables.h
+@@ -70,7 +70,7 @@ struct arpt_arp {
+ __u8 flags;
+ /* Inverse flags */
+ __u16 invflags;
+-};
++} __attribute__((aligned(4)));
+
+ /* Values for "flag" field in struct arpt_ip (general arp structure).
+ * No flags defined yet.
+--- a/net/core/utils.c
++++ b/net/core/utils.c
+@@ -460,8 +460,14 @@ void inet_proto_csum_replace16(__sum16 *
+ bool pseudohdr)
+ {
+ __be32 diff[] = {
+- ~from[0], ~from[1], ~from[2], ~from[3],
+- to[0], to[1], to[2], to[3],
++ ~net_hdr_word(&from[0]),
++ ~net_hdr_word(&from[1]),
++ ~net_hdr_word(&from[2]),
++ ~net_hdr_word(&from[3]),
++ net_hdr_word(&to[0]),
++ net_hdr_word(&to[1]),
++ net_hdr_word(&to[2]),
++ net_hdr_word(&to[3]),
+ };
+ if (skb->ip_summed != CHECKSUM_PARTIAL) {
+ *sum = csum_fold(csum_partial(diff, sizeof(diff),
+--- a/include/linux/etherdevice.h
++++ b/include/linux/etherdevice.h
+@@ -555,7 +555,7 @@ static inline bool is_etherdev_addr(cons
+ * @b: Pointer to Ethernet header
+ *
+ * Compare two Ethernet headers, returns 0 if equal.
+- * This assumes that the network header (i.e., IP header) is 4-byte
++ * This assumes that the network header (i.e., IP header) is 2-byte
+ * aligned OR the platform can handle unaligned access. This is the
+ * case for all packets coming into netif_receive_skb or similar
+ * entry points.
+@@ -578,11 +578,12 @@ static inline unsigned long compare_ethe
+ fold |= *(unsigned long *)(a + 6) ^ *(unsigned long *)(b + 6);
+ return fold;
+ #else
+- u32 *a32 = (u32 *)((u8 *)a + 2);
+- u32 *b32 = (u32 *)((u8 *)b + 2);
++ const u16 *a16 = a;
++ const u16 *b16 = b;
+
+- return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) |
+- (a32[1] ^ b32[1]) | (a32[2] ^ b32[2]);
++ return (a16[0] ^ b16[0]) | (a16[1] ^ b16[1]) | (a16[2] ^ b16[2]) |
++ (a16[3] ^ b16[3]) | (a16[4] ^ b16[4]) | (a16[5] ^ b16[5]) |
++ (a16[6] ^ b16[6]);
+ #endif
+ }
+
+--- a/net/ipv4/tcp_offload.c
++++ b/net/ipv4/tcp_offload.c
+@@ -63,7 +63,7 @@ static struct sk_buff *__tcpv4_gso_segme
+ th2 = tcp_hdr(seg->next);
+ iph2 = ip_hdr(seg->next);
+
+- if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++ if (!(net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) &&
+ iph->daddr == iph2->daddr && iph->saddr == iph2->saddr)
+ return segs;
+
+@@ -255,7 +255,7 @@ struct sk_buff *tcp_gro_lookup(struct li
+ continue;
+
+ th2 = tcp_hdr(p);
+- if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
++ if (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) {
+ NAPI_GRO_CB(p)->same_flow = 0;
+ continue;
+ }
+@@ -321,8 +321,8 @@ struct sk_buff *tcp_gro_receive(struct l
+ ~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH));
+ flush |= (__force int)(th->ack_seq ^ th2->ack_seq);
+ for (i = sizeof(*th); i < thlen; i += 4)
+- flush |= *(u32 *)((u8 *)th + i) ^
+- *(u32 *)((u8 *)th2 + i);
++ flush |= net_hdr_word((u8 *)th + i) ^
++ net_hdr_word((u8 *)th2 + i);
+
+ /* When we receive our second frame we can made a decision on if we
+ * continue this flow as an atomic flow with a fixed ID or if we use
+--- a/net/ipv6/netfilter/ip6table_mangle.c
++++ b/net/ipv6/netfilter/ip6table_mangle.c
+@@ -44,7 +44,7 @@ ip6t_mangle_out(void *priv, struct sk_bu
+ hop_limit = ipv6_hdr(skb)->hop_limit;
+
+ /* flowlabel and prio (includes version, which shouldn't change either */
+- flowlabel = *((u_int32_t *)ipv6_hdr(skb));
++ flowlabel = net_hdr_word(ipv6_hdr(skb));
+
+ ret = ip6t_do_table(priv, skb, state);
+
+@@ -53,7 +53,7 @@ ip6t_mangle_out(void *priv, struct sk_bu
+ !ipv6_addr_equal(&ipv6_hdr(skb)->daddr, &daddr) ||
+ skb->mark != mark ||
+ ipv6_hdr(skb)->hop_limit != hop_limit ||
+- flowlabel != *((u_int32_t *)ipv6_hdr(skb)))) {
++ flowlabel != net_hdr_word(ipv6_hdr(skb)))) {
+ err = ip6_route_me_harder(state->net, state->sk, skb);
+ if (err < 0)
+ ret = NF_DROP_ERR(err);
--- /dev/null
+From: Christopher Hill <ch6574@gmail.com>
+Subject: [PATCH] ath79: add Mikrotik rb4xx series drivers
+
+This adds 3 Mikrotik rb4xx series drivers as follows:
+
+rb4xx-cpld: This is in the mfd subsystem, and is the parent CPLD device
+that interfaces between the SoC SPI bus and its two children below.
+rb4xx-gpio: This is the GPIO expander.
+rb4xx-nand: This is the NAND driver.
+
+The history of this code comes in three phases.
+
+1. The first is a May 2015 attempt to push the equivalient ar71xx rb4xx
+drivers upstream. See https://lore.kernel.org/patchwork/patch/940880/.
+
+Module-author: Gabor Juhos <juhosg@openwrt.org>
+Module-author: Imre Kaloz <kaloz@openwrt.org>
+Module-author: Bert Vermeulen <bert@biot.com>
+
+2. Next several ar71xx patches were applied bringing the code current.
+
+commit 7bbf4117c6fe4b764d9d7c62fb2bcf6dd93bff2c
+Submitted-by: Hauke Mehrtens <hauke@hauke-m.de>
+
+commit af79fdbe4af32a287798b579141204bda056b8aa
+commit 889272d92db689fd9c910243635e44c9d8323095
+commit e21cb649a235180563363b8af5ba8296b9ac0baa
+commit 7c09fa4a7492ca436f2c94bd9a465b7c5bbeed6f
+Submitted-by: Felix Fietkau <nbd@nbd.name>
+
+3. Finally a heavy refactor to split the driver into the three new
+subsystems, and updated to work with the device tree configuration, plus
+updates and review feedback incorporated
+
+Reviewed-by: Thibaut VARÈNE <hacks@slashdirt.org>
+Submitted-by: Christopher Hill <ch6574@gmail.com>
+---
+ drivers/mfd/Kconfig | 8 ++++++++
+ drivers/mfd/Makefile | 1 +
+ drivers/gpio/Kconfig | 6 ++++++
+ drivers/gpio/Makefile | 1 +
+ drivers/mtd/nand/raw/Kconfig | 7 +++++++
+ drivers/mtd/nand/raw/Makefile | 1 +
+ 6 files changed, 24 insertions(+)
+
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -2261,6 +2261,14 @@ config RAVE_SP_CORE
+ Select this to get support for the Supervisory Processor
+ device found on several devices in RAVE line of hardware.
+
++config MFD_RB4XX_CPLD
++ tristate "CPLD driver for Mikrotik RB4xx series boards"
++ select MFD_CORE
++ depends on ATH79 || COMPILE_TEST
++ help
++ Enables support for the CPLD chip (NAND & GPIO) on Mikrotik
++ Routerboard RB4xx series.
++
+ config SGI_MFD_IOC3
+ bool "SGI IOC3 core driver"
+ depends on PCI && MIPS && 64BIT
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -269,6 +269,7 @@ obj-$(CONFIG_MFD_KHADAS_MCU) += khadas-
+ obj-$(CONFIG_MFD_ACER_A500_EC) += acer-ec-a500.o
+ obj-$(CONFIG_MFD_QCOM_PM8008) += qcom-pm8008.o
+
++obj-$(CONFIG_MFD_RB4XX_CPLD) += rb4xx-cpld.o
+ obj-$(CONFIG_SGI_MFD_IOC3) += ioc3.o
+ obj-$(CONFIG_MFD_SIMPLE_MFD_I2C) += simple-mfd-i2c.o
+ obj-$(CONFIG_MFD_SMPRO) += smpro-core.o
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -1696,6 +1696,12 @@ config GPIO_SODAVILLE
+ help
+ Say Y here to support Intel Sodaville GPIO.
+
++config GPIO_RB4XX
++ tristate "GPIO expander for Mikrotik RB4xx series boards"
++ depends on MFD_RB4XX_CPLD
++ help
++ GPIO driver for Mikrotik Routerboard RB4xx series.
++
+ endmenu
+
+ menu "SPI GPIO expanders"
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -131,6 +131,7 @@ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.
+ obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
+ obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
+ obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o
++obj-$(CONFIG_GPIO_RB4XX) += gpio-rb4xx.o
+ obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
+ obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
+ obj-$(CONFIG_GPIO_RDA) += gpio-rda.o
+--- a/drivers/mtd/nand/raw/Kconfig
++++ b/drivers/mtd/nand/raw/Kconfig
+@@ -551,4 +551,11 @@ config MTD_NAND_AR934X
+ Enables support for NAND controller on Qualcomm Atheros SoCs.
+ This controller is found on AR934x and QCA955x SoCs.
+
++config MTD_NAND_RB4XX
++ tristate "Support for NAND driver for Mikrotik RB4xx series boards"
++ depends on MFD_RB4XX_CPLD
++ help
++ Enables support for the NAND flash chip on Mikrotik Routerboard
++ RB4xx series.
++
+ endif # MTD_RAW_NAND
+--- a/drivers/mtd/nand/raw/Makefile
++++ b/drivers/mtd/nand/raw/Makefile
+@@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_ROCKCHIP) += rock
+ obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o
+ obj-$(CONFIG_MTD_NAND_RENESAS) += renesas-nand-controller.o
+ obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nand.o
++obj-$(CONFIG_MTD_NAND_RB4XX) += nand_rb4xx.o
+
+ nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
+ nand-objs += nand_onfi.o
--- /dev/null
+From: Denis Kalashnikov <denis281089@gmail.com>
+Subject: [PATCH] ath79: add support for reset key on MikroTik RB912UAG-2HPnD
+
+On MikroTik RB91x board series a reset key shares SoC gpio
+line #15 with NAND ALE and NAND IO7. So we need a custom
+gpio driver to manage this non-trivial connection schema.
+Also rb91x-nand needs to have an ability to disable a polling
+of the key while it works with NAND.
+
+While we've been integrating rb91x-key into a firmware, we've
+figured out that:
+* In the gpio-latch driver we need to add a "cansleep" suffix to
+several gpiolib calls,
+* When gpio-latch and rb91x-nand fail to get a gpio and an error
+is -EPROBE_DEFER, they shouldn't report about this, since this
+actually is not an error and occurs when the gpio-latch probe
+function is called before the rb91x-key probe.
+We fix these related things here too.
+
+Submitted-by: Denis Kalashnikov <denis281089@gmail.com>
+Reviewed-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
+Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
+---
+ drivers/gpio/Kconfig | 11 +++++++++++
+ drivers/gpio/Makefile | 2 ++
+ drivers/mtd/nand/raw/Kconfig | 6 ++++++
+ drivers/mtd/nand/raw/Makefile | 1 +
+ 7 files changed, 20 insertions(+)
+
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -371,6 +371,12 @@ config GPIO_IXP4XX
+
+ If unsure, say N.
+
++config GPIO_LATCH_MIKROTIK
++ tristate "MikroTik RouterBOARD GPIO latch support"
++ depends on ATH79
++ help
++ GPIO driver for latch on some MikroTik RouterBOARDs.
++
+ config GPIO_LOGICVC
+ tristate "Xylon LogiCVC GPIO support"
+ depends on MFD_SYSCON && OF
+@@ -553,6 +559,10 @@ config GPIO_ROCKCHIP
+ help
+ Say yes here to support GPIO on Rockchip SoCs.
+
++config GPIO_RB91X_KEY
++ tristate "MikroTik RB91x board series reset key support"
++ depends on ATH79
++
+ config GPIO_SAMA5D2_PIOBU
+ tristate "SAMA5D2 PIOBU GPIO support"
+ depends on MFD_SYSCON
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -81,6 +81,7 @@ obj-$(CONFIG_GPIO_IXP4XX) += gpio-ixp4x
+ obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o
+ obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o
+ obj-$(CONFIG_GPIO_LATCH) += gpio-latch.o
++obj-$(CONFIG_GPIO_LATCH_MIKROTIK) += gpio-latch-mikrotik.o
+ obj-$(CONFIG_GPIO_LJCA) += gpio-ljca.o
+ obj-$(CONFIG_GPIO_LOGICVC) += gpio-logicvc.o
+ obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o
+@@ -132,6 +133,7 @@ obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio
+ obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
+ obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o
+ obj-$(CONFIG_GPIO_RB4XX) += gpio-rb4xx.o
++obj-$(CONFIG_GPIO_RB91X_KEY) += gpio-rb91x-key.o
+ obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
+ obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
+ obj-$(CONFIG_GPIO_RDA) += gpio-rda.o
+--- a/drivers/mtd/nand/raw/Kconfig
++++ b/drivers/mtd/nand/raw/Kconfig
+@@ -558,4 +558,10 @@ config MTD_NAND_RB4XX
+ Enables support for the NAND flash chip on Mikrotik Routerboard
+ RB4xx series.
+
++config MTD_NAND_RB91X
++ tristate "MikroTik RB91x NAND driver support"
++ depends on ATH79 && MTD_RAW_NAND
++ help
++ Enables support for the NAND flash chip on MikroTik RB91x series.
++
+ endif # MTD_RAW_NAND
+--- a/drivers/mtd/nand/raw/Makefile
++++ b/drivers/mtd/nand/raw/Makefile
+@@ -59,6 +59,7 @@ obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-n
+ obj-$(CONFIG_MTD_NAND_RENESAS) += renesas-nand-controller.o
+ obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nand.o
+ obj-$(CONFIG_MTD_NAND_RB4XX) += nand_rb4xx.o
++obj-$(CONFIG_MTD_NAND_RB91X) += rb91x_nand.o
+
+ nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
+ nand-objs += nand_onfi.o
-console=serial0,115200 console=tty1 root=@ROOT@ rootfstype=squashfs,ext4 rootwait
+console=tty1 console=serial0,115200 root=@ROOT@ rootfstype=squashfs,ext4 rootwait
}
EXPORT_SYMBOL(drm_panel_init);
-@@ -289,16 +292,18 @@ int of_drm_get_panel_orientation(const s
+@@ -294,16 +297,18 @@ int of_drm_get_panel_orientation(const s
if (ret < 0)
return ret;
if (ret)
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -1600,9 +1600,14 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1597,9 +1597,14 @@ struct drm_plane *vc4_plane_init(struct
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
int vc4_plane_create_additional_planes(struct drm_device *drm)
{
struct drm_plane *cursor_plane;
-@@ -1618,24 +1623,35 @@ int vc4_plane_create_additional_planes(s
+@@ -1615,24 +1620,35 @@ int vc4_plane_create_additional_planes(s
* modest number of planes to expose, that should hopefully
* still cover any sane usecase.
*/
vc4_dlist_write(vc4_state, 0xc0c0c0c0);
}
-@@ -1649,6 +1652,8 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1646,6 +1649,8 @@ struct drm_plane *vc4_plane_init(struct
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
};
static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
-@@ -1575,6 +1635,16 @@ static bool vc4_format_mod_supported(str
+@@ -1572,6 +1632,16 @@ static bool vc4_format_mod_supported(str
case DRM_FORMAT_BGRX1010102:
case DRM_FORMAT_RGBA1010102:
case DRM_FORMAT_BGRA1010102:
}
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
-@@ -5677,7 +5677,7 @@ static void port_event(struct usb_hub *h
+@@ -5697,7 +5697,7 @@ static void port_event(struct usb_hub *h
port_dev->over_current_count++;
port_over_current_notify(port_dev);
static inline int mmc_blk_part_switch(struct mmc_card *card,
unsigned int part_type);
static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,
-@@ -3050,6 +3057,8 @@ static int mmc_blk_probe(struct mmc_card
+@@ -3052,6 +3059,8 @@ static int mmc_blk_probe(struct mmc_card
{
struct mmc_blk_data *md;
int ret = 0;
/*
* Check that the card supports the command class(es) we need.
-@@ -3057,7 +3066,16 @@ static int mmc_blk_probe(struct mmc_card
+@@ -3059,7 +3068,16 @@ static int mmc_blk_probe(struct mmc_card
if (!(card->csd.cmdclass & CCC_BLOCK_READ))
return -ENODEV;
card->complete_wq = alloc_workqueue("mmc_complete",
WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
-@@ -3072,6 +3090,17 @@ static int mmc_blk_probe(struct mmc_card
+@@ -3074,6 +3092,17 @@ static int mmc_blk_probe(struct mmc_card
goto out_free;
}
+#endif /* _TAS5713_H */
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
-@@ -1220,7 +1220,15 @@ int snd_soc_runtime_set_dai_fmt(struct s
+@@ -1223,7 +1223,15 @@ int snd_soc_runtime_set_dai_fmt(struct s
return 0;
for_each_rtd_codec_dais(rtd, i, codec_dai) {
--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c
+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c
-@@ -1773,7 +1773,7 @@ int vchiq_mmal_component_enable(struct v
+@@ -1774,7 +1774,7 @@ int vchiq_mmal_component_enable(struct v
ret = enable_component(instance, component);
if (ret == 0)
/* deals with receipt of buffer to host message */
static void buffer_to_host_cb(struct vchiq_mmal_instance *instance,
struct mmal_msg *msg, u32 msg_len)
-@@ -1330,6 +1423,7 @@ static int port_disable(struct vchiq_mma
+@@ -1331,6 +1424,7 @@ static int port_disable(struct vchiq_mma
mmalbuf->mmal_flags = 0;
mmalbuf->dts = MMAL_TIME_UNKNOWN;
mmalbuf->pts = MMAL_TIME_UNKNOWN;
port->buffer_cb(instance,
port, 0, mmalbuf);
}
-@@ -1631,6 +1725,43 @@ int mmal_vchi_buffer_cleanup(struct mmal
+@@ -1632,6 +1726,43 @@ int mmal_vchi_buffer_cleanup(struct mmal
}
EXPORT_SYMBOL_GPL(mmal_vchi_buffer_cleanup);
/* Initialise a mmal component and its ports
*
*/
-@@ -1680,6 +1811,7 @@ int vchiq_mmal_component_init(struct vch
+@@ -1681,6 +1812,7 @@ int vchiq_mmal_component_init(struct vch
ret = port_info_get(instance, &component->control);
if (ret < 0)
goto release_component;
for (idx = 0; idx < component->inputs; idx++) {
component->input[idx].type = MMAL_PORT_TYPE_INPUT;
-@@ -1690,6 +1822,7 @@ int vchiq_mmal_component_init(struct vch
+@@ -1691,6 +1823,7 @@ int vchiq_mmal_component_init(struct vch
ret = port_info_get(instance, &component->input[idx]);
if (ret < 0)
goto release_component;
}
for (idx = 0; idx < component->outputs; idx++) {
-@@ -1701,6 +1834,7 @@ int vchiq_mmal_component_init(struct vch
+@@ -1702,6 +1835,7 @@ int vchiq_mmal_component_init(struct vch
ret = port_info_get(instance, &component->output[idx]);
if (ret < 0)
goto release_component;
}
for (idx = 0; idx < component->clocks; idx++) {
-@@ -1712,6 +1846,7 @@ int vchiq_mmal_component_init(struct vch
+@@ -1713,6 +1847,7 @@ int vchiq_mmal_component_init(struct vch
ret = port_info_get(instance, &component->clock[idx]);
if (ret < 0)
goto release_component;
}
*component_out = component;
-@@ -1737,7 +1872,7 @@ EXPORT_SYMBOL_GPL(vchiq_mmal_component_i
+@@ -1738,7 +1873,7 @@ EXPORT_SYMBOL_GPL(vchiq_mmal_component_i
int vchiq_mmal_component_finalise(struct vchiq_mmal_instance *instance,
struct vchiq_mmal_component *component)
{
if (mutex_lock_interruptible(&instance->vchiq_mutex))
return -EINTR;
-@@ -1749,6 +1884,13 @@ int vchiq_mmal_component_finalise(struct
+@@ -1750,6 +1885,13 @@ int vchiq_mmal_component_finalise(struct
component->in_use = 0;
--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c
+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c
-@@ -1899,6 +1899,8 @@ int vchiq_mmal_component_finalise(struct
+@@ -1900,6 +1900,8 @@ int vchiq_mmal_component_finalise(struct
for (idx = 0; idx < component->clocks; idx++)
free_event_context(&component->clock[idx]);
--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c
+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c
-@@ -1765,9 +1765,26 @@ static void free_event_context(struct vc
+@@ -1766,9 +1766,26 @@ static void free_event_context(struct vc
{
struct mmal_msg_context *ctx = port->event_context;
}
/* Initialise a mmal component and its ports
-@@ -1865,6 +1882,7 @@ int vchiq_mmal_component_init(struct vch
+@@ -1866,6 +1883,7 @@ int vchiq_mmal_component_init(struct vch
release_component:
destroy_component(instance, component);
unlock:
if (component)
component->in_use = 0;
-@@ -1880,7 +1898,7 @@ EXPORT_SYMBOL_GPL(vchiq_mmal_component_i
+@@ -1881,7 +1899,7 @@ EXPORT_SYMBOL_GPL(vchiq_mmal_component_i
int vchiq_mmal_component_finalise(struct vchiq_mmal_instance *instance,
struct vchiq_mmal_component *component)
{
if (mutex_lock_interruptible(&instance->vchiq_mutex))
return -EINTR;
-@@ -1892,14 +1910,7 @@ int vchiq_mmal_component_finalise(struct
+@@ -1893,14 +1911,7 @@ int vchiq_mmal_component_finalise(struct
component->in_use = 0;
+ */
+ void (*fixup_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
+ struct usb_host_endpoint *ep, int interval);
- /* Returns the hardware-chosen device address */
- int (*address_device)(struct usb_hcd *, struct usb_device *udev);
- /* prepares the hardware to send commands to the device */
-@@ -435,6 +440,8 @@ extern void usb_hcd_unmap_urb_setup_for_
+ /* Set the hardware-chosen device address */
+ int (*address_device)(struct usb_hcd *, struct usb_device *udev,
+ unsigned int timeout_ms);
+@@ -436,6 +441,8 @@ extern void usb_hcd_unmap_urb_setup_for_
extern void usb_hcd_unmap_urb_for_dma(struct usb_hcd *, struct urb *);
extern void usb_hcd_flush_endpoint(struct usb_device *udev,
struct usb_host_endpoint *ep);
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
-@@ -1641,6 +1641,109 @@ command_cleanup:
+@@ -1643,6 +1643,109 @@ command_cleanup:
}
/*
* non-error returns are a promise to giveback() the urb later
* we drop ownership so next owner (or urb unlink) can get it
*/
-@@ -5469,6 +5572,7 @@ static const struct hc_driver xhci_hc_dr
+@@ -5480,6 +5583,7 @@ static const struct hc_driver xhci_hc_dr
.endpoint_reset = xhci_endpoint_reset,
.check_bandwidth = xhci_check_bandwidth,
.reset_bandwidth = xhci_reset_bandwidth,
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
-@@ -2522,9 +2522,11 @@ int xhci_mem_init(struct xhci_hcd *xhci,
+@@ -2524,9 +2524,11 @@ int xhci_mem_init(struct xhci_hcd *xhci,
* Event ring setup: Allocate a normal ring, but also setup
* the event ring segment table (ERST). Section 4.9.3.
*/
if (!xhci->event_ring)
goto fail;
if (xhci_check_trb_in_td_math(xhci) < 0)
-@@ -2537,7 +2539,7 @@ int xhci_mem_init(struct xhci_hcd *xhci,
+@@ -2539,7 +2541,7 @@ int xhci_mem_init(struct xhci_hcd *xhci,
/* set ERST count with the number of entries in the segment table */
val = readl(&xhci->ir_set->erst_size);
val &= ERST_SIZE_MASK;
val);
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
-@@ -1672,8 +1672,8 @@ struct urb_priv {
+@@ -1677,8 +1677,8 @@ struct urb_priv {
* Each segment table entry is 4*32bits long. 1K seems like an ok size:
* (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
* meaning 64 ring segments.
} else if (msg->u.buffer_from_host.buffer_header.length == 0) {
/* empty buffer */
if (msg->u.buffer_from_host.buffer_header.flags &
-@@ -1528,6 +1551,9 @@ int vchiq_mmal_port_parameter_set(struct
+@@ -1529,6 +1552,9 @@ int vchiq_mmal_port_parameter_set(struct
mutex_unlock(&instance->vchiq_mutex);
return ret;
}
EXPORT_SYMBOL_GPL(vchiq_mmal_port_parameter_set);
-@@ -1696,6 +1722,31 @@ int vchiq_mmal_submit_buffer(struct vchi
+@@ -1697,6 +1723,31 @@ int vchiq_mmal_submit_buffer(struct vchi
unsigned long flags = 0;
int ret;
ret = buffer_from_host(instance, port, buffer);
if (ret == -EINVAL) {
/* Port is disabled. Queue for when it is enabled. */
-@@ -1729,6 +1780,16 @@ int mmal_vchi_buffer_cleanup(struct mmal
+@@ -1730,6 +1781,16 @@ int mmal_vchi_buffer_cleanup(struct mmal
release_msg_context(msg_context);
buf->msg_context = NULL;
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
-@@ -1243,6 +1243,15 @@ config HTC_EGPIO
+@@ -1244,6 +1244,15 @@ config HTC_EGPIO
several HTC phones. It provides basic support for input
pins, output pins, and IRQs.
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
-@@ -674,9 +674,9 @@ deq_found:
+@@ -675,9 +675,9 @@ deq_found:
}
if ((ep->ep_state & SET_DEQ_PENDING)) {
vchiq_release_message(instance->vchiq_instance, instance->service_handle, rmsg_handle);
-@@ -1086,9 +1101,9 @@ static int create_component(struct vchiq
+@@ -1087,9 +1102,9 @@ static int create_component(struct vchiq
component->outputs = rmsg->u.component_create_reply.output_num;
component->clocks = rmsg->u.component_create_reply.clock_num;
release_msg:
vchiq_release_message(instance->vchiq_instance, instance->service_handle, rmsg_handle);
-@@ -1257,10 +1272,9 @@ static int port_action_port(struct vchiq
+@@ -1258,10 +1273,9 @@ static int port_action_port(struct vchiq
ret = -rmsg->u.port_action_reply.status;
release_msg:
vchiq_release_message(instance->vchiq_instance, instance->service_handle, rmsg_handle);
-@@ -1304,11 +1318,11 @@ static int port_action_handle(struct vch
+@@ -1305,11 +1319,11 @@ static int port_action_handle(struct vch
ret = -rmsg->u.port_action_reply.status;
release_msg:
vchiq_release_message(instance->vchiq_instance, instance->service_handle, rmsg_handle);
-@@ -1347,9 +1361,9 @@ static int port_parameter_set(struct vch
+@@ -1348,9 +1362,9 @@ static int port_parameter_set(struct vch
ret = -rmsg->u.port_parameter_set_reply.status;
release_msg:
vchiq_release_message(instance->vchiq_instance, instance->service_handle, rmsg_handle);
-@@ -1407,8 +1421,9 @@ static int port_parameter_get(struct vch
+@@ -1408,8 +1422,9 @@ static int port_parameter_get(struct vch
/* Always report the size of the returned parameter to the caller */
*value_size = rmsg->u.port_parameter_get_reply.size;
release_msg:
vchiq_release_message(instance->vchiq_instance, instance->service_handle, rmsg_handle);
-@@ -1665,7 +1680,7 @@ int vchiq_mmal_port_connect_tunnel(struc
+@@ -1666,7 +1681,7 @@ int vchiq_mmal_port_connect_tunnel(struc
if (!dst) {
/* do not make new connection */
ret = 0;
goto release_unlock;
}
-@@ -1683,14 +1698,14 @@ int vchiq_mmal_port_connect_tunnel(struc
+@@ -1684,14 +1699,14 @@ int vchiq_mmal_port_connect_tunnel(struc
/* set new format */
ret = port_info_set(instance, dst);
if (ret) {
goto release_unlock;
}
-@@ -1699,9 +1714,9 @@ int vchiq_mmal_port_connect_tunnel(struc
+@@ -1700,9 +1715,9 @@ int vchiq_mmal_port_connect_tunnel(struc
MMAL_MSG_PORT_ACTION_TYPE_CONNECT,
dst->component->handle, dst->handle);
if (ret < 0) {
goto release_unlock;
}
src->connected = dst;
-@@ -1726,7 +1741,8 @@ int vchiq_mmal_submit_buffer(struct vchi
+@@ -1727,7 +1742,8 @@ int vchiq_mmal_submit_buffer(struct vchi
* videobuf2 won't let us have the dmabuf there.
*/
if (port->zero_copy && buffer->dma_buf && !buffer->vcsm_handle) {
ret = vc_sm_cma_import_dmabuf(buffer->dma_buf,
&buffer->vcsm_handle);
if (ret) {
-@@ -1742,8 +1758,8 @@ int vchiq_mmal_submit_buffer(struct vchi
+@@ -1743,8 +1759,8 @@ int vchiq_mmal_submit_buffer(struct vchi
vc_sm_cma_free(buffer->vcsm_handle);
return ret;
}
}
ret = buffer_from_host(instance, port, buffer);
-@@ -1782,8 +1798,8 @@ int mmal_vchi_buffer_cleanup(struct mmal
+@@ -1783,8 +1799,8 @@ int mmal_vchi_buffer_cleanup(struct mmal
if (buf->vcsm_handle) {
int ret;
--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c
+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c
-@@ -1500,6 +1500,8 @@ static int port_enable(struct vchiq_mmal
+@@ -1501,6 +1501,8 @@ static int port_enable(struct vchiq_mmal
port->enabled = 1;
pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
-@@ -664,6 +664,15 @@ static int xhci_move_dequeue_past_td(str
+@@ -665,6 +665,15 @@ static int xhci_move_dequeue_past_td(str
} while (!cycle_found || !td_last_trb_found);
deq_found:
addr = xhci_trb_virt_to_dma(new_seg, new_deq);
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
-@@ -1902,6 +1902,7 @@ struct xhci_hcd {
+@@ -1907,6 +1907,7 @@ struct xhci_hcd {
#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
if (ret)
return -ENOMEM;
-@@ -1811,7 +1815,7 @@ int xhci_alloc_erst(struct xhci_hcd *xhc
+@@ -1813,7 +1817,7 @@ int xhci_alloc_erst(struct xhci_hcd *xhc
for (val = 0; val < evt_ring->num_segs; val++) {
entry = &erst->entries[val];
entry->seg_addr = cpu_to_le64(seg->dma);
xhci_err(xhci, "Tried to move enqueue past ring segment\n");
return;
}
-@@ -3150,7 +3153,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd
+@@ -3151,7 +3154,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd
* that clears the EHB.
*/
while (xhci_handle_event(xhci) > 0) {
continue;
xhci_update_erst_dequeue(xhci, event_ring_deq);
event_ring_deq = xhci->event_ring->dequeue;
-@@ -3292,7 +3295,8 @@ static int prepare_ring(struct xhci_hcd
+@@ -3293,7 +3296,8 @@ static int prepare_ring(struct xhci_hcd
}
}
* when the cycle bit is set to 1.
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
-@@ -1634,6 +1634,7 @@ struct xhci_ring {
+@@ -1639,6 +1639,7 @@ struct xhci_ring {
unsigned int num_trbs_free;
unsigned int num_trbs_free_temp;
unsigned int bounce_buf_len;
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
-@@ -1904,6 +1904,7 @@ struct xhci_hcd {
+@@ -1909,6 +1909,7 @@ struct xhci_hcd {
#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(47)
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
-@@ -3605,14 +3605,15 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3606,14 +3606,15 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
unsigned int num_trbs;
unsigned int start_cycle, num_sgs = 0;
unsigned int enqd_len, block_len, trb_buff_len, full_len;
full_len = urb->transfer_buffer_length;
/* If we have scatter/gather list, we use it. */
if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
-@@ -3649,6 +3650,17 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3650,6 +3651,17 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
start_cycle = ring->cycle_state;
send_addr = addr;
/* Queue the TRBs, even if they are zero-length */
for (enqd_len = 0; first_trb || enqd_len < full_len;
enqd_len += trb_buff_len) {
-@@ -3661,6 +3673,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3662,6 +3674,11 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
if (enqd_len + trb_buff_len > full_len)
trb_buff_len = full_len - enqd_len;
first_trb = false;
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
-@@ -1905,6 +1905,7 @@ struct xhci_hcd {
+@@ -1910,6 +1910,7 @@ struct xhci_hcd {
#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(47)
#define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(48)
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
-@@ -3605,7 +3605,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3606,7 +3606,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
unsigned int num_trbs;
unsigned int start_cycle, num_sgs = 0;
unsigned int enqd_len, block_len, trb_buff_len, full_len;
u32 field, length_field, remainder, maxpacket;
u64 addr, send_addr;
-@@ -3651,14 +3651,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3652,14 +3652,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
send_addr = addr;
if (xhci->quirks & XHCI_VLI_SS_BULK_OUT_BUG &&
}
/* Queue the TRBs, even if they are zero-length */
-@@ -3673,7 +3668,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3674,7 +3669,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
if (enqd_len + trb_buff_len > full_len)
trb_buff_len = full_len - enqd_len;
--- a/drivers/mmc/core/block.c
+++ b/drivers/mmc/core/block.c
-@@ -1970,7 +1970,7 @@ static void mmc_blk_mq_rw_recovery(struc
+@@ -1972,7 +1972,7 @@ static void mmc_blk_mq_rw_recovery(struc
return;
}
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
-@@ -1012,11 +1012,13 @@ static int xhci_invalidate_cancelled_tds
+@@ -1013,11 +1013,13 @@ static int xhci_invalidate_cancelled_tds
td->urb->stream_id, td->urb,
cached_td->urb->stream_id, cached_td->urb);
cached_td = td;
}
}
-@@ -1264,10 +1266,7 @@ static void update_ring_for_set_deq_comp
+@@ -1265,10 +1267,7 @@ static void update_ring_for_set_deq_comp
unsigned int ep_index)
{
union xhci_trb *dequeue_temp;
dequeue_temp = ep_ring->dequeue;
/* If we get two back-to-back stalls, and the first stalled transfer
-@@ -1282,8 +1281,6 @@ static void update_ring_for_set_deq_comp
+@@ -1283,8 +1282,6 @@ static void update_ring_for_set_deq_comp
}
while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
ep_ring->dequeue++;
if (trb_is_link(ep_ring->dequeue)) {
if (ep_ring->dequeue ==
-@@ -1293,15 +1290,10 @@ static void update_ring_for_set_deq_comp
+@@ -1294,15 +1291,10 @@ static void update_ring_for_set_deq_comp
ep_ring->dequeue = ep_ring->deq_seg->trbs;
}
if (ep_ring->dequeue == dequeue_temp) {
if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
-@@ -3582,6 +3582,48 @@ static int xhci_align_td(struct xhci_hcd
+@@ -3583,6 +3583,48 @@ static int xhci_align_td(struct xhci_hcd
return 1;
}
/* This is very similar to what ehci-q.c qtd_fill() does */
int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
struct urb *urb, int slot_id, unsigned int ep_index)
-@@ -3750,6 +3792,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3751,6 +3793,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
}
check_trb_math(urb, enqd_len);
giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
start_cycle, start_trb);
return 0;
-@@ -3885,6 +3929,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
+@@ -3886,6 +3930,8 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
/* Event on completion */
field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
return 0;
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
-@@ -1906,6 +1906,7 @@ struct xhci_hcd {
+@@ -1911,6 +1911,7 @@ struct xhci_hcd {
#define XHCI_AVOID_DQ_ON_LINK BIT_ULL(47)
#define XHCI_VLI_TRB_CACHE_BUG BIT_ULL(48)
#define XHCI_VLI_SS_BULK_OUT_BUG BIT_ULL(49)
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
-@@ -1730,7 +1730,7 @@ static void xhci_fixup_endpoint(struct u
+@@ -1732,7 +1732,7 @@ static void xhci_fixup_endpoint(struct u
return;
}
ctrl_ctx->add_flags = xhci_get_endpoint_flag_from_index(ep_index);
* hardware interrupt, we use a timer-based system. The original
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
-@@ -1559,6 +1559,9 @@ static void serial8250_stop_tx(struct ua
+@@ -1553,6 +1553,9 @@ static void serial8250_stop_tx(struct ua
serial_icr_write(up, UART_ACR, up->acr);
}
serial8250_rpm_put(up);
}
static inline void __start_tx(struct uart_port *port)
-@@ -1669,6 +1672,9 @@ static void serial8250_start_tx(struct u
+@@ -1663,6 +1666,9 @@ static void serial8250_start_tx(struct u
struct uart_8250_port *up = up_to_u8250p(port);
struct uart_8250_em485 *em485 = up->em485;
if (!port->x_char && uart_circ_empty(&port->state->xmit))
return;
-@@ -1889,6 +1895,9 @@ unsigned int serial8250_modem_status(str
+@@ -1883,6 +1889,9 @@ unsigned int serial8250_modem_status(str
uart_handle_cts_change(port, status & UART_MSR_CTS);
wake_up_interruptible(&port->state->port.delta_msr_wait);
--- a/fs/f2fs/segment.c
+++ b/fs/f2fs/segment.c
-@@ -663,9 +663,7 @@ init_thread:
+@@ -665,9 +665,7 @@ init_thread:
"f2fs_flush-%u:%u", MAJOR(dev), MINOR(dev));
if (IS_ERR(fcc->f2fs_issue_flush)) {
err = PTR_ERR(fcc->f2fs_issue_flush);
}
return err;
-@@ -5062,11 +5060,9 @@ int f2fs_build_segment_manager(struct f2
+@@ -5064,11 +5062,9 @@ int f2fs_build_segment_manager(struct f2
init_f2fs_rwsem(&sm_info->curseg_lock);
/* Control word */
vc4_dlist_write(vc4_state,
SCALER_CTL0_VALID |
-@@ -1717,7 +1717,7 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1714,7 +1714,7 @@ struct drm_plane *vc4_plane_init(struct
};
for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
formats[num_formats] = hvs_formats[i].drm;
num_formats++;
}
-@@ -1732,7 +1732,7 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1729,7 +1729,7 @@ struct drm_plane *vc4_plane_init(struct
return ERR_CAST(vc4_plane);
plane = &vc4_plane->base;
return 0;
}
-@@ -1716,7 +2345,7 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1713,7 +2342,7 @@ struct drm_plane *vc4_plane_init(struct
};
for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
formats[num_formats] = hvs_formats[i].drm;
num_formats++;
}
-@@ -1731,7 +2360,7 @@ struct drm_plane *vc4_plane_init(struct
+@@ -1728,7 +2357,7 @@ struct drm_plane *vc4_plane_init(struct
return ERR_CAST(vc4_plane);
plane = &vc4_plane->base;
+++ /dev/null
-From 146bbf9627f6c37816939de29538ec8ee9a7be1a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ma=C3=ADra=20Canal?= <mcanal@igalia.com>
-Date: Fri, 5 Jan 2024 15:07:34 -0300
-Subject: [PATCH] drm/vc4: don't check if plane->state->fb == state->fb
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Currently, when using non-blocking commits, we can see the following
-kernel warning:
-
-[ 110.908514] ------------[ cut here ]------------
-[ 110.908529] refcount_t: underflow; use-after-free.
-[ 110.908620] WARNING: CPU: 0 PID: 1866 at lib/refcount.c:87 refcount_dec_not_one+0xb8/0xc0
-[ 110.908664] Modules linked in: rfcomm snd_seq_dummy snd_hrtimer snd_seq snd_seq_device cmac algif_hash aes_arm64 aes_generic algif_skcipher af_alg bnep hid_logitech_hidpp vc4 brcmfmac hci_uart btbcm brcmutil bluetooth snd_soc_hdmi_codec cfg80211 cec drm_display_helper drm_dma_helper drm_kms_helper snd_soc_core snd_compress snd_pcm_dmaengine fb_sys_fops sysimgblt syscopyarea sysfillrect raspberrypi_hwmon ecdh_generic ecc rfkill libaes i2c_bcm2835 binfmt_misc joydev snd_bcm2835(C) bcm2835_codec(C) bcm2835_isp(C) v4l2_mem2mem videobuf2_dma_contig snd_pcm bcm2835_v4l2(C) raspberrypi_gpiomem bcm2835_mmal_vchiq(C) videobuf2_v4l2 snd_timer videobuf2_vmalloc videobuf2_memops videobuf2_common snd videodev vc_sm_cma(C) mc hid_logitech_dj uio_pdrv_genirq uio i2c_dev drm fuse dm_mod drm_panel_orientation_quirks backlight ip_tables x_tables ipv6
-[ 110.909086] CPU: 0 PID: 1866 Comm: kodi.bin Tainted: G C 6.1.66-v8+ #32
-[ 110.909104] Hardware name: Raspberry Pi 3 Model B Rev 1.2 (DT)
-[ 110.909114] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
-[ 110.909132] pc : refcount_dec_not_one+0xb8/0xc0
-[ 110.909152] lr : refcount_dec_not_one+0xb4/0xc0
-[ 110.909170] sp : ffffffc00913b9c0
-[ 110.909177] x29: ffffffc00913b9c0 x28: 000000556969bbb0 x27: 000000556990df60
-[ 110.909205] x26: 0000000000000002 x25: 0000000000000004 x24: ffffff8004448480
-[ 110.909230] x23: ffffff800570b500 x22: ffffff802e03a7bc x21: ffffffecfca68c78
-[ 110.909257] x20: ffffff8002b42000 x19: ffffff802e03a600 x18: 0000000000000000
-[ 110.909283] x17: 0000000000000011 x16: ffffffffffffffff x15: 0000000000000004
-[ 110.909308] x14: 0000000000000fff x13: ffffffed577e47e0 x12: 0000000000000003
-[ 110.909333] x11: 0000000000000000 x10: 0000000000000027 x9 : c912d0d083728c00
-[ 110.909359] x8 : c912d0d083728c00 x7 : 65646e75203a745f x6 : 746e756f63666572
-[ 110.909384] x5 : ffffffed579f62ee x4 : ffffffed579eb01e x3 : 0000000000000000
-[ 110.909409] x2 : 0000000000000000 x1 : ffffffc00913b750 x0 : 0000000000000001
-[ 110.909434] Call trace:
-[ 110.909441] refcount_dec_not_one+0xb8/0xc0
-[ 110.909461] vc4_bo_dec_usecnt+0x4c/0x1b0 [vc4]
-[ 110.909903] vc4_cleanup_fb+0x44/0x50 [vc4]
-[ 110.910315] drm_atomic_helper_cleanup_planes+0x88/0xa4 [drm_kms_helper]
-[ 110.910669] vc4_atomic_commit_tail+0x390/0x9dc [vc4]
-[ 110.911079] commit_tail+0xb0/0x164 [drm_kms_helper]
-[ 110.911397] drm_atomic_helper_commit+0x1d0/0x1f0 [drm_kms_helper]
-[ 110.911716] drm_atomic_commit+0xb0/0xdc [drm]
-[ 110.912569] drm_mode_atomic_ioctl+0x348/0x4b8 [drm]
-[ 110.913330] drm_ioctl_kernel+0xec/0x15c [drm]
-[ 110.914091] drm_ioctl+0x24c/0x3b0 [drm]
-[ 110.914850] __arm64_sys_ioctl+0x9c/0xd4
-[ 110.914873] invoke_syscall+0x4c/0x114
-[ 110.914897] el0_svc_common+0xd0/0x118
-[ 110.914917] do_el0_svc+0x38/0xd0
-[ 110.914936] el0_svc+0x30/0x8c
-[ 110.914958] el0t_64_sync_handler+0x84/0xf0
-[ 110.914979] el0t_64_sync+0x18c/0x190
-[ 110.914996] ---[ end trace 0000000000000000 ]---
-
-This happens because, although `prepare_fb` and `cleanup_fb` are
-perfectly balanced, we cannot guarantee consistency in the check
-plane->state->fb == state->fb. This means that sometimes we can increase
-the refcount in `prepare_fb` and don't decrease it in `cleanup_fb`. The
-opposite can also be true.
-
-In fact, the struct drm_plane .state shouldn't be accessed directly
-but instead, the `drm_atomic_get_new_plane_state()` helper function should
-be used. So, we could stick to this check, but using
-`drm_atomic_get_new_plane_state()`. But actually, this check is not really
-needed. We can increase and decrease the refcount symmetrically without
-problems.
-
-This is going to make the code more simple and consistent.
-
-Signed-off-by: Maíra Canal <mcanal@igalia.com>
----
- drivers/gpu/drm/vc4/vc4_plane.c | 5 +----
- 1 file changed, 1 insertion(+), 4 deletions(-)
-
---- a/drivers/gpu/drm/vc4/vc4_plane.c
-+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -2225,9 +2225,6 @@ static int vc4_prepare_fb(struct drm_pla
-
- drm_gem_plane_helper_prepare_fb(plane, state);
-
-- if (plane->state->fb == state->fb)
-- return 0;
--
- return vc4_bo_inc_usecnt(bo);
- }
-
-@@ -2236,7 +2233,7 @@ static void vc4_cleanup_fb(struct drm_pl
- {
- struct vc4_bo *bo;
-
-- if (plane->state->fb == state->fb || !state->fb)
-+ if (!state->fb)
- return;
-
- bo = to_vc4_bo(&drm_fb_dma_get_gem_obj(state->fb, 0)->base);
#include <linux/uaccess.h>
#include <asm/io.h>
-@@ -2245,6 +2247,69 @@ static void b44_adjust_link(struct net_d
+@@ -2247,6 +2249,69 @@ static void b44_adjust_link(struct net_d
}
}
static int b44_register_phy_one(struct b44 *bp)
{
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
-@@ -2281,6 +2346,9 @@ static int b44_register_phy_one(struct b
+@@ -2283,6 +2348,9 @@ static int b44_register_phy_one(struct b
if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&
(sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
dev_info(sdev->dev,
"could not find PHY at %i, use fixed one\n",
bp->phy_addr);
-@@ -2475,6 +2543,7 @@ static void b44_remove_one(struct ssb_de
+@@ -2477,6 +2545,7 @@ static void b44_remove_one(struct ssb_de
unregister_netdev(dev);
if (bp->flags & B44_FLAG_EXTERNAL_PHY)
b44_unregister_phy_one(bp);
if (bp->flags & B44_FLAG_EXTERNAL_PHY)
return 0;
-@@ -2175,6 +2200,8 @@ static int b44_get_invariants(struct b44
+@@ -2177,6 +2202,8 @@ static int b44_get_invariants(struct b44
* valid PHY address. */
bp->phy_addr &= 0x1F;
SUBTARGETS:=generic
KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
define Target/Description
Build firmware images for Broadcom BCM4908 SoC family routers.
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_ARCH_BCM4908=y
-CONFIG_ARCH_BCMBCA=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_B53=y
-CONFIG_BCM4908_ENET=y
-CONFIG_BCM7038_WDT=y
-CONFIG_BCM7XXX_PHY=y
-CONFIG_BCM_NET_PHYLIB=y
-CONFIG_BCM_PMB=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_PM=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_BRCMSTB=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_LEDS_BCM63138=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BCM_UNIMAC=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_BRCM_U_BOOT=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_BRCMNAND=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_OF_PARTS_BCM4908=y
-# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPLIT_CFE_BOOTFS=y
-# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_BCM_SF2=y
-CONFIG_NET_DSA_TAG_BRCM=y
-CONFIG_NET_DSA_TAG_BRCM_COMMON=y
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NO_IOPORT_MAP=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_U_BOOT_ENV=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PADATA=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_BRCM_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_BCM4908=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RELOCATABLE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_BCM63XX=y
-CONFIG_SERIAL_BCM63XX_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SRCU=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-From d0ae9c944b9472c5691a482297df7a57d7fd1199 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 19 Aug 2021 14:11:08 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix NAND node name
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This matches nand-controller.yaml requirements.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -295,7 +295,7 @@
- status = "okay";
- };
-
-- nand@1800 {
-+ nand-controller@1800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+++ /dev/null
-From 7b0c9ca7f18e8d2e2cf3c342d91f037d436777bf Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Fri, 5 Nov 2021 11:14:12 +0100
-Subject: [PATCH] dt-bindings: arm: bcm: document Netgear RAXE500 binding
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-One more BCM4908 based device.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
-+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
-@@ -29,6 +29,7 @@ properties:
- items:
- - enum:
- - asus,gt-ac5300
-+ - netgear,raxe500
- - const: brcm,bcm4908
-
- - description: BCM49408 based boards
+++ /dev/null
-From 72b1c5da796ec5266f2012c36470e226cb4f09c9 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 30 Dec 2021 12:05:35 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add pinctrl binding
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Describe pinmux block with its maps.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 135 ++++++++++++++++++
- 1 file changed, 135 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -286,6 +286,141 @@
- gpio-controller;
- };
-
-+ pinctrl@560 {
-+ compatible = "brcm,bcm4908-pinctrl";
-+ reg = <0x560 0x10>;
-+
-+ pins_led_0_a: led_0-a-pins {
-+ function = "led_0";
-+ groups = "led_0_grp_a";
-+ };
-+
-+ pins_led_1_a: led_1-a-pins {
-+ function = "led_1";
-+ groups = "led_1_grp_a";
-+ };
-+
-+ pins_led_2_a: led_2-a-pins {
-+ function = "led_2";
-+ groups = "led_2_grp_a";
-+ };
-+
-+ pins_led_3_a: led_3-a-pins {
-+ function = "led_3";
-+ groups = "led_3_grp_a";
-+ };
-+
-+ pins_led_4_a: led_4-a-pins {
-+ function = "led_4";
-+ groups = "led_4_grp_a";
-+ };
-+
-+ pins_led_5_a: led_5-a-pins {
-+ function = "led_5";
-+ groups = "led_5_grp_a";
-+ };
-+
-+ pins_led_6_a: led_6-a-pins {
-+ function = "led_6";
-+ groups = "led_6_grp_a";
-+ };
-+
-+ pins_led_7_a: led_7-a-pins {
-+ function = "led_7";
-+ groups = "led_7_grp_a";
-+ };
-+
-+ pins_led_8_a: led_8-a-pins {
-+ function = "led_8";
-+ groups = "led_8_grp_a";
-+ };
-+
-+ pins_led_9_a: led_9-a-pins {
-+ function = "led_9";
-+ groups = "led_9_grp_a";
-+ };
-+
-+ pins_led_21_a: led_21-a-pins {
-+ function = "led_21";
-+ groups = "led_21_grp_a";
-+ };
-+
-+ pins_led_22_a: led_22-a-pins {
-+ function = "led_22";
-+ groups = "led_22_grp_a";
-+ };
-+
-+ pins_led_26_a: led_26-a-pins {
-+ function = "led_26";
-+ groups = "led_26_grp_a";
-+ };
-+
-+ pins_led_27_a: led_27-a-pins {
-+ function = "led_27";
-+ groups = "led_27_grp_a";
-+ };
-+
-+ pins_led_28_a: led_28-a-pins {
-+ function = "led_28";
-+ groups = "led_28_grp_a";
-+ };
-+
-+ pins_led_29_a: led_29-a-pins {
-+ function = "led_29";
-+ groups = "led_29_grp_a";
-+ };
-+
-+ pins_led_30_a: led_30-a-pins {
-+ function = "led_30";
-+ groups = "led_30_grp_a";
-+ };
-+
-+ pins_hs_uart: hs_uart-pins {
-+ function = "hs_uart";
-+ groups = "hs_uart_grp";
-+ };
-+
-+ pins_i2c_a: i2c-a-pins {
-+ function = "i2c";
-+ groups = "i2c_grp_a";
-+ };
-+
-+ pins_i2c_b: i2c-b-pins {
-+ function = "i2c";
-+ groups = "i2c_grp_b";
-+ };
-+
-+ pins_i2s: i2s-pins {
-+ function = "i2s";
-+ groups = "i2s_grp";
-+ };
-+
-+ pins_nand_ctrl: nand_ctrl-pins {
-+ function = "nand_ctrl";
-+ groups = "nand_ctrl_grp";
-+ };
-+
-+ pins_nand_data: nand_data-pins {
-+ function = "nand_data";
-+ groups = "nand_data_grp";
-+ };
-+
-+ pins_emmc_ctrl: emmc_ctrl-pins {
-+ function = "emmc_ctrl";
-+ groups = "emmc_ctrl_grp";
-+ };
-+
-+ pins_usb0_pwr: usb0_pwr-pins {
-+ function = "usb0_pwr";
-+ groups = "usb0_pwr_grp";
-+ };
-+
-+ pins_usb1_pwr: usb1_pwr-pins {
-+ function = "usb1_pwr";
-+ groups = "usb1_pwr_grp";
-+ };
-+ };
-+
- uart0: serial@640 {
- compatible = "brcm,bcm6345-uart";
- reg = <0x640 0x18>;
+++ /dev/null
-From 47513f6dd93b5b7d91143219c2c1fb883664ed13 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 9 Feb 2022 21:14:17 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add watchdog block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 has the same watchdog as BCM63xx devices. Use "brcm,bcm6345-wdt"
-binding which matches the first SoC with that block.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -275,6 +275,15 @@
- twd: timer-mfd@400 {
- compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
- reg = <0x400 0x4c>;
-+ ranges = <0x0 0x400 0x4c>;
-+
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ watchdog@28 {
-+ compatible = "brcm,bcm6345-wdt";
-+ reg = <0x28 0x8>;
-+ };
- };
-
- gpio0: gpio-controller@500 {
+++ /dev/null
-From ba5dfa2fd8d0aed4e4b6f650ba9e8ea7cdd6ead1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 15 Feb 2022 07:36:39 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add I2C block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 uses the same I2C hw as BCM63xx / BCM67xx / BCM68xx SoCs.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -455,6 +455,15 @@
- };
- };
-
-+ i2c@2100 {
-+ compatible = "brcm,brcmper-i2c";
-+ reg = <0x2100 0x58>;
-+ clock-frequency = <97500>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_i2c_a>;
-+ status = "disabled";
-+ };
-+
- misc@2600 {
- compatible = "brcm,misc", "simple-mfd";
- reg = <0x2600 0xe4>;
+++ /dev/null
-From 82a58061ada60058ec00113c179380f945914709 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 8 Jun 2022 11:00:59 -0700
-Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63146
-
-Add DTS for ARMv8 based broadband SoC BCM63146. bcm63146.dtsi is the
-SoC description DTS header and bcm963146.dts is a simple DTS file for
-Broadcom BCM963146 Reference board that only enable the UART port.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
- .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 110 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm963146.dts | 30 +++++
- 3 files changed, 142 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -7,4 +7,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- bcm4912-asus-gt-ax6000.dtb \
- bcm94912.dtb \
- bcm963158.dtb \
-- bcm96858.dtb
-+ bcm96858.dtb \
-+ bcm963146.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-@@ -0,0 +1,110 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+/ {
-+ compatible = "brcm,bcm63146", "brcm,bcmbca";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
-+ interrupt-parent = <&gic>;
-+
-+ cpus {
-+ #address-cells = <2>;
-+ #size-cells = <0>;
-+
-+ B53_0: cpu@0 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x0>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ B53_1: cpu@1 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x1>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ L2_0: l2-cache0 {
-+ compatible = "cache";
-+ };
-+ };
-+
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-+ };
-+
-+ pmu: pmu {
-+ compatible = "arm,cortex-a53-pmu";
-+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-affinity = <&B53_0>, <&B53_1>;
-+ };
-+
-+ clocks: clocks {
-+ periph_clk: periph-clk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
-+ uart_clk: uart-clk {
-+ compatible = "fixed-factor-clock";
-+ #clock-cells = <0>;
-+ clocks = <&periph_clk>;
-+ clock-div = <4>;
-+ clock-mult = <1>;
-+ };
-+ };
-+
-+ psci {
-+ compatible = "arm,psci-0.2";
-+ method = "smc";
-+ };
-+
-+ axi@81000000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0x81000000 0x8000>;
-+
-+ gic: interrupt-controller@1000 {
-+ compatible = "arm,gic-400";
-+ #interrupt-cells = <3>;
-+ interrupt-controller;
-+ reg = <0x1000 0x1000>,
-+ <0x2000 0x2000>,
-+ <0x4000 0x2000>,
-+ <0x6000 0x2000>;
-+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-+ IRQ_TYPE_LEVEL_HIGH)>;
-+ };
-+ };
-+
-+ bus@ff800000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0xff800000 0x800000>;
-+
-+ uart0: serial@12000 {
-+ compatible = "arm,pl011", "arm,primecell";
-+ reg = <0x12000 0x1000>;
-+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&uart_clk>, <&uart_clk>;
-+ clock-names = "uartclk", "apb_pclk";
-+ status = "disabled";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm63146.dtsi"
-+
-+/ {
-+ model = "Broadcom BCM963146 Reference Board";
-+ compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
-+
-+ aliases {
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x0 0x0 0x0 0x08000000>;
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
+++ /dev/null
-From 64eca7ad058cff861b48cdead8dee40dfc284e9e Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 8 Jun 2022 11:04:36 -0700
-Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6856
-
-Add DTS for ARMv8 based broadband SoC BCM6856. bcm6856.dtsi is the
-SoC description DTS header and bcm96856.dts is a simple DTS file for
-Broadcom BCM96956 Reference board that only enable the UART port.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
- .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 103 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm96856.dts | 30 +++++
- 3 files changed, 135 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -8,4 +8,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- bcm94912.dtb \
- bcm963158.dtb \
- bcm96858.dtb \
-- bcm963146.dtb
-+ bcm963146.dtb \
-+ bcm96856.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-@@ -0,0 +1,103 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+/ {
-+ compatible = "brcm,bcm6856", "brcm,bcmbca";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
-+ interrupt-parent = <&gic>;
-+
-+ cpus {
-+ #address-cells = <2>;
-+ #size-cells = <0>;
-+
-+ B53_0: cpu@0 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x0>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ B53_1: cpu@1 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x1>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ L2_0: l2-cache0 {
-+ compatible = "cache";
-+ };
-+ };
-+
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-+ };
-+
-+ pmu: pmu {
-+ compatible = "arm,cortex-a53-pmu";
-+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-affinity = <&B53_0>, <&B53_1>;
-+ };
-+
-+ clocks: clocks {
-+ periph_clk:periph-clk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
-+ };
-+
-+ psci {
-+ compatible = "arm,psci-0.2";
-+ method = "smc";
-+ };
-+
-+ axi@81000000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0x81000000 0x8000>;
-+
-+ gic: interrupt-controller@1000 {
-+ compatible = "arm,gic-400";
-+ #interrupt-cells = <3>;
-+ interrupt-controller;
-+ reg = <0x1000 0x1000>, /* GICD */
-+ <0x2000 0x2000>, /* GICC */
-+ <0x4000 0x2000>, /* GICH */
-+ <0x6000 0x2000>; /* GICV */
-+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-+ IRQ_TYPE_LEVEL_HIGH)>;
-+ };
-+ };
-+
-+ bus@ff800000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0xff800000 0x800000>;
-+
-+ uart0: serial@640 {
-+ compatible = "brcm,bcm6345-uart";
-+ reg = <0x640 0x18>;
-+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&periph_clk>;
-+ clock-names = "refclk";
-+ status = "disabled";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm6856.dtsi"
-+
-+/ {
-+ model = "Broadcom BCM96856 Reference Board";
-+ compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
-+
-+ aliases {
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x0 0x0 0x0 0x08000000>;
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
+++ /dev/null
-From eab6bb0994b806525fc5e362e8b865f61c4a9e20 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Thu, 9 Jun 2022 17:15:33 -0700
-Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6813
-
-Add DTS for ARMv8 based broadband SoC BCM6813. bcm6813.dtsi is the
-SoC description DTS header and bcm96813.dts is a simple DTS file for
-Broadcom BCM96813 Reference board that only enable the UART port.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
- .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 128 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm96813.dts | 30 ++++
- 3 files changed, 160 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -9,4 +9,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- bcm963158.dtb \
- bcm96858.dtb \
- bcm963146.dtb \
-- bcm96856.dtb
-+ bcm96856.dtb \
-+ bcm96813.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-@@ -0,0 +1,128 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+/ {
-+ compatible = "brcm,bcm6813", "brcm,bcmbca";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
-+ interrupt-parent = <&gic>;
-+
-+ cpus {
-+ #address-cells = <2>;
-+ #size-cells = <0>;
-+
-+ B53_0: cpu@0 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x0>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ B53_1: cpu@1 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x1>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ B53_2: cpu@2 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x2>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ B53_3: cpu@3 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x3>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ L2_0: l2-cache0 {
-+ compatible = "cache";
-+ };
-+ };
-+
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-+ };
-+
-+ pmu: pmu {
-+ compatible = "arm,cortex-a53-pmu";
-+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-affinity = <&B53_0>, <&B53_1>,
-+ <&B53_2>, <&B53_3>;
-+ };
-+
-+ clocks: clocks {
-+ periph_clk: periph-clk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
-+ uart_clk: uart-clk {
-+ compatible = "fixed-factor-clock";
-+ #clock-cells = <0>;
-+ clocks = <&periph_clk>;
-+ clock-div = <4>;
-+ clock-mult = <1>;
-+ };
-+ };
-+
-+ psci {
-+ compatible = "arm,psci-0.2";
-+ method = "smc";
-+ };
-+
-+ axi@81000000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0x81000000 0x8000>;
-+
-+ gic: interrupt-controller@1000 {
-+ compatible = "arm,gic-400";
-+ #interrupt-cells = <3>;
-+ interrupt-controller;
-+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-+ reg = <0x1000 0x1000>,
-+ <0x2000 0x2000>,
-+ <0x4000 0x2000>,
-+ <0x6000 0x2000>;
-+ };
-+ };
-+
-+ bus@ff800000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0xff800000 0x800000>;
-+
-+ uart0: serial@12000 {
-+ compatible = "arm,pl011", "arm,primecell";
-+ reg = <0x12000 0x1000>;
-+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&uart_clk>, <&uart_clk>;
-+ clock-names = "uartclk", "apb_pclk";
-+ status = "disabled";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm6813.dtsi"
-+
-+/ {
-+ model = "Broadcom BCM96813 Reference Board";
-+ compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
-+
-+ aliases {
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x0 0x0 0x0 0x08000000>;
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
+++ /dev/null
-From ea559c81b61603d4044df6f826f10a832c42c98c Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 15 Jun 2022 17:52:59 -0700
-Subject: [PATCH] arm64: dts: broadcom: align gpio-key node names with dtschema
-
-The node names should be generic and DT schema expects certain pattern
-(e.g. with key/button/switch).
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20220616005333.18491-6-krzysztof.kozlowski@linaro.org
----
- .../broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts | 8 ++++----
- .../boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts | 8 ++++----
- 2 files changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-@@ -83,25 +83,25 @@
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
-- brightness {
-+ key-brightness {
- label = "LEDs";
- linux,code = <KEY_BRIGHTNESS_ZERO>;
- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
- };
-
-- wps {
-+ key-wps {
- label = "WPS";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
-
-- wifi {
-+ key-wifi {
- label = "WiFi";
- linux,code = <KEY_RFKILL>;
- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
- };
-
-- restart {
-+ key-restart {
- label = "Reset";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -18,25 +18,25 @@
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
-- wifi {
-+ key-wifi {
- label = "WiFi";
- linux,code = <KEY_RFKILL>;
- gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
- };
-
-- wps {
-+ key-wps {
- label = "WPS";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
- };
-
-- restart {
-+ key-restart {
- label = "Reset";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
- };
-
-- brightness {
-+ key-brightness {
- label = "LEDs";
- linux,code = <KEY_BRIGHTNESS_ZERO>;
- gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
+++ /dev/null
-From b4a544e415e9be33b37d9bfa9d9f9f4d13f553d6 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Fri, 8 Jul 2022 11:25:06 -0700
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix timer node for BCM4906 SoC
-
-The cpu mask value in interrupt property inherits from bcm4908.dtsi
-which sets to four cpus. Correct the value to two cpus for dual core
-BCM4906 SoC.
-
-Fixes: c8b404fb05dc ("arm64: dts: broadcom: bcm4908: add BCM4906 Netgear R8000P DTS files")
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi
-@@ -17,6 +17,14 @@
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-+ };
-+
- pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+++ /dev/null
-From fdcd652ce2b6b819f5c4dc3cead5215c84ee6933 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 1 Jun 2022 15:56:50 -0700
-Subject: [PATCH] arm64: bcmbca: add arch bcmbca machine entry
-
-Add ARCH_BCMBCA config for Broadcom Broadband SoC chipsets
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/Kconfig.platforms | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/Kconfig.platforms
-+++ b/arch/arm64/Kconfig.platforms
-@@ -65,6 +65,15 @@ config ARCH_BCM_IPROC
- help
- This enables support for Broadcom iProc based SoCs
-
-+config ARCH_BCMBCA
-+ bool "Broadcom Broadband SoC"
-+ help
-+ Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
-+ BCA chipset.
-+
-+ This enables support for Broadcom BCA ARM-based broadband chipsets,
-+ including the DSL, PON and Wireless family of chips.
-+
- config ARCH_BERLIN
- bool "Marvell Berlin SoC Family"
- select DW_APB_ICTL
+++ /dev/null
-From 456b6dd1baadd2da10e28ffd1717b06d1fa17a97 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 18 Jul 2022 15:20:58 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add remaining LED pins
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Include all 32 pins.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220718132100.13277-1-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 75 +++++++++++++++++++
- 1 file changed, 75 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -349,6 +349,61 @@
- groups = "led_9_grp_a";
- };
-
-+ pins_led_10_a: led_10-a-pins {
-+ function = "led_10";
-+ groups = "led_10_grp_a";
-+ };
-+
-+ pins_led_11_a: led_11-a-pins {
-+ function = "led_11";
-+ groups = "led_11_grp_a";
-+ };
-+
-+ pins_led_12_a: led_12-a-pins {
-+ function = "led_12";
-+ groups = "led_12_grp_a";
-+ };
-+
-+ pins_led_13_a: led_13-a-pins {
-+ function = "led_13";
-+ groups = "led_13_grp_a";
-+ };
-+
-+ pins_led_14_a: led_14-a-pins {
-+ function = "led_14";
-+ groups = "led_14_grp_a";
-+ };
-+
-+ pins_led_15_a: led_15-a-pins {
-+ function = "led_15";
-+ groups = "led_15_grp_a";
-+ };
-+
-+ pins_led_16_a: led_16-a-pins {
-+ function = "led_16";
-+ groups = "led_16_grp_a";
-+ };
-+
-+ pins_led_17_a: led_17-a-pins {
-+ function = "led_17";
-+ groups = "led_17_grp_a";
-+ };
-+
-+ pins_led_18_a: led_18-a-pins {
-+ function = "led_18";
-+ groups = "led_18_grp_a";
-+ };
-+
-+ pins_led_19_a: led_19-a-pins {
-+ function = "led_19";
-+ groups = "led_19_grp_a";
-+ };
-+
-+ pins_led_20_a: led_20-a-pins {
-+ function = "led_20";
-+ groups = "led_20_grp_a";
-+ };
-+
- pins_led_21_a: led_21-a-pins {
- function = "led_21";
- groups = "led_21_grp_a";
-@@ -359,6 +414,21 @@
- groups = "led_22_grp_a";
- };
-
-+ pins_led_23_a: led_23-a-pins {
-+ function = "led_23";
-+ groups = "led_23_grp_a";
-+ };
-+
-+ pins_led_24_a: led_24-a-pins {
-+ function = "led_24";
-+ groups = "led_24_grp_a";
-+ };
-+
-+ pins_led_25_a: led_25-a-pins {
-+ function = "led_25";
-+ groups = "led_25_grp_a";
-+ };
-+
- pins_led_26_a: led_26-a-pins {
- function = "led_26";
- groups = "led_26_grp_a";
-@@ -384,6 +454,11 @@
- groups = "led_30_grp_a";
- };
-
-+ pins_led_31_a: led_31-a-pins {
-+ function = "led_31";
-+ groups = "led_31_grp_a";
-+ };
-+
- pins_hs_uart: hs_uart-pins {
- function = "hs_uart";
- groups = "hs_uart_grp";
+++ /dev/null
-From 7de56b1dc1149c702d4cc1e89ccc251bfb2bc246 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 18 Jul 2022 15:20:59 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add LEDs controller block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 includes LEDs controller that supports multiple brightness
-levels & hardware blinking.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220718132100.13277-2-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -514,6 +514,14 @@
- status = "okay";
- };
-
-+ leds: leds@800 {
-+ compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds";
-+ reg = <0x800 0xdc>;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- nand-controller@1800 {
- #address-cells = <1>;
- #size-cells = <0>;
+++ /dev/null
-From 3bcae3396e986b4ab97a69e8de517e32f9691a4b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 18 Jul 2022 15:21:00 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add Asus GT-AC5300 LEDs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There are 5 software-controllable LEDs on PCB.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220718132100.13277-3-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../bcmbca/bcm4908-asus-gt-ac5300.dts | 48 +++++++++++++++++++
- 1 file changed, 48 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -2,6 +2,7 @@
-
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-
- #include "bcm4908.dtsi"
-
-@@ -118,6 +119,53 @@
- };
- };
-
-+&leds {
-+ led-power@11 {
-+ reg = <0x11>;
-+ function = LED_FUNCTION_POWER;
-+ color = <LED_COLOR_ID_WHITE>;
-+ default-state = "on";
-+ active-low;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_led_17_a>;
-+ };
-+
-+ led-wan-red@12 {
-+ reg = <0x12>;
-+ function = LED_FUNCTION_WAN;
-+ color = <LED_COLOR_ID_RED>;
-+ active-low;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_led_18_a>;
-+ };
-+
-+ led-wps@14 {
-+ reg = <0x14>;
-+ function = LED_FUNCTION_WPS;
-+ color = <LED_COLOR_ID_WHITE>;
-+ active-low;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_led_20_a>;
-+ };
-+
-+ led-wan-white@15 {
-+ reg = <0x15>;
-+ function = LED_FUNCTION_WAN;
-+ color = <LED_COLOR_ID_WHITE>;
-+ active-low;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_led_21_a>;
-+ };
-+
-+ led-lan@19 {
-+ reg = <0x19>;
-+ function = LED_FUNCTION_LAN;
-+ color = <LED_COLOR_ID_WHITE>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_led_25_a>;
-+ };
-+};
-+
- &nandcs {
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
+++ /dev/null
-From 4fdcbde682291fba2c3f45a41decd656d92a314f Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 3 Aug 2022 10:54:49 -0700
-Subject: [PATCH] arm64: dts: bcmbca: update BCM4908 board dts files
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Append "brcm,bcmbca" to compatible strings based on the new bcmbca
-binding rule for BCM4908 family based boards.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Acked-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220803175455.47638-4-william.zhang@broadcom.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts | 2 +-
- .../dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts | 2 +-
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts | 2 +-
- .../arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts | 2 +-
- 4 files changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-@@ -7,7 +7,7 @@
- #include "bcm4906.dtsi"
-
- / {
-- compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908";
-+ compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
- model = "Netgear R8000P";
-
- memory@0 {
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-@@ -7,7 +7,7 @@
- #include "bcm4906.dtsi"
-
- / {
-- compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908";
-+ compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
- model = "TP-Link Archer C2300 V1";
-
- memory@0 {
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -7,7 +7,7 @@
- #include "bcm4908.dtsi"
-
- / {
-- compatible = "asus,gt-ac5300", "brcm,bcm4908";
-+ compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca";
- model = "Asus GT-AC5300";
-
- memory@0 {
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts
-@@ -3,7 +3,7 @@
- #include "bcm4908.dtsi"
-
- / {
-- compatible = "netgear,raxe500", "brcm,bcm4908";
-+ compatible = "netgear,raxe500", "brcm,bcm4908", "brcm,bcmbca";
- model = "Netgear RAXE500";
-
- memory@0 {
+++ /dev/null
-From 72e0bdb6d7edb1785d58f2e8e7c80e1d2f93a319 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 3 Aug 2022 10:54:51 -0700
-Subject: [PATCH] arm64: dts: Add BCM4908 generic board dts
-
-Add generic bare bone bcm94908.dts file to support any 4908 based
-design. It supports cpu subsystem, memory and an uart console. This can
-be useful for board bring-up and cpu subsystem and memory related kernel
-test as well.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Link: https://lore.kernel.org/r/20220803175455.47638-6-william.zhang@broadcom.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 1 +
- .../boot/dts/broadcom/bcmbca/bcm94908.dts | 30 +++++++++++++++++++
- 2 files changed, 31 insertions(+)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- bcm4906-tplink-archer-c2300-v1.dtb \
- bcm4908-asus-gt-ac5300.dtb \
- bcm4908-netgear-raxe500.dtb \
-+ bcm94908.dtb \
- bcm4912-asus-gt-ax6000.dtb \
- bcm94912.dtb \
- bcm963158.dtb \
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm4908.dtsi"
-+
-+/ {
-+ model = "Broadcom BCM94908 Reference Board";
-+ compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca";
-+
-+ aliases {
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x0 0x0 0x0 0x08000000>;
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
+++ /dev/null
-From 68064196cffea33f090bd2e8d81cd5e20107ecf1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 3 Nov 2022 11:53:16 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add TWD block timer
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 TWD contains block with 4 timers. Add binding for it.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221103105316.21294-1-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -280,6 +280,11 @@
- #address-cells = <1>;
- #size-cells = <1>;
-
-+ timer@0 {
-+ compatible = "brcm,bcm63138-timer";
-+ reg = <0x0 0x28>;
-+ };
-+
- watchdog@28 {
- compatible = "brcm,bcm6345-wdt";
- reg = <0x28 0x8>;
+++ /dev/null
-From 4f9fb09175e87a233787a2dee1e5dabb14deb022 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 3 Nov 2022 12:00:15 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm6858: add TWD block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM6858 contains TWD block with timers, watchdog, and reset subblocks.
-Describe it.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221103110015.21761-1-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-@@ -109,6 +109,25 @@
- #size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x62000>;
-
-+ twd: timer-mfd@400 {
-+ compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
-+ reg = <0x400 0x4c>;
-+ ranges = <0x0 0x400 0x4c>;
-+
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ timer@0 {
-+ compatible = "brcm,bcm63138-timer";
-+ reg = <0x0 0x28>;
-+ };
-+
-+ watchdog@28 {
-+ compatible = "brcm,bcm6345-wdt";
-+ reg = <0x28 0x8>;
-+ };
-+ };
-+
- uart0: serial@640 {
- compatible = "brcm,bcm6345-uart";
- reg = <0x640 0x18>;
+++ /dev/null
-From e567e58d6819adc002c57b81e16b88da24d3b4aa Mon Sep 17 00:00:00 2001
-From: Pierre Gondois <pierre.gondois@arm.com>
-Date: Tue, 22 Nov 2022 17:32:07 +0100
-Subject: [PATCH] arm64: dts: Update cache properties for broadcom
-
-The DeviceTree Specification v0.3 specifies that the cache node
-'compatible' and 'cache-level' properties are 'required'. Cf.
-s3.8 Multi-level and Shared Cache Nodes
-The 'cache-unified' property should be present if one of the
-properties for unified cache is present ('cache-size', ...).
-
-Update the Device Trees accordingly.
-
-Acked-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
-Link: https://lore.kernel.org/r/20221122163208.3810985-3-pierre.gondois@arm.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++
- 9 files changed, 12 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -63,6 +63,7 @@
-
- l2: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-@@ -51,6 +51,7 @@
-
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-@@ -35,6 +35,7 @@
-
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-@@ -51,6 +51,7 @@
-
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-@@ -51,6 +51,7 @@
-
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-@@ -35,6 +35,7 @@
-
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-@@ -50,6 +50,7 @@
- };
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
-@@ -79,6 +79,7 @@
-
- CLUSTER0_L2: l2-cache@0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
-@@ -108,18 +108,22 @@
-
- CLUSTER0_L2: l2-cache@0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
-
- CLUSTER1_L2: l2-cache@100 {
- compatible = "cache";
-+ cache-level = <2>;
- };
-
- CLUSTER2_L2: l2-cache@200 {
- compatible = "cache";
-+ cache-level = <2>;
- };
-
- CLUSTER3_L2: l2-cache@300 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
+++ /dev/null
-From f5d83b714e304d5f3229da434af2eeea033c4f5d Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Mon, 6 Feb 2023 22:58:15 -0800
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: Add spi controller node
-
-Add support for HSSPI controller in ARMv8 chip dts files.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Link: https://lore.kernel.org/r/20230207065826.285013-5-william.zhang@broadcom.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 18 +++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 20 +++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 19 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 19 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 20 +++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 18 +++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 18 +++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm94908.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm94912.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm963146.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm963158.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm96813.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm96856.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm96858.dts | 4 ++++
- 14 files changed, 160 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -107,6 +107,12 @@
- clock-frequency = <50000000>;
- clock-output-names = "periph";
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <400000000>;
-+ };
- };
-
- soc {
-@@ -528,6 +534,18 @@
- #size-cells = <0>;
- };
-
-+ hsspi: spi@1000{
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+ reg = <0x1000 0x600>;
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
-+
- nand-controller@1800 {
- #address-cells = <1>;
- #size-cells = <0>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-@@ -79,6 +79,7 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
- uart_clk: uart-clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
-@@ -86,6 +87,12 @@
- clock-div = <4>;
- clock-mult = <1>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
- };
-
- psci {
-@@ -117,6 +124,19 @@
- #size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x800000>;
-
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";
-+ reg = <0x1000 0x600>, <0x2610 0x4>;
-+ reg-names = "hsspi", "spim-ctrl";
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
-+
- uart0: serial@12000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-@@ -60,6 +60,7 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
- uart_clk: uart-clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
-@@ -67,6 +68,12 @@
- clock-div = <4>;
- clock-mult = <1>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
- };
-
- psci {
-@@ -99,6 +106,18 @@
- #size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x800000>;
-
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+ reg = <0x1000 0x600>;
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
-+
- uart0: serial@12000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-@@ -79,6 +79,7 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
- uart_clk: uart-clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
-@@ -86,6 +87,12 @@
- clock-div = <4>;
- clock-mult = <1>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <400000000>;
-+ };
- };
-
- psci {
-@@ -117,6 +124,18 @@
- #size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x800000>;
-
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+ reg = <0x1000 0x600>;
-+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
-+
- uart0: serial@12000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-@@ -79,6 +79,7 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
- uart_clk: uart-clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
-@@ -86,6 +87,12 @@
- clock-div = <4>;
- clock-mult = <1>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
- };
-
- psci {
-@@ -117,6 +124,19 @@
- #size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x800000>;
-
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1";
-+ reg = <0x1000 0x600>, <0x2610 0x4>;
-+ reg-names = "hsspi", "spim-ctrl";
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
-+
- uart0: serial@12000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-@@ -60,6 +60,12 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <400000000>;
-+ };
- };
-
- psci {
-@@ -100,5 +106,17 @@
- clock-names = "refclk";
- status = "disabled";
- };
-+
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+ reg = <0x1000 0x600>;
-+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
- };
- };
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-@@ -78,6 +78,12 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <400000000>;
-+ };
- };
-
- psci {
-@@ -137,5 +143,17 @@
- clock-names = "refclk";
- status = "disabled";
- };
-+
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+ reg = <0x1000 0x600>;
-+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
- };
- };
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
+++ /dev/null
-From 23be9f68f933adee8163b8efc9c6bff71410cc7c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:43:59 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: fix LED nodenames
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This fixes:
-arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dtb: leds@800: 'led-lan@19', 'led-power@11', 'led-wan-red@12', 'led-wan-white@15', 'led-wps@14' do not match any of the regexes: '^led@[a-f0-9]+$', 'pinctrl-[0-9]+'
- From schema: Documentation/devicetree/bindings/leds/leds-bcm63138.yaml
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144400.21689-2-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -120,7 +120,7 @@
- };
-
- &leds {
-- led-power@11 {
-+ led@11 {
- reg = <0x11>;
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
-@@ -130,7 +130,7 @@
- pinctrl-0 = <&pins_led_17_a>;
- };
-
-- led-wan-red@12 {
-+ led@12 {
- reg = <0x12>;
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_RED>;
-@@ -139,7 +139,7 @@
- pinctrl-0 = <&pins_led_18_a>;
- };
-
-- led-wps@14 {
-+ led@14 {
- reg = <0x14>;
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
-@@ -148,7 +148,7 @@
- pinctrl-0 = <&pins_led_20_a>;
- };
-
-- led-wan-white@15 {
-+ led@15 {
- reg = <0x15>;
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
-@@ -157,7 +157,7 @@
- pinctrl-0 = <&pins_led_21_a>;
- };
-
-- led-lan@19 {
-+ led@19 {
- reg = <0x19>;
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_WHITE>;
+++ /dev/null
-From 477cad715de1dfc256a20da3ed83b62f3cb2944d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:45:18 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add on-SoC USB ports
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 has 3 USB controllers each with 2 USB ports. Home routers often
-have LEDs indicating state of selected USB ports. Describe those SoC USB
-ports to allow using them as LED trigger sources.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144520.21816-1-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 39 +++++++++++++++++++
- 1 file changed, 39 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -148,6 +148,19 @@
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb_phy PHY_TYPE_USB2>;
- status = "disabled";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ ehci_port1: port@1 {
-+ reg = <1>;
-+ #trigger-source-cells = <0>;
-+ };
-+
-+ ehci_port2: port@2 {
-+ reg = <2>;
-+ #trigger-source-cells = <0>;
-+ };
- };
-
- ohci: usb@c400 {
-@@ -156,6 +169,19 @@
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb_phy PHY_TYPE_USB2>;
- status = "disabled";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ ohci_port1: port@1 {
-+ reg = <1>;
-+ #trigger-source-cells = <0>;
-+ };
-+
-+ ohci_port2: port@2 {
-+ reg = <2>;
-+ #trigger-source-cells = <0>;
-+ };
- };
-
- xhci: usb@d000 {
-@@ -164,6 +190,19 @@
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb_phy PHY_TYPE_USB3>;
- status = "disabled";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ xhci_port1: port@1 {
-+ reg = <1>;
-+ #trigger-source-cells = <0>;
-+ };
-+
-+ xhci_port2: port@2 {
-+ reg = <2>;
-+ #trigger-source-cells = <0>;
-+ };
- };
-
- bus@80000 {
+++ /dev/null
-From 889e53ccccc29ff4bf8d4c89cca34e8768845747 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:45:19 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add Netgear R8000P USB
- LED triggers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This device has 2 USB LEDs meant to be triggered by devices in relevant
-USB ports.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144520.21816-2-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-@@ -58,12 +58,16 @@
- function = "usb2";
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
-+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
-+ linux,default-trigger = "usbport";
- };
-
- led-usb3 {
- function = "usb3";
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
-+ trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>;
-+ linux,default-trigger = "usbport";
- };
-
- led-wifi {
+++ /dev/null
-From e6d356b146b75f1f77621aab7950a1eb550859f9 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:45:20 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add TP-Link C2300 USB
- LED triggers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This device has 2 USB LEDs meant to be triggered by devices in relevant
-USB ports.
-
-While at it fix typo in USB LED name.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144520.21816-3-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-@@ -64,12 +64,16 @@
- function = "usb2";
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
-+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
-+ linux,default-trigger = "usbport";
- };
-
- led-usb3 {
-- function = "usbd3";
-+ function = "usb3";
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
-+ trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>;
-+ linux,default-trigger = "usbport";
- };
-
- led-brightness {
+++ /dev/null
-From 002181f5b150e60c77f21de7ad4dd10e4614cd91 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 11 Jul 2022 17:30:41 +0200
-Subject: [PATCH] mtd: parsers: add Broadcom's U-Boot parser
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Broadcom stores environment variables blocks inside U-Boot partition
-itself. This driver finds & registers them.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20220711153041.6036-2-zajec5@gmail.com
----
- drivers/mtd/parsers/Kconfig | 10 ++++
- drivers/mtd/parsers/Makefile | 1 +
- drivers/mtd/parsers/brcm_u-boot.c | 84 +++++++++++++++++++++++++++++++
- 3 files changed, 95 insertions(+)
- create mode 100644 drivers/mtd/parsers/brcm_u-boot.c
-
---- a/drivers/mtd/parsers/Kconfig
-+++ b/drivers/mtd/parsers/Kconfig
-@@ -20,6 +20,16 @@ config MTD_BCM63XX_PARTS
- This provides partition parsing for BCM63xx devices with CFE
- bootloaders.
-
-+config MTD_BRCM_U_BOOT
-+ tristate "Broadcom's U-Boot partition parser"
-+ depends on ARCH_BCM4908 || COMPILE_TEST
-+ help
-+ Broadcom uses a custom way of storing U-Boot environment variables.
-+ They are placed inside U-Boot partition itself at unspecified offset.
-+ It's possible to locate them by looking for a custom header with a
-+ magic value. This driver does that and creates subpartitions for
-+ each found environment variables block.
-+
- config MTD_CMDLINE_PARTS
- tristate "Command line partition table parsing"
- depends on MTD
---- a/drivers/mtd/parsers/Makefile
-+++ b/drivers/mtd/parsers/Makefile
-@@ -2,6 +2,7 @@
- obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
- obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o
- obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o
-+obj-$(CONFIG_MTD_BRCM_U_BOOT) += brcm_u-boot.o
- obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
- obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
- obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
---- /dev/null
-+++ b/drivers/mtd/parsers/brcm_u-boot.c
-@@ -0,0 +1,84 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright © 2022 Rafał Miłecki <rafal@milecki.pl>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+
-+#define BRCM_U_BOOT_MAX_OFFSET 0x200000
-+#define BRCM_U_BOOT_STEP 0x1000
-+
-+#define BRCM_U_BOOT_MAX_PARTS 2
-+
-+#define BRCM_U_BOOT_MAGIC 0x75456e76 /* uEnv */
-+
-+struct brcm_u_boot_header {
-+ __le32 magic;
-+ __le32 length;
-+} __packed;
-+
-+static const char *names[BRCM_U_BOOT_MAX_PARTS] = {
-+ "u-boot-env",
-+ "u-boot-env-backup",
-+};
-+
-+static int brcm_u_boot_parse(struct mtd_info *mtd,
-+ const struct mtd_partition **pparts,
-+ struct mtd_part_parser_data *data)
-+{
-+ struct brcm_u_boot_header header;
-+ struct mtd_partition *parts;
-+ size_t bytes_read;
-+ size_t offset;
-+ int err;
-+ int i = 0;
-+
-+ parts = kcalloc(BRCM_U_BOOT_MAX_PARTS, sizeof(*parts), GFP_KERNEL);
-+ if (!parts)
-+ return -ENOMEM;
-+
-+ for (offset = 0;
-+ offset < min_t(size_t, mtd->size, BRCM_U_BOOT_MAX_OFFSET);
-+ offset += BRCM_U_BOOT_STEP) {
-+ err = mtd_read(mtd, offset, sizeof(header), &bytes_read, (uint8_t *)&header);
-+ if (err && !mtd_is_bitflip(err)) {
-+ pr_err("Failed to read from %s at 0x%zx: %d\n", mtd->name, offset, err);
-+ continue;
-+ }
-+
-+ if (le32_to_cpu(header.magic) != BRCM_U_BOOT_MAGIC)
-+ continue;
-+
-+ parts[i].name = names[i];
-+ parts[i].offset = offset;
-+ parts[i].size = sizeof(header) + le32_to_cpu(header.length);
-+ i++;
-+ pr_info("offset:0x%zx magic:0x%08x BINGO\n", offset, header.magic);
-+
-+ if (i == BRCM_U_BOOT_MAX_PARTS)
-+ break;
-+ }
-+
-+ *pparts = parts;
-+
-+ return i;
-+};
-+
-+static const struct of_device_id brcm_u_boot_of_match_table[] = {
-+ { .compatible = "brcm,u-boot" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, brcm_u_boot_of_match_table);
-+
-+static struct mtd_part_parser brcm_u_boot_mtd_parser = {
-+ .parse_fn = brcm_u_boot_parse,
-+ .name = "brcm_u-boot",
-+ .of_match_table = brcm_u_boot_of_match_table,
-+};
-+module_mtd_part_parser(brcm_u_boot_mtd_parser);
-+
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From af30f8eaa8fe4ff1987280f716309711997bd979 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 29 Dec 2021 18:16:42 +0100
-Subject: [PATCH] net: dsa: bcm_sf2: refactor LED regs access
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-1. Define more regs. Some switches (e.g. BCM4908) have up to 6 regs.
-2. Add helper for handling non-lineral port <-> reg mappings.
-3. Add support for 12 B LED reg blocks on BCM4908 (different layout)
-
-Complete support for LEDs setup will be implemented once Linux receives
-a proper design & implementation for "hardware" LEDs.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Link: https://lore.kernel.org/r/20211229171642.22942-1-zajec5@gmail.com
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/dsa/bcm_sf2.c | 54 ++++++++++++++++++++++++----
- drivers/net/dsa/bcm_sf2.h | 10 ++++++
- drivers/net/dsa/bcm_sf2_regs.h | 65 +++++++++++++++++++++++++++++++---
- 3 files changed, 119 insertions(+), 10 deletions(-)
-
---- a/drivers/net/dsa/bcm_sf2.c
-+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -62,6 +62,38 @@ static u16 bcm_sf2_reg_rgmii_cntrl(struc
- return REG_SWITCH_STATUS;
- }
-
-+static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port)
-+{
-+ switch (port) {
-+ case 0:
-+ return REG_LED_0_CNTRL;
-+ case 1:
-+ return REG_LED_1_CNTRL;
-+ case 2:
-+ return REG_LED_2_CNTRL;
-+ }
-+
-+ switch (priv->type) {
-+ case BCM4908_DEVICE_ID:
-+ switch (port) {
-+ case 3:
-+ return REG_LED_3_CNTRL;
-+ case 7:
-+ return REG_LED_4_CNTRL;
-+ default:
-+ break;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ WARN_ONCE(1, "Unsupported port %d\n", port);
-+
-+ /* RO fallback reg */
-+ return REG_SWITCH_STATUS;
-+}
-+
- /* Return the number of active ports, not counting the IMP (CPU) port */
- static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
- {
-@@ -187,9 +219,14 @@ static void bcm_sf2_gphy_enable_set(stru
-
- /* Use PHY-driven LED signaling */
- if (!enable) {
-- reg = reg_readl(priv, REG_LED_CNTRL(0));
-- reg |= SPDLNK_SRC_SEL;
-- reg_writel(priv, reg, REG_LED_CNTRL(0));
-+ u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0);
-+
-+ if (priv->type == BCM7278_DEVICE_ID ||
-+ priv->type == BCM7445_DEVICE_ID) {
-+ reg = reg_led_readl(priv, led_ctrl, 0);
-+ reg |= LED_CNTRL_SPDLNK_SRC_SEL;
-+ reg_led_writel(priv, reg, led_ctrl, 0);
-+ }
- }
- }
-
-@@ -1247,9 +1284,14 @@ static const u16 bcm_sf2_4908_reg_offset
- [REG_SPHY_CNTRL] = 0x24,
- [REG_CROSSBAR] = 0xc8,
- [REG_RGMII_11_CNTRL] = 0x014c,
-- [REG_LED_0_CNTRL] = 0x40,
-- [REG_LED_1_CNTRL] = 0x4c,
-- [REG_LED_2_CNTRL] = 0x58,
-+ [REG_LED_0_CNTRL] = 0x40,
-+ [REG_LED_1_CNTRL] = 0x4c,
-+ [REG_LED_2_CNTRL] = 0x58,
-+ [REG_LED_3_CNTRL] = 0x64,
-+ [REG_LED_4_CNTRL] = 0x88,
-+ [REG_LED_5_CNTRL] = 0xa0,
-+ [REG_LED_AGGREGATE_CTRL] = 0xb8,
-+
- };
-
- static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
---- a/drivers/net/dsa/bcm_sf2.h
-+++ b/drivers/net/dsa/bcm_sf2.h
-@@ -210,6 +210,16 @@ SF2_IO_MACRO(acb);
- SWITCH_INTR_L2(0);
- SWITCH_INTR_L2(1);
-
-+static inline u32 reg_led_readl(struct bcm_sf2_priv *priv, u16 off, u16 reg)
-+{
-+ return readl_relaxed(priv->reg + priv->reg_offsets[off] + reg);
-+}
-+
-+static inline void reg_led_writel(struct bcm_sf2_priv *priv, u32 val, u16 off, u16 reg)
-+{
-+ writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg);
-+}
-+
- /* RXNFC */
- int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
- struct ethtool_rxnfc *nfc, u32 *rule_locs);
---- a/drivers/net/dsa/bcm_sf2_regs.h
-+++ b/drivers/net/dsa/bcm_sf2_regs.h
-@@ -25,6 +25,10 @@ enum bcm_sf2_reg_offs {
- REG_LED_0_CNTRL,
- REG_LED_1_CNTRL,
- REG_LED_2_CNTRL,
-+ REG_LED_3_CNTRL,
-+ REG_LED_4_CNTRL,
-+ REG_LED_5_CNTRL,
-+ REG_LED_AGGREGATE_CTRL,
- REG_SWITCH_REG_MAX,
- };
-
-@@ -56,6 +60,63 @@ enum bcm_sf2_reg_offs {
- #define CROSSBAR_BCM4908_EXT_GPHY4 1
- #define CROSSBAR_BCM4908_EXT_RGMII 2
-
-+/* Relative to REG_LED_*_CNTRL (BCM7278, BCM7445) */
-+#define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0
-+#define LED_CNTRL_M10_ENCODE_SHIFT 2
-+#define LED_CNTRL_M100_ENCODE_SHIFT 4
-+#define LED_CNTRL_M1000_ENCODE_SHIFT 6
-+#define LED_CNTRL_SEL_NO_LINK_ENCODE_SHIFT 8
-+#define LED_CNTRL_SEL_10M_ENCODE_SHIFT 10
-+#define LED_CNTRL_SEL_100M_ENCODE_SHIFT 12
-+#define LED_CNTRL_SEL_1000M_ENCODE_SHIFT 14
-+#define LED_CNTRL_RX_DV_EN (1 << 16)
-+#define LED_CNTRL_TX_EN_EN (1 << 17)
-+#define LED_CNTRL_SPDLNK_LED0_ACT_SEL_SHIFT 18
-+#define LED_CNTRL_SPDLNK_LED1_ACT_SEL_SHIFT 20
-+#define LED_CNTRL_ACT_LED_ACT_SEL_SHIFT 22
-+#define LED_CNTRL_SPDLNK_SRC_SEL (1 << 24)
-+#define LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL (1 << 25)
-+#define LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL (1 << 26)
-+#define LED_CNTRL_ACT_LED_POL_SEL (1 << 27)
-+#define LED_CNTRL_MASK 0x3
-+
-+/* Register relative to REG_LED_*_CNTRL (BCM4908) */
-+#define REG_LED_CTRL 0x0
-+#define LED_CTRL_RX_ACT_EN 0x00000001
-+#define LED_CTRL_TX_ACT_EN 0x00000002
-+#define LED_CTRL_SPDLNK_LED0_ACT_SEL 0x00000004
-+#define LED_CTRL_SPDLNK_LED1_ACT_SEL 0x00000008
-+#define LED_CTRL_SPDLNK_LED2_ACT_SEL 0x00000010
-+#define LED_CTRL_ACT_LED_ACT_SEL 0x00000020
-+#define LED_CTRL_SPDLNK_LED0_ACT_POL_SEL 0x00000040
-+#define LED_CTRL_SPDLNK_LED1_ACT_POL_SEL 0x00000080
-+#define LED_CTRL_SPDLNK_LED2_ACT_POL_SEL 0x00000100
-+#define LED_CTRL_ACT_LED_POL_SEL 0x00000200
-+#define LED_CTRL_LED_SPD_OVRD 0x00001c00
-+#define LED_CTRL_LNK_STATUS_OVRD 0x00002000
-+#define LED_CTRL_SPD_OVRD_EN 0x00004000
-+#define LED_CTRL_LNK_OVRD_EN 0x00008000
-+
-+/* Register relative to REG_LED_*_CNTRL (BCM4908) */
-+#define REG_LED_LINK_SPEED_ENC_SEL 0x4
-+#define LED_LINK_SPEED_ENC_SEL_NO_LINK_SHIFT 0
-+#define LED_LINK_SPEED_ENC_SEL_10M_SHIFT 3
-+#define LED_LINK_SPEED_ENC_SEL_100M_SHIFT 6
-+#define LED_LINK_SPEED_ENC_SEL_1000M_SHIFT 9
-+#define LED_LINK_SPEED_ENC_SEL_2500M_SHIFT 12
-+#define LED_LINK_SPEED_ENC_SEL_10G_SHIFT 15
-+#define LED_LINK_SPEED_ENC_SEL_MASK 0x7
-+
-+/* Register relative to REG_LED_*_CNTRL (BCM4908) */
-+#define REG_LED_LINK_SPEED_ENC 0x8
-+#define LED_LINK_SPEED_ENC_NO_LINK_SHIFT 0
-+#define LED_LINK_SPEED_ENC_M10_SHIFT 3
-+#define LED_LINK_SPEED_ENC_M100_SHIFT 6
-+#define LED_LINK_SPEED_ENC_M1000_SHIFT 9
-+#define LED_LINK_SPEED_ENC_M2500_SHIFT 12
-+#define LED_LINK_SPEED_ENC_M10G_SHIFT 15
-+#define LED_LINK_SPEED_ENC_MASK 0x7
-+
- /* Relative to REG_RGMII_CNTRL */
- #define RGMII_MODE_EN (1 << 0)
- #define ID_MODE_DIS (1 << 1)
-@@ -73,10 +134,6 @@ enum bcm_sf2_reg_offs {
- #define LPI_COUNT_SHIFT 9
- #define LPI_COUNT_MASK 0x3F
-
--#define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x))
--
--#define SPDLNK_SRC_SEL (1 << 24)
--
- /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
- #define INTRL2_CPU_STATUS 0x00
- #define INTRL2_CPU_SET 0x04
+++ /dev/null
-From e93a766da57fff3273bcb618edf5dfca1fb86b89 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 15 Sep 2022 15:30:13 +0200
-Subject: [PATCH] net: broadcom: bcm4908_enet: handle -EPROBE_DEFER when
- getting MAC
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reading MAC from OF may return -EPROBE_DEFER if underlaying NVMEM device
-isn't ready yet. In such case pass that error code up and "wait" to be
-probed later.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220915133013.2243-1-zajec5@gmail.com
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/ethernet/broadcom/bcm4908_enet.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
-@@ -720,6 +720,8 @@ static int bcm4908_enet_probe(struct pla
-
- SET_NETDEV_DEV(netdev, &pdev->dev);
- err = of_get_ethdev_address(dev->of_node, netdev);
-+ if (err == -EPROBE_DEFER)
-+ goto err_dma_free;
- if (err)
- eth_hw_addr_random(netdev);
- netdev->netdev_ops = &bcm4908_enet_netdev_ops;
-@@ -730,14 +732,17 @@ static int bcm4908_enet_probe(struct pla
- netif_napi_add(netdev, &enet->rx_ring.napi, bcm4908_enet_poll_rx, NAPI_POLL_WEIGHT);
-
- err = register_netdev(netdev);
-- if (err) {
-- bcm4908_enet_dma_free(enet);
-- return err;
-- }
-+ if (err)
-+ goto err_dma_free;
-
- platform_set_drvdata(pdev, enet);
-
- return 0;
-+
-+err_dma_free:
-+ bcm4908_enet_dma_free(enet);
-+
-+ return err;
- }
-
- static int bcm4908_enet_remove(struct platform_device *pdev)
+++ /dev/null
-From 3a1cc23a75abcd9cea585eb84846507363d58397 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 25 Oct 2022 15:22:45 +0200
-Subject: [PATCH] net: broadcom: bcm4908_enet: use build_skb()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-RX code can be more efficient with the build_skb(). Allocating actual
-SKB around eth packet buffer - right before passing it up - results in
-a better cache usage.
-
-Without RPS (echo 0 > rps_cpus) BCM4908 NAT masq performance "jumps"
-between two speeds: ~900 Mbps and 940 Mbps (it's a 4 CPUs SoC). This
-change bumps the lower speed from 905 Mb/s to 918 Mb/s (tested using
-single stream iperf 2.0.5 traffic).
-
-There are more optimizations to consider. One obvious to try is GRO
-however as BCM4908 doesn't do hw csum is may actually lower performance.
-Sometimes. Some early testing:
-
-┌─────────────────────────────────┬─────────────────────┬────────────────────┐
-│ │ netif_receive_skb() │ napi_gro_receive() │
-├─────────────────────────────────┼─────────────────────┼────────────────────┤
-│ netdev_alloc_skb() │ 905 Mb/s │ 892 Mb/s │
-│ napi_alloc_frag() + build_skb() │ 918 Mb/s │ 917 Mb/s │
-└─────────────────────────────────┴─────────────────────┴────────────────────┘
-
-Another ideas:
-1. napi_build_skb()
-2. skb_copy_from_linear_data() for small packets
-
-Those need proper testing first though. That can be done later.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221025132245.22871-1-zajec5@gmail.com
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
- drivers/net/ethernet/broadcom/bcm4908_enet.c | 53 +++++++++++++-------
- 1 file changed, 36 insertions(+), 17 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
-@@ -36,13 +36,24 @@
- #define ENET_MAX_ETH_OVERHEAD (ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
- ETH_FCS_LEN + 4) /* 32 */
-
-+#define ENET_RX_SKB_BUF_SIZE (NET_SKB_PAD + NET_IP_ALIGN + \
-+ ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
-+ ENET_MTU_MAX + ETH_FCS_LEN + 4)
-+#define ENET_RX_SKB_BUF_ALLOC_SIZE (SKB_DATA_ALIGN(ENET_RX_SKB_BUF_SIZE) + \
-+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
-+#define ENET_RX_BUF_DMA_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
-+#define ENET_RX_BUF_DMA_SIZE (ENET_RX_SKB_BUF_SIZE - ENET_RX_BUF_DMA_OFFSET)
-+
- struct bcm4908_enet_dma_ring_bd {
- __le32 ctl;
- __le32 addr;
- } __packed;
-
- struct bcm4908_enet_dma_ring_slot {
-- struct sk_buff *skb;
-+ union {
-+ void *buf; /* RX */
-+ struct sk_buff *skb; /* TX */
-+ };
- unsigned int len;
- dma_addr_t dma_addr;
- };
-@@ -260,22 +271,21 @@ static int bcm4908_enet_dma_alloc_rx_buf
- u32 tmp;
- int err;
-
-- slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD;
--
-- slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
-- if (!slot->skb)
-+ slot->buf = napi_alloc_frag(ENET_RX_SKB_BUF_ALLOC_SIZE);
-+ if (!slot->buf)
- return -ENOMEM;
-
-- slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
-+ slot->dma_addr = dma_map_single(dev, slot->buf + ENET_RX_BUF_DMA_OFFSET,
-+ ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE);
- err = dma_mapping_error(dev, slot->dma_addr);
- if (err) {
- dev_err(dev, "Failed to map DMA buffer: %d\n", err);
-- kfree_skb(slot->skb);
-- slot->skb = NULL;
-+ skb_free_frag(slot->buf);
-+ slot->buf = NULL;
- return err;
- }
-
-- tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
-+ tmp = ENET_RX_BUF_DMA_SIZE << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
- tmp |= DMA_CTL_STATUS_OWN;
- if (idx == enet->rx_ring.length - 1)
- tmp |= DMA_CTL_STATUS_WRAP;
-@@ -315,11 +325,11 @@ static void bcm4908_enet_dma_uninit(stru
-
- for (i = rx_ring->length - 1; i >= 0; i--) {
- slot = &rx_ring->slots[i];
-- if (!slot->skb)
-+ if (!slot->buf)
- continue;
- dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
-- kfree_skb(slot->skb);
-- slot->skb = NULL;
-+ skb_free_frag(slot->buf);
-+ slot->buf = NULL;
- }
- }
-
-@@ -575,6 +585,7 @@ static int bcm4908_enet_poll_rx(struct n
- while (handled < weight) {
- struct bcm4908_enet_dma_ring_bd *buf_desc;
- struct bcm4908_enet_dma_ring_slot slot;
-+ struct sk_buff *skb;
- u32 ctl;
- int len;
- int err;
-@@ -598,16 +609,24 @@ static int bcm4908_enet_poll_rx(struct n
-
- if (len < ETH_ZLEN ||
- (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
-- kfree_skb(slot.skb);
-+ skb_free_frag(slot.buf);
- enet->netdev->stats.rx_dropped++;
- break;
- }
-
-- dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
-+ dma_unmap_single(dev, slot.dma_addr, ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE);
-+
-+ skb = build_skb(slot.buf, ENET_RX_SKB_BUF_ALLOC_SIZE);
-+ if (unlikely(!skb)) {
-+ skb_free_frag(slot.buf);
-+ enet->netdev->stats.rx_dropped++;
-+ break;
-+ }
-+ skb_reserve(skb, ENET_RX_BUF_DMA_OFFSET);
-+ skb_put(skb, len - ETH_FCS_LEN);
-+ skb->protocol = eth_type_trans(skb, enet->netdev);
-
-- skb_put(slot.skb, len - ETH_FCS_LEN);
-- slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
-- netif_receive_skb(slot.skb);
-+ netif_receive_skb(skb);
-
- enet->netdev->stats.rx_packets++;
- enet->netdev->stats.rx_bytes += len;
+++ /dev/null
-From 471ef777ec79baadc5cd9773d08f95f49cf5e2b1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 31 Oct 2022 11:48:56 +0100
-Subject: [PATCH] net: broadcom: bcm4908_enet: report queued and transmitted
- bytes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This allows BQL to operate avoiding buffer bloat and reducing latency.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221031104856.32388-1-zajec5@gmail.com
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/ethernet/broadcom/bcm4908_enet.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
-@@ -505,6 +505,7 @@ static int bcm4908_enet_stop(struct net_
- netif_carrier_off(netdev);
- napi_disable(&rx_ring->napi);
- napi_disable(&tx_ring->napi);
-+ netdev_reset_queue(netdev);
-
- bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring);
- bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring);
-@@ -564,6 +565,8 @@ static int bcm4908_enet_start_xmit(struc
- if (ring->write_idx + 1 == ring->length - 1)
- tmp |= DMA_CTL_STATUS_WRAP;
-
-+ netdev_sent_queue(enet->netdev, skb->len);
-+
- buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
- buf_desc->ctl = cpu_to_le32(tmp);
-
-@@ -671,6 +674,7 @@ static int bcm4908_enet_poll_tx(struct n
- tx_ring->read_idx = 0;
- }
-
-+ netdev_completed_queue(enet->netdev, handled, bytes);
- enet->netdev->stats.tx_packets += handled;
- enet->netdev->stats.tx_bytes += bytes;
-
+++ /dev/null
-From 7b5730f0ff24b0d7d1cb660a482384a807618a46 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 24 Jan 2022 11:22:42 +0100
-Subject: [PATCH] dt-bindings: pinctrl: Add binding for BCM4908 pinctrl
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-It's hardware block that is part of every SoC from BCM4908 family.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20220124102243.14912-1-zajec5@gmail.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- .../pinctrl/brcm,bcm4908-pinctrl.yaml | 72 +++++++++++++++++++
- MAINTAINERS | 7 ++
- 2 files changed, 79 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-@@ -0,0 +1,72 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Broadcom BCM4908 pin controller
-+
-+maintainers:
-+ - Rafał Miłecki <rafal@milecki.pl>
-+
-+description:
-+ Binding for pin controller present on BCM4908 family SoCs.
-+
-+properties:
-+ compatible:
-+ const: brcm,bcm4908-pinctrl
-+
-+ reg:
-+ maxItems: 1
-+
-+patternProperties:
-+ '-pins$':
-+ type: object
-+ $ref: pinmux-node.yaml#
-+
-+ properties:
-+ function:
-+ enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8,
-+ led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16,
-+ led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24,
-+ led_25, led_26, led_27, led_28, led_29, led_30, led_31,
-+ hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr,
-+ usb1_pwr ]
-+
-+ groups:
-+ minItems: 1
-+ maxItems: 2
-+ items:
-+ enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a,
-+ led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a,
-+ led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b,
-+ led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b,
-+ led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a,
-+ led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a,
-+ led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a,
-+ led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a,
-+ led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a,
-+ led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp,
-+ nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp,
-+ usb1_pwr_grp ]
-+
-+allOf:
-+ - $ref: pinctrl.yaml#
-+
-+required:
-+ - compatible
-+ - reg
-+
-+unevaluatedProperties: false
-+
-+examples:
-+ - |
-+ pinctrl@ff800560 {
-+ compatible = "brcm,bcm4908-pinctrl";
-+ reg = <0xff800560 0x10>;
-+
-+ led_0-a-pins {
-+ function = "led_0";
-+ groups = "led_0_grp_a";
-+ };
-+ };
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -3573,6 +3573,13 @@ F: Documentation/devicetree/bindings/net
- F: drivers/net/ethernet/broadcom/bcm4908_enet.*
- F: drivers/net/ethernet/broadcom/unimac.h
-
-+BROADCOM BCM4908 PINMUX DRIVER
-+M: Rafał Miłecki <rafal@milecki.pl>
-+M: bcm-kernel-feedback-list@broadcom.com
-+L: linux-gpio@vger.kernel.org
-+S: Maintained
-+F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-+
- BROADCOM BCM5301X ARM ARCHITECTURE
- M: Hauke Mehrtens <hauke@hauke-m.de>
- M: Rafał Miłecki <zajec5@gmail.com>
+++ /dev/null
-From f7e322d99f1180270fb4a3e1ae992b3116cfcf34 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 24 Jan 2022 11:22:43 +0100
-Subject: [PATCH] pinctrl: bcm: add driver for BCM4908 pinmux
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 has its own pins layout so it needs a custom binding and a Linux
-driver.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
-Link: https://lore.kernel.org/r/20220124102243.14912-2-zajec5@gmail.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- MAINTAINERS | 1 +
- drivers/pinctrl/bcm/Kconfig | 14 +
- drivers/pinctrl/bcm/Makefile | 1 +
- drivers/pinctrl/bcm/pinctrl-bcm4908.c | 563 ++++++++++++++++++++++++++
- 4 files changed, 579 insertions(+)
- create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm4908.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -3579,6 +3579,7 @@ M: bcm-kernel-feedback-list@broadcom.com
- L: linux-gpio@vger.kernel.org
- S: Maintained
- F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-+F: drivers/pinctrl/bcm/pinctrl-bcm4908.c
-
- BROADCOM BCM5301X ARM ARCHITECTURE
- M: Hauke Mehrtens <hauke@hauke-m.de>
---- a/drivers/pinctrl/bcm/Kconfig
-+++ b/drivers/pinctrl/bcm/Kconfig
-@@ -29,6 +29,20 @@ config PINCTRL_BCM2835
- help
- Say Y here to enable the Broadcom BCM2835 GPIO driver.
-
-+config PINCTRL_BCM4908
-+ tristate "Broadcom BCM4908 pinmux driver"
-+ depends on OF && (ARCH_BCM4908 || COMPILE_TEST)
-+ select PINMUX
-+ select PINCONF
-+ select GENERIC_PINCONF
-+ select GENERIC_PINCTRL_GROUPS
-+ select GENERIC_PINMUX_FUNCTIONS
-+ default ARCH_BCM4908
-+ help
-+ Driver for BCM4908 family SoCs with integrated pin controller.
-+
-+ If compiled as module it will be called pinctrl-bcm4908.
-+
- config PINCTRL_BCM63XX
- bool
- select PINMUX
---- a/drivers/pinctrl/bcm/Makefile
-+++ b/drivers/pinctrl/bcm/Makefile
-@@ -3,6 +3,7 @@
-
- obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
- obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
-+obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o
- obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
- obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o
- obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
---- /dev/null
-+++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c
-@@ -0,0 +1,560 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/* Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> */
-+
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/pinctrl/pinconf-generic.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/string_helpers.h>
-+
-+#include "../core.h"
-+#include "../pinmux.h"
-+
-+#define BCM4908_NUM_PINS 86
-+
-+#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00
-+#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04
-+#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08
-+#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12
-+#define BCM4908_TEST_PORT_COMMAND 0x0c
-+#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021
-+
-+struct bcm4908_pinctrl {
-+ struct device *dev;
-+ void __iomem *base;
-+ struct mutex mutex;
-+ struct pinctrl_dev *pctldev;
-+ struct pinctrl_desc pctldesc;
-+};
-+
-+/*
-+ * Groups
-+ */
-+
-+struct bcm4908_pinctrl_pin_setup {
-+ unsigned int number;
-+ unsigned int function;
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = {
-+ { 0, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = {
-+ { 1, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = {
-+ { 2, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = {
-+ { 3, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = {
-+ { 4, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = {
-+ { 5, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = {
-+ { 6, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = {
-+ { 7, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = {
-+ { 8, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = {
-+ { 9, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = {
-+ { 10, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = {
-+ { 11, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = {
-+ { 12, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = {
-+ { 13, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = {
-+ { 14, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = {
-+ { 15, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = {
-+ { 16, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = {
-+ { 17, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = {
-+ { 18, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = {
-+ { 19, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = {
-+ { 20, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = {
-+ { 21, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = {
-+ { 22, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = {
-+ { 23, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = {
-+ { 24, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = {
-+ { 25, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = {
-+ { 26, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = {
-+ { 27, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = {
-+ { 28, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = {
-+ { 29, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = {
-+ { 30, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = {
-+ { 31, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = {
-+ { 8, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = {
-+ { 9, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = {
-+ { 0, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = {
-+ { 1, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = {
-+ { 30, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = {
-+ { 10, 0 }, /* CTS */
-+ { 11, 0 }, /* RTS */
-+ { 12, 0 }, /* RXD */
-+ { 13, 0 }, /* TXD */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = {
-+ { 18, 0 }, /* SDA */
-+ { 19, 0 }, /* SCL */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = {
-+ { 22, 0 }, /* SDA */
-+ { 23, 0 }, /* SCL */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = {
-+ { 27, 0 }, /* MCLK */
-+ { 28, 0 }, /* LRCK */
-+ { 29, 0 }, /* SDATA */
-+ { 30, 0 }, /* SCLK */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = {
-+ { 32, 0 },
-+ { 33, 0 },
-+ { 34, 0 },
-+ { 43, 0 },
-+ { 44, 0 },
-+ { 45, 0 },
-+ { 56, 1 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = {
-+ { 35, 0 },
-+ { 36, 0 },
-+ { 37, 0 },
-+ { 38, 0 },
-+ { 39, 0 },
-+ { 40, 0 },
-+ { 41, 0 },
-+ { 42, 0 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = {
-+ { 46, 0 },
-+ { 47, 0 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = {
-+ { 63, 0 },
-+ { 64, 0 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = {
-+ { 66, 0 },
-+ { 67, 0 },
-+};
-+
-+struct bcm4908_pinctrl_grp {
-+ const char *name;
-+ const struct bcm4908_pinctrl_pin_setup *pins;
-+ const unsigned int num_pins;
-+};
-+
-+static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = {
-+ { "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) },
-+ { "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) },
-+ { "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) },
-+ { "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) },
-+ { "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) },
-+ { "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) },
-+ { "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) },
-+ { "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) },
-+ { "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) },
-+ { "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) },
-+ { "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) },
-+ { "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) },
-+ { "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) },
-+ { "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) },
-+ { "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) },
-+ { "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) },
-+ { "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) },
-+ { "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) },
-+ { "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) },
-+ { "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) },
-+ { "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) },
-+ { "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) },
-+ { "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) },
-+ { "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) },
-+ { "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) },
-+ { "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) },
-+ { "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) },
-+ { "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) },
-+ { "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) },
-+ { "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) },
-+ { "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) },
-+ { "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) },
-+ { "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) },
-+ { "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) },
-+ { "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) },
-+ { "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) },
-+ { "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) },
-+ { "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) },
-+ { "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) },
-+ { "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) },
-+ { "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) },
-+ { "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) },
-+ { "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) },
-+ { "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) },
-+ { "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) },
-+ { "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) },
-+};
-+
-+/*
-+ * Functions
-+ */
-+
-+struct bcm4908_pinctrl_function {
-+ const char *name;
-+ const char **groups;
-+ const unsigned int num_groups;
-+};
-+
-+static const char *led_0_groups[] = { "led_0_grp_a" };
-+static const char *led_1_groups[] = { "led_1_grp_a" };
-+static const char *led_2_groups[] = { "led_2_grp_a" };
-+static const char *led_3_groups[] = { "led_3_grp_a" };
-+static const char *led_4_groups[] = { "led_4_grp_a" };
-+static const char *led_5_groups[] = { "led_5_grp_a" };
-+static const char *led_6_groups[] = { "led_6_grp_a" };
-+static const char *led_7_groups[] = { "led_7_grp_a" };
-+static const char *led_8_groups[] = { "led_8_grp_a" };
-+static const char *led_9_groups[] = { "led_9_grp_a" };
-+static const char *led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" };
-+static const char *led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" };
-+static const char *led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" };
-+static const char *led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" };
-+static const char *led_14_groups[] = { "led_14_grp_a" };
-+static const char *led_15_groups[] = { "led_15_grp_a" };
-+static const char *led_16_groups[] = { "led_16_grp_a" };
-+static const char *led_17_groups[] = { "led_17_grp_a" };
-+static const char *led_18_groups[] = { "led_18_grp_a" };
-+static const char *led_19_groups[] = { "led_19_grp_a" };
-+static const char *led_20_groups[] = { "led_20_grp_a" };
-+static const char *led_21_groups[] = { "led_21_grp_a" };
-+static const char *led_22_groups[] = { "led_22_grp_a" };
-+static const char *led_23_groups[] = { "led_23_grp_a" };
-+static const char *led_24_groups[] = { "led_24_grp_a" };
-+static const char *led_25_groups[] = { "led_25_grp_a" };
-+static const char *led_26_groups[] = { "led_26_grp_a" };
-+static const char *led_27_groups[] = { "led_27_grp_a" };
-+static const char *led_28_groups[] = { "led_28_grp_a" };
-+static const char *led_29_groups[] = { "led_29_grp_a" };
-+static const char *led_30_groups[] = { "led_30_grp_a" };
-+static const char *led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" };
-+static const char *hs_uart_groups[] = { "hs_uart_grp" };
-+static const char *i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" };
-+static const char *i2s_groups[] = { "i2s_grp" };
-+static const char *nand_ctrl_groups[] = { "nand_ctrl_grp" };
-+static const char *nand_data_groups[] = { "nand_data_grp" };
-+static const char *emmc_ctrl_groups[] = { "emmc_ctrl_grp" };
-+static const char *usb0_pwr_groups[] = { "usb0_pwr_grp" };
-+static const char *usb1_pwr_groups[] = { "usb1_pwr_grp" };
-+
-+static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = {
-+ { "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) },
-+ { "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) },
-+ { "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) },
-+ { "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) },
-+ { "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) },
-+ { "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) },
-+ { "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) },
-+ { "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) },
-+ { "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) },
-+ { "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) },
-+ { "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) },
-+ { "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) },
-+ { "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) },
-+ { "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) },
-+ { "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) },
-+ { "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) },
-+ { "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) },
-+ { "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) },
-+ { "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) },
-+ { "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) },
-+ { "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) },
-+ { "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) },
-+ { "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) },
-+ { "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) },
-+ { "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) },
-+ { "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) },
-+ { "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) },
-+ { "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) },
-+ { "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) },
-+ { "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) },
-+ { "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) },
-+ { "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) },
-+ { "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) },
-+ { "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) },
-+ { "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) },
-+ { "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) },
-+ { "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) },
-+ { "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) },
-+ { "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) },
-+ { "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) },
-+};
-+
-+/*
-+ * Groups code
-+ */
-+
-+static const struct pinctrl_ops bcm4908_pinctrl_ops = {
-+ .get_groups_count = pinctrl_generic_get_group_count,
-+ .get_group_name = pinctrl_generic_get_group_name,
-+ .get_group_pins = pinctrl_generic_get_group_pins,
-+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
-+ .dt_free_map = pinconf_generic_dt_free_map,
-+};
-+
-+/*
-+ * Functions code
-+ */
-+
-+static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
-+ unsigned int func_selector,
-+ unsigned int group_selector)
-+{
-+ struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
-+ const struct bcm4908_pinctrl_grp *group;
-+ struct group_desc *group_desc;
-+ int i;
-+
-+ group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector);
-+ if (!group_desc)
-+ return -EINVAL;
-+ group = group_desc->data;
-+
-+ mutex_lock(&bcm4908_pinctrl->mutex);
-+ for (i = 0; i < group->num_pins; i++) {
-+ u32 lsb = 0;
-+
-+ lsb |= group->pins[i].number;
-+ lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT;
-+
-+ writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB);
-+ writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB);
-+ writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG,
-+ bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND);
-+ }
-+ mutex_unlock(&bcm4908_pinctrl->mutex);
-+
-+ return 0;
-+}
-+
-+static const struct pinmux_ops bcm4908_pinctrl_pmxops = {
-+ .get_functions_count = pinmux_generic_get_function_count,
-+ .get_function_name = pinmux_generic_get_function_name,
-+ .get_function_groups = pinmux_generic_get_function_groups,
-+ .set_mux = bcm4908_pinctrl_set_mux,
-+};
-+
-+/*
-+ * Controller code
-+ */
-+
-+static struct pinctrl_desc bcm4908_pinctrl_desc = {
-+ .name = "bcm4908-pinctrl",
-+ .pctlops = &bcm4908_pinctrl_ops,
-+ .pmxops = &bcm4908_pinctrl_pmxops,
-+};
-+
-+static const struct of_device_id bcm4908_pinctrl_of_match_table[] = {
-+ { .compatible = "brcm,bcm4908-pinctrl", },
-+ { }
-+};
-+
-+static int bcm4908_pinctrl_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct bcm4908_pinctrl *bcm4908_pinctrl;
-+ struct pinctrl_desc *pctldesc;
-+ struct pinctrl_pin_desc *pins;
-+ int i;
-+
-+ bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL);
-+ if (!bcm4908_pinctrl)
-+ return -ENOMEM;
-+ pctldesc = &bcm4908_pinctrl->pctldesc;
-+ platform_set_drvdata(pdev, bcm4908_pinctrl);
-+
-+ /* Set basic properties */
-+
-+ bcm4908_pinctrl->dev = dev;
-+
-+ bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(bcm4908_pinctrl->base))
-+ return PTR_ERR(bcm4908_pinctrl->base);
-+
-+ mutex_init(&bcm4908_pinctrl->mutex);
-+
-+ memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc));
-+
-+ /* Set pinctrl properties */
-+
-+ pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL);
-+ if (!pins)
-+ return -ENOMEM;
-+ for (i = 0; i < BCM4908_NUM_PINS; i++) {
-+ pins[i].number = i;
-+ pins[i].name = devm_kasprintf(dev, GFP_KERNEL, "pin-%d", i);
-+ if (!pins[i].name)
-+ return -ENOMEM;
-+ }
-+ pctldesc->pins = pins;
-+ pctldesc->npins = BCM4908_NUM_PINS;
-+
-+ /* Register */
-+
-+ bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl);
-+ if (IS_ERR(bcm4908_pinctrl->pctldev))
-+ return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev),
-+ "Failed to register pinctrl\n");
-+
-+ /* Groups */
-+
-+ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) {
-+ const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i];
-+ int *pins;
-+ int j;
-+
-+ pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL);
-+ if (!pins)
-+ return -ENOMEM;
-+ for (j = 0; j < group->num_pins; j++)
-+ pins[j] = group->pins[j].number;
-+
-+ pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name,
-+ pins, group->num_pins, (void *)group);
-+ }
-+
-+ /* Functions */
-+
-+ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) {
-+ const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i];
-+
-+ pinmux_generic_add_function(bcm4908_pinctrl->pctldev,
-+ function->name,
-+ function->groups,
-+ function->num_groups, NULL);
-+ }
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm4908_pinctrl_driver = {
-+ .probe = bcm4908_pinctrl_probe,
-+ .driver = {
-+ .name = "bcm4908-pinctrl",
-+ .of_match_table = bcm4908_pinctrl_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(bcm4908_pinctrl_driver);
-+
-+MODULE_AUTHOR("Rafał Miłecki");
-+MODULE_LICENSE("GPL v2");
-+MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);
+++ /dev/null
-From d0aee048d648ec2d9aa7af43b127ebf847d497d5 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Fri, 11 Feb 2022 11:58:06 +0100
-Subject: [PATCH] i2c: brcmstb: allow compiling on BCM4908
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 SoCs use the same I2C hardware block as STB and BCM63xx devices.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/Kconfig | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/i2c/busses/Kconfig
-+++ b/drivers/i2c/busses/Kconfig
-@@ -477,8 +477,8 @@ config I2C_BCM_KONA
-
- config I2C_BRCMSTB
- tristate "BRCM Settop/DSL I2C controller"
-- depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || \
-- ARCH_BCM_63XX || COMPILE_TEST
-+ depends on ARCH_BCM2835 || ARCH_BCM4908 || ARCH_BCM_63XX || \
-+ ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
- default y
- help
- If you say yes to this option, support will be included for the
+++ /dev/null
-From cd91fb2776967b2b2dea27307a3f23ba3d9bbb32 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 9 Feb 2022 21:32:02 +0100
-Subject: [PATCH] watchdog: allow building BCM7038_WDT for BCM4908
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 is a SoCs family that shares a lot of hardware with BCM63xx
-including the watchdog block. Allow building this driver for it.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20220209203202.26395-1-zajec5@gmail.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -1756,7 +1756,7 @@ config BCM7038_WDT
- tristate "BCM7038 Watchdog"
- select WATCHDOG_CORE
- depends on HAS_IOMEM
-- depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
-+ depends on ARCH_BCM4908 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
- help
- Watchdog driver for the built-in hardware in Broadcom 7038 and
- later SoCs used in set-top boxes. BCM7038 was made public
+++ /dev/null
-From 2dd441f16d6ad6104d85c4e5dfeb6dde4df26869 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 16 Feb 2022 07:34:08 +0100
-Subject: [PATCH] watchdog: bcm7038_wdt: Support BCM6345 compatible string
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-A new "compatible" value has been added in the commit 17fffe91ba36
-("dt-bindings: watchdog: Add BCM6345 compatible to BCM7038 binding").
-It's meant to be used for BCM63xx SoCs family but hardware block can be
-programmed just like the 7038 one.
-
-Cc: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20220216063408.23168-1-zajec5@gmail.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/bcm7038_wdt.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/watchdog/bcm7038_wdt.c
-+++ b/drivers/watchdog/bcm7038_wdt.c
-@@ -212,6 +212,7 @@ static SIMPLE_DEV_PM_OPS(bcm7038_wdt_pm_
- bcm7038_wdt_resume);
-
- static const struct of_device_id bcm7038_wdt_match[] = {
-+ { .compatible = "brcm,bcm6345-wdt" },
- { .compatible = "brcm,bcm7038-wdt" },
- {},
- };
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 28 Mar 2024 10:24:34 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: set
- brcm,wp-not-connected
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Every described BCM4908 board has WP pin not connected. This caused
-problems for drivers since day 0 but there was no property to describe
-that properly. Projects like OpenWrt were modifying Linux driver to deal
-with it.
-
-It's not clear if that is hardware limitation or just reference design
-being copied over and over but this applies to all known / supported
-BCM4908 boards. Handle it by marking WP as not connected by default.
-
-Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files")
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -593,6 +593,7 @@
- reg-names = "nand", "nand-int-base";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "nand_ctlrdy";
-+ brcm,wp-not-connected;
- status = "okay";
-
- nandcs: nand@0 {
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 15 Feb 2021 22:01:03 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: limit amount of GPIOs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Linux driver can't handle more than 64 GPIOs
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -340,7 +340,7 @@
- gpio0: gpio-controller@500 {
- compatible = "brcm,bcm6345-gpio";
- reg-names = "dirout", "dat";
-- reg = <0x500 0x28>, <0x528 0x28>;
-+ reg = <0x500 0x8>, <0x528 0x8>;
-
- #gpio-cells = <2>;
- gpio-controller;
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 12 Aug 2021 11:52:42 +0200
-Subject: [PATCH] arm64: don't issue HVC on boot
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Broadcom's CFE loader seems to miss setting SCR_EL3.HCE which results in
-generating an UNDEF and kernel panic on the first HVC.
-
-HVC gets issued by kernels 5.12+ while booting, by kexec and KVM. Until
-someone finds a workaround we have to avoid all above.
-
-Workarounds: 0c93df9622d4 ("arm64: Initialise as nVHE before switching to VHE")
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- arch/arm64/kernel/hyp-stub.S | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/kernel/hyp-stub.S
-+++ b/arch/arm64/kernel/hyp-stub.S
-@@ -238,7 +238,7 @@ SYM_FUNC_START(switch_to_vhe)
-
- // Turn the world upside down
- mov x0, #HVC_VHE_RESTART
-- hvc #0
-+// hvc #0
- 1:
- ret
- SYM_FUNC_END(switch_to_vhe)
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 15 Feb 2021 23:59:26 +0100
-Subject: [PATCH] net: dsa: bcm_sf2: enable GPHY for switch probing
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-GPHY needs to be enabled to succesfully probe & setup switch port
-connected to it. Otherwise hardcoding PHY OUI would be required.
-
-Before:
-brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch wan (uninitialized): error -5 setting up PHY for tree 0, switch 0, port 7
-
-After:
-brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch wan (uninitialized): PHY [800c05c0.mdio--1:0c] driver [Generic PHY] (irq=POLL)
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- drivers/net/dsa/bcm_sf2.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/dsa/bcm_sf2.c
-+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -1548,10 +1548,14 @@ static int bcm_sf2_sw_probe(struct platf
- rev = reg_readl(priv, REG_PHY_REVISION);
- priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
-
-+ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
-+
- ret = b53_switch_register(dev);
- if (ret)
- goto out_mdio;
-
-+ bcm_sf2_gphy_enable_set(priv->dev->ds, false);
-+
- dev_info(&pdev->dev,
- "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
- priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 16 Feb 2021 00:06:35 +0100
-Subject: [PATCH] net: dsa: bcm_sf2: keep GPHY enabled on the BCM4908
-
-Trying to access disabled PHY results in MDIO_READ_FAIL and:
-[ 11.962886] brcm-sf2 80080000.switch wan: configuring for phy/internal link mode
-[ 11.972500] 8021q: adding VLAN 0 to HW filter on device wan
-[ 11.980205] ------------[ cut here ]------------
-[ 11.984885] WARNING: CPU: 0 PID: 7 at phy_error+0x10/0x58
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- drivers/net/dsa/bcm_sf2.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/net/dsa/bcm_sf2.c
-+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -1562,6 +1562,12 @@ static int bcm_sf2_sw_probe(struct platf
- priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
- priv->irq0, priv->irq1);
-
-+ /* BCM4908 has 5 GPHYs which means bcm_sf2_port_setup() will not enable
-+ * GPHY when needed. Leave it enabled here.
-+ */
-+ if (priv->type == BCM4908_DEVICE_ID)
-+ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
-+
- return 0;
-
- out_mdio:
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -283,6 +283,11 @@
+@@ -280,6 +280,11 @@
#address-cells = <1>;
#size-cells = <1>;
};
soc {
-@@ -531,6 +537,18 @@
+@@ -528,6 +534,18 @@
#size-cells = <0>;
};
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -596,6 +596,7 @@
+@@ -593,6 +593,7 @@
reg-names = "nand", "nand-int-base";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "nand_ctlrdy";
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -343,7 +343,7 @@
+@@ -340,7 +340,7 @@
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
if (xhci->quirks & XHCI_NEC_HOST)
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
-@@ -1902,6 +1902,7 @@ struct xhci_hcd {
+@@ -1907,6 +1907,7 @@ struct xhci_hcd {
#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
#define NETIF_F_UPPER_DISABLES NETIF_F_LRO
/* changeable features with no special hardware requirements */
--#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
+#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO)
/* Changeable features with no special hardware requirements that defaults to off. */
--#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
-+#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
#define NETIF_F_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \
NETIF_F_HW_VLAN_CTAG_RX | \
if (xhci->quirks & XHCI_NEC_HOST)
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
-@@ -1907,6 +1907,7 @@ struct xhci_hcd {
+@@ -1912,6 +1912,7 @@ struct xhci_hcd {
#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
subs r9, r9, #1 @ decrement the index
bge loop2
subs r4, r4, #1 @ decrement the way
+--- a/arch/arm/boot/compressed/vmlinux.lds.S
++++ b/arch/arm/boot/compressed/vmlinux.lds.S
+@@ -41,6 +41,7 @@ SECTIONS
+ *(.start)
+ *(.text)
+ *(.text.*)
++ *(.init.text)
+ ARM_STUBS_TEXT
+ }
+ .table : ALIGN(4) {
#define NETIF_F_UPPER_DISABLES NETIF_F_LRO
/* changeable features with no special hardware requirements */
--#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
+#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO)
/* Changeable features with no special hardware requirements that defaults to off. */
--#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
-+#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
#define NETIF_F_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \
NETIF_F_HW_VLAN_CTAG_RX | \
ucidef_set_bridge_device switch
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
;;
+inteno,xg6846)
+ ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan ext1"
+ ;;
comtrend,ar-5381u |\
comtrend,ar-5387un |\
innacomm,w3400v6 |\
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_BCM63XX_FW=y
CONFIG_MTD_SPLIT_BCM_WFI_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+/*
+ * Devicetree for the Inteno XG6846 router, mostly used as a
+ * media converter from fiber to twisted pair ethernet
+ * "fiber modem" in many households in Sweden. The Marvell
+ * switch has one of its ports connected to an SFP (Small Form
+ * Factor pluggable) optical fiber receiver, which is bridged
+ * to the twisted pair connector LAN1.
+ *
+ * This device tree is inspired by research from the OpenWrt
+ * and Sweclockers forums, including contributions from
+ * NPeca75, mrhaav and csom.
+ *
+ * Some devices have a USB type A host receptacle mounted,
+ * some do not.
+ */
+#include "bcm6328.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Inteno XG6846";
+ compatible = "inteno,xg6846", "brcm,bcm6328";
+
+ /* OpenWrt-specific aliases */
+ aliases {
+ led-boot = &led_pwr_red;
+ led-failsafe = &led_pwr_red;
+ led-running = &led_pwr_green;
+ led-upgrade = &led_pwr_red;
+ led-usb = &led_usb_green;
+ };
+
+ chosen {
+ bootargs = "rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
+ };
+
+ /*
+ * This I2C port is connected to the SFP and reflects the EEPROM etc
+ * inside the SFP module. If the module is not plugged in, consequently
+ * nothing will be found on the bus.
+ */
+ i2c0: i2c-sfp {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* This I2C bus is used for the external CATV connector (usually unused) */
+ i2c1: i2c-catv {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ debounce-interval = <60>;
+ };
+ };
+};
+
+&hsspi {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ /*
+ * HW 1.0-1.1: Spansion S25FL128S1
+ * HW 1.3: Winbond W25Q128
+ *
+ * Fast Read Data max speed is 50MHz, see the Winbond W25Q128
+ * datasheet table 9.5 "AC Electrical Characteristics", we can
+ * use this speed because the chip supports fast reads. Older
+ * HW has different NOR chips, I assume they can all do fast
+ * reads.
+ */
+ spi-max-frequency = <104000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ m25p,fast-read;
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cfe: partition@0 {
+ label = "cfe";
+ reg = <0x0000000 0x0010000>;
+ read-only;
+ };
+
+ partition@10000 {
+ compatible = "openwrt,uimage", "denx,uimage";
+ reg = <0x010000 0xfe0000>;
+ label = "firmware";
+ openwrt,offset = <0x30000>;
+ };
+
+ partition@ff0000 {
+ reg = <0xff0000 0x010000>;
+ label = "nvram";
+ };
+ };
+ };
+};
+
+&cfe {
+ compatible = "nvmem-cells";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_cfe_6a0: macaddr@6a0 {
+ reg = <0x6a0 0x6>;
+ };
+};
+
+ðernet {
+ status = "okay";
+
+ nvmem-cells = <&macaddr_cfe_6a0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&switch0 {
+ dsa,member = <0 0>;
+
+ ports {
+ switch0port4: port@4 {
+ reg = <4>;
+ label = "extsw";
+
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
+
+&mdio_ext {
+ switch1: switch@0 {
+ /* The switch is not using any external IRQ, sadly */
+ compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ dsa,member = <1 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-handle = <&lan1phy>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-handle = <&lan2phy>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ phy-handle = <&lan3phy>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ phy-handle = <&lan4phy>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "ext1";
+ phy-handle = <&ext1phy>;
+ };
+
+ port@5 {
+ reg = <5>;
+ phy-mode = "rgmii-id";
+ label = "wan";
+ sfp = <&sfp0>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ phy-mode = "rgmii-id";
+ label = "cpu";
+ ethernet = <&switch0port4>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lan1phy: ethernet-phy@0 {
+ reg = <0>;
+ interrupt-parent = <&switch1>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ lan2phy: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&switch1>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ lan3phy: ethernet-phy@2 {
+ reg = <2>;
+ interrupt-parent = <&switch1>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ lan4phy: ethernet-phy@3 {
+ reg = <3>;
+ interrupt-parent = <&switch1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ ext1phy: ethernet-phy@4 {
+ reg = <4>;
+ interrupt-parent = <&switch1>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl_xg6846_usb_spd_led: xg6846_usb_spd_led-pins {
+ function = "led";
+ pins = "gpio17";
+ };
+};
+
+&leds {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_xg6846_usb_spd_led>, /* GPIO16 LED USB */
+ <&pinctrl_ephy1_spd_led>, /* GPIO18 LED PWR red */
+ <&pinctrl_ephy3_spd_led>; /* GPIO20 LED PWR green */
+
+ /* On board variants without USB this LED is not mounted */
+ led_usb_green: led@16 {
+ reg = <16>;
+ active-low;
+ label = "green:usb";
+ default-state = "off";
+ };
+
+ /*
+ * LED 18 and 20 drive the same physical LED, the PWR
+ * LED that can be both red and green.
+ */
+ led_pwr_red: led@18 {
+ reg = <18>;
+ active-low;
+ label = "red:pwr";
+ default-state = "off";
+ };
+
+ led_pwr_green: led@20 {
+ reg = <20>;
+ active-low;
+ label = "green:pwr";
+ default-state = "off";
+ };
+
+};
include $(INCLUDE_DIR)/image.mk
KERNEL_LOADADDR := 0x80010000 # RAM start + 64K
+UBOOT_ENTRY := 0x81c00000
LOADER_ENTRY := 0x81000000 # RAM start + 16M, for relocate
LZMA_TEXT_START := 0x82000000 # RAM start + 32M
$(CFE_EXTRAS) $(1)
endef
+# Build a CFE image with just U-Boot
+define Build/cfe-bin-uboot
+ cp $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot.bin $@
+ $(call Build/lzma)
+ mv $@ $@.uboot.lzma
+ echo "dummy" > $@.dummyfs
+ $(STAGING_DIR_HOST)/bin/imagetag -i $@.uboot.lzma -f $@.dummyfs \
+ --output $@ --boardid $(CFE_BOARD_ID) --chipid $(CHIP_ID) \
+ --entry $(UBOOT_ENTRY) --load-addr $(UBOOT_ENTRY) \
+ --info1 "$(call ModelNameLimit16,$(DEVICE_NAME))" \
+ $(CFE_EXTRAS) $(1)
+ rm $@.uboot.lzma
+ rm $@.dummyfs
+endef
+
define Build/cfe-jffs2
$(STAGING_DIR_HOST)/bin/mkfs.jffs2 \
--big-endian \
KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma-cfe
endef
+# CFE images with U-Boot in front of the kernel, these will execute
+# U-Boot instead of the kernel and U-Boot will then proceed to load
+# the kernel. The reason to do this is that CFE is sometimes unable to
+# load big kernels even with the lzma loader tricks.
+define Device/bcm63xx-cfe-uboot
+ $(Device/bcm63xx-cfe)
+ KERNEL := kernel-bin | append-dtb | lzma | uImage lzma
+ IMAGE/cfe.bin := cfe-bin-uboot | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+ append-kernel | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+ append-rootfs $$$$(if $$$$(FLASH_MB),--pad $$$$(shell expr $$$$(FLASH_MB) / 2))
+ IMAGE/sysupgrade.bin := cfe-bin-uboot | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+ append-kernel | pad-to $$$$$$$$(($$(BLOCKSIZE))) | \
+ append-rootfs | append-metadata
+endef
+
# CFE expects a single JFFS2 partition with cferam and kernel. However,
# it's possible to fool CFE into properly loading both cferam and kernel
# from two different JFFS2 partitions by adding dummy files (see
endef
TARGET_DEVICES += innacomm_w3400v6
+define Device/inteno_xg6846
+ $(Device/bcm63xx-cfe-uboot)
+ DEVICE_VENDOR := Inteno
+ DEVICE_MODEL := XG6846
+ CHIP_ID := 6328
+ CFE_BOARD_ID := 96328avng
+ FLASH_MB := 16
+ DEVICE_PACKAGES := $(USB2_PACKAGES) \
+ kmod-i2c-core kmod-i2c-gpio \
+ kmod-leds-bcm6328 kmod-dsa-mv88e6xxx \
+ kmod-sfp
+endef
+TARGET_DEVICES += inteno_xg6846
+
define Device/nucom_r5010unv2
$(Device/bcm63xx-cfe)
DEVICE_VENDOR := NuCom
BOARDNAME:=AllWinner D1 RISC-V SoC
FEATURES:=ext4 squashfs
KERNELNAME:=Image dtbs
+SUBTARGETS:=generic
KERNEL_PATCHVER:=6.1
--- /dev/null
+BOARDNAME:=Generic
CPU_TYPE:=fa526
SUBTARGETS:=generic
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
define Target/Description
Build firmware images for the StorLink/Cortina Gemini CS351x ARM FA526 CPU
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_AMBA_PL08X=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_GEMINI=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_ARCH_MOXART is not set
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V4=y
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-# CONFIG_ARCH_MULTI_V5 is not set
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_UNWIND=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_ATA_FORCE=y
-CONFIG_ATA_VERBOSE_ERROR=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_PERCENTAGE=10
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-# CONFIG_CMA_SIZE_SEL_MBYTES is not set
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-CONFIG_CMA_SIZE_SEL_PERCENTAGE=y
-# CONFIG_CMA_SYSFS is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_GEMINI=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPU_32v4=y
-CONFIG_CPU_ABRT_EV4=y
-CONFIG_CPU_CACHE_FA=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_FA=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_FA526=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_NO_EFFICIENT_FFS=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_TLB_FA=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_SL3516=y
-# CONFIG_CRYPTO_DEV_SL3516_DEBUG is not set
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECHAINIV=y
-CONFIG_CRYPTO_ENGINE=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DRM=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_DMA_HELPER=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_NOMODESET=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ILITEK_IL9322=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_TVE200=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_93CX6=y
-CONFIG_ELF_CORE=y
-# CONFIG_EMBEDDED is not set
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-# CONFIG_EXPERT is not set
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_FARADAY_FTINTC010=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FTTMR010_TIMER=y
-CONFIG_FTWDT010_WATCHDOG=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GEMINI_ETHERNET=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_FTGPIO010=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HDMI=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IO_URING=y
-CONFIG_IPC_NS=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KCMP=y
-CONFIG_KERNEL_LZMA=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEYBOARD_DLINK_DIR685=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-# CONFIG_LDM_DEBUG is not set
-CONFIG_LDM_PARTITION=y
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_LINUX_MONO is not set
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MODULE_UNLOAD is not set
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_GEMINI=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_WRGG_FW=y
-CONFIG_NAMESPACES=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_REALTEK=y
-# CONFIG_NET_DSA_REALTEK_MDIO is not set
-# CONFIG_NET_DSA_REALTEK_RTL8365MB is not set
-CONFIG_NET_DSA_REALTEK_RTL8366RB=y
-CONFIG_NET_DSA_REALTEK_SMI=y
-CONFIG_NET_DSA_TAG_RTL4_A=y
-CONFIG_NET_NS=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-CONFIG_PATA_FTIDE010=y
-CONFIG_PCI=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_FTPCI100=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PID_NS=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_GEMINI=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GEMINI_POWEROFF=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_BUILD=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RELAY=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RSEQ=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_FTRTC010=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RTC_NVMEM=y
-CONFIG_SATA_GEMINI=y
-CONFIG_SATA_HOST=y
-CONFIG_SATA_PMP=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_SENSORS_DRIVETEMP=y
-CONFIG_SENSORS_GPIO_FAN=y
-CONFIG_SENSORS_LM75=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_STACKDEPOT=y
-CONFIG_STACKTRACE=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SWPHY=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB_COMMON=y
-# CONFIG_USB_FOTG210 is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_GPIO_VBUS=y
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USER_NS=y
-CONFIG_USE_OF=y
-CONFIG_UTS_NS=y
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VITESSE_PHY=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_INFLATE=y
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_AMBA_PL08X=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_GEMINI=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MOXART is not set
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V4=y
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V4_V5=y
+# CONFIG_ARCH_MULTI_V5 is not set
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_ATA_FORCE=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_CACHESTAT_SYSCALL=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_PERCENTAGE=10
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+# CONFIG_CMA_SIZE_SEL_MBYTES is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+CONFIG_CMA_SIZE_SEL_PERCENTAGE=y
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_GEMINI=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_32v4=y
+CONFIG_CPU_ABRT_EV4=y
+CONFIG_CPU_CACHE_FA=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_FA=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+CONFIG_CPU_FA526=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_TLB_FA=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_DEV_JH7110 is not set
+CONFIG_CRYPTO_DEV_SL3516=y
+# CONFIG_CRYPTO_DEV_SL3516_DEBUG is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_ENGINE=y
+CONFIG_CRYPTO_GENIV=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SIG2=y
+CONFIG_CRYPTO_USER=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DMADEVICES=y
+CONFIG_DMATEST=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ENGINE_RAID=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_GEM_DMA_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ILITEK_IL9322=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_TVE200=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_93CX6=y
+CONFIG_ELF_CORE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+# CONFIG_EXPERT is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_FARADAY_FTINTC010=y
+CONFIG_FB=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DMAMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FTTMR010_TIMER=y
+CONFIG_FTWDT010_WATCHDOG=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GEMINI_ETHERNET=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_FTGPIO010=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HDMI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_IO_URING=y
+CONFIG_IPC_NS=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYBOARD_DLINK_DIR685=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+# CONFIG_LDM_DEBUG is not set
+CONFIG_LDM_PARTITION=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO_LINUX_MONO is not set
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MODULE_UNLOAD is not set
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_GEMINI=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_WRGG_FW=y
+CONFIG_NAMESPACES=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_REALTEK=y
+# CONFIG_NET_DSA_REALTEK_MDIO is not set
+# CONFIG_NET_DSA_REALTEK_RTL8365MB is not set
+CONFIG_NET_DSA_REALTEK_RTL8366RB=y
+CONFIG_NET_DSA_REALTEK_SMI=y
+CONFIG_NET_DSA_TAG_RTL4_A=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_NS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PATA_FTIDE010=y
+CONFIG_PCI=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_FTPCI100=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PID_NS=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_GEMINI=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GEMINI_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RELAY=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_FTRTC010=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RTC_NVMEM=y
+CONFIG_SATA_GEMINI=y
+CONFIG_SATA_HOST=y
+CONFIG_SATA_PMP=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SENSORS_DRIVETEMP=y
+CONFIG_SENSORS_GPIO_FAN=y
+CONFIG_SENSORS_LM75=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_STACKDEPOT=y
+CONFIG_STACKTRACE=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_FOTG210 is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GPIO_VBUS=y
+CONFIG_USB_PHY=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USER_NS=y
+CONFIG_USE_OF=y
+CONFIG_UTS_NS=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VITESSE_PHY=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_INFLATE=y
# All DTB files are prefixed with "gemini-"
define Device/Default
PROFILES := Default
+ DEVICE_DTS_DIR = $$(DTS_DIR)/gemini
KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
KERNEL_NAME := zImage
KERNEL := kernel-bin | append-dtb
+++ /dev/null
-From d5a026cc8306ccd3e99e1455c87e38f8e6fa18df Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 7 Nov 2022 00:05:06 +0100
-Subject: [PATCH 01/29] usb: phy: phy-gpio-vbus-usb: Add device tree probing
-
-Make it possible to probe the GPIO VBUS detection driver
-from the device tree compatible for GPIO USB B connectors.
-
-Since this driver is using the "gpio-usb-b-connector"
-compatible, it is important to discern it from the role
-switch connector driver (which does not provide a phy),
-so we add some Kconfig text and depend on !USB_CONN_GPIO.
-
-Cc: Rob Herring <robh@kernel.org>
-Cc: Prashant Malani <pmalani@chromium.org>
-Cc: Felipe Balbi <balbi@kernel.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221106230506.1646101-1-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/phy/Kconfig
-+++ b/drivers/usb/phy/Kconfig
-@@ -93,12 +93,16 @@ config USB_GPIO_VBUS
- tristate "GPIO based peripheral-only VBUS sensing 'transceiver'"
- depends on GPIOLIB || COMPILE_TEST
- depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
-+ depends on !USB_CONN_GPIO
- select USB_PHY
- help
- Provides simple GPIO VBUS sensing for controllers with an
- internal transceiver via the usb_phy interface, and
- optionally control of a D+ pullup GPIO as well as a VBUS
-- current limit regulator.
-+ current limit regulator. This driver is for devices that do
-+ NOT support role switch. OTG devices that can do role switch
-+ (master/peripheral) shall use the USB based connection
-+ detection driver USB_CONN_GPIO.
-
- config OMAP_OTG
- tristate "OMAP USB OTG controller driver"
---- a/drivers/usb/phy/phy-gpio-vbus-usb.c
-+++ b/drivers/usb/phy/phy-gpio-vbus-usb.c
-@@ -366,12 +366,24 @@ static const struct dev_pm_ops gpio_vbus
-
- MODULE_ALIAS("platform:gpio-vbus");
-
-+/*
-+ * NOTE: this driver matches against "gpio-usb-b-connector" for
-+ * devices that do NOT support role switch.
-+ */
-+static const struct of_device_id gpio_vbus_of_match[] = {
-+ {
-+ .compatible = "gpio-usb-b-connector",
-+ },
-+ {},
-+};
-+
- static struct platform_driver gpio_vbus_driver = {
- .driver = {
- .name = "gpio-vbus",
- #ifdef CONFIG_PM
- .pm = &gpio_vbus_dev_pm_ops,
- #endif
-+ .of_match_table = gpio_vbus_of_match,
- },
- .probe = gpio_vbus_probe,
- .remove = gpio_vbus_remove,
+++ /dev/null
-From 30367636930864f71b2bd462adedcf8484313864 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 23 Oct 2022 16:47:06 +0200
-Subject: [PATCH 02/29] usb: fotg210: Collect pieces of dual mode controller
-
-The Faraday FOTG210 is a dual-mode OTG USB controller that can
-act as host, peripheral or both. To be able to probe from one
-hardware description and to follow the pattern of other dual-
-mode controllers such as MUSB or MTU3 we need to collect the
-two, currently completely separate drivers in the same
-directory.
-
-After this, users need to select the main symbol USB_FOTG210
-and then each respective subdriver. We pave the road to
-compile both drivers into the same kernel and select the
-one we want to use at probe() time, and possibly add OTG
-support in the end.
-
-This patch doesn't do much more than create the new symbol
-and collect the drivers in one place. We also add a comment
-for the section of dual-mode controllers in the Kconfig
-file so people can see what these selections are about.
-
-Also add myself as maintainer as there has been little
-response on my patches to these drivers.
-
-Cc: Fabian Vogt <fabian@ritter-vogt.de>
-Cc: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-Cc: Felipe Balbi <balbi@kernel.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221023144708.3596563-1-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/Kconfig
-+++ b/drivers/usb/Kconfig
-@@ -111,8 +111,12 @@ source "drivers/usb/usbip/Kconfig"
-
- endif
-
-+comment "USB dual-mode controller drivers"
-+
- source "drivers/usb/cdns3/Kconfig"
-
-+source "drivers/usb/fotg210/Kconfig"
-+
- source "drivers/usb/mtu3/Kconfig"
-
- source "drivers/usb/musb/Kconfig"
---- a/drivers/usb/Makefile
-+++ b/drivers/usb/Makefile
-@@ -17,6 +17,8 @@ obj-$(CONFIG_USB_CDNS_SUPPORT) += cdns3/
- obj-$(CONFIG_USB_CDNS3) += cdns3/
- obj-$(CONFIG_USB_CDNSP_PCI) += cdns3/
-
-+obj-$(CONFIG_USB_FOTG210) += fotg210/
-+
- obj-$(CONFIG_USB_MON) += mon/
- obj-$(CONFIG_USB_MTU3) += mtu3/
-
---- /dev/null
-+++ b/drivers/usb/fotg210/Kconfig
-@@ -0,0 +1,36 @@
-+# SPDX-License-Identifier: GPL-2.0
-+
-+config USB_FOTG210
-+ tristate "Faraday FOTG210 USB2 Dual Role controller"
-+ depends on USB || USB_GADGET
-+ depends on HAS_DMA && HAS_IOMEM
-+ default ARCH_GEMINI
-+ help
-+ Faraday FOTG210 is a dual-mode USB controller that can act
-+ in both host controller and peripheral controller mode.
-+
-+if USB_FOTG210
-+
-+config USB_FOTG210_HCD
-+ tristate "Faraday FOTG210 USB Host Controller support"
-+ depends on USB
-+ help
-+ Faraday FOTG210 is an OTG controller which can be configured as
-+ an USB2.0 host. It is designed to meet USB2.0 EHCI specification
-+ with minor modification.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called fotg210-hcd.
-+
-+config USB_FOTG210_UDC
-+ depends on USB_GADGET
-+ tristate "Faraday FOTG210 USB Peripheral Controller support"
-+ help
-+ Faraday USB2.0 OTG controller which can be configured as
-+ high speed or full speed USB device. This driver suppports
-+ Bulk Transfer so far.
-+
-+ Say "y" to link the driver statically, or "m" to build a
-+ dynamically linked module called "fotg210-udc".
-+
-+endif
---- /dev/null
-+++ b/drivers/usb/fotg210/Makefile
-@@ -0,0 +1,3 @@
-+# SPDX-License-Identifier: GPL-2.0
-+obj-$(CONFIG_USB_FOTG210_HCD) += fotg210-hcd.o
-+obj-$(CONFIG_USB_FOTG210_UDC) += fotg210-udc.o
---- a/drivers/usb/host/fotg210-hcd.c
-+++ /dev/null
-@@ -1,5724 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0+
--/* Faraday FOTG210 EHCI-like driver
-- *
-- * Copyright (c) 2013 Faraday Technology Corporation
-- *
-- * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-- * Feng-Hsin Chiang <john453@faraday-tech.com>
-- * Po-Yu Chuang <ratbert.chuang@gmail.com>
-- *
-- * Most of code borrowed from the Linux-3.7 EHCI driver
-- */
--#include <linux/module.h>
--#include <linux/of.h>
--#include <linux/device.h>
--#include <linux/dmapool.h>
--#include <linux/kernel.h>
--#include <linux/delay.h>
--#include <linux/ioport.h>
--#include <linux/sched.h>
--#include <linux/vmalloc.h>
--#include <linux/errno.h>
--#include <linux/init.h>
--#include <linux/hrtimer.h>
--#include <linux/list.h>
--#include <linux/interrupt.h>
--#include <linux/usb.h>
--#include <linux/usb/hcd.h>
--#include <linux/moduleparam.h>
--#include <linux/dma-mapping.h>
--#include <linux/debugfs.h>
--#include <linux/slab.h>
--#include <linux/uaccess.h>
--#include <linux/platform_device.h>
--#include <linux/io.h>
--#include <linux/iopoll.h>
--#include <linux/clk.h>
--
--#include <asm/byteorder.h>
--#include <asm/irq.h>
--#include <asm/unaligned.h>
--
--#define DRIVER_AUTHOR "Yuan-Hsin Chen"
--#define DRIVER_DESC "FOTG210 Host Controller (EHCI) Driver"
--static const char hcd_name[] = "fotg210_hcd";
--
--#undef FOTG210_URB_TRACE
--#define FOTG210_STATS
--
--/* magic numbers that can affect system performance */
--#define FOTG210_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
--#define FOTG210_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
--#define FOTG210_TUNE_RL_TT 0
--#define FOTG210_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
--#define FOTG210_TUNE_MULT_TT 1
--
--/* Some drivers think it's safe to schedule isochronous transfers more than 256
-- * ms into the future (partly as a result of an old bug in the scheduling
-- * code). In an attempt to avoid trouble, we will use a minimum scheduling
-- * length of 512 frames instead of 256.
-- */
--#define FOTG210_TUNE_FLS 1 /* (medium) 512-frame schedule */
--
--/* Initial IRQ latency: faster than hw default */
--static int log2_irq_thresh; /* 0 to 6 */
--module_param(log2_irq_thresh, int, S_IRUGO);
--MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
--
--/* initial park setting: slower than hw default */
--static unsigned park;
--module_param(park, uint, S_IRUGO);
--MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets");
--
--/* for link power management(LPM) feature */
--static unsigned int hird;
--module_param(hird, int, S_IRUGO);
--MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
--
--#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
--
--#include "fotg210.h"
--
--#define fotg210_dbg(fotg210, fmt, args...) \
-- dev_dbg(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
--#define fotg210_err(fotg210, fmt, args...) \
-- dev_err(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
--#define fotg210_info(fotg210, fmt, args...) \
-- dev_info(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
--#define fotg210_warn(fotg210, fmt, args...) \
-- dev_warn(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
--
--/* check the values in the HCSPARAMS register (host controller _Structural_
-- * parameters) see EHCI spec, Table 2-4 for each value
-- */
--static void dbg_hcs_params(struct fotg210_hcd *fotg210, char *label)
--{
-- u32 params = fotg210_readl(fotg210, &fotg210->caps->hcs_params);
--
-- fotg210_dbg(fotg210, "%s hcs_params 0x%x ports=%d\n", label, params,
-- HCS_N_PORTS(params));
--}
--
--/* check the values in the HCCPARAMS register (host controller _Capability_
-- * parameters) see EHCI Spec, Table 2-5 for each value
-- */
--static void dbg_hcc_params(struct fotg210_hcd *fotg210, char *label)
--{
-- u32 params = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
--
-- fotg210_dbg(fotg210, "%s hcc_params %04x uframes %s%s\n", label,
-- params,
-- HCC_PGM_FRAMELISTLEN(params) ? "256/512/1024" : "1024",
-- HCC_CANPARK(params) ? " park" : "");
--}
--
--static void __maybe_unused
--dbg_qtd(const char *label, struct fotg210_hcd *fotg210, struct fotg210_qtd *qtd)
--{
-- fotg210_dbg(fotg210, "%s td %p n%08x %08x t%08x p0=%08x\n", label, qtd,
-- hc32_to_cpup(fotg210, &qtd->hw_next),
-- hc32_to_cpup(fotg210, &qtd->hw_alt_next),
-- hc32_to_cpup(fotg210, &qtd->hw_token),
-- hc32_to_cpup(fotg210, &qtd->hw_buf[0]));
-- if (qtd->hw_buf[1])
-- fotg210_dbg(fotg210, " p1=%08x p2=%08x p3=%08x p4=%08x\n",
-- hc32_to_cpup(fotg210, &qtd->hw_buf[1]),
-- hc32_to_cpup(fotg210, &qtd->hw_buf[2]),
-- hc32_to_cpup(fotg210, &qtd->hw_buf[3]),
-- hc32_to_cpup(fotg210, &qtd->hw_buf[4]));
--}
--
--static void __maybe_unused
--dbg_qh(const char *label, struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
-- struct fotg210_qh_hw *hw = qh->hw;
--
-- fotg210_dbg(fotg210, "%s qh %p n%08x info %x %x qtd %x\n", label, qh,
-- hw->hw_next, hw->hw_info1, hw->hw_info2,
-- hw->hw_current);
--
-- dbg_qtd("overlay", fotg210, (struct fotg210_qtd *) &hw->hw_qtd_next);
--}
--
--static void __maybe_unused
--dbg_itd(const char *label, struct fotg210_hcd *fotg210, struct fotg210_itd *itd)
--{
-- fotg210_dbg(fotg210, "%s[%d] itd %p, next %08x, urb %p\n", label,
-- itd->frame, itd, hc32_to_cpu(fotg210, itd->hw_next),
-- itd->urb);
--
-- fotg210_dbg(fotg210,
-- " trans: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-- hc32_to_cpu(fotg210, itd->hw_transaction[0]),
-- hc32_to_cpu(fotg210, itd->hw_transaction[1]),
-- hc32_to_cpu(fotg210, itd->hw_transaction[2]),
-- hc32_to_cpu(fotg210, itd->hw_transaction[3]),
-- hc32_to_cpu(fotg210, itd->hw_transaction[4]),
-- hc32_to_cpu(fotg210, itd->hw_transaction[5]),
-- hc32_to_cpu(fotg210, itd->hw_transaction[6]),
-- hc32_to_cpu(fotg210, itd->hw_transaction[7]));
--
-- fotg210_dbg(fotg210,
-- " buf: %08x %08x %08x %08x %08x %08x %08x\n",
-- hc32_to_cpu(fotg210, itd->hw_bufp[0]),
-- hc32_to_cpu(fotg210, itd->hw_bufp[1]),
-- hc32_to_cpu(fotg210, itd->hw_bufp[2]),
-- hc32_to_cpu(fotg210, itd->hw_bufp[3]),
-- hc32_to_cpu(fotg210, itd->hw_bufp[4]),
-- hc32_to_cpu(fotg210, itd->hw_bufp[5]),
-- hc32_to_cpu(fotg210, itd->hw_bufp[6]));
--
-- fotg210_dbg(fotg210, " index: %d %d %d %d %d %d %d %d\n",
-- itd->index[0], itd->index[1], itd->index[2],
-- itd->index[3], itd->index[4], itd->index[5],
-- itd->index[6], itd->index[7]);
--}
--
--static int __maybe_unused
--dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
--{
-- return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
-- label, label[0] ? " " : "", status,
-- (status & STS_ASS) ? " Async" : "",
-- (status & STS_PSS) ? " Periodic" : "",
-- (status & STS_RECL) ? " Recl" : "",
-- (status & STS_HALT) ? " Halt" : "",
-- (status & STS_IAA) ? " IAA" : "",
-- (status & STS_FATAL) ? " FATAL" : "",
-- (status & STS_FLR) ? " FLR" : "",
-- (status & STS_PCD) ? " PCD" : "",
-- (status & STS_ERR) ? " ERR" : "",
-- (status & STS_INT) ? " INT" : "");
--}
--
--static int __maybe_unused
--dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
--{
-- return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s",
-- label, label[0] ? " " : "", enable,
-- (enable & STS_IAA) ? " IAA" : "",
-- (enable & STS_FATAL) ? " FATAL" : "",
-- (enable & STS_FLR) ? " FLR" : "",
-- (enable & STS_PCD) ? " PCD" : "",
-- (enable & STS_ERR) ? " ERR" : "",
-- (enable & STS_INT) ? " INT" : "");
--}
--
--static const char *const fls_strings[] = { "1024", "512", "256", "??" };
--
--static int dbg_command_buf(char *buf, unsigned len, const char *label,
-- u32 command)
--{
-- return scnprintf(buf, len,
-- "%s%scommand %07x %s=%d ithresh=%d%s%s%s period=%s%s %s",
-- label, label[0] ? " " : "", command,
-- (command & CMD_PARK) ? " park" : "(park)",
-- CMD_PARK_CNT(command),
-- (command >> 16) & 0x3f,
-- (command & CMD_IAAD) ? " IAAD" : "",
-- (command & CMD_ASE) ? " Async" : "",
-- (command & CMD_PSE) ? " Periodic" : "",
-- fls_strings[(command >> 2) & 0x3],
-- (command & CMD_RESET) ? " Reset" : "",
-- (command & CMD_RUN) ? "RUN" : "HALT");
--}
--
--static char *dbg_port_buf(char *buf, unsigned len, const char *label, int port,
-- u32 status)
--{
-- char *sig;
--
-- /* signaling state */
-- switch (status & (3 << 10)) {
-- case 0 << 10:
-- sig = "se0";
-- break;
-- case 1 << 10:
-- sig = "k";
-- break; /* low speed */
-- case 2 << 10:
-- sig = "j";
-- break;
-- default:
-- sig = "?";
-- break;
-- }
--
-- scnprintf(buf, len, "%s%sport:%d status %06x %d sig=%s%s%s%s%s%s%s%s",
-- label, label[0] ? " " : "", port, status,
-- status >> 25, /*device address */
-- sig,
-- (status & PORT_RESET) ? " RESET" : "",
-- (status & PORT_SUSPEND) ? " SUSPEND" : "",
-- (status & PORT_RESUME) ? " RESUME" : "",
-- (status & PORT_PEC) ? " PEC" : "",
-- (status & PORT_PE) ? " PE" : "",
-- (status & PORT_CSC) ? " CSC" : "",
-- (status & PORT_CONNECT) ? " CONNECT" : "");
--
-- return buf;
--}
--
--/* functions have the "wrong" filename when they're output... */
--#define dbg_status(fotg210, label, status) { \
-- char _buf[80]; \
-- dbg_status_buf(_buf, sizeof(_buf), label, status); \
-- fotg210_dbg(fotg210, "%s\n", _buf); \
--}
--
--#define dbg_cmd(fotg210, label, command) { \
-- char _buf[80]; \
-- dbg_command_buf(_buf, sizeof(_buf), label, command); \
-- fotg210_dbg(fotg210, "%s\n", _buf); \
--}
--
--#define dbg_port(fotg210, label, port, status) { \
-- char _buf[80]; \
-- fotg210_dbg(fotg210, "%s\n", \
-- dbg_port_buf(_buf, sizeof(_buf), label, port, status));\
--}
--
--/* troubleshooting help: expose state in debugfs */
--static int debug_async_open(struct inode *, struct file *);
--static int debug_periodic_open(struct inode *, struct file *);
--static int debug_registers_open(struct inode *, struct file *);
--static int debug_async_open(struct inode *, struct file *);
--
--static ssize_t debug_output(struct file*, char __user*, size_t, loff_t*);
--static int debug_close(struct inode *, struct file *);
--
--static const struct file_operations debug_async_fops = {
-- .owner = THIS_MODULE,
-- .open = debug_async_open,
-- .read = debug_output,
-- .release = debug_close,
-- .llseek = default_llseek,
--};
--static const struct file_operations debug_periodic_fops = {
-- .owner = THIS_MODULE,
-- .open = debug_periodic_open,
-- .read = debug_output,
-- .release = debug_close,
-- .llseek = default_llseek,
--};
--static const struct file_operations debug_registers_fops = {
-- .owner = THIS_MODULE,
-- .open = debug_registers_open,
-- .read = debug_output,
-- .release = debug_close,
-- .llseek = default_llseek,
--};
--
--static struct dentry *fotg210_debug_root;
--
--struct debug_buffer {
-- ssize_t (*fill_func)(struct debug_buffer *); /* fill method */
-- struct usb_bus *bus;
-- struct mutex mutex; /* protect filling of buffer */
-- size_t count; /* number of characters filled into buffer */
-- char *output_buf;
-- size_t alloc_size;
--};
--
--static inline char speed_char(u32 scratch)
--{
-- switch (scratch & (3 << 12)) {
-- case QH_FULL_SPEED:
-- return 'f';
--
-- case QH_LOW_SPEED:
-- return 'l';
--
-- case QH_HIGH_SPEED:
-- return 'h';
--
-- default:
-- return '?';
-- }
--}
--
--static inline char token_mark(struct fotg210_hcd *fotg210, __hc32 token)
--{
-- __u32 v = hc32_to_cpu(fotg210, token);
--
-- if (v & QTD_STS_ACTIVE)
-- return '*';
-- if (v & QTD_STS_HALT)
-- return '-';
-- if (!IS_SHORT_READ(v))
-- return ' ';
-- /* tries to advance through hw_alt_next */
-- return '/';
--}
--
--static void qh_lines(struct fotg210_hcd *fotg210, struct fotg210_qh *qh,
-- char **nextp, unsigned *sizep)
--{
-- u32 scratch;
-- u32 hw_curr;
-- struct fotg210_qtd *td;
-- unsigned temp;
-- unsigned size = *sizep;
-- char *next = *nextp;
-- char mark;
-- __le32 list_end = FOTG210_LIST_END(fotg210);
-- struct fotg210_qh_hw *hw = qh->hw;
--
-- if (hw->hw_qtd_next == list_end) /* NEC does this */
-- mark = '@';
-- else
-- mark = token_mark(fotg210, hw->hw_token);
-- if (mark == '/') { /* qh_alt_next controls qh advance? */
-- if ((hw->hw_alt_next & QTD_MASK(fotg210)) ==
-- fotg210->async->hw->hw_alt_next)
-- mark = '#'; /* blocked */
-- else if (hw->hw_alt_next == list_end)
-- mark = '.'; /* use hw_qtd_next */
-- /* else alt_next points to some other qtd */
-- }
-- scratch = hc32_to_cpup(fotg210, &hw->hw_info1);
-- hw_curr = (mark == '*') ? hc32_to_cpup(fotg210, &hw->hw_current) : 0;
-- temp = scnprintf(next, size,
-- "qh/%p dev%d %cs ep%d %08x %08x(%08x%c %s nak%d)",
-- qh, scratch & 0x007f,
-- speed_char(scratch),
-- (scratch >> 8) & 0x000f,
-- scratch, hc32_to_cpup(fotg210, &hw->hw_info2),
-- hc32_to_cpup(fotg210, &hw->hw_token), mark,
-- (cpu_to_hc32(fotg210, QTD_TOGGLE) & hw->hw_token)
-- ? "data1" : "data0",
-- (hc32_to_cpup(fotg210, &hw->hw_alt_next) >> 1) & 0x0f);
-- size -= temp;
-- next += temp;
--
-- /* hc may be modifying the list as we read it ... */
-- list_for_each_entry(td, &qh->qtd_list, qtd_list) {
-- scratch = hc32_to_cpup(fotg210, &td->hw_token);
-- mark = ' ';
-- if (hw_curr == td->qtd_dma)
-- mark = '*';
-- else if (hw->hw_qtd_next == cpu_to_hc32(fotg210, td->qtd_dma))
-- mark = '+';
-- else if (QTD_LENGTH(scratch)) {
-- if (td->hw_alt_next == fotg210->async->hw->hw_alt_next)
-- mark = '#';
-- else if (td->hw_alt_next != list_end)
-- mark = '/';
-- }
-- temp = snprintf(next, size,
-- "\n\t%p%c%s len=%d %08x urb %p",
-- td, mark, ({ char *tmp;
-- switch ((scratch>>8)&0x03) {
-- case 0:
-- tmp = "out";
-- break;
-- case 1:
-- tmp = "in";
-- break;
-- case 2:
-- tmp = "setup";
-- break;
-- default:
-- tmp = "?";
-- break;
-- } tmp; }),
-- (scratch >> 16) & 0x7fff,
-- scratch,
-- td->urb);
-- if (size < temp)
-- temp = size;
-- size -= temp;
-- next += temp;
-- }
--
-- temp = snprintf(next, size, "\n");
-- if (size < temp)
-- temp = size;
--
-- size -= temp;
-- next += temp;
--
-- *sizep = size;
-- *nextp = next;
--}
--
--static ssize_t fill_async_buffer(struct debug_buffer *buf)
--{
-- struct usb_hcd *hcd;
-- struct fotg210_hcd *fotg210;
-- unsigned long flags;
-- unsigned temp, size;
-- char *next;
-- struct fotg210_qh *qh;
--
-- hcd = bus_to_hcd(buf->bus);
-- fotg210 = hcd_to_fotg210(hcd);
-- next = buf->output_buf;
-- size = buf->alloc_size;
--
-- *next = 0;
--
-- /* dumps a snapshot of the async schedule.
-- * usually empty except for long-term bulk reads, or head.
-- * one QH per line, and TDs we know about
-- */
-- spin_lock_irqsave(&fotg210->lock, flags);
-- for (qh = fotg210->async->qh_next.qh; size > 0 && qh;
-- qh = qh->qh_next.qh)
-- qh_lines(fotg210, qh, &next, &size);
-- if (fotg210->async_unlink && size > 0) {
-- temp = scnprintf(next, size, "\nunlink =\n");
-- size -= temp;
-- next += temp;
--
-- for (qh = fotg210->async_unlink; size > 0 && qh;
-- qh = qh->unlink_next)
-- qh_lines(fotg210, qh, &next, &size);
-- }
-- spin_unlock_irqrestore(&fotg210->lock, flags);
--
-- return strlen(buf->output_buf);
--}
--
--/* count tds, get ep direction */
--static unsigned output_buf_tds_dir(char *buf, struct fotg210_hcd *fotg210,
-- struct fotg210_qh_hw *hw, struct fotg210_qh *qh, unsigned size)
--{
-- u32 scratch = hc32_to_cpup(fotg210, &hw->hw_info1);
-- struct fotg210_qtd *qtd;
-- char *type = "";
-- unsigned temp = 0;
--
-- /* count tds, get ep direction */
-- list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
-- temp++;
-- switch ((hc32_to_cpu(fotg210, qtd->hw_token) >> 8) & 0x03) {
-- case 0:
-- type = "out";
-- continue;
-- case 1:
-- type = "in";
-- continue;
-- }
-- }
--
-- return scnprintf(buf, size, "(%c%d ep%d%s [%d/%d] q%d p%d)",
-- speed_char(scratch), scratch & 0x007f,
-- (scratch >> 8) & 0x000f, type, qh->usecs,
-- qh->c_usecs, temp, (scratch >> 16) & 0x7ff);
--}
--
--#define DBG_SCHED_LIMIT 64
--static ssize_t fill_periodic_buffer(struct debug_buffer *buf)
--{
-- struct usb_hcd *hcd;
-- struct fotg210_hcd *fotg210;
-- unsigned long flags;
-- union fotg210_shadow p, *seen;
-- unsigned temp, size, seen_count;
-- char *next;
-- unsigned i;
-- __hc32 tag;
--
-- seen = kmalloc_array(DBG_SCHED_LIMIT, sizeof(*seen), GFP_ATOMIC);
-- if (!seen)
-- return 0;
--
-- seen_count = 0;
--
-- hcd = bus_to_hcd(buf->bus);
-- fotg210 = hcd_to_fotg210(hcd);
-- next = buf->output_buf;
-- size = buf->alloc_size;
--
-- temp = scnprintf(next, size, "size = %d\n", fotg210->periodic_size);
-- size -= temp;
-- next += temp;
--
-- /* dump a snapshot of the periodic schedule.
-- * iso changes, interrupt usually doesn't.
-- */
-- spin_lock_irqsave(&fotg210->lock, flags);
-- for (i = 0; i < fotg210->periodic_size; i++) {
-- p = fotg210->pshadow[i];
-- if (likely(!p.ptr))
-- continue;
--
-- tag = Q_NEXT_TYPE(fotg210, fotg210->periodic[i]);
--
-- temp = scnprintf(next, size, "%4d: ", i);
-- size -= temp;
-- next += temp;
--
-- do {
-- struct fotg210_qh_hw *hw;
--
-- switch (hc32_to_cpu(fotg210, tag)) {
-- case Q_TYPE_QH:
-- hw = p.qh->hw;
-- temp = scnprintf(next, size, " qh%d-%04x/%p",
-- p.qh->period,
-- hc32_to_cpup(fotg210,
-- &hw->hw_info2)
-- /* uframe masks */
-- & (QH_CMASK | QH_SMASK),
-- p.qh);
-- size -= temp;
-- next += temp;
-- /* don't repeat what follows this qh */
-- for (temp = 0; temp < seen_count; temp++) {
-- if (seen[temp].ptr != p.ptr)
-- continue;
-- if (p.qh->qh_next.ptr) {
-- temp = scnprintf(next, size,
-- " ...");
-- size -= temp;
-- next += temp;
-- }
-- break;
-- }
-- /* show more info the first time around */
-- if (temp == seen_count) {
-- temp = output_buf_tds_dir(next,
-- fotg210, hw,
-- p.qh, size);
--
-- if (seen_count < DBG_SCHED_LIMIT)
-- seen[seen_count++].qh = p.qh;
-- } else
-- temp = 0;
-- tag = Q_NEXT_TYPE(fotg210, hw->hw_next);
-- p = p.qh->qh_next;
-- break;
-- case Q_TYPE_FSTN:
-- temp = scnprintf(next, size,
-- " fstn-%8x/%p",
-- p.fstn->hw_prev, p.fstn);
-- tag = Q_NEXT_TYPE(fotg210, p.fstn->hw_next);
-- p = p.fstn->fstn_next;
-- break;
-- case Q_TYPE_ITD:
-- temp = scnprintf(next, size,
-- " itd/%p", p.itd);
-- tag = Q_NEXT_TYPE(fotg210, p.itd->hw_next);
-- p = p.itd->itd_next;
-- break;
-- }
-- size -= temp;
-- next += temp;
-- } while (p.ptr);
--
-- temp = scnprintf(next, size, "\n");
-- size -= temp;
-- next += temp;
-- }
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- kfree(seen);
--
-- return buf->alloc_size - size;
--}
--#undef DBG_SCHED_LIMIT
--
--static const char *rh_state_string(struct fotg210_hcd *fotg210)
--{
-- switch (fotg210->rh_state) {
-- case FOTG210_RH_HALTED:
-- return "halted";
-- case FOTG210_RH_SUSPENDED:
-- return "suspended";
-- case FOTG210_RH_RUNNING:
-- return "running";
-- case FOTG210_RH_STOPPING:
-- return "stopping";
-- }
-- return "?";
--}
--
--static ssize_t fill_registers_buffer(struct debug_buffer *buf)
--{
-- struct usb_hcd *hcd;
-- struct fotg210_hcd *fotg210;
-- unsigned long flags;
-- unsigned temp, size, i;
-- char *next, scratch[80];
-- static const char fmt[] = "%*s\n";
-- static const char label[] = "";
--
-- hcd = bus_to_hcd(buf->bus);
-- fotg210 = hcd_to_fotg210(hcd);
-- next = buf->output_buf;
-- size = buf->alloc_size;
--
-- spin_lock_irqsave(&fotg210->lock, flags);
--
-- if (!HCD_HW_ACCESSIBLE(hcd)) {
-- size = scnprintf(next, size,
-- "bus %s, device %s\n"
-- "%s\n"
-- "SUSPENDED(no register access)\n",
-- hcd->self.controller->bus->name,
-- dev_name(hcd->self.controller),
-- hcd->product_desc);
-- goto done;
-- }
--
-- /* Capability Registers */
-- i = HC_VERSION(fotg210, fotg210_readl(fotg210,
-- &fotg210->caps->hc_capbase));
-- temp = scnprintf(next, size,
-- "bus %s, device %s\n"
-- "%s\n"
-- "EHCI %x.%02x, rh state %s\n",
-- hcd->self.controller->bus->name,
-- dev_name(hcd->self.controller),
-- hcd->product_desc,
-- i >> 8, i & 0x0ff, rh_state_string(fotg210));
-- size -= temp;
-- next += temp;
--
-- /* FIXME interpret both types of params */
-- i = fotg210_readl(fotg210, &fotg210->caps->hcs_params);
-- temp = scnprintf(next, size, "structural params 0x%08x\n", i);
-- size -= temp;
-- next += temp;
--
-- i = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
-- temp = scnprintf(next, size, "capability params 0x%08x\n", i);
-- size -= temp;
-- next += temp;
--
-- /* Operational Registers */
-- temp = dbg_status_buf(scratch, sizeof(scratch), label,
-- fotg210_readl(fotg210, &fotg210->regs->status));
-- temp = scnprintf(next, size, fmt, temp, scratch);
-- size -= temp;
-- next += temp;
--
-- temp = dbg_command_buf(scratch, sizeof(scratch), label,
-- fotg210_readl(fotg210, &fotg210->regs->command));
-- temp = scnprintf(next, size, fmt, temp, scratch);
-- size -= temp;
-- next += temp;
--
-- temp = dbg_intr_buf(scratch, sizeof(scratch), label,
-- fotg210_readl(fotg210, &fotg210->regs->intr_enable));
-- temp = scnprintf(next, size, fmt, temp, scratch);
-- size -= temp;
-- next += temp;
--
-- temp = scnprintf(next, size, "uframe %04x\n",
-- fotg210_read_frame_index(fotg210));
-- size -= temp;
-- next += temp;
--
-- if (fotg210->async_unlink) {
-- temp = scnprintf(next, size, "async unlink qh %p\n",
-- fotg210->async_unlink);
-- size -= temp;
-- next += temp;
-- }
--
--#ifdef FOTG210_STATS
-- temp = scnprintf(next, size,
-- "irq normal %ld err %ld iaa %ld(lost %ld)\n",
-- fotg210->stats.normal, fotg210->stats.error,
-- fotg210->stats.iaa, fotg210->stats.lost_iaa);
-- size -= temp;
-- next += temp;
--
-- temp = scnprintf(next, size, "complete %ld unlink %ld\n",
-- fotg210->stats.complete, fotg210->stats.unlink);
-- size -= temp;
-- next += temp;
--#endif
--
--done:
-- spin_unlock_irqrestore(&fotg210->lock, flags);
--
-- return buf->alloc_size - size;
--}
--
--static struct debug_buffer
--*alloc_buffer(struct usb_bus *bus, ssize_t (*fill_func)(struct debug_buffer *))
--{
-- struct debug_buffer *buf;
--
-- buf = kzalloc(sizeof(struct debug_buffer), GFP_KERNEL);
--
-- if (buf) {
-- buf->bus = bus;
-- buf->fill_func = fill_func;
-- mutex_init(&buf->mutex);
-- buf->alloc_size = PAGE_SIZE;
-- }
--
-- return buf;
--}
--
--static int fill_buffer(struct debug_buffer *buf)
--{
-- int ret = 0;
--
-- if (!buf->output_buf)
-- buf->output_buf = vmalloc(buf->alloc_size);
--
-- if (!buf->output_buf) {
-- ret = -ENOMEM;
-- goto out;
-- }
--
-- ret = buf->fill_func(buf);
--
-- if (ret >= 0) {
-- buf->count = ret;
-- ret = 0;
-- }
--
--out:
-- return ret;
--}
--
--static ssize_t debug_output(struct file *file, char __user *user_buf,
-- size_t len, loff_t *offset)
--{
-- struct debug_buffer *buf = file->private_data;
-- int ret = 0;
--
-- mutex_lock(&buf->mutex);
-- if (buf->count == 0) {
-- ret = fill_buffer(buf);
-- if (ret != 0) {
-- mutex_unlock(&buf->mutex);
-- goto out;
-- }
-- }
-- mutex_unlock(&buf->mutex);
--
-- ret = simple_read_from_buffer(user_buf, len, offset,
-- buf->output_buf, buf->count);
--
--out:
-- return ret;
--
--}
--
--static int debug_close(struct inode *inode, struct file *file)
--{
-- struct debug_buffer *buf = file->private_data;
--
-- if (buf) {
-- vfree(buf->output_buf);
-- kfree(buf);
-- }
--
-- return 0;
--}
--static int debug_async_open(struct inode *inode, struct file *file)
--{
-- file->private_data = alloc_buffer(inode->i_private, fill_async_buffer);
--
-- return file->private_data ? 0 : -ENOMEM;
--}
--
--static int debug_periodic_open(struct inode *inode, struct file *file)
--{
-- struct debug_buffer *buf;
--
-- buf = alloc_buffer(inode->i_private, fill_periodic_buffer);
-- if (!buf)
-- return -ENOMEM;
--
-- buf->alloc_size = (sizeof(void *) == 4 ? 6 : 8)*PAGE_SIZE;
-- file->private_data = buf;
-- return 0;
--}
--
--static int debug_registers_open(struct inode *inode, struct file *file)
--{
-- file->private_data = alloc_buffer(inode->i_private,
-- fill_registers_buffer);
--
-- return file->private_data ? 0 : -ENOMEM;
--}
--
--static inline void create_debug_files(struct fotg210_hcd *fotg210)
--{
-- struct usb_bus *bus = &fotg210_to_hcd(fotg210)->self;
-- struct dentry *root;
--
-- root = debugfs_create_dir(bus->bus_name, fotg210_debug_root);
--
-- debugfs_create_file("async", S_IRUGO, root, bus, &debug_async_fops);
-- debugfs_create_file("periodic", S_IRUGO, root, bus,
-- &debug_periodic_fops);
-- debugfs_create_file("registers", S_IRUGO, root, bus,
-- &debug_registers_fops);
--}
--
--static inline void remove_debug_files(struct fotg210_hcd *fotg210)
--{
-- struct usb_bus *bus = &fotg210_to_hcd(fotg210)->self;
--
-- debugfs_lookup_and_remove(bus->bus_name, fotg210_debug_root);
--}
--
--/* handshake - spin reading hc until handshake completes or fails
-- * @ptr: address of hc register to be read
-- * @mask: bits to look at in result of read
-- * @done: value of those bits when handshake succeeds
-- * @usec: timeout in microseconds
-- *
-- * Returns negative errno, or zero on success
-- *
-- * Success happens when the "mask" bits have the specified value (hardware
-- * handshake done). There are two failure modes: "usec" have passed (major
-- * hardware flakeout), or the register reads as all-ones (hardware removed).
-- *
-- * That last failure should_only happen in cases like physical cardbus eject
-- * before driver shutdown. But it also seems to be caused by bugs in cardbus
-- * bridge shutdown: shutting down the bridge before the devices using it.
-- */
--static int handshake(struct fotg210_hcd *fotg210, void __iomem *ptr,
-- u32 mask, u32 done, int usec)
--{
-- u32 result;
-- int ret;
--
-- ret = readl_poll_timeout_atomic(ptr, result,
-- ((result & mask) == done ||
-- result == U32_MAX), 1, usec);
-- if (result == U32_MAX) /* card removed */
-- return -ENODEV;
--
-- return ret;
--}
--
--/* Force HC to halt state from unknown (EHCI spec section 2.3).
-- * Must be called with interrupts enabled and the lock not held.
-- */
--static int fotg210_halt(struct fotg210_hcd *fotg210)
--{
-- u32 temp;
--
-- spin_lock_irq(&fotg210->lock);
--
-- /* disable any irqs left enabled by previous code */
-- fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
--
-- /*
-- * This routine gets called during probe before fotg210->command
-- * has been initialized, so we can't rely on its value.
-- */
-- fotg210->command &= ~CMD_RUN;
-- temp = fotg210_readl(fotg210, &fotg210->regs->command);
-- temp &= ~(CMD_RUN | CMD_IAAD);
-- fotg210_writel(fotg210, temp, &fotg210->regs->command);
--
-- spin_unlock_irq(&fotg210->lock);
-- synchronize_irq(fotg210_to_hcd(fotg210)->irq);
--
-- return handshake(fotg210, &fotg210->regs->status,
-- STS_HALT, STS_HALT, 16 * 125);
--}
--
--/* Reset a non-running (STS_HALT == 1) controller.
-- * Must be called with interrupts enabled and the lock not held.
-- */
--static int fotg210_reset(struct fotg210_hcd *fotg210)
--{
-- int retval;
-- u32 command = fotg210_readl(fotg210, &fotg210->regs->command);
--
-- /* If the EHCI debug controller is active, special care must be
-- * taken before and after a host controller reset
-- */
-- if (fotg210->debug && !dbgp_reset_prep(fotg210_to_hcd(fotg210)))
-- fotg210->debug = NULL;
--
-- command |= CMD_RESET;
-- dbg_cmd(fotg210, "reset", command);
-- fotg210_writel(fotg210, command, &fotg210->regs->command);
-- fotg210->rh_state = FOTG210_RH_HALTED;
-- fotg210->next_statechange = jiffies;
-- retval = handshake(fotg210, &fotg210->regs->command,
-- CMD_RESET, 0, 250 * 1000);
--
-- if (retval)
-- return retval;
--
-- if (fotg210->debug)
-- dbgp_external_startup(fotg210_to_hcd(fotg210));
--
-- fotg210->port_c_suspend = fotg210->suspended_ports =
-- fotg210->resuming_ports = 0;
-- return retval;
--}
--
--/* Idle the controller (turn off the schedules).
-- * Must be called with interrupts enabled and the lock not held.
-- */
--static void fotg210_quiesce(struct fotg210_hcd *fotg210)
--{
-- u32 temp;
--
-- if (fotg210->rh_state != FOTG210_RH_RUNNING)
-- return;
--
-- /* wait for any schedule enables/disables to take effect */
-- temp = (fotg210->command << 10) & (STS_ASS | STS_PSS);
-- handshake(fotg210, &fotg210->regs->status, STS_ASS | STS_PSS, temp,
-- 16 * 125);
--
-- /* then disable anything that's still active */
-- spin_lock_irq(&fotg210->lock);
-- fotg210->command &= ~(CMD_ASE | CMD_PSE);
-- fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-- spin_unlock_irq(&fotg210->lock);
--
-- /* hardware can take 16 microframes to turn off ... */
-- handshake(fotg210, &fotg210->regs->status, STS_ASS | STS_PSS, 0,
-- 16 * 125);
--}
--
--static void end_unlink_async(struct fotg210_hcd *fotg210);
--static void unlink_empty_async(struct fotg210_hcd *fotg210);
--static void fotg210_work(struct fotg210_hcd *fotg210);
--static void start_unlink_intr(struct fotg210_hcd *fotg210,
-- struct fotg210_qh *qh);
--static void end_unlink_intr(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
--
--/* Set a bit in the USBCMD register */
--static void fotg210_set_command_bit(struct fotg210_hcd *fotg210, u32 bit)
--{
-- fotg210->command |= bit;
-- fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
--
-- /* unblock posted write */
-- fotg210_readl(fotg210, &fotg210->regs->command);
--}
--
--/* Clear a bit in the USBCMD register */
--static void fotg210_clear_command_bit(struct fotg210_hcd *fotg210, u32 bit)
--{
-- fotg210->command &= ~bit;
-- fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
--
-- /* unblock posted write */
-- fotg210_readl(fotg210, &fotg210->regs->command);
--}
--
--/* EHCI timer support... Now using hrtimers.
-- *
-- * Lots of different events are triggered from fotg210->hrtimer. Whenever
-- * the timer routine runs, it checks each possible event; events that are
-- * currently enabled and whose expiration time has passed get handled.
-- * The set of enabled events is stored as a collection of bitflags in
-- * fotg210->enabled_hrtimer_events, and they are numbered in order of
-- * increasing delay values (ranging between 1 ms and 100 ms).
-- *
-- * Rather than implementing a sorted list or tree of all pending events,
-- * we keep track only of the lowest-numbered pending event, in
-- * fotg210->next_hrtimer_event. Whenever fotg210->hrtimer gets restarted, its
-- * expiration time is set to the timeout value for this event.
-- *
-- * As a result, events might not get handled right away; the actual delay
-- * could be anywhere up to twice the requested delay. This doesn't
-- * matter, because none of the events are especially time-critical. The
-- * ones that matter most all have a delay of 1 ms, so they will be
-- * handled after 2 ms at most, which is okay. In addition to this, we
-- * allow for an expiration range of 1 ms.
-- */
--
--/* Delay lengths for the hrtimer event types.
-- * Keep this list sorted by delay length, in the same order as
-- * the event types indexed by enum fotg210_hrtimer_event in fotg210.h.
-- */
--static unsigned event_delays_ns[] = {
-- 1 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_POLL_ASS */
-- 1 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_POLL_PSS */
-- 1 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_POLL_DEAD */
-- 1125 * NSEC_PER_USEC, /* FOTG210_HRTIMER_UNLINK_INTR */
-- 2 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_FREE_ITDS */
-- 6 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_ASYNC_UNLINKS */
-- 10 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_IAA_WATCHDOG */
-- 10 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_DISABLE_PERIODIC */
-- 15 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_DISABLE_ASYNC */
-- 100 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_IO_WATCHDOG */
--};
--
--/* Enable a pending hrtimer event */
--static void fotg210_enable_event(struct fotg210_hcd *fotg210, unsigned event,
-- bool resched)
--{
-- ktime_t *timeout = &fotg210->hr_timeouts[event];
--
-- if (resched)
-- *timeout = ktime_add(ktime_get(), event_delays_ns[event]);
-- fotg210->enabled_hrtimer_events |= (1 << event);
--
-- /* Track only the lowest-numbered pending event */
-- if (event < fotg210->next_hrtimer_event) {
-- fotg210->next_hrtimer_event = event;
-- hrtimer_start_range_ns(&fotg210->hrtimer, *timeout,
-- NSEC_PER_MSEC, HRTIMER_MODE_ABS);
-- }
--}
--
--
--/* Poll the STS_ASS status bit; see when it agrees with CMD_ASE */
--static void fotg210_poll_ASS(struct fotg210_hcd *fotg210)
--{
-- unsigned actual, want;
--
-- /* Don't enable anything if the controller isn't running (e.g., died) */
-- if (fotg210->rh_state != FOTG210_RH_RUNNING)
-- return;
--
-- want = (fotg210->command & CMD_ASE) ? STS_ASS : 0;
-- actual = fotg210_readl(fotg210, &fotg210->regs->status) & STS_ASS;
--
-- if (want != actual) {
--
-- /* Poll again later, but give up after about 20 ms */
-- if (fotg210->ASS_poll_count++ < 20) {
-- fotg210_enable_event(fotg210, FOTG210_HRTIMER_POLL_ASS,
-- true);
-- return;
-- }
-- fotg210_dbg(fotg210, "Waited too long for the async schedule status (%x/%x), giving up\n",
-- want, actual);
-- }
-- fotg210->ASS_poll_count = 0;
--
-- /* The status is up-to-date; restart or stop the schedule as needed */
-- if (want == 0) { /* Stopped */
-- if (fotg210->async_count > 0)
-- fotg210_set_command_bit(fotg210, CMD_ASE);
--
-- } else { /* Running */
-- if (fotg210->async_count == 0) {
--
-- /* Turn off the schedule after a while */
-- fotg210_enable_event(fotg210,
-- FOTG210_HRTIMER_DISABLE_ASYNC,
-- true);
-- }
-- }
--}
--
--/* Turn off the async schedule after a brief delay */
--static void fotg210_disable_ASE(struct fotg210_hcd *fotg210)
--{
-- fotg210_clear_command_bit(fotg210, CMD_ASE);
--}
--
--
--/* Poll the STS_PSS status bit; see when it agrees with CMD_PSE */
--static void fotg210_poll_PSS(struct fotg210_hcd *fotg210)
--{
-- unsigned actual, want;
--
-- /* Don't do anything if the controller isn't running (e.g., died) */
-- if (fotg210->rh_state != FOTG210_RH_RUNNING)
-- return;
--
-- want = (fotg210->command & CMD_PSE) ? STS_PSS : 0;
-- actual = fotg210_readl(fotg210, &fotg210->regs->status) & STS_PSS;
--
-- if (want != actual) {
--
-- /* Poll again later, but give up after about 20 ms */
-- if (fotg210->PSS_poll_count++ < 20) {
-- fotg210_enable_event(fotg210, FOTG210_HRTIMER_POLL_PSS,
-- true);
-- return;
-- }
-- fotg210_dbg(fotg210, "Waited too long for the periodic schedule status (%x/%x), giving up\n",
-- want, actual);
-- }
-- fotg210->PSS_poll_count = 0;
--
-- /* The status is up-to-date; restart or stop the schedule as needed */
-- if (want == 0) { /* Stopped */
-- if (fotg210->periodic_count > 0)
-- fotg210_set_command_bit(fotg210, CMD_PSE);
--
-- } else { /* Running */
-- if (fotg210->periodic_count == 0) {
--
-- /* Turn off the schedule after a while */
-- fotg210_enable_event(fotg210,
-- FOTG210_HRTIMER_DISABLE_PERIODIC,
-- true);
-- }
-- }
--}
--
--/* Turn off the periodic schedule after a brief delay */
--static void fotg210_disable_PSE(struct fotg210_hcd *fotg210)
--{
-- fotg210_clear_command_bit(fotg210, CMD_PSE);
--}
--
--
--/* Poll the STS_HALT status bit; see when a dead controller stops */
--static void fotg210_handle_controller_death(struct fotg210_hcd *fotg210)
--{
-- if (!(fotg210_readl(fotg210, &fotg210->regs->status) & STS_HALT)) {
--
-- /* Give up after a few milliseconds */
-- if (fotg210->died_poll_count++ < 5) {
-- /* Try again later */
-- fotg210_enable_event(fotg210,
-- FOTG210_HRTIMER_POLL_DEAD, true);
-- return;
-- }
-- fotg210_warn(fotg210, "Waited too long for the controller to stop, giving up\n");
-- }
--
-- /* Clean up the mess */
-- fotg210->rh_state = FOTG210_RH_HALTED;
-- fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
-- fotg210_work(fotg210);
-- end_unlink_async(fotg210);
--
-- /* Not in process context, so don't try to reset the controller */
--}
--
--
--/* Handle unlinked interrupt QHs once they are gone from the hardware */
--static void fotg210_handle_intr_unlinks(struct fotg210_hcd *fotg210)
--{
-- bool stopped = (fotg210->rh_state < FOTG210_RH_RUNNING);
--
-- /*
-- * Process all the QHs on the intr_unlink list that were added
-- * before the current unlink cycle began. The list is in
-- * temporal order, so stop when we reach the first entry in the
-- * current cycle. But if the root hub isn't running then
-- * process all the QHs on the list.
-- */
-- fotg210->intr_unlinking = true;
-- while (fotg210->intr_unlink) {
-- struct fotg210_qh *qh = fotg210->intr_unlink;
--
-- if (!stopped && qh->unlink_cycle == fotg210->intr_unlink_cycle)
-- break;
-- fotg210->intr_unlink = qh->unlink_next;
-- qh->unlink_next = NULL;
-- end_unlink_intr(fotg210, qh);
-- }
--
-- /* Handle remaining entries later */
-- if (fotg210->intr_unlink) {
-- fotg210_enable_event(fotg210, FOTG210_HRTIMER_UNLINK_INTR,
-- true);
-- ++fotg210->intr_unlink_cycle;
-- }
-- fotg210->intr_unlinking = false;
--}
--
--
--/* Start another free-iTDs/siTDs cycle */
--static void start_free_itds(struct fotg210_hcd *fotg210)
--{
-- if (!(fotg210->enabled_hrtimer_events &
-- BIT(FOTG210_HRTIMER_FREE_ITDS))) {
-- fotg210->last_itd_to_free = list_entry(
-- fotg210->cached_itd_list.prev,
-- struct fotg210_itd, itd_list);
-- fotg210_enable_event(fotg210, FOTG210_HRTIMER_FREE_ITDS, true);
-- }
--}
--
--/* Wait for controller to stop using old iTDs and siTDs */
--static void end_free_itds(struct fotg210_hcd *fotg210)
--{
-- struct fotg210_itd *itd, *n;
--
-- if (fotg210->rh_state < FOTG210_RH_RUNNING)
-- fotg210->last_itd_to_free = NULL;
--
-- list_for_each_entry_safe(itd, n, &fotg210->cached_itd_list, itd_list) {
-- list_del(&itd->itd_list);
-- dma_pool_free(fotg210->itd_pool, itd, itd->itd_dma);
-- if (itd == fotg210->last_itd_to_free)
-- break;
-- }
--
-- if (!list_empty(&fotg210->cached_itd_list))
-- start_free_itds(fotg210);
--}
--
--
--/* Handle lost (or very late) IAA interrupts */
--static void fotg210_iaa_watchdog(struct fotg210_hcd *fotg210)
--{
-- if (fotg210->rh_state != FOTG210_RH_RUNNING)
-- return;
--
-- /*
-- * Lost IAA irqs wedge things badly; seen first with a vt8235.
-- * So we need this watchdog, but must protect it against both
-- * (a) SMP races against real IAA firing and retriggering, and
-- * (b) clean HC shutdown, when IAA watchdog was pending.
-- */
-- if (fotg210->async_iaa) {
-- u32 cmd, status;
--
-- /* If we get here, IAA is *REALLY* late. It's barely
-- * conceivable that the system is so busy that CMD_IAAD
-- * is still legitimately set, so let's be sure it's
-- * clear before we read STS_IAA. (The HC should clear
-- * CMD_IAAD when it sets STS_IAA.)
-- */
-- cmd = fotg210_readl(fotg210, &fotg210->regs->command);
--
-- /*
-- * If IAA is set here it either legitimately triggered
-- * after the watchdog timer expired (_way_ late, so we'll
-- * still count it as lost) ... or a silicon erratum:
-- * - VIA seems to set IAA without triggering the IRQ;
-- * - IAAD potentially cleared without setting IAA.
-- */
-- status = fotg210_readl(fotg210, &fotg210->regs->status);
-- if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
-- INCR(fotg210->stats.lost_iaa);
-- fotg210_writel(fotg210, STS_IAA,
-- &fotg210->regs->status);
-- }
--
-- fotg210_dbg(fotg210, "IAA watchdog: status %x cmd %x\n",
-- status, cmd);
-- end_unlink_async(fotg210);
-- }
--}
--
--
--/* Enable the I/O watchdog, if appropriate */
--static void turn_on_io_watchdog(struct fotg210_hcd *fotg210)
--{
-- /* Not needed if the controller isn't running or it's already enabled */
-- if (fotg210->rh_state != FOTG210_RH_RUNNING ||
-- (fotg210->enabled_hrtimer_events &
-- BIT(FOTG210_HRTIMER_IO_WATCHDOG)))
-- return;
--
-- /*
-- * Isochronous transfers always need the watchdog.
-- * For other sorts we use it only if the flag is set.
-- */
-- if (fotg210->isoc_count > 0 || (fotg210->need_io_watchdog &&
-- fotg210->async_count + fotg210->intr_count > 0))
-- fotg210_enable_event(fotg210, FOTG210_HRTIMER_IO_WATCHDOG,
-- true);
--}
--
--
--/* Handler functions for the hrtimer event types.
-- * Keep this array in the same order as the event types indexed by
-- * enum fotg210_hrtimer_event in fotg210.h.
-- */
--static void (*event_handlers[])(struct fotg210_hcd *) = {
-- fotg210_poll_ASS, /* FOTG210_HRTIMER_POLL_ASS */
-- fotg210_poll_PSS, /* FOTG210_HRTIMER_POLL_PSS */
-- fotg210_handle_controller_death, /* FOTG210_HRTIMER_POLL_DEAD */
-- fotg210_handle_intr_unlinks, /* FOTG210_HRTIMER_UNLINK_INTR */
-- end_free_itds, /* FOTG210_HRTIMER_FREE_ITDS */
-- unlink_empty_async, /* FOTG210_HRTIMER_ASYNC_UNLINKS */
-- fotg210_iaa_watchdog, /* FOTG210_HRTIMER_IAA_WATCHDOG */
-- fotg210_disable_PSE, /* FOTG210_HRTIMER_DISABLE_PERIODIC */
-- fotg210_disable_ASE, /* FOTG210_HRTIMER_DISABLE_ASYNC */
-- fotg210_work, /* FOTG210_HRTIMER_IO_WATCHDOG */
--};
--
--static enum hrtimer_restart fotg210_hrtimer_func(struct hrtimer *t)
--{
-- struct fotg210_hcd *fotg210 =
-- container_of(t, struct fotg210_hcd, hrtimer);
-- ktime_t now;
-- unsigned long events;
-- unsigned long flags;
-- unsigned e;
--
-- spin_lock_irqsave(&fotg210->lock, flags);
--
-- events = fotg210->enabled_hrtimer_events;
-- fotg210->enabled_hrtimer_events = 0;
-- fotg210->next_hrtimer_event = FOTG210_HRTIMER_NO_EVENT;
--
-- /*
-- * Check each pending event. If its time has expired, handle
-- * the event; otherwise re-enable it.
-- */
-- now = ktime_get();
-- for_each_set_bit(e, &events, FOTG210_HRTIMER_NUM_EVENTS) {
-- if (ktime_compare(now, fotg210->hr_timeouts[e]) >= 0)
-- event_handlers[e](fotg210);
-- else
-- fotg210_enable_event(fotg210, e, false);
-- }
--
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- return HRTIMER_NORESTART;
--}
--
--#define fotg210_bus_suspend NULL
--#define fotg210_bus_resume NULL
--
--static int check_reset_complete(struct fotg210_hcd *fotg210, int index,
-- u32 __iomem *status_reg, int port_status)
--{
-- if (!(port_status & PORT_CONNECT))
-- return port_status;
--
-- /* if reset finished and it's still not enabled -- handoff */
-- if (!(port_status & PORT_PE))
-- /* with integrated TT, there's nobody to hand it to! */
-- fotg210_dbg(fotg210, "Failed to enable port %d on root hub TT\n",
-- index + 1);
-- else
-- fotg210_dbg(fotg210, "port %d reset complete, port enabled\n",
-- index + 1);
--
-- return port_status;
--}
--
--
--/* build "status change" packet (one or two bytes) from HC registers */
--
--static int fotg210_hub_status_data(struct usb_hcd *hcd, char *buf)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-- u32 temp, status;
-- u32 mask;
-- int retval = 1;
-- unsigned long flags;
--
-- /* init status to no-changes */
-- buf[0] = 0;
--
-- /* Inform the core about resumes-in-progress by returning
-- * a non-zero value even if there are no status changes.
-- */
-- status = fotg210->resuming_ports;
--
-- mask = PORT_CSC | PORT_PEC;
-- /* PORT_RESUME from hardware ~= PORT_STAT_C_SUSPEND */
--
-- /* no hub change reports (bit 0) for now (power, ...) */
--
-- /* port N changes (bit N)? */
-- spin_lock_irqsave(&fotg210->lock, flags);
--
-- temp = fotg210_readl(fotg210, &fotg210->regs->port_status);
--
-- /*
-- * Return status information even for ports with OWNER set.
-- * Otherwise hub_wq wouldn't see the disconnect event when a
-- * high-speed device is switched over to the companion
-- * controller by the user.
-- */
--
-- if ((temp & mask) != 0 || test_bit(0, &fotg210->port_c_suspend) ||
-- (fotg210->reset_done[0] &&
-- time_after_eq(jiffies, fotg210->reset_done[0]))) {
-- buf[0] |= 1 << 1;
-- status = STS_PCD;
-- }
-- /* FIXME autosuspend idle root hubs */
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- return status ? retval : 0;
--}
--
--static void fotg210_hub_descriptor(struct fotg210_hcd *fotg210,
-- struct usb_hub_descriptor *desc)
--{
-- int ports = HCS_N_PORTS(fotg210->hcs_params);
-- u16 temp;
--
-- desc->bDescriptorType = USB_DT_HUB;
-- desc->bPwrOn2PwrGood = 10; /* fotg210 1.0, 2.3.9 says 20ms max */
-- desc->bHubContrCurrent = 0;
--
-- desc->bNbrPorts = ports;
-- temp = 1 + (ports / 8);
-- desc->bDescLength = 7 + 2 * temp;
--
-- /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
-- memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
-- memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
--
-- temp = HUB_CHAR_INDV_PORT_OCPM; /* per-port overcurrent reporting */
-- temp |= HUB_CHAR_NO_LPSM; /* no power switching */
-- desc->wHubCharacteristics = cpu_to_le16(temp);
--}
--
--static int fotg210_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
-- u16 wIndex, char *buf, u16 wLength)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-- int ports = HCS_N_PORTS(fotg210->hcs_params);
-- u32 __iomem *status_reg = &fotg210->regs->port_status;
-- u32 temp, temp1, status;
-- unsigned long flags;
-- int retval = 0;
-- unsigned selector;
--
-- /*
-- * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
-- * HCS_INDICATOR may say we can change LEDs to off/amber/green.
-- * (track current state ourselves) ... blink for diagnostics,
-- * power, "this is the one", etc. EHCI spec supports this.
-- */
--
-- spin_lock_irqsave(&fotg210->lock, flags);
-- switch (typeReq) {
-- case ClearHubFeature:
-- switch (wValue) {
-- case C_HUB_LOCAL_POWER:
-- case C_HUB_OVER_CURRENT:
-- /* no hub-wide feature/status flags */
-- break;
-- default:
-- goto error;
-- }
-- break;
-- case ClearPortFeature:
-- if (!wIndex || wIndex > ports)
-- goto error;
-- wIndex--;
-- temp = fotg210_readl(fotg210, status_reg);
-- temp &= ~PORT_RWC_BITS;
--
-- /*
-- * Even if OWNER is set, so the port is owned by the
-- * companion controller, hub_wq needs to be able to clear
-- * the port-change status bits (especially
-- * USB_PORT_STAT_C_CONNECTION).
-- */
--
-- switch (wValue) {
-- case USB_PORT_FEAT_ENABLE:
-- fotg210_writel(fotg210, temp & ~PORT_PE, status_reg);
-- break;
-- case USB_PORT_FEAT_C_ENABLE:
-- fotg210_writel(fotg210, temp | PORT_PEC, status_reg);
-- break;
-- case USB_PORT_FEAT_SUSPEND:
-- if (temp & PORT_RESET)
-- goto error;
-- if (!(temp & PORT_SUSPEND))
-- break;
-- if ((temp & PORT_PE) == 0)
-- goto error;
--
-- /* resume signaling for 20 msec */
-- fotg210_writel(fotg210, temp | PORT_RESUME, status_reg);
-- fotg210->reset_done[wIndex] = jiffies
-- + msecs_to_jiffies(USB_RESUME_TIMEOUT);
-- break;
-- case USB_PORT_FEAT_C_SUSPEND:
-- clear_bit(wIndex, &fotg210->port_c_suspend);
-- break;
-- case USB_PORT_FEAT_C_CONNECTION:
-- fotg210_writel(fotg210, temp | PORT_CSC, status_reg);
-- break;
-- case USB_PORT_FEAT_C_OVER_CURRENT:
-- fotg210_writel(fotg210, temp | OTGISR_OVC,
-- &fotg210->regs->otgisr);
-- break;
-- case USB_PORT_FEAT_C_RESET:
-- /* GetPortStatus clears reset */
-- break;
-- default:
-- goto error;
-- }
-- fotg210_readl(fotg210, &fotg210->regs->command);
-- break;
-- case GetHubDescriptor:
-- fotg210_hub_descriptor(fotg210, (struct usb_hub_descriptor *)
-- buf);
-- break;
-- case GetHubStatus:
-- /* no hub-wide feature/status flags */
-- memset(buf, 0, 4);
-- /*cpu_to_le32s ((u32 *) buf); */
-- break;
-- case GetPortStatus:
-- if (!wIndex || wIndex > ports)
-- goto error;
-- wIndex--;
-- status = 0;
-- temp = fotg210_readl(fotg210, status_reg);
--
-- /* wPortChange bits */
-- if (temp & PORT_CSC)
-- status |= USB_PORT_STAT_C_CONNECTION << 16;
-- if (temp & PORT_PEC)
-- status |= USB_PORT_STAT_C_ENABLE << 16;
--
-- temp1 = fotg210_readl(fotg210, &fotg210->regs->otgisr);
-- if (temp1 & OTGISR_OVC)
-- status |= USB_PORT_STAT_C_OVERCURRENT << 16;
--
-- /* whoever resumes must GetPortStatus to complete it!! */
-- if (temp & PORT_RESUME) {
--
-- /* Remote Wakeup received? */
-- if (!fotg210->reset_done[wIndex]) {
-- /* resume signaling for 20 msec */
-- fotg210->reset_done[wIndex] = jiffies
-- + msecs_to_jiffies(20);
-- /* check the port again */
-- mod_timer(&fotg210_to_hcd(fotg210)->rh_timer,
-- fotg210->reset_done[wIndex]);
-- }
--
-- /* resume completed? */
-- else if (time_after_eq(jiffies,
-- fotg210->reset_done[wIndex])) {
-- clear_bit(wIndex, &fotg210->suspended_ports);
-- set_bit(wIndex, &fotg210->port_c_suspend);
-- fotg210->reset_done[wIndex] = 0;
--
-- /* stop resume signaling */
-- temp = fotg210_readl(fotg210, status_reg);
-- fotg210_writel(fotg210, temp &
-- ~(PORT_RWC_BITS | PORT_RESUME),
-- status_reg);
-- clear_bit(wIndex, &fotg210->resuming_ports);
-- retval = handshake(fotg210, status_reg,
-- PORT_RESUME, 0, 2000);/* 2ms */
-- if (retval != 0) {
-- fotg210_err(fotg210,
-- "port %d resume error %d\n",
-- wIndex + 1, retval);
-- goto error;
-- }
-- temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
-- }
-- }
--
-- /* whoever resets must GetPortStatus to complete it!! */
-- if ((temp & PORT_RESET) && time_after_eq(jiffies,
-- fotg210->reset_done[wIndex])) {
-- status |= USB_PORT_STAT_C_RESET << 16;
-- fotg210->reset_done[wIndex] = 0;
-- clear_bit(wIndex, &fotg210->resuming_ports);
--
-- /* force reset to complete */
-- fotg210_writel(fotg210,
-- temp & ~(PORT_RWC_BITS | PORT_RESET),
-- status_reg);
-- /* REVISIT: some hardware needs 550+ usec to clear
-- * this bit; seems too long to spin routinely...
-- */
-- retval = handshake(fotg210, status_reg,
-- PORT_RESET, 0, 1000);
-- if (retval != 0) {
-- fotg210_err(fotg210, "port %d reset error %d\n",
-- wIndex + 1, retval);
-- goto error;
-- }
--
-- /* see what we found out */
-- temp = check_reset_complete(fotg210, wIndex, status_reg,
-- fotg210_readl(fotg210, status_reg));
--
-- /* restart schedule */
-- fotg210->command |= CMD_RUN;
-- fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-- }
--
-- if (!(temp & (PORT_RESUME|PORT_RESET))) {
-- fotg210->reset_done[wIndex] = 0;
-- clear_bit(wIndex, &fotg210->resuming_ports);
-- }
--
-- /* transfer dedicated ports to the companion hc */
-- if ((temp & PORT_CONNECT) &&
-- test_bit(wIndex, &fotg210->companion_ports)) {
-- temp &= ~PORT_RWC_BITS;
-- fotg210_writel(fotg210, temp, status_reg);
-- fotg210_dbg(fotg210, "port %d --> companion\n",
-- wIndex + 1);
-- temp = fotg210_readl(fotg210, status_reg);
-- }
--
-- /*
-- * Even if OWNER is set, there's no harm letting hub_wq
-- * see the wPortStatus values (they should all be 0 except
-- * for PORT_POWER anyway).
-- */
--
-- if (temp & PORT_CONNECT) {
-- status |= USB_PORT_STAT_CONNECTION;
-- status |= fotg210_port_speed(fotg210, temp);
-- }
-- if (temp & PORT_PE)
-- status |= USB_PORT_STAT_ENABLE;
--
-- /* maybe the port was unsuspended without our knowledge */
-- if (temp & (PORT_SUSPEND|PORT_RESUME)) {
-- status |= USB_PORT_STAT_SUSPEND;
-- } else if (test_bit(wIndex, &fotg210->suspended_ports)) {
-- clear_bit(wIndex, &fotg210->suspended_ports);
-- clear_bit(wIndex, &fotg210->resuming_ports);
-- fotg210->reset_done[wIndex] = 0;
-- if (temp & PORT_PE)
-- set_bit(wIndex, &fotg210->port_c_suspend);
-- }
--
-- temp1 = fotg210_readl(fotg210, &fotg210->regs->otgisr);
-- if (temp1 & OTGISR_OVC)
-- status |= USB_PORT_STAT_OVERCURRENT;
-- if (temp & PORT_RESET)
-- status |= USB_PORT_STAT_RESET;
-- if (test_bit(wIndex, &fotg210->port_c_suspend))
-- status |= USB_PORT_STAT_C_SUSPEND << 16;
--
-- if (status & ~0xffff) /* only if wPortChange is interesting */
-- dbg_port(fotg210, "GetStatus", wIndex + 1, temp);
-- put_unaligned_le32(status, buf);
-- break;
-- case SetHubFeature:
-- switch (wValue) {
-- case C_HUB_LOCAL_POWER:
-- case C_HUB_OVER_CURRENT:
-- /* no hub-wide feature/status flags */
-- break;
-- default:
-- goto error;
-- }
-- break;
-- case SetPortFeature:
-- selector = wIndex >> 8;
-- wIndex &= 0xff;
--
-- if (!wIndex || wIndex > ports)
-- goto error;
-- wIndex--;
-- temp = fotg210_readl(fotg210, status_reg);
-- temp &= ~PORT_RWC_BITS;
-- switch (wValue) {
-- case USB_PORT_FEAT_SUSPEND:
-- if ((temp & PORT_PE) == 0
-- || (temp & PORT_RESET) != 0)
-- goto error;
--
-- /* After above check the port must be connected.
-- * Set appropriate bit thus could put phy into low power
-- * mode if we have hostpc feature
-- */
-- fotg210_writel(fotg210, temp | PORT_SUSPEND,
-- status_reg);
-- set_bit(wIndex, &fotg210->suspended_ports);
-- break;
-- case USB_PORT_FEAT_RESET:
-- if (temp & PORT_RESUME)
-- goto error;
-- /* line status bits may report this as low speed,
-- * which can be fine if this root hub has a
-- * transaction translator built in.
-- */
-- fotg210_dbg(fotg210, "port %d reset\n", wIndex + 1);
-- temp |= PORT_RESET;
-- temp &= ~PORT_PE;
--
-- /*
-- * caller must wait, then call GetPortStatus
-- * usb 2.0 spec says 50 ms resets on root
-- */
-- fotg210->reset_done[wIndex] = jiffies
-- + msecs_to_jiffies(50);
-- fotg210_writel(fotg210, temp, status_reg);
-- break;
--
-- /* For downstream facing ports (these): one hub port is put
-- * into test mode according to USB2 11.24.2.13, then the hub
-- * must be reset (which for root hub now means rmmod+modprobe,
-- * or else system reboot). See EHCI 2.3.9 and 4.14 for info
-- * about the EHCI-specific stuff.
-- */
-- case USB_PORT_FEAT_TEST:
-- if (!selector || selector > 5)
-- goto error;
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- fotg210_quiesce(fotg210);
-- spin_lock_irqsave(&fotg210->lock, flags);
--
-- /* Put all enabled ports into suspend */
-- temp = fotg210_readl(fotg210, status_reg) &
-- ~PORT_RWC_BITS;
-- if (temp & PORT_PE)
-- fotg210_writel(fotg210, temp | PORT_SUSPEND,
-- status_reg);
--
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- fotg210_halt(fotg210);
-- spin_lock_irqsave(&fotg210->lock, flags);
--
-- temp = fotg210_readl(fotg210, status_reg);
-- temp |= selector << 16;
-- fotg210_writel(fotg210, temp, status_reg);
-- break;
--
-- default:
-- goto error;
-- }
-- fotg210_readl(fotg210, &fotg210->regs->command);
-- break;
--
-- default:
--error:
-- /* "stall" on error */
-- retval = -EPIPE;
-- }
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- return retval;
--}
--
--static void __maybe_unused fotg210_relinquish_port(struct usb_hcd *hcd,
-- int portnum)
--{
-- return;
--}
--
--static int __maybe_unused fotg210_port_handed_over(struct usb_hcd *hcd,
-- int portnum)
--{
-- return 0;
--}
--
--/* There's basically three types of memory:
-- * - data used only by the HCD ... kmalloc is fine
-- * - async and periodic schedules, shared by HC and HCD ... these
-- * need to use dma_pool or dma_alloc_coherent
-- * - driver buffers, read/written by HC ... single shot DMA mapped
-- *
-- * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
-- * No memory seen by this driver is pageable.
-- */
--
--/* Allocate the key transfer structures from the previously allocated pool */
--static inline void fotg210_qtd_init(struct fotg210_hcd *fotg210,
-- struct fotg210_qtd *qtd, dma_addr_t dma)
--{
-- memset(qtd, 0, sizeof(*qtd));
-- qtd->qtd_dma = dma;
-- qtd->hw_token = cpu_to_hc32(fotg210, QTD_STS_HALT);
-- qtd->hw_next = FOTG210_LIST_END(fotg210);
-- qtd->hw_alt_next = FOTG210_LIST_END(fotg210);
-- INIT_LIST_HEAD(&qtd->qtd_list);
--}
--
--static struct fotg210_qtd *fotg210_qtd_alloc(struct fotg210_hcd *fotg210,
-- gfp_t flags)
--{
-- struct fotg210_qtd *qtd;
-- dma_addr_t dma;
--
-- qtd = dma_pool_alloc(fotg210->qtd_pool, flags, &dma);
-- if (qtd != NULL)
-- fotg210_qtd_init(fotg210, qtd, dma);
--
-- return qtd;
--}
--
--static inline void fotg210_qtd_free(struct fotg210_hcd *fotg210,
-- struct fotg210_qtd *qtd)
--{
-- dma_pool_free(fotg210->qtd_pool, qtd, qtd->qtd_dma);
--}
--
--
--static void qh_destroy(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
-- /* clean qtds first, and know this is not linked */
-- if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) {
-- fotg210_dbg(fotg210, "unused qh not empty!\n");
-- BUG();
-- }
-- if (qh->dummy)
-- fotg210_qtd_free(fotg210, qh->dummy);
-- dma_pool_free(fotg210->qh_pool, qh->hw, qh->qh_dma);
-- kfree(qh);
--}
--
--static struct fotg210_qh *fotg210_qh_alloc(struct fotg210_hcd *fotg210,
-- gfp_t flags)
--{
-- struct fotg210_qh *qh;
-- dma_addr_t dma;
--
-- qh = kzalloc(sizeof(*qh), GFP_ATOMIC);
-- if (!qh)
-- goto done;
-- qh->hw = (struct fotg210_qh_hw *)
-- dma_pool_zalloc(fotg210->qh_pool, flags, &dma);
-- if (!qh->hw)
-- goto fail;
-- qh->qh_dma = dma;
-- INIT_LIST_HEAD(&qh->qtd_list);
--
-- /* dummy td enables safe urb queuing */
-- qh->dummy = fotg210_qtd_alloc(fotg210, flags);
-- if (qh->dummy == NULL) {
-- fotg210_dbg(fotg210, "no dummy td\n");
-- goto fail1;
-- }
--done:
-- return qh;
--fail1:
-- dma_pool_free(fotg210->qh_pool, qh->hw, qh->qh_dma);
--fail:
-- kfree(qh);
-- return NULL;
--}
--
--/* The queue heads and transfer descriptors are managed from pools tied
-- * to each of the "per device" structures.
-- * This is the initialisation and cleanup code.
-- */
--
--static void fotg210_mem_cleanup(struct fotg210_hcd *fotg210)
--{
-- if (fotg210->async)
-- qh_destroy(fotg210, fotg210->async);
-- fotg210->async = NULL;
--
-- if (fotg210->dummy)
-- qh_destroy(fotg210, fotg210->dummy);
-- fotg210->dummy = NULL;
--
-- /* DMA consistent memory and pools */
-- dma_pool_destroy(fotg210->qtd_pool);
-- fotg210->qtd_pool = NULL;
--
-- dma_pool_destroy(fotg210->qh_pool);
-- fotg210->qh_pool = NULL;
--
-- dma_pool_destroy(fotg210->itd_pool);
-- fotg210->itd_pool = NULL;
--
-- if (fotg210->periodic)
-- dma_free_coherent(fotg210_to_hcd(fotg210)->self.controller,
-- fotg210->periodic_size * sizeof(u32),
-- fotg210->periodic, fotg210->periodic_dma);
-- fotg210->periodic = NULL;
--
-- /* shadow periodic table */
-- kfree(fotg210->pshadow);
-- fotg210->pshadow = NULL;
--}
--
--/* remember to add cleanup code (above) if you add anything here */
--static int fotg210_mem_init(struct fotg210_hcd *fotg210, gfp_t flags)
--{
-- int i;
--
-- /* QTDs for control/bulk/intr transfers */
-- fotg210->qtd_pool = dma_pool_create("fotg210_qtd",
-- fotg210_to_hcd(fotg210)->self.controller,
-- sizeof(struct fotg210_qtd),
-- 32 /* byte alignment (for hw parts) */,
-- 4096 /* can't cross 4K */);
-- if (!fotg210->qtd_pool)
-- goto fail;
--
-- /* QHs for control/bulk/intr transfers */
-- fotg210->qh_pool = dma_pool_create("fotg210_qh",
-- fotg210_to_hcd(fotg210)->self.controller,
-- sizeof(struct fotg210_qh_hw),
-- 32 /* byte alignment (for hw parts) */,
-- 4096 /* can't cross 4K */);
-- if (!fotg210->qh_pool)
-- goto fail;
--
-- fotg210->async = fotg210_qh_alloc(fotg210, flags);
-- if (!fotg210->async)
-- goto fail;
--
-- /* ITD for high speed ISO transfers */
-- fotg210->itd_pool = dma_pool_create("fotg210_itd",
-- fotg210_to_hcd(fotg210)->self.controller,
-- sizeof(struct fotg210_itd),
-- 64 /* byte alignment (for hw parts) */,
-- 4096 /* can't cross 4K */);
-- if (!fotg210->itd_pool)
-- goto fail;
--
-- /* Hardware periodic table */
-- fotg210->periodic =
-- dma_alloc_coherent(fotg210_to_hcd(fotg210)->self.controller,
-- fotg210->periodic_size * sizeof(__le32),
-- &fotg210->periodic_dma, 0);
-- if (fotg210->periodic == NULL)
-- goto fail;
--
-- for (i = 0; i < fotg210->periodic_size; i++)
-- fotg210->periodic[i] = FOTG210_LIST_END(fotg210);
--
-- /* software shadow of hardware table */
-- fotg210->pshadow = kcalloc(fotg210->periodic_size, sizeof(void *),
-- flags);
-- if (fotg210->pshadow != NULL)
-- return 0;
--
--fail:
-- fotg210_dbg(fotg210, "couldn't init memory\n");
-- fotg210_mem_cleanup(fotg210);
-- return -ENOMEM;
--}
--/* EHCI hardware queue manipulation ... the core. QH/QTD manipulation.
-- *
-- * Control, bulk, and interrupt traffic all use "qh" lists. They list "qtd"
-- * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned
-- * buffers needed for the larger number). We use one QH per endpoint, queue
-- * multiple urbs (all three types) per endpoint. URBs may need several qtds.
-- *
-- * ISO traffic uses "ISO TD" (itd) records, and (along with
-- * interrupts) needs careful scheduling. Performance improvements can be
-- * an ongoing challenge. That's in "ehci-sched.c".
-- *
-- * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs,
-- * or otherwise through transaction translators (TTs) in USB 2.0 hubs using
-- * (b) special fields in qh entries or (c) split iso entries. TTs will
-- * buffer low/full speed data so the host collects it at high speed.
-- */
--
--/* fill a qtd, returning how much of the buffer we were able to queue up */
--static int qtd_fill(struct fotg210_hcd *fotg210, struct fotg210_qtd *qtd,
-- dma_addr_t buf, size_t len, int token, int maxpacket)
--{
-- int i, count;
-- u64 addr = buf;
--
-- /* one buffer entry per 4K ... first might be short or unaligned */
-- qtd->hw_buf[0] = cpu_to_hc32(fotg210, (u32)addr);
-- qtd->hw_buf_hi[0] = cpu_to_hc32(fotg210, (u32)(addr >> 32));
-- count = 0x1000 - (buf & 0x0fff); /* rest of that page */
-- if (likely(len < count)) /* ... iff needed */
-- count = len;
-- else {
-- buf += 0x1000;
-- buf &= ~0x0fff;
--
-- /* per-qtd limit: from 16K to 20K (best alignment) */
-- for (i = 1; count < len && i < 5; i++) {
-- addr = buf;
-- qtd->hw_buf[i] = cpu_to_hc32(fotg210, (u32)addr);
-- qtd->hw_buf_hi[i] = cpu_to_hc32(fotg210,
-- (u32)(addr >> 32));
-- buf += 0x1000;
-- if ((count + 0x1000) < len)
-- count += 0x1000;
-- else
-- count = len;
-- }
--
-- /* short packets may only terminate transfers */
-- if (count != len)
-- count -= (count % maxpacket);
-- }
-- qtd->hw_token = cpu_to_hc32(fotg210, (count << 16) | token);
-- qtd->length = count;
--
-- return count;
--}
--
--static inline void qh_update(struct fotg210_hcd *fotg210,
-- struct fotg210_qh *qh, struct fotg210_qtd *qtd)
--{
-- struct fotg210_qh_hw *hw = qh->hw;
--
-- /* writes to an active overlay are unsafe */
-- BUG_ON(qh->qh_state != QH_STATE_IDLE);
--
-- hw->hw_qtd_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-- hw->hw_alt_next = FOTG210_LIST_END(fotg210);
--
-- /* Except for control endpoints, we make hardware maintain data
-- * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
-- * and set the pseudo-toggle in udev. Only usb_clear_halt() will
-- * ever clear it.
-- */
-- if (!(hw->hw_info1 & cpu_to_hc32(fotg210, QH_TOGGLE_CTL))) {
-- unsigned is_out, epnum;
--
-- is_out = qh->is_out;
-- epnum = (hc32_to_cpup(fotg210, &hw->hw_info1) >> 8) & 0x0f;
-- if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) {
-- hw->hw_token &= ~cpu_to_hc32(fotg210, QTD_TOGGLE);
-- usb_settoggle(qh->dev, epnum, is_out, 1);
-- }
-- }
--
-- hw->hw_token &= cpu_to_hc32(fotg210, QTD_TOGGLE | QTD_STS_PING);
--}
--
--/* if it weren't for a common silicon quirk (writing the dummy into the qh
-- * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
-- * recovery (including urb dequeue) would need software changes to a QH...
-- */
--static void qh_refresh(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
-- struct fotg210_qtd *qtd;
--
-- if (list_empty(&qh->qtd_list))
-- qtd = qh->dummy;
-- else {
-- qtd = list_entry(qh->qtd_list.next,
-- struct fotg210_qtd, qtd_list);
-- /*
-- * first qtd may already be partially processed.
-- * If we come here during unlink, the QH overlay region
-- * might have reference to the just unlinked qtd. The
-- * qtd is updated in qh_completions(). Update the QH
-- * overlay here.
-- */
-- if (cpu_to_hc32(fotg210, qtd->qtd_dma) == qh->hw->hw_current) {
-- qh->hw->hw_qtd_next = qtd->hw_next;
-- qtd = NULL;
-- }
-- }
--
-- if (qtd)
-- qh_update(fotg210, qh, qtd);
--}
--
--static void qh_link_async(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
--
--static void fotg210_clear_tt_buffer_complete(struct usb_hcd *hcd,
-- struct usb_host_endpoint *ep)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-- struct fotg210_qh *qh = ep->hcpriv;
-- unsigned long flags;
--
-- spin_lock_irqsave(&fotg210->lock, flags);
-- qh->clearing_tt = 0;
-- if (qh->qh_state == QH_STATE_IDLE && !list_empty(&qh->qtd_list)
-- && fotg210->rh_state == FOTG210_RH_RUNNING)
-- qh_link_async(fotg210, qh);
-- spin_unlock_irqrestore(&fotg210->lock, flags);
--}
--
--static void fotg210_clear_tt_buffer(struct fotg210_hcd *fotg210,
-- struct fotg210_qh *qh, struct urb *urb, u32 token)
--{
--
-- /* If an async split transaction gets an error or is unlinked,
-- * the TT buffer may be left in an indeterminate state. We
-- * have to clear the TT buffer.
-- *
-- * Note: this routine is never called for Isochronous transfers.
-- */
-- if (urb->dev->tt && !usb_pipeint(urb->pipe) && !qh->clearing_tt) {
-- struct usb_device *tt = urb->dev->tt->hub;
--
-- dev_dbg(&tt->dev,
-- "clear tt buffer port %d, a%d ep%d t%08x\n",
-- urb->dev->ttport, urb->dev->devnum,
-- usb_pipeendpoint(urb->pipe), token);
--
-- if (urb->dev->tt->hub !=
-- fotg210_to_hcd(fotg210)->self.root_hub) {
-- if (usb_hub_clear_tt_buffer(urb) == 0)
-- qh->clearing_tt = 1;
-- }
-- }
--}
--
--static int qtd_copy_status(struct fotg210_hcd *fotg210, struct urb *urb,
-- size_t length, u32 token)
--{
-- int status = -EINPROGRESS;
--
-- /* count IN/OUT bytes, not SETUP (even short packets) */
-- if (likely(QTD_PID(token) != 2))
-- urb->actual_length += length - QTD_LENGTH(token);
--
-- /* don't modify error codes */
-- if (unlikely(urb->unlinked))
-- return status;
--
-- /* force cleanup after short read; not always an error */
-- if (unlikely(IS_SHORT_READ(token)))
-- status = -EREMOTEIO;
--
-- /* serious "can't proceed" faults reported by the hardware */
-- if (token & QTD_STS_HALT) {
-- if (token & QTD_STS_BABBLE) {
-- /* FIXME "must" disable babbling device's port too */
-- status = -EOVERFLOW;
-- /* CERR nonzero + halt --> stall */
-- } else if (QTD_CERR(token)) {
-- status = -EPIPE;
--
-- /* In theory, more than one of the following bits can be set
-- * since they are sticky and the transaction is retried.
-- * Which to test first is rather arbitrary.
-- */
-- } else if (token & QTD_STS_MMF) {
-- /* fs/ls interrupt xfer missed the complete-split */
-- status = -EPROTO;
-- } else if (token & QTD_STS_DBE) {
-- status = (QTD_PID(token) == 1) /* IN ? */
-- ? -ENOSR /* hc couldn't read data */
-- : -ECOMM; /* hc couldn't write data */
-- } else if (token & QTD_STS_XACT) {
-- /* timeout, bad CRC, wrong PID, etc */
-- fotg210_dbg(fotg210, "devpath %s ep%d%s 3strikes\n",
-- urb->dev->devpath,
-- usb_pipeendpoint(urb->pipe),
-- usb_pipein(urb->pipe) ? "in" : "out");
-- status = -EPROTO;
-- } else { /* unknown */
-- status = -EPROTO;
-- }
--
-- fotg210_dbg(fotg210,
-- "dev%d ep%d%s qtd token %08x --> status %d\n",
-- usb_pipedevice(urb->pipe),
-- usb_pipeendpoint(urb->pipe),
-- usb_pipein(urb->pipe) ? "in" : "out",
-- token, status);
-- }
--
-- return status;
--}
--
--static void fotg210_urb_done(struct fotg210_hcd *fotg210, struct urb *urb,
-- int status)
--__releases(fotg210->lock)
--__acquires(fotg210->lock)
--{
-- if (likely(urb->hcpriv != NULL)) {
-- struct fotg210_qh *qh = (struct fotg210_qh *) urb->hcpriv;
--
-- /* S-mask in a QH means it's an interrupt urb */
-- if ((qh->hw->hw_info2 & cpu_to_hc32(fotg210, QH_SMASK)) != 0) {
--
-- /* ... update hc-wide periodic stats (for usbfs) */
-- fotg210_to_hcd(fotg210)->self.bandwidth_int_reqs--;
-- }
-- }
--
-- if (unlikely(urb->unlinked)) {
-- INCR(fotg210->stats.unlink);
-- } else {
-- /* report non-error and short read status as zero */
-- if (status == -EINPROGRESS || status == -EREMOTEIO)
-- status = 0;
-- INCR(fotg210->stats.complete);
-- }
--
--#ifdef FOTG210_URB_TRACE
-- fotg210_dbg(fotg210,
-- "%s %s urb %p ep%d%s status %d len %d/%d\n",
-- __func__, urb->dev->devpath, urb,
-- usb_pipeendpoint(urb->pipe),
-- usb_pipein(urb->pipe) ? "in" : "out",
-- status,
-- urb->actual_length, urb->transfer_buffer_length);
--#endif
--
-- /* complete() can reenter this HCD */
-- usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
-- spin_unlock(&fotg210->lock);
-- usb_hcd_giveback_urb(fotg210_to_hcd(fotg210), urb, status);
-- spin_lock(&fotg210->lock);
--}
--
--static int qh_schedule(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
--
--/* Process and free completed qtds for a qh, returning URBs to drivers.
-- * Chases up to qh->hw_current. Returns number of completions called,
-- * indicating how much "real" work we did.
-- */
--static unsigned qh_completions(struct fotg210_hcd *fotg210,
-- struct fotg210_qh *qh)
--{
-- struct fotg210_qtd *last, *end = qh->dummy;
-- struct fotg210_qtd *qtd, *tmp;
-- int last_status;
-- int stopped;
-- unsigned count = 0;
-- u8 state;
-- struct fotg210_qh_hw *hw = qh->hw;
--
-- if (unlikely(list_empty(&qh->qtd_list)))
-- return count;
--
-- /* completions (or tasks on other cpus) must never clobber HALT
-- * till we've gone through and cleaned everything up, even when
-- * they add urbs to this qh's queue or mark them for unlinking.
-- *
-- * NOTE: unlinking expects to be done in queue order.
-- *
-- * It's a bug for qh->qh_state to be anything other than
-- * QH_STATE_IDLE, unless our caller is scan_async() or
-- * scan_intr().
-- */
-- state = qh->qh_state;
-- qh->qh_state = QH_STATE_COMPLETING;
-- stopped = (state == QH_STATE_IDLE);
--
--rescan:
-- last = NULL;
-- last_status = -EINPROGRESS;
-- qh->needs_rescan = 0;
--
-- /* remove de-activated QTDs from front of queue.
-- * after faults (including short reads), cleanup this urb
-- * then let the queue advance.
-- * if queue is stopped, handles unlinks.
-- */
-- list_for_each_entry_safe(qtd, tmp, &qh->qtd_list, qtd_list) {
-- struct urb *urb;
-- u32 token = 0;
--
-- urb = qtd->urb;
--
-- /* clean up any state from previous QTD ...*/
-- if (last) {
-- if (likely(last->urb != urb)) {
-- fotg210_urb_done(fotg210, last->urb,
-- last_status);
-- count++;
-- last_status = -EINPROGRESS;
-- }
-- fotg210_qtd_free(fotg210, last);
-- last = NULL;
-- }
--
-- /* ignore urbs submitted during completions we reported */
-- if (qtd == end)
-- break;
--
-- /* hardware copies qtd out of qh overlay */
-- rmb();
-- token = hc32_to_cpu(fotg210, qtd->hw_token);
--
-- /* always clean up qtds the hc de-activated */
--retry_xacterr:
-- if ((token & QTD_STS_ACTIVE) == 0) {
--
-- /* Report Data Buffer Error: non-fatal but useful */
-- if (token & QTD_STS_DBE)
-- fotg210_dbg(fotg210,
-- "detected DataBufferErr for urb %p ep%d%s len %d, qtd %p [qh %p]\n",
-- urb, usb_endpoint_num(&urb->ep->desc),
-- usb_endpoint_dir_in(&urb->ep->desc)
-- ? "in" : "out",
-- urb->transfer_buffer_length, qtd, qh);
--
-- /* on STALL, error, and short reads this urb must
-- * complete and all its qtds must be recycled.
-- */
-- if ((token & QTD_STS_HALT) != 0) {
--
-- /* retry transaction errors until we
-- * reach the software xacterr limit
-- */
-- if ((token & QTD_STS_XACT) &&
-- QTD_CERR(token) == 0 &&
-- ++qh->xacterrs < QH_XACTERR_MAX &&
-- !urb->unlinked) {
-- fotg210_dbg(fotg210,
-- "detected XactErr len %zu/%zu retry %d\n",
-- qtd->length - QTD_LENGTH(token),
-- qtd->length,
-- qh->xacterrs);
--
-- /* reset the token in the qtd and the
-- * qh overlay (which still contains
-- * the qtd) so that we pick up from
-- * where we left off
-- */
-- token &= ~QTD_STS_HALT;
-- token |= QTD_STS_ACTIVE |
-- (FOTG210_TUNE_CERR << 10);
-- qtd->hw_token = cpu_to_hc32(fotg210,
-- token);
-- wmb();
-- hw->hw_token = cpu_to_hc32(fotg210,
-- token);
-- goto retry_xacterr;
-- }
-- stopped = 1;
--
-- /* magic dummy for some short reads; qh won't advance.
-- * that silicon quirk can kick in with this dummy too.
-- *
-- * other short reads won't stop the queue, including
-- * control transfers (status stage handles that) or
-- * most other single-qtd reads ... the queue stops if
-- * URB_SHORT_NOT_OK was set so the driver submitting
-- * the urbs could clean it up.
-- */
-- } else if (IS_SHORT_READ(token) &&
-- !(qtd->hw_alt_next &
-- FOTG210_LIST_END(fotg210))) {
-- stopped = 1;
-- }
--
-- /* stop scanning when we reach qtds the hc is using */
-- } else if (likely(!stopped
-- && fotg210->rh_state >= FOTG210_RH_RUNNING)) {
-- break;
--
-- /* scan the whole queue for unlinks whenever it stops */
-- } else {
-- stopped = 1;
--
-- /* cancel everything if we halt, suspend, etc */
-- if (fotg210->rh_state < FOTG210_RH_RUNNING)
-- last_status = -ESHUTDOWN;
--
-- /* this qtd is active; skip it unless a previous qtd
-- * for its urb faulted, or its urb was canceled.
-- */
-- else if (last_status == -EINPROGRESS && !urb->unlinked)
-- continue;
--
-- /* qh unlinked; token in overlay may be most current */
-- if (state == QH_STATE_IDLE &&
-- cpu_to_hc32(fotg210, qtd->qtd_dma)
-- == hw->hw_current) {
-- token = hc32_to_cpu(fotg210, hw->hw_token);
--
-- /* An unlink may leave an incomplete
-- * async transaction in the TT buffer.
-- * We have to clear it.
-- */
-- fotg210_clear_tt_buffer(fotg210, qh, urb,
-- token);
-- }
-- }
--
-- /* unless we already know the urb's status, collect qtd status
-- * and update count of bytes transferred. in common short read
-- * cases with only one data qtd (including control transfers),
-- * queue processing won't halt. but with two or more qtds (for
-- * example, with a 32 KB transfer), when the first qtd gets a
-- * short read the second must be removed by hand.
-- */
-- if (last_status == -EINPROGRESS) {
-- last_status = qtd_copy_status(fotg210, urb,
-- qtd->length, token);
-- if (last_status == -EREMOTEIO &&
-- (qtd->hw_alt_next &
-- FOTG210_LIST_END(fotg210)))
-- last_status = -EINPROGRESS;
--
-- /* As part of low/full-speed endpoint-halt processing
-- * we must clear the TT buffer (11.17.5).
-- */
-- if (unlikely(last_status != -EINPROGRESS &&
-- last_status != -EREMOTEIO)) {
-- /* The TT's in some hubs malfunction when they
-- * receive this request following a STALL (they
-- * stop sending isochronous packets). Since a
-- * STALL can't leave the TT buffer in a busy
-- * state (if you believe Figures 11-48 - 11-51
-- * in the USB 2.0 spec), we won't clear the TT
-- * buffer in this case. Strictly speaking this
-- * is a violation of the spec.
-- */
-- if (last_status != -EPIPE)
-- fotg210_clear_tt_buffer(fotg210, qh,
-- urb, token);
-- }
-- }
--
-- /* if we're removing something not at the queue head,
-- * patch the hardware queue pointer.
-- */
-- if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
-- last = list_entry(qtd->qtd_list.prev,
-- struct fotg210_qtd, qtd_list);
-- last->hw_next = qtd->hw_next;
-- }
--
-- /* remove qtd; it's recycled after possible urb completion */
-- list_del(&qtd->qtd_list);
-- last = qtd;
--
-- /* reinit the xacterr counter for the next qtd */
-- qh->xacterrs = 0;
-- }
--
-- /* last urb's completion might still need calling */
-- if (likely(last != NULL)) {
-- fotg210_urb_done(fotg210, last->urb, last_status);
-- count++;
-- fotg210_qtd_free(fotg210, last);
-- }
--
-- /* Do we need to rescan for URBs dequeued during a giveback? */
-- if (unlikely(qh->needs_rescan)) {
-- /* If the QH is already unlinked, do the rescan now. */
-- if (state == QH_STATE_IDLE)
-- goto rescan;
--
-- /* Otherwise we have to wait until the QH is fully unlinked.
-- * Our caller will start an unlink if qh->needs_rescan is
-- * set. But if an unlink has already started, nothing needs
-- * to be done.
-- */
-- if (state != QH_STATE_LINKED)
-- qh->needs_rescan = 0;
-- }
--
-- /* restore original state; caller must unlink or relink */
-- qh->qh_state = state;
--
-- /* be sure the hardware's done with the qh before refreshing
-- * it after fault cleanup, or recovering from silicon wrongly
-- * overlaying the dummy qtd (which reduces DMA chatter).
-- */
-- if (stopped != 0 || hw->hw_qtd_next == FOTG210_LIST_END(fotg210)) {
-- switch (state) {
-- case QH_STATE_IDLE:
-- qh_refresh(fotg210, qh);
-- break;
-- case QH_STATE_LINKED:
-- /* We won't refresh a QH that's linked (after the HC
-- * stopped the queue). That avoids a race:
-- * - HC reads first part of QH;
-- * - CPU updates that first part and the token;
-- * - HC reads rest of that QH, including token
-- * Result: HC gets an inconsistent image, and then
-- * DMAs to/from the wrong memory (corrupting it).
-- *
-- * That should be rare for interrupt transfers,
-- * except maybe high bandwidth ...
-- */
--
-- /* Tell the caller to start an unlink */
-- qh->needs_rescan = 1;
-- break;
-- /* otherwise, unlink already started */
-- }
-- }
--
-- return count;
--}
--
--/* reverse of qh_urb_transaction: free a list of TDs.
-- * used for cleanup after errors, before HC sees an URB's TDs.
-- */
--static void qtd_list_free(struct fotg210_hcd *fotg210, struct urb *urb,
-- struct list_head *head)
--{
-- struct fotg210_qtd *qtd, *temp;
--
-- list_for_each_entry_safe(qtd, temp, head, qtd_list) {
-- list_del(&qtd->qtd_list);
-- fotg210_qtd_free(fotg210, qtd);
-- }
--}
--
--/* create a list of filled qtds for this URB; won't link into qh.
-- */
--static struct list_head *qh_urb_transaction(struct fotg210_hcd *fotg210,
-- struct urb *urb, struct list_head *head, gfp_t flags)
--{
-- struct fotg210_qtd *qtd, *qtd_prev;
-- dma_addr_t buf;
-- int len, this_sg_len, maxpacket;
-- int is_input;
-- u32 token;
-- int i;
-- struct scatterlist *sg;
--
-- /*
-- * URBs map to sequences of QTDs: one logical transaction
-- */
-- qtd = fotg210_qtd_alloc(fotg210, flags);
-- if (unlikely(!qtd))
-- return NULL;
-- list_add_tail(&qtd->qtd_list, head);
-- qtd->urb = urb;
--
-- token = QTD_STS_ACTIVE;
-- token |= (FOTG210_TUNE_CERR << 10);
-- /* for split transactions, SplitXState initialized to zero */
--
-- len = urb->transfer_buffer_length;
-- is_input = usb_pipein(urb->pipe);
-- if (usb_pipecontrol(urb->pipe)) {
-- /* SETUP pid */
-- qtd_fill(fotg210, qtd, urb->setup_dma,
-- sizeof(struct usb_ctrlrequest),
-- token | (2 /* "setup" */ << 8), 8);
--
-- /* ... and always at least one more pid */
-- token ^= QTD_TOGGLE;
-- qtd_prev = qtd;
-- qtd = fotg210_qtd_alloc(fotg210, flags);
-- if (unlikely(!qtd))
-- goto cleanup;
-- qtd->urb = urb;
-- qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-- list_add_tail(&qtd->qtd_list, head);
--
-- /* for zero length DATA stages, STATUS is always IN */
-- if (len == 0)
-- token |= (1 /* "in" */ << 8);
-- }
--
-- /*
-- * data transfer stage: buffer setup
-- */
-- i = urb->num_mapped_sgs;
-- if (len > 0 && i > 0) {
-- sg = urb->sg;
-- buf = sg_dma_address(sg);
--
-- /* urb->transfer_buffer_length may be smaller than the
-- * size of the scatterlist (or vice versa)
-- */
-- this_sg_len = min_t(int, sg_dma_len(sg), len);
-- } else {
-- sg = NULL;
-- buf = urb->transfer_dma;
-- this_sg_len = len;
-- }
--
-- if (is_input)
-- token |= (1 /* "in" */ << 8);
-- /* else it's already initted to "out" pid (0 << 8) */
--
-- maxpacket = usb_maxpacket(urb->dev, urb->pipe);
--
-- /*
-- * buffer gets wrapped in one or more qtds;
-- * last one may be "short" (including zero len)
-- * and may serve as a control status ack
-- */
-- for (;;) {
-- int this_qtd_len;
--
-- this_qtd_len = qtd_fill(fotg210, qtd, buf, this_sg_len, token,
-- maxpacket);
-- this_sg_len -= this_qtd_len;
-- len -= this_qtd_len;
-- buf += this_qtd_len;
--
-- /*
-- * short reads advance to a "magic" dummy instead of the next
-- * qtd ... that forces the queue to stop, for manual cleanup.
-- * (this will usually be overridden later.)
-- */
-- if (is_input)
-- qtd->hw_alt_next = fotg210->async->hw->hw_alt_next;
--
-- /* qh makes control packets use qtd toggle; maybe switch it */
-- if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
-- token ^= QTD_TOGGLE;
--
-- if (likely(this_sg_len <= 0)) {
-- if (--i <= 0 || len <= 0)
-- break;
-- sg = sg_next(sg);
-- buf = sg_dma_address(sg);
-- this_sg_len = min_t(int, sg_dma_len(sg), len);
-- }
--
-- qtd_prev = qtd;
-- qtd = fotg210_qtd_alloc(fotg210, flags);
-- if (unlikely(!qtd))
-- goto cleanup;
-- qtd->urb = urb;
-- qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-- list_add_tail(&qtd->qtd_list, head);
-- }
--
-- /*
-- * unless the caller requires manual cleanup after short reads,
-- * have the alt_next mechanism keep the queue running after the
-- * last data qtd (the only one, for control and most other cases).
-- */
-- if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0 ||
-- usb_pipecontrol(urb->pipe)))
-- qtd->hw_alt_next = FOTG210_LIST_END(fotg210);
--
-- /*
-- * control requests may need a terminating data "status" ack;
-- * other OUT ones may need a terminating short packet
-- * (zero length).
-- */
-- if (likely(urb->transfer_buffer_length != 0)) {
-- int one_more = 0;
--
-- if (usb_pipecontrol(urb->pipe)) {
-- one_more = 1;
-- token ^= 0x0100; /* "in" <--> "out" */
-- token |= QTD_TOGGLE; /* force DATA1 */
-- } else if (usb_pipeout(urb->pipe)
-- && (urb->transfer_flags & URB_ZERO_PACKET)
-- && !(urb->transfer_buffer_length % maxpacket)) {
-- one_more = 1;
-- }
-- if (one_more) {
-- qtd_prev = qtd;
-- qtd = fotg210_qtd_alloc(fotg210, flags);
-- if (unlikely(!qtd))
-- goto cleanup;
-- qtd->urb = urb;
-- qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-- list_add_tail(&qtd->qtd_list, head);
--
-- /* never any data in such packets */
-- qtd_fill(fotg210, qtd, 0, 0, token, 0);
-- }
-- }
--
-- /* by default, enable interrupt on urb completion */
-- if (likely(!(urb->transfer_flags & URB_NO_INTERRUPT)))
-- qtd->hw_token |= cpu_to_hc32(fotg210, QTD_IOC);
-- return head;
--
--cleanup:
-- qtd_list_free(fotg210, urb, head);
-- return NULL;
--}
--
--/* Would be best to create all qh's from config descriptors,
-- * when each interface/altsetting is established. Unlink
-- * any previous qh and cancel its urbs first; endpoints are
-- * implicitly reset then (data toggle too).
-- * That'd mean updating how usbcore talks to HCDs. (2.7?)
-- */
--
--
--/* Each QH holds a qtd list; a QH is used for everything except iso.
-- *
-- * For interrupt urbs, the scheduler must set the microframe scheduling
-- * mask(s) each time the QH gets scheduled. For highspeed, that's
-- * just one microframe in the s-mask. For split interrupt transactions
-- * there are additional complications: c-mask, maybe FSTNs.
-- */
--static struct fotg210_qh *qh_make(struct fotg210_hcd *fotg210, struct urb *urb,
-- gfp_t flags)
--{
-- struct fotg210_qh *qh = fotg210_qh_alloc(fotg210, flags);
-- struct usb_host_endpoint *ep;
-- u32 info1 = 0, info2 = 0;
-- int is_input, type;
-- int maxp = 0;
-- int mult;
-- struct usb_tt *tt = urb->dev->tt;
-- struct fotg210_qh_hw *hw;
--
-- if (!qh)
-- return qh;
--
-- /*
-- * init endpoint/device data for this QH
-- */
-- info1 |= usb_pipeendpoint(urb->pipe) << 8;
-- info1 |= usb_pipedevice(urb->pipe) << 0;
--
-- is_input = usb_pipein(urb->pipe);
-- type = usb_pipetype(urb->pipe);
-- ep = usb_pipe_endpoint(urb->dev, urb->pipe);
-- maxp = usb_endpoint_maxp(&ep->desc);
-- mult = usb_endpoint_maxp_mult(&ep->desc);
--
-- /* 1024 byte maxpacket is a hardware ceiling. High bandwidth
-- * acts like up to 3KB, but is built from smaller packets.
-- */
-- if (maxp > 1024) {
-- fotg210_dbg(fotg210, "bogus qh maxpacket %d\n", maxp);
-- goto done;
-- }
--
-- /* Compute interrupt scheduling parameters just once, and save.
-- * - allowing for high bandwidth, how many nsec/uframe are used?
-- * - split transactions need a second CSPLIT uframe; same question
-- * - splits also need a schedule gap (for full/low speed I/O)
-- * - qh has a polling interval
-- *
-- * For control/bulk requests, the HC or TT handles these.
-- */
-- if (type == PIPE_INTERRUPT) {
-- qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH,
-- is_input, 0, mult * maxp));
-- qh->start = NO_FRAME;
--
-- if (urb->dev->speed == USB_SPEED_HIGH) {
-- qh->c_usecs = 0;
-- qh->gap_uf = 0;
--
-- qh->period = urb->interval >> 3;
-- if (qh->period == 0 && urb->interval != 1) {
-- /* NOTE interval 2 or 4 uframes could work.
-- * But interval 1 scheduling is simpler, and
-- * includes high bandwidth.
-- */
-- urb->interval = 1;
-- } else if (qh->period > fotg210->periodic_size) {
-- qh->period = fotg210->periodic_size;
-- urb->interval = qh->period << 3;
-- }
-- } else {
-- int think_time;
--
-- /* gap is f(FS/LS transfer times) */
-- qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed,
-- is_input, 0, maxp) / (125 * 1000);
--
-- /* FIXME this just approximates SPLIT/CSPLIT times */
-- if (is_input) { /* SPLIT, gap, CSPLIT+DATA */
-- qh->c_usecs = qh->usecs + HS_USECS(0);
-- qh->usecs = HS_USECS(1);
-- } else { /* SPLIT+DATA, gap, CSPLIT */
-- qh->usecs += HS_USECS(1);
-- qh->c_usecs = HS_USECS(0);
-- }
--
-- think_time = tt ? tt->think_time : 0;
-- qh->tt_usecs = NS_TO_US(think_time +
-- usb_calc_bus_time(urb->dev->speed,
-- is_input, 0, maxp));
-- qh->period = urb->interval;
-- if (qh->period > fotg210->periodic_size) {
-- qh->period = fotg210->periodic_size;
-- urb->interval = qh->period;
-- }
-- }
-- }
--
-- /* support for tt scheduling, and access to toggles */
-- qh->dev = urb->dev;
--
-- /* using TT? */
-- switch (urb->dev->speed) {
-- case USB_SPEED_LOW:
-- info1 |= QH_LOW_SPEED;
-- fallthrough;
--
-- case USB_SPEED_FULL:
-- /* EPS 0 means "full" */
-- if (type != PIPE_INTERRUPT)
-- info1 |= (FOTG210_TUNE_RL_TT << 28);
-- if (type == PIPE_CONTROL) {
-- info1 |= QH_CONTROL_EP; /* for TT */
-- info1 |= QH_TOGGLE_CTL; /* toggle from qtd */
-- }
-- info1 |= maxp << 16;
--
-- info2 |= (FOTG210_TUNE_MULT_TT << 30);
--
-- /* Some Freescale processors have an erratum in which the
-- * port number in the queue head was 0..N-1 instead of 1..N.
-- */
-- if (fotg210_has_fsl_portno_bug(fotg210))
-- info2 |= (urb->dev->ttport-1) << 23;
-- else
-- info2 |= urb->dev->ttport << 23;
--
-- /* set the address of the TT; for TDI's integrated
-- * root hub tt, leave it zeroed.
-- */
-- if (tt && tt->hub != fotg210_to_hcd(fotg210)->self.root_hub)
-- info2 |= tt->hub->devnum << 16;
--
-- /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */
--
-- break;
--
-- case USB_SPEED_HIGH: /* no TT involved */
-- info1 |= QH_HIGH_SPEED;
-- if (type == PIPE_CONTROL) {
-- info1 |= (FOTG210_TUNE_RL_HS << 28);
-- info1 |= 64 << 16; /* usb2 fixed maxpacket */
-- info1 |= QH_TOGGLE_CTL; /* toggle from qtd */
-- info2 |= (FOTG210_TUNE_MULT_HS << 30);
-- } else if (type == PIPE_BULK) {
-- info1 |= (FOTG210_TUNE_RL_HS << 28);
-- /* The USB spec says that high speed bulk endpoints
-- * always use 512 byte maxpacket. But some device
-- * vendors decided to ignore that, and MSFT is happy
-- * to help them do so. So now people expect to use
-- * such nonconformant devices with Linux too; sigh.
-- */
-- info1 |= maxp << 16;
-- info2 |= (FOTG210_TUNE_MULT_HS << 30);
-- } else { /* PIPE_INTERRUPT */
-- info1 |= maxp << 16;
-- info2 |= mult << 30;
-- }
-- break;
-- default:
-- fotg210_dbg(fotg210, "bogus dev %p speed %d\n", urb->dev,
-- urb->dev->speed);
--done:
-- qh_destroy(fotg210, qh);
-- return NULL;
-- }
--
-- /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */
--
-- /* init as live, toggle clear, advance to dummy */
-- qh->qh_state = QH_STATE_IDLE;
-- hw = qh->hw;
-- hw->hw_info1 = cpu_to_hc32(fotg210, info1);
-- hw->hw_info2 = cpu_to_hc32(fotg210, info2);
-- qh->is_out = !is_input;
-- usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1);
-- qh_refresh(fotg210, qh);
-- return qh;
--}
--
--static void enable_async(struct fotg210_hcd *fotg210)
--{
-- if (fotg210->async_count++)
-- return;
--
-- /* Stop waiting to turn off the async schedule */
-- fotg210->enabled_hrtimer_events &= ~BIT(FOTG210_HRTIMER_DISABLE_ASYNC);
--
-- /* Don't start the schedule until ASS is 0 */
-- fotg210_poll_ASS(fotg210);
-- turn_on_io_watchdog(fotg210);
--}
--
--static void disable_async(struct fotg210_hcd *fotg210)
--{
-- if (--fotg210->async_count)
-- return;
--
-- /* The async schedule and async_unlink list are supposed to be empty */
-- WARN_ON(fotg210->async->qh_next.qh || fotg210->async_unlink);
--
-- /* Don't turn off the schedule until ASS is 1 */
-- fotg210_poll_ASS(fotg210);
--}
--
--/* move qh (and its qtds) onto async queue; maybe enable queue. */
--
--static void qh_link_async(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
-- __hc32 dma = QH_NEXT(fotg210, qh->qh_dma);
-- struct fotg210_qh *head;
--
-- /* Don't link a QH if there's a Clear-TT-Buffer pending */
-- if (unlikely(qh->clearing_tt))
-- return;
--
-- WARN_ON(qh->qh_state != QH_STATE_IDLE);
--
-- /* clear halt and/or toggle; and maybe recover from silicon quirk */
-- qh_refresh(fotg210, qh);
--
-- /* splice right after start */
-- head = fotg210->async;
-- qh->qh_next = head->qh_next;
-- qh->hw->hw_next = head->hw->hw_next;
-- wmb();
--
-- head->qh_next.qh = qh;
-- head->hw->hw_next = dma;
--
-- qh->xacterrs = 0;
-- qh->qh_state = QH_STATE_LINKED;
-- /* qtd completions reported later by interrupt */
--
-- enable_async(fotg210);
--}
--
--/* For control/bulk/interrupt, return QH with these TDs appended.
-- * Allocates and initializes the QH if necessary.
-- * Returns null if it can't allocate a QH it needs to.
-- * If the QH has TDs (urbs) already, that's great.
-- */
--static struct fotg210_qh *qh_append_tds(struct fotg210_hcd *fotg210,
-- struct urb *urb, struct list_head *qtd_list,
-- int epnum, void **ptr)
--{
-- struct fotg210_qh *qh = NULL;
-- __hc32 qh_addr_mask = cpu_to_hc32(fotg210, 0x7f);
--
-- qh = (struct fotg210_qh *) *ptr;
-- if (unlikely(qh == NULL)) {
-- /* can't sleep here, we have fotg210->lock... */
-- qh = qh_make(fotg210, urb, GFP_ATOMIC);
-- *ptr = qh;
-- }
-- if (likely(qh != NULL)) {
-- struct fotg210_qtd *qtd;
--
-- if (unlikely(list_empty(qtd_list)))
-- qtd = NULL;
-- else
-- qtd = list_entry(qtd_list->next, struct fotg210_qtd,
-- qtd_list);
--
-- /* control qh may need patching ... */
-- if (unlikely(epnum == 0)) {
-- /* usb_reset_device() briefly reverts to address 0 */
-- if (usb_pipedevice(urb->pipe) == 0)
-- qh->hw->hw_info1 &= ~qh_addr_mask;
-- }
--
-- /* just one way to queue requests: swap with the dummy qtd.
-- * only hc or qh_refresh() ever modify the overlay.
-- */
-- if (likely(qtd != NULL)) {
-- struct fotg210_qtd *dummy;
-- dma_addr_t dma;
-- __hc32 token;
--
-- /* to avoid racing the HC, use the dummy td instead of
-- * the first td of our list (becomes new dummy). both
-- * tds stay deactivated until we're done, when the
-- * HC is allowed to fetch the old dummy (4.10.2).
-- */
-- token = qtd->hw_token;
-- qtd->hw_token = HALT_BIT(fotg210);
--
-- dummy = qh->dummy;
--
-- dma = dummy->qtd_dma;
-- *dummy = *qtd;
-- dummy->qtd_dma = dma;
--
-- list_del(&qtd->qtd_list);
-- list_add(&dummy->qtd_list, qtd_list);
-- list_splice_tail(qtd_list, &qh->qtd_list);
--
-- fotg210_qtd_init(fotg210, qtd, qtd->qtd_dma);
-- qh->dummy = qtd;
--
-- /* hc must see the new dummy at list end */
-- dma = qtd->qtd_dma;
-- qtd = list_entry(qh->qtd_list.prev,
-- struct fotg210_qtd, qtd_list);
-- qtd->hw_next = QTD_NEXT(fotg210, dma);
--
-- /* let the hc process these next qtds */
-- wmb();
-- dummy->hw_token = token;
--
-- urb->hcpriv = qh;
-- }
-- }
-- return qh;
--}
--
--static int submit_async(struct fotg210_hcd *fotg210, struct urb *urb,
-- struct list_head *qtd_list, gfp_t mem_flags)
--{
-- int epnum;
-- unsigned long flags;
-- struct fotg210_qh *qh = NULL;
-- int rc;
--
-- epnum = urb->ep->desc.bEndpointAddress;
--
--#ifdef FOTG210_URB_TRACE
-- {
-- struct fotg210_qtd *qtd;
--
-- qtd = list_entry(qtd_list->next, struct fotg210_qtd, qtd_list);
-- fotg210_dbg(fotg210,
-- "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
-- __func__, urb->dev->devpath, urb,
-- epnum & 0x0f, (epnum & USB_DIR_IN)
-- ? "in" : "out",
-- urb->transfer_buffer_length,
-- qtd, urb->ep->hcpriv);
-- }
--#endif
--
-- spin_lock_irqsave(&fotg210->lock, flags);
-- if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
-- rc = -ESHUTDOWN;
-- goto done;
-- }
-- rc = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
-- if (unlikely(rc))
-- goto done;
--
-- qh = qh_append_tds(fotg210, urb, qtd_list, epnum, &urb->ep->hcpriv);
-- if (unlikely(qh == NULL)) {
-- usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
-- rc = -ENOMEM;
-- goto done;
-- }
--
-- /* Control/bulk operations through TTs don't need scheduling,
-- * the HC and TT handle it when the TT has a buffer ready.
-- */
-- if (likely(qh->qh_state == QH_STATE_IDLE))
-- qh_link_async(fotg210, qh);
--done:
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- if (unlikely(qh == NULL))
-- qtd_list_free(fotg210, urb, qtd_list);
-- return rc;
--}
--
--static void single_unlink_async(struct fotg210_hcd *fotg210,
-- struct fotg210_qh *qh)
--{
-- struct fotg210_qh *prev;
--
-- /* Add to the end of the list of QHs waiting for the next IAAD */
-- qh->qh_state = QH_STATE_UNLINK;
-- if (fotg210->async_unlink)
-- fotg210->async_unlink_last->unlink_next = qh;
-- else
-- fotg210->async_unlink = qh;
-- fotg210->async_unlink_last = qh;
--
-- /* Unlink it from the schedule */
-- prev = fotg210->async;
-- while (prev->qh_next.qh != qh)
-- prev = prev->qh_next.qh;
--
-- prev->hw->hw_next = qh->hw->hw_next;
-- prev->qh_next = qh->qh_next;
-- if (fotg210->qh_scan_next == qh)
-- fotg210->qh_scan_next = qh->qh_next.qh;
--}
--
--static void start_iaa_cycle(struct fotg210_hcd *fotg210, bool nested)
--{
-- /*
-- * Do nothing if an IAA cycle is already running or
-- * if one will be started shortly.
-- */
-- if (fotg210->async_iaa || fotg210->async_unlinking)
-- return;
--
-- /* Do all the waiting QHs at once */
-- fotg210->async_iaa = fotg210->async_unlink;
-- fotg210->async_unlink = NULL;
--
-- /* If the controller isn't running, we don't have to wait for it */
-- if (unlikely(fotg210->rh_state < FOTG210_RH_RUNNING)) {
-- if (!nested) /* Avoid recursion */
-- end_unlink_async(fotg210);
--
-- /* Otherwise start a new IAA cycle */
-- } else if (likely(fotg210->rh_state == FOTG210_RH_RUNNING)) {
-- /* Make sure the unlinks are all visible to the hardware */
-- wmb();
--
-- fotg210_writel(fotg210, fotg210->command | CMD_IAAD,
-- &fotg210->regs->command);
-- fotg210_readl(fotg210, &fotg210->regs->command);
-- fotg210_enable_event(fotg210, FOTG210_HRTIMER_IAA_WATCHDOG,
-- true);
-- }
--}
--
--/* the async qh for the qtds being unlinked are now gone from the HC */
--
--static void end_unlink_async(struct fotg210_hcd *fotg210)
--{
-- struct fotg210_qh *qh;
--
-- /* Process the idle QHs */
--restart:
-- fotg210->async_unlinking = true;
-- while (fotg210->async_iaa) {
-- qh = fotg210->async_iaa;
-- fotg210->async_iaa = qh->unlink_next;
-- qh->unlink_next = NULL;
--
-- qh->qh_state = QH_STATE_IDLE;
-- qh->qh_next.qh = NULL;
--
-- qh_completions(fotg210, qh);
-- if (!list_empty(&qh->qtd_list) &&
-- fotg210->rh_state == FOTG210_RH_RUNNING)
-- qh_link_async(fotg210, qh);
-- disable_async(fotg210);
-- }
-- fotg210->async_unlinking = false;
--
-- /* Start a new IAA cycle if any QHs are waiting for it */
-- if (fotg210->async_unlink) {
-- start_iaa_cycle(fotg210, true);
-- if (unlikely(fotg210->rh_state < FOTG210_RH_RUNNING))
-- goto restart;
-- }
--}
--
--static void unlink_empty_async(struct fotg210_hcd *fotg210)
--{
-- struct fotg210_qh *qh, *next;
-- bool stopped = (fotg210->rh_state < FOTG210_RH_RUNNING);
-- bool check_unlinks_later = false;
--
-- /* Unlink all the async QHs that have been empty for a timer cycle */
-- next = fotg210->async->qh_next.qh;
-- while (next) {
-- qh = next;
-- next = qh->qh_next.qh;
--
-- if (list_empty(&qh->qtd_list) &&
-- qh->qh_state == QH_STATE_LINKED) {
-- if (!stopped && qh->unlink_cycle ==
-- fotg210->async_unlink_cycle)
-- check_unlinks_later = true;
-- else
-- single_unlink_async(fotg210, qh);
-- }
-- }
--
-- /* Start a new IAA cycle if any QHs are waiting for it */
-- if (fotg210->async_unlink)
-- start_iaa_cycle(fotg210, false);
--
-- /* QHs that haven't been empty for long enough will be handled later */
-- if (check_unlinks_later) {
-- fotg210_enable_event(fotg210, FOTG210_HRTIMER_ASYNC_UNLINKS,
-- true);
-- ++fotg210->async_unlink_cycle;
-- }
--}
--
--/* makes sure the async qh will become idle */
--/* caller must own fotg210->lock */
--
--static void start_unlink_async(struct fotg210_hcd *fotg210,
-- struct fotg210_qh *qh)
--{
-- /*
-- * If the QH isn't linked then there's nothing we can do
-- * unless we were called during a giveback, in which case
-- * qh_completions() has to deal with it.
-- */
-- if (qh->qh_state != QH_STATE_LINKED) {
-- if (qh->qh_state == QH_STATE_COMPLETING)
-- qh->needs_rescan = 1;
-- return;
-- }
--
-- single_unlink_async(fotg210, qh);
-- start_iaa_cycle(fotg210, false);
--}
--
--static void scan_async(struct fotg210_hcd *fotg210)
--{
-- struct fotg210_qh *qh;
-- bool check_unlinks_later = false;
--
-- fotg210->qh_scan_next = fotg210->async->qh_next.qh;
-- while (fotg210->qh_scan_next) {
-- qh = fotg210->qh_scan_next;
-- fotg210->qh_scan_next = qh->qh_next.qh;
--rescan:
-- /* clean any finished work for this qh */
-- if (!list_empty(&qh->qtd_list)) {
-- int temp;
--
-- /*
-- * Unlinks could happen here; completion reporting
-- * drops the lock. That's why fotg210->qh_scan_next
-- * always holds the next qh to scan; if the next qh
-- * gets unlinked then fotg210->qh_scan_next is adjusted
-- * in single_unlink_async().
-- */
-- temp = qh_completions(fotg210, qh);
-- if (qh->needs_rescan) {
-- start_unlink_async(fotg210, qh);
-- } else if (list_empty(&qh->qtd_list)
-- && qh->qh_state == QH_STATE_LINKED) {
-- qh->unlink_cycle = fotg210->async_unlink_cycle;
-- check_unlinks_later = true;
-- } else if (temp != 0)
-- goto rescan;
-- }
-- }
--
-- /*
-- * Unlink empty entries, reducing DMA usage as well
-- * as HCD schedule-scanning costs. Delay for any qh
-- * we just scanned, there's a not-unusual case that it
-- * doesn't stay idle for long.
-- */
-- if (check_unlinks_later && fotg210->rh_state == FOTG210_RH_RUNNING &&
-- !(fotg210->enabled_hrtimer_events &
-- BIT(FOTG210_HRTIMER_ASYNC_UNLINKS))) {
-- fotg210_enable_event(fotg210,
-- FOTG210_HRTIMER_ASYNC_UNLINKS, true);
-- ++fotg210->async_unlink_cycle;
-- }
--}
--/* EHCI scheduled transaction support: interrupt, iso, split iso
-- * These are called "periodic" transactions in the EHCI spec.
-- *
-- * Note that for interrupt transfers, the QH/QTD manipulation is shared
-- * with the "asynchronous" transaction support (control/bulk transfers).
-- * The only real difference is in how interrupt transfers are scheduled.
-- *
-- * For ISO, we make an "iso_stream" head to serve the same role as a QH.
-- * It keeps track of every ITD (or SITD) that's linked, and holds enough
-- * pre-calculated schedule data to make appending to the queue be quick.
-- */
--static int fotg210_get_frame(struct usb_hcd *hcd);
--
--/* periodic_next_shadow - return "next" pointer on shadow list
-- * @periodic: host pointer to qh/itd
-- * @tag: hardware tag for type of this record
-- */
--static union fotg210_shadow *periodic_next_shadow(struct fotg210_hcd *fotg210,
-- union fotg210_shadow *periodic, __hc32 tag)
--{
-- switch (hc32_to_cpu(fotg210, tag)) {
-- case Q_TYPE_QH:
-- return &periodic->qh->qh_next;
-- case Q_TYPE_FSTN:
-- return &periodic->fstn->fstn_next;
-- default:
-- return &periodic->itd->itd_next;
-- }
--}
--
--static __hc32 *shadow_next_periodic(struct fotg210_hcd *fotg210,
-- union fotg210_shadow *periodic, __hc32 tag)
--{
-- switch (hc32_to_cpu(fotg210, tag)) {
-- /* our fotg210_shadow.qh is actually software part */
-- case Q_TYPE_QH:
-- return &periodic->qh->hw->hw_next;
-- /* others are hw parts */
-- default:
-- return periodic->hw_next;
-- }
--}
--
--/* caller must hold fotg210->lock */
--static void periodic_unlink(struct fotg210_hcd *fotg210, unsigned frame,
-- void *ptr)
--{
-- union fotg210_shadow *prev_p = &fotg210->pshadow[frame];
-- __hc32 *hw_p = &fotg210->periodic[frame];
-- union fotg210_shadow here = *prev_p;
--
-- /* find predecessor of "ptr"; hw and shadow lists are in sync */
-- while (here.ptr && here.ptr != ptr) {
-- prev_p = periodic_next_shadow(fotg210, prev_p,
-- Q_NEXT_TYPE(fotg210, *hw_p));
-- hw_p = shadow_next_periodic(fotg210, &here,
-- Q_NEXT_TYPE(fotg210, *hw_p));
-- here = *prev_p;
-- }
-- /* an interrupt entry (at list end) could have been shared */
-- if (!here.ptr)
-- return;
--
-- /* update shadow and hardware lists ... the old "next" pointers
-- * from ptr may still be in use, the caller updates them.
-- */
-- *prev_p = *periodic_next_shadow(fotg210, &here,
-- Q_NEXT_TYPE(fotg210, *hw_p));
--
-- *hw_p = *shadow_next_periodic(fotg210, &here,
-- Q_NEXT_TYPE(fotg210, *hw_p));
--}
--
--/* how many of the uframe's 125 usecs are allocated? */
--static unsigned short periodic_usecs(struct fotg210_hcd *fotg210,
-- unsigned frame, unsigned uframe)
--{
-- __hc32 *hw_p = &fotg210->periodic[frame];
-- union fotg210_shadow *q = &fotg210->pshadow[frame];
-- unsigned usecs = 0;
-- struct fotg210_qh_hw *hw;
--
-- while (q->ptr) {
-- switch (hc32_to_cpu(fotg210, Q_NEXT_TYPE(fotg210, *hw_p))) {
-- case Q_TYPE_QH:
-- hw = q->qh->hw;
-- /* is it in the S-mask? */
-- if (hw->hw_info2 & cpu_to_hc32(fotg210, 1 << uframe))
-- usecs += q->qh->usecs;
-- /* ... or C-mask? */
-- if (hw->hw_info2 & cpu_to_hc32(fotg210,
-- 1 << (8 + uframe)))
-- usecs += q->qh->c_usecs;
-- hw_p = &hw->hw_next;
-- q = &q->qh->qh_next;
-- break;
-- /* case Q_TYPE_FSTN: */
-- default:
-- /* for "save place" FSTNs, count the relevant INTR
-- * bandwidth from the previous frame
-- */
-- if (q->fstn->hw_prev != FOTG210_LIST_END(fotg210))
-- fotg210_dbg(fotg210, "ignoring FSTN cost ...\n");
--
-- hw_p = &q->fstn->hw_next;
-- q = &q->fstn->fstn_next;
-- break;
-- case Q_TYPE_ITD:
-- if (q->itd->hw_transaction[uframe])
-- usecs += q->itd->stream->usecs;
-- hw_p = &q->itd->hw_next;
-- q = &q->itd->itd_next;
-- break;
-- }
-- }
-- if (usecs > fotg210->uframe_periodic_max)
-- fotg210_err(fotg210, "uframe %d sched overrun: %d usecs\n",
-- frame * 8 + uframe, usecs);
-- return usecs;
--}
--
--static int same_tt(struct usb_device *dev1, struct usb_device *dev2)
--{
-- if (!dev1->tt || !dev2->tt)
-- return 0;
-- if (dev1->tt != dev2->tt)
-- return 0;
-- if (dev1->tt->multi)
-- return dev1->ttport == dev2->ttport;
-- else
-- return 1;
--}
--
--/* return true iff the device's transaction translator is available
-- * for a periodic transfer starting at the specified frame, using
-- * all the uframes in the mask.
-- */
--static int tt_no_collision(struct fotg210_hcd *fotg210, unsigned period,
-- struct usb_device *dev, unsigned frame, u32 uf_mask)
--{
-- if (period == 0) /* error */
-- return 0;
--
-- /* note bandwidth wastage: split never follows csplit
-- * (different dev or endpoint) until the next uframe.
-- * calling convention doesn't make that distinction.
-- */
-- for (; frame < fotg210->periodic_size; frame += period) {
-- union fotg210_shadow here;
-- __hc32 type;
-- struct fotg210_qh_hw *hw;
--
-- here = fotg210->pshadow[frame];
-- type = Q_NEXT_TYPE(fotg210, fotg210->periodic[frame]);
-- while (here.ptr) {
-- switch (hc32_to_cpu(fotg210, type)) {
-- case Q_TYPE_ITD:
-- type = Q_NEXT_TYPE(fotg210, here.itd->hw_next);
-- here = here.itd->itd_next;
-- continue;
-- case Q_TYPE_QH:
-- hw = here.qh->hw;
-- if (same_tt(dev, here.qh->dev)) {
-- u32 mask;
--
-- mask = hc32_to_cpu(fotg210,
-- hw->hw_info2);
-- /* "knows" no gap is needed */
-- mask |= mask >> 8;
-- if (mask & uf_mask)
-- break;
-- }
-- type = Q_NEXT_TYPE(fotg210, hw->hw_next);
-- here = here.qh->qh_next;
-- continue;
-- /* case Q_TYPE_FSTN: */
-- default:
-- fotg210_dbg(fotg210,
-- "periodic frame %d bogus type %d\n",
-- frame, type);
-- }
--
-- /* collision or error */
-- return 0;
-- }
-- }
--
-- /* no collision */
-- return 1;
--}
--
--static void enable_periodic(struct fotg210_hcd *fotg210)
--{
-- if (fotg210->periodic_count++)
-- return;
--
-- /* Stop waiting to turn off the periodic schedule */
-- fotg210->enabled_hrtimer_events &=
-- ~BIT(FOTG210_HRTIMER_DISABLE_PERIODIC);
--
-- /* Don't start the schedule until PSS is 0 */
-- fotg210_poll_PSS(fotg210);
-- turn_on_io_watchdog(fotg210);
--}
--
--static void disable_periodic(struct fotg210_hcd *fotg210)
--{
-- if (--fotg210->periodic_count)
-- return;
--
-- /* Don't turn off the schedule until PSS is 1 */
-- fotg210_poll_PSS(fotg210);
--}
--
--/* periodic schedule slots have iso tds (normal or split) first, then a
-- * sparse tree for active interrupt transfers.
-- *
-- * this just links in a qh; caller guarantees uframe masks are set right.
-- * no FSTN support (yet; fotg210 0.96+)
-- */
--static void qh_link_periodic(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
-- unsigned i;
-- unsigned period = qh->period;
--
-- dev_dbg(&qh->dev->dev,
-- "link qh%d-%04x/%p start %d [%d/%d us]\n", period,
-- hc32_to_cpup(fotg210, &qh->hw->hw_info2) &
-- (QH_CMASK | QH_SMASK), qh, qh->start, qh->usecs,
-- qh->c_usecs);
--
-- /* high bandwidth, or otherwise every microframe */
-- if (period == 0)
-- period = 1;
--
-- for (i = qh->start; i < fotg210->periodic_size; i += period) {
-- union fotg210_shadow *prev = &fotg210->pshadow[i];
-- __hc32 *hw_p = &fotg210->periodic[i];
-- union fotg210_shadow here = *prev;
-- __hc32 type = 0;
--
-- /* skip the iso nodes at list head */
-- while (here.ptr) {
-- type = Q_NEXT_TYPE(fotg210, *hw_p);
-- if (type == cpu_to_hc32(fotg210, Q_TYPE_QH))
-- break;
-- prev = periodic_next_shadow(fotg210, prev, type);
-- hw_p = shadow_next_periodic(fotg210, &here, type);
-- here = *prev;
-- }
--
-- /* sorting each branch by period (slow-->fast)
-- * enables sharing interior tree nodes
-- */
-- while (here.ptr && qh != here.qh) {
-- if (qh->period > here.qh->period)
-- break;
-- prev = &here.qh->qh_next;
-- hw_p = &here.qh->hw->hw_next;
-- here = *prev;
-- }
-- /* link in this qh, unless some earlier pass did that */
-- if (qh != here.qh) {
-- qh->qh_next = here;
-- if (here.qh)
-- qh->hw->hw_next = *hw_p;
-- wmb();
-- prev->qh = qh;
-- *hw_p = QH_NEXT(fotg210, qh->qh_dma);
-- }
-- }
-- qh->qh_state = QH_STATE_LINKED;
-- qh->xacterrs = 0;
--
-- /* update per-qh bandwidth for usbfs */
-- fotg210_to_hcd(fotg210)->self.bandwidth_allocated += qh->period
-- ? ((qh->usecs + qh->c_usecs) / qh->period)
-- : (qh->usecs * 8);
--
-- list_add(&qh->intr_node, &fotg210->intr_qh_list);
--
-- /* maybe enable periodic schedule processing */
-- ++fotg210->intr_count;
-- enable_periodic(fotg210);
--}
--
--static void qh_unlink_periodic(struct fotg210_hcd *fotg210,
-- struct fotg210_qh *qh)
--{
-- unsigned i;
-- unsigned period;
--
-- /*
-- * If qh is for a low/full-speed device, simply unlinking it
-- * could interfere with an ongoing split transaction. To unlink
-- * it safely would require setting the QH_INACTIVATE bit and
-- * waiting at least one frame, as described in EHCI 4.12.2.5.
-- *
-- * We won't bother with any of this. Instead, we assume that the
-- * only reason for unlinking an interrupt QH while the current URB
-- * is still active is to dequeue all the URBs (flush the whole
-- * endpoint queue).
-- *
-- * If rebalancing the periodic schedule is ever implemented, this
-- * approach will no longer be valid.
-- */
--
-- /* high bandwidth, or otherwise part of every microframe */
-- period = qh->period;
-- if (!period)
-- period = 1;
--
-- for (i = qh->start; i < fotg210->periodic_size; i += period)
-- periodic_unlink(fotg210, i, qh);
--
-- /* update per-qh bandwidth for usbfs */
-- fotg210_to_hcd(fotg210)->self.bandwidth_allocated -= qh->period
-- ? ((qh->usecs + qh->c_usecs) / qh->period)
-- : (qh->usecs * 8);
--
-- dev_dbg(&qh->dev->dev,
-- "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
-- qh->period, hc32_to_cpup(fotg210, &qh->hw->hw_info2) &
-- (QH_CMASK | QH_SMASK), qh, qh->start, qh->usecs,
-- qh->c_usecs);
--
-- /* qh->qh_next still "live" to HC */
-- qh->qh_state = QH_STATE_UNLINK;
-- qh->qh_next.ptr = NULL;
--
-- if (fotg210->qh_scan_next == qh)
-- fotg210->qh_scan_next = list_entry(qh->intr_node.next,
-- struct fotg210_qh, intr_node);
-- list_del(&qh->intr_node);
--}
--
--static void start_unlink_intr(struct fotg210_hcd *fotg210,
-- struct fotg210_qh *qh)
--{
-- /* If the QH isn't linked then there's nothing we can do
-- * unless we were called during a giveback, in which case
-- * qh_completions() has to deal with it.
-- */
-- if (qh->qh_state != QH_STATE_LINKED) {
-- if (qh->qh_state == QH_STATE_COMPLETING)
-- qh->needs_rescan = 1;
-- return;
-- }
--
-- qh_unlink_periodic(fotg210, qh);
--
-- /* Make sure the unlinks are visible before starting the timer */
-- wmb();
--
-- /*
-- * The EHCI spec doesn't say how long it takes the controller to
-- * stop accessing an unlinked interrupt QH. The timer delay is
-- * 9 uframes; presumably that will be long enough.
-- */
-- qh->unlink_cycle = fotg210->intr_unlink_cycle;
--
-- /* New entries go at the end of the intr_unlink list */
-- if (fotg210->intr_unlink)
-- fotg210->intr_unlink_last->unlink_next = qh;
-- else
-- fotg210->intr_unlink = qh;
-- fotg210->intr_unlink_last = qh;
--
-- if (fotg210->intr_unlinking)
-- ; /* Avoid recursive calls */
-- else if (fotg210->rh_state < FOTG210_RH_RUNNING)
-- fotg210_handle_intr_unlinks(fotg210);
-- else if (fotg210->intr_unlink == qh) {
-- fotg210_enable_event(fotg210, FOTG210_HRTIMER_UNLINK_INTR,
-- true);
-- ++fotg210->intr_unlink_cycle;
-- }
--}
--
--static void end_unlink_intr(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
-- struct fotg210_qh_hw *hw = qh->hw;
-- int rc;
--
-- qh->qh_state = QH_STATE_IDLE;
-- hw->hw_next = FOTG210_LIST_END(fotg210);
--
-- qh_completions(fotg210, qh);
--
-- /* reschedule QH iff another request is queued */
-- if (!list_empty(&qh->qtd_list) &&
-- fotg210->rh_state == FOTG210_RH_RUNNING) {
-- rc = qh_schedule(fotg210, qh);
--
-- /* An error here likely indicates handshake failure
-- * or no space left in the schedule. Neither fault
-- * should happen often ...
-- *
-- * FIXME kill the now-dysfunctional queued urbs
-- */
-- if (rc != 0)
-- fotg210_err(fotg210, "can't reschedule qh %p, err %d\n",
-- qh, rc);
-- }
--
-- /* maybe turn off periodic schedule */
-- --fotg210->intr_count;
-- disable_periodic(fotg210);
--}
--
--static int check_period(struct fotg210_hcd *fotg210, unsigned frame,
-- unsigned uframe, unsigned period, unsigned usecs)
--{
-- int claimed;
--
-- /* complete split running into next frame?
-- * given FSTN support, we could sometimes check...
-- */
-- if (uframe >= 8)
-- return 0;
--
-- /* convert "usecs we need" to "max already claimed" */
-- usecs = fotg210->uframe_periodic_max - usecs;
--
-- /* we "know" 2 and 4 uframe intervals were rejected; so
-- * for period 0, check _every_ microframe in the schedule.
-- */
-- if (unlikely(period == 0)) {
-- do {
-- for (uframe = 0; uframe < 7; uframe++) {
-- claimed = periodic_usecs(fotg210, frame,
-- uframe);
-- if (claimed > usecs)
-- return 0;
-- }
-- } while ((frame += 1) < fotg210->periodic_size);
--
-- /* just check the specified uframe, at that period */
-- } else {
-- do {
-- claimed = periodic_usecs(fotg210, frame, uframe);
-- if (claimed > usecs)
-- return 0;
-- } while ((frame += period) < fotg210->periodic_size);
-- }
--
-- /* success! */
-- return 1;
--}
--
--static int check_intr_schedule(struct fotg210_hcd *fotg210, unsigned frame,
-- unsigned uframe, const struct fotg210_qh *qh, __hc32 *c_maskp)
--{
-- int retval = -ENOSPC;
-- u8 mask = 0;
--
-- if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
-- goto done;
--
-- if (!check_period(fotg210, frame, uframe, qh->period, qh->usecs))
-- goto done;
-- if (!qh->c_usecs) {
-- retval = 0;
-- *c_maskp = 0;
-- goto done;
-- }
--
-- /* Make sure this tt's buffer is also available for CSPLITs.
-- * We pessimize a bit; probably the typical full speed case
-- * doesn't need the second CSPLIT.
-- *
-- * NOTE: both SPLIT and CSPLIT could be checked in just
-- * one smart pass...
-- */
-- mask = 0x03 << (uframe + qh->gap_uf);
-- *c_maskp = cpu_to_hc32(fotg210, mask << 8);
--
-- mask |= 1 << uframe;
-- if (tt_no_collision(fotg210, qh->period, qh->dev, frame, mask)) {
-- if (!check_period(fotg210, frame, uframe + qh->gap_uf + 1,
-- qh->period, qh->c_usecs))
-- goto done;
-- if (!check_period(fotg210, frame, uframe + qh->gap_uf,
-- qh->period, qh->c_usecs))
-- goto done;
-- retval = 0;
-- }
--done:
-- return retval;
--}
--
--/* "first fit" scheduling policy used the first time through,
-- * or when the previous schedule slot can't be re-used.
-- */
--static int qh_schedule(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
--{
-- int status;
-- unsigned uframe;
-- __hc32 c_mask;
-- unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
-- struct fotg210_qh_hw *hw = qh->hw;
--
-- qh_refresh(fotg210, qh);
-- hw->hw_next = FOTG210_LIST_END(fotg210);
-- frame = qh->start;
--
-- /* reuse the previous schedule slots, if we can */
-- if (frame < qh->period) {
-- uframe = ffs(hc32_to_cpup(fotg210, &hw->hw_info2) & QH_SMASK);
-- status = check_intr_schedule(fotg210, frame, --uframe,
-- qh, &c_mask);
-- } else {
-- uframe = 0;
-- c_mask = 0;
-- status = -ENOSPC;
-- }
--
-- /* else scan the schedule to find a group of slots such that all
-- * uframes have enough periodic bandwidth available.
-- */
-- if (status) {
-- /* "normal" case, uframing flexible except with splits */
-- if (qh->period) {
-- int i;
--
-- for (i = qh->period; status && i > 0; --i) {
-- frame = ++fotg210->random_frame % qh->period;
-- for (uframe = 0; uframe < 8; uframe++) {
-- status = check_intr_schedule(fotg210,
-- frame, uframe, qh,
-- &c_mask);
-- if (status == 0)
-- break;
-- }
-- }
--
-- /* qh->period == 0 means every uframe */
-- } else {
-- frame = 0;
-- status = check_intr_schedule(fotg210, 0, 0, qh,
-- &c_mask);
-- }
-- if (status)
-- goto done;
-- qh->start = frame;
--
-- /* reset S-frame and (maybe) C-frame masks */
-- hw->hw_info2 &= cpu_to_hc32(fotg210, ~(QH_CMASK | QH_SMASK));
-- hw->hw_info2 |= qh->period
-- ? cpu_to_hc32(fotg210, 1 << uframe)
-- : cpu_to_hc32(fotg210, QH_SMASK);
-- hw->hw_info2 |= c_mask;
-- } else
-- fotg210_dbg(fotg210, "reused qh %p schedule\n", qh);
--
-- /* stuff into the periodic schedule */
-- qh_link_periodic(fotg210, qh);
--done:
-- return status;
--}
--
--static int intr_submit(struct fotg210_hcd *fotg210, struct urb *urb,
-- struct list_head *qtd_list, gfp_t mem_flags)
--{
-- unsigned epnum;
-- unsigned long flags;
-- struct fotg210_qh *qh;
-- int status;
-- struct list_head empty;
--
-- /* get endpoint and transfer/schedule data */
-- epnum = urb->ep->desc.bEndpointAddress;
--
-- spin_lock_irqsave(&fotg210->lock, flags);
--
-- if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
-- status = -ESHUTDOWN;
-- goto done_not_linked;
-- }
-- status = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
-- if (unlikely(status))
-- goto done_not_linked;
--
-- /* get qh and force any scheduling errors */
-- INIT_LIST_HEAD(&empty);
-- qh = qh_append_tds(fotg210, urb, &empty, epnum, &urb->ep->hcpriv);
-- if (qh == NULL) {
-- status = -ENOMEM;
-- goto done;
-- }
-- if (qh->qh_state == QH_STATE_IDLE) {
-- status = qh_schedule(fotg210, qh);
-- if (status)
-- goto done;
-- }
--
-- /* then queue the urb's tds to the qh */
-- qh = qh_append_tds(fotg210, urb, qtd_list, epnum, &urb->ep->hcpriv);
-- BUG_ON(qh == NULL);
--
-- /* ... update usbfs periodic stats */
-- fotg210_to_hcd(fotg210)->self.bandwidth_int_reqs++;
--
--done:
-- if (unlikely(status))
-- usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
--done_not_linked:
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- if (status)
-- qtd_list_free(fotg210, urb, qtd_list);
--
-- return status;
--}
--
--static void scan_intr(struct fotg210_hcd *fotg210)
--{
-- struct fotg210_qh *qh;
--
-- list_for_each_entry_safe(qh, fotg210->qh_scan_next,
-- &fotg210->intr_qh_list, intr_node) {
--rescan:
-- /* clean any finished work for this qh */
-- if (!list_empty(&qh->qtd_list)) {
-- int temp;
--
-- /*
-- * Unlinks could happen here; completion reporting
-- * drops the lock. That's why fotg210->qh_scan_next
-- * always holds the next qh to scan; if the next qh
-- * gets unlinked then fotg210->qh_scan_next is adjusted
-- * in qh_unlink_periodic().
-- */
-- temp = qh_completions(fotg210, qh);
-- if (unlikely(qh->needs_rescan ||
-- (list_empty(&qh->qtd_list) &&
-- qh->qh_state == QH_STATE_LINKED)))
-- start_unlink_intr(fotg210, qh);
-- else if (temp != 0)
-- goto rescan;
-- }
-- }
--}
--
--/* fotg210_iso_stream ops work with both ITD and SITD */
--
--static struct fotg210_iso_stream *iso_stream_alloc(gfp_t mem_flags)
--{
-- struct fotg210_iso_stream *stream;
--
-- stream = kzalloc(sizeof(*stream), mem_flags);
-- if (likely(stream != NULL)) {
-- INIT_LIST_HEAD(&stream->td_list);
-- INIT_LIST_HEAD(&stream->free_list);
-- stream->next_uframe = -1;
-- }
-- return stream;
--}
--
--static void iso_stream_init(struct fotg210_hcd *fotg210,
-- struct fotg210_iso_stream *stream, struct usb_device *dev,
-- int pipe, unsigned interval)
--{
-- u32 buf1;
-- unsigned epnum, maxp;
-- int is_input;
-- long bandwidth;
-- unsigned multi;
-- struct usb_host_endpoint *ep;
--
-- /*
-- * this might be a "high bandwidth" highspeed endpoint,
-- * as encoded in the ep descriptor's wMaxPacket field
-- */
-- epnum = usb_pipeendpoint(pipe);
-- is_input = usb_pipein(pipe) ? USB_DIR_IN : 0;
-- ep = usb_pipe_endpoint(dev, pipe);
-- maxp = usb_endpoint_maxp(&ep->desc);
-- if (is_input)
-- buf1 = (1 << 11);
-- else
-- buf1 = 0;
--
-- multi = usb_endpoint_maxp_mult(&ep->desc);
-- buf1 |= maxp;
-- maxp *= multi;
--
-- stream->buf0 = cpu_to_hc32(fotg210, (epnum << 8) | dev->devnum);
-- stream->buf1 = cpu_to_hc32(fotg210, buf1);
-- stream->buf2 = cpu_to_hc32(fotg210, multi);
--
-- /* usbfs wants to report the average usecs per frame tied up
-- * when transfers on this endpoint are scheduled ...
-- */
-- if (dev->speed == USB_SPEED_FULL) {
-- interval <<= 3;
-- stream->usecs = NS_TO_US(usb_calc_bus_time(dev->speed,
-- is_input, 1, maxp));
-- stream->usecs /= 8;
-- } else {
-- stream->highspeed = 1;
-- stream->usecs = HS_USECS_ISO(maxp);
-- }
-- bandwidth = stream->usecs * 8;
-- bandwidth /= interval;
--
-- stream->bandwidth = bandwidth;
-- stream->udev = dev;
-- stream->bEndpointAddress = is_input | epnum;
-- stream->interval = interval;
-- stream->maxp = maxp;
--}
--
--static struct fotg210_iso_stream *iso_stream_find(struct fotg210_hcd *fotg210,
-- struct urb *urb)
--{
-- unsigned epnum;
-- struct fotg210_iso_stream *stream;
-- struct usb_host_endpoint *ep;
-- unsigned long flags;
--
-- epnum = usb_pipeendpoint(urb->pipe);
-- if (usb_pipein(urb->pipe))
-- ep = urb->dev->ep_in[epnum];
-- else
-- ep = urb->dev->ep_out[epnum];
--
-- spin_lock_irqsave(&fotg210->lock, flags);
-- stream = ep->hcpriv;
--
-- if (unlikely(stream == NULL)) {
-- stream = iso_stream_alloc(GFP_ATOMIC);
-- if (likely(stream != NULL)) {
-- ep->hcpriv = stream;
-- stream->ep = ep;
-- iso_stream_init(fotg210, stream, urb->dev, urb->pipe,
-- urb->interval);
-- }
--
-- /* if dev->ep[epnum] is a QH, hw is set */
-- } else if (unlikely(stream->hw != NULL)) {
-- fotg210_dbg(fotg210, "dev %s ep%d%s, not iso??\n",
-- urb->dev->devpath, epnum,
-- usb_pipein(urb->pipe) ? "in" : "out");
-- stream = NULL;
-- }
--
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- return stream;
--}
--
--/* fotg210_iso_sched ops can be ITD-only or SITD-only */
--
--static struct fotg210_iso_sched *iso_sched_alloc(unsigned packets,
-- gfp_t mem_flags)
--{
-- struct fotg210_iso_sched *iso_sched;
--
-- iso_sched = kzalloc(struct_size(iso_sched, packet, packets), mem_flags);
-- if (likely(iso_sched != NULL))
-- INIT_LIST_HEAD(&iso_sched->td_list);
--
-- return iso_sched;
--}
--
--static inline void itd_sched_init(struct fotg210_hcd *fotg210,
-- struct fotg210_iso_sched *iso_sched,
-- struct fotg210_iso_stream *stream, struct urb *urb)
--{
-- unsigned i;
-- dma_addr_t dma = urb->transfer_dma;
--
-- /* how many uframes are needed for these transfers */
-- iso_sched->span = urb->number_of_packets * stream->interval;
--
-- /* figure out per-uframe itd fields that we'll need later
-- * when we fit new itds into the schedule.
-- */
-- for (i = 0; i < urb->number_of_packets; i++) {
-- struct fotg210_iso_packet *uframe = &iso_sched->packet[i];
-- unsigned length;
-- dma_addr_t buf;
-- u32 trans;
--
-- length = urb->iso_frame_desc[i].length;
-- buf = dma + urb->iso_frame_desc[i].offset;
--
-- trans = FOTG210_ISOC_ACTIVE;
-- trans |= buf & 0x0fff;
-- if (unlikely(((i + 1) == urb->number_of_packets))
-- && !(urb->transfer_flags & URB_NO_INTERRUPT))
-- trans |= FOTG210_ITD_IOC;
-- trans |= length << 16;
-- uframe->transaction = cpu_to_hc32(fotg210, trans);
--
-- /* might need to cross a buffer page within a uframe */
-- uframe->bufp = (buf & ~(u64)0x0fff);
-- buf += length;
-- if (unlikely((uframe->bufp != (buf & ~(u64)0x0fff))))
-- uframe->cross = 1;
-- }
--}
--
--static void iso_sched_free(struct fotg210_iso_stream *stream,
-- struct fotg210_iso_sched *iso_sched)
--{
-- if (!iso_sched)
-- return;
-- /* caller must hold fotg210->lock!*/
-- list_splice(&iso_sched->td_list, &stream->free_list);
-- kfree(iso_sched);
--}
--
--static int itd_urb_transaction(struct fotg210_iso_stream *stream,
-- struct fotg210_hcd *fotg210, struct urb *urb, gfp_t mem_flags)
--{
-- struct fotg210_itd *itd;
-- dma_addr_t itd_dma;
-- int i;
-- unsigned num_itds;
-- struct fotg210_iso_sched *sched;
-- unsigned long flags;
--
-- sched = iso_sched_alloc(urb->number_of_packets, mem_flags);
-- if (unlikely(sched == NULL))
-- return -ENOMEM;
--
-- itd_sched_init(fotg210, sched, stream, urb);
--
-- if (urb->interval < 8)
-- num_itds = 1 + (sched->span + 7) / 8;
-- else
-- num_itds = urb->number_of_packets;
--
-- /* allocate/init ITDs */
-- spin_lock_irqsave(&fotg210->lock, flags);
-- for (i = 0; i < num_itds; i++) {
--
-- /*
-- * Use iTDs from the free list, but not iTDs that may
-- * still be in use by the hardware.
-- */
-- if (likely(!list_empty(&stream->free_list))) {
-- itd = list_first_entry(&stream->free_list,
-- struct fotg210_itd, itd_list);
-- if (itd->frame == fotg210->now_frame)
-- goto alloc_itd;
-- list_del(&itd->itd_list);
-- itd_dma = itd->itd_dma;
-- } else {
--alloc_itd:
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- itd = dma_pool_alloc(fotg210->itd_pool, mem_flags,
-- &itd_dma);
-- spin_lock_irqsave(&fotg210->lock, flags);
-- if (!itd) {
-- iso_sched_free(stream, sched);
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- return -ENOMEM;
-- }
-- }
--
-- memset(itd, 0, sizeof(*itd));
-- itd->itd_dma = itd_dma;
-- list_add(&itd->itd_list, &sched->td_list);
-- }
-- spin_unlock_irqrestore(&fotg210->lock, flags);
--
-- /* temporarily store schedule info in hcpriv */
-- urb->hcpriv = sched;
-- urb->error_count = 0;
-- return 0;
--}
--
--static inline int itd_slot_ok(struct fotg210_hcd *fotg210, u32 mod, u32 uframe,
-- u8 usecs, u32 period)
--{
-- uframe %= period;
-- do {
-- /* can't commit more than uframe_periodic_max usec */
-- if (periodic_usecs(fotg210, uframe >> 3, uframe & 0x7)
-- > (fotg210->uframe_periodic_max - usecs))
-- return 0;
--
-- /* we know urb->interval is 2^N uframes */
-- uframe += period;
-- } while (uframe < mod);
-- return 1;
--}
--
--/* This scheduler plans almost as far into the future as it has actual
-- * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
-- * "as small as possible" to be cache-friendlier.) That limits the size
-- * transfers you can stream reliably; avoid more than 64 msec per urb.
-- * Also avoid queue depths of less than fotg210's worst irq latency (affected
-- * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
-- * and other factors); or more than about 230 msec total (for portability,
-- * given FOTG210_TUNE_FLS and the slop). Or, write a smarter scheduler!
-- */
--
--#define SCHEDULE_SLOP 80 /* microframes */
--
--static int iso_stream_schedule(struct fotg210_hcd *fotg210, struct urb *urb,
-- struct fotg210_iso_stream *stream)
--{
-- u32 now, next, start, period, span;
-- int status;
-- unsigned mod = fotg210->periodic_size << 3;
-- struct fotg210_iso_sched *sched = urb->hcpriv;
--
-- period = urb->interval;
-- span = sched->span;
--
-- if (span > mod - SCHEDULE_SLOP) {
-- fotg210_dbg(fotg210, "iso request %p too long\n", urb);
-- status = -EFBIG;
-- goto fail;
-- }
--
-- now = fotg210_read_frame_index(fotg210) & (mod - 1);
--
-- /* Typical case: reuse current schedule, stream is still active.
-- * Hopefully there are no gaps from the host falling behind
-- * (irq delays etc), but if there are we'll take the next
-- * slot in the schedule, implicitly assuming URB_ISO_ASAP.
-- */
-- if (likely(!list_empty(&stream->td_list))) {
-- u32 excess;
--
-- /* For high speed devices, allow scheduling within the
-- * isochronous scheduling threshold. For full speed devices
-- * and Intel PCI-based controllers, don't (work around for
-- * Intel ICH9 bug).
-- */
-- if (!stream->highspeed && fotg210->fs_i_thresh)
-- next = now + fotg210->i_thresh;
-- else
-- next = now;
--
-- /* Fell behind (by up to twice the slop amount)?
-- * We decide based on the time of the last currently-scheduled
-- * slot, not the time of the next available slot.
-- */
-- excess = (stream->next_uframe - period - next) & (mod - 1);
-- if (excess >= mod - 2 * SCHEDULE_SLOP)
-- start = next + excess - mod + period *
-- DIV_ROUND_UP(mod - excess, period);
-- else
-- start = next + excess + period;
-- if (start - now >= mod) {
-- fotg210_dbg(fotg210, "request %p would overflow (%d+%d >= %d)\n",
-- urb, start - now - period, period,
-- mod);
-- status = -EFBIG;
-- goto fail;
-- }
-- }
--
-- /* need to schedule; when's the next (u)frame we could start?
-- * this is bigger than fotg210->i_thresh allows; scheduling itself
-- * isn't free, the slop should handle reasonably slow cpus. it
-- * can also help high bandwidth if the dma and irq loads don't
-- * jump until after the queue is primed.
-- */
-- else {
-- int done = 0;
--
-- start = SCHEDULE_SLOP + (now & ~0x07);
--
-- /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
--
-- /* find a uframe slot with enough bandwidth.
-- * Early uframes are more precious because full-speed
-- * iso IN transfers can't use late uframes,
-- * and therefore they should be allocated last.
-- */
-- next = start;
-- start += period;
-- do {
-- start--;
-- /* check schedule: enough space? */
-- if (itd_slot_ok(fotg210, mod, start,
-- stream->usecs, period))
-- done = 1;
-- } while (start > next && !done);
--
-- /* no room in the schedule */
-- if (!done) {
-- fotg210_dbg(fotg210, "iso resched full %p (now %d max %d)\n",
-- urb, now, now + mod);
-- status = -ENOSPC;
-- goto fail;
-- }
-- }
--
-- /* Tried to schedule too far into the future? */
-- if (unlikely(start - now + span - period >=
-- mod - 2 * SCHEDULE_SLOP)) {
-- fotg210_dbg(fotg210, "request %p would overflow (%d+%d >= %d)\n",
-- urb, start - now, span - period,
-- mod - 2 * SCHEDULE_SLOP);
-- status = -EFBIG;
-- goto fail;
-- }
--
-- stream->next_uframe = start & (mod - 1);
--
-- /* report high speed start in uframes; full speed, in frames */
-- urb->start_frame = stream->next_uframe;
-- if (!stream->highspeed)
-- urb->start_frame >>= 3;
--
-- /* Make sure scan_isoc() sees these */
-- if (fotg210->isoc_count == 0)
-- fotg210->next_frame = now >> 3;
-- return 0;
--
--fail:
-- iso_sched_free(stream, sched);
-- urb->hcpriv = NULL;
-- return status;
--}
--
--static inline void itd_init(struct fotg210_hcd *fotg210,
-- struct fotg210_iso_stream *stream, struct fotg210_itd *itd)
--{
-- int i;
--
-- /* it's been recently zeroed */
-- itd->hw_next = FOTG210_LIST_END(fotg210);
-- itd->hw_bufp[0] = stream->buf0;
-- itd->hw_bufp[1] = stream->buf1;
-- itd->hw_bufp[2] = stream->buf2;
--
-- for (i = 0; i < 8; i++)
-- itd->index[i] = -1;
--
-- /* All other fields are filled when scheduling */
--}
--
--static inline void itd_patch(struct fotg210_hcd *fotg210,
-- struct fotg210_itd *itd, struct fotg210_iso_sched *iso_sched,
-- unsigned index, u16 uframe)
--{
-- struct fotg210_iso_packet *uf = &iso_sched->packet[index];
-- unsigned pg = itd->pg;
--
-- uframe &= 0x07;
-- itd->index[uframe] = index;
--
-- itd->hw_transaction[uframe] = uf->transaction;
-- itd->hw_transaction[uframe] |= cpu_to_hc32(fotg210, pg << 12);
-- itd->hw_bufp[pg] |= cpu_to_hc32(fotg210, uf->bufp & ~(u32)0);
-- itd->hw_bufp_hi[pg] |= cpu_to_hc32(fotg210, (u32)(uf->bufp >> 32));
--
-- /* iso_frame_desc[].offset must be strictly increasing */
-- if (unlikely(uf->cross)) {
-- u64 bufp = uf->bufp + 4096;
--
-- itd->pg = ++pg;
-- itd->hw_bufp[pg] |= cpu_to_hc32(fotg210, bufp & ~(u32)0);
-- itd->hw_bufp_hi[pg] |= cpu_to_hc32(fotg210, (u32)(bufp >> 32));
-- }
--}
--
--static inline void itd_link(struct fotg210_hcd *fotg210, unsigned frame,
-- struct fotg210_itd *itd)
--{
-- union fotg210_shadow *prev = &fotg210->pshadow[frame];
-- __hc32 *hw_p = &fotg210->periodic[frame];
-- union fotg210_shadow here = *prev;
-- __hc32 type = 0;
--
-- /* skip any iso nodes which might belong to previous microframes */
-- while (here.ptr) {
-- type = Q_NEXT_TYPE(fotg210, *hw_p);
-- if (type == cpu_to_hc32(fotg210, Q_TYPE_QH))
-- break;
-- prev = periodic_next_shadow(fotg210, prev, type);
-- hw_p = shadow_next_periodic(fotg210, &here, type);
-- here = *prev;
-- }
--
-- itd->itd_next = here;
-- itd->hw_next = *hw_p;
-- prev->itd = itd;
-- itd->frame = frame;
-- wmb();
-- *hw_p = cpu_to_hc32(fotg210, itd->itd_dma | Q_TYPE_ITD);
--}
--
--/* fit urb's itds into the selected schedule slot; activate as needed */
--static void itd_link_urb(struct fotg210_hcd *fotg210, struct urb *urb,
-- unsigned mod, struct fotg210_iso_stream *stream)
--{
-- int packet;
-- unsigned next_uframe, uframe, frame;
-- struct fotg210_iso_sched *iso_sched = urb->hcpriv;
-- struct fotg210_itd *itd;
--
-- next_uframe = stream->next_uframe & (mod - 1);
--
-- if (unlikely(list_empty(&stream->td_list))) {
-- fotg210_to_hcd(fotg210)->self.bandwidth_allocated
-- += stream->bandwidth;
-- fotg210_dbg(fotg210,
-- "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
-- urb->dev->devpath, stream->bEndpointAddress & 0x0f,
-- (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
-- urb->interval,
-- next_uframe >> 3, next_uframe & 0x7);
-- }
--
-- /* fill iTDs uframe by uframe */
-- for (packet = 0, itd = NULL; packet < urb->number_of_packets;) {
-- if (itd == NULL) {
-- /* ASSERT: we have all necessary itds */
--
-- /* ASSERT: no itds for this endpoint in this uframe */
--
-- itd = list_entry(iso_sched->td_list.next,
-- struct fotg210_itd, itd_list);
-- list_move_tail(&itd->itd_list, &stream->td_list);
-- itd->stream = stream;
-- itd->urb = urb;
-- itd_init(fotg210, stream, itd);
-- }
--
-- uframe = next_uframe & 0x07;
-- frame = next_uframe >> 3;
--
-- itd_patch(fotg210, itd, iso_sched, packet, uframe);
--
-- next_uframe += stream->interval;
-- next_uframe &= mod - 1;
-- packet++;
--
-- /* link completed itds into the schedule */
-- if (((next_uframe >> 3) != frame)
-- || packet == urb->number_of_packets) {
-- itd_link(fotg210, frame & (fotg210->periodic_size - 1),
-- itd);
-- itd = NULL;
-- }
-- }
-- stream->next_uframe = next_uframe;
--
-- /* don't need that schedule data any more */
-- iso_sched_free(stream, iso_sched);
-- urb->hcpriv = NULL;
--
-- ++fotg210->isoc_count;
-- enable_periodic(fotg210);
--}
--
--#define ISO_ERRS (FOTG210_ISOC_BUF_ERR | FOTG210_ISOC_BABBLE |\
-- FOTG210_ISOC_XACTERR)
--
--/* Process and recycle a completed ITD. Return true iff its urb completed,
-- * and hence its completion callback probably added things to the hardware
-- * schedule.
-- *
-- * Note that we carefully avoid recycling this descriptor until after any
-- * completion callback runs, so that it won't be reused quickly. That is,
-- * assuming (a) no more than two urbs per frame on this endpoint, and also
-- * (b) only this endpoint's completions submit URBs. It seems some silicon
-- * corrupts things if you reuse completed descriptors very quickly...
-- */
--static bool itd_complete(struct fotg210_hcd *fotg210, struct fotg210_itd *itd)
--{
-- struct urb *urb = itd->urb;
-- struct usb_iso_packet_descriptor *desc;
-- u32 t;
-- unsigned uframe;
-- int urb_index = -1;
-- struct fotg210_iso_stream *stream = itd->stream;
-- struct usb_device *dev;
-- bool retval = false;
--
-- /* for each uframe with a packet */
-- for (uframe = 0; uframe < 8; uframe++) {
-- if (likely(itd->index[uframe] == -1))
-- continue;
-- urb_index = itd->index[uframe];
-- desc = &urb->iso_frame_desc[urb_index];
--
-- t = hc32_to_cpup(fotg210, &itd->hw_transaction[uframe]);
-- itd->hw_transaction[uframe] = 0;
--
-- /* report transfer status */
-- if (unlikely(t & ISO_ERRS)) {
-- urb->error_count++;
-- if (t & FOTG210_ISOC_BUF_ERR)
-- desc->status = usb_pipein(urb->pipe)
-- ? -ENOSR /* hc couldn't read */
-- : -ECOMM; /* hc couldn't write */
-- else if (t & FOTG210_ISOC_BABBLE)
-- desc->status = -EOVERFLOW;
-- else /* (t & FOTG210_ISOC_XACTERR) */
-- desc->status = -EPROTO;
--
-- /* HC need not update length with this error */
-- if (!(t & FOTG210_ISOC_BABBLE)) {
-- desc->actual_length = FOTG210_ITD_LENGTH(t);
-- urb->actual_length += desc->actual_length;
-- }
-- } else if (likely((t & FOTG210_ISOC_ACTIVE) == 0)) {
-- desc->status = 0;
-- desc->actual_length = FOTG210_ITD_LENGTH(t);
-- urb->actual_length += desc->actual_length;
-- } else {
-- /* URB was too late */
-- desc->status = -EXDEV;
-- }
-- }
--
-- /* handle completion now? */
-- if (likely((urb_index + 1) != urb->number_of_packets))
-- goto done;
--
-- /* ASSERT: it's really the last itd for this urb
-- * list_for_each_entry (itd, &stream->td_list, itd_list)
-- * BUG_ON (itd->urb == urb);
-- */
--
-- /* give urb back to the driver; completion often (re)submits */
-- dev = urb->dev;
-- fotg210_urb_done(fotg210, urb, 0);
-- retval = true;
-- urb = NULL;
--
-- --fotg210->isoc_count;
-- disable_periodic(fotg210);
--
-- if (unlikely(list_is_singular(&stream->td_list))) {
-- fotg210_to_hcd(fotg210)->self.bandwidth_allocated
-- -= stream->bandwidth;
-- fotg210_dbg(fotg210,
-- "deschedule devp %s ep%d%s-iso\n",
-- dev->devpath, stream->bEndpointAddress & 0x0f,
-- (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
-- }
--
--done:
-- itd->urb = NULL;
--
-- /* Add to the end of the free list for later reuse */
-- list_move_tail(&itd->itd_list, &stream->free_list);
--
-- /* Recycle the iTDs when the pipeline is empty (ep no longer in use) */
-- if (list_empty(&stream->td_list)) {
-- list_splice_tail_init(&stream->free_list,
-- &fotg210->cached_itd_list);
-- start_free_itds(fotg210);
-- }
--
-- return retval;
--}
--
--static int itd_submit(struct fotg210_hcd *fotg210, struct urb *urb,
-- gfp_t mem_flags)
--{
-- int status = -EINVAL;
-- unsigned long flags;
-- struct fotg210_iso_stream *stream;
--
-- /* Get iso_stream head */
-- stream = iso_stream_find(fotg210, urb);
-- if (unlikely(stream == NULL)) {
-- fotg210_dbg(fotg210, "can't get iso stream\n");
-- return -ENOMEM;
-- }
-- if (unlikely(urb->interval != stream->interval &&
-- fotg210_port_speed(fotg210, 0) ==
-- USB_PORT_STAT_HIGH_SPEED)) {
-- fotg210_dbg(fotg210, "can't change iso interval %d --> %d\n",
-- stream->interval, urb->interval);
-- goto done;
-- }
--
--#ifdef FOTG210_URB_TRACE
-- fotg210_dbg(fotg210,
-- "%s %s urb %p ep%d%s len %d, %d pkts %d uframes[%p]\n",
-- __func__, urb->dev->devpath, urb,
-- usb_pipeendpoint(urb->pipe),
-- usb_pipein(urb->pipe) ? "in" : "out",
-- urb->transfer_buffer_length,
-- urb->number_of_packets, urb->interval,
-- stream);
--#endif
--
-- /* allocate ITDs w/o locking anything */
-- status = itd_urb_transaction(stream, fotg210, urb, mem_flags);
-- if (unlikely(status < 0)) {
-- fotg210_dbg(fotg210, "can't init itds\n");
-- goto done;
-- }
--
-- /* schedule ... need to lock */
-- spin_lock_irqsave(&fotg210->lock, flags);
-- if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
-- status = -ESHUTDOWN;
-- goto done_not_linked;
-- }
-- status = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
-- if (unlikely(status))
-- goto done_not_linked;
-- status = iso_stream_schedule(fotg210, urb, stream);
-- if (likely(status == 0))
-- itd_link_urb(fotg210, urb, fotg210->periodic_size << 3, stream);
-- else
-- usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
--done_not_linked:
-- spin_unlock_irqrestore(&fotg210->lock, flags);
--done:
-- return status;
--}
--
--static inline int scan_frame_queue(struct fotg210_hcd *fotg210, unsigned frame,
-- unsigned now_frame, bool live)
--{
-- unsigned uf;
-- bool modified;
-- union fotg210_shadow q, *q_p;
-- __hc32 type, *hw_p;
--
-- /* scan each element in frame's queue for completions */
-- q_p = &fotg210->pshadow[frame];
-- hw_p = &fotg210->periodic[frame];
-- q.ptr = q_p->ptr;
-- type = Q_NEXT_TYPE(fotg210, *hw_p);
-- modified = false;
--
-- while (q.ptr) {
-- switch (hc32_to_cpu(fotg210, type)) {
-- case Q_TYPE_ITD:
-- /* If this ITD is still active, leave it for
-- * later processing ... check the next entry.
-- * No need to check for activity unless the
-- * frame is current.
-- */
-- if (frame == now_frame && live) {
-- rmb();
-- for (uf = 0; uf < 8; uf++) {
-- if (q.itd->hw_transaction[uf] &
-- ITD_ACTIVE(fotg210))
-- break;
-- }
-- if (uf < 8) {
-- q_p = &q.itd->itd_next;
-- hw_p = &q.itd->hw_next;
-- type = Q_NEXT_TYPE(fotg210,
-- q.itd->hw_next);
-- q = *q_p;
-- break;
-- }
-- }
--
-- /* Take finished ITDs out of the schedule
-- * and process them: recycle, maybe report
-- * URB completion. HC won't cache the
-- * pointer for much longer, if at all.
-- */
-- *q_p = q.itd->itd_next;
-- *hw_p = q.itd->hw_next;
-- type = Q_NEXT_TYPE(fotg210, q.itd->hw_next);
-- wmb();
-- modified = itd_complete(fotg210, q.itd);
-- q = *q_p;
-- break;
-- default:
-- fotg210_dbg(fotg210, "corrupt type %d frame %d shadow %p\n",
-- type, frame, q.ptr);
-- fallthrough;
-- case Q_TYPE_QH:
-- case Q_TYPE_FSTN:
-- /* End of the iTDs and siTDs */
-- q.ptr = NULL;
-- break;
-- }
--
-- /* assume completion callbacks modify the queue */
-- if (unlikely(modified && fotg210->isoc_count > 0))
-- return -EINVAL;
-- }
-- return 0;
--}
--
--static void scan_isoc(struct fotg210_hcd *fotg210)
--{
-- unsigned uf, now_frame, frame, ret;
-- unsigned fmask = fotg210->periodic_size - 1;
-- bool live;
--
-- /*
-- * When running, scan from last scan point up to "now"
-- * else clean up by scanning everything that's left.
-- * Touches as few pages as possible: cache-friendly.
-- */
-- if (fotg210->rh_state >= FOTG210_RH_RUNNING) {
-- uf = fotg210_read_frame_index(fotg210);
-- now_frame = (uf >> 3) & fmask;
-- live = true;
-- } else {
-- now_frame = (fotg210->next_frame - 1) & fmask;
-- live = false;
-- }
-- fotg210->now_frame = now_frame;
--
-- frame = fotg210->next_frame;
-- for (;;) {
-- ret = 1;
-- while (ret != 0)
-- ret = scan_frame_queue(fotg210, frame,
-- now_frame, live);
--
-- /* Stop when we have reached the current frame */
-- if (frame == now_frame)
-- break;
-- frame = (frame + 1) & fmask;
-- }
-- fotg210->next_frame = now_frame;
--}
--
--/* Display / Set uframe_periodic_max
-- */
--static ssize_t uframe_periodic_max_show(struct device *dev,
-- struct device_attribute *attr, char *buf)
--{
-- struct fotg210_hcd *fotg210;
-- int n;
--
-- fotg210 = hcd_to_fotg210(bus_to_hcd(dev_get_drvdata(dev)));
-- n = scnprintf(buf, PAGE_SIZE, "%d\n", fotg210->uframe_periodic_max);
-- return n;
--}
--
--
--static ssize_t uframe_periodic_max_store(struct device *dev,
-- struct device_attribute *attr, const char *buf, size_t count)
--{
-- struct fotg210_hcd *fotg210;
-- unsigned uframe_periodic_max;
-- unsigned frame, uframe;
-- unsigned short allocated_max;
-- unsigned long flags;
-- ssize_t ret;
--
-- fotg210 = hcd_to_fotg210(bus_to_hcd(dev_get_drvdata(dev)));
-- if (kstrtouint(buf, 0, &uframe_periodic_max) < 0)
-- return -EINVAL;
--
-- if (uframe_periodic_max < 100 || uframe_periodic_max >= 125) {
-- fotg210_info(fotg210, "rejecting invalid request for uframe_periodic_max=%u\n",
-- uframe_periodic_max);
-- return -EINVAL;
-- }
--
-- ret = -EINVAL;
--
-- /*
-- * lock, so that our checking does not race with possible periodic
-- * bandwidth allocation through submitting new urbs.
-- */
-- spin_lock_irqsave(&fotg210->lock, flags);
--
-- /*
-- * for request to decrease max periodic bandwidth, we have to check
-- * every microframe in the schedule to see whether the decrease is
-- * possible.
-- */
-- if (uframe_periodic_max < fotg210->uframe_periodic_max) {
-- allocated_max = 0;
--
-- for (frame = 0; frame < fotg210->periodic_size; ++frame)
-- for (uframe = 0; uframe < 7; ++uframe)
-- allocated_max = max(allocated_max,
-- periodic_usecs(fotg210, frame,
-- uframe));
--
-- if (allocated_max > uframe_periodic_max) {
-- fotg210_info(fotg210,
-- "cannot decrease uframe_periodic_max because periodic bandwidth is already allocated (%u > %u)\n",
-- allocated_max, uframe_periodic_max);
-- goto out_unlock;
-- }
-- }
--
-- /* increasing is always ok */
--
-- fotg210_info(fotg210,
-- "setting max periodic bandwidth to %u%% (== %u usec/uframe)\n",
-- 100 * uframe_periodic_max/125, uframe_periodic_max);
--
-- if (uframe_periodic_max != 100)
-- fotg210_warn(fotg210, "max periodic bandwidth set is non-standard\n");
--
-- fotg210->uframe_periodic_max = uframe_periodic_max;
-- ret = count;
--
--out_unlock:
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- return ret;
--}
--
--static DEVICE_ATTR_RW(uframe_periodic_max);
--
--static inline int create_sysfs_files(struct fotg210_hcd *fotg210)
--{
-- struct device *controller = fotg210_to_hcd(fotg210)->self.controller;
--
-- return device_create_file(controller, &dev_attr_uframe_periodic_max);
--}
--
--static inline void remove_sysfs_files(struct fotg210_hcd *fotg210)
--{
-- struct device *controller = fotg210_to_hcd(fotg210)->self.controller;
--
-- device_remove_file(controller, &dev_attr_uframe_periodic_max);
--}
--/* On some systems, leaving remote wakeup enabled prevents system shutdown.
-- * The firmware seems to think that powering off is a wakeup event!
-- * This routine turns off remote wakeup and everything else, on all ports.
-- */
--static void fotg210_turn_off_all_ports(struct fotg210_hcd *fotg210)
--{
-- u32 __iomem *status_reg = &fotg210->regs->port_status;
--
-- fotg210_writel(fotg210, PORT_RWC_BITS, status_reg);
--}
--
--/* Halt HC, turn off all ports, and let the BIOS use the companion controllers.
-- * Must be called with interrupts enabled and the lock not held.
-- */
--static void fotg210_silence_controller(struct fotg210_hcd *fotg210)
--{
-- fotg210_halt(fotg210);
--
-- spin_lock_irq(&fotg210->lock);
-- fotg210->rh_state = FOTG210_RH_HALTED;
-- fotg210_turn_off_all_ports(fotg210);
-- spin_unlock_irq(&fotg210->lock);
--}
--
--/* fotg210_shutdown kick in for silicon on any bus (not just pci, etc).
-- * This forcibly disables dma and IRQs, helping kexec and other cases
-- * where the next system software may expect clean state.
-- */
--static void fotg210_shutdown(struct usb_hcd *hcd)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--
-- spin_lock_irq(&fotg210->lock);
-- fotg210->shutdown = true;
-- fotg210->rh_state = FOTG210_RH_STOPPING;
-- fotg210->enabled_hrtimer_events = 0;
-- spin_unlock_irq(&fotg210->lock);
--
-- fotg210_silence_controller(fotg210);
--
-- hrtimer_cancel(&fotg210->hrtimer);
--}
--
--/* fotg210_work is called from some interrupts, timers, and so on.
-- * it calls driver completion functions, after dropping fotg210->lock.
-- */
--static void fotg210_work(struct fotg210_hcd *fotg210)
--{
-- /* another CPU may drop fotg210->lock during a schedule scan while
-- * it reports urb completions. this flag guards against bogus
-- * attempts at re-entrant schedule scanning.
-- */
-- if (fotg210->scanning) {
-- fotg210->need_rescan = true;
-- return;
-- }
-- fotg210->scanning = true;
--
--rescan:
-- fotg210->need_rescan = false;
-- if (fotg210->async_count)
-- scan_async(fotg210);
-- if (fotg210->intr_count > 0)
-- scan_intr(fotg210);
-- if (fotg210->isoc_count > 0)
-- scan_isoc(fotg210);
-- if (fotg210->need_rescan)
-- goto rescan;
-- fotg210->scanning = false;
--
-- /* the IO watchdog guards against hardware or driver bugs that
-- * misplace IRQs, and should let us run completely without IRQs.
-- * such lossage has been observed on both VT6202 and VT8235.
-- */
-- turn_on_io_watchdog(fotg210);
--}
--
--/* Called when the fotg210_hcd module is removed.
-- */
--static void fotg210_stop(struct usb_hcd *hcd)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--
-- fotg210_dbg(fotg210, "stop\n");
--
-- /* no more interrupts ... */
--
-- spin_lock_irq(&fotg210->lock);
-- fotg210->enabled_hrtimer_events = 0;
-- spin_unlock_irq(&fotg210->lock);
--
-- fotg210_quiesce(fotg210);
-- fotg210_silence_controller(fotg210);
-- fotg210_reset(fotg210);
--
-- hrtimer_cancel(&fotg210->hrtimer);
-- remove_sysfs_files(fotg210);
-- remove_debug_files(fotg210);
--
-- /* root hub is shut down separately (first, when possible) */
-- spin_lock_irq(&fotg210->lock);
-- end_free_itds(fotg210);
-- spin_unlock_irq(&fotg210->lock);
-- fotg210_mem_cleanup(fotg210);
--
--#ifdef FOTG210_STATS
-- fotg210_dbg(fotg210, "irq normal %ld err %ld iaa %ld (lost %ld)\n",
-- fotg210->stats.normal, fotg210->stats.error,
-- fotg210->stats.iaa, fotg210->stats.lost_iaa);
-- fotg210_dbg(fotg210, "complete %ld unlink %ld\n",
-- fotg210->stats.complete, fotg210->stats.unlink);
--#endif
--
-- dbg_status(fotg210, "fotg210_stop completed",
-- fotg210_readl(fotg210, &fotg210->regs->status));
--}
--
--/* one-time init, only for memory state */
--static int hcd_fotg210_init(struct usb_hcd *hcd)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-- u32 temp;
-- int retval;
-- u32 hcc_params;
-- struct fotg210_qh_hw *hw;
--
-- spin_lock_init(&fotg210->lock);
--
-- /*
-- * keep io watchdog by default, those good HCDs could turn off it later
-- */
-- fotg210->need_io_watchdog = 1;
--
-- hrtimer_init(&fotg210->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
-- fotg210->hrtimer.function = fotg210_hrtimer_func;
-- fotg210->next_hrtimer_event = FOTG210_HRTIMER_NO_EVENT;
--
-- hcc_params = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
--
-- /*
-- * by default set standard 80% (== 100 usec/uframe) max periodic
-- * bandwidth as required by USB 2.0
-- */
-- fotg210->uframe_periodic_max = 100;
--
-- /*
-- * hw default: 1K periodic list heads, one per frame.
-- * periodic_size can shrink by USBCMD update if hcc_params allows.
-- */
-- fotg210->periodic_size = DEFAULT_I_TDPS;
-- INIT_LIST_HEAD(&fotg210->intr_qh_list);
-- INIT_LIST_HEAD(&fotg210->cached_itd_list);
--
-- if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
-- /* periodic schedule size can be smaller than default */
-- switch (FOTG210_TUNE_FLS) {
-- case 0:
-- fotg210->periodic_size = 1024;
-- break;
-- case 1:
-- fotg210->periodic_size = 512;
-- break;
-- case 2:
-- fotg210->periodic_size = 256;
-- break;
-- default:
-- BUG();
-- }
-- }
-- retval = fotg210_mem_init(fotg210, GFP_KERNEL);
-- if (retval < 0)
-- return retval;
--
-- /* controllers may cache some of the periodic schedule ... */
-- fotg210->i_thresh = 2;
--
-- /*
-- * dedicate a qh for the async ring head, since we couldn't unlink
-- * a 'real' qh without stopping the async schedule [4.8]. use it
-- * as the 'reclamation list head' too.
-- * its dummy is used in hw_alt_next of many tds, to prevent the qh
-- * from automatically advancing to the next td after short reads.
-- */
-- fotg210->async->qh_next.qh = NULL;
-- hw = fotg210->async->hw;
-- hw->hw_next = QH_NEXT(fotg210, fotg210->async->qh_dma);
-- hw->hw_info1 = cpu_to_hc32(fotg210, QH_HEAD);
-- hw->hw_token = cpu_to_hc32(fotg210, QTD_STS_HALT);
-- hw->hw_qtd_next = FOTG210_LIST_END(fotg210);
-- fotg210->async->qh_state = QH_STATE_LINKED;
-- hw->hw_alt_next = QTD_NEXT(fotg210, fotg210->async->dummy->qtd_dma);
--
-- /* clear interrupt enables, set irq latency */
-- if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
-- log2_irq_thresh = 0;
-- temp = 1 << (16 + log2_irq_thresh);
-- if (HCC_CANPARK(hcc_params)) {
-- /* HW default park == 3, on hardware that supports it (like
-- * NVidia and ALI silicon), maximizes throughput on the async
-- * schedule by avoiding QH fetches between transfers.
-- *
-- * With fast usb storage devices and NForce2, "park" seems to
-- * make problems: throughput reduction (!), data errors...
-- */
-- if (park) {
-- park = min_t(unsigned, park, 3);
-- temp |= CMD_PARK;
-- temp |= park << 8;
-- }
-- fotg210_dbg(fotg210, "park %d\n", park);
-- }
-- if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
-- /* periodic schedule size can be smaller than default */
-- temp &= ~(3 << 2);
-- temp |= (FOTG210_TUNE_FLS << 2);
-- }
-- fotg210->command = temp;
--
-- /* Accept arbitrarily long scatter-gather lists */
-- if (!hcd->localmem_pool)
-- hcd->self.sg_tablesize = ~0;
-- return 0;
--}
--
--/* start HC running; it's halted, hcd_fotg210_init() has been run (once) */
--static int fotg210_run(struct usb_hcd *hcd)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-- u32 temp;
--
-- hcd->uses_new_polling = 1;
--
-- /* EHCI spec section 4.1 */
--
-- fotg210_writel(fotg210, fotg210->periodic_dma,
-- &fotg210->regs->frame_list);
-- fotg210_writel(fotg210, (u32)fotg210->async->qh_dma,
-- &fotg210->regs->async_next);
--
-- /*
-- * hcc_params controls whether fotg210->regs->segment must (!!!)
-- * be used; it constrains QH/ITD/SITD and QTD locations.
-- * dma_pool consistent memory always uses segment zero.
-- * streaming mappings for I/O buffers, like dma_map_single(),
-- * can return segments above 4GB, if the device allows.
-- *
-- * NOTE: the dma mask is visible through dev->dma_mask, so
-- * drivers can pass this info along ... like NETIF_F_HIGHDMA,
-- * Scsi_Host.highmem_io, and so forth. It's readonly to all
-- * host side drivers though.
-- */
-- fotg210_readl(fotg210, &fotg210->caps->hcc_params);
--
-- /*
-- * Philips, Intel, and maybe others need CMD_RUN before the
-- * root hub will detect new devices (why?); NEC doesn't
-- */
-- fotg210->command &= ~(CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
-- fotg210->command |= CMD_RUN;
-- fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-- dbg_cmd(fotg210, "init", fotg210->command);
--
-- /*
-- * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
-- * are explicitly handed to companion controller(s), so no TT is
-- * involved with the root hub. (Except where one is integrated,
-- * and there's no companion controller unless maybe for USB OTG.)
-- *
-- * Turning on the CF flag will transfer ownership of all ports
-- * from the companions to the EHCI controller. If any of the
-- * companions are in the middle of a port reset at the time, it
-- * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
-- * guarantees that no resets are in progress. After we set CF,
-- * a short delay lets the hardware catch up; new resets shouldn't
-- * be started before the port switching actions could complete.
-- */
-- down_write(&ehci_cf_port_reset_rwsem);
-- fotg210->rh_state = FOTG210_RH_RUNNING;
-- /* unblock posted writes */
-- fotg210_readl(fotg210, &fotg210->regs->command);
-- usleep_range(5000, 10000);
-- up_write(&ehci_cf_port_reset_rwsem);
-- fotg210->last_periodic_enable = ktime_get_real();
--
-- temp = HC_VERSION(fotg210,
-- fotg210_readl(fotg210, &fotg210->caps->hc_capbase));
-- fotg210_info(fotg210,
-- "USB %x.%x started, EHCI %x.%02x\n",
-- ((fotg210->sbrn & 0xf0) >> 4), (fotg210->sbrn & 0x0f),
-- temp >> 8, temp & 0xff);
--
-- fotg210_writel(fotg210, INTR_MASK,
-- &fotg210->regs->intr_enable); /* Turn On Interrupts */
--
-- /* GRR this is run-once init(), being done every time the HC starts.
-- * So long as they're part of class devices, we can't do it init()
-- * since the class device isn't created that early.
-- */
-- create_debug_files(fotg210);
-- create_sysfs_files(fotg210);
--
-- return 0;
--}
--
--static int fotg210_setup(struct usb_hcd *hcd)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-- int retval;
--
-- fotg210->regs = (void __iomem *)fotg210->caps +
-- HC_LENGTH(fotg210,
-- fotg210_readl(fotg210, &fotg210->caps->hc_capbase));
-- dbg_hcs_params(fotg210, "reset");
-- dbg_hcc_params(fotg210, "reset");
--
-- /* cache this readonly data; minimize chip reads */
-- fotg210->hcs_params = fotg210_readl(fotg210,
-- &fotg210->caps->hcs_params);
--
-- fotg210->sbrn = HCD_USB2;
--
-- /* data structure init */
-- retval = hcd_fotg210_init(hcd);
-- if (retval)
-- return retval;
--
-- retval = fotg210_halt(fotg210);
-- if (retval)
-- return retval;
--
-- fotg210_reset(fotg210);
--
-- return 0;
--}
--
--static irqreturn_t fotg210_irq(struct usb_hcd *hcd)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-- u32 status, masked_status, pcd_status = 0, cmd;
-- int bh;
--
-- spin_lock(&fotg210->lock);
--
-- status = fotg210_readl(fotg210, &fotg210->regs->status);
--
-- /* e.g. cardbus physical eject */
-- if (status == ~(u32) 0) {
-- fotg210_dbg(fotg210, "device removed\n");
-- goto dead;
-- }
--
-- /*
-- * We don't use STS_FLR, but some controllers don't like it to
-- * remain on, so mask it out along with the other status bits.
-- */
-- masked_status = status & (INTR_MASK | STS_FLR);
--
-- /* Shared IRQ? */
-- if (!masked_status ||
-- unlikely(fotg210->rh_state == FOTG210_RH_HALTED)) {
-- spin_unlock(&fotg210->lock);
-- return IRQ_NONE;
-- }
--
-- /* clear (just) interrupts */
-- fotg210_writel(fotg210, masked_status, &fotg210->regs->status);
-- cmd = fotg210_readl(fotg210, &fotg210->regs->command);
-- bh = 0;
--
-- /* unrequested/ignored: Frame List Rollover */
-- dbg_status(fotg210, "irq", status);
--
-- /* INT, ERR, and IAA interrupt rates can be throttled */
--
-- /* normal [4.15.1.2] or error [4.15.1.1] completion */
-- if (likely((status & (STS_INT|STS_ERR)) != 0)) {
-- if (likely((status & STS_ERR) == 0))
-- INCR(fotg210->stats.normal);
-- else
-- INCR(fotg210->stats.error);
-- bh = 1;
-- }
--
-- /* complete the unlinking of some qh [4.15.2.3] */
-- if (status & STS_IAA) {
--
-- /* Turn off the IAA watchdog */
-- fotg210->enabled_hrtimer_events &=
-- ~BIT(FOTG210_HRTIMER_IAA_WATCHDOG);
--
-- /*
-- * Mild optimization: Allow another IAAD to reset the
-- * hrtimer, if one occurs before the next expiration.
-- * In theory we could always cancel the hrtimer, but
-- * tests show that about half the time it will be reset
-- * for some other event anyway.
-- */
-- if (fotg210->next_hrtimer_event == FOTG210_HRTIMER_IAA_WATCHDOG)
-- ++fotg210->next_hrtimer_event;
--
-- /* guard against (alleged) silicon errata */
-- if (cmd & CMD_IAAD)
-- fotg210_dbg(fotg210, "IAA with IAAD still set?\n");
-- if (fotg210->async_iaa) {
-- INCR(fotg210->stats.iaa);
-- end_unlink_async(fotg210);
-- } else
-- fotg210_dbg(fotg210, "IAA with nothing unlinked?\n");
-- }
--
-- /* remote wakeup [4.3.1] */
-- if (status & STS_PCD) {
-- int pstatus;
-- u32 __iomem *status_reg = &fotg210->regs->port_status;
--
-- /* kick root hub later */
-- pcd_status = status;
--
-- /* resume root hub? */
-- if (fotg210->rh_state == FOTG210_RH_SUSPENDED)
-- usb_hcd_resume_root_hub(hcd);
--
-- pstatus = fotg210_readl(fotg210, status_reg);
--
-- if (test_bit(0, &fotg210->suspended_ports) &&
-- ((pstatus & PORT_RESUME) ||
-- !(pstatus & PORT_SUSPEND)) &&
-- (pstatus & PORT_PE) &&
-- fotg210->reset_done[0] == 0) {
--
-- /* start 20 msec resume signaling from this port,
-- * and make hub_wq collect PORT_STAT_C_SUSPEND to
-- * stop that signaling. Use 5 ms extra for safety,
-- * like usb_port_resume() does.
-- */
-- fotg210->reset_done[0] = jiffies + msecs_to_jiffies(25);
-- set_bit(0, &fotg210->resuming_ports);
-- fotg210_dbg(fotg210, "port 1 remote wakeup\n");
-- mod_timer(&hcd->rh_timer, fotg210->reset_done[0]);
-- }
-- }
--
-- /* PCI errors [4.15.2.4] */
-- if (unlikely((status & STS_FATAL) != 0)) {
-- fotg210_err(fotg210, "fatal error\n");
-- dbg_cmd(fotg210, "fatal", cmd);
-- dbg_status(fotg210, "fatal", status);
--dead:
-- usb_hc_died(hcd);
--
-- /* Don't let the controller do anything more */
-- fotg210->shutdown = true;
-- fotg210->rh_state = FOTG210_RH_STOPPING;
-- fotg210->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
-- fotg210_writel(fotg210, fotg210->command,
-- &fotg210->regs->command);
-- fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
-- fotg210_handle_controller_death(fotg210);
--
-- /* Handle completions when the controller stops */
-- bh = 0;
-- }
--
-- if (bh)
-- fotg210_work(fotg210);
-- spin_unlock(&fotg210->lock);
-- if (pcd_status)
-- usb_hcd_poll_rh_status(hcd);
-- return IRQ_HANDLED;
--}
--
--/* non-error returns are a promise to giveback() the urb later
-- * we drop ownership so next owner (or urb unlink) can get it
-- *
-- * urb + dev is in hcd.self.controller.urb_list
-- * we're queueing TDs onto software and hardware lists
-- *
-- * hcd-specific init for hcpriv hasn't been done yet
-- *
-- * NOTE: control, bulk, and interrupt share the same code to append TDs
-- * to a (possibly active) QH, and the same QH scanning code.
-- */
--static int fotg210_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
-- gfp_t mem_flags)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-- struct list_head qtd_list;
--
-- INIT_LIST_HEAD(&qtd_list);
--
-- switch (usb_pipetype(urb->pipe)) {
-- case PIPE_CONTROL:
-- /* qh_completions() code doesn't handle all the fault cases
-- * in multi-TD control transfers. Even 1KB is rare anyway.
-- */
-- if (urb->transfer_buffer_length > (16 * 1024))
-- return -EMSGSIZE;
-- fallthrough;
-- /* case PIPE_BULK: */
-- default:
-- if (!qh_urb_transaction(fotg210, urb, &qtd_list, mem_flags))
-- return -ENOMEM;
-- return submit_async(fotg210, urb, &qtd_list, mem_flags);
--
-- case PIPE_INTERRUPT:
-- if (!qh_urb_transaction(fotg210, urb, &qtd_list, mem_flags))
-- return -ENOMEM;
-- return intr_submit(fotg210, urb, &qtd_list, mem_flags);
--
-- case PIPE_ISOCHRONOUS:
-- return itd_submit(fotg210, urb, mem_flags);
-- }
--}
--
--/* remove from hardware lists
-- * completions normally happen asynchronously
-- */
--
--static int fotg210_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-- struct fotg210_qh *qh;
-- unsigned long flags;
-- int rc;
--
-- spin_lock_irqsave(&fotg210->lock, flags);
-- rc = usb_hcd_check_unlink_urb(hcd, urb, status);
-- if (rc)
-- goto done;
--
-- switch (usb_pipetype(urb->pipe)) {
-- /* case PIPE_CONTROL: */
-- /* case PIPE_BULK:*/
-- default:
-- qh = (struct fotg210_qh *) urb->hcpriv;
-- if (!qh)
-- break;
-- switch (qh->qh_state) {
-- case QH_STATE_LINKED:
-- case QH_STATE_COMPLETING:
-- start_unlink_async(fotg210, qh);
-- break;
-- case QH_STATE_UNLINK:
-- case QH_STATE_UNLINK_WAIT:
-- /* already started */
-- break;
-- case QH_STATE_IDLE:
-- /* QH might be waiting for a Clear-TT-Buffer */
-- qh_completions(fotg210, qh);
-- break;
-- }
-- break;
--
-- case PIPE_INTERRUPT:
-- qh = (struct fotg210_qh *) urb->hcpriv;
-- if (!qh)
-- break;
-- switch (qh->qh_state) {
-- case QH_STATE_LINKED:
-- case QH_STATE_COMPLETING:
-- start_unlink_intr(fotg210, qh);
-- break;
-- case QH_STATE_IDLE:
-- qh_completions(fotg210, qh);
-- break;
-- default:
-- fotg210_dbg(fotg210, "bogus qh %p state %d\n",
-- qh, qh->qh_state);
-- goto done;
-- }
-- break;
--
-- case PIPE_ISOCHRONOUS:
-- /* itd... */
--
-- /* wait till next completion, do it then. */
-- /* completion irqs can wait up to 1024 msec, */
-- break;
-- }
--done:
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- return rc;
--}
--
--/* bulk qh holds the data toggle */
--
--static void fotg210_endpoint_disable(struct usb_hcd *hcd,
-- struct usb_host_endpoint *ep)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-- unsigned long flags;
-- struct fotg210_qh *qh, *tmp;
--
-- /* ASSERT: any requests/urbs are being unlinked */
-- /* ASSERT: nobody can be submitting urbs for this any more */
--
--rescan:
-- spin_lock_irqsave(&fotg210->lock, flags);
-- qh = ep->hcpriv;
-- if (!qh)
-- goto done;
--
-- /* endpoints can be iso streams. for now, we don't
-- * accelerate iso completions ... so spin a while.
-- */
-- if (qh->hw == NULL) {
-- struct fotg210_iso_stream *stream = ep->hcpriv;
--
-- if (!list_empty(&stream->td_list))
-- goto idle_timeout;
--
-- /* BUG_ON(!list_empty(&stream->free_list)); */
-- kfree(stream);
-- goto done;
-- }
--
-- if (fotg210->rh_state < FOTG210_RH_RUNNING)
-- qh->qh_state = QH_STATE_IDLE;
-- switch (qh->qh_state) {
-- case QH_STATE_LINKED:
-- case QH_STATE_COMPLETING:
-- for (tmp = fotg210->async->qh_next.qh;
-- tmp && tmp != qh;
-- tmp = tmp->qh_next.qh)
-- continue;
-- /* periodic qh self-unlinks on empty, and a COMPLETING qh
-- * may already be unlinked.
-- */
-- if (tmp)
-- start_unlink_async(fotg210, qh);
-- fallthrough;
-- case QH_STATE_UNLINK: /* wait for hw to finish? */
-- case QH_STATE_UNLINK_WAIT:
--idle_timeout:
-- spin_unlock_irqrestore(&fotg210->lock, flags);
-- schedule_timeout_uninterruptible(1);
-- goto rescan;
-- case QH_STATE_IDLE: /* fully unlinked */
-- if (qh->clearing_tt)
-- goto idle_timeout;
-- if (list_empty(&qh->qtd_list)) {
-- qh_destroy(fotg210, qh);
-- break;
-- }
-- fallthrough;
-- default:
-- /* caller was supposed to have unlinked any requests;
-- * that's not our job. just leak this memory.
-- */
-- fotg210_err(fotg210, "qh %p (#%02x) state %d%s\n",
-- qh, ep->desc.bEndpointAddress, qh->qh_state,
-- list_empty(&qh->qtd_list) ? "" : "(has tds)");
-- break;
-- }
--done:
-- ep->hcpriv = NULL;
-- spin_unlock_irqrestore(&fotg210->lock, flags);
--}
--
--static void fotg210_endpoint_reset(struct usb_hcd *hcd,
-- struct usb_host_endpoint *ep)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-- struct fotg210_qh *qh;
-- int eptype = usb_endpoint_type(&ep->desc);
-- int epnum = usb_endpoint_num(&ep->desc);
-- int is_out = usb_endpoint_dir_out(&ep->desc);
-- unsigned long flags;
--
-- if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
-- return;
--
-- spin_lock_irqsave(&fotg210->lock, flags);
-- qh = ep->hcpriv;
--
-- /* For Bulk and Interrupt endpoints we maintain the toggle state
-- * in the hardware; the toggle bits in udev aren't used at all.
-- * When an endpoint is reset by usb_clear_halt() we must reset
-- * the toggle bit in the QH.
-- */
-- if (qh) {
-- usb_settoggle(qh->dev, epnum, is_out, 0);
-- if (!list_empty(&qh->qtd_list)) {
-- WARN_ONCE(1, "clear_halt for a busy endpoint\n");
-- } else if (qh->qh_state == QH_STATE_LINKED ||
-- qh->qh_state == QH_STATE_COMPLETING) {
--
-- /* The toggle value in the QH can't be updated
-- * while the QH is active. Unlink it now;
-- * re-linking will call qh_refresh().
-- */
-- if (eptype == USB_ENDPOINT_XFER_BULK)
-- start_unlink_async(fotg210, qh);
-- else
-- start_unlink_intr(fotg210, qh);
-- }
-- }
-- spin_unlock_irqrestore(&fotg210->lock, flags);
--}
--
--static int fotg210_get_frame(struct usb_hcd *hcd)
--{
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--
-- return (fotg210_read_frame_index(fotg210) >> 3) %
-- fotg210->periodic_size;
--}
--
--/* The EHCI in ChipIdea HDRC cannot be a separate module or device,
-- * because its registers (and irq) are shared between host/gadget/otg
-- * functions and in order to facilitate role switching we cannot
-- * give the fotg210 driver exclusive access to those.
-- */
--MODULE_DESCRIPTION(DRIVER_DESC);
--MODULE_AUTHOR(DRIVER_AUTHOR);
--MODULE_LICENSE("GPL");
--
--static const struct hc_driver fotg210_fotg210_hc_driver = {
-- .description = hcd_name,
-- .product_desc = "Faraday USB2.0 Host Controller",
-- .hcd_priv_size = sizeof(struct fotg210_hcd),
--
-- /*
-- * generic hardware linkage
-- */
-- .irq = fotg210_irq,
-- .flags = HCD_MEMORY | HCD_DMA | HCD_USB2,
--
-- /*
-- * basic lifecycle operations
-- */
-- .reset = hcd_fotg210_init,
-- .start = fotg210_run,
-- .stop = fotg210_stop,
-- .shutdown = fotg210_shutdown,
--
-- /*
-- * managing i/o requests and associated device resources
-- */
-- .urb_enqueue = fotg210_urb_enqueue,
-- .urb_dequeue = fotg210_urb_dequeue,
-- .endpoint_disable = fotg210_endpoint_disable,
-- .endpoint_reset = fotg210_endpoint_reset,
--
-- /*
-- * scheduling support
-- */
-- .get_frame_number = fotg210_get_frame,
--
-- /*
-- * root hub support
-- */
-- .hub_status_data = fotg210_hub_status_data,
-- .hub_control = fotg210_hub_control,
-- .bus_suspend = fotg210_bus_suspend,
-- .bus_resume = fotg210_bus_resume,
--
-- .relinquish_port = fotg210_relinquish_port,
-- .port_handed_over = fotg210_port_handed_over,
--
-- .clear_tt_buffer_complete = fotg210_clear_tt_buffer_complete,
--};
--
--static void fotg210_init(struct fotg210_hcd *fotg210)
--{
-- u32 value;
--
-- iowrite32(GMIR_MDEV_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
-- &fotg210->regs->gmir);
--
-- value = ioread32(&fotg210->regs->otgcsr);
-- value &= ~OTGCSR_A_BUS_DROP;
-- value |= OTGCSR_A_BUS_REQ;
-- iowrite32(value, &fotg210->regs->otgcsr);
--}
--
--/*
-- * fotg210_hcd_probe - initialize faraday FOTG210 HCDs
-- *
-- * Allocates basic resources for this USB host controller, and
-- * then invokes the start() method for the HCD associated with it
-- * through the hotplug entry's driver_data.
-- */
--static int fotg210_hcd_probe(struct platform_device *pdev)
--{
-- struct device *dev = &pdev->dev;
-- struct usb_hcd *hcd;
-- struct resource *res;
-- int irq;
-- int retval;
-- struct fotg210_hcd *fotg210;
--
-- if (usb_disabled())
-- return -ENODEV;
--
-- pdev->dev.power.power_state = PMSG_ON;
--
-- irq = platform_get_irq(pdev, 0);
-- if (irq < 0)
-- return irq;
--
-- hcd = usb_create_hcd(&fotg210_fotg210_hc_driver, dev,
-- dev_name(dev));
-- if (!hcd) {
-- dev_err(dev, "failed to create hcd\n");
-- retval = -ENOMEM;
-- goto fail_create_hcd;
-- }
--
-- hcd->has_tt = 1;
--
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- hcd->regs = devm_ioremap_resource(&pdev->dev, res);
-- if (IS_ERR(hcd->regs)) {
-- retval = PTR_ERR(hcd->regs);
-- goto failed_put_hcd;
-- }
--
-- hcd->rsrc_start = res->start;
-- hcd->rsrc_len = resource_size(res);
--
-- fotg210 = hcd_to_fotg210(hcd);
--
-- fotg210->caps = hcd->regs;
--
-- /* It's OK not to supply this clock */
-- fotg210->pclk = clk_get(dev, "PCLK");
-- if (!IS_ERR(fotg210->pclk)) {
-- retval = clk_prepare_enable(fotg210->pclk);
-- if (retval) {
-- dev_err(dev, "failed to enable PCLK\n");
-- goto failed_put_hcd;
-- }
-- } else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
-- /*
-- * Percolate deferrals, for anything else,
-- * just live without the clocking.
-- */
-- retval = PTR_ERR(fotg210->pclk);
-- goto failed_dis_clk;
-- }
--
-- retval = fotg210_setup(hcd);
-- if (retval)
-- goto failed_dis_clk;
--
-- fotg210_init(fotg210);
--
-- retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
-- if (retval) {
-- dev_err(dev, "failed to add hcd with err %d\n", retval);
-- goto failed_dis_clk;
-- }
-- device_wakeup_enable(hcd->self.controller);
-- platform_set_drvdata(pdev, hcd);
--
-- return retval;
--
--failed_dis_clk:
-- if (!IS_ERR(fotg210->pclk)) {
-- clk_disable_unprepare(fotg210->pclk);
-- clk_put(fotg210->pclk);
-- }
--failed_put_hcd:
-- usb_put_hcd(hcd);
--fail_create_hcd:
-- dev_err(dev, "init %s fail, %d\n", dev_name(dev), retval);
-- return retval;
--}
--
--/*
-- * fotg210_hcd_remove - shutdown processing for EHCI HCDs
-- * @dev: USB Host Controller being removed
-- *
-- */
--static int fotg210_hcd_remove(struct platform_device *pdev)
--{
-- struct usb_hcd *hcd = platform_get_drvdata(pdev);
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--
-- if (!IS_ERR(fotg210->pclk)) {
-- clk_disable_unprepare(fotg210->pclk);
-- clk_put(fotg210->pclk);
-- }
--
-- usb_remove_hcd(hcd);
-- usb_put_hcd(hcd);
--
-- return 0;
--}
--
--#ifdef CONFIG_OF
--static const struct of_device_id fotg210_of_match[] = {
-- { .compatible = "faraday,fotg210" },
-- {},
--};
--MODULE_DEVICE_TABLE(of, fotg210_of_match);
--#endif
--
--static struct platform_driver fotg210_hcd_driver = {
-- .driver = {
-- .name = "fotg210-hcd",
-- .of_match_table = of_match_ptr(fotg210_of_match),
-- },
-- .probe = fotg210_hcd_probe,
-- .remove = fotg210_hcd_remove,
--};
--
--static int __init fotg210_hcd_init(void)
--{
-- int retval = 0;
--
-- if (usb_disabled())
-- return -ENODEV;
--
-- set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
-- if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
-- test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
-- pr_warn("Warning! fotg210_hcd should always be loaded before uhci_hcd and ohci_hcd, not after\n");
--
-- pr_debug("%s: block sizes: qh %zd qtd %zd itd %zd\n",
-- hcd_name, sizeof(struct fotg210_qh),
-- sizeof(struct fotg210_qtd),
-- sizeof(struct fotg210_itd));
--
-- fotg210_debug_root = debugfs_create_dir("fotg210", usb_debug_root);
--
-- retval = platform_driver_register(&fotg210_hcd_driver);
-- if (retval < 0)
-- goto clean;
-- return retval;
--
--clean:
-- debugfs_remove(fotg210_debug_root);
-- fotg210_debug_root = NULL;
--
-- clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
-- return retval;
--}
--module_init(fotg210_hcd_init);
--
--static void __exit fotg210_hcd_cleanup(void)
--{
-- platform_driver_unregister(&fotg210_hcd_driver);
-- debugfs_remove(fotg210_debug_root);
-- clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
--}
--module_exit(fotg210_hcd_cleanup);
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210-hcd.c
-@@ -0,0 +1,5727 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/* Faraday FOTG210 EHCI-like driver
-+ *
-+ * Copyright (c) 2013 Faraday Technology Corporation
-+ *
-+ * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-+ * Feng-Hsin Chiang <john453@faraday-tech.com>
-+ * Po-Yu Chuang <ratbert.chuang@gmail.com>
-+ *
-+ * Most of code borrowed from the Linux-3.7 EHCI driver
-+ */
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/device.h>
-+#include <linux/dmapool.h>
-+#include <linux/kernel.h>
-+#include <linux/delay.h>
-+#include <linux/ioport.h>
-+#include <linux/sched.h>
-+#include <linux/vmalloc.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/hrtimer.h>
-+#include <linux/list.h>
-+#include <linux/interrupt.h>
-+#include <linux/usb.h>
-+#include <linux/usb/hcd.h>
-+#include <linux/moduleparam.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/debugfs.h>
-+#include <linux/slab.h>
-+#include <linux/uaccess.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/clk.h>
-+
-+#include <asm/byteorder.h>
-+#include <asm/irq.h>
-+#include <asm/unaligned.h>
-+
-+#define DRIVER_AUTHOR "Yuan-Hsin Chen"
-+#define DRIVER_DESC "FOTG210 Host Controller (EHCI) Driver"
-+static const char hcd_name[] = "fotg210_hcd";
-+
-+#undef FOTG210_URB_TRACE
-+#define FOTG210_STATS
-+
-+/* magic numbers that can affect system performance */
-+#define FOTG210_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
-+#define FOTG210_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
-+#define FOTG210_TUNE_RL_TT 0
-+#define FOTG210_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
-+#define FOTG210_TUNE_MULT_TT 1
-+
-+/* Some drivers think it's safe to schedule isochronous transfers more than 256
-+ * ms into the future (partly as a result of an old bug in the scheduling
-+ * code). In an attempt to avoid trouble, we will use a minimum scheduling
-+ * length of 512 frames instead of 256.
-+ */
-+#define FOTG210_TUNE_FLS 1 /* (medium) 512-frame schedule */
-+
-+/* Initial IRQ latency: faster than hw default */
-+static int log2_irq_thresh; /* 0 to 6 */
-+module_param(log2_irq_thresh, int, S_IRUGO);
-+MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
-+
-+/* initial park setting: slower than hw default */
-+static unsigned park;
-+module_param(park, uint, S_IRUGO);
-+MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets");
-+
-+/* for link power management(LPM) feature */
-+static unsigned int hird;
-+module_param(hird, int, S_IRUGO);
-+MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
-+
-+#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
-+
-+#include "fotg210-hcd.h"
-+
-+#define fotg210_dbg(fotg210, fmt, args...) \
-+ dev_dbg(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
-+#define fotg210_err(fotg210, fmt, args...) \
-+ dev_err(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
-+#define fotg210_info(fotg210, fmt, args...) \
-+ dev_info(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
-+#define fotg210_warn(fotg210, fmt, args...) \
-+ dev_warn(fotg210_to_hcd(fotg210)->self.controller, fmt, ## args)
-+
-+/* check the values in the HCSPARAMS register (host controller _Structural_
-+ * parameters) see EHCI spec, Table 2-4 for each value
-+ */
-+static void dbg_hcs_params(struct fotg210_hcd *fotg210, char *label)
-+{
-+ u32 params = fotg210_readl(fotg210, &fotg210->caps->hcs_params);
-+
-+ fotg210_dbg(fotg210, "%s hcs_params 0x%x ports=%d\n", label, params,
-+ HCS_N_PORTS(params));
-+}
-+
-+/* check the values in the HCCPARAMS register (host controller _Capability_
-+ * parameters) see EHCI Spec, Table 2-5 for each value
-+ */
-+static void dbg_hcc_params(struct fotg210_hcd *fotg210, char *label)
-+{
-+ u32 params = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
-+
-+ fotg210_dbg(fotg210, "%s hcc_params %04x uframes %s%s\n", label,
-+ params,
-+ HCC_PGM_FRAMELISTLEN(params) ? "256/512/1024" : "1024",
-+ HCC_CANPARK(params) ? " park" : "");
-+}
-+
-+static void __maybe_unused
-+dbg_qtd(const char *label, struct fotg210_hcd *fotg210, struct fotg210_qtd *qtd)
-+{
-+ fotg210_dbg(fotg210, "%s td %p n%08x %08x t%08x p0=%08x\n", label, qtd,
-+ hc32_to_cpup(fotg210, &qtd->hw_next),
-+ hc32_to_cpup(fotg210, &qtd->hw_alt_next),
-+ hc32_to_cpup(fotg210, &qtd->hw_token),
-+ hc32_to_cpup(fotg210, &qtd->hw_buf[0]));
-+ if (qtd->hw_buf[1])
-+ fotg210_dbg(fotg210, " p1=%08x p2=%08x p3=%08x p4=%08x\n",
-+ hc32_to_cpup(fotg210, &qtd->hw_buf[1]),
-+ hc32_to_cpup(fotg210, &qtd->hw_buf[2]),
-+ hc32_to_cpup(fotg210, &qtd->hw_buf[3]),
-+ hc32_to_cpup(fotg210, &qtd->hw_buf[4]));
-+}
-+
-+static void __maybe_unused
-+dbg_qh(const char *label, struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+ struct fotg210_qh_hw *hw = qh->hw;
-+
-+ fotg210_dbg(fotg210, "%s qh %p n%08x info %x %x qtd %x\n", label, qh,
-+ hw->hw_next, hw->hw_info1, hw->hw_info2,
-+ hw->hw_current);
-+
-+ dbg_qtd("overlay", fotg210, (struct fotg210_qtd *) &hw->hw_qtd_next);
-+}
-+
-+static void __maybe_unused
-+dbg_itd(const char *label, struct fotg210_hcd *fotg210, struct fotg210_itd *itd)
-+{
-+ fotg210_dbg(fotg210, "%s[%d] itd %p, next %08x, urb %p\n", label,
-+ itd->frame, itd, hc32_to_cpu(fotg210, itd->hw_next),
-+ itd->urb);
-+
-+ fotg210_dbg(fotg210,
-+ " trans: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-+ hc32_to_cpu(fotg210, itd->hw_transaction[0]),
-+ hc32_to_cpu(fotg210, itd->hw_transaction[1]),
-+ hc32_to_cpu(fotg210, itd->hw_transaction[2]),
-+ hc32_to_cpu(fotg210, itd->hw_transaction[3]),
-+ hc32_to_cpu(fotg210, itd->hw_transaction[4]),
-+ hc32_to_cpu(fotg210, itd->hw_transaction[5]),
-+ hc32_to_cpu(fotg210, itd->hw_transaction[6]),
-+ hc32_to_cpu(fotg210, itd->hw_transaction[7]));
-+
-+ fotg210_dbg(fotg210,
-+ " buf: %08x %08x %08x %08x %08x %08x %08x\n",
-+ hc32_to_cpu(fotg210, itd->hw_bufp[0]),
-+ hc32_to_cpu(fotg210, itd->hw_bufp[1]),
-+ hc32_to_cpu(fotg210, itd->hw_bufp[2]),
-+ hc32_to_cpu(fotg210, itd->hw_bufp[3]),
-+ hc32_to_cpu(fotg210, itd->hw_bufp[4]),
-+ hc32_to_cpu(fotg210, itd->hw_bufp[5]),
-+ hc32_to_cpu(fotg210, itd->hw_bufp[6]));
-+
-+ fotg210_dbg(fotg210, " index: %d %d %d %d %d %d %d %d\n",
-+ itd->index[0], itd->index[1], itd->index[2],
-+ itd->index[3], itd->index[4], itd->index[5],
-+ itd->index[6], itd->index[7]);
-+}
-+
-+static int __maybe_unused
-+dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
-+{
-+ return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
-+ label, label[0] ? " " : "", status,
-+ (status & STS_ASS) ? " Async" : "",
-+ (status & STS_PSS) ? " Periodic" : "",
-+ (status & STS_RECL) ? " Recl" : "",
-+ (status & STS_HALT) ? " Halt" : "",
-+ (status & STS_IAA) ? " IAA" : "",
-+ (status & STS_FATAL) ? " FATAL" : "",
-+ (status & STS_FLR) ? " FLR" : "",
-+ (status & STS_PCD) ? " PCD" : "",
-+ (status & STS_ERR) ? " ERR" : "",
-+ (status & STS_INT) ? " INT" : "");
-+}
-+
-+static int __maybe_unused
-+dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
-+{
-+ return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s",
-+ label, label[0] ? " " : "", enable,
-+ (enable & STS_IAA) ? " IAA" : "",
-+ (enable & STS_FATAL) ? " FATAL" : "",
-+ (enable & STS_FLR) ? " FLR" : "",
-+ (enable & STS_PCD) ? " PCD" : "",
-+ (enable & STS_ERR) ? " ERR" : "",
-+ (enable & STS_INT) ? " INT" : "");
-+}
-+
-+static const char *const fls_strings[] = { "1024", "512", "256", "??" };
-+
-+static int dbg_command_buf(char *buf, unsigned len, const char *label,
-+ u32 command)
-+{
-+ return scnprintf(buf, len,
-+ "%s%scommand %07x %s=%d ithresh=%d%s%s%s period=%s%s %s",
-+ label, label[0] ? " " : "", command,
-+ (command & CMD_PARK) ? " park" : "(park)",
-+ CMD_PARK_CNT(command),
-+ (command >> 16) & 0x3f,
-+ (command & CMD_IAAD) ? " IAAD" : "",
-+ (command & CMD_ASE) ? " Async" : "",
-+ (command & CMD_PSE) ? " Periodic" : "",
-+ fls_strings[(command >> 2) & 0x3],
-+ (command & CMD_RESET) ? " Reset" : "",
-+ (command & CMD_RUN) ? "RUN" : "HALT");
-+}
-+
-+static char *dbg_port_buf(char *buf, unsigned len, const char *label, int port,
-+ u32 status)
-+{
-+ char *sig;
-+
-+ /* signaling state */
-+ switch (status & (3 << 10)) {
-+ case 0 << 10:
-+ sig = "se0";
-+ break;
-+ case 1 << 10:
-+ sig = "k";
-+ break; /* low speed */
-+ case 2 << 10:
-+ sig = "j";
-+ break;
-+ default:
-+ sig = "?";
-+ break;
-+ }
-+
-+ scnprintf(buf, len, "%s%sport:%d status %06x %d sig=%s%s%s%s%s%s%s%s",
-+ label, label[0] ? " " : "", port, status,
-+ status >> 25, /*device address */
-+ sig,
-+ (status & PORT_RESET) ? " RESET" : "",
-+ (status & PORT_SUSPEND) ? " SUSPEND" : "",
-+ (status & PORT_RESUME) ? " RESUME" : "",
-+ (status & PORT_PEC) ? " PEC" : "",
-+ (status & PORT_PE) ? " PE" : "",
-+ (status & PORT_CSC) ? " CSC" : "",
-+ (status & PORT_CONNECT) ? " CONNECT" : "");
-+
-+ return buf;
-+}
-+
-+/* functions have the "wrong" filename when they're output... */
-+#define dbg_status(fotg210, label, status) { \
-+ char _buf[80]; \
-+ dbg_status_buf(_buf, sizeof(_buf), label, status); \
-+ fotg210_dbg(fotg210, "%s\n", _buf); \
-+}
-+
-+#define dbg_cmd(fotg210, label, command) { \
-+ char _buf[80]; \
-+ dbg_command_buf(_buf, sizeof(_buf), label, command); \
-+ fotg210_dbg(fotg210, "%s\n", _buf); \
-+}
-+
-+#define dbg_port(fotg210, label, port, status) { \
-+ char _buf[80]; \
-+ fotg210_dbg(fotg210, "%s\n", \
-+ dbg_port_buf(_buf, sizeof(_buf), label, port, status));\
-+}
-+
-+/* troubleshooting help: expose state in debugfs */
-+static int debug_async_open(struct inode *, struct file *);
-+static int debug_periodic_open(struct inode *, struct file *);
-+static int debug_registers_open(struct inode *, struct file *);
-+static int debug_async_open(struct inode *, struct file *);
-+
-+static ssize_t debug_output(struct file*, char __user*, size_t, loff_t*);
-+static int debug_close(struct inode *, struct file *);
-+
-+static const struct file_operations debug_async_fops = {
-+ .owner = THIS_MODULE,
-+ .open = debug_async_open,
-+ .read = debug_output,
-+ .release = debug_close,
-+ .llseek = default_llseek,
-+};
-+static const struct file_operations debug_periodic_fops = {
-+ .owner = THIS_MODULE,
-+ .open = debug_periodic_open,
-+ .read = debug_output,
-+ .release = debug_close,
-+ .llseek = default_llseek,
-+};
-+static const struct file_operations debug_registers_fops = {
-+ .owner = THIS_MODULE,
-+ .open = debug_registers_open,
-+ .read = debug_output,
-+ .release = debug_close,
-+ .llseek = default_llseek,
-+};
-+
-+static struct dentry *fotg210_debug_root;
-+
-+struct debug_buffer {
-+ ssize_t (*fill_func)(struct debug_buffer *); /* fill method */
-+ struct usb_bus *bus;
-+ struct mutex mutex; /* protect filling of buffer */
-+ size_t count; /* number of characters filled into buffer */
-+ char *output_buf;
-+ size_t alloc_size;
-+};
-+
-+static inline char speed_char(u32 scratch)
-+{
-+ switch (scratch & (3 << 12)) {
-+ case QH_FULL_SPEED:
-+ return 'f';
-+
-+ case QH_LOW_SPEED:
-+ return 'l';
-+
-+ case QH_HIGH_SPEED:
-+ return 'h';
-+
-+ default:
-+ return '?';
-+ }
-+}
-+
-+static inline char token_mark(struct fotg210_hcd *fotg210, __hc32 token)
-+{
-+ __u32 v = hc32_to_cpu(fotg210, token);
-+
-+ if (v & QTD_STS_ACTIVE)
-+ return '*';
-+ if (v & QTD_STS_HALT)
-+ return '-';
-+ if (!IS_SHORT_READ(v))
-+ return ' ';
-+ /* tries to advance through hw_alt_next */
-+ return '/';
-+}
-+
-+static void qh_lines(struct fotg210_hcd *fotg210, struct fotg210_qh *qh,
-+ char **nextp, unsigned *sizep)
-+{
-+ u32 scratch;
-+ u32 hw_curr;
-+ struct fotg210_qtd *td;
-+ unsigned temp;
-+ unsigned size = *sizep;
-+ char *next = *nextp;
-+ char mark;
-+ __le32 list_end = FOTG210_LIST_END(fotg210);
-+ struct fotg210_qh_hw *hw = qh->hw;
-+
-+ if (hw->hw_qtd_next == list_end) /* NEC does this */
-+ mark = '@';
-+ else
-+ mark = token_mark(fotg210, hw->hw_token);
-+ if (mark == '/') { /* qh_alt_next controls qh advance? */
-+ if ((hw->hw_alt_next & QTD_MASK(fotg210)) ==
-+ fotg210->async->hw->hw_alt_next)
-+ mark = '#'; /* blocked */
-+ else if (hw->hw_alt_next == list_end)
-+ mark = '.'; /* use hw_qtd_next */
-+ /* else alt_next points to some other qtd */
-+ }
-+ scratch = hc32_to_cpup(fotg210, &hw->hw_info1);
-+ hw_curr = (mark == '*') ? hc32_to_cpup(fotg210, &hw->hw_current) : 0;
-+ temp = scnprintf(next, size,
-+ "qh/%p dev%d %cs ep%d %08x %08x(%08x%c %s nak%d)",
-+ qh, scratch & 0x007f,
-+ speed_char(scratch),
-+ (scratch >> 8) & 0x000f,
-+ scratch, hc32_to_cpup(fotg210, &hw->hw_info2),
-+ hc32_to_cpup(fotg210, &hw->hw_token), mark,
-+ (cpu_to_hc32(fotg210, QTD_TOGGLE) & hw->hw_token)
-+ ? "data1" : "data0",
-+ (hc32_to_cpup(fotg210, &hw->hw_alt_next) >> 1) & 0x0f);
-+ size -= temp;
-+ next += temp;
-+
-+ /* hc may be modifying the list as we read it ... */
-+ list_for_each_entry(td, &qh->qtd_list, qtd_list) {
-+ scratch = hc32_to_cpup(fotg210, &td->hw_token);
-+ mark = ' ';
-+ if (hw_curr == td->qtd_dma)
-+ mark = '*';
-+ else if (hw->hw_qtd_next == cpu_to_hc32(fotg210, td->qtd_dma))
-+ mark = '+';
-+ else if (QTD_LENGTH(scratch)) {
-+ if (td->hw_alt_next == fotg210->async->hw->hw_alt_next)
-+ mark = '#';
-+ else if (td->hw_alt_next != list_end)
-+ mark = '/';
-+ }
-+ temp = snprintf(next, size,
-+ "\n\t%p%c%s len=%d %08x urb %p",
-+ td, mark, ({ char *tmp;
-+ switch ((scratch>>8)&0x03) {
-+ case 0:
-+ tmp = "out";
-+ break;
-+ case 1:
-+ tmp = "in";
-+ break;
-+ case 2:
-+ tmp = "setup";
-+ break;
-+ default:
-+ tmp = "?";
-+ break;
-+ } tmp; }),
-+ (scratch >> 16) & 0x7fff,
-+ scratch,
-+ td->urb);
-+ if (size < temp)
-+ temp = size;
-+ size -= temp;
-+ next += temp;
-+ if (temp == size)
-+ goto done;
-+ }
-+
-+ temp = snprintf(next, size, "\n");
-+ if (size < temp)
-+ temp = size;
-+
-+ size -= temp;
-+ next += temp;
-+
-+done:
-+ *sizep = size;
-+ *nextp = next;
-+}
-+
-+static ssize_t fill_async_buffer(struct debug_buffer *buf)
-+{
-+ struct usb_hcd *hcd;
-+ struct fotg210_hcd *fotg210;
-+ unsigned long flags;
-+ unsigned temp, size;
-+ char *next;
-+ struct fotg210_qh *qh;
-+
-+ hcd = bus_to_hcd(buf->bus);
-+ fotg210 = hcd_to_fotg210(hcd);
-+ next = buf->output_buf;
-+ size = buf->alloc_size;
-+
-+ *next = 0;
-+
-+ /* dumps a snapshot of the async schedule.
-+ * usually empty except for long-term bulk reads, or head.
-+ * one QH per line, and TDs we know about
-+ */
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ for (qh = fotg210->async->qh_next.qh; size > 0 && qh;
-+ qh = qh->qh_next.qh)
-+ qh_lines(fotg210, qh, &next, &size);
-+ if (fotg210->async_unlink && size > 0) {
-+ temp = scnprintf(next, size, "\nunlink =\n");
-+ size -= temp;
-+ next += temp;
-+
-+ for (qh = fotg210->async_unlink; size > 0 && qh;
-+ qh = qh->unlink_next)
-+ qh_lines(fotg210, qh, &next, &size);
-+ }
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+
-+ return strlen(buf->output_buf);
-+}
-+
-+/* count tds, get ep direction */
-+static unsigned output_buf_tds_dir(char *buf, struct fotg210_hcd *fotg210,
-+ struct fotg210_qh_hw *hw, struct fotg210_qh *qh, unsigned size)
-+{
-+ u32 scratch = hc32_to_cpup(fotg210, &hw->hw_info1);
-+ struct fotg210_qtd *qtd;
-+ char *type = "";
-+ unsigned temp = 0;
-+
-+ /* count tds, get ep direction */
-+ list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
-+ temp++;
-+ switch ((hc32_to_cpu(fotg210, qtd->hw_token) >> 8) & 0x03) {
-+ case 0:
-+ type = "out";
-+ continue;
-+ case 1:
-+ type = "in";
-+ continue;
-+ }
-+ }
-+
-+ return scnprintf(buf, size, "(%c%d ep%d%s [%d/%d] q%d p%d)",
-+ speed_char(scratch), scratch & 0x007f,
-+ (scratch >> 8) & 0x000f, type, qh->usecs,
-+ qh->c_usecs, temp, (scratch >> 16) & 0x7ff);
-+}
-+
-+#define DBG_SCHED_LIMIT 64
-+static ssize_t fill_periodic_buffer(struct debug_buffer *buf)
-+{
-+ struct usb_hcd *hcd;
-+ struct fotg210_hcd *fotg210;
-+ unsigned long flags;
-+ union fotg210_shadow p, *seen;
-+ unsigned temp, size, seen_count;
-+ char *next;
-+ unsigned i;
-+ __hc32 tag;
-+
-+ seen = kmalloc_array(DBG_SCHED_LIMIT, sizeof(*seen), GFP_ATOMIC);
-+ if (!seen)
-+ return 0;
-+
-+ seen_count = 0;
-+
-+ hcd = bus_to_hcd(buf->bus);
-+ fotg210 = hcd_to_fotg210(hcd);
-+ next = buf->output_buf;
-+ size = buf->alloc_size;
-+
-+ temp = scnprintf(next, size, "size = %d\n", fotg210->periodic_size);
-+ size -= temp;
-+ next += temp;
-+
-+ /* dump a snapshot of the periodic schedule.
-+ * iso changes, interrupt usually doesn't.
-+ */
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ for (i = 0; i < fotg210->periodic_size; i++) {
-+ p = fotg210->pshadow[i];
-+ if (likely(!p.ptr))
-+ continue;
-+
-+ tag = Q_NEXT_TYPE(fotg210, fotg210->periodic[i]);
-+
-+ temp = scnprintf(next, size, "%4d: ", i);
-+ size -= temp;
-+ next += temp;
-+
-+ do {
-+ struct fotg210_qh_hw *hw;
-+
-+ switch (hc32_to_cpu(fotg210, tag)) {
-+ case Q_TYPE_QH:
-+ hw = p.qh->hw;
-+ temp = scnprintf(next, size, " qh%d-%04x/%p",
-+ p.qh->period,
-+ hc32_to_cpup(fotg210,
-+ &hw->hw_info2)
-+ /* uframe masks */
-+ & (QH_CMASK | QH_SMASK),
-+ p.qh);
-+ size -= temp;
-+ next += temp;
-+ /* don't repeat what follows this qh */
-+ for (temp = 0; temp < seen_count; temp++) {
-+ if (seen[temp].ptr != p.ptr)
-+ continue;
-+ if (p.qh->qh_next.ptr) {
-+ temp = scnprintf(next, size,
-+ " ...");
-+ size -= temp;
-+ next += temp;
-+ }
-+ break;
-+ }
-+ /* show more info the first time around */
-+ if (temp == seen_count) {
-+ temp = output_buf_tds_dir(next,
-+ fotg210, hw,
-+ p.qh, size);
-+
-+ if (seen_count < DBG_SCHED_LIMIT)
-+ seen[seen_count++].qh = p.qh;
-+ } else
-+ temp = 0;
-+ tag = Q_NEXT_TYPE(fotg210, hw->hw_next);
-+ p = p.qh->qh_next;
-+ break;
-+ case Q_TYPE_FSTN:
-+ temp = scnprintf(next, size,
-+ " fstn-%8x/%p",
-+ p.fstn->hw_prev, p.fstn);
-+ tag = Q_NEXT_TYPE(fotg210, p.fstn->hw_next);
-+ p = p.fstn->fstn_next;
-+ break;
-+ case Q_TYPE_ITD:
-+ temp = scnprintf(next, size,
-+ " itd/%p", p.itd);
-+ tag = Q_NEXT_TYPE(fotg210, p.itd->hw_next);
-+ p = p.itd->itd_next;
-+ break;
-+ }
-+ size -= temp;
-+ next += temp;
-+ } while (p.ptr);
-+
-+ temp = scnprintf(next, size, "\n");
-+ size -= temp;
-+ next += temp;
-+ }
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ kfree(seen);
-+
-+ return buf->alloc_size - size;
-+}
-+#undef DBG_SCHED_LIMIT
-+
-+static const char *rh_state_string(struct fotg210_hcd *fotg210)
-+{
-+ switch (fotg210->rh_state) {
-+ case FOTG210_RH_HALTED:
-+ return "halted";
-+ case FOTG210_RH_SUSPENDED:
-+ return "suspended";
-+ case FOTG210_RH_RUNNING:
-+ return "running";
-+ case FOTG210_RH_STOPPING:
-+ return "stopping";
-+ }
-+ return "?";
-+}
-+
-+static ssize_t fill_registers_buffer(struct debug_buffer *buf)
-+{
-+ struct usb_hcd *hcd;
-+ struct fotg210_hcd *fotg210;
-+ unsigned long flags;
-+ unsigned temp, size, i;
-+ char *next, scratch[80];
-+ static const char fmt[] = "%*s\n";
-+ static const char label[] = "";
-+
-+ hcd = bus_to_hcd(buf->bus);
-+ fotg210 = hcd_to_fotg210(hcd);
-+ next = buf->output_buf;
-+ size = buf->alloc_size;
-+
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+
-+ if (!HCD_HW_ACCESSIBLE(hcd)) {
-+ size = scnprintf(next, size,
-+ "bus %s, device %s\n"
-+ "%s\n"
-+ "SUSPENDED(no register access)\n",
-+ hcd->self.controller->bus->name,
-+ dev_name(hcd->self.controller),
-+ hcd->product_desc);
-+ goto done;
-+ }
-+
-+ /* Capability Registers */
-+ i = HC_VERSION(fotg210, fotg210_readl(fotg210,
-+ &fotg210->caps->hc_capbase));
-+ temp = scnprintf(next, size,
-+ "bus %s, device %s\n"
-+ "%s\n"
-+ "EHCI %x.%02x, rh state %s\n",
-+ hcd->self.controller->bus->name,
-+ dev_name(hcd->self.controller),
-+ hcd->product_desc,
-+ i >> 8, i & 0x0ff, rh_state_string(fotg210));
-+ size -= temp;
-+ next += temp;
-+
-+ /* FIXME interpret both types of params */
-+ i = fotg210_readl(fotg210, &fotg210->caps->hcs_params);
-+ temp = scnprintf(next, size, "structural params 0x%08x\n", i);
-+ size -= temp;
-+ next += temp;
-+
-+ i = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
-+ temp = scnprintf(next, size, "capability params 0x%08x\n", i);
-+ size -= temp;
-+ next += temp;
-+
-+ /* Operational Registers */
-+ temp = dbg_status_buf(scratch, sizeof(scratch), label,
-+ fotg210_readl(fotg210, &fotg210->regs->status));
-+ temp = scnprintf(next, size, fmt, temp, scratch);
-+ size -= temp;
-+ next += temp;
-+
-+ temp = dbg_command_buf(scratch, sizeof(scratch), label,
-+ fotg210_readl(fotg210, &fotg210->regs->command));
-+ temp = scnprintf(next, size, fmt, temp, scratch);
-+ size -= temp;
-+ next += temp;
-+
-+ temp = dbg_intr_buf(scratch, sizeof(scratch), label,
-+ fotg210_readl(fotg210, &fotg210->regs->intr_enable));
-+ temp = scnprintf(next, size, fmt, temp, scratch);
-+ size -= temp;
-+ next += temp;
-+
-+ temp = scnprintf(next, size, "uframe %04x\n",
-+ fotg210_read_frame_index(fotg210));
-+ size -= temp;
-+ next += temp;
-+
-+ if (fotg210->async_unlink) {
-+ temp = scnprintf(next, size, "async unlink qh %p\n",
-+ fotg210->async_unlink);
-+ size -= temp;
-+ next += temp;
-+ }
-+
-+#ifdef FOTG210_STATS
-+ temp = scnprintf(next, size,
-+ "irq normal %ld err %ld iaa %ld(lost %ld)\n",
-+ fotg210->stats.normal, fotg210->stats.error,
-+ fotg210->stats.iaa, fotg210->stats.lost_iaa);
-+ size -= temp;
-+ next += temp;
-+
-+ temp = scnprintf(next, size, "complete %ld unlink %ld\n",
-+ fotg210->stats.complete, fotg210->stats.unlink);
-+ size -= temp;
-+ next += temp;
-+#endif
-+
-+done:
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+
-+ return buf->alloc_size - size;
-+}
-+
-+static struct debug_buffer
-+*alloc_buffer(struct usb_bus *bus, ssize_t (*fill_func)(struct debug_buffer *))
-+{
-+ struct debug_buffer *buf;
-+
-+ buf = kzalloc(sizeof(struct debug_buffer), GFP_KERNEL);
-+
-+ if (buf) {
-+ buf->bus = bus;
-+ buf->fill_func = fill_func;
-+ mutex_init(&buf->mutex);
-+ buf->alloc_size = PAGE_SIZE;
-+ }
-+
-+ return buf;
-+}
-+
-+static int fill_buffer(struct debug_buffer *buf)
-+{
-+ int ret = 0;
-+
-+ if (!buf->output_buf)
-+ buf->output_buf = vmalloc(buf->alloc_size);
-+
-+ if (!buf->output_buf) {
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ ret = buf->fill_func(buf);
-+
-+ if (ret >= 0) {
-+ buf->count = ret;
-+ ret = 0;
-+ }
-+
-+out:
-+ return ret;
-+}
-+
-+static ssize_t debug_output(struct file *file, char __user *user_buf,
-+ size_t len, loff_t *offset)
-+{
-+ struct debug_buffer *buf = file->private_data;
-+ int ret = 0;
-+
-+ mutex_lock(&buf->mutex);
-+ if (buf->count == 0) {
-+ ret = fill_buffer(buf);
-+ if (ret != 0) {
-+ mutex_unlock(&buf->mutex);
-+ goto out;
-+ }
-+ }
-+ mutex_unlock(&buf->mutex);
-+
-+ ret = simple_read_from_buffer(user_buf, len, offset,
-+ buf->output_buf, buf->count);
-+
-+out:
-+ return ret;
-+
-+}
-+
-+static int debug_close(struct inode *inode, struct file *file)
-+{
-+ struct debug_buffer *buf = file->private_data;
-+
-+ if (buf) {
-+ vfree(buf->output_buf);
-+ kfree(buf);
-+ }
-+
-+ return 0;
-+}
-+static int debug_async_open(struct inode *inode, struct file *file)
-+{
-+ file->private_data = alloc_buffer(inode->i_private, fill_async_buffer);
-+
-+ return file->private_data ? 0 : -ENOMEM;
-+}
-+
-+static int debug_periodic_open(struct inode *inode, struct file *file)
-+{
-+ struct debug_buffer *buf;
-+
-+ buf = alloc_buffer(inode->i_private, fill_periodic_buffer);
-+ if (!buf)
-+ return -ENOMEM;
-+
-+ buf->alloc_size = (sizeof(void *) == 4 ? 6 : 8)*PAGE_SIZE;
-+ file->private_data = buf;
-+ return 0;
-+}
-+
-+static int debug_registers_open(struct inode *inode, struct file *file)
-+{
-+ file->private_data = alloc_buffer(inode->i_private,
-+ fill_registers_buffer);
-+
-+ return file->private_data ? 0 : -ENOMEM;
-+}
-+
-+static inline void create_debug_files(struct fotg210_hcd *fotg210)
-+{
-+ struct usb_bus *bus = &fotg210_to_hcd(fotg210)->self;
-+ struct dentry *root;
-+
-+ root = debugfs_create_dir(bus->bus_name, fotg210_debug_root);
-+
-+ debugfs_create_file("async", S_IRUGO, root, bus, &debug_async_fops);
-+ debugfs_create_file("periodic", S_IRUGO, root, bus,
-+ &debug_periodic_fops);
-+ debugfs_create_file("registers", S_IRUGO, root, bus,
-+ &debug_registers_fops);
-+}
-+
-+static inline void remove_debug_files(struct fotg210_hcd *fotg210)
-+{
-+ struct usb_bus *bus = &fotg210_to_hcd(fotg210)->self;
-+
-+ debugfs_lookup_and_remove(bus->bus_name, fotg210_debug_root);
-+}
-+
-+/* handshake - spin reading hc until handshake completes or fails
-+ * @ptr: address of hc register to be read
-+ * @mask: bits to look at in result of read
-+ * @done: value of those bits when handshake succeeds
-+ * @usec: timeout in microseconds
-+ *
-+ * Returns negative errno, or zero on success
-+ *
-+ * Success happens when the "mask" bits have the specified value (hardware
-+ * handshake done). There are two failure modes: "usec" have passed (major
-+ * hardware flakeout), or the register reads as all-ones (hardware removed).
-+ *
-+ * That last failure should_only happen in cases like physical cardbus eject
-+ * before driver shutdown. But it also seems to be caused by bugs in cardbus
-+ * bridge shutdown: shutting down the bridge before the devices using it.
-+ */
-+static int handshake(struct fotg210_hcd *fotg210, void __iomem *ptr,
-+ u32 mask, u32 done, int usec)
-+{
-+ u32 result;
-+ int ret;
-+
-+ ret = readl_poll_timeout_atomic(ptr, result,
-+ ((result & mask) == done ||
-+ result == U32_MAX), 1, usec);
-+ if (result == U32_MAX) /* card removed */
-+ return -ENODEV;
-+
-+ return ret;
-+}
-+
-+/* Force HC to halt state from unknown (EHCI spec section 2.3).
-+ * Must be called with interrupts enabled and the lock not held.
-+ */
-+static int fotg210_halt(struct fotg210_hcd *fotg210)
-+{
-+ u32 temp;
-+
-+ spin_lock_irq(&fotg210->lock);
-+
-+ /* disable any irqs left enabled by previous code */
-+ fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
-+
-+ /*
-+ * This routine gets called during probe before fotg210->command
-+ * has been initialized, so we can't rely on its value.
-+ */
-+ fotg210->command &= ~CMD_RUN;
-+ temp = fotg210_readl(fotg210, &fotg210->regs->command);
-+ temp &= ~(CMD_RUN | CMD_IAAD);
-+ fotg210_writel(fotg210, temp, &fotg210->regs->command);
-+
-+ spin_unlock_irq(&fotg210->lock);
-+ synchronize_irq(fotg210_to_hcd(fotg210)->irq);
-+
-+ return handshake(fotg210, &fotg210->regs->status,
-+ STS_HALT, STS_HALT, 16 * 125);
-+}
-+
-+/* Reset a non-running (STS_HALT == 1) controller.
-+ * Must be called with interrupts enabled and the lock not held.
-+ */
-+static int fotg210_reset(struct fotg210_hcd *fotg210)
-+{
-+ int retval;
-+ u32 command = fotg210_readl(fotg210, &fotg210->regs->command);
-+
-+ /* If the EHCI debug controller is active, special care must be
-+ * taken before and after a host controller reset
-+ */
-+ if (fotg210->debug && !dbgp_reset_prep(fotg210_to_hcd(fotg210)))
-+ fotg210->debug = NULL;
-+
-+ command |= CMD_RESET;
-+ dbg_cmd(fotg210, "reset", command);
-+ fotg210_writel(fotg210, command, &fotg210->regs->command);
-+ fotg210->rh_state = FOTG210_RH_HALTED;
-+ fotg210->next_statechange = jiffies;
-+ retval = handshake(fotg210, &fotg210->regs->command,
-+ CMD_RESET, 0, 250 * 1000);
-+
-+ if (retval)
-+ return retval;
-+
-+ if (fotg210->debug)
-+ dbgp_external_startup(fotg210_to_hcd(fotg210));
-+
-+ fotg210->port_c_suspend = fotg210->suspended_ports =
-+ fotg210->resuming_ports = 0;
-+ return retval;
-+}
-+
-+/* Idle the controller (turn off the schedules).
-+ * Must be called with interrupts enabled and the lock not held.
-+ */
-+static void fotg210_quiesce(struct fotg210_hcd *fotg210)
-+{
-+ u32 temp;
-+
-+ if (fotg210->rh_state != FOTG210_RH_RUNNING)
-+ return;
-+
-+ /* wait for any schedule enables/disables to take effect */
-+ temp = (fotg210->command << 10) & (STS_ASS | STS_PSS);
-+ handshake(fotg210, &fotg210->regs->status, STS_ASS | STS_PSS, temp,
-+ 16 * 125);
-+
-+ /* then disable anything that's still active */
-+ spin_lock_irq(&fotg210->lock);
-+ fotg210->command &= ~(CMD_ASE | CMD_PSE);
-+ fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-+ spin_unlock_irq(&fotg210->lock);
-+
-+ /* hardware can take 16 microframes to turn off ... */
-+ handshake(fotg210, &fotg210->regs->status, STS_ASS | STS_PSS, 0,
-+ 16 * 125);
-+}
-+
-+static void end_unlink_async(struct fotg210_hcd *fotg210);
-+static void unlink_empty_async(struct fotg210_hcd *fotg210);
-+static void fotg210_work(struct fotg210_hcd *fotg210);
-+static void start_unlink_intr(struct fotg210_hcd *fotg210,
-+ struct fotg210_qh *qh);
-+static void end_unlink_intr(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
-+
-+/* Set a bit in the USBCMD register */
-+static void fotg210_set_command_bit(struct fotg210_hcd *fotg210, u32 bit)
-+{
-+ fotg210->command |= bit;
-+ fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-+
-+ /* unblock posted write */
-+ fotg210_readl(fotg210, &fotg210->regs->command);
-+}
-+
-+/* Clear a bit in the USBCMD register */
-+static void fotg210_clear_command_bit(struct fotg210_hcd *fotg210, u32 bit)
-+{
-+ fotg210->command &= ~bit;
-+ fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-+
-+ /* unblock posted write */
-+ fotg210_readl(fotg210, &fotg210->regs->command);
-+}
-+
-+/* EHCI timer support... Now using hrtimers.
-+ *
-+ * Lots of different events are triggered from fotg210->hrtimer. Whenever
-+ * the timer routine runs, it checks each possible event; events that are
-+ * currently enabled and whose expiration time has passed get handled.
-+ * The set of enabled events is stored as a collection of bitflags in
-+ * fotg210->enabled_hrtimer_events, and they are numbered in order of
-+ * increasing delay values (ranging between 1 ms and 100 ms).
-+ *
-+ * Rather than implementing a sorted list or tree of all pending events,
-+ * we keep track only of the lowest-numbered pending event, in
-+ * fotg210->next_hrtimer_event. Whenever fotg210->hrtimer gets restarted, its
-+ * expiration time is set to the timeout value for this event.
-+ *
-+ * As a result, events might not get handled right away; the actual delay
-+ * could be anywhere up to twice the requested delay. This doesn't
-+ * matter, because none of the events are especially time-critical. The
-+ * ones that matter most all have a delay of 1 ms, so they will be
-+ * handled after 2 ms at most, which is okay. In addition to this, we
-+ * allow for an expiration range of 1 ms.
-+ */
-+
-+/* Delay lengths for the hrtimer event types.
-+ * Keep this list sorted by delay length, in the same order as
-+ * the event types indexed by enum fotg210_hrtimer_event in fotg210.h.
-+ */
-+static unsigned event_delays_ns[] = {
-+ 1 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_POLL_ASS */
-+ 1 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_POLL_PSS */
-+ 1 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_POLL_DEAD */
-+ 1125 * NSEC_PER_USEC, /* FOTG210_HRTIMER_UNLINK_INTR */
-+ 2 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_FREE_ITDS */
-+ 6 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_ASYNC_UNLINKS */
-+ 10 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_IAA_WATCHDOG */
-+ 10 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_DISABLE_PERIODIC */
-+ 15 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_DISABLE_ASYNC */
-+ 100 * NSEC_PER_MSEC, /* FOTG210_HRTIMER_IO_WATCHDOG */
-+};
-+
-+/* Enable a pending hrtimer event */
-+static void fotg210_enable_event(struct fotg210_hcd *fotg210, unsigned event,
-+ bool resched)
-+{
-+ ktime_t *timeout = &fotg210->hr_timeouts[event];
-+
-+ if (resched)
-+ *timeout = ktime_add(ktime_get(), event_delays_ns[event]);
-+ fotg210->enabled_hrtimer_events |= (1 << event);
-+
-+ /* Track only the lowest-numbered pending event */
-+ if (event < fotg210->next_hrtimer_event) {
-+ fotg210->next_hrtimer_event = event;
-+ hrtimer_start_range_ns(&fotg210->hrtimer, *timeout,
-+ NSEC_PER_MSEC, HRTIMER_MODE_ABS);
-+ }
-+}
-+
-+
-+/* Poll the STS_ASS status bit; see when it agrees with CMD_ASE */
-+static void fotg210_poll_ASS(struct fotg210_hcd *fotg210)
-+{
-+ unsigned actual, want;
-+
-+ /* Don't enable anything if the controller isn't running (e.g., died) */
-+ if (fotg210->rh_state != FOTG210_RH_RUNNING)
-+ return;
-+
-+ want = (fotg210->command & CMD_ASE) ? STS_ASS : 0;
-+ actual = fotg210_readl(fotg210, &fotg210->regs->status) & STS_ASS;
-+
-+ if (want != actual) {
-+
-+ /* Poll again later, but give up after about 20 ms */
-+ if (fotg210->ASS_poll_count++ < 20) {
-+ fotg210_enable_event(fotg210, FOTG210_HRTIMER_POLL_ASS,
-+ true);
-+ return;
-+ }
-+ fotg210_dbg(fotg210, "Waited too long for the async schedule status (%x/%x), giving up\n",
-+ want, actual);
-+ }
-+ fotg210->ASS_poll_count = 0;
-+
-+ /* The status is up-to-date; restart or stop the schedule as needed */
-+ if (want == 0) { /* Stopped */
-+ if (fotg210->async_count > 0)
-+ fotg210_set_command_bit(fotg210, CMD_ASE);
-+
-+ } else { /* Running */
-+ if (fotg210->async_count == 0) {
-+
-+ /* Turn off the schedule after a while */
-+ fotg210_enable_event(fotg210,
-+ FOTG210_HRTIMER_DISABLE_ASYNC,
-+ true);
-+ }
-+ }
-+}
-+
-+/* Turn off the async schedule after a brief delay */
-+static void fotg210_disable_ASE(struct fotg210_hcd *fotg210)
-+{
-+ fotg210_clear_command_bit(fotg210, CMD_ASE);
-+}
-+
-+
-+/* Poll the STS_PSS status bit; see when it agrees with CMD_PSE */
-+static void fotg210_poll_PSS(struct fotg210_hcd *fotg210)
-+{
-+ unsigned actual, want;
-+
-+ /* Don't do anything if the controller isn't running (e.g., died) */
-+ if (fotg210->rh_state != FOTG210_RH_RUNNING)
-+ return;
-+
-+ want = (fotg210->command & CMD_PSE) ? STS_PSS : 0;
-+ actual = fotg210_readl(fotg210, &fotg210->regs->status) & STS_PSS;
-+
-+ if (want != actual) {
-+
-+ /* Poll again later, but give up after about 20 ms */
-+ if (fotg210->PSS_poll_count++ < 20) {
-+ fotg210_enable_event(fotg210, FOTG210_HRTIMER_POLL_PSS,
-+ true);
-+ return;
-+ }
-+ fotg210_dbg(fotg210, "Waited too long for the periodic schedule status (%x/%x), giving up\n",
-+ want, actual);
-+ }
-+ fotg210->PSS_poll_count = 0;
-+
-+ /* The status is up-to-date; restart or stop the schedule as needed */
-+ if (want == 0) { /* Stopped */
-+ if (fotg210->periodic_count > 0)
-+ fotg210_set_command_bit(fotg210, CMD_PSE);
-+
-+ } else { /* Running */
-+ if (fotg210->periodic_count == 0) {
-+
-+ /* Turn off the schedule after a while */
-+ fotg210_enable_event(fotg210,
-+ FOTG210_HRTIMER_DISABLE_PERIODIC,
-+ true);
-+ }
-+ }
-+}
-+
-+/* Turn off the periodic schedule after a brief delay */
-+static void fotg210_disable_PSE(struct fotg210_hcd *fotg210)
-+{
-+ fotg210_clear_command_bit(fotg210, CMD_PSE);
-+}
-+
-+
-+/* Poll the STS_HALT status bit; see when a dead controller stops */
-+static void fotg210_handle_controller_death(struct fotg210_hcd *fotg210)
-+{
-+ if (!(fotg210_readl(fotg210, &fotg210->regs->status) & STS_HALT)) {
-+
-+ /* Give up after a few milliseconds */
-+ if (fotg210->died_poll_count++ < 5) {
-+ /* Try again later */
-+ fotg210_enable_event(fotg210,
-+ FOTG210_HRTIMER_POLL_DEAD, true);
-+ return;
-+ }
-+ fotg210_warn(fotg210, "Waited too long for the controller to stop, giving up\n");
-+ }
-+
-+ /* Clean up the mess */
-+ fotg210->rh_state = FOTG210_RH_HALTED;
-+ fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
-+ fotg210_work(fotg210);
-+ end_unlink_async(fotg210);
-+
-+ /* Not in process context, so don't try to reset the controller */
-+}
-+
-+
-+/* Handle unlinked interrupt QHs once they are gone from the hardware */
-+static void fotg210_handle_intr_unlinks(struct fotg210_hcd *fotg210)
-+{
-+ bool stopped = (fotg210->rh_state < FOTG210_RH_RUNNING);
-+
-+ /*
-+ * Process all the QHs on the intr_unlink list that were added
-+ * before the current unlink cycle began. The list is in
-+ * temporal order, so stop when we reach the first entry in the
-+ * current cycle. But if the root hub isn't running then
-+ * process all the QHs on the list.
-+ */
-+ fotg210->intr_unlinking = true;
-+ while (fotg210->intr_unlink) {
-+ struct fotg210_qh *qh = fotg210->intr_unlink;
-+
-+ if (!stopped && qh->unlink_cycle == fotg210->intr_unlink_cycle)
-+ break;
-+ fotg210->intr_unlink = qh->unlink_next;
-+ qh->unlink_next = NULL;
-+ end_unlink_intr(fotg210, qh);
-+ }
-+
-+ /* Handle remaining entries later */
-+ if (fotg210->intr_unlink) {
-+ fotg210_enable_event(fotg210, FOTG210_HRTIMER_UNLINK_INTR,
-+ true);
-+ ++fotg210->intr_unlink_cycle;
-+ }
-+ fotg210->intr_unlinking = false;
-+}
-+
-+
-+/* Start another free-iTDs/siTDs cycle */
-+static void start_free_itds(struct fotg210_hcd *fotg210)
-+{
-+ if (!(fotg210->enabled_hrtimer_events &
-+ BIT(FOTG210_HRTIMER_FREE_ITDS))) {
-+ fotg210->last_itd_to_free = list_entry(
-+ fotg210->cached_itd_list.prev,
-+ struct fotg210_itd, itd_list);
-+ fotg210_enable_event(fotg210, FOTG210_HRTIMER_FREE_ITDS, true);
-+ }
-+}
-+
-+/* Wait for controller to stop using old iTDs and siTDs */
-+static void end_free_itds(struct fotg210_hcd *fotg210)
-+{
-+ struct fotg210_itd *itd, *n;
-+
-+ if (fotg210->rh_state < FOTG210_RH_RUNNING)
-+ fotg210->last_itd_to_free = NULL;
-+
-+ list_for_each_entry_safe(itd, n, &fotg210->cached_itd_list, itd_list) {
-+ list_del(&itd->itd_list);
-+ dma_pool_free(fotg210->itd_pool, itd, itd->itd_dma);
-+ if (itd == fotg210->last_itd_to_free)
-+ break;
-+ }
-+
-+ if (!list_empty(&fotg210->cached_itd_list))
-+ start_free_itds(fotg210);
-+}
-+
-+
-+/* Handle lost (or very late) IAA interrupts */
-+static void fotg210_iaa_watchdog(struct fotg210_hcd *fotg210)
-+{
-+ if (fotg210->rh_state != FOTG210_RH_RUNNING)
-+ return;
-+
-+ /*
-+ * Lost IAA irqs wedge things badly; seen first with a vt8235.
-+ * So we need this watchdog, but must protect it against both
-+ * (a) SMP races against real IAA firing and retriggering, and
-+ * (b) clean HC shutdown, when IAA watchdog was pending.
-+ */
-+ if (fotg210->async_iaa) {
-+ u32 cmd, status;
-+
-+ /* If we get here, IAA is *REALLY* late. It's barely
-+ * conceivable that the system is so busy that CMD_IAAD
-+ * is still legitimately set, so let's be sure it's
-+ * clear before we read STS_IAA. (The HC should clear
-+ * CMD_IAAD when it sets STS_IAA.)
-+ */
-+ cmd = fotg210_readl(fotg210, &fotg210->regs->command);
-+
-+ /*
-+ * If IAA is set here it either legitimately triggered
-+ * after the watchdog timer expired (_way_ late, so we'll
-+ * still count it as lost) ... or a silicon erratum:
-+ * - VIA seems to set IAA without triggering the IRQ;
-+ * - IAAD potentially cleared without setting IAA.
-+ */
-+ status = fotg210_readl(fotg210, &fotg210->regs->status);
-+ if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
-+ INCR(fotg210->stats.lost_iaa);
-+ fotg210_writel(fotg210, STS_IAA,
-+ &fotg210->regs->status);
-+ }
-+
-+ fotg210_dbg(fotg210, "IAA watchdog: status %x cmd %x\n",
-+ status, cmd);
-+ end_unlink_async(fotg210);
-+ }
-+}
-+
-+
-+/* Enable the I/O watchdog, if appropriate */
-+static void turn_on_io_watchdog(struct fotg210_hcd *fotg210)
-+{
-+ /* Not needed if the controller isn't running or it's already enabled */
-+ if (fotg210->rh_state != FOTG210_RH_RUNNING ||
-+ (fotg210->enabled_hrtimer_events &
-+ BIT(FOTG210_HRTIMER_IO_WATCHDOG)))
-+ return;
-+
-+ /*
-+ * Isochronous transfers always need the watchdog.
-+ * For other sorts we use it only if the flag is set.
-+ */
-+ if (fotg210->isoc_count > 0 || (fotg210->need_io_watchdog &&
-+ fotg210->async_count + fotg210->intr_count > 0))
-+ fotg210_enable_event(fotg210, FOTG210_HRTIMER_IO_WATCHDOG,
-+ true);
-+}
-+
-+
-+/* Handler functions for the hrtimer event types.
-+ * Keep this array in the same order as the event types indexed by
-+ * enum fotg210_hrtimer_event in fotg210.h.
-+ */
-+static void (*event_handlers[])(struct fotg210_hcd *) = {
-+ fotg210_poll_ASS, /* FOTG210_HRTIMER_POLL_ASS */
-+ fotg210_poll_PSS, /* FOTG210_HRTIMER_POLL_PSS */
-+ fotg210_handle_controller_death, /* FOTG210_HRTIMER_POLL_DEAD */
-+ fotg210_handle_intr_unlinks, /* FOTG210_HRTIMER_UNLINK_INTR */
-+ end_free_itds, /* FOTG210_HRTIMER_FREE_ITDS */
-+ unlink_empty_async, /* FOTG210_HRTIMER_ASYNC_UNLINKS */
-+ fotg210_iaa_watchdog, /* FOTG210_HRTIMER_IAA_WATCHDOG */
-+ fotg210_disable_PSE, /* FOTG210_HRTIMER_DISABLE_PERIODIC */
-+ fotg210_disable_ASE, /* FOTG210_HRTIMER_DISABLE_ASYNC */
-+ fotg210_work, /* FOTG210_HRTIMER_IO_WATCHDOG */
-+};
-+
-+static enum hrtimer_restart fotg210_hrtimer_func(struct hrtimer *t)
-+{
-+ struct fotg210_hcd *fotg210 =
-+ container_of(t, struct fotg210_hcd, hrtimer);
-+ ktime_t now;
-+ unsigned long events;
-+ unsigned long flags;
-+ unsigned e;
-+
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+
-+ events = fotg210->enabled_hrtimer_events;
-+ fotg210->enabled_hrtimer_events = 0;
-+ fotg210->next_hrtimer_event = FOTG210_HRTIMER_NO_EVENT;
-+
-+ /*
-+ * Check each pending event. If its time has expired, handle
-+ * the event; otherwise re-enable it.
-+ */
-+ now = ktime_get();
-+ for_each_set_bit(e, &events, FOTG210_HRTIMER_NUM_EVENTS) {
-+ if (ktime_compare(now, fotg210->hr_timeouts[e]) >= 0)
-+ event_handlers[e](fotg210);
-+ else
-+ fotg210_enable_event(fotg210, e, false);
-+ }
-+
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ return HRTIMER_NORESTART;
-+}
-+
-+#define fotg210_bus_suspend NULL
-+#define fotg210_bus_resume NULL
-+
-+static int check_reset_complete(struct fotg210_hcd *fotg210, int index,
-+ u32 __iomem *status_reg, int port_status)
-+{
-+ if (!(port_status & PORT_CONNECT))
-+ return port_status;
-+
-+ /* if reset finished and it's still not enabled -- handoff */
-+ if (!(port_status & PORT_PE))
-+ /* with integrated TT, there's nobody to hand it to! */
-+ fotg210_dbg(fotg210, "Failed to enable port %d on root hub TT\n",
-+ index + 1);
-+ else
-+ fotg210_dbg(fotg210, "port %d reset complete, port enabled\n",
-+ index + 1);
-+
-+ return port_status;
-+}
-+
-+
-+/* build "status change" packet (one or two bytes) from HC registers */
-+
-+static int fotg210_hub_status_data(struct usb_hcd *hcd, char *buf)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+ u32 temp, status;
-+ u32 mask;
-+ int retval = 1;
-+ unsigned long flags;
-+
-+ /* init status to no-changes */
-+ buf[0] = 0;
-+
-+ /* Inform the core about resumes-in-progress by returning
-+ * a non-zero value even if there are no status changes.
-+ */
-+ status = fotg210->resuming_ports;
-+
-+ mask = PORT_CSC | PORT_PEC;
-+ /* PORT_RESUME from hardware ~= PORT_STAT_C_SUSPEND */
-+
-+ /* no hub change reports (bit 0) for now (power, ...) */
-+
-+ /* port N changes (bit N)? */
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+
-+ temp = fotg210_readl(fotg210, &fotg210->regs->port_status);
-+
-+ /*
-+ * Return status information even for ports with OWNER set.
-+ * Otherwise hub_wq wouldn't see the disconnect event when a
-+ * high-speed device is switched over to the companion
-+ * controller by the user.
-+ */
-+
-+ if ((temp & mask) != 0 || test_bit(0, &fotg210->port_c_suspend) ||
-+ (fotg210->reset_done[0] &&
-+ time_after_eq(jiffies, fotg210->reset_done[0]))) {
-+ buf[0] |= 1 << 1;
-+ status = STS_PCD;
-+ }
-+ /* FIXME autosuspend idle root hubs */
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ return status ? retval : 0;
-+}
-+
-+static void fotg210_hub_descriptor(struct fotg210_hcd *fotg210,
-+ struct usb_hub_descriptor *desc)
-+{
-+ int ports = HCS_N_PORTS(fotg210->hcs_params);
-+ u16 temp;
-+
-+ desc->bDescriptorType = USB_DT_HUB;
-+ desc->bPwrOn2PwrGood = 10; /* fotg210 1.0, 2.3.9 says 20ms max */
-+ desc->bHubContrCurrent = 0;
-+
-+ desc->bNbrPorts = ports;
-+ temp = 1 + (ports / 8);
-+ desc->bDescLength = 7 + 2 * temp;
-+
-+ /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
-+ memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
-+ memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
-+
-+ temp = HUB_CHAR_INDV_PORT_OCPM; /* per-port overcurrent reporting */
-+ temp |= HUB_CHAR_NO_LPSM; /* no power switching */
-+ desc->wHubCharacteristics = cpu_to_le16(temp);
-+}
-+
-+static int fotg210_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
-+ u16 wIndex, char *buf, u16 wLength)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+ int ports = HCS_N_PORTS(fotg210->hcs_params);
-+ u32 __iomem *status_reg = &fotg210->regs->port_status;
-+ u32 temp, temp1, status;
-+ unsigned long flags;
-+ int retval = 0;
-+ unsigned selector;
-+
-+ /*
-+ * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
-+ * HCS_INDICATOR may say we can change LEDs to off/amber/green.
-+ * (track current state ourselves) ... blink for diagnostics,
-+ * power, "this is the one", etc. EHCI spec supports this.
-+ */
-+
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ switch (typeReq) {
-+ case ClearHubFeature:
-+ switch (wValue) {
-+ case C_HUB_LOCAL_POWER:
-+ case C_HUB_OVER_CURRENT:
-+ /* no hub-wide feature/status flags */
-+ break;
-+ default:
-+ goto error;
-+ }
-+ break;
-+ case ClearPortFeature:
-+ if (!wIndex || wIndex > ports)
-+ goto error;
-+ wIndex--;
-+ temp = fotg210_readl(fotg210, status_reg);
-+ temp &= ~PORT_RWC_BITS;
-+
-+ /*
-+ * Even if OWNER is set, so the port is owned by the
-+ * companion controller, hub_wq needs to be able to clear
-+ * the port-change status bits (especially
-+ * USB_PORT_STAT_C_CONNECTION).
-+ */
-+
-+ switch (wValue) {
-+ case USB_PORT_FEAT_ENABLE:
-+ fotg210_writel(fotg210, temp & ~PORT_PE, status_reg);
-+ break;
-+ case USB_PORT_FEAT_C_ENABLE:
-+ fotg210_writel(fotg210, temp | PORT_PEC, status_reg);
-+ break;
-+ case USB_PORT_FEAT_SUSPEND:
-+ if (temp & PORT_RESET)
-+ goto error;
-+ if (!(temp & PORT_SUSPEND))
-+ break;
-+ if ((temp & PORT_PE) == 0)
-+ goto error;
-+
-+ /* resume signaling for 20 msec */
-+ fotg210_writel(fotg210, temp | PORT_RESUME, status_reg);
-+ fotg210->reset_done[wIndex] = jiffies
-+ + msecs_to_jiffies(USB_RESUME_TIMEOUT);
-+ break;
-+ case USB_PORT_FEAT_C_SUSPEND:
-+ clear_bit(wIndex, &fotg210->port_c_suspend);
-+ break;
-+ case USB_PORT_FEAT_C_CONNECTION:
-+ fotg210_writel(fotg210, temp | PORT_CSC, status_reg);
-+ break;
-+ case USB_PORT_FEAT_C_OVER_CURRENT:
-+ fotg210_writel(fotg210, temp | OTGISR_OVC,
-+ &fotg210->regs->otgisr);
-+ break;
-+ case USB_PORT_FEAT_C_RESET:
-+ /* GetPortStatus clears reset */
-+ break;
-+ default:
-+ goto error;
-+ }
-+ fotg210_readl(fotg210, &fotg210->regs->command);
-+ break;
-+ case GetHubDescriptor:
-+ fotg210_hub_descriptor(fotg210, (struct usb_hub_descriptor *)
-+ buf);
-+ break;
-+ case GetHubStatus:
-+ /* no hub-wide feature/status flags */
-+ memset(buf, 0, 4);
-+ /*cpu_to_le32s ((u32 *) buf); */
-+ break;
-+ case GetPortStatus:
-+ if (!wIndex || wIndex > ports)
-+ goto error;
-+ wIndex--;
-+ status = 0;
-+ temp = fotg210_readl(fotg210, status_reg);
-+
-+ /* wPortChange bits */
-+ if (temp & PORT_CSC)
-+ status |= USB_PORT_STAT_C_CONNECTION << 16;
-+ if (temp & PORT_PEC)
-+ status |= USB_PORT_STAT_C_ENABLE << 16;
-+
-+ temp1 = fotg210_readl(fotg210, &fotg210->regs->otgisr);
-+ if (temp1 & OTGISR_OVC)
-+ status |= USB_PORT_STAT_C_OVERCURRENT << 16;
-+
-+ /* whoever resumes must GetPortStatus to complete it!! */
-+ if (temp & PORT_RESUME) {
-+
-+ /* Remote Wakeup received? */
-+ if (!fotg210->reset_done[wIndex]) {
-+ /* resume signaling for 20 msec */
-+ fotg210->reset_done[wIndex] = jiffies
-+ + msecs_to_jiffies(20);
-+ /* check the port again */
-+ mod_timer(&fotg210_to_hcd(fotg210)->rh_timer,
-+ fotg210->reset_done[wIndex]);
-+ }
-+
-+ /* resume completed? */
-+ else if (time_after_eq(jiffies,
-+ fotg210->reset_done[wIndex])) {
-+ clear_bit(wIndex, &fotg210->suspended_ports);
-+ set_bit(wIndex, &fotg210->port_c_suspend);
-+ fotg210->reset_done[wIndex] = 0;
-+
-+ /* stop resume signaling */
-+ temp = fotg210_readl(fotg210, status_reg);
-+ fotg210_writel(fotg210, temp &
-+ ~(PORT_RWC_BITS | PORT_RESUME),
-+ status_reg);
-+ clear_bit(wIndex, &fotg210->resuming_ports);
-+ retval = handshake(fotg210, status_reg,
-+ PORT_RESUME, 0, 2000);/* 2ms */
-+ if (retval != 0) {
-+ fotg210_err(fotg210,
-+ "port %d resume error %d\n",
-+ wIndex + 1, retval);
-+ goto error;
-+ }
-+ temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
-+ }
-+ }
-+
-+ /* whoever resets must GetPortStatus to complete it!! */
-+ if ((temp & PORT_RESET) && time_after_eq(jiffies,
-+ fotg210->reset_done[wIndex])) {
-+ status |= USB_PORT_STAT_C_RESET << 16;
-+ fotg210->reset_done[wIndex] = 0;
-+ clear_bit(wIndex, &fotg210->resuming_ports);
-+
-+ /* force reset to complete */
-+ fotg210_writel(fotg210,
-+ temp & ~(PORT_RWC_BITS | PORT_RESET),
-+ status_reg);
-+ /* REVISIT: some hardware needs 550+ usec to clear
-+ * this bit; seems too long to spin routinely...
-+ */
-+ retval = handshake(fotg210, status_reg,
-+ PORT_RESET, 0, 1000);
-+ if (retval != 0) {
-+ fotg210_err(fotg210, "port %d reset error %d\n",
-+ wIndex + 1, retval);
-+ goto error;
-+ }
-+
-+ /* see what we found out */
-+ temp = check_reset_complete(fotg210, wIndex, status_reg,
-+ fotg210_readl(fotg210, status_reg));
-+
-+ /* restart schedule */
-+ fotg210->command |= CMD_RUN;
-+ fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-+ }
-+
-+ if (!(temp & (PORT_RESUME|PORT_RESET))) {
-+ fotg210->reset_done[wIndex] = 0;
-+ clear_bit(wIndex, &fotg210->resuming_ports);
-+ }
-+
-+ /* transfer dedicated ports to the companion hc */
-+ if ((temp & PORT_CONNECT) &&
-+ test_bit(wIndex, &fotg210->companion_ports)) {
-+ temp &= ~PORT_RWC_BITS;
-+ fotg210_writel(fotg210, temp, status_reg);
-+ fotg210_dbg(fotg210, "port %d --> companion\n",
-+ wIndex + 1);
-+ temp = fotg210_readl(fotg210, status_reg);
-+ }
-+
-+ /*
-+ * Even if OWNER is set, there's no harm letting hub_wq
-+ * see the wPortStatus values (they should all be 0 except
-+ * for PORT_POWER anyway).
-+ */
-+
-+ if (temp & PORT_CONNECT) {
-+ status |= USB_PORT_STAT_CONNECTION;
-+ status |= fotg210_port_speed(fotg210, temp);
-+ }
-+ if (temp & PORT_PE)
-+ status |= USB_PORT_STAT_ENABLE;
-+
-+ /* maybe the port was unsuspended without our knowledge */
-+ if (temp & (PORT_SUSPEND|PORT_RESUME)) {
-+ status |= USB_PORT_STAT_SUSPEND;
-+ } else if (test_bit(wIndex, &fotg210->suspended_ports)) {
-+ clear_bit(wIndex, &fotg210->suspended_ports);
-+ clear_bit(wIndex, &fotg210->resuming_ports);
-+ fotg210->reset_done[wIndex] = 0;
-+ if (temp & PORT_PE)
-+ set_bit(wIndex, &fotg210->port_c_suspend);
-+ }
-+
-+ temp1 = fotg210_readl(fotg210, &fotg210->regs->otgisr);
-+ if (temp1 & OTGISR_OVC)
-+ status |= USB_PORT_STAT_OVERCURRENT;
-+ if (temp & PORT_RESET)
-+ status |= USB_PORT_STAT_RESET;
-+ if (test_bit(wIndex, &fotg210->port_c_suspend))
-+ status |= USB_PORT_STAT_C_SUSPEND << 16;
-+
-+ if (status & ~0xffff) /* only if wPortChange is interesting */
-+ dbg_port(fotg210, "GetStatus", wIndex + 1, temp);
-+ put_unaligned_le32(status, buf);
-+ break;
-+ case SetHubFeature:
-+ switch (wValue) {
-+ case C_HUB_LOCAL_POWER:
-+ case C_HUB_OVER_CURRENT:
-+ /* no hub-wide feature/status flags */
-+ break;
-+ default:
-+ goto error;
-+ }
-+ break;
-+ case SetPortFeature:
-+ selector = wIndex >> 8;
-+ wIndex &= 0xff;
-+
-+ if (!wIndex || wIndex > ports)
-+ goto error;
-+ wIndex--;
-+ temp = fotg210_readl(fotg210, status_reg);
-+ temp &= ~PORT_RWC_BITS;
-+ switch (wValue) {
-+ case USB_PORT_FEAT_SUSPEND:
-+ if ((temp & PORT_PE) == 0
-+ || (temp & PORT_RESET) != 0)
-+ goto error;
-+
-+ /* After above check the port must be connected.
-+ * Set appropriate bit thus could put phy into low power
-+ * mode if we have hostpc feature
-+ */
-+ fotg210_writel(fotg210, temp | PORT_SUSPEND,
-+ status_reg);
-+ set_bit(wIndex, &fotg210->suspended_ports);
-+ break;
-+ case USB_PORT_FEAT_RESET:
-+ if (temp & PORT_RESUME)
-+ goto error;
-+ /* line status bits may report this as low speed,
-+ * which can be fine if this root hub has a
-+ * transaction translator built in.
-+ */
-+ fotg210_dbg(fotg210, "port %d reset\n", wIndex + 1);
-+ temp |= PORT_RESET;
-+ temp &= ~PORT_PE;
-+
-+ /*
-+ * caller must wait, then call GetPortStatus
-+ * usb 2.0 spec says 50 ms resets on root
-+ */
-+ fotg210->reset_done[wIndex] = jiffies
-+ + msecs_to_jiffies(50);
-+ fotg210_writel(fotg210, temp, status_reg);
-+ break;
-+
-+ /* For downstream facing ports (these): one hub port is put
-+ * into test mode according to USB2 11.24.2.13, then the hub
-+ * must be reset (which for root hub now means rmmod+modprobe,
-+ * or else system reboot). See EHCI 2.3.9 and 4.14 for info
-+ * about the EHCI-specific stuff.
-+ */
-+ case USB_PORT_FEAT_TEST:
-+ if (!selector || selector > 5)
-+ goto error;
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ fotg210_quiesce(fotg210);
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+
-+ /* Put all enabled ports into suspend */
-+ temp = fotg210_readl(fotg210, status_reg) &
-+ ~PORT_RWC_BITS;
-+ if (temp & PORT_PE)
-+ fotg210_writel(fotg210, temp | PORT_SUSPEND,
-+ status_reg);
-+
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ fotg210_halt(fotg210);
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+
-+ temp = fotg210_readl(fotg210, status_reg);
-+ temp |= selector << 16;
-+ fotg210_writel(fotg210, temp, status_reg);
-+ break;
-+
-+ default:
-+ goto error;
-+ }
-+ fotg210_readl(fotg210, &fotg210->regs->command);
-+ break;
-+
-+ default:
-+error:
-+ /* "stall" on error */
-+ retval = -EPIPE;
-+ }
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ return retval;
-+}
-+
-+static void __maybe_unused fotg210_relinquish_port(struct usb_hcd *hcd,
-+ int portnum)
-+{
-+ return;
-+}
-+
-+static int __maybe_unused fotg210_port_handed_over(struct usb_hcd *hcd,
-+ int portnum)
-+{
-+ return 0;
-+}
-+
-+/* There's basically three types of memory:
-+ * - data used only by the HCD ... kmalloc is fine
-+ * - async and periodic schedules, shared by HC and HCD ... these
-+ * need to use dma_pool or dma_alloc_coherent
-+ * - driver buffers, read/written by HC ... single shot DMA mapped
-+ *
-+ * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
-+ * No memory seen by this driver is pageable.
-+ */
-+
-+/* Allocate the key transfer structures from the previously allocated pool */
-+static inline void fotg210_qtd_init(struct fotg210_hcd *fotg210,
-+ struct fotg210_qtd *qtd, dma_addr_t dma)
-+{
-+ memset(qtd, 0, sizeof(*qtd));
-+ qtd->qtd_dma = dma;
-+ qtd->hw_token = cpu_to_hc32(fotg210, QTD_STS_HALT);
-+ qtd->hw_next = FOTG210_LIST_END(fotg210);
-+ qtd->hw_alt_next = FOTG210_LIST_END(fotg210);
-+ INIT_LIST_HEAD(&qtd->qtd_list);
-+}
-+
-+static struct fotg210_qtd *fotg210_qtd_alloc(struct fotg210_hcd *fotg210,
-+ gfp_t flags)
-+{
-+ struct fotg210_qtd *qtd;
-+ dma_addr_t dma;
-+
-+ qtd = dma_pool_alloc(fotg210->qtd_pool, flags, &dma);
-+ if (qtd != NULL)
-+ fotg210_qtd_init(fotg210, qtd, dma);
-+
-+ return qtd;
-+}
-+
-+static inline void fotg210_qtd_free(struct fotg210_hcd *fotg210,
-+ struct fotg210_qtd *qtd)
-+{
-+ dma_pool_free(fotg210->qtd_pool, qtd, qtd->qtd_dma);
-+}
-+
-+
-+static void qh_destroy(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+ /* clean qtds first, and know this is not linked */
-+ if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) {
-+ fotg210_dbg(fotg210, "unused qh not empty!\n");
-+ BUG();
-+ }
-+ if (qh->dummy)
-+ fotg210_qtd_free(fotg210, qh->dummy);
-+ dma_pool_free(fotg210->qh_pool, qh->hw, qh->qh_dma);
-+ kfree(qh);
-+}
-+
-+static struct fotg210_qh *fotg210_qh_alloc(struct fotg210_hcd *fotg210,
-+ gfp_t flags)
-+{
-+ struct fotg210_qh *qh;
-+ dma_addr_t dma;
-+
-+ qh = kzalloc(sizeof(*qh), GFP_ATOMIC);
-+ if (!qh)
-+ goto done;
-+ qh->hw = (struct fotg210_qh_hw *)
-+ dma_pool_zalloc(fotg210->qh_pool, flags, &dma);
-+ if (!qh->hw)
-+ goto fail;
-+ qh->qh_dma = dma;
-+ INIT_LIST_HEAD(&qh->qtd_list);
-+
-+ /* dummy td enables safe urb queuing */
-+ qh->dummy = fotg210_qtd_alloc(fotg210, flags);
-+ if (qh->dummy == NULL) {
-+ fotg210_dbg(fotg210, "no dummy td\n");
-+ goto fail1;
-+ }
-+done:
-+ return qh;
-+fail1:
-+ dma_pool_free(fotg210->qh_pool, qh->hw, qh->qh_dma);
-+fail:
-+ kfree(qh);
-+ return NULL;
-+}
-+
-+/* The queue heads and transfer descriptors are managed from pools tied
-+ * to each of the "per device" structures.
-+ * This is the initialisation and cleanup code.
-+ */
-+
-+static void fotg210_mem_cleanup(struct fotg210_hcd *fotg210)
-+{
-+ if (fotg210->async)
-+ qh_destroy(fotg210, fotg210->async);
-+ fotg210->async = NULL;
-+
-+ if (fotg210->dummy)
-+ qh_destroy(fotg210, fotg210->dummy);
-+ fotg210->dummy = NULL;
-+
-+ /* DMA consistent memory and pools */
-+ dma_pool_destroy(fotg210->qtd_pool);
-+ fotg210->qtd_pool = NULL;
-+
-+ dma_pool_destroy(fotg210->qh_pool);
-+ fotg210->qh_pool = NULL;
-+
-+ dma_pool_destroy(fotg210->itd_pool);
-+ fotg210->itd_pool = NULL;
-+
-+ if (fotg210->periodic)
-+ dma_free_coherent(fotg210_to_hcd(fotg210)->self.controller,
-+ fotg210->periodic_size * sizeof(u32),
-+ fotg210->periodic, fotg210->periodic_dma);
-+ fotg210->periodic = NULL;
-+
-+ /* shadow periodic table */
-+ kfree(fotg210->pshadow);
-+ fotg210->pshadow = NULL;
-+}
-+
-+/* remember to add cleanup code (above) if you add anything here */
-+static int fotg210_mem_init(struct fotg210_hcd *fotg210, gfp_t flags)
-+{
-+ int i;
-+
-+ /* QTDs for control/bulk/intr transfers */
-+ fotg210->qtd_pool = dma_pool_create("fotg210_qtd",
-+ fotg210_to_hcd(fotg210)->self.controller,
-+ sizeof(struct fotg210_qtd),
-+ 32 /* byte alignment (for hw parts) */,
-+ 4096 /* can't cross 4K */);
-+ if (!fotg210->qtd_pool)
-+ goto fail;
-+
-+ /* QHs for control/bulk/intr transfers */
-+ fotg210->qh_pool = dma_pool_create("fotg210_qh",
-+ fotg210_to_hcd(fotg210)->self.controller,
-+ sizeof(struct fotg210_qh_hw),
-+ 32 /* byte alignment (for hw parts) */,
-+ 4096 /* can't cross 4K */);
-+ if (!fotg210->qh_pool)
-+ goto fail;
-+
-+ fotg210->async = fotg210_qh_alloc(fotg210, flags);
-+ if (!fotg210->async)
-+ goto fail;
-+
-+ /* ITD for high speed ISO transfers */
-+ fotg210->itd_pool = dma_pool_create("fotg210_itd",
-+ fotg210_to_hcd(fotg210)->self.controller,
-+ sizeof(struct fotg210_itd),
-+ 64 /* byte alignment (for hw parts) */,
-+ 4096 /* can't cross 4K */);
-+ if (!fotg210->itd_pool)
-+ goto fail;
-+
-+ /* Hardware periodic table */
-+ fotg210->periodic =
-+ dma_alloc_coherent(fotg210_to_hcd(fotg210)->self.controller,
-+ fotg210->periodic_size * sizeof(__le32),
-+ &fotg210->periodic_dma, 0);
-+ if (fotg210->periodic == NULL)
-+ goto fail;
-+
-+ for (i = 0; i < fotg210->periodic_size; i++)
-+ fotg210->periodic[i] = FOTG210_LIST_END(fotg210);
-+
-+ /* software shadow of hardware table */
-+ fotg210->pshadow = kcalloc(fotg210->periodic_size, sizeof(void *),
-+ flags);
-+ if (fotg210->pshadow != NULL)
-+ return 0;
-+
-+fail:
-+ fotg210_dbg(fotg210, "couldn't init memory\n");
-+ fotg210_mem_cleanup(fotg210);
-+ return -ENOMEM;
-+}
-+/* EHCI hardware queue manipulation ... the core. QH/QTD manipulation.
-+ *
-+ * Control, bulk, and interrupt traffic all use "qh" lists. They list "qtd"
-+ * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned
-+ * buffers needed for the larger number). We use one QH per endpoint, queue
-+ * multiple urbs (all three types) per endpoint. URBs may need several qtds.
-+ *
-+ * ISO traffic uses "ISO TD" (itd) records, and (along with
-+ * interrupts) needs careful scheduling. Performance improvements can be
-+ * an ongoing challenge. That's in "ehci-sched.c".
-+ *
-+ * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs,
-+ * or otherwise through transaction translators (TTs) in USB 2.0 hubs using
-+ * (b) special fields in qh entries or (c) split iso entries. TTs will
-+ * buffer low/full speed data so the host collects it at high speed.
-+ */
-+
-+/* fill a qtd, returning how much of the buffer we were able to queue up */
-+static int qtd_fill(struct fotg210_hcd *fotg210, struct fotg210_qtd *qtd,
-+ dma_addr_t buf, size_t len, int token, int maxpacket)
-+{
-+ int i, count;
-+ u64 addr = buf;
-+
-+ /* one buffer entry per 4K ... first might be short or unaligned */
-+ qtd->hw_buf[0] = cpu_to_hc32(fotg210, (u32)addr);
-+ qtd->hw_buf_hi[0] = cpu_to_hc32(fotg210, (u32)(addr >> 32));
-+ count = 0x1000 - (buf & 0x0fff); /* rest of that page */
-+ if (likely(len < count)) /* ... iff needed */
-+ count = len;
-+ else {
-+ buf += 0x1000;
-+ buf &= ~0x0fff;
-+
-+ /* per-qtd limit: from 16K to 20K (best alignment) */
-+ for (i = 1; count < len && i < 5; i++) {
-+ addr = buf;
-+ qtd->hw_buf[i] = cpu_to_hc32(fotg210, (u32)addr);
-+ qtd->hw_buf_hi[i] = cpu_to_hc32(fotg210,
-+ (u32)(addr >> 32));
-+ buf += 0x1000;
-+ if ((count + 0x1000) < len)
-+ count += 0x1000;
-+ else
-+ count = len;
-+ }
-+
-+ /* short packets may only terminate transfers */
-+ if (count != len)
-+ count -= (count % maxpacket);
-+ }
-+ qtd->hw_token = cpu_to_hc32(fotg210, (count << 16) | token);
-+ qtd->length = count;
-+
-+ return count;
-+}
-+
-+static inline void qh_update(struct fotg210_hcd *fotg210,
-+ struct fotg210_qh *qh, struct fotg210_qtd *qtd)
-+{
-+ struct fotg210_qh_hw *hw = qh->hw;
-+
-+ /* writes to an active overlay are unsafe */
-+ BUG_ON(qh->qh_state != QH_STATE_IDLE);
-+
-+ hw->hw_qtd_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-+ hw->hw_alt_next = FOTG210_LIST_END(fotg210);
-+
-+ /* Except for control endpoints, we make hardware maintain data
-+ * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
-+ * and set the pseudo-toggle in udev. Only usb_clear_halt() will
-+ * ever clear it.
-+ */
-+ if (!(hw->hw_info1 & cpu_to_hc32(fotg210, QH_TOGGLE_CTL))) {
-+ unsigned is_out, epnum;
-+
-+ is_out = qh->is_out;
-+ epnum = (hc32_to_cpup(fotg210, &hw->hw_info1) >> 8) & 0x0f;
-+ if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) {
-+ hw->hw_token &= ~cpu_to_hc32(fotg210, QTD_TOGGLE);
-+ usb_settoggle(qh->dev, epnum, is_out, 1);
-+ }
-+ }
-+
-+ hw->hw_token &= cpu_to_hc32(fotg210, QTD_TOGGLE | QTD_STS_PING);
-+}
-+
-+/* if it weren't for a common silicon quirk (writing the dummy into the qh
-+ * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
-+ * recovery (including urb dequeue) would need software changes to a QH...
-+ */
-+static void qh_refresh(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+ struct fotg210_qtd *qtd;
-+
-+ if (list_empty(&qh->qtd_list))
-+ qtd = qh->dummy;
-+ else {
-+ qtd = list_entry(qh->qtd_list.next,
-+ struct fotg210_qtd, qtd_list);
-+ /*
-+ * first qtd may already be partially processed.
-+ * If we come here during unlink, the QH overlay region
-+ * might have reference to the just unlinked qtd. The
-+ * qtd is updated in qh_completions(). Update the QH
-+ * overlay here.
-+ */
-+ if (cpu_to_hc32(fotg210, qtd->qtd_dma) == qh->hw->hw_current) {
-+ qh->hw->hw_qtd_next = qtd->hw_next;
-+ qtd = NULL;
-+ }
-+ }
-+
-+ if (qtd)
-+ qh_update(fotg210, qh, qtd);
-+}
-+
-+static void qh_link_async(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
-+
-+static void fotg210_clear_tt_buffer_complete(struct usb_hcd *hcd,
-+ struct usb_host_endpoint *ep)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+ struct fotg210_qh *qh = ep->hcpriv;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ qh->clearing_tt = 0;
-+ if (qh->qh_state == QH_STATE_IDLE && !list_empty(&qh->qtd_list)
-+ && fotg210->rh_state == FOTG210_RH_RUNNING)
-+ qh_link_async(fotg210, qh);
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+}
-+
-+static void fotg210_clear_tt_buffer(struct fotg210_hcd *fotg210,
-+ struct fotg210_qh *qh, struct urb *urb, u32 token)
-+{
-+
-+ /* If an async split transaction gets an error or is unlinked,
-+ * the TT buffer may be left in an indeterminate state. We
-+ * have to clear the TT buffer.
-+ *
-+ * Note: this routine is never called for Isochronous transfers.
-+ */
-+ if (urb->dev->tt && !usb_pipeint(urb->pipe) && !qh->clearing_tt) {
-+ struct usb_device *tt = urb->dev->tt->hub;
-+
-+ dev_dbg(&tt->dev,
-+ "clear tt buffer port %d, a%d ep%d t%08x\n",
-+ urb->dev->ttport, urb->dev->devnum,
-+ usb_pipeendpoint(urb->pipe), token);
-+
-+ if (urb->dev->tt->hub !=
-+ fotg210_to_hcd(fotg210)->self.root_hub) {
-+ if (usb_hub_clear_tt_buffer(urb) == 0)
-+ qh->clearing_tt = 1;
-+ }
-+ }
-+}
-+
-+static int qtd_copy_status(struct fotg210_hcd *fotg210, struct urb *urb,
-+ size_t length, u32 token)
-+{
-+ int status = -EINPROGRESS;
-+
-+ /* count IN/OUT bytes, not SETUP (even short packets) */
-+ if (likely(QTD_PID(token) != 2))
-+ urb->actual_length += length - QTD_LENGTH(token);
-+
-+ /* don't modify error codes */
-+ if (unlikely(urb->unlinked))
-+ return status;
-+
-+ /* force cleanup after short read; not always an error */
-+ if (unlikely(IS_SHORT_READ(token)))
-+ status = -EREMOTEIO;
-+
-+ /* serious "can't proceed" faults reported by the hardware */
-+ if (token & QTD_STS_HALT) {
-+ if (token & QTD_STS_BABBLE) {
-+ /* FIXME "must" disable babbling device's port too */
-+ status = -EOVERFLOW;
-+ /* CERR nonzero + halt --> stall */
-+ } else if (QTD_CERR(token)) {
-+ status = -EPIPE;
-+
-+ /* In theory, more than one of the following bits can be set
-+ * since they are sticky and the transaction is retried.
-+ * Which to test first is rather arbitrary.
-+ */
-+ } else if (token & QTD_STS_MMF) {
-+ /* fs/ls interrupt xfer missed the complete-split */
-+ status = -EPROTO;
-+ } else if (token & QTD_STS_DBE) {
-+ status = (QTD_PID(token) == 1) /* IN ? */
-+ ? -ENOSR /* hc couldn't read data */
-+ : -ECOMM; /* hc couldn't write data */
-+ } else if (token & QTD_STS_XACT) {
-+ /* timeout, bad CRC, wrong PID, etc */
-+ fotg210_dbg(fotg210, "devpath %s ep%d%s 3strikes\n",
-+ urb->dev->devpath,
-+ usb_pipeendpoint(urb->pipe),
-+ usb_pipein(urb->pipe) ? "in" : "out");
-+ status = -EPROTO;
-+ } else { /* unknown */
-+ status = -EPROTO;
-+ }
-+
-+ fotg210_dbg(fotg210,
-+ "dev%d ep%d%s qtd token %08x --> status %d\n",
-+ usb_pipedevice(urb->pipe),
-+ usb_pipeendpoint(urb->pipe),
-+ usb_pipein(urb->pipe) ? "in" : "out",
-+ token, status);
-+ }
-+
-+ return status;
-+}
-+
-+static void fotg210_urb_done(struct fotg210_hcd *fotg210, struct urb *urb,
-+ int status)
-+__releases(fotg210->lock)
-+__acquires(fotg210->lock)
-+{
-+ if (likely(urb->hcpriv != NULL)) {
-+ struct fotg210_qh *qh = (struct fotg210_qh *) urb->hcpriv;
-+
-+ /* S-mask in a QH means it's an interrupt urb */
-+ if ((qh->hw->hw_info2 & cpu_to_hc32(fotg210, QH_SMASK)) != 0) {
-+
-+ /* ... update hc-wide periodic stats (for usbfs) */
-+ fotg210_to_hcd(fotg210)->self.bandwidth_int_reqs--;
-+ }
-+ }
-+
-+ if (unlikely(urb->unlinked)) {
-+ INCR(fotg210->stats.unlink);
-+ } else {
-+ /* report non-error and short read status as zero */
-+ if (status == -EINPROGRESS || status == -EREMOTEIO)
-+ status = 0;
-+ INCR(fotg210->stats.complete);
-+ }
-+
-+#ifdef FOTG210_URB_TRACE
-+ fotg210_dbg(fotg210,
-+ "%s %s urb %p ep%d%s status %d len %d/%d\n",
-+ __func__, urb->dev->devpath, urb,
-+ usb_pipeendpoint(urb->pipe),
-+ usb_pipein(urb->pipe) ? "in" : "out",
-+ status,
-+ urb->actual_length, urb->transfer_buffer_length);
-+#endif
-+
-+ /* complete() can reenter this HCD */
-+ usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
-+ spin_unlock(&fotg210->lock);
-+ usb_hcd_giveback_urb(fotg210_to_hcd(fotg210), urb, status);
-+ spin_lock(&fotg210->lock);
-+}
-+
-+static int qh_schedule(struct fotg210_hcd *fotg210, struct fotg210_qh *qh);
-+
-+/* Process and free completed qtds for a qh, returning URBs to drivers.
-+ * Chases up to qh->hw_current. Returns number of completions called,
-+ * indicating how much "real" work we did.
-+ */
-+static unsigned qh_completions(struct fotg210_hcd *fotg210,
-+ struct fotg210_qh *qh)
-+{
-+ struct fotg210_qtd *last, *end = qh->dummy;
-+ struct fotg210_qtd *qtd, *tmp;
-+ int last_status;
-+ int stopped;
-+ unsigned count = 0;
-+ u8 state;
-+ struct fotg210_qh_hw *hw = qh->hw;
-+
-+ if (unlikely(list_empty(&qh->qtd_list)))
-+ return count;
-+
-+ /* completions (or tasks on other cpus) must never clobber HALT
-+ * till we've gone through and cleaned everything up, even when
-+ * they add urbs to this qh's queue or mark them for unlinking.
-+ *
-+ * NOTE: unlinking expects to be done in queue order.
-+ *
-+ * It's a bug for qh->qh_state to be anything other than
-+ * QH_STATE_IDLE, unless our caller is scan_async() or
-+ * scan_intr().
-+ */
-+ state = qh->qh_state;
-+ qh->qh_state = QH_STATE_COMPLETING;
-+ stopped = (state == QH_STATE_IDLE);
-+
-+rescan:
-+ last = NULL;
-+ last_status = -EINPROGRESS;
-+ qh->needs_rescan = 0;
-+
-+ /* remove de-activated QTDs from front of queue.
-+ * after faults (including short reads), cleanup this urb
-+ * then let the queue advance.
-+ * if queue is stopped, handles unlinks.
-+ */
-+ list_for_each_entry_safe(qtd, tmp, &qh->qtd_list, qtd_list) {
-+ struct urb *urb;
-+ u32 token = 0;
-+
-+ urb = qtd->urb;
-+
-+ /* clean up any state from previous QTD ...*/
-+ if (last) {
-+ if (likely(last->urb != urb)) {
-+ fotg210_urb_done(fotg210, last->urb,
-+ last_status);
-+ count++;
-+ last_status = -EINPROGRESS;
-+ }
-+ fotg210_qtd_free(fotg210, last);
-+ last = NULL;
-+ }
-+
-+ /* ignore urbs submitted during completions we reported */
-+ if (qtd == end)
-+ break;
-+
-+ /* hardware copies qtd out of qh overlay */
-+ rmb();
-+ token = hc32_to_cpu(fotg210, qtd->hw_token);
-+
-+ /* always clean up qtds the hc de-activated */
-+retry_xacterr:
-+ if ((token & QTD_STS_ACTIVE) == 0) {
-+
-+ /* Report Data Buffer Error: non-fatal but useful */
-+ if (token & QTD_STS_DBE)
-+ fotg210_dbg(fotg210,
-+ "detected DataBufferErr for urb %p ep%d%s len %d, qtd %p [qh %p]\n",
-+ urb, usb_endpoint_num(&urb->ep->desc),
-+ usb_endpoint_dir_in(&urb->ep->desc)
-+ ? "in" : "out",
-+ urb->transfer_buffer_length, qtd, qh);
-+
-+ /* on STALL, error, and short reads this urb must
-+ * complete and all its qtds must be recycled.
-+ */
-+ if ((token & QTD_STS_HALT) != 0) {
-+
-+ /* retry transaction errors until we
-+ * reach the software xacterr limit
-+ */
-+ if ((token & QTD_STS_XACT) &&
-+ QTD_CERR(token) == 0 &&
-+ ++qh->xacterrs < QH_XACTERR_MAX &&
-+ !urb->unlinked) {
-+ fotg210_dbg(fotg210,
-+ "detected XactErr len %zu/%zu retry %d\n",
-+ qtd->length - QTD_LENGTH(token),
-+ qtd->length,
-+ qh->xacterrs);
-+
-+ /* reset the token in the qtd and the
-+ * qh overlay (which still contains
-+ * the qtd) so that we pick up from
-+ * where we left off
-+ */
-+ token &= ~QTD_STS_HALT;
-+ token |= QTD_STS_ACTIVE |
-+ (FOTG210_TUNE_CERR << 10);
-+ qtd->hw_token = cpu_to_hc32(fotg210,
-+ token);
-+ wmb();
-+ hw->hw_token = cpu_to_hc32(fotg210,
-+ token);
-+ goto retry_xacterr;
-+ }
-+ stopped = 1;
-+
-+ /* magic dummy for some short reads; qh won't advance.
-+ * that silicon quirk can kick in with this dummy too.
-+ *
-+ * other short reads won't stop the queue, including
-+ * control transfers (status stage handles that) or
-+ * most other single-qtd reads ... the queue stops if
-+ * URB_SHORT_NOT_OK was set so the driver submitting
-+ * the urbs could clean it up.
-+ */
-+ } else if (IS_SHORT_READ(token) &&
-+ !(qtd->hw_alt_next &
-+ FOTG210_LIST_END(fotg210))) {
-+ stopped = 1;
-+ }
-+
-+ /* stop scanning when we reach qtds the hc is using */
-+ } else if (likely(!stopped
-+ && fotg210->rh_state >= FOTG210_RH_RUNNING)) {
-+ break;
-+
-+ /* scan the whole queue for unlinks whenever it stops */
-+ } else {
-+ stopped = 1;
-+
-+ /* cancel everything if we halt, suspend, etc */
-+ if (fotg210->rh_state < FOTG210_RH_RUNNING)
-+ last_status = -ESHUTDOWN;
-+
-+ /* this qtd is active; skip it unless a previous qtd
-+ * for its urb faulted, or its urb was canceled.
-+ */
-+ else if (last_status == -EINPROGRESS && !urb->unlinked)
-+ continue;
-+
-+ /* qh unlinked; token in overlay may be most current */
-+ if (state == QH_STATE_IDLE &&
-+ cpu_to_hc32(fotg210, qtd->qtd_dma)
-+ == hw->hw_current) {
-+ token = hc32_to_cpu(fotg210, hw->hw_token);
-+
-+ /* An unlink may leave an incomplete
-+ * async transaction in the TT buffer.
-+ * We have to clear it.
-+ */
-+ fotg210_clear_tt_buffer(fotg210, qh, urb,
-+ token);
-+ }
-+ }
-+
-+ /* unless we already know the urb's status, collect qtd status
-+ * and update count of bytes transferred. in common short read
-+ * cases with only one data qtd (including control transfers),
-+ * queue processing won't halt. but with two or more qtds (for
-+ * example, with a 32 KB transfer), when the first qtd gets a
-+ * short read the second must be removed by hand.
-+ */
-+ if (last_status == -EINPROGRESS) {
-+ last_status = qtd_copy_status(fotg210, urb,
-+ qtd->length, token);
-+ if (last_status == -EREMOTEIO &&
-+ (qtd->hw_alt_next &
-+ FOTG210_LIST_END(fotg210)))
-+ last_status = -EINPROGRESS;
-+
-+ /* As part of low/full-speed endpoint-halt processing
-+ * we must clear the TT buffer (11.17.5).
-+ */
-+ if (unlikely(last_status != -EINPROGRESS &&
-+ last_status != -EREMOTEIO)) {
-+ /* The TT's in some hubs malfunction when they
-+ * receive this request following a STALL (they
-+ * stop sending isochronous packets). Since a
-+ * STALL can't leave the TT buffer in a busy
-+ * state (if you believe Figures 11-48 - 11-51
-+ * in the USB 2.0 spec), we won't clear the TT
-+ * buffer in this case. Strictly speaking this
-+ * is a violation of the spec.
-+ */
-+ if (last_status != -EPIPE)
-+ fotg210_clear_tt_buffer(fotg210, qh,
-+ urb, token);
-+ }
-+ }
-+
-+ /* if we're removing something not at the queue head,
-+ * patch the hardware queue pointer.
-+ */
-+ if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
-+ last = list_entry(qtd->qtd_list.prev,
-+ struct fotg210_qtd, qtd_list);
-+ last->hw_next = qtd->hw_next;
-+ }
-+
-+ /* remove qtd; it's recycled after possible urb completion */
-+ list_del(&qtd->qtd_list);
-+ last = qtd;
-+
-+ /* reinit the xacterr counter for the next qtd */
-+ qh->xacterrs = 0;
-+ }
-+
-+ /* last urb's completion might still need calling */
-+ if (likely(last != NULL)) {
-+ fotg210_urb_done(fotg210, last->urb, last_status);
-+ count++;
-+ fotg210_qtd_free(fotg210, last);
-+ }
-+
-+ /* Do we need to rescan for URBs dequeued during a giveback? */
-+ if (unlikely(qh->needs_rescan)) {
-+ /* If the QH is already unlinked, do the rescan now. */
-+ if (state == QH_STATE_IDLE)
-+ goto rescan;
-+
-+ /* Otherwise we have to wait until the QH is fully unlinked.
-+ * Our caller will start an unlink if qh->needs_rescan is
-+ * set. But if an unlink has already started, nothing needs
-+ * to be done.
-+ */
-+ if (state != QH_STATE_LINKED)
-+ qh->needs_rescan = 0;
-+ }
-+
-+ /* restore original state; caller must unlink or relink */
-+ qh->qh_state = state;
-+
-+ /* be sure the hardware's done with the qh before refreshing
-+ * it after fault cleanup, or recovering from silicon wrongly
-+ * overlaying the dummy qtd (which reduces DMA chatter).
-+ */
-+ if (stopped != 0 || hw->hw_qtd_next == FOTG210_LIST_END(fotg210)) {
-+ switch (state) {
-+ case QH_STATE_IDLE:
-+ qh_refresh(fotg210, qh);
-+ break;
-+ case QH_STATE_LINKED:
-+ /* We won't refresh a QH that's linked (after the HC
-+ * stopped the queue). That avoids a race:
-+ * - HC reads first part of QH;
-+ * - CPU updates that first part and the token;
-+ * - HC reads rest of that QH, including token
-+ * Result: HC gets an inconsistent image, and then
-+ * DMAs to/from the wrong memory (corrupting it).
-+ *
-+ * That should be rare for interrupt transfers,
-+ * except maybe high bandwidth ...
-+ */
-+
-+ /* Tell the caller to start an unlink */
-+ qh->needs_rescan = 1;
-+ break;
-+ /* otherwise, unlink already started */
-+ }
-+ }
-+
-+ return count;
-+}
-+
-+/* reverse of qh_urb_transaction: free a list of TDs.
-+ * used for cleanup after errors, before HC sees an URB's TDs.
-+ */
-+static void qtd_list_free(struct fotg210_hcd *fotg210, struct urb *urb,
-+ struct list_head *head)
-+{
-+ struct fotg210_qtd *qtd, *temp;
-+
-+ list_for_each_entry_safe(qtd, temp, head, qtd_list) {
-+ list_del(&qtd->qtd_list);
-+ fotg210_qtd_free(fotg210, qtd);
-+ }
-+}
-+
-+/* create a list of filled qtds for this URB; won't link into qh.
-+ */
-+static struct list_head *qh_urb_transaction(struct fotg210_hcd *fotg210,
-+ struct urb *urb, struct list_head *head, gfp_t flags)
-+{
-+ struct fotg210_qtd *qtd, *qtd_prev;
-+ dma_addr_t buf;
-+ int len, this_sg_len, maxpacket;
-+ int is_input;
-+ u32 token;
-+ int i;
-+ struct scatterlist *sg;
-+
-+ /*
-+ * URBs map to sequences of QTDs: one logical transaction
-+ */
-+ qtd = fotg210_qtd_alloc(fotg210, flags);
-+ if (unlikely(!qtd))
-+ return NULL;
-+ list_add_tail(&qtd->qtd_list, head);
-+ qtd->urb = urb;
-+
-+ token = QTD_STS_ACTIVE;
-+ token |= (FOTG210_TUNE_CERR << 10);
-+ /* for split transactions, SplitXState initialized to zero */
-+
-+ len = urb->transfer_buffer_length;
-+ is_input = usb_pipein(urb->pipe);
-+ if (usb_pipecontrol(urb->pipe)) {
-+ /* SETUP pid */
-+ qtd_fill(fotg210, qtd, urb->setup_dma,
-+ sizeof(struct usb_ctrlrequest),
-+ token | (2 /* "setup" */ << 8), 8);
-+
-+ /* ... and always at least one more pid */
-+ token ^= QTD_TOGGLE;
-+ qtd_prev = qtd;
-+ qtd = fotg210_qtd_alloc(fotg210, flags);
-+ if (unlikely(!qtd))
-+ goto cleanup;
-+ qtd->urb = urb;
-+ qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-+ list_add_tail(&qtd->qtd_list, head);
-+
-+ /* for zero length DATA stages, STATUS is always IN */
-+ if (len == 0)
-+ token |= (1 /* "in" */ << 8);
-+ }
-+
-+ /*
-+ * data transfer stage: buffer setup
-+ */
-+ i = urb->num_mapped_sgs;
-+ if (len > 0 && i > 0) {
-+ sg = urb->sg;
-+ buf = sg_dma_address(sg);
-+
-+ /* urb->transfer_buffer_length may be smaller than the
-+ * size of the scatterlist (or vice versa)
-+ */
-+ this_sg_len = min_t(int, sg_dma_len(sg), len);
-+ } else {
-+ sg = NULL;
-+ buf = urb->transfer_dma;
-+ this_sg_len = len;
-+ }
-+
-+ if (is_input)
-+ token |= (1 /* "in" */ << 8);
-+ /* else it's already initted to "out" pid (0 << 8) */
-+
-+ maxpacket = usb_maxpacket(urb->dev, urb->pipe);
-+
-+ /*
-+ * buffer gets wrapped in one or more qtds;
-+ * last one may be "short" (including zero len)
-+ * and may serve as a control status ack
-+ */
-+ for (;;) {
-+ int this_qtd_len;
-+
-+ this_qtd_len = qtd_fill(fotg210, qtd, buf, this_sg_len, token,
-+ maxpacket);
-+ this_sg_len -= this_qtd_len;
-+ len -= this_qtd_len;
-+ buf += this_qtd_len;
-+
-+ /*
-+ * short reads advance to a "magic" dummy instead of the next
-+ * qtd ... that forces the queue to stop, for manual cleanup.
-+ * (this will usually be overridden later.)
-+ */
-+ if (is_input)
-+ qtd->hw_alt_next = fotg210->async->hw->hw_alt_next;
-+
-+ /* qh makes control packets use qtd toggle; maybe switch it */
-+ if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
-+ token ^= QTD_TOGGLE;
-+
-+ if (likely(this_sg_len <= 0)) {
-+ if (--i <= 0 || len <= 0)
-+ break;
-+ sg = sg_next(sg);
-+ buf = sg_dma_address(sg);
-+ this_sg_len = min_t(int, sg_dma_len(sg), len);
-+ }
-+
-+ qtd_prev = qtd;
-+ qtd = fotg210_qtd_alloc(fotg210, flags);
-+ if (unlikely(!qtd))
-+ goto cleanup;
-+ qtd->urb = urb;
-+ qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-+ list_add_tail(&qtd->qtd_list, head);
-+ }
-+
-+ /*
-+ * unless the caller requires manual cleanup after short reads,
-+ * have the alt_next mechanism keep the queue running after the
-+ * last data qtd (the only one, for control and most other cases).
-+ */
-+ if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0 ||
-+ usb_pipecontrol(urb->pipe)))
-+ qtd->hw_alt_next = FOTG210_LIST_END(fotg210);
-+
-+ /*
-+ * control requests may need a terminating data "status" ack;
-+ * other OUT ones may need a terminating short packet
-+ * (zero length).
-+ */
-+ if (likely(urb->transfer_buffer_length != 0)) {
-+ int one_more = 0;
-+
-+ if (usb_pipecontrol(urb->pipe)) {
-+ one_more = 1;
-+ token ^= 0x0100; /* "in" <--> "out" */
-+ token |= QTD_TOGGLE; /* force DATA1 */
-+ } else if (usb_pipeout(urb->pipe)
-+ && (urb->transfer_flags & URB_ZERO_PACKET)
-+ && !(urb->transfer_buffer_length % maxpacket)) {
-+ one_more = 1;
-+ }
-+ if (one_more) {
-+ qtd_prev = qtd;
-+ qtd = fotg210_qtd_alloc(fotg210, flags);
-+ if (unlikely(!qtd))
-+ goto cleanup;
-+ qtd->urb = urb;
-+ qtd_prev->hw_next = QTD_NEXT(fotg210, qtd->qtd_dma);
-+ list_add_tail(&qtd->qtd_list, head);
-+
-+ /* never any data in such packets */
-+ qtd_fill(fotg210, qtd, 0, 0, token, 0);
-+ }
-+ }
-+
-+ /* by default, enable interrupt on urb completion */
-+ if (likely(!(urb->transfer_flags & URB_NO_INTERRUPT)))
-+ qtd->hw_token |= cpu_to_hc32(fotg210, QTD_IOC);
-+ return head;
-+
-+cleanup:
-+ qtd_list_free(fotg210, urb, head);
-+ return NULL;
-+}
-+
-+/* Would be best to create all qh's from config descriptors,
-+ * when each interface/altsetting is established. Unlink
-+ * any previous qh and cancel its urbs first; endpoints are
-+ * implicitly reset then (data toggle too).
-+ * That'd mean updating how usbcore talks to HCDs. (2.7?)
-+ */
-+
-+
-+/* Each QH holds a qtd list; a QH is used for everything except iso.
-+ *
-+ * For interrupt urbs, the scheduler must set the microframe scheduling
-+ * mask(s) each time the QH gets scheduled. For highspeed, that's
-+ * just one microframe in the s-mask. For split interrupt transactions
-+ * there are additional complications: c-mask, maybe FSTNs.
-+ */
-+static struct fotg210_qh *qh_make(struct fotg210_hcd *fotg210, struct urb *urb,
-+ gfp_t flags)
-+{
-+ struct fotg210_qh *qh = fotg210_qh_alloc(fotg210, flags);
-+ struct usb_host_endpoint *ep;
-+ u32 info1 = 0, info2 = 0;
-+ int is_input, type;
-+ int maxp = 0;
-+ int mult;
-+ struct usb_tt *tt = urb->dev->tt;
-+ struct fotg210_qh_hw *hw;
-+
-+ if (!qh)
-+ return qh;
-+
-+ /*
-+ * init endpoint/device data for this QH
-+ */
-+ info1 |= usb_pipeendpoint(urb->pipe) << 8;
-+ info1 |= usb_pipedevice(urb->pipe) << 0;
-+
-+ is_input = usb_pipein(urb->pipe);
-+ type = usb_pipetype(urb->pipe);
-+ ep = usb_pipe_endpoint(urb->dev, urb->pipe);
-+ maxp = usb_endpoint_maxp(&ep->desc);
-+ mult = usb_endpoint_maxp_mult(&ep->desc);
-+
-+ /* 1024 byte maxpacket is a hardware ceiling. High bandwidth
-+ * acts like up to 3KB, but is built from smaller packets.
-+ */
-+ if (maxp > 1024) {
-+ fotg210_dbg(fotg210, "bogus qh maxpacket %d\n", maxp);
-+ goto done;
-+ }
-+
-+ /* Compute interrupt scheduling parameters just once, and save.
-+ * - allowing for high bandwidth, how many nsec/uframe are used?
-+ * - split transactions need a second CSPLIT uframe; same question
-+ * - splits also need a schedule gap (for full/low speed I/O)
-+ * - qh has a polling interval
-+ *
-+ * For control/bulk requests, the HC or TT handles these.
-+ */
-+ if (type == PIPE_INTERRUPT) {
-+ qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH,
-+ is_input, 0, mult * maxp));
-+ qh->start = NO_FRAME;
-+
-+ if (urb->dev->speed == USB_SPEED_HIGH) {
-+ qh->c_usecs = 0;
-+ qh->gap_uf = 0;
-+
-+ qh->period = urb->interval >> 3;
-+ if (qh->period == 0 && urb->interval != 1) {
-+ /* NOTE interval 2 or 4 uframes could work.
-+ * But interval 1 scheduling is simpler, and
-+ * includes high bandwidth.
-+ */
-+ urb->interval = 1;
-+ } else if (qh->period > fotg210->periodic_size) {
-+ qh->period = fotg210->periodic_size;
-+ urb->interval = qh->period << 3;
-+ }
-+ } else {
-+ int think_time;
-+
-+ /* gap is f(FS/LS transfer times) */
-+ qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed,
-+ is_input, 0, maxp) / (125 * 1000);
-+
-+ /* FIXME this just approximates SPLIT/CSPLIT times */
-+ if (is_input) { /* SPLIT, gap, CSPLIT+DATA */
-+ qh->c_usecs = qh->usecs + HS_USECS(0);
-+ qh->usecs = HS_USECS(1);
-+ } else { /* SPLIT+DATA, gap, CSPLIT */
-+ qh->usecs += HS_USECS(1);
-+ qh->c_usecs = HS_USECS(0);
-+ }
-+
-+ think_time = tt ? tt->think_time : 0;
-+ qh->tt_usecs = NS_TO_US(think_time +
-+ usb_calc_bus_time(urb->dev->speed,
-+ is_input, 0, maxp));
-+ qh->period = urb->interval;
-+ if (qh->period > fotg210->periodic_size) {
-+ qh->period = fotg210->periodic_size;
-+ urb->interval = qh->period;
-+ }
-+ }
-+ }
-+
-+ /* support for tt scheduling, and access to toggles */
-+ qh->dev = urb->dev;
-+
-+ /* using TT? */
-+ switch (urb->dev->speed) {
-+ case USB_SPEED_LOW:
-+ info1 |= QH_LOW_SPEED;
-+ fallthrough;
-+
-+ case USB_SPEED_FULL:
-+ /* EPS 0 means "full" */
-+ if (type != PIPE_INTERRUPT)
-+ info1 |= (FOTG210_TUNE_RL_TT << 28);
-+ if (type == PIPE_CONTROL) {
-+ info1 |= QH_CONTROL_EP; /* for TT */
-+ info1 |= QH_TOGGLE_CTL; /* toggle from qtd */
-+ }
-+ info1 |= maxp << 16;
-+
-+ info2 |= (FOTG210_TUNE_MULT_TT << 30);
-+
-+ /* Some Freescale processors have an erratum in which the
-+ * port number in the queue head was 0..N-1 instead of 1..N.
-+ */
-+ if (fotg210_has_fsl_portno_bug(fotg210))
-+ info2 |= (urb->dev->ttport-1) << 23;
-+ else
-+ info2 |= urb->dev->ttport << 23;
-+
-+ /* set the address of the TT; for TDI's integrated
-+ * root hub tt, leave it zeroed.
-+ */
-+ if (tt && tt->hub != fotg210_to_hcd(fotg210)->self.root_hub)
-+ info2 |= tt->hub->devnum << 16;
-+
-+ /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */
-+
-+ break;
-+
-+ case USB_SPEED_HIGH: /* no TT involved */
-+ info1 |= QH_HIGH_SPEED;
-+ if (type == PIPE_CONTROL) {
-+ info1 |= (FOTG210_TUNE_RL_HS << 28);
-+ info1 |= 64 << 16; /* usb2 fixed maxpacket */
-+ info1 |= QH_TOGGLE_CTL; /* toggle from qtd */
-+ info2 |= (FOTG210_TUNE_MULT_HS << 30);
-+ } else if (type == PIPE_BULK) {
-+ info1 |= (FOTG210_TUNE_RL_HS << 28);
-+ /* The USB spec says that high speed bulk endpoints
-+ * always use 512 byte maxpacket. But some device
-+ * vendors decided to ignore that, and MSFT is happy
-+ * to help them do so. So now people expect to use
-+ * such nonconformant devices with Linux too; sigh.
-+ */
-+ info1 |= maxp << 16;
-+ info2 |= (FOTG210_TUNE_MULT_HS << 30);
-+ } else { /* PIPE_INTERRUPT */
-+ info1 |= maxp << 16;
-+ info2 |= mult << 30;
-+ }
-+ break;
-+ default:
-+ fotg210_dbg(fotg210, "bogus dev %p speed %d\n", urb->dev,
-+ urb->dev->speed);
-+done:
-+ qh_destroy(fotg210, qh);
-+ return NULL;
-+ }
-+
-+ /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */
-+
-+ /* init as live, toggle clear, advance to dummy */
-+ qh->qh_state = QH_STATE_IDLE;
-+ hw = qh->hw;
-+ hw->hw_info1 = cpu_to_hc32(fotg210, info1);
-+ hw->hw_info2 = cpu_to_hc32(fotg210, info2);
-+ qh->is_out = !is_input;
-+ usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1);
-+ qh_refresh(fotg210, qh);
-+ return qh;
-+}
-+
-+static void enable_async(struct fotg210_hcd *fotg210)
-+{
-+ if (fotg210->async_count++)
-+ return;
-+
-+ /* Stop waiting to turn off the async schedule */
-+ fotg210->enabled_hrtimer_events &= ~BIT(FOTG210_HRTIMER_DISABLE_ASYNC);
-+
-+ /* Don't start the schedule until ASS is 0 */
-+ fotg210_poll_ASS(fotg210);
-+ turn_on_io_watchdog(fotg210);
-+}
-+
-+static void disable_async(struct fotg210_hcd *fotg210)
-+{
-+ if (--fotg210->async_count)
-+ return;
-+
-+ /* The async schedule and async_unlink list are supposed to be empty */
-+ WARN_ON(fotg210->async->qh_next.qh || fotg210->async_unlink);
-+
-+ /* Don't turn off the schedule until ASS is 1 */
-+ fotg210_poll_ASS(fotg210);
-+}
-+
-+/* move qh (and its qtds) onto async queue; maybe enable queue. */
-+
-+static void qh_link_async(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+ __hc32 dma = QH_NEXT(fotg210, qh->qh_dma);
-+ struct fotg210_qh *head;
-+
-+ /* Don't link a QH if there's a Clear-TT-Buffer pending */
-+ if (unlikely(qh->clearing_tt))
-+ return;
-+
-+ WARN_ON(qh->qh_state != QH_STATE_IDLE);
-+
-+ /* clear halt and/or toggle; and maybe recover from silicon quirk */
-+ qh_refresh(fotg210, qh);
-+
-+ /* splice right after start */
-+ head = fotg210->async;
-+ qh->qh_next = head->qh_next;
-+ qh->hw->hw_next = head->hw->hw_next;
-+ wmb();
-+
-+ head->qh_next.qh = qh;
-+ head->hw->hw_next = dma;
-+
-+ qh->xacterrs = 0;
-+ qh->qh_state = QH_STATE_LINKED;
-+ /* qtd completions reported later by interrupt */
-+
-+ enable_async(fotg210);
-+}
-+
-+/* For control/bulk/interrupt, return QH with these TDs appended.
-+ * Allocates and initializes the QH if necessary.
-+ * Returns null if it can't allocate a QH it needs to.
-+ * If the QH has TDs (urbs) already, that's great.
-+ */
-+static struct fotg210_qh *qh_append_tds(struct fotg210_hcd *fotg210,
-+ struct urb *urb, struct list_head *qtd_list,
-+ int epnum, void **ptr)
-+{
-+ struct fotg210_qh *qh = NULL;
-+ __hc32 qh_addr_mask = cpu_to_hc32(fotg210, 0x7f);
-+
-+ qh = (struct fotg210_qh *) *ptr;
-+ if (unlikely(qh == NULL)) {
-+ /* can't sleep here, we have fotg210->lock... */
-+ qh = qh_make(fotg210, urb, GFP_ATOMIC);
-+ *ptr = qh;
-+ }
-+ if (likely(qh != NULL)) {
-+ struct fotg210_qtd *qtd;
-+
-+ if (unlikely(list_empty(qtd_list)))
-+ qtd = NULL;
-+ else
-+ qtd = list_entry(qtd_list->next, struct fotg210_qtd,
-+ qtd_list);
-+
-+ /* control qh may need patching ... */
-+ if (unlikely(epnum == 0)) {
-+ /* usb_reset_device() briefly reverts to address 0 */
-+ if (usb_pipedevice(urb->pipe) == 0)
-+ qh->hw->hw_info1 &= ~qh_addr_mask;
-+ }
-+
-+ /* just one way to queue requests: swap with the dummy qtd.
-+ * only hc or qh_refresh() ever modify the overlay.
-+ */
-+ if (likely(qtd != NULL)) {
-+ struct fotg210_qtd *dummy;
-+ dma_addr_t dma;
-+ __hc32 token;
-+
-+ /* to avoid racing the HC, use the dummy td instead of
-+ * the first td of our list (becomes new dummy). both
-+ * tds stay deactivated until we're done, when the
-+ * HC is allowed to fetch the old dummy (4.10.2).
-+ */
-+ token = qtd->hw_token;
-+ qtd->hw_token = HALT_BIT(fotg210);
-+
-+ dummy = qh->dummy;
-+
-+ dma = dummy->qtd_dma;
-+ *dummy = *qtd;
-+ dummy->qtd_dma = dma;
-+
-+ list_del(&qtd->qtd_list);
-+ list_add(&dummy->qtd_list, qtd_list);
-+ list_splice_tail(qtd_list, &qh->qtd_list);
-+
-+ fotg210_qtd_init(fotg210, qtd, qtd->qtd_dma);
-+ qh->dummy = qtd;
-+
-+ /* hc must see the new dummy at list end */
-+ dma = qtd->qtd_dma;
-+ qtd = list_entry(qh->qtd_list.prev,
-+ struct fotg210_qtd, qtd_list);
-+ qtd->hw_next = QTD_NEXT(fotg210, dma);
-+
-+ /* let the hc process these next qtds */
-+ wmb();
-+ dummy->hw_token = token;
-+
-+ urb->hcpriv = qh;
-+ }
-+ }
-+ return qh;
-+}
-+
-+static int submit_async(struct fotg210_hcd *fotg210, struct urb *urb,
-+ struct list_head *qtd_list, gfp_t mem_flags)
-+{
-+ int epnum;
-+ unsigned long flags;
-+ struct fotg210_qh *qh = NULL;
-+ int rc;
-+
-+ epnum = urb->ep->desc.bEndpointAddress;
-+
-+#ifdef FOTG210_URB_TRACE
-+ {
-+ struct fotg210_qtd *qtd;
-+
-+ qtd = list_entry(qtd_list->next, struct fotg210_qtd, qtd_list);
-+ fotg210_dbg(fotg210,
-+ "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
-+ __func__, urb->dev->devpath, urb,
-+ epnum & 0x0f, (epnum & USB_DIR_IN)
-+ ? "in" : "out",
-+ urb->transfer_buffer_length,
-+ qtd, urb->ep->hcpriv);
-+ }
-+#endif
-+
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
-+ rc = -ESHUTDOWN;
-+ goto done;
-+ }
-+ rc = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
-+ if (unlikely(rc))
-+ goto done;
-+
-+ qh = qh_append_tds(fotg210, urb, qtd_list, epnum, &urb->ep->hcpriv);
-+ if (unlikely(qh == NULL)) {
-+ usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
-+ rc = -ENOMEM;
-+ goto done;
-+ }
-+
-+ /* Control/bulk operations through TTs don't need scheduling,
-+ * the HC and TT handle it when the TT has a buffer ready.
-+ */
-+ if (likely(qh->qh_state == QH_STATE_IDLE))
-+ qh_link_async(fotg210, qh);
-+done:
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ if (unlikely(qh == NULL))
-+ qtd_list_free(fotg210, urb, qtd_list);
-+ return rc;
-+}
-+
-+static void single_unlink_async(struct fotg210_hcd *fotg210,
-+ struct fotg210_qh *qh)
-+{
-+ struct fotg210_qh *prev;
-+
-+ /* Add to the end of the list of QHs waiting for the next IAAD */
-+ qh->qh_state = QH_STATE_UNLINK;
-+ if (fotg210->async_unlink)
-+ fotg210->async_unlink_last->unlink_next = qh;
-+ else
-+ fotg210->async_unlink = qh;
-+ fotg210->async_unlink_last = qh;
-+
-+ /* Unlink it from the schedule */
-+ prev = fotg210->async;
-+ while (prev->qh_next.qh != qh)
-+ prev = prev->qh_next.qh;
-+
-+ prev->hw->hw_next = qh->hw->hw_next;
-+ prev->qh_next = qh->qh_next;
-+ if (fotg210->qh_scan_next == qh)
-+ fotg210->qh_scan_next = qh->qh_next.qh;
-+}
-+
-+static void start_iaa_cycle(struct fotg210_hcd *fotg210, bool nested)
-+{
-+ /*
-+ * Do nothing if an IAA cycle is already running or
-+ * if one will be started shortly.
-+ */
-+ if (fotg210->async_iaa || fotg210->async_unlinking)
-+ return;
-+
-+ /* Do all the waiting QHs at once */
-+ fotg210->async_iaa = fotg210->async_unlink;
-+ fotg210->async_unlink = NULL;
-+
-+ /* If the controller isn't running, we don't have to wait for it */
-+ if (unlikely(fotg210->rh_state < FOTG210_RH_RUNNING)) {
-+ if (!nested) /* Avoid recursion */
-+ end_unlink_async(fotg210);
-+
-+ /* Otherwise start a new IAA cycle */
-+ } else if (likely(fotg210->rh_state == FOTG210_RH_RUNNING)) {
-+ /* Make sure the unlinks are all visible to the hardware */
-+ wmb();
-+
-+ fotg210_writel(fotg210, fotg210->command | CMD_IAAD,
-+ &fotg210->regs->command);
-+ fotg210_readl(fotg210, &fotg210->regs->command);
-+ fotg210_enable_event(fotg210, FOTG210_HRTIMER_IAA_WATCHDOG,
-+ true);
-+ }
-+}
-+
-+/* the async qh for the qtds being unlinked are now gone from the HC */
-+
-+static void end_unlink_async(struct fotg210_hcd *fotg210)
-+{
-+ struct fotg210_qh *qh;
-+
-+ /* Process the idle QHs */
-+restart:
-+ fotg210->async_unlinking = true;
-+ while (fotg210->async_iaa) {
-+ qh = fotg210->async_iaa;
-+ fotg210->async_iaa = qh->unlink_next;
-+ qh->unlink_next = NULL;
-+
-+ qh->qh_state = QH_STATE_IDLE;
-+ qh->qh_next.qh = NULL;
-+
-+ qh_completions(fotg210, qh);
-+ if (!list_empty(&qh->qtd_list) &&
-+ fotg210->rh_state == FOTG210_RH_RUNNING)
-+ qh_link_async(fotg210, qh);
-+ disable_async(fotg210);
-+ }
-+ fotg210->async_unlinking = false;
-+
-+ /* Start a new IAA cycle if any QHs are waiting for it */
-+ if (fotg210->async_unlink) {
-+ start_iaa_cycle(fotg210, true);
-+ if (unlikely(fotg210->rh_state < FOTG210_RH_RUNNING))
-+ goto restart;
-+ }
-+}
-+
-+static void unlink_empty_async(struct fotg210_hcd *fotg210)
-+{
-+ struct fotg210_qh *qh, *next;
-+ bool stopped = (fotg210->rh_state < FOTG210_RH_RUNNING);
-+ bool check_unlinks_later = false;
-+
-+ /* Unlink all the async QHs that have been empty for a timer cycle */
-+ next = fotg210->async->qh_next.qh;
-+ while (next) {
-+ qh = next;
-+ next = qh->qh_next.qh;
-+
-+ if (list_empty(&qh->qtd_list) &&
-+ qh->qh_state == QH_STATE_LINKED) {
-+ if (!stopped && qh->unlink_cycle ==
-+ fotg210->async_unlink_cycle)
-+ check_unlinks_later = true;
-+ else
-+ single_unlink_async(fotg210, qh);
-+ }
-+ }
-+
-+ /* Start a new IAA cycle if any QHs are waiting for it */
-+ if (fotg210->async_unlink)
-+ start_iaa_cycle(fotg210, false);
-+
-+ /* QHs that haven't been empty for long enough will be handled later */
-+ if (check_unlinks_later) {
-+ fotg210_enable_event(fotg210, FOTG210_HRTIMER_ASYNC_UNLINKS,
-+ true);
-+ ++fotg210->async_unlink_cycle;
-+ }
-+}
-+
-+/* makes sure the async qh will become idle */
-+/* caller must own fotg210->lock */
-+
-+static void start_unlink_async(struct fotg210_hcd *fotg210,
-+ struct fotg210_qh *qh)
-+{
-+ /*
-+ * If the QH isn't linked then there's nothing we can do
-+ * unless we were called during a giveback, in which case
-+ * qh_completions() has to deal with it.
-+ */
-+ if (qh->qh_state != QH_STATE_LINKED) {
-+ if (qh->qh_state == QH_STATE_COMPLETING)
-+ qh->needs_rescan = 1;
-+ return;
-+ }
-+
-+ single_unlink_async(fotg210, qh);
-+ start_iaa_cycle(fotg210, false);
-+}
-+
-+static void scan_async(struct fotg210_hcd *fotg210)
-+{
-+ struct fotg210_qh *qh;
-+ bool check_unlinks_later = false;
-+
-+ fotg210->qh_scan_next = fotg210->async->qh_next.qh;
-+ while (fotg210->qh_scan_next) {
-+ qh = fotg210->qh_scan_next;
-+ fotg210->qh_scan_next = qh->qh_next.qh;
-+rescan:
-+ /* clean any finished work for this qh */
-+ if (!list_empty(&qh->qtd_list)) {
-+ int temp;
-+
-+ /*
-+ * Unlinks could happen here; completion reporting
-+ * drops the lock. That's why fotg210->qh_scan_next
-+ * always holds the next qh to scan; if the next qh
-+ * gets unlinked then fotg210->qh_scan_next is adjusted
-+ * in single_unlink_async().
-+ */
-+ temp = qh_completions(fotg210, qh);
-+ if (qh->needs_rescan) {
-+ start_unlink_async(fotg210, qh);
-+ } else if (list_empty(&qh->qtd_list)
-+ && qh->qh_state == QH_STATE_LINKED) {
-+ qh->unlink_cycle = fotg210->async_unlink_cycle;
-+ check_unlinks_later = true;
-+ } else if (temp != 0)
-+ goto rescan;
-+ }
-+ }
-+
-+ /*
-+ * Unlink empty entries, reducing DMA usage as well
-+ * as HCD schedule-scanning costs. Delay for any qh
-+ * we just scanned, there's a not-unusual case that it
-+ * doesn't stay idle for long.
-+ */
-+ if (check_unlinks_later && fotg210->rh_state == FOTG210_RH_RUNNING &&
-+ !(fotg210->enabled_hrtimer_events &
-+ BIT(FOTG210_HRTIMER_ASYNC_UNLINKS))) {
-+ fotg210_enable_event(fotg210,
-+ FOTG210_HRTIMER_ASYNC_UNLINKS, true);
-+ ++fotg210->async_unlink_cycle;
-+ }
-+}
-+/* EHCI scheduled transaction support: interrupt, iso, split iso
-+ * These are called "periodic" transactions in the EHCI spec.
-+ *
-+ * Note that for interrupt transfers, the QH/QTD manipulation is shared
-+ * with the "asynchronous" transaction support (control/bulk transfers).
-+ * The only real difference is in how interrupt transfers are scheduled.
-+ *
-+ * For ISO, we make an "iso_stream" head to serve the same role as a QH.
-+ * It keeps track of every ITD (or SITD) that's linked, and holds enough
-+ * pre-calculated schedule data to make appending to the queue be quick.
-+ */
-+static int fotg210_get_frame(struct usb_hcd *hcd);
-+
-+/* periodic_next_shadow - return "next" pointer on shadow list
-+ * @periodic: host pointer to qh/itd
-+ * @tag: hardware tag for type of this record
-+ */
-+static union fotg210_shadow *periodic_next_shadow(struct fotg210_hcd *fotg210,
-+ union fotg210_shadow *periodic, __hc32 tag)
-+{
-+ switch (hc32_to_cpu(fotg210, tag)) {
-+ case Q_TYPE_QH:
-+ return &periodic->qh->qh_next;
-+ case Q_TYPE_FSTN:
-+ return &periodic->fstn->fstn_next;
-+ default:
-+ return &periodic->itd->itd_next;
-+ }
-+}
-+
-+static __hc32 *shadow_next_periodic(struct fotg210_hcd *fotg210,
-+ union fotg210_shadow *periodic, __hc32 tag)
-+{
-+ switch (hc32_to_cpu(fotg210, tag)) {
-+ /* our fotg210_shadow.qh is actually software part */
-+ case Q_TYPE_QH:
-+ return &periodic->qh->hw->hw_next;
-+ /* others are hw parts */
-+ default:
-+ return periodic->hw_next;
-+ }
-+}
-+
-+/* caller must hold fotg210->lock */
-+static void periodic_unlink(struct fotg210_hcd *fotg210, unsigned frame,
-+ void *ptr)
-+{
-+ union fotg210_shadow *prev_p = &fotg210->pshadow[frame];
-+ __hc32 *hw_p = &fotg210->periodic[frame];
-+ union fotg210_shadow here = *prev_p;
-+
-+ /* find predecessor of "ptr"; hw and shadow lists are in sync */
-+ while (here.ptr && here.ptr != ptr) {
-+ prev_p = periodic_next_shadow(fotg210, prev_p,
-+ Q_NEXT_TYPE(fotg210, *hw_p));
-+ hw_p = shadow_next_periodic(fotg210, &here,
-+ Q_NEXT_TYPE(fotg210, *hw_p));
-+ here = *prev_p;
-+ }
-+ /* an interrupt entry (at list end) could have been shared */
-+ if (!here.ptr)
-+ return;
-+
-+ /* update shadow and hardware lists ... the old "next" pointers
-+ * from ptr may still be in use, the caller updates them.
-+ */
-+ *prev_p = *periodic_next_shadow(fotg210, &here,
-+ Q_NEXT_TYPE(fotg210, *hw_p));
-+
-+ *hw_p = *shadow_next_periodic(fotg210, &here,
-+ Q_NEXT_TYPE(fotg210, *hw_p));
-+}
-+
-+/* how many of the uframe's 125 usecs are allocated? */
-+static unsigned short periodic_usecs(struct fotg210_hcd *fotg210,
-+ unsigned frame, unsigned uframe)
-+{
-+ __hc32 *hw_p = &fotg210->periodic[frame];
-+ union fotg210_shadow *q = &fotg210->pshadow[frame];
-+ unsigned usecs = 0;
-+ struct fotg210_qh_hw *hw;
-+
-+ while (q->ptr) {
-+ switch (hc32_to_cpu(fotg210, Q_NEXT_TYPE(fotg210, *hw_p))) {
-+ case Q_TYPE_QH:
-+ hw = q->qh->hw;
-+ /* is it in the S-mask? */
-+ if (hw->hw_info2 & cpu_to_hc32(fotg210, 1 << uframe))
-+ usecs += q->qh->usecs;
-+ /* ... or C-mask? */
-+ if (hw->hw_info2 & cpu_to_hc32(fotg210,
-+ 1 << (8 + uframe)))
-+ usecs += q->qh->c_usecs;
-+ hw_p = &hw->hw_next;
-+ q = &q->qh->qh_next;
-+ break;
-+ /* case Q_TYPE_FSTN: */
-+ default:
-+ /* for "save place" FSTNs, count the relevant INTR
-+ * bandwidth from the previous frame
-+ */
-+ if (q->fstn->hw_prev != FOTG210_LIST_END(fotg210))
-+ fotg210_dbg(fotg210, "ignoring FSTN cost ...\n");
-+
-+ hw_p = &q->fstn->hw_next;
-+ q = &q->fstn->fstn_next;
-+ break;
-+ case Q_TYPE_ITD:
-+ if (q->itd->hw_transaction[uframe])
-+ usecs += q->itd->stream->usecs;
-+ hw_p = &q->itd->hw_next;
-+ q = &q->itd->itd_next;
-+ break;
-+ }
-+ }
-+ if (usecs > fotg210->uframe_periodic_max)
-+ fotg210_err(fotg210, "uframe %d sched overrun: %d usecs\n",
-+ frame * 8 + uframe, usecs);
-+ return usecs;
-+}
-+
-+static int same_tt(struct usb_device *dev1, struct usb_device *dev2)
-+{
-+ if (!dev1->tt || !dev2->tt)
-+ return 0;
-+ if (dev1->tt != dev2->tt)
-+ return 0;
-+ if (dev1->tt->multi)
-+ return dev1->ttport == dev2->ttport;
-+ else
-+ return 1;
-+}
-+
-+/* return true iff the device's transaction translator is available
-+ * for a periodic transfer starting at the specified frame, using
-+ * all the uframes in the mask.
-+ */
-+static int tt_no_collision(struct fotg210_hcd *fotg210, unsigned period,
-+ struct usb_device *dev, unsigned frame, u32 uf_mask)
-+{
-+ if (period == 0) /* error */
-+ return 0;
-+
-+ /* note bandwidth wastage: split never follows csplit
-+ * (different dev or endpoint) until the next uframe.
-+ * calling convention doesn't make that distinction.
-+ */
-+ for (; frame < fotg210->periodic_size; frame += period) {
-+ union fotg210_shadow here;
-+ __hc32 type;
-+ struct fotg210_qh_hw *hw;
-+
-+ here = fotg210->pshadow[frame];
-+ type = Q_NEXT_TYPE(fotg210, fotg210->periodic[frame]);
-+ while (here.ptr) {
-+ switch (hc32_to_cpu(fotg210, type)) {
-+ case Q_TYPE_ITD:
-+ type = Q_NEXT_TYPE(fotg210, here.itd->hw_next);
-+ here = here.itd->itd_next;
-+ continue;
-+ case Q_TYPE_QH:
-+ hw = here.qh->hw;
-+ if (same_tt(dev, here.qh->dev)) {
-+ u32 mask;
-+
-+ mask = hc32_to_cpu(fotg210,
-+ hw->hw_info2);
-+ /* "knows" no gap is needed */
-+ mask |= mask >> 8;
-+ if (mask & uf_mask)
-+ break;
-+ }
-+ type = Q_NEXT_TYPE(fotg210, hw->hw_next);
-+ here = here.qh->qh_next;
-+ continue;
-+ /* case Q_TYPE_FSTN: */
-+ default:
-+ fotg210_dbg(fotg210,
-+ "periodic frame %d bogus type %d\n",
-+ frame, type);
-+ }
-+
-+ /* collision or error */
-+ return 0;
-+ }
-+ }
-+
-+ /* no collision */
-+ return 1;
-+}
-+
-+static void enable_periodic(struct fotg210_hcd *fotg210)
-+{
-+ if (fotg210->periodic_count++)
-+ return;
-+
-+ /* Stop waiting to turn off the periodic schedule */
-+ fotg210->enabled_hrtimer_events &=
-+ ~BIT(FOTG210_HRTIMER_DISABLE_PERIODIC);
-+
-+ /* Don't start the schedule until PSS is 0 */
-+ fotg210_poll_PSS(fotg210);
-+ turn_on_io_watchdog(fotg210);
-+}
-+
-+static void disable_periodic(struct fotg210_hcd *fotg210)
-+{
-+ if (--fotg210->periodic_count)
-+ return;
-+
-+ /* Don't turn off the schedule until PSS is 1 */
-+ fotg210_poll_PSS(fotg210);
-+}
-+
-+/* periodic schedule slots have iso tds (normal or split) first, then a
-+ * sparse tree for active interrupt transfers.
-+ *
-+ * this just links in a qh; caller guarantees uframe masks are set right.
-+ * no FSTN support (yet; fotg210 0.96+)
-+ */
-+static void qh_link_periodic(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+ unsigned i;
-+ unsigned period = qh->period;
-+
-+ dev_dbg(&qh->dev->dev,
-+ "link qh%d-%04x/%p start %d [%d/%d us]\n", period,
-+ hc32_to_cpup(fotg210, &qh->hw->hw_info2) &
-+ (QH_CMASK | QH_SMASK), qh, qh->start, qh->usecs,
-+ qh->c_usecs);
-+
-+ /* high bandwidth, or otherwise every microframe */
-+ if (period == 0)
-+ period = 1;
-+
-+ for (i = qh->start; i < fotg210->periodic_size; i += period) {
-+ union fotg210_shadow *prev = &fotg210->pshadow[i];
-+ __hc32 *hw_p = &fotg210->periodic[i];
-+ union fotg210_shadow here = *prev;
-+ __hc32 type = 0;
-+
-+ /* skip the iso nodes at list head */
-+ while (here.ptr) {
-+ type = Q_NEXT_TYPE(fotg210, *hw_p);
-+ if (type == cpu_to_hc32(fotg210, Q_TYPE_QH))
-+ break;
-+ prev = periodic_next_shadow(fotg210, prev, type);
-+ hw_p = shadow_next_periodic(fotg210, &here, type);
-+ here = *prev;
-+ }
-+
-+ /* sorting each branch by period (slow-->fast)
-+ * enables sharing interior tree nodes
-+ */
-+ while (here.ptr && qh != here.qh) {
-+ if (qh->period > here.qh->period)
-+ break;
-+ prev = &here.qh->qh_next;
-+ hw_p = &here.qh->hw->hw_next;
-+ here = *prev;
-+ }
-+ /* link in this qh, unless some earlier pass did that */
-+ if (qh != here.qh) {
-+ qh->qh_next = here;
-+ if (here.qh)
-+ qh->hw->hw_next = *hw_p;
-+ wmb();
-+ prev->qh = qh;
-+ *hw_p = QH_NEXT(fotg210, qh->qh_dma);
-+ }
-+ }
-+ qh->qh_state = QH_STATE_LINKED;
-+ qh->xacterrs = 0;
-+
-+ /* update per-qh bandwidth for usbfs */
-+ fotg210_to_hcd(fotg210)->self.bandwidth_allocated += qh->period
-+ ? ((qh->usecs + qh->c_usecs) / qh->period)
-+ : (qh->usecs * 8);
-+
-+ list_add(&qh->intr_node, &fotg210->intr_qh_list);
-+
-+ /* maybe enable periodic schedule processing */
-+ ++fotg210->intr_count;
-+ enable_periodic(fotg210);
-+}
-+
-+static void qh_unlink_periodic(struct fotg210_hcd *fotg210,
-+ struct fotg210_qh *qh)
-+{
-+ unsigned i;
-+ unsigned period;
-+
-+ /*
-+ * If qh is for a low/full-speed device, simply unlinking it
-+ * could interfere with an ongoing split transaction. To unlink
-+ * it safely would require setting the QH_INACTIVATE bit and
-+ * waiting at least one frame, as described in EHCI 4.12.2.5.
-+ *
-+ * We won't bother with any of this. Instead, we assume that the
-+ * only reason for unlinking an interrupt QH while the current URB
-+ * is still active is to dequeue all the URBs (flush the whole
-+ * endpoint queue).
-+ *
-+ * If rebalancing the periodic schedule is ever implemented, this
-+ * approach will no longer be valid.
-+ */
-+
-+ /* high bandwidth, or otherwise part of every microframe */
-+ period = qh->period;
-+ if (!period)
-+ period = 1;
-+
-+ for (i = qh->start; i < fotg210->periodic_size; i += period)
-+ periodic_unlink(fotg210, i, qh);
-+
-+ /* update per-qh bandwidth for usbfs */
-+ fotg210_to_hcd(fotg210)->self.bandwidth_allocated -= qh->period
-+ ? ((qh->usecs + qh->c_usecs) / qh->period)
-+ : (qh->usecs * 8);
-+
-+ dev_dbg(&qh->dev->dev,
-+ "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
-+ qh->period, hc32_to_cpup(fotg210, &qh->hw->hw_info2) &
-+ (QH_CMASK | QH_SMASK), qh, qh->start, qh->usecs,
-+ qh->c_usecs);
-+
-+ /* qh->qh_next still "live" to HC */
-+ qh->qh_state = QH_STATE_UNLINK;
-+ qh->qh_next.ptr = NULL;
-+
-+ if (fotg210->qh_scan_next == qh)
-+ fotg210->qh_scan_next = list_entry(qh->intr_node.next,
-+ struct fotg210_qh, intr_node);
-+ list_del(&qh->intr_node);
-+}
-+
-+static void start_unlink_intr(struct fotg210_hcd *fotg210,
-+ struct fotg210_qh *qh)
-+{
-+ /* If the QH isn't linked then there's nothing we can do
-+ * unless we were called during a giveback, in which case
-+ * qh_completions() has to deal with it.
-+ */
-+ if (qh->qh_state != QH_STATE_LINKED) {
-+ if (qh->qh_state == QH_STATE_COMPLETING)
-+ qh->needs_rescan = 1;
-+ return;
-+ }
-+
-+ qh_unlink_periodic(fotg210, qh);
-+
-+ /* Make sure the unlinks are visible before starting the timer */
-+ wmb();
-+
-+ /*
-+ * The EHCI spec doesn't say how long it takes the controller to
-+ * stop accessing an unlinked interrupt QH. The timer delay is
-+ * 9 uframes; presumably that will be long enough.
-+ */
-+ qh->unlink_cycle = fotg210->intr_unlink_cycle;
-+
-+ /* New entries go at the end of the intr_unlink list */
-+ if (fotg210->intr_unlink)
-+ fotg210->intr_unlink_last->unlink_next = qh;
-+ else
-+ fotg210->intr_unlink = qh;
-+ fotg210->intr_unlink_last = qh;
-+
-+ if (fotg210->intr_unlinking)
-+ ; /* Avoid recursive calls */
-+ else if (fotg210->rh_state < FOTG210_RH_RUNNING)
-+ fotg210_handle_intr_unlinks(fotg210);
-+ else if (fotg210->intr_unlink == qh) {
-+ fotg210_enable_event(fotg210, FOTG210_HRTIMER_UNLINK_INTR,
-+ true);
-+ ++fotg210->intr_unlink_cycle;
-+ }
-+}
-+
-+static void end_unlink_intr(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+ struct fotg210_qh_hw *hw = qh->hw;
-+ int rc;
-+
-+ qh->qh_state = QH_STATE_IDLE;
-+ hw->hw_next = FOTG210_LIST_END(fotg210);
-+
-+ qh_completions(fotg210, qh);
-+
-+ /* reschedule QH iff another request is queued */
-+ if (!list_empty(&qh->qtd_list) &&
-+ fotg210->rh_state == FOTG210_RH_RUNNING) {
-+ rc = qh_schedule(fotg210, qh);
-+
-+ /* An error here likely indicates handshake failure
-+ * or no space left in the schedule. Neither fault
-+ * should happen often ...
-+ *
-+ * FIXME kill the now-dysfunctional queued urbs
-+ */
-+ if (rc != 0)
-+ fotg210_err(fotg210, "can't reschedule qh %p, err %d\n",
-+ qh, rc);
-+ }
-+
-+ /* maybe turn off periodic schedule */
-+ --fotg210->intr_count;
-+ disable_periodic(fotg210);
-+}
-+
-+static int check_period(struct fotg210_hcd *fotg210, unsigned frame,
-+ unsigned uframe, unsigned period, unsigned usecs)
-+{
-+ int claimed;
-+
-+ /* complete split running into next frame?
-+ * given FSTN support, we could sometimes check...
-+ */
-+ if (uframe >= 8)
-+ return 0;
-+
-+ /* convert "usecs we need" to "max already claimed" */
-+ usecs = fotg210->uframe_periodic_max - usecs;
-+
-+ /* we "know" 2 and 4 uframe intervals were rejected; so
-+ * for period 0, check _every_ microframe in the schedule.
-+ */
-+ if (unlikely(period == 0)) {
-+ do {
-+ for (uframe = 0; uframe < 7; uframe++) {
-+ claimed = periodic_usecs(fotg210, frame,
-+ uframe);
-+ if (claimed > usecs)
-+ return 0;
-+ }
-+ } while ((frame += 1) < fotg210->periodic_size);
-+
-+ /* just check the specified uframe, at that period */
-+ } else {
-+ do {
-+ claimed = periodic_usecs(fotg210, frame, uframe);
-+ if (claimed > usecs)
-+ return 0;
-+ } while ((frame += period) < fotg210->periodic_size);
-+ }
-+
-+ /* success! */
-+ return 1;
-+}
-+
-+static int check_intr_schedule(struct fotg210_hcd *fotg210, unsigned frame,
-+ unsigned uframe, const struct fotg210_qh *qh, __hc32 *c_maskp)
-+{
-+ int retval = -ENOSPC;
-+ u8 mask = 0;
-+
-+ if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
-+ goto done;
-+
-+ if (!check_period(fotg210, frame, uframe, qh->period, qh->usecs))
-+ goto done;
-+ if (!qh->c_usecs) {
-+ retval = 0;
-+ *c_maskp = 0;
-+ goto done;
-+ }
-+
-+ /* Make sure this tt's buffer is also available for CSPLITs.
-+ * We pessimize a bit; probably the typical full speed case
-+ * doesn't need the second CSPLIT.
-+ *
-+ * NOTE: both SPLIT and CSPLIT could be checked in just
-+ * one smart pass...
-+ */
-+ mask = 0x03 << (uframe + qh->gap_uf);
-+ *c_maskp = cpu_to_hc32(fotg210, mask << 8);
-+
-+ mask |= 1 << uframe;
-+ if (tt_no_collision(fotg210, qh->period, qh->dev, frame, mask)) {
-+ if (!check_period(fotg210, frame, uframe + qh->gap_uf + 1,
-+ qh->period, qh->c_usecs))
-+ goto done;
-+ if (!check_period(fotg210, frame, uframe + qh->gap_uf,
-+ qh->period, qh->c_usecs))
-+ goto done;
-+ retval = 0;
-+ }
-+done:
-+ return retval;
-+}
-+
-+/* "first fit" scheduling policy used the first time through,
-+ * or when the previous schedule slot can't be re-used.
-+ */
-+static int qh_schedule(struct fotg210_hcd *fotg210, struct fotg210_qh *qh)
-+{
-+ int status;
-+ unsigned uframe;
-+ __hc32 c_mask;
-+ unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
-+ struct fotg210_qh_hw *hw = qh->hw;
-+
-+ qh_refresh(fotg210, qh);
-+ hw->hw_next = FOTG210_LIST_END(fotg210);
-+ frame = qh->start;
-+
-+ /* reuse the previous schedule slots, if we can */
-+ if (frame < qh->period) {
-+ uframe = ffs(hc32_to_cpup(fotg210, &hw->hw_info2) & QH_SMASK);
-+ status = check_intr_schedule(fotg210, frame, --uframe,
-+ qh, &c_mask);
-+ } else {
-+ uframe = 0;
-+ c_mask = 0;
-+ status = -ENOSPC;
-+ }
-+
-+ /* else scan the schedule to find a group of slots such that all
-+ * uframes have enough periodic bandwidth available.
-+ */
-+ if (status) {
-+ /* "normal" case, uframing flexible except with splits */
-+ if (qh->period) {
-+ int i;
-+
-+ for (i = qh->period; status && i > 0; --i) {
-+ frame = ++fotg210->random_frame % qh->period;
-+ for (uframe = 0; uframe < 8; uframe++) {
-+ status = check_intr_schedule(fotg210,
-+ frame, uframe, qh,
-+ &c_mask);
-+ if (status == 0)
-+ break;
-+ }
-+ }
-+
-+ /* qh->period == 0 means every uframe */
-+ } else {
-+ frame = 0;
-+ status = check_intr_schedule(fotg210, 0, 0, qh,
-+ &c_mask);
-+ }
-+ if (status)
-+ goto done;
-+ qh->start = frame;
-+
-+ /* reset S-frame and (maybe) C-frame masks */
-+ hw->hw_info2 &= cpu_to_hc32(fotg210, ~(QH_CMASK | QH_SMASK));
-+ hw->hw_info2 |= qh->period
-+ ? cpu_to_hc32(fotg210, 1 << uframe)
-+ : cpu_to_hc32(fotg210, QH_SMASK);
-+ hw->hw_info2 |= c_mask;
-+ } else
-+ fotg210_dbg(fotg210, "reused qh %p schedule\n", qh);
-+
-+ /* stuff into the periodic schedule */
-+ qh_link_periodic(fotg210, qh);
-+done:
-+ return status;
-+}
-+
-+static int intr_submit(struct fotg210_hcd *fotg210, struct urb *urb,
-+ struct list_head *qtd_list, gfp_t mem_flags)
-+{
-+ unsigned epnum;
-+ unsigned long flags;
-+ struct fotg210_qh *qh;
-+ int status;
-+ struct list_head empty;
-+
-+ /* get endpoint and transfer/schedule data */
-+ epnum = urb->ep->desc.bEndpointAddress;
-+
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+
-+ if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
-+ status = -ESHUTDOWN;
-+ goto done_not_linked;
-+ }
-+ status = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
-+ if (unlikely(status))
-+ goto done_not_linked;
-+
-+ /* get qh and force any scheduling errors */
-+ INIT_LIST_HEAD(&empty);
-+ qh = qh_append_tds(fotg210, urb, &empty, epnum, &urb->ep->hcpriv);
-+ if (qh == NULL) {
-+ status = -ENOMEM;
-+ goto done;
-+ }
-+ if (qh->qh_state == QH_STATE_IDLE) {
-+ status = qh_schedule(fotg210, qh);
-+ if (status)
-+ goto done;
-+ }
-+
-+ /* then queue the urb's tds to the qh */
-+ qh = qh_append_tds(fotg210, urb, qtd_list, epnum, &urb->ep->hcpriv);
-+ BUG_ON(qh == NULL);
-+
-+ /* ... update usbfs periodic stats */
-+ fotg210_to_hcd(fotg210)->self.bandwidth_int_reqs++;
-+
-+done:
-+ if (unlikely(status))
-+ usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
-+done_not_linked:
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ if (status)
-+ qtd_list_free(fotg210, urb, qtd_list);
-+
-+ return status;
-+}
-+
-+static void scan_intr(struct fotg210_hcd *fotg210)
-+{
-+ struct fotg210_qh *qh;
-+
-+ list_for_each_entry_safe(qh, fotg210->qh_scan_next,
-+ &fotg210->intr_qh_list, intr_node) {
-+rescan:
-+ /* clean any finished work for this qh */
-+ if (!list_empty(&qh->qtd_list)) {
-+ int temp;
-+
-+ /*
-+ * Unlinks could happen here; completion reporting
-+ * drops the lock. That's why fotg210->qh_scan_next
-+ * always holds the next qh to scan; if the next qh
-+ * gets unlinked then fotg210->qh_scan_next is adjusted
-+ * in qh_unlink_periodic().
-+ */
-+ temp = qh_completions(fotg210, qh);
-+ if (unlikely(qh->needs_rescan ||
-+ (list_empty(&qh->qtd_list) &&
-+ qh->qh_state == QH_STATE_LINKED)))
-+ start_unlink_intr(fotg210, qh);
-+ else if (temp != 0)
-+ goto rescan;
-+ }
-+ }
-+}
-+
-+/* fotg210_iso_stream ops work with both ITD and SITD */
-+
-+static struct fotg210_iso_stream *iso_stream_alloc(gfp_t mem_flags)
-+{
-+ struct fotg210_iso_stream *stream;
-+
-+ stream = kzalloc(sizeof(*stream), mem_flags);
-+ if (likely(stream != NULL)) {
-+ INIT_LIST_HEAD(&stream->td_list);
-+ INIT_LIST_HEAD(&stream->free_list);
-+ stream->next_uframe = -1;
-+ }
-+ return stream;
-+}
-+
-+static void iso_stream_init(struct fotg210_hcd *fotg210,
-+ struct fotg210_iso_stream *stream, struct usb_device *dev,
-+ int pipe, unsigned interval)
-+{
-+ u32 buf1;
-+ unsigned epnum, maxp;
-+ int is_input;
-+ long bandwidth;
-+ unsigned multi;
-+ struct usb_host_endpoint *ep;
-+
-+ /*
-+ * this might be a "high bandwidth" highspeed endpoint,
-+ * as encoded in the ep descriptor's wMaxPacket field
-+ */
-+ epnum = usb_pipeendpoint(pipe);
-+ is_input = usb_pipein(pipe) ? USB_DIR_IN : 0;
-+ ep = usb_pipe_endpoint(dev, pipe);
-+ maxp = usb_endpoint_maxp(&ep->desc);
-+ if (is_input)
-+ buf1 = (1 << 11);
-+ else
-+ buf1 = 0;
-+
-+ multi = usb_endpoint_maxp_mult(&ep->desc);
-+ buf1 |= maxp;
-+ maxp *= multi;
-+
-+ stream->buf0 = cpu_to_hc32(fotg210, (epnum << 8) | dev->devnum);
-+ stream->buf1 = cpu_to_hc32(fotg210, buf1);
-+ stream->buf2 = cpu_to_hc32(fotg210, multi);
-+
-+ /* usbfs wants to report the average usecs per frame tied up
-+ * when transfers on this endpoint are scheduled ...
-+ */
-+ if (dev->speed == USB_SPEED_FULL) {
-+ interval <<= 3;
-+ stream->usecs = NS_TO_US(usb_calc_bus_time(dev->speed,
-+ is_input, 1, maxp));
-+ stream->usecs /= 8;
-+ } else {
-+ stream->highspeed = 1;
-+ stream->usecs = HS_USECS_ISO(maxp);
-+ }
-+ bandwidth = stream->usecs * 8;
-+ bandwidth /= interval;
-+
-+ stream->bandwidth = bandwidth;
-+ stream->udev = dev;
-+ stream->bEndpointAddress = is_input | epnum;
-+ stream->interval = interval;
-+ stream->maxp = maxp;
-+}
-+
-+static struct fotg210_iso_stream *iso_stream_find(struct fotg210_hcd *fotg210,
-+ struct urb *urb)
-+{
-+ unsigned epnum;
-+ struct fotg210_iso_stream *stream;
-+ struct usb_host_endpoint *ep;
-+ unsigned long flags;
-+
-+ epnum = usb_pipeendpoint(urb->pipe);
-+ if (usb_pipein(urb->pipe))
-+ ep = urb->dev->ep_in[epnum];
-+ else
-+ ep = urb->dev->ep_out[epnum];
-+
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ stream = ep->hcpriv;
-+
-+ if (unlikely(stream == NULL)) {
-+ stream = iso_stream_alloc(GFP_ATOMIC);
-+ if (likely(stream != NULL)) {
-+ ep->hcpriv = stream;
-+ stream->ep = ep;
-+ iso_stream_init(fotg210, stream, urb->dev, urb->pipe,
-+ urb->interval);
-+ }
-+
-+ /* if dev->ep[epnum] is a QH, hw is set */
-+ } else if (unlikely(stream->hw != NULL)) {
-+ fotg210_dbg(fotg210, "dev %s ep%d%s, not iso??\n",
-+ urb->dev->devpath, epnum,
-+ usb_pipein(urb->pipe) ? "in" : "out");
-+ stream = NULL;
-+ }
-+
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ return stream;
-+}
-+
-+/* fotg210_iso_sched ops can be ITD-only or SITD-only */
-+
-+static struct fotg210_iso_sched *iso_sched_alloc(unsigned packets,
-+ gfp_t mem_flags)
-+{
-+ struct fotg210_iso_sched *iso_sched;
-+
-+ iso_sched = kzalloc(struct_size(iso_sched, packet, packets), mem_flags);
-+ if (likely(iso_sched != NULL))
-+ INIT_LIST_HEAD(&iso_sched->td_list);
-+
-+ return iso_sched;
-+}
-+
-+static inline void itd_sched_init(struct fotg210_hcd *fotg210,
-+ struct fotg210_iso_sched *iso_sched,
-+ struct fotg210_iso_stream *stream, struct urb *urb)
-+{
-+ unsigned i;
-+ dma_addr_t dma = urb->transfer_dma;
-+
-+ /* how many uframes are needed for these transfers */
-+ iso_sched->span = urb->number_of_packets * stream->interval;
-+
-+ /* figure out per-uframe itd fields that we'll need later
-+ * when we fit new itds into the schedule.
-+ */
-+ for (i = 0; i < urb->number_of_packets; i++) {
-+ struct fotg210_iso_packet *uframe = &iso_sched->packet[i];
-+ unsigned length;
-+ dma_addr_t buf;
-+ u32 trans;
-+
-+ length = urb->iso_frame_desc[i].length;
-+ buf = dma + urb->iso_frame_desc[i].offset;
-+
-+ trans = FOTG210_ISOC_ACTIVE;
-+ trans |= buf & 0x0fff;
-+ if (unlikely(((i + 1) == urb->number_of_packets))
-+ && !(urb->transfer_flags & URB_NO_INTERRUPT))
-+ trans |= FOTG210_ITD_IOC;
-+ trans |= length << 16;
-+ uframe->transaction = cpu_to_hc32(fotg210, trans);
-+
-+ /* might need to cross a buffer page within a uframe */
-+ uframe->bufp = (buf & ~(u64)0x0fff);
-+ buf += length;
-+ if (unlikely((uframe->bufp != (buf & ~(u64)0x0fff))))
-+ uframe->cross = 1;
-+ }
-+}
-+
-+static void iso_sched_free(struct fotg210_iso_stream *stream,
-+ struct fotg210_iso_sched *iso_sched)
-+{
-+ if (!iso_sched)
-+ return;
-+ /* caller must hold fotg210->lock!*/
-+ list_splice(&iso_sched->td_list, &stream->free_list);
-+ kfree(iso_sched);
-+}
-+
-+static int itd_urb_transaction(struct fotg210_iso_stream *stream,
-+ struct fotg210_hcd *fotg210, struct urb *urb, gfp_t mem_flags)
-+{
-+ struct fotg210_itd *itd;
-+ dma_addr_t itd_dma;
-+ int i;
-+ unsigned num_itds;
-+ struct fotg210_iso_sched *sched;
-+ unsigned long flags;
-+
-+ sched = iso_sched_alloc(urb->number_of_packets, mem_flags);
-+ if (unlikely(sched == NULL))
-+ return -ENOMEM;
-+
-+ itd_sched_init(fotg210, sched, stream, urb);
-+
-+ if (urb->interval < 8)
-+ num_itds = 1 + (sched->span + 7) / 8;
-+ else
-+ num_itds = urb->number_of_packets;
-+
-+ /* allocate/init ITDs */
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ for (i = 0; i < num_itds; i++) {
-+
-+ /*
-+ * Use iTDs from the free list, but not iTDs that may
-+ * still be in use by the hardware.
-+ */
-+ if (likely(!list_empty(&stream->free_list))) {
-+ itd = list_first_entry(&stream->free_list,
-+ struct fotg210_itd, itd_list);
-+ if (itd->frame == fotg210->now_frame)
-+ goto alloc_itd;
-+ list_del(&itd->itd_list);
-+ itd_dma = itd->itd_dma;
-+ } else {
-+alloc_itd:
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ itd = dma_pool_alloc(fotg210->itd_pool, mem_flags,
-+ &itd_dma);
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ if (!itd) {
-+ iso_sched_free(stream, sched);
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ return -ENOMEM;
-+ }
-+ }
-+
-+ memset(itd, 0, sizeof(*itd));
-+ itd->itd_dma = itd_dma;
-+ list_add(&itd->itd_list, &sched->td_list);
-+ }
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+
-+ /* temporarily store schedule info in hcpriv */
-+ urb->hcpriv = sched;
-+ urb->error_count = 0;
-+ return 0;
-+}
-+
-+static inline int itd_slot_ok(struct fotg210_hcd *fotg210, u32 mod, u32 uframe,
-+ u8 usecs, u32 period)
-+{
-+ uframe %= period;
-+ do {
-+ /* can't commit more than uframe_periodic_max usec */
-+ if (periodic_usecs(fotg210, uframe >> 3, uframe & 0x7)
-+ > (fotg210->uframe_periodic_max - usecs))
-+ return 0;
-+
-+ /* we know urb->interval is 2^N uframes */
-+ uframe += period;
-+ } while (uframe < mod);
-+ return 1;
-+}
-+
-+/* This scheduler plans almost as far into the future as it has actual
-+ * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
-+ * "as small as possible" to be cache-friendlier.) That limits the size
-+ * transfers you can stream reliably; avoid more than 64 msec per urb.
-+ * Also avoid queue depths of less than fotg210's worst irq latency (affected
-+ * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
-+ * and other factors); or more than about 230 msec total (for portability,
-+ * given FOTG210_TUNE_FLS and the slop). Or, write a smarter scheduler!
-+ */
-+
-+#define SCHEDULE_SLOP 80 /* microframes */
-+
-+static int iso_stream_schedule(struct fotg210_hcd *fotg210, struct urb *urb,
-+ struct fotg210_iso_stream *stream)
-+{
-+ u32 now, next, start, period, span;
-+ int status;
-+ unsigned mod = fotg210->periodic_size << 3;
-+ struct fotg210_iso_sched *sched = urb->hcpriv;
-+
-+ period = urb->interval;
-+ span = sched->span;
-+
-+ if (span > mod - SCHEDULE_SLOP) {
-+ fotg210_dbg(fotg210, "iso request %p too long\n", urb);
-+ status = -EFBIG;
-+ goto fail;
-+ }
-+
-+ now = fotg210_read_frame_index(fotg210) & (mod - 1);
-+
-+ /* Typical case: reuse current schedule, stream is still active.
-+ * Hopefully there are no gaps from the host falling behind
-+ * (irq delays etc), but if there are we'll take the next
-+ * slot in the schedule, implicitly assuming URB_ISO_ASAP.
-+ */
-+ if (likely(!list_empty(&stream->td_list))) {
-+ u32 excess;
-+
-+ /* For high speed devices, allow scheduling within the
-+ * isochronous scheduling threshold. For full speed devices
-+ * and Intel PCI-based controllers, don't (work around for
-+ * Intel ICH9 bug).
-+ */
-+ if (!stream->highspeed && fotg210->fs_i_thresh)
-+ next = now + fotg210->i_thresh;
-+ else
-+ next = now;
-+
-+ /* Fell behind (by up to twice the slop amount)?
-+ * We decide based on the time of the last currently-scheduled
-+ * slot, not the time of the next available slot.
-+ */
-+ excess = (stream->next_uframe - period - next) & (mod - 1);
-+ if (excess >= mod - 2 * SCHEDULE_SLOP)
-+ start = next + excess - mod + period *
-+ DIV_ROUND_UP(mod - excess, period);
-+ else
-+ start = next + excess + period;
-+ if (start - now >= mod) {
-+ fotg210_dbg(fotg210, "request %p would overflow (%d+%d >= %d)\n",
-+ urb, start - now - period, period,
-+ mod);
-+ status = -EFBIG;
-+ goto fail;
-+ }
-+ }
-+
-+ /* need to schedule; when's the next (u)frame we could start?
-+ * this is bigger than fotg210->i_thresh allows; scheduling itself
-+ * isn't free, the slop should handle reasonably slow cpus. it
-+ * can also help high bandwidth if the dma and irq loads don't
-+ * jump until after the queue is primed.
-+ */
-+ else {
-+ int done = 0;
-+
-+ start = SCHEDULE_SLOP + (now & ~0x07);
-+
-+ /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
-+
-+ /* find a uframe slot with enough bandwidth.
-+ * Early uframes are more precious because full-speed
-+ * iso IN transfers can't use late uframes,
-+ * and therefore they should be allocated last.
-+ */
-+ next = start;
-+ start += period;
-+ do {
-+ start--;
-+ /* check schedule: enough space? */
-+ if (itd_slot_ok(fotg210, mod, start,
-+ stream->usecs, period))
-+ done = 1;
-+ } while (start > next && !done);
-+
-+ /* no room in the schedule */
-+ if (!done) {
-+ fotg210_dbg(fotg210, "iso resched full %p (now %d max %d)\n",
-+ urb, now, now + mod);
-+ status = -ENOSPC;
-+ goto fail;
-+ }
-+ }
-+
-+ /* Tried to schedule too far into the future? */
-+ if (unlikely(start - now + span - period >=
-+ mod - 2 * SCHEDULE_SLOP)) {
-+ fotg210_dbg(fotg210, "request %p would overflow (%d+%d >= %d)\n",
-+ urb, start - now, span - period,
-+ mod - 2 * SCHEDULE_SLOP);
-+ status = -EFBIG;
-+ goto fail;
-+ }
-+
-+ stream->next_uframe = start & (mod - 1);
-+
-+ /* report high speed start in uframes; full speed, in frames */
-+ urb->start_frame = stream->next_uframe;
-+ if (!stream->highspeed)
-+ urb->start_frame >>= 3;
-+
-+ /* Make sure scan_isoc() sees these */
-+ if (fotg210->isoc_count == 0)
-+ fotg210->next_frame = now >> 3;
-+ return 0;
-+
-+fail:
-+ iso_sched_free(stream, sched);
-+ urb->hcpriv = NULL;
-+ return status;
-+}
-+
-+static inline void itd_init(struct fotg210_hcd *fotg210,
-+ struct fotg210_iso_stream *stream, struct fotg210_itd *itd)
-+{
-+ int i;
-+
-+ /* it's been recently zeroed */
-+ itd->hw_next = FOTG210_LIST_END(fotg210);
-+ itd->hw_bufp[0] = stream->buf0;
-+ itd->hw_bufp[1] = stream->buf1;
-+ itd->hw_bufp[2] = stream->buf2;
-+
-+ for (i = 0; i < 8; i++)
-+ itd->index[i] = -1;
-+
-+ /* All other fields are filled when scheduling */
-+}
-+
-+static inline void itd_patch(struct fotg210_hcd *fotg210,
-+ struct fotg210_itd *itd, struct fotg210_iso_sched *iso_sched,
-+ unsigned index, u16 uframe)
-+{
-+ struct fotg210_iso_packet *uf = &iso_sched->packet[index];
-+ unsigned pg = itd->pg;
-+
-+ uframe &= 0x07;
-+ itd->index[uframe] = index;
-+
-+ itd->hw_transaction[uframe] = uf->transaction;
-+ itd->hw_transaction[uframe] |= cpu_to_hc32(fotg210, pg << 12);
-+ itd->hw_bufp[pg] |= cpu_to_hc32(fotg210, uf->bufp & ~(u32)0);
-+ itd->hw_bufp_hi[pg] |= cpu_to_hc32(fotg210, (u32)(uf->bufp >> 32));
-+
-+ /* iso_frame_desc[].offset must be strictly increasing */
-+ if (unlikely(uf->cross)) {
-+ u64 bufp = uf->bufp + 4096;
-+
-+ itd->pg = ++pg;
-+ itd->hw_bufp[pg] |= cpu_to_hc32(fotg210, bufp & ~(u32)0);
-+ itd->hw_bufp_hi[pg] |= cpu_to_hc32(fotg210, (u32)(bufp >> 32));
-+ }
-+}
-+
-+static inline void itd_link(struct fotg210_hcd *fotg210, unsigned frame,
-+ struct fotg210_itd *itd)
-+{
-+ union fotg210_shadow *prev = &fotg210->pshadow[frame];
-+ __hc32 *hw_p = &fotg210->periodic[frame];
-+ union fotg210_shadow here = *prev;
-+ __hc32 type = 0;
-+
-+ /* skip any iso nodes which might belong to previous microframes */
-+ while (here.ptr) {
-+ type = Q_NEXT_TYPE(fotg210, *hw_p);
-+ if (type == cpu_to_hc32(fotg210, Q_TYPE_QH))
-+ break;
-+ prev = periodic_next_shadow(fotg210, prev, type);
-+ hw_p = shadow_next_periodic(fotg210, &here, type);
-+ here = *prev;
-+ }
-+
-+ itd->itd_next = here;
-+ itd->hw_next = *hw_p;
-+ prev->itd = itd;
-+ itd->frame = frame;
-+ wmb();
-+ *hw_p = cpu_to_hc32(fotg210, itd->itd_dma | Q_TYPE_ITD);
-+}
-+
-+/* fit urb's itds into the selected schedule slot; activate as needed */
-+static void itd_link_urb(struct fotg210_hcd *fotg210, struct urb *urb,
-+ unsigned mod, struct fotg210_iso_stream *stream)
-+{
-+ int packet;
-+ unsigned next_uframe, uframe, frame;
-+ struct fotg210_iso_sched *iso_sched = urb->hcpriv;
-+ struct fotg210_itd *itd;
-+
-+ next_uframe = stream->next_uframe & (mod - 1);
-+
-+ if (unlikely(list_empty(&stream->td_list))) {
-+ fotg210_to_hcd(fotg210)->self.bandwidth_allocated
-+ += stream->bandwidth;
-+ fotg210_dbg(fotg210,
-+ "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
-+ urb->dev->devpath, stream->bEndpointAddress & 0x0f,
-+ (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
-+ urb->interval,
-+ next_uframe >> 3, next_uframe & 0x7);
-+ }
-+
-+ /* fill iTDs uframe by uframe */
-+ for (packet = 0, itd = NULL; packet < urb->number_of_packets;) {
-+ if (itd == NULL) {
-+ /* ASSERT: we have all necessary itds */
-+
-+ /* ASSERT: no itds for this endpoint in this uframe */
-+
-+ itd = list_entry(iso_sched->td_list.next,
-+ struct fotg210_itd, itd_list);
-+ list_move_tail(&itd->itd_list, &stream->td_list);
-+ itd->stream = stream;
-+ itd->urb = urb;
-+ itd_init(fotg210, stream, itd);
-+ }
-+
-+ uframe = next_uframe & 0x07;
-+ frame = next_uframe >> 3;
-+
-+ itd_patch(fotg210, itd, iso_sched, packet, uframe);
-+
-+ next_uframe += stream->interval;
-+ next_uframe &= mod - 1;
-+ packet++;
-+
-+ /* link completed itds into the schedule */
-+ if (((next_uframe >> 3) != frame)
-+ || packet == urb->number_of_packets) {
-+ itd_link(fotg210, frame & (fotg210->periodic_size - 1),
-+ itd);
-+ itd = NULL;
-+ }
-+ }
-+ stream->next_uframe = next_uframe;
-+
-+ /* don't need that schedule data any more */
-+ iso_sched_free(stream, iso_sched);
-+ urb->hcpriv = NULL;
-+
-+ ++fotg210->isoc_count;
-+ enable_periodic(fotg210);
-+}
-+
-+#define ISO_ERRS (FOTG210_ISOC_BUF_ERR | FOTG210_ISOC_BABBLE |\
-+ FOTG210_ISOC_XACTERR)
-+
-+/* Process and recycle a completed ITD. Return true iff its urb completed,
-+ * and hence its completion callback probably added things to the hardware
-+ * schedule.
-+ *
-+ * Note that we carefully avoid recycling this descriptor until after any
-+ * completion callback runs, so that it won't be reused quickly. That is,
-+ * assuming (a) no more than two urbs per frame on this endpoint, and also
-+ * (b) only this endpoint's completions submit URBs. It seems some silicon
-+ * corrupts things if you reuse completed descriptors very quickly...
-+ */
-+static bool itd_complete(struct fotg210_hcd *fotg210, struct fotg210_itd *itd)
-+{
-+ struct urb *urb = itd->urb;
-+ struct usb_iso_packet_descriptor *desc;
-+ u32 t;
-+ unsigned uframe;
-+ int urb_index = -1;
-+ struct fotg210_iso_stream *stream = itd->stream;
-+ struct usb_device *dev;
-+ bool retval = false;
-+
-+ /* for each uframe with a packet */
-+ for (uframe = 0; uframe < 8; uframe++) {
-+ if (likely(itd->index[uframe] == -1))
-+ continue;
-+ urb_index = itd->index[uframe];
-+ desc = &urb->iso_frame_desc[urb_index];
-+
-+ t = hc32_to_cpup(fotg210, &itd->hw_transaction[uframe]);
-+ itd->hw_transaction[uframe] = 0;
-+
-+ /* report transfer status */
-+ if (unlikely(t & ISO_ERRS)) {
-+ urb->error_count++;
-+ if (t & FOTG210_ISOC_BUF_ERR)
-+ desc->status = usb_pipein(urb->pipe)
-+ ? -ENOSR /* hc couldn't read */
-+ : -ECOMM; /* hc couldn't write */
-+ else if (t & FOTG210_ISOC_BABBLE)
-+ desc->status = -EOVERFLOW;
-+ else /* (t & FOTG210_ISOC_XACTERR) */
-+ desc->status = -EPROTO;
-+
-+ /* HC need not update length with this error */
-+ if (!(t & FOTG210_ISOC_BABBLE)) {
-+ desc->actual_length = FOTG210_ITD_LENGTH(t);
-+ urb->actual_length += desc->actual_length;
-+ }
-+ } else if (likely((t & FOTG210_ISOC_ACTIVE) == 0)) {
-+ desc->status = 0;
-+ desc->actual_length = FOTG210_ITD_LENGTH(t);
-+ urb->actual_length += desc->actual_length;
-+ } else {
-+ /* URB was too late */
-+ desc->status = -EXDEV;
-+ }
-+ }
-+
-+ /* handle completion now? */
-+ if (likely((urb_index + 1) != urb->number_of_packets))
-+ goto done;
-+
-+ /* ASSERT: it's really the last itd for this urb
-+ * list_for_each_entry (itd, &stream->td_list, itd_list)
-+ * BUG_ON (itd->urb == urb);
-+ */
-+
-+ /* give urb back to the driver; completion often (re)submits */
-+ dev = urb->dev;
-+ fotg210_urb_done(fotg210, urb, 0);
-+ retval = true;
-+ urb = NULL;
-+
-+ --fotg210->isoc_count;
-+ disable_periodic(fotg210);
-+
-+ if (unlikely(list_is_singular(&stream->td_list))) {
-+ fotg210_to_hcd(fotg210)->self.bandwidth_allocated
-+ -= stream->bandwidth;
-+ fotg210_dbg(fotg210,
-+ "deschedule devp %s ep%d%s-iso\n",
-+ dev->devpath, stream->bEndpointAddress & 0x0f,
-+ (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
-+ }
-+
-+done:
-+ itd->urb = NULL;
-+
-+ /* Add to the end of the free list for later reuse */
-+ list_move_tail(&itd->itd_list, &stream->free_list);
-+
-+ /* Recycle the iTDs when the pipeline is empty (ep no longer in use) */
-+ if (list_empty(&stream->td_list)) {
-+ list_splice_tail_init(&stream->free_list,
-+ &fotg210->cached_itd_list);
-+ start_free_itds(fotg210);
-+ }
-+
-+ return retval;
-+}
-+
-+static int itd_submit(struct fotg210_hcd *fotg210, struct urb *urb,
-+ gfp_t mem_flags)
-+{
-+ int status = -EINVAL;
-+ unsigned long flags;
-+ struct fotg210_iso_stream *stream;
-+
-+ /* Get iso_stream head */
-+ stream = iso_stream_find(fotg210, urb);
-+ if (unlikely(stream == NULL)) {
-+ fotg210_dbg(fotg210, "can't get iso stream\n");
-+ return -ENOMEM;
-+ }
-+ if (unlikely(urb->interval != stream->interval &&
-+ fotg210_port_speed(fotg210, 0) ==
-+ USB_PORT_STAT_HIGH_SPEED)) {
-+ fotg210_dbg(fotg210, "can't change iso interval %d --> %d\n",
-+ stream->interval, urb->interval);
-+ goto done;
-+ }
-+
-+#ifdef FOTG210_URB_TRACE
-+ fotg210_dbg(fotg210,
-+ "%s %s urb %p ep%d%s len %d, %d pkts %d uframes[%p]\n",
-+ __func__, urb->dev->devpath, urb,
-+ usb_pipeendpoint(urb->pipe),
-+ usb_pipein(urb->pipe) ? "in" : "out",
-+ urb->transfer_buffer_length,
-+ urb->number_of_packets, urb->interval,
-+ stream);
-+#endif
-+
-+ /* allocate ITDs w/o locking anything */
-+ status = itd_urb_transaction(stream, fotg210, urb, mem_flags);
-+ if (unlikely(status < 0)) {
-+ fotg210_dbg(fotg210, "can't init itds\n");
-+ goto done;
-+ }
-+
-+ /* schedule ... need to lock */
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ if (unlikely(!HCD_HW_ACCESSIBLE(fotg210_to_hcd(fotg210)))) {
-+ status = -ESHUTDOWN;
-+ goto done_not_linked;
-+ }
-+ status = usb_hcd_link_urb_to_ep(fotg210_to_hcd(fotg210), urb);
-+ if (unlikely(status))
-+ goto done_not_linked;
-+ status = iso_stream_schedule(fotg210, urb, stream);
-+ if (likely(status == 0))
-+ itd_link_urb(fotg210, urb, fotg210->periodic_size << 3, stream);
-+ else
-+ usb_hcd_unlink_urb_from_ep(fotg210_to_hcd(fotg210), urb);
-+done_not_linked:
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+done:
-+ return status;
-+}
-+
-+static inline int scan_frame_queue(struct fotg210_hcd *fotg210, unsigned frame,
-+ unsigned now_frame, bool live)
-+{
-+ unsigned uf;
-+ bool modified;
-+ union fotg210_shadow q, *q_p;
-+ __hc32 type, *hw_p;
-+
-+ /* scan each element in frame's queue for completions */
-+ q_p = &fotg210->pshadow[frame];
-+ hw_p = &fotg210->periodic[frame];
-+ q.ptr = q_p->ptr;
-+ type = Q_NEXT_TYPE(fotg210, *hw_p);
-+ modified = false;
-+
-+ while (q.ptr) {
-+ switch (hc32_to_cpu(fotg210, type)) {
-+ case Q_TYPE_ITD:
-+ /* If this ITD is still active, leave it for
-+ * later processing ... check the next entry.
-+ * No need to check for activity unless the
-+ * frame is current.
-+ */
-+ if (frame == now_frame && live) {
-+ rmb();
-+ for (uf = 0; uf < 8; uf++) {
-+ if (q.itd->hw_transaction[uf] &
-+ ITD_ACTIVE(fotg210))
-+ break;
-+ }
-+ if (uf < 8) {
-+ q_p = &q.itd->itd_next;
-+ hw_p = &q.itd->hw_next;
-+ type = Q_NEXT_TYPE(fotg210,
-+ q.itd->hw_next);
-+ q = *q_p;
-+ break;
-+ }
-+ }
-+
-+ /* Take finished ITDs out of the schedule
-+ * and process them: recycle, maybe report
-+ * URB completion. HC won't cache the
-+ * pointer for much longer, if at all.
-+ */
-+ *q_p = q.itd->itd_next;
-+ *hw_p = q.itd->hw_next;
-+ type = Q_NEXT_TYPE(fotg210, q.itd->hw_next);
-+ wmb();
-+ modified = itd_complete(fotg210, q.itd);
-+ q = *q_p;
-+ break;
-+ default:
-+ fotg210_dbg(fotg210, "corrupt type %d frame %d shadow %p\n",
-+ type, frame, q.ptr);
-+ fallthrough;
-+ case Q_TYPE_QH:
-+ case Q_TYPE_FSTN:
-+ /* End of the iTDs and siTDs */
-+ q.ptr = NULL;
-+ break;
-+ }
-+
-+ /* assume completion callbacks modify the queue */
-+ if (unlikely(modified && fotg210->isoc_count > 0))
-+ return -EINVAL;
-+ }
-+ return 0;
-+}
-+
-+static void scan_isoc(struct fotg210_hcd *fotg210)
-+{
-+ unsigned uf, now_frame, frame, ret;
-+ unsigned fmask = fotg210->periodic_size - 1;
-+ bool live;
-+
-+ /*
-+ * When running, scan from last scan point up to "now"
-+ * else clean up by scanning everything that's left.
-+ * Touches as few pages as possible: cache-friendly.
-+ */
-+ if (fotg210->rh_state >= FOTG210_RH_RUNNING) {
-+ uf = fotg210_read_frame_index(fotg210);
-+ now_frame = (uf >> 3) & fmask;
-+ live = true;
-+ } else {
-+ now_frame = (fotg210->next_frame - 1) & fmask;
-+ live = false;
-+ }
-+ fotg210->now_frame = now_frame;
-+
-+ frame = fotg210->next_frame;
-+ for (;;) {
-+ ret = 1;
-+ while (ret != 0)
-+ ret = scan_frame_queue(fotg210, frame,
-+ now_frame, live);
-+
-+ /* Stop when we have reached the current frame */
-+ if (frame == now_frame)
-+ break;
-+ frame = (frame + 1) & fmask;
-+ }
-+ fotg210->next_frame = now_frame;
-+}
-+
-+/* Display / Set uframe_periodic_max
-+ */
-+static ssize_t uframe_periodic_max_show(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct fotg210_hcd *fotg210;
-+ int n;
-+
-+ fotg210 = hcd_to_fotg210(bus_to_hcd(dev_get_drvdata(dev)));
-+ n = scnprintf(buf, PAGE_SIZE, "%d\n", fotg210->uframe_periodic_max);
-+ return n;
-+}
-+
-+
-+static ssize_t uframe_periodic_max_store(struct device *dev,
-+ struct device_attribute *attr, const char *buf, size_t count)
-+{
-+ struct fotg210_hcd *fotg210;
-+ unsigned uframe_periodic_max;
-+ unsigned frame, uframe;
-+ unsigned short allocated_max;
-+ unsigned long flags;
-+ ssize_t ret;
-+
-+ fotg210 = hcd_to_fotg210(bus_to_hcd(dev_get_drvdata(dev)));
-+ if (kstrtouint(buf, 0, &uframe_periodic_max) < 0)
-+ return -EINVAL;
-+
-+ if (uframe_periodic_max < 100 || uframe_periodic_max >= 125) {
-+ fotg210_info(fotg210, "rejecting invalid request for uframe_periodic_max=%u\n",
-+ uframe_periodic_max);
-+ return -EINVAL;
-+ }
-+
-+ ret = -EINVAL;
-+
-+ /*
-+ * lock, so that our checking does not race with possible periodic
-+ * bandwidth allocation through submitting new urbs.
-+ */
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+
-+ /*
-+ * for request to decrease max periodic bandwidth, we have to check
-+ * every microframe in the schedule to see whether the decrease is
-+ * possible.
-+ */
-+ if (uframe_periodic_max < fotg210->uframe_periodic_max) {
-+ allocated_max = 0;
-+
-+ for (frame = 0; frame < fotg210->periodic_size; ++frame)
-+ for (uframe = 0; uframe < 7; ++uframe)
-+ allocated_max = max(allocated_max,
-+ periodic_usecs(fotg210, frame,
-+ uframe));
-+
-+ if (allocated_max > uframe_periodic_max) {
-+ fotg210_info(fotg210,
-+ "cannot decrease uframe_periodic_max because periodic bandwidth is already allocated (%u > %u)\n",
-+ allocated_max, uframe_periodic_max);
-+ goto out_unlock;
-+ }
-+ }
-+
-+ /* increasing is always ok */
-+
-+ fotg210_info(fotg210,
-+ "setting max periodic bandwidth to %u%% (== %u usec/uframe)\n",
-+ 100 * uframe_periodic_max/125, uframe_periodic_max);
-+
-+ if (uframe_periodic_max != 100)
-+ fotg210_warn(fotg210, "max periodic bandwidth set is non-standard\n");
-+
-+ fotg210->uframe_periodic_max = uframe_periodic_max;
-+ ret = count;
-+
-+out_unlock:
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ return ret;
-+}
-+
-+static DEVICE_ATTR_RW(uframe_periodic_max);
-+
-+static inline int create_sysfs_files(struct fotg210_hcd *fotg210)
-+{
-+ struct device *controller = fotg210_to_hcd(fotg210)->self.controller;
-+
-+ return device_create_file(controller, &dev_attr_uframe_periodic_max);
-+}
-+
-+static inline void remove_sysfs_files(struct fotg210_hcd *fotg210)
-+{
-+ struct device *controller = fotg210_to_hcd(fotg210)->self.controller;
-+
-+ device_remove_file(controller, &dev_attr_uframe_periodic_max);
-+}
-+/* On some systems, leaving remote wakeup enabled prevents system shutdown.
-+ * The firmware seems to think that powering off is a wakeup event!
-+ * This routine turns off remote wakeup and everything else, on all ports.
-+ */
-+static void fotg210_turn_off_all_ports(struct fotg210_hcd *fotg210)
-+{
-+ u32 __iomem *status_reg = &fotg210->regs->port_status;
-+
-+ fotg210_writel(fotg210, PORT_RWC_BITS, status_reg);
-+}
-+
-+/* Halt HC, turn off all ports, and let the BIOS use the companion controllers.
-+ * Must be called with interrupts enabled and the lock not held.
-+ */
-+static void fotg210_silence_controller(struct fotg210_hcd *fotg210)
-+{
-+ fotg210_halt(fotg210);
-+
-+ spin_lock_irq(&fotg210->lock);
-+ fotg210->rh_state = FOTG210_RH_HALTED;
-+ fotg210_turn_off_all_ports(fotg210);
-+ spin_unlock_irq(&fotg210->lock);
-+}
-+
-+/* fotg210_shutdown kick in for silicon on any bus (not just pci, etc).
-+ * This forcibly disables dma and IRQs, helping kexec and other cases
-+ * where the next system software may expect clean state.
-+ */
-+static void fotg210_shutdown(struct usb_hcd *hcd)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+
-+ spin_lock_irq(&fotg210->lock);
-+ fotg210->shutdown = true;
-+ fotg210->rh_state = FOTG210_RH_STOPPING;
-+ fotg210->enabled_hrtimer_events = 0;
-+ spin_unlock_irq(&fotg210->lock);
-+
-+ fotg210_silence_controller(fotg210);
-+
-+ hrtimer_cancel(&fotg210->hrtimer);
-+}
-+
-+/* fotg210_work is called from some interrupts, timers, and so on.
-+ * it calls driver completion functions, after dropping fotg210->lock.
-+ */
-+static void fotg210_work(struct fotg210_hcd *fotg210)
-+{
-+ /* another CPU may drop fotg210->lock during a schedule scan while
-+ * it reports urb completions. this flag guards against bogus
-+ * attempts at re-entrant schedule scanning.
-+ */
-+ if (fotg210->scanning) {
-+ fotg210->need_rescan = true;
-+ return;
-+ }
-+ fotg210->scanning = true;
-+
-+rescan:
-+ fotg210->need_rescan = false;
-+ if (fotg210->async_count)
-+ scan_async(fotg210);
-+ if (fotg210->intr_count > 0)
-+ scan_intr(fotg210);
-+ if (fotg210->isoc_count > 0)
-+ scan_isoc(fotg210);
-+ if (fotg210->need_rescan)
-+ goto rescan;
-+ fotg210->scanning = false;
-+
-+ /* the IO watchdog guards against hardware or driver bugs that
-+ * misplace IRQs, and should let us run completely without IRQs.
-+ * such lossage has been observed on both VT6202 and VT8235.
-+ */
-+ turn_on_io_watchdog(fotg210);
-+}
-+
-+/* Called when the fotg210_hcd module is removed.
-+ */
-+static void fotg210_stop(struct usb_hcd *hcd)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+
-+ fotg210_dbg(fotg210, "stop\n");
-+
-+ /* no more interrupts ... */
-+
-+ spin_lock_irq(&fotg210->lock);
-+ fotg210->enabled_hrtimer_events = 0;
-+ spin_unlock_irq(&fotg210->lock);
-+
-+ fotg210_quiesce(fotg210);
-+ fotg210_silence_controller(fotg210);
-+ fotg210_reset(fotg210);
-+
-+ hrtimer_cancel(&fotg210->hrtimer);
-+ remove_sysfs_files(fotg210);
-+ remove_debug_files(fotg210);
-+
-+ /* root hub is shut down separately (first, when possible) */
-+ spin_lock_irq(&fotg210->lock);
-+ end_free_itds(fotg210);
-+ spin_unlock_irq(&fotg210->lock);
-+ fotg210_mem_cleanup(fotg210);
-+
-+#ifdef FOTG210_STATS
-+ fotg210_dbg(fotg210, "irq normal %ld err %ld iaa %ld (lost %ld)\n",
-+ fotg210->stats.normal, fotg210->stats.error,
-+ fotg210->stats.iaa, fotg210->stats.lost_iaa);
-+ fotg210_dbg(fotg210, "complete %ld unlink %ld\n",
-+ fotg210->stats.complete, fotg210->stats.unlink);
-+#endif
-+
-+ dbg_status(fotg210, "fotg210_stop completed",
-+ fotg210_readl(fotg210, &fotg210->regs->status));
-+}
-+
-+/* one-time init, only for memory state */
-+static int hcd_fotg210_init(struct usb_hcd *hcd)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+ u32 temp;
-+ int retval;
-+ u32 hcc_params;
-+ struct fotg210_qh_hw *hw;
-+
-+ spin_lock_init(&fotg210->lock);
-+
-+ /*
-+ * keep io watchdog by default, those good HCDs could turn off it later
-+ */
-+ fotg210->need_io_watchdog = 1;
-+
-+ hrtimer_init(&fotg210->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
-+ fotg210->hrtimer.function = fotg210_hrtimer_func;
-+ fotg210->next_hrtimer_event = FOTG210_HRTIMER_NO_EVENT;
-+
-+ hcc_params = fotg210_readl(fotg210, &fotg210->caps->hcc_params);
-+
-+ /*
-+ * by default set standard 80% (== 100 usec/uframe) max periodic
-+ * bandwidth as required by USB 2.0
-+ */
-+ fotg210->uframe_periodic_max = 100;
-+
-+ /*
-+ * hw default: 1K periodic list heads, one per frame.
-+ * periodic_size can shrink by USBCMD update if hcc_params allows.
-+ */
-+ fotg210->periodic_size = DEFAULT_I_TDPS;
-+ INIT_LIST_HEAD(&fotg210->intr_qh_list);
-+ INIT_LIST_HEAD(&fotg210->cached_itd_list);
-+
-+ if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
-+ /* periodic schedule size can be smaller than default */
-+ switch (FOTG210_TUNE_FLS) {
-+ case 0:
-+ fotg210->periodic_size = 1024;
-+ break;
-+ case 1:
-+ fotg210->periodic_size = 512;
-+ break;
-+ case 2:
-+ fotg210->periodic_size = 256;
-+ break;
-+ default:
-+ BUG();
-+ }
-+ }
-+ retval = fotg210_mem_init(fotg210, GFP_KERNEL);
-+ if (retval < 0)
-+ return retval;
-+
-+ /* controllers may cache some of the periodic schedule ... */
-+ fotg210->i_thresh = 2;
-+
-+ /*
-+ * dedicate a qh for the async ring head, since we couldn't unlink
-+ * a 'real' qh without stopping the async schedule [4.8]. use it
-+ * as the 'reclamation list head' too.
-+ * its dummy is used in hw_alt_next of many tds, to prevent the qh
-+ * from automatically advancing to the next td after short reads.
-+ */
-+ fotg210->async->qh_next.qh = NULL;
-+ hw = fotg210->async->hw;
-+ hw->hw_next = QH_NEXT(fotg210, fotg210->async->qh_dma);
-+ hw->hw_info1 = cpu_to_hc32(fotg210, QH_HEAD);
-+ hw->hw_token = cpu_to_hc32(fotg210, QTD_STS_HALT);
-+ hw->hw_qtd_next = FOTG210_LIST_END(fotg210);
-+ fotg210->async->qh_state = QH_STATE_LINKED;
-+ hw->hw_alt_next = QTD_NEXT(fotg210, fotg210->async->dummy->qtd_dma);
-+
-+ /* clear interrupt enables, set irq latency */
-+ if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
-+ log2_irq_thresh = 0;
-+ temp = 1 << (16 + log2_irq_thresh);
-+ if (HCC_CANPARK(hcc_params)) {
-+ /* HW default park == 3, on hardware that supports it (like
-+ * NVidia and ALI silicon), maximizes throughput on the async
-+ * schedule by avoiding QH fetches between transfers.
-+ *
-+ * With fast usb storage devices and NForce2, "park" seems to
-+ * make problems: throughput reduction (!), data errors...
-+ */
-+ if (park) {
-+ park = min_t(unsigned, park, 3);
-+ temp |= CMD_PARK;
-+ temp |= park << 8;
-+ }
-+ fotg210_dbg(fotg210, "park %d\n", park);
-+ }
-+ if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
-+ /* periodic schedule size can be smaller than default */
-+ temp &= ~(3 << 2);
-+ temp |= (FOTG210_TUNE_FLS << 2);
-+ }
-+ fotg210->command = temp;
-+
-+ /* Accept arbitrarily long scatter-gather lists */
-+ if (!hcd->localmem_pool)
-+ hcd->self.sg_tablesize = ~0;
-+ return 0;
-+}
-+
-+/* start HC running; it's halted, hcd_fotg210_init() has been run (once) */
-+static int fotg210_run(struct usb_hcd *hcd)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+ u32 temp;
-+
-+ hcd->uses_new_polling = 1;
-+
-+ /* EHCI spec section 4.1 */
-+
-+ fotg210_writel(fotg210, fotg210->periodic_dma,
-+ &fotg210->regs->frame_list);
-+ fotg210_writel(fotg210, (u32)fotg210->async->qh_dma,
-+ &fotg210->regs->async_next);
-+
-+ /*
-+ * hcc_params controls whether fotg210->regs->segment must (!!!)
-+ * be used; it constrains QH/ITD/SITD and QTD locations.
-+ * dma_pool consistent memory always uses segment zero.
-+ * streaming mappings for I/O buffers, like dma_map_single(),
-+ * can return segments above 4GB, if the device allows.
-+ *
-+ * NOTE: the dma mask is visible through dev->dma_mask, so
-+ * drivers can pass this info along ... like NETIF_F_HIGHDMA,
-+ * Scsi_Host.highmem_io, and so forth. It's readonly to all
-+ * host side drivers though.
-+ */
-+ fotg210_readl(fotg210, &fotg210->caps->hcc_params);
-+
-+ /*
-+ * Philips, Intel, and maybe others need CMD_RUN before the
-+ * root hub will detect new devices (why?); NEC doesn't
-+ */
-+ fotg210->command &= ~(CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
-+ fotg210->command |= CMD_RUN;
-+ fotg210_writel(fotg210, fotg210->command, &fotg210->regs->command);
-+ dbg_cmd(fotg210, "init", fotg210->command);
-+
-+ /*
-+ * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
-+ * are explicitly handed to companion controller(s), so no TT is
-+ * involved with the root hub. (Except where one is integrated,
-+ * and there's no companion controller unless maybe for USB OTG.)
-+ *
-+ * Turning on the CF flag will transfer ownership of all ports
-+ * from the companions to the EHCI controller. If any of the
-+ * companions are in the middle of a port reset at the time, it
-+ * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
-+ * guarantees that no resets are in progress. After we set CF,
-+ * a short delay lets the hardware catch up; new resets shouldn't
-+ * be started before the port switching actions could complete.
-+ */
-+ down_write(&ehci_cf_port_reset_rwsem);
-+ fotg210->rh_state = FOTG210_RH_RUNNING;
-+ /* unblock posted writes */
-+ fotg210_readl(fotg210, &fotg210->regs->command);
-+ usleep_range(5000, 10000);
-+ up_write(&ehci_cf_port_reset_rwsem);
-+ fotg210->last_periodic_enable = ktime_get_real();
-+
-+ temp = HC_VERSION(fotg210,
-+ fotg210_readl(fotg210, &fotg210->caps->hc_capbase));
-+ fotg210_info(fotg210,
-+ "USB %x.%x started, EHCI %x.%02x\n",
-+ ((fotg210->sbrn & 0xf0) >> 4), (fotg210->sbrn & 0x0f),
-+ temp >> 8, temp & 0xff);
-+
-+ fotg210_writel(fotg210, INTR_MASK,
-+ &fotg210->regs->intr_enable); /* Turn On Interrupts */
-+
-+ /* GRR this is run-once init(), being done every time the HC starts.
-+ * So long as they're part of class devices, we can't do it init()
-+ * since the class device isn't created that early.
-+ */
-+ create_debug_files(fotg210);
-+ create_sysfs_files(fotg210);
-+
-+ return 0;
-+}
-+
-+static int fotg210_setup(struct usb_hcd *hcd)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+ int retval;
-+
-+ fotg210->regs = (void __iomem *)fotg210->caps +
-+ HC_LENGTH(fotg210,
-+ fotg210_readl(fotg210, &fotg210->caps->hc_capbase));
-+ dbg_hcs_params(fotg210, "reset");
-+ dbg_hcc_params(fotg210, "reset");
-+
-+ /* cache this readonly data; minimize chip reads */
-+ fotg210->hcs_params = fotg210_readl(fotg210,
-+ &fotg210->caps->hcs_params);
-+
-+ fotg210->sbrn = HCD_USB2;
-+
-+ /* data structure init */
-+ retval = hcd_fotg210_init(hcd);
-+ if (retval)
-+ return retval;
-+
-+ retval = fotg210_halt(fotg210);
-+ if (retval)
-+ return retval;
-+
-+ fotg210_reset(fotg210);
-+
-+ return 0;
-+}
-+
-+static irqreturn_t fotg210_irq(struct usb_hcd *hcd)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+ u32 status, masked_status, pcd_status = 0, cmd;
-+ int bh;
-+
-+ spin_lock(&fotg210->lock);
-+
-+ status = fotg210_readl(fotg210, &fotg210->regs->status);
-+
-+ /* e.g. cardbus physical eject */
-+ if (status == ~(u32) 0) {
-+ fotg210_dbg(fotg210, "device removed\n");
-+ goto dead;
-+ }
-+
-+ /*
-+ * We don't use STS_FLR, but some controllers don't like it to
-+ * remain on, so mask it out along with the other status bits.
-+ */
-+ masked_status = status & (INTR_MASK | STS_FLR);
-+
-+ /* Shared IRQ? */
-+ if (!masked_status ||
-+ unlikely(fotg210->rh_state == FOTG210_RH_HALTED)) {
-+ spin_unlock(&fotg210->lock);
-+ return IRQ_NONE;
-+ }
-+
-+ /* clear (just) interrupts */
-+ fotg210_writel(fotg210, masked_status, &fotg210->regs->status);
-+ cmd = fotg210_readl(fotg210, &fotg210->regs->command);
-+ bh = 0;
-+
-+ /* unrequested/ignored: Frame List Rollover */
-+ dbg_status(fotg210, "irq", status);
-+
-+ /* INT, ERR, and IAA interrupt rates can be throttled */
-+
-+ /* normal [4.15.1.2] or error [4.15.1.1] completion */
-+ if (likely((status & (STS_INT|STS_ERR)) != 0)) {
-+ if (likely((status & STS_ERR) == 0))
-+ INCR(fotg210->stats.normal);
-+ else
-+ INCR(fotg210->stats.error);
-+ bh = 1;
-+ }
-+
-+ /* complete the unlinking of some qh [4.15.2.3] */
-+ if (status & STS_IAA) {
-+
-+ /* Turn off the IAA watchdog */
-+ fotg210->enabled_hrtimer_events &=
-+ ~BIT(FOTG210_HRTIMER_IAA_WATCHDOG);
-+
-+ /*
-+ * Mild optimization: Allow another IAAD to reset the
-+ * hrtimer, if one occurs before the next expiration.
-+ * In theory we could always cancel the hrtimer, but
-+ * tests show that about half the time it will be reset
-+ * for some other event anyway.
-+ */
-+ if (fotg210->next_hrtimer_event == FOTG210_HRTIMER_IAA_WATCHDOG)
-+ ++fotg210->next_hrtimer_event;
-+
-+ /* guard against (alleged) silicon errata */
-+ if (cmd & CMD_IAAD)
-+ fotg210_dbg(fotg210, "IAA with IAAD still set?\n");
-+ if (fotg210->async_iaa) {
-+ INCR(fotg210->stats.iaa);
-+ end_unlink_async(fotg210);
-+ } else
-+ fotg210_dbg(fotg210, "IAA with nothing unlinked?\n");
-+ }
-+
-+ /* remote wakeup [4.3.1] */
-+ if (status & STS_PCD) {
-+ int pstatus;
-+ u32 __iomem *status_reg = &fotg210->regs->port_status;
-+
-+ /* kick root hub later */
-+ pcd_status = status;
-+
-+ /* resume root hub? */
-+ if (fotg210->rh_state == FOTG210_RH_SUSPENDED)
-+ usb_hcd_resume_root_hub(hcd);
-+
-+ pstatus = fotg210_readl(fotg210, status_reg);
-+
-+ if (test_bit(0, &fotg210->suspended_ports) &&
-+ ((pstatus & PORT_RESUME) ||
-+ !(pstatus & PORT_SUSPEND)) &&
-+ (pstatus & PORT_PE) &&
-+ fotg210->reset_done[0] == 0) {
-+
-+ /* start 20 msec resume signaling from this port,
-+ * and make hub_wq collect PORT_STAT_C_SUSPEND to
-+ * stop that signaling. Use 5 ms extra for safety,
-+ * like usb_port_resume() does.
-+ */
-+ fotg210->reset_done[0] = jiffies + msecs_to_jiffies(25);
-+ set_bit(0, &fotg210->resuming_ports);
-+ fotg210_dbg(fotg210, "port 1 remote wakeup\n");
-+ mod_timer(&hcd->rh_timer, fotg210->reset_done[0]);
-+ }
-+ }
-+
-+ /* PCI errors [4.15.2.4] */
-+ if (unlikely((status & STS_FATAL) != 0)) {
-+ fotg210_err(fotg210, "fatal error\n");
-+ dbg_cmd(fotg210, "fatal", cmd);
-+ dbg_status(fotg210, "fatal", status);
-+dead:
-+ usb_hc_died(hcd);
-+
-+ /* Don't let the controller do anything more */
-+ fotg210->shutdown = true;
-+ fotg210->rh_state = FOTG210_RH_STOPPING;
-+ fotg210->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
-+ fotg210_writel(fotg210, fotg210->command,
-+ &fotg210->regs->command);
-+ fotg210_writel(fotg210, 0, &fotg210->regs->intr_enable);
-+ fotg210_handle_controller_death(fotg210);
-+
-+ /* Handle completions when the controller stops */
-+ bh = 0;
-+ }
-+
-+ if (bh)
-+ fotg210_work(fotg210);
-+ spin_unlock(&fotg210->lock);
-+ if (pcd_status)
-+ usb_hcd_poll_rh_status(hcd);
-+ return IRQ_HANDLED;
-+}
-+
-+/* non-error returns are a promise to giveback() the urb later
-+ * we drop ownership so next owner (or urb unlink) can get it
-+ *
-+ * urb + dev is in hcd.self.controller.urb_list
-+ * we're queueing TDs onto software and hardware lists
-+ *
-+ * hcd-specific init for hcpriv hasn't been done yet
-+ *
-+ * NOTE: control, bulk, and interrupt share the same code to append TDs
-+ * to a (possibly active) QH, and the same QH scanning code.
-+ */
-+static int fotg210_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
-+ gfp_t mem_flags)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+ struct list_head qtd_list;
-+
-+ INIT_LIST_HEAD(&qtd_list);
-+
-+ switch (usb_pipetype(urb->pipe)) {
-+ case PIPE_CONTROL:
-+ /* qh_completions() code doesn't handle all the fault cases
-+ * in multi-TD control transfers. Even 1KB is rare anyway.
-+ */
-+ if (urb->transfer_buffer_length > (16 * 1024))
-+ return -EMSGSIZE;
-+ fallthrough;
-+ /* case PIPE_BULK: */
-+ default:
-+ if (!qh_urb_transaction(fotg210, urb, &qtd_list, mem_flags))
-+ return -ENOMEM;
-+ return submit_async(fotg210, urb, &qtd_list, mem_flags);
-+
-+ case PIPE_INTERRUPT:
-+ if (!qh_urb_transaction(fotg210, urb, &qtd_list, mem_flags))
-+ return -ENOMEM;
-+ return intr_submit(fotg210, urb, &qtd_list, mem_flags);
-+
-+ case PIPE_ISOCHRONOUS:
-+ return itd_submit(fotg210, urb, mem_flags);
-+ }
-+}
-+
-+/* remove from hardware lists
-+ * completions normally happen asynchronously
-+ */
-+
-+static int fotg210_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+ struct fotg210_qh *qh;
-+ unsigned long flags;
-+ int rc;
-+
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ rc = usb_hcd_check_unlink_urb(hcd, urb, status);
-+ if (rc)
-+ goto done;
-+
-+ switch (usb_pipetype(urb->pipe)) {
-+ /* case PIPE_CONTROL: */
-+ /* case PIPE_BULK:*/
-+ default:
-+ qh = (struct fotg210_qh *) urb->hcpriv;
-+ if (!qh)
-+ break;
-+ switch (qh->qh_state) {
-+ case QH_STATE_LINKED:
-+ case QH_STATE_COMPLETING:
-+ start_unlink_async(fotg210, qh);
-+ break;
-+ case QH_STATE_UNLINK:
-+ case QH_STATE_UNLINK_WAIT:
-+ /* already started */
-+ break;
-+ case QH_STATE_IDLE:
-+ /* QH might be waiting for a Clear-TT-Buffer */
-+ qh_completions(fotg210, qh);
-+ break;
-+ }
-+ break;
-+
-+ case PIPE_INTERRUPT:
-+ qh = (struct fotg210_qh *) urb->hcpriv;
-+ if (!qh)
-+ break;
-+ switch (qh->qh_state) {
-+ case QH_STATE_LINKED:
-+ case QH_STATE_COMPLETING:
-+ start_unlink_intr(fotg210, qh);
-+ break;
-+ case QH_STATE_IDLE:
-+ qh_completions(fotg210, qh);
-+ break;
-+ default:
-+ fotg210_dbg(fotg210, "bogus qh %p state %d\n",
-+ qh, qh->qh_state);
-+ goto done;
-+ }
-+ break;
-+
-+ case PIPE_ISOCHRONOUS:
-+ /* itd... */
-+
-+ /* wait till next completion, do it then. */
-+ /* completion irqs can wait up to 1024 msec, */
-+ break;
-+ }
-+done:
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ return rc;
-+}
-+
-+/* bulk qh holds the data toggle */
-+
-+static void fotg210_endpoint_disable(struct usb_hcd *hcd,
-+ struct usb_host_endpoint *ep)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+ unsigned long flags;
-+ struct fotg210_qh *qh, *tmp;
-+
-+ /* ASSERT: any requests/urbs are being unlinked */
-+ /* ASSERT: nobody can be submitting urbs for this any more */
-+
-+rescan:
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ qh = ep->hcpriv;
-+ if (!qh)
-+ goto done;
-+
-+ /* endpoints can be iso streams. for now, we don't
-+ * accelerate iso completions ... so spin a while.
-+ */
-+ if (qh->hw == NULL) {
-+ struct fotg210_iso_stream *stream = ep->hcpriv;
-+
-+ if (!list_empty(&stream->td_list))
-+ goto idle_timeout;
-+
-+ /* BUG_ON(!list_empty(&stream->free_list)); */
-+ kfree(stream);
-+ goto done;
-+ }
-+
-+ if (fotg210->rh_state < FOTG210_RH_RUNNING)
-+ qh->qh_state = QH_STATE_IDLE;
-+ switch (qh->qh_state) {
-+ case QH_STATE_LINKED:
-+ case QH_STATE_COMPLETING:
-+ for (tmp = fotg210->async->qh_next.qh;
-+ tmp && tmp != qh;
-+ tmp = tmp->qh_next.qh)
-+ continue;
-+ /* periodic qh self-unlinks on empty, and a COMPLETING qh
-+ * may already be unlinked.
-+ */
-+ if (tmp)
-+ start_unlink_async(fotg210, qh);
-+ fallthrough;
-+ case QH_STATE_UNLINK: /* wait for hw to finish? */
-+ case QH_STATE_UNLINK_WAIT:
-+idle_timeout:
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+ schedule_timeout_uninterruptible(1);
-+ goto rescan;
-+ case QH_STATE_IDLE: /* fully unlinked */
-+ if (qh->clearing_tt)
-+ goto idle_timeout;
-+ if (list_empty(&qh->qtd_list)) {
-+ qh_destroy(fotg210, qh);
-+ break;
-+ }
-+ fallthrough;
-+ default:
-+ /* caller was supposed to have unlinked any requests;
-+ * that's not our job. just leak this memory.
-+ */
-+ fotg210_err(fotg210, "qh %p (#%02x) state %d%s\n",
-+ qh, ep->desc.bEndpointAddress, qh->qh_state,
-+ list_empty(&qh->qtd_list) ? "" : "(has tds)");
-+ break;
-+ }
-+done:
-+ ep->hcpriv = NULL;
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+}
-+
-+static void fotg210_endpoint_reset(struct usb_hcd *hcd,
-+ struct usb_host_endpoint *ep)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+ struct fotg210_qh *qh;
-+ int eptype = usb_endpoint_type(&ep->desc);
-+ int epnum = usb_endpoint_num(&ep->desc);
-+ int is_out = usb_endpoint_dir_out(&ep->desc);
-+ unsigned long flags;
-+
-+ if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
-+ return;
-+
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+ qh = ep->hcpriv;
-+
-+ /* For Bulk and Interrupt endpoints we maintain the toggle state
-+ * in the hardware; the toggle bits in udev aren't used at all.
-+ * When an endpoint is reset by usb_clear_halt() we must reset
-+ * the toggle bit in the QH.
-+ */
-+ if (qh) {
-+ usb_settoggle(qh->dev, epnum, is_out, 0);
-+ if (!list_empty(&qh->qtd_list)) {
-+ WARN_ONCE(1, "clear_halt for a busy endpoint\n");
-+ } else if (qh->qh_state == QH_STATE_LINKED ||
-+ qh->qh_state == QH_STATE_COMPLETING) {
-+
-+ /* The toggle value in the QH can't be updated
-+ * while the QH is active. Unlink it now;
-+ * re-linking will call qh_refresh().
-+ */
-+ if (eptype == USB_ENDPOINT_XFER_BULK)
-+ start_unlink_async(fotg210, qh);
-+ else
-+ start_unlink_intr(fotg210, qh);
-+ }
-+ }
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+}
-+
-+static int fotg210_get_frame(struct usb_hcd *hcd)
-+{
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+
-+ return (fotg210_read_frame_index(fotg210) >> 3) %
-+ fotg210->periodic_size;
-+}
-+
-+/* The EHCI in ChipIdea HDRC cannot be a separate module or device,
-+ * because its registers (and irq) are shared between host/gadget/otg
-+ * functions and in order to facilitate role switching we cannot
-+ * give the fotg210 driver exclusive access to those.
-+ */
-+MODULE_DESCRIPTION(DRIVER_DESC);
-+MODULE_AUTHOR(DRIVER_AUTHOR);
-+MODULE_LICENSE("GPL");
-+
-+static const struct hc_driver fotg210_fotg210_hc_driver = {
-+ .description = hcd_name,
-+ .product_desc = "Faraday USB2.0 Host Controller",
-+ .hcd_priv_size = sizeof(struct fotg210_hcd),
-+
-+ /*
-+ * generic hardware linkage
-+ */
-+ .irq = fotg210_irq,
-+ .flags = HCD_MEMORY | HCD_DMA | HCD_USB2,
-+
-+ /*
-+ * basic lifecycle operations
-+ */
-+ .reset = hcd_fotg210_init,
-+ .start = fotg210_run,
-+ .stop = fotg210_stop,
-+ .shutdown = fotg210_shutdown,
-+
-+ /*
-+ * managing i/o requests and associated device resources
-+ */
-+ .urb_enqueue = fotg210_urb_enqueue,
-+ .urb_dequeue = fotg210_urb_dequeue,
-+ .endpoint_disable = fotg210_endpoint_disable,
-+ .endpoint_reset = fotg210_endpoint_reset,
-+
-+ /*
-+ * scheduling support
-+ */
-+ .get_frame_number = fotg210_get_frame,
-+
-+ /*
-+ * root hub support
-+ */
-+ .hub_status_data = fotg210_hub_status_data,
-+ .hub_control = fotg210_hub_control,
-+ .bus_suspend = fotg210_bus_suspend,
-+ .bus_resume = fotg210_bus_resume,
-+
-+ .relinquish_port = fotg210_relinquish_port,
-+ .port_handed_over = fotg210_port_handed_over,
-+
-+ .clear_tt_buffer_complete = fotg210_clear_tt_buffer_complete,
-+};
-+
-+static void fotg210_init(struct fotg210_hcd *fotg210)
-+{
-+ u32 value;
-+
-+ iowrite32(GMIR_MDEV_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
-+ &fotg210->regs->gmir);
-+
-+ value = ioread32(&fotg210->regs->otgcsr);
-+ value &= ~OTGCSR_A_BUS_DROP;
-+ value |= OTGCSR_A_BUS_REQ;
-+ iowrite32(value, &fotg210->regs->otgcsr);
-+}
-+
-+/*
-+ * fotg210_hcd_probe - initialize faraday FOTG210 HCDs
-+ *
-+ * Allocates basic resources for this USB host controller, and
-+ * then invokes the start() method for the HCD associated with it
-+ * through the hotplug entry's driver_data.
-+ */
-+static int fotg210_hcd_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct usb_hcd *hcd;
-+ struct resource *res;
-+ int irq;
-+ int retval;
-+ struct fotg210_hcd *fotg210;
-+
-+ if (usb_disabled())
-+ return -ENODEV;
-+
-+ pdev->dev.power.power_state = PMSG_ON;
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0)
-+ return irq;
-+
-+ hcd = usb_create_hcd(&fotg210_fotg210_hc_driver, dev,
-+ dev_name(dev));
-+ if (!hcd) {
-+ dev_err(dev, "failed to create hcd\n");
-+ retval = -ENOMEM;
-+ goto fail_create_hcd;
-+ }
-+
-+ hcd->has_tt = 1;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ hcd->regs = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(hcd->regs)) {
-+ retval = PTR_ERR(hcd->regs);
-+ goto failed_put_hcd;
-+ }
-+
-+ hcd->rsrc_start = res->start;
-+ hcd->rsrc_len = resource_size(res);
-+
-+ fotg210 = hcd_to_fotg210(hcd);
-+
-+ fotg210->caps = hcd->regs;
-+
-+ /* It's OK not to supply this clock */
-+ fotg210->pclk = clk_get(dev, "PCLK");
-+ if (!IS_ERR(fotg210->pclk)) {
-+ retval = clk_prepare_enable(fotg210->pclk);
-+ if (retval) {
-+ dev_err(dev, "failed to enable PCLK\n");
-+ goto failed_put_hcd;
-+ }
-+ } else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
-+ /*
-+ * Percolate deferrals, for anything else,
-+ * just live without the clocking.
-+ */
-+ retval = PTR_ERR(fotg210->pclk);
-+ goto failed_dis_clk;
-+ }
-+
-+ retval = fotg210_setup(hcd);
-+ if (retval)
-+ goto failed_dis_clk;
-+
-+ fotg210_init(fotg210);
-+
-+ retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
-+ if (retval) {
-+ dev_err(dev, "failed to add hcd with err %d\n", retval);
-+ goto failed_dis_clk;
-+ }
-+ device_wakeup_enable(hcd->self.controller);
-+ platform_set_drvdata(pdev, hcd);
-+
-+ return retval;
-+
-+failed_dis_clk:
-+ if (!IS_ERR(fotg210->pclk)) {
-+ clk_disable_unprepare(fotg210->pclk);
-+ clk_put(fotg210->pclk);
-+ }
-+failed_put_hcd:
-+ usb_put_hcd(hcd);
-+fail_create_hcd:
-+ dev_err(dev, "init %s fail, %d\n", dev_name(dev), retval);
-+ return retval;
-+}
-+
-+/*
-+ * fotg210_hcd_remove - shutdown processing for EHCI HCDs
-+ * @dev: USB Host Controller being removed
-+ *
-+ */
-+static int fotg210_hcd_remove(struct platform_device *pdev)
-+{
-+ struct usb_hcd *hcd = platform_get_drvdata(pdev);
-+ struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-+
-+ if (!IS_ERR(fotg210->pclk)) {
-+ clk_disable_unprepare(fotg210->pclk);
-+ clk_put(fotg210->pclk);
-+ }
-+
-+ usb_remove_hcd(hcd);
-+ usb_put_hcd(hcd);
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_OF
-+static const struct of_device_id fotg210_of_match[] = {
-+ { .compatible = "faraday,fotg210" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, fotg210_of_match);
-+#endif
-+
-+static struct platform_driver fotg210_hcd_driver = {
-+ .driver = {
-+ .name = "fotg210-hcd",
-+ .of_match_table = of_match_ptr(fotg210_of_match),
-+ },
-+ .probe = fotg210_hcd_probe,
-+ .remove = fotg210_hcd_remove,
-+};
-+
-+static int __init fotg210_hcd_init(void)
-+{
-+ int retval = 0;
-+
-+ if (usb_disabled())
-+ return -ENODEV;
-+
-+ set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
-+ if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
-+ test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
-+ pr_warn("Warning! fotg210_hcd should always be loaded before uhci_hcd and ohci_hcd, not after\n");
-+
-+ pr_debug("%s: block sizes: qh %zd qtd %zd itd %zd\n",
-+ hcd_name, sizeof(struct fotg210_qh),
-+ sizeof(struct fotg210_qtd),
-+ sizeof(struct fotg210_itd));
-+
-+ fotg210_debug_root = debugfs_create_dir("fotg210", usb_debug_root);
-+
-+ retval = platform_driver_register(&fotg210_hcd_driver);
-+ if (retval < 0)
-+ goto clean;
-+ return retval;
-+
-+clean:
-+ debugfs_remove(fotg210_debug_root);
-+ fotg210_debug_root = NULL;
-+
-+ clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
-+ return retval;
-+}
-+module_init(fotg210_hcd_init);
-+
-+static void __exit fotg210_hcd_cleanup(void)
-+{
-+ platform_driver_unregister(&fotg210_hcd_driver);
-+ debugfs_remove(fotg210_debug_root);
-+ clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
-+}
-+module_exit(fotg210_hcd_cleanup);
---- a/drivers/usb/gadget/udc/fotg210-udc.c
-+++ /dev/null
-@@ -1,1239 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0
--/*
-- * FOTG210 UDC Driver supports Bulk transfer so far
-- *
-- * Copyright (C) 2013 Faraday Technology Corporation
-- *
-- * Author : Yuan-Hsin Chen <yhchen@faraday-tech.com>
-- */
--
--#include <linux/dma-mapping.h>
--#include <linux/err.h>
--#include <linux/interrupt.h>
--#include <linux/io.h>
--#include <linux/module.h>
--#include <linux/platform_device.h>
--#include <linux/usb/ch9.h>
--#include <linux/usb/gadget.h>
--
--#include "fotg210.h"
--
--#define DRIVER_DESC "FOTG210 USB Device Controller Driver"
--#define DRIVER_VERSION "30-April-2013"
--
--static const char udc_name[] = "fotg210_udc";
--static const char * const fotg210_ep_name[] = {
-- "ep0", "ep1", "ep2", "ep3", "ep4"};
--
--static void fotg210_disable_fifo_int(struct fotg210_ep *ep)
--{
-- u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
--
-- if (ep->dir_in)
-- value |= DMISGR1_MF_IN_INT(ep->epnum - 1);
-- else
-- value |= DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
-- iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
--}
--
--static void fotg210_enable_fifo_int(struct fotg210_ep *ep)
--{
-- u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
--
-- if (ep->dir_in)
-- value &= ~DMISGR1_MF_IN_INT(ep->epnum - 1);
-- else
-- value &= ~DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
-- iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
--}
--
--static void fotg210_set_cxdone(struct fotg210_udc *fotg210)
--{
-- u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
--
-- value |= DCFESR_CX_DONE;
-- iowrite32(value, fotg210->reg + FOTG210_DCFESR);
--}
--
--static void fotg210_done(struct fotg210_ep *ep, struct fotg210_request *req,
-- int status)
--{
-- list_del_init(&req->queue);
--
-- /* don't modify queue heads during completion callback */
-- if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
-- req->req.status = -ESHUTDOWN;
-- else
-- req->req.status = status;
--
-- spin_unlock(&ep->fotg210->lock);
-- usb_gadget_giveback_request(&ep->ep, &req->req);
-- spin_lock(&ep->fotg210->lock);
--
-- if (ep->epnum) {
-- if (list_empty(&ep->queue))
-- fotg210_disable_fifo_int(ep);
-- } else {
-- fotg210_set_cxdone(ep->fotg210);
-- }
--}
--
--static void fotg210_fifo_ep_mapping(struct fotg210_ep *ep, u32 epnum,
-- u32 dir_in)
--{
-- struct fotg210_udc *fotg210 = ep->fotg210;
-- u32 val;
--
-- /* Driver should map an ep to a fifo and then map the fifo
-- * to the ep. What a brain-damaged design!
-- */
--
-- /* map a fifo to an ep */
-- val = ioread32(fotg210->reg + FOTG210_EPMAP);
-- val &= ~EPMAP_FIFONOMSK(epnum, dir_in);
-- val |= EPMAP_FIFONO(epnum, dir_in);
-- iowrite32(val, fotg210->reg + FOTG210_EPMAP);
--
-- /* map the ep to the fifo */
-- val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
-- val &= ~FIFOMAP_EPNOMSK(epnum);
-- val |= FIFOMAP_EPNO(epnum);
-- iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
--
-- /* enable fifo */
-- val = ioread32(fotg210->reg + FOTG210_FIFOCF);
-- val |= FIFOCF_FIFO_EN(epnum - 1);
-- iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
--}
--
--static void fotg210_set_fifo_dir(struct fotg210_ep *ep, u32 epnum, u32 dir_in)
--{
-- struct fotg210_udc *fotg210 = ep->fotg210;
-- u32 val;
--
-- val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
-- val |= (dir_in ? FIFOMAP_DIRIN(epnum - 1) : FIFOMAP_DIROUT(epnum - 1));
-- iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
--}
--
--static void fotg210_set_tfrtype(struct fotg210_ep *ep, u32 epnum, u32 type)
--{
-- struct fotg210_udc *fotg210 = ep->fotg210;
-- u32 val;
--
-- val = ioread32(fotg210->reg + FOTG210_FIFOCF);
-- val |= FIFOCF_TYPE(type, epnum - 1);
-- iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
--}
--
--static void fotg210_set_mps(struct fotg210_ep *ep, u32 epnum, u32 mps,
-- u32 dir_in)
--{
-- struct fotg210_udc *fotg210 = ep->fotg210;
-- u32 val;
-- u32 offset = dir_in ? FOTG210_INEPMPSR(epnum) :
-- FOTG210_OUTEPMPSR(epnum);
--
-- val = ioread32(fotg210->reg + offset);
-- val |= INOUTEPMPSR_MPS(mps);
-- iowrite32(val, fotg210->reg + offset);
--}
--
--static int fotg210_config_ep(struct fotg210_ep *ep,
-- const struct usb_endpoint_descriptor *desc)
--{
-- struct fotg210_udc *fotg210 = ep->fotg210;
--
-- fotg210_set_fifo_dir(ep, ep->epnum, ep->dir_in);
-- fotg210_set_tfrtype(ep, ep->epnum, ep->type);
-- fotg210_set_mps(ep, ep->epnum, ep->ep.maxpacket, ep->dir_in);
-- fotg210_fifo_ep_mapping(ep, ep->epnum, ep->dir_in);
--
-- fotg210->ep[ep->epnum] = ep;
--
-- return 0;
--}
--
--static int fotg210_ep_enable(struct usb_ep *_ep,
-- const struct usb_endpoint_descriptor *desc)
--{
-- struct fotg210_ep *ep;
--
-- ep = container_of(_ep, struct fotg210_ep, ep);
--
-- ep->desc = desc;
-- ep->epnum = usb_endpoint_num(desc);
-- ep->type = usb_endpoint_type(desc);
-- ep->dir_in = usb_endpoint_dir_in(desc);
-- ep->ep.maxpacket = usb_endpoint_maxp(desc);
--
-- return fotg210_config_ep(ep, desc);
--}
--
--static void fotg210_reset_tseq(struct fotg210_udc *fotg210, u8 epnum)
--{
-- struct fotg210_ep *ep = fotg210->ep[epnum];
-- u32 value;
-- void __iomem *reg;
--
-- reg = (ep->dir_in) ?
-- fotg210->reg + FOTG210_INEPMPSR(epnum) :
-- fotg210->reg + FOTG210_OUTEPMPSR(epnum);
--
-- /* Note: Driver needs to set and clear INOUTEPMPSR_RESET_TSEQ
-- * bit. Controller wouldn't clear this bit. WTF!!!
-- */
--
-- value = ioread32(reg);
-- value |= INOUTEPMPSR_RESET_TSEQ;
-- iowrite32(value, reg);
--
-- value = ioread32(reg);
-- value &= ~INOUTEPMPSR_RESET_TSEQ;
-- iowrite32(value, reg);
--}
--
--static int fotg210_ep_release(struct fotg210_ep *ep)
--{
-- if (!ep->epnum)
-- return 0;
-- ep->epnum = 0;
-- ep->stall = 0;
-- ep->wedged = 0;
--
-- fotg210_reset_tseq(ep->fotg210, ep->epnum);
--
-- return 0;
--}
--
--static int fotg210_ep_disable(struct usb_ep *_ep)
--{
-- struct fotg210_ep *ep;
-- struct fotg210_request *req;
-- unsigned long flags;
--
-- BUG_ON(!_ep);
--
-- ep = container_of(_ep, struct fotg210_ep, ep);
--
-- while (!list_empty(&ep->queue)) {
-- req = list_entry(ep->queue.next,
-- struct fotg210_request, queue);
-- spin_lock_irqsave(&ep->fotg210->lock, flags);
-- fotg210_done(ep, req, -ECONNRESET);
-- spin_unlock_irqrestore(&ep->fotg210->lock, flags);
-- }
--
-- return fotg210_ep_release(ep);
--}
--
--static struct usb_request *fotg210_ep_alloc_request(struct usb_ep *_ep,
-- gfp_t gfp_flags)
--{
-- struct fotg210_request *req;
--
-- req = kzalloc(sizeof(struct fotg210_request), gfp_flags);
-- if (!req)
-- return NULL;
--
-- INIT_LIST_HEAD(&req->queue);
--
-- return &req->req;
--}
--
--static void fotg210_ep_free_request(struct usb_ep *_ep,
-- struct usb_request *_req)
--{
-- struct fotg210_request *req;
--
-- req = container_of(_req, struct fotg210_request, req);
-- kfree(req);
--}
--
--static void fotg210_enable_dma(struct fotg210_ep *ep,
-- dma_addr_t d, u32 len)
--{
-- u32 value;
-- struct fotg210_udc *fotg210 = ep->fotg210;
--
-- /* set transfer length and direction */
-- value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
-- value &= ~(DMACPSR1_DMA_LEN(0xFFFF) | DMACPSR1_DMA_TYPE(1));
-- value |= DMACPSR1_DMA_LEN(len) | DMACPSR1_DMA_TYPE(ep->dir_in);
-- iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
--
-- /* set device DMA target FIFO number */
-- value = ioread32(fotg210->reg + FOTG210_DMATFNR);
-- if (ep->epnum)
-- value |= DMATFNR_ACC_FN(ep->epnum - 1);
-- else
-- value |= DMATFNR_ACC_CXF;
-- iowrite32(value, fotg210->reg + FOTG210_DMATFNR);
--
-- /* set DMA memory address */
-- iowrite32(d, fotg210->reg + FOTG210_DMACPSR2);
--
-- /* enable MDMA_EROR and MDMA_CMPLT interrupt */
-- value = ioread32(fotg210->reg + FOTG210_DMISGR2);
-- value &= ~(DMISGR2_MDMA_CMPLT | DMISGR2_MDMA_ERROR);
-- iowrite32(value, fotg210->reg + FOTG210_DMISGR2);
--
-- /* start DMA */
-- value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
-- value |= DMACPSR1_DMA_START;
-- iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
--}
--
--static void fotg210_disable_dma(struct fotg210_ep *ep)
--{
-- iowrite32(DMATFNR_DISDMA, ep->fotg210->reg + FOTG210_DMATFNR);
--}
--
--static void fotg210_wait_dma_done(struct fotg210_ep *ep)
--{
-- u32 value;
--
-- do {
-- value = ioread32(ep->fotg210->reg + FOTG210_DISGR2);
-- if ((value & DISGR2_USBRST_INT) ||
-- (value & DISGR2_DMA_ERROR))
-- goto dma_reset;
-- } while (!(value & DISGR2_DMA_CMPLT));
--
-- value &= ~DISGR2_DMA_CMPLT;
-- iowrite32(value, ep->fotg210->reg + FOTG210_DISGR2);
-- return;
--
--dma_reset:
-- value = ioread32(ep->fotg210->reg + FOTG210_DMACPSR1);
-- value |= DMACPSR1_DMA_ABORT;
-- iowrite32(value, ep->fotg210->reg + FOTG210_DMACPSR1);
--
-- /* reset fifo */
-- if (ep->epnum) {
-- value = ioread32(ep->fotg210->reg +
-- FOTG210_FIBCR(ep->epnum - 1));
-- value |= FIBCR_FFRST;
-- iowrite32(value, ep->fotg210->reg +
-- FOTG210_FIBCR(ep->epnum - 1));
-- } else {
-- value = ioread32(ep->fotg210->reg + FOTG210_DCFESR);
-- value |= DCFESR_CX_CLR;
-- iowrite32(value, ep->fotg210->reg + FOTG210_DCFESR);
-- }
--}
--
--static void fotg210_start_dma(struct fotg210_ep *ep,
-- struct fotg210_request *req)
--{
-- struct device *dev = &ep->fotg210->gadget.dev;
-- dma_addr_t d;
-- u8 *buffer;
-- u32 length;
--
-- if (ep->epnum) {
-- if (ep->dir_in) {
-- buffer = req->req.buf;
-- length = req->req.length;
-- } else {
-- buffer = req->req.buf + req->req.actual;
-- length = ioread32(ep->fotg210->reg +
-- FOTG210_FIBCR(ep->epnum - 1)) & FIBCR_BCFX;
-- if (length > req->req.length - req->req.actual)
-- length = req->req.length - req->req.actual;
-- }
-- } else {
-- buffer = req->req.buf + req->req.actual;
-- if (req->req.length - req->req.actual > ep->ep.maxpacket)
-- length = ep->ep.maxpacket;
-- else
-- length = req->req.length - req->req.actual;
-- }
--
-- d = dma_map_single(dev, buffer, length,
-- ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
--
-- if (dma_mapping_error(dev, d)) {
-- pr_err("dma_mapping_error\n");
-- return;
-- }
--
-- fotg210_enable_dma(ep, d, length);
--
-- /* check if dma is done */
-- fotg210_wait_dma_done(ep);
--
-- fotg210_disable_dma(ep);
--
-- /* update actual transfer length */
-- req->req.actual += length;
--
-- dma_unmap_single(dev, d, length, DMA_TO_DEVICE);
--}
--
--static void fotg210_ep0_queue(struct fotg210_ep *ep,
-- struct fotg210_request *req)
--{
-- if (!req->req.length) {
-- fotg210_done(ep, req, 0);
-- return;
-- }
-- if (ep->dir_in) { /* if IN */
-- fotg210_start_dma(ep, req);
-- if (req->req.length == req->req.actual)
-- fotg210_done(ep, req, 0);
-- } else { /* OUT */
-- u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR0);
--
-- value &= ~DMISGR0_MCX_OUT_INT;
-- iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR0);
-- }
--}
--
--static int fotg210_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
-- gfp_t gfp_flags)
--{
-- struct fotg210_ep *ep;
-- struct fotg210_request *req;
-- unsigned long flags;
-- int request = 0;
--
-- ep = container_of(_ep, struct fotg210_ep, ep);
-- req = container_of(_req, struct fotg210_request, req);
--
-- if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
-- return -ESHUTDOWN;
--
-- spin_lock_irqsave(&ep->fotg210->lock, flags);
--
-- if (list_empty(&ep->queue))
-- request = 1;
--
-- list_add_tail(&req->queue, &ep->queue);
--
-- req->req.actual = 0;
-- req->req.status = -EINPROGRESS;
--
-- if (!ep->epnum) /* ep0 */
-- fotg210_ep0_queue(ep, req);
-- else if (request && !ep->stall)
-- fotg210_enable_fifo_int(ep);
--
-- spin_unlock_irqrestore(&ep->fotg210->lock, flags);
--
-- return 0;
--}
--
--static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
--{
-- struct fotg210_ep *ep;
-- struct fotg210_request *req;
-- unsigned long flags;
--
-- ep = container_of(_ep, struct fotg210_ep, ep);
-- req = container_of(_req, struct fotg210_request, req);
--
-- spin_lock_irqsave(&ep->fotg210->lock, flags);
-- if (!list_empty(&ep->queue))
-- fotg210_done(ep, req, -ECONNRESET);
-- spin_unlock_irqrestore(&ep->fotg210->lock, flags);
--
-- return 0;
--}
--
--static void fotg210_set_epnstall(struct fotg210_ep *ep)
--{
-- struct fotg210_udc *fotg210 = ep->fotg210;
-- u32 value;
-- void __iomem *reg;
--
-- /* check if IN FIFO is empty before stall */
-- if (ep->dir_in) {
-- do {
-- value = ioread32(fotg210->reg + FOTG210_DCFESR);
-- } while (!(value & DCFESR_FIFO_EMPTY(ep->epnum - 1)));
-- }
--
-- reg = (ep->dir_in) ?
-- fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
-- fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
-- value = ioread32(reg);
-- value |= INOUTEPMPSR_STL_EP;
-- iowrite32(value, reg);
--}
--
--static void fotg210_clear_epnstall(struct fotg210_ep *ep)
--{
-- struct fotg210_udc *fotg210 = ep->fotg210;
-- u32 value;
-- void __iomem *reg;
--
-- reg = (ep->dir_in) ?
-- fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
-- fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
-- value = ioread32(reg);
-- value &= ~INOUTEPMPSR_STL_EP;
-- iowrite32(value, reg);
--}
--
--static int fotg210_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
--{
-- struct fotg210_ep *ep;
-- struct fotg210_udc *fotg210;
-- unsigned long flags;
--
-- ep = container_of(_ep, struct fotg210_ep, ep);
--
-- fotg210 = ep->fotg210;
--
-- spin_lock_irqsave(&ep->fotg210->lock, flags);
--
-- if (value) {
-- fotg210_set_epnstall(ep);
-- ep->stall = 1;
-- if (wedge)
-- ep->wedged = 1;
-- } else {
-- fotg210_reset_tseq(fotg210, ep->epnum);
-- fotg210_clear_epnstall(ep);
-- ep->stall = 0;
-- ep->wedged = 0;
-- if (!list_empty(&ep->queue))
-- fotg210_enable_fifo_int(ep);
-- }
--
-- spin_unlock_irqrestore(&ep->fotg210->lock, flags);
-- return 0;
--}
--
--static int fotg210_ep_set_halt(struct usb_ep *_ep, int value)
--{
-- return fotg210_set_halt_and_wedge(_ep, value, 0);
--}
--
--static int fotg210_ep_set_wedge(struct usb_ep *_ep)
--{
-- return fotg210_set_halt_and_wedge(_ep, 1, 1);
--}
--
--static void fotg210_ep_fifo_flush(struct usb_ep *_ep)
--{
--}
--
--static const struct usb_ep_ops fotg210_ep_ops = {
-- .enable = fotg210_ep_enable,
-- .disable = fotg210_ep_disable,
--
-- .alloc_request = fotg210_ep_alloc_request,
-- .free_request = fotg210_ep_free_request,
--
-- .queue = fotg210_ep_queue,
-- .dequeue = fotg210_ep_dequeue,
--
-- .set_halt = fotg210_ep_set_halt,
-- .fifo_flush = fotg210_ep_fifo_flush,
-- .set_wedge = fotg210_ep_set_wedge,
--};
--
--static void fotg210_clear_tx0byte(struct fotg210_udc *fotg210)
--{
-- u32 value = ioread32(fotg210->reg + FOTG210_TX0BYTE);
--
-- value &= ~(TX0BYTE_EP1 | TX0BYTE_EP2 | TX0BYTE_EP3
-- | TX0BYTE_EP4);
-- iowrite32(value, fotg210->reg + FOTG210_TX0BYTE);
--}
--
--static void fotg210_clear_rx0byte(struct fotg210_udc *fotg210)
--{
-- u32 value = ioread32(fotg210->reg + FOTG210_RX0BYTE);
--
-- value &= ~(RX0BYTE_EP1 | RX0BYTE_EP2 | RX0BYTE_EP3
-- | RX0BYTE_EP4);
-- iowrite32(value, fotg210->reg + FOTG210_RX0BYTE);
--}
--
--/* read 8-byte setup packet only */
--static void fotg210_rdsetupp(struct fotg210_udc *fotg210,
-- u8 *buffer)
--{
-- int i = 0;
-- u8 *tmp = buffer;
-- u32 data;
-- u32 length = 8;
--
-- iowrite32(DMATFNR_ACC_CXF, fotg210->reg + FOTG210_DMATFNR);
--
-- for (i = (length >> 2); i > 0; i--) {
-- data = ioread32(fotg210->reg + FOTG210_CXPORT);
-- *tmp = data & 0xFF;
-- *(tmp + 1) = (data >> 8) & 0xFF;
-- *(tmp + 2) = (data >> 16) & 0xFF;
-- *(tmp + 3) = (data >> 24) & 0xFF;
-- tmp = tmp + 4;
-- }
--
-- switch (length % 4) {
-- case 1:
-- data = ioread32(fotg210->reg + FOTG210_CXPORT);
-- *tmp = data & 0xFF;
-- break;
-- case 2:
-- data = ioread32(fotg210->reg + FOTG210_CXPORT);
-- *tmp = data & 0xFF;
-- *(tmp + 1) = (data >> 8) & 0xFF;
-- break;
-- case 3:
-- data = ioread32(fotg210->reg + FOTG210_CXPORT);
-- *tmp = data & 0xFF;
-- *(tmp + 1) = (data >> 8) & 0xFF;
-- *(tmp + 2) = (data >> 16) & 0xFF;
-- break;
-- default:
-- break;
-- }
--
-- iowrite32(DMATFNR_DISDMA, fotg210->reg + FOTG210_DMATFNR);
--}
--
--static void fotg210_set_configuration(struct fotg210_udc *fotg210)
--{
-- u32 value = ioread32(fotg210->reg + FOTG210_DAR);
--
-- value |= DAR_AFT_CONF;
-- iowrite32(value, fotg210->reg + FOTG210_DAR);
--}
--
--static void fotg210_set_dev_addr(struct fotg210_udc *fotg210, u32 addr)
--{
-- u32 value = ioread32(fotg210->reg + FOTG210_DAR);
--
-- value |= (addr & 0x7F);
-- iowrite32(value, fotg210->reg + FOTG210_DAR);
--}
--
--static void fotg210_set_cxstall(struct fotg210_udc *fotg210)
--{
-- u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
--
-- value |= DCFESR_CX_STL;
-- iowrite32(value, fotg210->reg + FOTG210_DCFESR);
--}
--
--static void fotg210_request_error(struct fotg210_udc *fotg210)
--{
-- fotg210_set_cxstall(fotg210);
-- pr_err("request error!!\n");
--}
--
--static void fotg210_set_address(struct fotg210_udc *fotg210,
-- struct usb_ctrlrequest *ctrl)
--{
-- if (le16_to_cpu(ctrl->wValue) >= 0x0100) {
-- fotg210_request_error(fotg210);
-- } else {
-- fotg210_set_dev_addr(fotg210, le16_to_cpu(ctrl->wValue));
-- fotg210_set_cxdone(fotg210);
-- }
--}
--
--static void fotg210_set_feature(struct fotg210_udc *fotg210,
-- struct usb_ctrlrequest *ctrl)
--{
-- switch (ctrl->bRequestType & USB_RECIP_MASK) {
-- case USB_RECIP_DEVICE:
-- fotg210_set_cxdone(fotg210);
-- break;
-- case USB_RECIP_INTERFACE:
-- fotg210_set_cxdone(fotg210);
-- break;
-- case USB_RECIP_ENDPOINT: {
-- u8 epnum;
-- epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
-- if (epnum)
-- fotg210_set_epnstall(fotg210->ep[epnum]);
-- else
-- fotg210_set_cxstall(fotg210);
-- fotg210_set_cxdone(fotg210);
-- }
-- break;
-- default:
-- fotg210_request_error(fotg210);
-- break;
-- }
--}
--
--static void fotg210_clear_feature(struct fotg210_udc *fotg210,
-- struct usb_ctrlrequest *ctrl)
--{
-- struct fotg210_ep *ep =
-- fotg210->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
--
-- switch (ctrl->bRequestType & USB_RECIP_MASK) {
-- case USB_RECIP_DEVICE:
-- fotg210_set_cxdone(fotg210);
-- break;
-- case USB_RECIP_INTERFACE:
-- fotg210_set_cxdone(fotg210);
-- break;
-- case USB_RECIP_ENDPOINT:
-- if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
-- if (ep->wedged) {
-- fotg210_set_cxdone(fotg210);
-- break;
-- }
-- if (ep->stall)
-- fotg210_set_halt_and_wedge(&ep->ep, 0, 0);
-- }
-- fotg210_set_cxdone(fotg210);
-- break;
-- default:
-- fotg210_request_error(fotg210);
-- break;
-- }
--}
--
--static int fotg210_is_epnstall(struct fotg210_ep *ep)
--{
-- struct fotg210_udc *fotg210 = ep->fotg210;
-- u32 value;
-- void __iomem *reg;
--
-- reg = (ep->dir_in) ?
-- fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
-- fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
-- value = ioread32(reg);
-- return value & INOUTEPMPSR_STL_EP ? 1 : 0;
--}
--
--/* For EP0 requests triggered by this driver (currently GET_STATUS response) */
--static void fotg210_ep0_complete(struct usb_ep *_ep, struct usb_request *req)
--{
-- struct fotg210_ep *ep;
-- struct fotg210_udc *fotg210;
--
-- ep = container_of(_ep, struct fotg210_ep, ep);
-- fotg210 = ep->fotg210;
--
-- if (req->status || req->actual != req->length) {
-- dev_warn(&fotg210->gadget.dev, "EP0 request failed: %d\n", req->status);
-- }
--}
--
--static void fotg210_get_status(struct fotg210_udc *fotg210,
-- struct usb_ctrlrequest *ctrl)
--{
-- u8 epnum;
--
-- switch (ctrl->bRequestType & USB_RECIP_MASK) {
-- case USB_RECIP_DEVICE:
-- fotg210->ep0_data = cpu_to_le16(1 << USB_DEVICE_SELF_POWERED);
-- break;
-- case USB_RECIP_INTERFACE:
-- fotg210->ep0_data = cpu_to_le16(0);
-- break;
-- case USB_RECIP_ENDPOINT:
-- epnum = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
-- if (epnum)
-- fotg210->ep0_data =
-- cpu_to_le16(fotg210_is_epnstall(fotg210->ep[epnum])
-- << USB_ENDPOINT_HALT);
-- else
-- fotg210_request_error(fotg210);
-- break;
--
-- default:
-- fotg210_request_error(fotg210);
-- return; /* exit */
-- }
--
-- fotg210->ep0_req->buf = &fotg210->ep0_data;
-- fotg210->ep0_req->length = 2;
--
-- spin_unlock(&fotg210->lock);
-- fotg210_ep_queue(fotg210->gadget.ep0, fotg210->ep0_req, GFP_ATOMIC);
-- spin_lock(&fotg210->lock);
--}
--
--static int fotg210_setup_packet(struct fotg210_udc *fotg210,
-- struct usb_ctrlrequest *ctrl)
--{
-- u8 *p = (u8 *)ctrl;
-- u8 ret = 0;
--
-- fotg210_rdsetupp(fotg210, p);
--
-- fotg210->ep[0]->dir_in = ctrl->bRequestType & USB_DIR_IN;
--
-- if (fotg210->gadget.speed == USB_SPEED_UNKNOWN) {
-- u32 value = ioread32(fotg210->reg + FOTG210_DMCR);
-- fotg210->gadget.speed = value & DMCR_HS_EN ?
-- USB_SPEED_HIGH : USB_SPEED_FULL;
-- }
--
-- /* check request */
-- if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
-- switch (ctrl->bRequest) {
-- case USB_REQ_GET_STATUS:
-- fotg210_get_status(fotg210, ctrl);
-- break;
-- case USB_REQ_CLEAR_FEATURE:
-- fotg210_clear_feature(fotg210, ctrl);
-- break;
-- case USB_REQ_SET_FEATURE:
-- fotg210_set_feature(fotg210, ctrl);
-- break;
-- case USB_REQ_SET_ADDRESS:
-- fotg210_set_address(fotg210, ctrl);
-- break;
-- case USB_REQ_SET_CONFIGURATION:
-- fotg210_set_configuration(fotg210);
-- ret = 1;
-- break;
-- default:
-- ret = 1;
-- break;
-- }
-- } else {
-- ret = 1;
-- }
--
-- return ret;
--}
--
--static void fotg210_ep0out(struct fotg210_udc *fotg210)
--{
-- struct fotg210_ep *ep = fotg210->ep[0];
--
-- if (!list_empty(&ep->queue) && !ep->dir_in) {
-- struct fotg210_request *req;
--
-- req = list_first_entry(&ep->queue,
-- struct fotg210_request, queue);
--
-- if (req->req.length)
-- fotg210_start_dma(ep, req);
--
-- if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
-- fotg210_done(ep, req, 0);
-- } else {
-- pr_err("%s : empty queue\n", __func__);
-- }
--}
--
--static void fotg210_ep0in(struct fotg210_udc *fotg210)
--{
-- struct fotg210_ep *ep = fotg210->ep[0];
--
-- if ((!list_empty(&ep->queue)) && (ep->dir_in)) {
-- struct fotg210_request *req;
--
-- req = list_entry(ep->queue.next,
-- struct fotg210_request, queue);
--
-- if (req->req.length)
-- fotg210_start_dma(ep, req);
--
-- if (req->req.actual == req->req.length)
-- fotg210_done(ep, req, 0);
-- } else {
-- fotg210_set_cxdone(fotg210);
-- }
--}
--
--static void fotg210_clear_comabt_int(struct fotg210_udc *fotg210)
--{
-- u32 value = ioread32(fotg210->reg + FOTG210_DISGR0);
--
-- value &= ~DISGR0_CX_COMABT_INT;
-- iowrite32(value, fotg210->reg + FOTG210_DISGR0);
--}
--
--static void fotg210_in_fifo_handler(struct fotg210_ep *ep)
--{
-- struct fotg210_request *req = list_entry(ep->queue.next,
-- struct fotg210_request, queue);
--
-- if (req->req.length)
-- fotg210_start_dma(ep, req);
-- fotg210_done(ep, req, 0);
--}
--
--static void fotg210_out_fifo_handler(struct fotg210_ep *ep)
--{
-- struct fotg210_request *req = list_entry(ep->queue.next,
-- struct fotg210_request, queue);
-- int disgr1 = ioread32(ep->fotg210->reg + FOTG210_DISGR1);
--
-- fotg210_start_dma(ep, req);
--
-- /* Complete the request when it's full or a short packet arrived.
-- * Like other drivers, short_not_ok isn't handled.
-- */
--
-- if (req->req.length == req->req.actual ||
-- (disgr1 & DISGR1_SPK_INT(ep->epnum - 1)))
-- fotg210_done(ep, req, 0);
--}
--
--static irqreturn_t fotg210_irq(int irq, void *_fotg210)
--{
-- struct fotg210_udc *fotg210 = _fotg210;
-- u32 int_grp = ioread32(fotg210->reg + FOTG210_DIGR);
-- u32 int_msk = ioread32(fotg210->reg + FOTG210_DMIGR);
--
-- int_grp &= ~int_msk;
--
-- spin_lock(&fotg210->lock);
--
-- if (int_grp & DIGR_INT_G2) {
-- void __iomem *reg = fotg210->reg + FOTG210_DISGR2;
-- u32 int_grp2 = ioread32(reg);
-- u32 int_msk2 = ioread32(fotg210->reg + FOTG210_DMISGR2);
-- u32 value;
--
-- int_grp2 &= ~int_msk2;
--
-- if (int_grp2 & DISGR2_USBRST_INT) {
-- usb_gadget_udc_reset(&fotg210->gadget,
-- fotg210->driver);
-- value = ioread32(reg);
-- value &= ~DISGR2_USBRST_INT;
-- iowrite32(value, reg);
-- pr_info("fotg210 udc reset\n");
-- }
-- if (int_grp2 & DISGR2_SUSP_INT) {
-- value = ioread32(reg);
-- value &= ~DISGR2_SUSP_INT;
-- iowrite32(value, reg);
-- pr_info("fotg210 udc suspend\n");
-- }
-- if (int_grp2 & DISGR2_RESM_INT) {
-- value = ioread32(reg);
-- value &= ~DISGR2_RESM_INT;
-- iowrite32(value, reg);
-- pr_info("fotg210 udc resume\n");
-- }
-- if (int_grp2 & DISGR2_ISO_SEQ_ERR_INT) {
-- value = ioread32(reg);
-- value &= ~DISGR2_ISO_SEQ_ERR_INT;
-- iowrite32(value, reg);
-- pr_info("fotg210 iso sequence error\n");
-- }
-- if (int_grp2 & DISGR2_ISO_SEQ_ABORT_INT) {
-- value = ioread32(reg);
-- value &= ~DISGR2_ISO_SEQ_ABORT_INT;
-- iowrite32(value, reg);
-- pr_info("fotg210 iso sequence abort\n");
-- }
-- if (int_grp2 & DISGR2_TX0BYTE_INT) {
-- fotg210_clear_tx0byte(fotg210);
-- value = ioread32(reg);
-- value &= ~DISGR2_TX0BYTE_INT;
-- iowrite32(value, reg);
-- pr_info("fotg210 transferred 0 byte\n");
-- }
-- if (int_grp2 & DISGR2_RX0BYTE_INT) {
-- fotg210_clear_rx0byte(fotg210);
-- value = ioread32(reg);
-- value &= ~DISGR2_RX0BYTE_INT;
-- iowrite32(value, reg);
-- pr_info("fotg210 received 0 byte\n");
-- }
-- if (int_grp2 & DISGR2_DMA_ERROR) {
-- value = ioread32(reg);
-- value &= ~DISGR2_DMA_ERROR;
-- iowrite32(value, reg);
-- }
-- }
--
-- if (int_grp & DIGR_INT_G0) {
-- void __iomem *reg = fotg210->reg + FOTG210_DISGR0;
-- u32 int_grp0 = ioread32(reg);
-- u32 int_msk0 = ioread32(fotg210->reg + FOTG210_DMISGR0);
-- struct usb_ctrlrequest ctrl;
--
-- int_grp0 &= ~int_msk0;
--
-- /* the highest priority in this source register */
-- if (int_grp0 & DISGR0_CX_COMABT_INT) {
-- fotg210_clear_comabt_int(fotg210);
-- pr_info("fotg210 CX command abort\n");
-- }
--
-- if (int_grp0 & DISGR0_CX_SETUP_INT) {
-- if (fotg210_setup_packet(fotg210, &ctrl)) {
-- spin_unlock(&fotg210->lock);
-- if (fotg210->driver->setup(&fotg210->gadget,
-- &ctrl) < 0)
-- fotg210_set_cxstall(fotg210);
-- spin_lock(&fotg210->lock);
-- }
-- }
-- if (int_grp0 & DISGR0_CX_COMEND_INT)
-- pr_info("fotg210 cmd end\n");
--
-- if (int_grp0 & DISGR0_CX_IN_INT)
-- fotg210_ep0in(fotg210);
--
-- if (int_grp0 & DISGR0_CX_OUT_INT)
-- fotg210_ep0out(fotg210);
--
-- if (int_grp0 & DISGR0_CX_COMFAIL_INT) {
-- fotg210_set_cxstall(fotg210);
-- pr_info("fotg210 ep0 fail\n");
-- }
-- }
--
-- if (int_grp & DIGR_INT_G1) {
-- void __iomem *reg = fotg210->reg + FOTG210_DISGR1;
-- u32 int_grp1 = ioread32(reg);
-- u32 int_msk1 = ioread32(fotg210->reg + FOTG210_DMISGR1);
-- int fifo;
--
-- int_grp1 &= ~int_msk1;
--
-- for (fifo = 0; fifo < FOTG210_MAX_FIFO_NUM; fifo++) {
-- if (int_grp1 & DISGR1_IN_INT(fifo))
-- fotg210_in_fifo_handler(fotg210->ep[fifo + 1]);
--
-- if ((int_grp1 & DISGR1_OUT_INT(fifo)) ||
-- (int_grp1 & DISGR1_SPK_INT(fifo)))
-- fotg210_out_fifo_handler(fotg210->ep[fifo + 1]);
-- }
-- }
--
-- spin_unlock(&fotg210->lock);
--
-- return IRQ_HANDLED;
--}
--
--static void fotg210_disable_unplug(struct fotg210_udc *fotg210)
--{
-- u32 reg = ioread32(fotg210->reg + FOTG210_PHYTMSR);
--
-- reg &= ~PHYTMSR_UNPLUG;
-- iowrite32(reg, fotg210->reg + FOTG210_PHYTMSR);
--}
--
--static int fotg210_udc_start(struct usb_gadget *g,
-- struct usb_gadget_driver *driver)
--{
-- struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
-- u32 value;
--
-- /* hook up the driver */
-- fotg210->driver = driver;
--
-- /* enable device global interrupt */
-- value = ioread32(fotg210->reg + FOTG210_DMCR);
-- value |= DMCR_GLINT_EN;
-- iowrite32(value, fotg210->reg + FOTG210_DMCR);
--
-- return 0;
--}
--
--static void fotg210_init(struct fotg210_udc *fotg210)
--{
-- u32 value;
--
-- /* disable global interrupt and set int polarity to active high */
-- iowrite32(GMIR_MHC_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
-- fotg210->reg + FOTG210_GMIR);
--
-- /* disable device global interrupt */
-- value = ioread32(fotg210->reg + FOTG210_DMCR);
-- value &= ~DMCR_GLINT_EN;
-- iowrite32(value, fotg210->reg + FOTG210_DMCR);
--
-- /* enable only grp2 irqs we handle */
-- iowrite32(~(DISGR2_DMA_ERROR | DISGR2_RX0BYTE_INT | DISGR2_TX0BYTE_INT
-- | DISGR2_ISO_SEQ_ABORT_INT | DISGR2_ISO_SEQ_ERR_INT
-- | DISGR2_RESM_INT | DISGR2_SUSP_INT | DISGR2_USBRST_INT),
-- fotg210->reg + FOTG210_DMISGR2);
--
-- /* disable all fifo interrupt */
-- iowrite32(~(u32)0, fotg210->reg + FOTG210_DMISGR1);
--
-- /* disable cmd end */
-- value = ioread32(fotg210->reg + FOTG210_DMISGR0);
-- value |= DMISGR0_MCX_COMEND;
-- iowrite32(value, fotg210->reg + FOTG210_DMISGR0);
--}
--
--static int fotg210_udc_stop(struct usb_gadget *g)
--{
-- struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
-- unsigned long flags;
--
-- spin_lock_irqsave(&fotg210->lock, flags);
--
-- fotg210_init(fotg210);
-- fotg210->driver = NULL;
--
-- spin_unlock_irqrestore(&fotg210->lock, flags);
--
-- return 0;
--}
--
--static const struct usb_gadget_ops fotg210_gadget_ops = {
-- .udc_start = fotg210_udc_start,
-- .udc_stop = fotg210_udc_stop,
--};
--
--static int fotg210_udc_remove(struct platform_device *pdev)
--{
-- struct fotg210_udc *fotg210 = platform_get_drvdata(pdev);
-- int i;
--
-- usb_del_gadget_udc(&fotg210->gadget);
-- iounmap(fotg210->reg);
-- free_irq(platform_get_irq(pdev, 0), fotg210);
--
-- fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
-- for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
-- kfree(fotg210->ep[i]);
-- kfree(fotg210);
--
-- return 0;
--}
--
--static int fotg210_udc_probe(struct platform_device *pdev)
--{
-- struct resource *res, *ires;
-- struct fotg210_udc *fotg210 = NULL;
-- struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
-- int ret = 0;
-- int i;
--
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- if (!res) {
-- pr_err("platform_get_resource error.\n");
-- return -ENODEV;
-- }
--
-- ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-- if (!ires) {
-- pr_err("platform_get_resource IORESOURCE_IRQ error.\n");
-- return -ENODEV;
-- }
--
-- ret = -ENOMEM;
--
-- /* initialize udc */
-- fotg210 = kzalloc(sizeof(struct fotg210_udc), GFP_KERNEL);
-- if (fotg210 == NULL)
-- goto err;
--
-- for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
-- _ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
-- if (_ep[i] == NULL)
-- goto err_alloc;
-- fotg210->ep[i] = _ep[i];
-- }
--
-- fotg210->reg = ioremap(res->start, resource_size(res));
-- if (fotg210->reg == NULL) {
-- pr_err("ioremap error.\n");
-- goto err_alloc;
-- }
--
-- spin_lock_init(&fotg210->lock);
--
-- platform_set_drvdata(pdev, fotg210);
--
-- fotg210->gadget.ops = &fotg210_gadget_ops;
--
-- fotg210->gadget.max_speed = USB_SPEED_HIGH;
-- fotg210->gadget.dev.parent = &pdev->dev;
-- fotg210->gadget.dev.dma_mask = pdev->dev.dma_mask;
-- fotg210->gadget.name = udc_name;
--
-- INIT_LIST_HEAD(&fotg210->gadget.ep_list);
--
-- for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
-- struct fotg210_ep *ep = fotg210->ep[i];
--
-- if (i) {
-- INIT_LIST_HEAD(&fotg210->ep[i]->ep.ep_list);
-- list_add_tail(&fotg210->ep[i]->ep.ep_list,
-- &fotg210->gadget.ep_list);
-- }
-- ep->fotg210 = fotg210;
-- INIT_LIST_HEAD(&ep->queue);
-- ep->ep.name = fotg210_ep_name[i];
-- ep->ep.ops = &fotg210_ep_ops;
-- usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
--
-- if (i == 0) {
-- ep->ep.caps.type_control = true;
-- } else {
-- ep->ep.caps.type_iso = true;
-- ep->ep.caps.type_bulk = true;
-- ep->ep.caps.type_int = true;
-- }
--
-- ep->ep.caps.dir_in = true;
-- ep->ep.caps.dir_out = true;
-- }
-- usb_ep_set_maxpacket_limit(&fotg210->ep[0]->ep, 0x40);
-- fotg210->gadget.ep0 = &fotg210->ep[0]->ep;
-- INIT_LIST_HEAD(&fotg210->gadget.ep0->ep_list);
--
-- fotg210->ep0_req = fotg210_ep_alloc_request(&fotg210->ep[0]->ep,
-- GFP_KERNEL);
-- if (fotg210->ep0_req == NULL)
-- goto err_map;
--
-- fotg210->ep0_req->complete = fotg210_ep0_complete;
--
-- fotg210_init(fotg210);
--
-- fotg210_disable_unplug(fotg210);
--
-- ret = request_irq(ires->start, fotg210_irq, IRQF_SHARED,
-- udc_name, fotg210);
-- if (ret < 0) {
-- pr_err("request_irq error (%d)\n", ret);
-- goto err_req;
-- }
--
-- ret = usb_add_gadget_udc(&pdev->dev, &fotg210->gadget);
-- if (ret)
-- goto err_add_udc;
--
-- dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
--
-- return 0;
--
--err_add_udc:
-- free_irq(ires->start, fotg210);
--
--err_req:
-- fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
--
--err_map:
-- iounmap(fotg210->reg);
--
--err_alloc:
-- for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
-- kfree(fotg210->ep[i]);
-- kfree(fotg210);
--
--err:
-- return ret;
--}
--
--static struct platform_driver fotg210_driver = {
-- .driver = {
-- .name = udc_name,
-- },
-- .probe = fotg210_udc_probe,
-- .remove = fotg210_udc_remove,
--};
--
--module_platform_driver(fotg210_driver);
--
--MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
--MODULE_LICENSE("GPL");
--MODULE_DESCRIPTION(DRIVER_DESC);
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -0,0 +1,1239 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * FOTG210 UDC Driver supports Bulk transfer so far
-+ *
-+ * Copyright (C) 2013 Faraday Technology Corporation
-+ *
-+ * Author : Yuan-Hsin Chen <yhchen@faraday-tech.com>
-+ */
-+
-+#include <linux/dma-mapping.h>
-+#include <linux/err.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/usb/ch9.h>
-+#include <linux/usb/gadget.h>
-+
-+#include "fotg210-udc.h"
-+
-+#define DRIVER_DESC "FOTG210 USB Device Controller Driver"
-+#define DRIVER_VERSION "30-April-2013"
-+
-+static const char udc_name[] = "fotg210_udc";
-+static const char * const fotg210_ep_name[] = {
-+ "ep0", "ep1", "ep2", "ep3", "ep4"};
-+
-+static void fotg210_disable_fifo_int(struct fotg210_ep *ep)
-+{
-+ u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
-+
-+ if (ep->dir_in)
-+ value |= DMISGR1_MF_IN_INT(ep->epnum - 1);
-+ else
-+ value |= DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
-+ iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
-+}
-+
-+static void fotg210_enable_fifo_int(struct fotg210_ep *ep)
-+{
-+ u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
-+
-+ if (ep->dir_in)
-+ value &= ~DMISGR1_MF_IN_INT(ep->epnum - 1);
-+ else
-+ value &= ~DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
-+ iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
-+}
-+
-+static void fotg210_set_cxdone(struct fotg210_udc *fotg210)
-+{
-+ u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
-+
-+ value |= DCFESR_CX_DONE;
-+ iowrite32(value, fotg210->reg + FOTG210_DCFESR);
-+}
-+
-+static void fotg210_done(struct fotg210_ep *ep, struct fotg210_request *req,
-+ int status)
-+{
-+ list_del_init(&req->queue);
-+
-+ /* don't modify queue heads during completion callback */
-+ if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
-+ req->req.status = -ESHUTDOWN;
-+ else
-+ req->req.status = status;
-+
-+ spin_unlock(&ep->fotg210->lock);
-+ usb_gadget_giveback_request(&ep->ep, &req->req);
-+ spin_lock(&ep->fotg210->lock);
-+
-+ if (ep->epnum) {
-+ if (list_empty(&ep->queue))
-+ fotg210_disable_fifo_int(ep);
-+ } else {
-+ fotg210_set_cxdone(ep->fotg210);
-+ }
-+}
-+
-+static void fotg210_fifo_ep_mapping(struct fotg210_ep *ep, u32 epnum,
-+ u32 dir_in)
-+{
-+ struct fotg210_udc *fotg210 = ep->fotg210;
-+ u32 val;
-+
-+ /* Driver should map an ep to a fifo and then map the fifo
-+ * to the ep. What a brain-damaged design!
-+ */
-+
-+ /* map a fifo to an ep */
-+ val = ioread32(fotg210->reg + FOTG210_EPMAP);
-+ val &= ~EPMAP_FIFONOMSK(epnum, dir_in);
-+ val |= EPMAP_FIFONO(epnum, dir_in);
-+ iowrite32(val, fotg210->reg + FOTG210_EPMAP);
-+
-+ /* map the ep to the fifo */
-+ val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
-+ val &= ~FIFOMAP_EPNOMSK(epnum);
-+ val |= FIFOMAP_EPNO(epnum);
-+ iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
-+
-+ /* enable fifo */
-+ val = ioread32(fotg210->reg + FOTG210_FIFOCF);
-+ val |= FIFOCF_FIFO_EN(epnum - 1);
-+ iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
-+}
-+
-+static void fotg210_set_fifo_dir(struct fotg210_ep *ep, u32 epnum, u32 dir_in)
-+{
-+ struct fotg210_udc *fotg210 = ep->fotg210;
-+ u32 val;
-+
-+ val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
-+ val |= (dir_in ? FIFOMAP_DIRIN(epnum - 1) : FIFOMAP_DIROUT(epnum - 1));
-+ iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
-+}
-+
-+static void fotg210_set_tfrtype(struct fotg210_ep *ep, u32 epnum, u32 type)
-+{
-+ struct fotg210_udc *fotg210 = ep->fotg210;
-+ u32 val;
-+
-+ val = ioread32(fotg210->reg + FOTG210_FIFOCF);
-+ val |= FIFOCF_TYPE(type, epnum - 1);
-+ iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
-+}
-+
-+static void fotg210_set_mps(struct fotg210_ep *ep, u32 epnum, u32 mps,
-+ u32 dir_in)
-+{
-+ struct fotg210_udc *fotg210 = ep->fotg210;
-+ u32 val;
-+ u32 offset = dir_in ? FOTG210_INEPMPSR(epnum) :
-+ FOTG210_OUTEPMPSR(epnum);
-+
-+ val = ioread32(fotg210->reg + offset);
-+ val |= INOUTEPMPSR_MPS(mps);
-+ iowrite32(val, fotg210->reg + offset);
-+}
-+
-+static int fotg210_config_ep(struct fotg210_ep *ep,
-+ const struct usb_endpoint_descriptor *desc)
-+{
-+ struct fotg210_udc *fotg210 = ep->fotg210;
-+
-+ fotg210_set_fifo_dir(ep, ep->epnum, ep->dir_in);
-+ fotg210_set_tfrtype(ep, ep->epnum, ep->type);
-+ fotg210_set_mps(ep, ep->epnum, ep->ep.maxpacket, ep->dir_in);
-+ fotg210_fifo_ep_mapping(ep, ep->epnum, ep->dir_in);
-+
-+ fotg210->ep[ep->epnum] = ep;
-+
-+ return 0;
-+}
-+
-+static int fotg210_ep_enable(struct usb_ep *_ep,
-+ const struct usb_endpoint_descriptor *desc)
-+{
-+ struct fotg210_ep *ep;
-+
-+ ep = container_of(_ep, struct fotg210_ep, ep);
-+
-+ ep->desc = desc;
-+ ep->epnum = usb_endpoint_num(desc);
-+ ep->type = usb_endpoint_type(desc);
-+ ep->dir_in = usb_endpoint_dir_in(desc);
-+ ep->ep.maxpacket = usb_endpoint_maxp(desc);
-+
-+ return fotg210_config_ep(ep, desc);
-+}
-+
-+static void fotg210_reset_tseq(struct fotg210_udc *fotg210, u8 epnum)
-+{
-+ struct fotg210_ep *ep = fotg210->ep[epnum];
-+ u32 value;
-+ void __iomem *reg;
-+
-+ reg = (ep->dir_in) ?
-+ fotg210->reg + FOTG210_INEPMPSR(epnum) :
-+ fotg210->reg + FOTG210_OUTEPMPSR(epnum);
-+
-+ /* Note: Driver needs to set and clear INOUTEPMPSR_RESET_TSEQ
-+ * bit. Controller wouldn't clear this bit. WTF!!!
-+ */
-+
-+ value = ioread32(reg);
-+ value |= INOUTEPMPSR_RESET_TSEQ;
-+ iowrite32(value, reg);
-+
-+ value = ioread32(reg);
-+ value &= ~INOUTEPMPSR_RESET_TSEQ;
-+ iowrite32(value, reg);
-+}
-+
-+static int fotg210_ep_release(struct fotg210_ep *ep)
-+{
-+ if (!ep->epnum)
-+ return 0;
-+ ep->epnum = 0;
-+ ep->stall = 0;
-+ ep->wedged = 0;
-+
-+ fotg210_reset_tseq(ep->fotg210, ep->epnum);
-+
-+ return 0;
-+}
-+
-+static int fotg210_ep_disable(struct usb_ep *_ep)
-+{
-+ struct fotg210_ep *ep;
-+ struct fotg210_request *req;
-+ unsigned long flags;
-+
-+ BUG_ON(!_ep);
-+
-+ ep = container_of(_ep, struct fotg210_ep, ep);
-+
-+ while (!list_empty(&ep->queue)) {
-+ req = list_entry(ep->queue.next,
-+ struct fotg210_request, queue);
-+ spin_lock_irqsave(&ep->fotg210->lock, flags);
-+ fotg210_done(ep, req, -ECONNRESET);
-+ spin_unlock_irqrestore(&ep->fotg210->lock, flags);
-+ }
-+
-+ return fotg210_ep_release(ep);
-+}
-+
-+static struct usb_request *fotg210_ep_alloc_request(struct usb_ep *_ep,
-+ gfp_t gfp_flags)
-+{
-+ struct fotg210_request *req;
-+
-+ req = kzalloc(sizeof(struct fotg210_request), gfp_flags);
-+ if (!req)
-+ return NULL;
-+
-+ INIT_LIST_HEAD(&req->queue);
-+
-+ return &req->req;
-+}
-+
-+static void fotg210_ep_free_request(struct usb_ep *_ep,
-+ struct usb_request *_req)
-+{
-+ struct fotg210_request *req;
-+
-+ req = container_of(_req, struct fotg210_request, req);
-+ kfree(req);
-+}
-+
-+static void fotg210_enable_dma(struct fotg210_ep *ep,
-+ dma_addr_t d, u32 len)
-+{
-+ u32 value;
-+ struct fotg210_udc *fotg210 = ep->fotg210;
-+
-+ /* set transfer length and direction */
-+ value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
-+ value &= ~(DMACPSR1_DMA_LEN(0xFFFF) | DMACPSR1_DMA_TYPE(1));
-+ value |= DMACPSR1_DMA_LEN(len) | DMACPSR1_DMA_TYPE(ep->dir_in);
-+ iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
-+
-+ /* set device DMA target FIFO number */
-+ value = ioread32(fotg210->reg + FOTG210_DMATFNR);
-+ if (ep->epnum)
-+ value |= DMATFNR_ACC_FN(ep->epnum - 1);
-+ else
-+ value |= DMATFNR_ACC_CXF;
-+ iowrite32(value, fotg210->reg + FOTG210_DMATFNR);
-+
-+ /* set DMA memory address */
-+ iowrite32(d, fotg210->reg + FOTG210_DMACPSR2);
-+
-+ /* enable MDMA_EROR and MDMA_CMPLT interrupt */
-+ value = ioread32(fotg210->reg + FOTG210_DMISGR2);
-+ value &= ~(DMISGR2_MDMA_CMPLT | DMISGR2_MDMA_ERROR);
-+ iowrite32(value, fotg210->reg + FOTG210_DMISGR2);
-+
-+ /* start DMA */
-+ value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
-+ value |= DMACPSR1_DMA_START;
-+ iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
-+}
-+
-+static void fotg210_disable_dma(struct fotg210_ep *ep)
-+{
-+ iowrite32(DMATFNR_DISDMA, ep->fotg210->reg + FOTG210_DMATFNR);
-+}
-+
-+static void fotg210_wait_dma_done(struct fotg210_ep *ep)
-+{
-+ u32 value;
-+
-+ do {
-+ value = ioread32(ep->fotg210->reg + FOTG210_DISGR2);
-+ if ((value & DISGR2_USBRST_INT) ||
-+ (value & DISGR2_DMA_ERROR))
-+ goto dma_reset;
-+ } while (!(value & DISGR2_DMA_CMPLT));
-+
-+ value &= ~DISGR2_DMA_CMPLT;
-+ iowrite32(value, ep->fotg210->reg + FOTG210_DISGR2);
-+ return;
-+
-+dma_reset:
-+ value = ioread32(ep->fotg210->reg + FOTG210_DMACPSR1);
-+ value |= DMACPSR1_DMA_ABORT;
-+ iowrite32(value, ep->fotg210->reg + FOTG210_DMACPSR1);
-+
-+ /* reset fifo */
-+ if (ep->epnum) {
-+ value = ioread32(ep->fotg210->reg +
-+ FOTG210_FIBCR(ep->epnum - 1));
-+ value |= FIBCR_FFRST;
-+ iowrite32(value, ep->fotg210->reg +
-+ FOTG210_FIBCR(ep->epnum - 1));
-+ } else {
-+ value = ioread32(ep->fotg210->reg + FOTG210_DCFESR);
-+ value |= DCFESR_CX_CLR;
-+ iowrite32(value, ep->fotg210->reg + FOTG210_DCFESR);
-+ }
-+}
-+
-+static void fotg210_start_dma(struct fotg210_ep *ep,
-+ struct fotg210_request *req)
-+{
-+ struct device *dev = &ep->fotg210->gadget.dev;
-+ dma_addr_t d;
-+ u8 *buffer;
-+ u32 length;
-+
-+ if (ep->epnum) {
-+ if (ep->dir_in) {
-+ buffer = req->req.buf;
-+ length = req->req.length;
-+ } else {
-+ buffer = req->req.buf + req->req.actual;
-+ length = ioread32(ep->fotg210->reg +
-+ FOTG210_FIBCR(ep->epnum - 1)) & FIBCR_BCFX;
-+ if (length > req->req.length - req->req.actual)
-+ length = req->req.length - req->req.actual;
-+ }
-+ } else {
-+ buffer = req->req.buf + req->req.actual;
-+ if (req->req.length - req->req.actual > ep->ep.maxpacket)
-+ length = ep->ep.maxpacket;
-+ else
-+ length = req->req.length - req->req.actual;
-+ }
-+
-+ d = dma_map_single(dev, buffer, length,
-+ ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
-+
-+ if (dma_mapping_error(dev, d)) {
-+ pr_err("dma_mapping_error\n");
-+ return;
-+ }
-+
-+ fotg210_enable_dma(ep, d, length);
-+
-+ /* check if dma is done */
-+ fotg210_wait_dma_done(ep);
-+
-+ fotg210_disable_dma(ep);
-+
-+ /* update actual transfer length */
-+ req->req.actual += length;
-+
-+ dma_unmap_single(dev, d, length, DMA_TO_DEVICE);
-+}
-+
-+static void fotg210_ep0_queue(struct fotg210_ep *ep,
-+ struct fotg210_request *req)
-+{
-+ if (!req->req.length) {
-+ fotg210_done(ep, req, 0);
-+ return;
-+ }
-+ if (ep->dir_in) { /* if IN */
-+ fotg210_start_dma(ep, req);
-+ if (req->req.length == req->req.actual)
-+ fotg210_done(ep, req, 0);
-+ } else { /* OUT */
-+ u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR0);
-+
-+ value &= ~DMISGR0_MCX_OUT_INT;
-+ iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR0);
-+ }
-+}
-+
-+static int fotg210_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
-+ gfp_t gfp_flags)
-+{
-+ struct fotg210_ep *ep;
-+ struct fotg210_request *req;
-+ unsigned long flags;
-+ int request = 0;
-+
-+ ep = container_of(_ep, struct fotg210_ep, ep);
-+ req = container_of(_req, struct fotg210_request, req);
-+
-+ if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
-+ return -ESHUTDOWN;
-+
-+ spin_lock_irqsave(&ep->fotg210->lock, flags);
-+
-+ if (list_empty(&ep->queue))
-+ request = 1;
-+
-+ list_add_tail(&req->queue, &ep->queue);
-+
-+ req->req.actual = 0;
-+ req->req.status = -EINPROGRESS;
-+
-+ if (!ep->epnum) /* ep0 */
-+ fotg210_ep0_queue(ep, req);
-+ else if (request && !ep->stall)
-+ fotg210_enable_fifo_int(ep);
-+
-+ spin_unlock_irqrestore(&ep->fotg210->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
-+{
-+ struct fotg210_ep *ep;
-+ struct fotg210_request *req;
-+ unsigned long flags;
-+
-+ ep = container_of(_ep, struct fotg210_ep, ep);
-+ req = container_of(_req, struct fotg210_request, req);
-+
-+ spin_lock_irqsave(&ep->fotg210->lock, flags);
-+ if (!list_empty(&ep->queue))
-+ fotg210_done(ep, req, -ECONNRESET);
-+ spin_unlock_irqrestore(&ep->fotg210->lock, flags);
-+
-+ return 0;
-+}
-+
-+static void fotg210_set_epnstall(struct fotg210_ep *ep)
-+{
-+ struct fotg210_udc *fotg210 = ep->fotg210;
-+ u32 value;
-+ void __iomem *reg;
-+
-+ /* check if IN FIFO is empty before stall */
-+ if (ep->dir_in) {
-+ do {
-+ value = ioread32(fotg210->reg + FOTG210_DCFESR);
-+ } while (!(value & DCFESR_FIFO_EMPTY(ep->epnum - 1)));
-+ }
-+
-+ reg = (ep->dir_in) ?
-+ fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
-+ fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
-+ value = ioread32(reg);
-+ value |= INOUTEPMPSR_STL_EP;
-+ iowrite32(value, reg);
-+}
-+
-+static void fotg210_clear_epnstall(struct fotg210_ep *ep)
-+{
-+ struct fotg210_udc *fotg210 = ep->fotg210;
-+ u32 value;
-+ void __iomem *reg;
-+
-+ reg = (ep->dir_in) ?
-+ fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
-+ fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
-+ value = ioread32(reg);
-+ value &= ~INOUTEPMPSR_STL_EP;
-+ iowrite32(value, reg);
-+}
-+
-+static int fotg210_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
-+{
-+ struct fotg210_ep *ep;
-+ struct fotg210_udc *fotg210;
-+ unsigned long flags;
-+
-+ ep = container_of(_ep, struct fotg210_ep, ep);
-+
-+ fotg210 = ep->fotg210;
-+
-+ spin_lock_irqsave(&ep->fotg210->lock, flags);
-+
-+ if (value) {
-+ fotg210_set_epnstall(ep);
-+ ep->stall = 1;
-+ if (wedge)
-+ ep->wedged = 1;
-+ } else {
-+ fotg210_reset_tseq(fotg210, ep->epnum);
-+ fotg210_clear_epnstall(ep);
-+ ep->stall = 0;
-+ ep->wedged = 0;
-+ if (!list_empty(&ep->queue))
-+ fotg210_enable_fifo_int(ep);
-+ }
-+
-+ spin_unlock_irqrestore(&ep->fotg210->lock, flags);
-+ return 0;
-+}
-+
-+static int fotg210_ep_set_halt(struct usb_ep *_ep, int value)
-+{
-+ return fotg210_set_halt_and_wedge(_ep, value, 0);
-+}
-+
-+static int fotg210_ep_set_wedge(struct usb_ep *_ep)
-+{
-+ return fotg210_set_halt_and_wedge(_ep, 1, 1);
-+}
-+
-+static void fotg210_ep_fifo_flush(struct usb_ep *_ep)
-+{
-+}
-+
-+static const struct usb_ep_ops fotg210_ep_ops = {
-+ .enable = fotg210_ep_enable,
-+ .disable = fotg210_ep_disable,
-+
-+ .alloc_request = fotg210_ep_alloc_request,
-+ .free_request = fotg210_ep_free_request,
-+
-+ .queue = fotg210_ep_queue,
-+ .dequeue = fotg210_ep_dequeue,
-+
-+ .set_halt = fotg210_ep_set_halt,
-+ .fifo_flush = fotg210_ep_fifo_flush,
-+ .set_wedge = fotg210_ep_set_wedge,
-+};
-+
-+static void fotg210_clear_tx0byte(struct fotg210_udc *fotg210)
-+{
-+ u32 value = ioread32(fotg210->reg + FOTG210_TX0BYTE);
-+
-+ value &= ~(TX0BYTE_EP1 | TX0BYTE_EP2 | TX0BYTE_EP3
-+ | TX0BYTE_EP4);
-+ iowrite32(value, fotg210->reg + FOTG210_TX0BYTE);
-+}
-+
-+static void fotg210_clear_rx0byte(struct fotg210_udc *fotg210)
-+{
-+ u32 value = ioread32(fotg210->reg + FOTG210_RX0BYTE);
-+
-+ value &= ~(RX0BYTE_EP1 | RX0BYTE_EP2 | RX0BYTE_EP3
-+ | RX0BYTE_EP4);
-+ iowrite32(value, fotg210->reg + FOTG210_RX0BYTE);
-+}
-+
-+/* read 8-byte setup packet only */
-+static void fotg210_rdsetupp(struct fotg210_udc *fotg210,
-+ u8 *buffer)
-+{
-+ int i = 0;
-+ u8 *tmp = buffer;
-+ u32 data;
-+ u32 length = 8;
-+
-+ iowrite32(DMATFNR_ACC_CXF, fotg210->reg + FOTG210_DMATFNR);
-+
-+ for (i = (length >> 2); i > 0; i--) {
-+ data = ioread32(fotg210->reg + FOTG210_CXPORT);
-+ *tmp = data & 0xFF;
-+ *(tmp + 1) = (data >> 8) & 0xFF;
-+ *(tmp + 2) = (data >> 16) & 0xFF;
-+ *(tmp + 3) = (data >> 24) & 0xFF;
-+ tmp = tmp + 4;
-+ }
-+
-+ switch (length % 4) {
-+ case 1:
-+ data = ioread32(fotg210->reg + FOTG210_CXPORT);
-+ *tmp = data & 0xFF;
-+ break;
-+ case 2:
-+ data = ioread32(fotg210->reg + FOTG210_CXPORT);
-+ *tmp = data & 0xFF;
-+ *(tmp + 1) = (data >> 8) & 0xFF;
-+ break;
-+ case 3:
-+ data = ioread32(fotg210->reg + FOTG210_CXPORT);
-+ *tmp = data & 0xFF;
-+ *(tmp + 1) = (data >> 8) & 0xFF;
-+ *(tmp + 2) = (data >> 16) & 0xFF;
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ iowrite32(DMATFNR_DISDMA, fotg210->reg + FOTG210_DMATFNR);
-+}
-+
-+static void fotg210_set_configuration(struct fotg210_udc *fotg210)
-+{
-+ u32 value = ioread32(fotg210->reg + FOTG210_DAR);
-+
-+ value |= DAR_AFT_CONF;
-+ iowrite32(value, fotg210->reg + FOTG210_DAR);
-+}
-+
-+static void fotg210_set_dev_addr(struct fotg210_udc *fotg210, u32 addr)
-+{
-+ u32 value = ioread32(fotg210->reg + FOTG210_DAR);
-+
-+ value |= (addr & 0x7F);
-+ iowrite32(value, fotg210->reg + FOTG210_DAR);
-+}
-+
-+static void fotg210_set_cxstall(struct fotg210_udc *fotg210)
-+{
-+ u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
-+
-+ value |= DCFESR_CX_STL;
-+ iowrite32(value, fotg210->reg + FOTG210_DCFESR);
-+}
-+
-+static void fotg210_request_error(struct fotg210_udc *fotg210)
-+{
-+ fotg210_set_cxstall(fotg210);
-+ pr_err("request error!!\n");
-+}
-+
-+static void fotg210_set_address(struct fotg210_udc *fotg210,
-+ struct usb_ctrlrequest *ctrl)
-+{
-+ if (le16_to_cpu(ctrl->wValue) >= 0x0100) {
-+ fotg210_request_error(fotg210);
-+ } else {
-+ fotg210_set_dev_addr(fotg210, le16_to_cpu(ctrl->wValue));
-+ fotg210_set_cxdone(fotg210);
-+ }
-+}
-+
-+static void fotg210_set_feature(struct fotg210_udc *fotg210,
-+ struct usb_ctrlrequest *ctrl)
-+{
-+ switch (ctrl->bRequestType & USB_RECIP_MASK) {
-+ case USB_RECIP_DEVICE:
-+ fotg210_set_cxdone(fotg210);
-+ break;
-+ case USB_RECIP_INTERFACE:
-+ fotg210_set_cxdone(fotg210);
-+ break;
-+ case USB_RECIP_ENDPOINT: {
-+ u8 epnum;
-+ epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
-+ if (epnum)
-+ fotg210_set_epnstall(fotg210->ep[epnum]);
-+ else
-+ fotg210_set_cxstall(fotg210);
-+ fotg210_set_cxdone(fotg210);
-+ }
-+ break;
-+ default:
-+ fotg210_request_error(fotg210);
-+ break;
-+ }
-+}
-+
-+static void fotg210_clear_feature(struct fotg210_udc *fotg210,
-+ struct usb_ctrlrequest *ctrl)
-+{
-+ struct fotg210_ep *ep =
-+ fotg210->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
-+
-+ switch (ctrl->bRequestType & USB_RECIP_MASK) {
-+ case USB_RECIP_DEVICE:
-+ fotg210_set_cxdone(fotg210);
-+ break;
-+ case USB_RECIP_INTERFACE:
-+ fotg210_set_cxdone(fotg210);
-+ break;
-+ case USB_RECIP_ENDPOINT:
-+ if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
-+ if (ep->wedged) {
-+ fotg210_set_cxdone(fotg210);
-+ break;
-+ }
-+ if (ep->stall)
-+ fotg210_set_halt_and_wedge(&ep->ep, 0, 0);
-+ }
-+ fotg210_set_cxdone(fotg210);
-+ break;
-+ default:
-+ fotg210_request_error(fotg210);
-+ break;
-+ }
-+}
-+
-+static int fotg210_is_epnstall(struct fotg210_ep *ep)
-+{
-+ struct fotg210_udc *fotg210 = ep->fotg210;
-+ u32 value;
-+ void __iomem *reg;
-+
-+ reg = (ep->dir_in) ?
-+ fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
-+ fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
-+ value = ioread32(reg);
-+ return value & INOUTEPMPSR_STL_EP ? 1 : 0;
-+}
-+
-+/* For EP0 requests triggered by this driver (currently GET_STATUS response) */
-+static void fotg210_ep0_complete(struct usb_ep *_ep, struct usb_request *req)
-+{
-+ struct fotg210_ep *ep;
-+ struct fotg210_udc *fotg210;
-+
-+ ep = container_of(_ep, struct fotg210_ep, ep);
-+ fotg210 = ep->fotg210;
-+
-+ if (req->status || req->actual != req->length) {
-+ dev_warn(&fotg210->gadget.dev, "EP0 request failed: %d\n", req->status);
-+ }
-+}
-+
-+static void fotg210_get_status(struct fotg210_udc *fotg210,
-+ struct usb_ctrlrequest *ctrl)
-+{
-+ u8 epnum;
-+
-+ switch (ctrl->bRequestType & USB_RECIP_MASK) {
-+ case USB_RECIP_DEVICE:
-+ fotg210->ep0_data = cpu_to_le16(1 << USB_DEVICE_SELF_POWERED);
-+ break;
-+ case USB_RECIP_INTERFACE:
-+ fotg210->ep0_data = cpu_to_le16(0);
-+ break;
-+ case USB_RECIP_ENDPOINT:
-+ epnum = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
-+ if (epnum)
-+ fotg210->ep0_data =
-+ cpu_to_le16(fotg210_is_epnstall(fotg210->ep[epnum])
-+ << USB_ENDPOINT_HALT);
-+ else
-+ fotg210_request_error(fotg210);
-+ break;
-+
-+ default:
-+ fotg210_request_error(fotg210);
-+ return; /* exit */
-+ }
-+
-+ fotg210->ep0_req->buf = &fotg210->ep0_data;
-+ fotg210->ep0_req->length = 2;
-+
-+ spin_unlock(&fotg210->lock);
-+ fotg210_ep_queue(fotg210->gadget.ep0, fotg210->ep0_req, GFP_ATOMIC);
-+ spin_lock(&fotg210->lock);
-+}
-+
-+static int fotg210_setup_packet(struct fotg210_udc *fotg210,
-+ struct usb_ctrlrequest *ctrl)
-+{
-+ u8 *p = (u8 *)ctrl;
-+ u8 ret = 0;
-+
-+ fotg210_rdsetupp(fotg210, p);
-+
-+ fotg210->ep[0]->dir_in = ctrl->bRequestType & USB_DIR_IN;
-+
-+ if (fotg210->gadget.speed == USB_SPEED_UNKNOWN) {
-+ u32 value = ioread32(fotg210->reg + FOTG210_DMCR);
-+ fotg210->gadget.speed = value & DMCR_HS_EN ?
-+ USB_SPEED_HIGH : USB_SPEED_FULL;
-+ }
-+
-+ /* check request */
-+ if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
-+ switch (ctrl->bRequest) {
-+ case USB_REQ_GET_STATUS:
-+ fotg210_get_status(fotg210, ctrl);
-+ break;
-+ case USB_REQ_CLEAR_FEATURE:
-+ fotg210_clear_feature(fotg210, ctrl);
-+ break;
-+ case USB_REQ_SET_FEATURE:
-+ fotg210_set_feature(fotg210, ctrl);
-+ break;
-+ case USB_REQ_SET_ADDRESS:
-+ fotg210_set_address(fotg210, ctrl);
-+ break;
-+ case USB_REQ_SET_CONFIGURATION:
-+ fotg210_set_configuration(fotg210);
-+ ret = 1;
-+ break;
-+ default:
-+ ret = 1;
-+ break;
-+ }
-+ } else {
-+ ret = 1;
-+ }
-+
-+ return ret;
-+}
-+
-+static void fotg210_ep0out(struct fotg210_udc *fotg210)
-+{
-+ struct fotg210_ep *ep = fotg210->ep[0];
-+
-+ if (!list_empty(&ep->queue) && !ep->dir_in) {
-+ struct fotg210_request *req;
-+
-+ req = list_first_entry(&ep->queue,
-+ struct fotg210_request, queue);
-+
-+ if (req->req.length)
-+ fotg210_start_dma(ep, req);
-+
-+ if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
-+ fotg210_done(ep, req, 0);
-+ } else {
-+ pr_err("%s : empty queue\n", __func__);
-+ }
-+}
-+
-+static void fotg210_ep0in(struct fotg210_udc *fotg210)
-+{
-+ struct fotg210_ep *ep = fotg210->ep[0];
-+
-+ if ((!list_empty(&ep->queue)) && (ep->dir_in)) {
-+ struct fotg210_request *req;
-+
-+ req = list_entry(ep->queue.next,
-+ struct fotg210_request, queue);
-+
-+ if (req->req.length)
-+ fotg210_start_dma(ep, req);
-+
-+ if (req->req.actual == req->req.length)
-+ fotg210_done(ep, req, 0);
-+ } else {
-+ fotg210_set_cxdone(fotg210);
-+ }
-+}
-+
-+static void fotg210_clear_comabt_int(struct fotg210_udc *fotg210)
-+{
-+ u32 value = ioread32(fotg210->reg + FOTG210_DISGR0);
-+
-+ value &= ~DISGR0_CX_COMABT_INT;
-+ iowrite32(value, fotg210->reg + FOTG210_DISGR0);
-+}
-+
-+static void fotg210_in_fifo_handler(struct fotg210_ep *ep)
-+{
-+ struct fotg210_request *req = list_entry(ep->queue.next,
-+ struct fotg210_request, queue);
-+
-+ if (req->req.length)
-+ fotg210_start_dma(ep, req);
-+ fotg210_done(ep, req, 0);
-+}
-+
-+static void fotg210_out_fifo_handler(struct fotg210_ep *ep)
-+{
-+ struct fotg210_request *req = list_entry(ep->queue.next,
-+ struct fotg210_request, queue);
-+ int disgr1 = ioread32(ep->fotg210->reg + FOTG210_DISGR1);
-+
-+ fotg210_start_dma(ep, req);
-+
-+ /* Complete the request when it's full or a short packet arrived.
-+ * Like other drivers, short_not_ok isn't handled.
-+ */
-+
-+ if (req->req.length == req->req.actual ||
-+ (disgr1 & DISGR1_SPK_INT(ep->epnum - 1)))
-+ fotg210_done(ep, req, 0);
-+}
-+
-+static irqreturn_t fotg210_irq(int irq, void *_fotg210)
-+{
-+ struct fotg210_udc *fotg210 = _fotg210;
-+ u32 int_grp = ioread32(fotg210->reg + FOTG210_DIGR);
-+ u32 int_msk = ioread32(fotg210->reg + FOTG210_DMIGR);
-+
-+ int_grp &= ~int_msk;
-+
-+ spin_lock(&fotg210->lock);
-+
-+ if (int_grp & DIGR_INT_G2) {
-+ void __iomem *reg = fotg210->reg + FOTG210_DISGR2;
-+ u32 int_grp2 = ioread32(reg);
-+ u32 int_msk2 = ioread32(fotg210->reg + FOTG210_DMISGR2);
-+ u32 value;
-+
-+ int_grp2 &= ~int_msk2;
-+
-+ if (int_grp2 & DISGR2_USBRST_INT) {
-+ usb_gadget_udc_reset(&fotg210->gadget,
-+ fotg210->driver);
-+ value = ioread32(reg);
-+ value &= ~DISGR2_USBRST_INT;
-+ iowrite32(value, reg);
-+ pr_info("fotg210 udc reset\n");
-+ }
-+ if (int_grp2 & DISGR2_SUSP_INT) {
-+ value = ioread32(reg);
-+ value &= ~DISGR2_SUSP_INT;
-+ iowrite32(value, reg);
-+ pr_info("fotg210 udc suspend\n");
-+ }
-+ if (int_grp2 & DISGR2_RESM_INT) {
-+ value = ioread32(reg);
-+ value &= ~DISGR2_RESM_INT;
-+ iowrite32(value, reg);
-+ pr_info("fotg210 udc resume\n");
-+ }
-+ if (int_grp2 & DISGR2_ISO_SEQ_ERR_INT) {
-+ value = ioread32(reg);
-+ value &= ~DISGR2_ISO_SEQ_ERR_INT;
-+ iowrite32(value, reg);
-+ pr_info("fotg210 iso sequence error\n");
-+ }
-+ if (int_grp2 & DISGR2_ISO_SEQ_ABORT_INT) {
-+ value = ioread32(reg);
-+ value &= ~DISGR2_ISO_SEQ_ABORT_INT;
-+ iowrite32(value, reg);
-+ pr_info("fotg210 iso sequence abort\n");
-+ }
-+ if (int_grp2 & DISGR2_TX0BYTE_INT) {
-+ fotg210_clear_tx0byte(fotg210);
-+ value = ioread32(reg);
-+ value &= ~DISGR2_TX0BYTE_INT;
-+ iowrite32(value, reg);
-+ pr_info("fotg210 transferred 0 byte\n");
-+ }
-+ if (int_grp2 & DISGR2_RX0BYTE_INT) {
-+ fotg210_clear_rx0byte(fotg210);
-+ value = ioread32(reg);
-+ value &= ~DISGR2_RX0BYTE_INT;
-+ iowrite32(value, reg);
-+ pr_info("fotg210 received 0 byte\n");
-+ }
-+ if (int_grp2 & DISGR2_DMA_ERROR) {
-+ value = ioread32(reg);
-+ value &= ~DISGR2_DMA_ERROR;
-+ iowrite32(value, reg);
-+ }
-+ }
-+
-+ if (int_grp & DIGR_INT_G0) {
-+ void __iomem *reg = fotg210->reg + FOTG210_DISGR0;
-+ u32 int_grp0 = ioread32(reg);
-+ u32 int_msk0 = ioread32(fotg210->reg + FOTG210_DMISGR0);
-+ struct usb_ctrlrequest ctrl;
-+
-+ int_grp0 &= ~int_msk0;
-+
-+ /* the highest priority in this source register */
-+ if (int_grp0 & DISGR0_CX_COMABT_INT) {
-+ fotg210_clear_comabt_int(fotg210);
-+ pr_info("fotg210 CX command abort\n");
-+ }
-+
-+ if (int_grp0 & DISGR0_CX_SETUP_INT) {
-+ if (fotg210_setup_packet(fotg210, &ctrl)) {
-+ spin_unlock(&fotg210->lock);
-+ if (fotg210->driver->setup(&fotg210->gadget,
-+ &ctrl) < 0)
-+ fotg210_set_cxstall(fotg210);
-+ spin_lock(&fotg210->lock);
-+ }
-+ }
-+ if (int_grp0 & DISGR0_CX_COMEND_INT)
-+ pr_info("fotg210 cmd end\n");
-+
-+ if (int_grp0 & DISGR0_CX_IN_INT)
-+ fotg210_ep0in(fotg210);
-+
-+ if (int_grp0 & DISGR0_CX_OUT_INT)
-+ fotg210_ep0out(fotg210);
-+
-+ if (int_grp0 & DISGR0_CX_COMFAIL_INT) {
-+ fotg210_set_cxstall(fotg210);
-+ pr_info("fotg210 ep0 fail\n");
-+ }
-+ }
-+
-+ if (int_grp & DIGR_INT_G1) {
-+ void __iomem *reg = fotg210->reg + FOTG210_DISGR1;
-+ u32 int_grp1 = ioread32(reg);
-+ u32 int_msk1 = ioread32(fotg210->reg + FOTG210_DMISGR1);
-+ int fifo;
-+
-+ int_grp1 &= ~int_msk1;
-+
-+ for (fifo = 0; fifo < FOTG210_MAX_FIFO_NUM; fifo++) {
-+ if (int_grp1 & DISGR1_IN_INT(fifo))
-+ fotg210_in_fifo_handler(fotg210->ep[fifo + 1]);
-+
-+ if ((int_grp1 & DISGR1_OUT_INT(fifo)) ||
-+ (int_grp1 & DISGR1_SPK_INT(fifo)))
-+ fotg210_out_fifo_handler(fotg210->ep[fifo + 1]);
-+ }
-+ }
-+
-+ spin_unlock(&fotg210->lock);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static void fotg210_disable_unplug(struct fotg210_udc *fotg210)
-+{
-+ u32 reg = ioread32(fotg210->reg + FOTG210_PHYTMSR);
-+
-+ reg &= ~PHYTMSR_UNPLUG;
-+ iowrite32(reg, fotg210->reg + FOTG210_PHYTMSR);
-+}
-+
-+static int fotg210_udc_start(struct usb_gadget *g,
-+ struct usb_gadget_driver *driver)
-+{
-+ struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
-+ u32 value;
-+
-+ /* hook up the driver */
-+ fotg210->driver = driver;
-+
-+ /* enable device global interrupt */
-+ value = ioread32(fotg210->reg + FOTG210_DMCR);
-+ value |= DMCR_GLINT_EN;
-+ iowrite32(value, fotg210->reg + FOTG210_DMCR);
-+
-+ return 0;
-+}
-+
-+static void fotg210_init(struct fotg210_udc *fotg210)
-+{
-+ u32 value;
-+
-+ /* disable global interrupt and set int polarity to active high */
-+ iowrite32(GMIR_MHC_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
-+ fotg210->reg + FOTG210_GMIR);
-+
-+ /* disable device global interrupt */
-+ value = ioread32(fotg210->reg + FOTG210_DMCR);
-+ value &= ~DMCR_GLINT_EN;
-+ iowrite32(value, fotg210->reg + FOTG210_DMCR);
-+
-+ /* enable only grp2 irqs we handle */
-+ iowrite32(~(DISGR2_DMA_ERROR | DISGR2_RX0BYTE_INT | DISGR2_TX0BYTE_INT
-+ | DISGR2_ISO_SEQ_ABORT_INT | DISGR2_ISO_SEQ_ERR_INT
-+ | DISGR2_RESM_INT | DISGR2_SUSP_INT | DISGR2_USBRST_INT),
-+ fotg210->reg + FOTG210_DMISGR2);
-+
-+ /* disable all fifo interrupt */
-+ iowrite32(~(u32)0, fotg210->reg + FOTG210_DMISGR1);
-+
-+ /* disable cmd end */
-+ value = ioread32(fotg210->reg + FOTG210_DMISGR0);
-+ value |= DMISGR0_MCX_COMEND;
-+ iowrite32(value, fotg210->reg + FOTG210_DMISGR0);
-+}
-+
-+static int fotg210_udc_stop(struct usb_gadget *g)
-+{
-+ struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&fotg210->lock, flags);
-+
-+ fotg210_init(fotg210);
-+ fotg210->driver = NULL;
-+
-+ spin_unlock_irqrestore(&fotg210->lock, flags);
-+
-+ return 0;
-+}
-+
-+static const struct usb_gadget_ops fotg210_gadget_ops = {
-+ .udc_start = fotg210_udc_start,
-+ .udc_stop = fotg210_udc_stop,
-+};
-+
-+static int fotg210_udc_remove(struct platform_device *pdev)
-+{
-+ struct fotg210_udc *fotg210 = platform_get_drvdata(pdev);
-+ int i;
-+
-+ usb_del_gadget_udc(&fotg210->gadget);
-+ iounmap(fotg210->reg);
-+ free_irq(platform_get_irq(pdev, 0), fotg210);
-+
-+ fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
-+ for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
-+ kfree(fotg210->ep[i]);
-+ kfree(fotg210);
-+
-+ return 0;
-+}
-+
-+static int fotg210_udc_probe(struct platform_device *pdev)
-+{
-+ struct resource *res, *ires;
-+ struct fotg210_udc *fotg210 = NULL;
-+ struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
-+ int ret = 0;
-+ int i;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ pr_err("platform_get_resource error.\n");
-+ return -ENODEV;
-+ }
-+
-+ ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+ if (!ires) {
-+ pr_err("platform_get_resource IORESOURCE_IRQ error.\n");
-+ return -ENODEV;
-+ }
-+
-+ ret = -ENOMEM;
-+
-+ /* initialize udc */
-+ fotg210 = kzalloc(sizeof(struct fotg210_udc), GFP_KERNEL);
-+ if (fotg210 == NULL)
-+ goto err;
-+
-+ for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
-+ _ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
-+ if (_ep[i] == NULL)
-+ goto err_alloc;
-+ fotg210->ep[i] = _ep[i];
-+ }
-+
-+ fotg210->reg = ioremap(res->start, resource_size(res));
-+ if (fotg210->reg == NULL) {
-+ pr_err("ioremap error.\n");
-+ goto err_alloc;
-+ }
-+
-+ spin_lock_init(&fotg210->lock);
-+
-+ platform_set_drvdata(pdev, fotg210);
-+
-+ fotg210->gadget.ops = &fotg210_gadget_ops;
-+
-+ fotg210->gadget.max_speed = USB_SPEED_HIGH;
-+ fotg210->gadget.dev.parent = &pdev->dev;
-+ fotg210->gadget.dev.dma_mask = pdev->dev.dma_mask;
-+ fotg210->gadget.name = udc_name;
-+
-+ INIT_LIST_HEAD(&fotg210->gadget.ep_list);
-+
-+ for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
-+ struct fotg210_ep *ep = fotg210->ep[i];
-+
-+ if (i) {
-+ INIT_LIST_HEAD(&fotg210->ep[i]->ep.ep_list);
-+ list_add_tail(&fotg210->ep[i]->ep.ep_list,
-+ &fotg210->gadget.ep_list);
-+ }
-+ ep->fotg210 = fotg210;
-+ INIT_LIST_HEAD(&ep->queue);
-+ ep->ep.name = fotg210_ep_name[i];
-+ ep->ep.ops = &fotg210_ep_ops;
-+ usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
-+
-+ if (i == 0) {
-+ ep->ep.caps.type_control = true;
-+ } else {
-+ ep->ep.caps.type_iso = true;
-+ ep->ep.caps.type_bulk = true;
-+ ep->ep.caps.type_int = true;
-+ }
-+
-+ ep->ep.caps.dir_in = true;
-+ ep->ep.caps.dir_out = true;
-+ }
-+ usb_ep_set_maxpacket_limit(&fotg210->ep[0]->ep, 0x40);
-+ fotg210->gadget.ep0 = &fotg210->ep[0]->ep;
-+ INIT_LIST_HEAD(&fotg210->gadget.ep0->ep_list);
-+
-+ fotg210->ep0_req = fotg210_ep_alloc_request(&fotg210->ep[0]->ep,
-+ GFP_KERNEL);
-+ if (fotg210->ep0_req == NULL)
-+ goto err_map;
-+
-+ fotg210->ep0_req->complete = fotg210_ep0_complete;
-+
-+ fotg210_init(fotg210);
-+
-+ fotg210_disable_unplug(fotg210);
-+
-+ ret = request_irq(ires->start, fotg210_irq, IRQF_SHARED,
-+ udc_name, fotg210);
-+ if (ret < 0) {
-+ pr_err("request_irq error (%d)\n", ret);
-+ goto err_req;
-+ }
-+
-+ ret = usb_add_gadget_udc(&pdev->dev, &fotg210->gadget);
-+ if (ret)
-+ goto err_add_udc;
-+
-+ dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
-+
-+ return 0;
-+
-+err_add_udc:
-+ free_irq(ires->start, fotg210);
-+
-+err_req:
-+ fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
-+
-+err_map:
-+ iounmap(fotg210->reg);
-+
-+err_alloc:
-+ for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
-+ kfree(fotg210->ep[i]);
-+ kfree(fotg210);
-+
-+err:
-+ return ret;
-+}
-+
-+static struct platform_driver fotg210_driver = {
-+ .driver = {
-+ .name = udc_name,
-+ },
-+ .probe = fotg210_udc_probe,
-+ .remove = fotg210_udc_remove,
-+};
-+
-+module_platform_driver(fotg210_driver);
-+
-+MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION(DRIVER_DESC);
---- a/drivers/usb/gadget/udc/Kconfig
-+++ b/drivers/usb/gadget/udc/Kconfig
-@@ -108,17 +108,6 @@ config USB_FUSB300
- help
- Faraday usb device controller FUSB300 driver
-
--config USB_FOTG210_UDC
-- depends on HAS_DMA
-- tristate "Faraday FOTG210 USB Peripheral Controller"
-- help
-- Faraday USB2.0 OTG controller which can be configured as
-- high speed or full speed USB device. This driver supppors
-- Bulk Transfer so far.
--
-- Say "y" to link the driver statically, or "m" to build a
-- dynamically linked module called "fotg210_udc".
--
- config USB_GR_UDC
- tristate "Aeroflex Gaisler GRUSBDC USB Peripheral Controller Driver"
- depends on HAS_DMA
---- a/drivers/usb/gadget/udc/Makefile
-+++ b/drivers/usb/gadget/udc/Makefile
-@@ -34,7 +34,6 @@ obj-$(CONFIG_USB_EG20T) += pch_udc.o
- obj-$(CONFIG_USB_MV_UDC) += mv_udc.o
- mv_udc-y := mv_udc_core.o
- obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
--obj-$(CONFIG_USB_FOTG210_UDC) += fotg210-udc.o
- obj-$(CONFIG_USB_MV_U3D) += mv_u3d_core.o
- obj-$(CONFIG_USB_GR_UDC) += gr_udc.o
- obj-$(CONFIG_USB_GADGET_XILINX) += udc-xilinx.o
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -389,17 +389,6 @@ config USB_ISP1362_HCD
- To compile this driver as a module, choose M here: the
- module will be called isp1362-hcd.
-
--config USB_FOTG210_HCD
-- tristate "FOTG210 HCD support"
-- depends on USB && HAS_DMA && HAS_IOMEM
-- help
-- Faraday FOTG210 is an OTG controller which can be configured as
-- an USB2.0 host. It is designed to meet USB2.0 EHCI specification
-- with minor modification.
--
-- To compile this driver as a module, choose M here: the
-- module will be called fotg210-hcd.
--
- config USB_MAX3421_HCD
- tristate "MAX3421 HCD (USB-over-SPI) support"
- depends on USB && SPI
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -84,6 +84,5 @@ obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
- obj-$(CONFIG_USB_EHCI_MV) += ehci-mv.o
- obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o
- obj-$(CONFIG_USB_HCD_SSB) += ssb-hcd.o
--obj-$(CONFIG_USB_FOTG210_HCD) += fotg210-hcd.o
- obj-$(CONFIG_USB_MAX3421_HCD) += max3421-hcd.o
- obj-$(CONFIG_USB_XEN_HCD) += xen-hcd.o
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210-hcd.h
-@@ -0,0 +1,688 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+#ifndef __LINUX_FOTG210_H
-+#define __LINUX_FOTG210_H
-+
-+#include <linux/usb/ehci-dbgp.h>
-+
-+/* definitions used for the EHCI driver */
-+
-+/*
-+ * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
-+ * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
-+ * the host controller implementation.
-+ *
-+ * To facilitate the strongest possible byte-order checking from "sparse"
-+ * and so on, we use __leXX unless that's not practical.
-+ */
-+#define __hc32 __le32
-+#define __hc16 __le16
-+
-+/* statistics can be kept for tuning/monitoring */
-+struct fotg210_stats {
-+ /* irq usage */
-+ unsigned long normal;
-+ unsigned long error;
-+ unsigned long iaa;
-+ unsigned long lost_iaa;
-+
-+ /* termination of urbs from core */
-+ unsigned long complete;
-+ unsigned long unlink;
-+};
-+
-+/* fotg210_hcd->lock guards shared data against other CPUs:
-+ * fotg210_hcd: async, unlink, periodic (and shadow), ...
-+ * usb_host_endpoint: hcpriv
-+ * fotg210_qh: qh_next, qtd_list
-+ * fotg210_qtd: qtd_list
-+ *
-+ * Also, hold this lock when talking to HC registers or
-+ * when updating hw_* fields in shared qh/qtd/... structures.
-+ */
-+
-+#define FOTG210_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
-+
-+/*
-+ * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
-+ * controller may be doing DMA. Lower values mean there's no DMA.
-+ */
-+enum fotg210_rh_state {
-+ FOTG210_RH_HALTED,
-+ FOTG210_RH_SUSPENDED,
-+ FOTG210_RH_RUNNING,
-+ FOTG210_RH_STOPPING
-+};
-+
-+/*
-+ * Timer events, ordered by increasing delay length.
-+ * Always update event_delays_ns[] and event_handlers[] (defined in
-+ * ehci-timer.c) in parallel with this list.
-+ */
-+enum fotg210_hrtimer_event {
-+ FOTG210_HRTIMER_POLL_ASS, /* Poll for async schedule off */
-+ FOTG210_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
-+ FOTG210_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
-+ FOTG210_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
-+ FOTG210_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
-+ FOTG210_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
-+ FOTG210_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
-+ FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
-+ FOTG210_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
-+ FOTG210_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
-+ FOTG210_HRTIMER_NUM_EVENTS /* Must come last */
-+};
-+#define FOTG210_HRTIMER_NO_EVENT 99
-+
-+struct fotg210_hcd { /* one per controller */
-+ /* timing support */
-+ enum fotg210_hrtimer_event next_hrtimer_event;
-+ unsigned enabled_hrtimer_events;
-+ ktime_t hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
-+ struct hrtimer hrtimer;
-+
-+ int PSS_poll_count;
-+ int ASS_poll_count;
-+ int died_poll_count;
-+
-+ /* glue to PCI and HCD framework */
-+ struct fotg210_caps __iomem *caps;
-+ struct fotg210_regs __iomem *regs;
-+ struct ehci_dbg_port __iomem *debug;
-+
-+ __u32 hcs_params; /* cached register copy */
-+ spinlock_t lock;
-+ enum fotg210_rh_state rh_state;
-+
-+ /* general schedule support */
-+ bool scanning:1;
-+ bool need_rescan:1;
-+ bool intr_unlinking:1;
-+ bool async_unlinking:1;
-+ bool shutdown:1;
-+ struct fotg210_qh *qh_scan_next;
-+
-+ /* async schedule support */
-+ struct fotg210_qh *async;
-+ struct fotg210_qh *dummy; /* For AMD quirk use */
-+ struct fotg210_qh *async_unlink;
-+ struct fotg210_qh *async_unlink_last;
-+ struct fotg210_qh *async_iaa;
-+ unsigned async_unlink_cycle;
-+ unsigned async_count; /* async activity count */
-+
-+ /* periodic schedule support */
-+#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
-+ unsigned periodic_size;
-+ __hc32 *periodic; /* hw periodic table */
-+ dma_addr_t periodic_dma;
-+ struct list_head intr_qh_list;
-+ unsigned i_thresh; /* uframes HC might cache */
-+
-+ union fotg210_shadow *pshadow; /* mirror hw periodic table */
-+ struct fotg210_qh *intr_unlink;
-+ struct fotg210_qh *intr_unlink_last;
-+ unsigned intr_unlink_cycle;
-+ unsigned now_frame; /* frame from HC hardware */
-+ unsigned next_frame; /* scan periodic, start here */
-+ unsigned intr_count; /* intr activity count */
-+ unsigned isoc_count; /* isoc activity count */
-+ unsigned periodic_count; /* periodic activity count */
-+ /* max periodic time per uframe */
-+ unsigned uframe_periodic_max;
-+
-+
-+ /* list of itds completed while now_frame was still active */
-+ struct list_head cached_itd_list;
-+ struct fotg210_itd *last_itd_to_free;
-+
-+ /* per root hub port */
-+ unsigned long reset_done[FOTG210_MAX_ROOT_PORTS];
-+
-+ /* bit vectors (one bit per port)
-+ * which ports were already suspended at the start of a bus suspend
-+ */
-+ unsigned long bus_suspended;
-+
-+ /* which ports are edicated to the companion controller */
-+ unsigned long companion_ports;
-+
-+ /* which ports are owned by the companion during a bus suspend */
-+ unsigned long owned_ports;
-+
-+ /* which ports have the change-suspend feature turned on */
-+ unsigned long port_c_suspend;
-+
-+ /* which ports are suspended */
-+ unsigned long suspended_ports;
-+
-+ /* which ports have started to resume */
-+ unsigned long resuming_ports;
-+
-+ /* per-HC memory pools (could be per-bus, but ...) */
-+ struct dma_pool *qh_pool; /* qh per active urb */
-+ struct dma_pool *qtd_pool; /* one or more per qh */
-+ struct dma_pool *itd_pool; /* itd per iso urb */
-+
-+ unsigned random_frame;
-+ unsigned long next_statechange;
-+ ktime_t last_periodic_enable;
-+ u32 command;
-+
-+ /* SILICON QUIRKS */
-+ unsigned need_io_watchdog:1;
-+ unsigned fs_i_thresh:1; /* Intel iso scheduling */
-+
-+ u8 sbrn; /* packed release number */
-+
-+ /* irq statistics */
-+#ifdef FOTG210_STATS
-+ struct fotg210_stats stats;
-+# define INCR(x) ((x)++)
-+#else
-+# define INCR(x) do {} while (0)
-+#endif
-+
-+ /* silicon clock */
-+ struct clk *pclk;
-+};
-+
-+/* convert between an HCD pointer and the corresponding FOTG210_HCD */
-+static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
-+{
-+ return (struct fotg210_hcd *)(hcd->hcd_priv);
-+}
-+static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
-+{
-+ return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
-+
-+/* Section 2.2 Host Controller Capability Registers */
-+struct fotg210_caps {
-+ /* these fields are specified as 8 and 16 bit registers,
-+ * but some hosts can't perform 8 or 16 bit PCI accesses.
-+ * some hosts treat caplength and hciversion as parts of a 32-bit
-+ * register, others treat them as two separate registers, this
-+ * affects the memory map for big endian controllers.
-+ */
-+ u32 hc_capbase;
-+#define HC_LENGTH(fotg210, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
-+ (fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
-+#define HC_VERSION(fotg210, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
-+ (fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
-+ u32 hcs_params; /* HCSPARAMS - offset 0x4 */
-+#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
-+
-+ u32 hcc_params; /* HCCPARAMS - offset 0x8 */
-+#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
-+#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
-+ u8 portroute[8]; /* nibbles for routing - offset 0xC */
-+};
-+
-+
-+/* Section 2.3 Host Controller Operational Registers */
-+struct fotg210_regs {
-+
-+ /* USBCMD: offset 0x00 */
-+ u32 command;
-+
-+/* EHCI 1.1 addendum */
-+/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
-+#define CMD_PARK (1<<11) /* enable "park" on async qh */
-+#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
-+#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
-+#define CMD_ASE (1<<5) /* async schedule enable */
-+#define CMD_PSE (1<<4) /* periodic schedule enable */
-+/* 3:2 is periodic frame list size */
-+#define CMD_RESET (1<<1) /* reset HC not bus */
-+#define CMD_RUN (1<<0) /* start/stop HC */
-+
-+ /* USBSTS: offset 0x04 */
-+ u32 status;
-+#define STS_ASS (1<<15) /* Async Schedule Status */
-+#define STS_PSS (1<<14) /* Periodic Schedule Status */
-+#define STS_RECL (1<<13) /* Reclamation */
-+#define STS_HALT (1<<12) /* Not running (any reason) */
-+/* some bits reserved */
-+ /* these STS_* flags are also intr_enable bits (USBINTR) */
-+#define STS_IAA (1<<5) /* Interrupted on async advance */
-+#define STS_FATAL (1<<4) /* such as some PCI access errors */
-+#define STS_FLR (1<<3) /* frame list rolled over */
-+#define STS_PCD (1<<2) /* port change detect */
-+#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
-+#define STS_INT (1<<0) /* "normal" completion (short, ...) */
-+
-+ /* USBINTR: offset 0x08 */
-+ u32 intr_enable;
-+
-+ /* FRINDEX: offset 0x0C */
-+ u32 frame_index; /* current microframe number */
-+ /* CTRLDSSEGMENT: offset 0x10 */
-+ u32 segment; /* address bits 63:32 if needed */
-+ /* PERIODICLISTBASE: offset 0x14 */
-+ u32 frame_list; /* points to periodic list */
-+ /* ASYNCLISTADDR: offset 0x18 */
-+ u32 async_next; /* address of next async queue head */
-+
-+ u32 reserved1;
-+ /* PORTSC: offset 0x20 */
-+ u32 port_status;
-+/* 31:23 reserved */
-+#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
-+#define PORT_RESET (1<<8) /* reset port */
-+#define PORT_SUSPEND (1<<7) /* suspend port */
-+#define PORT_RESUME (1<<6) /* resume it */
-+#define PORT_PEC (1<<3) /* port enable change */
-+#define PORT_PE (1<<2) /* port enable */
-+#define PORT_CSC (1<<1) /* connect status change */
-+#define PORT_CONNECT (1<<0) /* device connected */
-+#define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
-+ u32 reserved2[19];
-+
-+ /* OTGCSR: offet 0x70 */
-+ u32 otgcsr;
-+#define OTGCSR_HOST_SPD_TYP (3 << 22)
-+#define OTGCSR_A_BUS_DROP (1 << 5)
-+#define OTGCSR_A_BUS_REQ (1 << 4)
-+
-+ /* OTGISR: offset 0x74 */
-+ u32 otgisr;
-+#define OTGISR_OVC (1 << 10)
-+
-+ u32 reserved3[15];
-+
-+ /* GMIR: offset 0xB4 */
-+ u32 gmir;
-+#define GMIR_INT_POLARITY (1 << 3) /*Active High*/
-+#define GMIR_MHC_INT (1 << 2)
-+#define GMIR_MOTG_INT (1 << 1)
-+#define GMIR_MDEV_INT (1 << 0)
-+};
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#define QTD_NEXT(fotg210, dma) cpu_to_hc32(fotg210, (u32)dma)
-+
-+/*
-+ * EHCI Specification 0.95 Section 3.5
-+ * QTD: describe data transfer components (buffer, direction, ...)
-+ * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
-+ *
-+ * These are associated only with "QH" (Queue Head) structures,
-+ * used with control, bulk, and interrupt transfers.
-+ */
-+struct fotg210_qtd {
-+ /* first part defined by EHCI spec */
-+ __hc32 hw_next; /* see EHCI 3.5.1 */
-+ __hc32 hw_alt_next; /* see EHCI 3.5.2 */
-+ __hc32 hw_token; /* see EHCI 3.5.3 */
-+#define QTD_TOGGLE (1 << 31) /* data toggle */
-+#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
-+#define QTD_IOC (1 << 15) /* interrupt on complete */
-+#define QTD_CERR(tok) (((tok)>>10) & 0x3)
-+#define QTD_PID(tok) (((tok)>>8) & 0x3)
-+#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
-+#define QTD_STS_HALT (1 << 6) /* halted on error */
-+#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
-+#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
-+#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
-+#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
-+#define QTD_STS_STS (1 << 1) /* split transaction state */
-+#define QTD_STS_PING (1 << 0) /* issue PING? */
-+
-+#define ACTIVE_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
-+#define HALT_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_HALT)
-+#define STATUS_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_STS)
-+
-+ __hc32 hw_buf[5]; /* see EHCI 3.5.4 */
-+ __hc32 hw_buf_hi[5]; /* Appendix B */
-+
-+ /* the rest is HCD-private */
-+ dma_addr_t qtd_dma; /* qtd address */
-+ struct list_head qtd_list; /* sw qtd list */
-+ struct urb *urb; /* qtd's urb */
-+ size_t length; /* length of buffer */
-+} __aligned(32);
-+
-+/* mask NakCnt+T in qh->hw_alt_next */
-+#define QTD_MASK(fotg210) cpu_to_hc32(fotg210, ~0x1f)
-+
-+#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* type tag from {qh,itd,fstn}->hw_next */
-+#define Q_NEXT_TYPE(fotg210, dma) ((dma) & cpu_to_hc32(fotg210, 3 << 1))
-+
-+/*
-+ * Now the following defines are not converted using the
-+ * cpu_to_le32() macro anymore, since we have to support
-+ * "dynamic" switching between be and le support, so that the driver
-+ * can be used on one system with SoC EHCI controller using big-endian
-+ * descriptors as well as a normal little-endian PCI EHCI controller.
-+ */
-+/* values for that type tag */
-+#define Q_TYPE_ITD (0 << 1)
-+#define Q_TYPE_QH (1 << 1)
-+#define Q_TYPE_SITD (2 << 1)
-+#define Q_TYPE_FSTN (3 << 1)
-+
-+/* next async queue entry, or pointer to interrupt/periodic QH */
-+#define QH_NEXT(fotg210, dma) \
-+ (cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
-+
-+/* for periodic/async schedules and qtd lists, mark end of list */
-+#define FOTG210_LIST_END(fotg210) \
-+ cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
-+
-+/*
-+ * Entries in periodic shadow table are pointers to one of four kinds
-+ * of data structure. That's dictated by the hardware; a type tag is
-+ * encoded in the low bits of the hardware's periodic schedule. Use
-+ * Q_NEXT_TYPE to get the tag.
-+ *
-+ * For entries in the async schedule, the type tag always says "qh".
-+ */
-+union fotg210_shadow {
-+ struct fotg210_qh *qh; /* Q_TYPE_QH */
-+ struct fotg210_itd *itd; /* Q_TYPE_ITD */
-+ struct fotg210_fstn *fstn; /* Q_TYPE_FSTN */
-+ __hc32 *hw_next; /* (all types) */
-+ void *ptr;
-+};
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * EHCI Specification 0.95 Section 3.6
-+ * QH: describes control/bulk/interrupt endpoints
-+ * See Fig 3-7 "Queue Head Structure Layout".
-+ *
-+ * These appear in both the async and (for interrupt) periodic schedules.
-+ */
-+
-+/* first part defined by EHCI spec */
-+struct fotg210_qh_hw {
-+ __hc32 hw_next; /* see EHCI 3.6.1 */
-+ __hc32 hw_info1; /* see EHCI 3.6.2 */
-+#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
-+#define QH_HEAD (1 << 15) /* Head of async reclamation list */
-+#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
-+#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
-+#define QH_LOW_SPEED (1 << 12)
-+#define QH_FULL_SPEED (0 << 12)
-+#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
-+ __hc32 hw_info2; /* see EHCI 3.6.2 */
-+#define QH_SMASK 0x000000ff
-+#define QH_CMASK 0x0000ff00
-+#define QH_HUBADDR 0x007f0000
-+#define QH_HUBPORT 0x3f800000
-+#define QH_MULT 0xc0000000
-+ __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
-+
-+ /* qtd overlay (hardware parts of a struct fotg210_qtd) */
-+ __hc32 hw_qtd_next;
-+ __hc32 hw_alt_next;
-+ __hc32 hw_token;
-+ __hc32 hw_buf[5];
-+ __hc32 hw_buf_hi[5];
-+} __aligned(32);
-+
-+struct fotg210_qh {
-+ struct fotg210_qh_hw *hw; /* Must come first */
-+ /* the rest is HCD-private */
-+ dma_addr_t qh_dma; /* address of qh */
-+ union fotg210_shadow qh_next; /* ptr to qh; or periodic */
-+ struct list_head qtd_list; /* sw qtd list */
-+ struct list_head intr_node; /* list of intr QHs */
-+ struct fotg210_qtd *dummy;
-+ struct fotg210_qh *unlink_next; /* next on unlink list */
-+
-+ unsigned unlink_cycle;
-+
-+ u8 needs_rescan; /* Dequeue during giveback */
-+ u8 qh_state;
-+#define QH_STATE_LINKED 1 /* HC sees this */
-+#define QH_STATE_UNLINK 2 /* HC may still see this */
-+#define QH_STATE_IDLE 3 /* HC doesn't see this */
-+#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
-+#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
-+
-+ u8 xacterrs; /* XactErr retry counter */
-+#define QH_XACTERR_MAX 32 /* XactErr retry limit */
-+
-+ /* periodic schedule info */
-+ u8 usecs; /* intr bandwidth */
-+ u8 gap_uf; /* uframes split/csplit gap */
-+ u8 c_usecs; /* ... split completion bw */
-+ u16 tt_usecs; /* tt downstream bandwidth */
-+ unsigned short period; /* polling interval */
-+ unsigned short start; /* where polling starts */
-+#define NO_FRAME ((unsigned short)~0) /* pick new start */
-+
-+ struct usb_device *dev; /* access to TT */
-+ unsigned is_out:1; /* bulk or intr OUT */
-+ unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
-+};
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* description of one iso transaction (up to 3 KB data if highspeed) */
-+struct fotg210_iso_packet {
-+ /* These will be copied to iTD when scheduling */
-+ u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
-+ __hc32 transaction; /* itd->hw_transaction[i] |= */
-+ u8 cross; /* buf crosses pages */
-+ /* for full speed OUT splits */
-+ u32 buf1;
-+};
-+
-+/* temporary schedule data for packets from iso urbs (both speeds)
-+ * each packet is one logical usb transaction to the device (not TT),
-+ * beginning at stream->next_uframe
-+ */
-+struct fotg210_iso_sched {
-+ struct list_head td_list;
-+ unsigned span;
-+ struct fotg210_iso_packet packet[];
-+};
-+
-+/*
-+ * fotg210_iso_stream - groups all (s)itds for this endpoint.
-+ * acts like a qh would, if EHCI had them for ISO.
-+ */
-+struct fotg210_iso_stream {
-+ /* first field matches fotg210_hq, but is NULL */
-+ struct fotg210_qh_hw *hw;
-+
-+ u8 bEndpointAddress;
-+ u8 highspeed;
-+ struct list_head td_list; /* queued itds */
-+ struct list_head free_list; /* list of unused itds */
-+ struct usb_device *udev;
-+ struct usb_host_endpoint *ep;
-+
-+ /* output of (re)scheduling */
-+ int next_uframe;
-+ __hc32 splits;
-+
-+ /* the rest is derived from the endpoint descriptor,
-+ * trusting urb->interval == f(epdesc->bInterval) and
-+ * including the extra info for hw_bufp[0..2]
-+ */
-+ u8 usecs, c_usecs;
-+ u16 interval;
-+ u16 tt_usecs;
-+ u16 maxp;
-+ u16 raw_mask;
-+ unsigned bandwidth;
-+
-+ /* This is used to initialize iTD's hw_bufp fields */
-+ __hc32 buf0;
-+ __hc32 buf1;
-+ __hc32 buf2;
-+
-+ /* this is used to initialize sITD's tt info */
-+ __hc32 address;
-+};
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * EHCI Specification 0.95 Section 3.3
-+ * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
-+ *
-+ * Schedule records for high speed iso xfers
-+ */
-+struct fotg210_itd {
-+ /* first part defined by EHCI spec */
-+ __hc32 hw_next; /* see EHCI 3.3.1 */
-+ __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */
-+#define FOTG210_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
-+#define FOTG210_ISOC_BUF_ERR (1<<30) /* Data buffer error */
-+#define FOTG210_ISOC_BABBLE (1<<29) /* babble detected */
-+#define FOTG210_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
-+#define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
-+#define FOTG210_ITD_IOC (1 << 15) /* interrupt on complete */
-+
-+#define ITD_ACTIVE(fotg210) cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
-+
-+ __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
-+ __hc32 hw_bufp_hi[7]; /* Appendix B */
-+
-+ /* the rest is HCD-private */
-+ dma_addr_t itd_dma; /* for this itd */
-+ union fotg210_shadow itd_next; /* ptr to periodic q entry */
-+
-+ struct urb *urb;
-+ struct fotg210_iso_stream *stream; /* endpoint's queue */
-+ struct list_head itd_list; /* list of stream's itds */
-+
-+ /* any/all hw_transactions here may be used by that urb */
-+ unsigned frame; /* where scheduled */
-+ unsigned pg;
-+ unsigned index[8]; /* in urb->iso_frame_desc */
-+} __aligned(32);
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * EHCI Specification 0.96 Section 3.7
-+ * Periodic Frame Span Traversal Node (FSTN)
-+ *
-+ * Manages split interrupt transactions (using TT) that span frame boundaries
-+ * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
-+ * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
-+ * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
-+ */
-+struct fotg210_fstn {
-+ __hc32 hw_next; /* any periodic q entry */
-+ __hc32 hw_prev; /* qh or FOTG210_LIST_END */
-+
-+ /* the rest is HCD-private */
-+ dma_addr_t fstn_dma;
-+ union fotg210_shadow fstn_next; /* ptr to periodic q entry */
-+} __aligned(32);
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/* Prepare the PORTSC wakeup flags during controller suspend/resume */
-+
-+#define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
-+ fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup)
-+
-+#define fotg210_prepare_ports_for_controller_resume(fotg210) \
-+ fotg210_adjust_port_wakeup_flags(fotg210, false, false)
-+
-+/*-------------------------------------------------------------------------*/
-+
-+/*
-+ * Some EHCI controllers have a Transaction Translator built into the
-+ * root hub. This is a non-standard feature. Each controller will need
-+ * to add code to the following inline functions, and call them as
-+ * needed (mostly in root hub code).
-+ */
-+
-+static inline unsigned int
-+fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
-+{
-+ return (readl(&fotg210->regs->otgcsr)
-+ & OTGCSR_HOST_SPD_TYP) >> 22;
-+}
-+
-+/* Returns the speed of a device attached to a port on the root hub. */
-+static inline unsigned int
-+fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
-+{
-+ switch (fotg210_get_speed(fotg210, portsc)) {
-+ case 0:
-+ return 0;
-+ case 1:
-+ return USB_PORT_STAT_LOW_SPEED;
-+ case 2:
-+ default:
-+ return USB_PORT_STAT_HIGH_SPEED;
-+ }
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#define fotg210_has_fsl_portno_bug(e) (0)
-+
-+/*
-+ * While most USB host controllers implement their registers in
-+ * little-endian format, a minority (celleb companion chip) implement
-+ * them in big endian format.
-+ *
-+ * This attempts to support either format at compile time without a
-+ * runtime penalty, or both formats with the additional overhead
-+ * of checking a flag bit.
-+ *
-+ */
-+
-+#define fotg210_big_endian_mmio(e) 0
-+#define fotg210_big_endian_capbase(e) 0
-+
-+static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
-+ __u32 __iomem *regs)
-+{
-+ return readl(regs);
-+}
-+
-+static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
-+ const unsigned int val, __u32 __iomem *regs)
-+{
-+ writel(val, regs);
-+}
-+
-+/* cpu to fotg210 */
-+static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
-+{
-+ return cpu_to_le32(x);
-+}
-+
-+/* fotg210 to cpu */
-+static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
-+{
-+ return le32_to_cpu(x);
-+}
-+
-+static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
-+ const __hc32 *x)
-+{
-+ return le32_to_cpup(x);
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
-+{
-+ return fotg210_readl(fotg210, &fotg210->regs->frame_index);
-+}
-+
-+/*-------------------------------------------------------------------------*/
-+
-+#endif /* __LINUX_FOTG210_H */
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -0,0 +1,249 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Faraday FOTG210 USB OTG controller
-+ *
-+ * Copyright (C) 2013 Faraday Technology Corporation
-+ * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-+ */
-+
-+#include <linux/kernel.h>
-+
-+#define FOTG210_MAX_NUM_EP 5 /* ep0...ep4 */
-+#define FOTG210_MAX_FIFO_NUM 4 /* fifo0...fifo4 */
-+
-+/* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
-+#define FOTG210_GMIR 0xC4
-+#define GMIR_INT_POLARITY 0x8 /*Active High*/
-+#define GMIR_MHC_INT 0x4
-+#define GMIR_MOTG_INT 0x2
-+#define GMIR_MDEV_INT 0x1
-+
-+/* Device Main Control Register(0x100) */
-+#define FOTG210_DMCR 0x100
-+#define DMCR_HS_EN (1 << 6)
-+#define DMCR_CHIP_EN (1 << 5)
-+#define DMCR_SFRST (1 << 4)
-+#define DMCR_GOSUSP (1 << 3)
-+#define DMCR_GLINT_EN (1 << 2)
-+#define DMCR_HALF_SPEED (1 << 1)
-+#define DMCR_CAP_RMWAKUP (1 << 0)
-+
-+/* Device Address Register(0x104) */
-+#define FOTG210_DAR 0x104
-+#define DAR_AFT_CONF (1 << 7)
-+
-+/* Device Test Register(0x108) */
-+#define FOTG210_DTR 0x108
-+#define DTR_TST_CLRFF (1 << 0)
-+
-+/* PHY Test Mode Selector register(0x114) */
-+#define FOTG210_PHYTMSR 0x114
-+#define PHYTMSR_TST_PKT (1 << 4)
-+#define PHYTMSR_TST_SE0NAK (1 << 3)
-+#define PHYTMSR_TST_KSTA (1 << 2)
-+#define PHYTMSR_TST_JSTA (1 << 1)
-+#define PHYTMSR_UNPLUG (1 << 0)
-+
-+/* Cx configuration and FIFO Empty Status register(0x120) */
-+#define FOTG210_DCFESR 0x120
-+#define DCFESR_FIFO_EMPTY(fifo) (1 << 8 << (fifo))
-+#define DCFESR_CX_EMP (1 << 5)
-+#define DCFESR_CX_CLR (1 << 3)
-+#define DCFESR_CX_STL (1 << 2)
-+#define DCFESR_TST_PKDONE (1 << 1)
-+#define DCFESR_CX_DONE (1 << 0)
-+
-+/* Device IDLE Counter Register(0x124) */
-+#define FOTG210_DICR 0x124
-+
-+/* Device Mask of Interrupt Group Register (0x130) */
-+#define FOTG210_DMIGR 0x130
-+#define DMIGR_MINT_G0 (1 << 0)
-+
-+/* Device Mask of Interrupt Source Group 0(0x134) */
-+#define FOTG210_DMISGR0 0x134
-+#define DMISGR0_MCX_COMEND (1 << 3)
-+#define DMISGR0_MCX_OUT_INT (1 << 2)
-+#define DMISGR0_MCX_IN_INT (1 << 1)
-+#define DMISGR0_MCX_SETUP_INT (1 << 0)
-+
-+/* Device Mask of Interrupt Source Group 1 Register(0x138)*/
-+#define FOTG210_DMISGR1 0x138
-+#define DMISGR1_MF3_IN_INT (1 << 19)
-+#define DMISGR1_MF2_IN_INT (1 << 18)
-+#define DMISGR1_MF1_IN_INT (1 << 17)
-+#define DMISGR1_MF0_IN_INT (1 << 16)
-+#define DMISGR1_MF_IN_INT(fifo) (1 << (16 + (fifo)))
-+#define DMISGR1_MF3_SPK_INT (1 << 7)
-+#define DMISGR1_MF3_OUT_INT (1 << 6)
-+#define DMISGR1_MF2_SPK_INT (1 << 5)
-+#define DMISGR1_MF2_OUT_INT (1 << 4)
-+#define DMISGR1_MF1_SPK_INT (1 << 3)
-+#define DMISGR1_MF1_OUT_INT (1 << 2)
-+#define DMISGR1_MF0_SPK_INT (1 << 1)
-+#define DMISGR1_MF0_OUT_INT (1 << 0)
-+#define DMISGR1_MF_OUTSPK_INT(fifo) (0x3 << (fifo) * 2)
-+
-+/* Device Mask of Interrupt Source Group 2 Register (0x13C) */
-+#define FOTG210_DMISGR2 0x13C
-+#define DMISGR2_MDMA_ERROR (1 << 8)
-+#define DMISGR2_MDMA_CMPLT (1 << 7)
-+
-+/* Device Interrupt group Register (0x140) */
-+#define FOTG210_DIGR 0x140
-+#define DIGR_INT_G2 (1 << 2)
-+#define DIGR_INT_G1 (1 << 1)
-+#define DIGR_INT_G0 (1 << 0)
-+
-+/* Device Interrupt Source Group 0 Register (0x144) */
-+#define FOTG210_DISGR0 0x144
-+#define DISGR0_CX_COMABT_INT (1 << 5)
-+#define DISGR0_CX_COMFAIL_INT (1 << 4)
-+#define DISGR0_CX_COMEND_INT (1 << 3)
-+#define DISGR0_CX_OUT_INT (1 << 2)
-+#define DISGR0_CX_IN_INT (1 << 1)
-+#define DISGR0_CX_SETUP_INT (1 << 0)
-+
-+/* Device Interrupt Source Group 1 Register (0x148) */
-+#define FOTG210_DISGR1 0x148
-+#define DISGR1_OUT_INT(fifo) (1 << ((fifo) * 2))
-+#define DISGR1_SPK_INT(fifo) (1 << 1 << ((fifo) * 2))
-+#define DISGR1_IN_INT(fifo) (1 << 16 << (fifo))
-+
-+/* Device Interrupt Source Group 2 Register (0x14C) */
-+#define FOTG210_DISGR2 0x14C
-+#define DISGR2_DMA_ERROR (1 << 8)
-+#define DISGR2_DMA_CMPLT (1 << 7)
-+#define DISGR2_RX0BYTE_INT (1 << 6)
-+#define DISGR2_TX0BYTE_INT (1 << 5)
-+#define DISGR2_ISO_SEQ_ABORT_INT (1 << 4)
-+#define DISGR2_ISO_SEQ_ERR_INT (1 << 3)
-+#define DISGR2_RESM_INT (1 << 2)
-+#define DISGR2_SUSP_INT (1 << 1)
-+#define DISGR2_USBRST_INT (1 << 0)
-+
-+/* Device Receive Zero-Length Data Packet Register (0x150)*/
-+#define FOTG210_RX0BYTE 0x150
-+#define RX0BYTE_EP8 (1 << 7)
-+#define RX0BYTE_EP7 (1 << 6)
-+#define RX0BYTE_EP6 (1 << 5)
-+#define RX0BYTE_EP5 (1 << 4)
-+#define RX0BYTE_EP4 (1 << 3)
-+#define RX0BYTE_EP3 (1 << 2)
-+#define RX0BYTE_EP2 (1 << 1)
-+#define RX0BYTE_EP1 (1 << 0)
-+
-+/* Device Transfer Zero-Length Data Packet Register (0x154)*/
-+#define FOTG210_TX0BYTE 0x154
-+#define TX0BYTE_EP8 (1 << 7)
-+#define TX0BYTE_EP7 (1 << 6)
-+#define TX0BYTE_EP6 (1 << 5)
-+#define TX0BYTE_EP5 (1 << 4)
-+#define TX0BYTE_EP4 (1 << 3)
-+#define TX0BYTE_EP3 (1 << 2)
-+#define TX0BYTE_EP2 (1 << 1)
-+#define TX0BYTE_EP1 (1 << 0)
-+
-+/* Device IN Endpoint x MaxPacketSize Register(0x160+4*(x-1)) */
-+#define FOTG210_INEPMPSR(ep) (0x160 + 4 * ((ep) - 1))
-+#define INOUTEPMPSR_MPS(mps) ((mps) & 0x2FF)
-+#define INOUTEPMPSR_STL_EP (1 << 11)
-+#define INOUTEPMPSR_RESET_TSEQ (1 << 12)
-+
-+/* Device OUT Endpoint x MaxPacketSize Register(0x180+4*(x-1)) */
-+#define FOTG210_OUTEPMPSR(ep) (0x180 + 4 * ((ep) - 1))
-+
-+/* Device Endpoint 1~4 Map Register (0x1A0) */
-+#define FOTG210_EPMAP 0x1A0
-+#define EPMAP_FIFONO(ep, dir) \
-+ ((((ep) - 1) << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
-+#define EPMAP_FIFONOMSK(ep, dir) \
-+ ((3 << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
-+
-+/* Device FIFO Map Register (0x1A8) */
-+#define FOTG210_FIFOMAP 0x1A8
-+#define FIFOMAP_DIROUT(fifo) (0x0 << 4 << (fifo) * 8)
-+#define FIFOMAP_DIRIN(fifo) (0x1 << 4 << (fifo) * 8)
-+#define FIFOMAP_BIDIR(fifo) (0x2 << 4 << (fifo) * 8)
-+#define FIFOMAP_NA(fifo) (0x3 << 4 << (fifo) * 8)
-+#define FIFOMAP_EPNO(ep) ((ep) << ((ep) - 1) * 8)
-+#define FIFOMAP_EPNOMSK(ep) (0xF << ((ep) - 1) * 8)
-+
-+/* Device FIFO Confuguration Register (0x1AC) */
-+#define FOTG210_FIFOCF 0x1AC
-+#define FIFOCF_TYPE(type, fifo) ((type) << (fifo) * 8)
-+#define FIFOCF_BLK_SIN(fifo) (0x0 << (fifo) * 8 << 2)
-+#define FIFOCF_BLK_DUB(fifo) (0x1 << (fifo) * 8 << 2)
-+#define FIFOCF_BLK_TRI(fifo) (0x2 << (fifo) * 8 << 2)
-+#define FIFOCF_BLKSZ_512(fifo) (0x0 << (fifo) * 8 << 4)
-+#define FIFOCF_BLKSZ_1024(fifo) (0x1 << (fifo) * 8 << 4)
-+#define FIFOCF_FIFO_EN(fifo) (0x1 << (fifo) * 8 << 5)
-+
-+/* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */
-+#define FOTG210_FIBCR(fifo) (0x1B0 + (fifo) * 4)
-+#define FIBCR_BCFX 0x7FF
-+#define FIBCR_FFRST (1 << 12)
-+
-+/* Device DMA Target FIFO Number Register (0x1C0) */
-+#define FOTG210_DMATFNR 0x1C0
-+#define DMATFNR_ACC_CXF (1 << 4)
-+#define DMATFNR_ACC_F3 (1 << 3)
-+#define DMATFNR_ACC_F2 (1 << 2)
-+#define DMATFNR_ACC_F1 (1 << 1)
-+#define DMATFNR_ACC_F0 (1 << 0)
-+#define DMATFNR_ACC_FN(fifo) (1 << (fifo))
-+#define DMATFNR_DISDMA 0
-+
-+/* Device DMA Controller Parameter setting 1 Register (0x1C8) */
-+#define FOTG210_DMACPSR1 0x1C8
-+#define DMACPSR1_DMA_LEN(len) (((len) & 0xFFFF) << 8)
-+#define DMACPSR1_DMA_ABORT (1 << 3)
-+#define DMACPSR1_DMA_TYPE(dir_in) (((dir_in) ? 1 : 0) << 1)
-+#define DMACPSR1_DMA_START (1 << 0)
-+
-+/* Device DMA Controller Parameter setting 2 Register (0x1CC) */
-+#define FOTG210_DMACPSR2 0x1CC
-+
-+/* Device DMA Controller Parameter setting 3 Register (0x1CC) */
-+#define FOTG210_CXPORT 0x1D0
-+
-+struct fotg210_request {
-+ struct usb_request req;
-+ struct list_head queue;
-+};
-+
-+struct fotg210_ep {
-+ struct usb_ep ep;
-+ struct fotg210_udc *fotg210;
-+
-+ struct list_head queue;
-+ unsigned stall:1;
-+ unsigned wedged:1;
-+ unsigned use_dma:1;
-+
-+ unsigned char epnum;
-+ unsigned char type;
-+ unsigned char dir_in;
-+ unsigned int maxp;
-+ const struct usb_endpoint_descriptor *desc;
-+};
-+
-+struct fotg210_udc {
-+ spinlock_t lock; /* protect the struct */
-+ void __iomem *reg;
-+
-+ unsigned long irq_trigger;
-+
-+ struct usb_gadget gadget;
-+ struct usb_gadget_driver *driver;
-+
-+ struct fotg210_ep *ep[FOTG210_MAX_NUM_EP];
-+
-+ struct usb_request *ep0_req; /* for internal request */
-+ __le16 ep0_data;
-+ u8 ep0_dir; /* 0/0x80 out/in */
-+
-+ u8 reenum; /* if re-enumeration */
-+};
-+
-+#define gadget_to_fotg210(g) container_of((g), struct fotg210_udc, gadget)
---- a/drivers/usb/gadget/udc/fotg210.h
-+++ /dev/null
-@@ -1,249 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0+
--/*
-- * Faraday FOTG210 USB OTG controller
-- *
-- * Copyright (C) 2013 Faraday Technology Corporation
-- * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-- */
--
--#include <linux/kernel.h>
--
--#define FOTG210_MAX_NUM_EP 5 /* ep0...ep4 */
--#define FOTG210_MAX_FIFO_NUM 4 /* fifo0...fifo4 */
--
--/* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
--#define FOTG210_GMIR 0xC4
--#define GMIR_INT_POLARITY 0x8 /*Active High*/
--#define GMIR_MHC_INT 0x4
--#define GMIR_MOTG_INT 0x2
--#define GMIR_MDEV_INT 0x1
--
--/* Device Main Control Register(0x100) */
--#define FOTG210_DMCR 0x100
--#define DMCR_HS_EN (1 << 6)
--#define DMCR_CHIP_EN (1 << 5)
--#define DMCR_SFRST (1 << 4)
--#define DMCR_GOSUSP (1 << 3)
--#define DMCR_GLINT_EN (1 << 2)
--#define DMCR_HALF_SPEED (1 << 1)
--#define DMCR_CAP_RMWAKUP (1 << 0)
--
--/* Device Address Register(0x104) */
--#define FOTG210_DAR 0x104
--#define DAR_AFT_CONF (1 << 7)
--
--/* Device Test Register(0x108) */
--#define FOTG210_DTR 0x108
--#define DTR_TST_CLRFF (1 << 0)
--
--/* PHY Test Mode Selector register(0x114) */
--#define FOTG210_PHYTMSR 0x114
--#define PHYTMSR_TST_PKT (1 << 4)
--#define PHYTMSR_TST_SE0NAK (1 << 3)
--#define PHYTMSR_TST_KSTA (1 << 2)
--#define PHYTMSR_TST_JSTA (1 << 1)
--#define PHYTMSR_UNPLUG (1 << 0)
--
--/* Cx configuration and FIFO Empty Status register(0x120) */
--#define FOTG210_DCFESR 0x120
--#define DCFESR_FIFO_EMPTY(fifo) (1 << 8 << (fifo))
--#define DCFESR_CX_EMP (1 << 5)
--#define DCFESR_CX_CLR (1 << 3)
--#define DCFESR_CX_STL (1 << 2)
--#define DCFESR_TST_PKDONE (1 << 1)
--#define DCFESR_CX_DONE (1 << 0)
--
--/* Device IDLE Counter Register(0x124) */
--#define FOTG210_DICR 0x124
--
--/* Device Mask of Interrupt Group Register (0x130) */
--#define FOTG210_DMIGR 0x130
--#define DMIGR_MINT_G0 (1 << 0)
--
--/* Device Mask of Interrupt Source Group 0(0x134) */
--#define FOTG210_DMISGR0 0x134
--#define DMISGR0_MCX_COMEND (1 << 3)
--#define DMISGR0_MCX_OUT_INT (1 << 2)
--#define DMISGR0_MCX_IN_INT (1 << 1)
--#define DMISGR0_MCX_SETUP_INT (1 << 0)
--
--/* Device Mask of Interrupt Source Group 1 Register(0x138)*/
--#define FOTG210_DMISGR1 0x138
--#define DMISGR1_MF3_IN_INT (1 << 19)
--#define DMISGR1_MF2_IN_INT (1 << 18)
--#define DMISGR1_MF1_IN_INT (1 << 17)
--#define DMISGR1_MF0_IN_INT (1 << 16)
--#define DMISGR1_MF_IN_INT(fifo) (1 << (16 + (fifo)))
--#define DMISGR1_MF3_SPK_INT (1 << 7)
--#define DMISGR1_MF3_OUT_INT (1 << 6)
--#define DMISGR1_MF2_SPK_INT (1 << 5)
--#define DMISGR1_MF2_OUT_INT (1 << 4)
--#define DMISGR1_MF1_SPK_INT (1 << 3)
--#define DMISGR1_MF1_OUT_INT (1 << 2)
--#define DMISGR1_MF0_SPK_INT (1 << 1)
--#define DMISGR1_MF0_OUT_INT (1 << 0)
--#define DMISGR1_MF_OUTSPK_INT(fifo) (0x3 << (fifo) * 2)
--
--/* Device Mask of Interrupt Source Group 2 Register (0x13C) */
--#define FOTG210_DMISGR2 0x13C
--#define DMISGR2_MDMA_ERROR (1 << 8)
--#define DMISGR2_MDMA_CMPLT (1 << 7)
--
--/* Device Interrupt group Register (0x140) */
--#define FOTG210_DIGR 0x140
--#define DIGR_INT_G2 (1 << 2)
--#define DIGR_INT_G1 (1 << 1)
--#define DIGR_INT_G0 (1 << 0)
--
--/* Device Interrupt Source Group 0 Register (0x144) */
--#define FOTG210_DISGR0 0x144
--#define DISGR0_CX_COMABT_INT (1 << 5)
--#define DISGR0_CX_COMFAIL_INT (1 << 4)
--#define DISGR0_CX_COMEND_INT (1 << 3)
--#define DISGR0_CX_OUT_INT (1 << 2)
--#define DISGR0_CX_IN_INT (1 << 1)
--#define DISGR0_CX_SETUP_INT (1 << 0)
--
--/* Device Interrupt Source Group 1 Register (0x148) */
--#define FOTG210_DISGR1 0x148
--#define DISGR1_OUT_INT(fifo) (1 << ((fifo) * 2))
--#define DISGR1_SPK_INT(fifo) (1 << 1 << ((fifo) * 2))
--#define DISGR1_IN_INT(fifo) (1 << 16 << (fifo))
--
--/* Device Interrupt Source Group 2 Register (0x14C) */
--#define FOTG210_DISGR2 0x14C
--#define DISGR2_DMA_ERROR (1 << 8)
--#define DISGR2_DMA_CMPLT (1 << 7)
--#define DISGR2_RX0BYTE_INT (1 << 6)
--#define DISGR2_TX0BYTE_INT (1 << 5)
--#define DISGR2_ISO_SEQ_ABORT_INT (1 << 4)
--#define DISGR2_ISO_SEQ_ERR_INT (1 << 3)
--#define DISGR2_RESM_INT (1 << 2)
--#define DISGR2_SUSP_INT (1 << 1)
--#define DISGR2_USBRST_INT (1 << 0)
--
--/* Device Receive Zero-Length Data Packet Register (0x150)*/
--#define FOTG210_RX0BYTE 0x150
--#define RX0BYTE_EP8 (1 << 7)
--#define RX0BYTE_EP7 (1 << 6)
--#define RX0BYTE_EP6 (1 << 5)
--#define RX0BYTE_EP5 (1 << 4)
--#define RX0BYTE_EP4 (1 << 3)
--#define RX0BYTE_EP3 (1 << 2)
--#define RX0BYTE_EP2 (1 << 1)
--#define RX0BYTE_EP1 (1 << 0)
--
--/* Device Transfer Zero-Length Data Packet Register (0x154)*/
--#define FOTG210_TX0BYTE 0x154
--#define TX0BYTE_EP8 (1 << 7)
--#define TX0BYTE_EP7 (1 << 6)
--#define TX0BYTE_EP6 (1 << 5)
--#define TX0BYTE_EP5 (1 << 4)
--#define TX0BYTE_EP4 (1 << 3)
--#define TX0BYTE_EP3 (1 << 2)
--#define TX0BYTE_EP2 (1 << 1)
--#define TX0BYTE_EP1 (1 << 0)
--
--/* Device IN Endpoint x MaxPacketSize Register(0x160+4*(x-1)) */
--#define FOTG210_INEPMPSR(ep) (0x160 + 4 * ((ep) - 1))
--#define INOUTEPMPSR_MPS(mps) ((mps) & 0x2FF)
--#define INOUTEPMPSR_STL_EP (1 << 11)
--#define INOUTEPMPSR_RESET_TSEQ (1 << 12)
--
--/* Device OUT Endpoint x MaxPacketSize Register(0x180+4*(x-1)) */
--#define FOTG210_OUTEPMPSR(ep) (0x180 + 4 * ((ep) - 1))
--
--/* Device Endpoint 1~4 Map Register (0x1A0) */
--#define FOTG210_EPMAP 0x1A0
--#define EPMAP_FIFONO(ep, dir) \
-- ((((ep) - 1) << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
--#define EPMAP_FIFONOMSK(ep, dir) \
-- ((3 << ((ep) - 1) * 8) << ((dir) ? 0 : 4))
--
--/* Device FIFO Map Register (0x1A8) */
--#define FOTG210_FIFOMAP 0x1A8
--#define FIFOMAP_DIROUT(fifo) (0x0 << 4 << (fifo) * 8)
--#define FIFOMAP_DIRIN(fifo) (0x1 << 4 << (fifo) * 8)
--#define FIFOMAP_BIDIR(fifo) (0x2 << 4 << (fifo) * 8)
--#define FIFOMAP_NA(fifo) (0x3 << 4 << (fifo) * 8)
--#define FIFOMAP_EPNO(ep) ((ep) << ((ep) - 1) * 8)
--#define FIFOMAP_EPNOMSK(ep) (0xF << ((ep) - 1) * 8)
--
--/* Device FIFO Confuguration Register (0x1AC) */
--#define FOTG210_FIFOCF 0x1AC
--#define FIFOCF_TYPE(type, fifo) ((type) << (fifo) * 8)
--#define FIFOCF_BLK_SIN(fifo) (0x0 << (fifo) * 8 << 2)
--#define FIFOCF_BLK_DUB(fifo) (0x1 << (fifo) * 8 << 2)
--#define FIFOCF_BLK_TRI(fifo) (0x2 << (fifo) * 8 << 2)
--#define FIFOCF_BLKSZ_512(fifo) (0x0 << (fifo) * 8 << 4)
--#define FIFOCF_BLKSZ_1024(fifo) (0x1 << (fifo) * 8 << 4)
--#define FIFOCF_FIFO_EN(fifo) (0x1 << (fifo) * 8 << 5)
--
--/* Device FIFO n Instruction and Byte Count Register (0x1B0+4*n) */
--#define FOTG210_FIBCR(fifo) (0x1B0 + (fifo) * 4)
--#define FIBCR_BCFX 0x7FF
--#define FIBCR_FFRST (1 << 12)
--
--/* Device DMA Target FIFO Number Register (0x1C0) */
--#define FOTG210_DMATFNR 0x1C0
--#define DMATFNR_ACC_CXF (1 << 4)
--#define DMATFNR_ACC_F3 (1 << 3)
--#define DMATFNR_ACC_F2 (1 << 2)
--#define DMATFNR_ACC_F1 (1 << 1)
--#define DMATFNR_ACC_F0 (1 << 0)
--#define DMATFNR_ACC_FN(fifo) (1 << (fifo))
--#define DMATFNR_DISDMA 0
--
--/* Device DMA Controller Parameter setting 1 Register (0x1C8) */
--#define FOTG210_DMACPSR1 0x1C8
--#define DMACPSR1_DMA_LEN(len) (((len) & 0xFFFF) << 8)
--#define DMACPSR1_DMA_ABORT (1 << 3)
--#define DMACPSR1_DMA_TYPE(dir_in) (((dir_in) ? 1 : 0) << 1)
--#define DMACPSR1_DMA_START (1 << 0)
--
--/* Device DMA Controller Parameter setting 2 Register (0x1CC) */
--#define FOTG210_DMACPSR2 0x1CC
--
--/* Device DMA Controller Parameter setting 3 Register (0x1CC) */
--#define FOTG210_CXPORT 0x1D0
--
--struct fotg210_request {
-- struct usb_request req;
-- struct list_head queue;
--};
--
--struct fotg210_ep {
-- struct usb_ep ep;
-- struct fotg210_udc *fotg210;
--
-- struct list_head queue;
-- unsigned stall:1;
-- unsigned wedged:1;
-- unsigned use_dma:1;
--
-- unsigned char epnum;
-- unsigned char type;
-- unsigned char dir_in;
-- unsigned int maxp;
-- const struct usb_endpoint_descriptor *desc;
--};
--
--struct fotg210_udc {
-- spinlock_t lock; /* protect the struct */
-- void __iomem *reg;
--
-- unsigned long irq_trigger;
--
-- struct usb_gadget gadget;
-- struct usb_gadget_driver *driver;
--
-- struct fotg210_ep *ep[FOTG210_MAX_NUM_EP];
--
-- struct usb_request *ep0_req; /* for internal request */
-- __le16 ep0_data;
-- u8 ep0_dir; /* 0/0x80 out/in */
--
-- u8 reenum; /* if re-enumeration */
--};
--
--#define gadget_to_fotg210(g) container_of((g), struct fotg210_udc, gadget)
---- a/drivers/usb/host/fotg210.h
-+++ /dev/null
-@@ -1,688 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0 */
--#ifndef __LINUX_FOTG210_H
--#define __LINUX_FOTG210_H
--
--#include <linux/usb/ehci-dbgp.h>
--
--/* definitions used for the EHCI driver */
--
--/*
-- * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
-- * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
-- * the host controller implementation.
-- *
-- * To facilitate the strongest possible byte-order checking from "sparse"
-- * and so on, we use __leXX unless that's not practical.
-- */
--#define __hc32 __le32
--#define __hc16 __le16
--
--/* statistics can be kept for tuning/monitoring */
--struct fotg210_stats {
-- /* irq usage */
-- unsigned long normal;
-- unsigned long error;
-- unsigned long iaa;
-- unsigned long lost_iaa;
--
-- /* termination of urbs from core */
-- unsigned long complete;
-- unsigned long unlink;
--};
--
--/* fotg210_hcd->lock guards shared data against other CPUs:
-- * fotg210_hcd: async, unlink, periodic (and shadow), ...
-- * usb_host_endpoint: hcpriv
-- * fotg210_qh: qh_next, qtd_list
-- * fotg210_qtd: qtd_list
-- *
-- * Also, hold this lock when talking to HC registers or
-- * when updating hw_* fields in shared qh/qtd/... structures.
-- */
--
--#define FOTG210_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
--
--/*
-- * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
-- * controller may be doing DMA. Lower values mean there's no DMA.
-- */
--enum fotg210_rh_state {
-- FOTG210_RH_HALTED,
-- FOTG210_RH_SUSPENDED,
-- FOTG210_RH_RUNNING,
-- FOTG210_RH_STOPPING
--};
--
--/*
-- * Timer events, ordered by increasing delay length.
-- * Always update event_delays_ns[] and event_handlers[] (defined in
-- * ehci-timer.c) in parallel with this list.
-- */
--enum fotg210_hrtimer_event {
-- FOTG210_HRTIMER_POLL_ASS, /* Poll for async schedule off */
-- FOTG210_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
-- FOTG210_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
-- FOTG210_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
-- FOTG210_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
-- FOTG210_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
-- FOTG210_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
-- FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
-- FOTG210_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
-- FOTG210_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
-- FOTG210_HRTIMER_NUM_EVENTS /* Must come last */
--};
--#define FOTG210_HRTIMER_NO_EVENT 99
--
--struct fotg210_hcd { /* one per controller */
-- /* timing support */
-- enum fotg210_hrtimer_event next_hrtimer_event;
-- unsigned enabled_hrtimer_events;
-- ktime_t hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
-- struct hrtimer hrtimer;
--
-- int PSS_poll_count;
-- int ASS_poll_count;
-- int died_poll_count;
--
-- /* glue to PCI and HCD framework */
-- struct fotg210_caps __iomem *caps;
-- struct fotg210_regs __iomem *regs;
-- struct ehci_dbg_port __iomem *debug;
--
-- __u32 hcs_params; /* cached register copy */
-- spinlock_t lock;
-- enum fotg210_rh_state rh_state;
--
-- /* general schedule support */
-- bool scanning:1;
-- bool need_rescan:1;
-- bool intr_unlinking:1;
-- bool async_unlinking:1;
-- bool shutdown:1;
-- struct fotg210_qh *qh_scan_next;
--
-- /* async schedule support */
-- struct fotg210_qh *async;
-- struct fotg210_qh *dummy; /* For AMD quirk use */
-- struct fotg210_qh *async_unlink;
-- struct fotg210_qh *async_unlink_last;
-- struct fotg210_qh *async_iaa;
-- unsigned async_unlink_cycle;
-- unsigned async_count; /* async activity count */
--
-- /* periodic schedule support */
--#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
-- unsigned periodic_size;
-- __hc32 *periodic; /* hw periodic table */
-- dma_addr_t periodic_dma;
-- struct list_head intr_qh_list;
-- unsigned i_thresh; /* uframes HC might cache */
--
-- union fotg210_shadow *pshadow; /* mirror hw periodic table */
-- struct fotg210_qh *intr_unlink;
-- struct fotg210_qh *intr_unlink_last;
-- unsigned intr_unlink_cycle;
-- unsigned now_frame; /* frame from HC hardware */
-- unsigned next_frame; /* scan periodic, start here */
-- unsigned intr_count; /* intr activity count */
-- unsigned isoc_count; /* isoc activity count */
-- unsigned periodic_count; /* periodic activity count */
-- /* max periodic time per uframe */
-- unsigned uframe_periodic_max;
--
--
-- /* list of itds completed while now_frame was still active */
-- struct list_head cached_itd_list;
-- struct fotg210_itd *last_itd_to_free;
--
-- /* per root hub port */
-- unsigned long reset_done[FOTG210_MAX_ROOT_PORTS];
--
-- /* bit vectors (one bit per port)
-- * which ports were already suspended at the start of a bus suspend
-- */
-- unsigned long bus_suspended;
--
-- /* which ports are edicated to the companion controller */
-- unsigned long companion_ports;
--
-- /* which ports are owned by the companion during a bus suspend */
-- unsigned long owned_ports;
--
-- /* which ports have the change-suspend feature turned on */
-- unsigned long port_c_suspend;
--
-- /* which ports are suspended */
-- unsigned long suspended_ports;
--
-- /* which ports have started to resume */
-- unsigned long resuming_ports;
--
-- /* per-HC memory pools (could be per-bus, but ...) */
-- struct dma_pool *qh_pool; /* qh per active urb */
-- struct dma_pool *qtd_pool; /* one or more per qh */
-- struct dma_pool *itd_pool; /* itd per iso urb */
--
-- unsigned random_frame;
-- unsigned long next_statechange;
-- ktime_t last_periodic_enable;
-- u32 command;
--
-- /* SILICON QUIRKS */
-- unsigned need_io_watchdog:1;
-- unsigned fs_i_thresh:1; /* Intel iso scheduling */
--
-- u8 sbrn; /* packed release number */
--
-- /* irq statistics */
--#ifdef FOTG210_STATS
-- struct fotg210_stats stats;
--# define INCR(x) ((x)++)
--#else
--# define INCR(x) do {} while (0)
--#endif
--
-- /* silicon clock */
-- struct clk *pclk;
--};
--
--/* convert between an HCD pointer and the corresponding FOTG210_HCD */
--static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
--{
-- return (struct fotg210_hcd *)(hcd->hcd_priv);
--}
--static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
--{
-- return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
--}
--
--/*-------------------------------------------------------------------------*/
--
--/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
--
--/* Section 2.2 Host Controller Capability Registers */
--struct fotg210_caps {
-- /* these fields are specified as 8 and 16 bit registers,
-- * but some hosts can't perform 8 or 16 bit PCI accesses.
-- * some hosts treat caplength and hciversion as parts of a 32-bit
-- * register, others treat them as two separate registers, this
-- * affects the memory map for big endian controllers.
-- */
-- u32 hc_capbase;
--#define HC_LENGTH(fotg210, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
-- (fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
--#define HC_VERSION(fotg210, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
-- (fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
-- u32 hcs_params; /* HCSPARAMS - offset 0x4 */
--#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
--
-- u32 hcc_params; /* HCCPARAMS - offset 0x8 */
--#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
--#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
-- u8 portroute[8]; /* nibbles for routing - offset 0xC */
--};
--
--
--/* Section 2.3 Host Controller Operational Registers */
--struct fotg210_regs {
--
-- /* USBCMD: offset 0x00 */
-- u32 command;
--
--/* EHCI 1.1 addendum */
--/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
--#define CMD_PARK (1<<11) /* enable "park" on async qh */
--#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
--#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
--#define CMD_ASE (1<<5) /* async schedule enable */
--#define CMD_PSE (1<<4) /* periodic schedule enable */
--/* 3:2 is periodic frame list size */
--#define CMD_RESET (1<<1) /* reset HC not bus */
--#define CMD_RUN (1<<0) /* start/stop HC */
--
-- /* USBSTS: offset 0x04 */
-- u32 status;
--#define STS_ASS (1<<15) /* Async Schedule Status */
--#define STS_PSS (1<<14) /* Periodic Schedule Status */
--#define STS_RECL (1<<13) /* Reclamation */
--#define STS_HALT (1<<12) /* Not running (any reason) */
--/* some bits reserved */
-- /* these STS_* flags are also intr_enable bits (USBINTR) */
--#define STS_IAA (1<<5) /* Interrupted on async advance */
--#define STS_FATAL (1<<4) /* such as some PCI access errors */
--#define STS_FLR (1<<3) /* frame list rolled over */
--#define STS_PCD (1<<2) /* port change detect */
--#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
--#define STS_INT (1<<0) /* "normal" completion (short, ...) */
--
-- /* USBINTR: offset 0x08 */
-- u32 intr_enable;
--
-- /* FRINDEX: offset 0x0C */
-- u32 frame_index; /* current microframe number */
-- /* CTRLDSSEGMENT: offset 0x10 */
-- u32 segment; /* address bits 63:32 if needed */
-- /* PERIODICLISTBASE: offset 0x14 */
-- u32 frame_list; /* points to periodic list */
-- /* ASYNCLISTADDR: offset 0x18 */
-- u32 async_next; /* address of next async queue head */
--
-- u32 reserved1;
-- /* PORTSC: offset 0x20 */
-- u32 port_status;
--/* 31:23 reserved */
--#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
--#define PORT_RESET (1<<8) /* reset port */
--#define PORT_SUSPEND (1<<7) /* suspend port */
--#define PORT_RESUME (1<<6) /* resume it */
--#define PORT_PEC (1<<3) /* port enable change */
--#define PORT_PE (1<<2) /* port enable */
--#define PORT_CSC (1<<1) /* connect status change */
--#define PORT_CONNECT (1<<0) /* device connected */
--#define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
-- u32 reserved2[19];
--
-- /* OTGCSR: offet 0x70 */
-- u32 otgcsr;
--#define OTGCSR_HOST_SPD_TYP (3 << 22)
--#define OTGCSR_A_BUS_DROP (1 << 5)
--#define OTGCSR_A_BUS_REQ (1 << 4)
--
-- /* OTGISR: offset 0x74 */
-- u32 otgisr;
--#define OTGISR_OVC (1 << 10)
--
-- u32 reserved3[15];
--
-- /* GMIR: offset 0xB4 */
-- u32 gmir;
--#define GMIR_INT_POLARITY (1 << 3) /*Active High*/
--#define GMIR_MHC_INT (1 << 2)
--#define GMIR_MOTG_INT (1 << 1)
--#define GMIR_MDEV_INT (1 << 0)
--};
--
--/*-------------------------------------------------------------------------*/
--
--#define QTD_NEXT(fotg210, dma) cpu_to_hc32(fotg210, (u32)dma)
--
--/*
-- * EHCI Specification 0.95 Section 3.5
-- * QTD: describe data transfer components (buffer, direction, ...)
-- * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
-- *
-- * These are associated only with "QH" (Queue Head) structures,
-- * used with control, bulk, and interrupt transfers.
-- */
--struct fotg210_qtd {
-- /* first part defined by EHCI spec */
-- __hc32 hw_next; /* see EHCI 3.5.1 */
-- __hc32 hw_alt_next; /* see EHCI 3.5.2 */
-- __hc32 hw_token; /* see EHCI 3.5.3 */
--#define QTD_TOGGLE (1 << 31) /* data toggle */
--#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
--#define QTD_IOC (1 << 15) /* interrupt on complete */
--#define QTD_CERR(tok) (((tok)>>10) & 0x3)
--#define QTD_PID(tok) (((tok)>>8) & 0x3)
--#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
--#define QTD_STS_HALT (1 << 6) /* halted on error */
--#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
--#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
--#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
--#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
--#define QTD_STS_STS (1 << 1) /* split transaction state */
--#define QTD_STS_PING (1 << 0) /* issue PING? */
--
--#define ACTIVE_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
--#define HALT_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_HALT)
--#define STATUS_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_STS)
--
-- __hc32 hw_buf[5]; /* see EHCI 3.5.4 */
-- __hc32 hw_buf_hi[5]; /* Appendix B */
--
-- /* the rest is HCD-private */
-- dma_addr_t qtd_dma; /* qtd address */
-- struct list_head qtd_list; /* sw qtd list */
-- struct urb *urb; /* qtd's urb */
-- size_t length; /* length of buffer */
--} __aligned(32);
--
--/* mask NakCnt+T in qh->hw_alt_next */
--#define QTD_MASK(fotg210) cpu_to_hc32(fotg210, ~0x1f)
--
--#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
--
--/*-------------------------------------------------------------------------*/
--
--/* type tag from {qh,itd,fstn}->hw_next */
--#define Q_NEXT_TYPE(fotg210, dma) ((dma) & cpu_to_hc32(fotg210, 3 << 1))
--
--/*
-- * Now the following defines are not converted using the
-- * cpu_to_le32() macro anymore, since we have to support
-- * "dynamic" switching between be and le support, so that the driver
-- * can be used on one system with SoC EHCI controller using big-endian
-- * descriptors as well as a normal little-endian PCI EHCI controller.
-- */
--/* values for that type tag */
--#define Q_TYPE_ITD (0 << 1)
--#define Q_TYPE_QH (1 << 1)
--#define Q_TYPE_SITD (2 << 1)
--#define Q_TYPE_FSTN (3 << 1)
--
--/* next async queue entry, or pointer to interrupt/periodic QH */
--#define QH_NEXT(fotg210, dma) \
-- (cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
--
--/* for periodic/async schedules and qtd lists, mark end of list */
--#define FOTG210_LIST_END(fotg210) \
-- cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
--
--/*
-- * Entries in periodic shadow table are pointers to one of four kinds
-- * of data structure. That's dictated by the hardware; a type tag is
-- * encoded in the low bits of the hardware's periodic schedule. Use
-- * Q_NEXT_TYPE to get the tag.
-- *
-- * For entries in the async schedule, the type tag always says "qh".
-- */
--union fotg210_shadow {
-- struct fotg210_qh *qh; /* Q_TYPE_QH */
-- struct fotg210_itd *itd; /* Q_TYPE_ITD */
-- struct fotg210_fstn *fstn; /* Q_TYPE_FSTN */
-- __hc32 *hw_next; /* (all types) */
-- void *ptr;
--};
--
--/*-------------------------------------------------------------------------*/
--
--/*
-- * EHCI Specification 0.95 Section 3.6
-- * QH: describes control/bulk/interrupt endpoints
-- * See Fig 3-7 "Queue Head Structure Layout".
-- *
-- * These appear in both the async and (for interrupt) periodic schedules.
-- */
--
--/* first part defined by EHCI spec */
--struct fotg210_qh_hw {
-- __hc32 hw_next; /* see EHCI 3.6.1 */
-- __hc32 hw_info1; /* see EHCI 3.6.2 */
--#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
--#define QH_HEAD (1 << 15) /* Head of async reclamation list */
--#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
--#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
--#define QH_LOW_SPEED (1 << 12)
--#define QH_FULL_SPEED (0 << 12)
--#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
-- __hc32 hw_info2; /* see EHCI 3.6.2 */
--#define QH_SMASK 0x000000ff
--#define QH_CMASK 0x0000ff00
--#define QH_HUBADDR 0x007f0000
--#define QH_HUBPORT 0x3f800000
--#define QH_MULT 0xc0000000
-- __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
--
-- /* qtd overlay (hardware parts of a struct fotg210_qtd) */
-- __hc32 hw_qtd_next;
-- __hc32 hw_alt_next;
-- __hc32 hw_token;
-- __hc32 hw_buf[5];
-- __hc32 hw_buf_hi[5];
--} __aligned(32);
--
--struct fotg210_qh {
-- struct fotg210_qh_hw *hw; /* Must come first */
-- /* the rest is HCD-private */
-- dma_addr_t qh_dma; /* address of qh */
-- union fotg210_shadow qh_next; /* ptr to qh; or periodic */
-- struct list_head qtd_list; /* sw qtd list */
-- struct list_head intr_node; /* list of intr QHs */
-- struct fotg210_qtd *dummy;
-- struct fotg210_qh *unlink_next; /* next on unlink list */
--
-- unsigned unlink_cycle;
--
-- u8 needs_rescan; /* Dequeue during giveback */
-- u8 qh_state;
--#define QH_STATE_LINKED 1 /* HC sees this */
--#define QH_STATE_UNLINK 2 /* HC may still see this */
--#define QH_STATE_IDLE 3 /* HC doesn't see this */
--#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
--#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
--
-- u8 xacterrs; /* XactErr retry counter */
--#define QH_XACTERR_MAX 32 /* XactErr retry limit */
--
-- /* periodic schedule info */
-- u8 usecs; /* intr bandwidth */
-- u8 gap_uf; /* uframes split/csplit gap */
-- u8 c_usecs; /* ... split completion bw */
-- u16 tt_usecs; /* tt downstream bandwidth */
-- unsigned short period; /* polling interval */
-- unsigned short start; /* where polling starts */
--#define NO_FRAME ((unsigned short)~0) /* pick new start */
--
-- struct usb_device *dev; /* access to TT */
-- unsigned is_out:1; /* bulk or intr OUT */
-- unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
--};
--
--/*-------------------------------------------------------------------------*/
--
--/* description of one iso transaction (up to 3 KB data if highspeed) */
--struct fotg210_iso_packet {
-- /* These will be copied to iTD when scheduling */
-- u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
-- __hc32 transaction; /* itd->hw_transaction[i] |= */
-- u8 cross; /* buf crosses pages */
-- /* for full speed OUT splits */
-- u32 buf1;
--};
--
--/* temporary schedule data for packets from iso urbs (both speeds)
-- * each packet is one logical usb transaction to the device (not TT),
-- * beginning at stream->next_uframe
-- */
--struct fotg210_iso_sched {
-- struct list_head td_list;
-- unsigned span;
-- struct fotg210_iso_packet packet[];
--};
--
--/*
-- * fotg210_iso_stream - groups all (s)itds for this endpoint.
-- * acts like a qh would, if EHCI had them for ISO.
-- */
--struct fotg210_iso_stream {
-- /* first field matches fotg210_hq, but is NULL */
-- struct fotg210_qh_hw *hw;
--
-- u8 bEndpointAddress;
-- u8 highspeed;
-- struct list_head td_list; /* queued itds */
-- struct list_head free_list; /* list of unused itds */
-- struct usb_device *udev;
-- struct usb_host_endpoint *ep;
--
-- /* output of (re)scheduling */
-- int next_uframe;
-- __hc32 splits;
--
-- /* the rest is derived from the endpoint descriptor,
-- * trusting urb->interval == f(epdesc->bInterval) and
-- * including the extra info for hw_bufp[0..2]
-- */
-- u8 usecs, c_usecs;
-- u16 interval;
-- u16 tt_usecs;
-- u16 maxp;
-- u16 raw_mask;
-- unsigned bandwidth;
--
-- /* This is used to initialize iTD's hw_bufp fields */
-- __hc32 buf0;
-- __hc32 buf1;
-- __hc32 buf2;
--
-- /* this is used to initialize sITD's tt info */
-- __hc32 address;
--};
--
--/*-------------------------------------------------------------------------*/
--
--/*
-- * EHCI Specification 0.95 Section 3.3
-- * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
-- *
-- * Schedule records for high speed iso xfers
-- */
--struct fotg210_itd {
-- /* first part defined by EHCI spec */
-- __hc32 hw_next; /* see EHCI 3.3.1 */
-- __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */
--#define FOTG210_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
--#define FOTG210_ISOC_BUF_ERR (1<<30) /* Data buffer error */
--#define FOTG210_ISOC_BABBLE (1<<29) /* babble detected */
--#define FOTG210_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
--#define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
--#define FOTG210_ITD_IOC (1 << 15) /* interrupt on complete */
--
--#define ITD_ACTIVE(fotg210) cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
--
-- __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
-- __hc32 hw_bufp_hi[7]; /* Appendix B */
--
-- /* the rest is HCD-private */
-- dma_addr_t itd_dma; /* for this itd */
-- union fotg210_shadow itd_next; /* ptr to periodic q entry */
--
-- struct urb *urb;
-- struct fotg210_iso_stream *stream; /* endpoint's queue */
-- struct list_head itd_list; /* list of stream's itds */
--
-- /* any/all hw_transactions here may be used by that urb */
-- unsigned frame; /* where scheduled */
-- unsigned pg;
-- unsigned index[8]; /* in urb->iso_frame_desc */
--} __aligned(32);
--
--/*-------------------------------------------------------------------------*/
--
--/*
-- * EHCI Specification 0.96 Section 3.7
-- * Periodic Frame Span Traversal Node (FSTN)
-- *
-- * Manages split interrupt transactions (using TT) that span frame boundaries
-- * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
-- * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
-- * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
-- */
--struct fotg210_fstn {
-- __hc32 hw_next; /* any periodic q entry */
-- __hc32 hw_prev; /* qh or FOTG210_LIST_END */
--
-- /* the rest is HCD-private */
-- dma_addr_t fstn_dma;
-- union fotg210_shadow fstn_next; /* ptr to periodic q entry */
--} __aligned(32);
--
--/*-------------------------------------------------------------------------*/
--
--/* Prepare the PORTSC wakeup flags during controller suspend/resume */
--
--#define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
-- fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup)
--
--#define fotg210_prepare_ports_for_controller_resume(fotg210) \
-- fotg210_adjust_port_wakeup_flags(fotg210, false, false)
--
--/*-------------------------------------------------------------------------*/
--
--/*
-- * Some EHCI controllers have a Transaction Translator built into the
-- * root hub. This is a non-standard feature. Each controller will need
-- * to add code to the following inline functions, and call them as
-- * needed (mostly in root hub code).
-- */
--
--static inline unsigned int
--fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
--{
-- return (readl(&fotg210->regs->otgcsr)
-- & OTGCSR_HOST_SPD_TYP) >> 22;
--}
--
--/* Returns the speed of a device attached to a port on the root hub. */
--static inline unsigned int
--fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
--{
-- switch (fotg210_get_speed(fotg210, portsc)) {
-- case 0:
-- return 0;
-- case 1:
-- return USB_PORT_STAT_LOW_SPEED;
-- case 2:
-- default:
-- return USB_PORT_STAT_HIGH_SPEED;
-- }
--}
--
--/*-------------------------------------------------------------------------*/
--
--#define fotg210_has_fsl_portno_bug(e) (0)
--
--/*
-- * While most USB host controllers implement their registers in
-- * little-endian format, a minority (celleb companion chip) implement
-- * them in big endian format.
-- *
-- * This attempts to support either format at compile time without a
-- * runtime penalty, or both formats with the additional overhead
-- * of checking a flag bit.
-- *
-- */
--
--#define fotg210_big_endian_mmio(e) 0
--#define fotg210_big_endian_capbase(e) 0
--
--static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
-- __u32 __iomem *regs)
--{
-- return readl(regs);
--}
--
--static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
-- const unsigned int val, __u32 __iomem *regs)
--{
-- writel(val, regs);
--}
--
--/* cpu to fotg210 */
--static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
--{
-- return cpu_to_le32(x);
--}
--
--/* fotg210 to cpu */
--static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
--{
-- return le32_to_cpu(x);
--}
--
--static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
-- const __hc32 *x)
--{
-- return le32_to_cpup(x);
--}
--
--/*-------------------------------------------------------------------------*/
--
--static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
--{
-- return fotg210_readl(fotg210, &fotg210->regs->frame_index);
--}
--
--/*-------------------------------------------------------------------------*/
--
--#endif /* __LINUX_FOTG210_H */
+++ /dev/null
-From 0dbc77a99267a5efef0603a4b49ac02ece6a3f23 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 23 Oct 2022 16:47:07 +0200
-Subject: [PATCH 03/29] usb: fotg210: Compile into one module
-
-It is since ages perfectly possible to compile both of these
-modules into the same kernel, which makes no sense since it
-is one piece of hardware.
-
-Compile one module named "fotg210.ko" for both HCD and UDC
-drivers by collecting the init calls into a fotg210-core.c
-file and start to centralize things handling one and the same
-piece of hardware.
-
-Stub out the initcalls if one or the other part of the driver
-was not selected.
-
-Tested by compiling one or the other or both of the drivers
-into the kernel and as modules.
-
-Cc: Fabian Vogt <fabian@ritter-vogt.de>
-Cc: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-Cc: Felipe Balbi <balbi@kernel.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221023144708.3596563-2-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/Kconfig
-+++ b/drivers/usb/fotg210/Kconfig
-@@ -12,7 +12,7 @@ config USB_FOTG210
- if USB_FOTG210
-
- config USB_FOTG210_HCD
-- tristate "Faraday FOTG210 USB Host Controller support"
-+ bool "Faraday FOTG210 USB Host Controller support"
- depends on USB
- help
- Faraday FOTG210 is an OTG controller which can be configured as
-@@ -24,7 +24,7 @@ config USB_FOTG210_HCD
-
- config USB_FOTG210_UDC
- depends on USB_GADGET
-- tristate "Faraday FOTG210 USB Peripheral Controller support"
-+ bool "Faraday FOTG210 USB Peripheral Controller support"
- help
- Faraday USB2.0 OTG controller which can be configured as
- high speed or full speed USB device. This driver suppports
---- a/drivers/usb/fotg210/Makefile
-+++ b/drivers/usb/fotg210/Makefile
-@@ -1,3 +1,10 @@
- # SPDX-License-Identifier: GPL-2.0
--obj-$(CONFIG_USB_FOTG210_HCD) += fotg210-hcd.o
--obj-$(CONFIG_USB_FOTG210_UDC) += fotg210-udc.o
-+
-+# This setup links the different object files into one single
-+# module so we don't have to EXPORT() a lot of internal symbols
-+# or create unnecessary submodules.
-+fotg210-objs-y += fotg210-core.o
-+fotg210-objs-$(CONFIG_USB_FOTG210_HCD) += fotg210-hcd.o
-+fotg210-objs-$(CONFIG_USB_FOTG210_UDC) += fotg210-udc.o
-+fotg210-objs := $(fotg210-objs-y)
-+obj-$(CONFIG_USB_FOTG210) += fotg210.o
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -0,0 +1,79 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Central probing code for the FOTG210 dual role driver
-+ * We register one driver for the hardware and then we decide
-+ * whether to proceed with probing the host or the peripheral
-+ * driver.
-+ */
-+#include <linux/device.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/usb.h>
-+
-+#include "fotg210.h"
-+
-+static int fotg210_probe(struct platform_device *pdev)
-+{
-+ int ret;
-+
-+ if (IS_ENABLED(CONFIG_USB_FOTG210_HCD)) {
-+ ret = fotg210_hcd_probe(pdev);
-+ if (ret)
-+ return ret;
-+ }
-+ if (IS_ENABLED(CONFIG_USB_FOTG210_UDC))
-+ ret = fotg210_udc_probe(pdev);
-+
-+ return ret;
-+}
-+
-+static int fotg210_remove(struct platform_device *pdev)
-+{
-+ if (IS_ENABLED(CONFIG_USB_FOTG210_HCD))
-+ fotg210_hcd_remove(pdev);
-+ if (IS_ENABLED(CONFIG_USB_FOTG210_UDC))
-+ fotg210_udc_remove(pdev);
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_OF
-+static const struct of_device_id fotg210_of_match[] = {
-+ { .compatible = "faraday,fotg210" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, fotg210_of_match);
-+#endif
-+
-+static struct platform_driver fotg210_driver = {
-+ .driver = {
-+ .name = "fotg210",
-+ .of_match_table = of_match_ptr(fotg210_of_match),
-+ },
-+ .probe = fotg210_probe,
-+ .remove = fotg210_remove,
-+};
-+
-+static int __init fotg210_init(void)
-+{
-+ if (usb_disabled())
-+ return -ENODEV;
-+
-+ if (IS_ENABLED(CONFIG_USB_FOTG210_HCD))
-+ fotg210_hcd_init();
-+ return platform_driver_register(&fotg210_driver);
-+}
-+module_init(fotg210_init);
-+
-+static void __exit fotg210_cleanup(void)
-+{
-+ platform_driver_unregister(&fotg210_driver);
-+ if (IS_ENABLED(CONFIG_USB_FOTG210_HCD))
-+ fotg210_hcd_cleanup();
-+}
-+module_exit(fotg210_cleanup);
-+
-+MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang");
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("FOTG210 Dual Role Controller Driver");
---- a/drivers/usb/fotg210/fotg210-hcd.c
-+++ b/drivers/usb/fotg210/fotg210-hcd.c
-@@ -39,8 +39,8 @@
- #include <asm/irq.h>
- #include <asm/unaligned.h>
-
--#define DRIVER_AUTHOR "Yuan-Hsin Chen"
--#define DRIVER_DESC "FOTG210 Host Controller (EHCI) Driver"
-+#include "fotg210.h"
-+
- static const char hcd_name[] = "fotg210_hcd";
-
- #undef FOTG210_URB_TRACE
-@@ -5490,9 +5490,6 @@ static int fotg210_get_frame(struct usb_
- * functions and in order to facilitate role switching we cannot
- * give the fotg210 driver exclusive access to those.
- */
--MODULE_DESCRIPTION(DRIVER_DESC);
--MODULE_AUTHOR(DRIVER_AUTHOR);
--MODULE_LICENSE("GPL");
-
- static const struct hc_driver fotg210_fotg210_hc_driver = {
- .description = hcd_name,
-@@ -5560,7 +5557,7 @@ static void fotg210_init(struct fotg210_
- * then invokes the start() method for the HCD associated with it
- * through the hotplug entry's driver_data.
- */
--static int fotg210_hcd_probe(struct platform_device *pdev)
-+int fotg210_hcd_probe(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
- struct usb_hcd *hcd;
-@@ -5652,7 +5649,7 @@ fail_create_hcd:
- * @dev: USB Host Controller being removed
- *
- */
--static int fotg210_hcd_remove(struct platform_device *pdev)
-+int fotg210_hcd_remove(struct platform_device *pdev)
- {
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
-@@ -5668,27 +5665,8 @@ static int fotg210_hcd_remove(struct pla
- return 0;
- }
-
--#ifdef CONFIG_OF
--static const struct of_device_id fotg210_of_match[] = {
-- { .compatible = "faraday,fotg210" },
-- {},
--};
--MODULE_DEVICE_TABLE(of, fotg210_of_match);
--#endif
--
--static struct platform_driver fotg210_hcd_driver = {
-- .driver = {
-- .name = "fotg210-hcd",
-- .of_match_table = of_match_ptr(fotg210_of_match),
-- },
-- .probe = fotg210_hcd_probe,
-- .remove = fotg210_hcd_remove,
--};
--
--static int __init fotg210_hcd_init(void)
-+int __init fotg210_hcd_init(void)
- {
-- int retval = 0;
--
- if (usb_disabled())
- return -ENODEV;
-
-@@ -5704,24 +5682,11 @@ static int __init fotg210_hcd_init(void)
-
- fotg210_debug_root = debugfs_create_dir("fotg210", usb_debug_root);
-
-- retval = platform_driver_register(&fotg210_hcd_driver);
-- if (retval < 0)
-- goto clean;
-- return retval;
--
--clean:
-- debugfs_remove(fotg210_debug_root);
-- fotg210_debug_root = NULL;
--
-- clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
-- return retval;
-+ return 0;
- }
--module_init(fotg210_hcd_init);
-
--static void __exit fotg210_hcd_cleanup(void)
-+void __exit fotg210_hcd_cleanup(void)
- {
-- platform_driver_unregister(&fotg210_hcd_driver);
- debugfs_remove(fotg210_debug_root);
- clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
- }
--module_exit(fotg210_hcd_cleanup);
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -16,6 +16,7 @@
- #include <linux/usb/ch9.h>
- #include <linux/usb/gadget.h>
-
-+#include "fotg210.h"
- #include "fotg210-udc.h"
-
- #define DRIVER_DESC "FOTG210 USB Device Controller Driver"
-@@ -1081,7 +1082,7 @@ static const struct usb_gadget_ops fotg2
- .udc_stop = fotg210_udc_stop,
- };
-
--static int fotg210_udc_remove(struct platform_device *pdev)
-+int fotg210_udc_remove(struct platform_device *pdev)
- {
- struct fotg210_udc *fotg210 = platform_get_drvdata(pdev);
- int i;
-@@ -1098,7 +1099,7 @@ static int fotg210_udc_remove(struct pla
- return 0;
- }
-
--static int fotg210_udc_probe(struct platform_device *pdev)
-+int fotg210_udc_probe(struct platform_device *pdev)
- {
- struct resource *res, *ires;
- struct fotg210_udc *fotg210 = NULL;
-@@ -1223,17 +1224,3 @@ err_alloc:
- err:
- return ret;
- }
--
--static struct platform_driver fotg210_driver = {
-- .driver = {
-- .name = udc_name,
-- },
-- .probe = fotg210_udc_probe,
-- .remove = fotg210_udc_remove,
--};
--
--module_platform_driver(fotg210_driver);
--
--MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
--MODULE_LICENSE("GPL");
--MODULE_DESCRIPTION(DRIVER_DESC);
---- /dev/null
-+++ b/drivers/usb/fotg210/fotg210.h
-@@ -0,0 +1,42 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+#ifndef __FOTG210_H
-+#define __FOTG210_H
-+
-+#ifdef CONFIG_USB_FOTG210_HCD
-+int fotg210_hcd_probe(struct platform_device *pdev);
-+int fotg210_hcd_remove(struct platform_device *pdev);
-+int fotg210_hcd_init(void);
-+void fotg210_hcd_cleanup(void);
-+#else
-+static inline int fotg210_hcd_probe(struct platform_device *pdev)
-+{
-+ return 0;
-+}
-+static inline int fotg210_hcd_remove(struct platform_device *pdev)
-+{
-+ return 0;
-+}
-+static inline int fotg210_hcd_init(void)
-+{
-+ return 0;
-+}
-+static inline void fotg210_hcd_cleanup(void)
-+{
-+}
-+#endif
-+
-+#ifdef CONFIG_USB_FOTG210_UDC
-+int fotg210_udc_probe(struct platform_device *pdev);
-+int fotg210_udc_remove(struct platform_device *pdev);
-+#else
-+static inline int fotg210_udc_probe(struct platform_device *pdev)
-+{
-+ return 0;
-+}
-+static inline int fotg210_udc_remove(struct platform_device *pdev)
-+{
-+ return 0;
-+}
-+#endif
-+
-+#endif /* __FOTG210_H */
+++ /dev/null
-From 7c0b661926097e935f2711857596fc2277b2304a Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 23 Oct 2022 16:47:08 +0200
-Subject: [PATCH 04/29] usb: fotg210: Select subdriver by mode
-
-Check which mode the hardware is in, and selecte the peripheral
-driver if the hardware is in explicit peripheral mode, otherwise
-select host mode.
-
-This should solve the immediate problem that both subdrivers
-can get probed.
-
-Cc: Fabian Vogt <fabian@ritter-vogt.de>
-Cc: Yuan-Hsin Chen <yhchen@faraday-tech.com>
-Cc: Felipe Balbi <balbi@kernel.org>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221023144708.3596563-3-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -10,30 +10,37 @@
- #include <linux/of.h>
- #include <linux/platform_device.h>
- #include <linux/usb.h>
-+#include <linux/usb/otg.h>
-
- #include "fotg210.h"
-
- static int fotg210_probe(struct platform_device *pdev)
- {
-+ struct device *dev = &pdev->dev;
-+ enum usb_dr_mode mode;
- int ret;
-
-- if (IS_ENABLED(CONFIG_USB_FOTG210_HCD)) {
-- ret = fotg210_hcd_probe(pdev);
-- if (ret)
-- return ret;
-- }
-- if (IS_ENABLED(CONFIG_USB_FOTG210_UDC))
-+ mode = usb_get_dr_mode(dev);
-+
-+ if (mode == USB_DR_MODE_PERIPHERAL)
- ret = fotg210_udc_probe(pdev);
-+ else
-+ ret = fotg210_hcd_probe(pdev);
-
- return ret;
- }
-
- static int fotg210_remove(struct platform_device *pdev)
- {
-- if (IS_ENABLED(CONFIG_USB_FOTG210_HCD))
-- fotg210_hcd_remove(pdev);
-- if (IS_ENABLED(CONFIG_USB_FOTG210_UDC))
-+ struct device *dev = &pdev->dev;
-+ enum usb_dr_mode mode;
-+
-+ mode = usb_get_dr_mode(dev);
-+
-+ if (mode == USB_DR_MODE_PERIPHERAL)
- fotg210_udc_remove(pdev);
-+ else
-+ fotg210_hcd_remove(pdev);
-
- return 0;
- }
+++ /dev/null
-From f7f6c8aca91093e2f886ec97910b1a7d9a69bf9b Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 9 Nov 2022 21:05:54 +0100
-Subject: [PATCH 05/29] usb: fotg2: add Gemini-specific handling
-
-The Cortina Systems Gemini has bolted on a PHY inside the
-silicon that can be handled by six bits in a MISC register in
-the system controller.
-
-If we are running on Gemini, look up a syscon regmap through
-a phandle and enable VBUS and optionally the Mini-B connector.
-
-If the device is flagged as "wakeup-source" using the standard
-DT bindings, we also enable this in the global controller for
-respective port.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221109200554.1957185-1-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/Kconfig
-+++ b/drivers/usb/fotg210/Kconfig
-@@ -5,6 +5,7 @@ config USB_FOTG210
- depends on USB || USB_GADGET
- depends on HAS_DMA && HAS_IOMEM
- default ARCH_GEMINI
-+ select MFD_SYSCON
- help
- Faraday FOTG210 is a dual-mode USB controller that can act
- in both host controller and peripheral controller mode.
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -5,15 +5,86 @@
- * whether to proceed with probing the host or the peripheral
- * driver.
- */
-+#include <linux/bitops.h>
- #include <linux/device.h>
-+#include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/of.h>
- #include <linux/platform_device.h>
-+#include <linux/regmap.h>
- #include <linux/usb.h>
- #include <linux/usb/otg.h>
-
- #include "fotg210.h"
-
-+/*
-+ * Gemini-specific initialization function, only executed on the
-+ * Gemini SoC using the global misc control register.
-+ *
-+ * The gemini USB blocks are connected to either Mini-A (host mode) or
-+ * Mini-B (peripheral mode) plugs. There is no role switch support on the
-+ * Gemini SoC, just either-or.
-+ */
-+#define GEMINI_GLOBAL_MISC_CTRL 0x30
-+#define GEMINI_MISC_USB0_WAKEUP BIT(14)
-+#define GEMINI_MISC_USB1_WAKEUP BIT(15)
-+#define GEMINI_MISC_USB0_VBUS_ON BIT(22)
-+#define GEMINI_MISC_USB1_VBUS_ON BIT(23)
-+#define GEMINI_MISC_USB0_MINI_B BIT(29)
-+#define GEMINI_MISC_USB1_MINI_B BIT(30)
-+
-+static int fotg210_gemini_init(struct device *dev, struct resource *res,
-+ enum usb_dr_mode mode)
-+{
-+ struct device_node *np = dev->of_node;
-+ struct regmap *map;
-+ bool wakeup;
-+ u32 mask, val;
-+ int ret;
-+
-+ map = syscon_regmap_lookup_by_phandle(np, "syscon");
-+ if (IS_ERR(map)) {
-+ dev_err(dev, "no syscon\n");
-+ return PTR_ERR(map);
-+ }
-+ wakeup = of_property_read_bool(np, "wakeup-source");
-+
-+ /*
-+ * Figure out if this is USB0 or USB1 by simply checking the
-+ * physical base address.
-+ */
-+ mask = 0;
-+ if (res->start == 0x69000000) {
-+ mask = GEMINI_MISC_USB1_VBUS_ON | GEMINI_MISC_USB1_MINI_B |
-+ GEMINI_MISC_USB1_WAKEUP;
-+ if (mode == USB_DR_MODE_HOST)
-+ val = GEMINI_MISC_USB1_VBUS_ON;
-+ else
-+ val = GEMINI_MISC_USB1_MINI_B;
-+ if (wakeup)
-+ val |= GEMINI_MISC_USB1_WAKEUP;
-+ } else {
-+ mask = GEMINI_MISC_USB0_VBUS_ON | GEMINI_MISC_USB0_MINI_B |
-+ GEMINI_MISC_USB0_WAKEUP;
-+ if (mode == USB_DR_MODE_HOST)
-+ val = GEMINI_MISC_USB0_VBUS_ON;
-+ else
-+ val = GEMINI_MISC_USB0_MINI_B;
-+ if (wakeup)
-+ val |= GEMINI_MISC_USB0_WAKEUP;
-+ }
-+
-+ ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, mask, val);
-+ if (ret) {
-+ dev_err(dev, "failed to initialize Gemini PHY\n");
-+ return ret;
-+ }
-+
-+ dev_info(dev, "initialized Gemini PHY in %s mode\n",
-+ (mode == USB_DR_MODE_HOST) ? "host" : "gadget");
-+ return 0;
-+}
-+
- static int fotg210_probe(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
-@@ -22,6 +93,15 @@ static int fotg210_probe(struct platform
-
- mode = usb_get_dr_mode(dev);
-
-+ if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) {
-+ struct resource *res;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ ret = fotg210_gemini_init(dev, res, mode);
-+ if (ret)
-+ return ret;
-+ }
-+
- if (mode == USB_DR_MODE_PERIPHERAL)
- ret = fotg210_udc_probe(pdev);
- else
+++ /dev/null
-From 6e002d41889bc52213a26ff91338d340505e0336 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Fri, 11 Nov 2022 15:48:21 +0100
-Subject: [PATCH 06/29] usb: fotg210: Fix Kconfig for USB host modules
-
-The kernel robot reports a link failure when activating the
-FOTG210 host subdriver with =y on a system where the USB host
-core is a module (CONFIG_USB=m).
-
-This is a bit of special case, so mimic the Kconfig incantations
-from DWC3: let the subdrivers for host or peripheral depend
-on the host or gadget support being =y or the same as the
-FOTG210 core itself.
-
-This should ensure that either:
-
-- The host (CONFIG_USB) or gadget (CONFIG_GADGET) is compiled
- in and then the FOTG210 can be either module or compiled
- in.
-
-- The host or gadget is modular, and then the FOTG210 module
- must be a module too, or we cannot resolve the symbols
- at link time.
-
-Reported-by: kernel test robot <lkp@intel.com>
-Link: https://lore.kernel.org/linux-usb/202211112132.0BUPGKCd-lkp@intel.com/
-Cc: Arnd Bergmann <arnd@arndb.de>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221111144821.113665-1-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/Kconfig
-+++ b/drivers/usb/fotg210/Kconfig
-@@ -14,7 +14,7 @@ if USB_FOTG210
-
- config USB_FOTG210_HCD
- bool "Faraday FOTG210 USB Host Controller support"
-- depends on USB
-+ depends on USB=y || USB=USB_FOTG210
- help
- Faraday FOTG210 is an OTG controller which can be configured as
- an USB2.0 host. It is designed to meet USB2.0 EHCI specification
-@@ -24,7 +24,7 @@ config USB_FOTG210_HCD
- module will be called fotg210-hcd.
-
- config USB_FOTG210_UDC
-- depends on USB_GADGET
-+ depends on USB_GADGET=y || USB_GADGET=USB_FOTG210
- bool "Faraday FOTG210 USB Peripheral Controller support"
- help
- Faraday USB2.0 OTG controller which can be configured as
+++ /dev/null
-From 466b10510add46afd21ca19505b29d35ad853370 Mon Sep 17 00:00:00 2001
-From: Geert Uytterhoeven <geert+renesas@glider.be>
-Date: Mon, 21 Nov 2022 16:22:19 +0100
-Subject: [PATCH 07/29] usb: USB_FOTG210 should depend on ARCH_GEMINI
-
-The Faraday Technology FOTG210 USB2 Dual Role Controller is only present
-on Cortina Systems Gemini SoCs. Hence add a dependency on ARCH_GEMINI,
-to prevent asking the user about its drivers when configuring a kernel
-without Cortina Systems Gemini SoC support.
-
-Fixes: 1dd33a9f1b95ab59 ("usb: fotg210: Collect pieces of dual mode controller")
-Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/a989b3b798ecaf3b45f35160e30e605636d66a77.1669044086.git.geert+renesas@glider.be
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/Kconfig
-+++ b/drivers/usb/fotg210/Kconfig
-@@ -4,6 +4,7 @@ config USB_FOTG210
- tristate "Faraday FOTG210 USB2 Dual Role controller"
- depends on USB || USB_GADGET
- depends on HAS_DMA && HAS_IOMEM
-+ depends on ARCH_GEMINI || COMPILE_TEST
- default ARCH_GEMINI
- select MFD_SYSCON
- help
+++ /dev/null
-From 27cd321a365fecac857e41ad1681062994142e4a Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 14 Nov 2022 12:51:58 +0100
-Subject: [PATCH 08/29] fotg210-udc: Use dev pointer in probe and dev_messages
-
-Add a local struct device *dev pointer and use dev_err()
-etc to report status.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221114115201.302887-1-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1104,6 +1104,7 @@ int fotg210_udc_probe(struct platform_de
- struct resource *res, *ires;
- struct fotg210_udc *fotg210 = NULL;
- struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
-+ struct device *dev = &pdev->dev;
- int ret = 0;
- int i;
-
-@@ -1135,7 +1136,7 @@ int fotg210_udc_probe(struct platform_de
-
- fotg210->reg = ioremap(res->start, resource_size(res));
- if (fotg210->reg == NULL) {
-- pr_err("ioremap error.\n");
-+ dev_err(dev, "ioremap error\n");
- goto err_alloc;
- }
-
-@@ -1146,8 +1147,8 @@ int fotg210_udc_probe(struct platform_de
- fotg210->gadget.ops = &fotg210_gadget_ops;
-
- fotg210->gadget.max_speed = USB_SPEED_HIGH;
-- fotg210->gadget.dev.parent = &pdev->dev;
-- fotg210->gadget.dev.dma_mask = pdev->dev.dma_mask;
-+ fotg210->gadget.dev.parent = dev;
-+ fotg210->gadget.dev.dma_mask = dev->dma_mask;
- fotg210->gadget.name = udc_name;
-
- INIT_LIST_HEAD(&fotg210->gadget.ep_list);
-@@ -1195,15 +1196,15 @@ int fotg210_udc_probe(struct platform_de
- ret = request_irq(ires->start, fotg210_irq, IRQF_SHARED,
- udc_name, fotg210);
- if (ret < 0) {
-- pr_err("request_irq error (%d)\n", ret);
-+ dev_err(dev, "request_irq error (%d)\n", ret);
- goto err_req;
- }
-
-- ret = usb_add_gadget_udc(&pdev->dev, &fotg210->gadget);
-+ ret = usb_add_gadget_udc(dev, &fotg210->gadget);
- if (ret)
- goto err_add_udc;
-
-- dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
-+ dev_info(dev, "version %s\n", DRIVER_VERSION);
-
- return 0;
-
+++ /dev/null
-From 03e4b585ac947e2d422bedf03179bbfec3aca3cf Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 14 Nov 2022 12:51:59 +0100
-Subject: [PATCH 09/29] fotg210-udc: Support optional external PHY
-
-This adds support for an optional external PHY to the FOTG210
-UDC driver.
-
-Tested with the GPIO VBUS PHY driver on the Gemini SoC.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221114115201.302887-2-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -15,6 +15,8 @@
- #include <linux/platform_device.h>
- #include <linux/usb/ch9.h>
- #include <linux/usb/gadget.h>
-+#include <linux/usb/otg.h>
-+#include <linux/usb/phy.h>
-
- #include "fotg210.h"
- #include "fotg210-udc.h"
-@@ -1022,10 +1024,18 @@ static int fotg210_udc_start(struct usb_
- {
- struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
- u32 value;
-+ int ret;
-
- /* hook up the driver */
- fotg210->driver = driver;
-
-+ if (!IS_ERR_OR_NULL(fotg210->phy)) {
-+ ret = otg_set_peripheral(fotg210->phy->otg,
-+ &fotg210->gadget);
-+ if (ret)
-+ dev_err(fotg210->dev, "can't bind to phy\n");
-+ }
-+
- /* enable device global interrupt */
- value = ioread32(fotg210->reg + FOTG210_DMCR);
- value |= DMCR_GLINT_EN;
-@@ -1067,6 +1077,9 @@ static int fotg210_udc_stop(struct usb_g
- struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
- unsigned long flags;
-
-+ if (!IS_ERR_OR_NULL(fotg210->phy))
-+ return otg_set_peripheral(fotg210->phy->otg, NULL);
-+
- spin_lock_irqsave(&fotg210->lock, flags);
-
- fotg210_init(fotg210);
-@@ -1082,12 +1095,50 @@ static const struct usb_gadget_ops fotg2
- .udc_stop = fotg210_udc_stop,
- };
-
-+/**
-+ * fotg210_phy_event - Called by phy upon VBus event
-+ * @nb: notifier block
-+ * @action: phy action, is vbus connect or disconnect
-+ * @data: the usb_gadget structure in fotg210
-+ *
-+ * Called by the USB Phy when a cable connect or disconnect is sensed.
-+ *
-+ * Returns NOTIFY_OK or NOTIFY_DONE
-+ */
-+static int fotg210_phy_event(struct notifier_block *nb, unsigned long action,
-+ void *data)
-+{
-+ struct usb_gadget *gadget = data;
-+
-+ if (!gadget)
-+ return NOTIFY_DONE;
-+
-+ switch (action) {
-+ case USB_EVENT_VBUS:
-+ usb_gadget_vbus_connect(gadget);
-+ return NOTIFY_OK;
-+ case USB_EVENT_NONE:
-+ usb_gadget_vbus_disconnect(gadget);
-+ return NOTIFY_OK;
-+ default:
-+ return NOTIFY_DONE;
-+ }
-+}
-+
-+static struct notifier_block fotg210_phy_notifier = {
-+ .notifier_call = fotg210_phy_event,
-+};
-+
- int fotg210_udc_remove(struct platform_device *pdev)
- {
- struct fotg210_udc *fotg210 = platform_get_drvdata(pdev);
- int i;
-
- usb_del_gadget_udc(&fotg210->gadget);
-+ if (!IS_ERR_OR_NULL(fotg210->phy)) {
-+ usb_unregister_notifier(fotg210->phy, &fotg210_phy_notifier);
-+ usb_put_phy(fotg210->phy);
-+ }
- iounmap(fotg210->reg);
- free_irq(platform_get_irq(pdev, 0), fotg210);
-
-@@ -1127,6 +1178,22 @@ int fotg210_udc_probe(struct platform_de
- if (fotg210 == NULL)
- goto err;
-
-+ fotg210->dev = dev;
-+
-+ fotg210->phy = devm_usb_get_phy_by_phandle(dev->parent, "usb-phy", 0);
-+ if (IS_ERR(fotg210->phy)) {
-+ ret = PTR_ERR(fotg210->phy);
-+ if (ret == -EPROBE_DEFER)
-+ goto err;
-+ dev_info(dev, "no PHY found\n");
-+ fotg210->phy = NULL;
-+ } else {
-+ ret = usb_phy_init(fotg210->phy);
-+ if (ret)
-+ goto err;
-+ dev_info(dev, "found and initialized PHY\n");
-+ }
-+
- for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
- _ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
- if (_ep[i] == NULL)
-@@ -1200,6 +1267,9 @@ int fotg210_udc_probe(struct platform_de
- goto err_req;
- }
-
-+ if (!IS_ERR_OR_NULL(fotg210->phy))
-+ usb_register_notifier(fotg210->phy, &fotg210_phy_notifier);
-+
- ret = usb_add_gadget_udc(dev, &fotg210->gadget);
- if (ret)
- goto err_add_udc;
-@@ -1209,6 +1279,8 @@ int fotg210_udc_probe(struct platform_de
- return 0;
-
- err_add_udc:
-+ if (!IS_ERR_OR_NULL(fotg210->phy))
-+ usb_unregister_notifier(fotg210->phy, &fotg210_phy_notifier);
- free_irq(ires->start, fotg210);
-
- err_req:
---- a/drivers/usb/fotg210/fotg210-udc.h
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -234,6 +234,8 @@ struct fotg210_udc {
-
- unsigned long irq_trigger;
-
-+ struct device *dev;
-+ struct usb_phy *phy;
- struct usb_gadget gadget;
- struct usb_gadget_driver *driver;
-
+++ /dev/null
-From 772ea3ec2b9363b45ef9a4768ea205f758c3debc Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 14 Nov 2022 12:52:00 +0100
-Subject: [PATCH 10/29] fotg210-udc: Handle PCLK
-
-This adds optional handling of the peripheral clock PCLK.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221114115201.302887-3-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -15,6 +15,7 @@
- #include <linux/platform_device.h>
- #include <linux/usb/ch9.h>
- #include <linux/usb/gadget.h>
-+#include <linux/clk.h>
- #include <linux/usb/otg.h>
- #include <linux/usb/phy.h>
-
-@@ -1145,6 +1146,10 @@ int fotg210_udc_remove(struct platform_d
- fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
- for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
- kfree(fotg210->ep[i]);
-+
-+ if (!IS_ERR(fotg210->pclk))
-+ clk_disable_unprepare(fotg210->pclk);
-+
- kfree(fotg210);
-
- return 0;
-@@ -1180,17 +1185,34 @@ int fotg210_udc_probe(struct platform_de
-
- fotg210->dev = dev;
-
-+ /* It's OK not to supply this clock */
-+ fotg210->pclk = devm_clk_get(dev, "PCLK");
-+ if (!IS_ERR(fotg210->pclk)) {
-+ ret = clk_prepare_enable(fotg210->pclk);
-+ if (ret) {
-+ dev_err(dev, "failed to enable PCLK\n");
-+ return ret;
-+ }
-+ } else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
-+ /*
-+ * Percolate deferrals, for anything else,
-+ * just live without the clocking.
-+ */
-+ ret = -EPROBE_DEFER;
-+ goto err;
-+ }
-+
- fotg210->phy = devm_usb_get_phy_by_phandle(dev->parent, "usb-phy", 0);
- if (IS_ERR(fotg210->phy)) {
- ret = PTR_ERR(fotg210->phy);
- if (ret == -EPROBE_DEFER)
-- goto err;
-+ goto err_pclk;
- dev_info(dev, "no PHY found\n");
- fotg210->phy = NULL;
- } else {
- ret = usb_phy_init(fotg210->phy);
- if (ret)
-- goto err;
-+ goto err_pclk;
- dev_info(dev, "found and initialized PHY\n");
- }
-
-@@ -1292,6 +1314,10 @@ err_map:
- err_alloc:
- for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
- kfree(fotg210->ep[i]);
-+err_pclk:
-+ if (!IS_ERR(fotg210->pclk))
-+ clk_disable_unprepare(fotg210->pclk);
-+
- kfree(fotg210);
-
- err:
---- a/drivers/usb/fotg210/fotg210-udc.h
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -231,6 +231,7 @@ struct fotg210_ep {
- struct fotg210_udc {
- spinlock_t lock; /* protect the struct */
- void __iomem *reg;
-+ struct clk *pclk;
-
- unsigned long irq_trigger;
-
+++ /dev/null
-From eda686d41e298a9d16708d2ec8d12d8e682dd7ca Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 14 Nov 2022 12:52:01 +0100
-Subject: [PATCH 11/29] fotg210-udc: Get IRQ using platform_get_irq()
-
-The platform_get_irq() is necessary to use to get dynamic
-IRQ resolution when instantiating the device from the
-device tree. IRQs are not passed as resources in that
-case.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221114115201.302887-4-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1157,10 +1157,11 @@ int fotg210_udc_remove(struct platform_d
-
- int fotg210_udc_probe(struct platform_device *pdev)
- {
-- struct resource *res, *ires;
-+ struct resource *res;
- struct fotg210_udc *fotg210 = NULL;
- struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
- struct device *dev = &pdev->dev;
-+ int irq;
- int ret = 0;
- int i;
-
-@@ -1170,9 +1171,9 @@ int fotg210_udc_probe(struct platform_de
- return -ENODEV;
- }
-
-- ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-- if (!ires) {
-- pr_err("platform_get_resource IORESOURCE_IRQ error.\n");
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ pr_err("could not get irq\n");
- return -ENODEV;
- }
-
-@@ -1202,7 +1203,7 @@ int fotg210_udc_probe(struct platform_de
- goto err;
- }
-
-- fotg210->phy = devm_usb_get_phy_by_phandle(dev->parent, "usb-phy", 0);
-+ fotg210->phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
- if (IS_ERR(fotg210->phy)) {
- ret = PTR_ERR(fotg210->phy);
- if (ret == -EPROBE_DEFER)
-@@ -1282,7 +1283,7 @@ int fotg210_udc_probe(struct platform_de
-
- fotg210_disable_unplug(fotg210);
-
-- ret = request_irq(ires->start, fotg210_irq, IRQF_SHARED,
-+ ret = request_irq(irq, fotg210_irq, IRQF_SHARED,
- udc_name, fotg210);
- if (ret < 0) {
- dev_err(dev, "request_irq error (%d)\n", ret);
-@@ -1303,7 +1304,7 @@ int fotg210_udc_probe(struct platform_de
- err_add_udc:
- if (!IS_ERR_OR_NULL(fotg210->phy))
- usb_unregister_notifier(fotg210->phy, &fotg210_phy_notifier);
-- free_irq(ires->start, fotg210);
-+ free_irq(irq, fotg210);
-
- err_req:
- fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
+++ /dev/null
-From 7889a2f0256c55e0184dffd0001d0782f9e4cb83 Mon Sep 17 00:00:00 2001
-From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
-Date: Mon, 14 Nov 2022 21:38:04 +0100
-Subject: [PATCH 12/29] usb: fotg210-udc: Remove a useless assignment
-
-There is no need to use an intermediate array for these memory allocations,
-so, axe it.
-
-While at it, turn a '== NULL' into a shorter '!' when testing memory
-allocation failure.
-
-Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/deab9696fc4000499470e7ccbca7c36fca17bd4e.1668458274.git.christophe.jaillet@wanadoo.fr
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1159,7 +1159,6 @@ int fotg210_udc_probe(struct platform_de
- {
- struct resource *res;
- struct fotg210_udc *fotg210 = NULL;
-- struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
- struct device *dev = &pdev->dev;
- int irq;
- int ret = 0;
-@@ -1218,10 +1217,9 @@ int fotg210_udc_probe(struct platform_de
- }
-
- for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
-- _ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
-- if (_ep[i] == NULL)
-+ fotg210->ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
-+ if (!fotg210->ep[i])
- goto err_alloc;
-- fotg210->ep[i] = _ep[i];
- }
-
- fotg210->reg = ioremap(res->start, resource_size(res));
+++ /dev/null
-From 7b95ade85ac18eec63e81ac58a482b3e88361ffd Mon Sep 17 00:00:00 2001
-From: Yi Yang <yiyang13@huawei.com>
-Date: Fri, 2 Dec 2022 09:21:26 +0800
-Subject: [PATCH 13/29] usb: fotg210-udc: fix potential memory leak in
- fotg210_udc_probe()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In fotg210_udc_probe(), if devm_clk_get() or clk_prepare_enable()
-fails, 'fotg210' will not be freed, which will lead to a memory leak.
-Fix it by moving kfree() to a proper location.
-
-In addition，we can use "return -ENOMEM" instead of "goto err"
-to simplify the code.
-
-Fixes: 718a38d092ec ("fotg210-udc: Handle PCLK")
-Reviewed-by: Andrzej Pietrasiewicz <andrzej.p@collabora.com>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Signed-off-by: Yi Yang <yiyang13@huawei.com>
-Link: https://lore.kernel.org/r/20221202012126.246953-1-yiyang13@huawei.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1176,12 +1176,10 @@ int fotg210_udc_probe(struct platform_de
- return -ENODEV;
- }
-
-- ret = -ENOMEM;
--
- /* initialize udc */
- fotg210 = kzalloc(sizeof(struct fotg210_udc), GFP_KERNEL);
- if (fotg210 == NULL)
-- goto err;
-+ return -ENOMEM;
-
- fotg210->dev = dev;
-
-@@ -1191,7 +1189,7 @@ int fotg210_udc_probe(struct platform_de
- ret = clk_prepare_enable(fotg210->pclk);
- if (ret) {
- dev_err(dev, "failed to enable PCLK\n");
-- return ret;
-+ goto err;
- }
- } else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
- /*
-@@ -1317,8 +1315,7 @@ err_pclk:
- if (!IS_ERR(fotg210->pclk))
- clk_disable_unprepare(fotg210->pclk);
-
-- kfree(fotg210);
--
- err:
-+ kfree(fotg210);
- return ret;
- }
+++ /dev/null
-From d8eed400495029ba551704ff0fae1dad87332291 Mon Sep 17 00:00:00 2001
-From: Arnd Bergmann <arnd@arndb.de>
-Date: Thu, 15 Dec 2022 17:57:20 +0100
-Subject: [PATCH 14/29] usb: fotg210: fix OTG-only build
-
-The fotg210 module combines the HCD and OTG drivers, which then
-fails to build when only the USB gadget support is enabled
-in the kernel but host support is not:
-
-aarch64-linux-ld: drivers/usb/fotg210/fotg210-core.o: in function `fotg210_init':
-fotg210-core.c:(.init.text+0xc): undefined reference to `usb_disabled'
-
-Move the check for usb_disabled() after the check for the HCD module,
-and let the OTG driver still be probed in this configuration.
-
-A nicer approach might be to have the common portion built as a
-library module, with the two platform other files registering
-their own platform_driver instances separately.
-
-Fixes: ddacd6ef44ca ("usb: fotg210: Fix Kconfig for USB host modules")
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-Link: https://lore.kernel.org/r/20221215165728.2062984-1-arnd@kernel.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -144,10 +144,7 @@ static struct platform_driver fotg210_dr
-
- static int __init fotg210_init(void)
- {
-- if (usb_disabled())
-- return -ENODEV;
--
-- if (IS_ENABLED(CONFIG_USB_FOTG210_HCD))
-+ if (IS_ENABLED(CONFIG_USB_FOTG210_HCD) && !usb_disabled())
- fotg210_hcd_init();
- return platform_driver_register(&fotg210_driver);
- }
+++ /dev/null
-From eaaa85d907fe27852dd960b2bc5d7bcf11bc3ebd Mon Sep 17 00:00:00 2001
-From: Yang Yingliang <yangyingliang@huawei.com>
-Date: Fri, 30 Dec 2022 14:54:27 +0800
-Subject: [PATCH 15/29] usb: fotg210-udc: fix error return code in
- fotg210_udc_probe()
-
-After commit 5f217ccd520f ("fotg210-udc: Support optional external PHY"),
-the error code is re-assigned to 0 in fotg210_udc_probe(), if allocate or
-map memory fails after the assignment, it can't return an error code. Set
-the error code to -ENOMEM to fix this problem.
-
-Fixes: 5f217ccd520f ("fotg210-udc: Support optional external PHY")
-Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20221230065427.944586-1-yangyingliang@huawei.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1214,6 +1214,8 @@ int fotg210_udc_probe(struct platform_de
- dev_info(dev, "found and initialized PHY\n");
- }
-
-+ ret = -ENOMEM;
-+
- for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
- fotg210->ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
- if (!fotg210->ep[i])
+++ /dev/null
-From 407577548b2fcd41cc72ee05df1f05a430ed30a0 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:16 +0100
-Subject: [PATCH 16/29] usb: fotg210: List different variants
-
-There are at least two variants of the FOTG: FOTG200 and
-FOTG210. Handle them in this driver and let's add
-more quirks as we go along.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-2-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -127,7 +127,9 @@ static int fotg210_remove(struct platfor
-
- #ifdef CONFIG_OF
- static const struct of_device_id fotg210_of_match[] = {
-+ { .compatible = "faraday,fotg200" },
- { .compatible = "faraday,fotg210" },
-+ /* TODO: can we also handle FUSB220? */
- {},
- };
- MODULE_DEVICE_TABLE(of, fotg210_of_match);
+++ /dev/null
-From fa735ad1afeb5791d5562617b9bbed74574d3e81 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:17 +0100
-Subject: [PATCH 17/29] usb: fotg210: Acquire memory resource in core
-
-The subdrivers are obtaining and mapping the memory resource
-separately. Create a common state container for the shared
-resources and start populating this by acquiring the IO
-memory resource and remap it and pass this to the subdrivers
-for host and peripheral.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-3-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -33,9 +33,10 @@
- #define GEMINI_MISC_USB0_MINI_B BIT(29)
- #define GEMINI_MISC_USB1_MINI_B BIT(30)
-
--static int fotg210_gemini_init(struct device *dev, struct resource *res,
-+static int fotg210_gemini_init(struct fotg210 *fotg, struct resource *res,
- enum usb_dr_mode mode)
- {
-+ struct device *dev = fotg->dev;
- struct device_node *np = dev->of_node;
- struct regmap *map;
- bool wakeup;
-@@ -47,6 +48,7 @@ static int fotg210_gemini_init(struct de
- dev_err(dev, "no syscon\n");
- return PTR_ERR(map);
- }
-+ fotg->map = map;
- wakeup = of_property_read_bool(np, "wakeup-source");
-
- /*
-@@ -55,6 +57,7 @@ static int fotg210_gemini_init(struct de
- */
- mask = 0;
- if (res->start == 0x69000000) {
-+ fotg->port = GEMINI_PORT_1;
- mask = GEMINI_MISC_USB1_VBUS_ON | GEMINI_MISC_USB1_MINI_B |
- GEMINI_MISC_USB1_WAKEUP;
- if (mode == USB_DR_MODE_HOST)
-@@ -64,6 +67,7 @@ static int fotg210_gemini_init(struct de
- if (wakeup)
- val |= GEMINI_MISC_USB1_WAKEUP;
- } else {
-+ fotg->port = GEMINI_PORT_0;
- mask = GEMINI_MISC_USB0_VBUS_ON | GEMINI_MISC_USB0_MINI_B |
- GEMINI_MISC_USB0_WAKEUP;
- if (mode == USB_DR_MODE_HOST)
-@@ -89,23 +93,34 @@ static int fotg210_probe(struct platform
- {
- struct device *dev = &pdev->dev;
- enum usb_dr_mode mode;
-+ struct fotg210 *fotg;
- int ret;
-
-+ fotg = devm_kzalloc(dev, sizeof(*fotg), GFP_KERNEL);
-+ if (!fotg)
-+ return -ENOMEM;
-+ fotg->dev = dev;
-+
-+ fotg->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!fotg->res)
-+ return -ENODEV;
-+
-+ fotg->base = devm_ioremap_resource(dev, fotg->res);
-+ if (!fotg->base)
-+ return -ENOMEM;
-+
- mode = usb_get_dr_mode(dev);
-
- if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) {
-- struct resource *res;
--
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- ret = fotg210_gemini_init(dev, res, mode);
-+ ret = fotg210_gemini_init(fotg, fotg->res, mode);
- if (ret)
- return ret;
- }
-
- if (mode == USB_DR_MODE_PERIPHERAL)
-- ret = fotg210_udc_probe(pdev);
-+ ret = fotg210_udc_probe(pdev, fotg);
- else
-- ret = fotg210_hcd_probe(pdev);
-+ ret = fotg210_hcd_probe(pdev, fotg);
-
- return ret;
- }
---- a/drivers/usb/fotg210/fotg210-hcd.c
-+++ b/drivers/usb/fotg210/fotg210-hcd.c
-@@ -5557,11 +5557,10 @@ static void fotg210_init(struct fotg210_
- * then invokes the start() method for the HCD associated with it
- * through the hotplug entry's driver_data.
- */
--int fotg210_hcd_probe(struct platform_device *pdev)
-+int fotg210_hcd_probe(struct platform_device *pdev, struct fotg210 *fotg)
- {
- struct device *dev = &pdev->dev;
- struct usb_hcd *hcd;
-- struct resource *res;
- int irq;
- int retval;
- struct fotg210_hcd *fotg210;
-@@ -5585,18 +5584,14 @@ int fotg210_hcd_probe(struct platform_de
-
- hcd->has_tt = 1;
-
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- hcd->regs = devm_ioremap_resource(&pdev->dev, res);
-- if (IS_ERR(hcd->regs)) {
-- retval = PTR_ERR(hcd->regs);
-- goto failed_put_hcd;
-- }
-+ hcd->regs = fotg->base;
-
-- hcd->rsrc_start = res->start;
-- hcd->rsrc_len = resource_size(res);
-+ hcd->rsrc_start = fotg->res->start;
-+ hcd->rsrc_len = resource_size(fotg->res);
-
- fotg210 = hcd_to_fotg210(hcd);
-
-+ fotg210->fotg = fotg;
- fotg210->caps = hcd->regs;
-
- /* It's OK not to supply this clock */
---- a/drivers/usb/fotg210/fotg210-hcd.h
-+++ b/drivers/usb/fotg210/fotg210-hcd.h
-@@ -182,6 +182,7 @@ struct fotg210_hcd { /* one per contro
- # define INCR(x) do {} while (0)
- #endif
-
-+ struct fotg210 *fotg; /* Overarching FOTG210 device */
- /* silicon clock */
- struct clk *pclk;
- };
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1155,21 +1155,14 @@ int fotg210_udc_remove(struct platform_d
- return 0;
- }
-
--int fotg210_udc_probe(struct platform_device *pdev)
-+int fotg210_udc_probe(struct platform_device *pdev, struct fotg210 *fotg)
- {
-- struct resource *res;
- struct fotg210_udc *fotg210 = NULL;
- struct device *dev = &pdev->dev;
- int irq;
- int ret = 0;
- int i;
-
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- if (!res) {
-- pr_err("platform_get_resource error.\n");
-- return -ENODEV;
-- }
--
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- pr_err("could not get irq\n");
-@@ -1182,6 +1175,7 @@ int fotg210_udc_probe(struct platform_de
- return -ENOMEM;
-
- fotg210->dev = dev;
-+ fotg210->fotg = fotg;
-
- /* It's OK not to supply this clock */
- fotg210->pclk = devm_clk_get(dev, "PCLK");
-@@ -1222,11 +1216,7 @@ int fotg210_udc_probe(struct platform_de
- goto err_alloc;
- }
-
-- fotg210->reg = ioremap(res->start, resource_size(res));
-- if (fotg210->reg == NULL) {
-- dev_err(dev, "ioremap error\n");
-- goto err_alloc;
-- }
-+ fotg210->reg = fotg->base;
-
- spin_lock_init(&fotg210->lock);
-
---- a/drivers/usb/fotg210/fotg210-udc.h
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -236,6 +236,7 @@ struct fotg210_udc {
- unsigned long irq_trigger;
-
- struct device *dev;
-+ struct fotg210 *fotg;
- struct usb_phy *phy;
- struct usb_gadget gadget;
- struct usb_gadget_driver *driver;
---- a/drivers/usb/fotg210/fotg210.h
-+++ b/drivers/usb/fotg210/fotg210.h
-@@ -2,13 +2,28 @@
- #ifndef __FOTG210_H
- #define __FOTG210_H
-
-+enum gemini_port {
-+ GEMINI_PORT_NONE = 0,
-+ GEMINI_PORT_0,
-+ GEMINI_PORT_1,
-+};
-+
-+struct fotg210 {
-+ struct device *dev;
-+ struct resource *res;
-+ void __iomem *base;
-+ struct regmap *map;
-+ enum gemini_port port;
-+};
-+
- #ifdef CONFIG_USB_FOTG210_HCD
--int fotg210_hcd_probe(struct platform_device *pdev);
-+int fotg210_hcd_probe(struct platform_device *pdev, struct fotg210 *fotg);
- int fotg210_hcd_remove(struct platform_device *pdev);
- int fotg210_hcd_init(void);
- void fotg210_hcd_cleanup(void);
- #else
--static inline int fotg210_hcd_probe(struct platform_device *pdev)
-+static inline int fotg210_hcd_probe(struct platform_device *pdev,
-+ struct fotg210 *fotg)
- {
- return 0;
- }
-@@ -26,10 +41,11 @@ static inline void fotg210_hcd_cleanup(v
- #endif
-
- #ifdef CONFIG_USB_FOTG210_UDC
--int fotg210_udc_probe(struct platform_device *pdev);
-+int fotg210_udc_probe(struct platform_device *pdev, struct fotg210 *fotg);
- int fotg210_udc_remove(struct platform_device *pdev);
- #else
--static inline int fotg210_udc_probe(struct platform_device *pdev)
-+static inline int fotg210_udc_probe(struct platform_device *pdev,
-+ struct fotg210 *fotg)
- {
- return 0;
- }
+++ /dev/null
-From fb8e1e8dbc47e7aff7624b47adaa0a84d2983802 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:18 +0100
-Subject: [PATCH 18/29] usb: fotg210: Move clock handling to core
-
-Grab the optional silicon block clock, prepare and enable it in
-the core before proceeding to prepare the host or peripheral
-driver. This saves duplicate code and also uses the simple
-devm_clk_get_optional_enabled() to do everything we really
-want to do.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-4-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -6,6 +6,7 @@
- * driver.
- */
- #include <linux/bitops.h>
-+#include <linux/clk.h>
- #include <linux/device.h>
- #include <linux/mfd/syscon.h>
- #include <linux/module.h>
-@@ -109,6 +110,10 @@ static int fotg210_probe(struct platform
- if (!fotg->base)
- return -ENOMEM;
-
-+ fotg->pclk = devm_clk_get_optional_enabled(dev, "PCLK");
-+ if (IS_ERR(fotg->pclk))
-+ return PTR_ERR(fotg->pclk);
-+
- mode = usb_get_dr_mode(dev);
-
- if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) {
---- a/drivers/usb/fotg210/fotg210-hcd.c
-+++ b/drivers/usb/fotg210/fotg210-hcd.c
-@@ -33,7 +33,6 @@
- #include <linux/platform_device.h>
- #include <linux/io.h>
- #include <linux/iopoll.h>
--#include <linux/clk.h>
-
- #include <asm/byteorder.h>
- #include <asm/irq.h>
-@@ -5594,44 +5593,22 @@ int fotg210_hcd_probe(struct platform_de
- fotg210->fotg = fotg;
- fotg210->caps = hcd->regs;
-
-- /* It's OK not to supply this clock */
-- fotg210->pclk = clk_get(dev, "PCLK");
-- if (!IS_ERR(fotg210->pclk)) {
-- retval = clk_prepare_enable(fotg210->pclk);
-- if (retval) {
-- dev_err(dev, "failed to enable PCLK\n");
-- goto failed_put_hcd;
-- }
-- } else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
-- /*
-- * Percolate deferrals, for anything else,
-- * just live without the clocking.
-- */
-- retval = PTR_ERR(fotg210->pclk);
-- goto failed_dis_clk;
-- }
--
- retval = fotg210_setup(hcd);
- if (retval)
-- goto failed_dis_clk;
-+ goto failed_put_hcd;
-
- fotg210_init(fotg210);
-
- retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (retval) {
- dev_err(dev, "failed to add hcd with err %d\n", retval);
-- goto failed_dis_clk;
-+ goto failed_put_hcd;
- }
- device_wakeup_enable(hcd->self.controller);
- platform_set_drvdata(pdev, hcd);
-
- return retval;
-
--failed_dis_clk:
-- if (!IS_ERR(fotg210->pclk)) {
-- clk_disable_unprepare(fotg210->pclk);
-- clk_put(fotg210->pclk);
-- }
- failed_put_hcd:
- usb_put_hcd(hcd);
- fail_create_hcd:
-@@ -5647,12 +5624,6 @@ fail_create_hcd:
- int fotg210_hcd_remove(struct platform_device *pdev)
- {
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
-- struct fotg210_hcd *fotg210 = hcd_to_fotg210(hcd);
--
-- if (!IS_ERR(fotg210->pclk)) {
-- clk_disable_unprepare(fotg210->pclk);
-- clk_put(fotg210->pclk);
-- }
-
- usb_remove_hcd(hcd);
- usb_put_hcd(hcd);
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -15,7 +15,6 @@
- #include <linux/platform_device.h>
- #include <linux/usb/ch9.h>
- #include <linux/usb/gadget.h>
--#include <linux/clk.h>
- #include <linux/usb/otg.h>
- #include <linux/usb/phy.h>
-
-@@ -1147,9 +1146,6 @@ int fotg210_udc_remove(struct platform_d
- for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
- kfree(fotg210->ep[i]);
-
-- if (!IS_ERR(fotg210->pclk))
-- clk_disable_unprepare(fotg210->pclk);
--
- kfree(fotg210);
-
- return 0;
-@@ -1177,34 +1173,17 @@ int fotg210_udc_probe(struct platform_de
- fotg210->dev = dev;
- fotg210->fotg = fotg;
-
-- /* It's OK not to supply this clock */
-- fotg210->pclk = devm_clk_get(dev, "PCLK");
-- if (!IS_ERR(fotg210->pclk)) {
-- ret = clk_prepare_enable(fotg210->pclk);
-- if (ret) {
-- dev_err(dev, "failed to enable PCLK\n");
-- goto err;
-- }
-- } else if (PTR_ERR(fotg210->pclk) == -EPROBE_DEFER) {
-- /*
-- * Percolate deferrals, for anything else,
-- * just live without the clocking.
-- */
-- ret = -EPROBE_DEFER;
-- goto err;
-- }
--
- fotg210->phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
- if (IS_ERR(fotg210->phy)) {
- ret = PTR_ERR(fotg210->phy);
- if (ret == -EPROBE_DEFER)
-- goto err_pclk;
-+ goto err_free;
- dev_info(dev, "no PHY found\n");
- fotg210->phy = NULL;
- } else {
- ret = usb_phy_init(fotg210->phy);
- if (ret)
-- goto err_pclk;
-+ goto err_free;
- dev_info(dev, "found and initialized PHY\n");
- }
-
-@@ -1303,11 +1282,8 @@ err_map:
- err_alloc:
- for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
- kfree(fotg210->ep[i]);
--err_pclk:
-- if (!IS_ERR(fotg210->pclk))
-- clk_disable_unprepare(fotg210->pclk);
-
--err:
-+err_free:
- kfree(fotg210);
- return ret;
- }
---- a/drivers/usb/fotg210/fotg210-udc.h
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -231,7 +231,6 @@ struct fotg210_ep {
- struct fotg210_udc {
- spinlock_t lock; /* protect the struct */
- void __iomem *reg;
-- struct clk *pclk;
-
- unsigned long irq_trigger;
-
---- a/drivers/usb/fotg210/fotg210.h
-+++ b/drivers/usb/fotg210/fotg210.h
-@@ -12,6 +12,7 @@ struct fotg210 {
- struct device *dev;
- struct resource *res;
- void __iomem *base;
-+ struct clk *pclk;
- struct regmap *map;
- enum gemini_port port;
- };
+++ /dev/null
-From b1b07abb598211de3ce7f52abdf8dcb24384341e Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:19 +0100
-Subject: [PATCH 19/29] usb: fotg210: Check role register in core
-
-Read the role register and check that we are in host/peripheral
-mode and issue warnings if we're not in the right role when
-probing respective driver.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-5-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -18,6 +18,11 @@
-
- #include "fotg210.h"
-
-+/* Role Register 0x80 */
-+#define FOTG210_RR 0x80
-+#define FOTG210_RR_ID BIT(21) /* 1 = B-device, 0 = A-device */
-+#define FOTG210_RR_CROLE BIT(20) /* 1 = device, 0 = host */
-+
- /*
- * Gemini-specific initialization function, only executed on the
- * Gemini SoC using the global misc control register.
-@@ -95,6 +100,7 @@ static int fotg210_probe(struct platform
- struct device *dev = &pdev->dev;
- enum usb_dr_mode mode;
- struct fotg210 *fotg;
-+ u32 val;
- int ret;
-
- fotg = devm_kzalloc(dev, sizeof(*fotg), GFP_KERNEL);
-@@ -122,10 +128,16 @@ static int fotg210_probe(struct platform
- return ret;
- }
-
-- if (mode == USB_DR_MODE_PERIPHERAL)
-+ val = readl(fotg->base + FOTG210_RR);
-+ if (mode == USB_DR_MODE_PERIPHERAL) {
-+ if (!(val & FOTG210_RR_CROLE))
-+ dev_err(dev, "block not in device role\n");
- ret = fotg210_udc_probe(pdev, fotg);
-- else
-+ } else {
-+ if (val & FOTG210_RR_CROLE)
-+ dev_err(dev, "block not in host role\n");
- ret = fotg210_hcd_probe(pdev, fotg);
-+ }
-
- return ret;
- }
+++ /dev/null
-From d7c2b0b6da75b86cf5ddbcd51a74d74e19bbf178 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:20 +0100
-Subject: [PATCH 20/29] usb: fotg210-udc: Assign of_node and speed on start
-
-Follow the example set by other drivers to assign of_node
-and speed to the driver when binding, also print bound
-info akin to other UDC drivers.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-6-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1028,6 +1028,10 @@ static int fotg210_udc_start(struct usb_
-
- /* hook up the driver */
- fotg210->driver = driver;
-+ fotg210->gadget.dev.of_node = fotg210->dev->of_node;
-+ fotg210->gadget.speed = USB_SPEED_UNKNOWN;
-+
-+ dev_info(fotg210->dev, "bound driver %s\n", driver->driver.name);
-
- if (!IS_ERR_OR_NULL(fotg210->phy)) {
- ret = otg_set_peripheral(fotg210->phy->otg,
-@@ -1084,6 +1088,7 @@ static int fotg210_udc_stop(struct usb_g
-
- fotg210_init(fotg210);
- fotg210->driver = NULL;
-+ fotg210->gadget.speed = USB_SPEED_UNKNOWN;
-
- spin_unlock_irqrestore(&fotg210->lock, flags);
-
+++ /dev/null
-From 2fbbfb2c556944945639b17b13fcb1e05272b646 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Wed, 18 Jan 2023 08:09:21 +0100
-Subject: [PATCH 21/29] usb: fotg210-udc: Implement VBUS session
-
-Implement VBUS session handling for FOTG210. This is
-mainly used by the UDC driver which needs to call down to
-the FOTG210 core and enable/disable VBUS, as this needs to be
-handled outside of the HCD and UDC drivers, by platform
-specific glue code.
-
-The Gemini has a special bit in a system register to turn
-VBUS on and off so we implement this in the FOTG210 core.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230103-gemini-fotg210-usb-v2-7-100388af9810@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-core.c
-+++ b/drivers/usb/fotg210/fotg210-core.c
-@@ -95,6 +95,35 @@ static int fotg210_gemini_init(struct fo
- return 0;
- }
-
-+/**
-+ * fotg210_vbus() - Called by gadget driver to enable/disable VBUS
-+ * @enable: true to enable VBUS, false to disable VBUS
-+ */
-+void fotg210_vbus(struct fotg210 *fotg, bool enable)
-+{
-+ u32 mask;
-+ u32 val;
-+ int ret;
-+
-+ switch (fotg->port) {
-+ case GEMINI_PORT_0:
-+ mask = GEMINI_MISC_USB0_VBUS_ON;
-+ val = enable ? GEMINI_MISC_USB0_VBUS_ON : 0;
-+ break;
-+ case GEMINI_PORT_1:
-+ mask = GEMINI_MISC_USB1_VBUS_ON;
-+ val = enable ? GEMINI_MISC_USB1_VBUS_ON : 0;
-+ break;
-+ default:
-+ return;
-+ }
-+ ret = regmap_update_bits(fotg->map, GEMINI_GLOBAL_MISC_CTRL, mask, val);
-+ if (ret)
-+ dev_err(fotg->dev, "failed to %s VBUS\n",
-+ enable ? "enable" : "disable");
-+ dev_info(fotg->dev, "%s: %s VBUS\n", __func__, enable ? "enable" : "disable");
-+}
-+
- static int fotg210_probe(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -1095,9 +1095,26 @@ static int fotg210_udc_stop(struct usb_g
- return 0;
- }
-
-+/**
-+ * fotg210_vbus_session - Called by external transceiver to enable/disable udc
-+ * @_gadget: usb gadget
-+ * @is_active: 0 if should disable UDC VBUS, 1 if should enable
-+ *
-+ * Returns 0
-+ */
-+static int fotg210_vbus_session(struct usb_gadget *g, int is_active)
-+{
-+ struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
-+
-+ /* Call down to core integration layer to drive or disable VBUS */
-+ fotg210_vbus(fotg210->fotg, is_active);
-+ return 0;
-+}
-+
- static const struct usb_gadget_ops fotg210_gadget_ops = {
- .udc_start = fotg210_udc_start,
- .udc_stop = fotg210_udc_stop,
-+ .vbus_session = fotg210_vbus_session,
- };
-
- /**
---- a/drivers/usb/fotg210/fotg210.h
-+++ b/drivers/usb/fotg210/fotg210.h
-@@ -17,6 +17,8 @@ struct fotg210 {
- enum gemini_port port;
- };
-
-+void fotg210_vbus(struct fotg210 *fotg, bool enable);
-+
- #ifdef CONFIG_USB_FOTG210_HCD
- int fotg210_hcd_probe(struct platform_device *pdev, struct fotg210 *fotg);
- int fotg210_hcd_remove(struct platform_device *pdev);
+++ /dev/null
-From f011d1eab23f4c063c5441c0d5a22898adf9145c Mon Sep 17 00:00:00 2001
-From: Fabian Vogt <fabian@ritter-vogt.de>
-Date: Mon, 23 Jan 2023 08:35:07 +0100
-Subject: [PATCH 22/29] fotg210-udc: Introduce and use a fotg210_ack_int
- function
-
-This is in preparation of support for devices where interrupts are acked
-differently.
-
-Signed-off-by: Fabian Vogt <fabian@ritter-vogt.de>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230123073508.2350402-3-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -28,6 +28,14 @@ static const char udc_name[] = "fotg210_
- static const char * const fotg210_ep_name[] = {
- "ep0", "ep1", "ep2", "ep3", "ep4"};
-
-+static void fotg210_ack_int(struct fotg210_udc *fotg210, u32 offset, u32 mask)
-+{
-+ u32 value = ioread32(fotg210->reg + offset);
-+
-+ value &= ~mask;
-+ iowrite32(value, fotg210->reg + offset);
-+}
-+
- static void fotg210_disable_fifo_int(struct fotg210_ep *ep)
- {
- u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
-@@ -303,8 +311,7 @@ static void fotg210_wait_dma_done(struct
- goto dma_reset;
- } while (!(value & DISGR2_DMA_CMPLT));
-
-- value &= ~DISGR2_DMA_CMPLT;
-- iowrite32(value, ep->fotg210->reg + FOTG210_DISGR2);
-+ fotg210_ack_int(ep->fotg210, FOTG210_DISGR2, DISGR2_DMA_CMPLT);
- return;
-
- dma_reset:
-@@ -844,14 +851,6 @@ static void fotg210_ep0in(struct fotg210
- }
- }
-
--static void fotg210_clear_comabt_int(struct fotg210_udc *fotg210)
--{
-- u32 value = ioread32(fotg210->reg + FOTG210_DISGR0);
--
-- value &= ~DISGR0_CX_COMABT_INT;
-- iowrite32(value, fotg210->reg + FOTG210_DISGR0);
--}
--
- static void fotg210_in_fifo_handler(struct fotg210_ep *ep)
- {
- struct fotg210_request *req = list_entry(ep->queue.next,
-@@ -893,60 +892,43 @@ static irqreturn_t fotg210_irq(int irq,
- void __iomem *reg = fotg210->reg + FOTG210_DISGR2;
- u32 int_grp2 = ioread32(reg);
- u32 int_msk2 = ioread32(fotg210->reg + FOTG210_DMISGR2);
-- u32 value;
-
- int_grp2 &= ~int_msk2;
-
- if (int_grp2 & DISGR2_USBRST_INT) {
- usb_gadget_udc_reset(&fotg210->gadget,
- fotg210->driver);
-- value = ioread32(reg);
-- value &= ~DISGR2_USBRST_INT;
-- iowrite32(value, reg);
-+ fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_USBRST_INT);
- pr_info("fotg210 udc reset\n");
- }
- if (int_grp2 & DISGR2_SUSP_INT) {
-- value = ioread32(reg);
-- value &= ~DISGR2_SUSP_INT;
-- iowrite32(value, reg);
-+ fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_SUSP_INT);
- pr_info("fotg210 udc suspend\n");
- }
- if (int_grp2 & DISGR2_RESM_INT) {
-- value = ioread32(reg);
-- value &= ~DISGR2_RESM_INT;
-- iowrite32(value, reg);
-+ fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_RESM_INT);
- pr_info("fotg210 udc resume\n");
- }
- if (int_grp2 & DISGR2_ISO_SEQ_ERR_INT) {
-- value = ioread32(reg);
-- value &= ~DISGR2_ISO_SEQ_ERR_INT;
-- iowrite32(value, reg);
-+ fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_ISO_SEQ_ERR_INT);
- pr_info("fotg210 iso sequence error\n");
- }
- if (int_grp2 & DISGR2_ISO_SEQ_ABORT_INT) {
-- value = ioread32(reg);
-- value &= ~DISGR2_ISO_SEQ_ABORT_INT;
-- iowrite32(value, reg);
-+ fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_ISO_SEQ_ABORT_INT);
- pr_info("fotg210 iso sequence abort\n");
- }
- if (int_grp2 & DISGR2_TX0BYTE_INT) {
- fotg210_clear_tx0byte(fotg210);
-- value = ioread32(reg);
-- value &= ~DISGR2_TX0BYTE_INT;
-- iowrite32(value, reg);
-+ fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_TX0BYTE_INT);
- pr_info("fotg210 transferred 0 byte\n");
- }
- if (int_grp2 & DISGR2_RX0BYTE_INT) {
- fotg210_clear_rx0byte(fotg210);
-- value = ioread32(reg);
-- value &= ~DISGR2_RX0BYTE_INT;
-- iowrite32(value, reg);
-+ fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_RX0BYTE_INT);
- pr_info("fotg210 received 0 byte\n");
- }
- if (int_grp2 & DISGR2_DMA_ERROR) {
-- value = ioread32(reg);
-- value &= ~DISGR2_DMA_ERROR;
-- iowrite32(value, reg);
-+ fotg210_ack_int(fotg210, FOTG210_DISGR2, DISGR2_DMA_ERROR);
- }
- }
-
-@@ -960,7 +942,7 @@ static irqreturn_t fotg210_irq(int irq,
-
- /* the highest priority in this source register */
- if (int_grp0 & DISGR0_CX_COMABT_INT) {
-- fotg210_clear_comabt_int(fotg210);
-+ fotg210_ack_int(fotg210, FOTG210_DISGR0, DISGR0_CX_COMABT_INT);
- pr_info("fotg210 CX command abort\n");
- }
-
+++ /dev/null
-From 367747c7813cecf19b46ef7134691f903ab76dc9 Mon Sep 17 00:00:00 2001
-From: Fabian Vogt <fabian@ritter-vogt.de>
-Date: Mon, 23 Jan 2023 08:35:08 +0100
-Subject: [PATCH 23/29] fotg210-udc: Improve device initialization
-
-Reset the device explicitly to get into a known state and also set the chip
-enable bit. Additionally, mask interrupts which aren't handled.
-
-Signed-off-by: Fabian Vogt <fabian@ritter-vogt.de>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230123073508.2350402-4-linus.walleij@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-udc.c
-+++ b/drivers/usb/fotg210/fotg210-udc.c
-@@ -7,6 +7,7 @@
- * Author : Yuan-Hsin Chen <yhchen@faraday-tech.com>
- */
-
-+#include <linux/delay.h>
- #include <linux/dma-mapping.h>
- #include <linux/err.h>
- #include <linux/interrupt.h>
-@@ -1022,6 +1023,11 @@ static int fotg210_udc_start(struct usb_
- dev_err(fotg210->dev, "can't bind to phy\n");
- }
-
-+ /* chip enable */
-+ value = ioread32(fotg210->reg + FOTG210_DMCR);
-+ value |= DMCR_CHIP_EN;
-+ iowrite32(value, fotg210->reg + FOTG210_DMCR);
-+
- /* enable device global interrupt */
- value = ioread32(fotg210->reg + FOTG210_DMCR);
- value |= DMCR_GLINT_EN;
-@@ -1038,6 +1044,15 @@ static void fotg210_init(struct fotg210_
- iowrite32(GMIR_MHC_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
- fotg210->reg + FOTG210_GMIR);
-
-+ /* mask interrupts for groups other than 0-2 */
-+ iowrite32(~(DMIGR_MINT_G0 | DMIGR_MINT_G1 | DMIGR_MINT_G2),
-+ fotg210->reg + FOTG210_DMIGR);
-+
-+ /* udc software reset */
-+ iowrite32(DMCR_SFRST, fotg210->reg + FOTG210_DMCR);
-+ /* Better wait a bit, but without a datasheet, no idea how long. */
-+ usleep_range(100, 200);
-+
- /* disable device global interrupt */
- value = ioread32(fotg210->reg + FOTG210_DMCR);
- value &= ~DMCR_GLINT_EN;
---- a/drivers/usb/fotg210/fotg210-udc.h
-+++ b/drivers/usb/fotg210/fotg210-udc.h
-@@ -58,6 +58,8 @@
-
- /* Device Mask of Interrupt Group Register (0x130) */
- #define FOTG210_DMIGR 0x130
-+#define DMIGR_MINT_G2 (1 << 2)
-+#define DMIGR_MINT_G1 (1 << 1)
- #define DMIGR_MINT_G0 (1 << 0)
-
- /* Device Mask of Interrupt Source Group 0(0x134) */
+++ /dev/null
-From 482830a70408a5d30af264b3d6706f818c78b2b2 Mon Sep 17 00:00:00 2001
-From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
-Date: Fri, 20 Jan 2023 17:44:33 +0200
-Subject: [PATCH 24/29] usb: fotg210-hcd: use sysfs_emit() to instead of
- scnprintf()
-
-Follow the advice of the Documentation/filesystems/sysfs.rst and show()
-should only use sysfs_emit() or sysfs_emit_at() when formatting the
-value to be returned to user space.
-
-Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
-Link: https://lore.kernel.org/r/20230120154437.22025-1-andriy.shevchenko@linux.intel.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
---- a/drivers/usb/fotg210/fotg210-hcd.c
-+++ b/drivers/usb/fotg210/fotg210-hcd.c
-@@ -4686,14 +4686,11 @@ static ssize_t uframe_periodic_max_show(
- struct device_attribute *attr, char *buf)
- {
- struct fotg210_hcd *fotg210;
-- int n;
-
- fotg210 = hcd_to_fotg210(bus_to_hcd(dev_get_drvdata(dev)));
-- n = scnprintf(buf, PAGE_SIZE, "%d\n", fotg210->uframe_periodic_max);
-- return n;
-+ return sysfs_emit(buf, "%d\n", fotg210->uframe_periodic_max);
- }
-
--
- static ssize_t uframe_periodic_max_store(struct device *dev,
- struct device_attribute *attr, const char *buf, size_t count)
- {
+++ /dev/null
-From 6b84aa39a063eec883d410a9893cec70fce56163 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 4 Dec 2022 20:02:28 +0100
-Subject: [PATCH 25/29] ARM: dts: gemini: Push down flash address/size cells
-
-The platforms not defining any OF partions complain like
-this:
-
-../arch/arm/boot/dts/gemini.dtsi:19.25-28.5: Warning
- (avoid_unnecessary_addr_size): /soc/flash@30000000: unnecessary
- #address-cells/#size-cells without "ranges" or child "reg" property
-
-Get rid of this by only defining the address-cells and
-size-cells where it is actually used by OF partitions.
-
-Link: https://lore.kernel.org/r/20221204190230.3345590-1-linus.walleij@linaro.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
---- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
-+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
-@@ -164,6 +164,8 @@
- compatible = "cortina,gemini-flash", "jedec-flash";
- status = "okay";
- reg = <0x30000000 0x00080000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-
- /*
- * This "RedBoot" is the Storlink derivative.
---- a/arch/arm/boot/dts/gemini-wbd111.dts
-+++ b/arch/arm/boot/dts/gemini-wbd111.dts
-@@ -86,6 +86,8 @@
- status = "okay";
- /* 8MB of flash */
- reg = <0x30000000 0x00800000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-
- partition@0 {
- label = "RedBoot";
---- a/arch/arm/boot/dts/gemini-wbd222.dts
-+++ b/arch/arm/boot/dts/gemini-wbd222.dts
-@@ -90,6 +90,8 @@
- status = "okay";
- /* 8MB of flash */
- reg = <0x30000000 0x00800000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-
- partition@0 {
- label = "RedBoot";
---- a/arch/arm/boot/dts/gemini.dtsi
-+++ b/arch/arm/boot/dts/gemini.dtsi
-@@ -22,8 +22,6 @@
- pinctrl-names = "default";
- pinctrl-0 = <&pflash_default_pins>;
- bank-width = <2>;
-- #address-cells = <1>;
-- #size-cells = <1>;
- status = "disabled";
- };
-
+++ /dev/null
-From 0e733f5af628210f372585e431504a7024e7b571 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 4 Dec 2022 20:02:29 +0100
-Subject: [PATCH 26/29] ARM: dts: gemini: wbd111: Use RedBoot partion parser
-
-This is clearly a RedBoot partitioned device with 0x20000
-sized erase blocks.
-
-Link: https://lore.kernel.org/r/20221204190230.3345590-2-linus.walleij@linaro.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
---- a/arch/arm/boot/dts/gemini-wbd111.dts
-+++ b/arch/arm/boot/dts/gemini-wbd111.dts
-@@ -86,36 +86,11 @@
- status = "okay";
- /* 8MB of flash */
- reg = <0x30000000 0x00800000>;
-- #address-cells = <1>;
-- #size-cells = <1>;
-
-- partition@0 {
-- label = "RedBoot";
-- reg = <0x00000000 0x00020000>;
-- read-only;
-- };
-- partition@20000 {
-- label = "kernel";
-- reg = <0x00020000 0x00100000>;
-- };
-- partition@120000 {
-- label = "rootfs";
-- reg = <0x00120000 0x006a0000>;
-- };
-- partition@7c0000 {
-- label = "VCTL";
-- reg = <0x007c0000 0x00010000>;
-- read-only;
-- };
-- partition@7d0000 {
-- label = "cfg";
-- reg = <0x007d0000 0x00010000>;
-- read-only;
-- };
-- partition@7e0000 {
-- label = "FIS";
-- reg = <0x007e0000 0x00010000>;
-- read-only;
-+ partitions {
-+ compatible = "redboot-fis";
-+ /* Eraseblock at 0x7e0000 */
-+ fis-index-block = <0x3f>;
- };
- };
-
+++ /dev/null
-From 8558e2e1110a5daa4ac9e1c5b5c15e1651a8fb94 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sun, 4 Dec 2022 20:02:30 +0100
-Subject: [PATCH 27/29] ARM: dts: gemini: wbd222: Use RedBoot partion parser
-
-This is clearly a RedBoot partitioned device with 0x20000
-sized erase blocks.
-
-Link: https://lore.kernel.org/r/20221204190230.3345590-3-linus.walleij@linaro.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
---- a/arch/arm/boot/dts/gemini-wbd222.dts
-+++ b/arch/arm/boot/dts/gemini-wbd222.dts
-@@ -90,36 +90,11 @@
- status = "okay";
- /* 8MB of flash */
- reg = <0x30000000 0x00800000>;
-- #address-cells = <1>;
-- #size-cells = <1>;
-
-- partition@0 {
-- label = "RedBoot";
-- reg = <0x00000000 0x00020000>;
-- read-only;
-- };
-- partition@20000 {
-- label = "kernel";
-- reg = <0x00020000 0x00100000>;
-- };
-- partition@120000 {
-- label = "rootfs";
-- reg = <0x00120000 0x006a0000>;
-- };
-- partition@7c0000 {
-- label = "VCTL";
-- reg = <0x007c0000 0x00010000>;
-- read-only;
-- };
-- partition@7d0000 {
-- label = "cfg";
-- reg = <0x007d0000 0x00010000>;
-- read-only;
-- };
-- partition@7e0000 {
-- label = "FIS";
-- reg = <0x007e0000 0x00010000>;
-- read-only;
-+ partitions {
-+ compatible = "redboot-fis";
-+ /* Eraseblock at 0x7e0000 */
-+ fis-index-block = <0x3f>;
- };
- };
-
+++ /dev/null
-From d5c01ce4a1016507c69682894cf6b66301abca3d Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 23 Jan 2023 08:39:15 +0100
-Subject: [PATCH 28/29] ARM: dts: gemini: Fix USB block version
-
-The FOTG version in the Gemini is the FOTG200, fix this
-up.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230123073916.2350839-1-linus.walleij@linaro.org
----
---- a/arch/arm/boot/dts/gemini.dtsi
-+++ b/arch/arm/boot/dts/gemini.dtsi
-@@ -439,7 +439,7 @@
- };
-
- usb0: usb@68000000 {
-- compatible = "cortina,gemini-usb", "faraday,fotg210";
-+ compatible = "cortina,gemini-usb", "faraday,fotg200";
- reg = <0x68000000 0x1000>;
- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&syscon GEMINI_RESET_USB0>;
-@@ -460,7 +460,7 @@
- };
-
- usb1: usb@69000000 {
-- compatible = "cortina,gemini-usb", "faraday,fotg210";
-+ compatible = "cortina,gemini-usb", "faraday,fotg200";
- reg = <0x69000000 0x1000>;
- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&syscon GEMINI_RESET_USB1>;
+++ /dev/null
-From 296184694ae7a4e388603c95499e98d30b21cc09 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 23 Jan 2023 08:39:16 +0100
-Subject: [PATCH 29/29] ARM: dts: gemini: Enable DNS313 FOTG210 as periph
-
-Add the GPIO-based VBUS phy, and enable the FOTG210
-USB1 block for use as peripheral.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20230123073916.2350839-2-linus.walleij@linaro.org
----
---- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
-+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
-@@ -80,6 +80,15 @@
- #cooling-cells = <2>;
- };
-
-+ /*
-+ * This is the type B USB connector on the device,
-+ * a GPIO-controlled USB VBUS detect
-+ */
-+ usb1_phy: phy {
-+ compatible = "gpio-usb-b-connector", "usb-b-connector";
-+ #phy-cells = <0>;
-+ vbus-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
-+ };
-
- /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */
- i2c {
-@@ -302,5 +311,13 @@
- ide@63000000 {
- status = "okay";
- };
-+
-+ usb@69000000 {
-+ status = "okay";
-+ dr_mode = "peripheral";
-+ usb-phy = <&usb1_phy>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&usb_default_pins>;
-+ };
- };
- };
---- a/arch/arm/boot/dts/gemini.dtsi
-+++ b/arch/arm/boot/dts/gemini.dtsi
-@@ -455,6 +455,8 @@
- */
- pinctrl-names = "default";
- pinctrl-0 = <&usb_default_pins>;
-+ /* Default to host mode */
-+ dr_mode = "host";
- syscon = <&syscon>;
- status = "disabled";
- };
+++ /dev/null
-From 36ee838bf83c01cff7cb47c7b07be278d2950ac0 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 11 Mar 2019 15:44:29 +0100
-Subject: [PATCH 2/2] ARM: dts: Augment DIR-685 partition table for OpenWrt
-
-Rename the firmware partition so that the firmware MTD
-splitter will do its job, drop the rootfs arguments as
-the MTD splitter will set this up automatically.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
---- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts
-+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts
-@@ -20,7 +20,7 @@
- };
-
- chosen {
-- bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300";
-+ bootargs = "console=ttyS0,19200n8 consoleblank=300";
- stdout-path = "uart0:19200n8";
- };
-
-@@ -317,9 +317,9 @@
- * this is called "upgrade" on the vendor system.
- */
- partition@40000 {
-- label = "upgrade";
-+ compatible = "wrg";
-+ label = "firmware";
- reg = <0x00040000 0x01f40000>;
-- read-only;
- };
- /* RGDB, Residental Gateway Database? */
- partition@1f80000 {
--- /dev/null
+From f8001196455311eb128fcafd98cb2050a70218df Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 6 Jan 2024 01:12:22 +0100
+Subject: [PATCH 4/4] net: ethernet: cortina: Drop TSO support
+
+The recent change to allow large frames without hardware checksumming
+slotted in software checksumming in the driver if hardware could not
+do it.
+
+This will however upset TSO (TCP Segment Offloading). Typical
+error dumps includes this:
+
+skb len=2961 headroom=222 headlen=66 tailroom=0
+(...)
+WARNING: CPU: 0 PID: 956 at net/core/dev.c:3259 skb_warn_bad_offload+0x7c/0x108
+gemini-ethernet-port: caps=(0x0000010000154813, 0x00002007ffdd7889)
+
+And the packets do not go through.
+
+The TSO implementation is bogus: a TSO enabled driver must propagate
+the skb_shinfo(skb)->gso_size value to the TSO engine on the NIC.
+
+Drop the size check and TSO offloading features for now: this
+needs to be fixed up properly.
+
+After this ethernet works fine on Gemini devices with a direct connected
+PHY such as D-Link DNS-313.
+
+Also tested to still be working with a DSA switch using the Gemini
+ethernet as conduit interface.
+
+Link: https://lore.kernel.org/netdev/CANn89iJLfxng1sYL5Zk0mknXpyYQPCp83m3KgD2KJ2_hKCpEUg@mail.gmail.com/
+Suggested-by: Eric Dumazet <edumazet@google.com>
+Fixes: d4d0c5b4d279 ("net: ethernet: cortina: Handle large frames")
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Reviewed-by: Eric Dumazet <edumazet@google.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/cortina/gemini.c | 15 ++-------------
+ 1 file changed, 2 insertions(+), 13 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -79,8 +79,7 @@ MODULE_PARM_DESC(debug, "Debug level (0=
+ #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
+
+ #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
+- NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
+- NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
++ NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM)
+
+ /**
+ * struct gmac_queue_page - page buffer per-page info
+@@ -1143,23 +1142,13 @@ static int gmac_map_tx_bufs(struct net_d
+ struct gmac_txdesc *txd;
+ skb_frag_t *skb_frag;
+ dma_addr_t mapping;
+- unsigned short mtu;
+ void *buffer;
+ int ret;
+
+- mtu = ETH_HLEN;
+- mtu += netdev->mtu;
+- if (skb->protocol == htons(ETH_P_8021Q))
+- mtu += VLAN_HLEN;
+-
++ /* TODO: implement proper TSO using MTU in word3 */
+ word1 = skb->len;
+ word3 = SOF_BIT;
+
+- if (word1 > mtu) {
+- word1 |= TSS_MTU_ENABLE_BIT;
+- word3 |= mtu;
+- }
+-
+ if (skb->len >= ETH_FRAME_LEN) {
+ /* Hardware offloaded checksumming isn't working on frames
+ * bigger than 1514 bytes. A hypothesis about this is that the
--- /dev/null
+From 091cde88b5ff2a2ca5739ce41f9cf5640a95222f Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sun, 11 Feb 2024 22:24:25 +0100
+Subject: [PATCH] ARM: dts: gemini: Map reset keys to KEY_RESTART
+
+This maps the misc "reset", "setup" and "facory reset" keys to the
+only key a standard userspace is likely to understand: KEY_RESTART.
+On OpenWrt this will simply restart the system under controlled
+forms.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20240211-gemini-dts-v1-3-6c09adeb4c2e@linaro.org
+---
+ arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts | 4 ++--
+ arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts | 4 ++--
+ arch/arm/boot/dts/gemini/gemini-sl93512r.dts | 2 +-
+ arch/arm/boot/dts/gemini/gemini-sq201.dts | 2 +-
+ arch/arm/boot/dts/gemini/gemini-wbd111.dts | 4 ++--
+ arch/arm/boot/dts/gemini/gemini-wbd222.dts | 4 ++--
+ 6 files changed, 10 insertions(+), 10 deletions(-)
+
+--- a/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
++++ b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
+@@ -27,10 +27,10 @@
+ gpio_keys {
+ compatible = "gpio-keys";
+
+- button-esc {
++ button-reset {
+ debounce-interval = <100>;
+ wakeup-source;
+- linux,code = <KEY_ESC>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
+ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
+--- a/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts
++++ b/arch/arm/boot/dts/gemini/gemini-dlink-dns-313.dts
+@@ -33,10 +33,10 @@
+ gpio_keys {
+ compatible = "gpio-keys";
+
+- button-esc {
++ button-reset {
+ debounce-interval = <100>;
+ wakeup-source;
+- linux,code = <KEY_ESC>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ };
+--- a/arch/arm/boot/dts/gemini/gemini-sl93512r.dts
++++ b/arch/arm/boot/dts/gemini/gemini-sl93512r.dts
+@@ -43,7 +43,7 @@
+ button-setup {
+ debounce-interval = <50>;
+ wakeup-source;
+- linux,code = <KEY_SETUP>;
++ linux,code = <KEY_RESTART>;
+ label = "factory reset";
+ /* Conflict with NAND flash */
+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+--- a/arch/arm/boot/dts/gemini/gemini-sq201.dts
++++ b/arch/arm/boot/dts/gemini/gemini-sq201.dts
+@@ -30,7 +30,7 @@
+ button-setup {
+ debounce-interval = <100>;
+ wakeup-source;
+- linux,code = <KEY_SETUP>;
++ linux,code = <KEY_RESTART>;
+ label = "factory reset";
+ /* Conflict with NAND flash */
+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+--- a/arch/arm/boot/dts/gemini/gemini-wbd111.dts
++++ b/arch/arm/boot/dts/gemini/gemini-wbd111.dts
+@@ -28,10 +28,10 @@
+ gpio_keys {
+ compatible = "gpio-keys";
+
+- button-setup {
++ button-reset {
+ debounce-interval = <100>;
+ wakeup-source;
+- linux,code = <KEY_SETUP>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ /* Conflict with ICE */
+ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+--- a/arch/arm/boot/dts/gemini/gemini-wbd222.dts
++++ b/arch/arm/boot/dts/gemini/gemini-wbd222.dts
+@@ -27,10 +27,10 @@
+ gpio_keys {
+ compatible = "gpio-keys";
+
+- button-setup {
++ button-reset {
+ debounce-interval = <100>;
+ wakeup-source;
+- linux,code = <KEY_SETUP>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ /* Conflict with ICE */
+ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
--- /dev/null
+From 81889eb2b37bc21df4ff259441e8fc12d4f27cd9 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 9 May 2024 08:48:31 +0200
+Subject: [PATCH] net: ethernet: cortina: Locking fixes
+
+This fixes a probably long standing problem in the Cortina
+Gemini ethernet driver: there are some paths in the code
+where the IRQ registers are written without taking the proper
+locks.
+
+Fixes: 4d5ae32f5e1e ("net: ethernet: Add a driver for Gemini gigabit ethernet")
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -1107,10 +1107,13 @@ static void gmac_tx_irq_enable(struct ne
+ {
+ struct gemini_ethernet_port *port = netdev_priv(netdev);
+ struct gemini_ethernet *geth = port->geth;
++ unsigned long flags;
+ u32 val, mask;
+
+ netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
+
++ spin_lock_irqsave(&geth->irq_lock, flags);
++
+ mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
+
+ if (en)
+@@ -1119,6 +1122,8 @@ static void gmac_tx_irq_enable(struct ne
+ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
+ val = en ? val | mask : val & ~mask;
+ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
+ }
+
+ static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
+@@ -1415,15 +1420,19 @@ static unsigned int gmac_rx(struct net_d
+ union gmac_rxdesc_3 word3;
+ struct page *page = NULL;
+ unsigned int page_offs;
++ unsigned long flags;
+ unsigned short r, w;
+ union dma_rwptr rw;
+ dma_addr_t mapping;
+ int frag_nr = 0;
+
++ spin_lock_irqsave(&geth->irq_lock, flags);
+ rw.bits32 = readl(ptr_reg);
+ /* Reset interrupt as all packages until here are taken into account */
+ writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
+ geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++
+ r = rw.bits.rptr;
+ w = rw.bits.wptr;
+
+@@ -1726,10 +1735,9 @@ static irqreturn_t gmac_irq(int irq, voi
+ gmac_update_hw_stats(netdev);
+
+ if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
++ spin_lock(&geth->irq_lock);
+ writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
+ geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
+-
+- spin_lock(&geth->irq_lock);
+ u64_stats_update_begin(&port->ir_stats_syncp);
+ ++port->stats.rx_fifo_errors;
+ u64_stats_update_end(&port->ir_stats_syncp);
--- /dev/null
+From 30fcba19ed88997a2909e4a68b4d39ff371357c3 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Wed, 1 May 2024 21:46:31 +0200
+Subject: [PATCH 1/5] net: ethernet: cortina: Restore TSO support
+
+An earlier commit deleted the TSO support in the Cortina Gemini
+driver because the driver was confusing gso_size and MTU,
+probably because what the Linux kernel calls "gso_size" was
+called "MTU" in the datasheet.
+
+Restore the functionality properly reading the gso_size from
+the skbuff.
+
+Tested with iperf3, running a server on a different machine
+and client on the device with the cortina gemini ethernet:
+
+Connecting to host 192.168.1.2, port 5201
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=1c8a
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=1c8a
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=27da
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=0b92
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=2bda
+(...)
+
+(The hardware MSS 0x05ea here includes the ethernet headers.)
+
+If I disable all segment offloading on the receiving host and
+dump packets using tcpdump -xx like this:
+
+ethtool -K enp2s0 gro off gso off tso off
+tcpdump -xx -i enp2s0 host 192.168.1.136
+
+I get segmented packages such as this when running iperf3:
+
+23:16:54.024139 IP OpenWrt.lan.59168 > Fecusia.targus-getdata1:
+Flags [.], seq 1486:2934, ack 1, win 4198,
+options [nop,nop,TS val 3886192908 ecr 3601341877], length 1448
+0x0000: fc34 9701 a0c6 14d6 4da8 3c4f 0800 4500
+0x0010: 05dc 16a0 4000 4006 9aa1 c0a8 0188 c0a8
+0x0020: 0102 e720 1451 ff25 9822 4c52 29cf 8010
+0x0030: 1066 ac8c 0000 0101 080a e7a2 990c d6a8
+(...)
+0x05c0: 5e49 e109 fe8c 4617 5e18 7a82 7eae d647
+0x05d0: e8ee ae64 dc88 c897 3f8a 07a4 3a33 6b1b
+0x05e0: 3501 a30f 2758 cc44 4b4a
+
+Several such packets often follow after each other verifying
+the segmentation into 0x05a8 (1448) byte packages also on the
+reveiving end. As can be seen, the ethernet frames are
+0x05ea (1514) in size.
+
+Performance with iperf3 before this patch: ~15.5 Mbit/s
+Performance with iperf3 after this patch: ~175 Mbit/s
+
+This was running a 60 second test (twice) the best measurement
+was 179 Mbit/s.
+
+For comparison if I run iperf3 with UDP I get around 1.05 Mbit/s
+both before and after this patch.
+
+While this is a gigabit ethernet interface, the CPU is a cheap
+D-Link DIR-685 router (based on the ARMv5 Faraday FA526 at
+~50 MHz), and the software is not supposed to drive traffic,
+as the device has a DSA chip, so this kind of numbers can be
+expected.
+
+Fixes: ac631873c9e7 ("net: ethernet: cortina: Drop TSO support")
+Reviewed-by: Eric Dumazet <edumazet@google.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 23 +++++++++++++++++++----
+ 1 file changed, 19 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -79,7 +79,8 @@ MODULE_PARM_DESC(debug, "Debug level (0=
+ #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
+
+ #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
+- NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM)
++ NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
++ NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
+
+ /**
+ * struct gmac_queue_page - page buffer per-page info
+@@ -1148,13 +1149,25 @@ static int gmac_map_tx_bufs(struct net_d
+ skb_frag_t *skb_frag;
+ dma_addr_t mapping;
+ void *buffer;
++ u16 mss;
+ int ret;
+
+- /* TODO: implement proper TSO using MTU in word3 */
+ word1 = skb->len;
+ word3 = SOF_BIT;
+
+- if (skb->len >= ETH_FRAME_LEN) {
++ mss = skb_shinfo(skb)->gso_size;
++ if (mss) {
++ /* This means we are dealing with TCP and skb->len is the
++ * sum total of all the segments. The TSO will deal with
++ * chopping this up for us.
++ */
++ /* The accelerator needs the full frame size here */
++ mss += skb_tcp_all_headers(skb);
++ netdev_dbg(netdev, "segment offloading mss = %04x len=%04x\n",
++ mss, skb->len);
++ word1 |= TSS_MTU_ENABLE_BIT;
++ word3 |= mss;
++ } else if (skb->len >= ETH_FRAME_LEN) {
+ /* Hardware offloaded checksumming isn't working on frames
+ * bigger than 1514 bytes. A hypothesis about this is that the
+ * checksum buffer is only 1518 bytes, so when the frames get
+@@ -1169,7 +1182,9 @@ static int gmac_map_tx_bufs(struct net_d
+ return ret;
+ }
+ word1 |= TSS_BYPASS_BIT;
+- } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
++ }
++
++ if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ int tcp = 0;
+
+ /* We do not switch off the checksumming on non TCP/UDP
--- /dev/null
+From 91fb8a7328dda827bc6c0da240a1eb17028416cd Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 9 May 2024 23:59:28 +0200
+Subject: [PATCH 2/5] net: ethernet: cortina: Use TSO also on common TCP
+
+It is possible to push the segment offloader to also
+process non-segmented frames: just pass the skb->len
+or desired MSS to the offloader and it will handle them.
+
+This is especially good if the user sets up the MTU
+and the frames get big, because the checksumming engine
+cannot handle any frames bigger than 1518 bytes, so
+segmenting them all to be at max that will be helpful
+for the hardware, which only need to quirk odd frames
+such as big UDP ping packets.
+
+The vendor driver always uses the TSO like this, and
+the driver seems more stable after this, so apparently
+the hardware may have been engineered to always use
+the TSO on anything it can handle.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 31 +++++++++++++++++++++------
+ 1 file changed, 24 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -1148,6 +1148,7 @@ static int gmac_map_tx_bufs(struct net_d
+ struct gmac_txdesc *txd;
+ skb_frag_t *skb_frag;
+ dma_addr_t mapping;
++ bool tcp = false;
+ void *buffer;
+ u16 mss;
+ int ret;
+@@ -1155,6 +1156,13 @@ static int gmac_map_tx_bufs(struct net_d
+ word1 = skb->len;
+ word3 = SOF_BIT;
+
++ /* Determine if we are doing TCP */
++ if (skb->protocol == htons(ETH_P_IP))
++ tcp = (ip_hdr(skb)->protocol == IPPROTO_TCP);
++ else
++ /* IPv6 */
++ tcp = (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP);
++
+ mss = skb_shinfo(skb)->gso_size;
+ if (mss) {
+ /* This means we are dealing with TCP and skb->len is the
+@@ -1167,6 +1175,20 @@ static int gmac_map_tx_bufs(struct net_d
+ mss, skb->len);
+ word1 |= TSS_MTU_ENABLE_BIT;
+ word3 |= mss;
++ } else if (tcp) {
++ /* Even if we are not using TSO, use the segment offloader
++ * for transferring the TCP frame: the TSO engine will deal
++ * with chopping up frames that exceed ETH_DATA_LEN which
++ * the checksumming engine cannot handle (see below) into
++ * manageable chunks. It flawlessly deals with quite big
++ * frames and frames containing custom DSA EtherTypes.
++ */
++ mss = netdev->mtu + skb_tcp_all_headers(skb);
++ mss = min(mss, skb->len);
++ netdev_dbg(netdev, "botched TSO len %04x mtu %04x mss %04x\n",
++ skb->len, netdev->mtu, mss);
++ word1 |= TSS_MTU_ENABLE_BIT;
++ word3 |= mss;
+ } else if (skb->len >= ETH_FRAME_LEN) {
+ /* Hardware offloaded checksumming isn't working on frames
+ * bigger than 1514 bytes. A hypothesis about this is that the
+@@ -1185,21 +1207,16 @@ static int gmac_map_tx_bufs(struct net_d
+ }
+
+ if (skb->ip_summed == CHECKSUM_PARTIAL) {
+- int tcp = 0;
+-
+ /* We do not switch off the checksumming on non TCP/UDP
+ * frames: as is shown from tests, the checksumming engine
+ * is smart enough to see that a frame is not actually TCP
+ * or UDP and then just pass it through without any changes
+ * to the frame.
+ */
+- if (skb->protocol == htons(ETH_P_IP)) {
++ if (skb->protocol == htons(ETH_P_IP))
+ word1 |= TSS_IP_CHKSUM_BIT;
+- tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
+- } else { /* IPv6 */
++ else
+ word1 |= TSS_IPV6_ENABLE_BIT;
+- tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
+- }
+
+ word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
+ }
--- /dev/null
+From fa01c904b844e6033445f75b0b4d46a8e83b6086 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 10 May 2024 19:48:27 +0200
+Subject: [PATCH 3/5] net: ethernet: cortina: Rename adjust link callback
+
+The callback passed to of_phy_get_and_connect() in the
+Cortina Gemini driver is called "gmac_speed_set" which is
+archaic, rename it to "gmac_adjust_link" following the
+pattern of most other drivers.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -288,7 +288,7 @@ static void gmac_set_flow_control(struct
+ spin_unlock_irqrestore(&port->config_lock, flags);
+ }
+
+-static void gmac_speed_set(struct net_device *netdev)
++static void gmac_adjust_link(struct net_device *netdev)
+ {
+ struct gemini_ethernet_port *port = netdev_priv(netdev);
+ struct phy_device *phydev = netdev->phydev;
+@@ -367,7 +367,7 @@ static int gmac_setup_phy(struct net_dev
+
+ phy = of_phy_get_and_connect(netdev,
+ dev->of_node,
+- gmac_speed_set);
++ gmac_adjust_link);
+ if (!phy)
+ return -ENODEV;
+ netdev->phydev = phy;
--- /dev/null
+From 50ac9765c674bac803719c6b8294670edc6df31d Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 10 May 2024 19:44:39 +0200
+Subject: [PATCH 4/5] net: ethernet: cortina: Use negotiated TX/RX pause
+
+Instead of directly poking into registers of the PHY, use
+the existing function to query phylib about this directly.
+
+Suggested-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 15 +++++----------
+ 1 file changed, 5 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -293,8 +293,8 @@ static void gmac_adjust_link(struct net_
+ struct gemini_ethernet_port *port = netdev_priv(netdev);
+ struct phy_device *phydev = netdev->phydev;
+ union gmac_status status, old_status;
+- int pause_tx = 0;
+- int pause_rx = 0;
++ bool pause_tx = false;
++ bool pause_rx = false;
+
+ status.bits32 = readl(port->gmac_base + GMAC_STATUS);
+ old_status.bits32 = status.bits32;
+@@ -329,14 +329,9 @@ static void gmac_adjust_link(struct net_
+ }
+
+ if (phydev->duplex == DUPLEX_FULL) {
+- u16 lcladv = phy_read(phydev, MII_ADVERTISE);
+- u16 rmtadv = phy_read(phydev, MII_LPA);
+- u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
+-
+- if (cap & FLOW_CTRL_RX)
+- pause_rx = 1;
+- if (cap & FLOW_CTRL_TX)
+- pause_tx = 1;
++ phy_get_pause(phydev, &pause_tx, &pause_rx);
++ netdev_dbg(netdev, "set negotiated pause params pause TX = %s, pause RX = %s\n",
++ pause_tx ? "ON" : "OFF", pause_rx ? "ON" : "OFF");
+ }
+
+ gmac_set_flow_control(netdev, pause_tx, pause_rx);
--- /dev/null
+From 4eed4b87f17d10b7586349c13c3a30f9c24c9ba4 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Wed, 8 May 2024 23:21:17 +0200
+Subject: [PATCH 5/5] net: ethernet: cortina: Implement .set_pauseparam()
+
+The Cortina Gemini ethernet can very well set up TX or RX
+pausing, so add this functionality to the driver in a
+.set_pauseparam() callback. Essentially just call down to
+phylib and let phylib deal with this, .adjust_link()
+will respect the setting from phylib.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -2143,6 +2143,19 @@ static void gmac_get_pauseparam(struct n
+ pparam->autoneg = true;
+ }
+
++static int gmac_set_pauseparam(struct net_device *netdev,
++ struct ethtool_pauseparam *pparam)
++{
++ struct phy_device *phydev = netdev->phydev;
++
++ if (!pparam->autoneg)
++ return -EOPNOTSUPP;
++
++ phy_set_asym_pause(phydev, pparam->rx_pause, pparam->tx_pause);
++
++ return 0;
++}
++
+ static void gmac_get_ringparam(struct net_device *netdev,
+ struct ethtool_ringparam *rp,
+ struct kernel_ethtool_ringparam *kernel_rp,
+@@ -2263,6 +2276,7 @@ static const struct ethtool_ops gmac_351
+ .set_link_ksettings = gmac_set_ksettings,
+ .nway_reset = gmac_nway_reset,
+ .get_pauseparam = gmac_get_pauseparam,
++ .set_pauseparam = gmac_set_pauseparam,
+ .get_ringparam = gmac_get_ringparam,
+ .set_ringparam = gmac_set_ringparam,
+ .get_coalesce = gmac_get_coalesce,
--- /dev/null
+From c1aa34cd568bc7b86b82353034070c32b6ebe6db Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 11 Mar 2019 15:44:29 +0100
+Subject: [PATCH] ARM: dts: Augment DIR-685 partition table for OpenWrt
+
+Rename the firmware partition so that the firmware MTD
+splitter will do its job, drop the rootfs arguments as
+the MTD splitter will set this up automatically.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
++++ b/arch/arm/boot/dts/gemini/gemini-dlink-dir-685.dts
+@@ -20,7 +20,7 @@
+ };
+
+ chosen {
+- bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300";
++ bootargs = "console=ttyS0,19200n8 consoleblank=300";
+ stdout-path = "uart0:19200n8";
+ };
+
+@@ -317,9 +317,9 @@
+ * this is called "upgrade" on the vendor system.
+ */
+ partition@40000 {
+- label = "upgrade";
++ compatible = "wrg";
++ label = "firmware";
+ reg = <0x00040000 0x01f40000>;
+- read-only;
+ };
+ /* RGDB, Residental Gateway Database? */
+ partition@1f80000 {
--- a/arch/Kconfig
+++ b/arch/Kconfig
-@@ -1299,6 +1299,14 @@ config ARCH_HAS_ELFCORE_COMPAT
+@@ -1307,6 +1307,14 @@ config ARCH_HAS_ELFCORE_COMPAT
config ARCH_HAS_PARANOID_L1D_FLUSH
bool
source "scripts/gcc-plugins/Kconfig"
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
-@@ -85,6 +85,7 @@ config X86
+@@ -86,6 +86,7 @@ config X86
select ARCH_HAS_PMEM_API if X86_64
select ARCH_HAS_PTE_DEVMAP if X86_64
select ARCH_HAS_PTE_SPECIAL
--- a/kernel/bounds.c
+++ b/kernel/bounds.c
@@ -22,6 +22,11 @@ int main(void)
- DEFINE(NR_CPUS_BITS, ilog2(CONFIG_NR_CPUS));
+ DEFINE(NR_CPUS_BITS, order_base_2(CONFIG_NR_CPUS));
#endif
DEFINE(SPINLOCK_SIZE, sizeof(spinlock_t));
+#ifdef CONFIG_LRU_GEN
get_scan_count(lruvec, sc, nr);
/* Record the original scan target for proportional adjustments later */
-@@ -3372,6 +4142,9 @@ static void snapshot_refaults(struct mem
+@@ -3375,6 +4145,9 @@ static void snapshot_refaults(struct mem
struct lruvec *target_lruvec;
unsigned long refaults;
target_lruvec = mem_cgroup_lruvec(target_memcg, pgdat);
refaults = lruvec_page_state(target_lruvec, WORKINGSET_ACTIVATE_ANON);
target_lruvec->refaults[0] = refaults;
-@@ -3736,12 +4509,16 @@ unsigned long try_to_free_mem_cgroup_pag
+@@ -3739,12 +4512,16 @@ unsigned long try_to_free_mem_cgroup_pag
}
#endif
if (!can_age_anon_pages(pgdat, sc))
return;
-@@ -4058,12 +4835,11 @@ restart:
+@@ -4061,12 +4838,11 @@ restart:
sc.may_swap = !nr_boost_reclaim;
/*
--- a/fs/exec.c
+++ b/fs/exec.c
-@@ -1013,6 +1013,7 @@ static int exec_mmap(struct mm_struct *m
+@@ -1014,6 +1014,7 @@ static int exec_mmap(struct mm_struct *m
active_mm = tsk->active_mm;
tsk->active_mm = mm;
tsk->mm = mm;
/*
* This prevents preemption while active_mm is being loaded and
* it and mm are being updated, which could cause problems for
-@@ -1028,6 +1029,7 @@ static int exec_mmap(struct mm_struct *m
+@@ -1029,6 +1030,7 @@ static int exec_mmap(struct mm_struct *m
tsk->mm->vmacache_seqnum = 0;
vmacache_flush(tsk);
task_unlock(tsk);
--- a/fs/exec.c
+++ b/fs/exec.c
-@@ -1013,7 +1013,6 @@ static int exec_mmap(struct mm_struct *m
+@@ -1014,7 +1014,6 @@ static int exec_mmap(struct mm_struct *m
active_mm = tsk->active_mm;
tsk->active_mm = mm;
tsk->mm = mm;
/*
* This prevents preemption while active_mm is being loaded and
* it and mm are being updated, which could cause problems for
-@@ -1028,6 +1027,7 @@ static int exec_mmap(struct mm_struct *m
+@@ -1029,6 +1028,7 @@ static int exec_mmap(struct mm_struct *m
local_irq_enable();
tsk->mm->vmacache_seqnum = 0;
vmacache_flush(tsk);
static void mem_cgroup_css_free(struct cgroup_subsys_state *css)
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
-@@ -7661,6 +7661,7 @@ static void __init free_area_init_node(i
+@@ -7663,6 +7663,7 @@ static void __init free_area_init_node(i
pgdat_set_deferred_range(pgdat);
free_area_init_core(pgdat);
list_del(&dst->list);
kfree(dst);
}
-@@ -805,7 +809,7 @@ static int dsa_switch_setup_tag_protocol
+@@ -827,7 +831,7 @@ static int dsa_switch_setup_tag_protocol
int port, err;
if (tag_ops->proto == dst->default_proto)
for (port = 0; port < ds->num_ports; port++) {
if (!dsa_is_cpu_port(ds, port))
-@@ -821,6 +825,17 @@ static int dsa_switch_setup_tag_protocol
+@@ -843,6 +847,17 @@ static int dsa_switch_setup_tag_protocol
}
}
return 0;
}
-@@ -1132,6 +1147,46 @@ static void dsa_tree_teardown(struct dsa
+@@ -1154,6 +1169,46 @@ static void dsa_tree_teardown(struct dsa
dst->setup = false;
}
/* Since the dsa/tagging sysfs device attribute is per master, the assumption
* is that all DSA switches within a tree share the same tagger, otherwise
* they would have formed disjoint trees (different "dsa,member" values).
-@@ -1164,12 +1219,15 @@ int dsa_tree_change_tag_proto(struct dsa
+@@ -1186,12 +1241,15 @@ int dsa_tree_change_tag_proto(struct dsa
goto out_unlock;
}
rtnl_unlock();
-@@ -1257,6 +1315,7 @@ static int dsa_port_parse_cpu(struct dsa
+@@ -1279,6 +1337,7 @@ static int dsa_port_parse_cpu(struct dsa
struct dsa_switch *ds = dp->ds;
struct dsa_switch_tree *dst = ds->dst;
enum dsa_tag_protocol default_proto;
/* Find out which protocol the switch would prefer. */
default_proto = dsa_get_tag_protocol(dp, master);
-@@ -1311,6 +1370,12 @@ static int dsa_port_parse_cpu(struct dsa
+@@ -1333,6 +1392,12 @@ static int dsa_port_parse_cpu(struct dsa
*/
dsa_tag_driver_put(tag_ops);
} else {
list_del(&dst->list);
kfree(dst);
}
-@@ -826,17 +822,29 @@ static int dsa_switch_setup_tag_protocol
+@@ -848,17 +844,29 @@ static int dsa_switch_setup_tag_protocol
}
connect:
}
static int dsa_switch_setup(struct dsa_switch *ds)
-@@ -1156,13 +1164,6 @@ static int dsa_tree_bind_tag_proto(struc
+@@ -1178,13 +1186,6 @@ static int dsa_tree_bind_tag_proto(struc
dst->tag_ops = tag_ops;
/* Notify the switches from this tree about the connection
* to the new tagger
*/
-@@ -1172,16 +1173,14 @@ static int dsa_tree_bind_tag_proto(struc
+@@ -1194,16 +1195,14 @@ static int dsa_tree_bind_tag_proto(struc
goto out_disconnect;
/* Notify the old tagger about the disconnection from this tree */
dst->tag_ops = old_tag_ops;
return err;
-@@ -1315,7 +1314,6 @@ static int dsa_port_parse_cpu(struct dsa
+@@ -1337,7 +1336,6 @@ static int dsa_port_parse_cpu(struct dsa
struct dsa_switch *ds = dp->ds;
struct dsa_switch_tree *dst = ds->dst;
enum dsa_tag_protocol default_proto;
/* Find out which protocol the switch would prefer. */
default_proto = dsa_get_tag_protocol(dp, master);
-@@ -1370,12 +1368,6 @@ static int dsa_port_parse_cpu(struct dsa
+@@ -1392,12 +1390,6 @@ static int dsa_port_parse_cpu(struct dsa
*/
dsa_tag_driver_put(tag_ops);
} else {
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Mon, 7 Feb 2022 10:27:22 +0100
-Subject: [PATCH] arm64: dts: mediatek: mt7622: add support for coherent
- DMA
-
-It improves performance by eliminating the need for a cache flush on rx and tx
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -357,7 +357,7 @@
- };
-
- cci_control2: slave-if@5000 {
-- compatible = "arm,cci-400-ctrl-if";
-+ compatible = "arm,cci-400-ctrl-if", "syscon";
- interface-type = "ace";
- reg = <0x5000 0x1000>;
- };
-@@ -938,6 +938,8 @@
- power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
- mediatek,ethsys = <ðsys>;
- mediatek,sgmiisys = <&sgmiisys>;
-+ mediatek,cci-control = <&cci_control2>;
-+ dma-coherent;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Sat, 5 Feb 2022 18:36:36 +0100
-Subject: [PATCH] arm64: dts: mediatek: mt7622: introduce nodes for
- Wireless Ethernet Dispatch
-
-Introduce wed0 and wed1 nodes in order to enable offloading forwarding
-between ethernet and wireless devices on the mt7622 chipset.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -894,6 +894,11 @@
- };
- };
-
-+ hifsys: syscon@1af00000 {
-+ compatible = "mediatek,mt7622-hifsys", "syscon";
-+ reg = <0 0x1af00000 0 0x70>;
-+ };
-+
- ethsys: syscon@1b000000 {
- compatible = "mediatek,mt7622-ethsys",
- "syscon";
-@@ -912,6 +917,26 @@
- #dma-cells = <1>;
- };
-
-+ pcie_mirror: pcie-mirror@10000400 {
-+ compatible = "mediatek,mt7622-pcie-mirror",
-+ "syscon";
-+ reg = <0 0x10000400 0 0x10>;
-+ };
-+
-+ wed0: wed@1020a000 {
-+ compatible = "mediatek,mt7622-wed",
-+ "syscon";
-+ reg = <0 0x1020a000 0 0x1000>;
-+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
-+ };
-+
-+ wed1: wed@1020b000 {
-+ compatible = "mediatek,mt7622-wed",
-+ "syscon";
-+ reg = <0 0x1020b000 0 0x1000>;
-+ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
-+ };
-+
- eth: ethernet@1b100000 {
- compatible = "mediatek,mt7622-eth",
- "mediatek,mt2701-eth",
-@@ -939,6 +964,9 @@
- mediatek,ethsys = <ðsys>;
- mediatek,sgmiisys = <&sgmiisys>;
- mediatek,cci-control = <&cci_control2>;
-+ mediatek,wed = <&wed0>, <&wed1>;
-+ mediatek,pcie-mirror = <&pcie_mirror>;
-+ mediatek,hifsys = <&hifsys>;
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <0>;
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -963,7 +963,7 @@
+@@ -957,7 +957,7 @@
power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
mediatek,ethsys = <ðsys>;
mediatek,sgmiisys = <&sgmiisys>;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -1243,27 +1243,31 @@ static int
+@@ -1425,27 +1425,31 @@ static int
mt7530_port_bridge_join(struct dsa_switch *ds, int port,
struct net_device *bridge)
{
}
/* Add the all other ports to this port matrix. */
-@@ -1368,24 +1372,28 @@ static void
+@@ -1550,24 +1554,28 @@ static void
mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
struct net_device *bridge)
{
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2499,6 +2499,32 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2687,6 +2687,32 @@ mt7531_setup(struct dsa_switch *ds)
return 0;
}
static bool
mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
const struct phylink_link_state *state)
-@@ -2535,6 +2561,37 @@ static bool mt7531_is_rgmii_port(struct
+@@ -2723,6 +2749,37 @@ static bool mt7531_is_rgmii_port(struct
return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
}
static bool
mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
const struct phylink_link_state *state)
-@@ -3011,6 +3068,18 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3199,6 +3256,18 @@ mt7531_cpu_port_config(struct dsa_switch
return 0;
}
static void
mt7530_mac_port_validate(struct dsa_switch *ds, int port,
unsigned long *supported)
-@@ -3246,6 +3315,7 @@ static const struct dsa_switch_ops mt753
+@@ -3435,6 +3504,7 @@ static const struct dsa_switch_ops mt753
.port_vlan_del = mt7530_port_vlan_del,
.port_mirror_add = mt753x_port_mirror_add,
.port_mirror_del = mt753x_port_mirror_del,
.phylink_validate = mt753x_phylink_validate,
.phylink_mac_link_state = mt753x_phylink_mac_link_state,
.phylink_mac_config = mt753x_phylink_mac_config,
-@@ -3263,6 +3333,7 @@ static const struct mt753x_info mt753x_t
+@@ -3452,6 +3522,7 @@ static const struct mt753x_info mt753x_t
.phy_read = mt7530_phy_read,
.phy_write = mt7530_phy_write,
.pad_setup = mt7530_pad_clk_setup,
.phy_mode_supported = mt7530_phy_mode_supported,
.mac_port_validate = mt7530_mac_port_validate,
.mac_port_get_state = mt7530_phylink_mac_link_state,
-@@ -3274,6 +3345,7 @@ static const struct mt753x_info mt753x_t
+@@ -3463,6 +3534,7 @@ static const struct mt753x_info mt753x_t
.phy_read = mt7530_phy_read,
.phy_write = mt7530_phy_write,
.pad_setup = mt7530_pad_clk_setup,
.phy_mode_supported = mt7530_phy_mode_supported,
.mac_port_validate = mt7530_mac_port_validate,
.mac_port_get_state = mt7530_phylink_mac_link_state,
-@@ -3286,6 +3358,7 @@ static const struct mt753x_info mt753x_t
+@@ -3475,6 +3547,7 @@ static const struct mt753x_info mt753x_t
.phy_write = mt7531_ind_phy_write,
.pad_setup = mt7531_pad_setup,
.cpu_port_config = mt7531_cpu_port_config,
.phy_mode_supported = mt7531_phy_mode_supported,
.mac_port_validate = mt7531_mac_port_validate,
.mac_port_get_state = mt7531_phylink_mac_link_state,
-@@ -3348,6 +3421,7 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3537,6 +3610,7 @@ mt7530_probe(struct mdio_device *mdiodev
*/
if (!priv->info->sw_setup || !priv->info->pad_setup ||
!priv->info->phy_read || !priv->info->phy_write ||
!priv->info->mac_port_get_state || !priv->info->mac_port_config)
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -796,6 +796,8 @@ struct mt753x_info {
+@@ -807,6 +807,8 @@ struct mt753x_info {
int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
int (*cpu_port_config)(struct dsa_switch *ds, int port);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2525,37 +2525,6 @@ static void mt7530_mac_port_get_caps(str
+@@ -2713,37 +2713,6 @@ static void mt7530_mac_port_get_caps(str
}
}
static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
{
return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
-@@ -2592,44 +2561,6 @@ static void mt7531_mac_port_get_caps(str
+@@ -2780,44 +2749,6 @@ static void mt7531_mac_port_get_caps(str
}
}
static int
mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
{
-@@ -2884,9 +2815,6 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -3072,9 +3003,6 @@ mt753x_phylink_mac_config(struct dsa_swi
struct mt7530_priv *priv = ds->priv;
u32 mcr_cur, mcr_new;
switch (port) {
case 0 ... 4: /* Internal phy */
if (state->interface != PHY_INTERFACE_MODE_GMII)
-@@ -3102,12 +3030,6 @@ mt753x_phylink_validate(struct dsa_switc
+@@ -3290,12 +3218,6 @@ mt753x_phylink_validate(struct dsa_switc
__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
struct mt7530_priv *priv = ds->priv;
phylink_set_port_modes(mask);
if (state->interface != PHY_INTERFACE_MODE_TRGMII &&
-@@ -3334,7 +3256,6 @@ static const struct mt753x_info mt753x_t
+@@ -3523,7 +3445,6 @@ static const struct mt753x_info mt753x_t
.phy_write = mt7530_phy_write,
.pad_setup = mt7530_pad_clk_setup,
.mac_port_get_caps = mt7530_mac_port_get_caps,
.mac_port_validate = mt7530_mac_port_validate,
.mac_port_get_state = mt7530_phylink_mac_link_state,
.mac_port_config = mt7530_mac_config,
-@@ -3346,7 +3267,6 @@ static const struct mt753x_info mt753x_t
+@@ -3535,7 +3456,6 @@ static const struct mt753x_info mt753x_t
.phy_write = mt7530_phy_write,
.pad_setup = mt7530_pad_clk_setup,
.mac_port_get_caps = mt7530_mac_port_get_caps,
.mac_port_validate = mt7530_mac_port_validate,
.mac_port_get_state = mt7530_phylink_mac_link_state,
.mac_port_config = mt7530_mac_config,
-@@ -3359,7 +3279,6 @@ static const struct mt753x_info mt753x_t
+@@ -3548,7 +3468,6 @@ static const struct mt753x_info mt753x_t
.pad_setup = mt7531_pad_setup,
.cpu_port_config = mt7531_cpu_port_config,
.mac_port_get_caps = mt7531_mac_port_get_caps,
.mac_port_validate = mt7531_mac_port_validate,
.mac_port_get_state = mt7531_phylink_mac_link_state,
.mac_port_config = mt7531_mac_config,
-@@ -3422,7 +3341,6 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3611,7 +3530,6 @@ mt7530_probe(struct mdio_device *mdiodev
if (!priv->info->sw_setup || !priv->info->pad_setup ||
!priv->info->phy_read || !priv->info->phy_write ||
!priv->info->mac_port_get_caps ||
return -EINVAL;
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -798,8 +798,6 @@ struct mt753x_info {
+@@ -809,8 +809,6 @@ struct mt753x_info {
int (*cpu_port_config)(struct dsa_switch *ds, int port);
void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
struct phylink_config *config);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3054,11 +3054,6 @@ mt753x_phylink_validate(struct dsa_switc
+@@ -3242,11 +3242,6 @@ mt753x_phylink_validate(struct dsa_switc
linkmode_and(supported, supported, mask);
linkmode_and(state->advertising, state->advertising, mask);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2632,12 +2632,13 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2820,12 +2820,13 @@ static int mt7531_rgmii_setup(struct mt7
}
static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
phylink_set(supported, 2500baseX_Full);
phylink_set(supported, 2500baseT_Full);
}
-@@ -3010,16 +3011,18 @@ static void mt753x_phylink_get_caps(stru
+@@ -3198,16 +3199,18 @@ static void mt753x_phylink_get_caps(stru
static void
mt7530_mac_port_validate(struct dsa_switch *ds, int port,
}
static void
-@@ -3042,12 +3045,13 @@ mt753x_phylink_validate(struct dsa_switc
+@@ -3230,12 +3233,13 @@ mt753x_phylink_validate(struct dsa_switc
}
/* This switch only supports 1G full-duplex. */
phylink_set(mask, Asym_Pause);
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -799,6 +799,7 @@ struct mt753x_info {
+@@ -810,6 +810,7 @@ struct mt753x_info {
void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
struct phylink_config *config);
void (*mac_port_validate)(struct dsa_switch *ds, int port,
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2631,19 +2631,6 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2819,19 +2819,6 @@ static int mt7531_rgmii_setup(struct mt7
return 0;
}
static void
mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
unsigned int mode, phy_interface_t interface,
-@@ -3010,51 +2997,21 @@ static void mt753x_phylink_get_caps(stru
+@@ -3198,51 +3185,21 @@ static void mt753x_phylink_get_caps(stru
}
static void
linkmode_and(supported, supported, mask);
linkmode_and(state->advertising, state->advertising, mask);
-@@ -3255,7 +3212,6 @@ static const struct mt753x_info mt753x_t
+@@ -3444,7 +3401,6 @@ static const struct mt753x_info mt753x_t
.phy_write = mt7530_phy_write,
.pad_setup = mt7530_pad_clk_setup,
.mac_port_get_caps = mt7530_mac_port_get_caps,
.mac_port_get_state = mt7530_phylink_mac_link_state,
.mac_port_config = mt7530_mac_config,
},
-@@ -3266,7 +3222,6 @@ static const struct mt753x_info mt753x_t
+@@ -3455,7 +3411,6 @@ static const struct mt753x_info mt753x_t
.phy_write = mt7530_phy_write,
.pad_setup = mt7530_pad_clk_setup,
.mac_port_get_caps = mt7530_mac_port_get_caps,
.mac_port_get_state = mt7530_phylink_mac_link_state,
.mac_port_config = mt7530_mac_config,
},
-@@ -3278,7 +3233,6 @@ static const struct mt753x_info mt753x_t
+@@ -3467,7 +3422,6 @@ static const struct mt753x_info mt753x_t
.pad_setup = mt7531_pad_setup,
.cpu_port_config = mt7531_cpu_port_config,
.mac_port_get_caps = mt7531_mac_port_get_caps,
.mac_port_get_state = mt7531_phylink_mac_link_state,
.mac_port_config = mt7531_mac_config,
.mac_pcs_an_restart = mt7531_sgmii_restart_an,
-@@ -3340,7 +3294,6 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3529,7 +3483,6 @@ mt7530_probe(struct mdio_device *mdiodev
if (!priv->info->sw_setup || !priv->info->pad_setup ||
!priv->info->phy_read || !priv->info->phy_write ||
!priv->info->mac_port_get_caps ||
/* String, offset, and register size in bytes if different from 4 bytes */
static const struct mt7530_mib_desc mt7530_mib[] = {
MIB_DESC(1, 0x00, "TxDrop"),
-@@ -2631,12 +2636,11 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2819,12 +2824,11 @@ static int mt7531_rgmii_setup(struct mt7
return 0;
}
unsigned int val;
/* For adjusting speed and duplex of SGMII force mode. */
-@@ -2662,6 +2666,9 @@ mt7531_sgmii_link_up_force(struct dsa_sw
+@@ -2850,6 +2854,9 @@ mt7531_sgmii_link_up_force(struct dsa_sw
/* MT7531 SGMII 1G force mode can only work in full duplex mode,
* no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
*/
if ((speed == SPEED_10 || speed == SPEED_100) &&
duplex != DUPLEX_FULL)
-@@ -2737,9 +2744,10 @@ static int mt7531_sgmii_setup_mode_an(st
+@@ -2925,9 +2932,10 @@ static int mt7531_sgmii_setup_mode_an(st
return 0;
}
u32 val;
/* Only restart AN when AN is enabled */
-@@ -2796,6 +2804,24 @@ mt753x_mac_config(struct dsa_switch *ds,
+@@ -2984,6 +2992,24 @@ mt753x_mac_config(struct dsa_switch *ds,
return priv->info->mac_port_config(ds, port, mode, state->interface);
}
static void
mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
const struct phylink_link_state *state)
-@@ -2857,17 +2883,6 @@ unsupported:
+@@ -3045,17 +3071,6 @@ unsupported:
mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
}
static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
unsigned int mode,
phy_interface_t interface)
-@@ -2877,16 +2892,13 @@ static void mt753x_phylink_mac_link_down
+@@ -3065,16 +3080,13 @@ static void mt753x_phylink_mac_link_down
mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
}
}
static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
-@@ -2899,8 +2911,6 @@ static void mt753x_phylink_mac_link_up(s
+@@ -3087,8 +3099,6 @@ static void mt753x_phylink_mac_link_up(s
struct mt7530_priv *priv = ds->priv;
u32 mcr;
mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
/* MT753x MAC works in 1G full duplex mode for all up-clocked
-@@ -2978,6 +2988,8 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3166,6 +3176,8 @@ mt7531_cpu_port_config(struct dsa_switch
return ret;
mt7530_write(priv, MT7530_PMCR_P(port),
PMCR_CPU_PORT_SETTING(priv->id));
mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
speed, DUPLEX_FULL, true, true);
-@@ -3017,16 +3029,13 @@ mt753x_phylink_validate(struct dsa_switc
+@@ -3205,16 +3217,13 @@ mt753x_phylink_validate(struct dsa_switc
linkmode_and(state->advertising, state->advertising, mask);
}
pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
state->link = (pmsr & PMSR_LINK);
-@@ -3053,8 +3062,6 @@ mt7530_phylink_mac_link_state(struct dsa
+@@ -3241,8 +3250,6 @@ mt7530_phylink_mac_link_state(struct dsa
state->pause |= MLO_PAUSE_RX;
if (pmsr & PMSR_TX_FC)
state->pause |= MLO_PAUSE_TX;
}
static int
-@@ -3096,32 +3103,49 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
+@@ -3284,32 +3291,49 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
return 0;
}
if (ret)
return ret;
-@@ -3134,6 +3158,13 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3322,6 +3346,13 @@ mt753x_setup(struct dsa_switch *ds)
if (ret && priv->irq)
mt7530_free_irq_common(priv);
return ret;
}
-@@ -3195,9 +3226,8 @@ static const struct dsa_switch_ops mt753
+@@ -3384,9 +3415,8 @@ static const struct dsa_switch_ops mt753
.port_mirror_del = mt753x_port_mirror_del,
.phylink_get_caps = mt753x_phylink_get_caps,
.phylink_validate = mt753x_phylink_validate,
.phylink_mac_link_down = mt753x_phylink_mac_link_down,
.phylink_mac_link_up = mt753x_phylink_mac_link_up,
.get_mac_eee = mt753x_get_mac_eee,
-@@ -3207,36 +3237,34 @@ static const struct dsa_switch_ops mt753
+@@ -3396,36 +3426,34 @@ static const struct dsa_switch_ops mt753
static const struct mt753x_info mt753x_table[] = {
[ID_MT7621] = {
.id = ID_MT7621,
},
};
-@@ -3294,7 +3322,7 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3483,7 +3511,7 @@ mt7530_probe(struct mdio_device *mdiodev
if (!priv->info->sw_setup || !priv->info->pad_setup ||
!priv->info->phy_read || !priv->info->phy_write ||
!priv->info->mac_port_get_caps ||
priv->id = priv->info->id;
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -768,6 +768,12 @@ static const char *p5_intf_modes(unsigne
+@@ -779,6 +779,12 @@ static const char *p5_intf_modes(unsigne
struct mt7530_priv;
/* struct mt753x_info - This is the main data structure for holding the specific
* part for each supported device
* @sw_setup: Holding the handler to a device initialization
-@@ -779,18 +785,14 @@ struct mt7530_priv;
+@@ -790,18 +796,14 @@ struct mt7530_priv;
* port
* @mac_port_validate: Holding the way to set addition validate type for a
* certan MAC port
int (*sw_setup)(struct dsa_switch *ds);
int (*phy_read)(struct mt7530_priv *priv, int port, int regnum);
int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
-@@ -801,15 +803,9 @@ struct mt753x_info {
+@@ -812,15 +814,9 @@ struct mt753x_info {
void (*mac_port_validate)(struct dsa_switch *ds, int port,
phy_interface_t interface,
unsigned long *supported);
};
/* struct mt7530_priv - This is the main data structure for holding the state
-@@ -851,6 +847,7 @@ struct mt7530_priv {
+@@ -862,6 +858,7 @@ struct mt7530_priv {
u8 mirror_tx;
struct mt7530_port ports[MT7530_NUM_PORTS];
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3008,25 +3008,16 @@ static void mt753x_phylink_get_caps(stru
+@@ -3196,25 +3196,16 @@ static void mt753x_phylink_get_caps(stru
priv->info->mac_port_get_caps(ds, port, config);
}
}
static void mt7530_pcs_get_state(struct phylink_pcs *pcs,
-@@ -3128,12 +3119,14 @@ static void mt7530_pcs_an_restart(struct
+@@ -3316,12 +3307,14 @@ static void mt7530_pcs_an_restart(struct
}
static const struct phylink_pcs_ops mt7530_pcs_ops = {
.pcs_get_state = mt7531_pcs_get_state,
.pcs_config = mt753x_pcs_config,
.pcs_an_restart = mt7531_pcs_an_restart,
-@@ -3225,7 +3218,6 @@ static const struct dsa_switch_ops mt753
+@@ -3414,7 +3407,6 @@ static const struct dsa_switch_ops mt753
.port_mirror_add = mt753x_port_mirror_add,
.port_mirror_del = mt753x_port_mirror_del,
.phylink_get_caps = mt753x_phylink_get_caps,
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3005,6 +3005,12 @@ static void mt753x_phylink_get_caps(stru
+@@ -3193,6 +3193,12 @@ static void mt753x_phylink_get_caps(stru
config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
MAC_10 | MAC_100 | MAC_1000FD;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3143,9 +3143,16 @@ static int
+@@ -3331,9 +3331,16 @@ static int
mt753x_setup(struct dsa_switch *ds)
{
struct mt7530_priv *priv = ds->priv;
if (ret)
return ret;
-@@ -3157,13 +3164,6 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3345,13 +3352,6 @@ mt753x_setup(struct dsa_switch *ds)
if (ret && priv->irq)
mt7530_free_irq_common(priv);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -1589,11 +1589,11 @@ static void
+@@ -1771,11 +1771,11 @@ static void
mt7530_hw_vlan_add(struct mt7530_priv *priv,
struct mt7530_hw_vlan_entry *entry)
{
/* Validate the entry with independent learning, create egress tag per
* VLAN and joining the port as one of the port members.
-@@ -1604,22 +1604,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p
+@@ -1786,22 +1786,20 @@ mt7530_hw_vlan_add(struct mt7530_priv *p
/* Decide whether adding tag or not for those outgoing packets from the
* port inside the VLAN.
}
static void
-@@ -1638,11 +1636,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p
+@@ -1820,11 +1818,7 @@ mt7530_hw_vlan_del(struct mt7530_priv *p
return;
}
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -1093,6 +1093,7 @@ static int
+@@ -1275,6 +1275,7 @@ static int
mt7530_port_enable(struct dsa_switch *ds, int port,
struct phy_device *phy)
{
struct mt7530_priv *priv = ds->priv;
mutex_lock(&priv->reg_mutex);
-@@ -1101,7 +1102,11 @@ mt7530_port_enable(struct dsa_switch *ds
+@@ -1283,7 +1284,11 @@ mt7530_port_enable(struct dsa_switch *ds
* restore the port matrix if the port is the member of a certain
* bridge.
*/
priv->ports[port].enable = true;
mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
priv->ports[port].pm);
-@@ -1249,7 +1254,8 @@ mt7530_port_bridge_join(struct dsa_switc
+@@ -1431,7 +1436,8 @@ mt7530_port_bridge_join(struct dsa_switc
struct net_device *bridge)
{
struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
struct mt7530_priv *priv = ds->priv;
mutex_lock(&priv->reg_mutex);
-@@ -1326,9 +1332,12 @@ mt7530_port_set_vlan_unaware(struct dsa_
+@@ -1508,9 +1514,12 @@ mt7530_port_set_vlan_unaware(struct dsa_
* the CPU port get out of VLAN filtering mode.
*/
if (all_user_ports_removed) {
| PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
}
}
-@@ -1378,6 +1387,7 @@ mt7530_port_bridge_leave(struct dsa_swit
+@@ -1560,6 +1569,7 @@ mt7530_port_bridge_leave(struct dsa_swit
struct net_device *bridge)
{
struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
struct mt7530_priv *priv = ds->priv;
mutex_lock(&priv->reg_mutex);
-@@ -1406,8 +1416,8 @@ mt7530_port_bridge_leave(struct dsa_swit
+@@ -1588,8 +1598,8 @@ mt7530_port_bridge_leave(struct dsa_swit
*/
if (priv->ports[port].enable)
mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
/* When a port is removed from the bridge, the port would be set up
* back to the default as is at initial boot which is a VLAN-unaware
-@@ -1570,6 +1580,9 @@ static int
+@@ -1752,6 +1762,9 @@ static int
mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
struct netlink_ext_ack *extack)
{
if (vlan_filtering) {
/* The port is being kept as VLAN-unaware port when bridge is
* set up with vlan_filtering not being set, Otherwise, the
-@@ -1577,7 +1590,7 @@ mt7530_port_vlan_filtering(struct dsa_sw
+@@ -1759,7 +1772,7 @@ mt7530_port_vlan_filtering(struct dsa_sw
* for becoming a VLAN-aware port.
*/
mt7530_port_set_vlan_aware(ds, port);
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -11783,6 +11783,14 @@ L: netdev@vger.kernel.org
+@@ -11790,6 +11790,14 @@ L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ethernet/mediatek/
--- a/net/dsa/dsa2.c
+++ b/net/dsa/dsa2.c
-@@ -1034,6 +1034,8 @@ static int dsa_tree_setup_master(struct
+@@ -1056,6 +1056,8 @@ static int dsa_tree_setup_master(struct
struct dsa_port *dp;
int err;
list_for_each_entry(dp, &dst->ports, list) {
if (dsa_port_is_cpu(dp)) {
err = dsa_master_setup(dp->master, dp);
-@@ -1042,6 +1044,8 @@ static int dsa_tree_setup_master(struct
+@@ -1064,6 +1066,8 @@ static int dsa_tree_setup_master(struct
}
}
return 0;
}
-@@ -1049,9 +1053,13 @@ static void dsa_tree_teardown_master(str
+@@ -1071,9 +1075,13 @@ static void dsa_tree_teardown_master(str
{
struct dsa_port *dp;
--- a/net/dsa/dsa2.c
+++ b/net/dsa/dsa2.c
-@@ -999,23 +999,28 @@ static void dsa_tree_teardown_switches(s
+@@ -1021,23 +1021,28 @@ static void dsa_tree_teardown_switches(s
dsa_switch_teardown(dp->ds);
}
}
}
-@@ -1024,7 +1029,21 @@ static int dsa_tree_setup_switches(struc
+@@ -1046,7 +1051,21 @@ static int dsa_tree_setup_switches(struc
teardown:
dsa_tree_teardown_ports(dst);
return err;
}
-@@ -1111,10 +1130,14 @@ static int dsa_tree_setup(struct dsa_swi
+@@ -1133,10 +1152,14 @@ static int dsa_tree_setup(struct dsa_swi
if (err)
goto teardown_cpu_ports;
err = dsa_tree_setup_lags(dst);
if (err)
goto teardown_master;
-@@ -1127,8 +1150,9 @@ static int dsa_tree_setup(struct dsa_swi
+@@ -1149,8 +1172,9 @@ static int dsa_tree_setup(struct dsa_swi
teardown_master:
dsa_tree_teardown_master(dst);
--- a/net/dsa/dsa2.c
+++ b/net/dsa/dsa2.c
-@@ -545,6 +545,7 @@ static void dsa_port_teardown(struct dsa
+@@ -567,6 +567,7 @@ static void dsa_port_teardown(struct dsa
struct devlink_port *dlp = &dp->devlink_port;
struct dsa_switch *ds = dp->ds;
struct dsa_mac_addr *a, *tmp;
if (!dp->setup)
return;
-@@ -566,9 +567,11 @@ static void dsa_port_teardown(struct dsa
+@@ -588,9 +589,11 @@ static void dsa_port_teardown(struct dsa
dsa_port_link_unregister_of(dp);
break;
case DSA_PORT_TYPE_USER:
}
break;
}
-@@ -1130,17 +1133,17 @@ static int dsa_tree_setup(struct dsa_swi
+@@ -1152,17 +1155,17 @@ static int dsa_tree_setup(struct dsa_swi
if (err)
goto teardown_cpu_ports;
dst->setup = true;
-@@ -1148,10 +1151,10 @@ static int dsa_tree_setup(struct dsa_swi
+@@ -1170,10 +1173,10 @@ static int dsa_tree_setup(struct dsa_swi
return 0;
teardown_switches:
dsa_tree_teardown_switches(dst);
teardown_cpu_ports:
-@@ -1169,10 +1172,10 @@ static void dsa_tree_teardown(struct dsa
+@@ -1191,10 +1194,10 @@ static void dsa_tree_teardown(struct dsa
dsa_tree_teardown_lags(dst);
static inline bool dsa_is_unused_port(struct dsa_switch *ds, int p)
{
return dsa_to_port(ds, p)->type == DSA_PORT_TYPE_UNUSED;
-@@ -949,6 +959,13 @@ struct dsa_switch_ops {
+@@ -957,6 +967,13 @@ struct dsa_switch_ops {
int (*tag_8021q_vlan_add)(struct dsa_switch *ds, int port, u16 vid,
u16 flags);
int (*tag_8021q_vlan_del)(struct dsa_switch *ds, int port, u16 vid);
#define DSA_DEVLINK_PARAM_DRIVER(_id, _name, _type, _cmodes) \
--- a/net/dsa/dsa2.c
+++ b/net/dsa/dsa2.c
-@@ -1275,6 +1275,52 @@ out_unlock:
+@@ -1297,6 +1297,52 @@ out_unlock:
return err;
}
#include "dsa_priv.h"
-@@ -1060,9 +1061,18 @@ static int dsa_tree_setup_master(struct
+@@ -1082,9 +1083,18 @@ static int dsa_tree_setup_master(struct
list_for_each_entry(dp, &dst->ports, list) {
if (dsa_port_is_cpu(dp)) {
}
}
-@@ -1077,9 +1087,19 @@ static void dsa_tree_teardown_master(str
+@@ -1099,9 +1109,19 @@ static void dsa_tree_teardown_master(str
rtnl_lock();
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2791,9 +2791,6 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2979,9 +2979,6 @@ mt7531_mac_config(struct dsa_switch *ds,
case PHY_INTERFACE_MODE_NA:
case PHY_INTERFACE_MODE_1000BASEX:
case PHY_INTERFACE_MODE_2500BASEX:
return mt7531_sgmii_setup_mode_force(priv, port, interface);
default:
return -EINVAL;
-@@ -2869,13 +2866,6 @@ unsupported:
+@@ -3057,13 +3054,6 @@ unsupported:
return;
}
mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
mcr_new = mcr_cur;
mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
-@@ -3012,6 +3002,9 @@ static void mt753x_phylink_get_caps(stru
+@@ -3200,6 +3190,9 @@ static void mt753x_phylink_get_caps(stru
config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
MAC_10 | MAC_100 | MAC_1000FD;
/* This driver does not make use of the speed, duplex, pause or the
* advertisement in its mac_config, so it is safe to mark this driver
* as non-legacy.
-@@ -3077,6 +3070,7 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
+@@ -3265,6 +3258,7 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
state->link = !!(status & MT7531_SGMII_LINK_STATUS);
if (state->interface == PHY_INTERFACE_MODE_SGMII &&
(status & MT7531_SGMII_AN_ENABLE)) {
val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
-@@ -3107,16 +3101,44 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
+@@ -3295,16 +3289,44 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
return 0;
}
}
static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
-@@ -3157,6 +3179,8 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3345,6 +3367,8 @@ mt753x_setup(struct dsa_switch *ds)
priv->pcs[i].pcs.ops = priv->info->pcs_ops;
priv->pcs[i].priv = priv;
priv->pcs[i].port = i;
ret = priv->info->sw_setup(ds);
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -400,6 +400,7 @@ enum mt7530_vlan_port_acc_frm {
+@@ -410,6 +410,7 @@ enum mt7530_vlan_port_acc_frm {
#define MT7531_SGMII_LINK_STATUS BIT(18)
#define MT7531_SGMII_AN_ENABLE BIT(12)
#define MT7531_SGMII_AN_RESTART BIT(9)
#include <linux/phylink.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
-@@ -2643,128 +2644,11 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2831,128 +2832,11 @@ static int mt7531_rgmii_setup(struct mt7
return 0;
}
static int
mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
phy_interface_t interface)
-@@ -2787,11 +2671,11 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2975,11 +2859,11 @@ mt7531_mac_config(struct dsa_switch *ds,
phydev = dp->slave->phydev;
return mt7531_rgmii_setup(priv, port, interface, phydev);
case PHY_INTERFACE_MODE_SGMII:
default:
return -EINVAL;
}
-@@ -2816,11 +2700,11 @@ mt753x_phylink_mac_select_pcs(struct dsa
+@@ -3004,11 +2888,11 @@ mt753x_phylink_mac_select_pcs(struct dsa
switch (interface) {
case PHY_INTERFACE_MODE_TRGMII:
default:
return NULL;
}
-@@ -3061,86 +2945,6 @@ static void mt7530_pcs_get_state(struct
+@@ -3249,86 +3133,6 @@ static void mt7530_pcs_get_state(struct
state->pause |= MLO_PAUSE_TX;
}
static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
phy_interface_t interface,
const unsigned long *advertising,
-@@ -3160,18 +2964,57 @@ static const struct phylink_pcs_ops mt75
+@@ -3348,18 +3152,57 @@ static const struct phylink_pcs_ops mt75
.pcs_an_restart = mt7530_pcs_an_restart,
};
int i, ret;
/* Initialise the PCS devices */
-@@ -3179,8 +3022,6 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3367,8 +3210,6 @@ mt753x_setup(struct dsa_switch *ds)
priv->pcs[i].pcs.ops = priv->info->pcs_ops;
priv->pcs[i].priv = priv;
priv->pcs[i].port = i;
}
ret = priv->info->sw_setup(ds);
-@@ -3195,6 +3036,16 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3383,6 +3224,16 @@ mt753x_setup(struct dsa_switch *ds)
if (ret && priv->irq)
mt7530_free_irq_common(priv);
return ret;
}
-@@ -3286,7 +3137,7 @@ static const struct mt753x_info mt753x_t
+@@ -3475,7 +3326,7 @@ static const struct mt753x_info mt753x_t
},
[ID_MT7531] = {
.id = ID_MT7531,
.sw_setup = mt7531_setup,
.phy_read = mt7531_ind_phy_read,
.phy_write = mt7531_ind_phy_write,
-@@ -3394,7 +3245,7 @@ static void
+@@ -3583,7 +3434,7 @@ static void
mt7530_remove(struct mdio_device *mdiodev)
{
struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
if (!priv)
return;
-@@ -3413,6 +3264,10 @@ mt7530_remove(struct mdio_device *mdiode
+@@ -3602,6 +3453,10 @@ mt7530_remove(struct mdio_device *mdiode
mt7530_free_irq(priv);
dsa_unregister_switch(priv->ds);
dev_set_drvdata(&mdiodev->dev, NULL);
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -391,47 +391,8 @@ enum mt7530_vlan_port_acc_frm {
+@@ -401,47 +401,8 @@ enum mt7530_vlan_port_acc_frm {
CCR_TX_OCT_CNT_BAD)
/* MT7531 SGMII register group */
/* Register for system reset */
#define MT7530_SYS_CTRL 0x7000
-@@ -730,13 +691,13 @@ struct mt7530_fdb {
+@@ -741,13 +702,13 @@ struct mt7530_fdb {
* @pm: The matrix used to show all connections with the port.
* @pvid: The VLAN specified is to be considered a PVID at ingress. Any
* untagged frames will be assigned to the related VLAN.
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2996,26 +2996,56 @@ static const struct regmap_bus mt7531_re
+@@ -3184,26 +3184,56 @@ static const struct regmap_bus mt7531_re
.reg_update_bits = mt7530_regmap_update_bits,
};
int i, ret;
/* Initialise the PCS devices */
-@@ -3037,15 +3067,11 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3225,15 +3255,11 @@ mt753x_setup(struct dsa_switch *ds)
if (ret && priv->irq)
mt7530_free_irq_common(priv);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2969,7 +2969,7 @@ static int mt7530_regmap_read(void *cont
+@@ -3157,7 +3157,7 @@ static int mt7530_regmap_read(void *cont
{
struct mt7530_priv *priv = context;
return 0;
};
-@@ -2977,23 +2977,25 @@ static int mt7530_regmap_write(void *con
+@@ -3165,23 +3165,25 @@ static int mt7530_regmap_write(void *con
{
struct mt7530_priv *priv = context;
};
static int
-@@ -3019,6 +3021,9 @@ mt7531_create_sgmii(struct mt7530_priv *
+@@ -3207,6 +3209,9 @@ mt7531_create_sgmii(struct mt7530_priv *
mt7531_pcs_config[i]->reg_stride = 4;
mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
mt7531_pcs_config[i]->max_register = 0x17c;
}
static void
-@@ -2965,22 +2986,6 @@ static const struct phylink_pcs_ops mt75
+@@ -3153,22 +3174,6 @@ static const struct phylink_pcs_ops mt75
.pcs_an_restart = mt7530_pcs_an_restart,
};
static void
mt7530_mdio_regmap_lock(void *mdio_lock)
{
-@@ -2993,7 +2998,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc
+@@ -3181,7 +3186,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc
mutex_unlock(mdio_lock);
}
.reg_write = mt7530_regmap_write,
.reg_read = mt7530_regmap_read,
};
-@@ -3026,7 +3031,7 @@ mt7531_create_sgmii(struct mt7530_priv *
+@@ -3214,7 +3219,7 @@ mt7531_create_sgmii(struct mt7530_priv *
mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
regmap = devm_regmap_init(priv->dev,
mt7531_pcs_config[i]);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
-@@ -3191,6 +3196,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match)
+@@ -3380,6 +3385,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match)
static int
mt7530_probe(struct mdio_device *mdiodev)
{
struct mt7530_priv *priv;
struct device_node *dn;
-@@ -3270,6 +3276,21 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3459,6 +3465,21 @@ mt7530_probe(struct mdio_device *mdiodev
mutex_init(&priv->reg_mutex);
dev_set_drvdata(&mdiodev->dev, priv);
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -774,6 +774,7 @@ struct mt753x_info {
+@@ -785,6 +785,7 @@ struct mt753x_info {
* @dev: The device pointer
* @ds: The pointer to the dsa core structure
* @bus: The bus used for the device and built-in PHY
* @rstc: The pointer to reset control used by MCM
* @core_pwr: The power supplied into the core
* @io_pwr: The power supplied into the I/O
-@@ -794,6 +795,7 @@ struct mt7530_priv {
+@@ -805,6 +806,7 @@ struct mt7530_priv {
struct device *dev;
struct dsa_switch *ds;
struct mii_bus *bus;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3077,12 +3077,6 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3265,12 +3265,6 @@ mt753x_setup(struct dsa_switch *ds)
if (ret && priv->irq)
mt7530_free_irq_common(priv);
return ret;
}
-@@ -3199,6 +3193,7 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3388,6 +3382,7 @@ mt7530_probe(struct mdio_device *mdiodev
static struct regmap_config *regmap_config;
struct mt7530_priv *priv;
struct device_node *dn;
dn = mdiodev->dev.of_node;
-@@ -3291,6 +3286,12 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3480,6 +3475,12 @@ mt7530_probe(struct mdio_device *mdiodev
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
}
static void
-@@ -646,14 +650,13 @@ static int
+@@ -660,14 +664,13 @@ static int
mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
int regnum)
{
ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
!(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -686,7 +689,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr
+@@ -700,7 +703,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr
ret = val & MT7531_MDIO_RW_DATA_MASK;
out:
return ret;
}
-@@ -695,14 +698,13 @@ static int
+@@ -709,14 +712,13 @@ static int
mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
int regnum, u32 data)
{
ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
!(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -734,7 +736,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p
+@@ -748,7 +750,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p
}
out:
return ret;
}
-@@ -742,14 +744,13 @@ out:
+@@ -756,14 +758,13 @@ out:
static int
mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
{
ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
!(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -772,7 +773,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr
+@@ -786,7 +787,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr
ret = val & MT7531_MDIO_RW_DATA_MASK;
out:
return ret;
}
-@@ -781,14 +782,13 @@ static int
+@@ -795,14 +796,13 @@ static int
mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
u16 data)
{
ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
!(reg & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -810,7 +810,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p
+@@ -824,7 +824,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p
}
out:
return ret;
}
-@@ -1162,7 +1162,6 @@ static int
+@@ -1344,7 +1344,6 @@ static int
mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
{
struct mt7530_priv *priv = ds->priv;
int length;
u32 val;
-@@ -1173,7 +1172,7 @@ mt7530_port_change_mtu(struct dsa_switch
+@@ -1355,7 +1354,7 @@ mt7530_port_change_mtu(struct dsa_switch
if (!dsa_is_cpu_port(ds, port))
return 0;
val = mt7530_mii_read(priv, MT7530_GMACCR);
val &= ~MAX_RX_PKT_LEN_MASK;
-@@ -1194,7 +1193,7 @@ mt7530_port_change_mtu(struct dsa_switch
+@@ -1376,7 +1375,7 @@ mt7530_port_change_mtu(struct dsa_switch
mt7530_mii_write(priv, MT7530_GMACCR, val);
return 0;
}
-@@ -1990,10 +1989,10 @@ mt7530_irq_thread_fn(int irq, void *dev_
+@@ -2172,10 +2171,10 @@ mt7530_irq_thread_fn(int irq, void *dev_
u32 val;
int p;
for (p = 0; p < MT7530_NUM_PHYS; p++) {
if (BIT(p) & val) {
-@@ -2029,7 +2028,7 @@ mt7530_irq_bus_lock(struct irq_data *d)
+@@ -2211,7 +2210,7 @@ mt7530_irq_bus_lock(struct irq_data *d)
{
struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
}
static void
-@@ -2038,7 +2037,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da
+@@ -2220,7 +2219,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da
struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -951,6 +951,24 @@ mt7530_set_ageing_time(struct dsa_switch
+@@ -965,6 +965,24 @@ mt7530_set_ageing_time(struct dsa_switch
return 0;
}
struct mt7530_priv *priv = ds->priv;
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -709,24 +709,6 @@ enum p5_interface_select {
+@@ -720,24 +720,6 @@ enum p5_interface_select {
P5_INTF_SEL_GMAC5_SGMII,
};
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3205,44 +3205,21 @@ static const struct of_device_id mt7530_
+@@ -3394,44 +3394,21 @@ static const struct of_device_id mt7530_
MODULE_DEVICE_TABLE(of, mt7530_of_match);
static int
if (!priv->info)
return -EINVAL;
-@@ -3256,23 +3233,53 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3445,23 +3422,53 @@ mt7530_probe(struct mdio_device *mdiodev
return -EINVAL;
priv->id = priv->info->id;
priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(priv->reset)) {
-@@ -3281,12 +3288,15 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3470,12 +3477,15 @@ mt7530_probe(struct mdio_device *mdiodev
}
}
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3323,6 +3323,17 @@ mt7530_probe(struct mdio_device *mdiodev
+@@ -3512,6 +3512,17 @@ mt7530_probe(struct mdio_device *mdiodev
}
static void
mt7530_remove(struct mdio_device *mdiodev)
{
struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
-@@ -3341,16 +3352,11 @@ mt7530_remove(struct mdio_device *mdiode
+@@ -3530,16 +3541,11 @@ mt7530_remove(struct mdio_device *mdiode
dev_err(priv->dev, "Failed to disable io pwr: %d\n",
ret);
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -11895,6 +11895,7 @@ M: Landen Chao <Landen.Chao@mediatek.com
+@@ -11902,6 +11902,7 @@ M: Landen Chao <Landen.Chao@mediatek.com
M: DENG Qingfang <dqfext@gmail.com>
L: netdev@vger.kernel.org
S: Maintained
static u32
mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
{
-@@ -3003,72 +2954,6 @@ static const struct phylink_pcs_ops mt75
+@@ -3191,72 +3142,6 @@ static const struct phylink_pcs_ops mt75
.pcs_an_restart = mt7530_pcs_an_restart,
};
static int
mt753x_setup(struct dsa_switch *ds)
{
-@@ -3127,7 +3012,7 @@ static int mt753x_set_mac_eee(struct dsa
+@@ -3315,7 +3200,7 @@ static int mt753x_set_mac_eee(struct dsa
return 0;
}
+const struct dsa_switch_ops mt7530_switch_ops = {
.get_tag_protocol = mtk_get_tag_protocol,
.setup = mt753x_setup,
- .get_strings = mt7530_get_strings,
-@@ -3161,8 +3046,9 @@ static const struct dsa_switch_ops mt753
+ .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port,
+@@ -3350,8 +3235,9 @@ static const struct dsa_switch_ops mt753
.get_mac_eee = mt753x_get_mac_eee,
.set_mac_eee = mt753x_set_mac_eee,
};
[ID_MT7621] = {
.id = ID_MT7621,
.pcs_ops = &mt7530_pcs_ops,
-@@ -3195,16 +3081,9 @@ static const struct mt753x_info mt753x_t
+@@ -3384,16 +3270,9 @@ static const struct mt753x_info mt753x_t
.mac_port_config = mt7531_mac_config,
},
};
mt7530_probe_common(struct mt7530_priv *priv)
{
struct device *dev = priv->dev;
-@@ -3241,88 +3120,9 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3430,88 +3309,9 @@ mt7530_probe_common(struct mt7530_priv *
return 0;
}
mt7530_remove_common(struct mt7530_priv *priv)
{
if (priv->irq)
-@@ -3333,57 +3133,6 @@ mt7530_remove_common(struct mt7530_priv
+@@ -3522,57 +3322,6 @@ mt7530_remove_common(struct mt7530_priv
mutex_destroy(&priv->reg_mutex);
}
MODULE_LICENSE("GPL");
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -834,4 +834,10 @@ static inline void INIT_MT7530_DUMMY_POL
+@@ -845,4 +845,10 @@ static inline void INIT_MT7530_DUMMY_POL
p->reg = reg;
}
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -11893,9 +11893,11 @@ MEDIATEK SWITCH DRIVER
+@@ -11900,9 +11900,11 @@ MEDIATEK SWITCH DRIVER
M: Sean Wang <sean.wang@mediatek.com>
M: Landen Chao <Landen.Chao@mediatek.com>
M: DENG Qingfang <dqfext@gmail.com>
+MODULE_LICENSE("GPL");
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2037,6 +2037,47 @@ static const struct irq_domain_ops mt753
+@@ -2219,6 +2219,47 @@ static const struct irq_domain_ops mt753
};
static void
mt7530_setup_mdio_irq(struct mt7530_priv *priv)
{
struct dsa_switch *ds = priv->ds;
-@@ -2070,8 +2111,15 @@ mt7530_setup_irq(struct mt7530_priv *pri
+@@ -2252,8 +2293,15 @@ mt7530_setup_irq(struct mt7530_priv *pri
return priv->irq ? : -EINVAL;
}
if (!priv->irq_domain) {
dev_err(dev, "failed to create IRQ domain\n");
return -ENOMEM;
-@@ -2566,6 +2614,25 @@ static void mt7531_mac_port_get_caps(str
+@@ -2754,6 +2802,25 @@ static void mt7531_mac_port_get_caps(str
}
}
static int
mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
{
-@@ -2642,6 +2709,17 @@ static bool mt753x_is_mac_port(u32 port)
+@@ -2830,6 +2897,17 @@ static bool mt753x_is_mac_port(u32 port)
}
static int
mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
phy_interface_t interface)
{
-@@ -2711,7 +2789,8 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2899,7 +2977,8 @@ mt753x_phylink_mac_config(struct dsa_swi
switch (port) {
case 0 ... 4: /* Internal phy */
goto unsupported;
break;
case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
-@@ -2789,7 +2868,8 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2977,7 +3056,8 @@ static void mt753x_phylink_mac_link_up(s
/* MT753x MAC works in 1G full duplex mode for all up-clocked
* variants.
*/
(phy_interface_mode_is_8023z(interface))) {
speed = SPEED_1000;
duplex = DUPLEX_FULL;
-@@ -2869,6 +2949,21 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3057,6 +3137,21 @@ mt7531_cpu_port_config(struct dsa_switch
return 0;
}
static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
struct phylink_config *config)
{
-@@ -3014,6 +3109,27 @@ static int mt753x_set_mac_eee(struct dsa
+@@ -3202,6 +3297,27 @@ static int mt753x_set_mac_eee(struct dsa
return 0;
}
const struct dsa_switch_ops mt7530_switch_ops = {
.get_tag_protocol = mtk_get_tag_protocol,
.setup = mt753x_setup,
-@@ -3082,6 +3198,17 @@ const struct mt753x_info mt753x_table[]
+@@ -3271,6 +3387,17 @@ const struct mt753x_info mt753x_table[]
.mac_port_get_caps = mt7531_mac_port_get_caps,
.mac_port_config = mt7531_mac_config,
},
};
#define NUM_TRGMII_CTRL 5
-@@ -54,11 +55,11 @@ enum mt753x_id {
- #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
+@@ -59,11 +60,11 @@ enum mt753x_id {
#define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
+ #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
-#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
+#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
MT7531_MIRROR_MASK : MIRROR_MASK)
/* Registers for BPDU and PAE frame control*/
-@@ -322,9 +323,8 @@ enum mt7530_vlan_port_acc_frm {
+@@ -332,9 +333,8 @@ enum mt7530_vlan_port_acc_frm {
MT7531_FORCE_DPX | \
MT7531_FORCE_RX_FC | \
MT7531_FORCE_TX_FC)
}
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -3076,6 +3076,12 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3264,6 +3264,12 @@ mt753x_setup(struct dsa_switch *ds)
if (ret && priv->irq)
mt7530_free_irq_common(priv);
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -768,10 +768,10 @@ struct mt753x_info {
+@@ -779,10 +779,10 @@ struct mt753x_info {
* registers
* @p6_interface Holding the current port 6 interface
* @p5_intf_sel: Holding the current port 5 interface select
*/
struct mt7530_priv {
struct device *dev;
-@@ -790,7 +790,6 @@ struct mt7530_priv {
+@@ -801,7 +801,6 @@ struct mt7530_priv {
unsigned int p5_intf_sel;
u8 mirror_rx;
u8 mirror_tx;
struct mt7530_port ports[MT7530_NUM_PORTS];
struct mt753x_pcs pcs[MT7530_NUM_PORTS];
/* protect among processes for registers access*/
-@@ -798,6 +797,7 @@ struct mt7530_priv {
+@@ -809,6 +808,7 @@ struct mt7530_priv {
int irq;
struct irq_domain *irq_domain;
u32 irq_enable;
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -12694,6 +12694,7 @@ F: include/uapi/linux/meye.h
+@@ -12701,6 +12701,7 @@ F: include/uapi/linux/meye.h
MOTORCOMM PHY DRIVER
M: Peter Geis <pgwipeout@gmail.com>
--- /dev/null
+From 2203718c2f59ffdd6c78d54e5add594aebb4461e Mon Sep 17 00:00:00 2001
+From: Georgi Valkov <gvalkov@gmail.com>
+Date: Wed, 7 Jun 2023 15:56:59 +0200
+Subject: [PATCH 1/4] usbnet: ipheth: fix risk of NULL pointer deallocation
+
+The cleanup precedure in ipheth_probe will attempt to free a
+NULL pointer in dev->ctrl_buf if the memory allocation for
+this buffer is not successful. While kfree ignores NULL pointers,
+and the existing code is safe, it is a better design to rearrange
+the goto labels and avoid this.
+
+Signed-off-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -510,8 +510,8 @@ err_register_netdev:
+ ipheth_free_urbs(dev);
+ err_alloc_urbs:
+ err_get_macaddr:
+-err_alloc_ctrl_buf:
+ kfree(dev->ctrl_buf);
++err_alloc_ctrl_buf:
+ err_endpoints:
+ free_netdev(netdev);
+ return retval;
--- /dev/null
+From 3e65efcca87a9bb5f3b864e0a43d167bc0a8688c Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:00 +0200
+Subject: [PATCH 2/4] usbnet: ipheth: transmit URBs without trailing padding
+
+The behaviour of the official iOS tethering driver on macOS is to not
+transmit any trailing padding at the end of URBs. This is applicable
+to both NCM and legacy modes, including older devices.
+
+Adapt the driver to not include trailing padding in TX URBs, matching
+the behaviour of the official macOS driver.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Tested-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -373,12 +373,10 @@ static netdev_tx_t ipheth_tx(struct sk_b
+ }
+
+ memcpy(dev->tx_buf, skb->data, skb->len);
+- if (skb->len < IPHETH_BUF_SIZE)
+- memset(dev->tx_buf + skb->len, 0, IPHETH_BUF_SIZE - skb->len);
+
+ usb_fill_bulk_urb(dev->tx_urb, udev,
+ usb_sndbulkpipe(udev, dev->bulk_out),
+- dev->tx_buf, IPHETH_BUF_SIZE,
++ dev->tx_buf, skb->len,
+ ipheth_sndbulk_callback,
+ dev);
+ dev->tx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
--- /dev/null
+From a2d274c62e44b1995c170595db3865c6fe701226 Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:01 +0200
+Subject: [PATCH 3/4] usbnet: ipheth: add CDC NCM support
+
+Recent iOS releases support CDC NCM encapsulation on RX. This mode is
+the default on macOS and Windows. In this mode, an iOS device may include
+one or more Ethernet frames inside a single URB.
+
+Freshly booted iOS devices start in legacy mode, but are put into
+NCM mode by the official Apple driver. When reconnecting such a device
+from a macOS/Windows machine to a Linux host, the device stays in
+NCM mode, making it unusable with the legacy ipheth driver code.
+
+To correctly support such a device, the driver has to either support
+the NCM mode too, or put the device back into legacy mode.
+
+To match the behaviour of the macOS/Windows driver, and since there
+is no documented control command to revert to legacy mode, implement
+NCM support. The device is attempted to be put into NCM mode by default,
+and falls back to legacy mode if the attempt fails.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Tested-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 180 +++++++++++++++++++++++++++++++++------
+ 1 file changed, 155 insertions(+), 25 deletions(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -52,6 +52,7 @@
+ #include <linux/ethtool.h>
+ #include <linux/usb.h>
+ #include <linux/workqueue.h>
++#include <linux/usb/cdc.h>
+
+ #define USB_VENDOR_APPLE 0x05ac
+
+@@ -59,8 +60,12 @@
+ #define IPHETH_USBINTF_SUBCLASS 253
+ #define IPHETH_USBINTF_PROTO 1
+
+-#define IPHETH_BUF_SIZE 1514
+ #define IPHETH_IP_ALIGN 2 /* padding at front of URB */
++#define IPHETH_NCM_HEADER_SIZE (12 + 96) /* NCMH + NCM0 */
++#define IPHETH_TX_BUF_SIZE ETH_FRAME_LEN
++#define IPHETH_RX_BUF_SIZE_LEGACY (IPHETH_IP_ALIGN + ETH_FRAME_LEN)
++#define IPHETH_RX_BUF_SIZE_NCM 65536
++
+ #define IPHETH_TX_TIMEOUT (5 * HZ)
+
+ #define IPHETH_INTFNUM 2
+@@ -71,6 +76,7 @@
+ #define IPHETH_CTRL_TIMEOUT (5 * HZ)
+
+ #define IPHETH_CMD_GET_MACADDR 0x00
++#define IPHETH_CMD_ENABLE_NCM 0x04
+ #define IPHETH_CMD_CARRIER_CHECK 0x45
+
+ #define IPHETH_CARRIER_CHECK_TIMEOUT round_jiffies_relative(1 * HZ)
+@@ -97,6 +103,8 @@ struct ipheth_device {
+ u8 bulk_out;
+ struct delayed_work carrier_work;
+ bool confirmed_pairing;
++ int (*rcvbulk_callback)(struct urb *urb);
++ size_t rx_buf_len;
+ };
+
+ static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags);
+@@ -116,12 +124,12 @@ static int ipheth_alloc_urbs(struct iphe
+ if (rx_urb == NULL)
+ goto free_tx_urb;
+
+- tx_buf = usb_alloc_coherent(iphone->udev, IPHETH_BUF_SIZE,
++ tx_buf = usb_alloc_coherent(iphone->udev, IPHETH_TX_BUF_SIZE,
+ GFP_KERNEL, &tx_urb->transfer_dma);
+ if (tx_buf == NULL)
+ goto free_rx_urb;
+
+- rx_buf = usb_alloc_coherent(iphone->udev, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN,
++ rx_buf = usb_alloc_coherent(iphone->udev, iphone->rx_buf_len,
+ GFP_KERNEL, &rx_urb->transfer_dma);
+ if (rx_buf == NULL)
+ goto free_tx_buf;
+@@ -134,7 +142,7 @@ static int ipheth_alloc_urbs(struct iphe
+ return 0;
+
+ free_tx_buf:
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE, tx_buf,
++ usb_free_coherent(iphone->udev, IPHETH_TX_BUF_SIZE, tx_buf,
+ tx_urb->transfer_dma);
+ free_rx_urb:
+ usb_free_urb(rx_urb);
+@@ -146,9 +154,9 @@ error_nomem:
+
+ static void ipheth_free_urbs(struct ipheth_device *iphone)
+ {
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN, iphone->rx_buf,
++ usb_free_coherent(iphone->udev, iphone->rx_buf_len, iphone->rx_buf,
+ iphone->rx_urb->transfer_dma);
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE, iphone->tx_buf,
++ usb_free_coherent(iphone->udev, IPHETH_TX_BUF_SIZE, iphone->tx_buf,
+ iphone->tx_urb->transfer_dma);
+ usb_free_urb(iphone->rx_urb);
+ usb_free_urb(iphone->tx_urb);
+@@ -160,15 +168,106 @@ static void ipheth_kill_urbs(struct iphe
+ usb_kill_urb(dev->rx_urb);
+ }
+
+-static void ipheth_rcvbulk_callback(struct urb *urb)
++static int ipheth_consume_skb(char *buf, int len, struct ipheth_device *dev)
+ {
+- struct ipheth_device *dev;
+ struct sk_buff *skb;
+- int status;
++
++ skb = dev_alloc_skb(len);
++ if (!skb) {
++ dev->net->stats.rx_dropped++;
++ return -ENOMEM;
++ }
++
++ skb_put_data(skb, buf, len);
++ skb->dev = dev->net;
++ skb->protocol = eth_type_trans(skb, dev->net);
++
++ dev->net->stats.rx_packets++;
++ dev->net->stats.rx_bytes += len;
++ netif_rx(skb);
++
++ return 0;
++}
++
++static int ipheth_rcvbulk_callback_legacy(struct urb *urb)
++{
++ struct ipheth_device *dev;
++ char *buf;
++ int len;
++
++ dev = urb->context;
++
++ if (urb->actual_length <= IPHETH_IP_ALIGN) {
++ dev->net->stats.rx_length_errors++;
++ return -EINVAL;
++ }
++ len = urb->actual_length - IPHETH_IP_ALIGN;
++ buf = urb->transfer_buffer + IPHETH_IP_ALIGN;
++
++ return ipheth_consume_skb(buf, len, dev);
++}
++
++static int ipheth_rcvbulk_callback_ncm(struct urb *urb)
++{
++ struct usb_cdc_ncm_nth16 *ncmh;
++ struct usb_cdc_ncm_ndp16 *ncm0;
++ struct usb_cdc_ncm_dpe16 *dpe;
++ struct ipheth_device *dev;
++ int retval = -EINVAL;
+ char *buf;
+ int len;
+
+ dev = urb->context;
++
++ if (urb->actual_length < IPHETH_NCM_HEADER_SIZE) {
++ dev->net->stats.rx_length_errors++;
++ return retval;
++ }
++
++ ncmh = urb->transfer_buffer;
++ if (ncmh->dwSignature != cpu_to_le32(USB_CDC_NCM_NTH16_SIGN) ||
++ le16_to_cpu(ncmh->wNdpIndex) >= urb->actual_length) {
++ dev->net->stats.rx_errors++;
++ return retval;
++ }
++
++ ncm0 = urb->transfer_buffer + le16_to_cpu(ncmh->wNdpIndex);
++ if (ncm0->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN) ||
++ le16_to_cpu(ncmh->wHeaderLength) + le16_to_cpu(ncm0->wLength) >=
++ urb->actual_length) {
++ dev->net->stats.rx_errors++;
++ return retval;
++ }
++
++ dpe = ncm0->dpe16;
++ while (le16_to_cpu(dpe->wDatagramIndex) != 0 &&
++ le16_to_cpu(dpe->wDatagramLength) != 0) {
++ if (le16_to_cpu(dpe->wDatagramIndex) >= urb->actual_length ||
++ le16_to_cpu(dpe->wDatagramIndex) +
++ le16_to_cpu(dpe->wDatagramLength) > urb->actual_length) {
++ dev->net->stats.rx_length_errors++;
++ return retval;
++ }
++
++ buf = urb->transfer_buffer + le16_to_cpu(dpe->wDatagramIndex);
++ len = le16_to_cpu(dpe->wDatagramLength);
++
++ retval = ipheth_consume_skb(buf, len, dev);
++ if (retval != 0)
++ return retval;
++
++ dpe++;
++ }
++
++ return 0;
++}
++
++static void ipheth_rcvbulk_callback(struct urb *urb)
++{
++ struct ipheth_device *dev;
++ int retval, status;
++
++ dev = urb->context;
+ if (dev == NULL)
+ return;
+
+@@ -191,25 +290,27 @@ static void ipheth_rcvbulk_callback(stru
+ dev->net->stats.rx_length_errors++;
+ return;
+ }
+- len = urb->actual_length - IPHETH_IP_ALIGN;
+- buf = urb->transfer_buffer + IPHETH_IP_ALIGN;
+
+- skb = dev_alloc_skb(len);
+- if (!skb) {
+- dev_err(&dev->intf->dev, "%s: dev_alloc_skb: -ENOMEM\n",
+- __func__);
+- dev->net->stats.rx_dropped++;
++ /* RX URBs starting with 0x00 0x01 do not encapsulate Ethernet frames,
++ * but rather are control frames. Their purpose is not documented, and
++ * they don't affect driver functionality, okay to drop them.
++ * There is usually just one 4-byte control frame as the very first
++ * URB received from the bulk IN endpoint.
++ */
++ if (unlikely
++ (((char *)urb->transfer_buffer)[0] == 0 &&
++ ((char *)urb->transfer_buffer)[1] == 1))
++ goto rx_submit;
++
++ retval = dev->rcvbulk_callback(urb);
++ if (retval != 0) {
++ dev_err(&dev->intf->dev, "%s: callback retval: %d\n",
++ __func__, retval);
+ return;
+ }
+
+- skb_put_data(skb, buf, len);
+- skb->dev = dev->net;
+- skb->protocol = eth_type_trans(skb, dev->net);
+-
+- dev->net->stats.rx_packets++;
+- dev->net->stats.rx_bytes += len;
++rx_submit:
+ dev->confirmed_pairing = true;
+- netif_rx(skb);
+ ipheth_rx_submit(dev, GFP_ATOMIC);
+ }
+
+@@ -310,6 +411,27 @@ static int ipheth_get_macaddr(struct iph
+ return retval;
+ }
+
++static int ipheth_enable_ncm(struct ipheth_device *dev)
++{
++ struct usb_device *udev = dev->udev;
++ int retval;
++
++ retval = usb_control_msg(udev,
++ usb_sndctrlpipe(udev, IPHETH_CTRL_ENDP),
++ IPHETH_CMD_ENABLE_NCM, /* request */
++ 0x41, /* request type */
++ 0x00, /* value */
++ 0x02, /* index */
++ NULL,
++ 0,
++ IPHETH_CTRL_TIMEOUT);
++
++ dev_info(&dev->intf->dev, "%s: usb_control_msg: %d\n",
++ __func__, retval);
++
++ return retval;
++}
++
+ static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags)
+ {
+ struct usb_device *udev = dev->udev;
+@@ -317,7 +439,7 @@ static int ipheth_rx_submit(struct iphet
+
+ usb_fill_bulk_urb(dev->rx_urb, udev,
+ usb_rcvbulkpipe(udev, dev->bulk_in),
+- dev->rx_buf, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN,
++ dev->rx_buf, dev->rx_buf_len,
+ ipheth_rcvbulk_callback,
+ dev);
+ dev->rx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
+@@ -365,7 +487,7 @@ static netdev_tx_t ipheth_tx(struct sk_b
+ int retval;
+
+ /* Paranoid */
+- if (skb->len > IPHETH_BUF_SIZE) {
++ if (skb->len > IPHETH_TX_BUF_SIZE) {
+ WARN(1, "%s: skb too large: %d bytes\n", __func__, skb->len);
+ dev->net->stats.tx_dropped++;
+ dev_kfree_skb_any(skb);
+@@ -448,6 +570,8 @@ static int ipheth_probe(struct usb_inter
+ dev->net = netdev;
+ dev->intf = intf;
+ dev->confirmed_pairing = false;
++ dev->rx_buf_len = IPHETH_RX_BUF_SIZE_LEGACY;
++ dev->rcvbulk_callback = ipheth_rcvbulk_callback_legacy;
+ /* Set up endpoints */
+ hintf = usb_altnum_to_altsetting(intf, IPHETH_ALT_INTFNUM);
+ if (hintf == NULL) {
+@@ -479,6 +603,12 @@ static int ipheth_probe(struct usb_inter
+ if (retval)
+ goto err_get_macaddr;
+
++ retval = ipheth_enable_ncm(dev);
++ if (!retval) {
++ dev->rx_buf_len = IPHETH_RX_BUF_SIZE_NCM;
++ dev->rcvbulk_callback = ipheth_rcvbulk_callback_ncm;
++ }
++
+ INIT_DELAYED_WORK(&dev->carrier_work, ipheth_carrier_check_work);
+
+ retval = ipheth_alloc_urbs(dev);
--- /dev/null
+From 0c6e9d32ef0ccfcf2d875cbcff23bf345a54d585 Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:02 +0200
+Subject: [PATCH 4/4] usbnet: ipheth: update Kconfig description
+
+This module has for a long time not been limited to iPhone <= 3GS.
+Update description to match the actual state of the driver.
+
+Remove dead link from 2010, instead reference an existing userspace
+iOS device pairing implementation as part of libimobiledevice.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/Kconfig | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/usb/Kconfig
++++ b/drivers/net/usb/Kconfig
+@@ -582,12 +582,10 @@ config USB_IPHETH
+ default n
+ help
+ Module used to share Internet connection (tethering) from your
+- iPhone (Original, 3G and 3GS) to your system.
+- Note that you need userspace libraries and programs that are needed
+- to pair your device with your system and that understand the iPhone
+- protocol.
+-
+- For more information: http://giagio.com/wiki/moin.cgi/iPhoneEthernetDriver
++ iPhone to your system.
++ Note that you need a corresponding userspace library/program
++ to pair your device with your system, for example usbmuxd
++ <https://github.com/libimobiledevice/usbmuxd>.
+
+ config USB_SIERRA_NET
+ tristate "USB-to-WWAN Driver for Sierra Wireless modems"
ax88179_reset(dev);
-@@ -1507,17 +1508,19 @@ ax88179_tx_fixup(struct usbnet *dev, str
+@@ -1502,17 +1503,19 @@ ax88179_tx_fixup(struct usbnet *dev, str
{
u32 tx_hdr1, tx_hdr2;
int frame_size = dev->maxpacket;
if ((skb_header_cloned(skb) || headroom < 0) &&
pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) {
dev_kfree_skb_any(skb);
-@@ -1528,6 +1531,8 @@ ax88179_tx_fixup(struct usbnet *dev, str
+@@ -1523,6 +1526,8 @@ ax88179_tx_fixup(struct usbnet *dev, str
put_unaligned_le32(tx_hdr1, ptr);
put_unaligned_le32(tx_hdr2, ptr + 4);
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -17959,6 +17959,11 @@ L: netdev@vger.kernel.org
+@@ -17966,6 +17966,11 @@ L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ethernet/dlink/sundance.c
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -12358,6 +12358,14 @@ S: Supported
+@@ -12365,6 +12365,14 @@ S: Supported
F: Documentation/devicetree/bindings/mtd/atmel-nand.txt
F: drivers/mtd/nand/raw/atmel/*
imx_ocotp_nvmem_config.priv = priv;
--- a/drivers/nvmem/meson-efuse.c
+++ b/drivers/nvmem/meson-efuse.c
-@@ -93,6 +93,7 @@ static int meson_efuse_probe(struct plat
+@@ -74,6 +74,7 @@ static int meson_efuse_probe(struct plat
econfig->dev = dev;
econfig->name = dev_name(dev);
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
-@@ -2287,6 +2287,23 @@ struct btmtk_section_map {
+@@ -2289,6 +2289,23 @@ struct btmtk_section_map {
};
} __packed;
static void btusb_mtk_wmt_recv(struct urb *urb)
{
struct hci_dev *hdev = urb->context;
-@@ -3941,6 +3958,7 @@ static int btusb_probe(struct usb_interf
+@@ -3943,6 +3960,7 @@ static int btusb_probe(struct usb_interf
hdev->shutdown = btusb_mtk_shutdown;
hdev->manufacturer = 70;
hdev->cmd_timeout = btusb_mtk_cmd_timeout;
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
-@@ -2292,7 +2292,7 @@ static int btusb_set_bdaddr_mtk(struct h
+@@ -2294,7 +2294,7 @@ static int btusb_set_bdaddr_mtk(struct h
struct sk_buff *skb;
long ret;
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
-@@ -476,6 +476,9 @@ static const struct usb_device_id blackl
+@@ -478,6 +478,9 @@ static const struct usb_device_id blackl
{ USB_DEVICE(0x13d3, 0x3564), .driver_info = BTUSB_MEDIATEK |
BTUSB_WIDEBAND_SPEECH |
BTUSB_VALID_LE_STATES },
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
-@@ -467,6 +467,9 @@ static const struct usb_device_id blackl
+@@ -469,6 +469,9 @@ static const struct usb_device_id blackl
BTUSB_VALID_LE_STATES },
/* Additional MediaTek MT7921 Bluetooth devices */
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
-@@ -485,6 +485,9 @@ static const struct usb_device_id blackl
+@@ -487,6 +487,9 @@ static const struct usb_device_id blackl
{ USB_DEVICE(0x0489, 0xe0cd), .driver_info = BTUSB_MEDIATEK |
BTUSB_WIDEBAND_SPEECH |
BTUSB_VALID_LE_STATES },
static void mem_cgroup_css_free(struct cgroup_subsys_state *css)
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
-@@ -7943,6 +7943,7 @@ static void __init free_area_init_node(i
+@@ -7945,6 +7945,7 @@ static void __init free_area_init_node(i
pgdat_set_deferred_range(pgdat);
free_area_init_core(pgdat);
--- /dev/null
+From 66a5c40f60f5d88ad8d47ba6a4ba05892853fa1f Mon Sep 17 00:00:00 2001
+From: Tanzir Hasan <tanzirh@google.com>
+Date: Tue, 26 Dec 2023 18:00:00 +0000
+Subject: [PATCH] kernel.h: removed REPEAT_BYTE from kernel.h
+
+This patch creates wordpart.h and includes it in asm/word-at-a-time.h
+for all architectures. WORD_AT_A_TIME_CONSTANTS depends on kernel.h
+because of REPEAT_BYTE. Moving this to another header and including it
+where necessary allows us to not include the bloated kernel.h. Making
+this implicit dependency on REPEAT_BYTE explicit allows for later
+improvements in the lib/string.c inclusion list.
+
+Suggested-by: Al Viro <viro@zeniv.linux.org.uk>
+Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Tanzir Hasan <tanzirh@google.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Link: https://lore.kernel.org/r/20231226-libstringheader-v6-1-80aa08c7652c@google.com
+Signed-off-by: Kees Cook <keescook@chromium.org>
+---
+ arch/arm/include/asm/word-at-a-time.h | 3 ++-
+ arch/arm64/include/asm/word-at-a-time.h | 3 ++-
+ arch/powerpc/include/asm/word-at-a-time.h | 4 ++--
+ arch/riscv/include/asm/word-at-a-time.h | 3 ++-
+ arch/s390/include/asm/word-at-a-time.h | 3 ++-
+ arch/sh/include/asm/word-at-a-time.h | 2 ++
+ arch/x86/include/asm/word-at-a-time.h | 3 ++-
+ arch/x86/kvm/mmu/mmu.c | 1 +
+ fs/namei.c | 2 +-
+ include/asm-generic/word-at-a-time.h | 3 ++-
+ include/linux/kernel.h | 8 --------
+ include/linux/wordpart.h | 13 +++++++++++++
+ 12 files changed, 31 insertions(+), 17 deletions(-)
+ create mode 100644 include/linux/wordpart.h
+
+--- a/arch/arm/include/asm/word-at-a-time.h
++++ b/arch/arm/include/asm/word-at-a-time.h
+@@ -8,7 +8,8 @@
+ * Little-endian word-at-a-time zero byte handling.
+ * Heavily based on the x86 algorithm.
+ */
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+
+ struct word_at_a_time {
+ const unsigned long one_bits, high_bits;
+--- a/arch/arm64/include/asm/word-at-a-time.h
++++ b/arch/arm64/include/asm/word-at-a-time.h
+@@ -9,7 +9,8 @@
+
+ #ifndef __AARCH64EB__
+
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+
+ struct word_at_a_time {
+ const unsigned long one_bits, high_bits;
+--- a/arch/powerpc/include/asm/word-at-a-time.h
++++ b/arch/powerpc/include/asm/word-at-a-time.h
+@@ -4,8 +4,8 @@
+ /*
+ * Word-at-a-time interfaces for PowerPC.
+ */
+-
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ #include <asm/asm-compat.h>
+ #include <asm/extable.h>
+
+--- a/arch/sh/include/asm/word-at-a-time.h
++++ b/arch/sh/include/asm/word-at-a-time.h
+@@ -5,6 +5,8 @@
+ #ifdef CONFIG_CPU_BIG_ENDIAN
+ # include <asm-generic/word-at-a-time.h>
+ #else
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ /*
+ * Little-endian version cribbed from x86.
+ */
+--- a/arch/x86/include/asm/word-at-a-time.h
++++ b/arch/x86/include/asm/word-at-a-time.h
+@@ -2,7 +2,8 @@
+ #ifndef _ASM_WORD_AT_A_TIME_H
+ #define _ASM_WORD_AT_A_TIME_H
+
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+
+ /*
+ * This is largely generic for little-endian machines, but the
+--- a/arch/x86/kvm/mmu/mmu.c
++++ b/arch/x86/kvm/mmu/mmu.c
+@@ -44,6 +44,7 @@
+ #include <linux/kern_levels.h>
+ #include <linux/kstrtox.h>
+ #include <linux/kthread.h>
++#include <linux/wordpart.h>
+
+ #include <asm/page.h>
+ #include <asm/memtype.h>
+--- a/fs/namei.c
++++ b/fs/namei.c
+@@ -17,8 +17,8 @@
+
+ #include <linux/init.h>
+ #include <linux/export.h>
+-#include <linux/kernel.h>
+ #include <linux/slab.h>
++#include <linux/wordpart.h>
+ #include <linux/fs.h>
+ #include <linux/namei.h>
+ #include <linux/pagemap.h>
+--- a/include/asm-generic/word-at-a-time.h
++++ b/include/asm-generic/word-at-a-time.h
+@@ -2,7 +2,8 @@
+ #ifndef _ASM_WORD_AT_A_TIME_H
+ #define _ASM_WORD_AT_A_TIME_H
+
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ #include <asm/byteorder.h>
+
+ #ifdef __BIG_ENDIAN
+--- a/include/linux/kernel.h
++++ b/include/linux/kernel.h
+@@ -36,14 +36,6 @@
+
+ #define STACK_MAGIC 0xdeadbeef
+
+-/**
+- * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
+- * @x: value to repeat
+- *
+- * NOTE: @x is not checked for > 0xff; larger values produce odd results.
+- */
+-#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x))
+-
+ /* generic data direction definitions */
+ #define READ 0
+ #define WRITE 1
+--- /dev/null
++++ b/include/linux/wordpart.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#ifndef _LINUX_WORDPART_H
++#define _LINUX_WORDPART_H
++/**
++ * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
++ * @x: value to repeat
++ *
++ * NOTE: @x is not checked for > 0xff; larger values produce odd results.
++ */
++#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x))
++
++#endif // _LINUX_WORDPART_H
--- /dev/null
+From adeb04362d74188c1e22ccb824b15a0a7b3de2f4 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Wed, 14 Feb 2024 19:26:32 +0200
+Subject: [PATCH] kernel.h: Move upper_*_bits() and lower_*_bits() to
+ wordpart.h
+
+The wordpart.h header is collecting APIs related to the handling
+parts of the word (usually in byte granularity). The upper_*_bits()
+and lower_*_bits() are good candidates to be moved to there.
+
+This helps to clean up header dependency hell with regard to kernel.h
+as the latter gathers completely unrelated stuff together and slows
+down compilation (especially when it's included into other header).
+
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Link: https://lore.kernel.org/r/20240214172752.3605073-1-andriy.shevchenko@linux.intel.com
+Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
+Signed-off-by: Kees Cook <keescook@chromium.org>
+---
+ include/linux/kernel.h | 30 ++----------------------------
+ include/linux/wordpart.h | 29 +++++++++++++++++++++++++++++
+ 2 files changed, 31 insertions(+), 28 deletions(-)
+
+--- a/include/linux/kernel.h
++++ b/include/linux/kernel.h
+@@ -30,6 +30,8 @@
+ #include <linux/build_bug.h>
+ #include <linux/static_call_types.h>
+ #include <linux/instruction_pointer.h>
++#include <linux/wordpart.h>
++
+ #include <asm/byteorder.h>
+
+ #include <uapi/linux/kernel.h>
+@@ -55,34 +57,6 @@
+ } \
+ )
+
+-/**
+- * upper_32_bits - return bits 32-63 of a number
+- * @n: the number we're accessing
+- *
+- * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
+- * the "right shift count >= width of type" warning when that quantity is
+- * 32-bits.
+- */
+-#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
+-
+-/**
+- * lower_32_bits - return bits 0-31 of a number
+- * @n: the number we're accessing
+- */
+-#define lower_32_bits(n) ((u32)((n) & 0xffffffff))
+-
+-/**
+- * upper_16_bits - return bits 16-31 of a number
+- * @n: the number we're accessing
+- */
+-#define upper_16_bits(n) ((u16)((n) >> 16))
+-
+-/**
+- * lower_16_bits - return bits 0-15 of a number
+- * @n: the number we're accessing
+- */
+-#define lower_16_bits(n) ((u16)((n) & 0xffff))
+-
+ struct completion;
+ struct user;
+
+--- a/include/linux/wordpart.h
++++ b/include/linux/wordpart.h
+@@ -2,6 +2,35 @@
+
+ #ifndef _LINUX_WORDPART_H
+ #define _LINUX_WORDPART_H
++
++/**
++ * upper_32_bits - return bits 32-63 of a number
++ * @n: the number we're accessing
++ *
++ * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
++ * the "right shift count >= width of type" warning when that quantity is
++ * 32-bits.
++ */
++#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
++
++/**
++ * lower_32_bits - return bits 0-31 of a number
++ * @n: the number we're accessing
++ */
++#define lower_32_bits(n) ((u32)((n) & 0xffffffff))
++
++/**
++ * upper_16_bits - return bits 16-31 of a number
++ * @n: the number we're accessing
++ */
++#define upper_16_bits(n) ((u16)((n) >> 16))
++
++/**
++ * lower_16_bits - return bits 0-15 of a number
++ * @n: the number we're accessing
++ */
++#define lower_16_bits(n) ((u16)((n) & 0xffff))
++
+ /**
+ * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
+ * @x: value to repeat
--- /dev/null
+From 773bbe10449731c9525457873e0c2342e5cf883b Mon Sep 17 00:00:00 2001
+From: Michael Walle <michael@walle.cc>
+Date: Thu, 11 Aug 2022 00:06:53 +0200
+Subject: [PATCH] mtd: spi-nor: add generic flash driver
+
+Our SFDP parsing is everything we need to support all basic operations
+of a flash device. If the flash isn't found in our in-kernel flash
+database, gracefully fall back to a driver described solely by its SFDP
+tables.
+
+Signed-off-by: Michael Walle <michael@walle.cc>
+Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
+Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com>
+Reviewed-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
+Link: https://lore.kernel.org/r/20220810220654.1297699-7-michael@walle.cc
+---
+ drivers/mtd/spi-nor/core.c | 26 ++++++++++++++++++++++++--
+ drivers/mtd/spi-nor/core.h | 1 +
+ drivers/mtd/spi-nor/sfdp.c | 27 +++++++++++++++++++++++++++
+ 3 files changed, 52 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -1636,6 +1636,16 @@ static const struct spi_nor_manufacturer
+ &spi_nor_xmc,
+ };
+
++static const struct flash_info spi_nor_generic_flash = {
++ .name = "spi-nor-generic",
++ /*
++ * JESD216 rev A doesn't specify the page size, therefore we need a
++ * sane default.
++ */
++ .page_size = 256,
++ .parse_sfdp = true,
++};
++
+ static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
+ const u8 *id)
+ {
+@@ -1669,6 +1679,14 @@ static const struct flash_info *spi_nor_
+ }
+
+ info = spi_nor_match_id(nor, id);
++
++ /* Fallback to a generic flash described only by its SFDP data. */
++ if (!info) {
++ ret = spi_nor_check_sfdp_signature(nor);
++ if (!ret)
++ info = &spi_nor_generic_flash;
++ }
++
+ if (!info) {
+ dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
+ SPI_NOR_MAX_ID_LEN, id);
+@@ -2105,8 +2123,12 @@ static int spi_nor_select_pp(struct spi_
+ * spi_nor_select_uniform_erase() - select optimum uniform erase type
+ * @map: the erase map of the SPI NOR
+ * @wanted_size: the erase type size to search for. Contains the value of
+- * info->sector_size or of the "small sector" size in case
+- * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
++ * info->sector_size, the "small sector" size in case
++ * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined or 0 if
++ * there is no information about the sector size. The
++ * latter is the case if the flash parameters are parsed
++ * solely by SFDP, then the largest supported erase type
++ * is selected.
+ *
+ * Once the optimum uniform sector erase command is found, disable all the
+ * other.
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -708,6 +708,8 @@ int spi_nor_controller_ops_read_reg(stru
+ int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
+ const u8 *buf, size_t len);
+
++int spi_nor_check_sfdp_signature(struct spi_nor *nor);
++
+ static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
+ {
+ return container_of(mtd, struct spi_nor, mtd);
+--- a/drivers/mtd/spi-nor/sfdp.c
++++ b/drivers/mtd/spi-nor/sfdp.c
+@@ -1250,6 +1250,33 @@ static void spi_nor_post_sfdp_fixups(str
+ }
+
+ /**
++ * spi_nor_check_sfdp_signature() - check for a valid SFDP signature
++ * @nor: pointer to a 'struct spi_nor'
++ *
++ * Used to detect if the flash supports the RDSFDP command as well as the
++ * presence of a valid SFDP table.
++ *
++ * Return: 0 on success, -errno otherwise.
++ */
++int spi_nor_check_sfdp_signature(struct spi_nor *nor)
++{
++ u32 signature;
++ int err;
++
++ /* Get the SFDP header. */
++ err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(signature),
++ &signature);
++ if (err < 0)
++ return err;
++
++ /* Check the SFDP signature. */
++ if (le32_to_cpu(signature) != SFDP_SIGNATURE)
++ return -EINVAL;
++
++ return 0;
++}
++
++/**
+ * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
+ * @nor: pointer to a 'struct spi_nor'
+ *
--- /dev/null
+From: Richard Gobert <richardbgobert@gmail.com>
+Date: Wed, 3 Jan 2024 15:44:21 +0100
+Subject: [PATCH] net: gro: parse ipv6 ext headers without frag0 invalidation
+
+The existing code always pulls the IPv6 header and sets the transport
+offset initially. Then optionally again pulls any extension headers in
+ipv6_gso_pull_exthdrs and sets the transport offset again on return from
+that call. skb->data is set at the start of the first extension header
+before calling ipv6_gso_pull_exthdrs, and must disable the frag0
+optimization because that function uses pskb_may_pull/pskb_pull instead of
+skb_gro_ helpers. It sets the GRO offset to the TCP header with
+skb_gro_pull and sets the transport header. Then returns skb->data to its
+position before this block.
+
+This commit introduces a new helper function - ipv6_gro_pull_exthdrs -
+which is used in ipv6_gro_receive to pull ipv6 ext headers instead of
+ipv6_gso_pull_exthdrs. Thus, there is no modification of skb->data, all
+operations use skb_gro_* helpers, and the frag0 fast path can be taken for
+IPv6 packets with ext headers.
+
+Signed-off-by: Richard Gobert <richardbgobert@gmail.com>
+Reviewed-by: Willem de Bruijn <willemb@google.com>
+Reviewed-by: David Ahern <dsahern@kernel.org>
+Reviewed-by: Eric Dumazet <edumazet@google.com>
+Link: https://lore.kernel.org/r/504130f6-b56c-4dcc-882c-97942c59f5b7@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+
+--- a/net/ipv6/ip6_offload.c
++++ b/net/ipv6/ip6_offload.c
+@@ -36,6 +36,40 @@
+ INDIRECT_CALL_L4(cb, f2, f1, head, skb); \
+ })
+
++static int ipv6_gro_pull_exthdrs(struct sk_buff *skb, int off, int proto)
++{
++ const struct net_offload *ops = NULL;
++ struct ipv6_opt_hdr *opth;
++
++ for (;;) {
++ int len;
++
++ ops = rcu_dereference(inet6_offloads[proto]);
++
++ if (unlikely(!ops))
++ break;
++
++ if (!(ops->flags & INET6_PROTO_GSO_EXTHDR))
++ break;
++
++ opth = skb_gro_header(skb, off + sizeof(*opth), off);
++ if (unlikely(!opth))
++ break;
++
++ len = ipv6_optlen(opth);
++
++ opth = skb_gro_header(skb, off + len, off);
++ if (unlikely(!opth))
++ break;
++ proto = opth->nexthdr;
++
++ off += len;
++ }
++
++ skb_gro_pull(skb, off - skb_network_offset(skb));
++ return proto;
++}
++
+ static int ipv6_gso_pull_exthdrs(struct sk_buff *skb, int proto)
+ {
+ const struct net_offload *ops = NULL;
+@@ -224,28 +258,25 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
+ goto out;
+
+ skb_set_network_header(skb, off);
+- skb_gro_pull(skb, sizeof(*iph));
+- skb_set_transport_header(skb, skb_gro_offset(skb));
+
+- flush += ntohs(iph->payload_len) != skb_gro_len(skb);
++ flush += ntohs(iph->payload_len) != skb->len - hlen;
+
+ proto = iph->nexthdr;
+ ops = rcu_dereference(inet6_offloads[proto]);
+ if (!ops || !ops->callbacks.gro_receive) {
+- pskb_pull(skb, skb_gro_offset(skb));
+- skb_gro_frag0_invalidate(skb);
+- proto = ipv6_gso_pull_exthdrs(skb, proto);
+- skb_gro_pull(skb, -skb_transport_offset(skb));
+- skb_reset_transport_header(skb);
+- __skb_push(skb, skb_gro_offset(skb));
++ proto = ipv6_gro_pull_exthdrs(skb, hlen, proto);
+
+ ops = rcu_dereference(inet6_offloads[proto]);
+ if (!ops || !ops->callbacks.gro_receive)
+ goto out;
+
+- iph = ipv6_hdr(skb);
++ iph = skb_gro_network_header(skb);
++ } else {
++ skb_gro_pull(skb, sizeof(*iph));
+ }
+
++ skb_set_transport_header(skb, skb_gro_offset(skb));
++
+ NAPI_GRO_CB(skb)->proto = proto;
+
+ flush--;
--- /dev/null
+From: Richard Gobert <richardbgobert@gmail.com>
+Date: Tue, 30 Apr 2024 16:35:55 +0200
+Subject: [PATCH] net: gro: add flush check in udp_gro_receive_segment
+
+GRO-GSO path is supposed to be transparent and as such L3 flush checks are
+relevant to all UDP flows merging in GRO. This patch uses the same logic
+and code from tcp_gro_receive, terminating merge if flush is non zero.
+
+Fixes: e20cf8d3f1f7 ("udp: implement GRO for plain UDP sockets.")
+Signed-off-by: Richard Gobert <richardbgobert@gmail.com>
+Reviewed-by: Willem de Bruijn <willemb@google.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/net/ipv4/udp_offload.c
++++ b/net/ipv4/udp_offload.c
+@@ -463,6 +463,7 @@ static struct sk_buff *udp_gro_receive_s
+ struct sk_buff *p;
+ unsigned int ulen;
+ int ret = 0;
++ int flush;
+
+ /* requires non zero csum, for symmetry with GSO */
+ if (!uh->check) {
+@@ -496,13 +497,22 @@ static struct sk_buff *udp_gro_receive_s
+ return p;
+ }
+
++ flush = NAPI_GRO_CB(p)->flush;
++
++ if (NAPI_GRO_CB(p)->flush_id != 1 ||
++ NAPI_GRO_CB(p)->count != 1 ||
++ !NAPI_GRO_CB(p)->is_atomic)
++ flush |= NAPI_GRO_CB(p)->flush_id;
++ else
++ NAPI_GRO_CB(p)->is_atomic = false;
++
+ /* Terminate the flow on len mismatch or if it grow "too much".
+ * Under small packet flood GRO count could elsewhere grow a lot
+ * leading to excessive truesize values.
+ * On len mismatch merge the first packet shorter than gso_size,
+ * otherwise complete the GRO packet.
+ */
+- if (ulen > ntohs(uh2->len)) {
++ if (ulen > ntohs(uh2->len) || flush) {
+ pp = p;
+ } else {
+ if (NAPI_GRO_CB(skb)->is_flist) {
.mac_link_down = prestera_mac_link_down,
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -654,7 +654,6 @@ static void mtk_mac_link_up(struct phyli
+@@ -653,7 +653,6 @@ static void mtk_mac_link_up(struct phyli
}
static const struct phylink_mac_ops mtk_phylink_ops = {
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4333,6 +4333,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4332,6 +4332,7 @@ static const struct mtk_soc_data mt7986_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7986_CLKS_BITMAP,
.required_pctl = false,
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3480,11 +3480,8 @@ static void mtk_pending_work(struct work
+@@ -3479,11 +3479,8 @@ static void mtk_pending_work(struct work
rtnl_lock();
dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
/* stop all devices to make sure that dma is properly shut down */
for (i = 0; i < MTK_MAC_COUNT; i++) {
if (!eth->netdev[i])
-@@ -3518,7 +3515,7 @@ static void mtk_pending_work(struct work
+@@ -3517,7 +3514,7 @@ static void mtk_pending_work(struct work
dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3256,6 +3256,27 @@ static void mtk_set_mcr_max_rx(struct mt
+@@ -3255,6 +3255,27 @@ static void mtk_set_mcr_max_rx(struct mt
mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
}
static int mtk_hw_init(struct mtk_eth *eth)
{
u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
-@@ -3295,22 +3316,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3294,22 +3315,9 @@ static int mtk_hw_init(struct mtk_eth *e
return 0;
}
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3277,7 +3277,54 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3276,7 +3276,54 @@ static void mtk_hw_reset(struct mtk_eth
0x3ffffff);
}
{
u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
ETHSYS_DMA_AG_MAP_PPE;
-@@ -3316,7 +3363,12 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3315,7 +3362,12 @@ static int mtk_hw_init(struct mtk_eth *e
return 0;
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
/* Set FE to PDMAv2 if necessary */
-@@ -3507,7 +3559,7 @@ static void mtk_pending_work(struct work
+@@ -3506,7 +3558,7 @@ static void mtk_pending_work(struct work
if (eth->dev->pins)
pinctrl_select_state(eth->dev->pins->p,
eth->dev->pins->default_state);
/* restart DMA and enable IRQs */
for (i = 0; i < MTK_MAC_COUNT; i++) {
-@@ -4109,7 +4161,7 @@ static int mtk_probe(struct platform_dev
+@@ -4108,7 +4160,7 @@ static int mtk_probe(struct platform_dev
eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
INIT_WORK(ð->pending_work, mtk_pending_work);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -2844,14 +2844,29 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2843,14 +2843,29 @@ static void mtk_dma_free(struct mtk_eth
kfree(eth->scratch_head);
}
schedule_work(ð->pending_work);
}
-@@ -3331,15 +3346,17 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3330,15 +3345,17 @@ static int mtk_hw_init(struct mtk_eth *e
const struct mtk_reg_map *reg_map = eth->soc->reg_map;
int i, val, ret;
if (eth->ethsys)
regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
-@@ -3468,8 +3485,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3467,8 +3484,10 @@ static int mtk_hw_init(struct mtk_eth *e
return 0;
err_disable_pm:
return ret;
}
-@@ -3531,30 +3550,53 @@ static int mtk_do_ioctl(struct net_devic
+@@ -3530,30 +3549,53 @@ static int mtk_do_ioctl(struct net_devic
return -EOPNOTSUPP;
}
if (eth->dev->pins)
pinctrl_select_state(eth->dev->pins->p,
-@@ -3565,15 +3607,19 @@ static void mtk_pending_work(struct work
+@@ -3564,15 +3606,19 @@ static void mtk_pending_work(struct work
for (i = 0; i < MTK_MAC_COUNT; i++) {
if (!test_bit(i, &restart))
continue;
};
/* strings used by ethtool */
-@@ -3339,6 +3345,102 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3338,6 +3344,102 @@ static void mtk_hw_warm_reset(struct mtk
val, rst_mask);
}
static int mtk_hw_init(struct mtk_eth *eth, bool reset)
{
u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
-@@ -3657,6 +3759,7 @@ static int mtk_cleanup(struct mtk_eth *e
+@@ -3656,6 +3758,7 @@ static int mtk_cleanup(struct mtk_eth *e
mtk_unreg_dev(eth);
mtk_free_dev(eth);
cancel_work_sync(ð->pending_work);
return 0;
}
-@@ -4094,6 +4197,7 @@ static int mtk_probe(struct platform_dev
+@@ -4093,6 +4196,7 @@ static int mtk_probe(struct platform_dev
eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
INIT_WORK(ð->rx_dim.work, mtk_dim_rx);
eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
INIT_WORK(ð->tx_dim.work, mtk_dim_tx);
-@@ -4296,6 +4400,8 @@ static int mtk_probe(struct platform_dev
+@@ -4295,6 +4399,8 @@ static int mtk_probe(struct platform_dev
netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx);
platform_set_drvdata(pdev, eth);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3688,6 +3688,11 @@ static void mtk_pending_work(struct work
+@@ -3687,6 +3687,11 @@ static void mtk_pending_work(struct work
set_bit(MTK_RESETTING, ð->state);
mtk_prepare_for_reset(eth);
/* stop all devices to make sure that dma is properly shut down */
for (i = 0; i < MTK_MAC_COUNT; i++) {
-@@ -3725,6 +3730,8 @@ static void mtk_pending_work(struct work
+@@ -3724,6 +3729,8 @@ static void mtk_pending_work(struct work
clear_bit(MTK_RESETTING, ð->state);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -944,7 +944,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -943,7 +943,7 @@ static int mtk_init_fq_dma(struct mtk_et
{
const struct mtk_soc_data *soc = eth->soc;
dma_addr_t phy_ring_tail;
dma_addr_t dma_addr;
int i;
-@@ -2208,19 +2208,25 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2207,19 +2207,25 @@ static int mtk_tx_alloc(struct mtk_eth *
struct mtk_tx_ring *ring = ð->tx_ring;
int i, sz = soc->txrx.txd_size;
struct mtk_tx_dma_v2 *txd;
u32 next_ptr = ring->phys + next * sz;
txd = ring->dma + i * sz;
-@@ -2240,22 +2246,22 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2239,22 +2245,22 @@ static int mtk_tx_alloc(struct mtk_eth *
* descriptors in ring->dma_pdma.
*/
if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
ring->thresh = MAX_SKB_FRAGS;
/* make sure that all changes to the dma ring are flushed before we
-@@ -2267,14 +2273,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2266,14 +2272,14 @@ static int mtk_tx_alloc(struct mtk_eth *
mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
mtk_w32(eth,
mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
}
-@@ -2292,7 +2298,7 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2291,7 +2297,7 @@ static void mtk_tx_clean(struct mtk_eth
int i;
if (ring->buf) {
mtk_tx_unmap(eth, &ring->buf[i], NULL, false);
kfree(ring->buf);
ring->buf = NULL;
-@@ -2300,14 +2306,14 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2299,14 +2305,14 @@ static void mtk_tx_clean(struct mtk_eth
if (ring->dma) {
dma_free_coherent(eth->dma_dev,
ring->dma_pdma, ring->phys_pdma);
ring->dma_pdma = NULL;
}
-@@ -2832,7 +2838,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2831,7 +2837,7 @@ static void mtk_dma_free(struct mtk_eth
netdev_reset_queue(eth->netdev[i]);
if (eth->scratch_ring) {
dma_free_coherent(eth->dma_dev,
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4479,7 +4479,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4478,7 +4478,7 @@ static const struct mtk_soc_data mt7621_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7621_CLKS_BITMAP,
.required_pctl = false,
.hash_offset = 2,
.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
.txrx = {
-@@ -4518,7 +4518,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4517,7 +4517,7 @@ static const struct mtk_soc_data mt7623_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true,
},
.gdm1_cnt = 0x1c00,
.gdma_to_ppe = 0x3333,
-@@ -620,6 +624,75 @@ static void mtk_mac_link_down(struct phy
+@@ -619,6 +623,75 @@ static void mtk_mac_link_down(struct phy
mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
}
static void mtk_mac_link_up(struct phylink_config *config,
struct phy_device *phy,
unsigned int mode, phy_interface_t interface,
-@@ -645,6 +718,8 @@ static void mtk_mac_link_up(struct phyli
+@@ -644,6 +717,8 @@ static void mtk_mac_link_up(struct phyli
break;
}
/* Configure duplex */
if (duplex == DUPLEX_FULL)
mcr |= MAC_MCR_FORCE_DPX;
-@@ -1105,7 +1180,8 @@ static void mtk_tx_set_dma_desc_v1(struc
+@@ -1104,7 +1179,8 @@ static void mtk_tx_set_dma_desc_v1(struc
WRITE_ONCE(desc->txd1, info->addr);
if (info->last)
data |= TX_DMA_LS0;
WRITE_ONCE(desc->txd3, data);
-@@ -1139,9 +1215,6 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1138,9 +1214,6 @@ static void mtk_tx_set_dma_desc_v2(struc
data |= TX_DMA_LS0;
WRITE_ONCE(desc->txd3, data);
data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
WRITE_ONCE(desc->txd4, data);
-@@ -1185,11 +1258,12 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1184,11 +1257,12 @@ static int mtk_tx_map(struct sk_buff *sk
.gso = gso,
.csum = skb->ip_summed == CHECKSUM_PARTIAL,
.vlan = skb_vlan_tag_present(skb),
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
const struct mtk_soc_data *soc = eth->soc;
-@@ -1197,8 +1271,10 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1196,8 +1270,10 @@ static int mtk_tx_map(struct sk_buff *sk
struct mtk_tx_dma *itxd_pdma, *txd_pdma;
struct mtk_tx_buf *itx_buf, *tx_buf;
int i, n_desc = 1;
itxd = ring->next_free;
itxd_pdma = qdma_to_pdma(ring, itxd);
if (itxd == ring->last_free)
-@@ -1247,7 +1323,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1246,7 +1322,7 @@ static int mtk_tx_map(struct sk_buff *sk
memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
txd_info.size = min_t(unsigned int, frag_size,
soc->txrx.dma_max_len);
txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
!(frag_size - txd_info.size);
txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
-@@ -1286,7 +1362,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1285,7 +1361,7 @@ static int mtk_tx_map(struct sk_buff *sk
txd_pdma->txd2 |= TX_DMA_LS1;
}
skb_tx_timestamp(skb);
ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
-@@ -1298,8 +1374,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1297,8 +1373,7 @@ static int mtk_tx_map(struct sk_buff *sk
wmb();
if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
} else {
int next_idx;
-@@ -1368,7 +1443,7 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1367,7 +1442,7 @@ static void mtk_wake_queue(struct mtk_et
for (i = 0; i < MTK_MAC_COUNT; i++) {
if (!eth->netdev[i])
continue;
}
}
-@@ -1392,7 +1467,7 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1391,7 +1466,7 @@ static netdev_tx_t mtk_start_xmit(struct
tx_num = mtk_cal_txd_req(eth, skb);
if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
netif_err(eth, tx_queued, dev,
"Tx Ring full when queue awake!\n");
spin_unlock(ð->page_lock);
-@@ -1418,7 +1493,7 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1417,7 +1492,7 @@ static netdev_tx_t mtk_start_xmit(struct
goto drop;
if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
spin_unlock(ð->page_lock);
-@@ -1585,10 +1660,12 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1584,10 +1659,12 @@ static int mtk_xdp_submit_frame(struct m
struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
const struct mtk_soc_data *soc = eth->soc;
struct mtk_tx_ring *ring = ð->tx_ring;
};
int err, index = 0, n_desc = 1, nr_frags;
struct mtk_tx_buf *htx_buf, *tx_buf;
-@@ -1638,6 +1715,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1637,6 +1714,7 @@ static int mtk_xdp_submit_frame(struct m
memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
txd_info.size = skb_frag_size(&sinfo->frags[index]);
txd_info.last = index + 1 == nr_frags;
data = skb_frag_address(&sinfo->frags[index]);
index++;
-@@ -1992,8 +2070,46 @@ rx_done:
+@@ -1991,8 +2069,46 @@ rx_done:
return done;
}
{
const struct mtk_reg_map *reg_map = eth->soc->reg_map;
struct mtk_tx_ring *ring = ð->tx_ring;
-@@ -2025,12 +2141,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2024,12 +2140,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
break;
if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
budget--;
}
mtk_tx_unmap(eth, tx_buf, &bq, true);
-@@ -2049,7 +2162,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2048,7 +2161,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
}
static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
{
struct mtk_tx_ring *ring = ð->tx_ring;
struct mtk_tx_buf *tx_buf;
-@@ -2067,12 +2180,8 @@ static int mtk_poll_tx_pdma(struct mtk_e
+@@ -2066,12 +2179,8 @@ static int mtk_poll_tx_pdma(struct mtk_e
break;
if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
budget--;
}
mtk_tx_unmap(eth, tx_buf, &bq, true);
-@@ -2094,26 +2203,15 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -2093,26 +2202,15 @@ static int mtk_poll_tx(struct mtk_eth *e
{
struct mtk_tx_ring *ring = ð->tx_ring;
struct dim_sample dim_sample = {};
dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
&dim_sample);
-@@ -2123,7 +2221,7 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -2122,7 +2220,7 @@ static int mtk_poll_tx(struct mtk_eth *e
(atomic_read(&ring->free_count) > ring->thresh))
mtk_wake_queue(eth);
}
static void mtk_handle_status_irq(struct mtk_eth *eth)
-@@ -2209,6 +2307,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2208,6 +2306,7 @@ static int mtk_tx_alloc(struct mtk_eth *
int i, sz = soc->txrx.txd_size;
struct mtk_tx_dma_v2 *txd;
int ring_size;
if (MTK_HAS_CAPS(soc->caps, MTK_QDMA))
ring_size = MTK_QDMA_RING_SIZE;
-@@ -2276,8 +2375,25 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2275,8 +2374,25 @@ static int mtk_tx_alloc(struct mtk_eth *
ring->phys + ((ring_size - 1) * sz),
soc->reg_map->qdma.crx_ptr);
mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
} else {
mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0);
-@@ -2962,7 +3078,7 @@ static int mtk_start_dma(struct mtk_eth
+@@ -2961,7 +3077,7 @@ static int mtk_start_dma(struct mtk_eth
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
else
val |= MTK_RX_BT_32DWORDS;
mtk_w32(eth, val, reg_map->qdma.glo_cfg);
-@@ -3008,6 +3124,45 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3007,6 +3123,45 @@ static void mtk_gdm_config(struct mtk_et
mtk_w32(eth, 0, MTK_RST_GL);
}
static int mtk_open(struct net_device *dev)
{
struct mtk_mac *mac = netdev_priv(dev);
-@@ -3050,7 +3205,8 @@ static int mtk_open(struct net_device *d
+@@ -3049,7 +3204,8 @@ static int mtk_open(struct net_device *d
refcount_inc(ð->dma_refcnt);
phylink_start(mac->phylink);
return 0;
}
-@@ -3759,8 +3915,12 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -3758,8 +3914,12 @@ static int mtk_unreg_dev(struct mtk_eth
int i;
for (i = 0; i < MTK_MAC_COUNT; i++) {
unregister_netdev(eth->netdev[i]);
}
-@@ -3977,6 +4137,23 @@ static int mtk_set_rxnfc(struct net_devi
+@@ -3976,6 +4136,23 @@ static int mtk_set_rxnfc(struct net_devi
return ret;
}
static const struct ethtool_ops mtk_ethtool_ops = {
.get_link_ksettings = mtk_get_link_ksettings,
.set_link_ksettings = mtk_set_link_ksettings,
-@@ -4011,6 +4188,7 @@ static const struct net_device_ops mtk_n
+@@ -4010,6 +4187,7 @@ static const struct net_device_ops mtk_n
.ndo_setup_tc = mtk_eth_setup_tc,
.ndo_bpf = mtk_xdp,
.ndo_xdp_xmit = mtk_xdp_xmit,
};
static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
-@@ -4020,6 +4198,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4019,6 +4197,7 @@ static int mtk_add_mac(struct mtk_eth *e
struct phylink *phylink;
struct mtk_mac *mac;
int id, err;
if (!_id) {
dev_err(eth->dev, "missing mac id\n");
-@@ -4037,7 +4216,10 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4036,7 +4215,10 @@ static int mtk_add_mac(struct mtk_eth *e
return -EINVAL;
}
if (!eth->netdev[id]) {
dev_err(eth->dev, "alloc_etherdev failed\n");
return -ENOMEM;
-@@ -4145,6 +4327,11 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4144,6 +4326,11 @@ static int mtk_add_mac(struct mtk_eth *e
else
eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
#include "mtk_eth_soc.h"
#include "mtk_wed.h"
-@@ -2021,16 +2022,22 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2020,16 +2021,22 @@ static int mtk_poll_rx(struct napi_struc
htons(RX_DMA_VPID(trxd.rxd4)),
RX_DMA_VID(trxd.rxd4));
} else if (trxd.rxd2 & RX_DMA_VTAG) {
}
skb_record_rx_queue(skb, 0);
-@@ -2858,15 +2865,30 @@ static netdev_features_t mtk_fix_feature
+@@ -2857,15 +2864,30 @@ static netdev_features_t mtk_fix_feature
static int mtk_set_features(struct net_device *dev, netdev_features_t features)
{
}
/* wait for DMA to finish whatever it is doing before we start using it again */
-@@ -3163,11 +3185,45 @@ found:
+@@ -3162,11 +3184,45 @@ found:
return NOTIFY_DONE;
}
err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
if (err) {
-@@ -3688,6 +3744,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3687,6 +3743,10 @@ static int mtk_hw_init(struct mtk_eth *e
*/
val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
/* Enable RX VLan Offloading */
mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
-@@ -3907,6 +3967,12 @@ static int mtk_free_dev(struct mtk_eth *
+@@ -3906,6 +3966,12 @@ static int mtk_free_dev(struct mtk_eth *
free_netdev(eth->netdev[i]);
}
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3201,7 +3201,8 @@ static int mtk_open(struct net_device *d
+@@ -3200,7 +3200,8 @@ static int mtk_open(struct net_device *d
struct mtk_eth *eth = mac->hw;
int i, err;
for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
struct metadata_dst *md_dst = eth->dsa_meta[i];
-@@ -3218,7 +3219,8 @@ static int mtk_open(struct net_device *d
+@@ -3217,7 +3218,8 @@ static int mtk_open(struct net_device *d
}
} else {
/* Hardware special tag parsing needs to be disabled if at least
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3136,7 +3136,7 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3135,7 +3135,7 @@ static void mtk_gdm_config(struct mtk_et
val |= config;
val |= MTK_GDMA_SPECIAL_TAG;
mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
-@@ -3201,8 +3201,7 @@ static int mtk_open(struct net_device *d
+@@ -3200,8 +3200,7 @@ static int mtk_open(struct net_device *d
struct mtk_eth *eth = mac->hw;
int i, err;
for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
struct metadata_dst *md_dst = eth->dsa_meta[i];
-@@ -3219,8 +3218,7 @@ static int mtk_open(struct net_device *d
+@@ -3218,8 +3217,7 @@ static int mtk_open(struct net_device *d
}
} else {
/* Hardware special tag parsing needs to be disabled if at least
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1877,7 +1877,9 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1876,7 +1876,9 @@ static int mtk_poll_rx(struct napi_struc
while (done < budget) {
unsigned int pktlen, *rxdcsum;
dma_addr_t dma_addr;
u32 hash, reason;
int mac = 0;
-@@ -2017,27 +2019,29 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2016,27 +2018,29 @@ static int mtk_poll_rx(struct napi_struc
if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -719,8 +719,6 @@ static void mtk_mac_link_up(struct phyli
+@@ -718,8 +718,6 @@ static void mtk_mac_link_up(struct phyli
break;
}
mtk_eth_path_name(path), __func__, updated);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4803,6 +4803,26 @@ static const struct mtk_soc_data mt7629_
+@@ -4802,6 +4802,26 @@ static const struct mtk_soc_data mt7629_
},
};
static const struct mtk_soc_data mt7986_data = {
.reg_map = &mt7986_reg_map,
.ana_rgc3 = 0x128,
-@@ -4845,6 +4865,7 @@ const struct of_device_id of_mtk_match[]
+@@ -4844,6 +4864,7 @@ const struct of_device_id of_mtk_match[]
{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -744,8 +744,10 @@ static const struct phylink_mac_ops mtk_
+@@ -743,8 +743,10 @@ static const struct phylink_mac_ops mtk_
static int mtk_mdio_init(struct mtk_eth *eth)
{
mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
if (!mii_np) {
-@@ -772,6 +774,25 @@ static int mtk_mdio_init(struct mtk_eth
+@@ -771,6 +773,25 @@ static int mtk_mdio_init(struct mtk_eth
eth->mii_bus->parent = eth->dev;
snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
}
return NULL;
-@@ -4016,8 +4017,17 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -4015,8 +4016,17 @@ static int mtk_unreg_dev(struct mtk_eth
return 0;
}
mtk_unreg_dev(eth);
mtk_free_dev(eth);
cancel_work_sync(ð->pending_work);
-@@ -4457,6 +4467,36 @@ void mtk_eth_set_dma_device(struct mtk_e
+@@ -4456,6 +4466,36 @@ void mtk_eth_set_dma_device(struct mtk_e
rtnl_unlock();
}
static int mtk_probe(struct platform_device *pdev)
{
struct resource *res = NULL;
-@@ -4520,13 +4560,7 @@ static int mtk_probe(struct platform_dev
+@@ -4519,13 +4559,7 @@ static int mtk_probe(struct platform_dev
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
if (err)
return err;
-@@ -4537,14 +4571,17 @@ static int mtk_probe(struct platform_dev
+@@ -4536,14 +4570,17 @@ static int mtk_probe(struct platform_dev
"mediatek,pctl");
if (IS_ERR(eth->pctl)) {
dev_err(&pdev->dev, "no pctl regmap found\n");
}
if (eth->soc->offload_version) {
-@@ -4703,6 +4740,8 @@ err_deinit_hw:
+@@ -4702,6 +4739,8 @@ err_deinit_hw:
mtk_hw_deinit(eth);
err_wed_exit:
mtk_wed_exit();
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4691,8 +4691,8 @@ static int mtk_probe(struct platform_dev
+@@ -4690,8 +4690,8 @@ static int mtk_probe(struct platform_dev
for (i = 0; i < num_ppe; i++) {
u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
if (!eth->ppe[i]) {
err = -ENOMEM;
goto err_deinit_ppe;
-@@ -4816,6 +4816,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4815,6 +4815,7 @@ static const struct mtk_soc_data mt7622_
.required_pctl = false,
.offload_version = 2,
.hash_offset = 2,
.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
-@@ -4853,6 +4854,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4852,6 +4853,7 @@ static const struct mtk_soc_data mt7629_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7629_CLKS_BITMAP,
.required_pctl = false,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4873,6 +4875,7 @@ static const struct mtk_soc_data mt7981_
+@@ -4872,6 +4874,7 @@ static const struct mtk_soc_data mt7981_
.offload_version = 2,
.hash_offset = 4,
.foe_entry_size = sizeof(struct mtk_foe_entry),
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma_v2),
.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -4893,6 +4896,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4892,6 +4895,7 @@ static const struct mtk_soc_data mt7986_
.offload_version = 2,
.hash_offset = 4,
.foe_entry_size = sizeof(struct mtk_foe_entry),
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1897,9 +1897,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1896,9 +1896,7 @@ static int mtk_poll_rx(struct napi_struc
while (done < budget) {
unsigned int pktlen, *rxdcsum;
dma_addr_t dma_addr;
u32 hash, reason;
int mac = 0;
-@@ -2034,36 +2032,21 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2033,36 +2031,21 @@ static int mtk_poll_rx(struct napi_struc
skb_checksum_none_assert(skb);
skb->protocol = eth_type_trans(skb, netdev);
skb_record_rx_queue(skb, 0);
napi_gro_receive(napi, skb);
-@@ -2889,29 +2872,11 @@ static netdev_features_t mtk_fix_feature
+@@ -2888,29 +2871,11 @@ static netdev_features_t mtk_fix_feature
static int mtk_set_features(struct net_device *dev, netdev_features_t features)
{
return 0;
}
-@@ -3225,30 +3190,6 @@ static int mtk_open(struct net_device *d
+@@ -3224,30 +3189,6 @@ static int mtk_open(struct net_device *d
struct mtk_eth *eth = mac->hw;
int i, err;
err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
if (err) {
netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
-@@ -3287,6 +3228,35 @@ static int mtk_open(struct net_device *d
+@@ -3286,6 +3227,35 @@ static int mtk_open(struct net_device *d
phylink_start(mac->phylink);
netif_tx_start_all_queues(dev);
return 0;
}
-@@ -3771,10 +3741,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3770,10 +3740,9 @@ static int mtk_hw_init(struct mtk_eth *e
if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
/* set interrupt delays based on current Net DIM sample */
mtk_dim_rx(ð->rx_dim.work);
-@@ -4414,7 +4383,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4413,7 +4382,7 @@ static int mtk_add_mac(struct mtk_eth *e
eth->netdev[id]->hw_features |= NETIF_F_LRO;
eth->netdev[id]->vlan_features = eth->soc->hw_features &
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4765,7 +4765,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4764,7 +4764,7 @@ static const struct mtk_soc_data mt7621_
.required_pctl = false,
.offload_version = 1,
.hash_offset = 2,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4786,7 +4786,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4785,7 +4785,7 @@ static const struct mtk_soc_data mt7622_
.offload_version = 2,
.hash_offset = 2,
.has_accounting = true,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4805,7 +4805,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4804,7 +4804,7 @@ static const struct mtk_soc_data mt7623_
.required_pctl = true,
.offload_version = 1,
.hash_offset = 2,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4843,8 +4843,8 @@ static const struct mtk_soc_data mt7981_
+@@ -4842,8 +4842,8 @@ static const struct mtk_soc_data mt7981_
.required_pctl = false,
.offload_version = 2,
.hash_offset = 4,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma_v2),
.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -4864,8 +4864,8 @@ static const struct mtk_soc_data mt7986_
+@@ -4863,8 +4863,8 @@ static const struct mtk_soc_data mt7986_
.required_pctl = false,
.offload_version = 2,
.hash_offset = 4,
/* mt7623_pad_clk_setup */
for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
-@@ -4342,13 +4314,19 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4341,13 +4313,19 @@ static int mtk_add_mac(struct mtk_eth *e
mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
__set_bit(PHY_INTERFACE_MODE_TRGMII,
-@@ -4806,6 +4784,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4805,6 +4783,7 @@ static const struct mtk_soc_data mt7623_
.offload_version = 1,
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -555,38 +555,6 @@ static int mtk_mac_finish(struct phylink
+@@ -554,38 +554,6 @@ static int mtk_mac_finish(struct phylink
return 0;
}
static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
phy_interface_t interface)
{
-@@ -708,7 +676,6 @@ static void mtk_mac_link_up(struct phyli
+@@ -707,7 +675,6 @@ static void mtk_mac_link_up(struct phyli
static const struct phylink_mac_ops mtk_phylink_ops = {
.mac_select_pcs = mtk_mac_select_pcs,
.mac_config = mtk_mac_config,
.mac_finish = mtk_mac_finish,
.mac_link_down = mtk_mac_link_down,
-@@ -4309,8 +4276,6 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4308,8 +4275,6 @@ static int mtk_add_mac(struct mtk_eth *e
mac->phylink_config.dev = ð->netdev[id]->dev;
mac->phylink_config.type = PHYLINK_NETDEV;
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -580,7 +580,7 @@ static void mtk_set_queue_speed(struct m
+@@ -579,7 +579,7 @@ static void mtk_set_queue_speed(struct m
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
if (IS_ENABLED(CONFIG_SOC_MT7621)) {
-@@ -955,7 +955,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+@@ -954,7 +954,7 @@ static bool mtk_rx_get_desc(struct mtk_e
rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
}
-@@ -1013,7 +1013,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1012,7 +1012,7 @@ static int mtk_init_fq_dma(struct mtk_et
txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
txd->txd4 = 0;
txd->txd5 = 0;
txd->txd6 = 0;
txd->txd7 = 0;
-@@ -1204,7 +1204,7 @@ static void mtk_tx_set_dma_desc(struct n
+@@ -1203,7 +1203,7 @@ static void mtk_tx_set_dma_desc(struct n
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
mtk_tx_set_dma_desc_v2(dev, txd, info);
else
mtk_tx_set_dma_desc_v1(dev, txd, info);
-@@ -1511,7 +1511,7 @@ static void mtk_update_rx_cpu_idx(struct
+@@ -1510,7 +1510,7 @@ static void mtk_update_rx_cpu_idx(struct
static bool mtk_page_pool_enabled(struct mtk_eth *eth)
{
}
static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
-@@ -1853,7 +1853,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1852,7 +1852,7 @@ static int mtk_poll_rx(struct napi_struc
break;
/* find out which mac the packet come from. values start at 1 */
mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
!(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
-@@ -1949,7 +1949,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1948,7 +1948,7 @@ static int mtk_poll_rx(struct napi_struc
skb->dev = netdev;
bytes += skb->len;
reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -1974,8 +1974,8 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1973,8 +1973,8 @@ static int mtk_poll_rx(struct napi_struc
/* When using VLAN untagging in combination with DSA, the
* hardware treats the MTK special tag as a VLAN and untags it.
*/
unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
if (port < ARRAY_SIZE(eth->dsa_meta) &&
-@@ -2285,7 +2285,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2284,7 +2284,7 @@ static int mtk_tx_alloc(struct mtk_eth *
txd->txd2 = next_ptr;
txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
txd->txd4 = 0;
txd->txd5 = 0;
txd->txd6 = 0;
txd->txd7 = 0;
-@@ -2338,14 +2338,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2337,14 +2337,14 @@ static int mtk_tx_alloc(struct mtk_eth *
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
} else {
mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
-@@ -2474,7 +2474,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2473,7 +2473,7 @@ static int mtk_rx_alloc(struct mtk_eth *
rxd->rxd3 = 0;
rxd->rxd4 = 0;
rxd->rxd5 = 0;
rxd->rxd6 = 0;
rxd->rxd7 = 0;
-@@ -3025,7 +3025,7 @@ static int mtk_start_dma(struct mtk_eth
+@@ -3024,7 +3024,7 @@ static int mtk_start_dma(struct mtk_eth
MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
-@@ -3167,7 +3167,7 @@ static int mtk_open(struct net_device *d
+@@ -3166,7 +3166,7 @@ static int mtk_open(struct net_device *d
phylink_start(mac->phylink);
netif_tx_start_all_queues(dev);
return 0;
if (mtk_uses_dsa(dev) && !eth->prog) {
-@@ -3432,7 +3432,7 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3431,7 +3431,7 @@ static void mtk_hw_reset(struct mtk_eth
{
u32 val;
regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
val = RSTCTRL_PPE0_V2;
} else {
-@@ -3444,7 +3444,7 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3443,7 +3443,7 @@ static void mtk_hw_reset(struct mtk_eth
ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
0x3ffffff);
}
-@@ -3470,7 +3470,7 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3469,7 +3469,7 @@ static void mtk_hw_warm_reset(struct mtk
return;
}
rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
else
rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
-@@ -3640,7 +3640,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3639,7 +3639,7 @@ static int mtk_hw_init(struct mtk_eth *e
else
mtk_hw_reset(eth);
/* Set FE to PDMAv2 if necessary */
val = mtk_r32(eth, MTK_FE_GLO_MISC);
mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
-@@ -3677,7 +3677,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3676,7 +3676,7 @@ static int mtk_hw_init(struct mtk_eth *e
*/
val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
-@@ -3699,7 +3699,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3698,7 +3698,7 @@ static int mtk_hw_init(struct mtk_eth *e
mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
/* PSE should not drop port8 and port9 packets from WDMA Tx */
mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
-@@ -4488,7 +4488,7 @@ static int mtk_probe(struct platform_dev
+@@ -4487,7 +4487,7 @@ static int mtk_probe(struct platform_dev
}
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
err = -EINVAL;
-@@ -4596,9 +4596,8 @@ static int mtk_probe(struct platform_dev
+@@ -4595,9 +4595,8 @@ static int mtk_probe(struct platform_dev
}
if (eth->soc->offload_version) {
num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
for (i = 0; i < num_ppe; i++) {
u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
-@@ -4690,6 +4689,7 @@ static const struct mtk_soc_data mt2701_
+@@ -4689,6 +4688,7 @@ static const struct mtk_soc_data mt2701_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4706,6 +4706,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4705,6 +4705,7 @@ static const struct mtk_soc_data mt7621_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7621_CLKS_BITMAP,
.required_pctl = false,
.offload_version = 1,
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-@@ -4726,6 +4727,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4725,6 +4726,7 @@ static const struct mtk_soc_data mt7622_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7622_CLKS_BITMAP,
.required_pctl = false,
.offload_version = 2,
.hash_offset = 2,
.has_accounting = true,
-@@ -4746,6 +4748,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4745,6 +4747,7 @@ static const struct mtk_soc_data mt7623_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true,
.offload_version = 1,
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-@@ -4768,6 +4771,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4767,6 +4770,7 @@ static const struct mtk_soc_data mt7629_
.required_clks = MT7629_CLKS_BITMAP,
.required_pctl = false,
.has_accounting = true,
.txrx = {
.txd_size = sizeof(struct mtk_tx_dma),
.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4785,6 +4789,7 @@ static const struct mtk_soc_data mt7981_
+@@ -4784,6 +4788,7 @@ static const struct mtk_soc_data mt7981_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7981_CLKS_BITMAP,
.required_pctl = false,
.offload_version = 2,
.hash_offset = 4,
.has_accounting = true,
-@@ -4806,6 +4811,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4805,6 +4810,7 @@ static const struct mtk_soc_data mt7986_
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7986_CLKS_BITMAP,
.required_pctl = false,
.offload_version = 2,
.hash_offset = 4,
.has_accounting = true,
-@@ -4826,6 +4832,7 @@ static const struct mtk_soc_data rt5350_
+@@ -4825,6 +4831,7 @@ static const struct mtk_soc_data rt5350_
.hw_features = MTK_HW_FEATURES_MT7628,
.required_clks = MT7628_CLKS_BITMAP,
.required_pctl = false,
else
val = MTK_FOE_IB2_MIB_CNT;
@@ -965,7 +965,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
- MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |
+ MTK_PPE_SCAN_MODE_CHECK_AGE) |
FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,
MTK_PPE_ENTRIES_SHIFT);
- if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -881,7 +881,7 @@ static void mtk_stats_update(struct mtk_
+@@ -880,7 +880,7 @@ static void mtk_stats_update(struct mtk_
{
int i;
if (!eth->mac[i] || !eth->mac[i]->hw_stats)
continue;
if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
-@@ -1386,7 +1386,7 @@ static int mtk_queue_stopped(struct mtk_
+@@ -1385,7 +1385,7 @@ static int mtk_queue_stopped(struct mtk_
{
int i;
if (!eth->netdev[i])
continue;
if (netif_queue_stopped(eth->netdev[i]))
-@@ -1400,7 +1400,7 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1399,7 +1399,7 @@ static void mtk_wake_queue(struct mtk_et
{
int i;
if (!eth->netdev[i])
continue;
netif_tx_wake_all_queues(eth->netdev[i]);
-@@ -1859,7 +1859,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1858,7 +1858,7 @@ static int mtk_poll_rx(struct napi_struc
!(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
!eth->netdev[mac]))
goto release_desc;
-@@ -2899,7 +2899,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2898,7 +2898,7 @@ static void mtk_dma_free(struct mtk_eth
const struct mtk_soc_data *soc = eth->soc;
int i;
if (eth->netdev[i])
netdev_reset_queue(eth->netdev[i]);
if (eth->scratch_ring) {
-@@ -3053,8 +3053,13 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3052,8 +3052,13 @@ static void mtk_gdm_config(struct mtk_et
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
return;
/* default setup the forward port to send frame to PDMA */
val &= ~0xffff;
-@@ -3064,7 +3069,7 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3063,7 +3068,7 @@ static void mtk_gdm_config(struct mtk_et
val |= config;
val |= MTK_GDMA_SPECIAL_TAG;
mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
-@@ -3661,15 +3666,15 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3660,15 +3665,15 @@ static int mtk_hw_init(struct mtk_eth *e
* up with the more appropriate value when mtk_mac_config call is being
* invoked.
*/
}
/* Indicates CDM to parse the MTK special tag from CPU
-@@ -3849,7 +3854,7 @@ static void mtk_pending_work(struct work
+@@ -3848,7 +3853,7 @@ static void mtk_pending_work(struct work
mtk_prepare_for_reset(eth);
/* stop all devices to make sure that dma is properly shut down */
if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
continue;
-@@ -3865,8 +3870,8 @@ static void mtk_pending_work(struct work
+@@ -3864,8 +3869,8 @@ static void mtk_pending_work(struct work
mtk_hw_init(eth, true);
/* restart DMA and enable IRQs */
continue;
if (mtk_open(eth->netdev[i])) {
-@@ -3893,7 +3898,7 @@ static int mtk_free_dev(struct mtk_eth *
+@@ -3892,7 +3897,7 @@ static int mtk_free_dev(struct mtk_eth *
{
int i;
if (!eth->netdev[i])
continue;
free_netdev(eth->netdev[i]);
-@@ -3912,7 +3917,7 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -3911,7 +3916,7 @@ static int mtk_unreg_dev(struct mtk_eth
{
int i;
struct mtk_mac *mac;
if (!eth->netdev[i])
continue;
-@@ -4213,7 +4218,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4212,7 +4217,7 @@ static int mtk_add_mac(struct mtk_eth *e
}
id = be32_to_cpup(_id);
dev_err(eth->dev, "%d is not a valid mac id\n", id);
return -EINVAL;
}
-@@ -4358,7 +4363,7 @@ void mtk_eth_set_dma_device(struct mtk_e
+@@ -4357,7 +4362,7 @@ void mtk_eth_set_dma_device(struct mtk_e
rtnl_lock();
dev = eth->netdev[i];
if (!dev || !(dev->flags & IFF_UP))
-@@ -4664,7 +4669,7 @@ static int mtk_remove(struct platform_de
+@@ -4663,7 +4668,7 @@ static int mtk_remove(struct platform_de
int i;
/* stop all devices to make sure that dma is properly shut down */
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -861,17 +861,32 @@ void mtk_stats_update_mac(struct mtk_mac
+@@ -860,17 +860,32 @@ void mtk_stats_update_mac(struct mtk_mac
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
hw_stats->rx_flow_control_packets +=
mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
}
u64_stats_update_end(&hw_stats->syncp);
-@@ -1175,7 +1190,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1174,7 +1189,10 @@ static void mtk_tx_set_dma_desc_v2(struc
data |= TX_DMA_LS0;
WRITE_ONCE(desc->txd3, data);
data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
WRITE_ONCE(desc->txd4, data);
-@@ -1186,6 +1204,8 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1185,6 +1203,8 @@ static void mtk_tx_set_dma_desc_v2(struc
/* tx checksum offload */
if (info->csum)
data |= TX_DMA_CHKSUM_V2;
}
WRITE_ONCE(desc->txd5, data);
-@@ -1251,8 +1271,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1250,8 +1270,7 @@ static int mtk_tx_map(struct sk_buff *sk
mtk_tx_set_dma_desc(dev, itxd, &txd_info);
itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
k++);
-@@ -1300,8 +1319,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1299,8 +1318,7 @@ static int mtk_tx_map(struct sk_buff *sk
memset(tx_buf, 0, sizeof(*tx_buf));
tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
txd_info.size, k++);
-@@ -1603,7 +1621,7 @@ static int mtk_xdp_frame_map(struct mtk_
+@@ -1602,7 +1620,7 @@ static int mtk_xdp_frame_map(struct mtk_
}
mtk_tx_set_dma_desc(dev, txd, txd_info);
tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
-@@ -1853,11 +1871,24 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1852,11 +1870,24 @@ static int mtk_poll_rx(struct napi_struc
break;
/* find out which mac the packet come from. values start at 1 */
if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
!eth->netdev[mac]))
-@@ -2079,7 +2110,6 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2078,7 +2109,6 @@ static int mtk_poll_tx_qdma(struct mtk_e
while ((cpu != dma) && budget) {
u32 next_cpu = desc->txd2;
desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
-@@ -2087,15 +2117,13 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2086,15 +2116,13 @@ static int mtk_poll_tx_qdma(struct mtk_e
tx_buf = mtk_desc_to_tx_buf(ring, desc,
eth->soc->txrx.txd_size);
budget--;
}
-@@ -3704,7 +3732,24 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3703,7 +3731,24 @@ static int mtk_hw_init(struct mtk_eth *e
mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
/* PSE should not drop port8 and port9 packets from WDMA Tx */
mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
-@@ -4266,7 +4311,11 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4265,7 +4310,11 @@ static int mtk_add_mac(struct mtk_eth *e
}
spin_lock_init(&mac->hw_stats->stats_lock);
u64_stats_init(&mac->hw_stats->syncp);
return;
err_phy:
-@@ -725,11 +841,15 @@ static int mtk_mdio_init(struct mtk_eth
+@@ -724,11 +840,15 @@ static int mtk_mdio_init(struct mtk_eth
}
divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
-@@ -1190,10 +1310,19 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1189,10 +1309,19 @@ static void mtk_tx_set_dma_desc_v2(struc
data |= TX_DMA_LS0;
WRITE_ONCE(desc->txd3, data);
data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
WRITE_ONCE(desc->txd4, data);
-@@ -4360,6 +4489,17 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4359,6 +4488,17 @@ static int mtk_add_mac(struct mtk_eth *e
mac->phylink_config.supported_interfaces);
}
phylink = phylink_create(&mac->phylink_config,
of_fwnode_handle(mac->of_node),
phy_mode, &mtk_phylink_ops);
-@@ -4880,6 +5020,24 @@ static const struct mtk_soc_data mt7986_
+@@ -4879,6 +5019,24 @@ static const struct mtk_soc_data mt7986_
},
};
static const struct mtk_soc_data rt5350_data = {
.reg_map = &mt7628_reg_map,
.caps = MT7628_CAPS,
-@@ -4898,14 +5056,15 @@ static const struct mtk_soc_data rt5350_
+@@ -4897,14 +5055,15 @@ static const struct mtk_soc_data rt5350_
};
const struct of_device_id of_mtk_match[] = {
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1658,7 +1658,7 @@ static void mtk_update_rx_cpu_idx(struct
+@@ -1657,7 +1657,7 @@ static void mtk_update_rx_cpu_idx(struct
static bool mtk_page_pool_enabled(struct mtk_eth *eth)
{
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -5028,6 +5028,9 @@ static const struct mtk_soc_data mt7988_
+@@ -5027,6 +5027,9 @@ static const struct mtk_soc_data mt7988_
.required_clks = MT7988_CLKS_BITMAP,
.required_pctl = false,
.version = 3,
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -5030,6 +5030,7 @@ static const struct mtk_soc_data mt7988_
+@@ -5029,6 +5029,7 @@ static const struct mtk_soc_data mt7988_
.version = 3,
.offload_version = 2,
.hash_offset = 4,
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3594,19 +3594,34 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3593,19 +3593,34 @@ static void mtk_hw_reset(struct mtk_eth
{
u32 val;
regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
0x3ffffff);
}
-@@ -3632,13 +3647,21 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3631,13 +3646,21 @@ static void mtk_hw_warm_reset(struct mtk
return;
}
regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
-@@ -3990,11 +4013,17 @@ static void mtk_prepare_for_reset(struct
+@@ -3989,11 +4012,17 @@ static void mtk_prepare_for_reset(struct
u32 val;
int i;
/* adjust PPE configurations to prepare for reset */
for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
-@@ -4055,11 +4084,18 @@ static void mtk_pending_work(struct work
+@@ -4054,11 +4083,18 @@ static void mtk_pending_work(struct work
}
}
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1118,10 +1118,13 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1117,10 +1117,13 @@ static int mtk_init_fq_dma(struct mtk_et
dma_addr_t dma_addr;
int i;
if (unlikely(!eth->scratch_ring))
return -ENOMEM;
-@@ -2429,8 +2432,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2428,8 +2431,14 @@ static int mtk_tx_alloc(struct mtk_eth *
if (!ring->buf)
goto no_tx_mem;
if (!ring->dma)
goto no_tx_mem;
-@@ -2529,8 +2538,7 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2528,8 +2537,7 @@ static void mtk_tx_clean(struct mtk_eth
kfree(ring->buf);
ring->buf = NULL;
}
dma_free_coherent(eth->dma_dev,
ring->dma_size * soc->txrx.txd_size,
ring->dma, ring->phys);
-@@ -2549,9 +2557,14 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2548,9 +2556,14 @@ static int mtk_rx_alloc(struct mtk_eth *
{
const struct mtk_reg_map *reg_map = eth->soc->reg_map;
struct mtk_rx_ring *ring;
if (rx_flag == MTK_RX_FLAGS_QDMA) {
if (ring_no)
return -EINVAL;
-@@ -2586,9 +2599,20 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2585,9 +2598,20 @@ static int mtk_rx_alloc(struct mtk_eth *
ring->page_pool = pp;
}
if (!ring->dma)
return -ENOMEM;
-@@ -2673,7 +2697,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2672,7 +2696,7 @@ static int mtk_rx_alloc(struct mtk_eth *
return 0;
}
{
int i;
-@@ -2696,7 +2720,7 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2695,7 +2719,7 @@ static void mtk_rx_clean(struct mtk_eth
ring->data = NULL;
}
dma_free_coherent(eth->dma_dev,
ring->dma_size * eth->soc->txrx.rxd_size,
ring->dma, ring->phys);
-@@ -3059,7 +3083,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -3058,7 +3082,7 @@ static void mtk_dma_free(struct mtk_eth
for (i = 0; i < MTK_MAX_DEVS; i++)
if (eth->netdev[i])
netdev_reset_queue(eth->netdev[i]);
dma_free_coherent(eth->dma_dev,
MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
eth->scratch_ring, eth->phy_scratch_ring);
-@@ -3067,13 +3091,13 @@ static void mtk_dma_free(struct mtk_eth
+@@ -3066,13 +3090,13 @@ static void mtk_dma_free(struct mtk_eth
eth->phy_scratch_ring = 0;
}
mtk_tx_clean(eth);
}
kfree(eth->scratch_head);
-@@ -4641,7 +4665,7 @@ static int mtk_sgmii_init(struct mtk_eth
+@@ -4640,7 +4664,7 @@ static int mtk_sgmii_init(struct mtk_eth
static int mtk_probe(struct platform_device *pdev)
{
struct device_node *mac_np;
struct mtk_eth *eth;
int err, i;
-@@ -4661,6 +4685,20 @@ static int mtk_probe(struct platform_dev
+@@ -4660,6 +4684,20 @@ static int mtk_probe(struct platform_dev
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
eth->ip_align = NET_IP_ALIGN;
spin_lock_init(ð->page_lock);
spin_lock_init(ð->tx_irq_lock);
spin_lock_init(ð->rx_irq_lock);
-@@ -4724,6 +4762,18 @@ static int mtk_probe(struct platform_dev
+@@ -4723,6 +4761,18 @@ static int mtk_probe(struct platform_dev
err = -EINVAL;
goto err_destroy_sgmii;
}
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1311,6 +1311,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1310,6 +1310,10 @@ static void mtk_tx_set_dma_desc_v2(struc
data = TX_DMA_PLEN0(info->size);
if (info->last)
data |= TX_DMA_LS0;
WRITE_ONCE(desc->txd3, data);
/* set forward port */
-@@ -1980,6 +1984,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1979,6 +1983,7 @@ static int mtk_poll_rx(struct napi_struc
bool xdp_flush = false;
int idx;
struct sk_buff *skb;
u8 *data, *new_data;
struct mtk_rx_dma_v2 *rxd, trxd;
int done = 0, bytes = 0;
-@@ -2095,7 +2100,10 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2094,7 +2099,10 @@ static int mtk_poll_rx(struct napi_struc
goto release_desc;
}
ring->buf_size, DMA_FROM_DEVICE);
skb = build_skb(data, ring->frag_size);
-@@ -2161,6 +2169,9 @@ release_desc:
+@@ -2160,6 +2168,9 @@ release_desc:
else
rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
ring->calc_idx = idx;
done++;
}
-@@ -2653,6 +2664,9 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2652,6 +2663,9 @@ static int mtk_rx_alloc(struct mtk_eth *
else
rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
rxd->rxd3 = 0;
rxd->rxd4 = 0;
if (mtk_is_netsys_v2_or_greater(eth)) {
-@@ -2699,6 +2713,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2698,6 +2712,7 @@ static int mtk_rx_alloc(struct mtk_eth *
static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
{
int i;
if (ring->data && ring->dma) {
-@@ -2712,7 +2727,10 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2711,7 +2726,10 @@ static void mtk_rx_clean(struct mtk_eth
if (!rxd->rxd1)
continue;
ring->buf_size, DMA_FROM_DEVICE);
mtk_rx_put_buff(ring, ring->data[i], false);
}
-@@ -4699,6 +4717,14 @@ static int mtk_probe(struct platform_dev
+@@ -4698,6 +4716,14 @@ static int mtk_probe(struct platform_dev
}
}
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1988,11 +1988,11 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1987,11 +1987,11 @@ static int mtk_poll_rx(struct napi_struc
u8 *data, *new_data;
struct mtk_rx_dma_v2 *rxd, trxd;
int done = 0, bytes = 0;
u32 hash, reason;
int mac = 0;
-@@ -2169,7 +2169,8 @@ release_desc:
+@@ -2168,7 +2168,8 @@ release_desc:
else
rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
--- /dev/null
+From f13b2b33c7674fa0988dfaa9adb95d7d912b489f Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 10 Apr 2024 20:42:38 +0100
+Subject: [PATCH 1/2] net: dsa: introduce dsa_phylink_to_port()
+
+We convert from a phylink_config struct to a dsa_port struct in many
+places, let's provide a helper for this.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/E1rudqA-006K9B-85@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ include/net/dsa.h | 6 ++++++
+ net/dsa/port.c | 12 ++++++------
+ 2 files changed, 12 insertions(+), 6 deletions(-)
+
+--- a/include/net/dsa.h
++++ b/include/net/dsa.h
+@@ -337,6 +337,12 @@ struct dsa_port {
+ struct list_head vlans;
+ };
+
++static inline struct dsa_port *
++dsa_phylink_to_port(struct phylink_config *config)
++{
++ return container_of(config, struct dsa_port, pl_config);
++}
++
+ /* TODO: ideally DSA ports would have a single dp->link_dp member,
+ * and no dst->rtable nor this struct dsa_link would be needed,
+ * but this would require some more complex tree walking,
+--- a/net/dsa/port.c
++++ b/net/dsa/port.c
+@@ -1552,7 +1552,7 @@ static void dsa_port_phylink_validate(st
+ unsigned long *supported,
+ struct phylink_link_state *state)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_validate) {
+@@ -1567,7 +1567,7 @@ static void dsa_port_phylink_validate(st
+ static void dsa_port_phylink_mac_pcs_get_state(struct phylink_config *config,
+ struct phylink_link_state *state)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+ int err;
+
+@@ -1589,7 +1589,7 @@ static struct phylink_pcs *
+ dsa_port_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
+ struct dsa_switch *ds = dp->ds;
+
+@@ -1603,7 +1603,7 @@ static void dsa_port_phylink_mac_config(
+ unsigned int mode,
+ const struct phylink_link_state *state)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_mac_config)
+@@ -1614,7 +1614,7 @@ static void dsa_port_phylink_mac_config(
+
+ static void dsa_port_phylink_mac_an_restart(struct phylink_config *config)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_mac_an_restart)
+@@ -1627,7 +1627,7 @@ static void dsa_port_phylink_mac_link_do
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct phy_device *phydev = NULL;
+ struct dsa_switch *ds = dp->ds;
+
+@@ -1650,7 +1650,7 @@ static void dsa_port_phylink_mac_link_up
+ int speed, int duplex,
+ bool tx_pause, bool rx_pause)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_mac_link_up) {
--- /dev/null
+From c22d8240fcd73a1c3ec8dcb055bd583fb970c375 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 10 Apr 2024 20:42:43 +0100
+Subject: [PATCH 2/2] net: dsa: allow DSA switch drivers to provide their own
+ phylink mac ops
+
+Rather than having a shim for each and every phylink MAC operation,
+allow DSA switch drivers to provide their own ops structure. When a
+DSA driver provides the phylink MAC operations, the shimmed ops must
+not be provided, so fail an attempt to register a switch with both
+the phylink_mac_ops in struct dsa_switch and the phylink_mac_*
+operations populated in dsa_switch_ops populated.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Link: https://lore.kernel.org/r/E1rudqF-006K9H-Cc@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ include/net/dsa.h | 5 +++++
+ net/dsa/dsa.c | 11 +++++++++++
+ net/dsa/port.c | 26 ++++++++++++++++++++------
+ 3 files changed, 36 insertions(+), 6 deletions(-)
+
+--- a/include/net/dsa.h
++++ b/include/net/dsa.h
+@@ -468,6 +468,11 @@ struct dsa_switch {
+ const struct dsa_switch_ops *ops;
+
+ /*
++ * Allow a DSA switch driver to override the phylink MAC ops
++ */
++ const struct phylink_mac_ops *phylink_mac_ops;
++
++ /*
+ * Slave mii_bus and devices for the individual ports.
+ */
+ u32 phys_mii_mask;
+--- a/net/dsa/port.c
++++ b/net/dsa/port.c
+@@ -1675,6 +1675,7 @@ static const struct phylink_mac_ops dsa_
+
+ int dsa_port_phylink_create(struct dsa_port *dp)
+ {
++ const struct phylink_mac_ops *mac_ops;
+ struct dsa_switch *ds = dp->ds;
+ phy_interface_t mode;
+ struct phylink *pl;
+@@ -1694,8 +1695,12 @@ int dsa_port_phylink_create(struct dsa_p
+ if (ds->ops->phylink_get_caps)
+ ds->ops->phylink_get_caps(ds, dp->index, &dp->pl_config);
+
+- pl = phylink_create(&dp->pl_config, of_fwnode_handle(dp->dn),
+- mode, &dsa_port_phylink_mac_ops);
++ mac_ops = &dsa_port_phylink_mac_ops;
++ if (ds->phylink_mac_ops)
++ mac_ops = ds->phylink_mac_ops;
++
++ pl = phylink_create(&dp->pl_config, of_fwnode_handle(dp->dn), mode,
++ mac_ops);
+ if (IS_ERR(pl)) {
+ pr_err("error creating PHYLINK: %ld\n", PTR_ERR(pl));
+ return PTR_ERR(pl);
+@@ -1961,12 +1966,23 @@ static void dsa_shared_port_validate_of(
+ dn, dsa_port_is_cpu(dp) ? "CPU" : "DSA", dp->index);
+ }
+
++static void dsa_shared_port_link_down(struct dsa_port *dp)
++{
++ struct dsa_switch *ds = dp->ds;
++
++ if (ds->phylink_mac_ops && ds->phylink_mac_ops->mac_link_down)
++ ds->phylink_mac_ops->mac_link_down(&dp->pl_config, MLO_AN_FIXED,
++ PHY_INTERFACE_MODE_NA);
++ else if (ds->ops->phylink_mac_link_down)
++ ds->ops->phylink_mac_link_down(ds, dp->index, MLO_AN_FIXED,
++ PHY_INTERFACE_MODE_NA);
++}
++
+ int dsa_shared_port_link_register_of(struct dsa_port *dp)
+ {
+ struct dsa_switch *ds = dp->ds;
+ bool missing_link_description;
+ bool missing_phy_mode;
+- int port = dp->index;
+
+ dsa_shared_port_validate_of(dp, &missing_phy_mode,
+ &missing_link_description);
+@@ -1982,9 +1998,7 @@ int dsa_shared_port_link_register_of(str
+ "Skipping phylink registration for %s port %d\n",
+ dsa_port_is_cpu(dp) ? "CPU" : "DSA", dp->index);
+ } else {
+- if (ds->ops->phylink_mac_link_down)
+- ds->ops->phylink_mac_link_down(ds, port,
+- MLO_AN_FIXED, PHY_INTERFACE_MODE_NA);
++ dsa_shared_port_link_down(dp);
+
+ return dsa_shared_port_phylink_register(dp);
+ }
+--- a/net/dsa/dsa2.c
++++ b/net/dsa/dsa2.c
+@@ -1758,6 +1758,15 @@ static int dsa_switch_probe(struct dsa_s
+ if (!ds->num_ports)
+ return -EINVAL;
+
++ if (ds->phylink_mac_ops) {
++ if (ds->ops->phylink_mac_select_pcs ||
++ ds->ops->phylink_mac_config ||
++ ds->ops->phylink_mac_link_down ||
++ ds->ops->phylink_mac_link_up ||
++ ds->ops->adjust_link)
++ return -EINVAL;
++ }
++
+ if (np) {
+ err = dsa_switch_parse_of(ds, np);
+ if (err)
+++ /dev/null
-From patchwork Thu Mar 9 10:57:44 2023
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 8bit
-X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
-X-Patchwork-Id: 13167235
-X-Patchwork-Delegate: kuba@kernel.org
-Return-Path: <netdev-owner@vger.kernel.org>
-Date: Thu, 9 Mar 2023 10:57:44 +0000
-From: Daniel Golle <daniel@makrotopia.org>
-To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org,
- linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
- Russell King <linux@armlinux.org.uk>,
- Heiner Kallweit <hkallweit1@gmail.com>,
- Lorenzo Bianconi <lorenzo@kernel.org>,
- Mark Lee <Mark-MC.Lee@mediatek.com>,
- John Crispin <john@phrozen.org>, Felix Fietkau <nbd@nbd.name>,
- AngeloGioacchino Del Regno
- <angelogioacchino.delregno@collabora.com>,
- Matthias Brugger <matthias.bgg@gmail.com>,
- DENG Qingfang <dqfext@gmail.com>,
- Landen Chao <Landen.Chao@mediatek.com>,
- Sean Wang <sean.wang@mediatek.com>,
- Paolo Abeni <pabeni@redhat.com>,
- Jakub Kicinski <kuba@kernel.org>,
- Eric Dumazet <edumazet@google.com>,
- "David S. Miller" <davem@davemloft.net>,
- Vladimir Oltean <olteanv@gmail.com>,
- Florian Fainelli <f.fainelli@gmail.com>,
- Andrew Lunn <andrew@lunn.ch>,
- Vladimir Oltean <vladimir.oltean@nxp.com>
-Cc: =?iso-8859-1?q?Bj=F8rn?= Mork <bjorn@mork.no>,
- Frank Wunderlich <frank-w@public-files.de>,
- Alexander Couzens <lynxis@fe80.eu>
-Subject: [PATCH net-next v13 11/16] net: dsa: mt7530: use external PCS driver
-Message-ID:
- <2ac2ee40d3b0e705461b50613fda6a7edfdbc4b3.1678357225.git.daniel@makrotopia.org>
-References: <cover.1678357225.git.daniel@makrotopia.org>
-MIME-Version: 1.0
-Content-Disposition: inline
-In-Reply-To: <cover.1678357225.git.daniel@makrotopia.org>
-Precedence: bulk
-List-ID: <netdev.vger.kernel.org>
-X-Mailing-List: netdev@vger.kernel.org
-X-Patchwork-Delegate: kuba@kernel.org
-
-Implement regmap access wrappers, for now only to be used by the
-pcs-mtk driver.
-Make use of external PCS driver and drop the reduntant implementation
-in mt7530.c.
-As a nice side effect the SGMII registers can now also more easily be
-inspected for debugging via /sys/kernel/debug/regmap.
-
-Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
-Tested-by: Bjørn Mork <bjorn@mork.no>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Tested-by: Frank Wunderlich <frank-w@public-files.de>
----
- drivers/net/dsa/Kconfig | 1 +
- drivers/net/dsa/mt7530.c | 277 ++++++++++-----------------------------
- drivers/net/dsa/mt7530.h | 47 +------
- 3 files changed, 71 insertions(+), 254 deletions(-)
-
---- a/drivers/net/dsa/Kconfig
-+++ b/drivers/net/dsa/Kconfig
-@@ -37,6 +37,7 @@ config NET_DSA_MT7530
- tristate "MediaTek MT753x and MT7621 Ethernet switch support"
- select NET_DSA_TAG_MTK
- select MEDIATEK_GE_PHY
-+ select PCS_MTK_LYNXI
- help
- This enables support for the MediaTek MT7530, MT7531, and MT7621
- Ethernet switch chips.
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -14,6 +14,7 @@
- #include <linux/of_mdio.h>
- #include <linux/of_net.h>
- #include <linux/of_platform.h>
-+#include <linux/pcs/pcs-mtk-lynxi.h>
- #include <linux/phylink.h>
- #include <linux/regmap.h>
- #include <linux/regulator/consumer.h>
-@@ -2615,128 +2616,11 @@ static int mt7531_rgmii_setup(struct mt7
- return 0;
- }
-
--static void mt7531_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
-- phy_interface_t interface, int speed, int duplex)
--{
-- struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
-- int port = pcs_to_mt753x_pcs(pcs)->port;
-- unsigned int val;
--
-- /* For adjusting speed and duplex of SGMII force mode. */
-- if (interface != PHY_INTERFACE_MODE_SGMII ||
-- phylink_autoneg_inband(mode))
-- return;
--
-- /* SGMII force mode setting */
-- val = mt7530_read(priv, MT7531_SGMII_MODE(port));
-- val &= ~MT7531_SGMII_IF_MODE_MASK;
--
-- switch (speed) {
-- case SPEED_10:
-- val |= MT7531_SGMII_FORCE_SPEED_10;
-- break;
-- case SPEED_100:
-- val |= MT7531_SGMII_FORCE_SPEED_100;
-- break;
-- case SPEED_1000:
-- val |= MT7531_SGMII_FORCE_SPEED_1000;
-- break;
-- }
--
-- /* MT7531 SGMII 1G force mode can only work in full duplex mode,
-- * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
-- *
-- * The speed check is unnecessary as the MAC capabilities apply
-- * this restriction. --rmk
-- */
-- if ((speed == SPEED_10 || speed == SPEED_100) &&
-- duplex != DUPLEX_FULL)
-- val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
--
-- mt7530_write(priv, MT7531_SGMII_MODE(port), val);
--}
--
- static bool mt753x_is_mac_port(u32 port)
- {
- return (port == 5 || port == 6);
- }
-
--static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
-- phy_interface_t interface)
--{
-- u32 val;
--
-- if (!mt753x_is_mac_port(port))
-- return -EINVAL;
--
-- mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
-- MT7531_SGMII_PHYA_PWD);
--
-- val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
-- val &= ~MT7531_RG_TPHY_SPEED_MASK;
-- /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
-- * encoding.
-- */
-- val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
-- MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
-- mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
--
-- mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
--
-- /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
-- * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
-- */
-- mt7530_rmw(priv, MT7531_SGMII_MODE(port),
-- MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
-- MT7531_SGMII_FORCE_SPEED_1000);
--
-- mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
--
-- return 0;
--}
--
--static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
-- phy_interface_t interface)
--{
-- if (!mt753x_is_mac_port(port))
-- return -EINVAL;
--
-- mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
-- MT7531_SGMII_PHYA_PWD);
--
-- mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
-- MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
--
-- mt7530_set(priv, MT7531_SGMII_MODE(port),
-- MT7531_SGMII_REMOTE_FAULT_DIS |
-- MT7531_SGMII_SPEED_DUPLEX_AN);
--
-- mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
-- MT7531_SGMII_TX_CONFIG_MASK, 1);
--
-- mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
--
-- mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
--
-- mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
--
-- return 0;
--}
--
--static void mt7531_pcs_an_restart(struct phylink_pcs *pcs)
--{
-- struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
-- int port = pcs_to_mt753x_pcs(pcs)->port;
-- u32 val;
--
-- /* Only restart AN when AN is enabled */
-- val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
-- if (val & MT7531_SGMII_AN_ENABLE) {
-- val |= MT7531_SGMII_AN_RESTART;
-- mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
-- }
--}
--
- static int
- mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
- phy_interface_t interface)
-@@ -2759,11 +2643,11 @@ mt7531_mac_config(struct dsa_switch *ds,
- phydev = dp->slave->phydev;
- return mt7531_rgmii_setup(priv, port, interface, phydev);
- case PHY_INTERFACE_MODE_SGMII:
-- return mt7531_sgmii_setup_mode_an(priv, port, interface);
- case PHY_INTERFACE_MODE_NA:
- case PHY_INTERFACE_MODE_1000BASEX:
- case PHY_INTERFACE_MODE_2500BASEX:
-- return mt7531_sgmii_setup_mode_force(priv, port, interface);
-+ /* handled in SGMII PCS driver */
-+ return 0;
- default:
- return -EINVAL;
- }
-@@ -2788,11 +2672,11 @@ mt753x_phylink_mac_select_pcs(struct dsa
-
- switch (interface) {
- case PHY_INTERFACE_MODE_TRGMII:
-+ return &priv->pcs[port].pcs;
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
- case PHY_INTERFACE_MODE_2500BASEX:
-- return &priv->pcs[port].pcs;
--
-+ return priv->ports[port].sgmii_pcs;
- default:
- return NULL;
- }
-@@ -3033,86 +2917,6 @@ static void mt7530_pcs_get_state(struct
- state->pause |= MLO_PAUSE_TX;
- }
-
--static int
--mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
-- struct phylink_link_state *state)
--{
-- u32 status, val;
-- u16 config_reg;
--
-- status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
-- state->link = !!(status & MT7531_SGMII_LINK_STATUS);
-- state->an_complete = !!(status & MT7531_SGMII_AN_COMPLETE);
-- if (state->interface == PHY_INTERFACE_MODE_SGMII &&
-- (status & MT7531_SGMII_AN_ENABLE)) {
-- val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
-- config_reg = val >> 16;
--
-- switch (config_reg & LPA_SGMII_SPD_MASK) {
-- case LPA_SGMII_1000:
-- state->speed = SPEED_1000;
-- break;
-- case LPA_SGMII_100:
-- state->speed = SPEED_100;
-- break;
-- case LPA_SGMII_10:
-- state->speed = SPEED_10;
-- break;
-- default:
-- dev_err(priv->dev, "invalid sgmii PHY speed\n");
-- state->link = false;
-- return -EINVAL;
-- }
--
-- if (config_reg & LPA_SGMII_FULL_DUPLEX)
-- state->duplex = DUPLEX_FULL;
-- else
-- state->duplex = DUPLEX_HALF;
-- }
--
-- return 0;
--}
--
--static void
--mt7531_sgmii_pcs_get_state_inband(struct mt7530_priv *priv, int port,
-- struct phylink_link_state *state)
--{
-- unsigned int val;
--
-- val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
-- state->link = !!(val & MT7531_SGMII_LINK_STATUS);
-- if (!state->link)
-- return;
--
-- state->an_complete = state->link;
--
-- if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
-- state->speed = SPEED_2500;
-- else
-- state->speed = SPEED_1000;
--
-- state->duplex = DUPLEX_FULL;
-- state->pause = MLO_PAUSE_NONE;
--}
--
--static void mt7531_pcs_get_state(struct phylink_pcs *pcs,
-- struct phylink_link_state *state)
--{
-- struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
-- int port = pcs_to_mt753x_pcs(pcs)->port;
--
-- if (state->interface == PHY_INTERFACE_MODE_SGMII) {
-- mt7531_sgmii_pcs_get_state_an(priv, port, state);
-- return;
-- } else if ((state->interface == PHY_INTERFACE_MODE_1000BASEX) ||
-- (state->interface == PHY_INTERFACE_MODE_2500BASEX)) {
-- mt7531_sgmii_pcs_get_state_inband(priv, port, state);
-- return;
-- }
--
-- state->link = false;
--}
--
- static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
- phy_interface_t interface,
- const unsigned long *advertising,
-@@ -3132,18 +2936,57 @@ static const struct phylink_pcs_ops mt75
- .pcs_an_restart = mt7530_pcs_an_restart,
- };
-
--static const struct phylink_pcs_ops mt7531_pcs_ops = {
-- .pcs_validate = mt753x_pcs_validate,
-- .pcs_get_state = mt7531_pcs_get_state,
-- .pcs_config = mt753x_pcs_config,
-- .pcs_an_restart = mt7531_pcs_an_restart,
-- .pcs_link_up = mt7531_pcs_link_up,
-+static int mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
-+{
-+ struct mt7530_priv *priv = context;
-+
-+ *val = mt7530_read(priv, reg);
-+ return 0;
-+};
-+
-+static int mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
-+{
-+ struct mt7530_priv *priv = context;
-+
-+ mt7530_write(priv, reg, val);
-+ return 0;
-+};
-+
-+static int mt7530_regmap_update_bits(void *context, unsigned int reg,
-+ unsigned int mask, unsigned int val)
-+{
-+ struct mt7530_priv *priv = context;
-+
-+ mt7530_rmw(priv, reg, mask, val);
-+ return 0;
-+};
-+
-+static const struct regmap_bus mt7531_regmap_bus = {
-+ .reg_write = mt7530_regmap_write,
-+ .reg_read = mt7530_regmap_read,
-+ .reg_update_bits = mt7530_regmap_update_bits,
-+};
-+
-+#define MT7531_PCS_REGMAP_CONFIG(_name, _reg_base) \
-+ { \
-+ .name = _name, \
-+ .reg_bits = 16, \
-+ .val_bits = 32, \
-+ .reg_stride = 4, \
-+ .reg_base = _reg_base, \
-+ .max_register = 0x17c, \
-+ }
-+
-+static const struct regmap_config mt7531_pcs_config[] = {
-+ MT7531_PCS_REGMAP_CONFIG("port5", MT7531_SGMII_REG_BASE(5)),
-+ MT7531_PCS_REGMAP_CONFIG("port6", MT7531_SGMII_REG_BASE(6)),
- };
-
- static int
- mt753x_setup(struct dsa_switch *ds)
- {
- struct mt7530_priv *priv = ds->priv;
-+ struct regmap *regmap;
- int i, ret;
-
- /* Initialise the PCS devices */
-@@ -3151,8 +2994,6 @@ mt753x_setup(struct dsa_switch *ds)
- priv->pcs[i].pcs.ops = priv->info->pcs_ops;
- priv->pcs[i].priv = priv;
- priv->pcs[i].port = i;
-- if (mt753x_is_mac_port(i))
-- priv->pcs[i].pcs.poll = 1;
- }
-
- ret = priv->info->sw_setup(ds);
-@@ -3167,6 +3008,16 @@ mt753x_setup(struct dsa_switch *ds)
- if (ret && priv->irq)
- mt7530_free_irq_common(priv);
-
-+ if (priv->id == ID_MT7531)
-+ for (i = 0; i < 2; i++) {
-+ regmap = devm_regmap_init(ds->dev,
-+ &mt7531_regmap_bus, priv,
-+ &mt7531_pcs_config[i]);
-+ priv->ports[5 + i].sgmii_pcs =
-+ mtk_pcs_lynxi_create(ds->dev, regmap,
-+ MT7531_PHYA_CTRL_SIGNAL3, 0);
-+ }
-+
- return ret;
- }
-
-@@ -3258,7 +3109,7 @@ static const struct mt753x_info mt753x_t
- },
- [ID_MT7531] = {
- .id = ID_MT7531,
-- .pcs_ops = &mt7531_pcs_ops,
-+ .pcs_ops = &mt7530_pcs_ops,
- .sw_setup = mt7531_setup,
- .phy_read = mt7531_ind_phy_read,
- .phy_write = mt7531_ind_phy_write,
-@@ -3366,7 +3217,7 @@ static void
- mt7530_remove(struct mdio_device *mdiodev)
- {
- struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
-- int ret = 0;
-+ int ret = 0, i;
-
- if (!priv)
- return;
-@@ -3385,6 +3236,10 @@ mt7530_remove(struct mdio_device *mdiode
- mt7530_free_irq(priv);
-
- dsa_unregister_switch(priv->ds);
-+
-+ for (i = 0; i < 2; ++i)
-+ mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
-+
- mutex_destroy(&priv->reg_mutex);
- }
-
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -371,47 +371,8 @@ enum mt7530_vlan_port_acc_frm {
- CCR_TX_OCT_CNT_BAD)
-
- /* MT7531 SGMII register group */
--#define MT7531_SGMII_REG_BASE 0x5000
--#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
-- ((p) - 5) * 0x1000 + (r))
--
--/* Register forSGMII PCS_CONTROL_1 */
--#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
--#define MT7531_SGMII_LINK_STATUS BIT(18)
--#define MT7531_SGMII_AN_ENABLE BIT(12)
--#define MT7531_SGMII_AN_RESTART BIT(9)
--#define MT7531_SGMII_AN_COMPLETE BIT(21)
--
--/* Register for SGMII PCS_SPPED_ABILITY */
--#define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
--#define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
--#define MT7531_SGMII_TX_CONFIG BIT(0)
--
--/* Register for SGMII_MODE */
--#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
--#define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
--#define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1)
--#define MT7531_SGMII_FORCE_DUPLEX BIT(4)
--#define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2)
--#define MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
--#define MT7531_SGMII_FORCE_SPEED_100 BIT(2)
--#define MT7531_SGMII_FORCE_SPEED_10 0
--#define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1)
--
--enum mt7531_sgmii_force_duplex {
-- MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
-- MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
--};
--
--/* Fields of QPHY_PWR_STATE_CTRL */
--#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
--#define MT7531_SGMII_PHYA_PWD BIT(4)
--
--/* Values of SGMII SPEED */
--#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
--#define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3))
--#define MT7531_RG_TPHY_SPEED_1_25G 0x0
--#define MT7531_RG_TPHY_SPEED_3_125G BIT(2)
-+#define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
-+#define MT7531_PHYA_CTRL_SIGNAL3 0x128
-
- /* Register for system reset */
- #define MT7530_SYS_CTRL 0x7000
-@@ -710,13 +671,13 @@ struct mt7530_fdb {
- * @pm: The matrix used to show all connections with the port.
- * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
- * untagged frames will be assigned to the related VLAN.
-- * @vlan_filtering: The flags indicating whether the port that can recognize
-- * VLAN-tagged frames.
-+ * @sgmii_pcs: Pointer to PCS instance for SerDes ports
- */
- struct mt7530_port {
- bool enable;
- u32 pm;
- u16 pvid;
-+ struct phylink_pcs *sgmii_pcs;
- };
-
- /* Port 5 interface select definitions */
--- /dev/null
+From 27b692012840f658c84a3102c0aeca2676f03132 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 15 Dec 2022 03:47:59 +0000
+Subject: [PATCH 01/48] net: dsa: mt7530: remove redundant assignment
+
+Russell King correctly pointed out that the MAC_2500FD capability is
+already added for port 5 (if not in RGMII mode) and port 6 (which only
+supports SGMII) by mt7531_mac_port_get_caps. Remove the reduntant
+setting of this capability flag which was added by a previous commit.
+
+Fixes: e19de30d2080 ("net: dsa: mt7530: add support for in-band link status")
+Reported-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/Y5qY7x6la5TxZxzX@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3198,9 +3198,6 @@ static void mt753x_phylink_get_caps(stru
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10 | MAC_100 | MAC_1000FD;
+
+- if ((priv->id == ID_MT7531) && mt753x_is_mac_port(port))
+- config->mac_capabilities |= MAC_2500FD;
+-
+ /* This driver does not make use of the speed, duplex, pause or the
+ * advertisement in its mac_config, so it is safe to mark this driver
+ * as non-legacy.
--- /dev/null
+From 05dc5ea089f947a69a5db092ef4cad6a0f3c96ce Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 19 Mar 2023 12:58:43 +0000
+Subject: [PATCH 02/48] net: dsa: mt7530: use external PCS driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Implement regmap access wrappers, for now only to be used by the
+pcs-mtk-lynxi driver.
+Make use of this external PCS driver and drop the now reduntant
+implementation in mt7530.c.
+As a nice side effect the SGMII registers can now also more easily be
+inspected for debugging via /sys/kernel/debug/regmap.
+
+Tested-by: Bjørn Mork <bjorn@mork.no>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Frank Wunderlich <frank-w@public-files.de>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/Kconfig | 1 +
+ drivers/net/dsa/mt7530.c | 277 ++++++++++-----------------------------
+ drivers/net/dsa/mt7530.h | 47 +------
+ 3 files changed, 71 insertions(+), 254 deletions(-)
+
+--- a/drivers/net/dsa/Kconfig
++++ b/drivers/net/dsa/Kconfig
+@@ -37,6 +37,7 @@ config NET_DSA_MT7530
+ tristate "MediaTek MT753x and MT7621 Ethernet switch support"
+ select NET_DSA_TAG_MTK
+ select MEDIATEK_GE_PHY
++ select PCS_MTK_LYNXI
+ help
+ This enables support for the MediaTek MT7530, MT7531, and MT7621
+ Ethernet switch chips.
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -14,6 +14,7 @@
+ #include <linux/of_mdio.h>
+ #include <linux/of_net.h>
+ #include <linux/of_platform.h>
++#include <linux/pcs/pcs-mtk-lynxi.h>
+ #include <linux/phylink.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
+@@ -2839,128 +2840,11 @@ static int mt7531_rgmii_setup(struct mt7
+ return 0;
+ }
+
+-static void mt7531_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
+- phy_interface_t interface, int speed, int duplex)
+-{
+- struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
+- int port = pcs_to_mt753x_pcs(pcs)->port;
+- unsigned int val;
+-
+- /* For adjusting speed and duplex of SGMII force mode. */
+- if (interface != PHY_INTERFACE_MODE_SGMII ||
+- phylink_autoneg_inband(mode))
+- return;
+-
+- /* SGMII force mode setting */
+- val = mt7530_read(priv, MT7531_SGMII_MODE(port));
+- val &= ~MT7531_SGMII_IF_MODE_MASK;
+-
+- switch (speed) {
+- case SPEED_10:
+- val |= MT7531_SGMII_FORCE_SPEED_10;
+- break;
+- case SPEED_100:
+- val |= MT7531_SGMII_FORCE_SPEED_100;
+- break;
+- case SPEED_1000:
+- val |= MT7531_SGMII_FORCE_SPEED_1000;
+- break;
+- }
+-
+- /* MT7531 SGMII 1G force mode can only work in full duplex mode,
+- * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
+- *
+- * The speed check is unnecessary as the MAC capabilities apply
+- * this restriction. --rmk
+- */
+- if ((speed == SPEED_10 || speed == SPEED_100) &&
+- duplex != DUPLEX_FULL)
+- val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
+-
+- mt7530_write(priv, MT7531_SGMII_MODE(port), val);
+-}
+-
+ static bool mt753x_is_mac_port(u32 port)
+ {
+ return (port == 5 || port == 6);
+ }
+
+-static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
+- phy_interface_t interface)
+-{
+- u32 val;
+-
+- if (!mt753x_is_mac_port(port))
+- return -EINVAL;
+-
+- mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
+- MT7531_SGMII_PHYA_PWD);
+-
+- val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
+- val &= ~MT7531_RG_TPHY_SPEED_MASK;
+- /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
+- * encoding.
+- */
+- val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
+- MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
+- mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
+-
+- mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
+-
+- /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
+- * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
+- */
+- mt7530_rmw(priv, MT7531_SGMII_MODE(port),
+- MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
+- MT7531_SGMII_FORCE_SPEED_1000);
+-
+- mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
+-
+- return 0;
+-}
+-
+-static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
+- phy_interface_t interface)
+-{
+- if (!mt753x_is_mac_port(port))
+- return -EINVAL;
+-
+- mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
+- MT7531_SGMII_PHYA_PWD);
+-
+- mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
+- MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
+-
+- mt7530_set(priv, MT7531_SGMII_MODE(port),
+- MT7531_SGMII_REMOTE_FAULT_DIS |
+- MT7531_SGMII_SPEED_DUPLEX_AN);
+-
+- mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
+- MT7531_SGMII_TX_CONFIG_MASK, 1);
+-
+- mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
+-
+- mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
+-
+- mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
+-
+- return 0;
+-}
+-
+-static void mt7531_pcs_an_restart(struct phylink_pcs *pcs)
+-{
+- struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
+- int port = pcs_to_mt753x_pcs(pcs)->port;
+- u32 val;
+-
+- /* Only restart AN when AN is enabled */
+- val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
+- if (val & MT7531_SGMII_AN_ENABLE) {
+- val |= MT7531_SGMII_AN_RESTART;
+- mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
+- }
+-}
+-
+ static int
+ mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ phy_interface_t interface)
+@@ -2983,11 +2867,11 @@ mt7531_mac_config(struct dsa_switch *ds,
+ phydev = dp->slave->phydev;
+ return mt7531_rgmii_setup(priv, port, interface, phydev);
+ case PHY_INTERFACE_MODE_SGMII:
+- return mt7531_sgmii_setup_mode_an(priv, port, interface);
+ case PHY_INTERFACE_MODE_NA:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+- return mt7531_sgmii_setup_mode_force(priv, port, interface);
++ /* handled in SGMII PCS driver */
++ return 0;
+ default:
+ return -EINVAL;
+ }
+@@ -3012,11 +2896,11 @@ mt753x_phylink_mac_select_pcs(struct dsa
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_TRGMII:
++ return &priv->pcs[port].pcs;
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+- return &priv->pcs[port].pcs;
+-
++ return priv->ports[port].sgmii_pcs;
+ default:
+ return NULL;
+ }
+@@ -3254,86 +3138,6 @@ static void mt7530_pcs_get_state(struct
+ state->pause |= MLO_PAUSE_TX;
+ }
+
+-static int
+-mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
+- struct phylink_link_state *state)
+-{
+- u32 status, val;
+- u16 config_reg;
+-
+- status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
+- state->link = !!(status & MT7531_SGMII_LINK_STATUS);
+- state->an_complete = !!(status & MT7531_SGMII_AN_COMPLETE);
+- if (state->interface == PHY_INTERFACE_MODE_SGMII &&
+- (status & MT7531_SGMII_AN_ENABLE)) {
+- val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
+- config_reg = val >> 16;
+-
+- switch (config_reg & LPA_SGMII_SPD_MASK) {
+- case LPA_SGMII_1000:
+- state->speed = SPEED_1000;
+- break;
+- case LPA_SGMII_100:
+- state->speed = SPEED_100;
+- break;
+- case LPA_SGMII_10:
+- state->speed = SPEED_10;
+- break;
+- default:
+- dev_err(priv->dev, "invalid sgmii PHY speed\n");
+- state->link = false;
+- return -EINVAL;
+- }
+-
+- if (config_reg & LPA_SGMII_FULL_DUPLEX)
+- state->duplex = DUPLEX_FULL;
+- else
+- state->duplex = DUPLEX_HALF;
+- }
+-
+- return 0;
+-}
+-
+-static void
+-mt7531_sgmii_pcs_get_state_inband(struct mt7530_priv *priv, int port,
+- struct phylink_link_state *state)
+-{
+- unsigned int val;
+-
+- val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
+- state->link = !!(val & MT7531_SGMII_LINK_STATUS);
+- if (!state->link)
+- return;
+-
+- state->an_complete = state->link;
+-
+- if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
+- state->speed = SPEED_2500;
+- else
+- state->speed = SPEED_1000;
+-
+- state->duplex = DUPLEX_FULL;
+- state->pause = MLO_PAUSE_NONE;
+-}
+-
+-static void mt7531_pcs_get_state(struct phylink_pcs *pcs,
+- struct phylink_link_state *state)
+-{
+- struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
+- int port = pcs_to_mt753x_pcs(pcs)->port;
+-
+- if (state->interface == PHY_INTERFACE_MODE_SGMII) {
+- mt7531_sgmii_pcs_get_state_an(priv, port, state);
+- return;
+- } else if ((state->interface == PHY_INTERFACE_MODE_1000BASEX) ||
+- (state->interface == PHY_INTERFACE_MODE_2500BASEX)) {
+- mt7531_sgmii_pcs_get_state_inband(priv, port, state);
+- return;
+- }
+-
+- state->link = false;
+-}
+-
+ static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+@@ -3353,18 +3157,57 @@ static const struct phylink_pcs_ops mt75
+ .pcs_an_restart = mt7530_pcs_an_restart,
+ };
+
+-static const struct phylink_pcs_ops mt7531_pcs_ops = {
+- .pcs_validate = mt753x_pcs_validate,
+- .pcs_get_state = mt7531_pcs_get_state,
+- .pcs_config = mt753x_pcs_config,
+- .pcs_an_restart = mt7531_pcs_an_restart,
+- .pcs_link_up = mt7531_pcs_link_up,
++static int mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
++{
++ struct mt7530_priv *priv = context;
++
++ *val = mt7530_read(priv, reg);
++ return 0;
++};
++
++static int mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
++{
++ struct mt7530_priv *priv = context;
++
++ mt7530_write(priv, reg, val);
++ return 0;
++};
++
++static int mt7530_regmap_update_bits(void *context, unsigned int reg,
++ unsigned int mask, unsigned int val)
++{
++ struct mt7530_priv *priv = context;
++
++ mt7530_rmw(priv, reg, mask, val);
++ return 0;
++};
++
++static const struct regmap_bus mt7531_regmap_bus = {
++ .reg_write = mt7530_regmap_write,
++ .reg_read = mt7530_regmap_read,
++ .reg_update_bits = mt7530_regmap_update_bits,
++};
++
++#define MT7531_PCS_REGMAP_CONFIG(_name, _reg_base) \
++ { \
++ .name = _name, \
++ .reg_bits = 16, \
++ .val_bits = 32, \
++ .reg_stride = 4, \
++ .reg_base = _reg_base, \
++ .max_register = 0x17c, \
++ }
++
++static const struct regmap_config mt7531_pcs_config[] = {
++ MT7531_PCS_REGMAP_CONFIG("port5", MT7531_SGMII_REG_BASE(5)),
++ MT7531_PCS_REGMAP_CONFIG("port6", MT7531_SGMII_REG_BASE(6)),
+ };
+
+ static int
+ mt753x_setup(struct dsa_switch *ds)
+ {
+ struct mt7530_priv *priv = ds->priv;
++ struct regmap *regmap;
+ int i, ret;
+
+ /* Initialise the PCS devices */
+@@ -3372,8 +3215,6 @@ mt753x_setup(struct dsa_switch *ds)
+ priv->pcs[i].pcs.ops = priv->info->pcs_ops;
+ priv->pcs[i].priv = priv;
+ priv->pcs[i].port = i;
+- if (mt753x_is_mac_port(i))
+- priv->pcs[i].pcs.poll = 1;
+ }
+
+ ret = priv->info->sw_setup(ds);
+@@ -3388,6 +3229,16 @@ mt753x_setup(struct dsa_switch *ds)
+ if (ret && priv->irq)
+ mt7530_free_irq_common(priv);
+
++ if (priv->id == ID_MT7531)
++ for (i = 0; i < 2; i++) {
++ regmap = devm_regmap_init(ds->dev,
++ &mt7531_regmap_bus, priv,
++ &mt7531_pcs_config[i]);
++ priv->ports[5 + i].sgmii_pcs =
++ mtk_pcs_lynxi_create(ds->dev, regmap,
++ MT7531_PHYA_CTRL_SIGNAL3, 0);
++ }
++
+ return ret;
+ }
+
+@@ -3480,7 +3331,7 @@ static const struct mt753x_info mt753x_t
+ },
+ [ID_MT7531] = {
+ .id = ID_MT7531,
+- .pcs_ops = &mt7531_pcs_ops,
++ .pcs_ops = &mt7530_pcs_ops,
+ .sw_setup = mt7531_setup,
+ .phy_read = mt7531_ind_phy_read,
+ .phy_write = mt7531_ind_phy_write,
+@@ -3588,7 +3439,7 @@ static void
+ mt7530_remove(struct mdio_device *mdiodev)
+ {
+ struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
+- int ret = 0;
++ int ret = 0, i;
+
+ if (!priv)
+ return;
+@@ -3607,6 +3458,10 @@ mt7530_remove(struct mdio_device *mdiode
+ mt7530_free_irq(priv);
+
+ dsa_unregister_switch(priv->ds);
++
++ for (i = 0; i < 2; ++i)
++ mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
++
+ mutex_destroy(&priv->reg_mutex);
+ }
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -401,47 +401,8 @@ enum mt7530_vlan_port_acc_frm {
+ CCR_TX_OCT_CNT_BAD)
+
+ /* MT7531 SGMII register group */
+-#define MT7531_SGMII_REG_BASE 0x5000
+-#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
+- ((p) - 5) * 0x1000 + (r))
+-
+-/* Register forSGMII PCS_CONTROL_1 */
+-#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
+-#define MT7531_SGMII_LINK_STATUS BIT(18)
+-#define MT7531_SGMII_AN_ENABLE BIT(12)
+-#define MT7531_SGMII_AN_RESTART BIT(9)
+-#define MT7531_SGMII_AN_COMPLETE BIT(21)
+-
+-/* Register for SGMII PCS_SPPED_ABILITY */
+-#define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
+-#define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
+-#define MT7531_SGMII_TX_CONFIG BIT(0)
+-
+-/* Register for SGMII_MODE */
+-#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
+-#define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
+-#define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1)
+-#define MT7531_SGMII_FORCE_DUPLEX BIT(4)
+-#define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2)
+-#define MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
+-#define MT7531_SGMII_FORCE_SPEED_100 BIT(2)
+-#define MT7531_SGMII_FORCE_SPEED_10 0
+-#define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1)
+-
+-enum mt7531_sgmii_force_duplex {
+- MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
+- MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
+-};
+-
+-/* Fields of QPHY_PWR_STATE_CTRL */
+-#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
+-#define MT7531_SGMII_PHYA_PWD BIT(4)
+-
+-/* Values of SGMII SPEED */
+-#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
+-#define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3))
+-#define MT7531_RG_TPHY_SPEED_1_25G 0x0
+-#define MT7531_RG_TPHY_SPEED_3_125G BIT(2)
++#define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
++#define MT7531_PHYA_CTRL_SIGNAL3 0x128
+
+ /* Register for system reset */
+ #define MT7530_SYS_CTRL 0x7000
+@@ -741,13 +702,13 @@ struct mt7530_fdb {
+ * @pm: The matrix used to show all connections with the port.
+ * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
+ * untagged frames will be assigned to the related VLAN.
+- * @vlan_filtering: The flags indicating whether the port that can recognize
+- * VLAN-tagged frames.
++ * @sgmii_pcs: Pointer to PCS instance for SerDes ports
+ */
+ struct mt7530_port {
+ bool enable;
+ u32 pm;
+ u16 pvid;
++ struct phylink_pcs *sgmii_pcs;
+ };
+
+ /* Port 5 interface select definitions */
--- /dev/null
+From cafbb70e148e7a4e318dcc1e36a96643815b6245 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:17:19 +0100
+Subject: [PATCH 03/48] net: dsa: mt7530: make some noise if register read
+ fails
+
+Simply returning the negative error value instead of the read value
+doesn't seem like a good idea. Return 0 instead and add WARN_ON_ONCE(1)
+so this kind of error will not go unnoticed.
+
+Suggested-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -224,9 +224,10 @@ mt7530_mii_read(struct mt7530_priv *priv
+ /* MT7530 uses 31 as the pseudo port */
+ ret = bus->write(bus, 0x1f, 0x1f, page);
+ if (ret < 0) {
++ WARN_ON_ONCE(1);
+ dev_err(&bus->dev,
+ "failed to read mt7530 register\n");
+- return ret;
++ return 0;
+ }
+
+ lo = bus->read(bus, 0x1f, r);
--- /dev/null
+From 8f83ad87e2df26ddf9b8afd4d2873644a872d929 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:17:30 +0100
+Subject: [PATCH 04/48] net: dsa: mt7530: refactor SGMII PCS creation
+
+Instead of macro templates use a dedidated function and allocated
+regmap_config when creating the regmaps for the pcs-mtk-lynxi
+instances.
+This is in preparation to switching to use unlocked regmap accessors
+and have regmap's locking API handle locking for us.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 74 +++++++++++++++++++++++++++-------------
+ 1 file changed, 50 insertions(+), 24 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3189,26 +3189,56 @@ static const struct regmap_bus mt7531_re
+ .reg_update_bits = mt7530_regmap_update_bits,
+ };
+
+-#define MT7531_PCS_REGMAP_CONFIG(_name, _reg_base) \
+- { \
+- .name = _name, \
+- .reg_bits = 16, \
+- .val_bits = 32, \
+- .reg_stride = 4, \
+- .reg_base = _reg_base, \
+- .max_register = 0x17c, \
++static int
++mt7531_create_sgmii(struct mt7530_priv *priv)
++{
++ struct regmap_config *mt7531_pcs_config[2];
++ struct phylink_pcs *pcs;
++ struct regmap *regmap;
++ int i, ret = 0;
++
++ for (i = 0; i < 2; i++) {
++ mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
++ sizeof(struct regmap_config),
++ GFP_KERNEL);
++ if (!mt7531_pcs_config[i]) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ mt7531_pcs_config[i]->name = i ? "port6" : "port5";
++ mt7531_pcs_config[i]->reg_bits = 16;
++ mt7531_pcs_config[i]->val_bits = 32;
++ mt7531_pcs_config[i]->reg_stride = 4;
++ mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
++ mt7531_pcs_config[i]->max_register = 0x17c;
++
++ regmap = devm_regmap_init(priv->dev,
++ &mt7531_regmap_bus, priv,
++ mt7531_pcs_config[i]);
++ if (IS_ERR(regmap)) {
++ ret = PTR_ERR(regmap);
++ break;
++ }
++ pcs = mtk_pcs_lynxi_create(priv->dev, regmap,
++ MT7531_PHYA_CTRL_SIGNAL3, 0);
++ if (!pcs) {
++ ret = -ENXIO;
++ break;
++ }
++ priv->ports[5 + i].sgmii_pcs = pcs;
+ }
+
+-static const struct regmap_config mt7531_pcs_config[] = {
+- MT7531_PCS_REGMAP_CONFIG("port5", MT7531_SGMII_REG_BASE(5)),
+- MT7531_PCS_REGMAP_CONFIG("port6", MT7531_SGMII_REG_BASE(6)),
+-};
++ if (ret && i)
++ mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs);
++
++ return ret;
++}
+
+ static int
+ mt753x_setup(struct dsa_switch *ds)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- struct regmap *regmap;
+ int i, ret;
+
+ /* Initialise the PCS devices */
+@@ -3230,15 +3260,11 @@ mt753x_setup(struct dsa_switch *ds)
+ if (ret && priv->irq)
+ mt7530_free_irq_common(priv);
+
+- if (priv->id == ID_MT7531)
+- for (i = 0; i < 2; i++) {
+- regmap = devm_regmap_init(ds->dev,
+- &mt7531_regmap_bus, priv,
+- &mt7531_pcs_config[i]);
+- priv->ports[5 + i].sgmii_pcs =
+- mtk_pcs_lynxi_create(ds->dev, regmap,
+- MT7531_PHYA_CTRL_SIGNAL3, 0);
+- }
++ if (priv->id == ID_MT7531) {
++ ret = mt7531_create_sgmii(priv);
++ if (ret && priv->irq)
++ mt7530_free_irq_common(priv);
++ }
+
+ return ret;
+ }
--- /dev/null
+From efb41b8e9b7bbb08ace1930373bff63d4f5cc6e2 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:17:40 +0100
+Subject: [PATCH 05/48] net: dsa: mt7530: use unlocked regmap accessors
+
+Instead of wrapping the locked register accessor functions, use the
+unlocked variants and add locking wrapper functions to let regmap
+handle the locking.
+
+This is a preparation towards being able to always use regmap to
+access switch registers instead of open-coded accessor functions.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 23 ++++++++++++++---------
+ 1 file changed, 14 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3162,7 +3162,7 @@ static int mt7530_regmap_read(void *cont
+ {
+ struct mt7530_priv *priv = context;
+
+- *val = mt7530_read(priv, reg);
++ *val = mt7530_mii_read(priv, reg);
+ return 0;
+ };
+
+@@ -3170,23 +3170,25 @@ static int mt7530_regmap_write(void *con
+ {
+ struct mt7530_priv *priv = context;
+
+- mt7530_write(priv, reg, val);
++ mt7530_mii_write(priv, reg, val);
+ return 0;
+ };
+
+-static int mt7530_regmap_update_bits(void *context, unsigned int reg,
+- unsigned int mask, unsigned int val)
++static void
++mt7530_mdio_regmap_lock(void *mdio_lock)
+ {
+- struct mt7530_priv *priv = context;
++ mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
++}
+
+- mt7530_rmw(priv, reg, mask, val);
+- return 0;
+-};
++static void
++mt7530_mdio_regmap_unlock(void *mdio_lock)
++{
++ mutex_unlock(mdio_lock);
++}
+
+ static const struct regmap_bus mt7531_regmap_bus = {
+ .reg_write = mt7530_regmap_write,
+ .reg_read = mt7530_regmap_read,
+- .reg_update_bits = mt7530_regmap_update_bits,
+ };
+
+ static int
+@@ -3212,6 +3214,9 @@ mt7531_create_sgmii(struct mt7530_priv *
+ mt7531_pcs_config[i]->reg_stride = 4;
+ mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
+ mt7531_pcs_config[i]->max_register = 0x17c;
++ mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock;
++ mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
++ mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
+
+ regmap = devm_regmap_init(priv->dev,
+ &mt7531_regmap_bus, priv,
--- /dev/null
+From c7945d11a060797c31b3f47d9c9e515b0bf2082f Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:17:52 +0100
+Subject: [PATCH 06/48] net: dsa: mt7530: use regmap to access switch register
+ space
+
+Use regmap API to access the switch register space.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 99 ++++++++++++++++++++++++----------------
+ drivers/net/dsa/mt7530.h | 2 +
+ 2 files changed, 62 insertions(+), 39 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -183,9 +183,9 @@ core_clear(struct mt7530_priv *priv, u32
+ }
+
+ static int
+-mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
++mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
+ {
+- struct mii_bus *bus = priv->bus;
++ struct mii_bus *bus = context;
+ u16 page, r, lo, hi;
+ int ret;
+
+@@ -197,24 +197,34 @@ mt7530_mii_write(struct mt7530_priv *pri
+ /* MT7530 uses 31 as the pseudo port */
+ ret = bus->write(bus, 0x1f, 0x1f, page);
+ if (ret < 0)
+- goto err;
++ return ret;
+
+ ret = bus->write(bus, 0x1f, r, lo);
+ if (ret < 0)
+- goto err;
++ return ret;
+
+ ret = bus->write(bus, 0x1f, 0x10, hi);
+-err:
++ return ret;
++}
++
++static int
++mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
++{
++ int ret;
++
++ ret = regmap_write(priv->regmap, reg, val);
++
+ if (ret < 0)
+- dev_err(&bus->dev,
++ dev_err(priv->dev,
+ "failed to write mt7530 register\n");
++
+ return ret;
+ }
+
+-static u32
+-mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
++static int
++mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
+ {
+- struct mii_bus *bus = priv->bus;
++ struct mii_bus *bus = context;
+ u16 page, r, lo, hi;
+ int ret;
+
+@@ -223,17 +233,32 @@ mt7530_mii_read(struct mt7530_priv *priv
+
+ /* MT7530 uses 31 as the pseudo port */
+ ret = bus->write(bus, 0x1f, 0x1f, page);
+- if (ret < 0) {
++ if (ret < 0)
++ return ret;
++
++ lo = bus->read(bus, 0x1f, r);
++ hi = bus->read(bus, 0x1f, 0x10);
++
++ *val = (hi << 16) | (lo & 0xffff);
++
++ return 0;
++}
++
++static u32
++mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
++{
++ int ret;
++ u32 val;
++
++ ret = regmap_read(priv->regmap, reg, &val);
++ if (ret) {
+ WARN_ON_ONCE(1);
+- dev_err(&bus->dev,
++ dev_err(priv->dev,
+ "failed to read mt7530 register\n");
+ return 0;
+ }
+
+- lo = bus->read(bus, 0x1f, r);
+- hi = bus->read(bus, 0x1f, 0x10);
+-
+- return (hi << 16) | (lo & 0xffff);
++ return val;
+ }
+
+ static void
+@@ -283,14 +308,10 @@ mt7530_rmw(struct mt7530_priv *priv, u32
+ u32 mask, u32 set)
+ {
+ struct mii_bus *bus = priv->bus;
+- u32 val;
+
+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+
+- val = mt7530_mii_read(priv, reg);
+- val &= ~mask;
+- val |= set;
+- mt7530_mii_write(priv, reg, val);
++ regmap_update_bits(priv->regmap, reg, mask, set);
+
+ mutex_unlock(&bus->mdio_lock);
+ }
+@@ -298,7 +319,7 @@ mt7530_rmw(struct mt7530_priv *priv, u32
+ static void
+ mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
+ {
+- mt7530_rmw(priv, reg, 0, val);
++ mt7530_rmw(priv, reg, val, val);
+ }
+
+ static void
+@@ -3158,22 +3179,6 @@ static const struct phylink_pcs_ops mt75
+ .pcs_an_restart = mt7530_pcs_an_restart,
+ };
+
+-static int mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
+-{
+- struct mt7530_priv *priv = context;
+-
+- *val = mt7530_mii_read(priv, reg);
+- return 0;
+-};
+-
+-static int mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
+-{
+- struct mt7530_priv *priv = context;
+-
+- mt7530_mii_write(priv, reg, val);
+- return 0;
+-};
+-
+ static void
+ mt7530_mdio_regmap_lock(void *mdio_lock)
+ {
+@@ -3186,7 +3191,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc
+ mutex_unlock(mdio_lock);
+ }
+
+-static const struct regmap_bus mt7531_regmap_bus = {
++static const struct regmap_bus mt7530_regmap_bus = {
+ .reg_write = mt7530_regmap_write,
+ .reg_read = mt7530_regmap_read,
+ };
+@@ -3219,7 +3224,7 @@ mt7531_create_sgmii(struct mt7530_priv *
+ mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
+
+ regmap = devm_regmap_init(priv->dev,
+- &mt7531_regmap_bus, priv,
++ &mt7530_regmap_bus, priv->bus,
+ mt7531_pcs_config[i]);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+@@ -3385,6 +3390,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match)
+ static int
+ mt7530_probe(struct mdio_device *mdiodev)
+ {
++ static struct regmap_config *regmap_config;
+ struct mt7530_priv *priv;
+ struct device_node *dn;
+
+@@ -3464,6 +3470,21 @@ mt7530_probe(struct mdio_device *mdiodev
+ mutex_init(&priv->reg_mutex);
+ dev_set_drvdata(&mdiodev->dev, priv);
+
++ regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
++ GFP_KERNEL);
++ if (!regmap_config)
++ return -ENOMEM;
++
++ regmap_config->reg_bits = 16;
++ regmap_config->val_bits = 32;
++ regmap_config->reg_stride = 4;
++ regmap_config->max_register = MT7530_CREV;
++ regmap_config->disable_locking = true;
++ priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
++ priv->bus, regmap_config);
++ if (IS_ERR(priv->regmap))
++ return PTR_ERR(priv->regmap);
++
+ return dsa_register_switch(priv->ds);
+ }
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -785,6 +785,7 @@ struct mt753x_info {
+ * @dev: The device pointer
+ * @ds: The pointer to the dsa core structure
+ * @bus: The bus used for the device and built-in PHY
++ * @regmap: The regmap instance representing all switch registers
+ * @rstc: The pointer to reset control used by MCM
+ * @core_pwr: The power supplied into the core
+ * @io_pwr: The power supplied into the I/O
+@@ -805,6 +806,7 @@ struct mt7530_priv {
+ struct device *dev;
+ struct dsa_switch *ds;
+ struct mii_bus *bus;
++ struct regmap *regmap;
+ struct reset_control *rstc;
+ struct regulator *core_pwr;
+ struct regulator *io_pwr;
--- /dev/null
+From 6b64b5bc3045a7e1ee5278df4f4ff315cd43d88a Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:18:04 +0100
+Subject: [PATCH 07/48] net: dsa: mt7530: move SGMII PCS creation to
+ mt7530_probe function
+
+Move creating the SGMII PCS from mt753x_setup() to the more appropriate
+mt7530_probe() function.
+This is done also in preparation of moving all functions related to
+MDIO-connected MT753x switches to a separate module.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 13 +++++++------
+ 1 file changed, 7 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3270,12 +3270,6 @@ mt753x_setup(struct dsa_switch *ds)
+ if (ret && priv->irq)
+ mt7530_free_irq_common(priv);
+
+- if (priv->id == ID_MT7531) {
+- ret = mt7531_create_sgmii(priv);
+- if (ret && priv->irq)
+- mt7530_free_irq_common(priv);
+- }
+-
+ return ret;
+ }
+
+@@ -3393,6 +3387,7 @@ mt7530_probe(struct mdio_device *mdiodev
+ static struct regmap_config *regmap_config;
+ struct mt7530_priv *priv;
+ struct device_node *dn;
++ int ret;
+
+ dn = mdiodev->dev.of_node;
+
+@@ -3485,6 +3480,12 @@ mt7530_probe(struct mdio_device *mdiodev
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
++ if (priv->id == ID_MT7531) {
++ ret = mt7531_create_sgmii(priv);
++ if (ret)
++ return ret;
++ }
++
+ return dsa_register_switch(priv->ds);
+ }
+
--- /dev/null
+From 504d39cbda402df3e6fd123d040520393b6a6297 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:18:16 +0100
+Subject: [PATCH 08/48] net: dsa: mt7530: introduce mutex helpers
+
+As the MDIO bus lock only needs to be involved if actually operating
+on an MDIO-connected switch we will need to skip locking for built-in
+switches which are accessed via MMIO.
+Create helper functions which simplify that upcoming change.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 73 ++++++++++++++++++++--------------------
+ 1 file changed, 36 insertions(+), 37 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -143,31 +143,40 @@ err:
+ }
+
+ static void
+-core_write(struct mt7530_priv *priv, u32 reg, u32 val)
++mt7530_mutex_lock(struct mt7530_priv *priv)
+ {
+- struct mii_bus *bus = priv->bus;
++ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++}
+
+- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++static void
++mt7530_mutex_unlock(struct mt7530_priv *priv)
++{
++ mutex_unlock(&priv->bus->mdio_lock);
++}
++
++static void
++core_write(struct mt7530_priv *priv, u32 reg, u32 val)
++{
++ mt7530_mutex_lock(priv);
+
+ core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
+
+- mutex_unlock(&bus->mdio_lock);
++ mt7530_mutex_unlock(priv);
+ }
+
+ static void
+ core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
+ {
+- struct mii_bus *bus = priv->bus;
+ u32 val;
+
+- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++ mt7530_mutex_lock(priv);
+
+ val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
+ val &= ~mask;
+ val |= set;
+ core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
+
+- mutex_unlock(&bus->mdio_lock);
++ mt7530_mutex_unlock(priv);
+ }
+
+ static void
+@@ -264,13 +273,11 @@ mt7530_mii_read(struct mt7530_priv *priv
+ static void
+ mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
+ {
+- struct mii_bus *bus = priv->bus;
+-
+- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++ mt7530_mutex_lock(priv);
+
+ mt7530_mii_write(priv, reg, val);
+
+- mutex_unlock(&bus->mdio_lock);
++ mt7530_mutex_unlock(priv);
+ }
+
+ static u32
+@@ -282,14 +289,13 @@ _mt7530_unlocked_read(struct mt7530_dumm
+ static u32
+ _mt7530_read(struct mt7530_dummy_poll *p)
+ {
+- struct mii_bus *bus = p->priv->bus;
+ u32 val;
+
+- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++ mt7530_mutex_lock(p->priv);
+
+ val = mt7530_mii_read(p->priv, p->reg);
+
+- mutex_unlock(&bus->mdio_lock);
++ mt7530_mutex_unlock(p->priv);
+
+ return val;
+ }
+@@ -307,13 +313,11 @@ static void
+ mt7530_rmw(struct mt7530_priv *priv, u32 reg,
+ u32 mask, u32 set)
+ {
+- struct mii_bus *bus = priv->bus;
+-
+- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++ mt7530_mutex_lock(priv);
+
+ regmap_update_bits(priv->regmap, reg, mask, set);
+
+- mutex_unlock(&bus->mdio_lock);
++ mt7530_mutex_unlock(priv);
+ }
+
+ static void
+@@ -659,14 +663,13 @@ static int
+ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
+ int regnum)
+ {
+- struct mii_bus *bus = priv->bus;
+ struct mt7530_dummy_poll p;
+ u32 reg, val;
+ int ret;
+
+ INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
+
+- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++ mt7530_mutex_lock(priv);
+
+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ !(val & MT7531_PHY_ACS_ST), 20, 100000);
+@@ -699,7 +702,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr
+
+ ret = val & MT7531_MDIO_RW_DATA_MASK;
+ out:
+- mutex_unlock(&bus->mdio_lock);
++ mt7530_mutex_unlock(priv);
+
+ return ret;
+ }
+@@ -708,14 +711,13 @@ static int
+ mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
+ int regnum, u32 data)
+ {
+- struct mii_bus *bus = priv->bus;
+ struct mt7530_dummy_poll p;
+ u32 val, reg;
+ int ret;
+
+ INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
+
+- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++ mt7530_mutex_lock(priv);
+
+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ !(val & MT7531_PHY_ACS_ST), 20, 100000);
+@@ -747,7 +749,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p
+ }
+
+ out:
+- mutex_unlock(&bus->mdio_lock);
++ mt7530_mutex_unlock(priv);
+
+ return ret;
+ }
+@@ -755,14 +757,13 @@ out:
+ static int
+ mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
+ {
+- struct mii_bus *bus = priv->bus;
+ struct mt7530_dummy_poll p;
+ int ret;
+ u32 val;
+
+ INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
+
+- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++ mt7530_mutex_lock(priv);
+
+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
+ !(val & MT7531_PHY_ACS_ST), 20, 100000);
+@@ -785,7 +786,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr
+
+ ret = val & MT7531_MDIO_RW_DATA_MASK;
+ out:
+- mutex_unlock(&bus->mdio_lock);
++ mt7530_mutex_unlock(priv);
+
+ return ret;
+ }
+@@ -794,14 +795,13 @@ static int
+ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
+ u16 data)
+ {
+- struct mii_bus *bus = priv->bus;
+ struct mt7530_dummy_poll p;
+ int ret;
+ u32 reg;
+
+ INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
+
+- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++ mt7530_mutex_lock(priv);
+
+ ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
+ !(reg & MT7531_PHY_ACS_ST), 20, 100000);
+@@ -823,7 +823,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p
+ }
+
+ out:
+- mutex_unlock(&bus->mdio_lock);
++ mt7530_mutex_unlock(priv);
+
+ return ret;
+ }
+@@ -1343,7 +1343,6 @@ static int
+ mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- struct mii_bus *bus = priv->bus;
+ int length;
+ u32 val;
+
+@@ -1354,7 +1353,7 @@ mt7530_port_change_mtu(struct dsa_switch
+ if (!dsa_is_cpu_port(ds, port))
+ return 0;
+
+- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
++ mt7530_mutex_lock(priv);
+
+ val = mt7530_mii_read(priv, MT7530_GMACCR);
+ val &= ~MAX_RX_PKT_LEN_MASK;
+@@ -1375,7 +1374,7 @@ mt7530_port_change_mtu(struct dsa_switch
+
+ mt7530_mii_write(priv, MT7530_GMACCR, val);
+
+- mutex_unlock(&bus->mdio_lock);
++ mt7530_mutex_unlock(priv);
+
+ return 0;
+ }
+@@ -2176,10 +2175,10 @@ mt7530_irq_thread_fn(int irq, void *dev_
+ u32 val;
+ int p;
+
+- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++ mt7530_mutex_lock(priv);
+ val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
+ mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
+- mutex_unlock(&priv->bus->mdio_lock);
++ mt7530_mutex_unlock(priv);
+
+ for (p = 0; p < MT7530_NUM_PHYS; p++) {
+ if (BIT(p) & val) {
+@@ -2215,7 +2214,7 @@ mt7530_irq_bus_lock(struct irq_data *d)
+ {
+ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
+
+- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++ mt7530_mutex_lock(priv);
+ }
+
+ static void
+@@ -2224,7 +2223,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da
+ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
+
+ mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
+- mutex_unlock(&priv->bus->mdio_lock);
++ mt7530_mutex_unlock(priv);
+ }
+
+ static struct irq_chip mt7530_irq_chip = {
--- /dev/null
+From dbef24b66807eef7498740fa8b8441bee64a96c4 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:18:28 +0100
+Subject: [PATCH 09/48] net: dsa: mt7530: move p5_intf_modes() function to
+ mt7530.c
+
+In preparation of splitting mt7530.c into a driver for MDIO-connected
+as well as MDIO-accessed built-in switches on one hand and MMIO-accessed
+built-in switches move the p5_inft_modes() function from mt7530.h to
+mt7530.c. The function is only needed there and will trigger a compiler
+warning about a defined but unused function otherwise when including
+mt7530.h in the to-be-introduced bus-specific drivers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 18 ++++++++++++++++++
+ drivers/net/dsa/mt7530.h | 18 ------------------
+ 2 files changed, 18 insertions(+), 18 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -964,6 +964,24 @@ mt7530_set_ageing_time(struct dsa_switch
+ return 0;
+ }
+
++static const char *p5_intf_modes(unsigned int p5_interface)
++{
++ switch (p5_interface) {
++ case P5_DISABLED:
++ return "DISABLED";
++ case P5_INTF_SEL_PHY_P0:
++ return "PHY P0";
++ case P5_INTF_SEL_PHY_P4:
++ return "PHY P4";
++ case P5_INTF_SEL_GMAC5:
++ return "GMAC5";
++ case P5_INTF_SEL_GMAC5_SGMII:
++ return "GMAC5_SGMII";
++ default:
++ return "unknown";
++ }
++}
++
+ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
+ {
+ struct mt7530_priv *priv = ds->priv;
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -720,24 +720,6 @@ enum p5_interface_select {
+ P5_INTF_SEL_GMAC5_SGMII,
+ };
+
+-static const char *p5_intf_modes(unsigned int p5_interface)
+-{
+- switch (p5_interface) {
+- case P5_DISABLED:
+- return "DISABLED";
+- case P5_INTF_SEL_PHY_P0:
+- return "PHY P0";
+- case P5_INTF_SEL_PHY_P4:
+- return "PHY P4";
+- case P5_INTF_SEL_GMAC5:
+- return "GMAC5";
+- case P5_INTF_SEL_GMAC5_SGMII:
+- return "GMAC5_SGMII";
+- default:
+- return "unknown";
+- }
+-}
+-
+ struct mt7530_priv;
+
+ struct mt753x_pcs {
--- /dev/null
+From a0c6527a38d518ff175c1b6ce248e9b06cc98d3b Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:18:39 +0100
+Subject: [PATCH 10/48] net: dsa: mt7530: introduce mt7530_probe_common helper
+ function
+
+Move commonly used parts from mt7530_probe into new mt7530_probe_common
+helper function which will be used by both, mt7530_probe and the
+to-be-introduced mt7988_probe.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 98 ++++++++++++++++++++++------------------
+ 1 file changed, 54 insertions(+), 44 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3399,44 +3399,21 @@ static const struct of_device_id mt7530_
+ MODULE_DEVICE_TABLE(of, mt7530_of_match);
+
+ static int
+-mt7530_probe(struct mdio_device *mdiodev)
++mt7530_probe_common(struct mt7530_priv *priv)
+ {
+- static struct regmap_config *regmap_config;
+- struct mt7530_priv *priv;
+- struct device_node *dn;
+- int ret;
++ struct device *dev = priv->dev;
+
+- dn = mdiodev->dev.of_node;
+-
+- priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
+- if (!priv)
+- return -ENOMEM;
+-
+- priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
++ priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
+ if (!priv->ds)
+ return -ENOMEM;
+
+- priv->ds->dev = &mdiodev->dev;
++ priv->ds->dev = dev;
+ priv->ds->num_ports = MT7530_NUM_PORTS;
+
+- /* Use medatek,mcm property to distinguish hardware type that would
+- * casues a little bit differences on power-on sequence.
+- */
+- priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
+- if (priv->mcm) {
+- dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
+-
+- priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
+- if (IS_ERR(priv->rstc)) {
+- dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
+- return PTR_ERR(priv->rstc);
+- }
+- }
+-
+ /* Get the hardware identifier from the devicetree node.
+ * We will need it for some of the clock and regulator setup.
+ */
+- priv->info = of_device_get_match_data(&mdiodev->dev);
++ priv->info = of_device_get_match_data(dev);
+ if (!priv->info)
+ return -EINVAL;
+
+@@ -3450,23 +3427,53 @@ mt7530_probe(struct mdio_device *mdiodev
+ return -EINVAL;
+
+ priv->id = priv->info->id;
++ priv->dev = dev;
++ priv->ds->priv = priv;
++ priv->ds->ops = &mt7530_switch_ops;
++ mutex_init(&priv->reg_mutex);
++ dev_set_drvdata(dev, priv);
+
+- if (priv->id == ID_MT7530) {
+- priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
+- if (IS_ERR(priv->core_pwr))
+- return PTR_ERR(priv->core_pwr);
++ return 0;
++}
+
+- priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
+- if (IS_ERR(priv->io_pwr))
+- return PTR_ERR(priv->io_pwr);
+- }
++static int
++mt7530_probe(struct mdio_device *mdiodev)
++{
++ static struct regmap_config *regmap_config;
++ struct mt7530_priv *priv;
++ struct device_node *dn;
++ int ret;
++
++ dn = mdiodev->dev.of_node;
++
++ priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
+
+- /* Not MCM that indicates switch works as the remote standalone
++ priv->bus = mdiodev->bus;
++ priv->dev = &mdiodev->dev;
++
++ ret = mt7530_probe_common(priv);
++ if (ret)
++ return ret;
++
++ /* Use medatek,mcm property to distinguish hardware type that would
++ * cause a little bit differences on power-on sequence.
++ * Not MCM that indicates switch works as the remote standalone
+ * integrated circuit so the GPIO pin would be used to complete
+ * the reset, otherwise memory-mapped register accessing used
+ * through syscon provides in the case of MCM.
+ */
+- if (!priv->mcm) {
++ priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
++ if (priv->mcm) {
++ dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
++
++ priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
++ if (IS_ERR(priv->rstc)) {
++ dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
++ return PTR_ERR(priv->rstc);
++ }
++ } else {
+ priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(priv->reset)) {
+@@ -3475,12 +3482,15 @@ mt7530_probe(struct mdio_device *mdiodev
+ }
+ }
+
+- priv->bus = mdiodev->bus;
+- priv->dev = &mdiodev->dev;
+- priv->ds->priv = priv;
+- priv->ds->ops = &mt7530_switch_ops;
+- mutex_init(&priv->reg_mutex);
+- dev_set_drvdata(&mdiodev->dev, priv);
++ if (priv->id == ID_MT7530) {
++ priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
++ if (IS_ERR(priv->core_pwr))
++ return PTR_ERR(priv->core_pwr);
++
++ priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
++ if (IS_ERR(priv->io_pwr))
++ return PTR_ERR(priv->io_pwr);
++ }
+
+ regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
+ GFP_KERNEL);
--- /dev/null
+From a7783b0b6f3b38abd34cecf515811691714dee57 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:18:50 +0100
+Subject: [PATCH 11/48] net: dsa: mt7530: introduce mt7530_remove_common helper
+ function
+
+Move commonly used parts from mt7530_remove into new
+mt7530_remove_common helper function which will be used by both,
+mt7530_remove and the to-be-introduced mt7988_remove.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 18 ++++++++++++------
+ 1 file changed, 12 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3517,6 +3517,17 @@ mt7530_probe(struct mdio_device *mdiodev
+ }
+
+ static void
++mt7530_remove_common(struct mt7530_priv *priv)
++{
++ if (priv->irq)
++ mt7530_free_irq(priv);
++
++ dsa_unregister_switch(priv->ds);
++
++ mutex_destroy(&priv->reg_mutex);
++}
++
++static void
+ mt7530_remove(struct mdio_device *mdiodev)
+ {
+ struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
+@@ -3535,15 +3546,10 @@ mt7530_remove(struct mdio_device *mdiode
+ dev_err(priv->dev, "Failed to disable io pwr: %d\n",
+ ret);
+
+- if (priv->irq)
+- mt7530_free_irq(priv);
+-
+- dsa_unregister_switch(priv->ds);
++ mt7530_remove_common(priv);
+
+ for (i = 0; i < 2; ++i)
+ mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
+-
+- mutex_destroy(&priv->reg_mutex);
+ }
+
+ static void mt7530_shutdown(struct mdio_device *mdiodev)
--- /dev/null
+From 5313432ca1e1a0677ad7b4f17a7e0186473f47aa Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:19:13 +0100
+Subject: [PATCH 12/48] net: dsa: mt7530: introduce separate MDIO driver
+
+Split MT7530 switch driver into a common part and a part specific
+for MDIO connected switches and multi-chip modules.
+Move MDIO-specific functions to newly introduced mt7530-mdio.c while
+keeping the common parts in mt7530.c.
+Introduce new Kconfig symbol CONFIG_NET_DSA_MT7530_MDIO which is
+implied by CONFIG_NET_DSA_MT7530.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ MAINTAINERS | 1 +
+ drivers/net/dsa/Kconfig | 18 ++-
+ drivers/net/dsa/Makefile | 1 +
+ drivers/net/dsa/mt7530-mdio.c | 271 ++++++++++++++++++++++++++++++++++
+ drivers/net/dsa/mt7530.c | 264 +--------------------------------
+ drivers/net/dsa/mt7530.h | 6 +
+ 6 files changed, 302 insertions(+), 259 deletions(-)
+ create mode 100644 drivers/net/dsa/mt7530-mdio.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -13069,6 +13069,7 @@ M: Landen Chao <Landen.Chao@mediatek.com
+ M: DENG Qingfang <dqfext@gmail.com>
+ L: netdev@vger.kernel.org
+ S: Maintained
++F: drivers/net/dsa/mt7530-mdio.c
+ F: drivers/net/dsa/mt7530.*
+ F: net/dsa/tag_mtk.c
+
+--- a/drivers/net/dsa/Kconfig
++++ b/drivers/net/dsa/Kconfig
+@@ -34,13 +34,25 @@ config NET_DSA_LANTIQ_GSWIP
+ the xrx200 / VR9 SoC.
+
+ config NET_DSA_MT7530
+- tristate "MediaTek MT753x and MT7621 Ethernet switch support"
++ tristate "MediaTek MT7530 and MT7531 Ethernet switch support"
+ select NET_DSA_TAG_MTK
++ imply NET_DSA_MT7530_MDIO
++ help
++ This enables support for the MediaTek MT7530 and MT7531 Ethernet
++ switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
++ MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
++ supported as well.
++
++config NET_DSA_MT7530_MDIO
++ tristate "MediaTek MT7530 MDIO interface driver"
++ depends on NET_DSA_MT7530
+ select MEDIATEK_GE_PHY
+ select PCS_MTK_LYNXI
+ help
+- This enables support for the MediaTek MT7530, MT7531, and MT7621
+- Ethernet switch chips.
++ This enables support for the MediaTek MT7530 and MT7531 switch
++ chips which are connected via MDIO, as well as multi-chip
++ module MT7530 which can be found in the MT7621AT, MT7621DAT,
++ MT7621ST and MT7623AI SoCs.
+
+ config NET_DSA_MV88E6060
+ tristate "Marvell 88E6060 ethernet switch chip support"
+--- a/drivers/net/dsa/Makefile
++++ b/drivers/net/dsa/Makefile
+@@ -7,6 +7,7 @@ obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdi
+ endif
+ obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
+ obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
++obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
+ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
+ obj-$(CONFIG_NET_DSA_RZN1_A5PSW) += rzn1_a5psw.o
+ obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
+--- /dev/null
++++ b/drivers/net/dsa/mt7530-mdio.c
+@@ -0,0 +1,271 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include <linux/gpio/consumer.h>
++#include <linux/mdio.h>
++#include <linux/module.h>
++#include <linux/pcs/pcs-mtk-lynxi.h>
++#include <linux/of_irq.h>
++#include <linux/of_mdio.h>
++#include <linux/of_net.h>
++#include <linux/of_platform.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/regulator/consumer.h>
++#include <net/dsa.h>
++
++#include "mt7530.h"
++
++static int
++mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
++{
++ struct mii_bus *bus = context;
++ u16 page, r, lo, hi;
++ int ret;
++
++ page = (reg >> 6) & 0x3ff;
++ r = (reg >> 2) & 0xf;
++ lo = val & 0xffff;
++ hi = val >> 16;
++
++ /* MT7530 uses 31 as the pseudo port */
++ ret = bus->write(bus, 0x1f, 0x1f, page);
++ if (ret < 0)
++ return ret;
++
++ ret = bus->write(bus, 0x1f, r, lo);
++ if (ret < 0)
++ return ret;
++
++ ret = bus->write(bus, 0x1f, 0x10, hi);
++ return ret;
++}
++
++static int
++mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
++{
++ struct mii_bus *bus = context;
++ u16 page, r, lo, hi;
++ int ret;
++
++ page = (reg >> 6) & 0x3ff;
++ r = (reg >> 2) & 0xf;
++
++ /* MT7530 uses 31 as the pseudo port */
++ ret = bus->write(bus, 0x1f, 0x1f, page);
++ if (ret < 0)
++ return ret;
++
++ lo = bus->read(bus, 0x1f, r);
++ hi = bus->read(bus, 0x1f, 0x10);
++
++ *val = (hi << 16) | (lo & 0xffff);
++
++ return 0;
++}
++
++static void
++mt7530_mdio_regmap_lock(void *mdio_lock)
++{
++ mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
++}
++
++static void
++mt7530_mdio_regmap_unlock(void *mdio_lock)
++{
++ mutex_unlock(mdio_lock);
++}
++
++static const struct regmap_bus mt7530_regmap_bus = {
++ .reg_write = mt7530_regmap_write,
++ .reg_read = mt7530_regmap_read,
++};
++
++static int
++mt7531_create_sgmii(struct mt7530_priv *priv)
++{
++ struct regmap_config *mt7531_pcs_config[2];
++ struct phylink_pcs *pcs;
++ struct regmap *regmap;
++ int i, ret = 0;
++
++ for (i = 0; i < 2; i++) {
++ mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
++ sizeof(struct regmap_config),
++ GFP_KERNEL);
++ if (!mt7531_pcs_config[i]) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ mt7531_pcs_config[i]->name = i ? "port6" : "port5";
++ mt7531_pcs_config[i]->reg_bits = 16;
++ mt7531_pcs_config[i]->val_bits = 32;
++ mt7531_pcs_config[i]->reg_stride = 4;
++ mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
++ mt7531_pcs_config[i]->max_register = 0x17c;
++ mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock;
++ mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
++ mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
++
++ regmap = devm_regmap_init(priv->dev,
++ &mt7530_regmap_bus, priv->bus,
++ mt7531_pcs_config[i]);
++ if (IS_ERR(regmap)) {
++ ret = PTR_ERR(regmap);
++ break;
++ }
++ pcs = mtk_pcs_lynxi_create(priv->dev, regmap,
++ MT7531_PHYA_CTRL_SIGNAL3, 0);
++ if (!pcs) {
++ ret = -ENXIO;
++ break;
++ }
++ priv->ports[5 + i].sgmii_pcs = pcs;
++ }
++
++ if (ret && i)
++ mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs);
++
++ return ret;
++}
++
++static const struct of_device_id mt7530_of_match[] = {
++ { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
++ { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
++ { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
++ { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mt7530_of_match);
++
++static int
++mt7530_probe(struct mdio_device *mdiodev)
++{
++ static struct regmap_config *regmap_config;
++ struct mt7530_priv *priv;
++ struct device_node *dn;
++ int ret;
++
++ dn = mdiodev->dev.of_node;
++
++ priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ priv->bus = mdiodev->bus;
++ priv->dev = &mdiodev->dev;
++
++ ret = mt7530_probe_common(priv);
++ if (ret)
++ return ret;
++
++ /* Use medatek,mcm property to distinguish hardware type that would
++ * cause a little bit differences on power-on sequence.
++ * Not MCM that indicates switch works as the remote standalone
++ * integrated circuit so the GPIO pin would be used to complete
++ * the reset, otherwise memory-mapped register accessing used
++ * through syscon provides in the case of MCM.
++ */
++ priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
++ if (priv->mcm) {
++ dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
++
++ priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
++ if (IS_ERR(priv->rstc)) {
++ dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
++ return PTR_ERR(priv->rstc);
++ }
++ } else {
++ priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
++ GPIOD_OUT_LOW);
++ if (IS_ERR(priv->reset)) {
++ dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
++ return PTR_ERR(priv->reset);
++ }
++ }
++
++ if (priv->id == ID_MT7530) {
++ priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
++ if (IS_ERR(priv->core_pwr))
++ return PTR_ERR(priv->core_pwr);
++
++ priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
++ if (IS_ERR(priv->io_pwr))
++ return PTR_ERR(priv->io_pwr);
++ }
++
++ regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
++ GFP_KERNEL);
++ if (!regmap_config)
++ return -ENOMEM;
++
++ regmap_config->reg_bits = 16;
++ regmap_config->val_bits = 32;
++ regmap_config->reg_stride = 4;
++ regmap_config->max_register = MT7530_CREV;
++ regmap_config->disable_locking = true;
++ priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
++ priv->bus, regmap_config);
++ if (IS_ERR(priv->regmap))
++ return PTR_ERR(priv->regmap);
++
++ if (priv->id == ID_MT7531) {
++ ret = mt7531_create_sgmii(priv);
++ if (ret)
++ return ret;
++ }
++
++ return dsa_register_switch(priv->ds);
++}
++
++static void
++mt7530_remove(struct mdio_device *mdiodev)
++{
++ struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
++ int ret = 0, i;
++
++ if (!priv)
++ return;
++
++ ret = regulator_disable(priv->core_pwr);
++ if (ret < 0)
++ dev_err(priv->dev,
++ "Failed to disable core power: %d\n", ret);
++
++ ret = regulator_disable(priv->io_pwr);
++ if (ret < 0)
++ dev_err(priv->dev, "Failed to disable io pwr: %d\n",
++ ret);
++
++ mt7530_remove_common(priv);
++
++ for (i = 0; i < 2; ++i)
++ mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
++}
++
++static void mt7530_shutdown(struct mdio_device *mdiodev)
++{
++ struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
++
++ if (!priv)
++ return;
++
++ dsa_switch_shutdown(priv->ds);
++
++ dev_set_drvdata(&mdiodev->dev, NULL);
++}
++
++static struct mdio_driver mt7530_mdio_driver = {
++ .probe = mt7530_probe,
++ .remove = mt7530_remove,
++ .shutdown = mt7530_shutdown,
++ .mdiodrv.driver = {
++ .name = "mt7530-mdio",
++ .of_match_table = mt7530_of_match,
++ },
++};
++
++mdio_module_driver(mt7530_mdio_driver);
++
++MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
++MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch (MDIO)");
++MODULE_LICENSE("GPL");
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -14,7 +14,6 @@
+ #include <linux/of_mdio.h>
+ #include <linux/of_net.h>
+ #include <linux/of_platform.h>
+-#include <linux/pcs/pcs-mtk-lynxi.h>
+ #include <linux/phylink.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
+@@ -192,31 +191,6 @@ core_clear(struct mt7530_priv *priv, u32
+ }
+
+ static int
+-mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
+-{
+- struct mii_bus *bus = context;
+- u16 page, r, lo, hi;
+- int ret;
+-
+- page = (reg >> 6) & 0x3ff;
+- r = (reg >> 2) & 0xf;
+- lo = val & 0xffff;
+- hi = val >> 16;
+-
+- /* MT7530 uses 31 as the pseudo port */
+- ret = bus->write(bus, 0x1f, 0x1f, page);
+- if (ret < 0)
+- return ret;
+-
+- ret = bus->write(bus, 0x1f, r, lo);
+- if (ret < 0)
+- return ret;
+-
+- ret = bus->write(bus, 0x1f, 0x10, hi);
+- return ret;
+-}
+-
+-static int
+ mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
+ {
+ int ret;
+@@ -230,29 +204,6 @@ mt7530_mii_write(struct mt7530_priv *pri
+ return ret;
+ }
+
+-static int
+-mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
+-{
+- struct mii_bus *bus = context;
+- u16 page, r, lo, hi;
+- int ret;
+-
+- page = (reg >> 6) & 0x3ff;
+- r = (reg >> 2) & 0xf;
+-
+- /* MT7530 uses 31 as the pseudo port */
+- ret = bus->write(bus, 0x1f, 0x1f, page);
+- if (ret < 0)
+- return ret;
+-
+- lo = bus->read(bus, 0x1f, r);
+- hi = bus->read(bus, 0x1f, 0x10);
+-
+- *val = (hi << 16) | (lo & 0xffff);
+-
+- return 0;
+-}
+-
+ static u32
+ mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
+ {
+@@ -3196,72 +3147,6 @@ static const struct phylink_pcs_ops mt75
+ .pcs_an_restart = mt7530_pcs_an_restart,
+ };
+
+-static void
+-mt7530_mdio_regmap_lock(void *mdio_lock)
+-{
+- mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
+-}
+-
+-static void
+-mt7530_mdio_regmap_unlock(void *mdio_lock)
+-{
+- mutex_unlock(mdio_lock);
+-}
+-
+-static const struct regmap_bus mt7530_regmap_bus = {
+- .reg_write = mt7530_regmap_write,
+- .reg_read = mt7530_regmap_read,
+-};
+-
+-static int
+-mt7531_create_sgmii(struct mt7530_priv *priv)
+-{
+- struct regmap_config *mt7531_pcs_config[2];
+- struct phylink_pcs *pcs;
+- struct regmap *regmap;
+- int i, ret = 0;
+-
+- for (i = 0; i < 2; i++) {
+- mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
+- sizeof(struct regmap_config),
+- GFP_KERNEL);
+- if (!mt7531_pcs_config[i]) {
+- ret = -ENOMEM;
+- break;
+- }
+-
+- mt7531_pcs_config[i]->name = i ? "port6" : "port5";
+- mt7531_pcs_config[i]->reg_bits = 16;
+- mt7531_pcs_config[i]->val_bits = 32;
+- mt7531_pcs_config[i]->reg_stride = 4;
+- mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
+- mt7531_pcs_config[i]->max_register = 0x17c;
+- mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock;
+- mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
+- mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
+-
+- regmap = devm_regmap_init(priv->dev,
+- &mt7530_regmap_bus, priv->bus,
+- mt7531_pcs_config[i]);
+- if (IS_ERR(regmap)) {
+- ret = PTR_ERR(regmap);
+- break;
+- }
+- pcs = mtk_pcs_lynxi_create(priv->dev, regmap,
+- MT7531_PHYA_CTRL_SIGNAL3, 0);
+- if (!pcs) {
+- ret = -ENXIO;
+- break;
+- }
+- priv->ports[5 + i].sgmii_pcs = pcs;
+- }
+-
+- if (ret && i)
+- mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs);
+-
+- return ret;
+-}
+-
+ static int
+ mt753x_setup(struct dsa_switch *ds)
+ {
+@@ -3320,7 +3205,7 @@ static int mt753x_set_mac_eee(struct dsa
+ return 0;
+ }
+
+-static const struct dsa_switch_ops mt7530_switch_ops = {
++const struct dsa_switch_ops mt7530_switch_ops = {
+ .get_tag_protocol = mtk_get_tag_protocol,
+ .setup = mt753x_setup,
+ .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port,
+@@ -3355,8 +3240,9 @@ static const struct dsa_switch_ops mt753
+ .get_mac_eee = mt753x_get_mac_eee,
+ .set_mac_eee = mt753x_set_mac_eee,
+ };
++EXPORT_SYMBOL_GPL(mt7530_switch_ops);
+
+-static const struct mt753x_info mt753x_table[] = {
++const struct mt753x_info mt753x_table[] = {
+ [ID_MT7621] = {
+ .id = ID_MT7621,
+ .pcs_ops = &mt7530_pcs_ops,
+@@ -3389,16 +3275,9 @@ static const struct mt753x_info mt753x_t
+ .mac_port_config = mt7531_mac_config,
+ },
+ };
++EXPORT_SYMBOL_GPL(mt753x_table);
+
+-static const struct of_device_id mt7530_of_match[] = {
+- { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
+- { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
+- { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
+- { /* sentinel */ },
+-};
+-MODULE_DEVICE_TABLE(of, mt7530_of_match);
+-
+-static int
++int
+ mt7530_probe_common(struct mt7530_priv *priv)
+ {
+ struct device *dev = priv->dev;
+@@ -3435,88 +3314,9 @@ mt7530_probe_common(struct mt7530_priv *
+
+ return 0;
+ }
++EXPORT_SYMBOL_GPL(mt7530_probe_common);
+
+-static int
+-mt7530_probe(struct mdio_device *mdiodev)
+-{
+- static struct regmap_config *regmap_config;
+- struct mt7530_priv *priv;
+- struct device_node *dn;
+- int ret;
+-
+- dn = mdiodev->dev.of_node;
+-
+- priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
+- if (!priv)
+- return -ENOMEM;
+-
+- priv->bus = mdiodev->bus;
+- priv->dev = &mdiodev->dev;
+-
+- ret = mt7530_probe_common(priv);
+- if (ret)
+- return ret;
+-
+- /* Use medatek,mcm property to distinguish hardware type that would
+- * cause a little bit differences on power-on sequence.
+- * Not MCM that indicates switch works as the remote standalone
+- * integrated circuit so the GPIO pin would be used to complete
+- * the reset, otherwise memory-mapped register accessing used
+- * through syscon provides in the case of MCM.
+- */
+- priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
+- if (priv->mcm) {
+- dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
+-
+- priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
+- if (IS_ERR(priv->rstc)) {
+- dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
+- return PTR_ERR(priv->rstc);
+- }
+- } else {
+- priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
+- GPIOD_OUT_LOW);
+- if (IS_ERR(priv->reset)) {
+- dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
+- return PTR_ERR(priv->reset);
+- }
+- }
+-
+- if (priv->id == ID_MT7530) {
+- priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
+- if (IS_ERR(priv->core_pwr))
+- return PTR_ERR(priv->core_pwr);
+-
+- priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
+- if (IS_ERR(priv->io_pwr))
+- return PTR_ERR(priv->io_pwr);
+- }
+-
+- regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
+- GFP_KERNEL);
+- if (!regmap_config)
+- return -ENOMEM;
+-
+- regmap_config->reg_bits = 16;
+- regmap_config->val_bits = 32;
+- regmap_config->reg_stride = 4;
+- regmap_config->max_register = MT7530_CREV;
+- regmap_config->disable_locking = true;
+- priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
+- priv->bus, regmap_config);
+- if (IS_ERR(priv->regmap))
+- return PTR_ERR(priv->regmap);
+-
+- if (priv->id == ID_MT7531) {
+- ret = mt7531_create_sgmii(priv);
+- if (ret)
+- return ret;
+- }
+-
+- return dsa_register_switch(priv->ds);
+-}
+-
+-static void
++void
+ mt7530_remove_common(struct mt7530_priv *priv)
+ {
+ if (priv->irq)
+@@ -3526,55 +3326,7 @@ mt7530_remove_common(struct mt7530_priv
+
+ mutex_destroy(&priv->reg_mutex);
+ }
+-
+-static void
+-mt7530_remove(struct mdio_device *mdiodev)
+-{
+- struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
+- int ret = 0, i;
+-
+- if (!priv)
+- return;
+-
+- ret = regulator_disable(priv->core_pwr);
+- if (ret < 0)
+- dev_err(priv->dev,
+- "Failed to disable core power: %d\n", ret);
+-
+- ret = regulator_disable(priv->io_pwr);
+- if (ret < 0)
+- dev_err(priv->dev, "Failed to disable io pwr: %d\n",
+- ret);
+-
+- mt7530_remove_common(priv);
+-
+- for (i = 0; i < 2; ++i)
+- mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
+-}
+-
+-static void mt7530_shutdown(struct mdio_device *mdiodev)
+-{
+- struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
+-
+- if (!priv)
+- return;
+-
+- dsa_switch_shutdown(priv->ds);
+-
+- dev_set_drvdata(&mdiodev->dev, NULL);
+-}
+-
+-static struct mdio_driver mt7530_mdio_driver = {
+- .probe = mt7530_probe,
+- .remove = mt7530_remove,
+- .shutdown = mt7530_shutdown,
+- .mdiodrv.driver = {
+- .name = "mt7530",
+- .of_match_table = mt7530_of_match,
+- },
+-};
+-
+-mdio_module_driver(mt7530_mdio_driver);
++EXPORT_SYMBOL_GPL(mt7530_remove_common);
+
+ MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
+ MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -845,4 +845,10 @@ static inline void INIT_MT7530_DUMMY_POL
+ p->reg = reg;
+ }
+
++int mt7530_probe_common(struct mt7530_priv *priv);
++void mt7530_remove_common(struct mt7530_priv *priv);
++
++extern const struct dsa_switch_ops mt7530_switch_ops;
++extern const struct mt753x_info mt753x_table[];
++
+ #endif /* __MT7530_H */
--- /dev/null
+From 86e1168a214b7ab0883acf1e7a6885a7a949e3e7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:19:28 +0100
+Subject: [PATCH 13/48] net: dsa: mt7530: skip locking if MDIO bus isn't
+ present
+
+As MT7530 and MT7531 internally use 32-bit wide registers, each access
+to any register of the switch requires several operations on the MDIO
+bus. Hence if there is congruent access, e.g. due to PCS or PHY
+polling, this can mess up and interfere with another ongoing register
+access sequence.
+
+However, the MDIO bus mutex is only relevant for MDIO-connected
+switches. Prepare switches which have there registers directly mapped
+into the SoCs register space via MMIO which do not require such
+locking. There we can simply use regmap's default locking mechanism.
+
+Hence guard mutex operations to only be performed in case of MDIO
+connected switches.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -144,13 +144,15 @@ err:
+ static void
+ mt7530_mutex_lock(struct mt7530_priv *priv)
+ {
+- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++ if (priv->bus)
++ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+ }
+
+ static void
+ mt7530_mutex_unlock(struct mt7530_priv *priv)
+ {
+- mutex_unlock(&priv->bus->mdio_lock);
++ if (priv->bus)
++ mutex_unlock(&priv->bus->mdio_lock);
+ }
+
+ static void
--- /dev/null
+From a1b87b6322db9186c8689710fe3e98f59e540949 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 3 Apr 2023 02:19:40 +0100
+Subject: [PATCH 14/48] net: dsa: mt7530: introduce driver for MT7988 built-in
+ switch
+
+Add driver for the built-in Gigabit Ethernet switch which can be found
+in the MediaTek MT7988 SoC.
+
+The switch shares most of its design with MT7530 and MT7531, but has
+it's registers mapped into the SoCs register space rather than being
+connected externally or internally via MDIO.
+
+Introduce a new platform driver to support that.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ MAINTAINERS | 2 +
+ drivers/net/dsa/Kconfig | 12 +++
+ drivers/net/dsa/Makefile | 1 +
+ drivers/net/dsa/mt7530-mmio.c | 101 +++++++++++++++++++++++++
+ drivers/net/dsa/mt7530.c | 135 +++++++++++++++++++++++++++++++++-
+ drivers/net/dsa/mt7530.h | 12 +--
+ 6 files changed, 253 insertions(+), 10 deletions(-)
+ create mode 100644 drivers/net/dsa/mt7530-mmio.c
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -13067,9 +13067,11 @@ MEDIATEK SWITCH DRIVER
+ M: Sean Wang <sean.wang@mediatek.com>
+ M: Landen Chao <Landen.Chao@mediatek.com>
+ M: DENG Qingfang <dqfext@gmail.com>
++M: Daniel Golle <daniel@makrotopia.org>
+ L: netdev@vger.kernel.org
+ S: Maintained
+ F: drivers/net/dsa/mt7530-mdio.c
++F: drivers/net/dsa/mt7530-mmio.c
+ F: drivers/net/dsa/mt7530.*
+ F: net/dsa/tag_mtk.c
+
+--- a/drivers/net/dsa/Kconfig
++++ b/drivers/net/dsa/Kconfig
+@@ -37,6 +37,7 @@ config NET_DSA_MT7530
+ tristate "MediaTek MT7530 and MT7531 Ethernet switch support"
+ select NET_DSA_TAG_MTK
+ imply NET_DSA_MT7530_MDIO
++ imply NET_DSA_MT7530_MMIO
+ help
+ This enables support for the MediaTek MT7530 and MT7531 Ethernet
+ switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
+@@ -54,6 +55,17 @@ config NET_DSA_MT7530_MDIO
+ module MT7530 which can be found in the MT7621AT, MT7621DAT,
+ MT7621ST and MT7623AI SoCs.
+
++config NET_DSA_MT7530_MMIO
++ tristate "MediaTek MT7530 MMIO interface driver"
++ depends on NET_DSA_MT7530
++ depends on HAS_IOMEM
++ help
++ This enables support for the built-in Ethernet switch found
++ in the MediaTek MT7988 SoC.
++ The switch is a similar design as MT7531, but the switch registers
++ are directly mapped into the SoCs register space rather than being
++ accessible via MDIO.
++
+ config NET_DSA_MV88E6060
+ tristate "Marvell 88E6060 ethernet switch chip support"
+ select NET_DSA_TAG_TRAILER
+--- a/drivers/net/dsa/Makefile
++++ b/drivers/net/dsa/Makefile
+@@ -8,6 +8,7 @@ endif
+ obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
+ obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
+ obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
++obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o
+ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
+ obj-$(CONFIG_NET_DSA_RZN1_A5PSW) += rzn1_a5psw.o
+ obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
+--- /dev/null
++++ b/drivers/net/dsa/mt7530-mmio.c
+@@ -0,0 +1,101 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <net/dsa.h>
++
++#include "mt7530.h"
++
++static const struct of_device_id mt7988_of_match[] = {
++ { .compatible = "mediatek,mt7988-switch", .data = &mt753x_table[ID_MT7988], },
++ { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mt7988_of_match);
++
++static int
++mt7988_probe(struct platform_device *pdev)
++{
++ static struct regmap_config *sw_regmap_config;
++ struct mt7530_priv *priv;
++ void __iomem *base_addr;
++ int ret;
++
++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ priv->bus = NULL;
++ priv->dev = &pdev->dev;
++
++ ret = mt7530_probe_common(priv);
++ if (ret)
++ return ret;
++
++ priv->rstc = devm_reset_control_get(&pdev->dev, NULL);
++ if (IS_ERR(priv->rstc)) {
++ dev_err(&pdev->dev, "Couldn't get our reset line\n");
++ return PTR_ERR(priv->rstc);
++ }
++
++ base_addr = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(base_addr)) {
++ dev_err(&pdev->dev, "cannot request I/O memory space\n");
++ return -ENXIO;
++ }
++
++ sw_regmap_config = devm_kzalloc(&pdev->dev, sizeof(*sw_regmap_config), GFP_KERNEL);
++ if (!sw_regmap_config)
++ return -ENOMEM;
++
++ sw_regmap_config->name = "switch";
++ sw_regmap_config->reg_bits = 16;
++ sw_regmap_config->val_bits = 32;
++ sw_regmap_config->reg_stride = 4;
++ sw_regmap_config->max_register = MT7530_CREV;
++ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base_addr, sw_regmap_config);
++ if (IS_ERR(priv->regmap))
++ return PTR_ERR(priv->regmap);
++
++ return dsa_register_switch(priv->ds);
++}
++
++static int
++mt7988_remove(struct platform_device *pdev)
++{
++ struct mt7530_priv *priv = platform_get_drvdata(pdev);
++
++ if (priv)
++ mt7530_remove_common(priv);
++
++ return 0;
++}
++
++static void mt7988_shutdown(struct platform_device *pdev)
++{
++ struct mt7530_priv *priv = platform_get_drvdata(pdev);
++
++ if (!priv)
++ return;
++
++ dsa_switch_shutdown(priv->ds);
++
++ dev_set_drvdata(&pdev->dev, NULL);
++}
++
++static struct platform_driver mt7988_platform_driver = {
++ .probe = mt7988_probe,
++ .remove = mt7988_remove,
++ .shutdown = mt7988_shutdown,
++ .driver = {
++ .name = "mt7530-mmio",
++ .of_match_table = mt7988_of_match,
++ },
++};
++module_platform_driver(mt7988_platform_driver);
++
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch (MMIO)");
++MODULE_LICENSE("GPL");
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2223,6 +2223,47 @@ static const struct irq_domain_ops mt753
+ };
+
+ static void
++mt7988_irq_mask(struct irq_data *d)
++{
++ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
++
++ priv->irq_enable &= ~BIT(d->hwirq);
++ mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
++}
++
++static void
++mt7988_irq_unmask(struct irq_data *d)
++{
++ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
++
++ priv->irq_enable |= BIT(d->hwirq);
++ mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
++}
++
++static struct irq_chip mt7988_irq_chip = {
++ .name = KBUILD_MODNAME,
++ .irq_mask = mt7988_irq_mask,
++ .irq_unmask = mt7988_irq_unmask,
++};
++
++static int
++mt7988_irq_map(struct irq_domain *domain, unsigned int irq,
++ irq_hw_number_t hwirq)
++{
++ irq_set_chip_data(irq, domain->host_data);
++ irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq);
++ irq_set_nested_thread(irq, true);
++ irq_set_noprobe(irq);
++
++ return 0;
++}
++
++static const struct irq_domain_ops mt7988_irq_domain_ops = {
++ .map = mt7988_irq_map,
++ .xlate = irq_domain_xlate_onecell,
++};
++
++static void
+ mt7530_setup_mdio_irq(struct mt7530_priv *priv)
+ {
+ struct dsa_switch *ds = priv->ds;
+@@ -2256,8 +2297,15 @@ mt7530_setup_irq(struct mt7530_priv *pri
+ return priv->irq ? : -EINVAL;
+ }
+
+- priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
+- &mt7530_irq_domain_ops, priv);
++ if (priv->id == ID_MT7988)
++ priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
++ &mt7988_irq_domain_ops,
++ priv);
++ else
++ priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
++ &mt7530_irq_domain_ops,
++ priv);
++
+ if (!priv->irq_domain) {
+ dev_err(dev, "failed to create IRQ domain\n");
+ return -ENOMEM;
+@@ -2762,6 +2810,25 @@ static void mt7531_mac_port_get_caps(str
+ }
+ }
+
++static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
++ struct phylink_config *config)
++{
++ phy_interface_zero(config->supported_interfaces);
++
++ switch (port) {
++ case 0 ... 4: /* Internal phy */
++ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
++ config->supported_interfaces);
++ break;
++
++ case 6:
++ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
++ config->supported_interfaces);
++ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
++ MAC_10000FD;
++ }
++}
++
+ static int
+ mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
+ {
+@@ -2838,6 +2905,17 @@ static bool mt753x_is_mac_port(u32 port)
+ }
+
+ static int
++mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
++ phy_interface_t interface)
++{
++ if (dsa_is_cpu_port(ds, port) &&
++ interface == PHY_INTERFACE_MODE_INTERNAL)
++ return 0;
++
++ return -EINVAL;
++}
++
++static int
+ mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ phy_interface_t interface)
+ {
+@@ -2907,7 +2985,8 @@ mt753x_phylink_mac_config(struct dsa_swi
+
+ switch (port) {
+ case 0 ... 4: /* Internal phy */
+- if (state->interface != PHY_INTERFACE_MODE_GMII)
++ if (state->interface != PHY_INTERFACE_MODE_GMII &&
++ state->interface != PHY_INTERFACE_MODE_INTERNAL)
+ goto unsupported;
+ break;
+ case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
+@@ -2985,7 +3064,8 @@ static void mt753x_phylink_mac_link_up(s
+ /* MT753x MAC works in 1G full duplex mode for all up-clocked
+ * variants.
+ */
+- if (interface == PHY_INTERFACE_MODE_TRGMII ||
++ if (interface == PHY_INTERFACE_MODE_INTERNAL ||
++ interface == PHY_INTERFACE_MODE_TRGMII ||
+ (phy_interface_mode_is_8023z(interface))) {
+ speed = SPEED_1000;
+ duplex = DUPLEX_FULL;
+@@ -3065,6 +3145,21 @@ mt7531_cpu_port_config(struct dsa_switch
+ return 0;
+ }
+
++static int
++mt7988_cpu_port_config(struct dsa_switch *ds, int port)
++{
++ struct mt7530_priv *priv = ds->priv;
++
++ mt7530_write(priv, MT7530_PMCR_P(port),
++ PMCR_CPU_PORT_SETTING(priv->id));
++
++ mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED,
++ PHY_INTERFACE_MODE_INTERNAL, NULL,
++ SPEED_10000, DUPLEX_FULL, true, true);
++
++ return 0;
++}
++
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+ {
+@@ -3207,6 +3302,27 @@ static int mt753x_set_mac_eee(struct dsa
+ return 0;
+ }
+
++static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
++{
++ return 0;
++}
++
++static int mt7988_setup(struct dsa_switch *ds)
++{
++ struct mt7530_priv *priv = ds->priv;
++
++ /* Reset the switch */
++ reset_control_assert(priv->rstc);
++ usleep_range(20, 50);
++ reset_control_deassert(priv->rstc);
++ usleep_range(20, 50);
++
++ /* Reset the switch PHYs */
++ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);
++
++ return mt7531_setup_common(ds);
++}
++
+ const struct dsa_switch_ops mt7530_switch_ops = {
+ .get_tag_protocol = mtk_get_tag_protocol,
+ .setup = mt753x_setup,
+@@ -3276,6 +3392,17 @@ const struct mt753x_info mt753x_table[]
+ .mac_port_get_caps = mt7531_mac_port_get_caps,
+ .mac_port_config = mt7531_mac_config,
+ },
++ [ID_MT7988] = {
++ .id = ID_MT7988,
++ .pcs_ops = &mt7530_pcs_ops,
++ .sw_setup = mt7988_setup,
++ .phy_read = mt7531_ind_phy_read,
++ .phy_write = mt7531_ind_phy_write,
++ .pad_setup = mt7988_pad_setup,
++ .cpu_port_config = mt7988_cpu_port_config,
++ .mac_port_get_caps = mt7988_mac_port_get_caps,
++ .mac_port_config = mt7988_mac_config,
++ },
+ };
+ EXPORT_SYMBOL_GPL(mt753x_table);
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -18,6 +18,7 @@ enum mt753x_id {
+ ID_MT7530 = 0,
+ ID_MT7621 = 1,
+ ID_MT7531 = 2,
++ ID_MT7988 = 3,
+ };
+
+ #define NUM_TRGMII_CTRL 5
+@@ -59,11 +60,11 @@ enum mt753x_id {
+ #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
+ #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
+
+-#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
++#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+ MT7531_CFC : MT7530_MFC)
+-#define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
++#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+ MT7531_MIRROR_EN : MIRROR_EN)
+-#define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
++#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+ MT7531_MIRROR_MASK : MIRROR_MASK)
+
+ /* Registers for BPDU and PAE frame control*/
+@@ -332,9 +333,8 @@ enum mt7530_vlan_port_acc_frm {
+ MT7531_FORCE_DPX | \
+ MT7531_FORCE_RX_FC | \
+ MT7531_FORCE_TX_FC)
+-#define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
+- MT7531_FORCE_MODE : \
+- PMCR_FORCE_MODE)
++#define PMCR_FORCE_MODE_ID(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
++ MT7531_FORCE_MODE : PMCR_FORCE_MODE)
+ #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+ PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+ PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
--- /dev/null
+From ed01748319b25456c5226ed0cb5e49e970da0e4f Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 16 Apr 2023 13:08:14 +0100
+Subject: [PATCH 15/48] net: dsa: mt7530: fix support for MT7531BE
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There are two variants of the MT7531 switch IC which got different
+features (and pins) regarding port 5:
+ * MT7531AE: SGMII/1000Base-X/2500Base-X SerDes PCS
+ * MT7531BE: RGMII
+
+Moving the creation of the SerDes PCS from mt753x_setup to mt7530_probe
+with commit 6de285229773 ("net: dsa: mt7530: move SGMII PCS creation
+to mt7530_probe function") works fine for MT7531AE which got two
+instances of mtk-pcs-lynxi, however, MT7531BE requires mt7531_pll_setup
+to setup clocks before the single PCS on port 6 (usually used as CPU
+port) starts to work and hence the PCS creation failed on MT7531BE.
+
+Fix this by introducing a pointer to mt7531_create_sgmii function in
+struct mt7530_priv and call it again at the end of mt753x_setup like it
+was before commit 6de285229773 ("net: dsa: mt7530: move SGMII PCS
+creation to mt7530_probe function").
+
+Fixes: 6de285229773 ("net: dsa: mt7530: move SGMII PCS creation to mt7530_probe function")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Acked-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/ZDvlLhhqheobUvOK@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530-mdio.c | 16 ++++++++--------
+ drivers/net/dsa/mt7530.c | 6 ++++++
+ drivers/net/dsa/mt7530.h | 4 ++--
+ 3 files changed, 16 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530-mdio.c
++++ b/drivers/net/dsa/mt7530-mdio.c
+@@ -81,14 +81,17 @@ static const struct regmap_bus mt7530_re
+ };
+
+ static int
+-mt7531_create_sgmii(struct mt7530_priv *priv)
++mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii)
+ {
+- struct regmap_config *mt7531_pcs_config[2];
++ struct regmap_config *mt7531_pcs_config[2] = {};
+ struct phylink_pcs *pcs;
+ struct regmap *regmap;
+ int i, ret = 0;
+
+- for (i = 0; i < 2; i++) {
++ /* MT7531AE has two SGMII units for port 5 and port 6
++ * MT7531BE has only one SGMII unit for port 6
++ */
++ for (i = dual_sgmii ? 0 : 1; i < 2; i++) {
+ mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
+ sizeof(struct regmap_config),
+ GFP_KERNEL);
+@@ -208,11 +211,8 @@ mt7530_probe(struct mdio_device *mdiodev
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+- if (priv->id == ID_MT7531) {
+- ret = mt7531_create_sgmii(priv);
+- if (ret)
+- return ret;
+- }
++ if (priv->id == ID_MT7531)
++ priv->create_sgmii = mt7531_create_sgmii;
+
+ return dsa_register_switch(priv->ds);
+ }
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3269,6 +3269,12 @@ mt753x_setup(struct dsa_switch *ds)
+ if (ret && priv->irq)
+ mt7530_free_irq_common(priv);
+
++ if (priv->create_sgmii) {
++ ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv));
++ if (ret && priv->irq)
++ mt7530_free_irq(priv);
++ }
++
+ return ret;
+ }
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -779,10 +779,10 @@ struct mt753x_info {
+ * registers
+ * @p6_interface Holding the current port 6 interface
+ * @p5_intf_sel: Holding the current port 5 interface select
+- *
+ * @irq: IRQ number of the switch
+ * @irq_domain: IRQ domain of the switch irq_chip
+ * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
++ * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
+ */
+ struct mt7530_priv {
+ struct device *dev;
+@@ -801,7 +801,6 @@ struct mt7530_priv {
+ unsigned int p5_intf_sel;
+ u8 mirror_rx;
+ u8 mirror_tx;
+-
+ struct mt7530_port ports[MT7530_NUM_PORTS];
+ struct mt753x_pcs pcs[MT7530_NUM_PORTS];
+ /* protect among processes for registers access*/
+@@ -809,6 +808,7 @@ struct mt7530_priv {
+ int irq;
+ struct irq_domain *irq_domain;
+ u32 irq_enable;
++ int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
+ };
+
+ struct mt7530_hw_vlan_entry {
--- /dev/null
+From fb6858e2c3b931433ea4d25871c272ee4c01bd99 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:07:29 +0100
+Subject: [PATCH 17/48] net: dsa: mt7530: update PCS driver to use neg_mode
+
+Update mt7530's embedded PCS driver to use neg_mode, even though it
+makes no use of it or the "mode" argument. This makes the driver
+consistent with converted drivers.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8Ej-00EaGR-Fk@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3225,7 +3225,7 @@ static void mt7530_pcs_get_state(struct
+ state->pause |= MLO_PAUSE_TX;
+ }
+
+-static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+@@ -3253,6 +3253,7 @@ mt753x_setup(struct dsa_switch *ds)
+ /* Initialise the PCS devices */
+ for (i = 0; i < priv->ds->num_ports; i++) {
+ priv->pcs[i].pcs.ops = priv->info->pcs_ops;
++ priv->pcs[i].pcs.neg_mode = true;
+ priv->pcs[i].priv = priv;
+ priv->pcs[i].port = i;
+ }
--- /dev/null
+From 03ede98ecc29b59fb364f735d6de0e6a4c1735fc Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Mon, 18 Sep 2023 21:19:12 +0200
+Subject: [PATCH 18/48] net: dsa: mt7530: Convert to platform remove callback
+ returning void
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The .remove() callback for a platform driver returns an int which makes
+many driver authors wrongly assume it's possible to do error handling by
+returning an error code. However the value returned is ignored (apart
+from emitting a warning) and this typically results in resource leaks.
+To improve here there is a quest to make the remove callback return
+void. In the first step of this quest all drivers are converted to
+.remove_new() which already returns void. Eventually after all drivers
+are converted, .remove_new() is renamed to .remove().
+
+Trivially convert this driver from always returning zero in the remove
+callback to the void returning variant.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530-mmio.c | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/dsa/mt7530-mmio.c
++++ b/drivers/net/dsa/mt7530-mmio.c
+@@ -62,15 +62,12 @@ mt7988_probe(struct platform_device *pde
+ return dsa_register_switch(priv->ds);
+ }
+
+-static int
+-mt7988_remove(struct platform_device *pdev)
++static void mt7988_remove(struct platform_device *pdev)
+ {
+ struct mt7530_priv *priv = platform_get_drvdata(pdev);
+
+ if (priv)
+ mt7530_remove_common(priv);
+-
+- return 0;
+ }
+
+ static void mt7988_shutdown(struct platform_device *pdev)
+@@ -87,7 +84,7 @@ static void mt7988_shutdown(struct platf
+
+ static struct platform_driver mt7988_platform_driver = {
+ .probe = mt7988_probe,
+- .remove = mt7988_remove,
++ .remove_new = mt7988_remove,
+ .shutdown = mt7988_shutdown,
+ .driver = {
+ .name = "mt7530-mmio",
--- /dev/null
+From 1a1a723d47c046d6c251651c9ade589040dafacf Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 27 Sep 2023 13:13:56 +0100
+Subject: [PATCH 19/48] net: dsa: mt753x: remove mt753x_phylink_pcs_link_up()
+
+Remove the mt753x_phylink_pcs_link_up() function for two reasons:
+
+1) priv->pcs[i].pcs.neg_mode is set true, meaning it doesn't take a
+ MLO_AN_FIXED anymore, but one of PHYLINK_PCS_NEG_*. However, this
+ is inconsequential due to...
+2) priv->pcs[port].pcs.ops is always initialised to point at
+ mt7530_pcs_ops, which does not have a pcs_link_up() member.
+
+So, let's remove mt753x_phylink_pcs_link_up() entirely.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Link: https://lore.kernel.org/r/E1qlTQS-008BWe-Va@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 11 -----------
+ 1 file changed, 11 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3040,15 +3040,6 @@ static void mt753x_phylink_mac_link_down
+ mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
+ }
+
+-static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs,
+- unsigned int mode,
+- phy_interface_t interface,
+- int speed, int duplex)
+-{
+- if (pcs->ops->pcs_link_up)
+- pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
+-}
+-
+ static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
+ unsigned int mode,
+ phy_interface_t interface,
+@@ -3137,8 +3128,6 @@ mt7531_cpu_port_config(struct dsa_switch
+ return ret;
+ mt7530_write(priv, MT7530_PMCR_P(port),
+ PMCR_CPU_PORT_SETTING(priv->id));
+- mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED,
+- interface, speed, DUPLEX_FULL);
+ mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
+ speed, DUPLEX_FULL, true, true);
+
--- /dev/null
+From 51e9c79a4d40fa3a64c0fbdab1ebbebf7cce2dba Mon Sep 17 00:00:00 2001
+From: Justin Stitt <justinstitt@google.com>
+Date: Mon, 9 Oct 2023 18:29:19 +0000
+Subject: [PATCH 20/48] net: dsa: mt7530: replace deprecated strncpy with
+ ethtool_sprintf
+
+`strncpy` is deprecated for use on NUL-terminated destination strings
+[1] and as such we should prefer more robust and less ambiguous string
+interfaces.
+
+ethtool_sprintf() is designed specifically for get_strings() usage.
+Let's replace strncpy in favor of this more robust and easier to
+understand interface.
+
+Link: https://www.kernel.org/doc/html/latest/process/deprecated.html#strncpy-on-nul-terminated-strings [1]
+Link: https://manpages.debian.org/testing/linux-manual-4.8/strscpy.9.en.html [2]
+Link: https://github.com/KSPP/linux/issues/90
+Signed-off-by: Justin Stitt <justinstitt@google.com>
+Reviewed-by: Kees Cook <keescook@chromium.org>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20231009-strncpy-drivers-net-dsa-mt7530-c-v1-1-ec6677a6436a@google.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -843,8 +843,7 @@ mt7530_get_strings(struct dsa_switch *ds
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
+- strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
+- ETH_GSTRING_LEN);
++ ethtool_sprintf(&data, "%s", mt7530_mib[i].name);
+ }
+
+ static void
--- /dev/null
+From 38be6fdf7e93431e91aac3884837b22236325f68 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:34:31 +0300
+Subject: [PATCH 21/48] net: dsa: mt7530: support OF-based registration of
+ switch MDIO bus
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently the MDIO bus of the switches the MT7530 DSA subdriver controls
+can only be registered as non-OF-based. Bring support for registering the
+bus OF-based.
+
+The subdrivers that control switches [with MDIO bus] probed on OF must
+follow this logic to support all cases properly:
+
+No switch MDIO bus defined: Populate ds->user_mii_bus, register the MDIO
+bus, set the interrupts for PHYs if "interrupt-controller" is defined at
+the switch node. This case should only be covered for the switches which
+their dt-bindings documentation didn't document the MDIO bus from the
+start. This is to keep supporting the device trees that do not describe the
+MDIO bus on the device tree but the MDIO bus is being used nonetheless.
+
+Switch MDIO bus defined: Don't populate ds->user_mii_bus, register the MDIO
+bus, set the interrupts for PHYs if ["interrupt-controller" is defined at
+the switch node and "interrupts" is defined at the PHY nodes under the
+switch MDIO bus node].
+
+Switch MDIO bus defined but explicitly disabled: If the device tree says
+status = "disabled" for the MDIO bus, we shouldn't need an MDIO bus at all.
+Instead, just exit as early as possible and do not call any MDIO API.
+
+The use of ds->user_mii_bus is inappropriate when the MDIO bus of the
+switch is described on the device tree [1], which is why we don't populate
+ds->user_mii_bus in that case.
+
+Link: https://lore.kernel.org/netdev/20231213120656.x46fyad6ls7sqyzv@skbuf/ [1]
+Suggested-by: David Bauer <mail@david-bauer.net>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122053431.7751-1-arinc.unal@arinc9.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 34 ++++++++++++++++++++++++++--------
+ 1 file changed, 26 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2350,24 +2350,40 @@ mt7530_free_irq_common(struct mt7530_pri
+ static void
+ mt7530_free_irq(struct mt7530_priv *priv)
+ {
+- mt7530_free_mdio_irq(priv);
++ struct device_node *mnp, *np = priv->dev->of_node;
++
++ mnp = of_get_child_by_name(np, "mdio");
++ if (!mnp)
++ mt7530_free_mdio_irq(priv);
++ of_node_put(mnp);
++
+ mt7530_free_irq_common(priv);
+ }
+
+ static int
+ mt7530_setup_mdio(struct mt7530_priv *priv)
+ {
++ struct device_node *mnp, *np = priv->dev->of_node;
+ struct dsa_switch *ds = priv->ds;
+ struct device *dev = priv->dev;
+ struct mii_bus *bus;
+ static int idx;
+- int ret;
++ int ret = 0;
++
++ mnp = of_get_child_by_name(np, "mdio");
++
++ if (mnp && !of_device_is_available(mnp))
++ goto out;
+
+ bus = devm_mdiobus_alloc(dev);
+- if (!bus)
+- return -ENOMEM;
++ if (!bus) {
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ if (!mnp)
++ ds->slave_mii_bus = bus;
+
+- ds->slave_mii_bus = bus;
+ bus->priv = priv;
+ bus->name = KBUILD_MODNAME "-mii";
+ snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
+@@ -2376,16 +2392,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+ bus->parent = dev;
+ bus->phy_mask = ~ds->phys_mii_mask;
+
+- if (priv->irq)
++ if (priv->irq && !mnp)
+ mt7530_setup_mdio_irq(priv);
+
+- ret = devm_mdiobus_register(dev, bus);
++ ret = devm_of_mdiobus_register(dev, bus, mnp);
+ if (ret) {
+ dev_err(dev, "failed to register MDIO bus: %d\n", ret);
+- if (priv->irq)
++ if (priv->irq && !mnp)
+ mt7530_free_mdio_irq(priv);
+ }
+
++out:
++ of_node_put(mnp);
+ return ret;
+ }
+
--- /dev/null
+From 022a254fafce88367914dfc8168fe687fc528cdb Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 05:17:25 +0000
+Subject: [PATCH 22/48] net: dsa: mt7530: fix 10M/100M speed on MT7988 switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Setup PMCR port register for actual speed and duplex on internally
+connected PHYs of the MT7988 built-in switch. This fixes links with
+speeds other than 1000M.
+
+Fixes: 110c18bfed41 ("net: dsa: mt7530: introduce driver for MT7988 built-in switch")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Acked-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/a5b04dfa8256d8302f402545a51ac4c626fdba25.1706071272.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3072,8 +3072,7 @@ static void mt753x_phylink_mac_link_up(s
+ /* MT753x MAC works in 1G full duplex mode for all up-clocked
+ * variants.
+ */
+- if (interface == PHY_INTERFACE_MODE_INTERNAL ||
+- interface == PHY_INTERFACE_MODE_TRGMII ||
++ if (interface == PHY_INTERFACE_MODE_TRGMII ||
+ (phy_interface_mode_is_8023z(interface))) {
+ speed = SPEED_1000;
+ duplex = DUPLEX_FULL;
--- /dev/null
+From a385398f77fad9eabe7cdc253e1a356484acc316 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:52 +0300
+Subject: [PATCH 23/48] net: dsa: mt7530: always trap frames to active CPU port
+ on MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On the MT7530 switch, the CPU_PORT field indicates which CPU port to trap
+frames to, regardless of the affinity of the inbound user port.
+
+When multiple CPU ports are in use, if the DSA conduit interface is down,
+trapped frames won't be passed to the conduit interface.
+
+To make trapping frames work including this case, implement
+ds->ops->conduit_state_change() on this subdriver and set the CPU_PORT
+field to the numerically smallest CPU port whose conduit interface is up.
+Introduce the active_cpu_ports field to store the information of the active
+CPU ports. Correct the macros, CPU_PORT is bits 4 through 6 of the
+register.
+
+Add a comment to explain frame trapping for this switch.
+
+Currently, the driver doesn't support the use of multiple CPU ports so this
+is not necessarily a bug fix.
+
+Suggested-by: Vladimir Oltean <olteanv@gmail.com>
+Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-1-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 35 +++++++++++++++++++++++++++++++----
+ drivers/net/dsa/mt7530.h | 6 ++++--
+ 2 files changed, 35 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1239,10 +1239,6 @@ mt753x_cpu_port_enable(struct dsa_switch
+ mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
+ UNU_FFP(BIT(port)));
+
+- /* Set CPU port number */
+- if (priv->id == ID_MT7530 || priv->id == ID_MT7621)
+- mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
+-
+ /* Add the CPU port to the CPU port bitmap for MT7531. Trapped frames
+ * will be forwarded to the CPU port that is affine to the inbound user
+ * port.
+@@ -3314,6 +3310,36 @@ static int mt753x_set_mac_eee(struct dsa
+ return 0;
+ }
+
++static void
++mt753x_conduit_state_change(struct dsa_switch *ds,
++ const struct net_device *conduit,
++ bool operational)
++{
++ struct dsa_port *cpu_dp = conduit->dsa_ptr;
++ struct mt7530_priv *priv = ds->priv;
++ int val = 0;
++ u8 mask;
++
++ /* Set the CPU port to trap frames to for MT7530. Trapped frames will be
++ * forwarded to the numerically smallest CPU port whose conduit
++ * interface is up.
++ */
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return;
++
++ mask = BIT(cpu_dp->index);
++
++ if (operational)
++ priv->active_cpu_ports |= mask;
++ else
++ priv->active_cpu_ports &= ~mask;
++
++ if (priv->active_cpu_ports)
++ val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
++
++ mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
++}
++
+ static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
+ {
+ return 0;
+@@ -3369,6 +3395,7 @@ const struct dsa_switch_ops mt7530_switc
+ .phylink_mac_link_up = mt753x_phylink_mac_link_up,
+ .get_mac_eee = mt753x_get_mac_eee,
+ .set_mac_eee = mt753x_set_mac_eee,
++ .master_state_change = mt753x_conduit_state_change,
+ };
+ EXPORT_SYMBOL_GPL(mt7530_switch_ops);
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -45,8 +45,8 @@ enum mt753x_id {
+ #define UNU_FFP(x) (((x) & 0xff) << 8)
+ #define UNU_FFP_MASK UNU_FFP(~0)
+ #define CPU_EN BIT(7)
+-#define CPU_PORT(x) ((x) << 4)
+-#define CPU_MASK (0xf << 4)
++#define CPU_PORT_MASK GENMASK(6, 4)
++#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x)
+ #define MIRROR_EN BIT(3)
+ #define MIRROR_PORT(x) ((x) & 0x7)
+ #define MIRROR_MASK 0x7
+@@ -783,6 +783,7 @@ struct mt753x_info {
+ * @irq_domain: IRQ domain of the switch irq_chip
+ * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
+ * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
++ * @active_cpu_ports: Holding the active CPU ports
+ */
+ struct mt7530_priv {
+ struct device *dev;
+@@ -809,6 +810,7 @@ struct mt7530_priv {
+ struct irq_domain *irq_domain;
+ u32 irq_enable;
+ int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
++ u8 active_cpu_ports;
+ };
+
+ struct mt7530_hw_vlan_entry {
--- /dev/null
+From e3c8f69af69e6c4022094309445c009faf5e8cef Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:53 +0300
+Subject: [PATCH 24/48] net: dsa: mt7530: use p5_interface_select as data type
+ for p5_intf_sel
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use the p5_interface_select enumeration as the data type for the
+p5_intf_sel field. This ensures p5_intf_sel can only take the values
+defined in the p5_interface_select enumeration.
+
+Remove the explicit assignment of 0 to P5_DISABLED as the first enum item
+is automatically assigned 0.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-2-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -713,7 +713,7 @@ struct mt7530_port {
+
+ /* Port 5 interface select definitions */
+ enum p5_interface_select {
+- P5_DISABLED = 0,
++ P5_DISABLED,
+ P5_INTF_SEL_PHY_P0,
+ P5_INTF_SEL_PHY_P4,
+ P5_INTF_SEL_GMAC5,
+@@ -799,7 +799,7 @@ struct mt7530_priv {
+ bool mcm;
+ phy_interface_t p6_interface;
+ phy_interface_t p5_interface;
+- unsigned int p5_intf_sel;
++ enum p5_interface_select p5_intf_sel;
+ u8 mirror_rx;
+ u8 mirror_tx;
+ struct mt7530_port ports[MT7530_NUM_PORTS];
--- /dev/null
+From b0d590a5cdd95ed863717b279751d6166083889f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:54 +0300
+Subject: [PATCH 25/48] net: dsa: mt7530: store port 5 SGMII capability of
+ MT7531
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Introduce the p5_sgmii field to store the information for whether port 5
+has got SGMII or not. Instead of reading the MT7531_TOP_SIG_SR register
+multiple times, the register will be read once and the value will be
+stored on the p5_sgmii field. This saves unnecessary reads of the
+register.
+
+Move the comment about MT7531AE and MT7531BE to mt7531_setup(), where the
+switch is identified.
+
+Get rid of mt7531_dual_sgmii_supported() now that priv->p5_sgmii stores the
+information. Address the code where mt7531_dual_sgmii_supported() is used.
+
+Get rid of mt7531_is_rgmii_port() which just prints the opposite of
+priv->p5_sgmii.
+
+Instead of calling mt7531_pll_setup() then returning, do not call it if
+port 5 is SGMII.
+
+Remove P5_INTF_SEL_GMAC5_SGMII. The p5_interface_select enum is supposed to
+represent the mode that port 5 is being used in, not the hardware
+information of port 5. Set p5_intf_sel to P5_INTF_SEL_GMAC5 instead, if
+port 5 is not dsa_is_unused_port().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-3-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530-mdio.c | 7 ++---
+ drivers/net/dsa/mt7530.c | 48 ++++++++++++-----------------------
+ drivers/net/dsa/mt7530.h | 6 +++--
+ 3 files changed, 22 insertions(+), 39 deletions(-)
+
+--- a/drivers/net/dsa/mt7530-mdio.c
++++ b/drivers/net/dsa/mt7530-mdio.c
+@@ -81,17 +81,14 @@ static const struct regmap_bus mt7530_re
+ };
+
+ static int
+-mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii)
++mt7531_create_sgmii(struct mt7530_priv *priv)
+ {
+ struct regmap_config *mt7531_pcs_config[2] = {};
+ struct phylink_pcs *pcs;
+ struct regmap *regmap;
+ int i, ret = 0;
+
+- /* MT7531AE has two SGMII units for port 5 and port 6
+- * MT7531BE has only one SGMII unit for port 6
+- */
+- for (i = dual_sgmii ? 0 : 1; i < 2; i++) {
++ for (i = priv->p5_sgmii ? 0 : 1; i < 2; i++) {
+ mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
+ sizeof(struct regmap_config),
+ GFP_KERNEL);
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -487,15 +487,6 @@ mt7530_pad_clk_setup(struct dsa_switch *
+ return 0;
+ }
+
+-static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
+-{
+- u32 val;
+-
+- val = mt7530_read(priv, MT7531_TOP_SIG_SR);
+-
+- return (val & PAD_DUAL_SGMII_EN) != 0;
+-}
+-
+ static int
+ mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
+ {
+@@ -510,9 +501,6 @@ mt7531_pll_setup(struct mt7530_priv *pri
+ u32 xtal;
+ u32 val;
+
+- if (mt7531_dual_sgmii_supported(priv))
+- return;
+-
+ val = mt7530_read(priv, MT7531_CREV);
+ top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
+ hwstrap = mt7530_read(priv, MT7531_HWTRAP);
+@@ -927,8 +915,6 @@ static const char *p5_intf_modes(unsigne
+ return "PHY P4";
+ case P5_INTF_SEL_GMAC5:
+ return "GMAC5";
+- case P5_INTF_SEL_GMAC5_SGMII:
+- return "GMAC5_SGMII";
+ default:
+ return "unknown";
+ }
+@@ -2697,6 +2683,12 @@ mt7531_setup(struct dsa_switch *ds)
+ return -ENODEV;
+ }
+
++ /* MT7531AE has got two SGMII units. One for port 5, one for port 6.
++ * MT7531BE has got only one SGMII unit which is for port 6.
++ */
++ val = mt7530_read(priv, MT7531_TOP_SIG_SR);
++ priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
++
+ /* all MACs must be forced link-down before sw reset */
+ for (i = 0; i < MT7530_NUM_PORTS; i++)
+ mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
+@@ -2706,21 +2698,18 @@ mt7531_setup(struct dsa_switch *ds)
+ SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
+ SYS_CTRL_REG_RST);
+
+- mt7531_pll_setup(priv);
+-
+- if (mt7531_dual_sgmii_supported(priv)) {
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
+-
++ if (!priv->p5_sgmii) {
++ mt7531_pll_setup(priv);
++ } else {
+ /* Let ds->slave_mii_bus be able to access external phy. */
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
+ MT7531_EXT_P_MDC_11);
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
+ MT7531_EXT_P_MDIO_12);
+- } else {
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+ }
+- dev_dbg(ds->dev, "P5 support %s interface\n",
+- p5_intf_modes(priv->p5_intf_sel));
++
++ if (!dsa_is_unused_port(ds, 5))
++ priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+
+ mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
+ MT7531_GPIO0_INTERRUPT);
+@@ -2787,11 +2776,6 @@ static void mt7530_mac_port_get_caps(str
+ }
+ }
+
+-static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
+-{
+- return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
+-}
+-
+ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+ {
+@@ -2804,7 +2788,7 @@ static void mt7531_mac_port_get_caps(str
+ break;
+
+ case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
+- if (mt7531_is_rgmii_port(priv, port)) {
++ if (!priv->p5_sgmii) {
+ phy_interface_set_rgmii(config->supported_interfaces);
+ break;
+ }
+@@ -2871,7 +2855,7 @@ static int mt7531_rgmii_setup(struct mt7
+ {
+ u32 val;
+
+- if (!mt7531_is_rgmii_port(priv, port)) {
++ if (priv->p5_sgmii) {
+ dev_err(priv->dev, "RGMII mode is not available for port %d\n",
+ port);
+ return -EINVAL;
+@@ -3114,7 +3098,7 @@ mt7531_cpu_port_config(struct dsa_switch
+
+ switch (port) {
+ case 5:
+- if (mt7531_is_rgmii_port(priv, port))
++ if (!priv->p5_sgmii)
+ interface = PHY_INTERFACE_MODE_RGMII;
+ else
+ interface = PHY_INTERFACE_MODE_2500BASEX;
+@@ -3272,7 +3256,7 @@ mt753x_setup(struct dsa_switch *ds)
+ mt7530_free_irq_common(priv);
+
+ if (priv->create_sgmii) {
+- ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv));
++ ret = priv->create_sgmii(priv);
+ if (ret && priv->irq)
+ mt7530_free_irq(priv);
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -717,7 +717,6 @@ enum p5_interface_select {
+ P5_INTF_SEL_PHY_P0,
+ P5_INTF_SEL_PHY_P4,
+ P5_INTF_SEL_GMAC5,
+- P5_INTF_SEL_GMAC5_SGMII,
+ };
+
+ struct mt7530_priv;
+@@ -779,6 +778,8 @@ struct mt753x_info {
+ * registers
+ * @p6_interface Holding the current port 6 interface
+ * @p5_intf_sel: Holding the current port 5 interface select
++ * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
++ * has got SGMII
+ * @irq: IRQ number of the switch
+ * @irq_domain: IRQ domain of the switch irq_chip
+ * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
+@@ -800,6 +801,7 @@ struct mt7530_priv {
+ phy_interface_t p6_interface;
+ phy_interface_t p5_interface;
+ enum p5_interface_select p5_intf_sel;
++ bool p5_sgmii;
+ u8 mirror_rx;
+ u8 mirror_tx;
+ struct mt7530_port ports[MT7530_NUM_PORTS];
+@@ -809,7 +811,7 @@ struct mt7530_priv {
+ int irq;
+ struct irq_domain *irq_domain;
+ u32 irq_enable;
+- int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
++ int (*create_sgmii)(struct mt7530_priv *priv);
+ u8 active_cpu_ports;
+ };
+
--- /dev/null
+From 0dcde4c1e7c47822a6b00d6f96b7f19e51536026 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:55 +0300
+Subject: [PATCH 26/48] net: dsa: mt7530: improve comments regarding switch
+ ports
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There's no logic to numerically order the CPU ports. Just state the port
+number instead.
+
+Remove the irrelevant PHY muxing information from
+mt7530_mac_port_get_caps(). Explain the supported MII modes instead.
+
+Remove the out of place PHY muxing information from
+mt753x_phylink_mac_config(). The function is for MT7530, MT7531, and the
+switch on the MT7988 SoC but there's no PHY muxing on MT7531 or the switch
+on the MT7988 SoC.
+
+These comments were gradually introduced with the commits below.
+commit ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API")
+commit 38f790a80560 ("net: dsa: mt7530: Add support for port 5")
+commit 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding
+a new hardware")
+commit c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch")
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-4-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 30 ++++++++++++++++++++----------
+ 1 file changed, 20 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2754,12 +2754,14 @@ static void mt7530_mac_port_get_caps(str
+ struct phylink_config *config)
+ {
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ /* Ports which are connected to switch PHYs. There is no MII pinout. */
++ case 0 ... 4:
+ __set_bit(PHY_INTERFACE_MODE_GMII,
+ config->supported_interfaces);
+ break;
+
+- case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
++ /* Port 5 supports rgmii with delays, mii, and gmii. */
++ case 5:
+ phy_interface_set_rgmii(config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_MII,
+ config->supported_interfaces);
+@@ -2767,7 +2769,8 @@ static void mt7530_mac_port_get_caps(str
+ config->supported_interfaces);
+ break;
+
+- case 6: /* 1st cpu port */
++ /* Port 6 supports rgmii and trgmii. */
++ case 6:
+ __set_bit(PHY_INTERFACE_MODE_RGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_TRGMII,
+@@ -2782,19 +2785,24 @@ static void mt7531_mac_port_get_caps(str
+ struct mt7530_priv *priv = ds->priv;
+
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ /* Ports which are connected to switch PHYs. There is no MII pinout. */
++ case 0 ... 4:
+ __set_bit(PHY_INTERFACE_MODE_GMII,
+ config->supported_interfaces);
+ break;
+
+- case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
++ /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on
++ * MT7531AE.
++ */
++ case 5:
+ if (!priv->p5_sgmii) {
+ phy_interface_set_rgmii(config->supported_interfaces);
+ break;
+ }
+ fallthrough;
+
+- case 6: /* 1st cpu port supports sgmii/8023z only */
++ /* Port 6 supports sgmii/802.3z. */
++ case 6:
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+@@ -2813,11 +2821,13 @@ static void mt7988_mac_port_get_caps(str
+ phy_interface_zero(config->supported_interfaces);
+
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ /* Ports which are connected to switch PHYs. There is no MII pinout. */
++ case 0 ... 4:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ break;
+
++ /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
+ case 6:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+@@ -2981,12 +2991,12 @@ mt753x_phylink_mac_config(struct dsa_swi
+ u32 mcr_cur, mcr_new;
+
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ case 0 ... 4:
+ if (state->interface != PHY_INTERFACE_MODE_GMII &&
+ state->interface != PHY_INTERFACE_MODE_INTERNAL)
+ goto unsupported;
+ break;
+- case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
++ case 5:
+ if (priv->p5_interface == state->interface)
+ break;
+
+@@ -2996,7 +3006,7 @@ mt753x_phylink_mac_config(struct dsa_swi
+ if (priv->p5_intf_sel != P5_DISABLED)
+ priv->p5_interface = state->interface;
+ break;
+- case 6: /* 1st cpu port */
++ case 6:
+ if (priv->p6_interface == state->interface)
+ break;
+
--- /dev/null
+From 0f03d9bfa1da1d26cb950e4b35b1ff7b9be1828f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:56 +0300
+Subject: [PATCH 27/48] net: dsa: mt7530: improve code path for setting up port
+ 5
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There're two code paths for setting up port 5:
+
+mt7530_setup()
+-> mt7530_setup_port5()
+
+mt753x_phylink_mac_config()
+-> mt753x_mac_config()
+ -> mt7530_mac_config()
+ -> mt7530_setup_port5()
+
+Currently mt7530_setup_port5() from mt7530_setup() always runs. If port 5
+is used as a CPU, DSA, or user port, mt7530_setup_port5() from
+mt753x_phylink_mac_config() won't run. That is because priv->p5_interface
+set on mt7530_setup_port5() will match state->interface on
+mt753x_phylink_mac_config() which will stop running mt7530_setup_port5()
+again.
+
+Therefore, mt7530_setup_port5() will never run from
+mt753x_phylink_mac_config().
+
+Address this by not running mt7530_setup_port5() from mt7530_setup() if
+port 5 is used as a CPU, DSA, or user port. This driver isn't in the
+dsa_switches_apply_workarounds[] array so phylink will always be present.
+
+To keep the cases where port 5 isn't controlled by phylink working as
+before, preserve the mt7530_setup_port5() call from mt7530_setup().
+
+Do not set priv->p5_intf_sel to P5_DISABLED. It is already set to that when
+"priv" is allocated.
+
+Move setting the interface to a more specific location. It's supposed to be
+overwritten if PHY muxing is detected.
+
+Improve the comment which explains the process.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-5-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 17 ++++++++---------
+ 1 file changed, 8 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2532,16 +2532,15 @@ mt7530_setup(struct dsa_switch *ds)
+ return ret;
+
+ /* Setup port 5 */
+- priv->p5_intf_sel = P5_DISABLED;
+- interface = PHY_INTERFACE_MODE_NA;
+-
+ if (!dsa_is_unused_port(ds, 5)) {
+ priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+- ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
+- if (ret && ret != -ENODEV)
+- return ret;
+ } else {
+- /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
++ /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.
++ * Set priv->p5_intf_sel to the appropriate value if PHY muxing
++ * is detected.
++ */
++ interface = PHY_INTERFACE_MODE_NA;
++
+ for_each_child_of_node(dn, mac_np) {
+ if (!of_device_is_compatible(mac_np,
+ "mediatek,eth-mac"))
+@@ -2572,6 +2571,8 @@ mt7530_setup(struct dsa_switch *ds)
+ of_node_put(phy_node);
+ break;
+ }
++
++ mt7530_setup_port5(ds, interface);
+ }
+
+ #ifdef CONFIG_GPIOLIB
+@@ -2582,8 +2583,6 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+ #endif /* CONFIG_GPIOLIB */
+
+- mt7530_setup_port5(ds, interface);
+-
+ /* Flush the FDB table */
+ ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
+ if (ret < 0)
--- /dev/null
+From 120581c81ad19704a9325505c83a82b7e760e96e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:57 +0300
+Subject: [PATCH 28/48] net: dsa: mt7530: do not set priv->p5_interface on
+ mt7530_setup_port5()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Running mt7530_setup_port5() from mt7530_setup() used to handle all cases
+of configuring port 5, including phylink.
+
+Setting priv->p5_interface under mt7530_setup_port5() makes sure that
+mt7530_setup_port5() from mt753x_phylink_mac_config() won't run.
+
+The commit ("net: dsa: mt7530: improve code path for setting up port 5")
+makes so that mt7530_setup_port5() from mt7530_setup() runs only on
+non-phylink cases.
+
+Get rid of unnecessarily setting priv->p5_interface under
+mt7530_setup_port5() as port 5 phylink configuration will be done by
+running mt7530_setup_port5() from mt753x_phylink_mac_config() now.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-6-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -985,8 +985,6 @@ static void mt7530_setup_port5(struct ds
+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
+ val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
+
+- priv->p5_interface = interface;
+-
+ unlock_exit:
+ mutex_unlock(&priv->reg_mutex);
+ }
--- /dev/null
+From 3b423061eb3a62e59b57939ae1e1234756a0f6a1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:58 +0300
+Subject: [PATCH 29/48] net: dsa: mt7530: do not run mt7530_setup_port5() if
+ port 5 is disabled
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There's no need to run all the code on mt7530_setup_port5() if port 5 is
+disabled. The only case for calling mt7530_setup_port5() from
+mt7530_setup() is when PHY muxing is enabled. That is because port 5 is not
+defined as a port on the devicetree, therefore, it cannot be controlled by
+phylink.
+
+Because of this, run mt7530_setup_port5() if priv->p5_intf_sel is
+P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4. Remove the P5_DISABLED case from
+mt7530_setup_port5().
+
+Stop initialising the interface variable as the remaining cases will always
+call mt7530_setup_port5() with it initialised.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-7-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 9 +++------
+ 1 file changed, 3 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -949,9 +949,6 @@ static void mt7530_setup_port5(struct ds
+ /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+ val &= ~MHWTRAP_P5_DIS;
+ break;
+- case P5_DISABLED:
+- interface = PHY_INTERFACE_MODE_NA;
+- break;
+ default:
+ dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
+ priv->p5_intf_sel);
+@@ -2537,8 +2534,6 @@ mt7530_setup(struct dsa_switch *ds)
+ * Set priv->p5_intf_sel to the appropriate value if PHY muxing
+ * is detected.
+ */
+- interface = PHY_INTERFACE_MODE_NA;
+-
+ for_each_child_of_node(dn, mac_np) {
+ if (!of_device_is_compatible(mac_np,
+ "mediatek,eth-mac"))
+@@ -2570,7 +2565,9 @@ mt7530_setup(struct dsa_switch *ds)
+ break;
+ }
+
+- mt7530_setup_port5(ds, interface);
++ if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||
++ priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)
++ mt7530_setup_port5(ds, interface);
+ }
+
+ #ifdef CONFIG_GPIOLIB
--- /dev/null
+From 959f4ac4940bebb84bdd25ac61470b3965e1e475 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:02 +0300
+Subject: [PATCH 30/48] net: dsa: mt7530: empty default case on
+ mt7530_setup_port5()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There're two code paths for setting up port 5:
+
+mt7530_setup()
+-> mt7530_setup_port5()
+
+mt753x_phylink_mac_config()
+-> mt753x_mac_config()
+ -> mt7530_mac_config()
+ -> mt7530_setup_port5()
+
+On the first code path, priv->p5_intf_sel is either set to
+P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4 when mt7530_setup_port5() is run.
+
+On the second code path, priv->p5_intf_sel is set to P5_INTF_SEL_GMAC5 when
+mt7530_setup_port5() is run.
+
+Empty the default case which will never run but is needed nonetheless to
+handle all the remaining enumeration values.
+
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-1-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -950,9 +950,7 @@ static void mt7530_setup_port5(struct ds
+ val &= ~MHWTRAP_P5_DIS;
+ break;
+ default:
+- dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
+- priv->p5_intf_sel);
+- goto unlock_exit;
++ break;
+ }
+
+ /* Setup RGMII settings */
+@@ -982,7 +980,6 @@ static void mt7530_setup_port5(struct ds
+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
+ val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
+
+-unlock_exit:
+ mutex_unlock(&priv->reg_mutex);
+ }
+
--- /dev/null
+From 9ec0a800c8e0850e1358b7402d6af557af81cb38 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:03 +0300
+Subject: [PATCH 31/48] net: dsa: mt7530: move XTAL check to mt7530_setup()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The crystal frequency concerns the switch core. The frequency should be
+checked when the switch is being set up so the driver can reject the
+unsupported hardware earlier and without requiring port 6 to be used.
+
+Move it to mt7530_setup(). Drop the unnecessary function printing.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-2-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -422,13 +422,6 @@ mt7530_pad_clk_setup(struct dsa_switch *
+
+ xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
+
+- if (xtal == HWTRAP_XTAL_20MHZ) {
+- dev_err(priv->dev,
+- "%s: MT7530 with a 20MHz XTAL is not supported!\n",
+- __func__);
+- return -EINVAL;
+- }
+-
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ trgint = 0;
+@@ -2461,6 +2454,12 @@ mt7530_setup(struct dsa_switch *ds)
+ return -ENODEV;
+ }
+
++ if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
++ dev_err(priv->dev,
++ "MT7530 with a 20MHz XTAL is not supported!\n");
++ return -EINVAL;
++ }
++
+ /* Reset the switch through internal reset */
+ mt7530_write(priv, MT7530_SYS_CTRL,
+ SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
--- /dev/null
+From 7199c736aa8cd9c69ae681a9c733408372c2ce76 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:04 +0300
+Subject: [PATCH 32/48] net: dsa: mt7530: simplify mt7530_pad_clk_setup()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This code is from before this driver was converted to phylink API. Phylink
+deals with the unsupported interface cases before mt7530_pad_clk_setup() is
+run. Therefore, the default case would never run. However, it must be
+defined nonetheless to handle all the remaining enumeration values, the
+phy-modes.
+
+Switch to if statement for RGMII and return which simplifies the code and
+saves an indent.
+
+Set P6_INTF_MODE, which is the three least significant bits of the
+MT7530_P6ECR register, to 0 for RGMII even though it will already be 0
+after reset. This is to keep supporting dynamic reconfiguration of the port
+in the case the interface changes from TRGMII to RGMII.
+
+Disable the TRGMII clocks for all cases. They will be enabled if TRGMII is
+being used.
+
+Read XTAL after checking for RGMII as it's only needed for the TRGMII
+interface mode.
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-3-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 91 ++++++++++++++++++----------------------
+ 1 file changed, 40 insertions(+), 51 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -418,65 +418,54 @@ static int
+ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- u32 ncpo1, ssc_delta, trgint, xtal;
++ u32 ncpo1, ssc_delta, xtal;
+
+- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
++ /* Disable the MT7530 TRGMII clocks */
++ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
+
+- switch (interface) {
+- case PHY_INTERFACE_MODE_RGMII:
+- trgint = 0;
+- break;
+- case PHY_INTERFACE_MODE_TRGMII:
+- trgint = 1;
+- if (xtal == HWTRAP_XTAL_25MHZ)
+- ssc_delta = 0x57;
+- else
+- ssc_delta = 0x87;
+- if (priv->id == ID_MT7621) {
+- /* PLL frequency: 125MHz: 1.0GBit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
+- ncpo1 = 0x0640;
+- if (xtal == HWTRAP_XTAL_25MHZ)
+- ncpo1 = 0x0a00;
+- } else { /* PLL frequency: 250MHz: 2.0Gbit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
+- ncpo1 = 0x0c80;
+- if (xtal == HWTRAP_XTAL_25MHZ)
+- ncpo1 = 0x1400;
+- }
+- break;
+- default:
+- dev_err(priv->dev, "xMII interface %d not supported\n",
+- interface);
+- return -EINVAL;
++ if (interface == PHY_INTERFACE_MODE_RGMII) {
++ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
++ P6_INTF_MODE(0));
++ return 0;
+ }
+
+- mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
+- P6_INTF_MODE(trgint));
++ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
+
+- if (trgint) {
+- /* Disable the MT7530 TRGMII clocks */
+- core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
+-
+- /* Setup the MT7530 TRGMII Tx Clock */
+- core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
+- core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
+- core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
+- core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
+- core_write(priv, CORE_PLL_GROUP4,
+- RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
+- RG_SYSPLL_BIAS_LPF_EN);
+- core_write(priv, CORE_PLL_GROUP2,
+- RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
+- RG_SYSPLL_POSDIV(1));
+- core_write(priv, CORE_PLL_GROUP7,
+- RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
+- RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
++ xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
+
+- /* Enable the MT7530 TRGMII clocks */
+- core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
++ if (xtal == HWTRAP_XTAL_25MHZ)
++ ssc_delta = 0x57;
++ else
++ ssc_delta = 0x87;
++
++ if (priv->id == ID_MT7621) {
++ /* PLL frequency: 125MHz: 1.0GBit */
++ if (xtal == HWTRAP_XTAL_40MHZ)
++ ncpo1 = 0x0640;
++ if (xtal == HWTRAP_XTAL_25MHZ)
++ ncpo1 = 0x0a00;
++ } else { /* PLL frequency: 250MHz: 2.0Gbit */
++ if (xtal == HWTRAP_XTAL_40MHZ)
++ ncpo1 = 0x0c80;
++ if (xtal == HWTRAP_XTAL_25MHZ)
++ ncpo1 = 0x1400;
+ }
+
++ /* Setup the MT7530 TRGMII Tx Clock */
++ core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
++ core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
++ core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
++ core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
++ core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
++ RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
++ core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL |
++ RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1));
++ core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG |
++ RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
++
++ /* Enable the MT7530 TRGMII clocks */
++ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
++
+ return 0;
+ }
+
--- /dev/null
+From 921a7deee767aa157b5372863a4c1cac53e5c53a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:05 +0300
+Subject: [PATCH 33/48] net: dsa: mt7530: call port 6 setup from
+ mt7530_mac_config()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+mt7530_pad_clk_setup() is called if port 6 is enabled. It used to do more
+things than setting up port 6. That part was moved to more appropriate
+locations, mt7530_setup() and mt7530_pll_setup().
+
+Now that all it does is set up port 6, rename it to mt7530_setup_port6(),
+and move it to a more appropriate location, under mt7530_mac_config().
+
+Change mt7530_setup_port6() to void as there're no error cases.
+
+Leave an empty mt7530_pad_clk_setup() to satisfy the pad_setup function
+pointer.
+
+This is the code path for setting up the ports before:
+
+dsa_switch_ops :: phylink_mac_config() -> mt753x_phylink_mac_config()
+-> mt753x_mac_config()
+ -> mt753x_info :: mac_port_config() -> mt7530_mac_config()
+ -> mt7530_setup_port5()
+-> mt753x_pad_setup()
+ -> mt753x_info :: pad_setup() -> mt7530_pad_clk_setup()
+
+This is after:
+
+dsa_switch_ops :: phylink_mac_config() -> mt753x_phylink_mac_config()
+-> mt753x_mac_config()
+ -> mt753x_info :: mac_port_config() -> mt7530_mac_config()
+ -> mt7530_setup_port5()
+ -> mt7530_setup_port6()
+
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-4-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 19 +++++++++++--------
+ 1 file changed, 11 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -414,8 +414,8 @@ mt753x_preferred_default_local_cpu_port(
+ }
+
+ /* Setup port 6 interface mode and TRGMII TX circuit */
+-static int
+-mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
++static void
++mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface)
+ {
+ struct mt7530_priv *priv = ds->priv;
+ u32 ncpo1, ssc_delta, xtal;
+@@ -426,7 +426,7 @@ mt7530_pad_clk_setup(struct dsa_switch *
+ if (interface == PHY_INTERFACE_MODE_RGMII) {
+ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
+ P6_INTF_MODE(0));
+- return 0;
++ return;
+ }
+
+ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
+@@ -465,7 +465,11 @@ mt7530_pad_clk_setup(struct dsa_switch *
+
+ /* Enable the MT7530 TRGMII clocks */
+ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
++}
+
++static int
++mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
++{
+ return 0;
+ }
+
+@@ -2829,11 +2833,10 @@ mt7530_mac_config(struct dsa_switch *ds,
+ {
+ struct mt7530_priv *priv = ds->priv;
+
+- /* Only need to setup port5. */
+- if (port != 5)
+- return 0;
+-
+- mt7530_setup_port5(priv->ds, interface);
++ if (port == 5)
++ mt7530_setup_port5(priv->ds, interface);
++ else if (port == 6)
++ mt7530_setup_port6(priv->ds, interface);
+
+ return 0;
+ }
--- /dev/null
+From fcbc5d900fa53f79963fe4626069739ee5567b4b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:06 +0300
+Subject: [PATCH 34/48] net: dsa: mt7530: remove pad_setup function pointer
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The pad_setup function pointer was introduced with 88bdef8be9f6 ("net: dsa:
+mt7530: Extend device data ready for adding a new hardware"). It was being
+used to set up the core clock and port 6 of the MT7530 switch, and pll of
+the MT7531 switch.
+
+All of these were moved to more appropriate locations, and it was never
+used for the switch on the MT7988 SoC. Therefore, this function pointer
+hasn't got a use anymore. Remove it.
+
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-5-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 36 ++----------------------------------
+ drivers/net/dsa/mt7530.h | 3 ---
+ 2 files changed, 2 insertions(+), 37 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -467,18 +467,6 @@ mt7530_setup_port6(struct dsa_switch *ds
+ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
+ }
+
+-static int
+-mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
+-{
+- return 0;
+-}
+-
+-static int
+-mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
+-{
+- return 0;
+-}
+-
+ static void
+ mt7531_pll_setup(struct mt7530_priv *priv)
+ {
+@@ -2820,14 +2808,6 @@ static void mt7988_mac_port_get_caps(str
+ }
+
+ static int
+-mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
+-{
+- struct mt7530_priv *priv = ds->priv;
+-
+- return priv->info->pad_setup(ds, state->interface);
+-}
+-
+-static int
+ mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ phy_interface_t interface)
+ {
+@@ -2992,8 +2972,6 @@ mt753x_phylink_mac_config(struct dsa_swi
+ if (priv->p6_interface == state->interface)
+ break;
+
+- mt753x_pad_setup(ds, state);
+-
+ if (mt753x_mac_config(ds, port, mode, state) < 0)
+ goto unsupported;
+
+@@ -3316,11 +3294,6 @@ mt753x_conduit_state_change(struct dsa_s
+ mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
+ }
+
+-static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
+-{
+- return 0;
+-}
+-
+ static int mt7988_setup(struct dsa_switch *ds)
+ {
+ struct mt7530_priv *priv = ds->priv;
+@@ -3382,7 +3355,6 @@ const struct mt753x_info mt753x_table[]
+ .sw_setup = mt7530_setup,
+ .phy_read = mt7530_phy_read,
+ .phy_write = mt7530_phy_write,
+- .pad_setup = mt7530_pad_clk_setup,
+ .mac_port_get_caps = mt7530_mac_port_get_caps,
+ .mac_port_config = mt7530_mac_config,
+ },
+@@ -3392,7 +3364,6 @@ const struct mt753x_info mt753x_table[]
+ .sw_setup = mt7530_setup,
+ .phy_read = mt7530_phy_read,
+ .phy_write = mt7530_phy_write,
+- .pad_setup = mt7530_pad_clk_setup,
+ .mac_port_get_caps = mt7530_mac_port_get_caps,
+ .mac_port_config = mt7530_mac_config,
+ },
+@@ -3402,7 +3373,6 @@ const struct mt753x_info mt753x_table[]
+ .sw_setup = mt7531_setup,
+ .phy_read = mt7531_ind_phy_read,
+ .phy_write = mt7531_ind_phy_write,
+- .pad_setup = mt7531_pad_setup,
+ .cpu_port_config = mt7531_cpu_port_config,
+ .mac_port_get_caps = mt7531_mac_port_get_caps,
+ .mac_port_config = mt7531_mac_config,
+@@ -3413,7 +3383,6 @@ const struct mt753x_info mt753x_table[]
+ .sw_setup = mt7988_setup,
+ .phy_read = mt7531_ind_phy_read,
+ .phy_write = mt7531_ind_phy_write,
+- .pad_setup = mt7988_pad_setup,
+ .cpu_port_config = mt7988_cpu_port_config,
+ .mac_port_get_caps = mt7988_mac_port_get_caps,
+ .mac_port_config = mt7988_mac_config,
+@@ -3443,9 +3412,8 @@ mt7530_probe_common(struct mt7530_priv *
+ /* Sanity check if these required device operations are filled
+ * properly.
+ */
+- if (!priv->info->sw_setup || !priv->info->pad_setup ||
+- !priv->info->phy_read || !priv->info->phy_write ||
+- !priv->info->mac_port_get_caps ||
++ if (!priv->info->sw_setup || !priv->info->phy_read ||
++ !priv->info->phy_write || !priv->info->mac_port_get_caps ||
+ !priv->info->mac_port_config)
+ return -EINVAL;
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -732,8 +732,6 @@ struct mt753x_pcs {
+ * @sw_setup: Holding the handler to a device initialization
+ * @phy_read: Holding the way reading PHY port
+ * @phy_write: Holding the way writing PHY port
+- * @pad_setup: Holding the way setting up the bus pad for a certain
+- * MAC port
+ * @phy_mode_supported: Check if the PHY type is being supported on a certain
+ * port
+ * @mac_port_validate: Holding the way to set addition validate type for a
+@@ -749,7 +747,6 @@ struct mt753x_info {
+ int (*sw_setup)(struct dsa_switch *ds);
+ int (*phy_read)(struct mt7530_priv *priv, int port, int regnum);
+ int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
+- int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
+ int (*cpu_port_config)(struct dsa_switch *ds, int port);
+ void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
+ struct phylink_config *config);
--- /dev/null
+From 58a94eb63233bb2ede13b183b6a6a03aa0a2dfc3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:07 +0300
+Subject: [PATCH 35/48] net: dsa: mt7530: correct port capabilities of MT7988
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On the switch on the MT7988 SoC, as shown in Block Diagram 8.1.1.3 on page
+125 of "MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open
+Version) v0.1", there are only 4 PHYs. That's port 0 to 3. Set the case for
+ports which connect to switch PHYs to '0 ... 3'.
+
+Port 4 and 5 are not used at all in this design.
+
+Link: https://wiki.banana-pi.org/Banana_Pi_BPI-R4#Documents [1]
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-6-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2793,7 +2793,7 @@ static void mt7988_mac_port_get_caps(str
+
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+- case 0 ... 4:
++ case 0 ... 3:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ break;
--- /dev/null
+From 4440ce33074be6bd55d1a0c8b5f4b6d433ae2c74 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:08 +0300
+Subject: [PATCH 36/48] net: dsa: mt7530: do not clear
+ config->supported_interfaces
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There's no need to clear the config->supported_interfaces bitmap before
+reporting the supported interfaces as all bits in the bitmap will already
+be initialized to zero when the phylink_config structure is allocated. The
+"config" pointer points to &dp->phylink_config, and "dp" is allocated by
+dsa_port_touch() with kzalloc(), so all its fields are filled with zeroes.
+
+There's no code that would change the bitmap beforehand. Remove it.
+
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-7-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2789,8 +2789,6 @@ static void mt7531_mac_port_get_caps(str
+ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+ {
+- phy_interface_zero(config->supported_interfaces);
+-
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+ case 0 ... 3:
--- /dev/null
+From 2f507aaeb1a12044f2376a255c2afff1f7432b0b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:42:57 +0200
+Subject: [PATCH 37/48] net: dsa: mt7530: remove .mac_port_config for MT7988
+ and make it optional
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+For the switch on the MT7988 SoC, the mac_port_config member for ID_MT7988
+in mt753x_table is not needed as the interfaces of all MACs are already
+handled on mt7988_mac_port_get_caps().
+
+Therefore, remove the mac_port_config member from ID_MT7988 in
+mt753x_table. Before calling priv->info->mac_port_config(), if there's no
+mac_port_config member in mt753x_table, exit mt753x_mac_config()
+successfully.
+
+Remove calling priv->info->mac_port_config() from the sanity check as the
+sanity check requires a pointer to a mac_port_config function to be
+non-NULL. This will fail for MT7988 as mac_port_config won't be a member of
+its info table.
+
+Co-developed-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 18 ++++--------------
+ 1 file changed, 4 insertions(+), 14 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2872,17 +2872,6 @@ static bool mt753x_is_mac_port(u32 port)
+ }
+
+ static int
+-mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+- phy_interface_t interface)
+-{
+- if (dsa_is_cpu_port(ds, port) &&
+- interface == PHY_INTERFACE_MODE_INTERNAL)
+- return 0;
+-
+- return -EINVAL;
+-}
+-
+-static int
+ mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ phy_interface_t interface)
+ {
+@@ -2922,6 +2911,9 @@ mt753x_mac_config(struct dsa_switch *ds,
+ {
+ struct mt7530_priv *priv = ds->priv;
+
++ if (!priv->info->mac_port_config)
++ return 0;
++
+ return priv->info->mac_port_config(ds, port, mode, state->interface);
+ }
+
+@@ -3383,7 +3375,6 @@ const struct mt753x_info mt753x_table[]
+ .phy_write = mt7531_ind_phy_write,
+ .cpu_port_config = mt7988_cpu_port_config,
+ .mac_port_get_caps = mt7988_mac_port_get_caps,
+- .mac_port_config = mt7988_mac_config,
+ },
+ };
+ EXPORT_SYMBOL_GPL(mt753x_table);
+@@ -3411,8 +3402,7 @@ mt7530_probe_common(struct mt7530_priv *
+ * properly.
+ */
+ if (!priv->info->sw_setup || !priv->info->phy_read ||
+- !priv->info->phy_write || !priv->info->mac_port_get_caps ||
+- !priv->info->mac_port_config)
++ !priv->info->phy_write || !priv->info->mac_port_get_caps)
+ return -EINVAL;
+
+ priv->id = priv->info->id;
--- /dev/null
+From 0e297b1c662825f7dcd97272323c81f502987e0f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:42:58 +0200
+Subject: [PATCH 38/48] net: dsa: mt7530: set interrupt register only for
+ MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Setting this register related to interrupts is only needed for the MT7530
+switch. Make an exclusive check to ensure this.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2259,7 +2259,7 @@ mt7530_setup_irq(struct mt7530_priv *pri
+ }
+
+ /* This register must be set for MT7530 to properly fire interrupts */
+- if (priv->id != ID_MT7531)
++ if (priv->id == ID_MT7530 || priv->id == ID_MT7621)
+ mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
+
+ ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
--- /dev/null
+From 0eb6bc551371070325b6606cc3bed6734ecad87d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:42:59 +0200
+Subject: [PATCH 39/48] net: dsa: mt7530: do not use SW_PHY_RST to reset MT7531
+ switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+According to the document MT7531 Reference Manual for Development Board
+v1.0, the SW_PHY_RST bit on the SYS_CTRL register doesn't exist for
+MT7531. This is likely why forcing link down on all ports is necessary for
+MT7531.
+
+Therefore, do not set SW_PHY_RST on mt7531_setup().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2660,14 +2660,12 @@ mt7531_setup(struct dsa_switch *ds)
+ val = mt7530_read(priv, MT7531_TOP_SIG_SR);
+ priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
+
+- /* all MACs must be forced link-down before sw reset */
++ /* Force link down on all ports before internal reset */
+ for (i = 0; i < MT7530_NUM_PORTS; i++)
+ mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
+
+ /* Reset the switch through internal reset */
+- mt7530_write(priv, MT7530_SYS_CTRL,
+- SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
+- SYS_CTRL_REG_RST);
++ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
+
+ if (!priv->p5_sgmii) {
+ mt7531_pll_setup(priv);
--- /dev/null
+From bb20b1b4d832de4eb98ec7c22906db7c04e3f7c5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:00 +0200
+Subject: [PATCH 40/48] net: dsa: mt7530: get rid of useless error returns on
+ phylink code path
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Remove error returns on the cases where they are already handled with the
+function the mac_port_get_caps member in mt753x_table points to.
+
+mt7531_mac_config() is also called from mt7531_cpu_port_config() outside of
+phylink but the port and interface modes are already handled there.
+
+Change the functions and the mac_port_config function pointer to void now
+that there're no error returns anymore.
+
+Remove mt753x_is_mac_port() that used to help the said error returns.
+
+On mt7531_mac_config(), switch to if statements to simplify the code.
+
+Remove internal phy cases from mt753x_phylink_mac_config(), there is no
+need to check the interface mode as that's already handled with the
+function the mac_port_get_caps member in mt753x_table points to.
+
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 81 ++++++++--------------------------------
+ drivers/net/dsa/mt7530.h | 6 +--
+ 2 files changed, 19 insertions(+), 68 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2803,7 +2803,7 @@ static void mt7988_mac_port_get_caps(str
+ }
+ }
+
+-static int
++static void
+ mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ phy_interface_t interface)
+ {
+@@ -2813,22 +2813,14 @@ mt7530_mac_config(struct dsa_switch *ds,
+ mt7530_setup_port5(priv->ds, interface);
+ else if (port == 6)
+ mt7530_setup_port6(priv->ds, interface);
+-
+- return 0;
+ }
+
+-static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
+- phy_interface_t interface,
+- struct phy_device *phydev)
++static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
++ phy_interface_t interface,
++ struct phy_device *phydev)
+ {
+ u32 val;
+
+- if (priv->p5_sgmii) {
+- dev_err(priv->dev, "RGMII mode is not available for port %d\n",
+- port);
+- return -EINVAL;
+- }
+-
+ val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
+ val |= GP_CLK_EN;
+ val &= ~GP_MODE_MASK;
+@@ -2856,20 +2848,14 @@ static int mt7531_rgmii_setup(struct mt7
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ break;
+ default:
+- return -EINVAL;
++ break;
+ }
+ }
+- mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
+
+- return 0;
+-}
+-
+-static bool mt753x_is_mac_port(u32 port)
+-{
+- return (port == 5 || port == 6);
++ mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
+ }
+
+-static int
++static void
+ mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ phy_interface_t interface)
+ {
+@@ -2877,42 +2863,21 @@ mt7531_mac_config(struct dsa_switch *ds,
+ struct phy_device *phydev;
+ struct dsa_port *dp;
+
+- if (!mt753x_is_mac_port(port)) {
+- dev_err(priv->dev, "port %d is not a MAC port\n", port);
+- return -EINVAL;
+- }
+-
+- switch (interface) {
+- case PHY_INTERFACE_MODE_RGMII:
+- case PHY_INTERFACE_MODE_RGMII_ID:
+- case PHY_INTERFACE_MODE_RGMII_RXID:
+- case PHY_INTERFACE_MODE_RGMII_TXID:
++ if (phy_interface_mode_is_rgmii(interface)) {
+ dp = dsa_to_port(ds, port);
+ phydev = dp->slave->phydev;
+- return mt7531_rgmii_setup(priv, port, interface, phydev);
+- case PHY_INTERFACE_MODE_SGMII:
+- case PHY_INTERFACE_MODE_NA:
+- case PHY_INTERFACE_MODE_1000BASEX:
+- case PHY_INTERFACE_MODE_2500BASEX:
+- /* handled in SGMII PCS driver */
+- return 0;
+- default:
+- return -EINVAL;
++ mt7531_rgmii_setup(priv, port, interface, phydev);
+ }
+-
+- return -EINVAL;
+ }
+
+-static int
++static void
+ mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ const struct phylink_link_state *state)
+ {
+ struct mt7530_priv *priv = ds->priv;
+
+- if (!priv->info->mac_port_config)
+- return 0;
+-
+- return priv->info->mac_port_config(ds, port, mode, state->interface);
++ if (priv->info->mac_port_config)
++ priv->info->mac_port_config(ds, port, mode, state->interface);
+ }
+
+ static struct phylink_pcs *
+@@ -2941,17 +2906,11 @@ mt753x_phylink_mac_config(struct dsa_swi
+ u32 mcr_cur, mcr_new;
+
+ switch (port) {
+- case 0 ... 4:
+- if (state->interface != PHY_INTERFACE_MODE_GMII &&
+- state->interface != PHY_INTERFACE_MODE_INTERNAL)
+- goto unsupported;
+- break;
+ case 5:
+ if (priv->p5_interface == state->interface)
+ break;
+
+- if (mt753x_mac_config(ds, port, mode, state) < 0)
+- goto unsupported;
++ mt753x_mac_config(ds, port, mode, state);
+
+ if (priv->p5_intf_sel != P5_DISABLED)
+ priv->p5_interface = state->interface;
+@@ -2960,16 +2919,10 @@ mt753x_phylink_mac_config(struct dsa_swi
+ if (priv->p6_interface == state->interface)
+ break;
+
+- if (mt753x_mac_config(ds, port, mode, state) < 0)
+- goto unsupported;
++ mt753x_mac_config(ds, port, mode, state);
+
+ priv->p6_interface = state->interface;
+ break;
+- default:
+-unsupported:
+- dev_err(ds->dev, "%s: unsupported %s port: %i\n",
+- __func__, phy_modes(state->interface), port);
+- return;
+ }
+
+ mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
+@@ -3052,7 +3005,6 @@ mt7531_cpu_port_config(struct dsa_switch
+ struct mt7530_priv *priv = ds->priv;
+ phy_interface_t interface;
+ int speed;
+- int ret;
+
+ switch (port) {
+ case 5:
+@@ -3077,9 +3029,8 @@ mt7531_cpu_port_config(struct dsa_switch
+ else
+ speed = SPEED_1000;
+
+- ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
+- if (ret)
+- return ret;
++ mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
++
+ mt7530_write(priv, MT7530_PMCR_P(port),
+ PMCR_CPU_PORT_SETTING(priv->id));
+ mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -753,9 +753,9 @@ struct mt753x_info {
+ void (*mac_port_validate)(struct dsa_switch *ds, int port,
+ phy_interface_t interface,
+ unsigned long *supported);
+- int (*mac_port_config)(struct dsa_switch *ds, int port,
+- unsigned int mode,
+- phy_interface_t interface);
++ void (*mac_port_config)(struct dsa_switch *ds, int port,
++ unsigned int mode,
++ phy_interface_t interface);
+ };
+
+ /* struct mt7530_priv - This is the main data structure for holding the state
--- /dev/null
+From 8554f6a7914d28b179671540f527897d85c88809 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:01 +0200
+Subject: [PATCH 41/48] net: dsa: mt7530: get rid of
+ priv->info->cpu_port_config()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+priv->info->cpu_port_config() is used for MT7531 and the switch on the
+MT7988 SoC. It sets up the ports described as a CPU port earlier than the
+phylink code path would do.
+
+This function is useless as:
+- Configuring the MACs can be done from the phylink_mac_config code path
+ instead.
+- All the link configuration it does on the CPU ports are later undone with
+ the port_enable, phylink_mac_config, and then phylink_mac_link_up code
+ path [1].
+
+priv->p5_interface and priv->p6_interface were being used to prevent
+configuring the MACs from the phylink_mac_config code path. Remove them now
+that they hold no purpose.
+
+Remove priv->info->cpu_port_config(). On mt753x_phylink_mac_config, switch
+to if statements to simplify the code.
+
+Remove the overwriting of the speed and duplex interfaces for certain
+interface modes. Phylink already provides the speed and duplex variables
+with proper values. Phylink already sets the max speed of TRGMII to
+SPEED_1000. Add SPEED_2500 for PHY_INTERFACE_MODE_2500BASEX to where the
+speed and EEE bits are set instead.
+
+On the switch on the MT7988 SoC, PHY_INTERFACE_MODE_INTERNAL is being used
+to describe the interface mode of the 10G MAC, which is of port 6. On
+mt7988_cpu_port_config() PMCR_FORCE_SPEED_1000 was set via the
+PMCR_CPU_PORT_SETTING() mask. Add SPEED_10000 case to where the speed bits
+are set to cover this. No need to add it to where the EEE bits are set as
+the "MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open Version)
+v0.1" document shows that these bits don't exist on the MT7530_PMCR_P(6)
+register.
+
+Remove the definition of PMCR_CPU_PORT_SETTING() now that it holds no
+purpose.
+
+Change mt753x_cpu_port_enable() to void now that there're no error cases
+left.
+
+Link: https://lore.kernel.org/netdev/ZHy2jQLesdYFMQtO@shell.armlinux.org.uk/ [1]
+Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 114 +++------------------------------------
+ drivers/net/dsa/mt7530.h | 11 ----
+ 2 files changed, 7 insertions(+), 118 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1170,18 +1170,10 @@ mt753x_trap_frames(struct mt7530_priv *p
+ MT753X_BPDU_CPU_ONLY);
+ }
+
+-static int
++static void
+ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- int ret;
+-
+- /* Setup max capability of CPU port at first */
+- if (priv->info->cpu_port_config) {
+- ret = priv->info->cpu_port_config(ds, port);
+- if (ret)
+- return ret;
+- }
+
+ /* Enable Mediatek header mode on the cpu port */
+ mt7530_write(priv, MT7530_PVC_P(port),
+@@ -1207,8 +1199,6 @@ mt753x_cpu_port_enable(struct dsa_switch
+ /* Set to fallback mode for independent VLAN learning */
+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
+ MT7530_PORT_FALLBACK_MODE);
+-
+- return 0;
+ }
+
+ static int
+@@ -2461,8 +2451,6 @@ mt7530_setup(struct dsa_switch *ds)
+ val |= MHWTRAP_MANUAL;
+ mt7530_write(priv, MT7530_MHWTRAP, val);
+
+- priv->p6_interface = PHY_INTERFACE_MODE_NA;
+-
+ if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+
+@@ -2480,9 +2468,7 @@ mt7530_setup(struct dsa_switch *ds)
+ mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
+
+ if (dsa_is_cpu_port(ds, i)) {
+- ret = mt753x_cpu_port_enable(ds, i);
+- if (ret)
+- return ret;
++ mt753x_cpu_port_enable(ds, i);
+ } else {
+ mt7530_port_disable(ds, i);
+
+@@ -2589,9 +2575,7 @@ mt7531_setup_common(struct dsa_switch *d
+ mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
+
+ if (dsa_is_cpu_port(ds, i)) {
+- ret = mt753x_cpu_port_enable(ds, i);
+- if (ret)
+- return ret;
++ mt753x_cpu_port_enable(ds, i);
+ } else {
+ mt7530_port_disable(ds, i);
+
+@@ -2683,10 +2667,6 @@ mt7531_setup(struct dsa_switch *ds)
+ mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
+ MT7531_GPIO0_INTERRUPT);
+
+- /* Let phylink decide the interface later. */
+- priv->p5_interface = PHY_INTERFACE_MODE_NA;
+- priv->p6_interface = PHY_INTERFACE_MODE_NA;
+-
+ /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
+ * phy_device has not yet been created provided for
+ * phy_[read,write]_mmd_indirect is called, we provide our own
+@@ -2905,26 +2885,9 @@ mt753x_phylink_mac_config(struct dsa_swi
+ struct mt7530_priv *priv = ds->priv;
+ u32 mcr_cur, mcr_new;
+
+- switch (port) {
+- case 5:
+- if (priv->p5_interface == state->interface)
+- break;
+-
++ if (port == 5 || port == 6)
+ mt753x_mac_config(ds, port, mode, state);
+
+- if (priv->p5_intf_sel != P5_DISABLED)
+- priv->p5_interface = state->interface;
+- break;
+- case 6:
+- if (priv->p6_interface == state->interface)
+- break;
+-
+- mt753x_mac_config(ds, port, mode, state);
+-
+- priv->p6_interface = state->interface;
+- break;
+- }
+-
+ mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
+ mcr_new = mcr_cur;
+ mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
+@@ -2960,17 +2923,10 @@ static void mt753x_phylink_mac_link_up(s
+
+ mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
+
+- /* MT753x MAC works in 1G full duplex mode for all up-clocked
+- * variants.
+- */
+- if (interface == PHY_INTERFACE_MODE_TRGMII ||
+- (phy_interface_mode_is_8023z(interface))) {
+- speed = SPEED_1000;
+- duplex = DUPLEX_FULL;
+- }
+-
+ switch (speed) {
+ case SPEED_1000:
++ case SPEED_2500:
++ case SPEED_10000:
+ mcr |= PMCR_FORCE_SPEED_1000;
+ break;
+ case SPEED_100:
+@@ -2988,6 +2944,7 @@ static void mt753x_phylink_mac_link_up(s
+ if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
+ switch (speed) {
+ case SPEED_1000:
++ case SPEED_2500:
+ mcr |= PMCR_FORCE_EEE1G;
+ break;
+ case SPEED_100:
+@@ -2999,61 +2956,6 @@ static void mt753x_phylink_mac_link_up(s
+ mt7530_set(priv, MT7530_PMCR_P(port), mcr);
+ }
+
+-static int
+-mt7531_cpu_port_config(struct dsa_switch *ds, int port)
+-{
+- struct mt7530_priv *priv = ds->priv;
+- phy_interface_t interface;
+- int speed;
+-
+- switch (port) {
+- case 5:
+- if (!priv->p5_sgmii)
+- interface = PHY_INTERFACE_MODE_RGMII;
+- else
+- interface = PHY_INTERFACE_MODE_2500BASEX;
+-
+- priv->p5_interface = interface;
+- break;
+- case 6:
+- interface = PHY_INTERFACE_MODE_2500BASEX;
+-
+- priv->p6_interface = interface;
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- if (interface == PHY_INTERFACE_MODE_2500BASEX)
+- speed = SPEED_2500;
+- else
+- speed = SPEED_1000;
+-
+- mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
+-
+- mt7530_write(priv, MT7530_PMCR_P(port),
+- PMCR_CPU_PORT_SETTING(priv->id));
+- mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
+- speed, DUPLEX_FULL, true, true);
+-
+- return 0;
+-}
+-
+-static int
+-mt7988_cpu_port_config(struct dsa_switch *ds, int port)
+-{
+- struct mt7530_priv *priv = ds->priv;
+-
+- mt7530_write(priv, MT7530_PMCR_P(port),
+- PMCR_CPU_PORT_SETTING(priv->id));
+-
+- mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED,
+- PHY_INTERFACE_MODE_INTERNAL, NULL,
+- SPEED_10000, DUPLEX_FULL, true, true);
+-
+- return 0;
+-}
+-
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+ {
+@@ -3312,7 +3214,6 @@ const struct mt753x_info mt753x_table[]
+ .sw_setup = mt7531_setup,
+ .phy_read = mt7531_ind_phy_read,
+ .phy_write = mt7531_ind_phy_write,
+- .cpu_port_config = mt7531_cpu_port_config,
+ .mac_port_get_caps = mt7531_mac_port_get_caps,
+ .mac_port_config = mt7531_mac_config,
+ },
+@@ -3322,7 +3223,6 @@ const struct mt753x_info mt753x_table[]
+ .sw_setup = mt7988_setup,
+ .phy_read = mt7531_ind_phy_read,
+ .phy_write = mt7531_ind_phy_write,
+- .cpu_port_config = mt7988_cpu_port_config,
+ .mac_port_get_caps = mt7988_mac_port_get_caps,
+ },
+ };
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -340,13 +340,6 @@ enum mt7530_vlan_port_acc_frm {
+ PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
+ PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
+ PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
+-#define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
+- PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
+- PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
+- PMCR_TX_EN | PMCR_RX_EN | \
+- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
+- PMCR_FORCE_SPEED_1000 | \
+- PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+
+ #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
+ #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
+@@ -747,7 +740,6 @@ struct mt753x_info {
+ int (*sw_setup)(struct dsa_switch *ds);
+ int (*phy_read)(struct mt7530_priv *priv, int port, int regnum);
+ int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
+- int (*cpu_port_config)(struct dsa_switch *ds, int port);
+ void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
+ struct phylink_config *config);
+ void (*mac_port_validate)(struct dsa_switch *ds, int port,
+@@ -773,7 +765,6 @@ struct mt753x_info {
+ * @ports: Holding the state among ports
+ * @reg_mutex: The lock for protecting among process accessing
+ * registers
+- * @p6_interface Holding the current port 6 interface
+ * @p5_intf_sel: Holding the current port 5 interface select
+ * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
+ * has got SGMII
+@@ -795,8 +786,6 @@ struct mt7530_priv {
+ const struct mt753x_info *info;
+ unsigned int id;
+ bool mcm;
+- phy_interface_t p6_interface;
+- phy_interface_t p5_interface;
+ enum p5_interface_select p5_intf_sel;
+ bool p5_sgmii;
+ u8 mirror_rx;
--- /dev/null
+From 0c282205ef8c6dd6d2c145fac1fb6aba3e65c02d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:02 +0200
+Subject: [PATCH 42/48] net: dsa: mt7530: get rid of mt753x_mac_config()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There is no need for a separate function to call
+priv->info->mac_port_config(). Call it from mt753x_phylink_mac_config()
+instead and remove mt753x_mac_config().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 14 ++------------
+ 1 file changed, 2 insertions(+), 12 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2850,16 +2850,6 @@ mt7531_mac_config(struct dsa_switch *ds,
+ }
+ }
+
+-static void
+-mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+- const struct phylink_link_state *state)
+-{
+- struct mt7530_priv *priv = ds->priv;
+-
+- if (priv->info->mac_port_config)
+- priv->info->mac_port_config(ds, port, mode, state->interface);
+-}
+-
+ static struct phylink_pcs *
+ mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
+ phy_interface_t interface)
+@@ -2885,8 +2875,8 @@ mt753x_phylink_mac_config(struct dsa_swi
+ struct mt7530_priv *priv = ds->priv;
+ u32 mcr_cur, mcr_new;
+
+- if (port == 5 || port == 6)
+- mt753x_mac_config(ds, port, mode, state);
++ if ((port == 5 || port == 6) && priv->info->mac_port_config)
++ priv->info->mac_port_config(ds, port, mode, state->interface);
+
+ mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
+ mcr_new = mcr_cur;
--- /dev/null
+From d55c300aa1fe240aa3eba18550ba6c4e2c4bd157 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:03 +0200
+Subject: [PATCH 43/48] net: dsa: mt7530: put initialising PCS devices code
+ back to original order
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The commit fae463084032 ("net: dsa: mt753x: fix pcs conversion regression")
+fixes regression caused by cpu_port_config manually calling phylink
+operations. cpu_port_config was deemed useless and was removed. Therefore,
+put initialising PCS devices code back to its original order.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3034,17 +3034,9 @@ static int
+ mt753x_setup(struct dsa_switch *ds)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- int i, ret;
++ int ret = priv->info->sw_setup(ds);
++ int i;
+
+- /* Initialise the PCS devices */
+- for (i = 0; i < priv->ds->num_ports; i++) {
+- priv->pcs[i].pcs.ops = priv->info->pcs_ops;
+- priv->pcs[i].pcs.neg_mode = true;
+- priv->pcs[i].priv = priv;
+- priv->pcs[i].port = i;
+- }
+-
+- ret = priv->info->sw_setup(ds);
+ if (ret)
+ return ret;
+
+@@ -3056,6 +3048,14 @@ mt753x_setup(struct dsa_switch *ds)
+ if (ret && priv->irq)
+ mt7530_free_irq_common(priv);
+
++ /* Initialise the PCS devices */
++ for (i = 0; i < priv->ds->num_ports; i++) {
++ priv->pcs[i].pcs.ops = priv->info->pcs_ops;
++ priv->pcs[i].pcs.neg_mode = true;
++ priv->pcs[i].priv = priv;
++ priv->pcs[i].port = i;
++ }
++
+ if (priv->create_sgmii) {
+ ret = priv->create_sgmii(priv);
+ if (ret && priv->irq)
--- /dev/null
+From a9544caa482a7ed215117a902f04185216997831 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:04 +0200
+Subject: [PATCH 44/48] net: dsa: mt7530: sort link settings ops and force link
+ down on all ports
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+port_enable and port_disable clears the link settings. Move that to
+mt7530_setup() and mt7531_setup_common() which set up the switches. This
+way, the link settings are cleared on all ports at setup, and then only
+once with phylink_mac_link_down() when a link goes down.
+
+Enable force mode at setup to apply the force part of the link settings.
+This ensures that disabled ports will have their link down.
+
+Suggested-by: Vladimir Oltean <olteanv@gmail.com>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1222,7 +1222,6 @@ mt7530_port_enable(struct dsa_switch *ds
+ priv->ports[port].enable = true;
+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
+ priv->ports[port].pm);
+- mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
+
+ mutex_unlock(&priv->reg_mutex);
+
+@@ -1242,7 +1241,6 @@ mt7530_port_disable(struct dsa_switch *d
+ priv->ports[port].enable = false;
+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
+ PCR_MATRIX_CLR);
+- mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
+
+ mutex_unlock(&priv->reg_mutex);
+ }
+@@ -2460,6 +2458,12 @@ mt7530_setup(struct dsa_switch *ds)
+ mt7530_mib_reset(ds);
+
+ for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ /* Clear link settings and enable force mode to force link down
++ * on all ports until they're enabled later.
++ */
++ mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ PMCR_FORCE_MODE, PMCR_FORCE_MODE);
++
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+ PCR_MATRIX_CLR);
+@@ -2565,6 +2569,12 @@ mt7531_setup_common(struct dsa_switch *d
+ UNU_FFP_MASK);
+
+ for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ /* Clear link settings and enable force mode to force link down
++ * on all ports until they're enabled later.
++ */
++ mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7531_FORCE_MODE, MT7531_FORCE_MODE);
++
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+ PCR_MATRIX_CLR);
--- /dev/null
+From 89017cac5f6fbaab23955818c31b3c7f1eb26f4a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:05 +0200
+Subject: [PATCH 45/48] net: dsa: mt7530: simplify link operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The "MT7621 Giga Switch Programming Guide v0.3", "MT7531 Reference Manual
+for Development Board v1.0", and "MT7988A Wi-Fi 7 Generation Router
+Platform: Datasheet (Open Version) v0.1" documents show that these bits are
+enabled at reset:
+
+PMCR_IFG_XMIT(1) (not part of PMCR_LINK_SETTINGS_MASK)
+PMCR_MAC_MODE (not part of PMCR_LINK_SETTINGS_MASK)
+PMCR_TX_EN
+PMCR_RX_EN
+PMCR_BACKOFF_EN (not part of PMCR_LINK_SETTINGS_MASK)
+PMCR_BACKPR_EN (not part of PMCR_LINK_SETTINGS_MASK)
+PMCR_TX_FC_EN
+PMCR_RX_FC_EN
+
+These bits also don't exist on the MT7530_PMCR_P(6) register of the switch
+on the MT7988 SoC:
+
+PMCR_IFG_XMIT()
+PMCR_MAC_MODE
+PMCR_BACKOFF_EN
+PMCR_BACKPR_EN
+
+Remove the setting of the bits not part of PMCR_LINK_SETTINGS_MASK on
+phylink_mac_config as they're already set.
+
+The bit for setting the port on force mode is already done on
+mt7530_setup() and mt7531_setup_common(). So get rid of
+PMCR_FORCE_MODE_ID() which helped determine which bit to use for the switch
+model.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 12 +-----------
+ drivers/net/dsa/mt7530.h | 2 --
+ 2 files changed, 1 insertion(+), 13 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2883,23 +2883,13 @@ mt753x_phylink_mac_config(struct dsa_swi
+ const struct phylink_link_state *state)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- u32 mcr_cur, mcr_new;
+
+ if ((port == 5 || port == 6) && priv->info->mac_port_config)
+ priv->info->mac_port_config(ds, port, mode, state->interface);
+
+- mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
+- mcr_new = mcr_cur;
+- mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
+- mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
+- PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
+-
+ /* Are we connected to external phy */
+ if (port == 5 && dsa_is_user_port(ds, 5))
+- mcr_new |= PMCR_EXT_PHY;
+-
+- if (mcr_new != mcr_cur)
+- mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
++ mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
+ }
+
+ static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -333,8 +333,6 @@ enum mt7530_vlan_port_acc_frm {
+ MT7531_FORCE_DPX | \
+ MT7531_FORCE_RX_FC | \
+ MT7531_FORCE_TX_FC)
+-#define PMCR_FORCE_MODE_ID(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_FORCE_MODE : PMCR_FORCE_MODE)
+ #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+ PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+ PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
--- /dev/null
+From 5754b3bdcd872aa229881b8f07f84a8404c7d72a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 12 Apr 2024 16:15:34 +0100
+Subject: [PATCH 1/5] net: dsa: mt7530: provide own phylink MAC operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Convert mt753x to provide its own phylink MAC operations, thus avoiding
+the shim layer in DSA's port.c
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/E1rvIco-006bQu-Fq@rmk-PC.armlinux.org.uk
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 46 +++++++++++++++++++++++++---------------
+ 1 file changed, 29 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2861,28 +2861,34 @@ mt7531_mac_config(struct dsa_switch *ds,
+ }
+
+ static struct phylink_pcs *
+-mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
++mt753x_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_TRGMII:
+- return &priv->pcs[port].pcs;
++ return &priv->pcs[dp->index].pcs;
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+- return priv->ports[port].sgmii_pcs;
++ return priv->ports[dp->index].sgmii_pcs;
+ default:
+ return NULL;
+ }
+ }
+
+ static void
+-mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
++mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode,
+ const struct phylink_link_state *state)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct dsa_switch *ds = dp->ds;
++ struct mt7530_priv *priv;
++ int port = dp->index;
++
++ priv = ds->priv;
+
+ if ((port == 5 || port == 6) && priv->info->mac_port_config)
+ priv->info->mac_port_config(ds, port, mode, state->interface);
+@@ -2892,23 +2898,25 @@ mt753x_phylink_mac_config(struct dsa_swi
+ mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
+ }
+
+-static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
++static void mt753x_phylink_mac_link_down(struct phylink_config *config,
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+
+- mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
++ mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ }
+
+-static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
++static void mt753x_phylink_mac_link_up(struct phylink_config *config,
++ struct phy_device *phydev,
+ unsigned int mode,
+ phy_interface_t interface,
+- struct phy_device *phydev,
+ int speed, int duplex,
+ bool tx_pause, bool rx_pause)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+ u32 mcr;
+
+ mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
+@@ -2943,7 +2951,7 @@ static void mt753x_phylink_mac_link_up(s
+ }
+ }
+
+- mt7530_set(priv, MT7530_PMCR_P(port), mcr);
++ mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
+ }
+
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+@@ -3169,16 +3177,19 @@ const struct dsa_switch_ops mt7530_switc
+ .port_mirror_add = mt753x_port_mirror_add,
+ .port_mirror_del = mt753x_port_mirror_del,
+ .phylink_get_caps = mt753x_phylink_get_caps,
+- .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs,
+- .phylink_mac_config = mt753x_phylink_mac_config,
+- .phylink_mac_link_down = mt753x_phylink_mac_link_down,
+- .phylink_mac_link_up = mt753x_phylink_mac_link_up,
+ .get_mac_eee = mt753x_get_mac_eee,
+ .set_mac_eee = mt753x_set_mac_eee,
+ .master_state_change = mt753x_conduit_state_change,
+ };
+ EXPORT_SYMBOL_GPL(mt7530_switch_ops);
+
++static const struct phylink_mac_ops mt753x_phylink_mac_ops = {
++ .mac_select_pcs = mt753x_phylink_mac_select_pcs,
++ .mac_config = mt753x_phylink_mac_config,
++ .mac_link_down = mt753x_phylink_mac_link_down,
++ .mac_link_up = mt753x_phylink_mac_link_up,
++};
++
+ const struct mt753x_info mt753x_table[] = {
+ [ID_MT7621] = {
+ .id = ID_MT7621,
+@@ -3248,6 +3259,7 @@ mt7530_probe_common(struct mt7530_priv *
+ priv->dev = dev;
+ priv->ds->priv = priv;
+ priv->ds->ops = &mt7530_switch_ops;
++ priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops;
+ mutex_init(&priv->reg_mutex);
+ dev_set_drvdata(dev, priv);
+
--- /dev/null
+From 019a17a5e76940ea86114838d1d638d4dc8d3750 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Sat, 13 Apr 2024 16:01:40 +0300
+Subject: [PATCH 3/5] net: dsa: mt7530: fix port mirroring for MT7988 SoC
+ switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The "MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open Version)
+v0.1" document shows bits 16 to 18 as the MIRROR_PORT field of the CPU
+forward control register. Currently, the MT7530 DSA subdriver configures
+bits 0 to 2 of the CPU forward control register which breaks the port
+mirroring feature for the MT7988 SoC switch.
+
+Fix this by using the MT7531_MIRROR_PORT_GET() and MT7531_MIRROR_PORT_SET()
+macros which utilise the correct bits.
+
+Fixes: 110c18bfed41 ("net: dsa: mt7530: introduce driver for MT7988 built-in switch")
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1890,14 +1890,16 @@ mt7530_port_vlan_del(struct dsa_switch *
+
+ static int mt753x_mirror_port_get(unsigned int id, u32 val)
+ {
+- return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
+- MIRROR_PORT(val);
++ return (id == ID_MT7531 || id == ID_MT7988) ?
++ MT7531_MIRROR_PORT_GET(val) :
++ MIRROR_PORT(val);
+ }
+
+ static int mt753x_mirror_port_set(unsigned int id, u32 val)
+ {
+- return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
+- MIRROR_PORT(val);
++ return (id == ID_MT7531 || id == ID_MT7988) ?
++ MT7531_MIRROR_PORT_SET(val) :
++ MIRROR_PORT(val);
+ }
+
+ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
--- /dev/null
+From 5053a6cf1d50d785078562470d2a63695a9f3bf2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Thu, 18 Apr 2024 08:35:30 +0300
+Subject: [PATCH 4/5] net: dsa: mt7530-mdio: read PHY address of switch from
+ device tree
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Read the PHY address the switch listens on from the reg property of the
+switch node on the device tree. This change brings support for MT7530
+switches on boards with such bootstrapping configuration where the switch
+listens on a different PHY address than the hardcoded PHY address on the
+driver, 31.
+
+As described on the "MT7621 Programming Guide v0.4" document, the MT7530
+switch and its PHYs can be configured to listen on the range of 7-12,
+15-20, 23-28, and 31 and 0-4 PHY addresses.
+
+There are operations where the switch PHY registers are used. For the PHY
+address of the control PHY, transform the MT753X_CTRL_PHY_ADDR constant
+into a macro and use it. The PHY address for the control PHY is 0 when the
+switch listens on 31. In any other case, it is one greater than the PHY
+address the switch listens on.
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530-mdio.c | 28 +++++++++++++-------------
+ drivers/net/dsa/mt7530.c | 37 +++++++++++++++++++++++------------
+ drivers/net/dsa/mt7530.h | 4 +++-
+ 3 files changed, 41 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/dsa/mt7530-mdio.c
++++ b/drivers/net/dsa/mt7530-mdio.c
+@@ -18,7 +18,8 @@
+ static int
+ mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
+ {
+- struct mii_bus *bus = context;
++ struct mt7530_priv *priv = context;
++ struct mii_bus *bus = priv->bus;
+ u16 page, r, lo, hi;
+ int ret;
+
+@@ -27,36 +28,35 @@ mt7530_regmap_write(void *context, unsig
+ lo = val & 0xffff;
+ hi = val >> 16;
+
+- /* MT7530 uses 31 as the pseudo port */
+- ret = bus->write(bus, 0x1f, 0x1f, page);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x1f, page);
+ if (ret < 0)
+ return ret;
+
+- ret = bus->write(bus, 0x1f, r, lo);
++ ret = bus->write(bus, priv->mdiodev->addr, r, lo);
+ if (ret < 0)
+ return ret;
+
+- ret = bus->write(bus, 0x1f, 0x10, hi);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x10, hi);
+ return ret;
+ }
+
+ static int
+ mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
+ {
+- struct mii_bus *bus = context;
++ struct mt7530_priv *priv = context;
++ struct mii_bus *bus = priv->bus;
+ u16 page, r, lo, hi;
+ int ret;
+
+ page = (reg >> 6) & 0x3ff;
+ r = (reg >> 2) & 0xf;
+
+- /* MT7530 uses 31 as the pseudo port */
+- ret = bus->write(bus, 0x1f, 0x1f, page);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x1f, page);
+ if (ret < 0)
+ return ret;
+
+- lo = bus->read(bus, 0x1f, r);
+- hi = bus->read(bus, 0x1f, 0x10);
++ lo = bus->read(bus, priv->mdiodev->addr, r);
++ hi = bus->read(bus, priv->mdiodev->addr, 0x10);
+
+ *val = (hi << 16) | (lo & 0xffff);
+
+@@ -107,8 +107,7 @@ mt7531_create_sgmii(struct mt7530_priv *
+ mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
+ mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
+
+- regmap = devm_regmap_init(priv->dev,
+- &mt7530_regmap_bus, priv->bus,
++ regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, priv,
+ mt7531_pcs_config[i]);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+@@ -153,6 +152,7 @@ mt7530_probe(struct mdio_device *mdiodev
+
+ priv->bus = mdiodev->bus;
+ priv->dev = &mdiodev->dev;
++ priv->mdiodev = mdiodev;
+
+ ret = mt7530_probe_common(priv);
+ if (ret)
+@@ -203,8 +203,8 @@ mt7530_probe(struct mdio_device *mdiodev
+ regmap_config->reg_stride = 4;
+ regmap_config->max_register = MT7530_CREV;
+ regmap_config->disable_locking = true;
+- priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
+- priv->bus, regmap_config);
++ priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, priv,
++ regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -86,22 +86,26 @@ core_read_mmd_indirect(struct mt7530_pri
+ int value, ret;
+
+ /* Write the desired MMD Devad */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+- ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, prtad);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+ /* Read the content of the MMD's selected register */
+- value = bus->read(bus, 0, MII_MMD_DATA);
++ value = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA);
+
+ return value;
+ err:
+@@ -118,22 +122,26 @@ core_write_mmd_indirect(struct mt7530_pr
+ int ret;
+
+ /* Write the desired MMD Devad */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+- ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, prtad);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+ /* Write the data into MMD's selected register */
+- ret = bus->write(bus, 0, MII_MMD_DATA, data);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, data);
+ err:
+ if (ret < 0)
+ dev_err(&bus->dev,
+@@ -2684,16 +2692,19 @@ mt7531_setup(struct dsa_switch *ds)
+ * phy_[read,write]_mmd_indirect is called, we provide our own
+ * mt7531_ind_mmd_phy_[read,write] to complete this function.
+ */
+- val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
++ val = mt7531_ind_c45_phy_read(priv,
++ MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+ MDIO_MMD_VEND2, CORE_PLL_GROUP4);
+ val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
+ val &= ~MT7531_PHY_PLL_OFF;
+- mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
+- CORE_PLL_GROUP4, val);
++ mt7531_ind_c45_phy_write(priv,
++ MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MDIO_MMD_VEND2, CORE_PLL_GROUP4, val);
+
+ /* Disable EEE advertisement on the switch PHYs. */
+- for (i = MT753X_CTRL_PHY_ADDR;
+- i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
++ for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr);
++ i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS;
++ i++) {
+ mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
+ 0);
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -629,7 +629,7 @@ enum mt7531_clk_skew {
+ #define MT7531_PHY_PLL_OFF BIT(5)
+ #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
+
+-#define MT753X_CTRL_PHY_ADDR 0
++#define MT753X_CTRL_PHY_ADDR(addr) ((addr + 1) & 0x1f)
+
+ #define CORE_PLL_GROUP5 0x404
+ #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
+@@ -771,6 +771,7 @@ struct mt753x_info {
+ * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
+ * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
+ * @active_cpu_ports: Holding the active CPU ports
++ * @mdiodev: The pointer to the MDIO device structure
+ */
+ struct mt7530_priv {
+ struct device *dev;
+@@ -797,6 +798,7 @@ struct mt7530_priv {
+ u32 irq_enable;
+ int (*create_sgmii)(struct mt7530_priv *priv);
+ u8 active_cpu_ports;
++ struct mdio_device *mdiodev;
+ };
+
+ struct mt7530_hw_vlan_entry {
--- /dev/null
+From 9764a08b3d260f4e7799d34bbfe64463db940d74 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Thu, 18 Apr 2024 08:35:31 +0300
+Subject: [PATCH 5/5] net: dsa: mt7530: simplify core operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The core_rmw() function calls core_read_mmd_indirect() to read the
+requested register, and then calls core_write_mmd_indirect() to write the
+requested value to the register. Because Clause 22 is used to access Clause
+45 registers, some operations on core_write_mmd_indirect() are
+unnecessarily run. Get rid of core_read_mmd_indirect() and
+core_write_mmd_indirect(), and run only the necessary operations on
+core_write() and core_rmw().
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 108 ++++++++++++++++-----------------------
+ 1 file changed, 43 insertions(+), 65 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -74,116 +74,94 @@ static const struct mt7530_mib_desc mt75
+ MIB_DESC(1, 0xb8, "RxArlDrop"),
+ };
+
+-/* Since phy_device has not yet been created and
+- * phy_{read,write}_mmd_indirect is not available, we provide our own
+- * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
+- * to complete this function.
+- */
+-static int
+-core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
++static void
++mt7530_mutex_lock(struct mt7530_priv *priv)
++{
++ if (priv->bus)
++ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++}
++
++static void
++mt7530_mutex_unlock(struct mt7530_priv *priv)
++{
++ if (priv->bus)
++ mutex_unlock(&priv->bus->mdio_lock);
++}
++
++static void
++core_write(struct mt7530_priv *priv, u32 reg, u32 val)
+ {
+ struct mii_bus *bus = priv->bus;
+- int value, ret;
++ int ret;
++
++ mt7530_mutex_lock(priv);
+
+ /* Write the desired MMD Devad */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad);
++ MII_MMD_CTRL, MDIO_MMD_VEND2);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, prtad);
++ MII_MMD_DATA, reg);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
++ MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+- /* Read the content of the MMD's selected register */
+- value = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA);
+-
+- return value;
++ /* Write the data into MMD's selected register */
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, val);
+ err:
+- dev_err(&bus->dev, "failed to read mmd register\n");
++ if (ret < 0)
++ dev_err(&bus->dev, "failed to write mmd register\n");
+
+- return ret;
++ mt7530_mutex_unlock(priv);
+ }
+
+-static int
+-core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
+- int devad, u32 data)
++static void
++core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
+ {
+ struct mii_bus *bus = priv->bus;
++ u32 val;
+ int ret;
+
++ mt7530_mutex_lock(priv);
++
+ /* Write the desired MMD Devad */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad);
++ MII_MMD_CTRL, MDIO_MMD_VEND2);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, prtad);
++ MII_MMD_DATA, reg);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
++ MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
++ /* Read the content of the MMD's selected register */
++ val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA);
++ val &= ~mask;
++ val |= set;
+ /* Write the data into MMD's selected register */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, data);
++ MII_MMD_DATA, val);
+ err:
+ if (ret < 0)
+- dev_err(&bus->dev,
+- "failed to write mmd register\n");
+- return ret;
+-}
+-
+-static void
+-mt7530_mutex_lock(struct mt7530_priv *priv)
+-{
+- if (priv->bus)
+- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+-}
+-
+-static void
+-mt7530_mutex_unlock(struct mt7530_priv *priv)
+-{
+- if (priv->bus)
+- mutex_unlock(&priv->bus->mdio_lock);
+-}
+-
+-static void
+-core_write(struct mt7530_priv *priv, u32 reg, u32 val)
+-{
+- mt7530_mutex_lock(priv);
+-
+- core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
+-
+- mt7530_mutex_unlock(priv);
+-}
+-
+-static void
+-core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
+-{
+- u32 val;
+-
+- mt7530_mutex_lock(priv);
+-
+- val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
+- val &= ~mask;
+- val |= set;
+- core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
++ dev_err(&bus->dev, "failed to write mmd register\n");
+
+ mt7530_mutex_unlock(priv);
+ }
--- /dev/null
+From 856e8954a0a88d1a4d2b43e9002b9249131a156f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:08 +0300
+Subject: [PATCH 01/15] net: dsa: mt7530: disable EEE abilities on failure on
+ MT7531 and MT7988
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 bits let the
+PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits determine the 1G/100 EEE
+abilities of the MAC. If MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 are
+unset, the abilities are left to be determined by PHY auto polling.
+
+The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
+made it so that the PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits are set on
+mt753x_phylink_mac_link_up(). But it did not set the MT7531_FORCE_EEE1G and
+MT7531_FORCE_EEE100 bits. Because of this, the EEE abilities will be
+determined by PHY auto polling, regardless of the result of phy_init_eee().
+
+Define these bits and add them to the MT7531_FORCE_MODE mask which is set
+in mt7531_setup_common(). With this, there won't be any EEE abilities set
+when phy_init_eee() returns a negative value.
+
+Thanks to Russell for explaining when phy_init_eee() could return a
+negative value below.
+
+Looking at phy_init_eee(), it could return a negative value when:
+
+1. phydev->drv is NULL
+2. if genphy_c45_eee_is_active() returns negative
+3. if genphy_c45_eee_is_active() returns zero, it returns -EPROTONOSUPPORT
+4. if phy_set_bits_mmd() fails (e.g. communication error with the PHY)
+
+If we then look at genphy_c45_eee_is_active(), then:
+
+genphy_c45_read_eee_adv() and genphy_c45_read_eee_lpa() propagate their
+non-zero return values, otherwise this function returns zero or positive
+integer.
+
+If we then look at genphy_c45_read_eee_adv(), then a failure of
+phy_read_mmd() would cause a negative value to be returned.
+
+Looking at genphy_c45_read_eee_lpa(), the same is true.
+
+So, it can be summarised as:
+
+- phydev->drv is NULL
+- there is a communication error accessing the PHY
+- EEE is not active
+
+otherwise, it returns zero on success.
+
+If one wishes to determine whether an error occurred vs EEE not being
+supported through negotiation for the negotiated speed, if it returns
+-EPROTONOSUPPORT in the latter case. Other error codes mean either the
+driver has been unloaded or communication error.
+
+In conclusion, determining the EEE abilities by PHY auto polling shouldn't
+result in having any EEE abilities enabled, when one of the last two
+situations in the summary happens. And it seems that if phydev->drv is
+NULL, there would be bigger problems with the device than a broken link. So
+this is not a bugfix.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.h | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -328,11 +328,15 @@ enum mt7530_vlan_port_acc_frm {
+ #define MT7531_FORCE_DPX BIT(29)
+ #define MT7531_FORCE_RX_FC BIT(28)
+ #define MT7531_FORCE_TX_FC BIT(27)
++#define MT7531_FORCE_EEE100 BIT(26)
++#define MT7531_FORCE_EEE1G BIT(25)
+ #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
+ MT7531_FORCE_SPD | \
+ MT7531_FORCE_DPX | \
+ MT7531_FORCE_RX_FC | \
+- MT7531_FORCE_TX_FC)
++ MT7531_FORCE_TX_FC | \
++ MT7531_FORCE_EEE100 | \
++ MT7531_FORCE_EEE1G)
+ #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+ PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+ PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
--- /dev/null
+From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:09 +0300
+Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the
+MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is
+for MT7530 only. Add MT7530 prefix to the definition for bit 15.
+
+Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT().
+
+Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to
+follow the naming on the "MT7621 Giga Switch Programming Guide v0.3",
+"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7
+Generation Router Platform: Datasheet (Open Version) v0.1" documents.
+
+These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along
+with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN.
+
+Remove PMCR_SPEED_MASK which doesn't have a use.
+
+Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the
+end for the mask that includes all force mode definitions.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 24 ++++++++---------
+ drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++-------------------
+ 2 files changed, 42 insertions(+), 40 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -903,7 +903,7 @@ static void mt7530_setup_port5(struct ds
+ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+- mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
++ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+ case P5_INTF_SEL_GMAC5:
+ /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+@@ -2449,8 +2449,8 @@ mt7530_setup(struct dsa_switch *ds)
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+- PMCR_FORCE_MODE, PMCR_FORCE_MODE);
++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7530_FORCE_MODE, MT7530_FORCE_MODE);
+
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2560,8 +2560,8 @@ mt7531_setup_common(struct dsa_switch *d
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+- MT7531_FORCE_MODE, MT7531_FORCE_MODE);
++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK);
+
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2644,7 +2644,7 @@ mt7531_setup(struct dsa_switch *ds)
+
+ /* Force link down on all ports before internal reset */
+ for (i = 0; i < MT7530_NUM_PORTS; i++)
+- mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
++ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+
+ /* Reset the switch through internal reset */
+ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
+@@ -2886,7 +2886,7 @@ mt753x_phylink_mac_config(struct phylink
+
+ /* Are we connected to external phy */
+ if (port == 5 && dsa_is_user_port(ds, 5))
+- mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
++ mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY);
+ }
+
+ static void mt753x_phylink_mac_link_down(struct phylink_config *config,
+@@ -2896,7 +2896,7 @@ static void mt753x_phylink_mac_link_down
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct mt7530_priv *priv = dp->ds->priv;
+
+- mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
++ mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ }
+
+ static void mt753x_phylink_mac_link_up(struct phylink_config *config,
+@@ -2910,7 +2910,7 @@ static void mt753x_phylink_mac_link_up(s
+ struct mt7530_priv *priv = dp->ds->priv;
+ u32 mcr;
+
+- mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
++ mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK;
+
+ switch (speed) {
+ case SPEED_1000:
+@@ -2925,9 +2925,9 @@ static void mt753x_phylink_mac_link_up(s
+ if (duplex == DUPLEX_FULL) {
+ mcr |= PMCR_FORCE_FDX;
+ if (tx_pause)
+- mcr |= PMCR_TX_FC_EN;
++ mcr |= PMCR_FORCE_TX_FC_EN;
+ if (rx_pause)
+- mcr |= PMCR_RX_FC_EN;
++ mcr |= PMCR_FORCE_RX_FC_EN;
+ }
+
+ if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
+@@ -2942,7 +2942,7 @@ static void mt753x_phylink_mac_link_up(s
+ }
+ }
+
+- mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
++ mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr);
+ }
+
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm {
+ #define G0_PORT_VID_DEF G0_PORT_VID(0)
+
+ /* Register for port MAC control register */
+-#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
+-#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
++#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100))
++#define PMCR_IFG_XMIT_MASK GENMASK(19, 18)
++#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x)
+ #define PMCR_EXT_PHY BIT(17)
+ #define PMCR_MAC_MODE BIT(16)
+-#define PMCR_FORCE_MODE BIT(15)
+-#define PMCR_TX_EN BIT(14)
+-#define PMCR_RX_EN BIT(13)
++#define MT7530_FORCE_MODE BIT(15)
++#define PMCR_MAC_TX_EN BIT(14)
++#define PMCR_MAC_RX_EN BIT(13)
+ #define PMCR_BACKOFF_EN BIT(9)
+ #define PMCR_BACKPR_EN BIT(8)
+ #define PMCR_FORCE_EEE1G BIT(7)
+ #define PMCR_FORCE_EEE100 BIT(6)
+-#define PMCR_TX_FC_EN BIT(5)
+-#define PMCR_RX_FC_EN BIT(4)
++#define PMCR_FORCE_RX_FC_EN BIT(5)
++#define PMCR_FORCE_TX_FC_EN BIT(4)
+ #define PMCR_FORCE_SPEED_1000 BIT(3)
+ #define PMCR_FORCE_SPEED_100 BIT(2)
+ #define PMCR_FORCE_FDX BIT(1)
+ #define PMCR_FORCE_LNK BIT(0)
+-#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
+- PMCR_FORCE_SPEED_1000)
+-#define MT7531_FORCE_LNK BIT(31)
+-#define MT7531_FORCE_SPD BIT(30)
+-#define MT7531_FORCE_DPX BIT(29)
+-#define MT7531_FORCE_RX_FC BIT(28)
+-#define MT7531_FORCE_TX_FC BIT(27)
+-#define MT7531_FORCE_EEE100 BIT(26)
+-#define MT7531_FORCE_EEE1G BIT(25)
+-#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
+- MT7531_FORCE_SPD | \
+- MT7531_FORCE_DPX | \
+- MT7531_FORCE_RX_FC | \
+- MT7531_FORCE_TX_FC | \
+- MT7531_FORCE_EEE100 | \
+- MT7531_FORCE_EEE1G)
+-#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+- PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
+- PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
+- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
++#define MT7531_FORCE_MODE_LNK BIT(31)
++#define MT7531_FORCE_MODE_SPD BIT(30)
++#define MT7531_FORCE_MODE_DPX BIT(29)
++#define MT7531_FORCE_MODE_RX_FC BIT(28)
++#define MT7531_FORCE_MODE_TX_FC BIT(27)
++#define MT7531_FORCE_MODE_EEE100 BIT(26)
++#define MT7531_FORCE_MODE_EEE1G BIT(25)
++#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \
++ MT7531_FORCE_MODE_SPD | \
++ MT7531_FORCE_MODE_DPX | \
++ MT7531_FORCE_MODE_RX_FC | \
++ MT7531_FORCE_MODE_TX_FC | \
++ MT7531_FORCE_MODE_EEE100 | \
++ MT7531_FORCE_MODE_EEE1G)
++#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
++ PMCR_FORCE_EEE1G | \
++ PMCR_FORCE_EEE100 | \
++ PMCR_FORCE_RX_FC_EN | \
++ PMCR_FORCE_TX_FC_EN | \
++ PMCR_FORCE_SPEED_1000 | \
++ PMCR_FORCE_SPEED_100 | \
++ PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+
+ #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
+ #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
--- /dev/null
+From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:10 +0300
+Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for
+ MT7530 switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The p5_intf_sel pointer is used to store the information of whether PHY
+muxing is used or not. PHY muxing is a feature specific to port 5 of the
+MT7530 switch. Do not use it for other switch models.
+
+Rename the pointer to p5_mode to store the mode the port is being used in.
+Rename the p5_interface_select enum to mt7530_p5_mode, the string
+representation to mt7530_p5_mode_str, and the enum elements.
+
+If PHY muxing is not detected, the default mode, GMAC5, will be used.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 62 +++++++++++++++++-----------------------
+ drivers/net/dsa/mt7530.h | 15 +++++-----
+ 2 files changed, 33 insertions(+), 44 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -864,19 +864,15 @@ mt7530_set_ageing_time(struct dsa_switch
+ return 0;
+ }
+
+-static const char *p5_intf_modes(unsigned int p5_interface)
++static const char *mt7530_p5_mode_str(unsigned int mode)
+ {
+- switch (p5_interface) {
+- case P5_DISABLED:
+- return "DISABLED";
+- case P5_INTF_SEL_PHY_P0:
+- return "PHY P0";
+- case P5_INTF_SEL_PHY_P4:
+- return "PHY P4";
+- case P5_INTF_SEL_GMAC5:
+- return "GMAC5";
++ switch (mode) {
++ case MUX_PHY_P0:
++ return "MUX PHY P0";
++ case MUX_PHY_P4:
++ return "MUX PHY P4";
+ default:
+- return "unknown";
++ return "GMAC5";
+ }
+ }
+
+@@ -893,23 +889,23 @@ static void mt7530_setup_port5(struct ds
+ val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
+ val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
+
+- switch (priv->p5_intf_sel) {
+- case P5_INTF_SEL_PHY_P0:
+- /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
++ switch (priv->p5_mode) {
++ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
++ case MUX_PHY_P0:
+ val |= MHWTRAP_PHY0_SEL;
+ fallthrough;
+- case P5_INTF_SEL_PHY_P4:
+- /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
++
++ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
++ case MUX_PHY_P4:
+ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+- case P5_INTF_SEL_GMAC5:
+- /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+- val &= ~MHWTRAP_P5_DIS;
+- break;
++
++ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
++ val &= ~MHWTRAP_P5_DIS;
+ break;
+ }
+
+@@ -937,8 +933,8 @@ static void mt7530_setup_port5(struct ds
+
+ mt7530_write(priv, MT7530_MHWTRAP, val);
+
+- dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
+- val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
++ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
++ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
+
+ mutex_unlock(&priv->reg_mutex);
+ }
+@@ -2481,13 +2477,11 @@ mt7530_setup(struct dsa_switch *ds)
+ if (ret)
+ return ret;
+
+- /* Setup port 5 */
+- if (!dsa_is_unused_port(ds, 5)) {
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+- } else {
++ /* Check for PHY muxing on port 5 */
++ if (dsa_is_unused_port(ds, 5)) {
+ /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.
+- * Set priv->p5_intf_sel to the appropriate value if PHY muxing
+- * is detected.
++ * Set priv->p5_mode to the appropriate value if PHY muxing is
++ * detected.
+ */
+ for_each_child_of_node(dn, mac_np) {
+ if (!of_device_is_compatible(mac_np,
+@@ -2511,17 +2505,16 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+ id = of_mdio_parse_addr(ds->dev, phy_node);
+ if (id == 0)
+- priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
++ priv->p5_mode = MUX_PHY_P0;
+ if (id == 4)
+- priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
++ priv->p5_mode = MUX_PHY_P4;
+ }
+ of_node_put(mac_np);
+ of_node_put(phy_node);
+ break;
+ }
+
+- if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||
+- priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)
++ if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
+ mt7530_setup_port5(ds, interface);
+ }
+
+@@ -2659,9 +2652,6 @@ mt7531_setup(struct dsa_switch *ds)
+ MT7531_EXT_P_MDIO_12);
+ }
+
+- if (!dsa_is_unused_port(ds, 5))
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+-
+ mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
+ MT7531_GPIO0_INTERRUPT);
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -708,12 +708,11 @@ struct mt7530_port {
+ struct phylink_pcs *sgmii_pcs;
+ };
+
+-/* Port 5 interface select definitions */
+-enum p5_interface_select {
+- P5_DISABLED,
+- P5_INTF_SEL_PHY_P0,
+- P5_INTF_SEL_PHY_P4,
+- P5_INTF_SEL_GMAC5,
++/* Port 5 mode definitions of the MT7530 switch */
++enum mt7530_p5_mode {
++ GMAC5,
++ MUX_PHY_P0,
++ MUX_PHY_P4,
+ };
+
+ struct mt7530_priv;
+@@ -769,7 +768,7 @@ struct mt753x_info {
+ * @ports: Holding the state among ports
+ * @reg_mutex: The lock for protecting among process accessing
+ * registers
+- * @p5_intf_sel: Holding the current port 5 interface select
++ * @p5_mode: Holding the current mode of port 5 of the MT7530 switch
+ * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
+ * has got SGMII
+ * @irq: IRQ number of the switch
+@@ -791,7 +790,7 @@ struct mt7530_priv {
+ const struct mt753x_info *info;
+ unsigned int id;
+ bool mcm;
+- enum p5_interface_select p5_intf_sel;
++ enum mt7530_p5_mode p5_mode;
+ bool p5_sgmii;
+ u8 mirror_rx;
+ u8 mirror_tx;
--- /dev/null
+From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:11 +0300
+Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to
+ mt753x_to_cpu_fw
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt753x_bpdu_port_fw enum is globally used for manipulating the process
+of deciding the forwardable ports, specifically concerning the CPU port(s).
+Therefore, rename it and the values in it to mt753x_to_cpu_fw.
+
+Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 44 ++++++++++-------------
+ drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++--------------------
+ 2 files changed, 56 insertions(+), 64 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1114,42 +1114,34 @@ mt753x_trap_frames(struct mt7530_priv *p
+ * VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_BPC,
+- MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
+- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
+- MT753X_BPDU_PORT_FW_MASK,
+- MT753X_PAE_BPDU_FR |
+- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
++ BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
++ PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
++ BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_RGAC1,
+- MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
+- MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
+- MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
+- MT753X_R02_BPDU_FR |
+- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_R01_BPDU_FR |
+- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
++ R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
++ R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
++ R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_RGAC2,
+- MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
+- MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
+- MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
+- MT753X_R0E_BPDU_FR |
+- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_R03_BPDU_FR |
+- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
++ R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
++ R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
++ R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+ }
+
+ static void
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -67,47 +67,47 @@ enum mt753x_id {
+ #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+ MT7531_MIRROR_MASK : MIRROR_MASK)
+
+-/* Registers for BPDU and PAE frame control*/
++/* Register for BPDU and PAE frame control */
+ #define MT753X_BPC 0x24
+-#define MT753X_PAE_BPDU_FR BIT(25)
+-#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
+-#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)
+-#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
+-#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
++#define PAE_BPDU_FR BIT(25)
++#define PAE_EG_TAG_MASK GENMASK(24, 22)
++#define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x)
++#define PAE_PORT_FW_MASK GENMASK(18, 16)
++#define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x)
++#define BPDU_EG_TAG_MASK GENMASK(8, 6)
++#define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x)
++#define BPDU_PORT_FW_MASK GENMASK(2, 0)
+
+-/* Register for :01 and :02 MAC DA frame control */
++/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
+ #define MT753X_RGAC1 0x28
+-#define MT753X_R02_BPDU_FR BIT(25)
+-#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
+-#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
+-#define MT753X_R01_BPDU_FR BIT(9)
+-#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
+-#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
++#define R02_BPDU_FR BIT(25)
++#define R02_EG_TAG_MASK GENMASK(24, 22)
++#define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x)
++#define R02_PORT_FW_MASK GENMASK(18, 16)
++#define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x)
++#define R01_BPDU_FR BIT(9)
++#define R01_EG_TAG_MASK GENMASK(8, 6)
++#define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x)
++#define R01_PORT_FW_MASK GENMASK(2, 0)
+
+-/* Register for :03 and :0E MAC DA frame control */
++/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
+ #define MT753X_RGAC2 0x2c
+-#define MT753X_R0E_BPDU_FR BIT(25)
+-#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
+-#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
+-#define MT753X_R03_BPDU_FR BIT(9)
+-#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
+-#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
++#define R0E_BPDU_FR BIT(25)
++#define R0E_EG_TAG_MASK GENMASK(24, 22)
++#define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x)
++#define R0E_PORT_FW_MASK GENMASK(18, 16)
++#define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x)
++#define R03_BPDU_FR BIT(9)
++#define R03_EG_TAG_MASK GENMASK(8, 6)
++#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x)
++#define R03_PORT_FW_MASK GENMASK(2, 0)
+
+-enum mt753x_bpdu_port_fw {
+- MT753X_BPDU_FOLLOW_MFC,
+- MT753X_BPDU_CPU_EXCLUDE = 4,
+- MT753X_BPDU_CPU_INCLUDE = 5,
+- MT753X_BPDU_CPU_ONLY = 6,
+- MT753X_BPDU_DROP = 7,
++enum mt753x_to_cpu_fw {
++ TO_CPU_FW_SYSTEM_DEFAULT,
++ TO_CPU_FW_CPU_EXCLUDE = 4,
++ TO_CPU_FW_CPU_INCLUDE = 5,
++ TO_CPU_FW_CPU_ONLY = 6,
++ TO_CPU_FW_DROP = 7,
+ };
+
+ /* Registers for address table access */
--- /dev/null
+From 1dbc1bdc2869e6d2929235c70d64e393aa5a5fa2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:12 +0300
+Subject: [PATCH 05/15] net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC,
+ add MT7531_QRY_FFP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988
+SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and
+MT7531/MT7988. Add MT7530 prefix to these definitions, and define the
+IGMP/MLD Query Frame Flooding Ports mask for MT7531.
+
+Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK.
+
+Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as
+macros.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 ++++++++--------------
+ drivers/net/dsa/mt7530.h | 69 +++++++++++++++++++++++++---------------
+ 2 files changed, 57 insertions(+), 50 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1154,7 +1154,7 @@ mt753x_cpu_port_enable(struct dsa_switch
+ PORT_SPEC_TAG);
+
+ /* Enable flooding on the CPU port */
+- mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
++ mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
+ UNU_FFP(BIT(port)));
+
+ /* Add the CPU port to the CPU port bitmap for MT7531. Trapped frames
+@@ -1318,15 +1318,15 @@ mt7530_port_bridge_flags(struct dsa_swit
+ flags.val & BR_LEARNING ? 0 : SA_DIS);
+
+ if (flags.mask & BR_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)),
+ flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
+
+ if (flags.mask & BR_MCAST_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)),
+ flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
+
+ if (flags.mask & BR_BCAST_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)),
+ flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
+
+ return 0;
+@@ -1862,20 +1862,6 @@ mt7530_port_vlan_del(struct dsa_switch *
+ return 0;
+ }
+
+-static int mt753x_mirror_port_get(unsigned int id, u32 val)
+-{
+- return (id == ID_MT7531 || id == ID_MT7988) ?
+- MT7531_MIRROR_PORT_GET(val) :
+- MIRROR_PORT(val);
+-}
+-
+-static int mt753x_mirror_port_set(unsigned int id, u32 val)
+-{
+- return (id == ID_MT7531 || id == ID_MT7988) ?
+- MT7531_MIRROR_PORT_SET(val) :
+- MIRROR_PORT(val);
+-}
+-
+ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress, struct netlink_ext_ack *extack)
+@@ -1891,14 +1877,14 @@ static int mt753x_port_mirror_add(struct
+ val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
+
+ /* MT7530 only supports one monitor port */
+- monitor_port = mt753x_mirror_port_get(priv->id, val);
++ monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
+ if (val & MT753X_MIRROR_EN(priv->id) &&
+ monitor_port != mirror->to_local_port)
+ return -EEXIST;
+
+ val |= MT753X_MIRROR_EN(priv->id);
+- val &= ~MT753X_MIRROR_MASK(priv->id);
+- val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
++ val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
++ val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
+ mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
+
+ val = mt7530_read(priv, MT7530_PCR_P(port));
+@@ -2538,7 +2524,7 @@ mt7531_setup_common(struct dsa_switch *d
+ mt7530_mib_reset(ds);
+
+ /* Disable flooding on all ports */
+- mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK |
++ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
+ UNU_FFP_MASK);
+
+ for (i = 0; i < MT7530_NUM_PORTS; i++) {
+@@ -3100,10 +3086,12 @@ mt753x_conduit_state_change(struct dsa_s
+ else
+ priv->active_cpu_ports &= ~mask;
+
+- if (priv->active_cpu_ports)
+- val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
++ if (priv->active_cpu_ports) {
++ val = MT7530_CPU_EN |
++ MT7530_CPU_PORT(__ffs(priv->active_cpu_ports));
++ }
+
+- mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
++ mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);
+ }
+
+ static int mt7988_setup(struct dsa_switch *ds)
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -36,36 +36,55 @@ enum mt753x_id {
+ #define MT753X_AGC 0xc
+ #define LOCAL_EN BIT(7)
+
+-/* Registers to mac forward control for unknown frames */
+-#define MT7530_MFC 0x10
+-#define BC_FFP(x) (((x) & 0xff) << 24)
+-#define BC_FFP_MASK BC_FFP(~0)
+-#define UNM_FFP(x) (((x) & 0xff) << 16)
+-#define UNM_FFP_MASK UNM_FFP(~0)
+-#define UNU_FFP(x) (((x) & 0xff) << 8)
+-#define UNU_FFP_MASK UNU_FFP(~0)
+-#define CPU_EN BIT(7)
+-#define CPU_PORT_MASK GENMASK(6, 4)
+-#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x)
+-#define MIRROR_EN BIT(3)
+-#define MIRROR_PORT(x) ((x) & 0x7)
+-#define MIRROR_MASK 0x7
++/* Register for MAC forward control */
++#define MT753X_MFC 0x10
++#define BC_FFP_MASK GENMASK(31, 24)
++#define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x)
++#define UNM_FFP_MASK GENMASK(23, 16)
++#define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x)
++#define UNU_FFP_MASK GENMASK(15, 8)
++#define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x)
++#define MT7530_CPU_EN BIT(7)
++#define MT7530_CPU_PORT_MASK GENMASK(6, 4)
++#define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x)
++#define MT7530_MIRROR_EN BIT(3)
++#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0)
++#define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x)
++#define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x)
++#define MT7531_QRY_FFP_MASK GENMASK(7, 0)
++#define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x)
+
+-/* Registers for CPU forward control */
++/* Register for CPU forward control */
+ #define MT7531_CFC 0x4
+ #define MT7531_MIRROR_EN BIT(19)
+-#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
+-#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
+-#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
++#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16)
++#define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x)
++#define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x)
+ #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
+ #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
+
+-#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_CFC : MT7530_MFC)
+-#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_MIRROR_EN : MIRROR_EN)
+-#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_MIRROR_MASK : MIRROR_MASK)
++#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_CFC : MT753X_MFC)
++
++#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_EN : MT7530_MIRROR_EN)
++
++#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_MASK : \
++ MT7530_MIRROR_PORT_MASK)
++
++#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_GET(val) : \
++ MT7530_MIRROR_PORT_GET(val))
++
++#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_SET(val) : \
++ MT7530_MIRROR_PORT_SET(val))
+
+ /* Register for BPDU and PAE frame control */
+ #define MT753X_BPC 0x24
--- /dev/null
+From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:13 +0300
+Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and
+ MT7530_MHWTRAP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531.
+It's called hardware trap on MT7530, software trap on MT7531. That's
+because some bits of the trap on MT7530 cannot be modified by software
+whilst all bits of the trap on MT7531 can. Rename the definitions for them
+to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the
+definitions specific to the switch model.
+
+Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ.
+
+Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on
+par with the "MT7621 Giga Switch Programming Guide v0.3" document.
+
+Make an enumaration for the XTAL frequency. Set the data type of the xtal
+variable on mt7531_pll_setup() to it.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++--------------------
+ drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------
+ 2 files changed, 54 insertions(+), 55 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -417,23 +417,23 @@ mt7530_setup_port6(struct dsa_switch *ds
+
+ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
+
+- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
++ xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK;
+
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ssc_delta = 0x57;
+ else
+ ssc_delta = 0x87;
+
+ if (priv->id == ID_MT7621) {
+ /* PLL frequency: 125MHz: 1.0GBit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
++ if (xtal == MT7530_XTAL_40MHZ)
+ ncpo1 = 0x0640;
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ncpo1 = 0x0a00;
+ } else { /* PLL frequency: 250MHz: 2.0Gbit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
++ if (xtal == MT7530_XTAL_40MHZ)
+ ncpo1 = 0x0c80;
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ncpo1 = 0x1400;
+ }
+
+@@ -456,19 +456,20 @@ mt7530_setup_port6(struct dsa_switch *ds
+ static void
+ mt7531_pll_setup(struct mt7530_priv *priv)
+ {
++ enum mt7531_xtal_fsel xtal;
+ u32 top_sig;
+ u32 hwstrap;
+- u32 xtal;
+ u32 val;
+
+ val = mt7530_read(priv, MT7531_CREV);
+ top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
+- hwstrap = mt7530_read(priv, MT7531_HWTRAP);
++ hwstrap = mt7530_read(priv, MT753X_TRAP);
+ if ((val & CHIP_REV_M) > 0)
+- xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
+- HWTRAP_XTAL_FSEL_25MHZ;
++ xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ :
++ MT7531_XTAL_FSEL_25MHZ;
+ else
+- xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
++ xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ :
++ MT7531_XTAL_FSEL_40MHZ;
+
+ /* Step 1 : Disable MT7531 COREPLL */
+ val = mt7530_read(priv, MT7531_PLLGP_EN);
+@@ -497,13 +498,13 @@ mt7531_pll_setup(struct mt7530_priv *pri
+ usleep_range(25, 35);
+
+ switch (xtal) {
+- case HWTRAP_XTAL_FSEL_25MHZ:
++ case MT7531_XTAL_FSEL_25MHZ:
+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ val &= ~RG_COREPLL_SDM_PCW_M;
+ val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
+ mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ break;
+- case HWTRAP_XTAL_FSEL_40MHZ:
++ case MT7531_XTAL_FSEL_40MHZ:
+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ val &= ~RG_COREPLL_SDM_PCW_M;
+ val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
+@@ -884,20 +885,20 @@ static void mt7530_setup_port5(struct ds
+
+ mutex_lock(&priv->reg_mutex);
+
+- val = mt7530_read(priv, MT7530_MHWTRAP);
++ val = mt7530_read(priv, MT753X_MTRAP);
+
+- val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
+- val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
++ val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
++ val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
+
+ switch (priv->p5_mode) {
+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+ case MUX_PHY_P0:
+- val |= MHWTRAP_PHY0_SEL;
++ val |= MT7530_P5_PHY0_SEL;
+ fallthrough;
+
+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ case MUX_PHY_P4:
+- val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
++ val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+@@ -905,13 +906,13 @@ static void mt7530_setup_port5(struct ds
+
+ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
+- val &= ~MHWTRAP_P5_DIS;
++ val &= ~MT7530_P5_DIS;
+ break;
+ }
+
+ /* Setup RGMII settings */
+ if (phy_interface_mode_is_rgmii(interface)) {
+- val |= MHWTRAP_P5_RGMII_MODE;
++ val |= MT7530_P5_RGMII_MODE;
+
+ /* P5 RGMII RX Clock Control: delay setting for 1000M */
+ mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
+@@ -931,7 +932,7 @@ static void mt7530_setup_port5(struct ds
+ P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
+ }
+
+- mt7530_write(priv, MT7530_MHWTRAP, val);
++ mt7530_write(priv, MT753X_MTRAP, val);
+
+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
+ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
+@@ -2370,7 +2371,7 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+
+ /* Waiting for MT7530 got to stable */
+- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
+ ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ 20, 1000000);
+ if (ret < 0) {
+@@ -2385,7 +2386,7 @@ mt7530_setup(struct dsa_switch *ds)
+ return -ENODEV;
+ }
+
+- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) {
+ dev_err(priv->dev,
+ "MT7530 with a 20MHz XTAL is not supported!\n");
+ return -EINVAL;
+@@ -2406,12 +2407,12 @@ mt7530_setup(struct dsa_switch *ds)
+ RD_TAP_MASK, RD_TAP(16));
+
+ /* Enable port 6 */
+- val = mt7530_read(priv, MT7530_MHWTRAP);
+- val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
+- val |= MHWTRAP_MANUAL;
+- mt7530_write(priv, MT7530_MHWTRAP, val);
++ val = mt7530_read(priv, MT753X_MTRAP);
++ val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
++ val |= MT7530_CHG_TRAP;
++ mt7530_write(priv, MT753X_MTRAP, val);
+
+- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+
+ mt753x_trap_frames(priv);
+@@ -2591,7 +2592,7 @@ mt7531_setup(struct dsa_switch *ds)
+ }
+
+ /* Waiting for MT7530 got to stable */
+- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
+ ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ 20, 1000000);
+ if (ret < 0) {
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -495,32 +495,30 @@ enum mt7531_clk_skew {
+ MT7531_CLK_SKEW_REVERSE = 3,
+ };
+
+-/* Register for hw trap status */
+-#define MT7530_HWTRAP 0x7800
+-#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
+-#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
+-#define HWTRAP_XTAL_40MHZ (BIT(10))
+-#define HWTRAP_XTAL_20MHZ (BIT(9))
++/* Register for trap status */
++#define MT753X_TRAP 0x7800
++#define MT7530_XTAL_MASK (BIT(10) | BIT(9))
++#define MT7530_XTAL_25MHZ (BIT(10) | BIT(9))
++#define MT7530_XTAL_40MHZ BIT(10)
++#define MT7530_XTAL_20MHZ BIT(9)
++#define MT7531_XTAL25 BIT(7)
+
+-#define MT7531_HWTRAP 0x7800
+-#define HWTRAP_XTAL_FSEL_MASK BIT(7)
+-#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
+-#define HWTRAP_XTAL_FSEL_40MHZ 0
+-/* Unique fields of (M)HWSTRAP for MT7531 */
+-#define XTAL_FSEL_S 7
+-#define XTAL_FSEL_M BIT(7)
+-#define PHY_EN BIT(6)
+-#define CHG_STRAP BIT(8)
++/* Register for trap modification */
++#define MT753X_MTRAP 0x7804
++#define MT7530_P5_PHY0_SEL BIT(20)
++#define MT7530_CHG_TRAP BIT(16)
++#define MT7530_P5_MAC_SEL BIT(13)
++#define MT7530_P6_DIS BIT(8)
++#define MT7530_P5_RGMII_MODE BIT(7)
++#define MT7530_P5_DIS BIT(6)
++#define MT7530_PHY_INDIRECT_ACCESS BIT(5)
++#define MT7531_CHG_STRAP BIT(8)
++#define MT7531_PHY_EN BIT(6)
+
+-/* Register for hw trap modification */
+-#define MT7530_MHWTRAP 0x7804
+-#define MHWTRAP_PHY0_SEL BIT(20)
+-#define MHWTRAP_MANUAL BIT(16)
+-#define MHWTRAP_P5_MAC_SEL BIT(13)
+-#define MHWTRAP_P6_DIS BIT(8)
+-#define MHWTRAP_P5_RGMII_MODE BIT(7)
+-#define MHWTRAP_P5_DIS BIT(6)
+-#define MHWTRAP_PHY_ACCESS BIT(5)
++enum mt7531_xtal_fsel {
++ MT7531_XTAL_FSEL_25MHZ,
++ MT7531_XTAL_FSEL_40MHZ,
++};
+
+ /* Register for TOP signal control */
+ #define MT7530_TOP_SIG_CTRL 0x7808
--- /dev/null
+From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:14 +0300
+Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for
+ MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On MT7530, the media-independent interfaces of port 5 and 6 are controlled
+by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
+these bits only when the relevant port is being enabled or disabled. This
+ensures that these ports will be disabled when they are not in use.
+
+Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
+done on mt7530_setup().
+
+Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only
+on the appropriate case.
+
+If PHY muxing is detected, clear MT7530_P5_DIS before calling
+mt7530_setup_port5().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++-----------
+ 1 file changed, 27 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -887,8 +887,7 @@ static void mt7530_setup_port5(struct ds
+
+ val = mt7530_read(priv, MT753X_MTRAP);
+
+- val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
+- val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
++ val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
+
+ switch (priv->p5_mode) {
+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+@@ -898,15 +897,13 @@ static void mt7530_setup_port5(struct ds
+
+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ case MUX_PHY_P4:
+- val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+-
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+
+ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
+- val &= ~MT7530_P5_DIS;
++ val |= MT7530_P5_MAC_SEL;
+ break;
+ }
+
+@@ -1200,6 +1197,14 @@ mt7530_port_enable(struct dsa_switch *ds
+
+ mutex_unlock(&priv->reg_mutex);
+
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return 0;
++
++ if (port == 5)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
++
+ return 0;
+ }
+
+@@ -1218,6 +1223,14 @@ mt7530_port_disable(struct dsa_switch *d
+ PCR_MATRIX_CLR);
+
+ mutex_unlock(&priv->reg_mutex);
++
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return;
++
++ if (port == 5)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
+ }
+
+ static int
+@@ -2406,11 +2419,11 @@ mt7530_setup(struct dsa_switch *ds)
+ mt7530_rmw(priv, MT7530_TRGMII_RD(i),
+ RD_TAP_MASK, RD_TAP(16));
+
+- /* Enable port 6 */
+- val = mt7530_read(priv, MT753X_MTRAP);
+- val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
+- val |= MT7530_CHG_TRAP;
+- mt7530_write(priv, MT753X_MTRAP, val);
++ /* Allow modifying the trap and directly access PHY registers via the
++ * MDIO bus the switch is on.
++ */
++ mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
++ MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
+
+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+@@ -2493,8 +2506,11 @@ mt7530_setup(struct dsa_switch *ds)
+ break;
+ }
+
+- if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
++ if (priv->p5_mode == MUX_PHY_P0 ||
++ priv->p5_mode == MUX_PHY_P4) {
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ mt7530_setup_port5(ds, interface);
++ }
+ }
+
+ #ifdef CONFIG_GPIOLIB
--- /dev/null
+From 1f5669efca65564c7533704917f79003c6b36c9c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:15 +0300
+Subject: [PATCH 08/15] net: dsa: mt7530: return mt7530_setup_mdio &
+ mt7531_setup_common on error
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt7530_setup_mdio() and mt7531_setup_common() functions should be
+checked for errors. Return if the functions return a non-zero value.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2672,7 +2672,9 @@ mt7531_setup(struct dsa_switch *ds)
+ 0);
+ }
+
+- mt7531_setup_common(ds);
++ ret = mt7531_setup_common(ds);
++ if (ret)
++ return ret;
+
+ /* Setup VLAN ID 0 for VLAN-unaware bridges */
+ ret = mt7530_setup_vlan0(priv);
+@@ -3031,6 +3033,8 @@ mt753x_setup(struct dsa_switch *ds)
+ ret = mt7530_setup_mdio(priv);
+ if (ret && priv->irq)
+ mt7530_free_irq_common(priv);
++ if (ret)
++ return ret;
+
+ /* Initialise the PCS devices */
+ for (i = 0; i < priv->ds->num_ports; i++) {
--- /dev/null
+From 6cc2d4ccd77509df74b7b8ef46bbc6ba0a571318 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:16 +0300
+Subject: [PATCH 09/15] net: dsa: mt7530: define MAC speed capabilities per
+ switch model
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+With the support of the MT7988 SoC switch, the MAC speed capabilities
+defined on mt753x_phylink_get_caps() won't apply to all switch models
+anymore. Move them to more appropriate locations instead of overwriting
+config->mac_capabilities.
+
+Remove the comment on mt753x_phylink_get_caps() as it's become invalid with
+the support of MT7531 and MT7988 SoC switch.
+
+Add break to case 6 of mt7988_mac_port_get_caps() to be explicit.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2690,6 +2690,8 @@ mt7531_setup(struct dsa_switch *ds)
+ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+ {
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
++
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+ case 0 ... 4:
+@@ -2721,6 +2723,8 @@ static void mt7531_mac_port_get_caps(str
+ {
+ struct mt7530_priv *priv = ds->priv;
+
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
++
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+ case 0 ... 4:
+@@ -2760,14 +2764,17 @@ static void mt7988_mac_port_get_caps(str
+ case 0 ... 3:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
++
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
+ break;
+
+ /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
+ case 6:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+- MAC_10000FD;
++
++ config->mac_capabilities |= MAC_10000FD;
++ break;
+ }
+ }
+
+@@ -2937,9 +2944,7 @@ static void mt753x_phylink_get_caps(stru
+ {
+ struct mt7530_priv *priv = ds->priv;
+
+- /* This switch only supports full-duplex at 1Gbps */
+- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+- MAC_10 | MAC_100 | MAC_1000FD;
++ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE;
+
+ /* This driver does not make use of the speed, duplex, pause or the
+ * advertisement in its mac_config, so it is safe to mark this driver
--- /dev/null
+From dd0f15fc877c10567699190bce0f55e96f4ad6b5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:17 +0300
+Subject: [PATCH 10/15] net: dsa: mt7530: get rid of function sanity check
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Get rid of checking whether functions are filled properly. priv->info which
+is an mt753x_info structure is filled and checked for before this check.
+It's unnecessary checking whether it's filled properly.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3235,13 +3235,6 @@ mt7530_probe_common(struct mt7530_priv *
+ if (!priv->info)
+ return -EINVAL;
+
+- /* Sanity check if these required device operations are filled
+- * properly.
+- */
+- if (!priv->info->sw_setup || !priv->info->phy_read ||
+- !priv->info->phy_write || !priv->info->mac_port_get_caps)
+- return -EINVAL;
+-
+ priv->id = priv->info->id;
+ priv->dev = dev;
+ priv->ds->priv = priv;
--- /dev/null
+From 2dff9759602b069f97ccc939e15a47ca051b2983 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:18 +0300
+Subject: [PATCH 11/15] net: dsa: mt7530: refactor MT7530_PMEEECR_P()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_PMEEECR_P() register is on MT7530, MT7531, and the switch on the
+MT7988 SoC. Rename the definition for them to MT753X_PMEEECR_P(). Use the
+FIELD_PREP and FIELD_GET macros. Rename GET_LPI_THRESH() and
+SET_LPI_THRESH() to LPI_THRESH_GET() and LPI_THRESH_SET().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 8 ++++----
+ drivers/net/dsa/mt7530.h | 13 +++++++------
+ 2 files changed, 11 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3062,10 +3062,10 @@ static int mt753x_get_mac_eee(struct dsa
+ struct ethtool_eee *e)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
++ u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port));
+
+ e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
+- e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
++ e->tx_lpi_timer = LPI_THRESH_GET(eeecr);
+
+ return 0;
+ }
+@@ -3079,11 +3079,11 @@ static int mt753x_set_mac_eee(struct dsa
+ if (e->tx_lpi_timer > 0xFFF)
+ return -EINVAL;
+
+- set = SET_LPI_THRESH(e->tx_lpi_timer);
++ set = LPI_THRESH_SET(e->tx_lpi_timer);
+ if (!e->tx_lpi_enabled)
+ /* Force LPI Mode without a delay */
+ set |= LPI_MODE_EN;
+- mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
++ mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set);
+
+ return 0;
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -364,13 +364,14 @@ enum mt7530_vlan_port_acc_frm {
+ PMCR_FORCE_SPEED_100 | \
+ PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+
+-#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
+-#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
+-#define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
++#define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100)
++#define WAKEUP_TIME_1000_MASK GENMASK(31, 24)
++#define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x)
++#define WAKEUP_TIME_100_MASK GENMASK(23, 16)
++#define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x)
+ #define LPI_THRESH_MASK GENMASK(15, 4)
+-#define LPI_THRESH_SHT 4
+-#define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
+-#define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
++#define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x)
++#define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x)
+ #define LPI_MODE_EN BIT(0)
+
+ #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
--- /dev/null
+From 21d67c2fabfe40baf33202d3287b67b6c16f8382 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:19 +0300
+Subject: [PATCH 12/15] net: dsa: mt7530: get rid of mac_port_validate member
+ of mt753x_info
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mac_port_validate member of the mt753x_info structure is not being
+used, remove it. Improve the member description section in the process.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.h | 10 +++-------
+ 1 file changed, 3 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -743,13 +743,12 @@ struct mt753x_pcs {
+
+ /* struct mt753x_info - This is the main data structure for holding the specific
+ * part for each supported device
++ * @id: Holding the identifier to a switch model
++ * @pcs_ops: Holding the pointer to the MAC PCS operations structure
+ * @sw_setup: Holding the handler to a device initialization
+ * @phy_read: Holding the way reading PHY port
+ * @phy_write: Holding the way writing PHY port
+- * @phy_mode_supported: Check if the PHY type is being supported on a certain
+- * port
+- * @mac_port_validate: Holding the way to set addition validate type for a
+- * certan MAC port
++ * @mac_port_get_caps: Holding the handler that provides MAC capabilities
+ * @mac_port_config: Holding the way setting up the PHY attribute to a
+ * certain MAC port
+ */
+@@ -763,9 +762,6 @@ struct mt753x_info {
+ int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
+ void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
+ struct phylink_config *config);
+- void (*mac_port_validate)(struct dsa_switch *ds, int port,
+- phy_interface_t interface,
+- unsigned long *supported);
+ void (*mac_port_config)(struct dsa_switch *ds, int port,
+ unsigned int mode,
+ phy_interface_t interface);
--- /dev/null
+From 6efc8ae3eb0363328f479191a0cf0dc12a16e090 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:20 +0300
+Subject: [PATCH 13/15] net: dsa: mt7530: use priv->ds->num_ports instead of
+ MT7530_NUM_PORTS
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use priv->ds->num_ports on all for loops which configure the switch
+registers. In the future, the value of MT7530_NUM_PORTS will depend on
+priv->id. Therefore, this change prepares the subdriver for a simpler
+implementation.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1418,7 +1418,7 @@ mt7530_port_set_vlan_unaware(struct dsa_
+ mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
+ G0_PORT_VID_DEF);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ if (dsa_is_user_port(ds, i) &&
+ dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
+ all_user_ports_removed = false;
+@@ -2433,7 +2433,7 @@ mt7530_setup(struct dsa_switch *ds)
+ /* Enable and reset MIB counters */
+ mt7530_mib_reset(ds);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+@@ -2544,7 +2544,7 @@ mt7531_setup_common(struct dsa_switch *d
+ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
+ UNU_FFP_MASK);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+@@ -2631,7 +2631,7 @@ mt7531_setup(struct dsa_switch *ds)
+ priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
+
+ /* Force link down on all ports before internal reset */
+- for (i = 0; i < MT7530_NUM_PORTS; i++)
++ for (i = 0; i < priv->ds->num_ports; i++)
+ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+
+ /* Reset the switch through internal reset */
--- /dev/null
+From 4794c12e3aefe05dd0063c2b6b0101854b143bac Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:21 +0300
+Subject: [PATCH 14/15] net: dsa: mt7530: do not pass port variable to
+ mt7531_rgmii_setup()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt7531_rgmii_setup() function does not use the port variable, do not
+pass the variable to it.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2790,7 +2790,7 @@ mt7530_mac_config(struct dsa_switch *ds,
+ mt7530_setup_port6(priv->ds, interface);
+ }
+
+-static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
++static void mt7531_rgmii_setup(struct mt7530_priv *priv,
+ phy_interface_t interface,
+ struct phy_device *phydev)
+ {
+@@ -2841,7 +2841,7 @@ mt7531_mac_config(struct dsa_switch *ds,
+ if (phy_interface_mode_is_rgmii(interface)) {
+ dp = dsa_to_port(ds, port);
+ phydev = dp->slave->phydev;
+- mt7531_rgmii_setup(priv, port, interface, phydev);
++ mt7531_rgmii_setup(priv, interface, phydev);
+ }
+ }
+
--- /dev/null
+From c45832fe783f468aaaace09ae95a30cbf0acf724 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:22 +0300
+Subject: [PATCH 15/15] net: dsa: mt7530: explain exposing MDIO bus of MT7531AE
+ better
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on MT7531AE.
+Therefore, the GPIO 11-12 pins are set to function as MDC and MDIO to
+expose the MDIO bus of the switch. Replace the comment with a better
+explanation.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2640,7 +2640,10 @@ mt7531_setup(struct dsa_switch *ds)
+ if (!priv->p5_sgmii) {
+ mt7531_pll_setup(priv);
+ } else {
+- /* Let ds->slave_mii_bus be able to access external phy. */
++ /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on
++ * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO
++ * to expose the MDIO bus of the switch.
++ */
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
+ MT7531_EXT_P_MDC_11);
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
--- /dev/null
+From 16e6592cd5c5bd74d8890973489f60176c692614 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Sun, 28 Apr 2024 12:19:58 +0300
+Subject: [PATCH] net: dsa: mt7530: do not set MT7530_P5_DIS when PHY muxing is
+ being used
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DSA initalises the ds->num_ports amount of ports in
+dsa_switch_touch_ports(). When the PHY muxing feature is in use, port 5
+won't be defined in the device tree. Because of this, the type member of
+the dsa_port structure for this port will be assigned DSA_PORT_TYPE_UNUSED.
+The dsa_port_setup() function calls ds->ops->port_disable() when the port
+type is DSA_PORT_TYPE_UNUSED.
+
+The MT7530_P5_DIS bit is unset in mt7530_setup() when PHY muxing is being
+used. mt7530_port_disable() which is assigned to ds->ops->port_disable() is
+called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS
+which breaks network connectivity when PHY muxing is being used.
+
+Therefore, do not set MT7530_P5_DIS when PHY muxing is being used.
+
+Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530")
+Reported-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240428-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v2-1-bb7c37d293f8@arinc9.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1227,7 +1227,8 @@ mt7530_port_disable(struct dsa_switch *d
+ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
+ return;
+
+- if (port == 5)
++ /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */
++ if (port == 5 && priv->p5_mode == GMAC5)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ else if (port == 6)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
--- /dev/null
+From d8dcf5bd6d0eace9f7c1daa14b63b3925b09d033 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 30 Apr 2024 08:01:33 +0300
+Subject: [PATCH] net: dsa: mt7530: detect PHY muxing when PHY is defined on
+ switch MDIO bus
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide
+direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO
+bus the switch listens on. The PHY muxing feature makes use of this.
+
+This is problematic as the PHY may be attached before the switch is
+initialised, in which case, the PHY will fail to be attached.
+
+Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration
+of switch MDIO bus"), we can describe the switch PHYs on the MDIO bus of
+the switch on the device tree. Extend the check to detect PHY muxing when
+the PHY is defined on the MDIO bus of the switch on the device tree.
+
+When the PHY is described this way, the switch will be initialised first,
+then the switch MDIO bus will be registered. Only after these steps, the
+PHY will be attached.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/20240430-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v2-1-9104d886d0db@arinc9.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2489,7 +2489,8 @@ mt7530_setup(struct dsa_switch *ds)
+ if (!phy_node)
+ continue;
+
+- if (phy_node->parent == priv->dev->of_node->parent) {
++ if (phy_node->parent == priv->dev->of_node->parent ||
++ phy_node->parent->parent == priv->dev->of_node) {
+ ret = of_get_phy_mode(mac_np, &interface);
+ if (ret && ret != -ENODEV) {
+ of_node_put(mac_np);
+++ /dev/null
-From c3552d3f85f06cf4b4818bd84c4fcc09d8d45165 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:17:19 +0100
-Subject: [PATCH 01/13] net: dsa: mt7530: make some noise if register read
- fails
-
-Simply returning the negative error value instead of the read value
-doesn't seem like a good idea. Return 0 instead and add WARN_ON_ONCE(1)
-so this kind of error will not go unnoticed.
-
-Suggested-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -224,9 +224,10 @@ mt7530_mii_read(struct mt7530_priv *priv
- /* MT7530 uses 31 as the pseudo port */
- ret = bus->write(bus, 0x1f, 0x1f, page);
- if (ret < 0) {
-+ WARN_ON_ONCE(1);
- dev_err(&bus->dev,
- "failed to read mt7530 register\n");
-- return ret;
-+ return 0;
- }
-
- lo = bus->read(bus, 0x1f, r);
+++ /dev/null
-From b896355fc4988216d4f38582d07add9252a795ae Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:17:30 +0100
-Subject: [PATCH 02/13] net: dsa: mt7530: refactor SGMII PCS creation
-
-Instead of macro templates use a dedidated function and allocated
-regmap_config when creating the regmaps for the pcs-mtk-lynxi
-instances.
-This is in preparation to switching to use unlocked regmap accessors
-and have regmap's locking API handle locking for us.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 74 +++++++++++++++++++++++++++-------------
- 1 file changed, 50 insertions(+), 24 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2968,26 +2968,56 @@ static const struct regmap_bus mt7531_re
- .reg_update_bits = mt7530_regmap_update_bits,
- };
-
--#define MT7531_PCS_REGMAP_CONFIG(_name, _reg_base) \
-- { \
-- .name = _name, \
-- .reg_bits = 16, \
-- .val_bits = 32, \
-- .reg_stride = 4, \
-- .reg_base = _reg_base, \
-- .max_register = 0x17c, \
-+static int
-+mt7531_create_sgmii(struct mt7530_priv *priv)
-+{
-+ struct regmap_config *mt7531_pcs_config[2];
-+ struct phylink_pcs *pcs;
-+ struct regmap *regmap;
-+ int i, ret = 0;
-+
-+ for (i = 0; i < 2; i++) {
-+ mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
-+ sizeof(struct regmap_config),
-+ GFP_KERNEL);
-+ if (!mt7531_pcs_config[i]) {
-+ ret = -ENOMEM;
-+ break;
-+ }
-+
-+ mt7531_pcs_config[i]->name = i ? "port6" : "port5";
-+ mt7531_pcs_config[i]->reg_bits = 16;
-+ mt7531_pcs_config[i]->val_bits = 32;
-+ mt7531_pcs_config[i]->reg_stride = 4;
-+ mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
-+ mt7531_pcs_config[i]->max_register = 0x17c;
-+
-+ regmap = devm_regmap_init(priv->dev,
-+ &mt7531_regmap_bus, priv,
-+ mt7531_pcs_config[i]);
-+ if (IS_ERR(regmap)) {
-+ ret = PTR_ERR(regmap);
-+ break;
-+ }
-+ pcs = mtk_pcs_lynxi_create(priv->dev, regmap,
-+ MT7531_PHYA_CTRL_SIGNAL3, 0);
-+ if (!pcs) {
-+ ret = -ENXIO;
-+ break;
-+ }
-+ priv->ports[5 + i].sgmii_pcs = pcs;
- }
-
--static const struct regmap_config mt7531_pcs_config[] = {
-- MT7531_PCS_REGMAP_CONFIG("port5", MT7531_SGMII_REG_BASE(5)),
-- MT7531_PCS_REGMAP_CONFIG("port6", MT7531_SGMII_REG_BASE(6)),
--};
-+ if (ret && i)
-+ mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs);
-+
-+ return ret;
-+}
-
- static int
- mt753x_setup(struct dsa_switch *ds)
- {
- struct mt7530_priv *priv = ds->priv;
-- struct regmap *regmap;
- int i, ret;
-
- /* Initialise the PCS devices */
-@@ -3009,15 +3039,11 @@ mt753x_setup(struct dsa_switch *ds)
- if (ret && priv->irq)
- mt7530_free_irq_common(priv);
-
-- if (priv->id == ID_MT7531)
-- for (i = 0; i < 2; i++) {
-- regmap = devm_regmap_init(ds->dev,
-- &mt7531_regmap_bus, priv,
-- &mt7531_pcs_config[i]);
-- priv->ports[5 + i].sgmii_pcs =
-- mtk_pcs_lynxi_create(ds->dev, regmap,
-- MT7531_PHYA_CTRL_SIGNAL3, 0);
-- }
-+ if (priv->id == ID_MT7531) {
-+ ret = mt7531_create_sgmii(priv);
-+ if (ret && priv->irq)
-+ mt7530_free_irq_common(priv);
-+ }
-
- return ret;
- }
+++ /dev/null
-From 33396408776385f3d2f6069646169a6b5b28e3b3 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:17:40 +0100
-Subject: [PATCH 03/13] net: dsa: mt7530: use unlocked regmap accessors
-
-Instead of wrapping the locked register accessor functions, use the
-unlocked variants and add locking wrapper functions to let regmap
-handle the locking.
-
-This is a preparation towards being able to always use regmap to
-access switch registers instead of open-coded accessor functions.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 23 ++++++++++++++---------
- 1 file changed, 14 insertions(+), 9 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2941,7 +2941,7 @@ static int mt7530_regmap_read(void *cont
- {
- struct mt7530_priv *priv = context;
-
-- *val = mt7530_read(priv, reg);
-+ *val = mt7530_mii_read(priv, reg);
- return 0;
- };
-
-@@ -2949,23 +2949,25 @@ static int mt7530_regmap_write(void *con
- {
- struct mt7530_priv *priv = context;
-
-- mt7530_write(priv, reg, val);
-+ mt7530_mii_write(priv, reg, val);
- return 0;
- };
-
--static int mt7530_regmap_update_bits(void *context, unsigned int reg,
-- unsigned int mask, unsigned int val)
-+static void
-+mt7530_mdio_regmap_lock(void *mdio_lock)
- {
-- struct mt7530_priv *priv = context;
-+ mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
-+}
-
-- mt7530_rmw(priv, reg, mask, val);
-- return 0;
--};
-+static void
-+mt7530_mdio_regmap_unlock(void *mdio_lock)
-+{
-+ mutex_unlock(mdio_lock);
-+}
-
- static const struct regmap_bus mt7531_regmap_bus = {
- .reg_write = mt7530_regmap_write,
- .reg_read = mt7530_regmap_read,
-- .reg_update_bits = mt7530_regmap_update_bits,
- };
-
- static int
-@@ -2991,6 +2993,9 @@ mt7531_create_sgmii(struct mt7530_priv *
- mt7531_pcs_config[i]->reg_stride = 4;
- mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
- mt7531_pcs_config[i]->max_register = 0x17c;
-+ mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock;
-+ mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
-+ mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
-
- regmap = devm_regmap_init(priv->dev,
- &mt7531_regmap_bus, priv,
+++ /dev/null
-From 743cba4345cb366248f9d375c6a9e50243dc0677 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:17:52 +0100
-Subject: [PATCH 04/13] net: dsa: mt7530: use regmap to access switch register
- space
-
-Use regmap API to access the switch register space.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 99 ++++++++++++++++++++++++----------------
- drivers/net/dsa/mt7530.h | 2 +
- 2 files changed, 62 insertions(+), 39 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -183,9 +183,9 @@ core_clear(struct mt7530_priv *priv, u32
- }
-
- static int
--mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
-+mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
- {
-- struct mii_bus *bus = priv->bus;
-+ struct mii_bus *bus = context;
- u16 page, r, lo, hi;
- int ret;
-
-@@ -197,24 +197,34 @@ mt7530_mii_write(struct mt7530_priv *pri
- /* MT7530 uses 31 as the pseudo port */
- ret = bus->write(bus, 0x1f, 0x1f, page);
- if (ret < 0)
-- goto err;
-+ return ret;
-
- ret = bus->write(bus, 0x1f, r, lo);
- if (ret < 0)
-- goto err;
-+ return ret;
-
- ret = bus->write(bus, 0x1f, 0x10, hi);
--err:
-+ return ret;
-+}
-+
-+static int
-+mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
-+{
-+ int ret;
-+
-+ ret = regmap_write(priv->regmap, reg, val);
-+
- if (ret < 0)
-- dev_err(&bus->dev,
-+ dev_err(priv->dev,
- "failed to write mt7530 register\n");
-+
- return ret;
- }
-
--static u32
--mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
-+static int
-+mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
- {
-- struct mii_bus *bus = priv->bus;
-+ struct mii_bus *bus = context;
- u16 page, r, lo, hi;
- int ret;
-
-@@ -223,17 +233,32 @@ mt7530_mii_read(struct mt7530_priv *priv
-
- /* MT7530 uses 31 as the pseudo port */
- ret = bus->write(bus, 0x1f, 0x1f, page);
-- if (ret < 0) {
-+ if (ret < 0)
-+ return ret;
-+
-+ lo = bus->read(bus, 0x1f, r);
-+ hi = bus->read(bus, 0x1f, 0x10);
-+
-+ *val = (hi << 16) | (lo & 0xffff);
-+
-+ return 0;
-+}
-+
-+static u32
-+mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
-+{
-+ int ret;
-+ u32 val;
-+
-+ ret = regmap_read(priv->regmap, reg, &val);
-+ if (ret) {
- WARN_ON_ONCE(1);
-- dev_err(&bus->dev,
-+ dev_err(priv->dev,
- "failed to read mt7530 register\n");
- return 0;
- }
-
-- lo = bus->read(bus, 0x1f, r);
-- hi = bus->read(bus, 0x1f, 0x10);
--
-- return (hi << 16) | (lo & 0xffff);
-+ return val;
- }
-
- static void
-@@ -283,14 +308,10 @@ mt7530_rmw(struct mt7530_priv *priv, u32
- u32 mask, u32 set)
- {
- struct mii_bus *bus = priv->bus;
-- u32 val;
-
- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
-
-- val = mt7530_mii_read(priv, reg);
-- val &= ~mask;
-- val |= set;
-- mt7530_mii_write(priv, reg, val);
-+ regmap_update_bits(priv->regmap, reg, mask, set);
-
- mutex_unlock(&bus->mdio_lock);
- }
-@@ -298,7 +319,7 @@ mt7530_rmw(struct mt7530_priv *priv, u32
- static void
- mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
- {
-- mt7530_rmw(priv, reg, 0, val);
-+ mt7530_rmw(priv, reg, val, val);
- }
-
- static void
-@@ -2937,22 +2958,6 @@ static const struct phylink_pcs_ops mt75
- .pcs_an_restart = mt7530_pcs_an_restart,
- };
-
--static int mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
--{
-- struct mt7530_priv *priv = context;
--
-- *val = mt7530_mii_read(priv, reg);
-- return 0;
--};
--
--static int mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
--{
-- struct mt7530_priv *priv = context;
--
-- mt7530_mii_write(priv, reg, val);
-- return 0;
--};
--
- static void
- mt7530_mdio_regmap_lock(void *mdio_lock)
- {
-@@ -2965,7 +2970,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc
- mutex_unlock(mdio_lock);
- }
-
--static const struct regmap_bus mt7531_regmap_bus = {
-+static const struct regmap_bus mt7530_regmap_bus = {
- .reg_write = mt7530_regmap_write,
- .reg_read = mt7530_regmap_read,
- };
-@@ -2998,7 +3003,7 @@ mt7531_create_sgmii(struct mt7530_priv *
- mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
-
- regmap = devm_regmap_init(priv->dev,
-- &mt7531_regmap_bus, priv,
-+ &mt7530_regmap_bus, priv->bus,
- mt7531_pcs_config[i]);
- if (IS_ERR(regmap)) {
- ret = PTR_ERR(regmap);
-@@ -3163,6 +3168,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match)
- static int
- mt7530_probe(struct mdio_device *mdiodev)
- {
-+ static struct regmap_config *regmap_config;
- struct mt7530_priv *priv;
- struct device_node *dn;
-
-@@ -3242,6 +3248,21 @@ mt7530_probe(struct mdio_device *mdiodev
- mutex_init(&priv->reg_mutex);
- dev_set_drvdata(&mdiodev->dev, priv);
-
-+ regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
-+ GFP_KERNEL);
-+ if (!regmap_config)
-+ return -ENOMEM;
-+
-+ regmap_config->reg_bits = 16;
-+ regmap_config->val_bits = 32;
-+ regmap_config->reg_stride = 4;
-+ regmap_config->max_register = MT7530_CREV;
-+ regmap_config->disable_locking = true;
-+ priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
-+ priv->bus, regmap_config);
-+ if (IS_ERR(priv->regmap))
-+ return PTR_ERR(priv->regmap);
-+
- return dsa_register_switch(priv->ds);
- }
-
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -754,6 +754,7 @@ struct mt753x_info {
- * @dev: The device pointer
- * @ds: The pointer to the dsa core structure
- * @bus: The bus used for the device and built-in PHY
-+ * @regmap: The regmap instance representing all switch registers
- * @rstc: The pointer to reset control used by MCM
- * @core_pwr: The power supplied into the core
- * @io_pwr: The power supplied into the I/O
-@@ -774,6 +775,7 @@ struct mt7530_priv {
- struct device *dev;
- struct dsa_switch *ds;
- struct mii_bus *bus;
-+ struct regmap *regmap;
- struct reset_control *rstc;
- struct regulator *core_pwr;
- struct regulator *io_pwr;
+++ /dev/null
-From f3cf1d06e2aef644b426c23b4bb570780b1f8d47 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:18:04 +0100
-Subject: [PATCH 05/13] net: dsa: mt7530: move SGMII PCS creation to
- mt7530_probe function
-
-Move creating the SGMII PCS from mt753x_setup() to the more appropriate
-mt7530_probe() function.
-This is done also in preparation of moving all functions related to
-MDIO-connected MT753x switches to a separate module.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 13 +++++++------
- 1 file changed, 7 insertions(+), 6 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -3049,12 +3049,6 @@ mt753x_setup(struct dsa_switch *ds)
- if (ret && priv->irq)
- mt7530_free_irq_common(priv);
-
-- if (priv->id == ID_MT7531) {
-- ret = mt7531_create_sgmii(priv);
-- if (ret && priv->irq)
-- mt7530_free_irq_common(priv);
-- }
--
- return ret;
- }
-
-@@ -3171,6 +3165,7 @@ mt7530_probe(struct mdio_device *mdiodev
- static struct regmap_config *regmap_config;
- struct mt7530_priv *priv;
- struct device_node *dn;
-+ int ret;
-
- dn = mdiodev->dev.of_node;
-
-@@ -3263,6 +3258,12 @@ mt7530_probe(struct mdio_device *mdiodev
- if (IS_ERR(priv->regmap))
- return PTR_ERR(priv->regmap);
-
-+ if (priv->id == ID_MT7531) {
-+ ret = mt7531_create_sgmii(priv);
-+ if (ret)
-+ return ret;
-+ }
-+
- return dsa_register_switch(priv->ds);
- }
-
+++ /dev/null
-From e4729ae7c095c0c87794bff47ea43e35d69de986 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:18:16 +0100
-Subject: [PATCH 06/13] net: dsa: mt7530: introduce mutex helpers
-
-As the MDIO bus lock only needs to be involved if actually operating
-on an MDIO-connected switch we will need to skip locking for built-in
-switches which are accessed via MMIO.
-Create helper functions which simplify that upcoming change.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 73 ++++++++++++++++++++--------------------
- 1 file changed, 36 insertions(+), 37 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -143,31 +143,40 @@ err:
- }
-
- static void
--core_write(struct mt7530_priv *priv, u32 reg, u32 val)
-+mt7530_mutex_lock(struct mt7530_priv *priv)
- {
-- struct mii_bus *bus = priv->bus;
-+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
-+}
-
-- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
-+static void
-+mt7530_mutex_unlock(struct mt7530_priv *priv)
-+{
-+ mutex_unlock(&priv->bus->mdio_lock);
-+}
-+
-+static void
-+core_write(struct mt7530_priv *priv, u32 reg, u32 val)
-+{
-+ mt7530_mutex_lock(priv);
-
- core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
-
-- mutex_unlock(&bus->mdio_lock);
-+ mt7530_mutex_unlock(priv);
- }
-
- static void
- core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
- {
-- struct mii_bus *bus = priv->bus;
- u32 val;
-
-- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ mt7530_mutex_lock(priv);
-
- val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
- val &= ~mask;
- val |= set;
- core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
-
-- mutex_unlock(&bus->mdio_lock);
-+ mt7530_mutex_unlock(priv);
- }
-
- static void
-@@ -264,13 +273,11 @@ mt7530_mii_read(struct mt7530_priv *priv
- static void
- mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
- {
-- struct mii_bus *bus = priv->bus;
--
-- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ mt7530_mutex_lock(priv);
-
- mt7530_mii_write(priv, reg, val);
-
-- mutex_unlock(&bus->mdio_lock);
-+ mt7530_mutex_unlock(priv);
- }
-
- static u32
-@@ -282,14 +289,13 @@ _mt7530_unlocked_read(struct mt7530_dumm
- static u32
- _mt7530_read(struct mt7530_dummy_poll *p)
- {
-- struct mii_bus *bus = p->priv->bus;
- u32 val;
-
-- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ mt7530_mutex_lock(p->priv);
-
- val = mt7530_mii_read(p->priv, p->reg);
-
-- mutex_unlock(&bus->mdio_lock);
-+ mt7530_mutex_unlock(p->priv);
-
- return val;
- }
-@@ -307,13 +313,11 @@ static void
- mt7530_rmw(struct mt7530_priv *priv, u32 reg,
- u32 mask, u32 set)
- {
-- struct mii_bus *bus = priv->bus;
--
-- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ mt7530_mutex_lock(priv);
-
- regmap_update_bits(priv->regmap, reg, mask, set);
-
-- mutex_unlock(&bus->mdio_lock);
-+ mt7530_mutex_unlock(priv);
- }
-
- static void
-@@ -645,14 +649,13 @@ static int
- mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
- int regnum)
- {
-- struct mii_bus *bus = priv->bus;
- struct mt7530_dummy_poll p;
- u32 reg, val;
- int ret;
-
- INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
-
-- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ mt7530_mutex_lock(priv);
-
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
- !(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -685,7 +688,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr
-
- ret = val & MT7531_MDIO_RW_DATA_MASK;
- out:
-- mutex_unlock(&bus->mdio_lock);
-+ mt7530_mutex_unlock(priv);
-
- return ret;
- }
-@@ -694,14 +697,13 @@ static int
- mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
- int regnum, u32 data)
- {
-- struct mii_bus *bus = priv->bus;
- struct mt7530_dummy_poll p;
- u32 val, reg;
- int ret;
-
- INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
-
-- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ mt7530_mutex_lock(priv);
-
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
- !(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -733,7 +735,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p
- }
-
- out:
-- mutex_unlock(&bus->mdio_lock);
-+ mt7530_mutex_unlock(priv);
-
- return ret;
- }
-@@ -741,14 +743,13 @@ out:
- static int
- mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
- {
-- struct mii_bus *bus = priv->bus;
- struct mt7530_dummy_poll p;
- int ret;
- u32 val;
-
- INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
-
-- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ mt7530_mutex_lock(priv);
-
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
- !(val & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -771,7 +772,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr
-
- ret = val & MT7531_MDIO_RW_DATA_MASK;
- out:
-- mutex_unlock(&bus->mdio_lock);
-+ mt7530_mutex_unlock(priv);
-
- return ret;
- }
-@@ -780,14 +781,13 @@ static int
- mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
- u16 data)
- {
-- struct mii_bus *bus = priv->bus;
- struct mt7530_dummy_poll p;
- int ret;
- u32 reg;
-
- INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
-
-- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ mt7530_mutex_lock(priv);
-
- ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
- !(reg & MT7531_PHY_ACS_ST), 20, 100000);
-@@ -809,7 +809,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p
- }
-
- out:
-- mutex_unlock(&bus->mdio_lock);
-+ mt7530_mutex_unlock(priv);
-
- return ret;
- }
-@@ -1125,7 +1125,6 @@ static int
- mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
- {
- struct mt7530_priv *priv = ds->priv;
-- struct mii_bus *bus = priv->bus;
- int length;
- u32 val;
-
-@@ -1136,7 +1135,7 @@ mt7530_port_change_mtu(struct dsa_switch
- if (!dsa_is_cpu_port(ds, port))
- return 0;
-
-- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ mt7530_mutex_lock(priv);
-
- val = mt7530_mii_read(priv, MT7530_GMACCR);
- val &= ~MAX_RX_PKT_LEN_MASK;
-@@ -1157,7 +1156,7 @@ mt7530_port_change_mtu(struct dsa_switch
-
- mt7530_mii_write(priv, MT7530_GMACCR, val);
-
-- mutex_unlock(&bus->mdio_lock);
-+ mt7530_mutex_unlock(priv);
-
- return 0;
- }
-@@ -1958,10 +1957,10 @@ mt7530_irq_thread_fn(int irq, void *dev_
- u32 val;
- int p;
-
-- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ mt7530_mutex_lock(priv);
- val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
- mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
-- mutex_unlock(&priv->bus->mdio_lock);
-+ mt7530_mutex_unlock(priv);
-
- for (p = 0; p < MT7530_NUM_PHYS; p++) {
- if (BIT(p) & val) {
-@@ -1997,7 +1996,7 @@ mt7530_irq_bus_lock(struct irq_data *d)
- {
- struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
-
-- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ mt7530_mutex_lock(priv);
- }
-
- static void
-@@ -2006,7 +2005,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da
- struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
-
- mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
-- mutex_unlock(&priv->bus->mdio_lock);
-+ mt7530_mutex_unlock(priv);
- }
-
- static struct irq_chip mt7530_irq_chip = {
+++ /dev/null
-From 0d7ae94a0c581f86939bebec0b6ccd66e640d1d8 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:18:28 +0100
-Subject: [PATCH 07/13] net: dsa: mt7530: move p5_intf_modes() function to
- mt7530.c
-
-In preparation of splitting mt7530.c into a driver for MDIO-connected
-as well as MDIO-accessed built-in switches on one hand and MMIO-accessed
-built-in switches move the p5_inft_modes() function from mt7530.h to
-mt7530.c. The function is only needed there and will trigger a compiler
-warning about a defined but unused function otherwise when including
-mt7530.h in the to-be-introduced bus-specific drivers.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 18 ++++++++++++++++++
- drivers/net/dsa/mt7530.h | 18 ------------------
- 2 files changed, 18 insertions(+), 18 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -950,6 +950,24 @@ mt7530_set_ageing_time(struct dsa_switch
- return 0;
- }
-
-+static const char *p5_intf_modes(unsigned int p5_interface)
-+{
-+ switch (p5_interface) {
-+ case P5_DISABLED:
-+ return "DISABLED";
-+ case P5_INTF_SEL_PHY_P0:
-+ return "PHY P0";
-+ case P5_INTF_SEL_PHY_P4:
-+ return "PHY P4";
-+ case P5_INTF_SEL_GMAC5:
-+ return "GMAC5";
-+ case P5_INTF_SEL_GMAC5_SGMII:
-+ return "GMAC5_SGMII";
-+ default:
-+ return "unknown";
-+ }
-+}
-+
- static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
- {
- struct mt7530_priv *priv = ds->priv;
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -689,24 +689,6 @@ enum p5_interface_select {
- P5_INTF_SEL_GMAC5_SGMII,
- };
-
--static const char *p5_intf_modes(unsigned int p5_interface)
--{
-- switch (p5_interface) {
-- case P5_DISABLED:
-- return "DISABLED";
-- case P5_INTF_SEL_PHY_P0:
-- return "PHY P0";
-- case P5_INTF_SEL_PHY_P4:
-- return "PHY P4";
-- case P5_INTF_SEL_GMAC5:
-- return "GMAC5";
-- case P5_INTF_SEL_GMAC5_SGMII:
-- return "GMAC5_SGMII";
-- default:
-- return "unknown";
-- }
--}
--
- struct mt7530_priv;
-
- struct mt753x_pcs {
+++ /dev/null
-From 4d632005c90e253c000d0db73b7cdb9d8dc2e2dd Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:18:39 +0100
-Subject: [PATCH 08/13] net: dsa: mt7530: introduce mt7530_probe_common helper
- function
-
-Move commonly used parts from mt7530_probe into new mt7530_probe_common
-helper function which will be used by both, mt7530_probe and the
-to-be-introduced mt7988_probe.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 98 ++++++++++++++++++++++------------------
- 1 file changed, 54 insertions(+), 44 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -3177,44 +3177,21 @@ static const struct of_device_id mt7530_
- MODULE_DEVICE_TABLE(of, mt7530_of_match);
-
- static int
--mt7530_probe(struct mdio_device *mdiodev)
-+mt7530_probe_common(struct mt7530_priv *priv)
- {
-- static struct regmap_config *regmap_config;
-- struct mt7530_priv *priv;
-- struct device_node *dn;
-- int ret;
-+ struct device *dev = priv->dev;
-
-- dn = mdiodev->dev.of_node;
--
-- priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
-- if (!priv)
-- return -ENOMEM;
--
-- priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
-+ priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
- if (!priv->ds)
- return -ENOMEM;
-
-- priv->ds->dev = &mdiodev->dev;
-+ priv->ds->dev = dev;
- priv->ds->num_ports = MT7530_NUM_PORTS;
-
-- /* Use medatek,mcm property to distinguish hardware type that would
-- * casues a little bit differences on power-on sequence.
-- */
-- priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
-- if (priv->mcm) {
-- dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
--
-- priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
-- if (IS_ERR(priv->rstc)) {
-- dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
-- return PTR_ERR(priv->rstc);
-- }
-- }
--
- /* Get the hardware identifier from the devicetree node.
- * We will need it for some of the clock and regulator setup.
- */
-- priv->info = of_device_get_match_data(&mdiodev->dev);
-+ priv->info = of_device_get_match_data(dev);
- if (!priv->info)
- return -EINVAL;
-
-@@ -3228,23 +3205,53 @@ mt7530_probe(struct mdio_device *mdiodev
- return -EINVAL;
-
- priv->id = priv->info->id;
-+ priv->dev = dev;
-+ priv->ds->priv = priv;
-+ priv->ds->ops = &mt7530_switch_ops;
-+ mutex_init(&priv->reg_mutex);
-+ dev_set_drvdata(dev, priv);
-
-- if (priv->id == ID_MT7530) {
-- priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
-- if (IS_ERR(priv->core_pwr))
-- return PTR_ERR(priv->core_pwr);
-+ return 0;
-+}
-
-- priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
-- if (IS_ERR(priv->io_pwr))
-- return PTR_ERR(priv->io_pwr);
-- }
-+static int
-+mt7530_probe(struct mdio_device *mdiodev)
-+{
-+ static struct regmap_config *regmap_config;
-+ struct mt7530_priv *priv;
-+ struct device_node *dn;
-+ int ret;
-+
-+ dn = mdiodev->dev.of_node;
-+
-+ priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-
-- /* Not MCM that indicates switch works as the remote standalone
-+ priv->bus = mdiodev->bus;
-+ priv->dev = &mdiodev->dev;
-+
-+ ret = mt7530_probe_common(priv);
-+ if (ret)
-+ return ret;
-+
-+ /* Use medatek,mcm property to distinguish hardware type that would
-+ * cause a little bit differences on power-on sequence.
-+ * Not MCM that indicates switch works as the remote standalone
- * integrated circuit so the GPIO pin would be used to complete
- * the reset, otherwise memory-mapped register accessing used
- * through syscon provides in the case of MCM.
- */
-- if (!priv->mcm) {
-+ priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
-+ if (priv->mcm) {
-+ dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
-+
-+ priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
-+ if (IS_ERR(priv->rstc)) {
-+ dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
-+ return PTR_ERR(priv->rstc);
-+ }
-+ } else {
- priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
- GPIOD_OUT_LOW);
- if (IS_ERR(priv->reset)) {
-@@ -3253,12 +3260,15 @@ mt7530_probe(struct mdio_device *mdiodev
- }
- }
-
-- priv->bus = mdiodev->bus;
-- priv->dev = &mdiodev->dev;
-- priv->ds->priv = priv;
-- priv->ds->ops = &mt7530_switch_ops;
-- mutex_init(&priv->reg_mutex);
-- dev_set_drvdata(&mdiodev->dev, priv);
-+ if (priv->id == ID_MT7530) {
-+ priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
-+ if (IS_ERR(priv->core_pwr))
-+ return PTR_ERR(priv->core_pwr);
-+
-+ priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
-+ if (IS_ERR(priv->io_pwr))
-+ return PTR_ERR(priv->io_pwr);
-+ }
-
- regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
- GFP_KERNEL);
+++ /dev/null
-From 69b838d2629e6b82bcd9e0ab3c1c03f46e5e01d3 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:18:50 +0100
-Subject: [PATCH 09/13] net: dsa: mt7530: introduce mt7530_remove_common helper
- function
-
-Move commonly used parts from mt7530_remove into new
-mt7530_remove_common helper function which will be used by both,
-mt7530_remove and the to-be-introduced mt7988_remove.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 18 ++++++++++++------
- 1 file changed, 12 insertions(+), 6 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -3295,6 +3295,17 @@ mt7530_probe(struct mdio_device *mdiodev
- }
-
- static void
-+mt7530_remove_common(struct mt7530_priv *priv)
-+{
-+ if (priv->irq)
-+ mt7530_free_irq(priv);
-+
-+ dsa_unregister_switch(priv->ds);
-+
-+ mutex_destroy(&priv->reg_mutex);
-+}
-+
-+static void
- mt7530_remove(struct mdio_device *mdiodev)
- {
- struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
-@@ -3313,15 +3324,10 @@ mt7530_remove(struct mdio_device *mdiode
- dev_err(priv->dev, "Failed to disable io pwr: %d\n",
- ret);
-
-- if (priv->irq)
-- mt7530_free_irq(priv);
--
-- dsa_unregister_switch(priv->ds);
-+ mt7530_remove_common(priv);
-
- for (i = 0; i < 2; ++i)
- mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
--
-- mutex_destroy(&priv->reg_mutex);
- }
-
- static void mt7530_shutdown(struct mdio_device *mdiodev)
+++ /dev/null
-From 8eceed6dbd74067dbf4d8e39f14734f4d2f35176 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:19:13 +0100
-Subject: [PATCH 10/13] net: dsa: mt7530: introduce separate MDIO driver
-
-Split MT7530 switch driver into a common part and a part specific
-for MDIO connected switches and multi-chip modules.
-Move MDIO-specific functions to newly introduced mt7530-mdio.c while
-keeping the common parts in mt7530.c.
-Introduce new Kconfig symbol CONFIG_NET_DSA_MT7530_MDIO which is
-implied by CONFIG_NET_DSA_MT7530.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- MAINTAINERS | 1 +
- drivers/net/dsa/Kconfig | 16 +-
- drivers/net/dsa/Makefile | 1 +
- drivers/net/dsa/mt7530-mdio.c | 271 ++++++++++++++++++++++++++++++++++
- drivers/net/dsa/mt7530.c | 264 +--------------------------------
- drivers/net/dsa/mt7530.h | 6 +
- 6 files changed, 301 insertions(+), 258 deletions(-)
- create mode 100644 drivers/net/dsa/mt7530-mdio.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -13069,6 +13069,7 @@ M: Landen Chao <Landen.Chao@mediatek.com
- M: DENG Qingfang <dqfext@gmail.com>
- L: netdev@vger.kernel.org
- S: Maintained
-+F: drivers/net/dsa/mt7530-mdio.c
- F: drivers/net/dsa/mt7530.*
- F: net/dsa/tag_mtk.c
-
---- a/drivers/net/dsa/Kconfig
-+++ b/drivers/net/dsa/Kconfig
-@@ -37,10 +37,22 @@ config NET_DSA_MT7530
- tristate "MediaTek MT753x and MT7621 Ethernet switch support"
- select NET_DSA_TAG_MTK
- select MEDIATEK_GE_PHY
-+ imply NET_DSA_MT7530_MDIO
-+ help
-+ This enables support for the MediaTek MT7530 and MT7531 Ethernet
-+ switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
-+ MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
-+ supported as well.
-+
-+config NET_DSA_MT7530_MDIO
-+ tristate "MediaTek MT7530 MDIO interface driver"
-+ depends on NET_DSA_MT7530
- select PCS_MTK_LYNXI
- help
-- This enables support for the MediaTek MT7530, MT7531, and MT7621
-- Ethernet switch chips.
-+ This enables support for the MediaTek MT7530 and MT7531 switch
-+ chips which are connected via MDIO, as well as multi-chip
-+ module MT7530 which can be found in the MT7621AT, MT7621DAT,
-+ MT7621ST and MT7623AI SoCs.
-
- config NET_DSA_MV88E6060
- tristate "Marvell 88E6060 ethernet switch chip support"
---- a/drivers/net/dsa/Makefile
-+++ b/drivers/net/dsa/Makefile
-@@ -7,6 +7,7 @@ obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdi
- endif
- obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
- obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
-+obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
- obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
- obj-$(CONFIG_NET_DSA_RZN1_A5PSW) += rzn1_a5psw.o
- obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
---- /dev/null
-+++ b/drivers/net/dsa/mt7530-mdio.c
-@@ -0,0 +1,271 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+#include <linux/gpio/consumer.h>
-+#include <linux/mdio.h>
-+#include <linux/module.h>
-+#include <linux/pcs/pcs-mtk-lynxi.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_mdio.h>
-+#include <linux/of_net.h>
-+#include <linux/of_platform.h>
-+#include <linux/regmap.h>
-+#include <linux/reset.h>
-+#include <linux/regulator/consumer.h>
-+#include <net/dsa.h>
-+
-+#include "mt7530.h"
-+
-+static int
-+mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
-+{
-+ struct mii_bus *bus = context;
-+ u16 page, r, lo, hi;
-+ int ret;
-+
-+ page = (reg >> 6) & 0x3ff;
-+ r = (reg >> 2) & 0xf;
-+ lo = val & 0xffff;
-+ hi = val >> 16;
-+
-+ /* MT7530 uses 31 as the pseudo port */
-+ ret = bus->write(bus, 0x1f, 0x1f, page);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = bus->write(bus, 0x1f, r, lo);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = bus->write(bus, 0x1f, 0x10, hi);
-+ return ret;
-+}
-+
-+static int
-+mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
-+{
-+ struct mii_bus *bus = context;
-+ u16 page, r, lo, hi;
-+ int ret;
-+
-+ page = (reg >> 6) & 0x3ff;
-+ r = (reg >> 2) & 0xf;
-+
-+ /* MT7530 uses 31 as the pseudo port */
-+ ret = bus->write(bus, 0x1f, 0x1f, page);
-+ if (ret < 0)
-+ return ret;
-+
-+ lo = bus->read(bus, 0x1f, r);
-+ hi = bus->read(bus, 0x1f, 0x10);
-+
-+ *val = (hi << 16) | (lo & 0xffff);
-+
-+ return 0;
-+}
-+
-+static void
-+mt7530_mdio_regmap_lock(void *mdio_lock)
-+{
-+ mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
-+}
-+
-+static void
-+mt7530_mdio_regmap_unlock(void *mdio_lock)
-+{
-+ mutex_unlock(mdio_lock);
-+}
-+
-+static const struct regmap_bus mt7530_regmap_bus = {
-+ .reg_write = mt7530_regmap_write,
-+ .reg_read = mt7530_regmap_read,
-+};
-+
-+static int
-+mt7531_create_sgmii(struct mt7530_priv *priv)
-+{
-+ struct regmap_config *mt7531_pcs_config[2];
-+ struct phylink_pcs *pcs;
-+ struct regmap *regmap;
-+ int i, ret = 0;
-+
-+ for (i = 0; i < 2; i++) {
-+ mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
-+ sizeof(struct regmap_config),
-+ GFP_KERNEL);
-+ if (!mt7531_pcs_config[i]) {
-+ ret = -ENOMEM;
-+ break;
-+ }
-+
-+ mt7531_pcs_config[i]->name = i ? "port6" : "port5";
-+ mt7531_pcs_config[i]->reg_bits = 16;
-+ mt7531_pcs_config[i]->val_bits = 32;
-+ mt7531_pcs_config[i]->reg_stride = 4;
-+ mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
-+ mt7531_pcs_config[i]->max_register = 0x17c;
-+ mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock;
-+ mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
-+ mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
-+
-+ regmap = devm_regmap_init(priv->dev,
-+ &mt7530_regmap_bus, priv->bus,
-+ mt7531_pcs_config[i]);
-+ if (IS_ERR(regmap)) {
-+ ret = PTR_ERR(regmap);
-+ break;
-+ }
-+ pcs = mtk_pcs_lynxi_create(priv->dev, regmap,
-+ MT7531_PHYA_CTRL_SIGNAL3, 0);
-+ if (!pcs) {
-+ ret = -ENXIO;
-+ break;
-+ }
-+ priv->ports[5 + i].sgmii_pcs = pcs;
-+ }
-+
-+ if (ret && i)
-+ mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs);
-+
-+ return ret;
-+}
-+
-+static const struct of_device_id mt7530_of_match[] = {
-+ { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
-+ { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
-+ { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
-+ { /* sentinel */ },
-+};
-+MODULE_DEVICE_TABLE(of, mt7530_of_match);
-+
-+static int
-+mt7530_probe(struct mdio_device *mdiodev)
-+{
-+ static struct regmap_config *regmap_config;
-+ struct mt7530_priv *priv;
-+ struct device_node *dn;
-+ int ret;
-+
-+ dn = mdiodev->dev.of_node;
-+
-+ priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->bus = mdiodev->bus;
-+ priv->dev = &mdiodev->dev;
-+
-+ ret = mt7530_probe_common(priv);
-+ if (ret)
-+ return ret;
-+
-+ /* Use medatek,mcm property to distinguish hardware type that would
-+ * cause a little bit differences on power-on sequence.
-+ * Not MCM that indicates switch works as the remote standalone
-+ * integrated circuit so the GPIO pin would be used to complete
-+ * the reset, otherwise memory-mapped register accessing used
-+ * through syscon provides in the case of MCM.
-+ */
-+ priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
-+ if (priv->mcm) {
-+ dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
-+
-+ priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
-+ if (IS_ERR(priv->rstc)) {
-+ dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
-+ return PTR_ERR(priv->rstc);
-+ }
-+ } else {
-+ priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
-+ GPIOD_OUT_LOW);
-+ if (IS_ERR(priv->reset)) {
-+ dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
-+ return PTR_ERR(priv->reset);
-+ }
-+ }
-+
-+ if (priv->id == ID_MT7530) {
-+ priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
-+ if (IS_ERR(priv->core_pwr))
-+ return PTR_ERR(priv->core_pwr);
-+
-+ priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
-+ if (IS_ERR(priv->io_pwr))
-+ return PTR_ERR(priv->io_pwr);
-+ }
-+
-+ regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
-+ GFP_KERNEL);
-+ if (!regmap_config)
-+ return -ENOMEM;
-+
-+ regmap_config->reg_bits = 16;
-+ regmap_config->val_bits = 32;
-+ regmap_config->reg_stride = 4;
-+ regmap_config->max_register = MT7530_CREV;
-+ regmap_config->disable_locking = true;
-+ priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
-+ priv->bus, regmap_config);
-+ if (IS_ERR(priv->regmap))
-+ return PTR_ERR(priv->regmap);
-+
-+ if (priv->id == ID_MT7531) {
-+ ret = mt7531_create_sgmii(priv);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ return dsa_register_switch(priv->ds);
-+}
-+
-+static void
-+mt7530_remove(struct mdio_device *mdiodev)
-+{
-+ struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
-+ int ret = 0, i;
-+
-+ if (!priv)
-+ return;
-+
-+ ret = regulator_disable(priv->core_pwr);
-+ if (ret < 0)
-+ dev_err(priv->dev,
-+ "Failed to disable core power: %d\n", ret);
-+
-+ ret = regulator_disable(priv->io_pwr);
-+ if (ret < 0)
-+ dev_err(priv->dev, "Failed to disable io pwr: %d\n",
-+ ret);
-+
-+ mt7530_remove_common(priv);
-+
-+ for (i = 0; i < 2; ++i)
-+ mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
-+}
-+
-+static void mt7530_shutdown(struct mdio_device *mdiodev)
-+{
-+ struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
-+
-+ if (!priv)
-+ return;
-+
-+ dsa_switch_shutdown(priv->ds);
-+
-+ dev_set_drvdata(&mdiodev->dev, NULL);
-+}
-+
-+static struct mdio_driver mt7530_mdio_driver = {
-+ .probe = mt7530_probe,
-+ .remove = mt7530_remove,
-+ .shutdown = mt7530_shutdown,
-+ .mdiodrv.driver = {
-+ .name = "mt7530-mdio",
-+ .of_match_table = mt7530_of_match,
-+ },
-+};
-+
-+mdio_module_driver(mt7530_mdio_driver);
-+
-+MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
-+MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch (MDIO)");
-+MODULE_LICENSE("GPL");
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -14,7 +14,6 @@
- #include <linux/of_mdio.h>
- #include <linux/of_net.h>
- #include <linux/of_platform.h>
--#include <linux/pcs/pcs-mtk-lynxi.h>
- #include <linux/phylink.h>
- #include <linux/regmap.h>
- #include <linux/regulator/consumer.h>
-@@ -192,31 +191,6 @@ core_clear(struct mt7530_priv *priv, u32
- }
-
- static int
--mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
--{
-- struct mii_bus *bus = context;
-- u16 page, r, lo, hi;
-- int ret;
--
-- page = (reg >> 6) & 0x3ff;
-- r = (reg >> 2) & 0xf;
-- lo = val & 0xffff;
-- hi = val >> 16;
--
-- /* MT7530 uses 31 as the pseudo port */
-- ret = bus->write(bus, 0x1f, 0x1f, page);
-- if (ret < 0)
-- return ret;
--
-- ret = bus->write(bus, 0x1f, r, lo);
-- if (ret < 0)
-- return ret;
--
-- ret = bus->write(bus, 0x1f, 0x10, hi);
-- return ret;
--}
--
--static int
- mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
- {
- int ret;
-@@ -230,29 +204,6 @@ mt7530_mii_write(struct mt7530_priv *pri
- return ret;
- }
-
--static int
--mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
--{
-- struct mii_bus *bus = context;
-- u16 page, r, lo, hi;
-- int ret;
--
-- page = (reg >> 6) & 0x3ff;
-- r = (reg >> 2) & 0xf;
--
-- /* MT7530 uses 31 as the pseudo port */
-- ret = bus->write(bus, 0x1f, 0x1f, page);
-- if (ret < 0)
-- return ret;
--
-- lo = bus->read(bus, 0x1f, r);
-- hi = bus->read(bus, 0x1f, 0x10);
--
-- *val = (hi << 16) | (lo & 0xffff);
--
-- return 0;
--}
--
- static u32
- mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
- {
-@@ -2975,72 +2926,6 @@ static const struct phylink_pcs_ops mt75
- .pcs_an_restart = mt7530_pcs_an_restart,
- };
-
--static void
--mt7530_mdio_regmap_lock(void *mdio_lock)
--{
-- mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
--}
--
--static void
--mt7530_mdio_regmap_unlock(void *mdio_lock)
--{
-- mutex_unlock(mdio_lock);
--}
--
--static const struct regmap_bus mt7530_regmap_bus = {
-- .reg_write = mt7530_regmap_write,
-- .reg_read = mt7530_regmap_read,
--};
--
--static int
--mt7531_create_sgmii(struct mt7530_priv *priv)
--{
-- struct regmap_config *mt7531_pcs_config[2];
-- struct phylink_pcs *pcs;
-- struct regmap *regmap;
-- int i, ret = 0;
--
-- for (i = 0; i < 2; i++) {
-- mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
-- sizeof(struct regmap_config),
-- GFP_KERNEL);
-- if (!mt7531_pcs_config[i]) {
-- ret = -ENOMEM;
-- break;
-- }
--
-- mt7531_pcs_config[i]->name = i ? "port6" : "port5";
-- mt7531_pcs_config[i]->reg_bits = 16;
-- mt7531_pcs_config[i]->val_bits = 32;
-- mt7531_pcs_config[i]->reg_stride = 4;
-- mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
-- mt7531_pcs_config[i]->max_register = 0x17c;
-- mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock;
-- mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
-- mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
--
-- regmap = devm_regmap_init(priv->dev,
-- &mt7530_regmap_bus, priv->bus,
-- mt7531_pcs_config[i]);
-- if (IS_ERR(regmap)) {
-- ret = PTR_ERR(regmap);
-- break;
-- }
-- pcs = mtk_pcs_lynxi_create(priv->dev, regmap,
-- MT7531_PHYA_CTRL_SIGNAL3, 0);
-- if (!pcs) {
-- ret = -ENXIO;
-- break;
-- }
-- priv->ports[5 + i].sgmii_pcs = pcs;
-- }
--
-- if (ret && i)
-- mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs);
--
-- return ret;
--}
--
- static int
- mt753x_setup(struct dsa_switch *ds)
- {
-@@ -3099,7 +2984,7 @@ static int mt753x_set_mac_eee(struct dsa
- return 0;
- }
-
--static const struct dsa_switch_ops mt7530_switch_ops = {
-+const struct dsa_switch_ops mt7530_switch_ops = {
- .get_tag_protocol = mtk_get_tag_protocol,
- .setup = mt753x_setup,
- .get_strings = mt7530_get_strings,
-@@ -3133,8 +3018,9 @@ static const struct dsa_switch_ops mt753
- .get_mac_eee = mt753x_get_mac_eee,
- .set_mac_eee = mt753x_set_mac_eee,
- };
-+EXPORT_SYMBOL_GPL(mt7530_switch_ops);
-
--static const struct mt753x_info mt753x_table[] = {
-+const struct mt753x_info mt753x_table[] = {
- [ID_MT7621] = {
- .id = ID_MT7621,
- .pcs_ops = &mt7530_pcs_ops,
-@@ -3167,16 +3053,9 @@ static const struct mt753x_info mt753x_t
- .mac_port_config = mt7531_mac_config,
- },
- };
-+EXPORT_SYMBOL_GPL(mt753x_table);
-
--static const struct of_device_id mt7530_of_match[] = {
-- { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
-- { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
-- { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
-- { /* sentinel */ },
--};
--MODULE_DEVICE_TABLE(of, mt7530_of_match);
--
--static int
-+int
- mt7530_probe_common(struct mt7530_priv *priv)
- {
- struct device *dev = priv->dev;
-@@ -3213,88 +3092,9 @@ mt7530_probe_common(struct mt7530_priv *
-
- return 0;
- }
-+EXPORT_SYMBOL_GPL(mt7530_probe_common);
-
--static int
--mt7530_probe(struct mdio_device *mdiodev)
--{
-- static struct regmap_config *regmap_config;
-- struct mt7530_priv *priv;
-- struct device_node *dn;
-- int ret;
--
-- dn = mdiodev->dev.of_node;
--
-- priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
-- if (!priv)
-- return -ENOMEM;
--
-- priv->bus = mdiodev->bus;
-- priv->dev = &mdiodev->dev;
--
-- ret = mt7530_probe_common(priv);
-- if (ret)
-- return ret;
--
-- /* Use medatek,mcm property to distinguish hardware type that would
-- * cause a little bit differences on power-on sequence.
-- * Not MCM that indicates switch works as the remote standalone
-- * integrated circuit so the GPIO pin would be used to complete
-- * the reset, otherwise memory-mapped register accessing used
-- * through syscon provides in the case of MCM.
-- */
-- priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
-- if (priv->mcm) {
-- dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
--
-- priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
-- if (IS_ERR(priv->rstc)) {
-- dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
-- return PTR_ERR(priv->rstc);
-- }
-- } else {
-- priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
-- GPIOD_OUT_LOW);
-- if (IS_ERR(priv->reset)) {
-- dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
-- return PTR_ERR(priv->reset);
-- }
-- }
--
-- if (priv->id == ID_MT7530) {
-- priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
-- if (IS_ERR(priv->core_pwr))
-- return PTR_ERR(priv->core_pwr);
--
-- priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
-- if (IS_ERR(priv->io_pwr))
-- return PTR_ERR(priv->io_pwr);
-- }
--
-- regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
-- GFP_KERNEL);
-- if (!regmap_config)
-- return -ENOMEM;
--
-- regmap_config->reg_bits = 16;
-- regmap_config->val_bits = 32;
-- regmap_config->reg_stride = 4;
-- regmap_config->max_register = MT7530_CREV;
-- regmap_config->disable_locking = true;
-- priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
-- priv->bus, regmap_config);
-- if (IS_ERR(priv->regmap))
-- return PTR_ERR(priv->regmap);
--
-- if (priv->id == ID_MT7531) {
-- ret = mt7531_create_sgmii(priv);
-- if (ret)
-- return ret;
-- }
--
-- return dsa_register_switch(priv->ds);
--}
--
--static void
-+void
- mt7530_remove_common(struct mt7530_priv *priv)
- {
- if (priv->irq)
-@@ -3304,55 +3104,7 @@ mt7530_remove_common(struct mt7530_priv
-
- mutex_destroy(&priv->reg_mutex);
- }
--
--static void
--mt7530_remove(struct mdio_device *mdiodev)
--{
-- struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
-- int ret = 0, i;
--
-- if (!priv)
-- return;
--
-- ret = regulator_disable(priv->core_pwr);
-- if (ret < 0)
-- dev_err(priv->dev,
-- "Failed to disable core power: %d\n", ret);
--
-- ret = regulator_disable(priv->io_pwr);
-- if (ret < 0)
-- dev_err(priv->dev, "Failed to disable io pwr: %d\n",
-- ret);
--
-- mt7530_remove_common(priv);
--
-- for (i = 0; i < 2; ++i)
-- mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
--}
--
--static void mt7530_shutdown(struct mdio_device *mdiodev)
--{
-- struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
--
-- if (!priv)
-- return;
--
-- dsa_switch_shutdown(priv->ds);
--
-- dev_set_drvdata(&mdiodev->dev, NULL);
--}
--
--static struct mdio_driver mt7530_mdio_driver = {
-- .probe = mt7530_probe,
-- .remove = mt7530_remove,
-- .shutdown = mt7530_shutdown,
-- .mdiodrv.driver = {
-- .name = "mt7530",
-- .of_match_table = mt7530_of_match,
-- },
--};
--
--mdio_module_driver(mt7530_mdio_driver);
-+EXPORT_SYMBOL_GPL(mt7530_remove_common);
-
- MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
- MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -814,4 +814,10 @@ static inline void INIT_MT7530_DUMMY_POL
- p->reg = reg;
- }
-
-+int mt7530_probe_common(struct mt7530_priv *priv);
-+void mt7530_remove_common(struct mt7530_priv *priv);
-+
-+extern const struct dsa_switch_ops mt7530_switch_ops;
-+extern const struct mt753x_info mt753x_table[];
-+
- #endif /* __MT7530_H */
+++ /dev/null
-From a52cadbf76593f8fcb2f4f62cb006e3f2a22ad06 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:19:28 +0100
-Subject: [PATCH 11/13] net: dsa: mt7530: skip locking if MDIO bus isn't
- present
-
-As MT7530 and MT7531 internally use 32-bit wide registers, each access
-to any register of the switch requires several operations on the MDIO
-bus. Hence if there is congruent access, e.g. due to PCS or PHY
-polling, this can mess up and interfere with another ongoing register
-access sequence.
-
-However, the MDIO bus mutex is only relevant for MDIO-connected
-switches. Prepare switches which have there registers directly mapped
-into the SoCs register space via MMIO which do not require such
-locking. There we can simply use regmap's default locking mechanism.
-
-Hence guard mutex operations to only be performed in case of MDIO
-connected switches.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mt7530.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -144,13 +144,15 @@ err:
- static void
- mt7530_mutex_lock(struct mt7530_priv *priv)
- {
-- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
-+ if (priv->bus)
-+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
- }
-
- static void
- mt7530_mutex_unlock(struct mt7530_priv *priv)
- {
-- mutex_unlock(&priv->bus->mdio_lock);
-+ if (priv->bus)
-+ mutex_unlock(&priv->bus->mdio_lock);
- }
-
- static void
+++ /dev/null
-From b361015763fedea439f13b336b15ef7bdf1f7d4f Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 3 Apr 2023 02:19:40 +0100
-Subject: [PATCH 12/13] net: dsa: mt7530: introduce driver for MT7988 built-in
- switch
-
-Add driver for the built-in Gigabit Ethernet switch which can be found
-in the MediaTek MT7988 SoC.
-
-The switch shares most of its design with MT7530 and MT7531, but has
-it's registers mapped into the SoCs register space rather than being
-connected externally or internally via MDIO.
-
-Introduce a new platform driver to support that.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- MAINTAINERS | 2 +
- drivers/net/dsa/Kconfig | 12 +++
- drivers/net/dsa/Makefile | 1 +
- drivers/net/dsa/mt7530-mmio.c | 101 +++++++++++++++++++++++++
- drivers/net/dsa/mt7530.c | 135 +++++++++++++++++++++++++++++++++-
- drivers/net/dsa/mt7530.h | 12 +--
- 6 files changed, 253 insertions(+), 10 deletions(-)
- create mode 100644 drivers/net/dsa/mt7530-mmio.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -13067,9 +13067,11 @@ MEDIATEK SWITCH DRIVER
- M: Sean Wang <sean.wang@mediatek.com>
- M: Landen Chao <Landen.Chao@mediatek.com>
- M: DENG Qingfang <dqfext@gmail.com>
-+M: Daniel Golle <daniel@makrotopia.org>
- L: netdev@vger.kernel.org
- S: Maintained
- F: drivers/net/dsa/mt7530-mdio.c
-+F: drivers/net/dsa/mt7530-mmio.c
- F: drivers/net/dsa/mt7530.*
- F: net/dsa/tag_mtk.c
-
---- a/drivers/net/dsa/Kconfig
-+++ b/drivers/net/dsa/Kconfig
-@@ -38,6 +38,7 @@ config NET_DSA_MT7530
- select NET_DSA_TAG_MTK
- select MEDIATEK_GE_PHY
- imply NET_DSA_MT7530_MDIO
-+ imply NET_DSA_MT7530_MMIO
- help
- This enables support for the MediaTek MT7530 and MT7531 Ethernet
- switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
-@@ -54,6 +55,17 @@ config NET_DSA_MT7530_MDIO
- module MT7530 which can be found in the MT7621AT, MT7621DAT,
- MT7621ST and MT7623AI SoCs.
-
-+config NET_DSA_MT7530_MMIO
-+ tristate "MediaTek MT7530 MMIO interface driver"
-+ depends on NET_DSA_MT7530
-+ depends on HAS_IOMEM
-+ help
-+ This enables support for the built-in Ethernet switch found
-+ in the MediaTek MT7988 SoC.
-+ The switch is a similar design as MT7531, but the switch registers
-+ are directly mapped into the SoCs register space rather than being
-+ accessible via MDIO.
-+
- config NET_DSA_MV88E6060
- tristate "Marvell 88E6060 ethernet switch chip support"
- select NET_DSA_TAG_TRAILER
---- a/drivers/net/dsa/Makefile
-+++ b/drivers/net/dsa/Makefile
-@@ -8,6 +8,7 @@ endif
- obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
- obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
- obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
-+obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o
- obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
- obj-$(CONFIG_NET_DSA_RZN1_A5PSW) += rzn1_a5psw.o
- obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
---- /dev/null
-+++ b/drivers/net/dsa/mt7530-mmio.c
-@@ -0,0 +1,101 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <net/dsa.h>
-+
-+#include "mt7530.h"
-+
-+static const struct of_device_id mt7988_of_match[] = {
-+ { .compatible = "mediatek,mt7988-switch", .data = &mt753x_table[ID_MT7988], },
-+ { /* sentinel */ },
-+};
-+MODULE_DEVICE_TABLE(of, mt7988_of_match);
-+
-+static int
-+mt7988_probe(struct platform_device *pdev)
-+{
-+ static struct regmap_config *sw_regmap_config;
-+ struct mt7530_priv *priv;
-+ void __iomem *base_addr;
-+ int ret;
-+
-+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->bus = NULL;
-+ priv->dev = &pdev->dev;
-+
-+ ret = mt7530_probe_common(priv);
-+ if (ret)
-+ return ret;
-+
-+ priv->rstc = devm_reset_control_get(&pdev->dev, NULL);
-+ if (IS_ERR(priv->rstc)) {
-+ dev_err(&pdev->dev, "Couldn't get our reset line\n");
-+ return PTR_ERR(priv->rstc);
-+ }
-+
-+ base_addr = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(base_addr)) {
-+ dev_err(&pdev->dev, "cannot request I/O memory space\n");
-+ return -ENXIO;
-+ }
-+
-+ sw_regmap_config = devm_kzalloc(&pdev->dev, sizeof(*sw_regmap_config), GFP_KERNEL);
-+ if (!sw_regmap_config)
-+ return -ENOMEM;
-+
-+ sw_regmap_config->name = "switch";
-+ sw_regmap_config->reg_bits = 16;
-+ sw_regmap_config->val_bits = 32;
-+ sw_regmap_config->reg_stride = 4;
-+ sw_regmap_config->max_register = MT7530_CREV;
-+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base_addr, sw_regmap_config);
-+ if (IS_ERR(priv->regmap))
-+ return PTR_ERR(priv->regmap);
-+
-+ return dsa_register_switch(priv->ds);
-+}
-+
-+static int
-+mt7988_remove(struct platform_device *pdev)
-+{
-+ struct mt7530_priv *priv = platform_get_drvdata(pdev);
-+
-+ if (priv)
-+ mt7530_remove_common(priv);
-+
-+ return 0;
-+}
-+
-+static void mt7988_shutdown(struct platform_device *pdev)
-+{
-+ struct mt7530_priv *priv = platform_get_drvdata(pdev);
-+
-+ if (!priv)
-+ return;
-+
-+ dsa_switch_shutdown(priv->ds);
-+
-+ dev_set_drvdata(&pdev->dev, NULL);
-+}
-+
-+static struct platform_driver mt7988_platform_driver = {
-+ .probe = mt7988_probe,
-+ .remove = mt7988_remove,
-+ .shutdown = mt7988_shutdown,
-+ .driver = {
-+ .name = "mt7530-mmio",
-+ .of_match_table = mt7988_of_match,
-+ },
-+};
-+module_platform_driver(mt7988_platform_driver);
-+
-+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
-+MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch (MMIO)");
-+MODULE_LICENSE("GPL");
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2005,6 +2005,47 @@ static const struct irq_domain_ops mt753
- };
-
- static void
-+mt7988_irq_mask(struct irq_data *d)
-+{
-+ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
-+
-+ priv->irq_enable &= ~BIT(d->hwirq);
-+ mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
-+}
-+
-+static void
-+mt7988_irq_unmask(struct irq_data *d)
-+{
-+ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
-+
-+ priv->irq_enable |= BIT(d->hwirq);
-+ mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
-+}
-+
-+static struct irq_chip mt7988_irq_chip = {
-+ .name = KBUILD_MODNAME,
-+ .irq_mask = mt7988_irq_mask,
-+ .irq_unmask = mt7988_irq_unmask,
-+};
-+
-+static int
-+mt7988_irq_map(struct irq_domain *domain, unsigned int irq,
-+ irq_hw_number_t hwirq)
-+{
-+ irq_set_chip_data(irq, domain->host_data);
-+ irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq);
-+ irq_set_nested_thread(irq, true);
-+ irq_set_noprobe(irq);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops mt7988_irq_domain_ops = {
-+ .map = mt7988_irq_map,
-+ .xlate = irq_domain_xlate_onecell,
-+};
-+
-+static void
- mt7530_setup_mdio_irq(struct mt7530_priv *priv)
- {
- struct dsa_switch *ds = priv->ds;
-@@ -2038,8 +2079,15 @@ mt7530_setup_irq(struct mt7530_priv *pri
- return priv->irq ? : -EINVAL;
- }
-
-- priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
-- &mt7530_irq_domain_ops, priv);
-+ if (priv->id == ID_MT7988)
-+ priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
-+ &mt7988_irq_domain_ops,
-+ priv);
-+ else
-+ priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
-+ &mt7530_irq_domain_ops,
-+ priv);
-+
- if (!priv->irq_domain) {
- dev_err(dev, "failed to create IRQ domain\n");
- return -ENOMEM;
-@@ -2538,6 +2586,25 @@ static void mt7531_mac_port_get_caps(str
- }
- }
-
-+static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
-+ struct phylink_config *config)
-+{
-+ phy_interface_zero(config->supported_interfaces);
-+
-+ switch (port) {
-+ case 0 ... 4: /* Internal phy */
-+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
-+ config->supported_interfaces);
-+ break;
-+
-+ case 6:
-+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
-+ config->supported_interfaces);
-+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
-+ MAC_10000FD;
-+ }
-+}
-+
- static int
- mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
- {
-@@ -2614,6 +2681,17 @@ static bool mt753x_is_mac_port(u32 port)
- }
-
- static int
-+mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
-+ phy_interface_t interface)
-+{
-+ if (dsa_is_cpu_port(ds, port) &&
-+ interface == PHY_INTERFACE_MODE_INTERNAL)
-+ return 0;
-+
-+ return -EINVAL;
-+}
-+
-+static int
- mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
- phy_interface_t interface)
- {
-@@ -2683,7 +2761,8 @@ mt753x_phylink_mac_config(struct dsa_swi
-
- switch (port) {
- case 0 ... 4: /* Internal phy */
-- if (state->interface != PHY_INTERFACE_MODE_GMII)
-+ if (state->interface != PHY_INTERFACE_MODE_GMII &&
-+ state->interface != PHY_INTERFACE_MODE_INTERNAL)
- goto unsupported;
- break;
- case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
-@@ -2761,7 +2840,8 @@ static void mt753x_phylink_mac_link_up(s
- /* MT753x MAC works in 1G full duplex mode for all up-clocked
- * variants.
- */
-- if (interface == PHY_INTERFACE_MODE_TRGMII ||
-+ if (interface == PHY_INTERFACE_MODE_INTERNAL ||
-+ interface == PHY_INTERFACE_MODE_TRGMII ||
- (phy_interface_mode_is_8023z(interface))) {
- speed = SPEED_1000;
- duplex = DUPLEX_FULL;
-@@ -2841,6 +2921,21 @@ mt7531_cpu_port_config(struct dsa_switch
- return 0;
- }
-
-+static int
-+mt7988_cpu_port_config(struct dsa_switch *ds, int port)
-+{
-+ struct mt7530_priv *priv = ds->priv;
-+
-+ mt7530_write(priv, MT7530_PMCR_P(port),
-+ PMCR_CPU_PORT_SETTING(priv->id));
-+
-+ mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED,
-+ PHY_INTERFACE_MODE_INTERNAL, NULL,
-+ SPEED_10000, DUPLEX_FULL, true, true);
-+
-+ return 0;
-+}
-+
- static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
- struct phylink_config *config)
- {
-@@ -2986,6 +3081,27 @@ static int mt753x_set_mac_eee(struct dsa
- return 0;
- }
-
-+static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
-+{
-+ return 0;
-+}
-+
-+static int mt7988_setup(struct dsa_switch *ds)
-+{
-+ struct mt7530_priv *priv = ds->priv;
-+
-+ /* Reset the switch */
-+ reset_control_assert(priv->rstc);
-+ usleep_range(20, 50);
-+ reset_control_deassert(priv->rstc);
-+ usleep_range(20, 50);
-+
-+ /* Reset the switch PHYs */
-+ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);
-+
-+ return mt7531_setup_common(ds);
-+}
-+
- const struct dsa_switch_ops mt7530_switch_ops = {
- .get_tag_protocol = mtk_get_tag_protocol,
- .setup = mt753x_setup,
-@@ -3054,6 +3170,17 @@ const struct mt753x_info mt753x_table[]
- .mac_port_get_caps = mt7531_mac_port_get_caps,
- .mac_port_config = mt7531_mac_config,
- },
-+ [ID_MT7988] = {
-+ .id = ID_MT7988,
-+ .pcs_ops = &mt7530_pcs_ops,
-+ .sw_setup = mt7988_setup,
-+ .phy_read = mt7531_ind_phy_read,
-+ .phy_write = mt7531_ind_phy_write,
-+ .pad_setup = mt7988_pad_setup,
-+ .cpu_port_config = mt7988_cpu_port_config,
-+ .mac_port_get_caps = mt7988_mac_port_get_caps,
-+ .mac_port_config = mt7988_mac_config,
-+ },
- };
- EXPORT_SYMBOL_GPL(mt753x_table);
-
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -18,6 +18,7 @@ enum mt753x_id {
- ID_MT7530 = 0,
- ID_MT7621 = 1,
- ID_MT7531 = 2,
-+ ID_MT7988 = 3,
- };
-
- #define NUM_TRGMII_CTRL 5
-@@ -54,11 +55,11 @@ enum mt753x_id {
- #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
- #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
-
--#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
-+#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
- MT7531_CFC : MT7530_MFC)
--#define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
-+#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
- MT7531_MIRROR_EN : MIRROR_EN)
--#define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
-+#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
- MT7531_MIRROR_MASK : MIRROR_MASK)
-
- /* Registers for BPDU and PAE frame control*/
-@@ -302,9 +303,8 @@ enum mt7530_vlan_port_acc_frm {
- MT7531_FORCE_DPX | \
- MT7531_FORCE_RX_FC | \
- MT7531_FORCE_TX_FC)
--#define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
-- MT7531_FORCE_MODE : \
-- PMCR_FORCE_MODE)
-+#define PMCR_FORCE_MODE_ID(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
-+ MT7531_FORCE_MODE : PMCR_FORCE_MODE)
- #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
- PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
+++ /dev/null
-From eb1dd407b4be7ca38166a38c56c8edf52c6a399f Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 16 Apr 2023 13:08:14 +0100
-Subject: [PATCH 13/13] net: dsa: mt7530: fix support for MT7531BE
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There are two variants of the MT7531 switch IC which got different
-features (and pins) regarding port 5:
- * MT7531AE: SGMII/1000Base-X/2500Base-X SerDes PCS
- * MT7531BE: RGMII
-
-Moving the creation of the SerDes PCS from mt753x_setup to mt7530_probe
-with commit 6de285229773 ("net: dsa: mt7530: move SGMII PCS creation
-to mt7530_probe function") works fine for MT7531AE which got two
-instances of mtk-pcs-lynxi, however, MT7531BE requires mt7531_pll_setup
-to setup clocks before the single PCS on port 6 (usually used as CPU
-port) starts to work and hence the PCS creation failed on MT7531BE.
-
-Fix this by introducing a pointer to mt7531_create_sgmii function in
-struct mt7530_priv and call it again at the end of mt753x_setup like it
-was before commit 6de285229773 ("net: dsa: mt7530: move SGMII PCS
-creation to mt7530_probe function").
-
-Fixes: 6de285229773 ("net: dsa: mt7530: move SGMII PCS creation to mt7530_probe function")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Acked-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Link: https://lore.kernel.org/r/ZDvlLhhqheobUvOK@makrotopia.org
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/dsa/mt7530-mdio.c | 16 ++++++++--------
- drivers/net/dsa/mt7530.c | 6 ++++++
- drivers/net/dsa/mt7530.h | 4 ++--
- 3 files changed, 16 insertions(+), 10 deletions(-)
-
---- a/drivers/net/dsa/mt7530-mdio.c
-+++ b/drivers/net/dsa/mt7530-mdio.c
-@@ -81,14 +81,17 @@ static const struct regmap_bus mt7530_re
- };
-
- static int
--mt7531_create_sgmii(struct mt7530_priv *priv)
-+mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii)
- {
-- struct regmap_config *mt7531_pcs_config[2];
-+ struct regmap_config *mt7531_pcs_config[2] = {};
- struct phylink_pcs *pcs;
- struct regmap *regmap;
- int i, ret = 0;
-
-- for (i = 0; i < 2; i++) {
-+ /* MT7531AE has two SGMII units for port 5 and port 6
-+ * MT7531BE has only one SGMII unit for port 6
-+ */
-+ for (i = dual_sgmii ? 0 : 1; i < 2; i++) {
- mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
- sizeof(struct regmap_config),
- GFP_KERNEL);
-@@ -208,11 +211,8 @@ mt7530_probe(struct mdio_device *mdiodev
- if (IS_ERR(priv->regmap))
- return PTR_ERR(priv->regmap);
-
-- if (priv->id == ID_MT7531) {
-- ret = mt7531_create_sgmii(priv);
-- if (ret)
-- return ret;
-- }
-+ if (priv->id == ID_MT7531)
-+ priv->create_sgmii = mt7531_create_sgmii;
-
- return dsa_register_switch(priv->ds);
- }
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -3048,6 +3048,12 @@ mt753x_setup(struct dsa_switch *ds)
- if (ret && priv->irq)
- mt7530_free_irq_common(priv);
-
-+ if (priv->create_sgmii) {
-+ ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv));
-+ if (ret && priv->irq)
-+ mt7530_free_irq(priv);
-+ }
-+
- return ret;
- }
-
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -748,10 +748,10 @@ struct mt753x_info {
- * registers
- * @p6_interface Holding the current port 6 interface
- * @p5_intf_sel: Holding the current port 5 interface select
-- *
- * @irq: IRQ number of the switch
- * @irq_domain: IRQ domain of the switch irq_chip
- * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
-+ * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
- */
- struct mt7530_priv {
- struct device *dev;
-@@ -770,7 +770,6 @@ struct mt7530_priv {
- unsigned int p5_intf_sel;
- u8 mirror_rx;
- u8 mirror_tx;
--
- struct mt7530_port ports[MT7530_NUM_PORTS];
- struct mt753x_pcs pcs[MT7530_NUM_PORTS];
- /* protect among processes for registers access*/
-@@ -778,6 +777,7 @@ struct mt7530_priv {
- int irq;
- struct irq_domain *irq_domain;
- u32 irq_enable;
-+ int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
- };
-
- struct mt7530_hw_vlan_entry {
--- /dev/null
+From 2203718c2f59ffdd6c78d54e5add594aebb4461e Mon Sep 17 00:00:00 2001
+From: Georgi Valkov <gvalkov@gmail.com>
+Date: Wed, 7 Jun 2023 15:56:59 +0200
+Subject: [PATCH 1/4] usbnet: ipheth: fix risk of NULL pointer deallocation
+
+The cleanup precedure in ipheth_probe will attempt to free a
+NULL pointer in dev->ctrl_buf if the memory allocation for
+this buffer is not successful. While kfree ignores NULL pointers,
+and the existing code is safe, it is a better design to rearrange
+the goto labels and avoid this.
+
+Signed-off-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -510,8 +510,8 @@ err_register_netdev:
+ ipheth_free_urbs(dev);
+ err_alloc_urbs:
+ err_get_macaddr:
+-err_alloc_ctrl_buf:
+ kfree(dev->ctrl_buf);
++err_alloc_ctrl_buf:
+ err_endpoints:
+ free_netdev(netdev);
+ return retval;
--- /dev/null
+From 3e65efcca87a9bb5f3b864e0a43d167bc0a8688c Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:00 +0200
+Subject: [PATCH 2/4] usbnet: ipheth: transmit URBs without trailing padding
+
+The behaviour of the official iOS tethering driver on macOS is to not
+transmit any trailing padding at the end of URBs. This is applicable
+to both NCM and legacy modes, including older devices.
+
+Adapt the driver to not include trailing padding in TX URBs, matching
+the behaviour of the official macOS driver.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Tested-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -373,12 +373,10 @@ static netdev_tx_t ipheth_tx(struct sk_b
+ }
+
+ memcpy(dev->tx_buf, skb->data, skb->len);
+- if (skb->len < IPHETH_BUF_SIZE)
+- memset(dev->tx_buf + skb->len, 0, IPHETH_BUF_SIZE - skb->len);
+
+ usb_fill_bulk_urb(dev->tx_urb, udev,
+ usb_sndbulkpipe(udev, dev->bulk_out),
+- dev->tx_buf, IPHETH_BUF_SIZE,
++ dev->tx_buf, skb->len,
+ ipheth_sndbulk_callback,
+ dev);
+ dev->tx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
--- /dev/null
+From a2d274c62e44b1995c170595db3865c6fe701226 Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:01 +0200
+Subject: [PATCH 3/4] usbnet: ipheth: add CDC NCM support
+
+Recent iOS releases support CDC NCM encapsulation on RX. This mode is
+the default on macOS and Windows. In this mode, an iOS device may include
+one or more Ethernet frames inside a single URB.
+
+Freshly booted iOS devices start in legacy mode, but are put into
+NCM mode by the official Apple driver. When reconnecting such a device
+from a macOS/Windows machine to a Linux host, the device stays in
+NCM mode, making it unusable with the legacy ipheth driver code.
+
+To correctly support such a device, the driver has to either support
+the NCM mode too, or put the device back into legacy mode.
+
+To match the behaviour of the macOS/Windows driver, and since there
+is no documented control command to revert to legacy mode, implement
+NCM support. The device is attempted to be put into NCM mode by default,
+and falls back to legacy mode if the attempt fails.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Tested-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 180 +++++++++++++++++++++++++++++++++------
+ 1 file changed, 155 insertions(+), 25 deletions(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -52,6 +52,7 @@
+ #include <linux/ethtool.h>
+ #include <linux/usb.h>
+ #include <linux/workqueue.h>
++#include <linux/usb/cdc.h>
+
+ #define USB_VENDOR_APPLE 0x05ac
+
+@@ -59,8 +60,12 @@
+ #define IPHETH_USBINTF_SUBCLASS 253
+ #define IPHETH_USBINTF_PROTO 1
+
+-#define IPHETH_BUF_SIZE 1514
+ #define IPHETH_IP_ALIGN 2 /* padding at front of URB */
++#define IPHETH_NCM_HEADER_SIZE (12 + 96) /* NCMH + NCM0 */
++#define IPHETH_TX_BUF_SIZE ETH_FRAME_LEN
++#define IPHETH_RX_BUF_SIZE_LEGACY (IPHETH_IP_ALIGN + ETH_FRAME_LEN)
++#define IPHETH_RX_BUF_SIZE_NCM 65536
++
+ #define IPHETH_TX_TIMEOUT (5 * HZ)
+
+ #define IPHETH_INTFNUM 2
+@@ -71,6 +76,7 @@
+ #define IPHETH_CTRL_TIMEOUT (5 * HZ)
+
+ #define IPHETH_CMD_GET_MACADDR 0x00
++#define IPHETH_CMD_ENABLE_NCM 0x04
+ #define IPHETH_CMD_CARRIER_CHECK 0x45
+
+ #define IPHETH_CARRIER_CHECK_TIMEOUT round_jiffies_relative(1 * HZ)
+@@ -97,6 +103,8 @@ struct ipheth_device {
+ u8 bulk_out;
+ struct delayed_work carrier_work;
+ bool confirmed_pairing;
++ int (*rcvbulk_callback)(struct urb *urb);
++ size_t rx_buf_len;
+ };
+
+ static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags);
+@@ -116,12 +124,12 @@ static int ipheth_alloc_urbs(struct iphe
+ if (rx_urb == NULL)
+ goto free_tx_urb;
+
+- tx_buf = usb_alloc_coherent(iphone->udev, IPHETH_BUF_SIZE,
++ tx_buf = usb_alloc_coherent(iphone->udev, IPHETH_TX_BUF_SIZE,
+ GFP_KERNEL, &tx_urb->transfer_dma);
+ if (tx_buf == NULL)
+ goto free_rx_urb;
+
+- rx_buf = usb_alloc_coherent(iphone->udev, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN,
++ rx_buf = usb_alloc_coherent(iphone->udev, iphone->rx_buf_len,
+ GFP_KERNEL, &rx_urb->transfer_dma);
+ if (rx_buf == NULL)
+ goto free_tx_buf;
+@@ -134,7 +142,7 @@ static int ipheth_alloc_urbs(struct iphe
+ return 0;
+
+ free_tx_buf:
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE, tx_buf,
++ usb_free_coherent(iphone->udev, IPHETH_TX_BUF_SIZE, tx_buf,
+ tx_urb->transfer_dma);
+ free_rx_urb:
+ usb_free_urb(rx_urb);
+@@ -146,9 +154,9 @@ error_nomem:
+
+ static void ipheth_free_urbs(struct ipheth_device *iphone)
+ {
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN, iphone->rx_buf,
++ usb_free_coherent(iphone->udev, iphone->rx_buf_len, iphone->rx_buf,
+ iphone->rx_urb->transfer_dma);
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE, iphone->tx_buf,
++ usb_free_coherent(iphone->udev, IPHETH_TX_BUF_SIZE, iphone->tx_buf,
+ iphone->tx_urb->transfer_dma);
+ usb_free_urb(iphone->rx_urb);
+ usb_free_urb(iphone->tx_urb);
+@@ -160,15 +168,106 @@ static void ipheth_kill_urbs(struct iphe
+ usb_kill_urb(dev->rx_urb);
+ }
+
+-static void ipheth_rcvbulk_callback(struct urb *urb)
++static int ipheth_consume_skb(char *buf, int len, struct ipheth_device *dev)
+ {
+- struct ipheth_device *dev;
+ struct sk_buff *skb;
+- int status;
++
++ skb = dev_alloc_skb(len);
++ if (!skb) {
++ dev->net->stats.rx_dropped++;
++ return -ENOMEM;
++ }
++
++ skb_put_data(skb, buf, len);
++ skb->dev = dev->net;
++ skb->protocol = eth_type_trans(skb, dev->net);
++
++ dev->net->stats.rx_packets++;
++ dev->net->stats.rx_bytes += len;
++ netif_rx(skb);
++
++ return 0;
++}
++
++static int ipheth_rcvbulk_callback_legacy(struct urb *urb)
++{
++ struct ipheth_device *dev;
++ char *buf;
++ int len;
++
++ dev = urb->context;
++
++ if (urb->actual_length <= IPHETH_IP_ALIGN) {
++ dev->net->stats.rx_length_errors++;
++ return -EINVAL;
++ }
++ len = urb->actual_length - IPHETH_IP_ALIGN;
++ buf = urb->transfer_buffer + IPHETH_IP_ALIGN;
++
++ return ipheth_consume_skb(buf, len, dev);
++}
++
++static int ipheth_rcvbulk_callback_ncm(struct urb *urb)
++{
++ struct usb_cdc_ncm_nth16 *ncmh;
++ struct usb_cdc_ncm_ndp16 *ncm0;
++ struct usb_cdc_ncm_dpe16 *dpe;
++ struct ipheth_device *dev;
++ int retval = -EINVAL;
+ char *buf;
+ int len;
+
+ dev = urb->context;
++
++ if (urb->actual_length < IPHETH_NCM_HEADER_SIZE) {
++ dev->net->stats.rx_length_errors++;
++ return retval;
++ }
++
++ ncmh = urb->transfer_buffer;
++ if (ncmh->dwSignature != cpu_to_le32(USB_CDC_NCM_NTH16_SIGN) ||
++ le16_to_cpu(ncmh->wNdpIndex) >= urb->actual_length) {
++ dev->net->stats.rx_errors++;
++ return retval;
++ }
++
++ ncm0 = urb->transfer_buffer + le16_to_cpu(ncmh->wNdpIndex);
++ if (ncm0->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN) ||
++ le16_to_cpu(ncmh->wHeaderLength) + le16_to_cpu(ncm0->wLength) >=
++ urb->actual_length) {
++ dev->net->stats.rx_errors++;
++ return retval;
++ }
++
++ dpe = ncm0->dpe16;
++ while (le16_to_cpu(dpe->wDatagramIndex) != 0 &&
++ le16_to_cpu(dpe->wDatagramLength) != 0) {
++ if (le16_to_cpu(dpe->wDatagramIndex) >= urb->actual_length ||
++ le16_to_cpu(dpe->wDatagramIndex) +
++ le16_to_cpu(dpe->wDatagramLength) > urb->actual_length) {
++ dev->net->stats.rx_length_errors++;
++ return retval;
++ }
++
++ buf = urb->transfer_buffer + le16_to_cpu(dpe->wDatagramIndex);
++ len = le16_to_cpu(dpe->wDatagramLength);
++
++ retval = ipheth_consume_skb(buf, len, dev);
++ if (retval != 0)
++ return retval;
++
++ dpe++;
++ }
++
++ return 0;
++}
++
++static void ipheth_rcvbulk_callback(struct urb *urb)
++{
++ struct ipheth_device *dev;
++ int retval, status;
++
++ dev = urb->context;
+ if (dev == NULL)
+ return;
+
+@@ -191,25 +290,27 @@ static void ipheth_rcvbulk_callback(stru
+ dev->net->stats.rx_length_errors++;
+ return;
+ }
+- len = urb->actual_length - IPHETH_IP_ALIGN;
+- buf = urb->transfer_buffer + IPHETH_IP_ALIGN;
+
+- skb = dev_alloc_skb(len);
+- if (!skb) {
+- dev_err(&dev->intf->dev, "%s: dev_alloc_skb: -ENOMEM\n",
+- __func__);
+- dev->net->stats.rx_dropped++;
++ /* RX URBs starting with 0x00 0x01 do not encapsulate Ethernet frames,
++ * but rather are control frames. Their purpose is not documented, and
++ * they don't affect driver functionality, okay to drop them.
++ * There is usually just one 4-byte control frame as the very first
++ * URB received from the bulk IN endpoint.
++ */
++ if (unlikely
++ (((char *)urb->transfer_buffer)[0] == 0 &&
++ ((char *)urb->transfer_buffer)[1] == 1))
++ goto rx_submit;
++
++ retval = dev->rcvbulk_callback(urb);
++ if (retval != 0) {
++ dev_err(&dev->intf->dev, "%s: callback retval: %d\n",
++ __func__, retval);
+ return;
+ }
+
+- skb_put_data(skb, buf, len);
+- skb->dev = dev->net;
+- skb->protocol = eth_type_trans(skb, dev->net);
+-
+- dev->net->stats.rx_packets++;
+- dev->net->stats.rx_bytes += len;
++rx_submit:
+ dev->confirmed_pairing = true;
+- netif_rx(skb);
+ ipheth_rx_submit(dev, GFP_ATOMIC);
+ }
+
+@@ -310,6 +411,27 @@ static int ipheth_get_macaddr(struct iph
+ return retval;
+ }
+
++static int ipheth_enable_ncm(struct ipheth_device *dev)
++{
++ struct usb_device *udev = dev->udev;
++ int retval;
++
++ retval = usb_control_msg(udev,
++ usb_sndctrlpipe(udev, IPHETH_CTRL_ENDP),
++ IPHETH_CMD_ENABLE_NCM, /* request */
++ 0x41, /* request type */
++ 0x00, /* value */
++ 0x02, /* index */
++ NULL,
++ 0,
++ IPHETH_CTRL_TIMEOUT);
++
++ dev_info(&dev->intf->dev, "%s: usb_control_msg: %d\n",
++ __func__, retval);
++
++ return retval;
++}
++
+ static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags)
+ {
+ struct usb_device *udev = dev->udev;
+@@ -317,7 +439,7 @@ static int ipheth_rx_submit(struct iphet
+
+ usb_fill_bulk_urb(dev->rx_urb, udev,
+ usb_rcvbulkpipe(udev, dev->bulk_in),
+- dev->rx_buf, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN,
++ dev->rx_buf, dev->rx_buf_len,
+ ipheth_rcvbulk_callback,
+ dev);
+ dev->rx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
+@@ -365,7 +487,7 @@ static netdev_tx_t ipheth_tx(struct sk_b
+ int retval;
+
+ /* Paranoid */
+- if (skb->len > IPHETH_BUF_SIZE) {
++ if (skb->len > IPHETH_TX_BUF_SIZE) {
+ WARN(1, "%s: skb too large: %d bytes\n", __func__, skb->len);
+ dev->net->stats.tx_dropped++;
+ dev_kfree_skb_any(skb);
+@@ -448,6 +570,8 @@ static int ipheth_probe(struct usb_inter
+ dev->net = netdev;
+ dev->intf = intf;
+ dev->confirmed_pairing = false;
++ dev->rx_buf_len = IPHETH_RX_BUF_SIZE_LEGACY;
++ dev->rcvbulk_callback = ipheth_rcvbulk_callback_legacy;
+ /* Set up endpoints */
+ hintf = usb_altnum_to_altsetting(intf, IPHETH_ALT_INTFNUM);
+ if (hintf == NULL) {
+@@ -479,6 +603,12 @@ static int ipheth_probe(struct usb_inter
+ if (retval)
+ goto err_get_macaddr;
+
++ retval = ipheth_enable_ncm(dev);
++ if (!retval) {
++ dev->rx_buf_len = IPHETH_RX_BUF_SIZE_NCM;
++ dev->rcvbulk_callback = ipheth_rcvbulk_callback_ncm;
++ }
++
+ INIT_DELAYED_WORK(&dev->carrier_work, ipheth_carrier_check_work);
+
+ retval = ipheth_alloc_urbs(dev);
--- /dev/null
+From 0c6e9d32ef0ccfcf2d875cbcff23bf345a54d585 Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:02 +0200
+Subject: [PATCH 4/4] usbnet: ipheth: update Kconfig description
+
+This module has for a long time not been limited to iPhone <= 3GS.
+Update description to match the actual state of the driver.
+
+Remove dead link from 2010, instead reference an existing userspace
+iOS device pairing implementation as part of libimobiledevice.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/Kconfig | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/usb/Kconfig
++++ b/drivers/net/usb/Kconfig
+@@ -583,12 +583,10 @@ config USB_IPHETH
+ default n
+ help
+ Module used to share Internet connection (tethering) from your
+- iPhone (Original, 3G and 3GS) to your system.
+- Note that you need userspace libraries and programs that are needed
+- to pair your device with your system and that understand the iPhone
+- protocol.
+-
+- For more information: http://giagio.com/wiki/moin.cgi/iPhoneEthernetDriver
++ iPhone to your system.
++ Note that you need a corresponding userspace library/program
++ to pair your device with your system, for example usbmuxd
++ <https://github.com/libimobiledevice/usbmuxd>.
+
+ config USB_SIERRA_NET
+ tristate "USB-to-WWAN Driver for Sierra Wireless modems"
--- /dev/null
+From b3f1a164c7f742503dc7159011f7ad6b092b660e Mon Sep 17 00:00:00 2001
+From: Greg Ungerer <gerg@kernel.org>
+Date: Fri, 24 Nov 2023 14:15:28 +1000
+Subject: [PATCH] net: dsa: mv88e6xxx: fix marvell 6350 switch probing
+
+As of commit de5c9bf40c45 ("net: phylink: require supported_interfaces to
+be filled") Marvell 88e6350 switches fail to be probed:
+
+ ...
+ mv88e6085 d0072004.mdio-mii:11: switch 0x3710 detected: Marvell 88E6350, revision 2
+ mv88e6085 d0072004.mdio-mii:11: phylink: error: empty supported_interfaces
+ error creating PHYLINK: -22
+ mv88e6085: probe of d0072004.mdio-mii:11 failed with error -22
+ ...
+
+The problem stems from the use of mv88e6185_phylink_get_caps() to get
+the device capabilities. Create a new dedicated phylink_get_caps for the
+6351 family (which the 6350 is one of) to properly support their set of
+capabilities.
+
+According to chip.h the 6351 switch family includes the 6171, 6175, 6350
+and 6351 switches, so update each of these to use the correct
+phylink_get_caps.
+
+Fixes: de5c9bf40c45 ("net: phylink: require supported_interfaces to be filled")
+Signed-off-by: Greg Ungerer <gerg@kernel.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mv88e6xxx/chip.c | 20 ++++++++++++++++----
+ 1 file changed, 16 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mv88e6xxx/chip.c
++++ b/drivers/net/dsa/mv88e6xxx/chip.c
+@@ -652,6 +652,18 @@ static void mv88e6250_phylink_get_caps(s
+ config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
+ }
+
++static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
++ struct phylink_config *config)
++{
++ unsigned long *supported = config->supported_interfaces;
++
++ /* Translate the default cmode */
++ mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
++
++ config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
++ MAC_1000FD;
++}
++
+ static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
+ {
+ u16 reg, val;
+@@ -4489,7 +4501,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .stu_getnext = mv88e6352_g1_stu_getnext,
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6172_ops = {
+@@ -4590,7 +4602,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .stu_getnext = mv88e6352_g1_stu_getnext,
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6176_ops = {
+@@ -5247,7 +5259,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .stu_getnext = mv88e6352_g1_stu_getnext,
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6351_ops = {
+@@ -5293,7 +5305,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+ .avb_ops = &mv88e6352_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6352_ops = {
--- /dev/null
+From 71e79430117d56c409c5ea485a263bc0d8083390 Mon Sep 17 00:00:00 2001
+From: Eric Woudstra <ericwouds@gmail.com>
+Date: Tue, 26 Mar 2024 17:23:05 +0100
+Subject: [PATCH] net: phy: air_en8811h: Add the Airoha EN8811H PHY driver
+
+Add the driver for the Airoha EN8811H 2.5 Gigabit PHY. The phy supports
+100/1000/2500 Mbps with auto negotiation only.
+
+The driver uses two firmware files, for which updated versions are added to
+linux-firmware already.
+
+Note: At phy-address + 8 there is another device on the mdio bus, that
+belongs to the EN881H. While the original driver writes to it, Airoha
+has confirmed this is not needed. Therefore, communication with this
+device is not included in this driver.
+
+Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240326162305.303598-3-ericwouds@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/Kconfig | 5 +
+ drivers/net/phy/Makefile | 1 +
+ drivers/net/phy/air_en8811h.c | 1086 +++++++++++++++++++++++++++++++++
+ 3 files changed, 1092 insertions(+)
+ create mode 100644 drivers/net/phy/air_en8811h.c
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -63,6 +63,11 @@ config SFP
+
+ comment "MII PHY device drivers"
+
++config AIR_EN8811H_PHY
++ tristate "Airoha EN8811H 2.5 Gigabit PHY"
++ help
++ Currently supports the Airoha EN8811H PHY.
++
+ config AMD_PHY
+ tristate "AMD PHYs"
+ help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -32,6 +32,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
+
+ obj-$(CONFIG_ADIN_PHY) += adin.o
+ obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
++obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
+ obj-$(CONFIG_AMD_PHY) += amd.o
+ obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
+ obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
+--- /dev/null
++++ b/drivers/net/phy/air_en8811h.c
+@@ -0,0 +1,1086 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Driver for the Airoha EN8811H 2.5 Gigabit PHY.
++ *
++ * Limitations of the EN8811H:
++ * - Only full duplex supported
++ * - Forced speed (AN off) is not supported by hardware (100Mbps)
++ *
++ * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
++ *
++ * Copyright (C) 2023 Airoha Technology Corp.
++ */
++
++#include <linux/phy.h>
++#include <linux/firmware.h>
++#include <linux/property.h>
++#include <linux/wordpart.h>
++#include <asm/unaligned.h>
++
++#define EN8811H_PHY_ID 0x03a2a411
++
++#define EN8811H_MD32_DM "airoha/EthMD32.dm.bin"
++#define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin"
++
++#define AIR_FW_ADDR_DM 0x00000000
++#define AIR_FW_ADDR_DSP 0x00100000
++
++/* MII Registers */
++#define AIR_AUX_CTRL_STATUS 0x1d
++#define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2)
++#define AIR_AUX_CTRL_STATUS_SPEED_100 0x4
++#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
++#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
++
++#define AIR_EXT_PAGE_ACCESS 0x1f
++#define AIR_PHY_PAGE_STANDARD 0x0000
++#define AIR_PHY_PAGE_EXTENDED_4 0x0004
++
++/* MII Registers Page 4*/
++#define AIR_BPBUS_MODE 0x10
++#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000
++#define AIR_BPBUS_MODE_ADDR_INCR BIT(15)
++#define AIR_BPBUS_WR_ADDR_HIGH 0x11
++#define AIR_BPBUS_WR_ADDR_LOW 0x12
++#define AIR_BPBUS_WR_DATA_HIGH 0x13
++#define AIR_BPBUS_WR_DATA_LOW 0x14
++#define AIR_BPBUS_RD_ADDR_HIGH 0x15
++#define AIR_BPBUS_RD_ADDR_LOW 0x16
++#define AIR_BPBUS_RD_DATA_HIGH 0x17
++#define AIR_BPBUS_RD_DATA_LOW 0x18
++
++/* Registers on MDIO_MMD_VEND1 */
++#define EN8811H_PHY_FW_STATUS 0x8009
++#define EN8811H_PHY_READY 0x02
++
++#define AIR_PHY_MCU_CMD_1 0x800c
++#define AIR_PHY_MCU_CMD_1_MODE1 0x0
++#define AIR_PHY_MCU_CMD_2 0x800d
++#define AIR_PHY_MCU_CMD_2_MODE1 0x0
++#define AIR_PHY_MCU_CMD_3 0x800e
++#define AIR_PHY_MCU_CMD_3_MODE1 0x1101
++#define AIR_PHY_MCU_CMD_3_DOCMD 0x1100
++#define AIR_PHY_MCU_CMD_4 0x800f
++#define AIR_PHY_MCU_CMD_4_MODE1 0x0002
++#define AIR_PHY_MCU_CMD_4_INTCLR 0x00e4
++
++/* Registers on MDIO_MMD_VEND2 */
++#define AIR_PHY_LED_BCR 0x021
++#define AIR_PHY_LED_BCR_MODE_MASK GENMASK(1, 0)
++#define AIR_PHY_LED_BCR_TIME_TEST BIT(2)
++#define AIR_PHY_LED_BCR_CLK_EN BIT(3)
++#define AIR_PHY_LED_BCR_EXT_CTRL BIT(15)
++
++#define AIR_PHY_LED_DUR_ON 0x022
++
++#define AIR_PHY_LED_DUR_BLINK 0x023
++
++#define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2))
++#define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8))
++#define AIR_PHY_LED_ON_LINK1000 BIT(0)
++#define AIR_PHY_LED_ON_LINK100 BIT(1)
++#define AIR_PHY_LED_ON_LINK10 BIT(2)
++#define AIR_PHY_LED_ON_LINKDOWN BIT(3)
++#define AIR_PHY_LED_ON_FDX BIT(4) /* Full duplex */
++#define AIR_PHY_LED_ON_HDX BIT(5) /* Half duplex */
++#define AIR_PHY_LED_ON_FORCE_ON BIT(6)
++#define AIR_PHY_LED_ON_LINK2500 BIT(8)
++#define AIR_PHY_LED_ON_POLARITY BIT(14)
++#define AIR_PHY_LED_ON_ENABLE BIT(15)
++
++#define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2))
++#define AIR_PHY_LED_BLINK_1000TX BIT(0)
++#define AIR_PHY_LED_BLINK_1000RX BIT(1)
++#define AIR_PHY_LED_BLINK_100TX BIT(2)
++#define AIR_PHY_LED_BLINK_100RX BIT(3)
++#define AIR_PHY_LED_BLINK_10TX BIT(4)
++#define AIR_PHY_LED_BLINK_10RX BIT(5)
++#define AIR_PHY_LED_BLINK_COLLISION BIT(6)
++#define AIR_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
++#define AIR_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
++#define AIR_PHY_LED_BLINK_FORCE_BLINK BIT(9)
++#define AIR_PHY_LED_BLINK_2500TX BIT(10)
++#define AIR_PHY_LED_BLINK_2500RX BIT(11)
++
++/* Registers on BUCKPBUS */
++#define EN8811H_2P5G_LPA 0x3b30
++#define EN8811H_2P5G_LPA_2P5G BIT(0)
++
++#define EN8811H_FW_VERSION 0x3b3c
++
++#define EN8811H_POLARITY 0xca0f8
++#define EN8811H_POLARITY_TX_NORMAL BIT(0)
++#define EN8811H_POLARITY_RX_REVERSE BIT(1)
++
++#define EN8811H_GPIO_OUTPUT 0xcf8b8
++#define EN8811H_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5))
++
++#define EN8811H_FW_CTRL_1 0x0f0018
++#define EN8811H_FW_CTRL_1_START 0x0
++#define EN8811H_FW_CTRL_1_FINISH 0x1
++#define EN8811H_FW_CTRL_2 0x800000
++#define EN8811H_FW_CTRL_2_LOADING BIT(11)
++
++/* Led definitions */
++#define EN8811H_LED_COUNT 3
++
++/* Default LED setup:
++ * GPIO5 <-> LED0 On: Link detected, blink Rx/Tx
++ * GPIO4 <-> LED1 On: Link detected at 2500 or 1000 Mbps
++ * GPIO3 <-> LED2 On: Link detected at 2500 or 100 Mbps
++ */
++#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK) | \
++ BIT(TRIGGER_NETDEV_RX) | \
++ BIT(TRIGGER_NETDEV_TX))
++#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++ BIT(TRIGGER_NETDEV_LINK_1000))
++#define AIR_DEFAULT_TRIGGER_LED2 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++ BIT(TRIGGER_NETDEV_LINK_100))
++
++struct led {
++ unsigned long rules;
++ unsigned long state;
++};
++
++struct en8811h_priv {
++ u32 firmware_version;
++ bool mcu_needs_restart;
++ struct led led[EN8811H_LED_COUNT];
++};
++
++enum {
++ AIR_PHY_LED_STATE_FORCE_ON,
++ AIR_PHY_LED_STATE_FORCE_BLINK,
++};
++
++enum {
++ AIR_PHY_LED_DUR_BLINK_32MS,
++ AIR_PHY_LED_DUR_BLINK_64MS,
++ AIR_PHY_LED_DUR_BLINK_128MS,
++ AIR_PHY_LED_DUR_BLINK_256MS,
++ AIR_PHY_LED_DUR_BLINK_512MS,
++ AIR_PHY_LED_DUR_BLINK_1024MS,
++};
++
++enum {
++ AIR_LED_DISABLE,
++ AIR_LED_ENABLE,
++};
++
++enum {
++ AIR_ACTIVE_LOW,
++ AIR_ACTIVE_HIGH,
++};
++
++enum {
++ AIR_LED_MODE_DISABLE,
++ AIR_LED_MODE_USER_DEFINE,
++};
++
++#define AIR_PHY_LED_DUR_UNIT 1024
++#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS)
++
++static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
++ BIT(TRIGGER_NETDEV_LINK) |
++ BIT(TRIGGER_NETDEV_LINK_10) |
++ BIT(TRIGGER_NETDEV_LINK_100) |
++ BIT(TRIGGER_NETDEV_LINK_1000) |
++ BIT(TRIGGER_NETDEV_LINK_2500) |
++ BIT(TRIGGER_NETDEV_RX) |
++ BIT(TRIGGER_NETDEV_TX);
++
++static int air_phy_read_page(struct phy_device *phydev)
++{
++ return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
++}
++
++static int air_phy_write_page(struct phy_device *phydev, int page)
++{
++ return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
++}
++
++static int __air_buckpbus_reg_write(struct phy_device *phydev,
++ u32 pbus_address, u32 pbus_data)
++{
++ int ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++ upper_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++ lower_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
++ upper_16_bits(pbus_data));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
++ lower_16_bits(pbus_data));
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++static int air_buckpbus_reg_write(struct phy_device *phydev,
++ u32 pbus_address, u32 pbus_data)
++{
++ int saved_page;
++ int ret = 0;
++
++ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++ if (saved_page >= 0) {
++ ret = __air_buckpbus_reg_write(phydev, pbus_address,
++ pbus_data);
++ if (ret < 0)
++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++ pbus_address, ret);
++ }
++
++ return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_buckpbus_reg_read(struct phy_device *phydev,
++ u32 pbus_address, u32 *pbus_data)
++{
++ int pbus_data_low, pbus_data_high;
++ int ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
++ upper_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
++ lower_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
++ if (pbus_data_high < 0)
++ return ret;
++
++ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
++ if (pbus_data_low < 0)
++ return ret;
++
++ *pbus_data = pbus_data_low | (pbus_data_high << 16);
++ return 0;
++}
++
++static int air_buckpbus_reg_read(struct phy_device *phydev,
++ u32 pbus_address, u32 *pbus_data)
++{
++ int saved_page;
++ int ret = 0;
++
++ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++ if (saved_page >= 0) {
++ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
++ if (ret < 0)
++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++ pbus_address, ret);
++ }
++
++ return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_buckpbus_reg_modify(struct phy_device *phydev,
++ u32 pbus_address, u32 mask, u32 set)
++{
++ int pbus_data_low, pbus_data_high;
++ u32 pbus_data_old, pbus_data_new;
++ int ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
++ upper_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
++ lower_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
++ if (pbus_data_high < 0)
++ return ret;
++
++ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
++ if (pbus_data_low < 0)
++ return ret;
++
++ pbus_data_old = pbus_data_low | (pbus_data_high << 16);
++ pbus_data_new = (pbus_data_old & ~mask) | set;
++ if (pbus_data_new == pbus_data_old)
++ return 0;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++ upper_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++ lower_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
++ upper_16_bits(pbus_data_new));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
++ lower_16_bits(pbus_data_new));
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++static int air_buckpbus_reg_modify(struct phy_device *phydev,
++ u32 pbus_address, u32 mask, u32 set)
++{
++ int saved_page;
++ int ret = 0;
++
++ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++ if (saved_page >= 0) {
++ ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
++ set);
++ if (ret < 0)
++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++ pbus_address, ret);
++ }
++
++ return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_write_buf(struct phy_device *phydev, u32 address,
++ const struct firmware *fw)
++{
++ unsigned int offset;
++ int ret;
++ u16 val;
++
++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR);
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++ upper_16_bits(address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++ lower_16_bits(address));
++ if (ret < 0)
++ return ret;
++
++ for (offset = 0; offset < fw->size; offset += 4) {
++ val = get_unaligned_le16(&fw->data[offset + 2]);
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val);
++ if (ret < 0)
++ return ret;
++
++ val = get_unaligned_le16(&fw->data[offset]);
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val);
++ if (ret < 0)
++ return ret;
++ }
++
++ return 0;
++}
++
++static int air_write_buf(struct phy_device *phydev, u32 address,
++ const struct firmware *fw)
++{
++ int saved_page;
++ int ret = 0;
++
++ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++ if (saved_page >= 0) {
++ ret = __air_write_buf(phydev, address, fw);
++ if (ret < 0)
++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++ address, ret);
++ }
++
++ return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int en8811h_wait_mcu_ready(struct phy_device *phydev)
++{
++ int ret, reg_value;
++
++ /* Because of mdio-lock, may have to wait for multiple loads */
++ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++ EN8811H_PHY_FW_STATUS, reg_value,
++ reg_value == EN8811H_PHY_READY,
++ 20000, 7500000, true);
++ if (ret) {
++ phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value);
++ return -ENODEV;
++ }
++
++ return 0;
++}
++
++static int en8811h_load_firmware(struct phy_device *phydev)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ struct device *dev = &phydev->mdio.dev;
++ const struct firmware *fw1, *fw2;
++ int ret;
++
++ ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
++ if (ret < 0)
++ return ret;
++
++ ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
++ if (ret < 0)
++ goto en8811h_load_firmware_rel1;
++
++ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++ EN8811H_FW_CTRL_1_START);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
++ EN8811H_FW_CTRL_2_LOADING,
++ EN8811H_FW_CTRL_2_LOADING);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = air_write_buf(phydev, AIR_FW_ADDR_DM, fw1);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
++ EN8811H_FW_CTRL_2_LOADING, 0);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++ EN8811H_FW_CTRL_1_FINISH);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = en8811h_wait_mcu_ready(phydev);
++
++ air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
++ &priv->firmware_version);
++ phydev_info(phydev, "MD32 firmware version: %08x\n",
++ priv->firmware_version);
++
++en8811h_load_firmware_out:
++ release_firmware(fw2);
++
++en8811h_load_firmware_rel1:
++ release_firmware(fw1);
++
++ if (ret < 0)
++ phydev_err(phydev, "Load firmware failed: %d\n", ret);
++
++ return ret;
++}
++
++static int en8811h_restart_mcu(struct phy_device *phydev)
++{
++ int ret;
++
++ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++ EN8811H_FW_CTRL_1_START);
++ if (ret < 0)
++ return ret;
++
++ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++ EN8811H_FW_CTRL_1_FINISH);
++ if (ret < 0)
++ return ret;
++
++ return en8811h_wait_mcu_ready(phydev);
++}
++
++static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ bool changed;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ if (on)
++ changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
++ &priv->led[index].state);
++ else
++ changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
++ &priv->led[index].state);
++
++ changed |= (priv->led[index].rules != 0);
++
++ if (changed)
++ return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
++ AIR_PHY_LED_ON(index),
++ AIR_PHY_LED_ON_MASK,
++ on ? AIR_PHY_LED_ON_FORCE_ON : 0);
++
++ return 0;
++}
++
++static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
++ bool blinking)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ bool changed;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ if (blinking)
++ changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++ &priv->led[index].state);
++ else
++ changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++ &priv->led[index].state);
++
++ changed |= (priv->led[index].rules != 0);
++
++ if (changed)
++ return phy_write_mmd(phydev, MDIO_MMD_VEND2,
++ AIR_PHY_LED_BLINK(index),
++ blinking ?
++ AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
++ else
++ return 0;
++}
++
++static int air_led_blink_set(struct phy_device *phydev, u8 index,
++ unsigned long *delay_on,
++ unsigned long *delay_off)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ bool blinking = false;
++ int err;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
++ blinking = true;
++ *delay_on = 50;
++ *delay_off = 50;
++ }
++
++ err = air_hw_led_blink_set(phydev, index, blinking);
++ if (err)
++ return err;
++
++ /* led-blink set, so switch led-on off */
++ err = air_hw_led_on_set(phydev, index, false);
++ if (err)
++ return err;
++
++ /* hw-control is off*/
++ if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
++ priv->led[index].rules = 0;
++
++ return 0;
++}
++
++static int air_led_brightness_set(struct phy_device *phydev, u8 index,
++ enum led_brightness value)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ int err;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ /* led-on set, so switch led-blink off */
++ err = air_hw_led_blink_set(phydev, index, false);
++ if (err)
++ return err;
++
++ err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
++ if (err)
++ return err;
++
++ /* hw-control is off */
++ if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
++ priv->led[index].rules = 0;
++
++ return 0;
++}
++
++static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
++ unsigned long *rules)
++{
++ struct en8811h_priv *priv = phydev->priv;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ *rules = priv->led[index].rules;
++
++ return 0;
++};
++
++static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
++ unsigned long rules)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ u16 on = 0, blink = 0;
++ int ret;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ priv->led[index].rules = rules;
++
++ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
++ on |= AIR_PHY_LED_ON_FDX;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= AIR_PHY_LED_ON_LINK10;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= AIR_PHY_LED_ON_LINK100;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= AIR_PHY_LED_ON_LINK1000;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= AIR_PHY_LED_ON_LINK2500;
++
++ if (rules & BIT(TRIGGER_NETDEV_RX)) {
++ blink |= AIR_PHY_LED_BLINK_10RX |
++ AIR_PHY_LED_BLINK_100RX |
++ AIR_PHY_LED_BLINK_1000RX |
++ AIR_PHY_LED_BLINK_2500RX;
++ }
++
++ if (rules & BIT(TRIGGER_NETDEV_TX)) {
++ blink |= AIR_PHY_LED_BLINK_10TX |
++ AIR_PHY_LED_BLINK_100TX |
++ AIR_PHY_LED_BLINK_1000TX |
++ AIR_PHY_LED_BLINK_2500TX;
++ }
++
++ if (blink || on) {
++ /* switch hw-control on, so led-on and led-blink are off */
++ clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
++ &priv->led[index].state);
++ clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++ &priv->led[index].state);
++ } else {
++ priv->led[index].rules = 0;
++ }
++
++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++ AIR_PHY_LED_ON_MASK, on);
++
++ if (ret < 0)
++ return ret;
++
++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
++ blink);
++};
++
++static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
++{
++ int val = 0;
++ int err;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ if (state == AIR_LED_ENABLE)
++ val |= AIR_PHY_LED_ON_ENABLE;
++ else
++ val &= ~AIR_PHY_LED_ON_ENABLE;
++
++ if (pol == AIR_ACTIVE_HIGH)
++ val |= AIR_PHY_LED_ON_POLARITY;
++ else
++ val &= ~AIR_PHY_LED_ON_POLARITY;
++
++ err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++ AIR_PHY_LED_ON_ENABLE |
++ AIR_PHY_LED_ON_POLARITY, val);
++
++ if (err < 0)
++ return err;
++
++ return 0;
++}
++
++static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ int ret, i;
++
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
++ dur);
++ if (ret < 0)
++ return ret;
++
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
++ dur >> 1);
++ if (ret < 0)
++ return ret;
++
++ switch (mode) {
++ case AIR_LED_MODE_DISABLE:
++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
++ AIR_PHY_LED_BCR_EXT_CTRL |
++ AIR_PHY_LED_BCR_MODE_MASK, 0);
++ if (ret < 0)
++ return ret;
++ break;
++ case AIR_LED_MODE_USER_DEFINE:
++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
++ AIR_PHY_LED_BCR_EXT_CTRL |
++ AIR_PHY_LED_BCR_CLK_EN,
++ AIR_PHY_LED_BCR_EXT_CTRL |
++ AIR_PHY_LED_BCR_CLK_EN);
++ if (ret < 0)
++ return ret;
++ break;
++ default:
++ phydev_err(phydev, "LED mode %d is not supported\n", mode);
++ return -EINVAL;
++ }
++
++ for (i = 0; i < num; ++i) {
++ ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
++ if (ret < 0) {
++ phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
++ return ret;
++ }
++ air_led_hw_control_set(phydev, i, priv->led[i].rules);
++ }
++
++ return 0;
++}
++
++static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
++ unsigned long rules)
++{
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ /* All combinations of the supported triggers are allowed */
++ if (rules & ~en8811h_led_trig)
++ return -EOPNOTSUPP;
++
++ return 0;
++};
++
++static int en8811h_probe(struct phy_device *phydev)
++{
++ struct en8811h_priv *priv;
++ int ret;
++
++ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
++ GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++ phydev->priv = priv;
++
++ ret = en8811h_load_firmware(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* mcu has just restarted after firmware load */
++ priv->mcu_needs_restart = false;
++
++ priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
++ priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
++ priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
++
++ /* MDIO_DEVS1/2 empty, so set mmds_present bits here */
++ phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
++
++ ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
++ AIR_LED_MODE_DISABLE);
++ if (ret < 0) {
++ phydev_err(phydev, "Failed to disable leds: %d\n", ret);
++ return ret;
++ }
++
++ /* Configure led gpio pins as output */
++ ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
++ EN8811H_GPIO_OUTPUT_345,
++ EN8811H_GPIO_OUTPUT_345);
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++static int en8811h_config_init(struct phy_device *phydev)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ struct device *dev = &phydev->mdio.dev;
++ u32 pbus_value;
++ int ret;
++
++ /* If restart happened in .probe(), no need to restart now */
++ if (priv->mcu_needs_restart) {
++ ret = en8811h_restart_mcu(phydev);
++ if (ret < 0)
++ return ret;
++ } else {
++ /* Next calls to .config_init() mcu needs to restart */
++ priv->mcu_needs_restart = true;
++ }
++
++ /* Select mode 1, the only mode supported.
++ * Configures the SerDes for 2500Base-X with rate adaptation
++ */
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1,
++ AIR_PHY_MCU_CMD_1_MODE1);
++ if (ret < 0)
++ return ret;
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2,
++ AIR_PHY_MCU_CMD_2_MODE1);
++ if (ret < 0)
++ return ret;
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
++ AIR_PHY_MCU_CMD_3_MODE1);
++ if (ret < 0)
++ return ret;
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
++ AIR_PHY_MCU_CMD_4_MODE1);
++ if (ret < 0)
++ return ret;
++
++ /* Serdes polarity */
++ pbus_value = 0;
++ if (device_property_read_bool(dev, "airoha,pnswap-rx"))
++ pbus_value |= EN8811H_POLARITY_RX_REVERSE;
++ else
++ pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
++ if (device_property_read_bool(dev, "airoha,pnswap-tx"))
++ pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
++ else
++ pbus_value |= EN8811H_POLARITY_TX_NORMAL;
++ ret = air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
++ EN8811H_POLARITY_RX_REVERSE |
++ EN8811H_POLARITY_TX_NORMAL, pbus_value);
++ if (ret < 0)
++ return ret;
++
++ ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
++ AIR_LED_MODE_USER_DEFINE);
++ if (ret < 0) {
++ phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int en8811h_get_features(struct phy_device *phydev)
++{
++ linkmode_set_bit_array(phy_basic_ports_array,
++ ARRAY_SIZE(phy_basic_ports_array),
++ phydev->supported);
++
++ return genphy_c45_pma_read_abilities(phydev);
++}
++
++static int en8811h_get_rate_matching(struct phy_device *phydev,
++ phy_interface_t iface)
++{
++ return RATE_MATCH_PAUSE;
++}
++
++static int en8811h_config_aneg(struct phy_device *phydev)
++{
++ bool changed = false;
++ int ret;
++ u32 adv;
++
++ if (phydev->autoneg == AUTONEG_DISABLE) {
++ phydev_warn(phydev, "Disabling autoneg is not supported\n");
++ return -EINVAL;
++ }
++
++ adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
++
++ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
++ MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
++ if (ret < 0)
++ return ret;
++ if (ret > 0)
++ changed = true;
++
++ return __genphy_config_aneg(phydev, changed);
++}
++
++static int en8811h_read_status(struct phy_device *phydev)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ u32 pbus_value;
++ int ret, val;
++
++ ret = genphy_update_link(phydev);
++ if (ret)
++ return ret;
++
++ phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
++ phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
++ phydev->speed = SPEED_UNKNOWN;
++ phydev->duplex = DUPLEX_UNKNOWN;
++ phydev->pause = 0;
++ phydev->asym_pause = 0;
++ phydev->rate_matching = RATE_MATCH_PAUSE;
++
++ ret = genphy_read_master_slave(phydev);
++ if (ret < 0)
++ return ret;
++
++ ret = genphy_read_lpa(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Get link partner 2.5GBASE-T ability from vendor register */
++ ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
++ if (ret < 0)
++ return ret;
++ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++ phydev->lp_advertising,
++ pbus_value & EN8811H_2P5G_LPA_2P5G);
++
++ if (phydev->autoneg_complete)
++ phy_resolve_aneg_pause(phydev);
++
++ if (!phydev->link)
++ return 0;
++
++ /* Get real speed from vendor register */
++ val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
++ if (val < 0)
++ return val;
++ switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
++ case AIR_AUX_CTRL_STATUS_SPEED_2500:
++ phydev->speed = SPEED_2500;
++ break;
++ case AIR_AUX_CTRL_STATUS_SPEED_1000:
++ phydev->speed = SPEED_1000;
++ break;
++ case AIR_AUX_CTRL_STATUS_SPEED_100:
++ phydev->speed = SPEED_100;
++ break;
++ }
++
++ /* Firmware before version 24011202 has no vendor register 2P5G_LPA.
++ * Assume link partner advertised it if connected at 2500Mbps.
++ */
++ if (priv->firmware_version < 0x24011202) {
++ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++ phydev->lp_advertising,
++ phydev->speed == SPEED_2500);
++ }
++
++ /* Only supports full duplex */
++ phydev->duplex = DUPLEX_FULL;
++
++ return 0;
++}
++
++static int en8811h_clear_intr(struct phy_device *phydev)
++{
++ int ret;
++
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
++ AIR_PHY_MCU_CMD_3_DOCMD);
++ if (ret < 0)
++ return ret;
++
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
++ AIR_PHY_MCU_CMD_4_INTCLR);
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
++{
++ int ret;
++
++ ret = en8811h_clear_intr(phydev);
++ if (ret < 0) {
++ phy_error(phydev);
++ return IRQ_NONE;
++ }
++
++ phy_trigger_machine(phydev);
++
++ return IRQ_HANDLED;
++}
++
++static struct phy_driver en8811h_driver[] = {
++{
++ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
++ .name = "Airoha EN8811H",
++ .probe = en8811h_probe,
++ .get_features = en8811h_get_features,
++ .config_init = en8811h_config_init,
++ .get_rate_matching = en8811h_get_rate_matching,
++ .config_aneg = en8811h_config_aneg,
++ .read_status = en8811h_read_status,
++ .config_intr = en8811h_clear_intr,
++ .handle_interrupt = en8811h_handle_interrupt,
++ .led_hw_is_supported = en8811h_led_hw_is_supported,
++ .read_page = air_phy_read_page,
++ .write_page = air_phy_write_page,
++ .led_blink_set = air_led_blink_set,
++ .led_brightness_set = air_led_brightness_set,
++ .led_hw_control_set = air_led_hw_control_set,
++ .led_hw_control_get = air_led_hw_control_get,
++} };
++
++module_phy_driver(en8811h_driver);
++
++static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
++ { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
++ { }
++};
++
++MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
++MODULE_FIRMWARE(EN8811H_MD32_DM);
++MODULE_FIRMWARE(EN8811H_MD32_DSP);
++
++MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
++MODULE_AUTHOR("Airoha");
++MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
++MODULE_LICENSE("GPL");
--- /dev/null
+From 87c33315af380ca12a2e59ac94edad4fe0481b4c Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@linaro.org>
+Date: Fri, 5 Apr 2024 13:08:59 +0300
+Subject: [PATCH] net: phy: air_en8811h: fix some error codes
+
+These error paths accidentally return "ret" which is zero/success
+instead of the correct error code.
+
+Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver")
+Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://lore.kernel.org/r/7ef2e230-dfb7-4a77-8973-9e5be1a99fc2@moroto.mountain
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/air_en8811h.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/air_en8811h.c
++++ b/drivers/net/phy/air_en8811h.c
+@@ -272,11 +272,11 @@ static int __air_buckpbus_reg_read(struc
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+- return ret;
++ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+- return ret;
++ return pbus_data_low;
+
+ *pbus_data = pbus_data_low | (pbus_data_high << 16);
+ return 0;
+@@ -323,11 +323,11 @@ static int __air_buckpbus_reg_modify(str
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+- return ret;
++ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+- return ret;
++ return pbus_data_low;
+
+ pbus_data_old = pbus_data_low | (pbus_data_high << 16);
+ pbus_data_new = (pbus_data_old & ~mask) | set;
__set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
} else {
if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
-@@ -839,7 +837,7 @@ static void mv88e6xxx_get_caps(struct ds
+@@ -851,7 +849,7 @@ static void mv88e6xxx_get_caps(struct ds
chip->info->ops->phylink_get_caps(chip, port, config);
mv88e6xxx_reg_unlock(chip);
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
config->supported_interfaces);
/* Internal ports with no phy-mode need GMII for PHYLIB */
-@@ -860,7 +858,7 @@ static void mv88e6xxx_mac_config(struct
+@@ -872,7 +870,7 @@ static void mv88e6xxx_mac_config(struct
mv88e6xxx_reg_lock(chip);
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -5944,7 +5944,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -5956,7 +5956,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6191X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
.max_vid = 8191,
.max_sid = 63,
.port_base_addr = 0x0,
-@@ -5967,7 +5968,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -5979,7 +5980,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6193X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
.max_vid = 8191,
.max_sid = 63,
.port_base_addr = 0x0,
-@@ -6286,7 +6288,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -6298,7 +6300,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6393X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -3328,7 +3328,7 @@ static int mv88e6xxx_setup_port(struct m
+@@ -3340,7 +3340,7 @@ static int mv88e6xxx_setup_port(struct m
caps = pl_config.mac_capabilities;
if (chip->info->ops->port_max_speed_mode)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -797,6 +797,8 @@ static void mv88e6393x_phylink_get_caps(
+@@ -809,6 +809,8 @@ static void mv88e6393x_phylink_get_caps(
unsigned long *supported = config->supported_interfaces;
bool is_6191x =
chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
-@@ -811,13 +813,17 @@ static void mv88e6393x_phylink_get_caps(
+@@ -823,13 +825,17 @@ static void mv88e6393x_phylink_get_caps(
/* 6191X supports >1G modes only on port 10 */
if (!is_6191x || port == 10) {
__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
}
}
-@@ -6231,6 +6237,32 @@ static const struct mv88e6xxx_info mv88e
+@@ -6243,6 +6249,32 @@ static const struct mv88e6xxx_info mv88e
.ptp_support = true,
.ops = &mv88e6352_ops,
},
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
-@@ -4154,17 +4154,6 @@ void intel_execlists_show_requests(struc
+@@ -4157,17 +4157,6 @@ void intel_execlists_show_requests(struc
spin_unlock_irqrestore(&sched_engine->lock, flags);
}
void intel_execlists_dump_active_requests(struct intel_engine_cs *engine,
struct i915_request *hung_rq,
struct drm_printer *m)
-@@ -4175,8 +4164,8 @@ void intel_execlists_dump_active_request
+@@ -4178,8 +4167,8 @@ void intel_execlists_dump_active_request
intel_engine_dump_active_requests(&engine->sched_engine->requests, hung_rq, m);
imx_ocotp_nvmem_config.priv = priv;
--- a/drivers/nvmem/meson-efuse.c
+++ b/drivers/nvmem/meson-efuse.c
-@@ -93,6 +93,7 @@ static int meson_efuse_probe(struct plat
+@@ -74,6 +74,7 @@ static int meson_efuse_probe(struct plat
econfig->dev = dev;
econfig->name = dev_name(dev);
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
-@@ -31,12 +31,7 @@
+@@ -30,12 +30,7 @@
#define MSM_ID_SMEM 137
enum _msm8996_version {
MSM8996_V3,
-@@ -154,12 +149,12 @@ static enum _msm8996_version qcom_cpufre
+@@ -153,12 +148,12 @@ static enum _msm8996_version qcom_cpufre
msm_id++;
switch ((enum _msm_id)*msm_id) {
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
-@@ -29,16 +29,8 @@
+@@ -28,16 +28,8 @@
#include <linux/slab.h>
#include <linux/soc/qcom/smem.h>
struct qcom_cpufreq_drv;
struct qcom_cpufreq_match_data {
-@@ -135,60 +127,32 @@ static void get_krait_bin_format_b(struc
+@@ -134,60 +126,32 @@ static void get_krait_bin_format_b(struc
dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
}
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -72,9 +72,9 @@ config SFP
- comment "MII PHY device drivers"
+@@ -77,9 +77,9 @@ config AIR_EN8811H_PHY
+ Currently supports the Airoha EN8811H PHY.
config AMD_PHY
- tristate "AMD PHYs"
--- a/drivers/bus/mhi/host/init.c
+++ b/drivers/bus/mhi/host/init.c
-@@ -881,6 +881,7 @@ static int parse_config(struct mhi_contr
+@@ -882,6 +882,7 @@ static int parse_config(struct mhi_contr
if (!mhi_cntrl->timeout_ms)
mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS;
if (!mhi_cntrl->buffer_len)
--- a/drivers/bus/mhi/host/internal.h
+++ b/drivers/bus/mhi/host/internal.h
-@@ -321,7 +321,7 @@ int __must_check mhi_read_reg_field(stru
+@@ -324,7 +324,7 @@ int __must_check mhi_read_reg_field(stru
u32 *out);
int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,
void __iomem *base, u32 offset, u32 mask,
ret = mhi_read_reg_field(mhi_cntrl, base, offset, mask, &out);
--- a/drivers/bus/mhi/host/pm.c
+++ b/drivers/bus/mhi/host/pm.c
-@@ -163,6 +163,7 @@ int mhi_ready_state_transition(struct mh
+@@ -171,6 +171,7 @@ int mhi_ready_state_transition(struct mh
enum mhi_pm_state cur_state;
struct device *dev = &mhi_cntrl->mhi_dev->dev;
u32 interval_us = 25000; /* poll register field every 25 milliseconds */
int ret, i;
/* Check if device entered error state */
-@@ -173,14 +174,18 @@ int mhi_ready_state_transition(struct mh
+@@ -181,14 +182,18 @@ int mhi_ready_state_transition(struct mh
/* Wait for RESET to be cleared and READY bit to be set by the device */
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
if (ret) {
dev_err(dev, "Device failed to enter MHI Ready\n");
return ret;
-@@ -479,7 +484,7 @@ static void mhi_pm_disable_transition(st
+@@ -487,7 +492,7 @@ static void mhi_pm_disable_transition(st
/* Wait for the reset bit to be cleared by the device */
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
if (ret)
dev_err(dev, "Device failed to clear MHI Reset\n");
-@@ -492,8 +497,8 @@ static void mhi_pm_disable_transition(st
+@@ -500,8 +505,8 @@ static void mhi_pm_disable_transition(st
if (!MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
/* wait for ready to be set */
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs,
if (ret)
dev_err(dev, "Device failed to enter READY state\n");
}
-@@ -1111,7 +1116,8 @@ int mhi_async_power_up(struct mhi_contro
+@@ -1125,7 +1130,8 @@ int mhi_async_power_up(struct mhi_contro
if (state == MHI_STATE_SYS_ERR) {
mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
if (ret) {
dev_info(dev, "Failed to reset MHI due to syserr state\n");
goto error_exit;
-@@ -1202,14 +1208,18 @@ EXPORT_SYMBOL_GPL(mhi_power_down);
+@@ -1216,14 +1222,18 @@ EXPORT_SYMBOL_GPL(mhi_power_down);
int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
{
int ret = mhi_async_power_up(mhi_cntrl);
--- /dev/null
+From 66a5c40f60f5d88ad8d47ba6a4ba05892853fa1f Mon Sep 17 00:00:00 2001
+From: Tanzir Hasan <tanzirh@google.com>
+Date: Tue, 26 Dec 2023 18:00:00 +0000
+Subject: [PATCH] kernel.h: removed REPEAT_BYTE from kernel.h
+
+This patch creates wordpart.h and includes it in asm/word-at-a-time.h
+for all architectures. WORD_AT_A_TIME_CONSTANTS depends on kernel.h
+because of REPEAT_BYTE. Moving this to another header and including it
+where necessary allows us to not include the bloated kernel.h. Making
+this implicit dependency on REPEAT_BYTE explicit allows for later
+improvements in the lib/string.c inclusion list.
+
+Suggested-by: Al Viro <viro@zeniv.linux.org.uk>
+Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Tanzir Hasan <tanzirh@google.com>
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Link: https://lore.kernel.org/r/20231226-libstringheader-v6-1-80aa08c7652c@google.com
+Signed-off-by: Kees Cook <keescook@chromium.org>
+---
+ arch/arm/include/asm/word-at-a-time.h | 3 ++-
+ arch/arm64/include/asm/word-at-a-time.h | 3 ++-
+ arch/powerpc/include/asm/word-at-a-time.h | 4 ++--
+ arch/riscv/include/asm/word-at-a-time.h | 3 ++-
+ arch/s390/include/asm/word-at-a-time.h | 3 ++-
+ arch/sh/include/asm/word-at-a-time.h | 2 ++
+ arch/x86/include/asm/word-at-a-time.h | 3 ++-
+ arch/x86/kvm/mmu/mmu.c | 1 +
+ fs/namei.c | 2 +-
+ include/asm-generic/word-at-a-time.h | 3 ++-
+ include/linux/kernel.h | 8 --------
+ include/linux/wordpart.h | 13 +++++++++++++
+ 12 files changed, 31 insertions(+), 17 deletions(-)
+ create mode 100644 include/linux/wordpart.h
+
+--- a/arch/arm/include/asm/word-at-a-time.h
++++ b/arch/arm/include/asm/word-at-a-time.h
+@@ -8,7 +8,8 @@
+ * Little-endian word-at-a-time zero byte handling.
+ * Heavily based on the x86 algorithm.
+ */
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+
+ struct word_at_a_time {
+ const unsigned long one_bits, high_bits;
+--- a/arch/arm64/include/asm/word-at-a-time.h
++++ b/arch/arm64/include/asm/word-at-a-time.h
+@@ -9,7 +9,8 @@
+
+ #ifndef __AARCH64EB__
+
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+
+ struct word_at_a_time {
+ const unsigned long one_bits, high_bits;
+--- a/arch/powerpc/include/asm/word-at-a-time.h
++++ b/arch/powerpc/include/asm/word-at-a-time.h
+@@ -4,8 +4,8 @@
+ /*
+ * Word-at-a-time interfaces for PowerPC.
+ */
+-
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ #include <asm/asm-compat.h>
+ #include <asm/extable.h>
+
+--- a/arch/sh/include/asm/word-at-a-time.h
++++ b/arch/sh/include/asm/word-at-a-time.h
+@@ -5,6 +5,8 @@
+ #ifdef CONFIG_CPU_BIG_ENDIAN
+ # include <asm-generic/word-at-a-time.h>
+ #else
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ /*
+ * Little-endian version cribbed from x86.
+ */
+--- a/arch/x86/include/asm/word-at-a-time.h
++++ b/arch/x86/include/asm/word-at-a-time.h
+@@ -2,7 +2,8 @@
+ #ifndef _ASM_WORD_AT_A_TIME_H
+ #define _ASM_WORD_AT_A_TIME_H
+
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+
+ /*
+ * This is largely generic for little-endian machines, but the
+--- a/arch/x86/kvm/mmu/mmu.c
++++ b/arch/x86/kvm/mmu/mmu.c
+@@ -47,6 +47,7 @@
+ #include <linux/kern_levels.h>
+ #include <linux/kstrtox.h>
+ #include <linux/kthread.h>
++#include <linux/wordpart.h>
+
+ #include <asm/page.h>
+ #include <asm/memtype.h>
+--- a/fs/namei.c
++++ b/fs/namei.c
+@@ -17,8 +17,8 @@
+
+ #include <linux/init.h>
+ #include <linux/export.h>
+-#include <linux/kernel.h>
+ #include <linux/slab.h>
++#include <linux/wordpart.h>
+ #include <linux/fs.h>
+ #include <linux/filelock.h>
+ #include <linux/namei.h>
+--- a/include/asm-generic/word-at-a-time.h
++++ b/include/asm-generic/word-at-a-time.h
+@@ -2,7 +2,8 @@
+ #ifndef _ASM_WORD_AT_A_TIME_H
+ #define _ASM_WORD_AT_A_TIME_H
+
+-#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/wordpart.h>
+ #include <asm/byteorder.h>
+
+ #ifdef __BIG_ENDIAN
+--- a/include/linux/kernel.h
++++ b/include/linux/kernel.h
+@@ -38,14 +38,6 @@
+
+ #define STACK_MAGIC 0xdeadbeef
+
+-/**
+- * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
+- * @x: value to repeat
+- *
+- * NOTE: @x is not checked for > 0xff; larger values produce odd results.
+- */
+-#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x))
+-
+ /* generic data direction definitions */
+ #define READ 0
+ #define WRITE 1
+--- /dev/null
++++ b/include/linux/wordpart.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#ifndef _LINUX_WORDPART_H
++#define _LINUX_WORDPART_H
++/**
++ * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
++ * @x: value to repeat
++ *
++ * NOTE: @x is not checked for > 0xff; larger values produce odd results.
++ */
++#define REPEAT_BYTE(x) ((~0ul / 0xff) * (x))
++
++#endif // _LINUX_WORDPART_H
--- /dev/null
+From adeb04362d74188c1e22ccb824b15a0a7b3de2f4 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Wed, 14 Feb 2024 19:26:32 +0200
+Subject: [PATCH] kernel.h: Move upper_*_bits() and lower_*_bits() to
+ wordpart.h
+
+The wordpart.h header is collecting APIs related to the handling
+parts of the word (usually in byte granularity). The upper_*_bits()
+and lower_*_bits() are good candidates to be moved to there.
+
+This helps to clean up header dependency hell with regard to kernel.h
+as the latter gathers completely unrelated stuff together and slows
+down compilation (especially when it's included into other header).
+
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Link: https://lore.kernel.org/r/20240214172752.3605073-1-andriy.shevchenko@linux.intel.com
+Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
+Signed-off-by: Kees Cook <keescook@chromium.org>
+---
+ include/linux/kernel.h | 30 ++----------------------------
+ include/linux/wordpart.h | 29 +++++++++++++++++++++++++++++
+ 2 files changed, 31 insertions(+), 28 deletions(-)
+
+--- a/include/linux/kernel.h
++++ b/include/linux/kernel.h
+@@ -32,6 +32,8 @@
+ #include <linux/sprintf.h>
+ #include <linux/static_call_types.h>
+ #include <linux/instruction_pointer.h>
++#include <linux/wordpart.h>
++
+ #include <asm/byteorder.h>
+
+ #include <uapi/linux/kernel.h>
+@@ -57,34 +59,6 @@
+ } \
+ )
+
+-/**
+- * upper_32_bits - return bits 32-63 of a number
+- * @n: the number we're accessing
+- *
+- * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
+- * the "right shift count >= width of type" warning when that quantity is
+- * 32-bits.
+- */
+-#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
+-
+-/**
+- * lower_32_bits - return bits 0-31 of a number
+- * @n: the number we're accessing
+- */
+-#define lower_32_bits(n) ((u32)((n) & 0xffffffff))
+-
+-/**
+- * upper_16_bits - return bits 16-31 of a number
+- * @n: the number we're accessing
+- */
+-#define upper_16_bits(n) ((u16)((n) >> 16))
+-
+-/**
+- * lower_16_bits - return bits 0-15 of a number
+- * @n: the number we're accessing
+- */
+-#define lower_16_bits(n) ((u16)((n) & 0xffff))
+-
+ struct completion;
+ struct user;
+
+--- a/include/linux/wordpart.h
++++ b/include/linux/wordpart.h
+@@ -2,6 +2,35 @@
+
+ #ifndef _LINUX_WORDPART_H
+ #define _LINUX_WORDPART_H
++
++/**
++ * upper_32_bits - return bits 32-63 of a number
++ * @n: the number we're accessing
++ *
++ * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
++ * the "right shift count >= width of type" warning when that quantity is
++ * 32-bits.
++ */
++#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
++
++/**
++ * lower_32_bits - return bits 0-31 of a number
++ * @n: the number we're accessing
++ */
++#define lower_32_bits(n) ((u32)((n) & 0xffffffff))
++
++/**
++ * upper_16_bits - return bits 16-31 of a number
++ * @n: the number we're accessing
++ */
++#define upper_16_bits(n) ((u16)((n) >> 16))
++
++/**
++ * lower_16_bits - return bits 0-15 of a number
++ * @n: the number we're accessing
++ */
++#define lower_16_bits(n) ((u16)((n) & 0xffff))
++
+ /**
+ * REPEAT_BYTE - repeat the value @x multiple times as an unsigned long value
+ * @x: value to repeat
--- /dev/null
+From: Richard Gobert <richardbgobert@gmail.com>
+Date: Wed, 3 Jan 2024 15:44:21 +0100
+Subject: [PATCH] net: gro: parse ipv6 ext headers without frag0 invalidation
+
+The existing code always pulls the IPv6 header and sets the transport
+offset initially. Then optionally again pulls any extension headers in
+ipv6_gso_pull_exthdrs and sets the transport offset again on return from
+that call. skb->data is set at the start of the first extension header
+before calling ipv6_gso_pull_exthdrs, and must disable the frag0
+optimization because that function uses pskb_may_pull/pskb_pull instead of
+skb_gro_ helpers. It sets the GRO offset to the TCP header with
+skb_gro_pull and sets the transport header. Then returns skb->data to its
+position before this block.
+
+This commit introduces a new helper function - ipv6_gro_pull_exthdrs -
+which is used in ipv6_gro_receive to pull ipv6 ext headers instead of
+ipv6_gso_pull_exthdrs. Thus, there is no modification of skb->data, all
+operations use skb_gro_* helpers, and the frag0 fast path can be taken for
+IPv6 packets with ext headers.
+
+Signed-off-by: Richard Gobert <richardbgobert@gmail.com>
+Reviewed-by: Willem de Bruijn <willemb@google.com>
+Reviewed-by: David Ahern <dsahern@kernel.org>
+Reviewed-by: Eric Dumazet <edumazet@google.com>
+Link: https://lore.kernel.org/r/504130f6-b56c-4dcc-882c-97942c59f5b7@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+
+--- a/net/ipv6/ip6_offload.c
++++ b/net/ipv6/ip6_offload.c
+@@ -37,6 +37,40 @@
+ INDIRECT_CALL_L4(cb, f2, f1, head, skb); \
+ })
+
++static int ipv6_gro_pull_exthdrs(struct sk_buff *skb, int off, int proto)
++{
++ const struct net_offload *ops = NULL;
++ struct ipv6_opt_hdr *opth;
++
++ for (;;) {
++ int len;
++
++ ops = rcu_dereference(inet6_offloads[proto]);
++
++ if (unlikely(!ops))
++ break;
++
++ if (!(ops->flags & INET6_PROTO_GSO_EXTHDR))
++ break;
++
++ opth = skb_gro_header(skb, off + sizeof(*opth), off);
++ if (unlikely(!opth))
++ break;
++
++ len = ipv6_optlen(opth);
++
++ opth = skb_gro_header(skb, off + len, off);
++ if (unlikely(!opth))
++ break;
++ proto = opth->nexthdr;
++
++ off += len;
++ }
++
++ skb_gro_pull(skb, off - skb_network_offset(skb));
++ return proto;
++}
++
+ static int ipv6_gso_pull_exthdrs(struct sk_buff *skb, int proto)
+ {
+ const struct net_offload *ops = NULL;
+@@ -206,28 +240,25 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
+ goto out;
+
+ skb_set_network_header(skb, off);
+- skb_gro_pull(skb, sizeof(*iph));
+- skb_set_transport_header(skb, skb_gro_offset(skb));
+
+- flush += ntohs(iph->payload_len) != skb_gro_len(skb);
++ flush += ntohs(iph->payload_len) != skb->len - hlen;
+
+ proto = iph->nexthdr;
+ ops = rcu_dereference(inet6_offloads[proto]);
+ if (!ops || !ops->callbacks.gro_receive) {
+- pskb_pull(skb, skb_gro_offset(skb));
+- skb_gro_frag0_invalidate(skb);
+- proto = ipv6_gso_pull_exthdrs(skb, proto);
+- skb_gro_pull(skb, -skb_transport_offset(skb));
+- skb_reset_transport_header(skb);
+- __skb_push(skb, skb_gro_offset(skb));
++ proto = ipv6_gro_pull_exthdrs(skb, hlen, proto);
+
+ ops = rcu_dereference(inet6_offloads[proto]);
+ if (!ops || !ops->callbacks.gro_receive)
+ goto out;
+
+- iph = ipv6_hdr(skb);
++ iph = skb_gro_network_header(skb);
++ } else {
++ skb_gro_pull(skb, sizeof(*iph));
+ }
+
++ skb_set_transport_header(skb, skb_gro_offset(skb));
++
+ NAPI_GRO_CB(skb)->proto = proto;
+
+ flush--;
--- /dev/null
+From: Richard Gobert <richardbgobert@gmail.com>
+Date: Tue, 30 Apr 2024 16:35:54 +0200
+Subject: [PATCH] net: gro: fix udp bad offset in socket lookup by adding
+ {inner_}network_offset to napi_gro_cb
+
+Commits a602456 ("udp: Add GRO functions to UDP socket") and 57c67ff ("udp:
+additional GRO support") introduce incorrect usage of {ip,ipv6}_hdr in the
+complete phase of gro. The functions always return skb->network_header,
+which in the case of encapsulated packets at the gro complete phase, is
+always set to the innermost L3 of the packet. That means that calling
+{ip,ipv6}_hdr for skbs which completed the GRO receive phase (both in
+gro_list and *_gro_complete) when parsing an encapsulated packet's _outer_
+L3/L4 may return an unexpected value.
+
+This incorrect usage leads to a bug in GRO's UDP socket lookup.
+udp{4,6}_lib_lookup_skb functions use ip_hdr/ipv6_hdr respectively. These
+*_hdr functions return network_header which will point to the innermost L3,
+resulting in the wrong offset being used in __udp{4,6}_lib_lookup with
+encapsulated packets.
+
+This patch adds network_offset and inner_network_offset to napi_gro_cb, and
+makes sure both are set correctly.
+
+To fix the issue, network_offsets union is used inside napi_gro_cb, in
+which both the outer and the inner network offsets are saved.
+
+Reproduction example:
+
+Endpoint configuration example (fou + local address bind)
+
+ # ip fou add port 6666 ipproto 4
+ # ip link add name tun1 type ipip remote 2.2.2.1 local 2.2.2.2 encap fou encap-dport 5555 encap-sport 6666 mode ipip
+ # ip link set tun1 up
+ # ip a add 1.1.1.2/24 dev tun1
+
+Netperf TCP_STREAM result on net-next before patch is applied:
+
+net-next main, GRO enabled:
+ $ netperf -H 1.1.1.2 -t TCP_STREAM -l 5
+ Recv Send Send
+ Socket Socket Message Elapsed
+ Size Size Size Time Throughput
+ bytes bytes bytes secs. 10^6bits/sec
+
+ 131072 16384 16384 5.28 2.37
+
+net-next main, GRO disabled:
+ $ netperf -H 1.1.1.2 -t TCP_STREAM -l 5
+ Recv Send Send
+ Socket Socket Message Elapsed
+ Size Size Size Time Throughput
+ bytes bytes bytes secs. 10^6bits/sec
+
+ 131072 16384 16384 5.01 2745.06
+
+patch applied, GRO enabled:
+ $ netperf -H 1.1.1.2 -t TCP_STREAM -l 5
+ Recv Send Send
+ Socket Socket Message Elapsed
+ Size Size Size Time Throughput
+ bytes bytes bytes secs. 10^6bits/sec
+
+ 131072 16384 16384 5.01 2877.38
+
+Fixes: a6024562ffd7 ("udp: Add GRO functions to UDP socket")
+Signed-off-by: Richard Gobert <richardbgobert@gmail.com>
+Reviewed-by: Eric Dumazet <edumazet@google.com>
+Reviewed-by: Willem de Bruijn <willemb@google.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/include/net/gro.h
++++ b/include/net/gro.h
+@@ -86,6 +86,15 @@ struct napi_gro_cb {
+
+ /* used to support CHECKSUM_COMPLETE for tunneling protocols */
+ __wsum csum;
++
++ /* L3 offsets */
++ union {
++ struct {
++ u16 network_offset;
++ u16 inner_network_offset;
++ };
++ u16 network_offsets[2];
++ };
+ };
+
+ #define NAPI_GRO_CB(skb) ((struct napi_gro_cb *)(skb)->cb)
+--- a/net/8021q/vlan_core.c
++++ b/net/8021q/vlan_core.c
+@@ -478,6 +478,8 @@ static struct sk_buff *vlan_gro_receive(
+ if (unlikely(!vhdr))
+ goto out;
+
++ NAPI_GRO_CB(skb)->network_offsets[NAPI_GRO_CB(skb)->encap_mark] = hlen;
++
+ type = vhdr->h_vlan_encapsulated_proto;
+
+ ptype = gro_find_receive_by_type(type);
+--- a/net/core/gro.c
++++ b/net/core/gro.c
+@@ -373,6 +373,7 @@ static inline void skb_gro_reset_offset(
+ const struct skb_shared_info *pinfo = skb_shinfo(skb);
+ const skb_frag_t *frag0 = &pinfo->frags[0];
+
++ NAPI_GRO_CB(skb)->network_offset = 0;
+ NAPI_GRO_CB(skb)->data_offset = 0;
+ NAPI_GRO_CB(skb)->frag0 = NULL;
+ NAPI_GRO_CB(skb)->frag0_len = 0;
+--- a/net/ipv4/af_inet.c
++++ b/net/ipv4/af_inet.c
+@@ -1571,6 +1571,7 @@ struct sk_buff *inet_gro_receive(struct
+ /* The above will be needed by the transport layer if there is one
+ * immediately following this IP hdr.
+ */
++ NAPI_GRO_CB(skb)->inner_network_offset = off;
+
+ /* Note : No need to call skb_gro_postpull_rcsum() here,
+ * as we already checked checksum over ipv4 header was 0
+--- a/net/ipv4/udp.c
++++ b/net/ipv4/udp.c
+@@ -534,7 +534,8 @@ static inline struct sock *__udp4_lib_lo
+ struct sock *udp4_lib_lookup_skb(const struct sk_buff *skb,
+ __be16 sport, __be16 dport)
+ {
+- const struct iphdr *iph = ip_hdr(skb);
++ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation];
++ const struct iphdr *iph = (struct iphdr *)(skb->data + offset);
+ struct net *net = dev_net(skb->dev);
+ int iif, sdif;
+
+--- a/net/ipv4/udp_offload.c
++++ b/net/ipv4/udp_offload.c
+@@ -718,7 +718,8 @@ EXPORT_SYMBOL(udp_gro_complete);
+
+ INDIRECT_CALLABLE_SCOPE int udp4_gro_complete(struct sk_buff *skb, int nhoff)
+ {
+- const struct iphdr *iph = ip_hdr(skb);
++ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation];
++ const struct iphdr *iph = (struct iphdr *)(skb->data + offset);
+ struct udphdr *uh = (struct udphdr *)(skb->data + nhoff);
+
+ /* do fraglist only if there is no outer UDP encap (or we already processed it) */
+--- a/net/ipv6/ip6_offload.c
++++ b/net/ipv6/ip6_offload.c
+@@ -240,6 +240,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
+ goto out;
+
+ skb_set_network_header(skb, off);
++ NAPI_GRO_CB(skb)->inner_network_offset = off;
+
+ flush += ntohs(iph->payload_len) != skb->len - hlen;
+
+--- a/net/ipv6/udp.c
++++ b/net/ipv6/udp.c
+@@ -275,7 +275,8 @@ static struct sock *__udp6_lib_lookup_sk
+ struct sock *udp6_lib_lookup_skb(const struct sk_buff *skb,
+ __be16 sport, __be16 dport)
+ {
+- const struct ipv6hdr *iph = ipv6_hdr(skb);
++ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation];
++ const struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + offset);
+ struct net *net = dev_net(skb->dev);
+ int iif, sdif;
+
+--- a/net/ipv6/udp_offload.c
++++ b/net/ipv6/udp_offload.c
+@@ -164,7 +164,8 @@ flush:
+
+ INDIRECT_CALLABLE_SCOPE int udp6_gro_complete(struct sk_buff *skb, int nhoff)
+ {
+- const struct ipv6hdr *ipv6h = ipv6_hdr(skb);
++ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation];
++ const struct ipv6hdr *ipv6h = (struct ipv6hdr *)(skb->data + offset);
+ struct udphdr *uh = (struct udphdr *)(skb->data + nhoff);
+
+ /* do fraglist only if there is no outer UDP encap (or we already processed it) */
--- /dev/null
+From: Richard Gobert <richardbgobert@gmail.com>
+Date: Tue, 30 Apr 2024 16:35:55 +0200
+Subject: [PATCH] net: gro: add flush check in udp_gro_receive_segment
+
+GRO-GSO path is supposed to be transparent and as such L3 flush checks are
+relevant to all UDP flows merging in GRO. This patch uses the same logic
+and code from tcp_gro_receive, terminating merge if flush is non zero.
+
+Fixes: e20cf8d3f1f7 ("udp: implement GRO for plain UDP sockets.")
+Signed-off-by: Richard Gobert <richardbgobert@gmail.com>
+Reviewed-by: Willem de Bruijn <willemb@google.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/net/ipv4/udp_offload.c
++++ b/net/ipv4/udp_offload.c
+@@ -471,6 +471,7 @@ static struct sk_buff *udp_gro_receive_s
+ struct sk_buff *p;
+ unsigned int ulen;
+ int ret = 0;
++ int flush;
+
+ /* requires non zero csum, for symmetry with GSO */
+ if (!uh->check) {
+@@ -504,13 +505,22 @@ static struct sk_buff *udp_gro_receive_s
+ return p;
+ }
+
++ flush = NAPI_GRO_CB(p)->flush;
++
++ if (NAPI_GRO_CB(p)->flush_id != 1 ||
++ NAPI_GRO_CB(p)->count != 1 ||
++ !NAPI_GRO_CB(p)->is_atomic)
++ flush |= NAPI_GRO_CB(p)->flush_id;
++ else
++ NAPI_GRO_CB(p)->is_atomic = false;
++
+ /* Terminate the flow on len mismatch or if it grow "too much".
+ * Under small packet flood GRO count could elsewhere grow a lot
+ * leading to excessive truesize values.
+ * On len mismatch merge the first packet shorter than gso_size,
+ * otherwise complete the GRO packet.
+ */
+- if (ulen > ntohs(uh2->len)) {
++ if (ulen > ntohs(uh2->len) || flush) {
+ pp = p;
+ } else {
+ if (NAPI_GRO_CB(skb)->is_flist) {
u32 vsc85xx_csr_read(struct phy_device *phydev,
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
-@@ -1650,20 +1650,22 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_1
+@@ -1658,20 +1658,22 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_1
/**
* phy_package_join - join a common PHY group
* @phydev: target phy_device struct
*
* This will set the shared pointer of the phydev to the shared storage.
* If this is the first call for a this cookie the shared storage will be
-@@ -1673,17 +1675,17 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_1
+@@ -1681,17 +1683,17 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_1
* Returns < 1 on error, 0 on success. Esp. calling phy_package_join()
* with the same cookie but a different priv_size is an error.
*/
if (!shared) {
ret = -ENOMEM;
shared = kzalloc(sizeof(*shared), GFP_KERNEL);
-@@ -1695,9 +1697,9 @@ int phy_package_join(struct phy_device *
+@@ -1703,9 +1705,9 @@ int phy_package_join(struct phy_device *
goto err_free;
shared->priv_size = priv_size;
}
} else {
ret = -EINVAL;
if (priv_size && priv_size != shared->priv_size)
-@@ -1735,7 +1737,7 @@ void phy_package_leave(struct phy_device
+@@ -1743,7 +1745,7 @@ void phy_package_leave(struct phy_device
return;
if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) {
mutex_unlock(&bus->shared_lock);
kfree(shared->priv);
kfree(shared);
-@@ -1754,7 +1756,8 @@ static void devm_phy_package_leave(struc
+@@ -1762,7 +1764,8 @@ static void devm_phy_package_leave(struc
* devm_phy_package_join - resource managed phy_package_join()
* @dev: device that is registering this PHY package
* @phydev: target phy_device struct
* @priv_size: if non-zero allocate this amount of bytes for private data
*
* Managed phy_package_join(). Shared storage fetched by this function,
-@@ -1762,7 +1765,7 @@ static void devm_phy_package_leave(struc
+@@ -1770,7 +1773,7 @@ static void devm_phy_package_leave(struc
* phy_package_join() for more information.
*/
int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
{
struct phy_device **ptr;
int ret;
-@@ -1772,7 +1775,7 @@ int devm_phy_package_join(struct device
+@@ -1780,7 +1783,7 @@ int devm_phy_package_join(struct device
if (!ptr)
return -ENOMEM;
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
-@@ -1698,6 +1698,7 @@ int phy_package_join(struct phy_device *
+@@ -1706,6 +1706,7 @@ int phy_package_join(struct phy_device *
shared->priv_size = priv_size;
}
shared->base_addr = base_addr;
refcount_set(&shared->refcnt, 1);
bus->shared[base_addr] = shared;
} else {
-@@ -1721,6 +1722,63 @@ err_unlock:
+@@ -1729,6 +1730,63 @@ err_unlock:
EXPORT_SYMBOL_GPL(phy_package_join);
/**
* phy_package_leave - leave a common PHY group
* @phydev: target phy_device struct
*
-@@ -1736,6 +1794,10 @@ void phy_package_leave(struct phy_device
+@@ -1744,6 +1802,10 @@ void phy_package_leave(struct phy_device
if (!shared)
return;
if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) {
bus->shared[shared->base_addr] = NULL;
mutex_unlock(&bus->shared_lock);
-@@ -1789,6 +1851,40 @@ int devm_phy_package_join(struct device
+@@ -1797,6 +1859,40 @@ int devm_phy_package_join(struct device
EXPORT_SYMBOL_GPL(devm_phy_package_join);
/**
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
-@@ -2607,12 +2607,15 @@ EXPORT_SYMBOL(genphy_read_status);
+@@ -2615,12 +2615,15 @@ EXPORT_SYMBOL(genphy_read_status);
/**
* genphy_c37_read_status - check the link status and update current link state
* @phydev: target phy_device struct
{
int lpa, err, old_link = phydev->link;
-@@ -2622,9 +2625,13 @@ int genphy_c37_read_status(struct phy_de
+@@ -2630,9 +2633,13 @@ int genphy_c37_read_status(struct phy_de
return err;
/* why bother the PHY if nothing can have changed */
--- /dev/null
+From abb45a2477f533cd4aab3085defdff131e2e8c4f Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 6 May 2024 14:32:46 +0200
+Subject: [PATCH] net: stmmac: dwmac-ipq806x: account for rgmii-txid/rxid/id
+ phy-mode
+
+Currently the ipq806x dwmac driver is almost always used attached to the
+CPU port of a switch and phy-mode was always set to "rgmii" or "sgmii".
+
+Some device came up with a special configuration where the PHY is
+directly attached to the GMAC port and in those case phy-mode needs to
+be set to "rgmii-id" to make the PHY correctly work and receive packets.
+
+Since the driver supports only "rgmii" and "sgmii" mode, when "rgmii-id"
+(or variants) mode is set, the mode is rejected and probe fails.
+
+Add support also for these phy-modes to correctly setup PHYs that requires
+delay applied to tx/rx.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
+@@ -171,6 +171,9 @@ static int ipq806x_gmac_set_speed(struct
+
+ switch (gmac->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
++ case PHY_INTERFACE_MODE_RGMII_ID:
++ case PHY_INTERFACE_MODE_RGMII_RXID:
++ case PHY_INTERFACE_MODE_RGMII_TXID:
+ div = get_clk_div_rgmii(gmac, speed);
+ clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
+ NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
+@@ -412,6 +415,9 @@ static int ipq806x_gmac_probe(struct pla
+ val |= NSS_COMMON_GMAC_CTL_CSYS_REQ;
+ switch (gmac->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
++ case PHY_INTERFACE_MODE_RGMII_ID:
++ case PHY_INTERFACE_MODE_RGMII_RXID:
++ case PHY_INTERFACE_MODE_RGMII_TXID:
+ val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+@@ -427,6 +433,9 @@ static int ipq806x_gmac_probe(struct pla
+ val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
+ switch (gmac->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
++ case PHY_INTERFACE_MODE_RGMII_ID:
++ case PHY_INTERFACE_MODE_RGMII_RXID:
++ case PHY_INTERFACE_MODE_RGMII_TXID:
+ val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
+ NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
+ break;
+@@ -444,6 +453,9 @@ static int ipq806x_gmac_probe(struct pla
+ val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id);
+ switch (gmac->phy_mode) {
+ case PHY_INTERFACE_MODE_RGMII:
++ case PHY_INTERFACE_MODE_RGMII_ID:
++ case PHY_INTERFACE_MODE_RGMII_RXID:
++ case PHY_INTERFACE_MODE_RGMII_TXID:
+ val |= NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
+ NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
+ break;
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1713,19 +1713,20 @@ mtk_wed_irq_set_mask(struct mtk_wed_devi
+@@ -1709,19 +1709,20 @@ mtk_wed_irq_set_mask(struct mtk_wed_devi
int mtk_wed_flow_add(int index)
{
struct mtk_wed_hw *hw = hw_list[index];
goto out;
}
-@@ -1744,14 +1745,15 @@ void mtk_wed_flow_remove(int index)
+@@ -1740,14 +1741,15 @@ void mtk_wed_flow_remove(int index)
{
struct mtk_wed_hw *hw = hw_list[index];
wdma_clr(dev, MTK_WDMA_GLO_CFG,
MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
@@ -606,7 +606,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
+ wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
- if (dev->hw->version == 1)
+ if (mtk_wed_is_v1(dev->hw))
return;
wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
-@@ -625,7 +625,7 @@ mtk_wed_deinit(struct mtk_wed_device *de
+@@ -624,7 +624,7 @@ mtk_wed_deinit(struct mtk_wed_device *de
MTK_WED_CTRL_WED_TX_BM_EN |
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
return;
wed_clr(dev, MTK_WED_CTRL,
-@@ -731,7 +731,7 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -730,7 +730,7 @@ mtk_wed_bus_init(struct mtk_wed_device *
static void
mtk_wed_set_wpdma(struct mtk_wed_device *dev)
{
wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
} else {
mtk_wed_bus_init(dev);
-@@ -762,7 +762,7 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
+@@ -761,7 +761,7 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
u32 offset = dev->hw->index ? 0x04000400 : 0;
wdma_set(dev, MTK_WDMA_GLO_CFG,
-@@ -935,7 +935,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -934,7 +934,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
wed_w32(dev, MTK_WED_TX_BM_TKID,
FIELD_PREP(MTK_WED_TX_BM_TKID_START,
dev->wlan.token_start) |
-@@ -968,7 +968,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -967,7 +967,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
wed_set(dev, MTK_WED_CTRL,
MTK_WED_CTRL_WED_TX_BM_EN |
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
-@@ -1218,7 +1218,7 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1217,7 +1217,7 @@ mtk_wed_reset_dma(struct mtk_wed_device
}
dev->init_done = false;
return;
if (!busy) {
-@@ -1344,7 +1344,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1343,7 +1343,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
MTK_WED_CTRL_WED_TX_BM_EN |
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
MTK_WED_PCIE_INT_TRIGGER_STATUS);
-@@ -1417,7 +1417,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1416,7 +1416,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
wdma_set(dev, MTK_WDMA_GLO_CFG,
MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
} else {
-@@ -1466,7 +1466,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1465,7 +1465,7 @@ mtk_wed_start(struct mtk_wed_device *dev
mtk_wed_set_ext_int(dev, true);
u32 val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN |
FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID,
dev->hw->index);
-@@ -1551,7 +1551,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1550,7 +1550,7 @@ mtk_wed_attach(struct mtk_wed_device *de
}
mtk_wed_hw_init_early(dev);
regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
BIT(hw->index), 0);
} else {
-@@ -1619,7 +1619,7 @@ static int
+@@ -1618,7 +1618,7 @@ static int
mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
{
struct mtk_wed_ring *ring = &dev->txfree_ring;
/*
* For txfree event handling, the same DMA ring is shared between WED
-@@ -1677,7 +1677,7 @@ mtk_wed_irq_get(struct mtk_wed_device *d
+@@ -1676,7 +1676,7 @@ mtk_wed_irq_get(struct mtk_wed_device *d
{
u32 val, ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
ext_mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
else
ext_mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
-@@ -1844,7 +1844,7 @@ mtk_wed_setup_tc(struct mtk_wed_device *
+@@ -1840,7 +1840,7 @@ mtk_wed_setup_tc(struct mtk_wed_device *
{
struct mtk_wed_hw *hw = wed->hw;
return -EOPNOTSUPP;
switch (type) {
-@@ -1918,9 +1918,9 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1914,9 +1914,9 @@ void mtk_wed_add_hw(struct device_node *
hw->wdma = wdma;
hw->index = index;
hw->irq = irq;
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
@@ -606,7 +606,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
+ wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
- if (mtk_wed_is_v1(dev->hw))
+ if (!mtk_wed_get_rx_capa(dev))
return;
wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
-@@ -733,16 +733,21 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -732,16 +732,21 @@ mtk_wed_set_wpdma(struct mtk_wed_device
{
if (mtk_wed_is_v1(dev->hw)) {
wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
}
static void
-@@ -974,15 +979,17 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -973,15 +978,17 @@ mtk_wed_hw_init(struct mtk_wed_device *d
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
} else {
wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
}
wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
-@@ -1354,8 +1361,6 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1353,8 +1360,6 @@ mtk_wed_configure_irq(struct mtk_wed_dev
wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
} else {
/* initail tx interrupt trigger */
wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
-@@ -1374,15 +1379,20 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1373,15 +1378,20 @@ mtk_wed_configure_irq(struct mtk_wed_dev
FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
dev->wlan.txfree_tbit));
wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
wed_set(dev, MTK_WED_WDMA_INT_CTRL,
-@@ -1401,6 +1411,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1400,6 +1410,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
static void
mtk_wed_dma_enable(struct mtk_wed_device *dev)
{
wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
wed_set(dev, MTK_WED_GLO_CFG,
-@@ -1420,33 +1432,33 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1419,33 +1431,33 @@ mtk_wed_dma_enable(struct mtk_wed_device
if (mtk_wed_is_v1(dev->hw)) {
wdma_set(dev, MTK_WDMA_GLO_CFG,
MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
}
static void
-@@ -1473,7 +1485,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1472,7 +1484,7 @@ mtk_wed_start(struct mtk_wed_device *dev
val |= BIT(0) | (BIT(1) * !!dev->hw->index);
regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
/* driver set mid ready and only once */
wed_w32(dev, MTK_WED_EXT_INT_MASK1,
MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
-@@ -1485,7 +1497,6 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1484,7 +1496,6 @@ mtk_wed_start(struct mtk_wed_device *dev
if (mtk_wed_rro_cfg(dev))
return;
}
mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
-@@ -1551,13 +1562,14 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1550,13 +1561,14 @@ mtk_wed_attach(struct mtk_wed_device *de
}
mtk_wed_hw_init_early(dev);
static void
wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
{
-@@ -747,7 +767,7 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -746,7 +766,7 @@ mtk_wed_set_wpdma(struct mtk_wed_device
return;
wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
}
static void
-@@ -941,22 +961,10 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -940,22 +960,10 @@ mtk_wed_hw_init(struct mtk_wed_device *d
wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
if (mtk_wed_is_v1(dev->hw)) {
wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
MTK_WED_TX_BM_DYN_THR_HI_V2);
-@@ -971,6 +979,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -970,6 +978,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
MTK_WED_TX_TKID_DYN_THR_HI);
}
mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
if (mtk_wed_is_v1(dev->hw)) {
-@@ -1105,13 +1118,8 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1104,13 +1117,8 @@ mtk_wed_rx_reset(struct mtk_wed_device *
if (ret) {
mtk_wed_reset(dev, MTK_WED_RESET_WED_RX_DMA);
} else {
wed_w32(dev, MTK_WED_RESET_IDX, 0);
}
-@@ -1164,7 +1172,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1163,7 +1171,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
if (busy) {
mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
} else {
wed_w32(dev, MTK_WED_RESET_IDX, 0);
}
-@@ -1256,7 +1265,6 @@ static int
+@@ -1255,7 +1264,6 @@ static int
mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
bool reset)
{
struct mtk_wed_ring *wdma;
if (idx >= ARRAY_SIZE(dev->rx_wdma))
-@@ -1264,7 +1272,7 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
+@@ -1263,7 +1271,7 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
wdma = &dev->rx_wdma[idx];
if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
return -ENOMEM;
wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
-@@ -1285,7 +1293,6 @@ static int
+@@ -1284,7 +1292,6 @@ static int
mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
bool reset)
{
struct mtk_wed_ring *wdma;
if (idx >= ARRAY_SIZE(dev->tx_wdma))
-@@ -1293,7 +1300,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+@@ -1292,7 +1299,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
wdma = &dev->tx_wdma[idx];
if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
return -ENOMEM;
wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
-@@ -1932,7 +1939,12 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1928,7 +1935,12 @@ void mtk_wed_add_hw(struct device_node *
hw->irq = irq;
hw->version = eth->soc->version;
hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
"mediatek,pcie-mirror");
hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
-@@ -1946,6 +1958,8 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1942,6 +1954,8 @@ void mtk_wed_add_hw(struct device_node *
regmap_write(hw->mirror, 0, 0);
regmap_write(hw->mirror, 4, 0);
}
}
mtk_wed_set_512_support(dev, false);
-@@ -652,6 +699,14 @@ mtk_wed_deinit(struct mtk_wed_device *de
+@@ -651,6 +698,14 @@ mtk_wed_deinit(struct mtk_wed_device *de
MTK_WED_CTRL_RX_ROUTE_QM_EN |
MTK_WED_CTRL_WED_RX_BM_EN |
MTK_WED_CTRL_RX_RRO_QM_EN);
}
static void
-@@ -701,21 +756,37 @@ mtk_wed_detach(struct mtk_wed_device *de
+@@ -700,21 +755,37 @@ mtk_wed_detach(struct mtk_wed_device *de
mutex_unlock(&hw_lock);
}
wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
-@@ -723,19 +794,9 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -722,19 +793,9 @@ mtk_wed_bus_init(struct mtk_wed_device *
/* pcie interrupt control: pola/source selection */
wed_set(dev, MTK_WED_PCIE_INT_CTRL,
MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
break;
}
case MTK_WED_BUS_AXI:
-@@ -773,18 +834,19 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -772,18 +833,19 @@ mtk_wed_set_wpdma(struct mtk_wed_device
static void
mtk_wed_hw_init_early(struct mtk_wed_device *dev)
{
wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
if (mtk_wed_is_v1(dev->hw)) {
-@@ -932,11 +994,18 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_
+@@ -931,11 +993,18 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_
}
/* configure RX_ROUTE_QM */
/* enable RX_ROUTE_QM */
wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
}
-@@ -949,22 +1018,30 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -948,22 +1017,30 @@ mtk_wed_hw_init(struct mtk_wed_device *d
dev->init_done = true;
mtk_wed_set_ext_int(dev, false);
wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
MTK_WED_TX_BM_DYN_THR_HI_V2);
-@@ -974,9 +1051,6 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -973,9 +1050,6 @@ mtk_wed_hw_init(struct mtk_wed_device *d
dev->tx_buf_ring.size / 128) |
FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
dev->tx_buf_ring.size / 128));
}
wed_w32(dev, dev->hw->soc->regmap.tx_bm_tkid,
-@@ -986,26 +1060,62 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -985,26 +1059,62 @@ mtk_wed_hw_init(struct mtk_wed_device *d
mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
}
static void
-@@ -1303,6 +1413,24 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+@@ -1302,6 +1412,24 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
dev->hw->soc->wdma_desc_size, true))
return -ENOMEM;
wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
wdma->desc_phys);
wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
-@@ -1368,6 +1496,9 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1367,6 +1495,9 @@ mtk_wed_configure_irq(struct mtk_wed_dev
wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
} else {
/* initail tx interrupt trigger */
wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
-@@ -1420,33 +1551,60 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1419,33 +1550,60 @@ mtk_wed_dma_enable(struct mtk_wed_device
{
int i;
wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
-@@ -1458,11 +1616,22 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1457,11 +1615,22 @@ mtk_wed_dma_enable(struct mtk_wed_device
MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
for (i = 0; i < MTK_WED_RX_QUEUES; i++)
mtk_wed_check_wfdma_rx_fill(dev, i);
-@@ -1502,6 +1671,12 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1501,6 +1670,12 @@ mtk_wed_start(struct mtk_wed_device *dev
wed_r32(dev, MTK_WED_EXT_INT_MASK1);
wed_r32(dev, MTK_WED_EXT_INT_MASK2);
if (mtk_wed_rro_cfg(dev))
return;
}
-@@ -1553,6 +1728,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1552,6 +1727,7 @@ mtk_wed_attach(struct mtk_wed_device *de
dev->irq = hw->irq;
dev->wdma_idx = hw->index;
dev->version = hw->version;
if (hw->eth->dma_dev == hw->eth->dev &&
of_dma_is_coherent(hw->eth->dev->of_node))
-@@ -1620,6 +1796,23 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
+@@ -1619,6 +1795,23 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
ring->reg_base = MTK_WED_RING_TX(idx);
ring->wpdma = regs;
/* WED -> WPDMA */
wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);
-@@ -1694,15 +1887,13 @@ mtk_wed_rx_ring_setup(struct mtk_wed_dev
+@@ -1693,15 +1886,13 @@ mtk_wed_rx_ring_setup(struct mtk_wed_dev
static u32
mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
{
val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
-@@ -1943,6 +2134,9 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1939,6 +2130,9 @@ void mtk_wed_add_hw(struct device_node *
case 2:
hw->soc = &mt7986_data;
break;
}
static void
-@@ -1546,6 +1537,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1545,6 +1536,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
}
static void
mtk_wed_dma_enable(struct mtk_wed_device *dev)
{
-@@ -1633,8 +1625,26 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1632,8 +1624,26 @@ mtk_wed_dma_enable(struct mtk_wed_device
wdma_set(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
}
mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
{
u32 desc_size = dev->hw->soc->tx_ring_desc_size;
-@@ -709,6 +840,7 @@ __mtk_wed_detach(struct mtk_wed_device *
+@@ -708,6 +839,7 @@ __mtk_wed_detach(struct mtk_wed_device *
mtk_wdma_rx_reset(dev);
mtk_wed_reset(dev, MTK_WED_RESET_WED);
mtk_wed_free_tx_buffer(dev);
mtk_wed_free_tx_rings(dev);
-@@ -1129,23 +1261,6 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
+@@ -1128,23 +1260,6 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
}
}
static int
mtk_wed_rx_reset(struct mtk_wed_device *dev)
{
-@@ -1692,6 +1807,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1691,6 +1806,7 @@ mtk_wed_start(struct mtk_wed_device *dev
}
mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
mtk_wed_dma_enable(dev);
dev->running = true;
-@@ -1748,6 +1864,10 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1747,6 +1863,10 @@ mtk_wed_attach(struct mtk_wed_device *de
if (ret)
goto out;
}
static void
-@@ -935,6 +1056,8 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -934,6 +1055,8 @@ mtk_wed_bus_init(struct mtk_wed_device *
static void
mtk_wed_set_wpdma(struct mtk_wed_device *dev)
{
if (mtk_wed_is_v1(dev->hw)) {
wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
return;
-@@ -952,6 +1075,15 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -951,6 +1074,15 @@ mtk_wed_set_wpdma(struct mtk_wed_device
wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring0, dev->wlan.wpdma_rx);
}
static void
-@@ -1763,6 +1895,165 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1762,6 +1894,165 @@ mtk_wed_dma_enable(struct mtk_wed_device
}
static void
mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
{
int i;
-@@ -2216,6 +2507,10 @@ void mtk_wed_add_hw(struct device_node *
+@@ -2212,6 +2503,10 @@ void mtk_wed_add_hw(struct device_node *
.detach = mtk_wed_detach,
.ppe_check = mtk_wed_ppe_check,
.setup_tc = mtk_wed_setup_tc,
wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
-@@ -1406,13 +1570,33 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1405,13 +1569,33 @@ mtk_wed_rx_reset(struct mtk_wed_device *
if (ret)
return ret;
wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
-@@ -1440,23 +1624,52 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1439,23 +1623,52 @@ mtk_wed_rx_reset(struct mtk_wed_device *
wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
}
mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV);
/* reset wed rx dma */
-@@ -1477,6 +1690,14 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1476,6 +1689,14 @@ mtk_wed_rx_reset(struct mtk_wed_device *
MTK_WED_CTRL_WED_RX_BM_BUSY);
mtk_wed_reset(dev, MTK_WED_RESET_RX_BM);
/* wo change to enable state */
val = MTK_WED_WO_STATE_ENABLE;
ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
-@@ -1494,6 +1715,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1493,6 +1714,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
false);
}
mtk_wed_free_rx_buffer(dev);
return 0;
}
-@@ -1527,15 +1749,41 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1526,15 +1748,41 @@ mtk_wed_reset_dma(struct mtk_wed_device
/* 2. reset WDMA rx DMA */
busy = !!mtk_wdma_rx_reset(dev);
wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);
wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);
-@@ -1551,8 +1799,13 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1550,8 +1798,13 @@ mtk_wed_reset_dma(struct mtk_wed_device
wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
for (i = 0; i < 100; i++) {
break;
}
-@@ -1574,6 +1827,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1573,6 +1826,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);
} else {
wed_w32(dev, MTK_WED_WPDMA_RESET_IDX,
MTK_WED_WPDMA_RESET_IDX_TX |
-@@ -1590,7 +1845,14 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1589,7 +1844,14 @@ mtk_wed_reset_dma(struct mtk_wed_device
wed_w32(dev, MTK_WED_RESET_IDX, 0);
}
}
static int
-@@ -1842,6 +2104,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1841,6 +2103,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4);
wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
}
wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
-@@ -1905,6 +2168,12 @@ mtk_wed_start_hw_rro(struct mtk_wed_devi
+@@ -1904,6 +2167,12 @@ mtk_wed_start_hw_rro(struct mtk_wed_devi
if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hw_rro)
return;
--- /dev/null
+From f13b2b33c7674fa0988dfaa9adb95d7d912b489f Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 10 Apr 2024 20:42:38 +0100
+Subject: [PATCH 1/2] net: dsa: introduce dsa_phylink_to_port()
+
+We convert from a phylink_config struct to a dsa_port struct in many
+places, let's provide a helper for this.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/E1rudqA-006K9B-85@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ include/net/dsa.h | 6 ++++++
+ net/dsa/port.c | 12 ++++++------
+ 2 files changed, 12 insertions(+), 6 deletions(-)
+
+--- a/include/net/dsa.h
++++ b/include/net/dsa.h
+@@ -327,6 +327,12 @@ struct dsa_port {
+ };
+ };
+
++static inline struct dsa_port *
++dsa_phylink_to_port(struct phylink_config *config)
++{
++ return container_of(config, struct dsa_port, pl_config);
++}
++
+ /* TODO: ideally DSA ports would have a single dp->link_dp member,
+ * and no dst->rtable nor this struct dsa_link would be needed,
+ * but this would require some more complex tree walking,
+--- a/net/dsa/port.c
++++ b/net/dsa/port.c
+@@ -1572,7 +1572,7 @@ static struct phylink_pcs *
+ dsa_port_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
+ struct dsa_switch *ds = dp->ds;
+
+@@ -1586,7 +1586,7 @@ static int dsa_port_phylink_mac_prepare(
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+ int err = 0;
+
+@@ -1601,7 +1601,7 @@ static void dsa_port_phylink_mac_config(
+ unsigned int mode,
+ const struct phylink_link_state *state)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_mac_config)
+@@ -1614,7 +1614,7 @@ static int dsa_port_phylink_mac_finish(s
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+ int err = 0;
+
+@@ -1629,7 +1629,7 @@ static void dsa_port_phylink_mac_link_do
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct phy_device *phydev = NULL;
+ struct dsa_switch *ds = dp->ds;
+
+@@ -1652,7 +1652,7 @@ static void dsa_port_phylink_mac_link_up
+ int speed, int duplex,
+ bool tx_pause, bool rx_pause)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_mac_link_up) {
--- /dev/null
+From c22d8240fcd73a1c3ec8dcb055bd583fb970c375 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 10 Apr 2024 20:42:43 +0100
+Subject: [PATCH 2/2] net: dsa: allow DSA switch drivers to provide their own
+ phylink mac ops
+
+Rather than having a shim for each and every phylink MAC operation,
+allow DSA switch drivers to provide their own ops structure. When a
+DSA driver provides the phylink MAC operations, the shimmed ops must
+not be provided, so fail an attempt to register a switch with both
+the phylink_mac_ops in struct dsa_switch and the phylink_mac_*
+operations populated in dsa_switch_ops populated.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Link: https://lore.kernel.org/r/E1rudqF-006K9H-Cc@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ include/net/dsa.h | 5 +++++
+ net/dsa/dsa.c | 11 +++++++++++
+ net/dsa/port.c | 26 ++++++++++++++++++++------
+ 3 files changed, 36 insertions(+), 6 deletions(-)
+
+--- a/include/net/dsa.h
++++ b/include/net/dsa.h
+@@ -458,6 +458,11 @@ struct dsa_switch {
+ const struct dsa_switch_ops *ops;
+
+ /*
++ * Allow a DSA switch driver to override the phylink MAC ops
++ */
++ const struct phylink_mac_ops *phylink_mac_ops;
++
++ /*
+ * Slave mii_bus and devices for the individual ports.
+ */
+ u32 phys_mii_mask;
+--- a/net/dsa/dsa.c
++++ b/net/dsa/dsa.c
+@@ -1510,6 +1510,17 @@ static int dsa_switch_probe(struct dsa_s
+ if (!ds->num_ports)
+ return -EINVAL;
+
++ if (ds->phylink_mac_ops) {
++ if (ds->ops->phylink_mac_select_pcs ||
++ ds->ops->phylink_mac_prepare ||
++ ds->ops->phylink_mac_config ||
++ ds->ops->phylink_mac_finish ||
++ ds->ops->phylink_mac_link_down ||
++ ds->ops->phylink_mac_link_up ||
++ ds->ops->adjust_link)
++ return -EINVAL;
++ }
++
+ if (np) {
+ err = dsa_switch_parse_of(ds, np);
+ if (err)
+--- a/net/dsa/port.c
++++ b/net/dsa/port.c
+@@ -1677,6 +1677,7 @@ static const struct phylink_mac_ops dsa_
+
+ int dsa_port_phylink_create(struct dsa_port *dp)
+ {
++ const struct phylink_mac_ops *mac_ops;
+ struct dsa_switch *ds = dp->ds;
+ phy_interface_t mode;
+ struct phylink *pl;
+@@ -1700,8 +1701,12 @@ int dsa_port_phylink_create(struct dsa_p
+ }
+ }
+
+- pl = phylink_create(&dp->pl_config, of_fwnode_handle(dp->dn),
+- mode, &dsa_port_phylink_mac_ops);
++ mac_ops = &dsa_port_phylink_mac_ops;
++ if (ds->phylink_mac_ops)
++ mac_ops = ds->phylink_mac_ops;
++
++ pl = phylink_create(&dp->pl_config, of_fwnode_handle(dp->dn), mode,
++ mac_ops);
+ if (IS_ERR(pl)) {
+ pr_err("error creating PHYLINK: %ld\n", PTR_ERR(pl));
+ return PTR_ERR(pl);
+@@ -1967,12 +1972,23 @@ static void dsa_shared_port_validate_of(
+ dn, dsa_port_is_cpu(dp) ? "CPU" : "DSA", dp->index);
+ }
+
++static void dsa_shared_port_link_down(struct dsa_port *dp)
++{
++ struct dsa_switch *ds = dp->ds;
++
++ if (ds->phylink_mac_ops && ds->phylink_mac_ops->mac_link_down)
++ ds->phylink_mac_ops->mac_link_down(&dp->pl_config, MLO_AN_FIXED,
++ PHY_INTERFACE_MODE_NA);
++ else if (ds->ops->phylink_mac_link_down)
++ ds->ops->phylink_mac_link_down(ds, dp->index, MLO_AN_FIXED,
++ PHY_INTERFACE_MODE_NA);
++}
++
+ int dsa_shared_port_link_register_of(struct dsa_port *dp)
+ {
+ struct dsa_switch *ds = dp->ds;
+ bool missing_link_description;
+ bool missing_phy_mode;
+- int port = dp->index;
+
+ dsa_shared_port_validate_of(dp, &missing_phy_mode,
+ &missing_link_description);
+@@ -1988,9 +2004,7 @@ int dsa_shared_port_link_register_of(str
+ "Skipping phylink registration for %s port %d\n",
+ dsa_port_is_cpu(dp) ? "CPU" : "DSA", dp->index);
+ } else {
+- if (ds->ops->phylink_mac_link_down)
+- ds->ops->phylink_mac_link_down(ds, port,
+- MLO_AN_FIXED, PHY_INTERFACE_MODE_NA);
++ dsa_shared_port_link_down(dp);
+
+ return dsa_shared_port_phylink_register(dp);
+ }
--- /dev/null
+From c278ec644377249aba5b1e1ca2b5705fd1c0132c Mon Sep 17 00:00:00 2001
+From: Paweł Owoc <frut3k7@gmail.com>
+Date: Mon, 1 Apr 2024 16:51:06 +0200
+Subject: [PATCH net-next v2] net: phy: aquantia: add support for AQR114C PHY ID
+
+Add support for AQR114C PHY ID. This PHY advertise 10G speed:
+SPEED(0x04): 0x6031
+ capabilities: -400g +5g +2.5g -200g -25g -10g-xr -100g -40g -10g/1g -10
+ +100 +1000 -10-ts -2-tl +10g
+EXTABLE(0x0B): 0x40fc
+ capabilities: -10g-cx4 -10g-lrm +10g-t +10g-kx4 +10g-kr +1000-t +1000-kx
+ +100-tx -10-t -p2mp -40g/100g -1000/100-t1 -25g -200g/400g
+ +2.5g/5g -1000-h
+
+but supports only up to 5G speed (as with AQR111/111B0).
+AQR111 init config is used to set max speed 5G.
+
+Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240401145114.1699451-1-frut3k7@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/aquantia/aquantia_main.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -28,6 +28,7 @@
+ #define PHY_ID_AQR412 0x03a1b712
+ #define PHY_ID_AQR113 0x31c31c40
+ #define PHY_ID_AQR113C 0x31c31c12
++#define PHY_ID_AQR114C 0x31c31c22
+ #define PHY_ID_AQR813 0x31c31cb2
+
+ #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
+@@ -880,6 +881,25 @@ static struct phy_driver aqr_driver[] =
+ .link_change_notify = aqr107_link_change_notify,
+ },
+ {
++ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C),
++ .name = "Aquantia AQR114C",
++ .probe = aqr107_probe,
++ .get_rate_matching = aqr107_get_rate_matching,
++ .config_init = aqr111_config_init,
++ .config_aneg = aqr_config_aneg,
++ .config_intr = aqr_config_intr,
++ .handle_interrupt = aqr_handle_interrupt,
++ .read_status = aqr107_read_status,
++ .get_tunable = aqr107_get_tunable,
++ .set_tunable = aqr107_set_tunable,
++ .suspend = aqr107_suspend,
++ .resume = aqr107_resume,
++ .get_sset_count = aqr107_get_sset_count,
++ .get_strings = aqr107_get_strings,
++ .get_stats = aqr107_get_stats,
++ .link_change_notify = aqr107_link_change_notify,
++},
++{
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
+ .name = "Aquantia AQR813",
+ .probe = aqr107_probe,
+@@ -916,6 +936,7 @@ static struct mdio_device_id __maybe_unu
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
+ { }
+ };
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -3003,13 +3003,25 @@ static void stmmac_tx_timer_arm(struct s
+@@ -2988,13 +2988,25 @@ static void stmmac_tx_timer_arm(struct s
{
struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
u32 tx_coal_timer = priv->tx_coal_timer[queue];
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2551,9 +2551,13 @@ static void stmmac_bump_dma_threshold(st
+@@ -2536,9 +2536,13 @@ static void stmmac_bump_dma_threshold(st
* @priv: driver private structure
* @budget: napi budget limiting this functions packet handling
* @queue: TX queue index
{
struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[queue];
-@@ -2713,7 +2717,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2698,7 +2702,7 @@ static int stmmac_tx_clean(struct stmmac
/* We still have pending packets, let's call for a new scheduling */
if (tx_q->dirty_tx != tx_q->cur_tx)
u64_stats_update_begin(&txq_stats->napi_syncp);
u64_stats_add(&txq_stats->napi.tx_packets, tx_packets);
-@@ -5605,6 +5609,7 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5590,6 +5594,7 @@ static int stmmac_napi_poll_tx(struct na
container_of(napi, struct stmmac_channel, tx_napi);
struct stmmac_priv *priv = ch->priv_data;
struct stmmac_txq_stats *txq_stats;
u32 chan = ch->index;
int work_done;
-@@ -5613,7 +5618,7 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5598,7 +5603,7 @@ static int stmmac_napi_poll_tx(struct na
u64_stats_inc(&txq_stats->napi.poll);
u64_stats_update_end(&txq_stats->napi_syncp);
work_done = min(work_done, budget);
if (work_done < budget && napi_complete_done(napi, work_done)) {
-@@ -5624,6 +5629,10 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5609,6 +5614,10 @@ static int stmmac_napi_poll_tx(struct na
spin_unlock_irqrestore(&ch->lock, flags);
}
return work_done;
}
-@@ -5632,6 +5641,7 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5617,6 +5626,7 @@ static int stmmac_napi_poll_rxtx(struct
struct stmmac_channel *ch =
container_of(napi, struct stmmac_channel, rxtx_napi);
struct stmmac_priv *priv = ch->priv_data;
int rx_done, tx_done, rxtx_done;
struct stmmac_rxq_stats *rxq_stats;
struct stmmac_txq_stats *txq_stats;
-@@ -5647,7 +5657,7 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5632,7 +5642,7 @@ static int stmmac_napi_poll_rxtx(struct
u64_stats_inc(&txq_stats->napi.poll);
u64_stats_update_end(&txq_stats->napi_syncp);
tx_done = min(tx_done, budget);
rx_done = stmmac_rx_zc(priv, budget, chan);
-@@ -5672,6 +5682,10 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5657,6 +5667,10 @@ static int stmmac_napi_poll_rxtx(struct
spin_unlock_irqrestore(&ch->lock, flags);
}
--- /dev/null
+From b91ef50f70e7c092c50c1b92e63ef3fb0041cdd4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Mon, 18 Sep 2023 21:19:12 +0200
+Subject: [PATCH 01/30] net: dsa: mt7530: Convert to platform remove callback
+ returning void
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The .remove() callback for a platform driver returns an int which makes
+many driver authors wrongly assume it's possible to do error handling by
+returning an error code. However the value returned is ignored (apart
+from emitting a warning) and this typically results in resource leaks.
+To improve here there is a quest to make the remove callback return
+void. In the first step of this quest all drivers are converted to
+.remove_new() which already returns void. Eventually after all drivers
+are converted, .remove_new() is renamed to .remove().
+
+Trivially convert this driver from always returning zero in the remove
+callback to the void returning variant.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530-mmio.c | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/dsa/mt7530-mmio.c
++++ b/drivers/net/dsa/mt7530-mmio.c
+@@ -63,15 +63,12 @@ mt7988_probe(struct platform_device *pde
+ return dsa_register_switch(priv->ds);
+ }
+
+-static int
+-mt7988_remove(struct platform_device *pdev)
++static void mt7988_remove(struct platform_device *pdev)
+ {
+ struct mt7530_priv *priv = platform_get_drvdata(pdev);
+
+ if (priv)
+ mt7530_remove_common(priv);
+-
+- return 0;
+ }
+
+ static void mt7988_shutdown(struct platform_device *pdev)
+@@ -88,7 +85,7 @@ static void mt7988_shutdown(struct platf
+
+ static struct platform_driver mt7988_platform_driver = {
+ .probe = mt7988_probe,
+- .remove = mt7988_remove,
++ .remove_new = mt7988_remove,
+ .shutdown = mt7988_shutdown,
+ .driver = {
+ .name = "mt7530-mmio",
--- /dev/null
+From d22c85764665af931c5c61bbe282b4116a88e792 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 27 Sep 2023 13:13:56 +0100
+Subject: [PATCH 02/30] net: dsa: mt753x: remove mt753x_phylink_pcs_link_up()
+
+Remove the mt753x_phylink_pcs_link_up() function for two reasons:
+
+1) priv->pcs[i].pcs.neg_mode is set true, meaning it doesn't take a
+ MLO_AN_FIXED anymore, but one of PHYLINK_PCS_NEG_*. However, this
+ is inconsequential due to...
+2) priv->pcs[port].pcs.ops is always initialised to point at
+ mt7530_pcs_ops, which does not have a pcs_link_up() member.
+
+So, let's remove mt753x_phylink_pcs_link_up() entirely.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Link: https://lore.kernel.org/r/E1qlTQS-008BWe-Va@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 11 -----------
+ 1 file changed, 11 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3037,15 +3037,6 @@ static void mt753x_phylink_mac_link_down
+ mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
+ }
+
+-static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs,
+- unsigned int mode,
+- phy_interface_t interface,
+- int speed, int duplex)
+-{
+- if (pcs->ops->pcs_link_up)
+- pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
+-}
+-
+ static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
+ unsigned int mode,
+ phy_interface_t interface,
+@@ -3133,8 +3124,6 @@ mt7531_cpu_port_config(struct dsa_switch
+ return ret;
+ mt7530_write(priv, MT7530_PMCR_P(port),
+ PMCR_CPU_PORT_SETTING(priv->id));
+- mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED,
+- interface, speed, DUPLEX_FULL);
+ mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
+ speed, DUPLEX_FULL, true, true);
+
--- /dev/null
+From 9b4f1f5a0801652056670a38503b4049eb413caf Mon Sep 17 00:00:00 2001
+From: Justin Stitt <justinstitt@google.com>
+Date: Mon, 9 Oct 2023 18:29:19 +0000
+Subject: [PATCH 03/30] net: dsa: mt7530: replace deprecated strncpy with
+ ethtool_sprintf
+
+`strncpy` is deprecated for use on NUL-terminated destination strings
+[1] and as such we should prefer more robust and less ambiguous string
+interfaces.
+
+ethtool_sprintf() is designed specifically for get_strings() usage.
+Let's replace strncpy in favor of this more robust and easier to
+understand interface.
+
+Link: https://www.kernel.org/doc/html/latest/process/deprecated.html#strncpy-on-nul-terminated-strings [1]
+Link: https://manpages.debian.org/testing/linux-manual-4.8/strscpy.9.en.html [2]
+Link: https://github.com/KSPP/linux/issues/90
+Signed-off-by: Justin Stitt <justinstitt@google.com>
+Reviewed-by: Kees Cook <keescook@chromium.org>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20231009-strncpy-drivers-net-dsa-mt7530-c-v1-1-ec6677a6436a@google.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -836,8 +836,7 @@ mt7530_get_strings(struct dsa_switch *ds
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
+- strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
+- ETH_GSTRING_LEN);
++ ethtool_sprintf(&data, "%s", mt7530_mib[i].name);
+ }
+
+ static void
--- /dev/null
+From af26b0d1bf934bbaa7cafb871a51e95087a088a0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:34:31 +0300
+Subject: [PATCH 04/30] net: dsa: mt7530: support OF-based registration of
+ switch MDIO bus
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently the MDIO bus of the switches the MT7530 DSA subdriver controls
+can only be registered as non-OF-based. Bring support for registering the
+bus OF-based.
+
+The subdrivers that control switches [with MDIO bus] probed on OF must
+follow this logic to support all cases properly:
+
+No switch MDIO bus defined: Populate ds->user_mii_bus, register the MDIO
+bus, set the interrupts for PHYs if "interrupt-controller" is defined at
+the switch node. This case should only be covered for the switches which
+their dt-bindings documentation didn't document the MDIO bus from the
+start. This is to keep supporting the device trees that do not describe the
+MDIO bus on the device tree but the MDIO bus is being used nonetheless.
+
+Switch MDIO bus defined: Don't populate ds->user_mii_bus, register the MDIO
+bus, set the interrupts for PHYs if ["interrupt-controller" is defined at
+the switch node and "interrupts" is defined at the PHY nodes under the
+switch MDIO bus node].
+
+Switch MDIO bus defined but explicitly disabled: If the device tree says
+status = "disabled" for the MDIO bus, we shouldn't need an MDIO bus at all.
+Instead, just exit as early as possible and do not call any MDIO API.
+
+The use of ds->user_mii_bus is inappropriate when the MDIO bus of the
+switch is described on the device tree [1], which is why we don't populate
+ds->user_mii_bus in that case.
+
+Link: https://lore.kernel.org/netdev/20231213120656.x46fyad6ls7sqyzv@skbuf/ [1]
+Suggested-by: David Bauer <mail@david-bauer.net>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122053431.7751-1-arinc.unal@arinc9.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 34 ++++++++++++++++++++++++++--------
+ 1 file changed, 26 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2345,24 +2345,40 @@ mt7530_free_irq_common(struct mt7530_pri
+ static void
+ mt7530_free_irq(struct mt7530_priv *priv)
+ {
+- mt7530_free_mdio_irq(priv);
++ struct device_node *mnp, *np = priv->dev->of_node;
++
++ mnp = of_get_child_by_name(np, "mdio");
++ if (!mnp)
++ mt7530_free_mdio_irq(priv);
++ of_node_put(mnp);
++
+ mt7530_free_irq_common(priv);
+ }
+
+ static int
+ mt7530_setup_mdio(struct mt7530_priv *priv)
+ {
++ struct device_node *mnp, *np = priv->dev->of_node;
+ struct dsa_switch *ds = priv->ds;
+ struct device *dev = priv->dev;
+ struct mii_bus *bus;
+ static int idx;
+- int ret;
++ int ret = 0;
++
++ mnp = of_get_child_by_name(np, "mdio");
++
++ if (mnp && !of_device_is_available(mnp))
++ goto out;
+
+ bus = devm_mdiobus_alloc(dev);
+- if (!bus)
+- return -ENOMEM;
++ if (!bus) {
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ if (!mnp)
++ ds->slave_mii_bus = bus;
+
+- ds->slave_mii_bus = bus;
+ bus->priv = priv;
+ bus->name = KBUILD_MODNAME "-mii";
+ snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
+@@ -2373,16 +2389,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+ bus->parent = dev;
+ bus->phy_mask = ~ds->phys_mii_mask;
+
+- if (priv->irq)
++ if (priv->irq && !mnp)
+ mt7530_setup_mdio_irq(priv);
+
+- ret = devm_mdiobus_register(dev, bus);
++ ret = devm_of_mdiobus_register(dev, bus, mnp);
+ if (ret) {
+ dev_err(dev, "failed to register MDIO bus: %d\n", ret);
+- if (priv->irq)
++ if (priv->irq && !mnp)
+ mt7530_free_mdio_irq(priv);
+ }
+
++out:
++ of_node_put(mnp);
+ return ret;
+ }
+
--- /dev/null
+From 617b07e08bcb1f69a72a085a7d847d1ca2999830 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:52 +0300
+Subject: [PATCH 05/30] net: dsa: mt7530: always trap frames to active CPU port
+ on MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On the MT7530 switch, the CPU_PORT field indicates which CPU port to trap
+frames to, regardless of the affinity of the inbound user port.
+
+When multiple CPU ports are in use, if the DSA conduit interface is down,
+trapped frames won't be passed to the conduit interface.
+
+To make trapping frames work including this case, implement
+ds->ops->conduit_state_change() on this subdriver and set the CPU_PORT
+field to the numerically smallest CPU port whose conduit interface is up.
+Introduce the active_cpu_ports field to store the information of the active
+CPU ports. Correct the macros, CPU_PORT is bits 4 through 6 of the
+register.
+
+Add a comment to explain frame trapping for this switch.
+
+Currently, the driver doesn't support the use of multiple CPU ports so this
+is not necessarily a bug fix.
+
+Suggested-by: Vladimir Oltean <olteanv@gmail.com>
+Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-1-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 35 +++++++++++++++++++++++++++++++----
+ drivers/net/dsa/mt7530.h | 6 ++++--
+ 2 files changed, 35 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1232,10 +1232,6 @@ mt753x_cpu_port_enable(struct dsa_switch
+ mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
+ UNU_FFP(BIT(port)));
+
+- /* Set CPU port number */
+- if (priv->id == ID_MT7530 || priv->id == ID_MT7621)
+- mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
+-
+ /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
+ * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
+ * is affine to the inbound user port.
+@@ -3305,6 +3301,36 @@ static int mt753x_set_mac_eee(struct dsa
+ return 0;
+ }
+
++static void
++mt753x_conduit_state_change(struct dsa_switch *ds,
++ const struct net_device *conduit,
++ bool operational)
++{
++ struct dsa_port *cpu_dp = conduit->dsa_ptr;
++ struct mt7530_priv *priv = ds->priv;
++ int val = 0;
++ u8 mask;
++
++ /* Set the CPU port to trap frames to for MT7530. Trapped frames will be
++ * forwarded to the numerically smallest CPU port whose conduit
++ * interface is up.
++ */
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return;
++
++ mask = BIT(cpu_dp->index);
++
++ if (operational)
++ priv->active_cpu_ports |= mask;
++ else
++ priv->active_cpu_ports &= ~mask;
++
++ if (priv->active_cpu_ports)
++ val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
++
++ mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
++}
++
+ static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
+ {
+ return 0;
+@@ -3360,6 +3386,7 @@ const struct dsa_switch_ops mt7530_switc
+ .phylink_mac_link_up = mt753x_phylink_mac_link_up,
+ .get_mac_eee = mt753x_get_mac_eee,
+ .set_mac_eee = mt753x_set_mac_eee,
++ .master_state_change = mt753x_conduit_state_change,
+ };
+ EXPORT_SYMBOL_GPL(mt7530_switch_ops);
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -45,8 +45,8 @@ enum mt753x_id {
+ #define UNU_FFP(x) (((x) & 0xff) << 8)
+ #define UNU_FFP_MASK UNU_FFP(~0)
+ #define CPU_EN BIT(7)
+-#define CPU_PORT(x) ((x) << 4)
+-#define CPU_MASK (0xf << 4)
++#define CPU_PORT_MASK GENMASK(6, 4)
++#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x)
+ #define MIRROR_EN BIT(3)
+ #define MIRROR_PORT(x) ((x) & 0x7)
+ #define MIRROR_MASK 0x7
+@@ -790,6 +790,7 @@ struct mt753x_info {
+ * @irq_domain: IRQ domain of the switch irq_chip
+ * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
+ * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
++ * @active_cpu_ports: Holding the active CPU ports
+ */
+ struct mt7530_priv {
+ struct device *dev;
+@@ -816,6 +817,7 @@ struct mt7530_priv {
+ struct irq_domain *irq_domain;
+ u32 irq_enable;
+ int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
++ u8 active_cpu_ports;
+ };
+
+ struct mt7530_hw_vlan_entry {
--- /dev/null
+From 07f411e26f82d75723df1c0c072e5602d06f4e30 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:53 +0300
+Subject: [PATCH 06/30] net: dsa: mt7530: use p5_interface_select as data type
+ for p5_intf_sel
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use the p5_interface_select enumeration as the data type for the
+p5_intf_sel field. This ensures p5_intf_sel can only take the values
+defined in the p5_interface_select enumeration.
+
+Remove the explicit assignment of 0 to P5_DISABLED as the first enum item
+is automatically assigned 0.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-2-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -713,7 +713,7 @@ struct mt7530_port {
+
+ /* Port 5 interface select definitions */
+ enum p5_interface_select {
+- P5_DISABLED = 0,
++ P5_DISABLED,
+ P5_INTF_SEL_PHY_P0,
+ P5_INTF_SEL_PHY_P4,
+ P5_INTF_SEL_GMAC5,
+@@ -806,7 +806,7 @@ struct mt7530_priv {
+ bool mcm;
+ phy_interface_t p6_interface;
+ phy_interface_t p5_interface;
+- unsigned int p5_intf_sel;
++ enum p5_interface_select p5_intf_sel;
+ u8 mirror_rx;
+ u8 mirror_tx;
+ struct mt7530_port ports[MT7530_NUM_PORTS];
--- /dev/null
+From 8f7db12efc189eedd196ed8d053236ce27add484 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:54 +0300
+Subject: [PATCH 07/30] net: dsa: mt7530: store port 5 SGMII capability of
+ MT7531
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Introduce the p5_sgmii field to store the information for whether port 5
+has got SGMII or not. Instead of reading the MT7531_TOP_SIG_SR register
+multiple times, the register will be read once and the value will be
+stored on the p5_sgmii field. This saves unnecessary reads of the
+register.
+
+Move the comment about MT7531AE and MT7531BE to mt7531_setup(), where the
+switch is identified.
+
+Get rid of mt7531_dual_sgmii_supported() now that priv->p5_sgmii stores the
+information. Address the code where mt7531_dual_sgmii_supported() is used.
+
+Get rid of mt7531_is_rgmii_port() which just prints the opposite of
+priv->p5_sgmii.
+
+Instead of calling mt7531_pll_setup() then returning, do not call it if
+port 5 is SGMII.
+
+Remove P5_INTF_SEL_GMAC5_SGMII. The p5_interface_select enum is supposed to
+represent the mode that port 5 is being used in, not the hardware
+information of port 5. Set p5_intf_sel to P5_INTF_SEL_GMAC5 instead, if
+port 5 is not dsa_is_unused_port().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-3-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530-mdio.c | 7 ++---
+ drivers/net/dsa/mt7530.c | 48 ++++++++++++-----------------------
+ drivers/net/dsa/mt7530.h | 6 +++--
+ 3 files changed, 22 insertions(+), 39 deletions(-)
+
+--- a/drivers/net/dsa/mt7530-mdio.c
++++ b/drivers/net/dsa/mt7530-mdio.c
+@@ -81,17 +81,14 @@ static const struct regmap_bus mt7530_re
+ };
+
+ static int
+-mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii)
++mt7531_create_sgmii(struct mt7530_priv *priv)
+ {
+ struct regmap_config *mt7531_pcs_config[2] = {};
+ struct phylink_pcs *pcs;
+ struct regmap *regmap;
+ int i, ret = 0;
+
+- /* MT7531AE has two SGMII units for port 5 and port 6
+- * MT7531BE has only one SGMII unit for port 6
+- */
+- for (i = dual_sgmii ? 0 : 1; i < 2; i++) {
++ for (i = priv->p5_sgmii ? 0 : 1; i < 2; i++) {
+ mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
+ sizeof(struct regmap_config),
+ GFP_KERNEL);
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -487,15 +487,6 @@ mt7530_pad_clk_setup(struct dsa_switch *
+ return 0;
+ }
+
+-static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
+-{
+- u32 val;
+-
+- val = mt7530_read(priv, MT7531_TOP_SIG_SR);
+-
+- return (val & PAD_DUAL_SGMII_EN) != 0;
+-}
+-
+ static int
+ mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
+ {
+@@ -510,9 +501,6 @@ mt7531_pll_setup(struct mt7530_priv *pri
+ u32 xtal;
+ u32 val;
+
+- if (mt7531_dual_sgmii_supported(priv))
+- return;
+-
+ val = mt7530_read(priv, MT7531_CREV);
+ top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
+ hwstrap = mt7530_read(priv, MT7531_HWTRAP);
+@@ -920,8 +908,6 @@ static const char *p5_intf_modes(unsigne
+ return "PHY P4";
+ case P5_INTF_SEL_GMAC5:
+ return "GMAC5";
+- case P5_INTF_SEL_GMAC5_SGMII:
+- return "GMAC5_SGMII";
+ default:
+ return "unknown";
+ }
+@@ -2694,6 +2680,12 @@ mt7531_setup(struct dsa_switch *ds)
+ return -ENODEV;
+ }
+
++ /* MT7531AE has got two SGMII units. One for port 5, one for port 6.
++ * MT7531BE has got only one SGMII unit which is for port 6.
++ */
++ val = mt7530_read(priv, MT7531_TOP_SIG_SR);
++ priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
++
+ /* all MACs must be forced link-down before sw reset */
+ for (i = 0; i < MT7530_NUM_PORTS; i++)
+ mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
+@@ -2703,21 +2695,18 @@ mt7531_setup(struct dsa_switch *ds)
+ SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
+ SYS_CTRL_REG_RST);
+
+- mt7531_pll_setup(priv);
+-
+- if (mt7531_dual_sgmii_supported(priv)) {
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
+-
++ if (!priv->p5_sgmii) {
++ mt7531_pll_setup(priv);
++ } else {
+ /* Let ds->slave_mii_bus be able to access external phy. */
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
+ MT7531_EXT_P_MDC_11);
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
+ MT7531_EXT_P_MDIO_12);
+- } else {
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+ }
+- dev_dbg(ds->dev, "P5 support %s interface\n",
+- p5_intf_modes(priv->p5_intf_sel));
++
++ if (!dsa_is_unused_port(ds, 5))
++ priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+
+ mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
+ MT7531_GPIO0_INTERRUPT);
+@@ -2784,11 +2773,6 @@ static void mt7530_mac_port_get_caps(str
+ }
+ }
+
+-static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
+-{
+- return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
+-}
+-
+ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+ {
+@@ -2801,7 +2785,7 @@ static void mt7531_mac_port_get_caps(str
+ break;
+
+ case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
+- if (mt7531_is_rgmii_port(priv, port)) {
++ if (!priv->p5_sgmii) {
+ phy_interface_set_rgmii(config->supported_interfaces);
+ break;
+ }
+@@ -2868,7 +2852,7 @@ static int mt7531_rgmii_setup(struct mt7
+ {
+ u32 val;
+
+- if (!mt7531_is_rgmii_port(priv, port)) {
++ if (priv->p5_sgmii) {
+ dev_err(priv->dev, "RGMII mode is not available for port %d\n",
+ port);
+ return -EINVAL;
+@@ -3111,7 +3095,7 @@ mt7531_cpu_port_config(struct dsa_switch
+
+ switch (port) {
+ case 5:
+- if (mt7531_is_rgmii_port(priv, port))
++ if (!priv->p5_sgmii)
+ interface = PHY_INTERFACE_MODE_RGMII;
+ else
+ interface = PHY_INTERFACE_MODE_2500BASEX;
+@@ -3263,7 +3247,7 @@ mt753x_setup(struct dsa_switch *ds)
+ mt7530_free_irq_common(priv);
+
+ if (priv->create_sgmii) {
+- ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv));
++ ret = priv->create_sgmii(priv);
+ if (ret && priv->irq)
+ mt7530_free_irq(priv);
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -717,7 +717,6 @@ enum p5_interface_select {
+ P5_INTF_SEL_PHY_P0,
+ P5_INTF_SEL_PHY_P4,
+ P5_INTF_SEL_GMAC5,
+- P5_INTF_SEL_GMAC5_SGMII,
+ };
+
+ struct mt7530_priv;
+@@ -786,6 +785,8 @@ struct mt753x_info {
+ * registers
+ * @p6_interface Holding the current port 6 interface
+ * @p5_intf_sel: Holding the current port 5 interface select
++ * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
++ * has got SGMII
+ * @irq: IRQ number of the switch
+ * @irq_domain: IRQ domain of the switch irq_chip
+ * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
+@@ -807,6 +808,7 @@ struct mt7530_priv {
+ phy_interface_t p6_interface;
+ phy_interface_t p5_interface;
+ enum p5_interface_select p5_intf_sel;
++ bool p5_sgmii;
+ u8 mirror_rx;
+ u8 mirror_tx;
+ struct mt7530_port ports[MT7530_NUM_PORTS];
+@@ -816,7 +818,7 @@ struct mt7530_priv {
+ int irq;
+ struct irq_domain *irq_domain;
+ u32 irq_enable;
+- int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
++ int (*create_sgmii)(struct mt7530_priv *priv);
+ u8 active_cpu_ports;
+ };
+
--- /dev/null
+From c91b7fb8fbb2e18ebb497e67f4252cec78e3a29b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:55 +0300
+Subject: [PATCH 08/30] net: dsa: mt7530: improve comments regarding switch
+ ports
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There's no logic to numerically order the CPU ports. Just state the port
+number instead.
+
+Remove the irrelevant PHY muxing information from
+mt7530_mac_port_get_caps(). Explain the supported MII modes instead.
+
+Remove the out of place PHY muxing information from
+mt753x_phylink_mac_config(). The function is for MT7530, MT7531, and the
+switch on the MT7988 SoC but there's no PHY muxing on MT7531 or the switch
+on the MT7988 SoC.
+
+These comments were gradually introduced with the commits below.
+commit ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API")
+commit 38f790a80560 ("net: dsa: mt7530: Add support for port 5")
+commit 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding
+a new hardware")
+commit c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch")
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-4-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 30 ++++++++++++++++++++----------
+ 1 file changed, 20 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2751,12 +2751,14 @@ static void mt7530_mac_port_get_caps(str
+ struct phylink_config *config)
+ {
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ /* Ports which are connected to switch PHYs. There is no MII pinout. */
++ case 0 ... 4:
+ __set_bit(PHY_INTERFACE_MODE_GMII,
+ config->supported_interfaces);
+ break;
+
+- case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
++ /* Port 5 supports rgmii with delays, mii, and gmii. */
++ case 5:
+ phy_interface_set_rgmii(config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_MII,
+ config->supported_interfaces);
+@@ -2764,7 +2766,8 @@ static void mt7530_mac_port_get_caps(str
+ config->supported_interfaces);
+ break;
+
+- case 6: /* 1st cpu port */
++ /* Port 6 supports rgmii and trgmii. */
++ case 6:
+ __set_bit(PHY_INTERFACE_MODE_RGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_TRGMII,
+@@ -2779,19 +2782,24 @@ static void mt7531_mac_port_get_caps(str
+ struct mt7530_priv *priv = ds->priv;
+
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ /* Ports which are connected to switch PHYs. There is no MII pinout. */
++ case 0 ... 4:
+ __set_bit(PHY_INTERFACE_MODE_GMII,
+ config->supported_interfaces);
+ break;
+
+- case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
++ /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on
++ * MT7531AE.
++ */
++ case 5:
+ if (!priv->p5_sgmii) {
+ phy_interface_set_rgmii(config->supported_interfaces);
+ break;
+ }
+ fallthrough;
+
+- case 6: /* 1st cpu port supports sgmii/8023z only */
++ /* Port 6 supports sgmii/802.3z. */
++ case 6:
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+@@ -2810,11 +2818,13 @@ static void mt7988_mac_port_get_caps(str
+ phy_interface_zero(config->supported_interfaces);
+
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ /* Ports which are connected to switch PHYs. There is no MII pinout. */
++ case 0 ... 4:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ break;
+
++ /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
+ case 6:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+@@ -2978,12 +2988,12 @@ mt753x_phylink_mac_config(struct dsa_swi
+ u32 mcr_cur, mcr_new;
+
+ switch (port) {
+- case 0 ... 4: /* Internal phy */
++ case 0 ... 4:
+ if (state->interface != PHY_INTERFACE_MODE_GMII &&
+ state->interface != PHY_INTERFACE_MODE_INTERNAL)
+ goto unsupported;
+ break;
+- case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
++ case 5:
+ if (priv->p5_interface == state->interface)
+ break;
+
+@@ -2993,7 +3003,7 @@ mt753x_phylink_mac_config(struct dsa_swi
+ if (priv->p5_intf_sel != P5_DISABLED)
+ priv->p5_interface = state->interface;
+ break;
+- case 6: /* 1st cpu port */
++ case 6:
+ if (priv->p6_interface == state->interface)
+ break;
+
--- /dev/null
+From c1b2294a9b4b9b6c0cbe58666cb86e0a9cb0abfd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:56 +0300
+Subject: [PATCH 09/30] net: dsa: mt7530: improve code path for setting up port
+ 5
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There're two code paths for setting up port 5:
+
+mt7530_setup()
+-> mt7530_setup_port5()
+
+mt753x_phylink_mac_config()
+-> mt753x_mac_config()
+ -> mt7530_mac_config()
+ -> mt7530_setup_port5()
+
+Currently mt7530_setup_port5() from mt7530_setup() always runs. If port 5
+is used as a CPU, DSA, or user port, mt7530_setup_port5() from
+mt753x_phylink_mac_config() won't run. That is because priv->p5_interface
+set on mt7530_setup_port5() will match state->interface on
+mt753x_phylink_mac_config() which will stop running mt7530_setup_port5()
+again.
+
+Therefore, mt7530_setup_port5() will never run from
+mt753x_phylink_mac_config().
+
+Address this by not running mt7530_setup_port5() from mt7530_setup() if
+port 5 is used as a CPU, DSA, or user port. This driver isn't in the
+dsa_switches_apply_workarounds[] array so phylink will always be present.
+
+To keep the cases where port 5 isn't controlled by phylink working as
+before, preserve the mt7530_setup_port5() call from mt7530_setup().
+
+Do not set priv->p5_intf_sel to P5_DISABLED. It is already set to that when
+"priv" is allocated.
+
+Move setting the interface to a more specific location. It's supposed to be
+overwritten if PHY muxing is detected.
+
+Improve the comment which explains the process.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-5-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 17 ++++++++---------
+ 1 file changed, 8 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2529,16 +2529,15 @@ mt7530_setup(struct dsa_switch *ds)
+ return ret;
+
+ /* Setup port 5 */
+- priv->p5_intf_sel = P5_DISABLED;
+- interface = PHY_INTERFACE_MODE_NA;
+-
+ if (!dsa_is_unused_port(ds, 5)) {
+ priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+- ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
+- if (ret && ret != -ENODEV)
+- return ret;
+ } else {
+- /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
++ /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.
++ * Set priv->p5_intf_sel to the appropriate value if PHY muxing
++ * is detected.
++ */
++ interface = PHY_INTERFACE_MODE_NA;
++
+ for_each_child_of_node(dn, mac_np) {
+ if (!of_device_is_compatible(mac_np,
+ "mediatek,eth-mac"))
+@@ -2569,6 +2568,8 @@ mt7530_setup(struct dsa_switch *ds)
+ of_node_put(phy_node);
+ break;
+ }
++
++ mt7530_setup_port5(ds, interface);
+ }
+
+ #ifdef CONFIG_GPIOLIB
+@@ -2579,8 +2580,6 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+ #endif /* CONFIG_GPIOLIB */
+
+- mt7530_setup_port5(ds, interface);
+-
+ /* Flush the FDB table */
+ ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
+ if (ret < 0)
--- /dev/null
+From cd1cee68e57eedb460a68d1f42abf9f740b17e94 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:57 +0300
+Subject: [PATCH 10/30] net: dsa: mt7530: do not set priv->p5_interface on
+ mt7530_setup_port5()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Running mt7530_setup_port5() from mt7530_setup() used to handle all cases
+of configuring port 5, including phylink.
+
+Setting priv->p5_interface under mt7530_setup_port5() makes sure that
+mt7530_setup_port5() from mt753x_phylink_mac_config() won't run.
+
+The commit ("net: dsa: mt7530: improve code path for setting up port 5")
+makes so that mt7530_setup_port5() from mt7530_setup() runs only on
+non-phylink cases.
+
+Get rid of unnecessarily setting priv->p5_interface under
+mt7530_setup_port5() as port 5 phylink configuration will be done by
+running mt7530_setup_port5() from mt753x_phylink_mac_config() now.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-6-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -978,8 +978,6 @@ static void mt7530_setup_port5(struct ds
+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
+ val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
+
+- priv->p5_interface = interface;
+-
+ unlock_exit:
+ mutex_unlock(&priv->reg_mutex);
+ }
--- /dev/null
+From e55a68aeb0f8b9c74b582b7a5e92b82988832bf8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Jan 2024 08:35:58 +0300
+Subject: [PATCH 11/30] net: dsa: mt7530: do not run mt7530_setup_port5() if
+ port 5 is disabled
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There's no need to run all the code on mt7530_setup_port5() if port 5 is
+disabled. The only case for calling mt7530_setup_port5() from
+mt7530_setup() is when PHY muxing is enabled. That is because port 5 is not
+defined as a port on the devicetree, therefore, it cannot be controlled by
+phylink.
+
+Because of this, run mt7530_setup_port5() if priv->p5_intf_sel is
+P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4. Remove the P5_DISABLED case from
+mt7530_setup_port5().
+
+Stop initialising the interface variable as the remaining cases will always
+call mt7530_setup_port5() with it initialised.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-7-042401f2b279@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 9 +++------
+ 1 file changed, 3 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -942,9 +942,6 @@ static void mt7530_setup_port5(struct ds
+ /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+ val &= ~MHWTRAP_P5_DIS;
+ break;
+- case P5_DISABLED:
+- interface = PHY_INTERFACE_MODE_NA;
+- break;
+ default:
+ dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
+ priv->p5_intf_sel);
+@@ -2534,8 +2531,6 @@ mt7530_setup(struct dsa_switch *ds)
+ * Set priv->p5_intf_sel to the appropriate value if PHY muxing
+ * is detected.
+ */
+- interface = PHY_INTERFACE_MODE_NA;
+-
+ for_each_child_of_node(dn, mac_np) {
+ if (!of_device_is_compatible(mac_np,
+ "mediatek,eth-mac"))
+@@ -2567,7 +2562,9 @@ mt7530_setup(struct dsa_switch *ds)
+ break;
+ }
+
+- mt7530_setup_port5(ds, interface);
++ if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||
++ priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)
++ mt7530_setup_port5(ds, interface);
+ }
+
+ #ifdef CONFIG_GPIOLIB
--- /dev/null
+From 1f538cda24bcb69919da2fcac0211b66281d3d4e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:02 +0300
+Subject: [PATCH 12/30] net: dsa: mt7530: empty default case on
+ mt7530_setup_port5()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There're two code paths for setting up port 5:
+
+mt7530_setup()
+-> mt7530_setup_port5()
+
+mt753x_phylink_mac_config()
+-> mt753x_mac_config()
+ -> mt7530_mac_config()
+ -> mt7530_setup_port5()
+
+On the first code path, priv->p5_intf_sel is either set to
+P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4 when mt7530_setup_port5() is run.
+
+On the second code path, priv->p5_intf_sel is set to P5_INTF_SEL_GMAC5 when
+mt7530_setup_port5() is run.
+
+Empty the default case which will never run but is needed nonetheless to
+handle all the remaining enumeration values.
+
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-1-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -943,9 +943,7 @@ static void mt7530_setup_port5(struct ds
+ val &= ~MHWTRAP_P5_DIS;
+ break;
+ default:
+- dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
+- priv->p5_intf_sel);
+- goto unlock_exit;
++ break;
+ }
+
+ /* Setup RGMII settings */
+@@ -975,7 +973,6 @@ static void mt7530_setup_port5(struct ds
+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
+ val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
+
+-unlock_exit:
+ mutex_unlock(&priv->reg_mutex);
+ }
+
--- /dev/null
+From 12c511cd31c2dc6bd96e4a89f7709d515aa8a76b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:03 +0300
+Subject: [PATCH 13/30] net: dsa: mt7530: move XTAL check to mt7530_setup()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The crystal frequency concerns the switch core. The frequency should be
+checked when the switch is being set up so the driver can reject the
+unsupported hardware earlier and without requiring port 6 to be used.
+
+Move it to mt7530_setup(). Drop the unnecessary function printing.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-2-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -422,13 +422,6 @@ mt7530_pad_clk_setup(struct dsa_switch *
+
+ xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
+
+- if (xtal == HWTRAP_XTAL_20MHZ) {
+- dev_err(priv->dev,
+- "%s: MT7530 with a 20MHz XTAL is not supported!\n",
+- __func__);
+- return -EINVAL;
+- }
+-
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ trgint = 0;
+@@ -2458,6 +2451,12 @@ mt7530_setup(struct dsa_switch *ds)
+ return -ENODEV;
+ }
+
++ if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
++ dev_err(priv->dev,
++ "MT7530 with a 20MHz XTAL is not supported!\n");
++ return -EINVAL;
++ }
++
+ /* Reset the switch through internal reset */
+ mt7530_write(priv, MT7530_SYS_CTRL,
+ SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
--- /dev/null
+From c33899a6a8c1a5723afbfc075600aba2e2bdbea7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:04 +0300
+Subject: [PATCH 14/30] net: dsa: mt7530: simplify mt7530_pad_clk_setup()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This code is from before this driver was converted to phylink API. Phylink
+deals with the unsupported interface cases before mt7530_pad_clk_setup() is
+run. Therefore, the default case would never run. However, it must be
+defined nonetheless to handle all the remaining enumeration values, the
+phy-modes.
+
+Switch to if statement for RGMII and return which simplifies the code and
+saves an indent.
+
+Set P6_INTF_MODE, which is the three least significant bits of the
+MT7530_P6ECR register, to 0 for RGMII even though it will already be 0
+after reset. This is to keep supporting dynamic reconfiguration of the port
+in the case the interface changes from TRGMII to RGMII.
+
+Disable the TRGMII clocks for all cases. They will be enabled if TRGMII is
+being used.
+
+Read XTAL after checking for RGMII as it's only needed for the TRGMII
+interface mode.
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-3-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 91 ++++++++++++++++++----------------------
+ 1 file changed, 40 insertions(+), 51 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -418,65 +418,54 @@ static int
+ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- u32 ncpo1, ssc_delta, trgint, xtal;
++ u32 ncpo1, ssc_delta, xtal;
+
+- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
++ /* Disable the MT7530 TRGMII clocks */
++ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
+
+- switch (interface) {
+- case PHY_INTERFACE_MODE_RGMII:
+- trgint = 0;
+- break;
+- case PHY_INTERFACE_MODE_TRGMII:
+- trgint = 1;
+- if (xtal == HWTRAP_XTAL_25MHZ)
+- ssc_delta = 0x57;
+- else
+- ssc_delta = 0x87;
+- if (priv->id == ID_MT7621) {
+- /* PLL frequency: 125MHz: 1.0GBit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
+- ncpo1 = 0x0640;
+- if (xtal == HWTRAP_XTAL_25MHZ)
+- ncpo1 = 0x0a00;
+- } else { /* PLL frequency: 250MHz: 2.0Gbit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
+- ncpo1 = 0x0c80;
+- if (xtal == HWTRAP_XTAL_25MHZ)
+- ncpo1 = 0x1400;
+- }
+- break;
+- default:
+- dev_err(priv->dev, "xMII interface %d not supported\n",
+- interface);
+- return -EINVAL;
++ if (interface == PHY_INTERFACE_MODE_RGMII) {
++ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
++ P6_INTF_MODE(0));
++ return 0;
+ }
+
+- mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
+- P6_INTF_MODE(trgint));
++ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
+
+- if (trgint) {
+- /* Disable the MT7530 TRGMII clocks */
+- core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
+-
+- /* Setup the MT7530 TRGMII Tx Clock */
+- core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
+- core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
+- core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
+- core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
+- core_write(priv, CORE_PLL_GROUP4,
+- RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
+- RG_SYSPLL_BIAS_LPF_EN);
+- core_write(priv, CORE_PLL_GROUP2,
+- RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
+- RG_SYSPLL_POSDIV(1));
+- core_write(priv, CORE_PLL_GROUP7,
+- RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
+- RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
++ xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
+
+- /* Enable the MT7530 TRGMII clocks */
+- core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
++ if (xtal == HWTRAP_XTAL_25MHZ)
++ ssc_delta = 0x57;
++ else
++ ssc_delta = 0x87;
++
++ if (priv->id == ID_MT7621) {
++ /* PLL frequency: 125MHz: 1.0GBit */
++ if (xtal == HWTRAP_XTAL_40MHZ)
++ ncpo1 = 0x0640;
++ if (xtal == HWTRAP_XTAL_25MHZ)
++ ncpo1 = 0x0a00;
++ } else { /* PLL frequency: 250MHz: 2.0Gbit */
++ if (xtal == HWTRAP_XTAL_40MHZ)
++ ncpo1 = 0x0c80;
++ if (xtal == HWTRAP_XTAL_25MHZ)
++ ncpo1 = 0x1400;
+ }
+
++ /* Setup the MT7530 TRGMII Tx Clock */
++ core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
++ core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
++ core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
++ core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
++ core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
++ RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
++ core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL |
++ RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1));
++ core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG |
++ RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
++
++ /* Enable the MT7530 TRGMII clocks */
++ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
++
+ return 0;
+ }
+
--- /dev/null
+From e612922de7070a28802216650ee88128a57290de Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:05 +0300
+Subject: [PATCH 15/30] net: dsa: mt7530: call port 6 setup from
+ mt7530_mac_config()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+mt7530_pad_clk_setup() is called if port 6 is enabled. It used to do more
+things than setting up port 6. That part was moved to more appropriate
+locations, mt7530_setup() and mt7530_pll_setup().
+
+Now that all it does is set up port 6, rename it to mt7530_setup_port6(),
+and move it to a more appropriate location, under mt7530_mac_config().
+
+Change mt7530_setup_port6() to void as there're no error cases.
+
+Leave an empty mt7530_pad_clk_setup() to satisfy the pad_setup function
+pointer.
+
+This is the code path for setting up the ports before:
+
+dsa_switch_ops :: phylink_mac_config() -> mt753x_phylink_mac_config()
+-> mt753x_mac_config()
+ -> mt753x_info :: mac_port_config() -> mt7530_mac_config()
+ -> mt7530_setup_port5()
+-> mt753x_pad_setup()
+ -> mt753x_info :: pad_setup() -> mt7530_pad_clk_setup()
+
+This is after:
+
+dsa_switch_ops :: phylink_mac_config() -> mt753x_phylink_mac_config()
+-> mt753x_mac_config()
+ -> mt753x_info :: mac_port_config() -> mt7530_mac_config()
+ -> mt7530_setup_port5()
+ -> mt7530_setup_port6()
+
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-4-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 19 +++++++++++--------
+ 1 file changed, 11 insertions(+), 8 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -414,8 +414,8 @@ mt753x_preferred_default_local_cpu_port(
+ }
+
+ /* Setup port 6 interface mode and TRGMII TX circuit */
+-static int
+-mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
++static void
++mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface)
+ {
+ struct mt7530_priv *priv = ds->priv;
+ u32 ncpo1, ssc_delta, xtal;
+@@ -426,7 +426,7 @@ mt7530_pad_clk_setup(struct dsa_switch *
+ if (interface == PHY_INTERFACE_MODE_RGMII) {
+ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
+ P6_INTF_MODE(0));
+- return 0;
++ return;
+ }
+
+ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
+@@ -465,7 +465,11 @@ mt7530_pad_clk_setup(struct dsa_switch *
+
+ /* Enable the MT7530 TRGMII clocks */
+ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
++}
+
++static int
++mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
++{
+ return 0;
+ }
+
+@@ -2826,11 +2830,10 @@ mt7530_mac_config(struct dsa_switch *ds,
+ {
+ struct mt7530_priv *priv = ds->priv;
+
+- /* Only need to setup port5. */
+- if (port != 5)
+- return 0;
+-
+- mt7530_setup_port5(priv->ds, interface);
++ if (port == 5)
++ mt7530_setup_port5(priv->ds, interface);
++ else if (port == 6)
++ mt7530_setup_port6(priv->ds, interface);
+
+ return 0;
+ }
--- /dev/null
+From af83e0c7d766078fcd5580c0c81b9e5b55ff5906 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:06 +0300
+Subject: [PATCH 16/30] net: dsa: mt7530: remove pad_setup function pointer
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The pad_setup function pointer was introduced with 88bdef8be9f6 ("net: dsa:
+mt7530: Extend device data ready for adding a new hardware"). It was being
+used to set up the core clock and port 6 of the MT7530 switch, and pll of
+the MT7531 switch.
+
+All of these were moved to more appropriate locations, and it was never
+used for the switch on the MT7988 SoC. Therefore, this function pointer
+hasn't got a use anymore. Remove it.
+
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-5-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 36 ++----------------------------------
+ drivers/net/dsa/mt7530.h | 3 ---
+ 2 files changed, 2 insertions(+), 37 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -467,18 +467,6 @@ mt7530_setup_port6(struct dsa_switch *ds
+ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
+ }
+
+-static int
+-mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
+-{
+- return 0;
+-}
+-
+-static int
+-mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
+-{
+- return 0;
+-}
+-
+ static void
+ mt7531_pll_setup(struct mt7530_priv *priv)
+ {
+@@ -2817,14 +2805,6 @@ static void mt7988_mac_port_get_caps(str
+ }
+
+ static int
+-mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
+-{
+- struct mt7530_priv *priv = ds->priv;
+-
+- return priv->info->pad_setup(ds, state->interface);
+-}
+-
+-static int
+ mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ phy_interface_t interface)
+ {
+@@ -2989,8 +2969,6 @@ mt753x_phylink_mac_config(struct dsa_swi
+ if (priv->p6_interface == state->interface)
+ break;
+
+- mt753x_pad_setup(ds, state);
+-
+ if (mt753x_mac_config(ds, port, mode, state) < 0)
+ goto unsupported;
+
+@@ -3307,11 +3285,6 @@ mt753x_conduit_state_change(struct dsa_s
+ mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
+ }
+
+-static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
+-{
+- return 0;
+-}
+-
+ static int mt7988_setup(struct dsa_switch *ds)
+ {
+ struct mt7530_priv *priv = ds->priv;
+@@ -3375,7 +3348,6 @@ const struct mt753x_info mt753x_table[]
+ .phy_write_c22 = mt7530_phy_write_c22,
+ .phy_read_c45 = mt7530_phy_read_c45,
+ .phy_write_c45 = mt7530_phy_write_c45,
+- .pad_setup = mt7530_pad_clk_setup,
+ .mac_port_get_caps = mt7530_mac_port_get_caps,
+ .mac_port_config = mt7530_mac_config,
+ },
+@@ -3387,7 +3359,6 @@ const struct mt753x_info mt753x_table[]
+ .phy_write_c22 = mt7530_phy_write_c22,
+ .phy_read_c45 = mt7530_phy_read_c45,
+ .phy_write_c45 = mt7530_phy_write_c45,
+- .pad_setup = mt7530_pad_clk_setup,
+ .mac_port_get_caps = mt7530_mac_port_get_caps,
+ .mac_port_config = mt7530_mac_config,
+ },
+@@ -3399,7 +3370,6 @@ const struct mt753x_info mt753x_table[]
+ .phy_write_c22 = mt7531_ind_c22_phy_write,
+ .phy_read_c45 = mt7531_ind_c45_phy_read,
+ .phy_write_c45 = mt7531_ind_c45_phy_write,
+- .pad_setup = mt7531_pad_setup,
+ .cpu_port_config = mt7531_cpu_port_config,
+ .mac_port_get_caps = mt7531_mac_port_get_caps,
+ .mac_port_config = mt7531_mac_config,
+@@ -3412,7 +3382,6 @@ const struct mt753x_info mt753x_table[]
+ .phy_write_c22 = mt7531_ind_c22_phy_write,
+ .phy_read_c45 = mt7531_ind_c45_phy_read,
+ .phy_write_c45 = mt7531_ind_c45_phy_write,
+- .pad_setup = mt7988_pad_setup,
+ .cpu_port_config = mt7988_cpu_port_config,
+ .mac_port_get_caps = mt7988_mac_port_get_caps,
+ .mac_port_config = mt7988_mac_config,
+@@ -3442,9 +3411,8 @@ mt7530_probe_common(struct mt7530_priv *
+ /* Sanity check if these required device operations are filled
+ * properly.
+ */
+- if (!priv->info->sw_setup || !priv->info->pad_setup ||
+- !priv->info->phy_read_c22 || !priv->info->phy_write_c22 ||
+- !priv->info->mac_port_get_caps ||
++ if (!priv->info->sw_setup || !priv->info->phy_read_c22 ||
++ !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps ||
+ !priv->info->mac_port_config)
+ return -EINVAL;
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -734,8 +734,6 @@ struct mt753x_pcs {
+ * @phy_write_c22: Holding the way writing PHY port using C22
+ * @phy_read_c45: Holding the way reading PHY port using C45
+ * @phy_write_c45: Holding the way writing PHY port using C45
+- * @pad_setup: Holding the way setting up the bus pad for a certain
+- * MAC port
+ * @phy_mode_supported: Check if the PHY type is being supported on a certain
+ * port
+ * @mac_port_validate: Holding the way to set addition validate type for a
+@@ -756,7 +754,6 @@ struct mt753x_info {
+ int regnum);
+ int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
+ int regnum, u16 val);
+- int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
+ int (*cpu_port_config)(struct dsa_switch *ds, int port);
+ void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
+ struct phylink_config *config);
--- /dev/null
+From 9716e3e2c21547c97a9d79119da8fdce5659c2cc Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:07 +0300
+Subject: [PATCH 17/30] net: dsa: mt7530: correct port capabilities of MT7988
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On the switch on the MT7988 SoC, as shown in Block Diagram 8.1.1.3 on page
+125 of "MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open
+Version) v0.1", there are only 4 PHYs. That's port 0 to 3. Set the case for
+ports which connect to switch PHYs to '0 ... 3'.
+
+Port 4 and 5 are not used at all in this design.
+
+Link: https://wiki.banana-pi.org/Banana_Pi_BPI-R4#Documents [1]
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-6-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2790,7 +2790,7 @@ static void mt7988_mac_port_get_caps(str
+
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+- case 0 ... 4:
++ case 0 ... 3:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ break;
--- /dev/null
+From 4d7b17712513710778c0f2f83ea5d9b55ed58c36 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 6 Feb 2024 01:08:08 +0300
+Subject: [PATCH 18/30] net: dsa: mt7530: do not clear
+ config->supported_interfaces
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There's no need to clear the config->supported_interfaces bitmap before
+reporting the supported interfaces as all bits in the bitmap will already
+be initialized to zero when the phylink_config structure is allocated. The
+"config" pointer points to &dp->phylink_config, and "dp" is allocated by
+dsa_port_touch() with kzalloc(), so all its fields are filled with zeroes.
+
+There's no code that would change the bitmap beforehand. Remove it.
+
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-7-d7d92a185cb1@arinc9.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2786,8 +2786,6 @@ static void mt7531_mac_port_get_caps(str
+ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+ {
+- phy_interface_zero(config->supported_interfaces);
+-
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+ case 0 ... 3:
--- /dev/null
+From 69e689e28191f9a242de6821a85f2c5ae4dbd5ae Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:42:57 +0200
+Subject: [PATCH 19/30] net: dsa: mt7530: remove .mac_port_config for MT7988
+ and make it optional
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+For the switch on the MT7988 SoC, the mac_port_config member for ID_MT7988
+in mt753x_table is not needed as the interfaces of all MACs are already
+handled on mt7988_mac_port_get_caps().
+
+Therefore, remove the mac_port_config member from ID_MT7988 in
+mt753x_table. Before calling priv->info->mac_port_config(), if there's no
+mac_port_config member in mt753x_table, exit mt753x_mac_config()
+successfully.
+
+Remove calling priv->info->mac_port_config() from the sanity check as the
+sanity check requires a pointer to a mac_port_config function to be
+non-NULL. This will fail for MT7988 as mac_port_config won't be a member of
+its info table.
+
+Co-developed-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 18 ++++--------------
+ 1 file changed, 4 insertions(+), 14 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2869,17 +2869,6 @@ static bool mt753x_is_mac_port(u32 port)
+ }
+
+ static int
+-mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+- phy_interface_t interface)
+-{
+- if (dsa_is_cpu_port(ds, port) &&
+- interface == PHY_INTERFACE_MODE_INTERNAL)
+- return 0;
+-
+- return -EINVAL;
+-}
+-
+-static int
+ mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ phy_interface_t interface)
+ {
+@@ -2919,6 +2908,9 @@ mt753x_mac_config(struct dsa_switch *ds,
+ {
+ struct mt7530_priv *priv = ds->priv;
+
++ if (!priv->info->mac_port_config)
++ return 0;
++
+ return priv->info->mac_port_config(ds, port, mode, state->interface);
+ }
+
+@@ -3382,7 +3374,6 @@ const struct mt753x_info mt753x_table[]
+ .phy_write_c45 = mt7531_ind_c45_phy_write,
+ .cpu_port_config = mt7988_cpu_port_config,
+ .mac_port_get_caps = mt7988_mac_port_get_caps,
+- .mac_port_config = mt7988_mac_config,
+ },
+ };
+ EXPORT_SYMBOL_GPL(mt753x_table);
+@@ -3410,8 +3401,7 @@ mt7530_probe_common(struct mt7530_priv *
+ * properly.
+ */
+ if (!priv->info->sw_setup || !priv->info->phy_read_c22 ||
+- !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps ||
+- !priv->info->mac_port_config)
++ !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps)
+ return -EINVAL;
+
+ priv->id = priv->info->id;
--- /dev/null
+From f8faa3a04ca860b31f22d7d526c5e3f3de511a8f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:42:58 +0200
+Subject: [PATCH 20/30] net: dsa: mt7530: set interrupt register only for
+ MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Setting this register related to interrupts is only needed for the MT7530
+switch. Make an exclusive check to ensure this.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2254,7 +2254,7 @@ mt7530_setup_irq(struct mt7530_priv *pri
+ }
+
+ /* This register must be set for MT7530 to properly fire interrupts */
+- if (priv->id != ID_MT7531)
++ if (priv->id == ID_MT7530 || priv->id == ID_MT7621)
+ mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
+
+ ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
--- /dev/null
+From 80f4f866d7dad41b12cf37476c38766a89b8b5c4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:42:59 +0200
+Subject: [PATCH 21/30] net: dsa: mt7530: do not use SW_PHY_RST to reset MT7531
+ switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+According to the document MT7531 Reference Manual for Development Board
+v1.0, the SW_PHY_RST bit on the SYS_CTRL register doesn't exist for
+MT7531. This is likely why forcing link down on all ports is necessary for
+MT7531.
+
+Therefore, do not set SW_PHY_RST on mt7531_setup().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2657,14 +2657,12 @@ mt7531_setup(struct dsa_switch *ds)
+ val = mt7530_read(priv, MT7531_TOP_SIG_SR);
+ priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
+
+- /* all MACs must be forced link-down before sw reset */
++ /* Force link down on all ports before internal reset */
+ for (i = 0; i < MT7530_NUM_PORTS; i++)
+ mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
+
+ /* Reset the switch through internal reset */
+- mt7530_write(priv, MT7530_SYS_CTRL,
+- SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
+- SYS_CTRL_REG_RST);
++ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
+
+ if (!priv->p5_sgmii) {
+ mt7531_pll_setup(priv);
--- /dev/null
+From 58670652cacb7c5752e01f29979d0ca4cdbfcc0a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:00 +0200
+Subject: [PATCH 22/30] net: dsa: mt7530: get rid of useless error returns on
+ phylink code path
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Remove error returns on the cases where they are already handled with the
+function the mac_port_get_caps member in mt753x_table points to.
+
+mt7531_mac_config() is also called from mt7531_cpu_port_config() outside of
+phylink but the port and interface modes are already handled there.
+
+Change the functions and the mac_port_config function pointer to void now
+that there're no error returns anymore.
+
+Remove mt753x_is_mac_port() that used to help the said error returns.
+
+On mt7531_mac_config(), switch to if statements to simplify the code.
+
+Remove internal phy cases from mt753x_phylink_mac_config(), there is no
+need to check the interface mode as that's already handled with the
+function the mac_port_get_caps member in mt753x_table points to.
+
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 81 ++++++++--------------------------------
+ drivers/net/dsa/mt7530.h | 6 +--
+ 2 files changed, 19 insertions(+), 68 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2800,7 +2800,7 @@ static void mt7988_mac_port_get_caps(str
+ }
+ }
+
+-static int
++static void
+ mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ phy_interface_t interface)
+ {
+@@ -2810,22 +2810,14 @@ mt7530_mac_config(struct dsa_switch *ds,
+ mt7530_setup_port5(priv->ds, interface);
+ else if (port == 6)
+ mt7530_setup_port6(priv->ds, interface);
+-
+- return 0;
+ }
+
+-static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
+- phy_interface_t interface,
+- struct phy_device *phydev)
++static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
++ phy_interface_t interface,
++ struct phy_device *phydev)
+ {
+ u32 val;
+
+- if (priv->p5_sgmii) {
+- dev_err(priv->dev, "RGMII mode is not available for port %d\n",
+- port);
+- return -EINVAL;
+- }
+-
+ val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
+ val |= GP_CLK_EN;
+ val &= ~GP_MODE_MASK;
+@@ -2853,20 +2845,14 @@ static int mt7531_rgmii_setup(struct mt7
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ break;
+ default:
+- return -EINVAL;
++ break;
+ }
+ }
+- mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
+
+- return 0;
+-}
+-
+-static bool mt753x_is_mac_port(u32 port)
+-{
+- return (port == 5 || port == 6);
++ mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
+ }
+
+-static int
++static void
+ mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ phy_interface_t interface)
+ {
+@@ -2874,42 +2860,21 @@ mt7531_mac_config(struct dsa_switch *ds,
+ struct phy_device *phydev;
+ struct dsa_port *dp;
+
+- if (!mt753x_is_mac_port(port)) {
+- dev_err(priv->dev, "port %d is not a MAC port\n", port);
+- return -EINVAL;
+- }
+-
+- switch (interface) {
+- case PHY_INTERFACE_MODE_RGMII:
+- case PHY_INTERFACE_MODE_RGMII_ID:
+- case PHY_INTERFACE_MODE_RGMII_RXID:
+- case PHY_INTERFACE_MODE_RGMII_TXID:
++ if (phy_interface_mode_is_rgmii(interface)) {
+ dp = dsa_to_port(ds, port);
+ phydev = dp->slave->phydev;
+- return mt7531_rgmii_setup(priv, port, interface, phydev);
+- case PHY_INTERFACE_MODE_SGMII:
+- case PHY_INTERFACE_MODE_NA:
+- case PHY_INTERFACE_MODE_1000BASEX:
+- case PHY_INTERFACE_MODE_2500BASEX:
+- /* handled in SGMII PCS driver */
+- return 0;
+- default:
+- return -EINVAL;
++ mt7531_rgmii_setup(priv, port, interface, phydev);
+ }
+-
+- return -EINVAL;
+ }
+
+-static int
++static void
+ mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+ const struct phylink_link_state *state)
+ {
+ struct mt7530_priv *priv = ds->priv;
+
+- if (!priv->info->mac_port_config)
+- return 0;
+-
+- return priv->info->mac_port_config(ds, port, mode, state->interface);
++ if (priv->info->mac_port_config)
++ priv->info->mac_port_config(ds, port, mode, state->interface);
+ }
+
+ static struct phylink_pcs *
+@@ -2938,17 +2903,11 @@ mt753x_phylink_mac_config(struct dsa_swi
+ u32 mcr_cur, mcr_new;
+
+ switch (port) {
+- case 0 ... 4:
+- if (state->interface != PHY_INTERFACE_MODE_GMII &&
+- state->interface != PHY_INTERFACE_MODE_INTERNAL)
+- goto unsupported;
+- break;
+ case 5:
+ if (priv->p5_interface == state->interface)
+ break;
+
+- if (mt753x_mac_config(ds, port, mode, state) < 0)
+- goto unsupported;
++ mt753x_mac_config(ds, port, mode, state);
+
+ if (priv->p5_intf_sel != P5_DISABLED)
+ priv->p5_interface = state->interface;
+@@ -2957,16 +2916,10 @@ mt753x_phylink_mac_config(struct dsa_swi
+ if (priv->p6_interface == state->interface)
+ break;
+
+- if (mt753x_mac_config(ds, port, mode, state) < 0)
+- goto unsupported;
++ mt753x_mac_config(ds, port, mode, state);
+
+ priv->p6_interface = state->interface;
+ break;
+- default:
+-unsupported:
+- dev_err(ds->dev, "%s: unsupported %s port: %i\n",
+- __func__, phy_modes(state->interface), port);
+- return;
+ }
+
+ mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
+@@ -3049,7 +3002,6 @@ mt7531_cpu_port_config(struct dsa_switch
+ struct mt7530_priv *priv = ds->priv;
+ phy_interface_t interface;
+ int speed;
+- int ret;
+
+ switch (port) {
+ case 5:
+@@ -3074,9 +3026,8 @@ mt7531_cpu_port_config(struct dsa_switch
+ else
+ speed = SPEED_1000;
+
+- ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
+- if (ret)
+- return ret;
++ mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
++
+ mt7530_write(priv, MT7530_PMCR_P(port),
+ PMCR_CPU_PORT_SETTING(priv->id));
+ mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -760,9 +760,9 @@ struct mt753x_info {
+ void (*mac_port_validate)(struct dsa_switch *ds, int port,
+ phy_interface_t interface,
+ unsigned long *supported);
+- int (*mac_port_config)(struct dsa_switch *ds, int port,
+- unsigned int mode,
+- phy_interface_t interface);
++ void (*mac_port_config)(struct dsa_switch *ds, int port,
++ unsigned int mode,
++ phy_interface_t interface);
+ };
+
+ /* struct mt7530_priv - This is the main data structure for holding the state
--- /dev/null
+From 859df5cf6ff07a9c930be4681284346aa73dd1fb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:01 +0200
+Subject: [PATCH 23/30] net: dsa: mt7530: get rid of
+ priv->info->cpu_port_config()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+priv->info->cpu_port_config() is used for MT7531 and the switch on the
+MT7988 SoC. It sets up the ports described as a CPU port earlier than the
+phylink code path would do.
+
+This function is useless as:
+- Configuring the MACs can be done from the phylink_mac_config code path
+ instead.
+- All the link configuration it does on the CPU ports are later undone with
+ the port_enable, phylink_mac_config, and then phylink_mac_link_up code
+ path [1].
+
+priv->p5_interface and priv->p6_interface were being used to prevent
+configuring the MACs from the phylink_mac_config code path. Remove them now
+that they hold no purpose.
+
+Remove priv->info->cpu_port_config(). On mt753x_phylink_mac_config, switch
+to if statements to simplify the code.
+
+Remove the overwriting of the speed and duplex interfaces for certain
+interface modes. Phylink already provides the speed and duplex variables
+with proper values. Phylink already sets the max speed of TRGMII to
+SPEED_1000. Add SPEED_2500 for PHY_INTERFACE_MODE_2500BASEX to where the
+speed and EEE bits are set instead.
+
+On the switch on the MT7988 SoC, PHY_INTERFACE_MODE_INTERNAL is being used
+to describe the interface mode of the 10G MAC, which is of port 6. On
+mt7988_cpu_port_config() PMCR_FORCE_SPEED_1000 was set via the
+PMCR_CPU_PORT_SETTING() mask. Add SPEED_10000 case to where the speed bits
+are set to cover this. No need to add it to where the EEE bits are set as
+the "MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open Version)
+v0.1" document shows that these bits don't exist on the MT7530_PMCR_P(6)
+register.
+
+Remove the definition of PMCR_CPU_PORT_SETTING() now that it holds no
+purpose.
+
+Change mt753x_cpu_port_enable() to void now that there're no error cases
+left.
+
+Link: https://lore.kernel.org/netdev/ZHy2jQLesdYFMQtO@shell.armlinux.org.uk/ [1]
+Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 114 +++------------------------------------
+ drivers/net/dsa/mt7530.h | 11 ----
+ 2 files changed, 7 insertions(+), 118 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1163,18 +1163,10 @@ mt753x_trap_frames(struct mt7530_priv *p
+ MT753X_BPDU_CPU_ONLY);
+ }
+
+-static int
++static void
+ mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- int ret;
+-
+- /* Setup max capability of CPU port at first */
+- if (priv->info->cpu_port_config) {
+- ret = priv->info->cpu_port_config(ds, port);
+- if (ret)
+- return ret;
+- }
+
+ /* Enable Mediatek header mode on the cpu port */
+ mt7530_write(priv, MT7530_PVC_P(port),
+@@ -1200,8 +1192,6 @@ mt753x_cpu_port_enable(struct dsa_switch
+ /* Set to fallback mode for independent VLAN learning */
+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
+ MT7530_PORT_FALLBACK_MODE);
+-
+- return 0;
+ }
+
+ static int
+@@ -2458,8 +2448,6 @@ mt7530_setup(struct dsa_switch *ds)
+ val |= MHWTRAP_MANUAL;
+ mt7530_write(priv, MT7530_MHWTRAP, val);
+
+- priv->p6_interface = PHY_INTERFACE_MODE_NA;
+-
+ if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+
+@@ -2477,9 +2465,7 @@ mt7530_setup(struct dsa_switch *ds)
+ mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
+
+ if (dsa_is_cpu_port(ds, i)) {
+- ret = mt753x_cpu_port_enable(ds, i);
+- if (ret)
+- return ret;
++ mt753x_cpu_port_enable(ds, i);
+ } else {
+ mt7530_port_disable(ds, i);
+
+@@ -2586,9 +2572,7 @@ mt7531_setup_common(struct dsa_switch *d
+ mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
+
+ if (dsa_is_cpu_port(ds, i)) {
+- ret = mt753x_cpu_port_enable(ds, i);
+- if (ret)
+- return ret;
++ mt753x_cpu_port_enable(ds, i);
+ } else {
+ mt7530_port_disable(ds, i);
+
+@@ -2680,10 +2664,6 @@ mt7531_setup(struct dsa_switch *ds)
+ mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
+ MT7531_GPIO0_INTERRUPT);
+
+- /* Let phylink decide the interface later. */
+- priv->p5_interface = PHY_INTERFACE_MODE_NA;
+- priv->p6_interface = PHY_INTERFACE_MODE_NA;
+-
+ /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
+ * phy_device has not yet been created provided for
+ * phy_[read,write]_mmd_indirect is called, we provide our own
+@@ -2902,26 +2882,9 @@ mt753x_phylink_mac_config(struct dsa_swi
+ struct mt7530_priv *priv = ds->priv;
+ u32 mcr_cur, mcr_new;
+
+- switch (port) {
+- case 5:
+- if (priv->p5_interface == state->interface)
+- break;
+-
++ if (port == 5 || port == 6)
+ mt753x_mac_config(ds, port, mode, state);
+
+- if (priv->p5_intf_sel != P5_DISABLED)
+- priv->p5_interface = state->interface;
+- break;
+- case 6:
+- if (priv->p6_interface == state->interface)
+- break;
+-
+- mt753x_mac_config(ds, port, mode, state);
+-
+- priv->p6_interface = state->interface;
+- break;
+- }
+-
+ mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
+ mcr_new = mcr_cur;
+ mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
+@@ -2957,17 +2920,10 @@ static void mt753x_phylink_mac_link_up(s
+
+ mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
+
+- /* MT753x MAC works in 1G full duplex mode for all up-clocked
+- * variants.
+- */
+- if (interface == PHY_INTERFACE_MODE_TRGMII ||
+- (phy_interface_mode_is_8023z(interface))) {
+- speed = SPEED_1000;
+- duplex = DUPLEX_FULL;
+- }
+-
+ switch (speed) {
+ case SPEED_1000:
++ case SPEED_2500:
++ case SPEED_10000:
+ mcr |= PMCR_FORCE_SPEED_1000;
+ break;
+ case SPEED_100:
+@@ -2985,6 +2941,7 @@ static void mt753x_phylink_mac_link_up(s
+ if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
+ switch (speed) {
+ case SPEED_1000:
++ case SPEED_2500:
+ mcr |= PMCR_FORCE_EEE1G;
+ break;
+ case SPEED_100:
+@@ -2996,61 +2953,6 @@ static void mt753x_phylink_mac_link_up(s
+ mt7530_set(priv, MT7530_PMCR_P(port), mcr);
+ }
+
+-static int
+-mt7531_cpu_port_config(struct dsa_switch *ds, int port)
+-{
+- struct mt7530_priv *priv = ds->priv;
+- phy_interface_t interface;
+- int speed;
+-
+- switch (port) {
+- case 5:
+- if (!priv->p5_sgmii)
+- interface = PHY_INTERFACE_MODE_RGMII;
+- else
+- interface = PHY_INTERFACE_MODE_2500BASEX;
+-
+- priv->p5_interface = interface;
+- break;
+- case 6:
+- interface = PHY_INTERFACE_MODE_2500BASEX;
+-
+- priv->p6_interface = interface;
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- if (interface == PHY_INTERFACE_MODE_2500BASEX)
+- speed = SPEED_2500;
+- else
+- speed = SPEED_1000;
+-
+- mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
+-
+- mt7530_write(priv, MT7530_PMCR_P(port),
+- PMCR_CPU_PORT_SETTING(priv->id));
+- mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
+- speed, DUPLEX_FULL, true, true);
+-
+- return 0;
+-}
+-
+-static int
+-mt7988_cpu_port_config(struct dsa_switch *ds, int port)
+-{
+- struct mt7530_priv *priv = ds->priv;
+-
+- mt7530_write(priv, MT7530_PMCR_P(port),
+- PMCR_CPU_PORT_SETTING(priv->id));
+-
+- mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED,
+- PHY_INTERFACE_MODE_INTERNAL, NULL,
+- SPEED_10000, DUPLEX_FULL, true, true);
+-
+- return 0;
+-}
+-
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+ {
+@@ -3309,7 +3211,6 @@ const struct mt753x_info mt753x_table[]
+ .phy_write_c22 = mt7531_ind_c22_phy_write,
+ .phy_read_c45 = mt7531_ind_c45_phy_read,
+ .phy_write_c45 = mt7531_ind_c45_phy_write,
+- .cpu_port_config = mt7531_cpu_port_config,
+ .mac_port_get_caps = mt7531_mac_port_get_caps,
+ .mac_port_config = mt7531_mac_config,
+ },
+@@ -3321,7 +3222,6 @@ const struct mt753x_info mt753x_table[]
+ .phy_write_c22 = mt7531_ind_c22_phy_write,
+ .phy_read_c45 = mt7531_ind_c45_phy_read,
+ .phy_write_c45 = mt7531_ind_c45_phy_write,
+- .cpu_port_config = mt7988_cpu_port_config,
+ .mac_port_get_caps = mt7988_mac_port_get_caps,
+ },
+ };
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -340,13 +340,6 @@ enum mt7530_vlan_port_acc_frm {
+ PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
+ PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
+ PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
+-#define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
+- PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
+- PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
+- PMCR_TX_EN | PMCR_RX_EN | \
+- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
+- PMCR_FORCE_SPEED_1000 | \
+- PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+
+ #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
+ #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
+@@ -754,7 +747,6 @@ struct mt753x_info {
+ int regnum);
+ int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
+ int regnum, u16 val);
+- int (*cpu_port_config)(struct dsa_switch *ds, int port);
+ void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
+ struct phylink_config *config);
+ void (*mac_port_validate)(struct dsa_switch *ds, int port,
+@@ -780,7 +772,6 @@ struct mt753x_info {
+ * @ports: Holding the state among ports
+ * @reg_mutex: The lock for protecting among process accessing
+ * registers
+- * @p6_interface Holding the current port 6 interface
+ * @p5_intf_sel: Holding the current port 5 interface select
+ * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
+ * has got SGMII
+@@ -802,8 +793,6 @@ struct mt7530_priv {
+ const struct mt753x_info *info;
+ unsigned int id;
+ bool mcm;
+- phy_interface_t p6_interface;
+- phy_interface_t p5_interface;
+ enum p5_interface_select p5_intf_sel;
+ bool p5_sgmii;
+ u8 mirror_rx;
--- /dev/null
+From c74a98baa8d098157975b3f94e496dd3a73e0864 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:02 +0200
+Subject: [PATCH 24/30] net: dsa: mt7530: get rid of mt753x_mac_config()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+There is no need for a separate function to call
+priv->info->mac_port_config(). Call it from mt753x_phylink_mac_config()
+instead and remove mt753x_mac_config().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 14 ++------------
+ 1 file changed, 2 insertions(+), 12 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2847,16 +2847,6 @@ mt7531_mac_config(struct dsa_switch *ds,
+ }
+ }
+
+-static void
+-mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
+- const struct phylink_link_state *state)
+-{
+- struct mt7530_priv *priv = ds->priv;
+-
+- if (priv->info->mac_port_config)
+- priv->info->mac_port_config(ds, port, mode, state->interface);
+-}
+-
+ static struct phylink_pcs *
+ mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
+ phy_interface_t interface)
+@@ -2882,8 +2872,8 @@ mt753x_phylink_mac_config(struct dsa_swi
+ struct mt7530_priv *priv = ds->priv;
+ u32 mcr_cur, mcr_new;
+
+- if (port == 5 || port == 6)
+- mt753x_mac_config(ds, port, mode, state);
++ if ((port == 5 || port == 6) && priv->info->mac_port_config)
++ priv->info->mac_port_config(ds, port, mode, state->interface);
+
+ mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
+ mcr_new = mcr_cur;
--- /dev/null
+From ab1ddb241bc1cb3d80aa51207810edd5cb0bbdc5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:03 +0200
+Subject: [PATCH 25/30] net: dsa: mt7530: put initialising PCS devices code
+ back to original order
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The commit fae463084032 ("net: dsa: mt753x: fix pcs conversion regression")
+fixes regression caused by cpu_port_config manually calling phylink
+operations. cpu_port_config was deemed useless and was removed. Therefore,
+put initialising PCS devices code back to its original order.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3025,17 +3025,9 @@ static int
+ mt753x_setup(struct dsa_switch *ds)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- int i, ret;
++ int ret = priv->info->sw_setup(ds);
++ int i;
+
+- /* Initialise the PCS devices */
+- for (i = 0; i < priv->ds->num_ports; i++) {
+- priv->pcs[i].pcs.ops = priv->info->pcs_ops;
+- priv->pcs[i].pcs.neg_mode = true;
+- priv->pcs[i].priv = priv;
+- priv->pcs[i].port = i;
+- }
+-
+- ret = priv->info->sw_setup(ds);
+ if (ret)
+ return ret;
+
+@@ -3047,6 +3039,14 @@ mt753x_setup(struct dsa_switch *ds)
+ if (ret && priv->irq)
+ mt7530_free_irq_common(priv);
+
++ /* Initialise the PCS devices */
++ for (i = 0; i < priv->ds->num_ports; i++) {
++ priv->pcs[i].pcs.ops = priv->info->pcs_ops;
++ priv->pcs[i].pcs.neg_mode = true;
++ priv->pcs[i].priv = priv;
++ priv->pcs[i].port = i;
++ }
++
+ if (priv->create_sgmii) {
+ ret = priv->create_sgmii(priv);
+ if (ret && priv->irq)
--- /dev/null
+From aa474698f75f4790a4de2052dd487736d2361b2e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:04 +0200
+Subject: [PATCH 26/30] net: dsa: mt7530: sort link settings ops and force link
+ down on all ports
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+port_enable and port_disable clears the link settings. Move that to
+mt7530_setup() and mt7531_setup_common() which set up the switches. This
+way, the link settings are cleared on all ports at setup, and then only
+once with phylink_mac_link_down() when a link goes down.
+
+Enable force mode at setup to apply the force part of the link settings.
+This ensures that disabled ports will have their link down.
+
+Suggested-by: Vladimir Oltean <olteanv@gmail.com>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 14 ++++++++++++--
+ 1 file changed, 12 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1215,7 +1215,6 @@ mt7530_port_enable(struct dsa_switch *ds
+ priv->ports[port].enable = true;
+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
+ priv->ports[port].pm);
+- mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
+
+ mutex_unlock(&priv->reg_mutex);
+
+@@ -1235,7 +1234,6 @@ mt7530_port_disable(struct dsa_switch *d
+ priv->ports[port].enable = false;
+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
+ PCR_MATRIX_CLR);
+- mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
+
+ mutex_unlock(&priv->reg_mutex);
+ }
+@@ -2457,6 +2455,12 @@ mt7530_setup(struct dsa_switch *ds)
+ mt7530_mib_reset(ds);
+
+ for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ /* Clear link settings and enable force mode to force link down
++ * on all ports until they're enabled later.
++ */
++ mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ PMCR_FORCE_MODE, PMCR_FORCE_MODE);
++
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+ PCR_MATRIX_CLR);
+@@ -2562,6 +2566,12 @@ mt7531_setup_common(struct dsa_switch *d
+ UNU_FFP_MASK);
+
+ for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ /* Clear link settings and enable force mode to force link down
++ * on all ports until they're enabled later.
++ */
++ mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7531_FORCE_MODE, MT7531_FORCE_MODE);
++
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+ PCR_MATRIX_CLR);
--- /dev/null
+From 1ca89c2e349d7c5e045911d741dacf4c83d029e7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Fri, 1 Mar 2024 12:43:05 +0200
+Subject: [PATCH 27/30] net: dsa: mt7530: simplify link operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The "MT7621 Giga Switch Programming Guide v0.3", "MT7531 Reference Manual
+for Development Board v1.0", and "MT7988A Wi-Fi 7 Generation Router
+Platform: Datasheet (Open Version) v0.1" documents show that these bits are
+enabled at reset:
+
+PMCR_IFG_XMIT(1) (not part of PMCR_LINK_SETTINGS_MASK)
+PMCR_MAC_MODE (not part of PMCR_LINK_SETTINGS_MASK)
+PMCR_TX_EN
+PMCR_RX_EN
+PMCR_BACKOFF_EN (not part of PMCR_LINK_SETTINGS_MASK)
+PMCR_BACKPR_EN (not part of PMCR_LINK_SETTINGS_MASK)
+PMCR_TX_FC_EN
+PMCR_RX_FC_EN
+
+These bits also don't exist on the MT7530_PMCR_P(6) register of the switch
+on the MT7988 SoC:
+
+PMCR_IFG_XMIT()
+PMCR_MAC_MODE
+PMCR_BACKOFF_EN
+PMCR_BACKPR_EN
+
+Remove the setting of the bits not part of PMCR_LINK_SETTINGS_MASK on
+phylink_mac_config as they're already set.
+
+The bit for setting the port on force mode is already done on
+mt7530_setup() and mt7531_setup_common(). So get rid of
+PMCR_FORCE_MODE_ID() which helped determine which bit to use for the switch
+model.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 12 +-----------
+ drivers/net/dsa/mt7530.h | 2 --
+ 2 files changed, 1 insertion(+), 13 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2880,23 +2880,13 @@ mt753x_phylink_mac_config(struct dsa_swi
+ const struct phylink_link_state *state)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- u32 mcr_cur, mcr_new;
+
+ if ((port == 5 || port == 6) && priv->info->mac_port_config)
+ priv->info->mac_port_config(ds, port, mode, state->interface);
+
+- mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
+- mcr_new = mcr_cur;
+- mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
+- mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
+- PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
+-
+ /* Are we connected to external phy */
+ if (port == 5 && dsa_is_user_port(ds, 5))
+- mcr_new |= PMCR_EXT_PHY;
+-
+- if (mcr_new != mcr_cur)
+- mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
++ mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
+ }
+
+ static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -333,8 +333,6 @@ enum mt7530_vlan_port_acc_frm {
+ MT7531_FORCE_DPX | \
+ MT7531_FORCE_RX_FC | \
+ MT7531_FORCE_TX_FC)
+-#define PMCR_FORCE_MODE_ID(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_FORCE_MODE : PMCR_FORCE_MODE)
+ #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+ PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+ PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
--- /dev/null
+From de16cf680331cd0bd7db97c3f8d376f5eac39cae Mon Sep 17 00:00:00 2001
+From: Justin Swartz <justin.swartz@risingedge.co.za>
+Date: Tue, 5 Mar 2024 06:39:51 +0200
+Subject: [PATCH 28/30] net: dsa: mt7530: disable LEDs before reset
+
+Disable LEDs just before resetting the MT7530 to avoid
+situations where the ESW_P4_LED_0 and ESW_P3_LED_0 pin
+states may cause an unintended external crystal frequency
+to be selected.
+
+The HT_XTAL_FSEL (External Crystal Frequency Selection)
+field of HWTRAP (the Hardware Trap register) stores a
+2-bit value that represents the state of the ESW_P4_LED_0
+and ESW_P4_LED_0 pins (seemingly) sampled just after the
+MT7530 has been reset, as:
+
+ ESW_P4_LED_0 ESW_P3_LED_0 Frequency
+ -----------------------------------------
+ 0 1 20MHz
+ 1 0 40MHz
+ 1 1 25MHz
+
+The value of HT_XTAL_FSEL is bootstrapped by pulling
+ESW_P4_LED_0 and ESW_P3_LED_0 up or down accordingly,
+but:
+
+ if a 40MHz crystal has been selected and
+ the ESW_P3_LED_0 pin is high during reset,
+
+ or a 20MHz crystal has been selected and
+ the ESW_P4_LED_0 pin is high during reset,
+
+ then the value of HT_XTAL_FSEL will indicate
+ that a 25MHz crystal is present.
+
+By default, the state of the LED pins is PHY controlled
+to reflect the link state.
+
+To illustrate, if a board has:
+
+ 5 ports with active low LED control,
+ and HT_XTAL_FSEL bootstrapped for 40MHz.
+
+When the MT7530 is powered up without any external
+connection, only the LED associated with Port 3 is
+illuminated as ESW_P3_LED_0 is low.
+
+In this state, directly after mt7530_setup()'s reset
+is performed, the HWTRAP register (0x7800) reflects
+the intended HT_XTAL_FSEL (HWTRAP bits 10:9) of 40MHz:
+
+ mt7530-mdio mdio-bus:1f: mt7530_read: 00007800 == 00007dcf
+
+ >>> bin(0x7dcf >> 9 & 0b11)
+ '0b10'
+
+But if a cable is connected to Port 3 and the link
+is active before mt7530_setup()'s reset takes place,
+then HT_XTAL_FSEL seems to be set for 25MHz:
+
+ mt7530-mdio mdio-bus:1f: mt7530_read: 00007800 == 00007fcf
+
+ >>> bin(0x7fcf >> 9 & 0b11)
+ '0b11'
+
+Once HT_XTAL_FSEL reflects 25MHz, none of the ports
+are functional until the MT7621 (or MT7530 itself)
+is reset.
+
+By disabling the LED pins just before reset, the chance
+of an unintended HT_XTAL_FSEL value is reduced.
+
+Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
+Link: https://lore.kernel.org/r/20240305043952.21590-1-justin.swartz@risingedge.co.za
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/dsa/mt7530.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2391,6 +2391,12 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+ }
+
++ /* Disable LEDs before reset to prevent the MT7530 sampling a
++ * potentially incorrect HT_XTAL_FSEL value.
++ */
++ mt7530_write(priv, MT7530_LED_EN, 0);
++ usleep_range(1000, 1100);
++
+ /* Reset whole chip through gpio pin or memory-mapped registers for
+ * different type of hardware
+ */
--- /dev/null
+From b9547109205c5e0a27e5bed568b0fc183fff906b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Thu, 14 Mar 2024 12:28:35 +0300
+Subject: [PATCH 30/30] net: dsa: mt7530: prevent possible incorrect XTAL
+ frequency selection
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On MT7530, the HT_XTAL_FSEL field of the HWTRAP register stores a 2-bit
+value that represents the frequency of the crystal oscillator connected to
+the switch IC. The field is populated by the state of the ESW_P4_LED_0 and
+ESW_P4_LED_0 pins, which is done right after reset is deasserted.
+
+ ESW_P4_LED_0 ESW_P3_LED_0 Frequency
+ -----------------------------------------
+ 0 0 Reserved
+ 0 1 20MHz
+ 1 0 40MHz
+ 1 1 25MHz
+
+On MT7531, the XTAL25 bit of the STRAP register stores this. The LAN0LED0
+pin is used to populate the bit. 25MHz when the pin is high, 40MHz when
+it's low.
+
+These pins are also used with LEDs, therefore, their state can be set to
+something other than the bootstrapping configuration. For example, a link
+may be established on port 3 before the DSA subdriver takes control of the
+switch which would set ESW_P3_LED_0 to high.
+
+Currently on mt7530_setup() and mt7531_setup(), 1000 - 1100 usec delay is
+described between reset assertion and deassertion. Some switch ICs in real
+life conditions cannot always have these pins set back to the bootstrapping
+configuration before reset deassertion in this amount of delay. This causes
+wrong crystal frequency to be selected which puts the switch in a
+nonfunctional state after reset deassertion.
+
+The tests below are conducted on an MT7530 with a 40MHz crystal oscillator
+by Justin Swartz.
+
+With a cable from an active peer connected to port 3 before reset, an
+incorrect crystal frequency (0b11 = 25MHz) is selected:
+
+ [1] [3] [5]
+ : : :
+ _____________________________ __________________
+ESW_P4_LED_0 |_______|
+ _____________________________
+ESW_P3_LED_0 |__________________________
+
+ : : : :
+ : : [4]...:
+ : :
+ [2]................:
+
+[1] Reset is asserted.
+[2] Period of 1000 - 1100 usec.
+[3] Reset is deasserted.
+[4] Period of 315 usec. HWTRAP register is populated with incorrect
+ XTAL frequency.
+[5] Signals reflect the bootstrapped configuration.
+
+Increase the delay between reset_control_assert() and
+reset_control_deassert(), and gpiod_set_value_cansleep(priv->reset, 0) and
+gpiod_set_value_cansleep(priv->reset, 1) to 5000 - 5100 usec. This amount
+ensures a higher possibility that the switch IC will have these pins back
+to the bootstrapping configuration before reset deassertion.
+
+With a cable from an active peer connected to port 3 before reset, the
+correct crystal frequency (0b10 = 40MHz) is selected:
+
+ [1] [2-1] [3] [5]
+ : : : :
+ _____________________________ __________________
+ESW_P4_LED_0 |_______|
+ ___________________ _______
+ESW_P3_LED_0 |_________| |__________________
+
+ : : : : :
+ : [2-2]...: [4]...:
+ [2]................:
+
+[1] Reset is asserted.
+[2] Period of 5000 - 5100 usec.
+[2-1] ESW_P3_LED_0 goes low.
+[2-2] Remaining period of 5000 - 5100 usec.
+[3] Reset is deasserted.
+[4] Period of 310 usec. HWTRAP register is populated with bootstrapped
+ XTAL frequency.
+[5] Signals reflect the bootstrapped configuration.
+
+ESW_P3_LED_0 low period before reset deassertion:
+
+ 5000 usec
+ - 5100 usec
+ TEST RESET HOLD
+ # (usec)
+ ---------------------
+ 1 5410
+ 2 5440
+ 3 4375
+ 4 5490
+ 5 5475
+ 6 4335
+ 7 4370
+ 8 5435
+ 9 4205
+ 10 4335
+ 11 3750
+ 12 3170
+ 13 4395
+ 14 4375
+ 15 3515
+ 16 4335
+ 17 4220
+ 18 4175
+ 19 4175
+ 20 4350
+
+ Min 3170
+ Max 5490
+
+ Median 4342.500
+ Avg 4466.500
+
+Revert commit 2920dd92b980 ("net: dsa: mt7530: disable LEDs before reset").
+Changing the state of pins via reset assertion is simpler and more
+efficient than doing so by setting the LED controller off.
+
+Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
+Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch")
+Co-developed-by: Justin Swartz <justin.swartz@risingedge.co.za>
+Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2391,12 +2391,6 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+ }
+
+- /* Disable LEDs before reset to prevent the MT7530 sampling a
+- * potentially incorrect HT_XTAL_FSEL value.
+- */
+- mt7530_write(priv, MT7530_LED_EN, 0);
+- usleep_range(1000, 1100);
+-
+ /* Reset whole chip through gpio pin or memory-mapped registers for
+ * different type of hardware
+ */
--- /dev/null
+From 5754b3bdcd872aa229881b8f07f84a8404c7d72a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 12 Apr 2024 16:15:34 +0100
+Subject: [PATCH 1/5] net: dsa: mt7530: provide own phylink MAC operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Convert mt753x to provide its own phylink MAC operations, thus avoiding
+the shim layer in DSA's port.c
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/E1rvIco-006bQu-Fq@rmk-PC.armlinux.org.uk
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 46 +++++++++++++++++++++++++---------------
+ 1 file changed, 29 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2858,28 +2858,34 @@ mt7531_mac_config(struct dsa_switch *ds,
+ }
+
+ static struct phylink_pcs *
+-mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
++mt753x_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_TRGMII:
+- return &priv->pcs[port].pcs;
++ return &priv->pcs[dp->index].pcs;
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+- return priv->ports[port].sgmii_pcs;
++ return priv->ports[dp->index].sgmii_pcs;
+ default:
+ return NULL;
+ }
+ }
+
+ static void
+-mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
++mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode,
+ const struct phylink_link_state *state)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct dsa_switch *ds = dp->ds;
++ struct mt7530_priv *priv;
++ int port = dp->index;
++
++ priv = ds->priv;
+
+ if ((port == 5 || port == 6) && priv->info->mac_port_config)
+ priv->info->mac_port_config(ds, port, mode, state->interface);
+@@ -2889,23 +2895,25 @@ mt753x_phylink_mac_config(struct dsa_swi
+ mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
+ }
+
+-static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
++static void mt753x_phylink_mac_link_down(struct phylink_config *config,
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+
+- mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
++ mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ }
+
+-static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
++static void mt753x_phylink_mac_link_up(struct phylink_config *config,
++ struct phy_device *phydev,
+ unsigned int mode,
+ phy_interface_t interface,
+- struct phy_device *phydev,
+ int speed, int duplex,
+ bool tx_pause, bool rx_pause)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+ u32 mcr;
+
+ mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
+@@ -2940,7 +2948,7 @@ static void mt753x_phylink_mac_link_up(s
+ }
+ }
+
+- mt7530_set(priv, MT7530_PMCR_P(port), mcr);
++ mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
+ }
+
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+@@ -3160,16 +3168,19 @@ const struct dsa_switch_ops mt7530_switc
+ .port_mirror_add = mt753x_port_mirror_add,
+ .port_mirror_del = mt753x_port_mirror_del,
+ .phylink_get_caps = mt753x_phylink_get_caps,
+- .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs,
+- .phylink_mac_config = mt753x_phylink_mac_config,
+- .phylink_mac_link_down = mt753x_phylink_mac_link_down,
+- .phylink_mac_link_up = mt753x_phylink_mac_link_up,
+ .get_mac_eee = mt753x_get_mac_eee,
+ .set_mac_eee = mt753x_set_mac_eee,
+ .master_state_change = mt753x_conduit_state_change,
+ };
+ EXPORT_SYMBOL_GPL(mt7530_switch_ops);
+
++static const struct phylink_mac_ops mt753x_phylink_mac_ops = {
++ .mac_select_pcs = mt753x_phylink_mac_select_pcs,
++ .mac_config = mt753x_phylink_mac_config,
++ .mac_link_down = mt753x_phylink_mac_link_down,
++ .mac_link_up = mt753x_phylink_mac_link_up,
++};
++
+ const struct mt753x_info mt753x_table[] = {
+ [ID_MT7621] = {
+ .id = ID_MT7621,
+@@ -3247,6 +3258,7 @@ mt7530_probe_common(struct mt7530_priv *
+ priv->dev = dev;
+ priv->ds->priv = priv;
+ priv->ds->ops = &mt7530_switch_ops;
++ priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops;
+ mutex_init(&priv->reg_mutex);
+ dev_set_drvdata(dev, priv);
+
--- /dev/null
+From 5053a6cf1d50d785078562470d2a63695a9f3bf2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Thu, 18 Apr 2024 08:35:30 +0300
+Subject: [PATCH 4/5] net: dsa: mt7530-mdio: read PHY address of switch from
+ device tree
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Read the PHY address the switch listens on from the reg property of the
+switch node on the device tree. This change brings support for MT7530
+switches on boards with such bootstrapping configuration where the switch
+listens on a different PHY address than the hardcoded PHY address on the
+driver, 31.
+
+As described on the "MT7621 Programming Guide v0.4" document, the MT7530
+switch and its PHYs can be configured to listen on the range of 7-12,
+15-20, 23-28, and 31 and 0-4 PHY addresses.
+
+There are operations where the switch PHY registers are used. For the PHY
+address of the control PHY, transform the MT753X_CTRL_PHY_ADDR constant
+into a macro and use it. The PHY address for the control PHY is 0 when the
+switch listens on 31. In any other case, it is one greater than the PHY
+address the switch listens on.
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530-mdio.c | 28 +++++++++++++-------------
+ drivers/net/dsa/mt7530.c | 37 +++++++++++++++++++++++------------
+ drivers/net/dsa/mt7530.h | 4 +++-
+ 3 files changed, 41 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/dsa/mt7530-mdio.c
++++ b/drivers/net/dsa/mt7530-mdio.c
+@@ -18,7 +18,8 @@
+ static int
+ mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
+ {
+- struct mii_bus *bus = context;
++ struct mt7530_priv *priv = context;
++ struct mii_bus *bus = priv->bus;
+ u16 page, r, lo, hi;
+ int ret;
+
+@@ -27,36 +28,35 @@ mt7530_regmap_write(void *context, unsig
+ lo = val & 0xffff;
+ hi = val >> 16;
+
+- /* MT7530 uses 31 as the pseudo port */
+- ret = bus->write(bus, 0x1f, 0x1f, page);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x1f, page);
+ if (ret < 0)
+ return ret;
+
+- ret = bus->write(bus, 0x1f, r, lo);
++ ret = bus->write(bus, priv->mdiodev->addr, r, lo);
+ if (ret < 0)
+ return ret;
+
+- ret = bus->write(bus, 0x1f, 0x10, hi);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x10, hi);
+ return ret;
+ }
+
+ static int
+ mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
+ {
+- struct mii_bus *bus = context;
++ struct mt7530_priv *priv = context;
++ struct mii_bus *bus = priv->bus;
+ u16 page, r, lo, hi;
+ int ret;
+
+ page = (reg >> 6) & 0x3ff;
+ r = (reg >> 2) & 0xf;
+
+- /* MT7530 uses 31 as the pseudo port */
+- ret = bus->write(bus, 0x1f, 0x1f, page);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x1f, page);
+ if (ret < 0)
+ return ret;
+
+- lo = bus->read(bus, 0x1f, r);
+- hi = bus->read(bus, 0x1f, 0x10);
++ lo = bus->read(bus, priv->mdiodev->addr, r);
++ hi = bus->read(bus, priv->mdiodev->addr, 0x10);
+
+ *val = (hi << 16) | (lo & 0xffff);
+
+@@ -107,8 +107,7 @@ mt7531_create_sgmii(struct mt7530_priv *
+ mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
+ mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
+
+- regmap = devm_regmap_init(priv->dev,
+- &mt7530_regmap_bus, priv->bus,
++ regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, priv,
+ mt7531_pcs_config[i]);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+@@ -153,6 +152,7 @@ mt7530_probe(struct mdio_device *mdiodev
+
+ priv->bus = mdiodev->bus;
+ priv->dev = &mdiodev->dev;
++ priv->mdiodev = mdiodev;
+
+ ret = mt7530_probe_common(priv);
+ if (ret)
+@@ -203,8 +203,8 @@ mt7530_probe(struct mdio_device *mdiodev
+ regmap_config->reg_stride = 4;
+ regmap_config->max_register = MT7530_CREV;
+ regmap_config->disable_locking = true;
+- priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
+- priv->bus, regmap_config);
++ priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, priv,
++ regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -86,22 +86,26 @@ core_read_mmd_indirect(struct mt7530_pri
+ int value, ret;
+
+ /* Write the desired MMD Devad */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+- ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, prtad);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+ /* Read the content of the MMD's selected register */
+- value = bus->read(bus, 0, MII_MMD_DATA);
++ value = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA);
+
+ return value;
+ err:
+@@ -118,22 +122,26 @@ core_write_mmd_indirect(struct mt7530_pr
+ int ret;
+
+ /* Write the desired MMD Devad */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+- ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, prtad);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+ /* Write the data into MMD's selected register */
+- ret = bus->write(bus, 0, MII_MMD_DATA, data);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, data);
+ err:
+ if (ret < 0)
+ dev_err(&bus->dev,
+@@ -2679,16 +2687,19 @@ mt7531_setup(struct dsa_switch *ds)
+ * phy_[read,write]_mmd_indirect is called, we provide our own
+ * mt7531_ind_mmd_phy_[read,write] to complete this function.
+ */
+- val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
++ val = mt7531_ind_c45_phy_read(priv,
++ MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+ MDIO_MMD_VEND2, CORE_PLL_GROUP4);
+ val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
+ val &= ~MT7531_PHY_PLL_OFF;
+- mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
+- CORE_PLL_GROUP4, val);
++ mt7531_ind_c45_phy_write(priv,
++ MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MDIO_MMD_VEND2, CORE_PLL_GROUP4, val);
+
+ /* Disable EEE advertisement on the switch PHYs. */
+- for (i = MT753X_CTRL_PHY_ADDR;
+- i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
++ for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr);
++ i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS;
++ i++) {
+ mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
+ 0);
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -629,7 +629,7 @@ enum mt7531_clk_skew {
+ #define MT7531_PHY_PLL_OFF BIT(5)
+ #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
+
+-#define MT753X_CTRL_PHY_ADDR 0
++#define MT753X_CTRL_PHY_ADDR(addr) ((addr + 1) & 0x1f)
+
+ #define CORE_PLL_GROUP5 0x404
+ #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
+@@ -778,6 +778,7 @@ struct mt753x_info {
+ * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
+ * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
+ * @active_cpu_ports: Holding the active CPU ports
++ * @mdiodev: The pointer to the MDIO device structure
+ */
+ struct mt7530_priv {
+ struct device *dev;
+@@ -804,6 +805,7 @@ struct mt7530_priv {
+ u32 irq_enable;
+ int (*create_sgmii)(struct mt7530_priv *priv);
+ u8 active_cpu_ports;
++ struct mdio_device *mdiodev;
+ };
+
+ struct mt7530_hw_vlan_entry {
--- /dev/null
+From 9764a08b3d260f4e7799d34bbfe64463db940d74 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Thu, 18 Apr 2024 08:35:31 +0300
+Subject: [PATCH 5/5] net: dsa: mt7530: simplify core operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The core_rmw() function calls core_read_mmd_indirect() to read the
+requested register, and then calls core_write_mmd_indirect() to write the
+requested value to the register. Because Clause 22 is used to access Clause
+45 registers, some operations on core_write_mmd_indirect() are
+unnecessarily run. Get rid of core_read_mmd_indirect() and
+core_write_mmd_indirect(), and run only the necessary operations on
+core_write() and core_rmw().
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 108 ++++++++++++++++-----------------------
+ 1 file changed, 43 insertions(+), 65 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -74,116 +74,94 @@ static const struct mt7530_mib_desc mt75
+ MIB_DESC(1, 0xb8, "RxArlDrop"),
+ };
+
+-/* Since phy_device has not yet been created and
+- * phy_{read,write}_mmd_indirect is not available, we provide our own
+- * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
+- * to complete this function.
+- */
+-static int
+-core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
++static void
++mt7530_mutex_lock(struct mt7530_priv *priv)
++{
++ if (priv->bus)
++ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++}
++
++static void
++mt7530_mutex_unlock(struct mt7530_priv *priv)
++{
++ if (priv->bus)
++ mutex_unlock(&priv->bus->mdio_lock);
++}
++
++static void
++core_write(struct mt7530_priv *priv, u32 reg, u32 val)
+ {
+ struct mii_bus *bus = priv->bus;
+- int value, ret;
++ int ret;
++
++ mt7530_mutex_lock(priv);
+
+ /* Write the desired MMD Devad */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad);
++ MII_MMD_CTRL, MDIO_MMD_VEND2);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, prtad);
++ MII_MMD_DATA, reg);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
++ MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+- /* Read the content of the MMD's selected register */
+- value = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA);
+-
+- return value;
++ /* Write the data into MMD's selected register */
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, val);
+ err:
+- dev_err(&bus->dev, "failed to read mmd register\n");
++ if (ret < 0)
++ dev_err(&bus->dev, "failed to write mmd register\n");
+
+- return ret;
++ mt7530_mutex_unlock(priv);
+ }
+
+-static int
+-core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
+- int devad, u32 data)
++static void
++core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
+ {
+ struct mii_bus *bus = priv->bus;
++ u32 val;
+ int ret;
+
++ mt7530_mutex_lock(priv);
++
+ /* Write the desired MMD Devad */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad);
++ MII_MMD_CTRL, MDIO_MMD_VEND2);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, prtad);
++ MII_MMD_DATA, reg);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
++ MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
++ /* Read the content of the MMD's selected register */
++ val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA);
++ val &= ~mask;
++ val |= set;
+ /* Write the data into MMD's selected register */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, data);
++ MII_MMD_DATA, val);
+ err:
+ if (ret < 0)
+- dev_err(&bus->dev,
+- "failed to write mmd register\n");
+- return ret;
+-}
+-
+-static void
+-mt7530_mutex_lock(struct mt7530_priv *priv)
+-{
+- if (priv->bus)
+- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+-}
+-
+-static void
+-mt7530_mutex_unlock(struct mt7530_priv *priv)
+-{
+- if (priv->bus)
+- mutex_unlock(&priv->bus->mdio_lock);
+-}
+-
+-static void
+-core_write(struct mt7530_priv *priv, u32 reg, u32 val)
+-{
+- mt7530_mutex_lock(priv);
+-
+- core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
+-
+- mt7530_mutex_unlock(priv);
+-}
+-
+-static void
+-core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
+-{
+- u32 val;
+-
+- mt7530_mutex_lock(priv);
+-
+- val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
+- val &= ~mask;
+- val |= set;
+- core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
++ dev_err(&bus->dev, "failed to write mmd register\n");
+
+ mt7530_mutex_unlock(priv);
+ }
--- /dev/null
+From 856e8954a0a88d1a4d2b43e9002b9249131a156f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:08 +0300
+Subject: [PATCH 01/15] net: dsa: mt7530: disable EEE abilities on failure on
+ MT7531 and MT7988
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 bits let the
+PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits determine the 1G/100 EEE
+abilities of the MAC. If MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 are
+unset, the abilities are left to be determined by PHY auto polling.
+
+The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
+made it so that the PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits are set on
+mt753x_phylink_mac_link_up(). But it did not set the MT7531_FORCE_EEE1G and
+MT7531_FORCE_EEE100 bits. Because of this, the EEE abilities will be
+determined by PHY auto polling, regardless of the result of phy_init_eee().
+
+Define these bits and add them to the MT7531_FORCE_MODE mask which is set
+in mt7531_setup_common(). With this, there won't be any EEE abilities set
+when phy_init_eee() returns a negative value.
+
+Thanks to Russell for explaining when phy_init_eee() could return a
+negative value below.
+
+Looking at phy_init_eee(), it could return a negative value when:
+
+1. phydev->drv is NULL
+2. if genphy_c45_eee_is_active() returns negative
+3. if genphy_c45_eee_is_active() returns zero, it returns -EPROTONOSUPPORT
+4. if phy_set_bits_mmd() fails (e.g. communication error with the PHY)
+
+If we then look at genphy_c45_eee_is_active(), then:
+
+genphy_c45_read_eee_adv() and genphy_c45_read_eee_lpa() propagate their
+non-zero return values, otherwise this function returns zero or positive
+integer.
+
+If we then look at genphy_c45_read_eee_adv(), then a failure of
+phy_read_mmd() would cause a negative value to be returned.
+
+Looking at genphy_c45_read_eee_lpa(), the same is true.
+
+So, it can be summarised as:
+
+- phydev->drv is NULL
+- there is a communication error accessing the PHY
+- EEE is not active
+
+otherwise, it returns zero on success.
+
+If one wishes to determine whether an error occurred vs EEE not being
+supported through negotiation for the negotiated speed, if it returns
+-EPROTONOSUPPORT in the latter case. Other error codes mean either the
+driver has been unloaded or communication error.
+
+In conclusion, determining the EEE abilities by PHY auto polling shouldn't
+result in having any EEE abilities enabled, when one of the last two
+situations in the summary happens. And it seems that if phydev->drv is
+NULL, there would be bigger problems with the device than a broken link. So
+this is not a bugfix.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.h | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -328,11 +328,15 @@ enum mt7530_vlan_port_acc_frm {
+ #define MT7531_FORCE_DPX BIT(29)
+ #define MT7531_FORCE_RX_FC BIT(28)
+ #define MT7531_FORCE_TX_FC BIT(27)
++#define MT7531_FORCE_EEE100 BIT(26)
++#define MT7531_FORCE_EEE1G BIT(25)
+ #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
+ MT7531_FORCE_SPD | \
+ MT7531_FORCE_DPX | \
+ MT7531_FORCE_RX_FC | \
+- MT7531_FORCE_TX_FC)
++ MT7531_FORCE_TX_FC | \
++ MT7531_FORCE_EEE100 | \
++ MT7531_FORCE_EEE1G)
+ #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+ PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+ PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
--- /dev/null
+From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:09 +0300
+Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the
+MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is
+for MT7530 only. Add MT7530 prefix to the definition for bit 15.
+
+Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT().
+
+Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to
+follow the naming on the "MT7621 Giga Switch Programming Guide v0.3",
+"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7
+Generation Router Platform: Datasheet (Open Version) v0.1" documents.
+
+These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along
+with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN.
+
+Remove PMCR_SPEED_MASK which doesn't have a use.
+
+Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the
+end for the mask that includes all force mode definitions.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 24 ++++++++---------
+ drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++-------------------
+ 2 files changed, 42 insertions(+), 40 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -896,7 +896,7 @@ static void mt7530_setup_port5(struct ds
+ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+- mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
++ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+ case P5_INTF_SEL_GMAC5:
+ /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+@@ -2444,8 +2444,8 @@ mt7530_setup(struct dsa_switch *ds)
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+- PMCR_FORCE_MODE, PMCR_FORCE_MODE);
++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7530_FORCE_MODE, MT7530_FORCE_MODE);
+
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2555,8 +2555,8 @@ mt7531_setup_common(struct dsa_switch *d
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+- MT7531_FORCE_MODE, MT7531_FORCE_MODE);
++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK);
+
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2639,7 +2639,7 @@ mt7531_setup(struct dsa_switch *ds)
+
+ /* Force link down on all ports before internal reset */
+ for (i = 0; i < MT7530_NUM_PORTS; i++)
+- mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
++ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+
+ /* Reset the switch through internal reset */
+ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
+@@ -2881,7 +2881,7 @@ mt753x_phylink_mac_config(struct phylink
+
+ /* Are we connected to external phy */
+ if (port == 5 && dsa_is_user_port(ds, 5))
+- mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
++ mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY);
+ }
+
+ static void mt753x_phylink_mac_link_down(struct phylink_config *config,
+@@ -2891,7 +2891,7 @@ static void mt753x_phylink_mac_link_down
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct mt7530_priv *priv = dp->ds->priv;
+
+- mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
++ mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ }
+
+ static void mt753x_phylink_mac_link_up(struct phylink_config *config,
+@@ -2905,7 +2905,7 @@ static void mt753x_phylink_mac_link_up(s
+ struct mt7530_priv *priv = dp->ds->priv;
+ u32 mcr;
+
+- mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
++ mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK;
+
+ switch (speed) {
+ case SPEED_1000:
+@@ -2920,9 +2920,9 @@ static void mt753x_phylink_mac_link_up(s
+ if (duplex == DUPLEX_FULL) {
+ mcr |= PMCR_FORCE_FDX;
+ if (tx_pause)
+- mcr |= PMCR_TX_FC_EN;
++ mcr |= PMCR_FORCE_TX_FC_EN;
+ if (rx_pause)
+- mcr |= PMCR_RX_FC_EN;
++ mcr |= PMCR_FORCE_RX_FC_EN;
+ }
+
+ if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
+@@ -2937,7 +2937,7 @@ static void mt753x_phylink_mac_link_up(s
+ }
+ }
+
+- mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
++ mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr);
+ }
+
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm {
+ #define G0_PORT_VID_DEF G0_PORT_VID(0)
+
+ /* Register for port MAC control register */
+-#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
+-#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
++#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100))
++#define PMCR_IFG_XMIT_MASK GENMASK(19, 18)
++#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x)
+ #define PMCR_EXT_PHY BIT(17)
+ #define PMCR_MAC_MODE BIT(16)
+-#define PMCR_FORCE_MODE BIT(15)
+-#define PMCR_TX_EN BIT(14)
+-#define PMCR_RX_EN BIT(13)
++#define MT7530_FORCE_MODE BIT(15)
++#define PMCR_MAC_TX_EN BIT(14)
++#define PMCR_MAC_RX_EN BIT(13)
+ #define PMCR_BACKOFF_EN BIT(9)
+ #define PMCR_BACKPR_EN BIT(8)
+ #define PMCR_FORCE_EEE1G BIT(7)
+ #define PMCR_FORCE_EEE100 BIT(6)
+-#define PMCR_TX_FC_EN BIT(5)
+-#define PMCR_RX_FC_EN BIT(4)
++#define PMCR_FORCE_RX_FC_EN BIT(5)
++#define PMCR_FORCE_TX_FC_EN BIT(4)
+ #define PMCR_FORCE_SPEED_1000 BIT(3)
+ #define PMCR_FORCE_SPEED_100 BIT(2)
+ #define PMCR_FORCE_FDX BIT(1)
+ #define PMCR_FORCE_LNK BIT(0)
+-#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
+- PMCR_FORCE_SPEED_1000)
+-#define MT7531_FORCE_LNK BIT(31)
+-#define MT7531_FORCE_SPD BIT(30)
+-#define MT7531_FORCE_DPX BIT(29)
+-#define MT7531_FORCE_RX_FC BIT(28)
+-#define MT7531_FORCE_TX_FC BIT(27)
+-#define MT7531_FORCE_EEE100 BIT(26)
+-#define MT7531_FORCE_EEE1G BIT(25)
+-#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
+- MT7531_FORCE_SPD | \
+- MT7531_FORCE_DPX | \
+- MT7531_FORCE_RX_FC | \
+- MT7531_FORCE_TX_FC | \
+- MT7531_FORCE_EEE100 | \
+- MT7531_FORCE_EEE1G)
+-#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+- PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
+- PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
+- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
++#define MT7531_FORCE_MODE_LNK BIT(31)
++#define MT7531_FORCE_MODE_SPD BIT(30)
++#define MT7531_FORCE_MODE_DPX BIT(29)
++#define MT7531_FORCE_MODE_RX_FC BIT(28)
++#define MT7531_FORCE_MODE_TX_FC BIT(27)
++#define MT7531_FORCE_MODE_EEE100 BIT(26)
++#define MT7531_FORCE_MODE_EEE1G BIT(25)
++#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \
++ MT7531_FORCE_MODE_SPD | \
++ MT7531_FORCE_MODE_DPX | \
++ MT7531_FORCE_MODE_RX_FC | \
++ MT7531_FORCE_MODE_TX_FC | \
++ MT7531_FORCE_MODE_EEE100 | \
++ MT7531_FORCE_MODE_EEE1G)
++#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
++ PMCR_FORCE_EEE1G | \
++ PMCR_FORCE_EEE100 | \
++ PMCR_FORCE_RX_FC_EN | \
++ PMCR_FORCE_TX_FC_EN | \
++ PMCR_FORCE_SPEED_1000 | \
++ PMCR_FORCE_SPEED_100 | \
++ PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+
+ #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
+ #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
--- /dev/null
+From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:10 +0300
+Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for
+ MT7530 switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The p5_intf_sel pointer is used to store the information of whether PHY
+muxing is used or not. PHY muxing is a feature specific to port 5 of the
+MT7530 switch. Do not use it for other switch models.
+
+Rename the pointer to p5_mode to store the mode the port is being used in.
+Rename the p5_interface_select enum to mt7530_p5_mode, the string
+representation to mt7530_p5_mode_str, and the enum elements.
+
+If PHY muxing is not detected, the default mode, GMAC5, will be used.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 62 +++++++++++++++++-----------------------
+ drivers/net/dsa/mt7530.h | 15 +++++-----
+ 2 files changed, 33 insertions(+), 44 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -857,19 +857,15 @@ mt7530_set_ageing_time(struct dsa_switch
+ return 0;
+ }
+
+-static const char *p5_intf_modes(unsigned int p5_interface)
++static const char *mt7530_p5_mode_str(unsigned int mode)
+ {
+- switch (p5_interface) {
+- case P5_DISABLED:
+- return "DISABLED";
+- case P5_INTF_SEL_PHY_P0:
+- return "PHY P0";
+- case P5_INTF_SEL_PHY_P4:
+- return "PHY P4";
+- case P5_INTF_SEL_GMAC5:
+- return "GMAC5";
++ switch (mode) {
++ case MUX_PHY_P0:
++ return "MUX PHY P0";
++ case MUX_PHY_P4:
++ return "MUX PHY P4";
+ default:
+- return "unknown";
++ return "GMAC5";
+ }
+ }
+
+@@ -886,23 +882,23 @@ static void mt7530_setup_port5(struct ds
+ val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
+ val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
+
+- switch (priv->p5_intf_sel) {
+- case P5_INTF_SEL_PHY_P0:
+- /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
++ switch (priv->p5_mode) {
++ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
++ case MUX_PHY_P0:
+ val |= MHWTRAP_PHY0_SEL;
+ fallthrough;
+- case P5_INTF_SEL_PHY_P4:
+- /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
++
++ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
++ case MUX_PHY_P4:
+ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+- case P5_INTF_SEL_GMAC5:
+- /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+- val &= ~MHWTRAP_P5_DIS;
+- break;
++
++ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
++ val &= ~MHWTRAP_P5_DIS;
+ break;
+ }
+
+@@ -930,8 +926,8 @@ static void mt7530_setup_port5(struct ds
+
+ mt7530_write(priv, MT7530_MHWTRAP, val);
+
+- dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
+- val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
++ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
++ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
+
+ mutex_unlock(&priv->reg_mutex);
+ }
+@@ -2476,13 +2472,11 @@ mt7530_setup(struct dsa_switch *ds)
+ if (ret)
+ return ret;
+
+- /* Setup port 5 */
+- if (!dsa_is_unused_port(ds, 5)) {
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+- } else {
++ /* Check for PHY muxing on port 5 */
++ if (dsa_is_unused_port(ds, 5)) {
+ /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.
+- * Set priv->p5_intf_sel to the appropriate value if PHY muxing
+- * is detected.
++ * Set priv->p5_mode to the appropriate value if PHY muxing is
++ * detected.
+ */
+ for_each_child_of_node(dn, mac_np) {
+ if (!of_device_is_compatible(mac_np,
+@@ -2506,17 +2500,16 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+ id = of_mdio_parse_addr(ds->dev, phy_node);
+ if (id == 0)
+- priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
++ priv->p5_mode = MUX_PHY_P0;
+ if (id == 4)
+- priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
++ priv->p5_mode = MUX_PHY_P4;
+ }
+ of_node_put(mac_np);
+ of_node_put(phy_node);
+ break;
+ }
+
+- if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||
+- priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)
++ if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
+ mt7530_setup_port5(ds, interface);
+ }
+
+@@ -2654,9 +2647,6 @@ mt7531_setup(struct dsa_switch *ds)
+ MT7531_EXT_P_MDIO_12);
+ }
+
+- if (!dsa_is_unused_port(ds, 5))
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+-
+ mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
+ MT7531_GPIO0_INTERRUPT);
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -708,12 +708,11 @@ struct mt7530_port {
+ struct phylink_pcs *sgmii_pcs;
+ };
+
+-/* Port 5 interface select definitions */
+-enum p5_interface_select {
+- P5_DISABLED,
+- P5_INTF_SEL_PHY_P0,
+- P5_INTF_SEL_PHY_P4,
+- P5_INTF_SEL_GMAC5,
++/* Port 5 mode definitions of the MT7530 switch */
++enum mt7530_p5_mode {
++ GMAC5,
++ MUX_PHY_P0,
++ MUX_PHY_P4,
+ };
+
+ struct mt7530_priv;
+@@ -776,7 +775,7 @@ struct mt753x_info {
+ * @ports: Holding the state among ports
+ * @reg_mutex: The lock for protecting among process accessing
+ * registers
+- * @p5_intf_sel: Holding the current port 5 interface select
++ * @p5_mode: Holding the current mode of port 5 of the MT7530 switch
+ * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
+ * has got SGMII
+ * @irq: IRQ number of the switch
+@@ -798,7 +797,7 @@ struct mt7530_priv {
+ const struct mt753x_info *info;
+ unsigned int id;
+ bool mcm;
+- enum p5_interface_select p5_intf_sel;
++ enum mt7530_p5_mode p5_mode;
+ bool p5_sgmii;
+ u8 mirror_rx;
+ u8 mirror_tx;
--- /dev/null
+From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:11 +0300
+Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to
+ mt753x_to_cpu_fw
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt753x_bpdu_port_fw enum is globally used for manipulating the process
+of deciding the forwardable ports, specifically concerning the CPU port(s).
+Therefore, rename it and the values in it to mt753x_to_cpu_fw.
+
+Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 44 ++++++++++-------------
+ drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++--------------------
+ 2 files changed, 56 insertions(+), 64 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1107,42 +1107,34 @@ mt753x_trap_frames(struct mt7530_priv *p
+ * VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_BPC,
+- MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
+- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
+- MT753X_BPDU_PORT_FW_MASK,
+- MT753X_PAE_BPDU_FR |
+- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
++ BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
++ PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
++ BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_RGAC1,
+- MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
+- MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
+- MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
+- MT753X_R02_BPDU_FR |
+- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_R01_BPDU_FR |
+- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
++ R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
++ R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
++ R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_RGAC2,
+- MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
+- MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
+- MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
+- MT753X_R0E_BPDU_FR |
+- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_R03_BPDU_FR |
+- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
++ R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
++ R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
++ R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+ }
+
+ static void
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -67,47 +67,47 @@ enum mt753x_id {
+ #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+ MT7531_MIRROR_MASK : MIRROR_MASK)
+
+-/* Registers for BPDU and PAE frame control*/
++/* Register for BPDU and PAE frame control */
+ #define MT753X_BPC 0x24
+-#define MT753X_PAE_BPDU_FR BIT(25)
+-#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
+-#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)
+-#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
+-#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
++#define PAE_BPDU_FR BIT(25)
++#define PAE_EG_TAG_MASK GENMASK(24, 22)
++#define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x)
++#define PAE_PORT_FW_MASK GENMASK(18, 16)
++#define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x)
++#define BPDU_EG_TAG_MASK GENMASK(8, 6)
++#define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x)
++#define BPDU_PORT_FW_MASK GENMASK(2, 0)
+
+-/* Register for :01 and :02 MAC DA frame control */
++/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
+ #define MT753X_RGAC1 0x28
+-#define MT753X_R02_BPDU_FR BIT(25)
+-#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
+-#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
+-#define MT753X_R01_BPDU_FR BIT(9)
+-#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
+-#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
++#define R02_BPDU_FR BIT(25)
++#define R02_EG_TAG_MASK GENMASK(24, 22)
++#define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x)
++#define R02_PORT_FW_MASK GENMASK(18, 16)
++#define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x)
++#define R01_BPDU_FR BIT(9)
++#define R01_EG_TAG_MASK GENMASK(8, 6)
++#define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x)
++#define R01_PORT_FW_MASK GENMASK(2, 0)
+
+-/* Register for :03 and :0E MAC DA frame control */
++/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
+ #define MT753X_RGAC2 0x2c
+-#define MT753X_R0E_BPDU_FR BIT(25)
+-#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
+-#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
+-#define MT753X_R03_BPDU_FR BIT(9)
+-#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
+-#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
++#define R0E_BPDU_FR BIT(25)
++#define R0E_EG_TAG_MASK GENMASK(24, 22)
++#define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x)
++#define R0E_PORT_FW_MASK GENMASK(18, 16)
++#define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x)
++#define R03_BPDU_FR BIT(9)
++#define R03_EG_TAG_MASK GENMASK(8, 6)
++#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x)
++#define R03_PORT_FW_MASK GENMASK(2, 0)
+
+-enum mt753x_bpdu_port_fw {
+- MT753X_BPDU_FOLLOW_MFC,
+- MT753X_BPDU_CPU_EXCLUDE = 4,
+- MT753X_BPDU_CPU_INCLUDE = 5,
+- MT753X_BPDU_CPU_ONLY = 6,
+- MT753X_BPDU_DROP = 7,
++enum mt753x_to_cpu_fw {
++ TO_CPU_FW_SYSTEM_DEFAULT,
++ TO_CPU_FW_CPU_EXCLUDE = 4,
++ TO_CPU_FW_CPU_INCLUDE = 5,
++ TO_CPU_FW_CPU_ONLY = 6,
++ TO_CPU_FW_DROP = 7,
+ };
+
+ /* Registers for address table access */
--- /dev/null
+From 1dbc1bdc2869e6d2929235c70d64e393aa5a5fa2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:12 +0300
+Subject: [PATCH 05/15] net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC,
+ add MT7531_QRY_FFP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988
+SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and
+MT7531/MT7988. Add MT7530 prefix to these definitions, and define the
+IGMP/MLD Query Frame Flooding Ports mask for MT7531.
+
+Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK.
+
+Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as
+macros.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 ++++++++--------------
+ drivers/net/dsa/mt7530.h | 69 +++++++++++++++++++++++++---------------
+ 2 files changed, 57 insertions(+), 50 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1147,7 +1147,7 @@ mt753x_cpu_port_enable(struct dsa_switch
+ PORT_SPEC_TAG);
+
+ /* Enable flooding on the CPU port */
+- mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
++ mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
+ UNU_FFP(BIT(port)));
+
+ /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
+@@ -1311,15 +1311,15 @@ mt7530_port_bridge_flags(struct dsa_swit
+ flags.val & BR_LEARNING ? 0 : SA_DIS);
+
+ if (flags.mask & BR_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)),
+ flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
+
+ if (flags.mask & BR_MCAST_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)),
+ flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
+
+ if (flags.mask & BR_BCAST_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)),
+ flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
+
+ return 0;
+@@ -1855,20 +1855,6 @@ mt7530_port_vlan_del(struct dsa_switch *
+ return 0;
+ }
+
+-static int mt753x_mirror_port_get(unsigned int id, u32 val)
+-{
+- return (id == ID_MT7531 || id == ID_MT7988) ?
+- MT7531_MIRROR_PORT_GET(val) :
+- MIRROR_PORT(val);
+-}
+-
+-static int mt753x_mirror_port_set(unsigned int id, u32 val)
+-{
+- return (id == ID_MT7531 || id == ID_MT7988) ?
+- MT7531_MIRROR_PORT_SET(val) :
+- MIRROR_PORT(val);
+-}
+-
+ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress, struct netlink_ext_ack *extack)
+@@ -1884,14 +1870,14 @@ static int mt753x_port_mirror_add(struct
+ val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
+
+ /* MT7530 only supports one monitor port */
+- monitor_port = mt753x_mirror_port_get(priv->id, val);
++ monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
+ if (val & MT753X_MIRROR_EN(priv->id) &&
+ monitor_port != mirror->to_local_port)
+ return -EEXIST;
+
+ val |= MT753X_MIRROR_EN(priv->id);
+- val &= ~MT753X_MIRROR_MASK(priv->id);
+- val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
++ val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
++ val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
+ mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
+
+ val = mt7530_read(priv, MT7530_PCR_P(port));
+@@ -2533,7 +2519,7 @@ mt7531_setup_common(struct dsa_switch *d
+ mt7530_mib_reset(ds);
+
+ /* Disable flooding on all ports */
+- mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK |
++ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
+ UNU_FFP_MASK);
+
+ for (i = 0; i < MT7530_NUM_PORTS; i++) {
+@@ -3089,10 +3075,12 @@ mt753x_conduit_state_change(struct dsa_s
+ else
+ priv->active_cpu_ports &= ~mask;
+
+- if (priv->active_cpu_ports)
+- val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
++ if (priv->active_cpu_ports) {
++ val = MT7530_CPU_EN |
++ MT7530_CPU_PORT(__ffs(priv->active_cpu_ports));
++ }
+
+- mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
++ mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);
+ }
+
+ static int mt7988_setup(struct dsa_switch *ds)
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -36,36 +36,55 @@ enum mt753x_id {
+ #define MT753X_AGC 0xc
+ #define LOCAL_EN BIT(7)
+
+-/* Registers to mac forward control for unknown frames */
+-#define MT7530_MFC 0x10
+-#define BC_FFP(x) (((x) & 0xff) << 24)
+-#define BC_FFP_MASK BC_FFP(~0)
+-#define UNM_FFP(x) (((x) & 0xff) << 16)
+-#define UNM_FFP_MASK UNM_FFP(~0)
+-#define UNU_FFP(x) (((x) & 0xff) << 8)
+-#define UNU_FFP_MASK UNU_FFP(~0)
+-#define CPU_EN BIT(7)
+-#define CPU_PORT_MASK GENMASK(6, 4)
+-#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x)
+-#define MIRROR_EN BIT(3)
+-#define MIRROR_PORT(x) ((x) & 0x7)
+-#define MIRROR_MASK 0x7
++/* Register for MAC forward control */
++#define MT753X_MFC 0x10
++#define BC_FFP_MASK GENMASK(31, 24)
++#define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x)
++#define UNM_FFP_MASK GENMASK(23, 16)
++#define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x)
++#define UNU_FFP_MASK GENMASK(15, 8)
++#define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x)
++#define MT7530_CPU_EN BIT(7)
++#define MT7530_CPU_PORT_MASK GENMASK(6, 4)
++#define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x)
++#define MT7530_MIRROR_EN BIT(3)
++#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0)
++#define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x)
++#define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x)
++#define MT7531_QRY_FFP_MASK GENMASK(7, 0)
++#define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x)
+
+-/* Registers for CPU forward control */
++/* Register for CPU forward control */
+ #define MT7531_CFC 0x4
+ #define MT7531_MIRROR_EN BIT(19)
+-#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
+-#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
+-#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
++#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16)
++#define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x)
++#define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x)
+ #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
+ #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
+
+-#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_CFC : MT7530_MFC)
+-#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_MIRROR_EN : MIRROR_EN)
+-#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_MIRROR_MASK : MIRROR_MASK)
++#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_CFC : MT753X_MFC)
++
++#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_EN : MT7530_MIRROR_EN)
++
++#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_MASK : \
++ MT7530_MIRROR_PORT_MASK)
++
++#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_GET(val) : \
++ MT7530_MIRROR_PORT_GET(val))
++
++#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_SET(val) : \
++ MT7530_MIRROR_PORT_SET(val))
+
+ /* Register for BPDU and PAE frame control */
+ #define MT753X_BPC 0x24
--- /dev/null
+From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:13 +0300
+Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and
+ MT7530_MHWTRAP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531.
+It's called hardware trap on MT7530, software trap on MT7531. That's
+because some bits of the trap on MT7530 cannot be modified by software
+whilst all bits of the trap on MT7531 can. Rename the definitions for them
+to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the
+definitions specific to the switch model.
+
+Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ.
+
+Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on
+par with the "MT7621 Giga Switch Programming Guide v0.3" document.
+
+Make an enumaration for the XTAL frequency. Set the data type of the xtal
+variable on mt7531_pll_setup() to it.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++--------------------
+ drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------
+ 2 files changed, 54 insertions(+), 55 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -417,23 +417,23 @@ mt7530_setup_port6(struct dsa_switch *ds
+
+ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
+
+- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
++ xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK;
+
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ssc_delta = 0x57;
+ else
+ ssc_delta = 0x87;
+
+ if (priv->id == ID_MT7621) {
+ /* PLL frequency: 125MHz: 1.0GBit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
++ if (xtal == MT7530_XTAL_40MHZ)
+ ncpo1 = 0x0640;
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ncpo1 = 0x0a00;
+ } else { /* PLL frequency: 250MHz: 2.0Gbit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
++ if (xtal == MT7530_XTAL_40MHZ)
+ ncpo1 = 0x0c80;
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ncpo1 = 0x1400;
+ }
+
+@@ -456,19 +456,20 @@ mt7530_setup_port6(struct dsa_switch *ds
+ static void
+ mt7531_pll_setup(struct mt7530_priv *priv)
+ {
++ enum mt7531_xtal_fsel xtal;
+ u32 top_sig;
+ u32 hwstrap;
+- u32 xtal;
+ u32 val;
+
+ val = mt7530_read(priv, MT7531_CREV);
+ top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
+- hwstrap = mt7530_read(priv, MT7531_HWTRAP);
++ hwstrap = mt7530_read(priv, MT753X_TRAP);
+ if ((val & CHIP_REV_M) > 0)
+- xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
+- HWTRAP_XTAL_FSEL_25MHZ;
++ xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ :
++ MT7531_XTAL_FSEL_25MHZ;
+ else
+- xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
++ xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ :
++ MT7531_XTAL_FSEL_40MHZ;
+
+ /* Step 1 : Disable MT7531 COREPLL */
+ val = mt7530_read(priv, MT7531_PLLGP_EN);
+@@ -497,13 +498,13 @@ mt7531_pll_setup(struct mt7530_priv *pri
+ usleep_range(25, 35);
+
+ switch (xtal) {
+- case HWTRAP_XTAL_FSEL_25MHZ:
++ case MT7531_XTAL_FSEL_25MHZ:
+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ val &= ~RG_COREPLL_SDM_PCW_M;
+ val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
+ mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ break;
+- case HWTRAP_XTAL_FSEL_40MHZ:
++ case MT7531_XTAL_FSEL_40MHZ:
+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ val &= ~RG_COREPLL_SDM_PCW_M;
+ val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
+@@ -877,20 +878,20 @@ static void mt7530_setup_port5(struct ds
+
+ mutex_lock(&priv->reg_mutex);
+
+- val = mt7530_read(priv, MT7530_MHWTRAP);
++ val = mt7530_read(priv, MT753X_MTRAP);
+
+- val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
+- val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
++ val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
++ val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
+
+ switch (priv->p5_mode) {
+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+ case MUX_PHY_P0:
+- val |= MHWTRAP_PHY0_SEL;
++ val |= MT7530_P5_PHY0_SEL;
+ fallthrough;
+
+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ case MUX_PHY_P4:
+- val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
++ val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+@@ -898,13 +899,13 @@ static void mt7530_setup_port5(struct ds
+
+ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
+- val &= ~MHWTRAP_P5_DIS;
++ val &= ~MT7530_P5_DIS;
+ break;
+ }
+
+ /* Setup RGMII settings */
+ if (phy_interface_mode_is_rgmii(interface)) {
+- val |= MHWTRAP_P5_RGMII_MODE;
++ val |= MT7530_P5_RGMII_MODE;
+
+ /* P5 RGMII RX Clock Control: delay setting for 1000M */
+ mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
+@@ -924,7 +925,7 @@ static void mt7530_setup_port5(struct ds
+ P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
+ }
+
+- mt7530_write(priv, MT7530_MHWTRAP, val);
++ mt7530_write(priv, MT753X_MTRAP, val);
+
+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
+ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
+@@ -2365,7 +2366,7 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+
+ /* Waiting for MT7530 got to stable */
+- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
+ ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ 20, 1000000);
+ if (ret < 0) {
+@@ -2380,7 +2381,7 @@ mt7530_setup(struct dsa_switch *ds)
+ return -ENODEV;
+ }
+
+- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) {
+ dev_err(priv->dev,
+ "MT7530 with a 20MHz XTAL is not supported!\n");
+ return -EINVAL;
+@@ -2401,12 +2402,12 @@ mt7530_setup(struct dsa_switch *ds)
+ RD_TAP_MASK, RD_TAP(16));
+
+ /* Enable port 6 */
+- val = mt7530_read(priv, MT7530_MHWTRAP);
+- val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
+- val |= MHWTRAP_MANUAL;
+- mt7530_write(priv, MT7530_MHWTRAP, val);
++ val = mt7530_read(priv, MT753X_MTRAP);
++ val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
++ val |= MT7530_CHG_TRAP;
++ mt7530_write(priv, MT753X_MTRAP, val);
+
+- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+
+ mt753x_trap_frames(priv);
+@@ -2586,7 +2587,7 @@ mt7531_setup(struct dsa_switch *ds)
+ }
+
+ /* Waiting for MT7530 got to stable */
+- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
+ ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ 20, 1000000);
+ if (ret < 0) {
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -495,32 +495,30 @@ enum mt7531_clk_skew {
+ MT7531_CLK_SKEW_REVERSE = 3,
+ };
+
+-/* Register for hw trap status */
+-#define MT7530_HWTRAP 0x7800
+-#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
+-#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
+-#define HWTRAP_XTAL_40MHZ (BIT(10))
+-#define HWTRAP_XTAL_20MHZ (BIT(9))
++/* Register for trap status */
++#define MT753X_TRAP 0x7800
++#define MT7530_XTAL_MASK (BIT(10) | BIT(9))
++#define MT7530_XTAL_25MHZ (BIT(10) | BIT(9))
++#define MT7530_XTAL_40MHZ BIT(10)
++#define MT7530_XTAL_20MHZ BIT(9)
++#define MT7531_XTAL25 BIT(7)
+
+-#define MT7531_HWTRAP 0x7800
+-#define HWTRAP_XTAL_FSEL_MASK BIT(7)
+-#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
+-#define HWTRAP_XTAL_FSEL_40MHZ 0
+-/* Unique fields of (M)HWSTRAP for MT7531 */
+-#define XTAL_FSEL_S 7
+-#define XTAL_FSEL_M BIT(7)
+-#define PHY_EN BIT(6)
+-#define CHG_STRAP BIT(8)
++/* Register for trap modification */
++#define MT753X_MTRAP 0x7804
++#define MT7530_P5_PHY0_SEL BIT(20)
++#define MT7530_CHG_TRAP BIT(16)
++#define MT7530_P5_MAC_SEL BIT(13)
++#define MT7530_P6_DIS BIT(8)
++#define MT7530_P5_RGMII_MODE BIT(7)
++#define MT7530_P5_DIS BIT(6)
++#define MT7530_PHY_INDIRECT_ACCESS BIT(5)
++#define MT7531_CHG_STRAP BIT(8)
++#define MT7531_PHY_EN BIT(6)
+
+-/* Register for hw trap modification */
+-#define MT7530_MHWTRAP 0x7804
+-#define MHWTRAP_PHY0_SEL BIT(20)
+-#define MHWTRAP_MANUAL BIT(16)
+-#define MHWTRAP_P5_MAC_SEL BIT(13)
+-#define MHWTRAP_P6_DIS BIT(8)
+-#define MHWTRAP_P5_RGMII_MODE BIT(7)
+-#define MHWTRAP_P5_DIS BIT(6)
+-#define MHWTRAP_PHY_ACCESS BIT(5)
++enum mt7531_xtal_fsel {
++ MT7531_XTAL_FSEL_25MHZ,
++ MT7531_XTAL_FSEL_40MHZ,
++};
+
+ /* Register for TOP signal control */
+ #define MT7530_TOP_SIG_CTRL 0x7808
--- /dev/null
+From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:14 +0300
+Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for
+ MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On MT7530, the media-independent interfaces of port 5 and 6 are controlled
+by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
+these bits only when the relevant port is being enabled or disabled. This
+ensures that these ports will be disabled when they are not in use.
+
+Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
+done on mt7530_setup().
+
+Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only
+on the appropriate case.
+
+If PHY muxing is detected, clear MT7530_P5_DIS before calling
+mt7530_setup_port5().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++-----------
+ 1 file changed, 27 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -880,8 +880,7 @@ static void mt7530_setup_port5(struct ds
+
+ val = mt7530_read(priv, MT753X_MTRAP);
+
+- val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
+- val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
++ val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
+
+ switch (priv->p5_mode) {
+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+@@ -891,15 +890,13 @@ static void mt7530_setup_port5(struct ds
+
+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ case MUX_PHY_P4:
+- val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+-
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+
+ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
+- val &= ~MT7530_P5_DIS;
++ val |= MT7530_P5_MAC_SEL;
+ break;
+ }
+
+@@ -1193,6 +1190,14 @@ mt7530_port_enable(struct dsa_switch *ds
+
+ mutex_unlock(&priv->reg_mutex);
+
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return 0;
++
++ if (port == 5)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
++
+ return 0;
+ }
+
+@@ -1211,6 +1216,14 @@ mt7530_port_disable(struct dsa_switch *d
+ PCR_MATRIX_CLR);
+
+ mutex_unlock(&priv->reg_mutex);
++
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return;
++
++ if (port == 5)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
+ }
+
+ static int
+@@ -2401,11 +2414,11 @@ mt7530_setup(struct dsa_switch *ds)
+ mt7530_rmw(priv, MT7530_TRGMII_RD(i),
+ RD_TAP_MASK, RD_TAP(16));
+
+- /* Enable port 6 */
+- val = mt7530_read(priv, MT753X_MTRAP);
+- val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
+- val |= MT7530_CHG_TRAP;
+- mt7530_write(priv, MT753X_MTRAP, val);
++ /* Allow modifying the trap and directly access PHY registers via the
++ * MDIO bus the switch is on.
++ */
++ mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
++ MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
+
+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+@@ -2488,8 +2501,11 @@ mt7530_setup(struct dsa_switch *ds)
+ break;
+ }
+
+- if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
++ if (priv->p5_mode == MUX_PHY_P0 ||
++ priv->p5_mode == MUX_PHY_P4) {
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ mt7530_setup_port5(ds, interface);
++ }
+ }
+
+ #ifdef CONFIG_GPIOLIB
--- /dev/null
+From 1f5669efca65564c7533704917f79003c6b36c9c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:15 +0300
+Subject: [PATCH 08/15] net: dsa: mt7530: return mt7530_setup_mdio &
+ mt7531_setup_common on error
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt7530_setup_mdio() and mt7531_setup_common() functions should be
+checked for errors. Return if the functions return a non-zero value.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2667,7 +2667,9 @@ mt7531_setup(struct dsa_switch *ds)
+ 0);
+ }
+
+- mt7531_setup_common(ds);
++ ret = mt7531_setup_common(ds);
++ if (ret)
++ return ret;
+
+ /* Setup VLAN ID 0 for VLAN-unaware bridges */
+ ret = mt7530_setup_vlan0(priv);
+@@ -3020,6 +3022,8 @@ mt753x_setup(struct dsa_switch *ds)
+ ret = mt7530_setup_mdio(priv);
+ if (ret && priv->irq)
+ mt7530_free_irq_common(priv);
++ if (ret)
++ return ret;
+
+ /* Initialise the PCS devices */
+ for (i = 0; i < priv->ds->num_ports; i++) {
--- /dev/null
+From 6cc2d4ccd77509df74b7b8ef46bbc6ba0a571318 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:16 +0300
+Subject: [PATCH 09/15] net: dsa: mt7530: define MAC speed capabilities per
+ switch model
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+With the support of the MT7988 SoC switch, the MAC speed capabilities
+defined on mt753x_phylink_get_caps() won't apply to all switch models
+anymore. Move them to more appropriate locations instead of overwriting
+config->mac_capabilities.
+
+Remove the comment on mt753x_phylink_get_caps() as it's become invalid with
+the support of MT7531 and MT7988 SoC switch.
+
+Add break to case 6 of mt7988_mac_port_get_caps() to be explicit.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2685,6 +2685,8 @@ mt7531_setup(struct dsa_switch *ds)
+ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+ {
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
++
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+ case 0 ... 4:
+@@ -2716,6 +2718,8 @@ static void mt7531_mac_port_get_caps(str
+ {
+ struct mt7530_priv *priv = ds->priv;
+
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
++
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+ case 0 ... 4:
+@@ -2755,14 +2759,17 @@ static void mt7988_mac_port_get_caps(str
+ case 0 ... 3:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
++
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
+ break;
+
+ /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
+ case 6:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+- MAC_10000FD;
++
++ config->mac_capabilities |= MAC_10000FD;
++ break;
+ }
+ }
+
+@@ -2932,9 +2939,7 @@ static void mt753x_phylink_get_caps(stru
+ {
+ struct mt7530_priv *priv = ds->priv;
+
+- /* This switch only supports full-duplex at 1Gbps */
+- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+- MAC_10 | MAC_100 | MAC_1000FD;
++ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE;
+
+ priv->info->mac_port_get_caps(ds, port, config);
+ }
--- /dev/null
+From dd0f15fc877c10567699190bce0f55e96f4ad6b5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:17 +0300
+Subject: [PATCH 10/15] net: dsa: mt7530: get rid of function sanity check
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Get rid of checking whether functions are filled properly. priv->info which
+is an mt753x_info structure is filled and checked for before this check.
+It's unnecessary checking whether it's filled properly.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3232,13 +3232,6 @@ mt7530_probe_common(struct mt7530_priv *
+ if (!priv->info)
+ return -EINVAL;
+
+- /* Sanity check if these required device operations are filled
+- * properly.
+- */
+- if (!priv->info->sw_setup || !priv->info->phy_read_c22 ||
+- !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps)
+- return -EINVAL;
+-
+ priv->id = priv->info->id;
+ priv->dev = dev;
+ priv->ds->priv = priv;
--- /dev/null
+From 2dff9759602b069f97ccc939e15a47ca051b2983 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:18 +0300
+Subject: [PATCH 11/15] net: dsa: mt7530: refactor MT7530_PMEEECR_P()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_PMEEECR_P() register is on MT7530, MT7531, and the switch on the
+MT7988 SoC. Rename the definition for them to MT753X_PMEEECR_P(). Use the
+FIELD_PREP and FIELD_GET macros. Rename GET_LPI_THRESH() and
+SET_LPI_THRESH() to LPI_THRESH_GET() and LPI_THRESH_SET().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 8 ++++----
+ drivers/net/dsa/mt7530.h | 13 +++++++------
+ 2 files changed, 11 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3051,10 +3051,10 @@ static int mt753x_get_mac_eee(struct dsa
+ struct ethtool_eee *e)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
++ u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port));
+
+ e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
+- e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
++ e->tx_lpi_timer = LPI_THRESH_GET(eeecr);
+
+ return 0;
+ }
+@@ -3068,11 +3068,11 @@ static int mt753x_set_mac_eee(struct dsa
+ if (e->tx_lpi_timer > 0xFFF)
+ return -EINVAL;
+
+- set = SET_LPI_THRESH(e->tx_lpi_timer);
++ set = LPI_THRESH_SET(e->tx_lpi_timer);
+ if (!e->tx_lpi_enabled)
+ /* Force LPI Mode without a delay */
+ set |= LPI_MODE_EN;
+- mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
++ mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set);
+
+ return 0;
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -364,13 +364,14 @@ enum mt7530_vlan_port_acc_frm {
+ PMCR_FORCE_SPEED_100 | \
+ PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+
+-#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
+-#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
+-#define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
++#define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100)
++#define WAKEUP_TIME_1000_MASK GENMASK(31, 24)
++#define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x)
++#define WAKEUP_TIME_100_MASK GENMASK(23, 16)
++#define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x)
+ #define LPI_THRESH_MASK GENMASK(15, 4)
+-#define LPI_THRESH_SHT 4
+-#define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
+-#define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
++#define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x)
++#define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x)
+ #define LPI_MODE_EN BIT(0)
+
+ #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
--- /dev/null
+From 21d67c2fabfe40baf33202d3287b67b6c16f8382 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:19 +0300
+Subject: [PATCH 12/15] net: dsa: mt7530: get rid of mac_port_validate member
+ of mt753x_info
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mac_port_validate member of the mt753x_info structure is not being
+used, remove it. Improve the member description section in the process.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.h | 10 +++-------
+ 1 file changed, 3 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -743,15 +743,14 @@ struct mt753x_pcs {
+
+ /* struct mt753x_info - This is the main data structure for holding the specific
+ * part for each supported device
++ * @id: Holding the identifier to a switch model
++ * @pcs_ops: Holding the pointer to the MAC PCS operations structure
+ * @sw_setup: Holding the handler to a device initialization
+ * @phy_read_c22: Holding the way reading PHY port using C22
+ * @phy_write_c22: Holding the way writing PHY port using C22
+ * @phy_read_c45: Holding the way reading PHY port using C45
+ * @phy_write_c45: Holding the way writing PHY port using C45
+- * @phy_mode_supported: Check if the PHY type is being supported on a certain
+- * port
+- * @mac_port_validate: Holding the way to set addition validate type for a
+- * certan MAC port
++ * @mac_port_get_caps: Holding the handler that provides MAC capabilities
+ * @mac_port_config: Holding the way setting up the PHY attribute to a
+ * certain MAC port
+ */
+@@ -770,9 +769,6 @@ struct mt753x_info {
+ int regnum, u16 val);
+ void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
+ struct phylink_config *config);
+- void (*mac_port_validate)(struct dsa_switch *ds, int port,
+- phy_interface_t interface,
+- unsigned long *supported);
+ void (*mac_port_config)(struct dsa_switch *ds, int port,
+ unsigned int mode,
+ phy_interface_t interface);
--- /dev/null
+From 6efc8ae3eb0363328f479191a0cf0dc12a16e090 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:20 +0300
+Subject: [PATCH 13/15] net: dsa: mt7530: use priv->ds->num_ports instead of
+ MT7530_NUM_PORTS
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use priv->ds->num_ports on all for loops which configure the switch
+registers. In the future, the value of MT7530_NUM_PORTS will depend on
+priv->id. Therefore, this change prepares the subdriver for a simpler
+implementation.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1411,7 +1411,7 @@ mt7530_port_set_vlan_unaware(struct dsa_
+ mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
+ G0_PORT_VID_DEF);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ if (dsa_is_user_port(ds, i) &&
+ dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
+ all_user_ports_removed = false;
+@@ -2428,7 +2428,7 @@ mt7530_setup(struct dsa_switch *ds)
+ /* Enable and reset MIB counters */
+ mt7530_mib_reset(ds);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+@@ -2539,7 +2539,7 @@ mt7531_setup_common(struct dsa_switch *d
+ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
+ UNU_FFP_MASK);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+@@ -2626,7 +2626,7 @@ mt7531_setup(struct dsa_switch *ds)
+ priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
+
+ /* Force link down on all ports before internal reset */
+- for (i = 0; i < MT7530_NUM_PORTS; i++)
++ for (i = 0; i < priv->ds->num_ports; i++)
+ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+
+ /* Reset the switch through internal reset */
--- /dev/null
+From c078ebbf5f6f6d8390035a9f92eeab766b78884d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:21 +0300
+Subject: [PATCH 14/15] net: dsa: mt7530: do not pass port variable to
+ mt7531_rgmii_setup()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt7531_rgmii_setup() function does not use the port variable, do not
+pass the variable to it.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2785,7 +2785,7 @@ mt7530_mac_config(struct dsa_switch *ds,
+ mt7530_setup_port6(priv->ds, interface);
+ }
+
+-static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
++static void mt7531_rgmii_setup(struct mt7530_priv *priv,
+ phy_interface_t interface,
+ struct phy_device *phydev)
+ {
+@@ -2836,7 +2836,7 @@ mt7531_mac_config(struct dsa_switch *ds,
+ if (phy_interface_mode_is_rgmii(interface)) {
+ dp = dsa_to_port(ds, port);
+ phydev = dp->slave->phydev;
+- mt7531_rgmii_setup(priv, port, interface, phydev);
++ mt7531_rgmii_setup(priv, interface, phydev);
+ }
+ }
+
--- /dev/null
+From e7a9cc3cc00b40e0bc2bae40bd2ece0e48fa51d5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:22 +0300
+Subject: [PATCH 15/15] net: dsa: mt7530: explain exposing MDIO bus of MT7531AE
+ better
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on MT7531AE.
+Therefore, the GPIO 11-12 pins are set to function as MDC and MDIO to
+expose the MDIO bus of the switch. Replace the comment with a better
+explanation.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2635,7 +2635,10 @@ mt7531_setup(struct dsa_switch *ds)
+ if (!priv->p5_sgmii) {
+ mt7531_pll_setup(priv);
+ } else {
+- /* Let ds->slave_mii_bus be able to access external phy. */
++ /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on
++ * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO
++ * to expose the MDIO bus of the switch.
++ */
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
+ MT7531_EXT_P_MDC_11);
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
--- /dev/null
+From 16e6592cd5c5bd74d8890973489f60176c692614 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Sun, 28 Apr 2024 12:19:58 +0300
+Subject: [PATCH] net: dsa: mt7530: do not set MT7530_P5_DIS when PHY muxing is
+ being used
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+DSA initalises the ds->num_ports amount of ports in
+dsa_switch_touch_ports(). When the PHY muxing feature is in use, port 5
+won't be defined in the device tree. Because of this, the type member of
+the dsa_port structure for this port will be assigned DSA_PORT_TYPE_UNUSED.
+The dsa_port_setup() function calls ds->ops->port_disable() when the port
+type is DSA_PORT_TYPE_UNUSED.
+
+The MT7530_P5_DIS bit is unset in mt7530_setup() when PHY muxing is being
+used. mt7530_port_disable() which is assigned to ds->ops->port_disable() is
+called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS
+which breaks network connectivity when PHY muxing is being used.
+
+Therefore, do not set MT7530_P5_DIS when PHY muxing is being used.
+
+Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530")
+Reported-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240428-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v2-1-bb7c37d293f8@arinc9.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1220,7 +1220,8 @@ mt7530_port_disable(struct dsa_switch *d
+ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
+ return;
+
+- if (port == 5)
++ /* Do not set MT7530_P5_DIS when port 5 is being used for PHY muxing. */
++ if (port == 5 && priv->p5_mode == GMAC5)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ else if (port == 6)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
--- /dev/null
+From d8dcf5bd6d0eace9f7c1daa14b63b3925b09d033 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 30 Apr 2024 08:01:33 +0300
+Subject: [PATCH] net: dsa: mt7530: detect PHY muxing when PHY is defined on
+ switch MDIO bus
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide
+direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO
+bus the switch listens on. The PHY muxing feature makes use of this.
+
+This is problematic as the PHY may be attached before the switch is
+initialised, in which case, the PHY will fail to be attached.
+
+Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration
+of switch MDIO bus"), we can describe the switch PHYs on the MDIO bus of
+the switch on the device tree. Extend the check to detect PHY muxing when
+the PHY is defined on the MDIO bus of the switch on the device tree.
+
+When the PHY is described this way, the switch will be initialised first,
+then the switch MDIO bus will be registered. Only after these steps, the
+PHY will be attached.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/20240430-b4-for-netnext-mt7530-use-switch-mdio-bus-for-phy-muxing-v2-1-9104d886d0db@arinc9.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2484,7 +2484,8 @@ mt7530_setup(struct dsa_switch *ds)
+ if (!phy_node)
+ continue;
+
+- if (phy_node->parent == priv->dev->of_node->parent) {
++ if (phy_node->parent == priv->dev->of_node->parent ||
++ phy_node->parent->parent == priv->dev->of_node) {
+ ret = of_get_phy_mode(mac_np, &interface);
+ if (ret && ret != -ENODEV) {
+ of_node_put(mac_np);
--- /dev/null
+From 71e79430117d56c409c5ea485a263bc0d8083390 Mon Sep 17 00:00:00 2001
+From: Eric Woudstra <ericwouds@gmail.com>
+Date: Tue, 26 Mar 2024 17:23:05 +0100
+Subject: [PATCH] net: phy: air_en8811h: Add the Airoha EN8811H PHY driver
+
+Add the driver for the Airoha EN8811H 2.5 Gigabit PHY. The phy supports
+100/1000/2500 Mbps with auto negotiation only.
+
+The driver uses two firmware files, for which updated versions are added to
+linux-firmware already.
+
+Note: At phy-address + 8 there is another device on the mdio bus, that
+belongs to the EN881H. While the original driver writes to it, Airoha
+has confirmed this is not needed. Therefore, communication with this
+device is not included in this driver.
+
+Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240326162305.303598-3-ericwouds@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/Kconfig | 5 +
+ drivers/net/phy/Makefile | 1 +
+ drivers/net/phy/air_en8811h.c | 1086 +++++++++++++++++++++++++++++++++
+ 3 files changed, 1092 insertions(+)
+ create mode 100644 drivers/net/phy/air_en8811h.c
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -68,6 +68,11 @@ config SFP
+
+ comment "MII PHY device drivers"
+
++config AIR_EN8811H_PHY
++ tristate "Airoha EN8811H 2.5 Gigabit PHY"
++ help
++ Currently supports the Airoha EN8811H PHY.
++
+ config AMD_PHY
+ tristate "AMD PHYs"
+ help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -34,6 +34,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
+
+ obj-$(CONFIG_ADIN_PHY) += adin.o
+ obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
++obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
+ obj-$(CONFIG_AMD_PHY) += amd.o
+ obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
+ obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
+--- /dev/null
++++ b/drivers/net/phy/air_en8811h.c
+@@ -0,0 +1,1086 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Driver for the Airoha EN8811H 2.5 Gigabit PHY.
++ *
++ * Limitations of the EN8811H:
++ * - Only full duplex supported
++ * - Forced speed (AN off) is not supported by hardware (100Mbps)
++ *
++ * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
++ *
++ * Copyright (C) 2023 Airoha Technology Corp.
++ */
++
++#include <linux/phy.h>
++#include <linux/firmware.h>
++#include <linux/property.h>
++#include <linux/wordpart.h>
++#include <asm/unaligned.h>
++
++#define EN8811H_PHY_ID 0x03a2a411
++
++#define EN8811H_MD32_DM "airoha/EthMD32.dm.bin"
++#define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin"
++
++#define AIR_FW_ADDR_DM 0x00000000
++#define AIR_FW_ADDR_DSP 0x00100000
++
++/* MII Registers */
++#define AIR_AUX_CTRL_STATUS 0x1d
++#define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2)
++#define AIR_AUX_CTRL_STATUS_SPEED_100 0x4
++#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
++#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
++
++#define AIR_EXT_PAGE_ACCESS 0x1f
++#define AIR_PHY_PAGE_STANDARD 0x0000
++#define AIR_PHY_PAGE_EXTENDED_4 0x0004
++
++/* MII Registers Page 4*/
++#define AIR_BPBUS_MODE 0x10
++#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000
++#define AIR_BPBUS_MODE_ADDR_INCR BIT(15)
++#define AIR_BPBUS_WR_ADDR_HIGH 0x11
++#define AIR_BPBUS_WR_ADDR_LOW 0x12
++#define AIR_BPBUS_WR_DATA_HIGH 0x13
++#define AIR_BPBUS_WR_DATA_LOW 0x14
++#define AIR_BPBUS_RD_ADDR_HIGH 0x15
++#define AIR_BPBUS_RD_ADDR_LOW 0x16
++#define AIR_BPBUS_RD_DATA_HIGH 0x17
++#define AIR_BPBUS_RD_DATA_LOW 0x18
++
++/* Registers on MDIO_MMD_VEND1 */
++#define EN8811H_PHY_FW_STATUS 0x8009
++#define EN8811H_PHY_READY 0x02
++
++#define AIR_PHY_MCU_CMD_1 0x800c
++#define AIR_PHY_MCU_CMD_1_MODE1 0x0
++#define AIR_PHY_MCU_CMD_2 0x800d
++#define AIR_PHY_MCU_CMD_2_MODE1 0x0
++#define AIR_PHY_MCU_CMD_3 0x800e
++#define AIR_PHY_MCU_CMD_3_MODE1 0x1101
++#define AIR_PHY_MCU_CMD_3_DOCMD 0x1100
++#define AIR_PHY_MCU_CMD_4 0x800f
++#define AIR_PHY_MCU_CMD_4_MODE1 0x0002
++#define AIR_PHY_MCU_CMD_4_INTCLR 0x00e4
++
++/* Registers on MDIO_MMD_VEND2 */
++#define AIR_PHY_LED_BCR 0x021
++#define AIR_PHY_LED_BCR_MODE_MASK GENMASK(1, 0)
++#define AIR_PHY_LED_BCR_TIME_TEST BIT(2)
++#define AIR_PHY_LED_BCR_CLK_EN BIT(3)
++#define AIR_PHY_LED_BCR_EXT_CTRL BIT(15)
++
++#define AIR_PHY_LED_DUR_ON 0x022
++
++#define AIR_PHY_LED_DUR_BLINK 0x023
++
++#define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2))
++#define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8))
++#define AIR_PHY_LED_ON_LINK1000 BIT(0)
++#define AIR_PHY_LED_ON_LINK100 BIT(1)
++#define AIR_PHY_LED_ON_LINK10 BIT(2)
++#define AIR_PHY_LED_ON_LINKDOWN BIT(3)
++#define AIR_PHY_LED_ON_FDX BIT(4) /* Full duplex */
++#define AIR_PHY_LED_ON_HDX BIT(5) /* Half duplex */
++#define AIR_PHY_LED_ON_FORCE_ON BIT(6)
++#define AIR_PHY_LED_ON_LINK2500 BIT(8)
++#define AIR_PHY_LED_ON_POLARITY BIT(14)
++#define AIR_PHY_LED_ON_ENABLE BIT(15)
++
++#define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2))
++#define AIR_PHY_LED_BLINK_1000TX BIT(0)
++#define AIR_PHY_LED_BLINK_1000RX BIT(1)
++#define AIR_PHY_LED_BLINK_100TX BIT(2)
++#define AIR_PHY_LED_BLINK_100RX BIT(3)
++#define AIR_PHY_LED_BLINK_10TX BIT(4)
++#define AIR_PHY_LED_BLINK_10RX BIT(5)
++#define AIR_PHY_LED_BLINK_COLLISION BIT(6)
++#define AIR_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
++#define AIR_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
++#define AIR_PHY_LED_BLINK_FORCE_BLINK BIT(9)
++#define AIR_PHY_LED_BLINK_2500TX BIT(10)
++#define AIR_PHY_LED_BLINK_2500RX BIT(11)
++
++/* Registers on BUCKPBUS */
++#define EN8811H_2P5G_LPA 0x3b30
++#define EN8811H_2P5G_LPA_2P5G BIT(0)
++
++#define EN8811H_FW_VERSION 0x3b3c
++
++#define EN8811H_POLARITY 0xca0f8
++#define EN8811H_POLARITY_TX_NORMAL BIT(0)
++#define EN8811H_POLARITY_RX_REVERSE BIT(1)
++
++#define EN8811H_GPIO_OUTPUT 0xcf8b8
++#define EN8811H_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5))
++
++#define EN8811H_FW_CTRL_1 0x0f0018
++#define EN8811H_FW_CTRL_1_START 0x0
++#define EN8811H_FW_CTRL_1_FINISH 0x1
++#define EN8811H_FW_CTRL_2 0x800000
++#define EN8811H_FW_CTRL_2_LOADING BIT(11)
++
++/* Led definitions */
++#define EN8811H_LED_COUNT 3
++
++/* Default LED setup:
++ * GPIO5 <-> LED0 On: Link detected, blink Rx/Tx
++ * GPIO4 <-> LED1 On: Link detected at 2500 or 1000 Mbps
++ * GPIO3 <-> LED2 On: Link detected at 2500 or 100 Mbps
++ */
++#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK) | \
++ BIT(TRIGGER_NETDEV_RX) | \
++ BIT(TRIGGER_NETDEV_TX))
++#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++ BIT(TRIGGER_NETDEV_LINK_1000))
++#define AIR_DEFAULT_TRIGGER_LED2 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++ BIT(TRIGGER_NETDEV_LINK_100))
++
++struct led {
++ unsigned long rules;
++ unsigned long state;
++};
++
++struct en8811h_priv {
++ u32 firmware_version;
++ bool mcu_needs_restart;
++ struct led led[EN8811H_LED_COUNT];
++};
++
++enum {
++ AIR_PHY_LED_STATE_FORCE_ON,
++ AIR_PHY_LED_STATE_FORCE_BLINK,
++};
++
++enum {
++ AIR_PHY_LED_DUR_BLINK_32MS,
++ AIR_PHY_LED_DUR_BLINK_64MS,
++ AIR_PHY_LED_DUR_BLINK_128MS,
++ AIR_PHY_LED_DUR_BLINK_256MS,
++ AIR_PHY_LED_DUR_BLINK_512MS,
++ AIR_PHY_LED_DUR_BLINK_1024MS,
++};
++
++enum {
++ AIR_LED_DISABLE,
++ AIR_LED_ENABLE,
++};
++
++enum {
++ AIR_ACTIVE_LOW,
++ AIR_ACTIVE_HIGH,
++};
++
++enum {
++ AIR_LED_MODE_DISABLE,
++ AIR_LED_MODE_USER_DEFINE,
++};
++
++#define AIR_PHY_LED_DUR_UNIT 1024
++#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64MS)
++
++static const unsigned long en8811h_led_trig = BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
++ BIT(TRIGGER_NETDEV_LINK) |
++ BIT(TRIGGER_NETDEV_LINK_10) |
++ BIT(TRIGGER_NETDEV_LINK_100) |
++ BIT(TRIGGER_NETDEV_LINK_1000) |
++ BIT(TRIGGER_NETDEV_LINK_2500) |
++ BIT(TRIGGER_NETDEV_RX) |
++ BIT(TRIGGER_NETDEV_TX);
++
++static int air_phy_read_page(struct phy_device *phydev)
++{
++ return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
++}
++
++static int air_phy_write_page(struct phy_device *phydev, int page)
++{
++ return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
++}
++
++static int __air_buckpbus_reg_write(struct phy_device *phydev,
++ u32 pbus_address, u32 pbus_data)
++{
++ int ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++ upper_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++ lower_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
++ upper_16_bits(pbus_data));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
++ lower_16_bits(pbus_data));
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++static int air_buckpbus_reg_write(struct phy_device *phydev,
++ u32 pbus_address, u32 pbus_data)
++{
++ int saved_page;
++ int ret = 0;
++
++ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++ if (saved_page >= 0) {
++ ret = __air_buckpbus_reg_write(phydev, pbus_address,
++ pbus_data);
++ if (ret < 0)
++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++ pbus_address, ret);
++ }
++
++ return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_buckpbus_reg_read(struct phy_device *phydev,
++ u32 pbus_address, u32 *pbus_data)
++{
++ int pbus_data_low, pbus_data_high;
++ int ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
++ upper_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
++ lower_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
++ if (pbus_data_high < 0)
++ return ret;
++
++ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
++ if (pbus_data_low < 0)
++ return ret;
++
++ *pbus_data = pbus_data_low | (pbus_data_high << 16);
++ return 0;
++}
++
++static int air_buckpbus_reg_read(struct phy_device *phydev,
++ u32 pbus_address, u32 *pbus_data)
++{
++ int saved_page;
++ int ret = 0;
++
++ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++ if (saved_page >= 0) {
++ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
++ if (ret < 0)
++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++ pbus_address, ret);
++ }
++
++ return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_buckpbus_reg_modify(struct phy_device *phydev,
++ u32 pbus_address, u32 mask, u32 set)
++{
++ int pbus_data_low, pbus_data_high;
++ u32 pbus_data_old, pbus_data_new;
++ int ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_FIXED);
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
++ upper_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
++ lower_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
++ if (pbus_data_high < 0)
++ return ret;
++
++ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
++ if (pbus_data_low < 0)
++ return ret;
++
++ pbus_data_old = pbus_data_low | (pbus_data_high << 16);
++ pbus_data_new = (pbus_data_old & ~mask) | set;
++ if (pbus_data_new == pbus_data_old)
++ return 0;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++ upper_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++ lower_16_bits(pbus_address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
++ upper_16_bits(pbus_data_new));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
++ lower_16_bits(pbus_data_new));
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++static int air_buckpbus_reg_modify(struct phy_device *phydev,
++ u32 pbus_address, u32 mask, u32 set)
++{
++ int saved_page;
++ int ret = 0;
++
++ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++ if (saved_page >= 0) {
++ ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask,
++ set);
++ if (ret < 0)
++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++ pbus_address, ret);
++ }
++
++ return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_write_buf(struct phy_device *phydev, u32 address,
++ const struct firmware *fw)
++{
++ unsigned int offset;
++ int ret;
++ u16 val;
++
++ ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR);
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
++ upper_16_bits(address));
++ if (ret < 0)
++ return ret;
++
++ ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
++ lower_16_bits(address));
++ if (ret < 0)
++ return ret;
++
++ for (offset = 0; offset < fw->size; offset += 4) {
++ val = get_unaligned_le16(&fw->data[offset + 2]);
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val);
++ if (ret < 0)
++ return ret;
++
++ val = get_unaligned_le16(&fw->data[offset]);
++ ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val);
++ if (ret < 0)
++ return ret;
++ }
++
++ return 0;
++}
++
++static int air_write_buf(struct phy_device *phydev, u32 address,
++ const struct firmware *fw)
++{
++ int saved_page;
++ int ret = 0;
++
++ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++ if (saved_page >= 0) {
++ ret = __air_write_buf(phydev, address, fw);
++ if (ret < 0)
++ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++ address, ret);
++ }
++
++ return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int en8811h_wait_mcu_ready(struct phy_device *phydev)
++{
++ int ret, reg_value;
++
++ /* Because of mdio-lock, may have to wait for multiple loads */
++ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++ EN8811H_PHY_FW_STATUS, reg_value,
++ reg_value == EN8811H_PHY_READY,
++ 20000, 7500000, true);
++ if (ret) {
++ phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value);
++ return -ENODEV;
++ }
++
++ return 0;
++}
++
++static int en8811h_load_firmware(struct phy_device *phydev)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ struct device *dev = &phydev->mdio.dev;
++ const struct firmware *fw1, *fw2;
++ int ret;
++
++ ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
++ if (ret < 0)
++ return ret;
++
++ ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
++ if (ret < 0)
++ goto en8811h_load_firmware_rel1;
++
++ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++ EN8811H_FW_CTRL_1_START);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
++ EN8811H_FW_CTRL_2_LOADING,
++ EN8811H_FW_CTRL_2_LOADING);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = air_write_buf(phydev, AIR_FW_ADDR_DM, fw1);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
++ EN8811H_FW_CTRL_2_LOADING, 0);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++ EN8811H_FW_CTRL_1_FINISH);
++ if (ret < 0)
++ goto en8811h_load_firmware_out;
++
++ ret = en8811h_wait_mcu_ready(phydev);
++
++ air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
++ &priv->firmware_version);
++ phydev_info(phydev, "MD32 firmware version: %08x\n",
++ priv->firmware_version);
++
++en8811h_load_firmware_out:
++ release_firmware(fw2);
++
++en8811h_load_firmware_rel1:
++ release_firmware(fw1);
++
++ if (ret < 0)
++ phydev_err(phydev, "Load firmware failed: %d\n", ret);
++
++ return ret;
++}
++
++static int en8811h_restart_mcu(struct phy_device *phydev)
++{
++ int ret;
++
++ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++ EN8811H_FW_CTRL_1_START);
++ if (ret < 0)
++ return ret;
++
++ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++ EN8811H_FW_CTRL_1_FINISH);
++ if (ret < 0)
++ return ret;
++
++ return en8811h_wait_mcu_ready(phydev);
++}
++
++static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ bool changed;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ if (on)
++ changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
++ &priv->led[index].state);
++ else
++ changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
++ &priv->led[index].state);
++
++ changed |= (priv->led[index].rules != 0);
++
++ if (changed)
++ return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
++ AIR_PHY_LED_ON(index),
++ AIR_PHY_LED_ON_MASK,
++ on ? AIR_PHY_LED_ON_FORCE_ON : 0);
++
++ return 0;
++}
++
++static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
++ bool blinking)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ bool changed;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ if (blinking)
++ changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++ &priv->led[index].state);
++ else
++ changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++ &priv->led[index].state);
++
++ changed |= (priv->led[index].rules != 0);
++
++ if (changed)
++ return phy_write_mmd(phydev, MDIO_MMD_VEND2,
++ AIR_PHY_LED_BLINK(index),
++ blinking ?
++ AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
++ else
++ return 0;
++}
++
++static int air_led_blink_set(struct phy_device *phydev, u8 index,
++ unsigned long *delay_on,
++ unsigned long *delay_off)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ bool blinking = false;
++ int err;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
++ blinking = true;
++ *delay_on = 50;
++ *delay_off = 50;
++ }
++
++ err = air_hw_led_blink_set(phydev, index, blinking);
++ if (err)
++ return err;
++
++ /* led-blink set, so switch led-on off */
++ err = air_hw_led_on_set(phydev, index, false);
++ if (err)
++ return err;
++
++ /* hw-control is off*/
++ if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
++ priv->led[index].rules = 0;
++
++ return 0;
++}
++
++static int air_led_brightness_set(struct phy_device *phydev, u8 index,
++ enum led_brightness value)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ int err;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ /* led-on set, so switch led-blink off */
++ err = air_hw_led_blink_set(phydev, index, false);
++ if (err)
++ return err;
++
++ err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
++ if (err)
++ return err;
++
++ /* hw-control is off */
++ if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
++ priv->led[index].rules = 0;
++
++ return 0;
++}
++
++static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
++ unsigned long *rules)
++{
++ struct en8811h_priv *priv = phydev->priv;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ *rules = priv->led[index].rules;
++
++ return 0;
++};
++
++static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
++ unsigned long rules)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ u16 on = 0, blink = 0;
++ int ret;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ priv->led[index].rules = rules;
++
++ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
++ on |= AIR_PHY_LED_ON_FDX;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= AIR_PHY_LED_ON_LINK10;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= AIR_PHY_LED_ON_LINK100;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= AIR_PHY_LED_ON_LINK1000;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
++ on |= AIR_PHY_LED_ON_LINK2500;
++
++ if (rules & BIT(TRIGGER_NETDEV_RX)) {
++ blink |= AIR_PHY_LED_BLINK_10RX |
++ AIR_PHY_LED_BLINK_100RX |
++ AIR_PHY_LED_BLINK_1000RX |
++ AIR_PHY_LED_BLINK_2500RX;
++ }
++
++ if (rules & BIT(TRIGGER_NETDEV_TX)) {
++ blink |= AIR_PHY_LED_BLINK_10TX |
++ AIR_PHY_LED_BLINK_100TX |
++ AIR_PHY_LED_BLINK_1000TX |
++ AIR_PHY_LED_BLINK_2500TX;
++ }
++
++ if (blink || on) {
++ /* switch hw-control on, so led-on and led-blink are off */
++ clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
++ &priv->led[index].state);
++ clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++ &priv->led[index].state);
++ } else {
++ priv->led[index].rules = 0;
++ }
++
++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++ AIR_PHY_LED_ON_MASK, on);
++
++ if (ret < 0)
++ return ret;
++
++ return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
++ blink);
++};
++
++static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
++{
++ int val = 0;
++ int err;
++
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ if (state == AIR_LED_ENABLE)
++ val |= AIR_PHY_LED_ON_ENABLE;
++ else
++ val &= ~AIR_PHY_LED_ON_ENABLE;
++
++ if (pol == AIR_ACTIVE_HIGH)
++ val |= AIR_PHY_LED_ON_POLARITY;
++ else
++ val &= ~AIR_PHY_LED_ON_POLARITY;
++
++ err = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++ AIR_PHY_LED_ON_ENABLE |
++ AIR_PHY_LED_ON_POLARITY, val);
++
++ if (err < 0)
++ return err;
++
++ return 0;
++}
++
++static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ int ret, i;
++
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
++ dur);
++ if (ret < 0)
++ return ret;
++
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
++ dur >> 1);
++ if (ret < 0)
++ return ret;
++
++ switch (mode) {
++ case AIR_LED_MODE_DISABLE:
++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
++ AIR_PHY_LED_BCR_EXT_CTRL |
++ AIR_PHY_LED_BCR_MODE_MASK, 0);
++ if (ret < 0)
++ return ret;
++ break;
++ case AIR_LED_MODE_USER_DEFINE:
++ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR,
++ AIR_PHY_LED_BCR_EXT_CTRL |
++ AIR_PHY_LED_BCR_CLK_EN,
++ AIR_PHY_LED_BCR_EXT_CTRL |
++ AIR_PHY_LED_BCR_CLK_EN);
++ if (ret < 0)
++ return ret;
++ break;
++ default:
++ phydev_err(phydev, "LED mode %d is not supported\n", mode);
++ return -EINVAL;
++ }
++
++ for (i = 0; i < num; ++i) {
++ ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
++ if (ret < 0) {
++ phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
++ return ret;
++ }
++ air_led_hw_control_set(phydev, i, priv->led[i].rules);
++ }
++
++ return 0;
++}
++
++static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
++ unsigned long rules)
++{
++ if (index >= EN8811H_LED_COUNT)
++ return -EINVAL;
++
++ /* All combinations of the supported triggers are allowed */
++ if (rules & ~en8811h_led_trig)
++ return -EOPNOTSUPP;
++
++ return 0;
++};
++
++static int en8811h_probe(struct phy_device *phydev)
++{
++ struct en8811h_priv *priv;
++ int ret;
++
++ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
++ GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++ phydev->priv = priv;
++
++ ret = en8811h_load_firmware(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* mcu has just restarted after firmware load */
++ priv->mcu_needs_restart = false;
++
++ priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
++ priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
++ priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
++
++ /* MDIO_DEVS1/2 empty, so set mmds_present bits here */
++ phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
++
++ ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
++ AIR_LED_MODE_DISABLE);
++ if (ret < 0) {
++ phydev_err(phydev, "Failed to disable leds: %d\n", ret);
++ return ret;
++ }
++
++ /* Configure led gpio pins as output */
++ ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
++ EN8811H_GPIO_OUTPUT_345,
++ EN8811H_GPIO_OUTPUT_345);
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++static int en8811h_config_init(struct phy_device *phydev)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ struct device *dev = &phydev->mdio.dev;
++ u32 pbus_value;
++ int ret;
++
++ /* If restart happened in .probe(), no need to restart now */
++ if (priv->mcu_needs_restart) {
++ ret = en8811h_restart_mcu(phydev);
++ if (ret < 0)
++ return ret;
++ } else {
++ /* Next calls to .config_init() mcu needs to restart */
++ priv->mcu_needs_restart = true;
++ }
++
++ /* Select mode 1, the only mode supported.
++ * Configures the SerDes for 2500Base-X with rate adaptation
++ */
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1,
++ AIR_PHY_MCU_CMD_1_MODE1);
++ if (ret < 0)
++ return ret;
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2,
++ AIR_PHY_MCU_CMD_2_MODE1);
++ if (ret < 0)
++ return ret;
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
++ AIR_PHY_MCU_CMD_3_MODE1);
++ if (ret < 0)
++ return ret;
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
++ AIR_PHY_MCU_CMD_4_MODE1);
++ if (ret < 0)
++ return ret;
++
++ /* Serdes polarity */
++ pbus_value = 0;
++ if (device_property_read_bool(dev, "airoha,pnswap-rx"))
++ pbus_value |= EN8811H_POLARITY_RX_REVERSE;
++ else
++ pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
++ if (device_property_read_bool(dev, "airoha,pnswap-tx"))
++ pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
++ else
++ pbus_value |= EN8811H_POLARITY_TX_NORMAL;
++ ret = air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
++ EN8811H_POLARITY_RX_REVERSE |
++ EN8811H_POLARITY_TX_NORMAL, pbus_value);
++ if (ret < 0)
++ return ret;
++
++ ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
++ AIR_LED_MODE_USER_DEFINE);
++ if (ret < 0) {
++ phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int en8811h_get_features(struct phy_device *phydev)
++{
++ linkmode_set_bit_array(phy_basic_ports_array,
++ ARRAY_SIZE(phy_basic_ports_array),
++ phydev->supported);
++
++ return genphy_c45_pma_read_abilities(phydev);
++}
++
++static int en8811h_get_rate_matching(struct phy_device *phydev,
++ phy_interface_t iface)
++{
++ return RATE_MATCH_PAUSE;
++}
++
++static int en8811h_config_aneg(struct phy_device *phydev)
++{
++ bool changed = false;
++ int ret;
++ u32 adv;
++
++ if (phydev->autoneg == AUTONEG_DISABLE) {
++ phydev_warn(phydev, "Disabling autoneg is not supported\n");
++ return -EINVAL;
++ }
++
++ adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
++
++ ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
++ MDIO_AN_10GBT_CTRL_ADV2_5G, adv);
++ if (ret < 0)
++ return ret;
++ if (ret > 0)
++ changed = true;
++
++ return __genphy_config_aneg(phydev, changed);
++}
++
++static int en8811h_read_status(struct phy_device *phydev)
++{
++ struct en8811h_priv *priv = phydev->priv;
++ u32 pbus_value;
++ int ret, val;
++
++ ret = genphy_update_link(phydev);
++ if (ret)
++ return ret;
++
++ phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
++ phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
++ phydev->speed = SPEED_UNKNOWN;
++ phydev->duplex = DUPLEX_UNKNOWN;
++ phydev->pause = 0;
++ phydev->asym_pause = 0;
++ phydev->rate_matching = RATE_MATCH_PAUSE;
++
++ ret = genphy_read_master_slave(phydev);
++ if (ret < 0)
++ return ret;
++
++ ret = genphy_read_lpa(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Get link partner 2.5GBASE-T ability from vendor register */
++ ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
++ if (ret < 0)
++ return ret;
++ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++ phydev->lp_advertising,
++ pbus_value & EN8811H_2P5G_LPA_2P5G);
++
++ if (phydev->autoneg_complete)
++ phy_resolve_aneg_pause(phydev);
++
++ if (!phydev->link)
++ return 0;
++
++ /* Get real speed from vendor register */
++ val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
++ if (val < 0)
++ return val;
++ switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
++ case AIR_AUX_CTRL_STATUS_SPEED_2500:
++ phydev->speed = SPEED_2500;
++ break;
++ case AIR_AUX_CTRL_STATUS_SPEED_1000:
++ phydev->speed = SPEED_1000;
++ break;
++ case AIR_AUX_CTRL_STATUS_SPEED_100:
++ phydev->speed = SPEED_100;
++ break;
++ }
++
++ /* Firmware before version 24011202 has no vendor register 2P5G_LPA.
++ * Assume link partner advertised it if connected at 2500Mbps.
++ */
++ if (priv->firmware_version < 0x24011202) {
++ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++ phydev->lp_advertising,
++ phydev->speed == SPEED_2500);
++ }
++
++ /* Only supports full duplex */
++ phydev->duplex = DUPLEX_FULL;
++
++ return 0;
++}
++
++static int en8811h_clear_intr(struct phy_device *phydev)
++{
++ int ret;
++
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3,
++ AIR_PHY_MCU_CMD_3_DOCMD);
++ if (ret < 0)
++ return ret;
++
++ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4,
++ AIR_PHY_MCU_CMD_4_INTCLR);
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
++{
++ int ret;
++
++ ret = en8811h_clear_intr(phydev);
++ if (ret < 0) {
++ phy_error(phydev);
++ return IRQ_NONE;
++ }
++
++ phy_trigger_machine(phydev);
++
++ return IRQ_HANDLED;
++}
++
++static struct phy_driver en8811h_driver[] = {
++{
++ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
++ .name = "Airoha EN8811H",
++ .probe = en8811h_probe,
++ .get_features = en8811h_get_features,
++ .config_init = en8811h_config_init,
++ .get_rate_matching = en8811h_get_rate_matching,
++ .config_aneg = en8811h_config_aneg,
++ .read_status = en8811h_read_status,
++ .config_intr = en8811h_clear_intr,
++ .handle_interrupt = en8811h_handle_interrupt,
++ .led_hw_is_supported = en8811h_led_hw_is_supported,
++ .read_page = air_phy_read_page,
++ .write_page = air_phy_write_page,
++ .led_blink_set = air_led_blink_set,
++ .led_brightness_set = air_led_brightness_set,
++ .led_hw_control_set = air_led_hw_control_set,
++ .led_hw_control_get = air_led_hw_control_get,
++} };
++
++module_phy_driver(en8811h_driver);
++
++static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
++ { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
++ { }
++};
++
++MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
++MODULE_FIRMWARE(EN8811H_MD32_DM);
++MODULE_FIRMWARE(EN8811H_MD32_DSP);
++
++MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
++MODULE_AUTHOR("Airoha");
++MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
++MODULE_LICENSE("GPL");
--- /dev/null
+From 87c33315af380ca12a2e59ac94edad4fe0481b4c Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@linaro.org>
+Date: Fri, 5 Apr 2024 13:08:59 +0300
+Subject: [PATCH] net: phy: air_en8811h: fix some error codes
+
+These error paths accidentally return "ret" which is zero/success
+instead of the correct error code.
+
+Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver")
+Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://lore.kernel.org/r/7ef2e230-dfb7-4a77-8973-9e5be1a99fc2@moroto.mountain
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/air_en8811h.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/air_en8811h.c
++++ b/drivers/net/phy/air_en8811h.c
+@@ -272,11 +272,11 @@ static int __air_buckpbus_reg_read(struc
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+- return ret;
++ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+- return ret;
++ return pbus_data_low;
+
+ *pbus_data = pbus_data_low | (pbus_data_high << 16);
+ return 0;
+@@ -323,11 +323,11 @@ static int __air_buckpbus_reg_modify(str
+
+ pbus_data_high = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+ if (pbus_data_high < 0)
+- return ret;
++ return pbus_data_high;
+
+ pbus_data_low = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+ if (pbus_data_low < 0)
+- return ret;
++ return pbus_data_low;
+
+ pbus_data_old = pbus_data_low | (pbus_data_high << 16);
+ pbus_data_new = (pbus_data_old & ~mask) | set;
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
-@@ -69,9 +69,9 @@ config SFP
- comment "MII PHY device drivers"
+@@ -74,9 +74,9 @@ config AIR_EN8811H_PHY
+ Currently supports the Airoha EN8811H PHY.
config AMD_PHY
- tristate "AMD PHYs"
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
-@@ -3198,6 +3198,7 @@ static int of_phy_led(struct phy_device
+@@ -3201,6 +3201,7 @@ static int of_phy_led(struct phy_device
struct device *dev = &phydev->mdio.dev;
struct led_init_data init_data = {};
struct led_classdev *cdev;
struct phy_led *phyled;
u32 index;
int err;
-@@ -3215,6 +3216,21 @@ static int of_phy_led(struct phy_device
+@@ -3218,6 +3219,21 @@ static int of_phy_led(struct phy_device
if (index > U8_MAX)
return -EINVAL;
--- a/drivers/bus/mhi/host/init.c
+++ b/drivers/bus/mhi/host/init.c
-@@ -881,6 +881,7 @@ static int parse_config(struct mhi_contr
+@@ -882,6 +882,7 @@ static int parse_config(struct mhi_contr
if (!mhi_cntrl->timeout_ms)
mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS;
if (!mhi_cntrl->buffer_len)
--- a/drivers/bus/mhi/host/internal.h
+++ b/drivers/bus/mhi/host/internal.h
-@@ -321,7 +321,7 @@ int __must_check mhi_read_reg_field(stru
+@@ -324,7 +324,7 @@ int __must_check mhi_read_reg_field(stru
u32 *out);
int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,
void __iomem *base, u32 offset, u32 mask,
ret = mhi_read_reg_field(mhi_cntrl, base, offset, mask, &out);
--- a/drivers/bus/mhi/host/pm.c
+++ b/drivers/bus/mhi/host/pm.c
-@@ -163,6 +163,7 @@ int mhi_ready_state_transition(struct mh
+@@ -171,6 +171,7 @@ int mhi_ready_state_transition(struct mh
enum mhi_pm_state cur_state;
struct device *dev = &mhi_cntrl->mhi_dev->dev;
u32 interval_us = 25000; /* poll register field every 25 milliseconds */
int ret, i;
/* Check if device entered error state */
-@@ -173,14 +174,18 @@ int mhi_ready_state_transition(struct mh
+@@ -181,14 +182,18 @@ int mhi_ready_state_transition(struct mh
/* Wait for RESET to be cleared and READY bit to be set by the device */
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
if (ret) {
dev_err(dev, "Device failed to enter MHI Ready\n");
return ret;
-@@ -479,7 +484,7 @@ static void mhi_pm_disable_transition(st
+@@ -487,7 +492,7 @@ static void mhi_pm_disable_transition(st
/* Wait for the reset bit to be cleared by the device */
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
if (ret)
dev_err(dev, "Device failed to clear MHI Reset\n");
-@@ -492,8 +497,8 @@ static void mhi_pm_disable_transition(st
+@@ -500,8 +505,8 @@ static void mhi_pm_disable_transition(st
if (!MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
/* wait for ready to be set */
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs,
if (ret)
dev_err(dev, "Device failed to enter READY state\n");
}
-@@ -1111,7 +1116,8 @@ int mhi_async_power_up(struct mhi_contro
+@@ -1125,7 +1130,8 @@ int mhi_async_power_up(struct mhi_contro
if (state == MHI_STATE_SYS_ERR) {
mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
if (ret) {
dev_info(dev, "Failed to reset MHI due to syserr state\n");
goto error_exit;
-@@ -1202,14 +1208,18 @@ EXPORT_SYMBOL_GPL(mhi_power_down);
+@@ -1216,14 +1222,18 @@ EXPORT_SYMBOL_GPL(mhi_power_down);
int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
{
int ret = mhi_async_power_up(mhi_cntrl);
# CONFIG_NFC is not set
# CONFIG_NFP is not set
# CONFIG_NFSD is not set
+# CONFIG_NFSD_V2 is not set
# CONFIG_NFSD_V2_ACL is not set
CONFIG_NFSD_V3=y
# CONFIG_NFSD_V3_ACL is not set
# CONFIG_NF_DUP_IPV4 is not set
# CONFIG_NF_DUP_IPV6 is not set
# CONFIG_NF_FLOW_TABLE is not set
+# CONFIG_NF_FLOW_TABLE_PROCFS is not set
# CONFIG_NF_LOG_ARP is not set
# CONFIG_NF_LOG_BRIDGE is not set
# CONFIG_NF_LOG_IPV4 is not set
# CONFIG_AHCI_QORIQ is not set
# CONFIG_AHCI_XGENE is not set
CONFIG_AIO=y
-# CONFIG_AIR_EN8811H_PHY is not set
# CONFIG_AIRO is not set
# CONFIG_AIRO_CS is not set
+# CONFIG_AIR_EN8811H_PHY is not set
# CONFIG_AIX_PARTITION is not set
# CONFIG_AK09911 is not set
# CONFIG_AK8974 is not set
# CONFIG_ARM64_ERRATUM_2441007 is not set
# CONFIG_ARM64_ERRATUM_2441009 is not set
# CONFIG_ARM64_ERRATUM_2658417 is not set
+# CONFIG_ARM64_ERRATUM_2966298 is not set
# CONFIG_ARM64_ERRATUM_819472 is not set
# CONFIG_ARM64_ERRATUM_824069 is not set
# CONFIG_ARM64_ERRATUM_826319 is not set
# CONFIG_ARM64_ERRATUM_843419 is not set
# CONFIG_ARM64_ERRATUM_845719 is not set
# CONFIG_ARM64_ERRATUM_858921 is not set
-# CONFIG_ARM64_ERRATUM_2966298 is not set
# CONFIG_ARM64_HW_AFDBM is not set
# CONFIG_ARM64_LSE_ATOMICS is not set
CONFIG_ARM64_MODULE_PLTS=y
# CONFIG_GPIO_TPIC2810 is not set
# CONFIG_GPIO_TS4900 is not set
# CONFIG_GPIO_TS5500 is not set
+# CONFIG_GPIO_VF610 is not set
# CONFIG_GPIO_VIRTIO is not set
# CONFIG_GPIO_VX855 is not set
# CONFIG_GPIO_WATCHDOG is not set
CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_LOCKD_V4=y
-CONFIG_LOCK_MM_AND_FIND_VMA=y
# CONFIG_LOCKUP_DETECTOR is not set
# CONFIG_LOCK_EVENT_COUNTS is not set
+CONFIG_LOCK_MM_AND_FIND_VMA=y
# CONFIG_LOCK_STAT is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_LOGFS is not set
# CONFIG_NFC is not set
# CONFIG_NFP is not set
# CONFIG_NFSD is not set
+# CONFIG_NFSD_V2 is not set
# CONFIG_NFSD_V2_ACL is not set
CONFIG_NFSD_V3=y
# CONFIG_NFSD_V3_ACL is not set
# CONFIG_NFS_FSCACHE is not set
# CONFIG_NFS_SWAP is not set
# CONFIG_NFS_V2 is not set
-# CONFIG_NFSD_V2 is not set
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_QCA7000 is not set
# CONFIG_QCA7000_SPI is not set
# CONFIG_QCA7000_UART is not set
-# CONFIG_QCA83XX_PHY is not set
# CONFIG_QCA807X_PHY is not set
# CONFIG_QCA808X_PHY is not set
+# CONFIG_QCA83XX_PHY is not set
# CONFIG_QCOM_A7PLL is not set
# CONFIG_QCOM_BAM_DMUX is not set
# CONFIG_QCOM_EMAC is not set
# CONFIG_TCS3414 is not set
# CONFIG_TCS3472 is not set
# CONFIG_TEE is not set
+# CONFIG_TEGRA210_ADMA is not set
+# CONFIG_TEGRA_ACONNECT is not set
# CONFIG_TEGRA_AHB is not set
# CONFIG_TEGRA_HOST1X is not set
# CONFIG_TEHUTI is not set
# CONFIG_TRUSTED_FOUNDATIONS is not set
# CONFIG_TRUSTED_KEYS is not set
# CONFIG_TRUSTED_KEYS_CAAM is not set
-# CONFIG_TRUSTED_KEYS_TPM is not set
# CONFIG_TRUSTED_KEYS_TEE is not set
+# CONFIG_TRUSTED_KEYS_TPM is not set
# CONFIG_TSL2583 is not set
# CONFIG_TSL2591 is not set
# CONFIG_TSL2772 is not set
# CONFIG_UFS_FS is not set
# CONFIG_UHID is not set
CONFIG_UID16=y
-# CONFIG_UIO is not set
# CONFIG_UIMAGE_FIT_BLK is not set
+# CONFIG_UIO is not set
# CONFIG_ULTRA is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_UNICODE is not set
# CONFIG_USB_CDNS3 is not set
# CONFIG_USB_CDNS3_IMX is not set
# CONFIG_USB_CDNS3_PCI_WRAP is not set
-# CONFIG_USB_CDNS_SUPPORT is not set
# CONFIG_USB_CDNSP_PCI is not set
+# CONFIG_USB_CDNS_SUPPORT is not set
# CONFIG_USB_CHAOSKEY is not set
# CONFIG_USB_CHIPIDEA is not set
# CONFIG_USB_CHIPIDEA_GENERIC is not set
# CONFIG_VIDEO_SMIAPP is not set
# CONFIG_VIDEO_SOLO6X10 is not set
# CONFIG_VIDEO_SONY_BTF_MPX is not set
-# CONFIG_VIDEO_SUN4I_CSI is not set
-# CONFIG_VIDEO_SUN6I_CSI is not set
-# CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 is not set
# CONFIG_VIDEO_SR030PC30 is not set
# CONFIG_VIDEO_STK1160_COMMON is not set
# CONFIG_VIDEO_ST_MIPID02 is not set
+# CONFIG_VIDEO_SUN4I_CSI is not set
+# CONFIG_VIDEO_SUN6I_CSI is not set
+# CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 is not set
# CONFIG_VIDEO_TC358743 is not set
# CONFIG_VIDEO_TDA1997X is not set
# CONFIG_VIDEO_TDA7432 is not set
# CONFIG_ARM_CCI_PMU is not set
# CONFIG_ARM_CCN is not set
# CONFIG_ARM_CMN is not set
+# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
# CONFIG_ARM_CPUIDLE is not set
CONFIG_ARM_CPU_TOPOLOGY=y
# CONFIG_ARM_CRYPTO is not set
# CONFIG_ARM_SDE_INTERFACE is not set
# CONFIG_ARM_SMCCC_SOC_ID is not set
# CONFIG_ARM_SMC_WATCHDOG is not set
+# CONFIG_ARM_SMMU_V3_PMU is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
# CONFIG_ARM_SPE_PMU is not set
# CONFIG_ARM_THUMBEE is not set
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
+# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
+# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_JDI_R63452 is not set
# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_LVDS is not set
+# CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set
# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
+# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set
# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
+# CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set
# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
# CONFIG_DRM_PANEL_TPO_Y17P is not set
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
+# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
+# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set
# CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN is not set
# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# CONFIG_REGULATOR_QCOM_REFGEN is not set
# CONFIG_REGULATOR_RAA215300 is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2 is not set
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RT4803 is not set
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_SPI_BCM2835 is not set
# CONFIG_SPI_BCM63XX_HSSPI is not set
# CONFIG_SPI_BCM_QSPI is not set
+# CONFIG_SPI_BCMBCA_HSSPI is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_BUTTERFLY is not set
# CONFIG_SPI_CADENCE is not set
+#define SYMTAB_DISCARD_GPL
+#endif
+
- /* Align . to a 8 byte boundary equals to maximum function alignment. */
- #define ALIGN_FUNCTION() . = ALIGN(8)
+ /* Align . function alignment. */
+ #define ALIGN_FUNCTION() . = ALIGN(CONFIG_FUNCTION_ALIGNMENT)
@@ -485,14 +495,14 @@
/* Kernel symbol table: Normal symbols */ \
depends on NETFILTER_ADVANCED
help
H.323 is a VoIP signalling protocol from ITU-T. As one of the most
-@@ -1105,7 +1104,6 @@ config NETFILTER_XT_TARGET_SECMARK
+@@ -1114,7 +1113,6 @@ config NETFILTER_XT_TARGET_SECMARK
config NETFILTER_XT_TARGET_TCPMSS
tristate '"TCPMSS" target support'
help
This option adds the flow table core infrastructure.
-@@ -1010,6 +1009,15 @@ config NETFILTER_XT_TARGET_NOTRACK
+@@ -1019,6 +1018,15 @@ config NETFILTER_XT_TARGET_NOTRACK
depends on NETFILTER_ADVANCED
select NETFILTER_XT_TARGET_CT
depends on NETFILTER_ADVANCED
--- a/net/netfilter/Makefile
+++ b/net/netfilter/Makefile
-@@ -143,6 +143,7 @@ obj-$(CONFIG_NETFILTER_XT_TARGET_CLASSIF
+@@ -144,6 +144,7 @@ obj-$(CONFIG_NETFILTER_XT_TARGET_CLASSIF
obj-$(CONFIG_NETFILTER_XT_TARGET_CONNSECMARK) += xt_CONNSECMARK.o
obj-$(CONFIG_NETFILTER_XT_TARGET_CT) += xt_CT.o
obj-$(CONFIG_NETFILTER_XT_TARGET_DSCP) += xt_DSCP.o
obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
--- /dev/null
+++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,701 @@
+@@ -0,0 +1,702 @@
+/*
+ * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
+ *
+ proto = veth->h_vlan_encapsulated_proto;
+ break;
+ case htons(ETH_P_PPP_SES):
-+ proto = nf_flow_pppoe_proto(skb);
++ if (!nf_flow_pppoe_proto(skb, &proto))
++ return NF_ACCEPT;
+ break;
+ default:
+ proto = skb->protocol;
#define QUECTEL_VENDOR_ID 0x2c7c
/* These Quectel products use Quectel's vendor ID */
-@@ -1147,6 +1152,11 @@ static const struct usb_device_id option
+@@ -1156,6 +1161,11 @@ static const struct usb_device_id option
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
.driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
/* Quectel products using Qualcomm vendor ID */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1188,6 +1198,11 @@ static const struct usb_device_id option
+@@ -1197,6 +1207,11 @@ static const struct usb_device_id option
.driver_info = ZLP },
{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
.driver_info = RSVD(4) },
+From 9fabf60187f1fa19e6f6bb5441587d485bd534b0 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 9 Apr 2024 17:06:38 +0100
+Subject: [PATCH] rndis_host: add a bunch of USB IDs
+
+Add a bunch of USB IDs found in various places online to the
+RNDIS USB network driver.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/usb/rndis_host.c | 40 ++++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
--- a/drivers/net/usb/rndis_host.c
+++ b/drivers/net/usb/rndis_host.c
@@ -630,6 +630,16 @@ static const struct driver_info zte_rndi
--- a/fs/locks.c
+++ b/fs/locks.c
-@@ -2953,6 +2953,8 @@ static const struct seq_operations locks
+@@ -3008,6 +3008,8 @@ static const struct seq_operations locks
static int __init proc_locks_init(void)
{
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
-@@ -1562,7 +1562,7 @@ static void device_links_purge(struct de
+@@ -1577,7 +1577,7 @@ static void device_links_purge(struct de
#define FW_DEVLINK_FLAGS_RPM (FW_DEVLINK_FLAGS_ON | \
DL_FLAG_PM_RUNTIME)
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 12:35:21 +0200
+Subject: [PATCH] net: enable fraglist GRO by default
+
+This can significantly improve performance for packet forwarding/bridging
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/linux/netdev_features.h
++++ b/include/linux/netdev_features.h
+@@ -242,10 +242,10 @@ static inline int find_next_netdev_featu
+ #define NETIF_F_UPPER_DISABLES NETIF_F_LRO
+
+ /* changeable features with no special hardware requirements */
+-#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO)
++#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
+
+ /* Changeable features with no special hardware requirements that defaults to off. */
+-#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD)
+
+ #define NETIF_F_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \
+ NETIF_F_HW_VLAN_CTAG_RX | \
obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
--- /dev/null
+++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,702 @@
+@@ -0,0 +1,703 @@
+/*
+ * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
+ *
+ proto = veth->h_vlan_encapsulated_proto;
+ break;
+ case htons(ETH_P_PPP_SES):
-+ proto = nf_flow_pppoe_proto(skb);
++ if (!nf_flow_pppoe_proto(skb, &proto))
++ return NF_ACCEPT;
+ break;
+ default:
+ proto = skb->protocol;
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -3488,6 +3488,9 @@ static int mv88e6xxx_setup_port(struct m
+@@ -3500,6 +3500,9 @@ static int mv88e6xxx_setup_port(struct m
else
reg = 1 << port;
const struct header_ops *header_ops;
unsigned char operstate;
-@@ -2206,6 +2213,10 @@ struct net_device {
+@@ -2204,6 +2211,10 @@ struct net_device {
struct mctp_dev __rcu *mctp_ptr;
#endif
*/
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -3040,6 +3040,10 @@ static inline int pskb_trim(struct sk_bu
+@@ -3045,6 +3045,10 @@ static inline int pskb_trim(struct sk_bu
return (len < skb->len) ? __pskb_trim(skb, len) : 0;
}
/**
* pskb_trim_unique - remove end from a paged unique (not cloned) buffer
* @skb: buffer to alter
-@@ -3189,16 +3193,6 @@ static inline struct sk_buff *dev_alloc_
+@@ -3194,16 +3198,6 @@ static inline struct sk_buff *dev_alloc_
}
{
--- a/net/ethernet/eth.c
+++ b/net/ethernet/eth.c
-@@ -171,6 +171,12 @@ __be16 eth_type_trans(struct sk_buff *sk
+@@ -159,6 +159,12 @@ __be16 eth_type_trans(struct sk_buff *sk
const struct ethhdr *eth;
skb->dev = dev;
#define QUECTEL_VENDOR_ID 0x2c7c
/* These Quectel products use Quectel's vendor ID */
-@@ -1147,6 +1152,11 @@ static const struct usb_device_id option
+@@ -1156,6 +1161,11 @@ static const struct usb_device_id option
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
.driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
/* Quectel products using Qualcomm vendor ID */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1188,6 +1198,11 @@ static const struct usb_device_id option
+@@ -1197,6 +1207,11 @@ static const struct usb_device_id option
.driver_info = ZLP },
{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
.driver_info = RSVD(4) },
+From 9fabf60187f1fa19e6f6bb5441587d485bd534b0 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 9 Apr 2024 17:06:38 +0100
+Subject: [PATCH] rndis_host: add a bunch of USB IDs
+
+Add a bunch of USB IDs found in various places online to the
+RNDIS USB network driver.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/usb/rndis_host.c | 40 ++++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
--- a/drivers/net/usb/rndis_host.c
+++ b/drivers/net/usb/rndis_host.c
@@ -630,6 +630,16 @@ static const struct driver_info zte_rndi
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
-@@ -1702,7 +1702,7 @@ static void device_links_purge(struct de
+@@ -1717,7 +1717,7 @@ static void device_links_purge(struct de
#define FW_DEVLINK_FLAGS_RPM (FW_DEVLINK_FLAGS_ON | \
DL_FLAG_PM_RUNTIME)
--- /dev/null
+--- a/tools/scripts/Makefile.include
++++ b/tools/scripts/Makefile.include
+@@ -72,8 +72,6 @@ $(call allow-override,CXX,$(CROSS_COMPIL
+ $(call allow-override,STRIP,$(CROSS_COMPILE)strip)
+ endif
+
+-CC_NO_CLANG := $(shell $(CC) -dM -E -x c /dev/null | grep -Fq "__clang__"; echo $$?)
+-
+ ifneq ($(LLVM),)
+ HOSTAR ?= $(LLVM_PREFIX)llvm-ar$(LLVM_SUFFIX)
+ HOSTCC ?= $(LLVM_PREFIX)clang$(LLVM_SUFFIX)
+@@ -84,6 +82,9 @@ HOSTCC ?= gcc
+ HOSTLD ?= ld
+ endif
+
++CC_NO_CLANG := $(shell $(CC) -dM -E -x c /dev/null | grep -Fq "__clang__"; echo $$?)
++HOSTCC_NO_CLANG := $(shell $(HOSTCC) -dM -E -x c /dev/null | grep -Fq "__clang__"; echo $$?)
++
+ # Some tools require Clang, LLC and/or LLVM utils
+ CLANG ?= clang
+ LLC ?= llc
+@@ -92,8 +93,9 @@ LLVM_OBJCOPY ?= llvm-objcopy
+ LLVM_STRIP ?= llvm-strip
+
+ ifeq ($(CC_NO_CLANG), 1)
+-EXTRA_WARNINGS += -Wstrict-aliasing=3
+-
++ ifeq ($(HOSTCC_NO_CLANG), 1)
++ EXTRA_WARNINGS += -Wstrict-aliasing=3
++ endif
+ else ifneq ($(CROSS_COMPILE),)
+ # Allow userspace to override CLANG_CROSS_FLAGS to specify their own
+ # sysroots and flags or to avoid the GCC call in pure Clang builds.
+--- a/tools/include/linux/types.h
++++ b/tools/include/linux/types.h
+@@ -56,6 +56,7 @@ typedef __s8 s8;
+ #define __user
+ #endif
+ #define __must_check
++#undef __cold
+ #define __cold
+
+ typedef __u16 __bitwise __le16;
+--- a/tools/objtool/include/objtool/objtool.h
++++ b/tools/objtool/include/objtool/objtool.h
+@@ -12,6 +12,7 @@
+
+ #include <objtool/elf.h>
+
++#undef __weak
+ #define __weak __attribute__((weak))
+
+ struct pv_state {
+--- a/tools/include/asm-generic/bitops/fls.h
++++ b/tools/include/asm-generic/bitops/fls.h
+@@ -2,6 +2,8 @@
+ #ifndef _ASM_GENERIC_BITOPS_FLS_H_
+ #define _ASM_GENERIC_BITOPS_FLS_H_
+
++#include <string.h>
++
+ /**
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+@@ -10,6 +12,7 @@
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+
++#define fls __linux_fls
+ static __always_inline int fls(unsigned int x)
+ {
+ int r = 32;
+--- a/tools/lib/string.c
++++ b/tools/lib/string.c
+@@ -96,6 +96,7 @@ int strtobool(const char *s, bool *res)
+ * If libc has strlcpy() then that version will override this
+ * implementation:
+ */
++#ifndef __APPLE__
+ #ifdef __clang__
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wignored-attributes"
+@@ -114,6 +115,7 @@ size_t __weak strlcpy(char *dest, const
+ #ifdef __clang__
+ #pragma clang diagnostic pop
+ #endif
++#endif
+
+ /**
+ * skip_spaces - Removes leading whitespace from @str.
if (err)
--- a/scripts/mod/modpost.c
+++ b/scripts/mod/modpost.c
-@@ -1745,7 +1745,9 @@ static void read_symbols(const char *mod
+@@ -1692,7 +1692,9 @@ static void read_symbols(const char *mod
symname = remove_dot(info.strtab + sym->st_name);
handle_symbol(mod, &info, sym, symname);
}
check_sec_ref(mod, &info);
-@@ -1918,8 +1920,10 @@ static void add_header(struct buffer *b,
+@@ -1865,8 +1867,10 @@ static void add_header(struct buffer *b,
buf_printf(b, "BUILD_SALT;\n");
buf_printf(b, "BUILD_LTO_INFO;\n");
buf_printf(b, "\n");
buf_printf(b, "\n");
buf_printf(b, "__visible struct module __this_module\n");
buf_printf(b, "__section(\".gnu.linkonce.this_module\") = {\n");
-@@ -1933,8 +1937,10 @@ static void add_header(struct buffer *b,
+@@ -1880,8 +1884,10 @@ static void add_header(struct buffer *b,
buf_printf(b, "\t.arch = MODULE_ARCH_INIT,\n");
buf_printf(b, "};\n");
buf_printf(b,
"\n"
-@@ -1942,8 +1948,10 @@ static void add_header(struct buffer *b,
+@@ -1889,8 +1895,10 @@ static void add_header(struct buffer *b,
"MODULE_INFO(retpoline, \"Y\");\n"
"#endif\n");
if (strstarts(mod->name, "tools/testing"))
buf_printf(b, "\nMODULE_INFO(test, \"Y\");\n");
-@@ -2053,11 +2061,13 @@ static void add_depends(struct buffer *b
+@@ -2000,11 +2008,13 @@ static void add_depends(struct buffer *b
static void add_srcversion(struct buffer *b, struct module *mod)
{
}
static void write_buf(struct buffer *b, const char *fname)
-@@ -2140,7 +2150,9 @@ static void write_mod_c_file(struct modu
+@@ -2087,7 +2097,9 @@ static void write_mod_c_file(struct modu
add_exported_symbols(&buf, mod);
add_versions(&buf, mod);
add_depends(&buf, mod);
+#else
+#include "elf.h"
+#endif
+ #include "../../include/linux/module_symbol.h"
#include "list.h"
- #include "elfconfig.h"
+++ /dev/null
-From b14784e7883390c20ed3ff904892255404a5914b Mon Sep 17 00:00:00 2001
-From: Felix Fietkau <nbd@nbd.name>
-Date: Fri, 7 Jul 2017 17:05:53 +0200
-Subject: add an optional config option for stripping all unnecessary symbol exports from the kernel image
-
-lede-commit: bb5a40c64b7c4f4848509fa0a6625055fc9e66cc
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
- include/asm-generic/vmlinux.lds.h | 18 +++++++++++++++---
- include/linux/export.h | 9 ++++++++-
- scripts/Makefile.build | 2 +-
- 3 files changed, 24 insertions(+), 5 deletions(-)
-
---- a/include/asm-generic/vmlinux.lds.h
-+++ b/include/asm-generic/vmlinux.lds.h
-@@ -81,6 +81,16 @@
- #define RO_EXCEPTION_TABLE
- #endif
-
-+#ifndef SYMTAB_KEEP
-+#define SYMTAB_KEEP KEEP(*(SORT(___ksymtab+*)))
-+#define SYMTAB_KEEP_GPL KEEP(*(SORT(___ksymtab_gpl+*)))
-+#endif
-+
-+#ifndef SYMTAB_DISCARD
-+#define SYMTAB_DISCARD
-+#define SYMTAB_DISCARD_GPL
-+#endif
-+
- /* Align . function alignment. */
- #define ALIGN_FUNCTION() . = ALIGN(CONFIG_FUNCTION_ALIGNMENT)
-
-@@ -486,14 +496,14 @@
- /* Kernel symbol table: Normal symbols */ \
- __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \
- __start___ksymtab = .; \
-- KEEP(*(SORT(___ksymtab+*))) \
-+ SYMTAB_KEEP \
- __stop___ksymtab = .; \
- } \
- \
- /* Kernel symbol table: GPL-only symbols */ \
- __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \
- __start___ksymtab_gpl = .; \
-- KEEP(*(SORT(___ksymtab_gpl+*))) \
-+ SYMTAB_KEEP_GPL \
- __stop___ksymtab_gpl = .; \
- } \
- \
-@@ -513,7 +523,7 @@
- \
- /* Kernel symbol table: strings */ \
- __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) { \
-- *(__ksymtab_strings) \
-+ *(__ksymtab_strings+*) \
- } \
- \
- /* __*init sections */ \
-@@ -1000,6 +1010,8 @@
- #define COMMON_DISCARDS \
- SANITIZER_DISCARDS \
- PATCHABLE_DISCARDS \
-+ SYMTAB_DISCARD \
-+ SYMTAB_DISCARD_GPL \
- *(.discard) \
- *(.discard.*) \
- *(.export_symbol) \
---- a/include/linux/export-internal.h
-+++ b/include/linux/export-internal.h
-@@ -26,6 +26,12 @@
- #define __KSYM_REF(sym) ".long " #sym
- #endif
-
-+#ifdef MODULE
-+#define __EXPORT_SUFFIX(sym)
-+#else
-+#define __EXPORT_SUFFIX(sym) "+" #sym
-+#endif
-+
- /*
- * For every exported symbol, do the following:
- *
-@@ -38,7 +44,7 @@
- * former apparently works on all arches according to the binutils source.
- */
- #define __KSYMTAB(name, sym, sec, ns) \
-- asm(" .section \"__ksymtab_strings\",\"aMS\",%progbits,1" "\n" \
-+ asm(" .section \"__ksymtab_strings" __EXPORT_SUFFIX(sym) "\",\"aMS\",%progbits,1" "\n" \
- "__kstrtab_" #name ":" "\n" \
- " .asciz \"" #name "\"" "\n" \
- "__kstrtabns_" #name ":" "\n" \
---- a/scripts/Makefile.build
-+++ b/scripts/Makefile.build
-@@ -366,7 +366,7 @@ targets += $(real-dtb-y) $(lib-y) $(alwa
- # Linker scripts preprocessor (.lds.S -> .lds)
- # ---------------------------------------------------------------------------
- quiet_cmd_cpp_lds_S = LDS $@
-- cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -U$(ARCH) \
-+ cmd_cpp_lds_S = $(CPP) $(EXTRA_LDSFLAGS) $(cpp_flags) -P -U$(ARCH) \
- -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
-
- $(obj)/%.lds: $(src)/%.lds.S FORCE
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 12:35:21 +0200
+Subject: [PATCH] net: enable fraglist GRO by default
+
+This can significantly improve performance for packet forwarding/bridging
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/linux/netdev_features.h
++++ b/include/linux/netdev_features.h
+@@ -242,10 +242,10 @@ static inline int find_next_netdev_featu
+ #define NETIF_F_UPPER_DISABLES NETIF_F_LRO
+
+ /* changeable features with no special hardware requirements */
+-#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO)
++#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
+
+ /* Changeable features with no special hardware requirements that defaults to off. */
+-#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD)
+
+ #define NETIF_F_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \
+ NETIF_F_HW_VLAN_CTAG_RX | \
obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
--- /dev/null
+++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,702 @@
+@@ -0,0 +1,703 @@
+/*
+ * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
+ *
+ proto = veth->h_vlan_encapsulated_proto;
+ break;
+ case htons(ETH_P_PPP_SES):
-+ proto = nf_flow_pppoe_proto(skb);
++ if (!nf_flow_pppoe_proto(skb, &proto))
++ return NF_ACCEPT;
+ break;
+ default:
+ proto = skb->protocol;
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -3305,6 +3305,9 @@ static int mv88e6xxx_setup_port(struct m
+@@ -3353,6 +3353,9 @@ static int mv88e6xxx_setup_port(struct m
else
reg = 1 << port;
const struct header_ops *header_ops;
unsigned char operstate;
-@@ -2259,6 +2266,10 @@ struct net_device {
+@@ -2257,6 +2264,10 @@ struct net_device {
struct mctp_dev __rcu *mctp_ptr;
#endif
*/
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -3075,6 +3075,10 @@ static inline int pskb_trim(struct sk_bu
+@@ -3080,6 +3080,10 @@ static inline int pskb_trim(struct sk_bu
return (len < skb->len) ? __pskb_trim(skb, len) : 0;
}
/**
* pskb_trim_unique - remove end from a paged unique (not cloned) buffer
* @skb: buffer to alter
-@@ -3240,16 +3244,6 @@ static inline struct sk_buff *dev_alloc_
+@@ -3245,16 +3249,6 @@ static inline struct sk_buff *dev_alloc_
}
{
--- a/net/ethernet/eth.c
+++ b/net/ethernet/eth.c
-@@ -171,6 +171,12 @@ __be16 eth_type_trans(struct sk_buff *sk
+@@ -159,6 +159,12 @@ __be16 eth_type_trans(struct sk_buff *sk
const struct ethhdr *eth;
skb->dev = dev;
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -101,6 +101,29 @@
+@@ -102,6 +102,29 @@
#define AQR107_OP_IN_PROG_SLEEP 1000
#define AQR107_OP_IN_PROG_TIMEOUT 100000
struct aqr107_hw_stat {
const char *name;
int reg;
-@@ -232,6 +255,51 @@ static int aqr_config_aneg(struct phy_de
+@@ -233,6 +256,51 @@ static int aqr_config_aneg(struct phy_de
return genphy_c45_check_and_restart_aneg(phydev, changed);
}
static int aqr_config_intr(struct phy_device *phydev)
{
bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
-@@ -809,7 +877,7 @@ static struct phy_driver aqr_driver[] =
+@@ -810,7 +878,7 @@ static struct phy_driver aqr_driver[] =
PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
.name = "Aquantia AQR112",
.probe = aqr107_probe,
.config_intr = aqr_config_intr,
.handle_interrupt = aqr_handle_interrupt,
.get_tunable = aqr107_get_tunable,
-@@ -827,7 +895,7 @@ static struct phy_driver aqr_driver[] =
+@@ -828,7 +896,7 @@ static struct phy_driver aqr_driver[] =
PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
.name = "Aquantia AQR412",
.probe = aqr107_probe,
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -288,10 +288,16 @@ static int aqr_config_aneg_set_prot(stru
+@@ -289,10 +289,16 @@ static int aqr_config_aneg_set_prot(stru
phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
aquantia_syscfg[if_type].start_rate);
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -29,6 +29,8 @@
- #define PHY_ID_AQR113 0x31c31c40
+@@ -30,6 +30,8 @@
#define PHY_ID_AQR113C 0x31c31c12
+ #define PHY_ID_AQR114C 0x31c31c22
#define PHY_ID_AQR813 0x31c31cb2
+#define PHY_ID_AQR112C 0x03a1b790
+#define PHY_ID_AQR112R 0x31c31d12
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
-@@ -972,6 +974,30 @@ static struct phy_driver aqr_driver[] =
+@@ -992,6 +994,30 @@ static struct phy_driver aqr_driver[] =
.get_stats = aqr107_get_stats,
.link_change_notify = aqr107_link_change_notify,
},
};
module_phy_driver(aqr_driver);
-@@ -991,6 +1017,8 @@ static struct mdio_device_id __maybe_unu
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+@@ -1012,6 +1038,8 @@ static struct mdio_device_id __maybe_unu
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },
#define QUECTEL_VENDOR_ID 0x2c7c
/* These Quectel products use Quectel's vendor ID */
-@@ -1152,6 +1157,11 @@ static const struct usb_device_id option
+@@ -1156,6 +1161,11 @@ static const struct usb_device_id option
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
.driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
/* Quectel products using Qualcomm vendor ID */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1193,6 +1203,11 @@ static const struct usb_device_id option
+@@ -1197,6 +1207,11 @@ static const struct usb_device_id option
.driver_info = ZLP },
{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
.driver_info = RSVD(4) },
+From 9fabf60187f1fa19e6f6bb5441587d485bd534b0 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 9 Apr 2024 17:06:38 +0100
+Subject: [PATCH] rndis_host: add a bunch of USB IDs
+
+Add a bunch of USB IDs found in various places online to the
+RNDIS USB network driver.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/usb/rndis_host.c | 40 ++++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
--- a/drivers/net/usb/rndis_host.c
+++ b/drivers/net/usb/rndis_host.c
@@ -630,6 +630,16 @@ static const struct driver_info zte_rndi
static void sock_def_write_space_wfree(struct sock *sk);
static void sock_def_write_space(struct sock *sk);
-@@ -589,6 +591,21 @@ discard_and_relse:
+@@ -590,6 +592,21 @@ discard_and_relse:
}
EXPORT_SYMBOL(__sk_receive_skb);
INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *,
u32));
INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,
-@@ -2246,9 +2263,11 @@ static void __sk_free(struct sock *sk)
+@@ -2247,9 +2264,11 @@ static void __sk_free(struct sock *sk)
if (likely(sk->sk_net_refcnt))
sock_inuse_add(sock_net(sk), -1);
--- a/net/core/sock.c
+++ b/net/core/sock.c
-@@ -4144,6 +4144,8 @@ static __net_initdata struct pernet_oper
+@@ -4145,6 +4145,8 @@ static __net_initdata struct pernet_oper
static int __init proto_init(void)
{
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
-@@ -1642,7 +1642,7 @@ static void device_links_purge(struct de
+@@ -1657,7 +1657,7 @@ static void device_links_purge(struct de
#define FW_DEVLINK_FLAGS_RPM (FW_DEVLINK_FLAGS_ON | \
DL_FLAG_PM_RUNTIME)
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
-@@ -7620,7 +7620,7 @@ static void __init alloc_node_mem_map(st
+@@ -7622,7 +7622,7 @@ static void __init alloc_node_mem_map(st
if (pgdat == NODE_DATA(0)) {
mem_map = NODE_DATA(0)->node_mem_map;
if (page_to_pfn(mem_map) != pgdat->node_start_pfn)
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
-@@ -204,6 +204,9 @@ static void __br_handle_local_finish(str
+@@ -209,6 +209,9 @@ static void __br_handle_local_finish(str
/* note: already called with rcu_read_lock */
static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb)
{
__br_handle_local_finish(skb);
/* return 1 to signal the okfn() was called so it's ok to use the skb */
-@@ -369,6 +372,17 @@ static rx_handler_result_t br_handle_fra
+@@ -376,6 +379,17 @@ static rx_handler_result_t br_handle_fra
forward:
switch (p->state) {
--- /dev/null
+From 52d14545d2fc276b1bf9ccf48d4612fab6edfb6a Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 6 May 2021 17:49:55 +0200
+Subject: [PATCH] mtd: spi-nor: Add support for BoHong bh25q128as
+
+Add MTD support for the BoHong bh25q128as SPI NOR chip.
+The chip has 16MB of total capacity, divided into a total of 256
+sectors, each 64KB sized. The chip also supports 4KB sectors.
+Additionally, it supports dual and quad read modes.
+
+Functionality was verified on an Tenbay WR1800K / MTK MT7621 board.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/mtd/spi-nor/Makefile | 1 +
+ drivers/mtd/spi-nor/bohong.c | 21 +++++++++++++++++++++
+ drivers/mtd/spi-nor/core.c | 1 +
+ drivers/mtd/spi-nor/core.h | 1 +
+ 4 files changed, 24 insertions(+)
+ create mode 100644 drivers/mtd/spi-nor/bohong.c
+
+--- a/drivers/mtd/spi-nor/Makefile
++++ b/drivers/mtd/spi-nor/Makefile
+@@ -2,6 +2,7 @@
+
+ spi-nor-objs := core.o sfdp.o swp.o otp.o sysfs.o
+ spi-nor-objs += atmel.o
++spi-nor-objs += bohong.o
+ spi-nor-objs += catalyst.o
+ spi-nor-objs += eon.o
+ spi-nor-objs += esmt.o
+--- /dev/null
++++ b/drivers/mtd/spi-nor/bohong.c
+@@ -0,0 +1,21 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2005, Intec Automation Inc.
++ * Copyright (C) 2014, Freescale Semiconductor, Inc.
++ */
++
++#include <linux/mtd/spi-nor.h>
++
++#include "core.h"
++
++static const struct flash_info bohong_parts[] = {
++ /* BoHong Microelectronics */
++ { "bh25q128as", INFO(0x684018, 0, 64 * 1024, 256,
++ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++};
++
++const struct spi_nor_manufacturer spi_nor_bohong = {
++ .name = "bohong",
++ .parts = bohong_parts,
++ .nparts = ARRAY_SIZE(bohong_parts),
++};
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -1844,6 +1844,7 @@ int spi_nor_sr2_bit7_quad_enable(struct
+
+ static const struct spi_nor_manufacturer *manufacturers[] = {
+ &spi_nor_atmel,
++ &spi_nor_bohong,
+ &spi_nor_catalyst,
+ &spi_nor_eon,
+ &spi_nor_esmt,
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -473,6 +473,7 @@ struct sfdp {
+
+ /* Manufacturer drivers. */
+ extern const struct spi_nor_manufacturer spi_nor_atmel;
++extern const struct spi_nor_manufacturer spi_nor_bohong;
+ extern const struct spi_nor_manufacturer spi_nor_catalyst;
+ extern const struct spi_nor_manufacturer spi_nor_eon;
+ extern const struct spi_nor_manufacturer spi_nor_esmt;
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
-@@ -17,6 +17,7 @@ spi-nor-objs += sst.o
+@@ -18,6 +18,7 @@ spi-nor-objs += sst.o
spi-nor-objs += winbond.o
spi-nor-objs += xilinx.o
spi-nor-objs += xmc.o
+};
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
-@@ -1860,6 +1860,7 @@ static const struct spi_nor_manufacturer
+@@ -1861,6 +1861,7 @@ static const struct spi_nor_manufacturer
&spi_nor_winbond,
&spi_nor_xilinx,
&spi_nor_xmc,
static const struct flash_info *
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
-@@ -489,6 +489,7 @@ extern const struct spi_nor_manufacturer
+@@ -490,6 +490,7 @@ extern const struct spi_nor_manufacturer
extern const struct spi_nor_manufacturer spi_nor_winbond;
extern const struct spi_nor_manufacturer spi_nor_xilinx;
extern const struct spi_nor_manufacturer spi_nor_xmc;
for (i = sizeof(struct ipt_entry);
i < e->target_offset;
i += m->u.match_size) {
-@@ -1222,12 +1259,15 @@ compat_copy_entry_to_user(struct ipt_ent
+@@ -1226,12 +1263,15 @@ compat_copy_entry_to_user(struct ipt_ent
compat_uint_t origsize;
const struct xt_entry_match *ematch;
int ret = 0;
/**
* eth_type_trans - determine the packet's protocol ID.
* @skb: received socket data
-@@ -173,6 +185,10 @@ __be16 eth_type_trans(struct sk_buff *sk
- } else {
- skb->pkt_type = PACKET_OTHERHOST;
- }
-+
-+ if (eth_check_local_mask(eth->h_dest, dev->dev_addr,
-+ dev->local_addr_mask))
-+ skb->gro_skip = 1;
- }
+@@ -165,6 +177,10 @@ __be16 eth_type_trans(struct sk_buff *sk
+
+ eth_skb_pkt_type(skb, dev);
++ if (unlikely(!ether_addr_equal_64bits(eth->h_dest, dev->dev_addr)) &&
++ eth_check_local_mask(eth->h_dest, dev->dev_addr, dev->local_addr_mask))
++ skb->gro_skip = 1;
++
/*
+ * Some variants of DSA tagging don't have an ethertype field
+ * at all, so we check here whether one of those tagging
--- a/net/netfilter/nf_flow_table_core.c
+++ b/net/netfilter/nf_flow_table_core.c
-@@ -606,13 +606,41 @@ void nf_flow_table_free(struct nf_flowta
- }
- EXPORT_SYMBOL_GPL(nf_flow_table_free);
+@@ -651,6 +651,23 @@ static struct pernet_operations nf_flow_
+ .exit_batch = nf_flow_table_pernet_exit,
+ };
+static int nf_flow_table_netdev_event(struct notifier_block *this,
+ unsigned long event, void *ptr)
+
static int __init nf_flow_table_module_init(void)
{
-- return nf_flow_table_offload_init();
-+ int ret;
-+
-+ ret = nf_flow_table_offload_init();
-+ if (ret)
-+ return ret;
-+
+ int ret;
+@@ -663,8 +680,14 @@ static int __init nf_flow_table_module_i
+ if (ret)
+ goto out_offload;
+
+ ret = register_netdevice_notifier(&flow_offload_netdev_notifier);
+ if (ret)
-+ nf_flow_table_offload_exit();
++ goto out_offload_init;
+
-+ return ret;
- }
+ return 0;
+
++out_offload_init:
++ nf_flow_table_offload_exit();
+ out_offload:
+ unregister_pernet_subsys(&nf_flow_table_net_ops);
+ return ret;
+@@ -672,6 +695,7 @@ out_offload:
static void __exit nf_flow_table_module_exit(void)
{
+ unregister_netdevice_notifier(&flow_offload_netdev_notifier);
nf_flow_table_offload_exit();
+ unregister_pernet_subsys(&nf_flow_table_net_ops);
}
-
--- a/net/netfilter/nft_flow_offload.c
+++ b/net/netfilter/nft_flow_offload.c
@@ -455,47 +455,14 @@ static struct nft_expr_type nft_flow_off
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
-@@ -7770,7 +7770,7 @@ static int nft_register_flowtable_net_ho
+@@ -7811,7 +7811,7 @@ static int nft_register_flowtable_net_ho
err = flowtable->data.type->setup(&flowtable->data,
hook->ops.dev,
FLOW_BLOCK_BIND);
if (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev)
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
-@@ -326,6 +326,8 @@ static rx_handler_result_t br_handle_fra
+@@ -331,6 +331,8 @@ static rx_handler_result_t br_handle_fra
fwd_mask |= p->group_fwd_mask;
switch (dest[5]) {
case 0x00: /* Bridge Group Address */
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2467,7 +2467,7 @@ mt7531_setup(struct dsa_switch *ds)
- struct mt7530_priv *priv = ds->priv;
- struct mt7530_dummy_poll p;
- u32 val, id;
-- int ret;
-+ int ret, i;
-
- /* Reset whole chip through gpio pin or memory-mapped registers for
- * different type of hardware
-@@ -2499,6 +2499,10 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2680,6 +2680,10 @@ mt7531_setup(struct dsa_switch *ds)
return -ENODEV;
}
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
-@@ -744,6 +744,38 @@ static int rtl8226_match_phy_device(stru
+@@ -79,6 +79,7 @@
+ #define RTLGEN_SPEED_MASK 0x0630
+
+ #define RTL_GENERIC_PHYID 0x001cc800
++#define RTL_8221B_VB_CG_PHYID 0x001cc849
+
+ MODULE_DESCRIPTION("Realtek PHY driver");
+ MODULE_AUTHOR("Johnson Leung");
+@@ -744,6 +745,38 @@ static int rtl8226_match_phy_device(stru
rtlgen_supports_2_5gbps(phydev);
}
+ id |= val;
+ }
+
-+ return (id == 0x001cc849);
++ return (id == RTL_8221B_VB_CG_PHYID);
+}
+
static int rtl822x_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
-@@ -1082,7 +1114,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1082,7 +1115,7 @@ static struct phy_driver realtek_drvs[]
.write_page = rtl821x_write_page,
.soft_reset = genphy_soft_reset,
}, {
+From d7943c31d57c11e1a517aa3ce2006fca44866870 Mon Sep 17 00:00:00 2001
+From: Jianhui Zhao <zhaojh329@gmail.com>
+Date: Sun, 24 Sep 2023 22:15:00 +0800
+Subject: [PATCH] net: phy: realtek: add interrupt support for RTL8221B
+
+This commit introduces interrupt support for RTL8221B.
+
+Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
+---
+ drivers/net/phy/realtek.c | 47 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
-@@ -971,6 +971,51 @@ static int rtl8221b_config_init(struct p
+@@ -972,6 +972,51 @@ static int rtl8221b_config_init(struct p
return 0;
}
static struct phy_driver realtek_drvs[] = {
{
PHY_ID_MATCH_EXACT(0x00008201),
-@@ -1119,6 +1164,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1120,6 +1165,8 @@ static struct phy_driver realtek_drvs[]
.get_features = rtl822x_get_features,
.config_init = rtl8221b_config_init,
.config_aneg = rtl822x_config_aneg,
--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
-@@ -4359,6 +4359,15 @@ int skb_gro_receive(struct sk_buff *p, s
+@@ -4360,6 +4360,15 @@ int skb_gro_receive(struct sk_buff *p, s
if (unlikely(p->len + len >= 65536 || NAPI_GRO_CB(skb)->flush))
return -E2BIG;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2174,10 +2174,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+@@ -2356,10 +2356,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr
{
struct dsa_switch *ds = priv->ds;
struct device *dev = priv->dev;
bus = devm_mdiobus_alloc(dev);
if (!bus)
return -ENOMEM;
-@@ -2194,7 +2197,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+@@ -2376,7 +2379,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr
if (priv->irq)
mt7530_setup_mdio_irq(priv);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2877,8 +2877,7 @@ static void mt753x_phylink_mac_link_up(s
+@@ -3065,8 +3065,7 @@ static void mt753x_phylink_mac_link_up(s
/* MT753x MAC works in 1G full duplex mode for all up-clocked
* variants.
*/
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
-@@ -206,6 +206,7 @@ static void quirk_mmio_always_on(struct
+@@ -207,6 +207,7 @@ static void quirk_mmio_always_on(struct
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
/*
* The Mellanox Tavor device gives false positive parity errors. Disable
* parity error reporting.
-@@ -3368,6 +3369,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
+@@ -3369,6 +3370,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
/*
* Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
* To work around this, query the size it should be configured to by the
-@@ -3393,6 +3396,8 @@ static void quirk_intel_ntb(struct pci_d
+@@ -3394,6 +3397,8 @@ static void quirk_intel_ntb(struct pci_d
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
/*
* Some BIOS implementations leave the Intel GPU interrupts enabled, even
* though no one is handling them (e.g., if the i915 driver is never
-@@ -3431,6 +3436,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
+@@ -3432,6 +3437,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
--- /dev/null
+From 38eb5b3370c29515d2ce92adac2d6eba96f276f5 Mon Sep 17 00:00:00 2001
+From: INAGAKI Hiroshi <musashino.open@gmail.com>
+Date: Wed, 20 Mar 2024 15:32:18 +0900
+Subject: [PATCH v2 1/2] dt-bindings: leds: add LED_FUNCTION_MOBILE for mobile
+ network
+
+Add LED_FUNCTION_MOBILE for LEDs that indicate status of mobile network
+connection. This is useful to distinguish those LEDs from LEDs that
+indicates status of wired "wan" connection.
+
+example (on stock fw):
+
+IIJ SA-W2 has "Mobile" LEDs that indicate status (no signal, too low,
+low, good) of mobile network connection via dongle connected to USB
+port.
+
+- no signal: (none, turned off)
+- too low: green:mobile & red:mobile (amber, blink)
+- low: green:mobile & red:mobile (amber, turned on)
+- good: green:mobile (turned on)
+
+Suggested-by: Hauke Mehrtens <hauke@hauke-m.de>
+Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
+---
+ include/dt-bindings/leds/common.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/include/dt-bindings/leds/common.h
++++ b/include/dt-bindings/leds/common.h
+@@ -83,6 +83,7 @@
+ #define LED_FUNCTION_INDICATOR "indicator"
+ #define LED_FUNCTION_LAN "lan"
+ #define LED_FUNCTION_MAIL "mail"
++#define LED_FUNCTION_MOBILE "mobile"
+ #define LED_FUNCTION_MTD "mtd"
+ #define LED_FUNCTION_PANIC "panic"
+ #define LED_FUNCTION_PROGRAMMING "programming"
--- /dev/null
+From e22afe910afcfb51b6ba6a0ae776939959727f54 Mon Sep 17 00:00:00 2001
+From: INAGAKI Hiroshi <musashino.open@gmail.com>
+Date: Wed, 20 Mar 2024 15:59:06 +0900
+Subject: [PATCH v2 2/2] dt-bindings: leds: add LED_FUNCTION_SPEED_* for link
+ speed on LAN/WAN
+
+Add LED_FUNCTION_SPEED_LAN and LED_FUNCTION_SPEED_WAN for LEDs that
+indicate link speed of ethernet ports on LAN/WAN. This is useful to
+distinguish those LEDs from LEDs that indicate link status (up/down).
+
+example:
+
+Fortinet FortiGate 30E/50E have LEDs that indicate link speed on each
+of the ethernet ports in addition to LEDs that indicate link status
+(up/down).
+
+- 1000 Mbps: green:speed-(lan|wan)-N
+- 100 Mbps: amber:speed-(lan|wan)-N
+- 10 Mbps: (none, turned off)
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
+---
+ include/dt-bindings/leds/common.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/dt-bindings/leds/common.h
++++ b/include/dt-bindings/leds/common.h
+@@ -89,6 +89,8 @@
+ #define LED_FUNCTION_PROGRAMMING "programming"
+ #define LED_FUNCTION_RX "rx"
+ #define LED_FUNCTION_SD "sd"
++#define LED_FUNCTION_SPEED_LAN "speed-lan"
++#define LED_FUNCTION_SPEED_WAN "speed-wan"
+ #define LED_FUNCTION_STANDBY "standby"
+ #define LED_FUNCTION_TORCH "torch"
+ #define LED_FUNCTION_TX "tx"
/*
* We need to store the untouched command line for future reference.
* We also need to store the touched command line since the parameter
-@@ -958,6 +981,7 @@ asmlinkage __visible void __init __no_sa
+@@ -960,6 +983,7 @@ asmlinkage __visible void __init __no_sa
pr_notice("%s", linux_banner);
early_security_init();
setup_arch(&command_line);
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
-@@ -7897,7 +7897,7 @@ static void __init alloc_node_mem_map(st
+@@ -7899,7 +7899,7 @@ static void __init alloc_node_mem_map(st
if (pgdat == NODE_DATA(0)) {
mem_map = NODE_DATA(0)->node_mem_map;
if (page_to_pfn(mem_map) != pgdat->node_start_pfn)
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
-@@ -222,6 +222,9 @@ static void __br_handle_local_finish(str
+@@ -227,6 +227,9 @@ static void __br_handle_local_finish(str
/* note: already called with rcu_read_lock */
static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb)
{
__br_handle_local_finish(skb);
/* return 1 to signal the okfn() was called so it's ok to use the skb */
-@@ -390,6 +393,17 @@ forward:
+@@ -397,6 +400,17 @@ forward:
goto defer_stp_filtering;
switch (p->state) {
--- /dev/null
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Wed, 13 Mar 2024 20:28:37 +0800
+Subject: [PATCH] mips: kernel: fix detect_memory_region() function
+
+1. Do not use memcmp() on unallocated memory, as the new introduced
+ fortify dynamic object size check[1] will report unexpected result.
+2. Use a fixed pattern instead of a random function pointer as the
+ magic value.
+3. Flip magic value and double check it.
+4. Enable this feature only for 32-bit CPUs. Currently, only ath79 and
+ ralink CPUs are using it.
+
+[1] 439a1bcac648 ("fortify: Use __builtin_dynamic_object_size() when available")
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ arch/mips/include/asm/bootinfo.h | 2 ++
+ arch/mips/kernel/setup.c | 17 ++++++++++++-----
+ 2 files changed, 14 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/include/asm/bootinfo.h
++++ b/arch/mips/include/asm/bootinfo.h
+@@ -93,7 +93,9 @@ const char *get_system_type(void);
+
+ extern unsigned long mips_machtype;
+
++#ifndef CONFIG_64BIT
+ extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max);
++#endif
+
+ extern void prom_init(void);
+ extern void prom_free_prom_memory(void);
+--- a/arch/mips/kernel/setup.c
++++ b/arch/mips/kernel/setup.c
+@@ -90,21 +90,27 @@ static struct resource bss_resource = {
+ unsigned long __kaslr_offset __ro_after_init;
+ EXPORT_SYMBOL(__kaslr_offset);
+
+-static void *detect_magic __initdata = detect_memory_region;
+-
+ #ifdef CONFIG_MIPS_AUTO_PFN_OFFSET
+ unsigned long ARCH_PFN_OFFSET;
+ EXPORT_SYMBOL(ARCH_PFN_OFFSET);
+ #endif
+
++#ifndef CONFIG_64BIT
++static u32 detect_magic __initdata;
++#define MIPS_MEM_TEST_PATTERN 0xaa5555aa
++
+ void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max)
+ {
+- void *dm = &detect_magic;
++ void *dm = (void *)KSEG1ADDR(&detect_magic);
+ phys_addr_t size;
+
+ for (size = sz_min; size < sz_max; size <<= 1) {
+- if (!memcmp(dm, dm + size, sizeof(detect_magic)))
+- break;
++ __raw_writel(MIPS_MEM_TEST_PATTERN, dm);
++ if (__raw_readl(dm) == __raw_readl(dm + size)) {
++ __raw_writel(~MIPS_MEM_TEST_PATTERN, dm);
++ if (__raw_readl(dm) == __raw_readl(dm + size))
++ break;
++ }
+ }
+
+ pr_debug("Memory: %lluMB of RAM detected at 0x%llx (min: %lluMB, max: %lluMB)\n",
+@@ -115,6 +121,7 @@ void __init detect_memory_region(phys_ad
+
+ memblock_add(start, size);
+ }
++#endif /* CONFIG_64BIT */
+
+ /*
+ * Manage initrd
return !!nor->params->erase_map.uniform_erase_type;
}
-@@ -2158,6 +2160,7 @@ static int spi_nor_select_erase(struct s
+@@ -2180,6 +2182,7 @@ static int spi_nor_select_erase(struct s
{
struct spi_nor_erase_map *map = &nor->params->erase_map;
const struct spi_nor_erase_type *erase = NULL;
struct mtd_info *mtd = &nor->mtd;
u32 wanted_size = nor->info->sector_size;
int i;
-@@ -2190,8 +2193,9 @@ static int spi_nor_select_erase(struct s
+@@ -2212,8 +2215,9 @@ static int spi_nor_select_erase(struct s
*/
for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
if (map->erase_type[i].size) {
}
}
-@@ -2199,6 +2203,9 @@ static int spi_nor_select_erase(struct s
+@@ -2221,6 +2225,9 @@ static int spi_nor_select_erase(struct s
return -EINVAL;
mtd->erasesize = erase->size;
--- a/drivers/mmc/core/block.c
+++ b/drivers/mmc/core/block.c
-@@ -2484,6 +2484,8 @@ static struct mmc_blk_data *mmc_blk_allo
+@@ -2486,6 +2486,8 @@ static struct mmc_blk_data *mmc_blk_allo
int area_type,
unsigned int part_type)
{
struct mmc_blk_data *md;
int devidx, ret;
char cap_str[10];
-@@ -2580,6 +2582,13 @@ static struct mmc_blk_data *mmc_blk_allo
+@@ -2582,6 +2584,13 @@ static struct mmc_blk_data *mmc_blk_allo
blk_queue_write_cache(md->queue.queue, cache_enabled, fua_enabled);
--- a/drivers/mmc/core/block.c
+++ b/drivers/mmc/core/block.c
-@@ -2538,6 +2538,7 @@ static struct mmc_blk_data *mmc_blk_allo
+@@ -2540,6 +2540,7 @@ static struct mmc_blk_data *mmc_blk_allo
md->disk->major = MMC_BLOCK_MAJOR;
md->disk->minors = perdev_minors;
md->disk->first_minor = devidx * perdev_minors;
+ &spi_nor_xtx,
};
- static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
+ static const struct flash_info spi_nor_generic_flash = {
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -633,6 +633,7 @@ extern const struct spi_nor_manufacturer
for (i = sizeof(struct ipt_entry);
i < e->target_offset;
i += m->u.match_size) {
-@@ -1223,12 +1260,15 @@ compat_copy_entry_to_user(struct ipt_ent
+@@ -1227,12 +1264,15 @@ compat_copy_entry_to_user(struct ipt_ent
compat_uint_t origsize;
const struct xt_entry_match *ematch;
int ret = 0;
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -3006,7 +3006,7 @@ static inline int pskb_network_may_pull(
+@@ -3012,7 +3012,7 @@ static inline int pskb_network_may_pull(
* NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8)
*/
#ifndef NET_SKB_PAD
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Subject: net: replace GRO optimization patch with a new one that supports VLANs/bridges with different MAC addresses
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
- include/linux/netdevice.h | 2 ++
- include/linux/skbuff.h | 3 ++-
- net/core/dev.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++
- net/ethernet/eth.c | 18 +++++++++++++++++-
- 4 files changed, 69 insertions(+), 2 deletions(-)
-
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -2157,6 +2157,8 @@ struct net_device {
- struct netdev_hw_addr_list mc;
- struct netdev_hw_addr_list dev_addrs;
-
-+ unsigned char local_addr_mask[MAX_ADDR_LEN];
-+
- #ifdef CONFIG_SYSFS
- struct kset *queues_kset;
- #endif
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -972,6 +972,7 @@ struct sk_buff {
- #ifdef CONFIG_IPV6_NDISC_NODETYPE
- __u8 ndisc_nodetype:2;
- #endif
-+ __u8 gro_skip:1;
-
- __u8 ipvs_property:1;
- __u8 inner_protocol_type:1;
---- a/net/core/gro.c
-+++ b/net/core/gro.c
-@@ -491,6 +491,9 @@ static enum gro_result dev_gro_receive(s
- int same_flow;
- int grow;
-
-+ if (skb->gro_skip)
-+ goto normal;
-+
- if (netif_elide_gro(skb->dev))
- goto normal;
-
---- a/net/core/dev.c
-+++ b/net/core/dev.c
-@@ -7625,6 +7625,48 @@ static void __netdev_adjacent_dev_unlink
- &upper_dev->adj_list.lower);
- }
-
-+static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr,
-+ struct net_device *dev)
-+{
-+ int i;
-+
-+ for (i = 0; i < dev->addr_len; i++)
-+ mask[i] |= addr[i] ^ dev->dev_addr[i];
-+}
-+
-+static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev,
-+ struct net_device *lower)
-+{
-+ struct net_device *cur;
-+ struct list_head *iter;
-+
-+ netdev_for_each_upper_dev_rcu(dev, cur, iter) {
-+ __netdev_addr_mask(mask, cur->dev_addr, lower);
-+ __netdev_upper_mask(mask, cur, lower);
-+ }
-+}
-+
-+static void __netdev_update_addr_mask(struct net_device *dev)
-+{
-+ unsigned char mask[MAX_ADDR_LEN];
-+ struct net_device *cur;
-+ struct list_head *iter;
-+
-+ memset(mask, 0, sizeof(mask));
-+ __netdev_upper_mask(mask, dev, dev);
-+ memcpy(dev->local_addr_mask, mask, dev->addr_len);
-+
-+ netdev_for_each_lower_dev(dev, cur, iter)
-+ __netdev_update_addr_mask(cur);
-+}
-+
-+static void netdev_update_addr_mask(struct net_device *dev)
-+{
-+ rcu_read_lock();
-+ __netdev_update_addr_mask(dev);
-+ rcu_read_unlock();
-+}
-+
- static int __netdev_upper_dev_link(struct net_device *dev,
- struct net_device *upper_dev, bool master,
- void *upper_priv, void *upper_info,
-@@ -7676,6 +7718,7 @@ static int __netdev_upper_dev_link(struc
- if (ret)
- return ret;
-
-+ netdev_update_addr_mask(dev);
- ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- &changeupper_info.info);
- ret = notifier_to_errno(ret);
-@@ -7772,6 +7815,7 @@ static void __netdev_upper_dev_unlink(st
-
- __netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
-
-+ netdev_update_addr_mask(dev);
- call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- &changeupper_info.info);
-
-@@ -8824,6 +8868,7 @@ int dev_set_mac_address(struct net_devic
- if (err)
- return err;
- dev->addr_assign_type = NET_ADDR_SET;
-+ netdev_update_addr_mask(dev);
- call_netdevice_notifiers(NETDEV_CHANGEADDR, dev);
- add_device_randomness(dev->dev_addr, dev->addr_len);
- return 0;
---- a/net/ethernet/eth.c
-+++ b/net/ethernet/eth.c
-@@ -143,6 +143,18 @@ u32 eth_get_headlen(const struct net_dev
- }
- EXPORT_SYMBOL(eth_get_headlen);
-
-+static inline bool
-+eth_check_local_mask(const void *addr1, const void *addr2, const void *mask)
-+{
-+ const u16 *a1 = addr1;
-+ const u16 *a2 = addr2;
-+ const u16 *m = mask;
-+
-+ return (((a1[0] ^ a2[0]) & ~m[0]) |
-+ ((a1[1] ^ a2[1]) & ~m[1]) |
-+ ((a1[2] ^ a2[2]) & ~m[2]));
-+}
-+
- /**
- * eth_type_trans - determine the packet's protocol ID.
- * @skb: received socket data
-@@ -174,6 +186,10 @@ __be16 eth_type_trans(struct sk_buff *sk
- } else {
- skb->pkt_type = PACKET_OTHERHOST;
- }
-+
-+ if (eth_check_local_mask(eth->h_dest, dev->dev_addr,
-+ dev->local_addr_mask))
-+ skb->gro_skip = 1;
- }
-
- /*
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 11:23:03 +0200
+Subject: [PATCH] net: add TCP fraglist GRO support
+
+When forwarding TCP after GRO, software segmentation is very expensive,
+especially when the checksum needs to be recalculated.
+One case where that's currently unavoidable is when routing packets over
+PPPoE. Performance improves significantly when using fraglist GRO
+implemented in the same way as for UDP.
+
+Here's a measurement of running 2 TCP streams through a MediaTek MT7622
+device (2-core Cortex-A53), which runs NAT with flow offload enabled from
+one ethernet port to PPPoE on another ethernet port + cake qdisc set to
+1Gbps.
+
+rx-gro-list off: 630 Mbit/s, CPU 35% idle
+rx-gro-list on: 770 Mbit/s, CPU 40% idle
+
+Signe-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/net/gro.h
++++ b/include/net/gro.h
+@@ -424,6 +424,7 @@ static inline __wsum ip6_gro_compute_pse
+ }
+
+ int skb_gro_receive(struct sk_buff *p, struct sk_buff *skb);
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb);
+
+ /* Pass the currently batched GRO_NORMAL SKBs up to the stack. */
+ static inline void gro_normal_list(struct napi_struct *napi)
+@@ -446,5 +447,48 @@ static inline void gro_normal_one(struct
+ gro_normal_list(napi);
+ }
+
++/* This function is the alternative of 'inet_iif' and 'inet_sdif'
++ * functions in case we can not rely on fields of IPCB.
++ *
++ * The caller must verify skb_valid_dst(skb) is false and skb->dev is initialized.
++ * The caller must hold the RCU read lock.
++ */
++static inline void inet_get_iif_sdif(const struct sk_buff *skb, int *iif, int *sdif)
++{
++ *iif = inet_iif(skb) ?: skb->dev->ifindex;
++ *sdif = 0;
++
++#if IS_ENABLED(CONFIG_NET_L3_MASTER_DEV)
++ if (netif_is_l3_slave(skb->dev)) {
++ struct net_device *master = netdev_master_upper_dev_get_rcu(skb->dev);
++
++ *sdif = *iif;
++ *iif = master ? master->ifindex : 0;
++ }
++#endif
++}
++
++/* This function is the alternative of 'inet6_iif' and 'inet6_sdif'
++ * functions in case we can not rely on fields of IP6CB.
++ *
++ * The caller must verify skb_valid_dst(skb) is false and skb->dev is initialized.
++ * The caller must hold the RCU read lock.
++ */
++static inline void inet6_get_iif_sdif(const struct sk_buff *skb, int *iif, int *sdif)
++{
++ /* using skb->dev->ifindex because skb_dst(skb) is not initialized */
++ *iif = skb->dev->ifindex;
++ *sdif = 0;
++
++#if IS_ENABLED(CONFIG_NET_L3_MASTER_DEV)
++ if (netif_is_l3_slave(skb->dev)) {
++ struct net_device *master = netdev_master_upper_dev_get_rcu(skb->dev);
++
++ *sdif = *iif;
++ *iif = master ? master->ifindex : 0;
++ }
++#endif
++}
++
+
+ #endif /* _NET_IPV6_GRO_H */
+--- a/include/net/tcp.h
++++ b/include/net/tcp.h
+@@ -2057,7 +2057,10 @@ void tcp_v4_destroy_sock(struct sock *sk
+
+ struct sk_buff *tcp_gso_segment(struct sk_buff *skb,
+ netdev_features_t features);
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb);
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb);
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th);
+ INDIRECT_CALLABLE_DECLARE(int tcp4_gro_complete(struct sk_buff *skb, int thoff));
+ INDIRECT_CALLABLE_DECLARE(struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb));
+ INDIRECT_CALLABLE_DECLARE(int tcp6_gro_complete(struct sk_buff *skb, int thoff));
+--- a/net/core/gro.c
++++ b/net/core/gro.c
+@@ -290,6 +290,33 @@ done:
+ return 0;
+ }
+
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
++{
++ if (unlikely(p->len + skb->len >= 65536))
++ return -E2BIG;
++
++ if (NAPI_GRO_CB(p)->last == p)
++ skb_shinfo(p)->frag_list = skb;
++ else
++ NAPI_GRO_CB(p)->last->next = skb;
++
++ skb_pull(skb, skb_gro_offset(skb));
++
++ NAPI_GRO_CB(p)->last = skb;
++ NAPI_GRO_CB(p)->count++;
++ p->data_len += skb->len;
++
++ /* sk ownership - if any - completely transferred to the aggregated packet */
++ skb->destructor = NULL;
++ skb->sk = NULL;
++ p->truesize += skb->truesize;
++ p->len += skb->len;
++
++ NAPI_GRO_CB(skb)->same_flow = 1;
++
++ return 0;
++}
++
+
+ static void napi_gro_complete(struct napi_struct *napi, struct sk_buff *skb)
+ {
+--- a/net/ipv4/tcp_offload.c
++++ b/net/ipv4/tcp_offload.c
+@@ -27,6 +27,70 @@ static void tcp_gso_tstamp(struct sk_buf
+ }
+ }
+
++static void __tcpv4_gso_segment_csum(struct sk_buff *seg,
++ __be32 *oldip, __be32 newip,
++ __be16 *oldport, __be16 newport)
++{
++ struct tcphdr *th;
++ struct iphdr *iph;
++
++ if (*oldip == newip && *oldport == newport)
++ return;
++
++ th = tcp_hdr(seg);
++ iph = ip_hdr(seg);
++
++ inet_proto_csum_replace4(&th->check, seg, *oldip, newip, true);
++ inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++ *oldport = newport;
++
++ csum_replace4(&iph->check, *oldip, newip);
++ *oldip = newip;
++}
++
++static struct sk_buff *__tcpv4_gso_segment_list_csum(struct sk_buff *segs)
++{
++ const struct tcphdr *th;
++ const struct iphdr *iph;
++ struct sk_buff *seg;
++ struct tcphdr *th2;
++ struct iphdr *iph2;
++
++ seg = segs;
++ th = tcp_hdr(seg);
++ iph = ip_hdr(seg);
++ th2 = tcp_hdr(seg->next);
++ iph2 = ip_hdr(seg->next);
++
++ if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++ iph->daddr == iph2->daddr && iph->saddr == iph2->saddr)
++ return segs;
++
++ while ((seg = seg->next)) {
++ th2 = tcp_hdr(seg);
++ iph2 = ip_hdr(seg);
++
++ __tcpv4_gso_segment_csum(seg,
++ &iph2->saddr, iph->saddr,
++ &th2->source, th->source);
++ __tcpv4_gso_segment_csum(seg,
++ &iph2->daddr, iph->daddr,
++ &th2->dest, th->dest);
++ }
++
++ return segs;
++}
++
++static struct sk_buff *__tcp4_gso_segment_list(struct sk_buff *skb,
++ netdev_features_t features)
++{
++ skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++ if (IS_ERR(skb))
++ return skb;
++
++ return __tcpv4_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp4_gso_segment(struct sk_buff *skb,
+ netdev_features_t features)
+ {
+@@ -36,6 +100,9 @@ static struct sk_buff *tcp4_gso_segment(
+ if (!pskb_may_pull(skb, sizeof(struct tcphdr)))
+ return ERR_PTR(-EINVAL);
+
++ if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++ return __tcp4_gso_segment_list(skb, features);
++
+ if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ const struct iphdr *iph = ip_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+@@ -177,61 +244,76 @@ out:
+ return segs;
+ }
+
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb)
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th)
+ {
+- struct sk_buff *pp = NULL;
++ struct tcphdr *th2;
+ struct sk_buff *p;
++
++ list_for_each_entry(p, head, list) {
++ if (!NAPI_GRO_CB(p)->same_flow)
++ continue;
++
++ th2 = tcp_hdr(p);
++ if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
++ NAPI_GRO_CB(p)->same_flow = 0;
++ continue;
++ }
++
++ return p;
++ }
++
++ return NULL;
++}
++
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb)
++{
++ unsigned int thlen, hlen, off;
+ struct tcphdr *th;
+- struct tcphdr *th2;
+- unsigned int len;
+- unsigned int thlen;
+- __be32 flags;
+- unsigned int mss = 1;
+- unsigned int hlen;
+- unsigned int off;
+- int flush = 1;
+- int i;
+
+ off = skb_gro_offset(skb);
+ hlen = off + sizeof(*th);
+ th = skb_gro_header(skb, hlen, off);
+ if (unlikely(!th))
+- goto out;
++ return NULL;
+
+ thlen = th->doff * 4;
+ if (thlen < sizeof(*th))
+- goto out;
++ return NULL;
+
+ hlen = off + thlen;
+ if (skb_gro_header_hard(skb, hlen)) {
+ th = skb_gro_header_slow(skb, hlen, off);
+ if (unlikely(!th))
+- goto out;
++ return NULL;
+ }
+
+ skb_gro_pull(skb, thlen);
+
+- len = skb_gro_len(skb);
+- flags = tcp_flag_word(th);
+-
+- list_for_each_entry(p, head, list) {
+- if (!NAPI_GRO_CB(p)->same_flow)
+- continue;
++ return th;
++}
+
+- th2 = tcp_hdr(p);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++ unsigned int thlen = th->doff * 4;
++ struct sk_buff *pp = NULL;
++ struct sk_buff *p;
++ struct tcphdr *th2;
++ unsigned int len;
++ __be32 flags;
++ unsigned int mss = 1;
++ int flush = 1;
++ int i;
+
+- if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
+- NAPI_GRO_CB(p)->same_flow = 0;
+- continue;
+- }
++ len = skb_gro_len(skb);
++ flags = tcp_flag_word(th);
+
+- goto found;
+- }
+- p = NULL;
+- goto out_check_final;
++ p = tcp_gro_lookup(head, th);
++ if (!p)
++ goto out_check_final;
+
+-found:
+ /* Include the IP ID check below from the inner most IP hdr */
++ th2 = tcp_hdr(p);
+ flush = NAPI_GRO_CB(p)->flush;
+ flush |= (__force int)(flags & TCP_FLAG_CWR);
+ flush |= (__force int)((flags ^ tcp_flag_word(th2)) &
+@@ -268,6 +350,19 @@ found:
+ flush |= p->decrypted ^ skb->decrypted;
+ #endif
+
++ if (unlikely(NAPI_GRO_CB(p)->is_flist)) {
++ flush |= (__force int)(flags ^ tcp_flag_word(th2));
++ flush |= skb->ip_summed != p->ip_summed;
++ flush |= skb->csum_level != p->csum_level;
++ flush |= !pskb_may_pull(skb, skb_gro_offset(skb));
++ flush |= NAPI_GRO_CB(p)->count >= 64;
++
++ if (flush || skb_gro_receive_list(p, skb))
++ mss = 1;
++
++ goto out_check_final;
++ }
++
+ if (flush || skb_gro_receive(p, skb)) {
+ mss = 1;
+ goto out_check_final;
+@@ -289,7 +384,6 @@ out_check_final:
+ if (p && (!NAPI_GRO_CB(skb)->same_flow || flush))
+ pp = p;
+
+-out:
+ NAPI_GRO_CB(skb)->flush |= (flush != 0);
+
+ return pp;
+@@ -315,18 +409,58 @@ int tcp_gro_complete(struct sk_buff *skb
+ }
+ EXPORT_SYMBOL(tcp_gro_complete);
+
++static void tcp4_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++ const struct iphdr *iph;
++ struct sk_buff *p;
++ struct sock *sk;
++ struct net *net;
++ int iif, sdif;
++
++ if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++ return;
++
++ p = tcp_gro_lookup(head, th);
++ if (p) {
++ NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++ return;
++ }
++
++ inet_get_iif_sdif(skb, &iif, &sdif);
++ iph = skb_gro_network_header(skb);
++ net = dev_net(skb->dev);
++ sk = __inet_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++ iph->saddr, th->source,
++ iph->daddr, ntohs(th->dest),
++ iif, sdif);
++ NAPI_GRO_CB(skb)->is_flist = !sk;
++ if (sk)
++ sock_put(sk);
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++ struct tcphdr *th;
++
+ /* Don't bother verifying checksum if we're going to flush anyway. */
+ if (!NAPI_GRO_CB(skb)->flush &&
+ skb_gro_checksum_validate(skb, IPPROTO_TCP,
+- inet_gro_compute_pseudo)) {
+- NAPI_GRO_CB(skb)->flush = 1;
+- return NULL;
+- }
++ inet_gro_compute_pseudo))
++ goto flush;
++
++ th = tcp_gro_pull_header(skb);
++ if (!th)
++ goto flush;
+
+- return tcp_gro_receive(head, skb);
++ tcp4_check_fraglist_gro(head, skb, th);
++
++ return tcp_gro_receive(head, skb, th);
++
++flush:
++ NAPI_GRO_CB(skb)->flush = 1;
++ return NULL;
+ }
+
+ INDIRECT_CALLABLE_SCOPE int tcp4_gro_complete(struct sk_buff *skb, int thoff)
+@@ -334,6 +468,15 @@ INDIRECT_CALLABLE_SCOPE int tcp4_gro_com
+ const struct iphdr *iph = ip_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+
++ if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++ skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV4;
++ skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++ __skb_incr_checksum_unnecessary(skb);
++
++ return 0;
++ }
++
+ th->check = ~tcp_v4_check(skb->len - thoff, iph->saddr,
+ iph->daddr, 0);
+ skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV4;
+--- a/net/ipv4/udp_offload.c
++++ b/net/ipv4/udp_offload.c
+@@ -425,33 +425,6 @@ out:
+ return segs;
+ }
+
+-static int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
+-{
+- if (unlikely(p->len + skb->len >= 65536))
+- return -E2BIG;
+-
+- if (NAPI_GRO_CB(p)->last == p)
+- skb_shinfo(p)->frag_list = skb;
+- else
+- NAPI_GRO_CB(p)->last->next = skb;
+-
+- skb_pull(skb, skb_gro_offset(skb));
+-
+- NAPI_GRO_CB(p)->last = skb;
+- NAPI_GRO_CB(p)->count++;
+- p->data_len += skb->len;
+-
+- /* sk ownership - if any - completely transferred to the aggregated packet */
+- skb->destructor = NULL;
+- skb->sk = NULL;
+- p->truesize += skb->truesize;
+- p->len += skb->len;
+-
+- NAPI_GRO_CB(skb)->same_flow = 1;
+-
+- return 0;
+-}
+-
+
+ #define UDP_GRO_CNT_MAX 64
+ static struct sk_buff *udp_gro_receive_segment(struct list_head *head,
+--- a/net/ipv6/tcpv6_offload.c
++++ b/net/ipv6/tcpv6_offload.c
+@@ -7,24 +7,67 @@
+ */
+ #include <linux/indirect_call_wrapper.h>
+ #include <linux/skbuff.h>
++#include <net/inet6_hashtables.h>
+ #include <net/gro.h>
+ #include <net/protocol.h>
+ #include <net/tcp.h>
+ #include <net/ip6_checksum.h>
+ #include "ip6_offload.h"
+
++static void tcp6_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++#if IS_ENABLED(CONFIG_IPV6)
++ const struct ipv6hdr *hdr;
++ struct sk_buff *p;
++ struct sock *sk;
++ struct net *net;
++ int iif, sdif;
++
++ if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++ return;
++
++ p = tcp_gro_lookup(head, th);
++ if (p) {
++ NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++ return;
++ }
++
++ inet6_get_iif_sdif(skb, &iif, &sdif);
++ hdr = skb_gro_network_header(skb);
++ net = dev_net(skb->dev);
++ sk = __inet6_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++ &hdr->saddr, th->source,
++ &hdr->daddr, ntohs(th->dest),
++ iif, sdif);
++ NAPI_GRO_CB(skb)->is_flist = !sk;
++ if (sk)
++ sock_put(sk);
++#endif /* IS_ENABLED(CONFIG_IPV6) */
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp6_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++ struct tcphdr *th;
++
+ /* Don't bother verifying checksum if we're going to flush anyway. */
+ if (!NAPI_GRO_CB(skb)->flush &&
+ skb_gro_checksum_validate(skb, IPPROTO_TCP,
+- ip6_gro_compute_pseudo)) {
+- NAPI_GRO_CB(skb)->flush = 1;
+- return NULL;
+- }
++ ip6_gro_compute_pseudo))
++ goto flush;
+
+- return tcp_gro_receive(head, skb);
++ th = tcp_gro_pull_header(skb);
++ if (!th)
++ goto flush;
++
++ tcp6_check_fraglist_gro(head, skb, th);
++
++ return tcp_gro_receive(head, skb, th);
++
++flush:
++ NAPI_GRO_CB(skb)->flush = 1;
++ return NULL;
+ }
+
+ INDIRECT_CALLABLE_SCOPE int tcp6_gro_complete(struct sk_buff *skb, int thoff)
+@@ -32,6 +75,15 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ const struct ipv6hdr *iph = ipv6_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+
++ if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++ skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV6;
++ skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++ __skb_incr_checksum_unnecessary(skb);
++
++ return 0;
++ }
++
+ th->check = ~tcp_v6_check(skb->len - thoff, &iph->saddr,
+ &iph->daddr, 0);
+ skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV6;
+@@ -39,6 +91,61 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ return tcp_gro_complete(skb);
+ }
+
++static void __tcpv6_gso_segment_csum(struct sk_buff *seg,
++ __be16 *oldport, __be16 newport)
++{
++ struct tcphdr *th;
++
++ if (*oldport == newport)
++ return;
++
++ th = tcp_hdr(seg);
++ inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++ *oldport = newport;
++}
++
++static struct sk_buff *__tcpv6_gso_segment_list_csum(struct sk_buff *segs)
++{
++ const struct tcphdr *th;
++ const struct ipv6hdr *iph;
++ struct sk_buff *seg;
++ struct tcphdr *th2;
++ struct ipv6hdr *iph2;
++
++ seg = segs;
++ th = tcp_hdr(seg);
++ iph = ipv6_hdr(seg);
++ th2 = tcp_hdr(seg->next);
++ iph2 = ipv6_hdr(seg->next);
++
++ if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++ ipv6_addr_equal(&iph->saddr, &iph2->saddr) &&
++ ipv6_addr_equal(&iph->daddr, &iph2->daddr))
++ return segs;
++
++ while ((seg = seg->next)) {
++ th2 = tcp_hdr(seg);
++ iph2 = ipv6_hdr(seg);
++
++ iph2->saddr = iph->saddr;
++ iph2->daddr = iph->daddr;
++ __tcpv6_gso_segment_csum(seg, &th2->source, th->source);
++ __tcpv6_gso_segment_csum(seg, &th2->dest, th->dest);
++ }
++
++ return segs;
++}
++
++static struct sk_buff *__tcp6_gso_segment_list(struct sk_buff *skb,
++ netdev_features_t features)
++{
++ skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++ if (IS_ERR(skb))
++ return skb;
++
++ return __tcpv6_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp6_gso_segment(struct sk_buff *skb,
+ netdev_features_t features)
+ {
+@@ -50,6 +157,9 @@ static struct sk_buff *tcp6_gso_segment(
+ if (!pskb_may_pull(skb, sizeof(*th)))
+ return ERR_PTR(-EINVAL);
+
++ if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++ return __tcp6_gso_segment_list(skb, features);
++
+ if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ const struct ipv6hdr *ipv6h = ipv6_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 27 Apr 2024 18:54:25 +0200
+Subject: [PATCH] net: bridge: fix multicast-to-unicast with fraglist GSO
+
+Calling skb_copy on a SKB_GSO_FRAGLIST skb is not valid, since it returns
+an invalid linearized skb. This code only needs to change the ethernet
+header, so pskb_copy is the right function to call here.
+
+Fixes: 6db6f0eae605 ("bridge: multicast to unicast")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/bridge/br_forward.c
++++ b/net/bridge/br_forward.c
+@@ -261,7 +261,7 @@ static void maybe_deliver_addr(struct ne
+ if (skb->dev == p->dev && ether_addr_equal(src, addr))
+ return;
+
+- skb = skb_copy(skb, GFP_ATOMIC);
++ skb = pskb_copy(skb, GFP_ATOMIC);
+ if (!skb) {
+ DEV_STATS_INC(dev, tx_dropped);
+ return;
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 27 Apr 2024 19:29:45 +0200
+Subject: [PATCH] net: core: reject skb_copy(_expand) for fraglist GSO skbs
+
+SKB_GSO_FRAGLIST skbs must not be linearized, otherwise they become
+invalid. Return NULL if such an skb is passed to skb_copy or
+skb_copy_expand, in order to prevent a crash on a potential later
+call to skb_gso_segment.
+
+Fixes: 3a1296a38d0c ("net: Support GRO/GSO fraglist chaining.")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/core/skbuff.c
++++ b/net/core/skbuff.c
+@@ -1720,11 +1720,17 @@ static inline int skb_alloc_rx_flag(cons
+
+ struct sk_buff *skb_copy(const struct sk_buff *skb, gfp_t gfp_mask)
+ {
+- int headerlen = skb_headroom(skb);
+- unsigned int size = skb_end_offset(skb) + skb->data_len;
+- struct sk_buff *n = __alloc_skb(size, gfp_mask,
+- skb_alloc_rx_flag(skb), NUMA_NO_NODE);
++ struct sk_buff *n;
++ unsigned int size;
++ int headerlen;
+
++ if (WARN_ON_ONCE(skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST))
++ return NULL;
++
++ headerlen = skb_headroom(skb);
++ size = skb_end_offset(skb) + skb->data_len;
++ n = __alloc_skb(size, gfp_mask,
++ skb_alloc_rx_flag(skb), NUMA_NO_NODE);
+ if (!n)
+ return NULL;
+
+@@ -2037,12 +2043,17 @@ struct sk_buff *skb_copy_expand(const st
+ /*
+ * Allocate the copy buffer
+ */
+- struct sk_buff *n = __alloc_skb(newheadroom + skb->len + newtailroom,
+- gfp_mask, skb_alloc_rx_flag(skb),
+- NUMA_NO_NODE);
+- int oldheadroom = skb_headroom(skb);
+ int head_copy_len, head_copy_off;
++ struct sk_buff *n;
++ int oldheadroom;
++
++ if (WARN_ON_ONCE(skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST))
++ return NULL;
+
++ oldheadroom = skb_headroom(skb);
++ n = __alloc_skb(newheadroom + skb->len + newtailroom,
++ gfp_mask, skb_alloc_rx_flag(skb),
++ NUMA_NO_NODE);
+ if (!n)
+ return NULL;
+
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sun, 5 May 2024 20:36:56 +0200
+Subject: [PATCH] net: bridge: fix corrupted ethernet header on
+ multicast-to-unicast
+
+The change from skb_copy to pskb_copy unfortunately changed the data
+copying to omit the ethernet header, since it was pulled before reaching
+this point. Fix this by calling __skb_push/pull around pskb_copy.
+
+Fixes: 59c878cbcdd8 ("net: bridge: fix multicast-to-unicast with fraglist GSO")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/bridge/br_forward.c
++++ b/net/bridge/br_forward.c
+@@ -253,6 +253,7 @@ static void maybe_deliver_addr(struct ne
+ {
+ struct net_device *dev = BR_INPUT_SKB_CB(skb)->brdev;
+ const unsigned char *src = eth_hdr(skb)->h_source;
++ struct sk_buff *nskb;
+
+ if (!should_deliver(p, skb))
+ return;
+@@ -261,12 +262,16 @@ static void maybe_deliver_addr(struct ne
+ if (skb->dev == p->dev && ether_addr_equal(src, addr))
+ return;
+
+- skb = pskb_copy(skb, GFP_ATOMIC);
+- if (!skb) {
++ __skb_push(skb, ETH_HLEN);
++ nskb = pskb_copy(skb, GFP_ATOMIC);
++ __skb_pull(skb, ETH_HLEN);
++ if (!nskb) {
+ DEV_STATS_INC(dev, tx_dropped);
+ return;
+ }
+
++ skb = nskb;
++ __skb_pull(skb, ETH_HLEN);
+ if (!is_broadcast_ether_addr(addr))
+ memcpy(eth_hdr(skb)->h_dest, addr, ETH_ALEN);
+
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
-@@ -7918,7 +7918,7 @@ static int nft_register_flowtable_net_ho
+@@ -7959,7 +7959,7 @@ static int nft_register_flowtable_net_ho
err = flowtable->data.type->setup(&flowtable->data,
hook->ops.dev,
FLOW_BLOCK_BIND);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4941,6 +4941,8 @@ static int mtk_probe(struct platform_dev
+@@ -4940,6 +4940,8 @@ static int mtk_probe(struct platform_dev
* for NAPI to work
*/
init_dummy_netdev(ð->dummy_dev);
if (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev)
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
-@@ -344,6 +344,8 @@ static rx_handler_result_t br_handle_fra
+@@ -349,6 +349,8 @@ static rx_handler_result_t br_handle_fra
fwd_mask |= p->group_fwd_mask;
switch (dest[5]) {
case 0x00: /* Bridge Group Address */
+++ /dev/null
-From 3fb8841513c4ec3a2e5d366df86230c45f239a57 Mon Sep 17 00:00:00 2001
-From: Alexander Couzens <lynxis@fe80.eu>
-Date: Sat, 13 Aug 2022 13:08:22 +0200
-Subject: [PATCH 03/10] net: mt7531: ensure all MACs are powered down before
- reset
-
-The datasheet [1] explicit describes it as requirement for a reset.
-
-[1] MT7531 Reference Manual for Development Board rev 1.0, page 735
-
-Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
----
- drivers/net/dsa/mt7530.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2252,6 +2252,10 @@ mt7530_setup(struct dsa_switch *ds)
- return -ENODEV;
- }
-
-+ /* all MACs must be forced link-down before sw reset */
-+ for (i = 0; i < MT7530_NUM_PORTS; i++)
-+ mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
-+
- /* Reset the switch through internal reset */
- mt7530_write(priv, MT7530_SYS_CTRL,
- SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
-@@ -754,6 +754,38 @@ static int rtl8226_match_phy_device(stru
+@@ -80,6 +80,7 @@
+
+ #define RTL_GENERIC_PHYID 0x001cc800
+ #define RTL_8211FVD_PHYID 0x001cc878
++#define RTL_8221B_VB_CG_PHYID 0x001cc849
+
+ MODULE_DESCRIPTION("Realtek PHY driver");
+ MODULE_AUTHOR("Johnson Leung");
+@@ -754,6 +755,38 @@ static int rtl8226_match_phy_device(stru
rtlgen_supports_2_5gbps(phydev);
}
+ id |= val;
+ }
+
-+ return (id == 0x001cc849);
++ return (id == RTL_8221B_VB_CG_PHYID);
+}
+
static int rtl822x_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
-@@ -1104,7 +1136,7 @@ static struct phy_driver realtek_drvs[]
+@@ -1104,7 +1137,7 @@ static struct phy_driver realtek_drvs[]
.write_page = rtl821x_write_page,
.soft_reset = genphy_soft_reset,
}, {
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
-@@ -2192,7 +2192,7 @@ struct net_device {
+@@ -2190,7 +2190,7 @@ struct net_device {
#if IS_ENABLED(CONFIG_AX25)
void *ax25_ptr;
#endif
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1562,12 +1562,28 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1561,12 +1561,28 @@ static void mtk_wake_queue(struct mtk_et
}
}
bool gso = false;
int tx_num;
-@@ -1589,6 +1605,18 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1588,6 +1604,18 @@ static netdev_tx_t mtk_start_xmit(struct
return NETDEV_TX_BUSY;
}
/* TSO: fill MSS info in tcp checksum field */
if (skb_is_gso(skb)) {
if (skb_cow_head(skb, 0)) {
-@@ -1604,8 +1632,14 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1603,8 +1631,14 @@ static netdev_tx_t mtk_start_xmit(struct
}
}
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -767,6 +767,7 @@ static void mtk_mac_link_up(struct phyli
+@@ -766,6 +766,7 @@ static void mtk_mac_link_up(struct phyli
MAC_MCR_FORCE_RX_FC);
/* Configure speed */
switch (speed) {
case SPEED_2500:
case SPEED_1000:
-@@ -3348,6 +3349,9 @@ found:
+@@ -3347,6 +3348,9 @@ found:
if (dp->index >= MTK_QDMA_NUM_QUEUES)
return NOTIFY_DONE;
+++ /dev/null
-From ef5976ae4e117fae9a61bb3c0f8319a917a425ea Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 11 Mar 2024 17:43:28 +0000
-Subject: [PATCH] net: mediatek: mtk_eth_soc: release MAC_MCR_FORCE_LINK only when MAC is up
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Clearing bit MAC_MCR_FORCE_LINK which forces the link down too early
-can result in MAC ending up in a broken/blocked state.
-
-Fix this by handling this bit in the .mac_link_up and .mac_link_down
-calls instead of in .mac_finish.
-
-Fixes: b8fc9f30821ec ("net: ethernet: mediatek: Add basic PHYLINK support")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -662,8 +662,7 @@ static int mtk_mac_finish(struct phylink
- mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
- mcr_new = mcr_cur;
- mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
-- MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK |
-- MAC_MCR_RX_FIFO_CLR_DIS;
-+ MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_RX_FIFO_CLR_DIS;
-
- /* Only update control register when needed! */
- if (mcr_new != mcr_cur)
-@@ -679,7 +678,7 @@ static void mtk_mac_link_down(struct phy
- phylink_config);
- u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
-
-- mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
-+ mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK);
- mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
- }
-
-@@ -788,7 +787,7 @@ static void mtk_mac_link_up(struct phyli
- if (rx_pause)
- mcr |= MAC_MCR_FORCE_RX_FC;
-
-- mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
-+ mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK;
- mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
- }
-
+++ /dev/null
-From c8262ebbf7ca546dd5ead3c0383a89eb401627ff Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 13 Mar 2024 17:55:02 +0000
-Subject: [PATCH] net: ethernet: mtk_eth_soc: fix PPE hanging issue
-
-A patch to resolve an issue was found in MediaTek's GPL-licensed SDK:
-In the mtk_ppe_stop() function, the PPE scan mode is not disabled before
-disabling the PPE. This can potentially lead to a hang during the process
-of disabling the PPE.
-
-Without this patch, the PPE may experience a hang during the reboot test.
-
-Reference: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/b40da332dfe763932a82f9f62a4709457a15dd6c
-
-Suggested-by: Bc-bocun Chen <bc-bocun.chen@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/ethernet/mediatek/mtk_ppe.c | 18 +++++++++++-------
- 1 file changed, 11 insertions(+), 7 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_ppe.c
-+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
-@@ -1002,7 +1002,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
- MTK_PPE_KEEPALIVE_DISABLE) |
- FIELD_PREP(MTK_PPE_TB_CFG_HASH_MODE, 1) |
- FIELD_PREP(MTK_PPE_TB_CFG_SCAN_MODE,
-- MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |
-+ MTK_PPE_SCAN_MODE_CHECK_AGE) |
- FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,
- MTK_PPE_ENTRIES_SHIFT);
- if (mtk_is_netsys_v2_or_greater(ppe->eth))
-@@ -1098,17 +1098,21 @@ int mtk_ppe_stop(struct mtk_ppe *ppe)
-
- mtk_ppe_cache_enable(ppe, false);
-
-- /* disable offload engine */
-- ppe_clear(ppe, MTK_PPE_GLO_CFG, MTK_PPE_GLO_CFG_EN);
-- ppe_w32(ppe, MTK_PPE_FLOW_CFG, 0);
--
- /* disable aging */
- val = MTK_PPE_TB_CFG_AGE_NON_L4 |
- MTK_PPE_TB_CFG_AGE_UNBIND |
- MTK_PPE_TB_CFG_AGE_TCP |
- MTK_PPE_TB_CFG_AGE_UDP |
-- MTK_PPE_TB_CFG_AGE_TCP_FIN;
-+ MTK_PPE_TB_CFG_AGE_TCP_FIN |
-+ MTK_PPE_TB_CFG_SCAN_MODE;
- ppe_clear(ppe, MTK_PPE_TB_CFG, val);
-
-- return mtk_ppe_wait_busy(ppe);
-+ if (mtk_ppe_wait_busy(ppe))
-+ return -ETIMEDOUT;
-+
-+ /* disable offload engine */
-+ ppe_clear(ppe, MTK_PPE_GLO_CFG, MTK_PPE_GLO_CFG_EN);
-+ ppe_w32(ppe, MTK_PPE_FLOW_CFG, 0);
-+
-+ return 0;
- }
+From d7943c31d57c11e1a517aa3ce2006fca44866870 Mon Sep 17 00:00:00 2001
+From: Jianhui Zhao <zhaojh329@gmail.com>
+Date: Sun, 24 Sep 2023 22:15:00 +0800
+Subject: [PATCH] net: phy: realtek: add interrupt support for RTL8221B
+
+This commit introduces interrupt support for RTL8221B.
+
+Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
+---
+ drivers/net/phy/realtek.c | 47 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
-@@ -981,6 +981,51 @@ static int rtl8221b_config_init(struct p
+@@ -982,6 +982,51 @@ static int rtl8221b_config_init(struct p
return 0;
}
static struct phy_driver realtek_drvs[] = {
{
PHY_ID_MATCH_EXACT(0x00008201),
-@@ -1141,6 +1186,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1142,6 +1187,8 @@ static struct phy_driver realtek_drvs[]
.get_features = rtl822x_get_features,
.config_init = rtl8221b_config_init,
.config_aneg = rtl822x_config_aneg,
--- /dev/null
+From 9be9a00adfac8118b6d685e71696f83187308c66 Mon Sep 17 00:00:00 2001
+Message-ID: <9be9a00adfac8118b6d685e71696f83187308c66.1715125851.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 7 May 2024 22:43:30 +0100
+Subject: [PATCH net] net: phy: air_en8811h: reset netdev rules when LED is set
+ manually
+To: Andrew Lunn <andrew@lunn.ch>,
+ Heiner Kallweit <hkallweit1@gmail.com>,
+ Russell King <linux@armlinux.org.uk>,
+ David S. Miller <davem@davemloft.net>,
+ Eric Dumazet <edumazet@google.com>,
+ Jakub Kicinski <kuba@kernel.org>,
+ Paolo Abeni <pabeni@redhat.com>,
+ SkyLake Huang <skylake.huang@mediatek.com>,
+ Eric Woudstra <ericwouds@gmail.com>,
+ netdev@vger.kernel.org,
+ linux-kernel@vger.kernel.org
+
+Setting LED_OFF via the brightness_set should deactivate hw control,
+so make sure netdev trigger rules also get cleared in that case.
+
+Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+This is basically a stop-gap measure until unified LED handling has
+been implemented accross all MediaTek and Airoha PHYs.
+See also
+https://patchwork.kernel.org/project/netdevbpf/patch/20240425023325.15586-3-SkyLake.Huang@mediatek.com/
+
+ drivers/net/phy/air_en8811h.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/phy/air_en8811h.c
++++ b/drivers/net/phy/air_en8811h.c
+@@ -544,6 +544,10 @@ static int air_hw_led_on_set(struct phy_
+
+ changed |= (priv->led[index].rules != 0);
+
++ /* clear netdev trigger rules in case LED_OFF has been set */
++ if (!on)
++ priv->led[index].rules = 0;
++
+ if (changed)
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
+ AIR_PHY_LED_ON(index),
+++ /dev/null
-From patchwork Tue Feb 6 19:47:51 2024
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Eric Woudstra <ericwouds@gmail.com>
-X-Patchwork-Id: 13547762
-X-Patchwork-Delegate: kuba@kernel.org
-From: Eric Woudstra <ericwouds@gmail.com>
-To: "David S. Miller" <davem@davemloft.net>,
- Eric Dumazet <edumazet@google.com>,
- Jakub Kicinski <kuba@kernel.org>,
- Paolo Abeni <pabeni@redhat.com>,
- Rob Herring <robh+dt@kernel.org>,
- Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
- Conor Dooley <conor+dt@kernel.org>,
- Andrew Lunn <andrew@lunn.ch>,
- Heiner Kallweit <hkallweit1@gmail.com>,
- Russell King <linux@armlinux.org.uk>,
- Matthias Brugger <matthias.bgg@gmail.com>,
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
- "Frank Wunderlich" <frank-w@public-files.de>,
- Daniel Golle <daniel@makrotopia.org>,
- Lucien Jheng <lucien.jheng@airoha.com>,
- Zhi-Jun You <hujy652@protonmail.com>
-Cc: netdev@vger.kernel.org,
- devicetree@vger.kernel.org,
- Eric Woudstra <ericwouds@gmail.com>
-Subject: [PATCH net-next 2/2] net: phy: air_en8811h: Add the Airoha EN8811H
- PHY driver
-Date: Tue, 6 Feb 2024 20:47:51 +0100
-Message-ID: <20240206194751.1901802-3-ericwouds@gmail.com>
-X-Mailer: git-send-email 2.42.1
-In-Reply-To: <20240206194751.1901802-1-ericwouds@gmail.com>
-References: <20240206194751.1901802-1-ericwouds@gmail.com>
-Precedence: bulk
-X-Mailing-List: netdev@vger.kernel.org
-List-Id: <netdev.vger.kernel.org>
-List-Subscribe: <mailto:netdev+subscribe@vger.kernel.org>
-List-Unsubscribe: <mailto:netdev+unsubscribe@vger.kernel.org>
-MIME-Version: 1.0
-X-Patchwork-Delegate: kuba@kernel.org
-
-* Source originated from airoha's en8811h v1.2.1 driver
- * Moved air_en8811h.h to air_en8811h.c
- * Removed air_pbus_reg_write() as it writes to another device on mdio-bus
- * Load firmware from /lib/firmware/airoha/ instead of /lib/firmware/
- * Added .get_rate_matching()
- * Use generic phy_read/write() and phy_read/write_mmd()
- * Edited .get_features() to use generic C45 functions
- * Edited .config_aneg() and .read_status() to use a mix of generic C22/C45
- * Use led handling functions from mediatek-ge-soc.c
- * Simplified led handling by storing led rules
- * Cleanup macro definitions
- * Cleanup code to pass checkpatch.pl
- * General code cleanup
-
-Changes from original RFC patch:
-
- * Use the correct order in Kconfig and Makefile
- * Change some register naming to correspond with datasheet
- * Use phy_driver .read_page() and .write_page()
- * Use module_phy_driver()
- * Use get_unaligned_le16() instead of macro
- * In .config_aneg() and .read_status() use genphy_xxx() C22
- * Use another vendor register to read real speed
- * Load firmware only once and store firmware version
- * Apply 2.5G LPA work-around (firmware before 24011202)
- * Read 2.5G LPA from vendor register (firmware 24011202 and later)
-
-Changes to be committed:
- modified: drivers/net/phy/Kconfig
- modified: drivers/net/phy/Makefile
- new file: drivers/net/phy/air_en8811h.c
-
-Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
----
- drivers/net/phy/Kconfig | 5 +
- drivers/net/phy/Makefile | 1 +
- drivers/net/phy/air_en8811h.c | 1006 +++++++++++++++++++++++++++++++++
- 3 files changed, 1012 insertions(+)
- create mode 100644 drivers/net/phy/air_en8811h.c
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -69,6 +69,11 @@ config SFP
-
- comment "MII PHY device drivers"
-
-+config AIR_EN8811H_PHY
-+ tristate "Airoha EN8811H 2.5 Gigabit PHY"
-+ help
-+ Currently supports the Airoha EN8811H PHY.
-+
- config AMD_PHY
- tristate "AMD and Altima PHYs"
- help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -32,6 +32,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
-
- obj-$(CONFIG_ADIN_PHY) += adin.o
- obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
-+obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
- obj-$(CONFIG_AMD_PHY) += amd.o
- obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
- obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
---- /dev/null
-+++ b/drivers/net/phy/air_en8811h.c
-@@ -0,0 +1,1006 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Driver for Airoha Ethernet PHYs
-+ *
-+ * Currently supporting the EN8811H.
-+ *
-+ * Limitations of the EN8811H:
-+ * - Only full duplex supported
-+ * - Forced speed (AN off) is not supported by hardware (100Mbps)
-+ *
-+ * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
-+ *
-+ * Copyright (C) 2023 Airoha Technology Corp.
-+ */
-+
-+#include <linux/phy.h>
-+#include <linux/firmware.h>
-+#include <linux/property.h>
-+#include <asm/unaligned.h>
-+
-+#define EN8811H_PHY_ID 0x03a2a411
-+
-+#define EN8811H_MD32_DM "airoha/EthMD32.dm.bin"
-+#define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin"
-+
-+#define AIR_FW_ADDR_DM 0x00000000
-+#define AIR_FW_ADDR_DSP 0x00100000
-+
-+/* u32 (DWORD) component macros */
-+#define LOWORD(d) ((u16)(u32)(d))
-+#define HIWORD(d) ((u16)(((u32)(d)) >> 16))
-+
-+/* MII Registers */
-+#define AIR_AUX_CTRL_STATUS 0x1d
-+#define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2)
-+#define AIR_AUX_CTRL_STATUS_SPEED_100 0x4
-+#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
-+#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
-+
-+#define AIR_EXT_PAGE_ACCESS 0x1f
-+#define AIR_PHY_PAGE_STANDARD 0x0000
-+#define AIR_PHY_PAGE_EXTENDED_4 0x0004
-+
-+/* MII Registers Page 4*/
-+#define AIR_PBUS_MODE 0x10
-+#define AIR_PBUS_MODE_ADDR_FIXED 0x0000
-+#define AIR_PBUS_MODE_ADDR_INCR BIT(15)
-+#define AIR_PBUS_WR_ADDR_HIGH 0x11
-+#define AIR_PBUS_WR_ADDR_LOW 0x12
-+#define AIR_PBUS_WR_DATA_HIGH 0x13
-+#define AIR_PBUS_WR_DATA_LOW 0x14
-+#define AIR_PBUS_RD_ADDR_HIGH 0x15
-+#define AIR_PBUS_RD_ADDR_LOW 0x16
-+#define AIR_PBUS_RD_DATA_HIGH 0x17
-+#define AIR_PBUS_RD_DATA_LOW 0x18
-+
-+/* Registers on MDIO_MMD_VEND1 */
-+#define EN8811H_PHY_FW_STATUS 0x8009
-+#define EN8811H_PHY_READY 0x02
-+
-+#define AIR_PHY_HOST_CMD_1 0x800c
-+#define AIR_PHY_HOST_CMD_1_MODE1 0x0
-+#define AIR_PHY_HOST_CMD_2 0x800d
-+#define AIR_PHY_HOST_CMD_2_MODE1 0x0
-+#define AIR_PHY_HOST_CMD_3 0x800e
-+#define AIR_PHY_HOST_CMD_3_MODE1 0x1101
-+#define AIR_PHY_HOST_CMD_3_DOCMD 0x1100
-+#define AIR_PHY_HOST_CMD_4 0x800f
-+#define AIR_PHY_HOST_CMD_4_MODE1 0x0002
-+#define AIR_PHY_HOST_CMD_4_INTCLR 0x00e4
-+
-+/* Registers on MDIO_MMD_VEND2 */
-+#define AIR_PHY_LED_BCR 0x021
-+#define AIR_PHY_LED_BCR_MODE_MASK GENMASK(1, 0)
-+#define AIR_PHY_LED_BCR_TIME_TEST BIT(2)
-+#define AIR_PHY_LED_BCR_CLK_EN BIT(3)
-+#define AIR_PHY_LED_BCR_EXT_CTRL BIT(15)
-+
-+#define AIR_PHY_LED_DUR_ON 0x022
-+
-+#define AIR_PHY_LED_DUR_BLINK 0x023
-+
-+#define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2))
-+#define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8))
-+#define AIR_PHY_LED_ON_LINK1000 BIT(0)
-+#define AIR_PHY_LED_ON_LINK100 BIT(1)
-+#define AIR_PHY_LED_ON_LINK10 BIT(2)
-+#define AIR_PHY_LED_ON_LINKDOWN BIT(3)
-+#define AIR_PHY_LED_ON_FDX BIT(4) /* Full duplex */
-+#define AIR_PHY_LED_ON_HDX BIT(5) /* Half duplex */
-+#define AIR_PHY_LED_ON_FORCE_ON BIT(6)
-+#define AIR_PHY_LED_ON_LINK2500 BIT(8)
-+#define AIR_PHY_LED_ON_POLARITY BIT(14)
-+#define AIR_PHY_LED_ON_ENABLE BIT(15)
-+
-+#define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2))
-+#define AIR_PHY_LED_BLINK_1000TX BIT(0)
-+#define AIR_PHY_LED_BLINK_1000RX BIT(1)
-+#define AIR_PHY_LED_BLINK_100TX BIT(2)
-+#define AIR_PHY_LED_BLINK_100RX BIT(3)
-+#define AIR_PHY_LED_BLINK_10TX BIT(4)
-+#define AIR_PHY_LED_BLINK_10RX BIT(5)
-+#define AIR_PHY_LED_BLINK_COLLISION BIT(6)
-+#define AIR_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
-+#define AIR_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
-+#define AIR_PHY_LED_BLINK_FORCE_BLINK BIT(9)
-+#define AIR_PHY_LED_BLINK_2500TX BIT(10)
-+#define AIR_PHY_LED_BLINK_2500RX BIT(11)
-+
-+/* Registers on BUCKPBUS */
-+#define EN8811H_2P5G_LPA 0x3b30
-+#define EN8811H_2P5G_LPA_2P5G BIT(0)
-+
-+#define EN8811H_FW_VERSION 0x3b3c
-+
-+#define EN8811H_POLARITY 0xca0f8
-+#define EN8811H_POLARITY_TX_NORMAL BIT(0)
-+#define EN8811H_POLARITY_RX_REVERSE BIT(1)
-+
-+#define EN8811H_GPIO_OUTPUT 0xcf8b8
-+#define EN8811H_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5))
-+
-+#define EN8811H_FW_CTRL_1 0x0f0018
-+#define EN8811H_FW_CTRL_1_START 0x0
-+#define EN8811H_FW_CTRL_1_FINISH 0x1
-+#define EN8811H_FW_CTRL_2 0x800000
-+#define EN8811H_FW_CTRL_2_LOADING BIT(11)
-+
-+#define EN8811H_LED_COUNT 3
-+
-+/* GPIO5 <-> BASE_T_LED0
-+ * GPIO4 <-> BASE_T_LED1
-+ * GPIO3 <-> BASE_T_LED2
-+ *
-+ * Default setup suitable for 2 leds connected:
-+ * 100M link up triggers led0, only led0 blinking on traffic
-+ * 1000M link up triggers led1, only led1 blinking on traffic
-+ * 2500M link up triggers led0 and led1, both blinking on traffic
-+ * Also suitable for 1 led connected:
-+ * any link up triggers led2
-+ */
-+#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK_2500) | \
-+ BIT(TRIGGER_NETDEV_LINK_100) | \
-+ BIT(TRIGGER_NETDEV_RX) | \
-+ BIT(TRIGGER_NETDEV_TX))
-+#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
-+ BIT(TRIGGER_NETDEV_LINK_1000) | \
-+ BIT(TRIGGER_NETDEV_RX) | \
-+ BIT(TRIGGER_NETDEV_TX))
-+#define AIR_DEFAULT_TRIGGER_LED2 BIT(TRIGGER_NETDEV_LINK)
-+
-+struct led {
-+ unsigned long rules;
-+ unsigned long state;
-+};
-+
-+struct en8811h_priv {
-+ u32 firmware_version;
-+ struct led led[EN8811H_LED_COUNT];
-+};
-+
-+enum {
-+ AIR_PHY_LED_STATE_FORCE_ON,
-+ AIR_PHY_LED_STATE_FORCE_BLINK,
-+};
-+
-+enum {
-+ AIR_PHY_LED_DUR_BLINK_32M,
-+ AIR_PHY_LED_DUR_BLINK_64M,
-+ AIR_PHY_LED_DUR_BLINK_128M,
-+ AIR_PHY_LED_DUR_BLINK_256M,
-+ AIR_PHY_LED_DUR_BLINK_512M,
-+ AIR_PHY_LED_DUR_BLINK_1024M,
-+};
-+
-+enum {
-+ AIR_LED_DISABLE,
-+ AIR_LED_ENABLE,
-+};
-+
-+enum {
-+ AIR_ACTIVE_LOW,
-+ AIR_ACTIVE_HIGH,
-+};
-+
-+enum {
-+ AIR_LED_MODE_DISABLE,
-+ AIR_LED_MODE_USER_DEFINE,
-+};
-+
-+#define AIR_PHY_LED_DUR_UNIT 1024
-+#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64M)
-+
-+static const unsigned long en8811h_led_trig = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
-+ BIT(TRIGGER_NETDEV_LINK) |
-+ BIT(TRIGGER_NETDEV_LINK_10) |
-+ BIT(TRIGGER_NETDEV_LINK_100) |
-+ BIT(TRIGGER_NETDEV_LINK_1000) |
-+ BIT(TRIGGER_NETDEV_LINK_2500) |
-+ BIT(TRIGGER_NETDEV_RX) |
-+ BIT(TRIGGER_NETDEV_TX));
-+
-+static int air_phy_read_page(struct phy_device *phydev)
-+{
-+ return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
-+}
-+
-+static int air_phy_write_page(struct phy_device *phydev, int page)
-+{
-+ return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
-+}
-+
-+static int __air_buckpbus_reg_write(struct phy_device *phydev,
-+ u32 pbus_address, u32 pbus_data)
-+{
-+ int ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(pbus_address));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW, LOWORD(pbus_address));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, HIWORD(pbus_data));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, LOWORD(pbus_data));
-+ if (ret < 0)
-+ return ret;
-+
-+ return 0;
-+}
-+
-+static int air_buckpbus_reg_write(struct phy_device *phydev,
-+ u32 pbus_address, u32 pbus_data)
-+{
-+ int ret, saved_page;
-+
-+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+ ret = __air_buckpbus_reg_write(phydev, pbus_address, pbus_data);
-+ if (ret < 0)
-+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+ pbus_address, ret);
-+
-+ return phy_restore_page(phydev, saved_page, ret);
-+;
-+}
-+
-+static int __air_buckpbus_reg_read(struct phy_device *phydev,
-+ u32 pbus_address, u32 *pbus_data)
-+{
-+ int pbus_data_low, pbus_data_high;
-+ int ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_HIGH, HIWORD(pbus_address));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_LOW, LOWORD(pbus_address));
-+ if (ret < 0)
-+ return ret;
-+
-+ pbus_data_high = __phy_read(phydev, AIR_PBUS_RD_DATA_HIGH);
-+ if (pbus_data_high < 0)
-+ return ret;
-+
-+ pbus_data_low = __phy_read(phydev, AIR_PBUS_RD_DATA_LOW);
-+ if (pbus_data_low < 0)
-+ return ret;
-+
-+ *pbus_data = (u16)pbus_data_low | ((u32)(u16)pbus_data_high << 16);
-+ return 0;
-+}
-+
-+static int air_buckpbus_reg_read(struct phy_device *phydev,
-+ u32 pbus_address, u32 *pbus_data)
-+{
-+ int ret, saved_page;
-+
-+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
-+ if (ret < 0)
-+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+ pbus_address, ret);
-+
-+ return phy_restore_page(phydev, saved_page, ret);
-+}
-+
-+static int __air_write_buf(struct phy_device *phydev, u32 address,
-+ const struct firmware *fw)
-+{
-+ unsigned int offset;
-+ int ret;
-+ u16 val;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_INCR);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(address));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW, LOWORD(address));
-+ if (ret < 0)
-+ return ret;
-+
-+ for (offset = 0; offset < fw->size; offset += 4) {
-+ val = get_unaligned_le16(&fw->data[offset + 2]);
-+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, val);
-+ if (ret < 0)
-+ return ret;
-+
-+ val = get_unaligned_le16(&fw->data[offset]);
-+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, val);
-+ if (ret < 0)
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int air_write_buf(struct phy_device *phydev, u32 address,
-+ const struct firmware *fw)
-+{
-+ int ret, saved_page;
-+
-+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+ ret = __air_write_buf(phydev, address, fw);
-+ if (ret < 0)
-+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+ address, ret);
-+
-+ return phy_restore_page(phydev, saved_page, ret);
-+}
-+
-+static int en8811h_load_firmware(struct phy_device *phydev)
-+{
-+ struct device *dev = &phydev->mdio.dev;
-+ const struct firmware *fw1, *fw2;
-+ u32 pbus_value;
-+ int ret;
-+
-+ ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_rel1;
-+
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+ EN8811H_FW_CTRL_1_START);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+ pbus_value |= EN8811H_FW_CTRL_2_LOADING;
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = air_write_buf(phydev, AIR_FW_ADDR_DM, fw1);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+ pbus_value &= ~EN8811H_FW_CTRL_2_LOADING;
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+ EN8811H_FW_CTRL_1_FINISH);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = 0;
-+
-+en8811h_load_firmware_out:
-+ release_firmware(fw2);
-+
-+en8811h_load_firmware_rel1:
-+ release_firmware(fw1);
-+
-+ if (ret < 0)
-+ phydev_err(phydev, "Load firmware failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int en8811h_restart_host(struct phy_device *phydev)
-+{
-+ int ret;
-+
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+ EN8811H_FW_CTRL_1_START);
-+ if (ret < 0)
-+ return ret;
-+
-+ return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+ EN8811H_FW_CTRL_1_FINISH);
-+}
-+
-+static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ bool changed;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ if (on)
-+ changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
-+ &priv->led[index].state);
-+ else
-+ changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
-+ &priv->led[index].state);
-+
-+ changed |= (priv->led[index].rules != 0);
-+
-+ if (changed)
-+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
-+ AIR_PHY_LED_ON(index),
-+ AIR_PHY_LED_ON_MASK,
-+ on ? AIR_PHY_LED_ON_FORCE_ON : 0);
-+
-+ return 0;
-+}
-+
-+static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
-+ bool blinking)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ bool changed;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ if (blinking)
-+ changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
-+ &priv->led[index].state);
-+ else
-+ changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
-+ &priv->led[index].state);
-+
-+ changed |= (priv->led[index].rules != 0);
-+
-+ if (changed)
-+ return phy_write_mmd(phydev, MDIO_MMD_VEND2,
-+ AIR_PHY_LED_BLINK(index),
-+ blinking ?
-+ AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
-+ else
-+ return 0;
-+}
-+
-+static int air_led_blink_set(struct phy_device *phydev, u8 index,
-+ unsigned long *delay_on,
-+ unsigned long *delay_off)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ bool blinking = false;
-+ int err;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
-+ blinking = true;
-+ *delay_on = 50;
-+ *delay_off = 50;
-+ }
-+
-+ err = air_hw_led_blink_set(phydev, index, blinking);
-+ if (err)
-+ return err;
-+
-+ /* led-blink set, so switch led-on off */
-+ err = air_hw_led_on_set(phydev, index, false);
-+ if (err)
-+ return err;
-+
-+ /* hw-control is off*/
-+ if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
-+ priv->led[index].rules = 0;
-+
-+ return 0;
-+}
-+
-+static int air_led_brightness_set(struct phy_device *phydev, u8 index,
-+ enum led_brightness value)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ int err;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ /* led-on set, so switch led-blink off */
-+ err = air_hw_led_blink_set(phydev, index, false);
-+ if (err)
-+ return err;
-+
-+ err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
-+ if (err)
-+ return err;
-+
-+ /* hw-control is off */
-+ if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
-+ priv->led[index].rules = 0;
-+
-+ return 0;
-+}
-+
-+static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
-+ unsigned long *rules)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ *rules = priv->led[index].rules;
-+
-+ return 0;
-+};
-+
-+static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
-+ unsigned long rules)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ u16 on = 0, blink = 0;
-+ int ret;
-+
-+ priv->led[index].rules = rules;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) {
-+ on |= AIR_PHY_LED_ON_LINK10;
-+ if (rules & BIT(TRIGGER_NETDEV_RX))
-+ blink |= AIR_PHY_LED_BLINK_10RX;
-+ if (rules & BIT(TRIGGER_NETDEV_TX))
-+ blink |= AIR_PHY_LED_BLINK_10TX;
-+ }
-+
-+ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) {
-+ on |= AIR_PHY_LED_ON_LINK100;
-+ if (rules & BIT(TRIGGER_NETDEV_RX))
-+ blink |= AIR_PHY_LED_BLINK_100RX;
-+ if (rules & BIT(TRIGGER_NETDEV_TX))
-+ blink |= AIR_PHY_LED_BLINK_100TX;
-+ }
-+
-+ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) {
-+ on |= AIR_PHY_LED_ON_LINK1000;
-+ if (rules & BIT(TRIGGER_NETDEV_RX))
-+ blink |= AIR_PHY_LED_BLINK_1000RX;
-+ if (rules & BIT(TRIGGER_NETDEV_TX))
-+ blink |= AIR_PHY_LED_BLINK_1000TX;
-+ }
-+
-+ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) {
-+ on |= AIR_PHY_LED_ON_LINK2500;
-+ if (rules & BIT(TRIGGER_NETDEV_RX))
-+ blink |= AIR_PHY_LED_BLINK_2500RX;
-+ if (rules & BIT(TRIGGER_NETDEV_TX))
-+ blink |= AIR_PHY_LED_BLINK_2500TX;
-+ }
-+
-+ if (on == 0) {
-+ if (rules & BIT(TRIGGER_NETDEV_RX)) {
-+ blink |= AIR_PHY_LED_BLINK_10RX |
-+ AIR_PHY_LED_BLINK_100RX |
-+ AIR_PHY_LED_BLINK_1000RX |
-+ AIR_PHY_LED_BLINK_2500RX;
-+ }
-+ if (rules & BIT(TRIGGER_NETDEV_TX)) {
-+ blink |= AIR_PHY_LED_BLINK_10TX |
-+ AIR_PHY_LED_BLINK_100TX |
-+ AIR_PHY_LED_BLINK_1000TX |
-+ AIR_PHY_LED_BLINK_2500TX;
-+ }
-+ }
-+
-+ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
-+ on |= AIR_PHY_LED_ON_FDX;
-+
-+ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
-+ on |= AIR_PHY_LED_ON_HDX;
-+
-+ if (blink || on) {
-+ /* switch hw-control on, so led-on and led-blink are off */
-+ clear_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state);
-+ clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state);
-+ } else {
-+ priv->led[index].rules = 0;
-+ }
-+
-+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
-+ AIR_PHY_LED_ON_MASK, on);
-+
-+ if (ret < 0)
-+ return ret;
-+
-+ return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
-+ blink);
-+};
-+
-+static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
-+{
-+ int cl45_data;
-+ int err;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index));
-+ if (cl45_data < 0)
-+ return cl45_data;
-+
-+ if (state == AIR_LED_ENABLE)
-+ cl45_data |= AIR_PHY_LED_ON_ENABLE;
-+ else
-+ cl45_data &= ~AIR_PHY_LED_ON_ENABLE;
-+
-+ if (pol == AIR_ACTIVE_HIGH)
-+ cl45_data |= AIR_PHY_LED_ON_POLARITY;
-+ else
-+ cl45_data &= ~AIR_PHY_LED_ON_POLARITY;
-+
-+ err = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
-+ cl45_data);
-+ if (err < 0)
-+ return err;
-+
-+ return 0;
-+}
-+
-+static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ int cl45_data = dur;
-+ int ret, i;
-+
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
-+ cl45_data);
-+ if (ret < 0)
-+ return ret;
-+
-+ cl45_data >>= 1;
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
-+ cl45_data);
-+ if (ret < 0)
-+ return ret;
-+
-+ cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR);
-+ if (cl45_data < 0)
-+ return cl45_data;
-+
-+ switch (mode) {
-+ case AIR_LED_MODE_DISABLE:
-+ cl45_data &= ~AIR_PHY_LED_BCR_EXT_CTRL;
-+ cl45_data &= ~AIR_PHY_LED_BCR_MODE_MASK;
-+ break;
-+ case AIR_LED_MODE_USER_DEFINE:
-+ cl45_data |= AIR_PHY_LED_BCR_EXT_CTRL;
-+ cl45_data |= AIR_PHY_LED_BCR_CLK_EN;
-+ break;
-+ default:
-+ phydev_err(phydev, "LED mode %d is not supported\n", mode);
-+ return -EINVAL;
-+ }
-+
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, cl45_data);
-+ if (ret < 0)
-+ return ret;
-+
-+ for (i = 0; i < num; ++i) {
-+ ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
-+ if (ret < 0) {
-+ phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
-+ return ret;
-+ }
-+ air_led_hw_control_set(phydev, i, priv->led[i].rules);
-+ }
-+
-+ return 0;
-+}
-+
-+static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
-+ unsigned long rules)
-+{
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ /* All combinations of the supported triggers are allowed */
-+ if (rules & ~en8811h_led_trig)
-+ return -EOPNOTSUPP;
-+
-+ return 0;
-+};
-+
-+static int en8811h_probe(struct phy_device *phydev)
-+{
-+ struct en8811h_priv *priv;
-+
-+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
-+ GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
-+ priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
-+ priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
-+
-+ phydev->priv = priv;
-+
-+ /* MDIO_DEVS1/2 empty, so set mmds_present bits here */
-+ phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
-+
-+ return 0;
-+}
-+
-+static int en8811h_config_init(struct phy_device *phydev)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ struct device *dev = &phydev->mdio.dev;
-+ int ret, pollret, reg_value;
-+ u32 pbus_value;
-+
-+ if (!priv->firmware_version)
-+ ret = en8811h_load_firmware(phydev);
-+ else
-+ ret = en8811h_restart_host(phydev);
-+ if (ret < 0)
-+ return ret;
-+
-+ /* Because of mdio-lock, may have to wait for multiple loads */
-+ pollret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
-+ EN8811H_PHY_FW_STATUS, reg_value,
-+ reg_value == EN8811H_PHY_READY,
-+ 20000, 7500000, true);
-+
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &pbus_value);
-+ if (ret < 0)
-+ return ret;
-+
-+ if (pollret || !pbus_value) {
-+ phydev_err(phydev, "Firmware not ready: 0x%x\n", reg_value);
-+ return -ENODEV;
-+ }
-+
-+ if (!priv->firmware_version) {
-+ phydev_info(phydev, "MD32 firmware version: %08x\n", pbus_value);
-+ priv->firmware_version = pbus_value;
-+ }
-+
-+ /* Select mode 1, the only mode supported */
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_1,
-+ AIR_PHY_HOST_CMD_1_MODE1);
-+ if (ret < 0)
-+ return ret;
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_2,
-+ AIR_PHY_HOST_CMD_2_MODE1);
-+ if (ret < 0)
-+ return ret;
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
-+ AIR_PHY_HOST_CMD_3_MODE1);
-+ if (ret < 0)
-+ return ret;
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
-+ AIR_PHY_HOST_CMD_4_MODE1);
-+ if (ret < 0)
-+ return ret;
-+
-+ /* Serdes polarity */
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_POLARITY, &pbus_value);
-+ if (ret < 0)
-+ return ret;
-+ if (device_property_read_bool(dev, "airoha,pnswap-rx"))
-+ pbus_value |= EN8811H_POLARITY_RX_REVERSE;
-+ else
-+ pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
-+ if (device_property_read_bool(dev, "airoha,pnswap-tx"))
-+ pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
-+ else
-+ pbus_value |= EN8811H_POLARITY_TX_NORMAL;
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_POLARITY, pbus_value);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
-+ AIR_LED_MODE_USER_DEFINE);
-+ if (ret < 0) {
-+ phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
-+ return ret;
-+ }
-+
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_GPIO_OUTPUT, &pbus_value);
-+ if (ret < 0)
-+ return ret;
-+ pbus_value |= EN8811H_GPIO_OUTPUT_345;
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_GPIO_OUTPUT, pbus_value);
-+ if (ret < 0)
-+ return ret;
-+
-+ return 0;
-+}
-+
-+static int en8811h_get_features(struct phy_device *phydev)
-+{
-+ linkmode_set_bit_array(phy_basic_ports_array,
-+ ARRAY_SIZE(phy_basic_ports_array),
-+ phydev->supported);
-+
-+ return genphy_c45_pma_read_abilities(phydev);
-+}
-+
-+static int en8811h_get_rate_matching(struct phy_device *phydev,
-+ phy_interface_t iface)
-+{
-+ return RATE_MATCH_PAUSE;
-+}
-+
-+static int en8811h_config_aneg(struct phy_device *phydev)
-+{
-+ bool changed = false;
-+ int err, val;
-+
-+ val = 0;
-+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+ phydev->advertising))
-+ val |= MDIO_AN_10GBT_CTRL_ADV2_5G;
-+ err = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
-+ MDIO_AN_10GBT_CTRL_ADV2_5G, val);
-+ if (err < 0)
-+ return err;
-+ if (err > 0)
-+ changed = true;
-+
-+ return __genphy_config_aneg(phydev, changed);
-+}
-+
-+static int en8811h_read_status(struct phy_device *phydev)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ u32 pbus_value;
-+ int ret, val;
-+
-+ ret = genphy_update_link(phydev);
-+ if (ret)
-+ return ret;
-+
-+ phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
-+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
-+ phydev->speed = SPEED_UNKNOWN;
-+ phydev->duplex = DUPLEX_UNKNOWN;
-+ phydev->pause = 0;
-+ phydev->asym_pause = 0;
-+
-+ ret = genphy_read_master_slave(phydev);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = genphy_read_lpa(phydev);
-+ if (ret < 0)
-+ return ret;
-+
-+ /* Get link partner 2.5GBASE-T ability from vendor register */
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
-+ if (ret < 0)
-+ return ret;
-+ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+ phydev->lp_advertising,
-+ pbus_value & EN8811H_2P5G_LPA_2P5G);
-+
-+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
-+ phy_resolve_aneg_pause(phydev);
-+
-+ if (!phydev->link)
-+ return 0;
-+
-+ /* Get real speed from vendor register */
-+ val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
-+ if (val < 0)
-+ return val;
-+ switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
-+ case AIR_AUX_CTRL_STATUS_SPEED_2500:
-+ phydev->speed = SPEED_2500;
-+ break;
-+ case AIR_AUX_CTRL_STATUS_SPEED_1000:
-+ phydev->speed = SPEED_1000;
-+ break;
-+ case AIR_AUX_CTRL_STATUS_SPEED_100:
-+ phydev->speed = SPEED_100;
-+ break;
-+ }
-+
-+ /* BUG in PHY firmware: MDIO_AN_10GBT_STAT_LP2_5G does not get set.
-+ * Firmware before version 24011202 has no vendor register 2P5G_LPA.
-+ * Assume link partner advertised it if connected at 2500Mbps.
-+ */
-+ if (priv->firmware_version < 0x24011202) {
-+ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+ phydev->lp_advertising,
-+ phydev->speed == SPEED_2500);
-+ }
-+
-+ /* Only supports full duplex */
-+ phydev->duplex = DUPLEX_FULL;
-+
-+ return 0;
-+}
-+
-+static int en8811h_clear_intr(struct phy_device *phydev)
-+{
-+ int ret;
-+
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
-+ AIR_PHY_HOST_CMD_3_DOCMD);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
-+ AIR_PHY_HOST_CMD_4_INTCLR);
-+ if (ret < 0)
-+ return ret;
-+
-+ return 0;
-+}
-+
-+static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
-+{
-+ int ret;
-+
-+ ret = en8811h_clear_intr(phydev);
-+ if (ret < 0) {
-+ phy_error(phydev);
-+ return IRQ_NONE;
-+ }
-+
-+ phy_trigger_machine(phydev);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct phy_driver en8811h_driver[] = {
-+{
-+ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
-+ .name = "Airoha EN8811H",
-+ .probe = en8811h_probe,
-+ .get_features = en8811h_get_features,
-+ .config_init = en8811h_config_init,
-+ .get_rate_matching = en8811h_get_rate_matching,
-+ .config_aneg = en8811h_config_aneg,
-+ .read_status = en8811h_read_status,
-+ .config_intr = en8811h_clear_intr,
-+ .handle_interrupt = en8811h_handle_interrupt,
-+ .led_hw_is_supported = en8811h_led_hw_is_supported,
-+ .read_page = air_phy_read_page,
-+ .write_page = air_phy_write_page,
-+ .led_blink_set = air_led_blink_set,
-+ .led_brightness_set = air_led_brightness_set,
-+ .led_hw_control_set = air_led_hw_control_set,
-+ .led_hw_control_get = air_led_hw_control_get,
-+} };
-+
-+module_phy_driver(en8811h_driver);
-+
-+static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
-+ { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
-+MODULE_FIRMWARE(EN8811H_MD32_DM);
-+MODULE_FIRMWARE(EN8811H_MD32_DSP);
-+
-+MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
-+MODULE_AUTHOR("Airoha");
-+MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
-+MODULE_LICENSE("GPL");
/**
* napi_disable - prevent NAPI from scheduling
-@@ -3152,6 +3153,7 @@ struct softnet_data {
+@@ -3150,6 +3151,7 @@ struct softnet_data {
unsigned int processed;
unsigned int time_squeeze;
unsigned int received_rps;
void netif_napi_add_weight(struct net_device *dev, struct napi_struct *napi,
int (*poll)(struct napi_struct *, int), int weight)
{
-@@ -11168,6 +11239,9 @@ static int dev_cpu_dead(unsigned int old
+@@ -11126,6 +11197,9 @@ static int dev_cpu_dead(unsigned int old
raise_softirq_irqoff(NET_TX_SOFTIRQ);
local_irq_enable();
#ifdef CONFIG_RPS
remsd = oldsd->rps_ipi_list;
oldsd->rps_ipi_list = NULL;
-@@ -11480,6 +11554,7 @@ static int __init net_dev_init(void)
+@@ -11438,6 +11512,7 @@ static int __init net_dev_init(void)
INIT_CSD(&sd->defer_csd, trigger_rx_softirq, sd);
spin_lock_init(&sd->defer_lock);
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -7025,6 +7025,7 @@ static int mv88e6xxx_register_switch(str
+@@ -7037,6 +7037,7 @@ static int mv88e6xxx_register_switch(str
ds->ops = &mv88e6xxx_switch_ops;
ds->ageing_time_min = chip->info->age_time_coeff;
ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
+++ /dev/null
-From 1d81e51d6d79d9098013b2e8cdd677bae998c5d8 Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Fri, 28 Apr 2023 02:22:59 +0200
-Subject: [PATCH 1/2] mt7530: register OF node for internal MDIO bus
-
-The MT753x switches provide a switch-internal MDIO bus for the embedded
-PHYs.
-
-Register a OF sub-node on the switch OF-node for this internal MDIO bus.
-This allows to configure the embedded PHYs using device-tree.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- drivers/net/dsa/mt7530.c | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2142,10 +2142,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr
- {
- struct dsa_switch *ds = priv->ds;
- struct device *dev = priv->dev;
-+ struct device_node *np, *mnp;
- struct mii_bus *bus;
- static int idx;
- int ret;
-
-+ np = priv->dev->of_node;
-+
- bus = devm_mdiobus_alloc(dev);
- if (!bus)
- return -ENOMEM;
-@@ -2162,7 +2165,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr
- if (priv->irq)
- mt7530_setup_mdio_irq(priv);
-
-- ret = devm_mdiobus_register(dev, bus);
-+ mnp = of_get_child_by_name(np, "mdio");
-+ ret = devm_of_mdiobus_register(dev, bus, mnp);
-+ of_node_put(mnp);
- if (ret) {
- dev_err(dev, "failed to register MDIO bus: %d\n", ret);
- if (priv->irq)
+++ /dev/null
-From a444877c10a665cd8a869e6d37facdb89fd95f79 Mon Sep 17 00:00:00 2001
-Message-ID: <a444877c10a665cd8a869e6d37facdb89fd95f79.1706070008.git.daniel@makrotopia.org>
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 24 Jan 2024 04:17:11 +0000
-Subject: [PATCH net] net: dsa: mt7530: fix 10M/100M speed on MT7988 switch
-To: Arınç ÜNAL <arinc.unal@arinc9.com>,
- Daniel Golle <daniel@makrotopia.org>,
- DENG Qingfang <dqfext@gmail.com>,
- Sean Wang <sean.wang@mediatek.com>,
- Andrew Lunn <andrew@lunn.ch>,
- Florian Fainelli <f.fainelli@gmail.com>,
- Vladimir Oltean <olteanv@gmail.com>,
- David S. Miller <davem@davemloft.net>,
- Eric Dumazet <edumazet@google.com>,
- Jakub Kicinski <kuba@kernel.org>,
- Paolo Abeni <pabeni@redhat.com>,
- Matthias Brugger <matthias.bgg@gmail.com>,
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
- netdev@vger.kernel.org,
- linux-kernel@vger.kernel.org,
- linux-arm-kernel@lists.infradead.org,
- linux-mediatek@lists.infradead.org
-
-Setup PMCR port register for actual speed and duplex on internally
-connected PHYs of the MT7988 built-in switch. This fixes links with
-speeds other than 1000M.
-
-Fixes: ("110c18bfed414 net: dsa: mt7530: introduce driver for MT7988 built-in switch")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/dsa/mt7530.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2849,8 +2849,7 @@ static void mt753x_phylink_mac_link_up(s
- /* MT753x MAC works in 1G full duplex mode for all up-clocked
- * variants.
- */
-- if (interface == PHY_INTERFACE_MODE_INTERNAL ||
-- interface == PHY_INTERFACE_MODE_TRGMII ||
-+ if (interface == PHY_INTERFACE_MODE_TRGMII ||
- (phy_interface_mode_is_8023z(interface))) {
- speed = SPEED_1000;
- duplex = DUPLEX_FULL;
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
-@@ -1711,4 +1711,19 @@ config GPIO_SIM
+@@ -1712,4 +1712,19 @@ config GPIO_SIM
endmenu
static struct amd_chipset_info {
struct pci_dev *nb_dev;
struct pci_dev *smbus_dev;
-@@ -633,6 +635,10 @@ bool usb_amd_pt_check_port(struct device
+@@ -631,6 +633,10 @@ bool usb_amd_pt_check_port(struct device
}
EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);
/*
* Make sure the controller is completely inactive, unable to
* generate interrupts or do DMA.
-@@ -712,8 +718,17 @@ reset_needed:
+@@ -710,8 +716,17 @@ reset_needed:
uhci_reset_hc(pdev, base);
return 1;
}
static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
{
u16 cmd;
-@@ -1285,3 +1300,4 @@ static void quirk_usb_early_handoff(stru
+@@ -1283,3 +1298,4 @@ static void quirk_usb_early_handoff(stru
}
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);
#endif /* __LINUX_USB_PCI_QUIRKS_H */
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
-@@ -483,7 +483,14 @@ extern int usb_hcd_pci_probe(struct pci_
+@@ -484,7 +484,14 @@ extern int usb_hcd_pci_probe(struct pci_
extern void usb_hcd_pci_remove(struct pci_dev *dev);
extern void usb_hcd_pci_shutdown(struct pci_dev *dev);
/*
* Define if arch has non-standard setup. This is a _PCI_ standard
-@@ -864,6 +867,12 @@ struct ata_port {
+@@ -865,6 +868,12 @@ struct ata_port {
#ifdef CONFIG_ATA_ACPI
struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */
#endif
--- /dev/null
+From 38eb5b3370c29515d2ce92adac2d6eba96f276f5 Mon Sep 17 00:00:00 2001
+From: INAGAKI Hiroshi <musashino.open@gmail.com>
+Date: Wed, 20 Mar 2024 15:32:18 +0900
+Subject: [PATCH v2 1/2] dt-bindings: leds: add LED_FUNCTION_MOBILE for mobile
+ network
+
+Add LED_FUNCTION_MOBILE for LEDs that indicate status of mobile network
+connection. This is useful to distinguish those LEDs from LEDs that
+indicates status of wired "wan" connection.
+
+example (on stock fw):
+
+IIJ SA-W2 has "Mobile" LEDs that indicate status (no signal, too low,
+low, good) of mobile network connection via dongle connected to USB
+port.
+
+- no signal: (none, turned off)
+- too low: green:mobile & red:mobile (amber, blink)
+- low: green:mobile & red:mobile (amber, turned on)
+- good: green:mobile (turned on)
+
+Suggested-by: Hauke Mehrtens <hauke@hauke-m.de>
+Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
+---
+ include/dt-bindings/leds/common.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/include/dt-bindings/leds/common.h
++++ b/include/dt-bindings/leds/common.h
+@@ -90,6 +90,7 @@
+ #define LED_FUNCTION_INDICATOR "indicator"
+ #define LED_FUNCTION_LAN "lan"
+ #define LED_FUNCTION_MAIL "mail"
++#define LED_FUNCTION_MOBILE "mobile"
+ #define LED_FUNCTION_MTD "mtd"
+ #define LED_FUNCTION_PANIC "panic"
+ #define LED_FUNCTION_PROGRAMMING "programming"
--- /dev/null
+From e22afe910afcfb51b6ba6a0ae776939959727f54 Mon Sep 17 00:00:00 2001
+From: INAGAKI Hiroshi <musashino.open@gmail.com>
+Date: Wed, 20 Mar 2024 15:59:06 +0900
+Subject: [PATCH v2 2/2] dt-bindings: leds: add LED_FUNCTION_SPEED_* for link
+ speed on LAN/WAN
+
+Add LED_FUNCTION_SPEED_LAN and LED_FUNCTION_SPEED_WAN for LEDs that
+indicate link speed of ethernet ports on LAN/WAN. This is useful to
+distinguish those LEDs from LEDs that indicate link status (up/down).
+
+example:
+
+Fortinet FortiGate 30E/50E have LEDs that indicate link speed on each
+of the ethernet ports in addition to LEDs that indicate link status
+(up/down).
+
+- 1000 Mbps: green:speed-(lan|wan)-N
+- 100 Mbps: amber:speed-(lan|wan)-N
+- 10 Mbps: (none, turned off)
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
+---
+ include/dt-bindings/leds/common.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/dt-bindings/leds/common.h
++++ b/include/dt-bindings/leds/common.h
+@@ -96,6 +96,8 @@
+ #define LED_FUNCTION_PROGRAMMING "programming"
+ #define LED_FUNCTION_RX "rx"
+ #define LED_FUNCTION_SD "sd"
++#define LED_FUNCTION_SPEED_LAN "speed-lan"
++#define LED_FUNCTION_SPEED_WAN "speed-wan"
+ #define LED_FUNCTION_STANDBY "standby"
+ #define LED_FUNCTION_TORCH "torch"
+ #define LED_FUNCTION_TX "tx"
help
--- a/init/main.c
+++ b/init/main.c
-@@ -611,6 +611,29 @@ static inline void setup_nr_cpu_ids(void
+@@ -612,6 +612,29 @@ static inline void setup_nr_cpu_ids(void
static inline void smp_prepare_cpus(unsigned int maxcpus) { }
#endif
/*
* We need to store the untouched command line for future reference.
* We also need to store the touched command line since the parameter
-@@ -958,6 +981,7 @@ asmlinkage __visible void __init __no_sa
+@@ -961,6 +984,7 @@ asmlinkage __visible void __init __no_sa
pr_notice("%s", linux_banner);
early_security_init();
setup_arch(&command_line);
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
-@@ -239,6 +239,9 @@ static void __br_handle_local_finish(str
+@@ -244,6 +244,9 @@ static void __br_handle_local_finish(str
/* note: already called with rcu_read_lock */
static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb)
{
__br_handle_local_finish(skb);
/* return 1 to signal the okfn() was called so it's ok to use the skb */
-@@ -408,6 +411,17 @@ forward:
+@@ -415,6 +418,17 @@ forward:
goto defer_stp_filtering;
switch (p->state) {
--- /dev/null
+From patchwork Sun Apr 21 07:39:52 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: INAGAKI Hiroshi <musashino.open@gmail.com>
+X-Patchwork-Id: 13637306
+From: INAGAKI Hiroshi <musashino.open@gmail.com>
+To: axboe@kernel.dk
+Cc: yang.yang29@zte.com,
+ justinstitt@google.com,
+ xu.panda@zte.com.cn,
+ linux-block@vger.kernel.org,
+ linux-kernel@vger.kernel.org,
+ INAGAKI Hiroshi <musashino.open@gmail.com>,
+ Naohiro Aota <naota@elisp.net>
+Subject: [PATCH] block: fix and simplify blkdevparts= cmdline parsing
+Date: Sun, 21 Apr 2024 16:39:52 +0900
+Message-ID: <20240421074005.565-1-musashino.open@gmail.com>
+X-Mailer: git-send-email 2.42.0.windows.2
+Precedence: bulk
+X-Mailing-List: linux-block@vger.kernel.org
+List-Id: <linux-block.vger.kernel.org>
+List-Subscribe: <mailto:linux-block+subscribe@vger.kernel.org>
+List-Unsubscribe: <mailto:linux-block+unsubscribe@vger.kernel.org>
+MIME-Version: 1.0
+
+Fix the cmdline parsing of the "blkdevparts=" parameter using strsep(),
+which makes the code simpler.
+
+Before commit 146afeb235cc ("block: use strscpy() to instead of
+strncpy()"), we used a strncpy() to copy a block device name and partition
+names. The commit simply replaced a strncpy() and NULL termination with
+a strscpy(). It did not update calculations of length passed to strscpy().
+While the length passed to strncpy() is just a length of valid characters
+without NULL termination ('\0'), strscpy() takes it as a length of the
+destination buffer, including a NULL termination.
+
+Since the source buffer is not necessarily NULL terminated, the current
+code copies "length - 1" characters and puts a NULL character in the
+destination buffer. It replaces the last character with NULL and breaks
+the parsing.
+
+As an example, that buffer will be passed to parse_parts() and breaks
+parsing sub-partitions due to the missing ')' at the end, like the
+following.
+
+example (Check Point V-80 & OpenWrt):
+
+- Linux Kernel 6.6
+
+ [ 0.000000] Kernel command line: console=ttyS0,115200 earlycon=uart8250,mmio32,0xf0512000 crashkernel=30M mvpp2x.queue_mode=1 blkdevparts=mmcblk1:48M@10M(kernel-1),1M(dtb-1),720M(rootfs-1),48M(kernel-2),1M(dtb-2),720M(rootfs-2),300M(default_sw),650M(logs),1M(preset_cfg),1M(adsl),-(storage) maxcpus=4
+ ...
+ [ 0.884016] mmc1: new HS200 MMC card at address 0001
+ [ 0.889951] mmcblk1: mmc1:0001 004GA0 3.69 GiB
+ [ 0.895043] cmdline partition format is invalid.
+ [ 0.895704] mmcblk1: p1
+ [ 0.903447] mmcblk1boot0: mmc1:0001 004GA0 2.00 MiB
+ [ 0.908667] mmcblk1boot1: mmc1:0001 004GA0 2.00 MiB
+ [ 0.913765] mmcblk1rpmb: mmc1:0001 004GA0 512 KiB, chardev (248:0)
+
+ 1. "48M@10M(kernel-1),..." is passed to strscpy() with length=17
+ from parse_parts()
+ 2. strscpy() returns -E2BIG and the destination buffer has
+ "48M@10M(kernel-1\0"
+ 3. "48M@10M(kernel-1\0" is passed to parse_subpart()
+ 4. parse_subpart() fails to find ')' when parsing a partition name,
+ and returns error
+
+- Linux Kernel 6.1
+
+ [ 0.000000] Kernel command line: console=ttyS0,115200 earlycon=uart8250,mmio32,0xf0512000 crashkernel=30M mvpp2x.queue_mode=1 blkdevparts=mmcblk1:48M@10M(kernel-1),1M(dtb-1),720M(rootfs-1),48M(kernel-2),1M(dtb-2),720M(rootfs-2),300M(default_sw),650M(logs),1M(preset_cfg),1M(adsl),-(storage) maxcpus=4
+ ...
+ [ 0.953142] mmc1: new HS200 MMC card at address 0001
+ [ 0.959114] mmcblk1: mmc1:0001 004GA0 3.69 GiB
+ [ 0.964259] mmcblk1: p1(kernel-1) p2(dtb-1) p3(rootfs-1) p4(kernel-2) p5(dtb-2) 6(rootfs-2) p7(default_sw) p8(logs) p9(preset_cfg) p10(adsl) p11(storage)
+ [ 0.979174] mmcblk1boot0: mmc1:0001 004GA0 2.00 MiB
+ [ 0.984674] mmcblk1boot1: mmc1:0001 004GA0 2.00 MiB
+ [ 0.989926] mmcblk1rpmb: mmc1:0001 004GA0 512 KiB, chardev (248:0
+
+By the way, strscpy() takes a length of destination buffer and it is
+often confusing when copying characters with a specified length. Using
+strsep() helps to separate the string by the specified character. Then,
+we can use strscpy() naturally with the size of the destination buffer.
+
+Separating the string on the fly is also useful to omit the redundant
+string copy, reducing memory usage and improve the code readability.
+
+Fixes: 146afeb235cc ("block: use strscpy() to instead of strncpy()")
+Suggested-by: Naohiro Aota <naota@elisp.net>
+Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+---
+ block/partitions/cmdline.c | 49 ++++++++++----------------------------
+ 1 file changed, 12 insertions(+), 37 deletions(-)
+
+--- a/block/partitions/cmdline.c
++++ b/block/partitions/cmdline.c
+@@ -70,8 +70,8 @@ static int parse_subpart(struct cmdline_
+ }
+
+ if (*partdef == '(') {
+- int length;
+- char *next = strchr(++partdef, ')');
++ partdef++;
++ char *next = strsep(&partdef, ")");
+
+ if (!next) {
+ pr_warn("cmdline partition format is invalid.");
+@@ -79,11 +79,7 @@ static int parse_subpart(struct cmdline_
+ goto fail;
+ }
+
+- length = min_t(int, next - partdef,
+- sizeof(new_subpart->name) - 1);
+- strscpy(new_subpart->name, partdef, length);
+-
+- partdef = ++next;
++ strscpy(new_subpart->name, next, sizeof(new_subpart->name));
+ } else
+ new_subpart->name[0] = '\0';
+
+@@ -117,14 +113,12 @@ static void free_subpart(struct cmdline_
+ }
+ }
+
+-static int parse_parts(struct cmdline_parts **parts, const char *bdevdef)
++static int parse_parts(struct cmdline_parts **parts, char *bdevdef)
+ {
+ int ret = -EINVAL;
+ char *next;
+- int length;
+ struct cmdline_subpart **next_subpart;
+ struct cmdline_parts *newparts;
+- char buf[BDEVNAME_SIZE + 32 + 4];
+
+ *parts = NULL;
+
+@@ -132,28 +126,19 @@ static int parse_parts(struct cmdline_pa
+ if (!newparts)
+ return -ENOMEM;
+
+- next = strchr(bdevdef, ':');
++ next = strsep(&bdevdef, ":");
+ if (!next) {
+ pr_warn("cmdline partition has no block device.");
+ goto fail;
+ }
+
+- length = min_t(int, next - bdevdef, sizeof(newparts->name) - 1);
+- strscpy(newparts->name, bdevdef, length);
++ strscpy(newparts->name, next, sizeof(newparts->name));
+ newparts->nr_subparts = 0;
+
+ next_subpart = &newparts->subpart;
+
+- while (next && *(++next)) {
+- bdevdef = next;
+- next = strchr(bdevdef, ',');
+-
+- length = (!next) ? (sizeof(buf) - 1) :
+- min_t(int, next - bdevdef, sizeof(buf) - 1);
+-
+- strscpy(buf, bdevdef, length);
+-
+- ret = parse_subpart(next_subpart, buf);
++ while ((next = strsep(&bdevdef, ","))) {
++ ret = parse_subpart(next_subpart, next);
+ if (ret)
+ goto fail;
+
+@@ -199,24 +184,17 @@ static int cmdline_parts_parse(struct cm
+
+ *parts = NULL;
+
+- next = pbuf = buf = kstrdup(cmdline, GFP_KERNEL);
++ pbuf = buf = kstrdup(cmdline, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ next_parts = parts;
+
+- while (next && *pbuf) {
+- next = strchr(pbuf, ';');
+- if (next)
+- *next = '\0';
+-
+- ret = parse_parts(next_parts, pbuf);
++ while ((next = strsep(&pbuf, ";"))) {
++ ret = parse_parts(next_parts, next);
+ if (ret)
+ goto fail;
+
+- if (next)
+- pbuf = ++next;
+-
+ next_parts = &(*next_parts)->next_parts;
+ }
+
+@@ -250,7 +228,6 @@ static struct cmdline_parts *bdev_parts;
+ static int add_part(int slot, struct cmdline_subpart *subpart,
+ struct parsed_partitions *state)
+ {
+- int label_min;
+ struct partition_meta_info *info;
+ char tmp[sizeof(info->volname) + 4];
+
+@@ -262,9 +239,7 @@ static int add_part(int slot, struct cmd
+
+ info = &state->parts[slot].info;
+
+- label_min = min_t(int, sizeof(info->volname) - 1,
+- sizeof(subpart->name));
+- strscpy(info->volname, subpart->name, label_min);
++ strscpy(info->volname, subpart->name, sizeof(info->volname));
+
+ snprintf(tmp, sizeof(tmp), "(%s)", info->volname);
+ strlcat(state->pp_buf, tmp, PAGE_SIZE);
2. Use a fixed pattern instead of a random function pointer as the
magic value.
3. Flip magic value and double check it.
+4. Enable this feature only for 32-bit CPUs. Currently, only ath79 and
+ ralink CPUs are using it.
[1] 439a1bcac648 ("fortify: Use __builtin_dynamic_object_size() when available")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
- arch/mips/kernel/setup.c | 16 +++++++++++-----
- 1 file changed, 11 insertions(+), 5 deletions(-)
+ arch/mips/include/asm/bootinfo.h | 2 ++
+ arch/mips/kernel/setup.c | 17 ++++++++++++-----
+ 2 files changed, 14 insertions(+), 5 deletions(-)
+--- a/arch/mips/include/asm/bootinfo.h
++++ b/arch/mips/include/asm/bootinfo.h
+@@ -93,7 +93,9 @@ const char *get_system_type(void);
+
+ extern unsigned long mips_machtype;
+
++#ifndef CONFIG_64BIT
+ extern void detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max);
++#endif
+
+ extern void prom_init(void);
+ extern void prom_free_prom_memory(void);
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
-@@ -46,6 +46,8 @@
- #include <asm/prom.h>
- #include <asm/fw/fw.h>
-
-+#define MIPS_MEM_TEST_PATTERN 0xaa5555aa
-+
- #ifdef CONFIG_MIPS_ELF_APPENDED_DTB
- char __section(".appended_dtb") __appended_dtb[0x100000];
- #endif /* CONFIG_MIPS_ELF_APPENDED_DTB */
-@@ -90,7 +92,7 @@ static struct resource bss_resource = {
+@@ -90,21 +90,27 @@ static struct resource bss_resource = {
unsigned long __kaslr_offset __ro_after_init;
EXPORT_SYMBOL(__kaslr_offset);
-static void *detect_magic __initdata = detect_memory_region;
-+static u32 detect_magic __initdata;
-
+-
#ifdef CONFIG_MIPS_AUTO_PFN_OFFSET
unsigned long ARCH_PFN_OFFSET;
-@@ -99,12 +101,16 @@ EXPORT_SYMBOL(ARCH_PFN_OFFSET);
+ EXPORT_SYMBOL(ARCH_PFN_OFFSET);
+ #endif
++#ifndef CONFIG_64BIT
++static u32 detect_magic __initdata;
++#define MIPS_MEM_TEST_PATTERN 0xaa5555aa
++
void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_addr_t sz_max)
{
- void *dm = &detect_magic;
}
pr_debug("Memory: %lluMB of RAM detected at 0x%llx (min: %lluMB, max: %lluMB)\n",
+@@ -115,6 +121,7 @@ void __init detect_memory_region(phys_ad
+
+ memblock_add(start, size);
+ }
++#endif /* CONFIG_64BIT */
+
+ /*
+ * Manage initrd
--- /dev/null
+From ecb8f9a7d69698ce20fc6f4d107718d56fa861df Mon Sep 17 00:00:00 2001
+From: Tony Ambardar <Tony.Ambardar@gmail.com>
+Date: Sat, 9 Mar 2024 16:44:53 -0800
+Subject: [PATCH] selftests/bpf: Improve portability of unprivileged tests
+
+The addition of general support for unprivileged tests in test_loader.c
+breaks building test_verifier on non-glibc (e.g. musl) systems, due to the
+inclusion of glibc extension '<error.h>' in 'unpriv_helpers.c'. However,
+the header is actually not needed, so remove it to restore building.
+
+Fixes: 1d56ade032a4 ("selftests/bpf: Unprivileged tests for test_loader.c")
+Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
+---
+ tools/testing/selftests/bpf/unpriv_helpers.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/tools/testing/selftests/bpf/unpriv_helpers.c
++++ b/tools/testing/selftests/bpf/unpriv_helpers.c
+@@ -2,7 +2,6 @@
+
+ #include <stdbool.h>
+ #include <stdlib.h>
+-#include <error.h>
+ #include <stdio.h>
+
+ #include "unpriv_helpers.h"
for (i = sizeof(struct ipt_entry);
i < e->target_offset;
i += m->u.match_size) {
-@@ -1221,12 +1258,15 @@ compat_copy_entry_to_user(struct ipt_ent
+@@ -1225,12 +1262,15 @@ compat_copy_entry_to_user(struct ipt_ent
compat_uint_t origsize;
const struct xt_entry_match *ematch;
int ret = 0;
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -3041,7 +3041,7 @@ static inline int pskb_network_may_pull(
+@@ -3047,7 +3047,7 @@ static inline int pskb_network_may_pull(
* NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8)
*/
#ifndef NET_SKB_PAD
memcpy(p->name, u->name, sizeof(u->name));
}
-@@ -1963,6 +2133,15 @@ static int ip6_tnl_validate(struct nlatt
+@@ -1964,6 +2134,15 @@ static int ip6_tnl_validate(struct nlatt
return 0;
}
static void ip6_tnl_netlink_parms(struct nlattr *data[],
struct __ip6_tnl_parm *parms)
{
-@@ -2000,6 +2179,46 @@ static void ip6_tnl_netlink_parms(struct
+@@ -2001,6 +2180,46 @@ static void ip6_tnl_netlink_parms(struct
if (data[IFLA_IPTUN_FWMARK])
parms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]);
}
static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev,
-@@ -2083,6 +2302,12 @@ static void ip6_tnl_dellink(struct net_d
+@@ -2084,6 +2303,12 @@ static void ip6_tnl_dellink(struct net_d
static size_t ip6_tnl_get_size(const struct net_device *dev)
{
return
/* IFLA_IPTUN_LINK */
nla_total_size(4) +
-@@ -2112,6 +2337,24 @@ static size_t ip6_tnl_get_size(const str
+@@ -2113,6 +2338,24 @@ static size_t ip6_tnl_get_size(const str
nla_total_size(0) +
/* IFLA_IPTUN_FWMARK */
nla_total_size(4) +
0;
}
-@@ -2119,6 +2362,9 @@ static int ip6_tnl_fill_info(struct sk_b
+@@ -2120,6 +2363,9 @@ static int ip6_tnl_fill_info(struct sk_b
{
struct ip6_tnl *tunnel = netdev_priv(dev);
struct __ip6_tnl_parm *parm = &tunnel->parms;
if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) ||
nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) ||
-@@ -2128,9 +2374,27 @@ static int ip6_tnl_fill_info(struct sk_b
+@@ -2129,9 +2375,27 @@ static int ip6_tnl_fill_info(struct sk_b
nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) ||
nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) ||
nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) ||
if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) ||
nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) ||
nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) ||
-@@ -2170,6 +2434,7 @@ static const struct nla_policy ip6_tnl_p
+@@ -2171,6 +2435,7 @@ static const struct nla_policy ip6_tnl_p
[IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 },
[IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG },
[IFLA_IPTUN_FWMARK] = { .type = NLA_U32 },
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Subject: net: replace GRO optimization patch with a new one that supports VLANs/bridges with different MAC addresses
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
- include/linux/netdevice.h | 2 ++
- include/linux/skbuff.h | 3 ++-
- net/core/dev.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++
- net/ethernet/eth.c | 18 +++++++++++++++++-
- 4 files changed, 69 insertions(+), 2 deletions(-)
-
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -2210,6 +2210,8 @@ struct net_device {
- struct netdev_hw_addr_list mc;
- struct netdev_hw_addr_list dev_addrs;
-
-+ unsigned char local_addr_mask[MAX_ADDR_LEN];
-+
- #ifdef CONFIG_SYSFS
- struct kset *queues_kset;
- #endif
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -964,6 +964,7 @@ struct sk_buff {
- #ifdef CONFIG_IPV6_NDISC_NODETYPE
- __u8 ndisc_nodetype:2;
- #endif
-+ __u8 gro_skip:1;
-
- #if IS_ENABLED(CONFIG_IP_VS)
- __u8 ipvs_property:1;
---- a/net/core/gro.c
-+++ b/net/core/gro.c
-@@ -445,6 +445,9 @@ static enum gro_result dev_gro_receive(s
- enum gro_result ret;
- int same_flow;
-
-+ if (skb->gro_skip)
-+ goto normal;
-+
- if (netif_elide_gro(skb->dev))
- goto normal;
-
---- a/net/core/dev.c
-+++ b/net/core/dev.c
-@@ -7689,6 +7689,48 @@ static void __netdev_adjacent_dev_unlink
- &upper_dev->adj_list.lower);
- }
-
-+static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr,
-+ struct net_device *dev)
-+{
-+ int i;
-+
-+ for (i = 0; i < dev->addr_len; i++)
-+ mask[i] |= addr[i] ^ dev->dev_addr[i];
-+}
-+
-+static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev,
-+ struct net_device *lower)
-+{
-+ struct net_device *cur;
-+ struct list_head *iter;
-+
-+ netdev_for_each_upper_dev_rcu(dev, cur, iter) {
-+ __netdev_addr_mask(mask, cur->dev_addr, lower);
-+ __netdev_upper_mask(mask, cur, lower);
-+ }
-+}
-+
-+static void __netdev_update_addr_mask(struct net_device *dev)
-+{
-+ unsigned char mask[MAX_ADDR_LEN];
-+ struct net_device *cur;
-+ struct list_head *iter;
-+
-+ memset(mask, 0, sizeof(mask));
-+ __netdev_upper_mask(mask, dev, dev);
-+ memcpy(dev->local_addr_mask, mask, dev->addr_len);
-+
-+ netdev_for_each_lower_dev(dev, cur, iter)
-+ __netdev_update_addr_mask(cur);
-+}
-+
-+static void netdev_update_addr_mask(struct net_device *dev)
-+{
-+ rcu_read_lock();
-+ __netdev_update_addr_mask(dev);
-+ rcu_read_unlock();
-+}
-+
- static int __netdev_upper_dev_link(struct net_device *dev,
- struct net_device *upper_dev, bool master,
- void *upper_priv, void *upper_info,
-@@ -7740,6 +7782,7 @@ static int __netdev_upper_dev_link(struc
- if (ret)
- return ret;
-
-+ netdev_update_addr_mask(dev);
- ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- &changeupper_info.info);
- ret = notifier_to_errno(ret);
-@@ -7836,6 +7879,7 @@ static void __netdev_upper_dev_unlink(st
-
- __netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
-
-+ netdev_update_addr_mask(dev);
- call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- &changeupper_info.info);
-
-@@ -8892,6 +8936,7 @@ int dev_set_mac_address(struct net_devic
- return err;
- }
- dev->addr_assign_type = NET_ADDR_SET;
-+ netdev_update_addr_mask(dev);
- call_netdevice_notifiers(NETDEV_CHANGEADDR, dev);
- add_device_randomness(dev->dev_addr, dev->addr_len);
- return 0;
---- a/net/ethernet/eth.c
-+++ b/net/ethernet/eth.c
-@@ -143,6 +143,18 @@ u32 eth_get_headlen(const struct net_dev
- }
- EXPORT_SYMBOL(eth_get_headlen);
-
-+static inline bool
-+eth_check_local_mask(const void *addr1, const void *addr2, const void *mask)
-+{
-+ const u16 *a1 = addr1;
-+ const u16 *a2 = addr2;
-+ const u16 *m = mask;
-+
-+ return (((a1[0] ^ a2[0]) & ~m[0]) |
-+ ((a1[1] ^ a2[1]) & ~m[1]) |
-+ ((a1[2] ^ a2[2]) & ~m[2]));
-+}
-+
- /**
- * eth_type_trans - determine the packet's protocol ID.
- * @skb: received socket data
-@@ -174,6 +186,10 @@ __be16 eth_type_trans(struct sk_buff *sk
- } else {
- skb->pkt_type = PACKET_OTHERHOST;
- }
-+
-+ if (eth_check_local_mask(eth->h_dest, dev->dev_addr,
-+ dev->local_addr_mask))
-+ skb->gro_skip = 1;
- }
-
- /*
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 11:23:03 +0200
+Subject: [PATCH] net: add TCP fraglist GRO support
+
+When forwarding TCP after GRO, software segmentation is very expensive,
+especially when the checksum needs to be recalculated.
+One case where that's currently unavoidable is when routing packets over
+PPPoE. Performance improves significantly when using fraglist GRO
+implemented in the same way as for UDP.
+
+Here's a measurement of running 2 TCP streams through a MediaTek MT7622
+device (2-core Cortex-A53), which runs NAT with flow offload enabled from
+one ethernet port to PPPoE on another ethernet port + cake qdisc set to
+1Gbps.
+
+rx-gro-list off: 630 Mbit/s, CPU 35% idle
+rx-gro-list on: 770 Mbit/s, CPU 40% idle
+
+Signe-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/net/gro.h
++++ b/include/net/gro.h
+@@ -439,6 +439,7 @@ static inline __wsum ip6_gro_compute_pse
+ }
+
+ int skb_gro_receive(struct sk_buff *p, struct sk_buff *skb);
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb);
+
+ /* Pass the currently batched GRO_NORMAL SKBs up to the stack. */
+ static inline void gro_normal_list(struct napi_struct *napi)
+--- a/include/net/tcp.h
++++ b/include/net/tcp.h
+@@ -2082,7 +2082,10 @@ void tcp_v4_destroy_sock(struct sock *sk
+
+ struct sk_buff *tcp_gso_segment(struct sk_buff *skb,
+ netdev_features_t features);
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb);
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb);
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th);
+ INDIRECT_CALLABLE_DECLARE(int tcp4_gro_complete(struct sk_buff *skb, int thoff));
+ INDIRECT_CALLABLE_DECLARE(struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb));
+ INDIRECT_CALLABLE_DECLARE(int tcp6_gro_complete(struct sk_buff *skb, int thoff));
+--- a/net/core/gro.c
++++ b/net/core/gro.c
+@@ -233,6 +233,33 @@ done:
+ return 0;
+ }
+
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
++{
++ if (unlikely(p->len + skb->len >= 65536))
++ return -E2BIG;
++
++ if (NAPI_GRO_CB(p)->last == p)
++ skb_shinfo(p)->frag_list = skb;
++ else
++ NAPI_GRO_CB(p)->last->next = skb;
++
++ skb_pull(skb, skb_gro_offset(skb));
++
++ NAPI_GRO_CB(p)->last = skb;
++ NAPI_GRO_CB(p)->count++;
++ p->data_len += skb->len;
++
++ /* sk ownership - if any - completely transferred to the aggregated packet */
++ skb->destructor = NULL;
++ skb->sk = NULL;
++ p->truesize += skb->truesize;
++ p->len += skb->len;
++
++ NAPI_GRO_CB(skb)->same_flow = 1;
++
++ return 0;
++}
++
+
+ static void napi_gro_complete(struct napi_struct *napi, struct sk_buff *skb)
+ {
+--- a/net/ipv4/tcp_offload.c
++++ b/net/ipv4/tcp_offload.c
+@@ -28,6 +28,70 @@ static void tcp_gso_tstamp(struct sk_buf
+ }
+ }
+
++static void __tcpv4_gso_segment_csum(struct sk_buff *seg,
++ __be32 *oldip, __be32 newip,
++ __be16 *oldport, __be16 newport)
++{
++ struct tcphdr *th;
++ struct iphdr *iph;
++
++ if (*oldip == newip && *oldport == newport)
++ return;
++
++ th = tcp_hdr(seg);
++ iph = ip_hdr(seg);
++
++ inet_proto_csum_replace4(&th->check, seg, *oldip, newip, true);
++ inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++ *oldport = newport;
++
++ csum_replace4(&iph->check, *oldip, newip);
++ *oldip = newip;
++}
++
++static struct sk_buff *__tcpv4_gso_segment_list_csum(struct sk_buff *segs)
++{
++ const struct tcphdr *th;
++ const struct iphdr *iph;
++ struct sk_buff *seg;
++ struct tcphdr *th2;
++ struct iphdr *iph2;
++
++ seg = segs;
++ th = tcp_hdr(seg);
++ iph = ip_hdr(seg);
++ th2 = tcp_hdr(seg->next);
++ iph2 = ip_hdr(seg->next);
++
++ if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++ iph->daddr == iph2->daddr && iph->saddr == iph2->saddr)
++ return segs;
++
++ while ((seg = seg->next)) {
++ th2 = tcp_hdr(seg);
++ iph2 = ip_hdr(seg);
++
++ __tcpv4_gso_segment_csum(seg,
++ &iph2->saddr, iph->saddr,
++ &th2->source, th->source);
++ __tcpv4_gso_segment_csum(seg,
++ &iph2->daddr, iph->daddr,
++ &th2->dest, th->dest);
++ }
++
++ return segs;
++}
++
++static struct sk_buff *__tcp4_gso_segment_list(struct sk_buff *skb,
++ netdev_features_t features)
++{
++ skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++ if (IS_ERR(skb))
++ return skb;
++
++ return __tcpv4_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp4_gso_segment(struct sk_buff *skb,
+ netdev_features_t features)
+ {
+@@ -37,6 +101,9 @@ static struct sk_buff *tcp4_gso_segment(
+ if (!pskb_may_pull(skb, sizeof(struct tcphdr)))
+ return ERR_PTR(-EINVAL);
+
++ if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++ return __tcp4_gso_segment_list(skb, features);
++
+ if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ const struct iphdr *iph = ip_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+@@ -178,61 +245,76 @@ out:
+ return segs;
+ }
+
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb)
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th)
+ {
+- struct sk_buff *pp = NULL;
++ struct tcphdr *th2;
+ struct sk_buff *p;
++
++ list_for_each_entry(p, head, list) {
++ if (!NAPI_GRO_CB(p)->same_flow)
++ continue;
++
++ th2 = tcp_hdr(p);
++ if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
++ NAPI_GRO_CB(p)->same_flow = 0;
++ continue;
++ }
++
++ return p;
++ }
++
++ return NULL;
++}
++
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb)
++{
++ unsigned int thlen, hlen, off;
+ struct tcphdr *th;
+- struct tcphdr *th2;
+- unsigned int len;
+- unsigned int thlen;
+- __be32 flags;
+- unsigned int mss = 1;
+- unsigned int hlen;
+- unsigned int off;
+- int flush = 1;
+- int i;
+
+ off = skb_gro_offset(skb);
+ hlen = off + sizeof(*th);
+ th = skb_gro_header(skb, hlen, off);
+ if (unlikely(!th))
+- goto out;
++ return NULL;
+
+ thlen = th->doff * 4;
+ if (thlen < sizeof(*th))
+- goto out;
++ return NULL;
+
+ hlen = off + thlen;
+ if (skb_gro_header_hard(skb, hlen)) {
+ th = skb_gro_header_slow(skb, hlen, off);
+ if (unlikely(!th))
+- goto out;
++ return NULL;
+ }
+
+ skb_gro_pull(skb, thlen);
+
+- len = skb_gro_len(skb);
+- flags = tcp_flag_word(th);
+-
+- list_for_each_entry(p, head, list) {
+- if (!NAPI_GRO_CB(p)->same_flow)
+- continue;
++ return th;
++}
+
+- th2 = tcp_hdr(p);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++ unsigned int thlen = th->doff * 4;
++ struct sk_buff *pp = NULL;
++ struct sk_buff *p;
++ struct tcphdr *th2;
++ unsigned int len;
++ __be32 flags;
++ unsigned int mss = 1;
++ int flush = 1;
++ int i;
+
+- if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
+- NAPI_GRO_CB(p)->same_flow = 0;
+- continue;
+- }
++ len = skb_gro_len(skb);
++ flags = tcp_flag_word(th);
+
+- goto found;
+- }
+- p = NULL;
+- goto out_check_final;
++ p = tcp_gro_lookup(head, th);
++ if (!p)
++ goto out_check_final;
+
+-found:
+ /* Include the IP ID check below from the inner most IP hdr */
++ th2 = tcp_hdr(p);
+ flush = NAPI_GRO_CB(p)->flush;
+ flush |= (__force int)(flags & TCP_FLAG_CWR);
+ flush |= (__force int)((flags ^ tcp_flag_word(th2)) &
+@@ -269,6 +351,19 @@ found:
+ flush |= p->decrypted ^ skb->decrypted;
+ #endif
+
++ if (unlikely(NAPI_GRO_CB(p)->is_flist)) {
++ flush |= (__force int)(flags ^ tcp_flag_word(th2));
++ flush |= skb->ip_summed != p->ip_summed;
++ flush |= skb->csum_level != p->csum_level;
++ flush |= !pskb_may_pull(skb, skb_gro_offset(skb));
++ flush |= NAPI_GRO_CB(p)->count >= 64;
++
++ if (flush || skb_gro_receive_list(p, skb))
++ mss = 1;
++
++ goto out_check_final;
++ }
++
+ if (flush || skb_gro_receive(p, skb)) {
+ mss = 1;
+ goto out_check_final;
+@@ -290,7 +385,6 @@ out_check_final:
+ if (p && (!NAPI_GRO_CB(skb)->same_flow || flush))
+ pp = p;
+
+-out:
+ NAPI_GRO_CB(skb)->flush |= (flush != 0);
+
+ return pp;
+@@ -314,18 +408,58 @@ void tcp_gro_complete(struct sk_buff *sk
+ }
+ EXPORT_SYMBOL(tcp_gro_complete);
+
++static void tcp4_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++ const struct iphdr *iph;
++ struct sk_buff *p;
++ struct sock *sk;
++ struct net *net;
++ int iif, sdif;
++
++ if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++ return;
++
++ p = tcp_gro_lookup(head, th);
++ if (p) {
++ NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++ return;
++ }
++
++ inet_get_iif_sdif(skb, &iif, &sdif);
++ iph = skb_gro_network_header(skb);
++ net = dev_net(skb->dev);
++ sk = __inet_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++ iph->saddr, th->source,
++ iph->daddr, ntohs(th->dest),
++ iif, sdif);
++ NAPI_GRO_CB(skb)->is_flist = !sk;
++ if (sk)
++ sock_put(sk);
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++ struct tcphdr *th;
++
+ /* Don't bother verifying checksum if we're going to flush anyway. */
+ if (!NAPI_GRO_CB(skb)->flush &&
+ skb_gro_checksum_validate(skb, IPPROTO_TCP,
+- inet_gro_compute_pseudo)) {
+- NAPI_GRO_CB(skb)->flush = 1;
+- return NULL;
+- }
++ inet_gro_compute_pseudo))
++ goto flush;
++
++ th = tcp_gro_pull_header(skb);
++ if (!th)
++ goto flush;
+
+- return tcp_gro_receive(head, skb);
++ tcp4_check_fraglist_gro(head, skb, th);
++
++ return tcp_gro_receive(head, skb, th);
++
++flush:
++ NAPI_GRO_CB(skb)->flush = 1;
++ return NULL;
+ }
+
+ INDIRECT_CALLABLE_SCOPE int tcp4_gro_complete(struct sk_buff *skb, int thoff)
+@@ -333,6 +467,15 @@ INDIRECT_CALLABLE_SCOPE int tcp4_gro_com
+ const struct iphdr *iph = ip_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+
++ if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++ skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV4;
++ skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++ __skb_incr_checksum_unnecessary(skb);
++
++ return 0;
++ }
++
+ th->check = ~tcp_v4_check(skb->len - thoff, iph->saddr,
+ iph->daddr, 0);
+ skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV4;
+--- a/net/ipv4/udp_offload.c
++++ b/net/ipv4/udp_offload.c
+@@ -433,33 +433,6 @@ out:
+ return segs;
+ }
+
+-static int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
+-{
+- if (unlikely(p->len + skb->len >= 65536))
+- return -E2BIG;
+-
+- if (NAPI_GRO_CB(p)->last == p)
+- skb_shinfo(p)->frag_list = skb;
+- else
+- NAPI_GRO_CB(p)->last->next = skb;
+-
+- skb_pull(skb, skb_gro_offset(skb));
+-
+- NAPI_GRO_CB(p)->last = skb;
+- NAPI_GRO_CB(p)->count++;
+- p->data_len += skb->len;
+-
+- /* sk ownership - if any - completely transferred to the aggregated packet */
+- skb->destructor = NULL;
+- skb->sk = NULL;
+- p->truesize += skb->truesize;
+- p->len += skb->len;
+-
+- NAPI_GRO_CB(skb)->same_flow = 1;
+-
+- return 0;
+-}
+-
+
+ #define UDP_GRO_CNT_MAX 64
+ static struct sk_buff *udp_gro_receive_segment(struct list_head *head,
+--- a/net/ipv6/tcpv6_offload.c
++++ b/net/ipv6/tcpv6_offload.c
+@@ -7,24 +7,67 @@
+ */
+ #include <linux/indirect_call_wrapper.h>
+ #include <linux/skbuff.h>
++#include <net/inet6_hashtables.h>
+ #include <net/gro.h>
+ #include <net/protocol.h>
+ #include <net/tcp.h>
+ #include <net/ip6_checksum.h>
+ #include "ip6_offload.h"
+
++static void tcp6_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++#if IS_ENABLED(CONFIG_IPV6)
++ const struct ipv6hdr *hdr;
++ struct sk_buff *p;
++ struct sock *sk;
++ struct net *net;
++ int iif, sdif;
++
++ if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++ return;
++
++ p = tcp_gro_lookup(head, th);
++ if (p) {
++ NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++ return;
++ }
++
++ inet6_get_iif_sdif(skb, &iif, &sdif);
++ hdr = skb_gro_network_header(skb);
++ net = dev_net(skb->dev);
++ sk = __inet6_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++ &hdr->saddr, th->source,
++ &hdr->daddr, ntohs(th->dest),
++ iif, sdif);
++ NAPI_GRO_CB(skb)->is_flist = !sk;
++ if (sk)
++ sock_put(sk);
++#endif /* IS_ENABLED(CONFIG_IPV6) */
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp6_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++ struct tcphdr *th;
++
+ /* Don't bother verifying checksum if we're going to flush anyway. */
+ if (!NAPI_GRO_CB(skb)->flush &&
+ skb_gro_checksum_validate(skb, IPPROTO_TCP,
+- ip6_gro_compute_pseudo)) {
+- NAPI_GRO_CB(skb)->flush = 1;
+- return NULL;
+- }
++ ip6_gro_compute_pseudo))
++ goto flush;
+
+- return tcp_gro_receive(head, skb);
++ th = tcp_gro_pull_header(skb);
++ if (!th)
++ goto flush;
++
++ tcp6_check_fraglist_gro(head, skb, th);
++
++ return tcp_gro_receive(head, skb, th);
++
++flush:
++ NAPI_GRO_CB(skb)->flush = 1;
++ return NULL;
+ }
+
+ INDIRECT_CALLABLE_SCOPE int tcp6_gro_complete(struct sk_buff *skb, int thoff)
+@@ -32,6 +75,15 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ const struct ipv6hdr *iph = ipv6_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+
++ if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++ skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV6;
++ skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++ __skb_incr_checksum_unnecessary(skb);
++
++ return 0;
++ }
++
+ th->check = ~tcp_v6_check(skb->len - thoff, &iph->saddr,
+ &iph->daddr, 0);
+ skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV6;
+@@ -40,6 +92,61 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ return 0;
+ }
+
++static void __tcpv6_gso_segment_csum(struct sk_buff *seg,
++ __be16 *oldport, __be16 newport)
++{
++ struct tcphdr *th;
++
++ if (*oldport == newport)
++ return;
++
++ th = tcp_hdr(seg);
++ inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++ *oldport = newport;
++}
++
++static struct sk_buff *__tcpv6_gso_segment_list_csum(struct sk_buff *segs)
++{
++ const struct tcphdr *th;
++ const struct ipv6hdr *iph;
++ struct sk_buff *seg;
++ struct tcphdr *th2;
++ struct ipv6hdr *iph2;
++
++ seg = segs;
++ th = tcp_hdr(seg);
++ iph = ipv6_hdr(seg);
++ th2 = tcp_hdr(seg->next);
++ iph2 = ipv6_hdr(seg->next);
++
++ if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++ ipv6_addr_equal(&iph->saddr, &iph2->saddr) &&
++ ipv6_addr_equal(&iph->daddr, &iph2->daddr))
++ return segs;
++
++ while ((seg = seg->next)) {
++ th2 = tcp_hdr(seg);
++ iph2 = ipv6_hdr(seg);
++
++ iph2->saddr = iph->saddr;
++ iph2->daddr = iph->daddr;
++ __tcpv6_gso_segment_csum(seg, &th2->source, th->source);
++ __tcpv6_gso_segment_csum(seg, &th2->dest, th->dest);
++ }
++
++ return segs;
++}
++
++static struct sk_buff *__tcp6_gso_segment_list(struct sk_buff *skb,
++ netdev_features_t features)
++{
++ skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++ if (IS_ERR(skb))
++ return skb;
++
++ return __tcpv6_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp6_gso_segment(struct sk_buff *skb,
+ netdev_features_t features)
+ {
+@@ -51,6 +158,9 @@ static struct sk_buff *tcp6_gso_segment(
+ if (!pskb_may_pull(skb, sizeof(*th)))
+ return ERR_PTR(-EINVAL);
+
++ if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++ return __tcp6_gso_segment_list(skb, features);
++
+ if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ const struct ipv6hdr *ipv6h = ipv6_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 27 Apr 2024 18:54:25 +0200
+Subject: [PATCH] net: bridge: fix multicast-to-unicast with fraglist GSO
+
+Calling skb_copy on a SKB_GSO_FRAGLIST skb is not valid, since it returns
+an invalid linearized skb. This code only needs to change the ethernet
+header, so pskb_copy is the right function to call here.
+
+Fixes: 6db6f0eae605 ("bridge: multicast to unicast")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/bridge/br_forward.c
++++ b/net/bridge/br_forward.c
+@@ -266,7 +266,7 @@ static void maybe_deliver_addr(struct ne
+ if (skb->dev == p->dev && ether_addr_equal(src, addr))
+ return;
+
+- skb = skb_copy(skb, GFP_ATOMIC);
++ skb = pskb_copy(skb, GFP_ATOMIC);
+ if (!skb) {
+ DEV_STATS_INC(dev, tx_dropped);
+ return;
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 27 Apr 2024 19:29:45 +0200
+Subject: [PATCH] net: core: reject skb_copy(_expand) for fraglist GSO skbs
+
+SKB_GSO_FRAGLIST skbs must not be linearized, otherwise they become
+invalid. Return NULL if such an skb is passed to skb_copy or
+skb_copy_expand, in order to prevent a crash on a potential later
+call to skb_gso_segment.
+
+Fixes: 3a1296a38d0c ("net: Support GRO/GSO fraglist chaining.")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/core/skbuff.c
++++ b/net/core/skbuff.c
+@@ -1971,11 +1971,17 @@ static inline int skb_alloc_rx_flag(cons
+
+ struct sk_buff *skb_copy(const struct sk_buff *skb, gfp_t gfp_mask)
+ {
+- int headerlen = skb_headroom(skb);
+- unsigned int size = skb_end_offset(skb) + skb->data_len;
+- struct sk_buff *n = __alloc_skb(size, gfp_mask,
+- skb_alloc_rx_flag(skb), NUMA_NO_NODE);
++ struct sk_buff *n;
++ unsigned int size;
++ int headerlen;
+
++ if (WARN_ON_ONCE(skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST))
++ return NULL;
++
++ headerlen = skb_headroom(skb);
++ size = skb_end_offset(skb) + skb->data_len;
++ n = __alloc_skb(size, gfp_mask,
++ skb_alloc_rx_flag(skb), NUMA_NO_NODE);
+ if (!n)
+ return NULL;
+
+@@ -2303,12 +2309,17 @@ struct sk_buff *skb_copy_expand(const st
+ /*
+ * Allocate the copy buffer
+ */
+- struct sk_buff *n = __alloc_skb(newheadroom + skb->len + newtailroom,
+- gfp_mask, skb_alloc_rx_flag(skb),
+- NUMA_NO_NODE);
+- int oldheadroom = skb_headroom(skb);
+ int head_copy_len, head_copy_off;
++ struct sk_buff *n;
++ int oldheadroom;
++
++ if (WARN_ON_ONCE(skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST))
++ return NULL;
+
++ oldheadroom = skb_headroom(skb);
++ n = __alloc_skb(newheadroom + skb->len + newtailroom,
++ gfp_mask, skb_alloc_rx_flag(skb),
++ NUMA_NO_NODE);
+ if (!n)
+ return NULL;
+
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sun, 5 May 2024 20:36:56 +0200
+Subject: [PATCH] net: bridge: fix corrupted ethernet header on
+ multicast-to-unicast
+
+The change from skb_copy to pskb_copy unfortunately changed the data
+copying to omit the ethernet header, since it was pulled before reaching
+this point. Fix this by calling __skb_push/pull around pskb_copy.
+
+Fixes: 59c878cbcdd8 ("net: bridge: fix multicast-to-unicast with fraglist GSO")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/bridge/br_forward.c
++++ b/net/bridge/br_forward.c
+@@ -258,6 +258,7 @@ static void maybe_deliver_addr(struct ne
+ {
+ struct net_device *dev = BR_INPUT_SKB_CB(skb)->brdev;
+ const unsigned char *src = eth_hdr(skb)->h_source;
++ struct sk_buff *nskb;
+
+ if (!should_deliver(p, skb))
+ return;
+@@ -266,12 +267,16 @@ static void maybe_deliver_addr(struct ne
+ if (skb->dev == p->dev && ether_addr_equal(src, addr))
+ return;
+
+- skb = pskb_copy(skb, GFP_ATOMIC);
+- if (!skb) {
++ __skb_push(skb, ETH_HLEN);
++ nskb = pskb_copy(skb, GFP_ATOMIC);
++ __skb_pull(skb, ETH_HLEN);
++ if (!nskb) {
+ DEV_STATS_INC(dev, tx_dropped);
+ return;
+ }
+
++ skb = nskb;
++ __skb_pull(skb, ETH_HLEN);
+ if (!is_broadcast_ether_addr(addr))
+ memcpy(eth_hdr(skb)->h_dest, addr, ETH_ALEN);
+
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
-@@ -8221,7 +8221,7 @@ static int nft_register_flowtable_net_ho
+@@ -8268,7 +8268,7 @@ static int nft_register_flowtable_net_ho
err = flowtable->data.type->setup(&flowtable->data,
hook->ops.dev,
FLOW_BLOCK_BIND);
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
-@@ -1900,6 +1900,9 @@ void phy_detach(struct phy_device *phyde
+@@ -1908,6 +1908,9 @@ void phy_detach(struct phy_device *phyde
if (phydev->devlink)
device_link_del(phydev->devlink);
if (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev)
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
-@@ -362,6 +362,8 @@ static rx_handler_result_t br_handle_fra
+@@ -367,6 +367,8 @@ static rx_handler_result_t br_handle_fra
fwd_mask |= p->group_fwd_mask;
switch (dest[5]) {
case 0x00: /* Bridge Group Address */
+++ /dev/null
-From 3fb8841513c4ec3a2e5d366df86230c45f239a57 Mon Sep 17 00:00:00 2001
-From: Alexander Couzens <lynxis@fe80.eu>
-Date: Sat, 13 Aug 2022 13:08:22 +0200
-Subject: [PATCH 03/10] net: mt7531: ensure all MACs are powered down before
- reset
-
-The datasheet [1] explicit describes it as requirement for a reset.
-
-[1] MT7531 Reference Manual for Development Board rev 1.0, page 735
-
-Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
----
- drivers/net/dsa/mt7530.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2304,6 +2304,10 @@ mt7530_setup(struct dsa_switch *ds)
- return -ENODEV;
- }
-
-+ /* all MACs must be forced link-down before sw reset */
-+ for (i = 0; i < MT7530_NUM_PORTS; i++)
-+ mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
-+
- /* Reset the switch through internal reset */
- mt7530_write(priv, MT7530_SYS_CTRL,
- SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
-From e52faf1564a8bcaf866f9a6c7bf0e8a8748afb15 Mon Sep 17 00:00:00 2001
+From 0de82310d2b32e78ff79d42c08b1122a6ede3778 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Sun, 30 Apr 2023 00:15:41 +0100
Subject: [PATCH] net: phy: realtek: detect early version of RTL8221B
over the implemented MMDs.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/realtek.c | 50 ++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 49 insertions(+), 1 deletion(-)
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
#define RTL_GENERIC_PHYID 0x001cc800
#define RTL_8211FVD_PHYID 0x001cc878
-+#define RTL_8221B_VB_CG 0x001cc849
++#define RTL_8221B_VB_CG_PHYID 0x001cc849
MODULE_DESCRIPTION("Realtek PHY driver");
MODULE_AUTHOR("Johnson Leung");
-@@ -801,6 +802,54 @@ static int rtl822x_probe(struct phy_devi
- return 0;
+@@ -782,6 +783,38 @@ static int rtl8226_match_phy_device(stru
+ rtlgen_supports_2_5gbps(phydev);
}
+static int rtl8221b_vb_cg_match_phy_device(struct phy_device *phydev)
+ int val;
+ u32 id;
+
-+ if (phydev->is_c45) {
-+ if (phydev->c45_ids.device_ids[1])
-+ return phydev->c45_ids.device_ids[1] == RTL_8221B_VB_CG;
-+ } else {
-+ if (phydev->phy_id)
-+ return phydev->phy_id == RTL_8221B_VB_CG;
-+ }
-+
+ if (phydev->mdio.bus->read_c45) {
+ val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PKGID1);
+ if (val < 0)
+ id |= val;
+ }
+
-+ if (id != RTL_8221B_VB_CG)
-+ return 0;
-+
-+ if (phydev->is_c45)
-+ phydev->c45_ids.device_ids[1] = id;
-+ else
-+ phydev->phy_id = id;
-+
-+ return 1;
++ return (id == RTL_8221B_VB_CG_PHYID);
+}
+
- static int rtlgen_resume(struct phy_device *phydev)
+ static int rtl822x_probe(struct phy_device *phydev)
{
- int ret = genphy_resume(phydev);
-@@ -1134,7 +1183,7 @@ static struct phy_driver realtek_drvs[]
+ struct device *dev = &phydev->mdio.dev;
+@@ -1134,7 +1167,7 @@ static struct phy_driver realtek_drvs[]
.write_page = rtl821x_write_page,
.soft_reset = genphy_soft_reset,
}, {
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
-@@ -2245,7 +2245,7 @@ struct net_device {
+@@ -2243,7 +2243,7 @@ struct net_device {
#if IS_ENABLED(CONFIG_AX25)
void *ax25_ptr;
#endif
+From d7943c31d57c11e1a517aa3ce2006fca44866870 Mon Sep 17 00:00:00 2001
+From: Jianhui Zhao <zhaojh329@gmail.com>
+Date: Sun, 24 Sep 2023 22:15:00 +0800
+Subject: [PATCH] net: phy: realtek: add interrupt support for RTL8221B
+
+This commit introduces interrupt support for RTL8221B.
+
+Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
+---
+ drivers/net/phy/realtek.c | 47 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
-@@ -1026,6 +1026,51 @@ static int rtl8221b_config_init(struct p
+@@ -1010,6 +1010,51 @@ static int rtl8221b_config_init(struct p
return 0;
}
static struct phy_driver realtek_drvs[] = {
{
PHY_ID_MATCH_EXACT(0x00008201),
-@@ -1188,6 +1233,8 @@ static struct phy_driver realtek_drvs[]
+@@ -1172,6 +1217,8 @@ static struct phy_driver realtek_drvs[]
.get_features = rtl822x_get_features,
.config_init = rtl8221b_config_init,
.config_aneg = rtl822x_config_aneg,
--- /dev/null
+From 9be9a00adfac8118b6d685e71696f83187308c66 Mon Sep 17 00:00:00 2001
+Message-ID: <9be9a00adfac8118b6d685e71696f83187308c66.1715125851.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 7 May 2024 22:43:30 +0100
+Subject: [PATCH net] net: phy: air_en8811h: reset netdev rules when LED is set
+ manually
+To: Andrew Lunn <andrew@lunn.ch>,
+ Heiner Kallweit <hkallweit1@gmail.com>,
+ Russell King <linux@armlinux.org.uk>,
+ David S. Miller <davem@davemloft.net>,
+ Eric Dumazet <edumazet@google.com>,
+ Jakub Kicinski <kuba@kernel.org>,
+ Paolo Abeni <pabeni@redhat.com>,
+ SkyLake Huang <skylake.huang@mediatek.com>,
+ Eric Woudstra <ericwouds@gmail.com>,
+ netdev@vger.kernel.org,
+ linux-kernel@vger.kernel.org
+
+Setting LED_OFF via the brightness_set should deactivate hw control,
+so make sure netdev trigger rules also get cleared in that case.
+
+Fixes: 71e79430117d ("net: phy: air_en8811h: Add the Airoha EN8811H PHY driver")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+This is basically a stop-gap measure until unified LED handling has
+been implemented accross all MediaTek and Airoha PHYs.
+See also
+https://patchwork.kernel.org/project/netdevbpf/patch/20240425023325.15586-3-SkyLake.Huang@mediatek.com/
+
+ drivers/net/phy/air_en8811h.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/net/phy/air_en8811h.c
++++ b/drivers/net/phy/air_en8811h.c
+@@ -544,6 +544,10 @@ static int air_hw_led_on_set(struct phy_
+
+ changed |= (priv->led[index].rules != 0);
+
++ /* clear netdev trigger rules in case LED_OFF has been set */
++ if (!on)
++ priv->led[index].rules = 0;
++
+ if (changed)
+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
+ AIR_PHY_LED_ON(index),
+++ /dev/null
-From patchwork Tue Feb 6 19:47:51 2024
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Eric Woudstra <ericwouds@gmail.com>
-X-Patchwork-Id: 13547762
-X-Patchwork-Delegate: kuba@kernel.org
-From: Eric Woudstra <ericwouds@gmail.com>
-To: "David S. Miller" <davem@davemloft.net>,
- Eric Dumazet <edumazet@google.com>,
- Jakub Kicinski <kuba@kernel.org>,
- Paolo Abeni <pabeni@redhat.com>,
- Rob Herring <robh+dt@kernel.org>,
- Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
- Conor Dooley <conor+dt@kernel.org>,
- Andrew Lunn <andrew@lunn.ch>,
- Heiner Kallweit <hkallweit1@gmail.com>,
- Russell King <linux@armlinux.org.uk>,
- Matthias Brugger <matthias.bgg@gmail.com>,
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
- "Frank Wunderlich" <frank-w@public-files.de>,
- Daniel Golle <daniel@makrotopia.org>,
- Lucien Jheng <lucien.jheng@airoha.com>,
- Zhi-Jun You <hujy652@protonmail.com>
-Cc: netdev@vger.kernel.org,
- devicetree@vger.kernel.org,
- Eric Woudstra <ericwouds@gmail.com>
-Subject: [PATCH net-next 2/2] net: phy: air_en8811h: Add the Airoha EN8811H
- PHY driver
-Date: Tue, 6 Feb 2024 20:47:51 +0100
-Message-ID: <20240206194751.1901802-3-ericwouds@gmail.com>
-X-Mailer: git-send-email 2.42.1
-In-Reply-To: <20240206194751.1901802-1-ericwouds@gmail.com>
-References: <20240206194751.1901802-1-ericwouds@gmail.com>
-Precedence: bulk
-X-Mailing-List: netdev@vger.kernel.org
-List-Id: <netdev.vger.kernel.org>
-List-Subscribe: <mailto:netdev+subscribe@vger.kernel.org>
-List-Unsubscribe: <mailto:netdev+unsubscribe@vger.kernel.org>
-MIME-Version: 1.0
-X-Patchwork-Delegate: kuba@kernel.org
-
-* Source originated from airoha's en8811h v1.2.1 driver
- * Moved air_en8811h.h to air_en8811h.c
- * Removed air_pbus_reg_write() as it writes to another device on mdio-bus
- * Load firmware from /lib/firmware/airoha/ instead of /lib/firmware/
- * Added .get_rate_matching()
- * Use generic phy_read/write() and phy_read/write_mmd()
- * Edited .get_features() to use generic C45 functions
- * Edited .config_aneg() and .read_status() to use a mix of generic C22/C45
- * Use led handling functions from mediatek-ge-soc.c
- * Simplified led handling by storing led rules
- * Cleanup macro definitions
- * Cleanup code to pass checkpatch.pl
- * General code cleanup
-
-Changes from original RFC patch:
-
- * Use the correct order in Kconfig and Makefile
- * Change some register naming to correspond with datasheet
- * Use phy_driver .read_page() and .write_page()
- * Use module_phy_driver()
- * Use get_unaligned_le16() instead of macro
- * In .config_aneg() and .read_status() use genphy_xxx() C22
- * Use another vendor register to read real speed
- * Load firmware only once and store firmware version
- * Apply 2.5G LPA work-around (firmware before 24011202)
- * Read 2.5G LPA from vendor register (firmware 24011202 and later)
-
-Changes to be committed:
- modified: drivers/net/phy/Kconfig
- modified: drivers/net/phy/Makefile
- new file: drivers/net/phy/air_en8811h.c
-
-Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
----
- drivers/net/phy/Kconfig | 5 +
- drivers/net/phy/Makefile | 1 +
- drivers/net/phy/air_en8811h.c | 1006 +++++++++++++++++++++++++++++++++
- 3 files changed, 1012 insertions(+)
- create mode 100644 drivers/net/phy/air_en8811h.c
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -68,6 +68,11 @@ config SFP
-
- comment "MII PHY device drivers"
-
-+config AIR_EN8811H_PHY
-+ tristate "Airoha EN8811H 2.5 Gigabit PHY"
-+ help
-+ Currently supports the Airoha EN8811H PHY.
-+
- config AMD_PHY
- tristate "AMD and Altima PHYs"
- help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -34,6 +34,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
-
- obj-$(CONFIG_ADIN_PHY) += adin.o
- obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
-+obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
- obj-$(CONFIG_AMD_PHY) += amd.o
- obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
- obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
---- /dev/null
-+++ b/drivers/net/phy/air_en8811h.c
-@@ -0,0 +1,1006 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Driver for Airoha Ethernet PHYs
-+ *
-+ * Currently supporting the EN8811H.
-+ *
-+ * Limitations of the EN8811H:
-+ * - Only full duplex supported
-+ * - Forced speed (AN off) is not supported by hardware (100Mbps)
-+ *
-+ * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
-+ *
-+ * Copyright (C) 2023 Airoha Technology Corp.
-+ */
-+
-+#include <linux/phy.h>
-+#include <linux/firmware.h>
-+#include <linux/property.h>
-+#include <asm/unaligned.h>
-+
-+#define EN8811H_PHY_ID 0x03a2a411
-+
-+#define EN8811H_MD32_DM "airoha/EthMD32.dm.bin"
-+#define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin"
-+
-+#define AIR_FW_ADDR_DM 0x00000000
-+#define AIR_FW_ADDR_DSP 0x00100000
-+
-+/* u32 (DWORD) component macros */
-+#define LOWORD(d) ((u16)(u32)(d))
-+#define HIWORD(d) ((u16)(((u32)(d)) >> 16))
-+
-+/* MII Registers */
-+#define AIR_AUX_CTRL_STATUS 0x1d
-+#define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2)
-+#define AIR_AUX_CTRL_STATUS_SPEED_100 0x4
-+#define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8
-+#define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc
-+
-+#define AIR_EXT_PAGE_ACCESS 0x1f
-+#define AIR_PHY_PAGE_STANDARD 0x0000
-+#define AIR_PHY_PAGE_EXTENDED_4 0x0004
-+
-+/* MII Registers Page 4*/
-+#define AIR_PBUS_MODE 0x10
-+#define AIR_PBUS_MODE_ADDR_FIXED 0x0000
-+#define AIR_PBUS_MODE_ADDR_INCR BIT(15)
-+#define AIR_PBUS_WR_ADDR_HIGH 0x11
-+#define AIR_PBUS_WR_ADDR_LOW 0x12
-+#define AIR_PBUS_WR_DATA_HIGH 0x13
-+#define AIR_PBUS_WR_DATA_LOW 0x14
-+#define AIR_PBUS_RD_ADDR_HIGH 0x15
-+#define AIR_PBUS_RD_ADDR_LOW 0x16
-+#define AIR_PBUS_RD_DATA_HIGH 0x17
-+#define AIR_PBUS_RD_DATA_LOW 0x18
-+
-+/* Registers on MDIO_MMD_VEND1 */
-+#define EN8811H_PHY_FW_STATUS 0x8009
-+#define EN8811H_PHY_READY 0x02
-+
-+#define AIR_PHY_HOST_CMD_1 0x800c
-+#define AIR_PHY_HOST_CMD_1_MODE1 0x0
-+#define AIR_PHY_HOST_CMD_2 0x800d
-+#define AIR_PHY_HOST_CMD_2_MODE1 0x0
-+#define AIR_PHY_HOST_CMD_3 0x800e
-+#define AIR_PHY_HOST_CMD_3_MODE1 0x1101
-+#define AIR_PHY_HOST_CMD_3_DOCMD 0x1100
-+#define AIR_PHY_HOST_CMD_4 0x800f
-+#define AIR_PHY_HOST_CMD_4_MODE1 0x0002
-+#define AIR_PHY_HOST_CMD_4_INTCLR 0x00e4
-+
-+/* Registers on MDIO_MMD_VEND2 */
-+#define AIR_PHY_LED_BCR 0x021
-+#define AIR_PHY_LED_BCR_MODE_MASK GENMASK(1, 0)
-+#define AIR_PHY_LED_BCR_TIME_TEST BIT(2)
-+#define AIR_PHY_LED_BCR_CLK_EN BIT(3)
-+#define AIR_PHY_LED_BCR_EXT_CTRL BIT(15)
-+
-+#define AIR_PHY_LED_DUR_ON 0x022
-+
-+#define AIR_PHY_LED_DUR_BLINK 0x023
-+
-+#define AIR_PHY_LED_ON(i) (0x024 + ((i) * 2))
-+#define AIR_PHY_LED_ON_MASK (GENMASK(6, 0) | BIT(8))
-+#define AIR_PHY_LED_ON_LINK1000 BIT(0)
-+#define AIR_PHY_LED_ON_LINK100 BIT(1)
-+#define AIR_PHY_LED_ON_LINK10 BIT(2)
-+#define AIR_PHY_LED_ON_LINKDOWN BIT(3)
-+#define AIR_PHY_LED_ON_FDX BIT(4) /* Full duplex */
-+#define AIR_PHY_LED_ON_HDX BIT(5) /* Half duplex */
-+#define AIR_PHY_LED_ON_FORCE_ON BIT(6)
-+#define AIR_PHY_LED_ON_LINK2500 BIT(8)
-+#define AIR_PHY_LED_ON_POLARITY BIT(14)
-+#define AIR_PHY_LED_ON_ENABLE BIT(15)
-+
-+#define AIR_PHY_LED_BLINK(i) (0x025 + ((i) * 2))
-+#define AIR_PHY_LED_BLINK_1000TX BIT(0)
-+#define AIR_PHY_LED_BLINK_1000RX BIT(1)
-+#define AIR_PHY_LED_BLINK_100TX BIT(2)
-+#define AIR_PHY_LED_BLINK_100RX BIT(3)
-+#define AIR_PHY_LED_BLINK_10TX BIT(4)
-+#define AIR_PHY_LED_BLINK_10RX BIT(5)
-+#define AIR_PHY_LED_BLINK_COLLISION BIT(6)
-+#define AIR_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
-+#define AIR_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
-+#define AIR_PHY_LED_BLINK_FORCE_BLINK BIT(9)
-+#define AIR_PHY_LED_BLINK_2500TX BIT(10)
-+#define AIR_PHY_LED_BLINK_2500RX BIT(11)
-+
-+/* Registers on BUCKPBUS */
-+#define EN8811H_2P5G_LPA 0x3b30
-+#define EN8811H_2P5G_LPA_2P5G BIT(0)
-+
-+#define EN8811H_FW_VERSION 0x3b3c
-+
-+#define EN8811H_POLARITY 0xca0f8
-+#define EN8811H_POLARITY_TX_NORMAL BIT(0)
-+#define EN8811H_POLARITY_RX_REVERSE BIT(1)
-+
-+#define EN8811H_GPIO_OUTPUT 0xcf8b8
-+#define EN8811H_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5))
-+
-+#define EN8811H_FW_CTRL_1 0x0f0018
-+#define EN8811H_FW_CTRL_1_START 0x0
-+#define EN8811H_FW_CTRL_1_FINISH 0x1
-+#define EN8811H_FW_CTRL_2 0x800000
-+#define EN8811H_FW_CTRL_2_LOADING BIT(11)
-+
-+#define EN8811H_LED_COUNT 3
-+
-+/* GPIO5 <-> BASE_T_LED0
-+ * GPIO4 <-> BASE_T_LED1
-+ * GPIO3 <-> BASE_T_LED2
-+ *
-+ * Default setup suitable for 2 leds connected:
-+ * 100M link up triggers led0, only led0 blinking on traffic
-+ * 1000M link up triggers led1, only led1 blinking on traffic
-+ * 2500M link up triggers led0 and led1, both blinking on traffic
-+ * Also suitable for 1 led connected:
-+ * any link up triggers led2
-+ */
-+#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK_2500) | \
-+ BIT(TRIGGER_NETDEV_LINK_100) | \
-+ BIT(TRIGGER_NETDEV_RX) | \
-+ BIT(TRIGGER_NETDEV_TX))
-+#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
-+ BIT(TRIGGER_NETDEV_LINK_1000) | \
-+ BIT(TRIGGER_NETDEV_RX) | \
-+ BIT(TRIGGER_NETDEV_TX))
-+#define AIR_DEFAULT_TRIGGER_LED2 BIT(TRIGGER_NETDEV_LINK)
-+
-+struct led {
-+ unsigned long rules;
-+ unsigned long state;
-+};
-+
-+struct en8811h_priv {
-+ u32 firmware_version;
-+ struct led led[EN8811H_LED_COUNT];
-+};
-+
-+enum {
-+ AIR_PHY_LED_STATE_FORCE_ON,
-+ AIR_PHY_LED_STATE_FORCE_BLINK,
-+};
-+
-+enum {
-+ AIR_PHY_LED_DUR_BLINK_32M,
-+ AIR_PHY_LED_DUR_BLINK_64M,
-+ AIR_PHY_LED_DUR_BLINK_128M,
-+ AIR_PHY_LED_DUR_BLINK_256M,
-+ AIR_PHY_LED_DUR_BLINK_512M,
-+ AIR_PHY_LED_DUR_BLINK_1024M,
-+};
-+
-+enum {
-+ AIR_LED_DISABLE,
-+ AIR_LED_ENABLE,
-+};
-+
-+enum {
-+ AIR_ACTIVE_LOW,
-+ AIR_ACTIVE_HIGH,
-+};
-+
-+enum {
-+ AIR_LED_MODE_DISABLE,
-+ AIR_LED_MODE_USER_DEFINE,
-+};
-+
-+#define AIR_PHY_LED_DUR_UNIT 1024
-+#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64M)
-+
-+static const unsigned long en8811h_led_trig = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
-+ BIT(TRIGGER_NETDEV_LINK) |
-+ BIT(TRIGGER_NETDEV_LINK_10) |
-+ BIT(TRIGGER_NETDEV_LINK_100) |
-+ BIT(TRIGGER_NETDEV_LINK_1000) |
-+ BIT(TRIGGER_NETDEV_LINK_2500) |
-+ BIT(TRIGGER_NETDEV_RX) |
-+ BIT(TRIGGER_NETDEV_TX));
-+
-+static int air_phy_read_page(struct phy_device *phydev)
-+{
-+ return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
-+}
-+
-+static int air_phy_write_page(struct phy_device *phydev, int page)
-+{
-+ return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
-+}
-+
-+static int __air_buckpbus_reg_write(struct phy_device *phydev,
-+ u32 pbus_address, u32 pbus_data)
-+{
-+ int ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(pbus_address));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW, LOWORD(pbus_address));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, HIWORD(pbus_data));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, LOWORD(pbus_data));
-+ if (ret < 0)
-+ return ret;
-+
-+ return 0;
-+}
-+
-+static int air_buckpbus_reg_write(struct phy_device *phydev,
-+ u32 pbus_address, u32 pbus_data)
-+{
-+ int ret, saved_page;
-+
-+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+ ret = __air_buckpbus_reg_write(phydev, pbus_address, pbus_data);
-+ if (ret < 0)
-+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+ pbus_address, ret);
-+
-+ return phy_restore_page(phydev, saved_page, ret);
-+;
-+}
-+
-+static int __air_buckpbus_reg_read(struct phy_device *phydev,
-+ u32 pbus_address, u32 *pbus_data)
-+{
-+ int pbus_data_low, pbus_data_high;
-+ int ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_HIGH, HIWORD(pbus_address));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_LOW, LOWORD(pbus_address));
-+ if (ret < 0)
-+ return ret;
-+
-+ pbus_data_high = __phy_read(phydev, AIR_PBUS_RD_DATA_HIGH);
-+ if (pbus_data_high < 0)
-+ return ret;
-+
-+ pbus_data_low = __phy_read(phydev, AIR_PBUS_RD_DATA_LOW);
-+ if (pbus_data_low < 0)
-+ return ret;
-+
-+ *pbus_data = (u16)pbus_data_low | ((u32)(u16)pbus_data_high << 16);
-+ return 0;
-+}
-+
-+static int air_buckpbus_reg_read(struct phy_device *phydev,
-+ u32 pbus_address, u32 *pbus_data)
-+{
-+ int ret, saved_page;
-+
-+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+ ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
-+ if (ret < 0)
-+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+ pbus_address, ret);
-+
-+ return phy_restore_page(phydev, saved_page, ret);
-+}
-+
-+static int __air_write_buf(struct phy_device *phydev, u32 address,
-+ const struct firmware *fw)
-+{
-+ unsigned int offset;
-+ int ret;
-+ u16 val;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_INCR);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(address));
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW, LOWORD(address));
-+ if (ret < 0)
-+ return ret;
-+
-+ for (offset = 0; offset < fw->size; offset += 4) {
-+ val = get_unaligned_le16(&fw->data[offset + 2]);
-+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, val);
-+ if (ret < 0)
-+ return ret;
-+
-+ val = get_unaligned_le16(&fw->data[offset]);
-+ ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, val);
-+ if (ret < 0)
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int air_write_buf(struct phy_device *phydev, u32 address,
-+ const struct firmware *fw)
-+{
-+ int ret, saved_page;
-+
-+ saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
-+
-+ ret = __air_write_buf(phydev, address, fw);
-+ if (ret < 0)
-+ phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
-+ address, ret);
-+
-+ return phy_restore_page(phydev, saved_page, ret);
-+}
-+
-+static int en8811h_load_firmware(struct phy_device *phydev)
-+{
-+ struct device *dev = &phydev->mdio.dev;
-+ const struct firmware *fw1, *fw2;
-+ u32 pbus_value;
-+ int ret;
-+
-+ ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_rel1;
-+
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+ EN8811H_FW_CTRL_1_START);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+ pbus_value |= EN8811H_FW_CTRL_2_LOADING;
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = air_write_buf(phydev, AIR_FW_ADDR_DM, fw1);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+ pbus_value &= ~EN8811H_FW_CTRL_2_LOADING;
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+ EN8811H_FW_CTRL_1_FINISH);
-+ if (ret < 0)
-+ goto en8811h_load_firmware_out;
-+
-+ ret = 0;
-+
-+en8811h_load_firmware_out:
-+ release_firmware(fw2);
-+
-+en8811h_load_firmware_rel1:
-+ release_firmware(fw1);
-+
-+ if (ret < 0)
-+ phydev_err(phydev, "Load firmware failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int en8811h_restart_host(struct phy_device *phydev)
-+{
-+ int ret;
-+
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+ EN8811H_FW_CTRL_1_START);
-+ if (ret < 0)
-+ return ret;
-+
-+ return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
-+ EN8811H_FW_CTRL_1_FINISH);
-+}
-+
-+static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ bool changed;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ if (on)
-+ changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
-+ &priv->led[index].state);
-+ else
-+ changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
-+ &priv->led[index].state);
-+
-+ changed |= (priv->led[index].rules != 0);
-+
-+ if (changed)
-+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
-+ AIR_PHY_LED_ON(index),
-+ AIR_PHY_LED_ON_MASK,
-+ on ? AIR_PHY_LED_ON_FORCE_ON : 0);
-+
-+ return 0;
-+}
-+
-+static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
-+ bool blinking)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ bool changed;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ if (blinking)
-+ changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
-+ &priv->led[index].state);
-+ else
-+ changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
-+ &priv->led[index].state);
-+
-+ changed |= (priv->led[index].rules != 0);
-+
-+ if (changed)
-+ return phy_write_mmd(phydev, MDIO_MMD_VEND2,
-+ AIR_PHY_LED_BLINK(index),
-+ blinking ?
-+ AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
-+ else
-+ return 0;
-+}
-+
-+static int air_led_blink_set(struct phy_device *phydev, u8 index,
-+ unsigned long *delay_on,
-+ unsigned long *delay_off)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ bool blinking = false;
-+ int err;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
-+ blinking = true;
-+ *delay_on = 50;
-+ *delay_off = 50;
-+ }
-+
-+ err = air_hw_led_blink_set(phydev, index, blinking);
-+ if (err)
-+ return err;
-+
-+ /* led-blink set, so switch led-on off */
-+ err = air_hw_led_on_set(phydev, index, false);
-+ if (err)
-+ return err;
-+
-+ /* hw-control is off*/
-+ if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
-+ priv->led[index].rules = 0;
-+
-+ return 0;
-+}
-+
-+static int air_led_brightness_set(struct phy_device *phydev, u8 index,
-+ enum led_brightness value)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ int err;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ /* led-on set, so switch led-blink off */
-+ err = air_hw_led_blink_set(phydev, index, false);
-+ if (err)
-+ return err;
-+
-+ err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
-+ if (err)
-+ return err;
-+
-+ /* hw-control is off */
-+ if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
-+ priv->led[index].rules = 0;
-+
-+ return 0;
-+}
-+
-+static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
-+ unsigned long *rules)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ *rules = priv->led[index].rules;
-+
-+ return 0;
-+};
-+
-+static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
-+ unsigned long rules)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ u16 on = 0, blink = 0;
-+ int ret;
-+
-+ priv->led[index].rules = rules;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK))) {
-+ on |= AIR_PHY_LED_ON_LINK10;
-+ if (rules & BIT(TRIGGER_NETDEV_RX))
-+ blink |= AIR_PHY_LED_BLINK_10RX;
-+ if (rules & BIT(TRIGGER_NETDEV_TX))
-+ blink |= AIR_PHY_LED_BLINK_10TX;
-+ }
-+
-+ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK))) {
-+ on |= AIR_PHY_LED_ON_LINK100;
-+ if (rules & BIT(TRIGGER_NETDEV_RX))
-+ blink |= AIR_PHY_LED_BLINK_100RX;
-+ if (rules & BIT(TRIGGER_NETDEV_TX))
-+ blink |= AIR_PHY_LED_BLINK_100TX;
-+ }
-+
-+ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) {
-+ on |= AIR_PHY_LED_ON_LINK1000;
-+ if (rules & BIT(TRIGGER_NETDEV_RX))
-+ blink |= AIR_PHY_LED_BLINK_1000RX;
-+ if (rules & BIT(TRIGGER_NETDEV_TX))
-+ blink |= AIR_PHY_LED_BLINK_1000TX;
-+ }
-+
-+ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) {
-+ on |= AIR_PHY_LED_ON_LINK2500;
-+ if (rules & BIT(TRIGGER_NETDEV_RX))
-+ blink |= AIR_PHY_LED_BLINK_2500RX;
-+ if (rules & BIT(TRIGGER_NETDEV_TX))
-+ blink |= AIR_PHY_LED_BLINK_2500TX;
-+ }
-+
-+ if (on == 0) {
-+ if (rules & BIT(TRIGGER_NETDEV_RX)) {
-+ blink |= AIR_PHY_LED_BLINK_10RX |
-+ AIR_PHY_LED_BLINK_100RX |
-+ AIR_PHY_LED_BLINK_1000RX |
-+ AIR_PHY_LED_BLINK_2500RX;
-+ }
-+ if (rules & BIT(TRIGGER_NETDEV_TX)) {
-+ blink |= AIR_PHY_LED_BLINK_10TX |
-+ AIR_PHY_LED_BLINK_100TX |
-+ AIR_PHY_LED_BLINK_1000TX |
-+ AIR_PHY_LED_BLINK_2500TX;
-+ }
-+ }
-+
-+ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
-+ on |= AIR_PHY_LED_ON_FDX;
-+
-+ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
-+ on |= AIR_PHY_LED_ON_HDX;
-+
-+ if (blink || on) {
-+ /* switch hw-control on, so led-on and led-blink are off */
-+ clear_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state);
-+ clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state);
-+ } else {
-+ priv->led[index].rules = 0;
-+ }
-+
-+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
-+ AIR_PHY_LED_ON_MASK, on);
-+
-+ if (ret < 0)
-+ return ret;
-+
-+ return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
-+ blink);
-+};
-+
-+static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
-+{
-+ int cl45_data;
-+ int err;
-+
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index));
-+ if (cl45_data < 0)
-+ return cl45_data;
-+
-+ if (state == AIR_LED_ENABLE)
-+ cl45_data |= AIR_PHY_LED_ON_ENABLE;
-+ else
-+ cl45_data &= ~AIR_PHY_LED_ON_ENABLE;
-+
-+ if (pol == AIR_ACTIVE_HIGH)
-+ cl45_data |= AIR_PHY_LED_ON_POLARITY;
-+ else
-+ cl45_data &= ~AIR_PHY_LED_ON_POLARITY;
-+
-+ err = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
-+ cl45_data);
-+ if (err < 0)
-+ return err;
-+
-+ return 0;
-+}
-+
-+static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ int cl45_data = dur;
-+ int ret, i;
-+
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
-+ cl45_data);
-+ if (ret < 0)
-+ return ret;
-+
-+ cl45_data >>= 1;
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
-+ cl45_data);
-+ if (ret < 0)
-+ return ret;
-+
-+ cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR);
-+ if (cl45_data < 0)
-+ return cl45_data;
-+
-+ switch (mode) {
-+ case AIR_LED_MODE_DISABLE:
-+ cl45_data &= ~AIR_PHY_LED_BCR_EXT_CTRL;
-+ cl45_data &= ~AIR_PHY_LED_BCR_MODE_MASK;
-+ break;
-+ case AIR_LED_MODE_USER_DEFINE:
-+ cl45_data |= AIR_PHY_LED_BCR_EXT_CTRL;
-+ cl45_data |= AIR_PHY_LED_BCR_CLK_EN;
-+ break;
-+ default:
-+ phydev_err(phydev, "LED mode %d is not supported\n", mode);
-+ return -EINVAL;
-+ }
-+
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, cl45_data);
-+ if (ret < 0)
-+ return ret;
-+
-+ for (i = 0; i < num; ++i) {
-+ ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
-+ if (ret < 0) {
-+ phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
-+ return ret;
-+ }
-+ air_led_hw_control_set(phydev, i, priv->led[i].rules);
-+ }
-+
-+ return 0;
-+}
-+
-+static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
-+ unsigned long rules)
-+{
-+ if (index >= EN8811H_LED_COUNT)
-+ return -EINVAL;
-+
-+ /* All combinations of the supported triggers are allowed */
-+ if (rules & ~en8811h_led_trig)
-+ return -EOPNOTSUPP;
-+
-+ return 0;
-+};
-+
-+static int en8811h_probe(struct phy_device *phydev)
-+{
-+ struct en8811h_priv *priv;
-+
-+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
-+ GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
-+ priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
-+ priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
-+
-+ phydev->priv = priv;
-+
-+ /* MDIO_DEVS1/2 empty, so set mmds_present bits here */
-+ phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
-+
-+ return 0;
-+}
-+
-+static int en8811h_config_init(struct phy_device *phydev)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ struct device *dev = &phydev->mdio.dev;
-+ int ret, pollret, reg_value;
-+ u32 pbus_value;
-+
-+ if (!priv->firmware_version)
-+ ret = en8811h_load_firmware(phydev);
-+ else
-+ ret = en8811h_restart_host(phydev);
-+ if (ret < 0)
-+ return ret;
-+
-+ /* Because of mdio-lock, may have to wait for multiple loads */
-+ pollret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
-+ EN8811H_PHY_FW_STATUS, reg_value,
-+ reg_value == EN8811H_PHY_READY,
-+ 20000, 7500000, true);
-+
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &pbus_value);
-+ if (ret < 0)
-+ return ret;
-+
-+ if (pollret || !pbus_value) {
-+ phydev_err(phydev, "Firmware not ready: 0x%x\n", reg_value);
-+ return -ENODEV;
-+ }
-+
-+ if (!priv->firmware_version) {
-+ phydev_info(phydev, "MD32 firmware version: %08x\n", pbus_value);
-+ priv->firmware_version = pbus_value;
-+ }
-+
-+ /* Select mode 1, the only mode supported */
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_1,
-+ AIR_PHY_HOST_CMD_1_MODE1);
-+ if (ret < 0)
-+ return ret;
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_2,
-+ AIR_PHY_HOST_CMD_2_MODE1);
-+ if (ret < 0)
-+ return ret;
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
-+ AIR_PHY_HOST_CMD_3_MODE1);
-+ if (ret < 0)
-+ return ret;
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
-+ AIR_PHY_HOST_CMD_4_MODE1);
-+ if (ret < 0)
-+ return ret;
-+
-+ /* Serdes polarity */
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_POLARITY, &pbus_value);
-+ if (ret < 0)
-+ return ret;
-+ if (device_property_read_bool(dev, "airoha,pnswap-rx"))
-+ pbus_value |= EN8811H_POLARITY_RX_REVERSE;
-+ else
-+ pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
-+ if (device_property_read_bool(dev, "airoha,pnswap-tx"))
-+ pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
-+ else
-+ pbus_value |= EN8811H_POLARITY_TX_NORMAL;
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_POLARITY, pbus_value);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
-+ AIR_LED_MODE_USER_DEFINE);
-+ if (ret < 0) {
-+ phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
-+ return ret;
-+ }
-+
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_GPIO_OUTPUT, &pbus_value);
-+ if (ret < 0)
-+ return ret;
-+ pbus_value |= EN8811H_GPIO_OUTPUT_345;
-+ ret = air_buckpbus_reg_write(phydev, EN8811H_GPIO_OUTPUT, pbus_value);
-+ if (ret < 0)
-+ return ret;
-+
-+ return 0;
-+}
-+
-+static int en8811h_get_features(struct phy_device *phydev)
-+{
-+ linkmode_set_bit_array(phy_basic_ports_array,
-+ ARRAY_SIZE(phy_basic_ports_array),
-+ phydev->supported);
-+
-+ return genphy_c45_pma_read_abilities(phydev);
-+}
-+
-+static int en8811h_get_rate_matching(struct phy_device *phydev,
-+ phy_interface_t iface)
-+{
-+ return RATE_MATCH_PAUSE;
-+}
-+
-+static int en8811h_config_aneg(struct phy_device *phydev)
-+{
-+ bool changed = false;
-+ int err, val;
-+
-+ val = 0;
-+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+ phydev->advertising))
-+ val |= MDIO_AN_10GBT_CTRL_ADV2_5G;
-+ err = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
-+ MDIO_AN_10GBT_CTRL_ADV2_5G, val);
-+ if (err < 0)
-+ return err;
-+ if (err > 0)
-+ changed = true;
-+
-+ return __genphy_config_aneg(phydev, changed);
-+}
-+
-+static int en8811h_read_status(struct phy_device *phydev)
-+{
-+ struct en8811h_priv *priv = phydev->priv;
-+ u32 pbus_value;
-+ int ret, val;
-+
-+ ret = genphy_update_link(phydev);
-+ if (ret)
-+ return ret;
-+
-+ phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
-+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
-+ phydev->speed = SPEED_UNKNOWN;
-+ phydev->duplex = DUPLEX_UNKNOWN;
-+ phydev->pause = 0;
-+ phydev->asym_pause = 0;
-+
-+ ret = genphy_read_master_slave(phydev);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = genphy_read_lpa(phydev);
-+ if (ret < 0)
-+ return ret;
-+
-+ /* Get link partner 2.5GBASE-T ability from vendor register */
-+ ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
-+ if (ret < 0)
-+ return ret;
-+ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+ phydev->lp_advertising,
-+ pbus_value & EN8811H_2P5G_LPA_2P5G);
-+
-+ if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
-+ phy_resolve_aneg_pause(phydev);
-+
-+ if (!phydev->link)
-+ return 0;
-+
-+ /* Get real speed from vendor register */
-+ val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
-+ if (val < 0)
-+ return val;
-+ switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
-+ case AIR_AUX_CTRL_STATUS_SPEED_2500:
-+ phydev->speed = SPEED_2500;
-+ break;
-+ case AIR_AUX_CTRL_STATUS_SPEED_1000:
-+ phydev->speed = SPEED_1000;
-+ break;
-+ case AIR_AUX_CTRL_STATUS_SPEED_100:
-+ phydev->speed = SPEED_100;
-+ break;
-+ }
-+
-+ /* BUG in PHY firmware: MDIO_AN_10GBT_STAT_LP2_5G does not get set.
-+ * Firmware before version 24011202 has no vendor register 2P5G_LPA.
-+ * Assume link partner advertised it if connected at 2500Mbps.
-+ */
-+ if (priv->firmware_version < 0x24011202) {
-+ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-+ phydev->lp_advertising,
-+ phydev->speed == SPEED_2500);
-+ }
-+
-+ /* Only supports full duplex */
-+ phydev->duplex = DUPLEX_FULL;
-+
-+ return 0;
-+}
-+
-+static int en8811h_clear_intr(struct phy_device *phydev)
-+{
-+ int ret;
-+
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
-+ AIR_PHY_HOST_CMD_3_DOCMD);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
-+ AIR_PHY_HOST_CMD_4_INTCLR);
-+ if (ret < 0)
-+ return ret;
-+
-+ return 0;
-+}
-+
-+static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
-+{
-+ int ret;
-+
-+ ret = en8811h_clear_intr(phydev);
-+ if (ret < 0) {
-+ phy_error(phydev);
-+ return IRQ_NONE;
-+ }
-+
-+ phy_trigger_machine(phydev);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct phy_driver en8811h_driver[] = {
-+{
-+ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
-+ .name = "Airoha EN8811H",
-+ .probe = en8811h_probe,
-+ .get_features = en8811h_get_features,
-+ .config_init = en8811h_config_init,
-+ .get_rate_matching = en8811h_get_rate_matching,
-+ .config_aneg = en8811h_config_aneg,
-+ .read_status = en8811h_read_status,
-+ .config_intr = en8811h_clear_intr,
-+ .handle_interrupt = en8811h_handle_interrupt,
-+ .led_hw_is_supported = en8811h_led_hw_is_supported,
-+ .read_page = air_phy_read_page,
-+ .write_page = air_phy_write_page,
-+ .led_blink_set = air_led_blink_set,
-+ .led_brightness_set = air_led_brightness_set,
-+ .led_hw_control_set = air_led_hw_control_set,
-+ .led_hw_control_get = air_led_hw_control_get,
-+} };
-+
-+module_phy_driver(en8811h_driver);
-+
-+static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
-+ { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
-+MODULE_FIRMWARE(EN8811H_MD32_DM);
-+MODULE_FIRMWARE(EN8811H_MD32_DSP);
-+
-+MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
-+MODULE_AUTHOR("Airoha");
-+MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
-+MODULE_LICENSE("GPL");
/**
* napi_disable - prevent NAPI from scheduling
-@@ -3238,6 +3239,7 @@ struct softnet_data {
+@@ -3236,6 +3237,7 @@ struct softnet_data {
/* stats */
unsigned int processed;
unsigned int time_squeeze;
void netif_napi_add_weight(struct net_device *dev, struct napi_struct *napi,
int (*poll)(struct napi_struct *, int), int weight)
{
-@@ -11351,6 +11422,9 @@ static int dev_cpu_dead(unsigned int old
+@@ -11306,6 +11377,9 @@ static int dev_cpu_dead(unsigned int old
raise_softirq_irqoff(NET_TX_SOFTIRQ);
local_irq_enable();
#ifdef CONFIG_RPS
remsd = oldsd->rps_ipi_list;
oldsd->rps_ipi_list = NULL;
-@@ -11666,6 +11740,7 @@ static int __init net_dev_init(void)
+@@ -11621,6 +11695,7 @@ static int __init net_dev_init(void)
INIT_CSD(&sd->defer_csd, trigger_rx_softirq, sd);
spin_lock_init(&sd->defer_lock);
static int min_rcvbuf = SOCK_MIN_RCVBUF;
static int max_skb_frags = MAX_SKB_FRAGS;
+static int backlog_threaded;
+ static int min_mem_pcpu_rsv = SK_MEMORY_PCPU_RESERVE;
static int net_msg_warn; /* Unused, but still a sysctl */
-
-@@ -188,6 +189,23 @@ static int rps_sock_flow_sysctl(struct c
+@@ -189,6 +190,23 @@ static int rps_sock_flow_sysctl(struct c
}
#endif /* CONFIG_RPS */
#ifdef CONFIG_NET_FLOW_LIMIT
static DEFINE_MUTEX(flow_limit_update_mutex);
-@@ -532,6 +550,15 @@ static struct ctl_table net_core_table[]
+@@ -541,6 +559,15 @@ static struct ctl_table net_core_table[]
.proc_handler = rps_sock_flow_sysctl
},
#endif
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -6883,6 +6883,7 @@ static int mv88e6xxx_register_switch(str
+@@ -6935,6 +6935,7 @@ static int mv88e6xxx_register_switch(str
ds->ops = &mv88e6xxx_switch_ops;
ds->ageing_time_min = chip->info->age_time_coeff;
ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
+++ /dev/null
-From 1d81e51d6d79d9098013b2e8cdd677bae998c5d8 Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Fri, 28 Apr 2023 02:22:59 +0200
-Subject: [PATCH 1/2] mt7530: register OF node for internal MDIO bus
-
-The MT753x switches provide a switch-internal MDIO bus for the embedded
-PHYs.
-
-Register a OF sub-node on the switch OF-node for this internal MDIO bus.
-This allows to configure the embedded PHYs using device-tree.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- drivers/net/dsa/mt7530.c | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2192,10 +2192,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr
- {
- struct dsa_switch *ds = priv->ds;
- struct device *dev = priv->dev;
-+ struct device_node *np, *mnp;
- struct mii_bus *bus;
- static int idx;
- int ret;
-
-+ np = priv->dev->of_node;
-+
- bus = devm_mdiobus_alloc(dev);
- if (!bus)
- return -ENOMEM;
-@@ -2214,7 +2217,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr
- if (priv->irq)
- mt7530_setup_mdio_irq(priv);
-
-- ret = devm_mdiobus_register(dev, bus);
-+ mnp = of_get_child_by_name(np, "mdio");
-+ ret = devm_of_mdiobus_register(dev, bus, mnp);
-+ of_node_put(mnp);
- if (ret) {
- dev_err(dev, "failed to register MDIO bus: %d\n", ret);
- if (priv->irq)
#endif /* __LINUX_USB_PCI_QUIRKS_H */
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
-@@ -484,7 +484,14 @@ extern int usb_hcd_pci_probe(struct pci_
+@@ -485,7 +485,14 @@ extern int usb_hcd_pci_probe(struct pci_
extern void usb_hcd_pci_remove(struct pci_dev *dev);
extern void usb_hcd_pci_shutdown(struct pci_dev *dev);
--- /dev/null
+From 38eb5b3370c29515d2ce92adac2d6eba96f276f5 Mon Sep 17 00:00:00 2001
+From: INAGAKI Hiroshi <musashino.open@gmail.com>
+Date: Wed, 20 Mar 2024 15:32:18 +0900
+Subject: [PATCH v2 1/2] dt-bindings: leds: add LED_FUNCTION_MOBILE for mobile
+ network
+
+Add LED_FUNCTION_MOBILE for LEDs that indicate status of mobile network
+connection. This is useful to distinguish those LEDs from LEDs that
+indicates status of wired "wan" connection.
+
+example (on stock fw):
+
+IIJ SA-W2 has "Mobile" LEDs that indicate status (no signal, too low,
+low, good) of mobile network connection via dongle connected to USB
+port.
+
+- no signal: (none, turned off)
+- too low: green:mobile & red:mobile (amber, blink)
+- low: green:mobile & red:mobile (amber, turned on)
+- good: green:mobile (turned on)
+
+Suggested-by: Hauke Mehrtens <hauke@hauke-m.de>
+Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
+---
+ include/dt-bindings/leds/common.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/include/dt-bindings/leds/common.h
++++ b/include/dt-bindings/leds/common.h
+@@ -90,6 +90,7 @@
+ #define LED_FUNCTION_INDICATOR "indicator"
+ #define LED_FUNCTION_LAN "lan"
+ #define LED_FUNCTION_MAIL "mail"
++#define LED_FUNCTION_MOBILE "mobile"
+ #define LED_FUNCTION_MTD "mtd"
+ #define LED_FUNCTION_PANIC "panic"
+ #define LED_FUNCTION_PROGRAMMING "programming"
--- /dev/null
+From e22afe910afcfb51b6ba6a0ae776939959727f54 Mon Sep 17 00:00:00 2001
+From: INAGAKI Hiroshi <musashino.open@gmail.com>
+Date: Wed, 20 Mar 2024 15:59:06 +0900
+Subject: [PATCH v2 2/2] dt-bindings: leds: add LED_FUNCTION_SPEED_* for link
+ speed on LAN/WAN
+
+Add LED_FUNCTION_SPEED_LAN and LED_FUNCTION_SPEED_WAN for LEDs that
+indicate link speed of ethernet ports on LAN/WAN. This is useful to
+distinguish those LEDs from LEDs that indicate link status (up/down).
+
+example:
+
+Fortinet FortiGate 30E/50E have LEDs that indicate link speed on each
+of the ethernet ports in addition to LEDs that indicate link status
+(up/down).
+
+- 1000 Mbps: green:speed-(lan|wan)-N
+- 100 Mbps: amber:speed-(lan|wan)-N
+- 10 Mbps: (none, turned off)
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
+---
+ include/dt-bindings/leds/common.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/dt-bindings/leds/common.h
++++ b/include/dt-bindings/leds/common.h
+@@ -96,6 +96,8 @@
+ #define LED_FUNCTION_PROGRAMMING "programming"
+ #define LED_FUNCTION_RX "rx"
+ #define LED_FUNCTION_SD "sd"
++#define LED_FUNCTION_SPEED_LAN "speed-lan"
++#define LED_FUNCTION_SPEED_WAN "speed-wan"
+ #define LED_FUNCTION_STANDBY "standby"
+ #define LED_FUNCTION_TORCH "torch"
+ #define LED_FUNCTION_TX "tx"
/*
* We need to store the untouched command line for future reference.
* We also need to store the touched command line since the parameter
-@@ -896,6 +919,7 @@ void start_kernel(void)
+@@ -898,6 +921,7 @@ void start_kernel(void)
pr_notice("%s", linux_banner);
early_security_init();
setup_arch(&command_line);
CPU_SUBTYPE:=neon-vfpv4
SUBTARGETS:=generic chromium mikrotik
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
KERNELNAME:=zImage Image dtbs
glinet,gl-ap1300|\
glinet,gl-b2200|\
google,wifi|\
+ linksys,whw03|\
linksys,whw03v2|\
luma,wrtq-329acn|\
mikrotik,cap-ac|\
aruba,ap-365|\
avm,fritzrepeater-1200|\
dlink,dap-2610|\
+ engenius,eap1300|\
extreme-networks,ws-ap3915i|\
meraki,mr33|\
meraki,mr74|\
wan_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
lan_mac=$(macaddr_add "$wan_mac" 1)
;;
+ linksys,whw03)
+ wan_mac=$(mmc_get_mac_ascii devinfo hw_mac_addr)
+ lan_mac="$wan_mac"
+ ;;
mikrotik,cap-ac |\
mikrotik,hap-ac2|\
mikrotik,hap-ac3|\
# OEM assigns 4 sequential MACs
ath10k_patch_mac $(macaddr_setbit_la $(macaddr_add "$(cat /sys/class/net/eth0/address)" 4))
;;
+ linksys,whw03)
+ caldata_extract_mmc "0:ART" 0x9000 0x2f20
+ ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 3)
+ ;;
netgear,rbr40|\
netgear,rbs40|\
netgear,rbr50|\
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 2)
;;
+ linksys,whw03)
+ caldata_extract_mmc "0:ART" 0x1000 0x2f20
+ ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 1)
+ ;;
meraki,mr33 |\
meraki,mr74)
caldata_extract_ubi "ART" 0x1000 0x2f20
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 3)
;;
+ linksys,whw03)
+ caldata_extract_mmc "0:ART" 0x5000 0x2f20
+ ath10k_patch_mac $(macaddr_add "$(cat /sys/class/net/eth0/address)" 2)
+ ;;
meraki,mr33 |\
meraki,mr74)
caldata_extract_ubi "ART" 0x5000 0x2f20
START=99
+mmc_resetbc() {
+ local part_label="$1"
+
+ . /lib/functions.sh
+
+ local part_device="$(find_mmc_part "$part_label")"
+ if [ "$part_device" = "" ]; then
+ >&2 echo "mmc_resetbc: Unknown partition label: $part_label"
+ return 1
+ fi
+
+ local magic_number="$(hexdump -e '"0x%02x\n"' -n 4 "$part_device")"
+ if [ "$magic_number" != "0x20110811" ]; then
+ >&2 echo "mmc_resetbc: Unexpected partition magic: $magic_number"
+ return 1
+ fi
+
+ local last_count=$(hexdump -e '"0x%02x\n"' -n 4 -s 4 "$part_device")
+ if [ "$last_count" != "0x00" ]; then
+ printf "\x00" | dd of="$part_device" bs=4 seek=1 count=1 conv=notrunc 2>/dev/null
+
+ last_count=$(hexdump -e '"0x%02x\n"' -n 4 -s 4 "$part_device")
+ if [ "$last_count" != "0x00" ]; then
+ >&2 echo "mmc_resetbc: Unable to reset boot counter"
+ return 1
+ fi
+ fi
+}
+
boot() {
case $(board_name) in
alfa-network,ap120c-ac)
linksys,whw03v2)
mtd resetbc s_env || true
;;
+ linksys,whw03)
+ mmc_resetbc s_env || true
+ ;;
netgear,wac510)
fw_setenv boot_cnt=0
;;
ip link set dev lan1 address $(macaddr_add "$base_mac" 1)
ip link set dev eth0 address $(macaddr_setbit "$base_mac" 7)
;;
+ linksys,whw03)
+ base_mac=$(mmc_get_mac_ascii devinfo hw_mac_addr)
+ ip link set dev eth0 address "$base_mac"
+ ip link set dev lan address "$base_mac"
+ ip link set dev wan address "$base_mac"
+ ;;
mikrotik,wap-ac|\
mikrotik,wap-ac-lte|\
mikrotik,wap-r-ac)
get_image "$1" | mtd -e "$part_label" write - "$part_label"
}
}
+
+linksys_get_cmdline_rootfs_device() {
+ if read cmdline < /proc/cmdline; then
+ case "$cmdline" in
+ *root=*)
+ local str="${cmdline##*root=}"
+ echo "${str%% *}"
+ return
+ ;;
+ esac
+ fi
+ return 1
+}
+
+linksys_get_current_boot_part_emmc() {
+ local boot_part="$(fw_printenv -n boot_part)"
+ if [ "$boot_part" = 1 ] || [ "$boot_part" = 2 ]; then
+ v "Current boot_part=$boot_part selected from bootloader environment"
+ else
+ local rootfs_device="$(linksys_get_cmdline_rootfs_device)"
+ if [ "$rootfs_device" = "$(find_mmc_part "rootfs")" ]; then
+ boot_part=1
+ elif [ "$rootfs_device" = "$(find_mmc_part "alt_rootfs")" ]; then
+ boot_part=2
+ else
+ v "Could not determine current boot_part"
+ return 1
+ fi
+ v "Current boot_part=$boot_part selected from cmdline rootfs=$rootfs_device"
+ fi
+ echo $boot_part
+}
+
+linksys_set_target_partitions_emmc() {
+ local current_boot_part="$1"
+
+ if [ "$current_boot_part" = 1 ]; then
+ CI_KERNPART="alt_kernel"
+ CI_ROOTPART="alt_rootfs"
+ fw_setenv -s - <<-EOF
+ boot_part 2
+ auto_recovery yes
+ EOF
+ elif [ "$current_boot_part" = 2 ]; then
+ CI_KERNPART="kernel"
+ CI_ROOTPART="rootfs"
+ fw_setenv -s - <<-EOF
+ boot_part 1
+ auto_recovery yes
+ EOF
+ else
+ v "Could not set target eMMC partitions"
+ return 1
+ fi
+
+ v "Target eMMC partitions: $CI_KERNPART, $CI_ROOTPART"
+}
+
+platform_do_upgrade_linksys_emmc() {
+ local file="$1"
+
+ mkdir -p /var/lock
+ local current_boot_part="$(linksys_get_current_boot_part_emmc)"
+ linksys_set_target_partitions_emmc "$current_boot_part" || exit 1
+ touch /var/lock/fw_printenv.lock
+
+ emmc_do_upgrade "$file"
+}
linksys,whw03v2)
platform_do_upgrade_linksys "$1"
;;
+ linksys,whw03)
+ platform_do_upgrade_linksys_emmc "$1"
+ ;;
meraki,mr33 |\
meraki,mr74)
CI_KERNPART="part.safe"
platform_copy_config() {
case "$(board_name)" in
glinet,gl-b2200 |\
- google,wifi)
+ google,wifi |\
+ linksys,whw03)
emmc_copy_config
;;
esac
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APQ_GCC_8084 is not set
-# CONFIG_APQ_MMCC_8084 is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_IPQ40XX=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-# CONFIG_ARCH_MDM9615 is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_ARCH_MSM8909 is not set
-# CONFIG_ARCH_MSM8916 is not set
-# CONFIG_ARCH_MSM8960 is not set
-# CONFIG_ARCH_MSM8974 is not set
-# CONFIG_ARCH_MSM8X60 is not set
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPUIDLE=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
-# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
-# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AT803X_PHY=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BCH=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_QCOM=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC8=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
-CONFIG_CRYPTO_BLAKE2S_ARM=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_QCE=y
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
-CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
-CONFIG_CRYPTO_DEV_QCOM_RNG=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXTCON=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_74X164=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_WATCHDOG=y
-CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_QCOM=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_OPTEE=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-# CONFIG_I2C_QCOM_CCI is not set
-CONFIG_I2C_QUP=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IPQ_APSS_PLL is not set
-CONFIG_IPQ_GCC_4019=y
-# CONFIG_IPQ_GCC_6018 is not set
-# CONFIG_IPQ_GCC_806X is not set
-# CONFIG_IPQ_GCC_8074 is not set
-# CONFIG_IPQ_LCC_806X is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-# CONFIG_KPSS_XCC is not set
-# CONFIG_KRAITCC is not set
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_LEDS_LP5523=y
-CONFIG_LEDS_LP5562=y
-CONFIG_LEDS_LP55XX_COMMON=y
-CONFIG_LEDS_TLC591XX=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MDIO_IPQ4019=y
-# CONFIG_MDM_GCC_9615 is not set
-# CONFIG_MDM_LCC_9615 is not set
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-# CONFIG_MFD_QCOM_RPM is not set
-# CONFIG_MFD_SPMI_PMIC is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_MSM=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MSM_GCC_8660 is not set
-# CONFIG_MSM_GCC_8909 is not set
-# CONFIG_MSM_GCC_8916 is not set
-# CONFIG_MSM_GCC_8939 is not set
-# CONFIG_MSM_GCC_8960 is not set
-# CONFIG_MSM_GCC_8974 is not set
-# CONFIG_MSM_GCC_8976 is not set
-# CONFIG_MSM_GCC_8994 is not set
-# CONFIG_MSM_GCC_8996 is not set
-# CONFIG_MSM_GCC_8998 is not set
-# CONFIG_MSM_GPUCC_8998 is not set
-# CONFIG_MSM_LCC_8960 is not set
-# CONFIG_MSM_MMCC_8960 is not set
-# CONFIG_MSM_MMCC_8974 is not set
-# CONFIG_MSM_MMCC_8996 is not set
-# CONFIG_MSM_MMCC_8998 is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_QCOM=y
-# CONFIG_MTD_QCOMSMEM_PARTS is not set
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SPLIT_WRGG_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_QCA8K_IPQ4019=y
-CONFIG_NET_DSA_TAG_OOB=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_QCOM_QFPROM=y
-# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OPTEE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_QCOM=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-# CONFIG_PHY_QCOM_EDP is not set
-CONFIG_PHY_QCOM_IPQ4019_USB=y
-# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
-# CONFIG_PHY_QCOM_IPQ806X_USB is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-# CONFIG_PHY_QCOM_QMP is not set
-# CONFIG_PHY_QCOM_QUSB2 is not set
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_APQ8064 is not set
-# CONFIG_PINCTRL_APQ8084 is not set
-CONFIG_PINCTRL_IPQ4019=y
-# CONFIG_PINCTRL_IPQ8064 is not set
-# CONFIG_PINCTRL_MDM9615 is not set
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_MSM8226 is not set
-# CONFIG_PINCTRL_MSM8660 is not set
-# CONFIG_PINCTRL_MSM8909 is not set
-# CONFIG_PINCTRL_MSM8916 is not set
-# CONFIG_PINCTRL_MSM8960 is not set
-# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_SDX65 is not set
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_POWER_RESET_MSM=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QCA807X_PHY=y
-# CONFIG_QCM_DISPCC_2290 is not set
-# CONFIG_QCM_GCC_2290 is not set
-CONFIG_QCOM_A53PLL=y
-# CONFIG_QCOM_ADM is not set
-CONFIG_QCOM_BAM_DMA=y
-# CONFIG_QCOM_COMMAND_DB is not set
-# CONFIG_QCOM_CPR is not set
-# CONFIG_QCOM_EBI2 is not set
-# CONFIG_QCOM_GENI_SE is not set
-# CONFIG_QCOM_GSBI is not set
-# CONFIG_QCOM_HFPLL is not set
-# CONFIG_QCOM_ICC_BWMON is not set
-# CONFIG_QCOM_IOMMU is not set
-CONFIG_QCOM_IPQ4019_ESS_EDMA=y
-# CONFIG_QCOM_LLCC is not set
-# CONFIG_QCOM_OCMEM is not set
-# CONFIG_QCOM_PDC is not set
-# CONFIG_QCOM_RMTFS_MEM is not set
-# CONFIG_QCOM_RPMH is not set
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-CONFIG_QCOM_SMEM=y
-# CONFIG_QCOM_SMSM is not set
-# CONFIG_QCOM_SOCINFO is not set
-# CONFIG_QCOM_SPM is not set
-# CONFIG_QCOM_STATS is not set
-CONFIG_QCOM_TCSR=y
-# CONFIG_QCOM_TSENS is not set
-CONFIG_QCOM_WDT=y
-# CONFIG_QCS_GCC_404 is not set
-# CONFIG_QCS_Q6SSTOP_404 is not set
-# CONFIG_QCS_TURING_404 is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-CONFIG_REGULATOR_VCTRL=y
-CONFIG_REGULATOR_VQMMC_IPQ4019=y
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_OPTEE is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SC_CAMCC_7280 is not set
-# CONFIG_SC_DISPCC_7180 is not set
-# CONFIG_SC_GCC_7180 is not set
-# CONFIG_SC_GCC_8280XP is not set
-# CONFIG_SC_GPUCC_7180 is not set
-# CONFIG_SC_LPASSCC_7280 is not set
-# CONFIG_SC_LPASS_CORECC_7180 is not set
-# CONFIG_SC_LPASS_CORECC_7280 is not set
-# CONFIG_SC_MSS_7180 is not set
-# CONFIG_SC_VIDEOCC_7180 is not set
-# CONFIG_SDM_CAMCC_845 is not set
-# CONFIG_SDM_DISPCC_845 is not set
-# CONFIG_SDM_GCC_660 is not set
-# CONFIG_SDM_GCC_845 is not set
-# CONFIG_SDM_GPUCC_845 is not set
-# CONFIG_SDM_LPASSCC_845 is not set
-# CONFIG_SDM_VIDEOCC_845 is not set
-# CONFIG_SDX_GCC_65 is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SKB_EXTENSIONS=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-# CONFIG_SM_CAMCC_8450 is not set
-# CONFIG_SM_GCC_8150 is not set
-# CONFIG_SM_GCC_8250 is not set
-# CONFIG_SM_GCC_8450 is not set
-# CONFIG_SM_GPUCC_6350 is not set
-# CONFIG_SM_GPUCC_8150 is not set
-# CONFIG_SM_GPUCC_8250 is not set
-# CONFIG_SM_GPUCC_8350 is not set
-# CONFIG_SM_VIDEOCC_8150 is not set
-# CONFIG_SM_VIDEOCC_8250 is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_QUP=y
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SPMI_MSM_PMIC_ARB=y
-# CONFIG_SPMI_PMIC_CLKDIV is not set
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TEE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
CONFIG_NVMEM_QCOM_QFPROM=y
# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_U_BOOT_ENV=y
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
+++ /dev/null
-// SPDX-License-Identifier: ISC
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "OpenMesh A42";
- compatible = "openmesh,a42";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- aliases {
- led-boot = &led_status_green;
- led-failsafe = &led_status_green;
- led-running = &led_status_green;
- led-upgrade = &led_status_green;
- label-mac-device = &swport5;
- };
-
- leds {
- compatible = "gpio-leds";
-
- status_red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_green: status_green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
- };
-
- watchdog {
- compatible = "linux,wdt-gpio";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- hw_algo = "toggle";
- /* hw_margin_ms is actually 300s but driver limits it to 60s */
- hw_margin_ms = <60000>;
- always-running;
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- /* partitions are passed via bootloader */
- partitions {
- partition-art {
- label = "0:ART";
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "ethernet2";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&swport5 {
- status = "okay";
- label = "ethernet1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "OM-A42";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "OM-A42";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "ALFA Network AP120C-AC";
- compatible = "alfa-network,ap120c-ac";
-
- aliases {
- led-boot = &status;
- led-failsafe = &status;
- led-running = &status;
- led-upgrade = &status;
- ethernet1 = &swport5;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- status: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <ðphy4 1 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "red:wlan5g";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_i2c3 {
- status = "okay";
-
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- tpm@29 {
- compatible = "atmel,at97sc3204t";
- reg = <0x29>;
- };
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 4 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- };
-
- partition@f0000 {
- label = "APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@180000 {
- label = "priv_data1";
- reg = <0x00180000 0x00010000>;
- read-only;
- };
-
- partition@190000 {
- label = "priv_data2";
- reg = <0x00190000 0x00010000>;
- read-only;
- };
- };
- };
-
- nand@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs1";
- reg = <0x00000000 0x04000000>;
- };
-
- partition@4000000 {
- label = "rootfs2";
- reg = <0x04000000 0x04000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial0_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-ðphy4 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-&tlmm {
- i2c0_pins: i2c0_pinmux {
- mux_i2c {
- function = "blsp_i2c0";
- pins = "gpio58", "gpio59";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_mdio {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_mdc {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial0_pins: serial0_pinmux {
- mux_uart {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi0_pins: spi0_pinmux {
- mux_spi {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio4";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MikroTik cAP ac";
- compatible = "mikrotik,cap-ac";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x08000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_user;
- led-failsafe = &led_user;
- led-running = &led_user;
- led-upgrade = &led_user;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- mode {
- label = "mode";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_LIGHTS_TOGGLE>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- led_user: user {
- label = "green:user";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-
- eth1 {
- label = "green:eth1";
- gpios = <ðphy4 1 GPIO_ACTIVE_HIGH>;
- };
-
- eth2 {
- label = "green:eth2";
- gpios = <ðphy3 1 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@100000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x100000 0xf00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-ðphy3 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-ðphy4 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-cAP-ac";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-cAP-ac";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EZVIZ CS-W3-WD1200G EUP";
- compatible = "ezviz,cs-w3-wd1200g-eup";
-
- aliases {
- led-boot = &led_status_green;
- led-failsafe = &led_status_red;
- led-running = &led_status_blue;
- led-upgrade = &led_status_green;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- reset-delay-us = <5000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_red: status_red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
- };
-
- led_status_green: status_green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
- };
-
- led_status_blue: status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition1@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition2@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition3@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition4@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition5@E0000 {
- label = "APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
-
- partition6@F0000 {
- label = "APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition7@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition9@580000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x00180000 0x00e80000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
- label = "wan";
- nvmem-cells = <&macaddr_art_6>;
- nvmem-cell-names = "mac-address";
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "D-Link DAP 2610";
- compatible = "dlink,dap-2610";
-
- aliases {
- led-boot = &led_red;
- led-failsafe = &led_red;
- led-running = &led_green;
- led-upgrade = &led_red;
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- rng@22000 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_red: red {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- };
-
- led_green: green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fixed-partitions";
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
- partition@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
- partition@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
- partition@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
- partition@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
- };
- partition@180000 {
- compatible = "wrg";
- label = "firmware";
- reg = <0x180000 0xdc0000>;
- };
- partition@fb0000 {
- label = "rgbd";
- reg = <0xfb0000 0x10000>;
- read-only;
- };
- partition@fc0000 {
- label = "bdcfg";
- reg = <0xfc0000 0x10000>;
- read-only;
- };
- partition@fd0000 {
- label = "langpack";
- reg = <0xfd0000 0x20000>;
- read-only;
- };
- partition@ff0000 {
- label = "certificate";
- reg = <0xff0000 0x10000>;
- read-only;
- };
- partition@f40000 {
- label = "captival";
- reg = <0xf40000 0x70000>;
- read-only;
- };
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "dlink,dap-2610";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "dlink,dap-2610";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Linksys EA6350v3";
- compatible = "linksys,ea6350v3";
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "linksys-ea6350v3";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "linksys-ea6350v3";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- SBL1@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- MBIB@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- QSEE@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- CDT@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- APPSBLENV@d0000 {
- label = "APPSBLENV";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- APPSBL@e0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000e0000 0x00080000>;
- read-only;
- };
- ART@160000 {
- label = "ART";
- reg = <0x00160000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- u_env@170000 {
- label = "u_env";
- reg = <0x00170000 0x00020000>;
- };
- s_env@190000 {
- label = "s_env";
- reg = <0x00190000 0x00020000>;
- };
- devinfo@1b0000 {
- label = "devinfo";
- reg = <0x001b0000 0x00010000>;
- };
- /* 0x001c0000 - 0x00200000 unused */
- };
- };
-
- flash@1 {
- status = "okay";
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- kernel@0 {
- label = "kernel";
- reg = <0x00000000 0x02800000>;
- };
- rootfs@500000 {
- label = "rootfs";
- reg = <0x00500000 0x02300000>;
- };
- alt_kernel@2800000 {
- label = "alt_kernel";
- reg = <0x02800000 0x02800000>;
- };
- alt_rootfs@2d00000 {
- label = "alt_rootfs";
- reg = <0x02d00000 0x02300000>;
- };
- sysdiag@5000000 {
- label = "sysdiag";
- reg = <0x05000000 0x00100000>;
- };
- syscfg@5100000 {
- label = "syscfg";
- reg = <0x05100000 0x02F00000>;
- };
- /* 0x00000000 - 0x08000000: 128 MiB */
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EnGenius EAP1300";
- compatible = "engenius,eap1300";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: orange {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- };
-
- lan {
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
-
- mesh {
- label = "blue:mesh";
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g {
- label = "blue:wlan2g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "yellow:wlan5g";
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio54", "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition6@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x00090000>;
- read-only;
- };
- partition7@180000 {
- label = "0:ART";
- reg = <0x00180000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition8@190000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x190000 0x1dc0000>;
- };
- partition9@1f50000 {
- label = "u-boot-env";
- reg = <0x01f50000 0x00010000>;
- };
- partition10@1f60000 {
- label = "userconfig";
- reg = <0x01f60000 0x000a0000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Edgecore ECW5211";
- compatible = "edgecore,ecw5211";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- ethernet0 = &swport5;
- ethernet1 = &gmac;
- };
-
- chosen {
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_mdio {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_mdc {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi0_pins: spi0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
-
- pin_cs {
- function = "gpio";
- pins = "gpio54", "gpio4";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- i2c0_pins: i2c0_pinmux {
- mux_i2c {
- function = "blsp_i2c0";
- pins = "gpio58", "gpio59";
- drive-strength = <16>;
- bias-disable;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV"; /* uboot env */
- reg = <0x000e0000 0x00010000>;
- };
-
- partition@f0000 {
- label = "0:APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- flash@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs";
- reg = <0x00000000 0x04000000>;
- };
- };
- };
-};
-
-&blsp1_i2c3 {
- status = "okay";
-
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- tpm@29 {
- compatible = "atmel,at97sc3204t";
- reg = <0x29>;
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EnGenius EMD1";
- compatible = "engenius,emd1";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g {
- label = "red:wlan2g";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "blue:wlan5g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- mesh {
- label = "orange:mesh";
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio54", "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition6@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition7@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
- partition8@180000 {
- label = "userconfig";
- reg = <0x00180000 0x00080000>;
- read-only;
- };
- partition9@200000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x200000 0x01e00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-EMD1";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-EMD1";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EnGenius EMR3500";
- compatible = "engenius,emr3500";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2_hs_phy: hsphy@a8000 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
-
- blue {
- label = "blue";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
-
- red {
- label = "red";
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
-
- orange {
- label = "orange";
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio54", "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
- partition@180000 {
- label = "userconfig";
- reg = <0x00180000 0x00080000>;
- read-only;
- };
- partition@200000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x200000 0x1e00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EnGenius ENS620EXT";
- compatible = "engenius,ens620ext";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- /*
- * Disable the broken restart as a workaround for the buggy
- * 3.0.0/3.0.1 U-boots that ship with the device.
- * Note: The watchdog is now used to restart this device.
- */
- restart@4ab000 {
- status = "disabled";
- };
- };
-
- buttons {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- };
-
- lan1 {
- label = "green:lan1";
- gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
- };
-
- lan2 {
- label = "green:lan2";
- gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00090000>;
- read-only;
- };
- partition@180000 {
- label = "ART";
- reg = <0x00180000 0x00010000>;
- read-only;
- };
- partition@190000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x00190000 0x14d0000>;
- };
- partition@1660000 {
- label = "failsafe";
- reg = <0x01660000 0x008F0000>;
- read-only;
- };
- partition@1f50000 {
- label = "u-boot-env";
- reg = <0x01f50000 0x00010000>;
- read-only;
- };
- partition@1f60000 {
- label = "userconfig";
- reg = <0x01f60000 0x000a0000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4018-ex61x0v2.dtsi"
-
-/ {
- model = "Netgear EX6100v2";
- compatible = "netgear,ex6100v2";
-};
-
-&wifi0 {
- qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
-};
-
-&wifi1 {
- qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4018-ex61x0v2.dtsi"
-
-/ {
- model = "Netgear EX6150v2";
- compatible = "netgear,ex6150v2";
-};
-
-&wifi0 {
- qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
-};
-
-&wifi1 {
- qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Netgear EX61X0v2";
- compatible = "netgear,ex61x0v2";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- aliases {
- led-boot = &power_amber;
- led-failsafe = &power_amber;
- led-running = &power_green;
- led-upgrade = &power_amber;
- label-mac-device = &gmac;
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- led_spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- num-chipselects = <0>;
-
- led_gpio: led_gpio@0 {
- compatible = "fairchild,74hc595";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <2>;
- registers-number = <1>;
- spi-max-frequency = <1000000>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power_amber: power_amber {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
- };
-
- power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
- };
-
- right {
- label = "blue:right";
- gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
- };
-
- left {
- label = "blue:left";
- gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
- };
-
- client_green {
- label = "green:client";
- gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
- };
-
- client_red {
- label = "red:client";
- gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
- };
-
- router_green {
- label = "green:router";
- gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
- };
-
- router_red {
- label = "red:router";
- gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- mx25l12805d@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <45000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition1@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition2@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition3@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition4@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition5@E0000 {
- label = "APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
-
- partition6@F0000 {
- label = "APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition7@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition8@180000 {
- label = "config";
- reg = <0x00180000 0x00010000>;
- read-only;
- };
-
- partition9@190000 {
- label = "pot";
- reg = <0x00190000 0x00010000>;
- read-only;
- };
-
- partition10@1a0000 {
- label = "dnidata";
- reg = <0x001a0000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_dnidata_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_dnidata_c: macaddr@c {
- reg = <0xc 0x6>;
- };
- };
- };
-
- partition11@1b0000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x001b0000 0x00e10000>;
- };
-
- partition12@fc0000 {
- label = "language";
- reg = <0x00fc0000 0x00040000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_dnidata_0>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "AVM FRITZ!Box 4040";
- compatible = "avm,fritzbox-4040";
-
- aliases {
- led-boot = &power;
- led-failsafe = &flash;
- led-running = &power;
- led-upgrade = &flash;
- label-mac-device = &gmac;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wlan {
- label = "wlan";
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- switch-leds {
- compatible = "gpio-leds";
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <ðphy0 0 GPIO_ACTIVE_HIGH>;
- };
-
- panic: info_red {
- label = "red:info";
- gpios = <ðphy0 1 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <ðphy1 0 GPIO_ACTIVE_HIGH>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <ðphy2 1 GPIO_ACTIVE_HIGH>;
- };
-
- lan {
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <ðphy3 0 GPIO_ACTIVE_HIGH>;
- };
-
- flash: info_amber {
- label = "amber:info";
- gpios = <ðphy3 1 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- status = "okay";
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "APPSBLENV"; /* uboot env - empty */
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition6@f0000 {
- label = "urlader"; /* APPSBL */
- reg = <0x000f0000 0x0002dc000>;
- read-only;
- };
- partition7@11dc00 {
- /* make a backup of this partition! */
- label = "urlader_config";
- reg = <0x0011dc00 0x00002400>;
- read-only;
- };
- partition8@120000 {
- label = "tffs1";
- reg = <0x00120000 0x00080000>;
- read-only;
- };
- partition9@1a0000 {
- label = "tffs2";
- reg = <0x001a0000 0x00080000>;
- read-only;
- };
- partition10@220000 {
- label = "uboot";
- reg = <0x00220000 0x00080000>;
- read-only;
- };
- partition11@2A0000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x002a0000 0x01c60000>;
- };
- partition12@1f00000 {
- label = "jffs2";
- reg = <0x01f00000 0x00100000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-ðphy0 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-ðphy1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- enable-usb-power {
- gpio-hog;
- line-name = "enable USB3 power";
- gpios = <1 GPIO_ACTIVE_HIGH>;
- output-high;
- };
-};
-
-ðphy2 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-ðphy3 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "GL.iNet GL-A1300";
- compatible = "glinet,gl-a1300", "qcom,ipq4019";
-
- aliases {
- led-boot = &led_run;
- led-failsafe = &led_run;
- led-running = &led_run;
- led-upgrade = &led_run;
- label-mac-device = &swport4;
- };
-
- chosen {
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- switch {
- label = "switch-button";
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_SETUP>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_run: blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
-
- white {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio_export {
- compatible = "gpio-export";
-
- usb {
- gpio-export,name = "usb_power";
- gpio-export,output = <1>;
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 5 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- };
-
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@180000 {
- label = "log";
- reg = <0x00180000 0x00020000>;
- };
- };
- };
-
- spi-nand@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x08000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- pinmux {
- pins = "gpio58", "gpio59";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- spi0_pins: spi0_pinmux {
- mux_spi {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio5";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp1_i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0 2>;
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0 0>;
-};
-
-&swport5 {
- status = "okay";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "GL-A1300";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "GL-A1300";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "GL.iNet GL-AP1300";
- compatible = "glinet,gl-ap1300";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 5 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- status = "okay";
-
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- };
-
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: mac-address@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: mac-address@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- spi-nand@1 {
- status = "okay";
-
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x08000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi0_pins: spi0_pinmux {
- mux_spi {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio5";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan";
-
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-};
-
-&swport5 {
- status = "okay";
- label = "wan";
-
- nvmem-cells = <&macaddr_art_6>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "GL-AP1300";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "GL-AP1300";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MikroTik hAP ac2";
- compatible = "mikrotik,hap-ac2";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x08000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_user;
- led-failsafe = &led_user;
- led-running = &led_user;
- led-upgrade = &led_user;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- mode {
- label = "mode";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- panic-indicator;
- };
-
- led_user: user {
- label = "green:user";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- enable-usb-power {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable USB power";
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- size = <0x2000>;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@100000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x100000 0xf00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-ðphy0 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy1 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy2 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy3 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy4 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-hAP-ac2";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-hAP-ac2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
-
-#include "qcom-ipq4018-jalapeno.dtsi"
-
-/ {
- model = "8devices Jalapeno";
- compatible = "8dev,jalapeno";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- aliases {
- ethernet1 = &swport5;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- usb3: usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- pinmux_1 {
- pins = "gpio53";
- function = "mdio";
- };
-
- pinmux_2 {
- pins = "gpio52";
- function = "mdc";
- };
-
- pinconf {
- pins = "gpio52", "gpio53";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
-
- pin_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- status = "okay";
-
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
-
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- spi-nand@1 {
- status = "okay";
-
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x08000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "8devices-Jalapeno";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "8devices-Jalapeno";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "devolo Magic 2 WiFi next";
- compatible = "devolo,magic-2-wifi-next";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- plc {
- gpio-export,name = "plc-enable";
- gpio-export,output = <1>;
- gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
- };
- };
-
- };
-
- keys {
- compatible = "gpio-keys";
-
- wlan {
- label = "WLAN";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- reset {
- label = "Reset";
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- status_dlan {
- label = "white:dlan";
- gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- status_wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- error_dlan {
- label = "red:dlan";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
- };
-};
-
-&tlmm {
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio61", "gpio60";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- button_pins: button_pinmux {
- mux {
- function = "gpio";
- pins = "gpio0", "gpio5";
- bias-disable;
- input;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "devolo,magic-2-wifi-next";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "devolo,magic-2-wifi-next";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- linux,modalias = "n25q128a11";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- };
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
- firmware@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x00180000 0x01a80000>;
- };
- };
- };
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
- label = "lan1";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "ghn";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2019, CRISIS INNOVATION LAB d.o.o.
- * Author: Robert Marko <robert@meshpoint.me>
- */
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq4018-jalapeno.dtsi"
-
-/ {
- model = "Crisis Innovation Lab MeshPoint.One";
- compatible = "cilab,meshpoint-one";
-
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- };
-
- soc {
- i2c-gpio {
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "i2c-gpio";
- gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */
- &tlmm 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */
- >;
-
- bme280@76 {
- status = "okay";
-
- compatible = "bosch,bme280";
- reg = <0x76>;
- };
-
- pcf2129@51 {
- status = "okay";
-
- compatible = "nxp,pcf2129";
- reg = <0x51>;
- };
-
- ina230@40 {
- status = "okay";
-
- compatible = "ti,ina230";
- reg = <0x40>;
- shunt-resistor = <2000>;
- };
-
- ina230@44 {
- status = "okay";
-
- compatible = "ti,ina230";
- reg = <0x44>;
- shunt-resistor = <2000>;
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART >;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4018-mf287_common.dtsi"
-
-/ {
- model = "ZTE MF287";
- compatible = "zte,mf287";
-};
-
-&gpio_modem_reset {
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-};
-
-&key_reset {
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-};
-
-&key_wps {
- gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-};
-
-&led_status {
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>,
- <&tlmm 1 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-
- spi-nand@1 { /* flash@1 ? */
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0x140000>;
- read-only;
- };
-
- partition@140000 {
- label = "ART";
- reg = <0x140000 0x140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@280000 {
- label = "mac";
- reg = <0x280000 0x140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mac_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@3c0000 {
- label = "cfg-param";
- reg = <0x3c0000 0x600000>;
- read-only;
- };
-
- partition@9c0000 {
- label = "oops";
- reg = <0x9c0000 0x140000>;
- };
-
- partition@b00000 {
- label = "web";
- reg = <0xb00000 0x800000>;
- };
-
- partition@1300000 {
- label = "rootfs";
- reg = <0x1300000 0x2200000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x3200000>;
- };
- };
- };
-
- zigbee@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "silabs,em3581";
- reg = <2>;
- spi-max-frequency = <12000000>;
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59", "gpio1";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&wifi0 {
- qcom,ath10k-calibration-variant = "zte,mf287";
-};
-
-&wifi1{
- qcom,ath10k-calibration-variant = "zte,mf287";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- };
-
- chosen {
- /*
- * bootargs forced by u-boot bootipq command:
- * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
- */
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status: led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- };
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- gpio_modem_reset: modem {
- gpio-export,name = "modem-reset";
- gpio-export,output = <0>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- key_reset: key-reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- };
-
- key_wps: key-wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_mac_0 2>;
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan4";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_mac_0 0>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_mac_0 1>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4018-mf287_common.dtsi"
-
-/ {
- model = "ZTE MF287Plus";
- compatible = "zte,mf287plus";
-};
-
-&gpio_modem_reset {
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-};
-
-&key_reset {
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-};
-
-&key_wps {
- gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-};
-
-&led_status {
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>,
- <&tlmm 1 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-
- spi-nand@1 { /* flash@1 ? */
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0x140000>;
- read-only;
- };
-
- partition@140000 {
- label = "ART";
- reg = <0x140000 0x140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@280000 {
- label = "mac";
- reg = <0x280000 0x140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mac_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@3c0000 {
- label = "cfg-param";
- reg = <0x3c0000 0x600000>;
- read-only;
- };
-
- partition@9c0000 {
- label = "oops";
- reg = <0x9c0000 0x140000>;
- };
-
- partition@b00000 {
- label = "web";
- reg = <0xb00000 0x800000>;
- };
-
- partition@1300000 {
- label = "rootfs";
- reg = <0x1300000 0x2200000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x3200000>;
- };
- };
- };
-
- zigbee@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "silabs,em3581";
- reg = <2>;
- spi-max-frequency = <12000000>;
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59", "gpio1";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&wifi0 {
- qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
-
-&wifi1{
- qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4018-mf287_common.dtsi"
-
-/ {
- model = "ZTE MF287Pro";
- compatible = "zte,mf287pro";
-
- regulator-usb-vbus {
- compatible = "regulator-fixed";
- regulator-name = "USB_VBUS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&tlmm 25 GPIO_ACTIVE_LOW>;
- };
-};
-
-&gpio_modem_reset {
- gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
-};
-
-&key_reset {
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-};
-
-&key_wps {
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
-};
-
-&led_status {
- gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>,
- <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-
- spi-nand@1 { /* flash@1 ? */
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0xa0000>;
- read-only;
- };
-
- partition@a0000 {
- label = "ART";
- reg = <0xa0000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@120000 {
- label = "mac";
- reg = <0x120000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mac_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1a0000 {
- label = "reserved2";
- reg = <0x1a0000 0xc0000>;
- };
-
- partition@260000 {
- label = "cfg-param";
- reg = <0x260000 0x400000>;
- read-only;
- };
-
- partition@660000 {
- label = "log";
- reg = <0x660000 0x400000>;
- };
-
- partition@a60000 {
- label = "oops";
- reg = <0xa60000 0xa0000>;
- };
-
- partition@b00000 {
- label = "reserved3";
- reg = <0xb00000 0x500000>;
- };
-
- partition@1000000 {
- label = "web";
- reg = <0x1000000 0x800000>;
- };
-
- partition@1800000 {
- label = "rootfs";
- reg = <0x1800000 0x1d00000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x3200000>;
- };
- };
- };
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio12", "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12", "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-/* The MF287Plus and MF287Pro share the same board data file */
-&wifi0 {
- qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
-
-/* The MF287Plus and MF287Pro share the same board data file */
-&wifi1{
- qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "ZyXEL NBG6617";
- compatible = "zyxel,nbg6617";
-
- chosen {
- /*
- * the vendor u-boot adds root and mtdparts cmdline parameters
- * which we don't want... but we have to overwrite them or else
- * the kernel will take them at face value.
- */
- bootargs-append = " mtdparts= root=31:13";
- };
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wlan {
- label = "wlan";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_RFKILL>;
- linux,input-type = <EV_SW>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
- linux,default-trigger = "usbport";
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-low;
- };
- };
- led_pins: led_pinmux {
- mux {
- pins = "gpio0", "gpio1", "gpio3", "gpio5", "gpio58";
- drive-strength = <0x8>;
- bias-disable;
- output-low;
- };
- };
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- status = "okay";
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "APPSBL"; /* u-boot */
- reg = <0x000e0000 0x00080000>;
- /* U-Boot Standalone App "zloader" is located at 0x64000 */
- read-only;
- };
- partition6@160000 {
- label = "APPSBLENV"; /* u-boot env */
- reg = <0x00160000 0x00010000>;
- };
- partition7@170000 {
- /* make a backup of this partition! */
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
- partition8@180000 {
- label = "kernel";
- reg = <0x00180000 0x00400000>;
- };
- partition9@580000 {
- label = "dualflag";
- reg = <0x00580000 0x00010000>;
- read-only;
- };
- partition10@590000 {
- label = "header";
- reg = <0x00590000 0x00010000>;
- };
- partition11@5a0000 {
- label = "romd";
- reg = <0x005a0000 0x00100000>;
- read-only;
- };
- partition12@6a0000 {
- label = "not_root_data";
- /*
- * for some strange reason, someone at ZyXEL
- * had the "great" idea to put the rootfs_data
- * in front of rootfs... Don't do that!
- * As a result this one, full MebiByte remains
- * unused.
- */
- reg = <0x006a0000 0x00100000>;
- };
- partition13@7a0000 {
- label = "rootfs";
- reg = <0x007a0000 0x01860000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>
- * Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Plasma Cloud PA1200";
- compatible = "plasmacloud,pa1200";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- aliases {
- led-boot = &led_status_purple;
- led-failsafe = &led_status_yellow;
- led-running = &led_status_cyan;
- led-upgrade = &led_status_yellow;
- label-mac-device = &swport5;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_cyan: status_cyan {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_CYAN>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_purple: status_purple {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_PURPLE>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_yellow: status_yellow {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
- };
-
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- /* partitions are passed via bootloader */
- partitions {
- partition-art {
- label = "0:ART";
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "ethernet2";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&swport5 {
- status = "okay";
- label = "ethernet1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "PlasmaCloud-PA1200";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "PlasmaCloud-PA1200";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ASUS RT-AC58U";
- compatible = "asus,rt-ac58u";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x8000000>;
- };
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: led-0 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led-1 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WAN;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- /*
- * linux,default-trigger = "90000.mdio-1:04:link";
- * sadly still lacks rx+tx
- */
- };
-
- led-2 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <2>;
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- led-3 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <5>;
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- led-4 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_USB;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- trigger-sources = <&usb3_port1>, <&usb3_port2>;
- linux,default-trigger = "usbport";
- };
-
- led-5 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- /*
- * U-boot looks for "n25q128a11" node,
- * if we don't have it, it will spit out the following warning:
- * "ipq: fdt fixup unable to find compatible node".
- */
- compatible = "jedec,spi-nor";
- reg = <0>;
- linux,modalias = "m25p80", "mx25l1606e", "n25q128a11";
- spi-max-frequency = <30000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
- /* 0x00180000 - 0x00200000 unused */
- };
- };
-
- spi-nand@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <30000000>;
-
- /*
- * U-boot looks for "spinand,mt29f" node,
- * if we don't have it, it will spit out the following warning:
- * "ipq: fdt fixup unable to find compatible node".
- */
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x08000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "RT-AC58U";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "RT-AC58U";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- aliases {
- serial0 = &blsp1_uart1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 4 1>;
- linux,code = <KEY_RESTART>;
- };
- };
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio54";
- };
- pinconf {
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio58", "gpio59";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 0>, <&tlmm 63 0>;
- num-cs = <2>;
- status = "okay";
-
- xt25f128b@0 {
- /*
- * Factory U-boot looks in 0:BOOTCONFIG partition for active
- * partitions settings and mangles the partition config so
- * 0:QSEE/0:QSEE_1, 0:CDT/0:CDT_1 and 0:APPSBL/0:APPSBL_1 pairs
- * can be swaped. It isn't a problem but we never can be sure where
- * OFW put factory images. "n25q128a11" is required for proper nor
- * recognition in u-boot.
- */
- compatible = "jedec,spi-nor", "n25q128a11";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:BOOTCONFIG";
- reg = <0x60000 0x20000>;
- read-only;
- };
-
- partition@80000 {
- label = "0:BOOTCONFIG1";
- reg = <0x80000 0x20000>;
- read-only;
- };
-
- partition@a0000 {
- label = "0:QSEE";
- reg = <0xa0000 0x60000>;
- read-only;
- };
-
- partition@100000 {
- label = "0:QSEE_1";
- reg = <0x100000 0x60000>;
- read-only;
- };
-
- partition@160000 {
- label = "0:CDT";
- reg = <0x160000 0x10000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:CDT_1";
- reg = <0x170000 0x10000>;
- read-only;
- };
-
- partition@180000 {
- label = "0:DDRPARAMS";
- reg = <0x180000 0x10000>;
- read-only;
- };
-
- partition@190000 {
- label = "0:APPSBLENV";
- reg = <0x190000 0x10000>;
- read-only;
- };
-
- partition@1a0000 {
- label = "0:APPSBL";
- reg = <0x1a0000 0xa0000>;
- read-only;
- };
-
- partition@240000 {
- label = "0:APPSBL_1";
- reg = <0x240000 0xa0000>;
- read-only;
- };
-
- partition@2e0000 {
- label = "0:ART";
- reg = <0x2e0000 0x10000>;
- read-only;
- };
-
- config: partition@2f0000 {
- label = "0:CONFIG";
- reg = <0x2f0000 0x10000>;
- read-only;
- };
-
- partition@300000 {
- label = "0:CONFIG_RW";
- reg = <0x300000 0x10000>;
- read-only;
- };
-
- partition@310000 {
- label = "0:EVENTSLOG";
- reg = <0x310000 0x90000>;
- read-only;
- };
- };
- };
-
- xt26g02a@1 {
- /*
- * Factory U-boot looks in 0:BOOTCONFIG partition for active
- * partitions settings and mangles the partition config so
- * rootfs/rootfs_1 pairs can be swaped.
- * It isn't a problem but we never can be sure where OFW put
- * factory images. "spinand,mt29f" value is required for proper
- * nand recognition in u-boot.
- */
- compatible = "spi-nand", "spinand,mt29f";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs_1";
- reg = <0x00000000 0x08000000>;
- };
-
- partition@8000000 {
- label = "rootfs";
- reg = <0x08000000 0x08000000>;
- };
- };
- };
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy-reset-gpio = <&tlmm 62 0>;
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4018-rutx.dtsi"
-
-/ {
- model = "Teltonika RUTX10";
- compatible = "teltonika,rutx10";
-
- soc {
- leds {
- compatible = "gpio-leds";
-
- wifi2g {
- label = "green:wifi2g";
- gpios = <&stm32_io 19 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wifi5g {
- label = "green:wifi5g";
- gpios = <&stm32_io 18 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- gpio_out {
- gpio-export,name = "gpio_out";
- gpio-export,output = <0>;
- gpio-export,direction_may_change = <0>;
- gpios = <&stm32_io 23 GPIO_ACTIVE_HIGH>;
- };
-
- gpio_in {
- gpio-export,name = "gpio_in";
- gpio-export,input = <0>;
- gpio-export,direction_may_change = <0>;
- gpios = <&stm32_io 24 GPIO_ACTIVE_LOW>;
- };
- };
- };
-};
-
-&blsp1_i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- clock-frequency = <400000>;
-
- stm32_io: stm32@74 {
- compatible = "tlt,stm32v1";
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- gpio-controller;
- interrupt-controller;
- interrupt-parent = <&tlmm>;
- interrupts = <5 2>;
- reg = <0x74>;
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4018-rutx.dtsi"
-
-/ {
- model = "Teltonika RUTX50";
- compatible = "teltonika,rutx50";
-
- aliases {
- led-boot = &led_rssi0;
- led-failsafe = &led_rssi0;
- led-running = &led_rssi0;
- led-upgrade = &led_rssi0;
- label-mac-device = &gmac;
- };
-
- soc {
- gpio-export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- gpio_modem_reset {
- gpio-export,name = "modem_reset";
- gpio-export,output = <0>;
- gpios = <&shift_io 8 GPIO_ACTIVE_HIGH>;
- };
-
- gpio_modem_power {
- gpio-export,name = "modem_power";
- gpio-export,output = <0>;
- gpios = <&shift_io 9 GPIO_ACTIVE_HIGH>;
- };
-
- gpio_out_1 {
- gpio-export,name = "sim-select";
- /* 0 = SIM1 ; 1 = SIM2 */
- gpio-export,output = <0>;
- gpios = <&shift_io 10 GPIO_ACTIVE_HIGH>;
- };
-
- gpio_in_1 {
- gpio-export,name = "sim-detect";
- gpio-export,input = <0>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- label = "green:sim1";
- gpios = <&shift_io 14 GPIO_ACTIVE_HIGH>;
- };
-
- led-1 {
- label = "green:sim2";
- gpios = <&shift_io 15 GPIO_ACTIVE_HIGH>;
- };
-
- led-2 {
- label = "green:eth";
- gpios = <&shift_io 6 GPIO_ACTIVE_HIGH>;
- };
-
- led-3 {
- label = "green:wifi";
- gpios = <&shift_io 7 GPIO_ACTIVE_HIGH>;
- };
-
- led-4 {
- label = "green:3g";
- gpios = <&shift_io 5 GPIO_ACTIVE_HIGH>;
- };
-
- led-5 {
- label = "green:4g";
- gpios = <&shift_io 4 GPIO_ACTIVE_HIGH>;
- };
-
- led-6 {
- label = "green:5g";
- gpios = <&shift_io 3 GPIO_ACTIVE_HIGH>;
- };
-
- led_rssi0: led-7 {
- label = "green:rssi0";
- gpios = <&shift_io 0 GPIO_ACTIVE_HIGH>;
- };
-
- led-8 {
- label = "green:rssi1";
- gpios = <&shift_io 1 GPIO_ACTIVE_HIGH>;
- };
-
- led-9 {
- label = "green:rssi2";
- gpios = <&shift_io 2 GPIO_ACTIVE_HIGH>;
- };
-
- led-10 {
- label = "green:wifi2g";
- gpios = <&shift_io 12 GPIO_ACTIVE_HIGH>;
- };
-
- led-11 {
- label = "green:wifi5g";
- gpios = <&shift_io 13 GPIO_ACTIVE_HIGH>;
- };
- };
-
- spi-gpio {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-sck = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- num-chipselects = <1>;
-
- shift_io: shift_io@0 {
- compatible = "fairchild,74hc595";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <2>;
- /* Attn: This is specific to RUTX50 in Teltonika GPL */
- registers-number = <2>;
- spi-max-frequency = <10000000>;
- };
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan4";
-};
-
-&swport5 {
- status = "okay";
-
- label = "wan";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MikroTik SXTsq 5 ac (RBSXTsqG-5acD)";
- compatible = "mikrotik,sxtsq-5-ac";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_user;
- led-failsafe = &led_user;
- led-running = &led_user;
- led-upgrade = &led_user;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII4>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- panic-indicator;
- };
-
- led_user: user {
- label = "green:user";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- rssilow {
- label = "green:rssilow";
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-
- rssimediumlow {
- label = "green:rssimediumlow";
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- rssimedium {
- label = "green:rssimedium";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
-
- rssimediumhigh {
- label = "green:rssimediumhigh";
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
-
- rssihigh {
- label = "green:rssihigh";
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@100000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x100000 0xf00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-SXTsq-5-ac";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-
- /delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
- phy-mode = "rgmii";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Netgear WAC510";
- compatible = "netgear,wac510";
-
- aliases {
- led-boot = &led_power_amber;
- led-failsafe = &led_power_amber;
- led-running = &led_power_green;
- led-upgrade = &led_power_amber;
- ethernet1 = &swport5;
- };
-
- chosen {
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- led_spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- num-chipselects = <0>;
-
- ssr: ssr@0 {
- compatible = "fairchild,74hc595";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <2>;
- registers-number = <1>;
- spi-max-frequency = <1000000>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power_amber: led-0 {
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_POWER;
- gpios = <&ssr 6 GPIO_ACTIVE_LOW>;
- panic-indicator;
- };
-
- led_power_green: led-1 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- gpios = <&ssr 5 GPIO_ACTIVE_LOW>;
- };
-
- led-2 {
- /* 2.4GHz blue - activity */
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <0>;
- gpios = <&ssr 4 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- led-3 {
- /* 2.4GHz green - link */
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <0>;
- gpios = <&ssr 3 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0radio";
- };
-
- led-4 {
- /* 5GHz blue - activity */
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <1>;
- gpios = <&ssr 2 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- led-5 {
- /* 5GHz green - link */
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <1>;
- gpios = <&ssr 1 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1radio";
- };
-
- led-6 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_ACTIVITY;
- gpios = <&ssr 0 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x000f0000>;
- read-only;
- };
-
- partition@1e0000 {
- label = "0:MANUDATA";
- reg = <0x001e0000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_manudata_6: macaddr@6 {
- compatible = "mac-base";
- reg = <0x6 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1f0000 {
- label = "0:ART";
- reg = <0x001f0000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- nand@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <48000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs";
- reg = <0x00000000 0x03800000>;
- };
-
- partition@3800000 {
- label = "rootfs_1";
- reg = <0x03800000 0x03800000>;
- };
-
- partition@7000000 {
- label = "var_config";
- reg = <0x07000000 0x00f00000>;
- read-only;
- };
-
- partition@7f00000 {
- label = "Oops_log";
- reg = <0x07f00000 0x000c0000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_manudata_6 0>;
- qcom,ath10k-calibration-variant = "Netgear-WAC510";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_manudata_6 16>;
- qcom,ath10k-calibration-variant = "Netgear-WAC510";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2022, Alexander Couzens <lynxis@fe80.eu> */
-
-#include "qcom-ipq4018-wap-ac.dtsi"
-
-/ {
- model = "MikroTik wAP ac LTE";
- compatible = "mikrotik,wap-ac-lte";
-
- soc {
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
- };
-};
-
-&tlmm {
- enable-usb-power {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable USB power";
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4018-wap-ac.dtsi"
-
-/ {
- model = "MikroTik wAP ac";
- compatible = "mikrotik,wap-ac";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- memory {
- device_type = "memory";
- reg = <0x80000000 0x08000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_user;
- led-failsafe = &led_user;
- led-running = &led_user;
- led-upgrade = &led_user;
- };
-
- soc {
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- led_user: user {
- label = "green:user";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- size = <0x2000>;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@100000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x100000 0xf00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "sw-eth2";
-};
-
-&swport5 {
- status = "okay";
- label = "sw-eth1";
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-wAP-ac";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-wAP-ac";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2022, Alexander Couzens <lynxis@fe80.eu> */
-
-#include "qcom-ipq4018-wap-ac.dtsi"
-
-/ {
- model = "MikroTik wAP R ac";
- compatible = "mikrotik,wap-r-ac";
-
- soc {
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
- };
-};
-
-&tlmm {
- enable-usb-power {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable USB power";
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Linksys WHW01";
- compatible = "linksys,whw01";
-
- aliases {
- serial0 = &blsp1_uart1;
- led-boot = &led_system_blue;
- led-running = &led_system_blue;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- bootargs-append = " root=/dev/ubiblock0_0";
- };
-
- soc {
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- ess_tcsr@1953000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-1 = <&i2c_0_pins>;
- pinctrl-names = "i2c_active", "i2c_sleep";
-
- leds@62 {
- compatible = "nxp,pca9633";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x62>;
-
- /* RGB? */
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_POWER;
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- };
-
- led_system_blue: led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- linux,default-trigger = "default-on";
- };
- };
-};
-
-&blsp1_spi1 {
- status = "okay";
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
-
- nor@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "APPSBL";
- reg = <0xd0000 0xa0000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@180000 {
- label = "u_env";
- reg = <0x180000 0x40000>;
- };
-
- partition@1c0000 {
- label = "s_env";
- reg = <0x1c0000 0x20000>;
- };
-
- partition@1e0000 {
- label = "devinfo";
- reg = <0x1e0000 0x20000>;
- read-only;
- };
- };
- };
-
- nand@1 {
- reg = <1>;
- compatible = "spi-nand";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "kernel";
- reg = <0x0000000 0x5000000>;
- };
-
- partition@600000 {
- label = "rootfs";
- reg = <0x0600000 0x4a00000>;
- };
-
- partition@5000000 {
- label = "alt_kernel";
- reg = <0x5000000 0x5000000>;
- };
-
- partition@5600000 {
- label = "alt_rootfs";
- reg = <0x5600000 0x4a00000>;
- };
-
- partition@a000000 {
- label = "sysdiag";
- reg = <0xa000000 0x0200000>;
- read-only;
- };
-
- partition@a200000 {
- label = "syscfg";
- reg = <0xa200000 0x5e00000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy-reset-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_mdio {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_mdc {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio54", "gpio4";
- };
-
- pinconf {
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinconf_cs {
- pins = "gpio54", "gpio4";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- function = "blsp_i2c0";
- pins = "gpio58", "gpio59";
- bias-disable;
- };
- };
-
- reset_pinmux {
- mux {
- pins = "gpio63";
- bias-pull-up;
- };
- };
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "linksys-whw01-v1";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "linksys-whw01-v1";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "eth1";
-};
-
-&swport5 {
- status = "okay";
- label = "eth2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Pakedge WR-1";
- compatible = "pakedge,wr-1";
-
- aliases {
- label-mac-device = &gmac;
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&key_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power: power {
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- };
-
- wlan2g {
- gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0000000 0x0040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x0040000 0x0020000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x0060000 0x0060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0x00c0000 0x0010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x00d0000 0x0010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0x00e0000 0x0010000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0x00f0000 0x0080000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x0170000 0x0010000>;
- read-only;
- };
-
- partition@180000 {
- label = "firmware";
- reg = <0x0180000 0x1e80000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&prng {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&tlmm {
- key_pins: key_pinmux {
- mux {
- function = "gpio";
- pins = "gpio59";
- bias-pull-up;
- };
- };
-
- led_pins: led_pinmux {
- mux {
- function = "gpio";
- pins = "gpio0", "gpio1", "gpio2";
- bias-none;
- drive-strength = <2>;
- output-low;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- function = "blsp_uart0";
- pins = "gpio60", "gpio61";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- bias-disable;
- drive-strength = <12>;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- bias-disable;
- drive-strength = <2>;
- output-high;
- };
- };
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "Pakedge-WR-1";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "Pakedge-WR-1";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "ZyXEL WRE6606";
- compatible = "zyxel,wre6606";
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- chosen {
- bootargs-append = " mtdparts=";
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g_green {
- label = "green:wlan5g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g_red {
- label = "red:wlan5g";
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_red {
- label = "red:wlan2g";
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_green {
- label = "green:wlan2g";
- gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- mx25l12805d@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition1@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition2@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition3@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition4@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition5@E0000 {
- label = "APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
-
- partition6@F0000 {
- label = "APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition7@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
-
- partition8@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x00180000 0x00ce0000>;
- };
-
- partition9@e60000 {
- label = "manufacture";
- reg = <0x00e60000 0x00050000>;
- read-only;
- };
-
- partition10@eb0000 {
- label = "storage";
- reg = <0x00eb0000 0x00150000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Luma Home WRTQ-329ACN";
- compatible = "luma,wrtq-329acn";
-
- i2c-gpio {
- compatible = "i2c-gpio";
- sda-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- scl-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* No driver exists */
- led_ring@48 {
- compatible = "ti,msp430";
- reg = <0x48>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c16";
- reg = <0x50>;
- pagesize = <16>;
- read-only;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-
-&blsp1_spi1 {
- status = "okay";
-
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x000000 0x040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x040000 0x020000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x060000 0x060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0x0c0000 0x010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x0d0000 0x010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0x0e0000 0x010000>;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0x0f0000 0x080000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0{
- reg = <0x0000 0x0006>;
- };
-
- macaddr_art_6: macaddr@6{
- reg = <0x0006 0x0006>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- flash@1 {
- status = "okay";
-
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x0000000 0x8000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial0_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-ðphy3 {
- status = "disabled";
-};
-
-&mdio {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_art_6>;
-};
-
-&swport5 {
- status = "okay";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_art_0>;
-};
-
-&tlmm {
- serial0_pins: serial0_pinmux {
- mux {
- function = "blsp_uart0";
- pins = "gpio60", "gpio61";
- bias-disable;
- };
- };
-
- spi0_pins: spi0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- bias-disable;
- drive-strength = <12>;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- bias-disable;
- drive-strength = <2>;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
-};
+++ /dev/null
-// SPDX-License-Identifier: ISC
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "OpenMesh A62";
- compatible = "openmesh,a62";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART >;
- };
- };
-
- aliases {
- led-boot = &led_status_green;
- led-failsafe = &led_status_green;
- led-running = &led_status_green;
- led-upgrade = &led_status_green;
- label-mac-device = &swport4;
- };
-
- leds {
- compatible = "gpio-leds";
-
- status_red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_green: status_green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
- };
-
- status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- };
- };
-
- watchdog {
- compatible = "linux,wdt-gpio";
- gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- hw_algo = "toggle";
- /* hw_margin_ms is actually 300s but driver limits it to 60s */
- hw_margin_ms = <60000>;
- always-running;
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- enable-usb-power {
- gpio-hog;
- gpios = <58 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "enable USB2 power";
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- /* partitions are passed via bootloader */
- partitions {
- partition-art {
- label = "0:ART";
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "OM-A62";
- ieee80211-freq-limit = <5170000 5350000>;
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_9000>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "ethernet1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
- status = "okay";
- label = "ethernet2";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "OM-A62";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "OM-A62";
- ieee80211-freq-limit = <5470000 5875000>;
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MobiPromo CM520-79F";
- compatible = "mobipromo,cm520-79f";
-
- aliases {
- led-boot = &led_sys;
- led-failsafe = &led_sys;
- led-running = &led_sys;
- led-upgrade = &led_sys;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <1000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- led_spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
- mosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
- num-chipselects = <0>;
-
- led_gpio: led_gpio@0 {
- compatible = "fairchild,74hc595";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <2>;
- registers-number = <1>;
- spi-max-frequency = <1000000>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "usbport";
- trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
- };
-
- led_sys: can {
- label = "blue:can";
- gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
- };
-
- lan1 {
- label = "blue:lan1";
- gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
- };
-
- lan2 {
- label = "blue:lan2";
- gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g {
- label = "blue:wlan2g";
- gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "blue:wlan5g";
- gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- status = "okay";
-};
-
-&blsp1_uart2 {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "MIBIB";
- reg = <0x100000 0x100000>;
- read-only;
- };
-
- partition@200000 {
- label = "BOOTCONFIG";
- reg = <0x200000 0x100000>;
- };
-
- partition@300000 {
- label = "QSEE";
- reg = <0x300000 0x100000>;
- read-only;
- };
-
- partition@400000 {
- label = "QSEE_1";
- reg = <0x400000 0x100000>;
- read-only;
- };
-
- partition@500000 {
- label = "CDT";
- reg = <0x500000 0x80000>;
- read-only;
- };
-
- partition@580000 {
- label = "CDT_1";
- reg = <0x580000 0x80000>;
- read-only;
- };
-
- partition@600000 {
- label = "BOOTCONFIG1";
- reg = <0x600000 0x80000>;
- };
-
- partition@680000 {
- label = "APPSBLENV";
- reg = <0x680000 0x80000>;
- };
-
- partition@700000 {
- label = "APPSBL";
- reg = <0x700000 0x200000>;
- read-only;
- };
-
- partition@900000 {
- label = "APPSBL_1";
- reg = <0x900000 0x200000>;
- read-only;
- };
-
- art: partition@b00000 {
- label = "ART";
- reg = <0xb00000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- macaddr_art_1006: macaddr@1006 {
- reg = <0x1006 0x6>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- macaddr_art_5006: macaddr@5006 {
- reg = <0x5006 0x6>;
- };
- };
- };
-
- partition@b80000 {
- label = "ubi";
- reg = <0xb80000 0x7480000>;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-
- nvmem-cells = <&macaddr_art_1006>;
- nvmem-cell-names = "mac-address";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-
- nvmem-cells = <&macaddr_art_5006>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "CM520-79F";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "CM520-79F";
-};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- *
- * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
- *
- */
-
-#include "qcom-ipq4019-e2600ac.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Qxwlan E2600AC c1";
- compatible = "qxwlan,e2600ac-c1";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
- };
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C1";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C1";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "sw-eth1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
- status = "okay";
-
- label = "sw-eth2";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- *
- * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
- *
- */
-
-#include "qcom-ipq4019-e2600ac.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Qxwlan E2600AC c2";
- compatible = "qxwlan,e2600ac-c2";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x04000000>;
- };
- };
- };
-};
-
-&tlmm {
- nand_pins: nand-pins {
-
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C2";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C2";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
- label = "sw-eth1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport4 {
- status = "okay";
- label = "sw-eth2";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
- status = "okay";
-
- label = "sw-eth3";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- *
- * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-
- model = "Qxwlan E2600AC";
- compatible = "qcom,ipq4019";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256MB */
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- serial@78af000 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- serial@78b0000 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- i2c@78b7000 { /* BLSP1 QUP2 */
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- };
-
- usb3: usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- leds {
- compatible = "gpio-leds";
-
- led1 {
- label = "green:wlan0";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- led2 {
- label = "green:wlan1";
- gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
- };
-
- led3 {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
- linux,default-trigger = "usbport";
- };
-
- led4 {
- label = "green:ctrl1";
- gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
- };
-
- led5 {
- label = "green:ctrl2";
- gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
- };
-
- led6 {
- label = "green:ctrl3";
- gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- i2c_0_pins: i2c-0-pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_0_pins: serial0-pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq4019-xx8300.dtsi"
-
-/ {
- model = "Linksys EA8300 (Dallas)";
- compatible = "linksys,ea8300", "qcom,ipq4019";
-
-
- aliases {
- led-boot = &led_wps_amber;
- led-failsafe = &led_wps;
- led-running = &led_linksys;
- led-upgrade = &led_world;
- serial0 = &blsp1_uart1;
- };
-
-
- leds {
- compatible = "gpio-leds";
-
- // Retain node names from running OEM on EA8300
-
- // Front panel LEDs, top to bottom
-
- led_plug: diag {
- label = "amber:plug";
- gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
- };
-
- led_world: internet {
- label = "amber:world";
- gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
- };
-
- led_wps: wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- };
-
- led_wps_amber: wps_amber {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_linksys: pwr {
- label = "white:linksys";
- gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
- };
-
- // On back panel, above USB socket
-
- led_usb: usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- trigger-sources = <&usb3_port1>, <&usb3_port2>,
- <&usb2_port1>;
- linux,default-trigger = "usbport";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
-};
-
-&wifi1 {
- status = "okay";
- ieee80211-freq-limit = <5170000 5330000>;
- qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
-};
-
-&wifi2 {
- status = "okay";
- ieee80211-freq-limit = <5490000 5835000>;
- qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "EnGenius EAP2200";
- compatible = "engenius,eap2200";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
- };
-
- lan1 {
- label = "blue:lan1";
- gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
- };
-
- lan2 {
- label = "blue:lan2";
- gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g {
- label = "blue:wlan2g";
- gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "yellow:wlan5g";
- gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- wlan5g2 {
- label = "yellow:wlan5g2";
- gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy2tpt";
- };
-
- mode {
- label = "blue:mode";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition6@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition7@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs1";
- reg = <0x00000000 0x04000000>;
- };
- partition@40000000 {
- label = "ubi";
- reg = <0x04000000 0x04000000>;
- };
-
- };
- };
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_9000>;
- ieee80211-freq-limit = <5470000 5875000>;
- qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
-};
-
-&wifi1 {
- status = "okay";
- ieee80211-freq-limit = <5170000 5350000>;
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "AVM FRITZ!Box 7530";
- compatible = "avm,fritzbox-7530";
-
- chosen {
- bootargs-append = " coherent_pool=4M";
- };
-
- aliases {
- led-boot = &power_green;
- led-failsafe = &info_red;
- led-running = &power_green;
- led-upgrade = &info_red;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wlan {
- label = "wlan";
- gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- dect {
- label = "dect";
- gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_PHONE>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- info_red: info_red {
- label = "red:info";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- };
-
- info {
- label = "green:info";
- gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
- };
-
- fon {
- label = "green:fon";
- gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- };
-
- power_green: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- usb-power {
- line-name = "enable USB3 power";
- gpios = <49 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- /delete-property/ nand-ecc-strength;
- /delete-property/ nand-ecc-step-size;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x000000 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "MIBIB";
- reg = <0x080000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "QSEE";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "CDT";
- reg = <0x180000 0x40000>;
- read-only;
- };
-
- partition@1c0000 {
- label = "QSEE_B";
- reg = <0x1c0000 0x80000>;
- read-only;
- };
-
- partition@240000 {
- label = "urlader0";
- reg = <0x240000 0x40000>;
- read-only;
- };
-
- partition@280000 {
- label = "urlader1";
- reg = <0x280000 0x40000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "nand-tffs";
- reg = <0x2c0000 0x840000>;
- read-only;
- };
-
- partition@b00000 {
- /* 'kernel1' in AVM firmware */
- label = "uboot0";
- reg = <0xb00000 0x400000>;
- };
-
- partition@f00000 {
- /* 'kernel2' in AVM firmware */
- label = "uboot1";
- reg = <0xf00000 0x400000>;
- };
-
- partition@1300000 {
- label = "ubi";
- reg = <0x1300000 0x6d00000>;
- };
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- dsl@1,0 {
- compatible = "intel,vrx518";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "AVM FRITZ!Repeater 1200";
- compatible = "avm,fritzrepeater-1200";
-
- aliases {
- led-boot = &power_green;
- led-failsafe = &power_red;
- led-running = &power_green;
- led-upgrade = &power_red;
- label-mac-device = &wifi0;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- ethphy: ethernet-phy@0 {
- reg = <0x0>;
- };
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- key {
- compatible = "gpio-keys";
-
- wps {
- label = "WPS button";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power_red: power_red {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
- };
-
- power_yellow {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- phy-reset {
- line-name = "PHY-reset";
- gpios = <19 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-
- phy-reset-2 {
- line-name = "PHY-reset-2";
- gpios = <47 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "MIBIB";
- reg = <0x80000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "QSEE";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "CDT";
- reg = <0x180000 0x40000>;
- read-only;
- };
-
- partition@1c0000 {
- label = "QSEE_B";
- reg = <0x1c0000 0x80000>;
- read-only;
- };
-
- partition@240000 {
- label = "urlader0";
- reg = <0x240000 0x40000>;
- read-only;
- };
-
- partition@280000 {
- label = "urlader1";
- reg = <0x280000 0x40000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "nand-tffs";
- reg = <0x2c0000 0x840000>;
- read-only;
- };
-
- partition@b00000 {
- /* 'kernel1' in AVM firmware */
- label = "uboot0";
- reg = <0xb00000 0x400000>;
- };
-
- partition@f00000 {
- /* 'kernel2' in AVM firmware */
- label = "uboot1";
- reg = <0xf00000 0x400000>;
- };
-
- partition@1300000 {
- label = "ubi";
- reg = <0x1300000 0x6d00000>;
- };
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-
- /delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
- phy-handle = <ðphy>;
- phy-mode = "rgmii-id";
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-ðphy2 {
- status = "disabled";
-};
-
-ðphy3 {
- status = "disabled";
-};
-
-ðphy4 {
- status = "disabled";
-};
-
-&psgmiiphy {
- status = "disabled";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "AVM FRITZ!Repeater 3000";
- compatible = "avm,fritzrepeater-3000";
-
- aliases {
- led-boot = &power_led;
- led-failsafe = &power_led;
- led-running = &power_led;
- led-upgrade = &power_led;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- key {
- compatible = "gpio-keys";
-
- connect {
- label = "Connect";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- connect_red {
- label = "red:connect";
- gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
- };
-
- connect_green {
- label = "green:connect";
- gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
- };
-
- connect_blue {
- label = "blue:connect";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- };
-
- power_led: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- /delete-property/ nand-ecc-strength;
- /delete-property/ nand-ecc-step-size;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x000000 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "MIBIB";
- reg = <0x080000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "QSEE";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "CDT";
- reg = <0x180000 0x40000>;
- read-only;
- };
-
- partition@1c0000 {
- label = "QSEE_B";
- reg = <0x1c0000 0x80000>;
- read-only;
- };
-
- partition@240000 {
- label = "urlader0";
- reg = <0x240000 0x40000>;
- read-only;
- };
-
- partition@280000 {
- label = "urlader1";
- reg = <0x280000 0x40000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "nand-tffs";
- reg = <0x2c0000 0x840000>;
- read-only;
- };
-
- partition@b00000 {
- /* 'kernel1' in AVM firmware */
- label = "uboot0";
- reg = <0xb00000 0x400000>;
- };
-
- partition@f00000 {
- /* 'kernel2' in AVM firmware */
- label = "uboot1";
- reg = <0xf00000 0x400000>;
- };
-
- partition@1300000 {
- label = "ubi";
- reg = <0x1300000 0x6d00000>;
- };
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- /* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
- qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
-};
-
-&wifi1 {
- status = "okay";
- ieee80211-freq-limit = <5170000 5350000>;
- /* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
- qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- /* QCA9984 */
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- ieee80211-freq-limit = <5470000 5875000>;
- /* Uses the reference BDF */
- };
- };
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "GL.iNet GL-B2200";
- compatible = "glinet,gl-b2200", "qcom,ipq4019";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- bootargs-append = " root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused";
- };
-
- aliases {
- ethernet1 = &swport4;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- linux,input-type = <1>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- linux,input-type = <1>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power_blue {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- internet_blue {
- label = "blue:internet";
- gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
- };
- power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- };
- internet_white {
- label = "white:internet";
- gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- cd-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vqmmc>;
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_spi2 {
- pinctrl-0 = <&spi_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- spidev1: spi@0 {
- compatible = "silabs,si3210";
- reg = <0>;
- spi-max-frequency = <24000000>;
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- };
- pinconf {
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- spi_1_pins: spi_1_pinmux {
- mux {
- pins = "gpio44", "gpio46", "gpio47";
- function = "blsp_spi1";
- bias-disable;
- };
- cs {
- pins = "gpio45";
- function = "gpio";
- bias-pull-up;
- };
- reset {
- pins = "gpio43";
- function = "gpio";
- output-high;
- };
- mux_2 {
- pins = "gpio35";
- function = "gpio";
- output-high;
- };
- host_int {
- pins = "gpio2";
- function = "gpio";
- input;
- };
- wake {
- pins = "gpio48";
- function = "gpio";
- output-high;
- };
- };
-
- sd_pins: sd_pins {
- pinmux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio29", "gpio30", "gpio31", "gpio32";
- drive-strength = <10>;
- };
-
- pinmux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
-
- pinmux_sd7 {
- function = "sdio";
- pins = "gpio28";
- drive-strength = <10>;
- bias-disable;
- };
- };
-
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- status = "okay";
- /* Bootlog shows this is a 168c:0056 - QCA 9888v2 */
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_9000>;
- qcom,ath10k-calibration-variant = "GL-B2200";
- ieee80211-freq-limit = <5450000 5900000>;
- };
- };
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "wan";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "GL-B2200";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "GL-B2200";
- ieee80211-freq-limit = <5100000 5400000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2019, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "8devices Habanero DVK";
- compatible = "8dev,habanero-dvk";
-
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_upgrade;
- ethernet1 = &swport5;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- usb3: usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_upgrade: upgrade {
- label = "green:upgrade";
- gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
- };
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
-
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vqmmc>;
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56", "gpio57",
- "gpio60", "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67", "gpio68",
- "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- sd_pins: sd_pins {
- pinmux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio28", "gpio29", "gpio30", "gpio31";
- drive-strength = <10>;
- };
-
- pinmux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
-
- pinmux_sd7 {
- function = "sdio";
- pins = "gpio32";
- drive-strength = <10>;
- bias-disable;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env */
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition@180000 {
- label = "cfg";
- reg = <0x00180000 0x00040000>;
- };
- partition@1c0000 {
- label = "firmware";
- compatible = "denx,fit";
- reg = <0x001c0000 0x01e40000>;
- };
- };
- };
-};
-
-/* Some DVK boards ship without NAND */
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- /* Free slot for use */
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- };
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "8devices-Habanero";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "8devices-Habanero";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MikroTik hAP ac3 LTE6 kit";
- compatible = "mikrotik,hap-ac3-lte6-kit";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_status_blue;
- led-failsafe = &led_status_red;
- led-running = &led_status_blue;
- led-upgrade = &led_status_red;
- };
-
- soc {
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_blue: status-blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_red: status-red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_status_green: status-green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
- };
-
- ethernet {
- label = "green:ethernet";
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
- };
-
- lan1 {
- label = "green:lan1";
- gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
- };
-
- lan2 {
- label = "green:lan2";
- gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
- };
-
- lan3 {
- label = "green:lan3";
- gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
- };
-
- lan4 {
- label = "green:lan4";
- gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- enable-usb-power {
- gpio-hog;
- gpios = <44 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable USB power";
- };
-
- enable-mpcie-power {
- gpio-hog;
- gpios = <51 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable mPCI-E power";
- };
-
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <10000000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
-
- partitions {
- compatible = "fixed-partitions";
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- size = <0x2000>;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@110000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x110000 0xef0000>;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&blsp1_uart1 {
- status = "okay";
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
-};
-
-&wifi1 {
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&prng {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MikroTik hAP ac3";
- compatible = "mikrotik,hap-ac3";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_status_blue;
- led-failsafe = &led_status_red;
- led-running = &led_status_blue;
- led-upgrade = &led_status_red;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- mode {
- label = "mode";
- gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- };
-
- led {
- label = "led";
- gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_blue: status-blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_red: status-red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_status_green: status-green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
- };
-
- ethernet {
- label = "green:ethernet";
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
- };
-
- lan1 {
- label = "green:lan1";
- gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
- };
-
- lan2 {
- label = "green:lan2";
- gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
- };
-
- lan3 {
- label = "green:lan3";
- gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
- };
-
- lan4 {
- label = "green:lan4";
- gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
- };
-
- poe {
- label = "red:poe";
- gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio55", "gpio56", "gpio57", "gpio60",
- "gpio62", "gpio63", "gpio64", "gpio65",
- "gpio66", "gpio67", "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- enable-usb-power {
- gpio-hog;
- gpios = <44 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable USB power";
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- size = <0x2000>;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "kernel";
- reg = <0x0 0xa00000>;
- };
-
- partition@a00000 {
- label = "ubi";
- reg = <0xa00000 0x7600000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-hAP-ac3";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-hAP-ac3";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Netgear LBR20";
- compatible = "netgear,lbr20";
-
- chosen {
- bootargs-append = "ubi.mtd=ubi root=/dev/ubiblock0_0";
- };
-
- aliases {
- led-boot = &led_backlight_white;
- led-failsafe = &led_status_green;
- led-running = &led_status_green;
- led-upgrade = &led_status_red;
- label-mac-device = &gmac;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_green: led-status-green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- led_status_red: led-status-red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- lte_rst {
- gpio-export,name = "lte_rst";
- gpio-export,output = <1>;
- gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
- };
-
- lte_pwrkey {
- gpio-export,name = "lte_pwrkey";
- gpio-export,output = <1>;
- gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
- };
-
- lte_usb_boot {
- gpio-export,name = "lte_usb_boot";
- gpio-export,output = <0>;
- gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
- };
-
- lte_pwm {
- gpio-export,name = "lte_pwm";
- gpio-export,output = <1>;
- gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
- };
-
- };
-
- soc {
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-};
-
-&crypto {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio-pinmux {
- mux_mdio {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_mdc {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial-pinmux {
- function = "blsp_uart0";
- pins = "gpio16", "gpio17";
- bias-disable;
- };
-
- nand_pins: nand-pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00100000>;
- read-only;
- };
-
- partition@100000 {
- label = "0:MIBIB";
- reg = <0x00100000 0x00100000>;
- read-only;
- };
-
- partition@200000 {
- label = "0:BOOTCONFIG";
- reg = <0x00200000 0x00100000>;
- read-only;
- };
-
- partition@300000 {
- label = "0:QSEE";
- reg = <0x00300000 0x00100000>;
- read-only;
- };
-
- partition@400000 {
- label = "0:QSEE_1";
- reg = <0x00400000 0x00100000>;
- read-only;
- };
-
- partition@500000 {
- label = "0:CDT";
- reg = <0x00500000 0x00080000>;
- read-only;
- };
-
- partition@580000 {
- label = "0:CDT_1";
- reg = <0x00580000 0x00080000>;
- read-only;
- };
-
- partition@600000 {
- label = "0:BOOTCONFIG1";
- reg = <0x00600000 0x00080000>;
- read-only;
- };
-
- partition@680000 {
- label = "0:APPSBLENV";
- reg = <0x00680000 0x00080000>;
- };
-
- partition@700000 {
- label = "0:APPSBL";
- reg = <0x00700000 0x00200000>;
- read-only;
- };
-
- partition@900000 {
- label = "0:APPSBL_1";
- reg = <0x00900000 0x00200000>;
- read-only;
- };
-
- partition@b00000 {
- label = "0:ART";
- reg = <0x00b00000 0x00080000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
-
- };
- };
-
- partition@b80000 {
- label = "0:ART.bak";
- reg = <0x00b80000 0x00080000>;
- read-only;
- };
-
- partition@c00000 {
- label = "config";
- reg = <0x00c00000 0x00100000>;
- read-only;
- };
-
- partition@d00000 {
- label = "boarddata1";
- reg = <0x00d00000 0x00080000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- mac_address_lan: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- mac_address_wan: macaddr@6 {
- compatible = "mac-base";
- reg = <0x6 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- mac_address_wlan_5g: macaddr@c {
- compatible = "mac-base";
- reg = <0xc 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- mac_address_wlan_2nd5g: macaddr@12 {
- compatible = "mac-base";
- reg = <0x12 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- };
- };
-
- partition@d80000 {
- label = "boarddata2";
- reg = <0x00d80000 0x00040000>;
- read-only;
- };
-
- partition@dc0000 {
- label = "pot";
- reg = <0x00dc0000 0x00100000>;
- read-only;
- };
-
- partition@ec0000 {
- label = "boarddata1.bak";
- reg = <0x00ec0000 0x00080000>;
- read-only;
- };
-
- partition@f40000 {
- label = "boarddata2.bak";
- reg = <0x00f40000 0x00040000>;
- read-only;
- };
-
- partition@f80000 {
- label = "language";
- reg = <0x00f80000 0x00300000>;
- read-only;
- };
-
- partition@1280000 {
- label = "cert";
- reg = <0x01280000 0x00080000>;
- read-only;
- };
-
- partition@1300000 {
- label = "ntgrdata";
- reg = <0x01300000 0x09300000>;
- };
-
- partition@a600000 {
- label = "kernel";
- reg = <0x0a600000 0x00700000>;
- };
-
- partition@a9c0000 {
- label = "ubi";
- reg = <0x0ad00000 0x05300000>;
- };
-
- };
- };
-};
-
-&blsp1_i2c3 {
- status = "okay";
-
- led-controller {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,tlc59108"; /* really is tlc59208f */
- reg = <0x27>;
-
- led_backlight_green: led-backlight-green {
- function = LED_FUNCTION_BACKLIGHT;
- color = <LED_COLOR_ID_GREEN>;
- reg = <0x0>;
- linux,default-trigger = "default-off";
- };
-
- led_backlight_red: led-backlight-red {
- function = LED_FUNCTION_BACKLIGHT;
- color = <LED_COLOR_ID_RED>;
- reg = <0x1>;
- linux,default-trigger = "default-off";
- };
-
- led_backlight_blue: led-backlight-blue {
- function = LED_FUNCTION_BACKLIGHT;
- color = <LED_COLOR_ID_BLUE>;
- reg = <0x2>;
- linux,default-trigger = "default-off";
- };
-
- led_backlight_white: led-backlight-white {
- function = LED_FUNCTION_BACKLIGHT;
- color = <LED_COLOR_ID_WHITE>;
- reg = <0x3>;
- linux,default-trigger = "default-off";
- };
-
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&mac_address_lan 0>;
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
- label = "lan2";
-};
-
-&pcie0 {
- status = "okay";
- perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- ieee80211-freq-limit = <5170000 5350000>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_9000>, <&mac_address_wlan_2nd5g 0>;
- qcom,ath10k-calibration-variant = "Netgear-LBR20";
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&mac_address_lan 0>;
- qcom,ath10k-calibration-variant = "Netgear-LBR20";
-};
-
-&wifi1 {
- status = "okay";
- ieee80211-freq-limit = <5470000 5815000>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&mac_address_wlan_5g 0>;
- qcom,ath10k-calibration-variant = "Netgear-LBR20";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "YYeTs LE1";
- compatible = "yyets,le1";
-
- aliases {
- led-boot = &led_usb;
- led-failsafe = &led_usb;
- led-upgrade = &led_usb;
-
- ethernet0 = &swport5;
- ethernet1 = &gmac;
- label-mac-device = &gmac;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_usb: usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "usbport";
- trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&prng {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cells = <&precal_art_1000>;
- nvmem-cell-names = "pre-calibration";
- qcom,ath10k-calibration-variant = "YYeTs-LE1";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cells = <&precal_art_5000>;
- nvmem-cell-names = "pre-calibration";
- qcom,ath10k-calibration-variant = "YYeTs-LE1";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2019, Robert Marko <robimarko@gmail.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Mikrotik Wireless Wire Dish LHGG-60ad";
- compatible = "mikrotik,lhgg-60ad";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &user;
- led-failsafe = &user;
- led-running = &user;
- led-upgrade = &user;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- panic-indicator;
- };
-
- user: user {
- label = "yellow:user";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-
- align-left {
- label = "green:align-left";
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- align-right {
- label = "green:align-right";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
-
- wlan-rx {
- label = "green:align-down";
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
-
- wlan-tx {
- label = "green:align-up";
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi-0-pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- m25p80@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- size = <0x2000>;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@100000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x100000 0xf00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- /* wil6210 802.11ad card */
- wifi: wifi@1,0 {
- status = "okay";
- /* wil6210 driver has no compatible */
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-ðphy2 {
- status = "disabled";
-};
-
-ðphy3 {
- status = "disabled";
-};
-
-ðphy4 {
- status = "disabled";
-};
-
-&psgmiiphy {
- status = "disabled";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-
- /delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
- phy-handle = <ðphy0>;
- phy-mode = "rgmii-id";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ASUS Lyra MAP-AC2200";
- compatible = "asus,map-ac2200";
-
- aliases {
- led-boot = &led_blue0;
- led-failsafe = &led_red0;
- led-running = &led_blue0;
- led-upgrade = &led_red0;
- ethernet1 = &swport4;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "MIBIB";
- reg = <0x80000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "QSEE";
- reg = <0x100000 0x100000>;
- read-only;
- };
-
- partition@200000 {
- label = "CDT";
- reg = <0x200000 0x80000>;
- read-only;
- };
-
- partition@280000 {
- label = "APPSBL";
- reg = <0x280000 0x140000>;
- read-only;
- };
-
- partition@3c0000 {
- label = "APPSBLENV";
- reg = <0x3c0000 0x40000>;
- read-only;
- };
-
- partition@400000 {
- label = "ubi";
- reg = <0x400000 0x7c00000>;
- };
- };
- };
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- pinmux {
- function = "blsp_i2c0";
- pins = "gpio20", "gpio21";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
- enable_ext_pa_high {
- gpio-hog;
- gpios = <44 GPIO_ACTIVE_HIGH>,
- <46 GPIO_ACTIVE_HIGH>;
- output-high;
- bias-pull-down;
- line-name = "enable external PA output-high";
- };
- enable_ext_pa_low {
- gpio-hog;
- gpios = <45 GPIO_ACTIVE_HIGH>,
- <47 GPIO_ACTIVE_HIGH>;
- output-low;
- bias-pull-down;
- line-name = "enable external PA output-low";
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
- ieee80211-freq-limit = <5470000 5875000>;
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
- ieee80211-freq-limit = <5170000 5350000>;
- };
- };
-};
-
-&usb2_hs_phy {
- /* Bluetooth module attached via USB */
- status = "okay";
-};
-
-&blsp1_i2c3 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- led-controller@32 {
- /* 9-channel RGB LED controller */
- compatible = "national,lp5523";
- reg = <0x32>;
- clock-mode = /bits/ 8 <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /*
- * There is only one single extremely bright RGB-LED.
- * The RGB-color channels are running in parallel to
- * increase the current delivery capabilities beyond
- * what a single PWM-output of the controller can do.
- */
-
- led_blue0: led@0 {
- chan-name = "blue-0";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <0>;
- color = <LED_COLOR_ID_BLUE>;
- function-enumerator = <0>;
- };
-
- led@1 {
- chan-name = "blue-1";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <1>;
- color = <LED_COLOR_ID_BLUE>;
- function-enumerator = <1>;
- };
-
- led@2 {
- chan-name = "blue-2";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <2>;
- color = <LED_COLOR_ID_BLUE>;
- function-enumerator = <2>;
- };
-
- led_green0: led@3 {
- chan-name = "green-0";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <3>;
- color = <LED_COLOR_ID_GREEN>;
- function-enumerator = <0>;
- };
-
- led@4 {
- chan-name = "green-1";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <4>;
- color = <LED_COLOR_ID_GREEN>;
- function-enumerator = <1>;
- };
-
- led@5 {
- chan-name = "green-2";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <5>;
- color = <LED_COLOR_ID_GREEN>;
- function-enumerator = <2>;
- };
-
- led_red0: led@6 {
- chan-name = "red-0";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <6>;
- color = <LED_COLOR_ID_RED>;
- function-enumerator = <0>;
- };
-
- led@7 {
- chan-name = "red-1";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <7>;
- color = <LED_COLOR_ID_RED>;
- function-enumerator = <1>;
- };
-
- led@8 {
- chan-name = "red-2";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <8>;
- color = <LED_COLOR_ID_RED>;
- function-enumerator = <2>;
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "wan";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Marcin Gajda <mgajda@o2.pl>.
-
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ZTE MF18A";
- compatible = "zte,mf18a";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- chosen {
- /*
- * bootargs forced by u-boot bootipq command:
- * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
- */
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_internal: led-0 {
- label = "blue:internal";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- led_power: led-1 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- led-2 {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- led-3 {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
- };
-
- led-4 {
- function = LED_FUNCTION_WLAN;
- label = "blue:smart";
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- led-5 {
- label = "red:smart";
- gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
- };
-
- resetzwave {
- label = "resetzwave";
- gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- /* u-boot is looking for "n25q128a11" property */
- compatible = "jedec,spi-nor", "n25q128a11";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_config_0 0>;
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-
- label = "wan";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_config_0 1>;
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan";
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0xa0000>;
- read-only;
- };
-
- partition@a0000 {
- label = "ART";
- reg = <0xa0000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
-
- partition@120000 {
- label = "mac";
- reg = <0x120000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_config_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1a0000 {
- label = "reserved2";
- reg = <0x1a0000 0xc0000>;
- read-only;
- };
-
- partition@260000 {
- label = "cfg-param";
- reg = <0x260000 0x400000>;
- read-only;
- };
-
- partition@660000 {
- label = "log";
- reg = <0x660000 0x400000>;
- };
-
- partition@a60000 {
- label = "oops";
- reg = <0xa60000 0xa0000>;
- };
-
- partition@b00000 {
- label = "reserved3";
- reg = <0xb00000 0x500000>;
- read-only;
- };
-
- partition@1000000 {
- label = "web";
- reg = <0x1000000 0x800000>;
- };
-
- partition@1800000 {
- label = "rootfs";
- reg = <0x1800000 0x1d00000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x2800000>;
-
- };
- partition@7600000 {
- label = "iot-db";
- reg = <0x7600000 0xa00000>;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 2>;
- qcom,ath10k-calibration-variant = "ZTE-MF18A";
-};
-
-//* This node is used for 5Ghz on QCA9982 */
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
- clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "pci168c,0040";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_9000>, <&macaddr_config_0 3>;
- qcom,ath10k-calibration-variant = "ZTE-MF18A";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ZTE MF282Plus";
- compatible = "zte,mf282plus";
-
- aliases {
- led-boot = &led_internal;
- led-failsafe = &led_internal;
- led-running = &led_internal;
- led-upgrade = &led_internal;
- };
-
- chosen {
- /*
- * bootargs forced by u-boot bootipq command:
- * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
- */
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- modem {
- gpio-export,name = "modem-reset";
- gpio-export,output = <0>;
- gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_internal: led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- label = "blue:internal_led";
- default-state = "keep";
- };
-
- led-1 {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wifi {
- label = "wifi";
- linux,code = <KEY_RFKILL>;
- gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
- };
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- /* u-boot is looking for "n25q128a11" property */
- compatible = "jedec,spi-nor", "n25q128a11";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_config_0 0>;
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0xa0000>;
- read-only;
- };
-
- partition@a0000 {
- label = "ART";
- reg = <0xa0000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@120000 {
- label = "mac";
- reg = <0x120000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_config_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1a0000 {
- label = "reserved2";
- reg = <0x1a0000 0xc0000>;
- read-only;
- };
-
- partition@260000 {
- label = "cfg-param";
- reg = <0x260000 0x400000>;
- read-only;
- };
-
- partition@660000 {
- label = "log";
- reg = <0x660000 0x400000>;
- };
-
- partition@a60000 {
- label = "oops";
- reg = <0xa60000 0xa0000>;
- };
-
- partition@b00000 {
- label = "reserved3";
- reg = <0xb00000 0x500000>;
- read-only;
- };
-
- partition@1000000 {
- label = "web";
- reg = <0x1000000 0x800000>;
- };
-
- partition@1800000 {
- label = "rootfs";
- reg = <0x1800000 0x1d00000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x2800000>;
- };
-
- partition@7600000 {
- label = "extra-cfg";
- reg = <0x7600000 0xa00000>;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-/*
- * The MD5 sum of the board file of the MF286D is identical to the board
- * file in the OEM firmware
- */
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 1>;
- qcom,ath10k-calibration-variant = "zte,mf286d";
-};
-
-/*
- * The MD5 sum of the board file of the MF286D is identical to the board
- * file in the OEM firmware
- */
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_config_0 1>;
- qcom,ath10k-calibration-variant = "zte,mf286d";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ZTE MF286D";
- compatible = "zte,mf286d";
-
- aliases {
- led-boot = &led_internal;
- led-failsafe = &led_internal;
- led-running = &led_internal;
- led-upgrade = &led_internal;
- };
-
- chosen {
- /*
- * bootargs forced by u-boot bootipq command:
- * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
- */
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_internal: led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- label = "blue:internal_led";
- default-state = "keep";
- };
-
- led-1 {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wifi {
- label = "wifi";
- linux,code = <KEY_RFKILL>;
- gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
- };
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- /* u-boot is looking for "n25q128a11" property */
- compatible = "jedec,spi-nor", "n25q128a11";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_config_0 0>;
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0xa0000>;
- read-only;
- };
-
- partition@a0000 {
- label = "ART";
- reg = <0xa0000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@120000 {
- label = "mac";
- reg = <0x120000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_config_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1a0000 {
- label = "reserved2";
- reg = <0x1a0000 0xc0000>;
- read-only;
- };
-
- partition@260000 {
- label = "cfg-param";
- reg = <0x260000 0x400000>;
- read-only;
- };
-
- partition@660000 {
- label = "log";
- reg = <0x660000 0x400000>;
- };
-
- partition@a60000 {
- label = "oops";
- reg = <0xa60000 0xa0000>;
- };
-
- partition@b00000 {
- label = "reserved3";
- reg = <0xb00000 0x500000>;
- read-only;
- };
-
- partition@1000000 {
- label = "web";
- reg = <0x1000000 0x800000>;
- };
-
- partition@1800000 {
- label = "rootfs";
- reg = <0x1800000 0x1d00000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x3200000>;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan4";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport5 {
- status = "okay";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_config_0 1>;
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 2>;
- qcom,ath10k-calibration-variant = "zte,mf286d";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_config_0 3>;
- qcom,ath10k-calibration-variant = "zte,mf286d";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ZTE MF289F";
- compatible = "zte,mf289f";
-
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- };
-
- chosen {
- /*
- * bootargs forced by u-boot bootipq command:
- * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
- */
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- /*
- * This node is used to restart modem module to avoid anomalous
- * behaviours on initial communication.
- */
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status: led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- };
-
- led-1 {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- key-reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
-
- key-wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
-};
-
-&watchdog {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>,
- <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-
- spi-nand@1 { /* flash@1 ? */
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0xa0000>;
- read-only;
- };
-
- partition@a0000 {
- label = "ART";
- reg = <0xa0000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@120000 {
- label = "mac";
- reg = <0x120000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mac_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1a0000 {
- label = "reserved2";
- reg = <0x1a0000 0xc0000>;
- read-only;
- };
-
- partition@260000 {
- label = "cfg-param";
- reg = <0x260000 0x400000>;
- read-only;
- };
-
- partition@660000 {
- label = "log";
- reg = <0x660000 0x400000>;
- };
-
- partition@a60000 {
- label = "oops";
- reg = <0xa60000 0xa0000>;
- };
-
- partition@b00000 {
- label = "reserved3";
- reg = <0xb00000 0x500000>;
- read-only;
- };
-
- partition@1000000 {
- label = "web";
- reg = <0x1000000 0x800000>;
- };
-
- partition@1800000 {
- label = "rootfs";
- reg = <0x1800000 0x1d00000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x3200000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_mac_0 0>;
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-
- label = "wan";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_mac_0 1>;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12", "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_mac_0 2>;
- qcom,ath10k-calibration-variant = "zte,mf289f";
-};
-
-/* This node is used only on AT2 version for 5Ghz on IPQ4019 with board-id=21 */
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_mac_0 3>;
- qcom,ath10k-calibration-variant = "zte,mf289f";
-};
-
-/* This node is used only on AT1 version for 5Ghz on QCA9984 */
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
- clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_mac_0 4>;
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "zte,mf289f";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq4019-xx8300.dtsi"
-
-/ {
- model = "Linksys MR8300 (Dallas)";
- compatible = "linksys,mr8300", "qcom,ipq4019";
-
- aliases {
- led-boot = &led_blue;
- led-failsafe = &led_red;
- led-running = &led_blue;
- led-upgrade = &led_amber;
- serial0 = &blsp1_uart1;
- };
-
- // Top panel LEDs, above Linksys logo
- leds {
- compatible = "gpio-leds";
-
- led_red: red {
- function = LED_FUNCTION_ALARM;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
- };
-
- led_amber: amber {
- function = LED_FUNCTION_PROGRAMMING;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_blue: blue {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- };
-
- // On back panel, above USB socket
-
- led_usb: usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- trigger-sources = <&usb3_port1>, <&usb3_port2>,
- <&usb2_port1>;
- linux,default-trigger = "usbport";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
-};
-
-&wifi1 {
- status = "okay";
- ieee80211-freq-limit = <5170000 5330000>;
- qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
-};
-
-&wifi2 {
- status = "okay";
- ieee80211-freq-limit = <5490000 5835000>;
- qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Sony NCP-HG100/Cellular";
- compatible = "sony,ncp-hg100-cellular";
-
- aliases {
- led-boot = &led_cloud_green;
- led-failsafe = &led_cloud_red;
- led-running = &led_cloud_green;
- led-upgrade = &led_cloud_green;
- label-mac-device = &gmac;
- };
-
- chosen {
- bootargs = "console=ttyMSM0,115200n8 root=/dev/mmcblk0p15 rootfstype=squashfs,ext4";
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-
- soc {
- tcsr@1949000 {
- status = "okay";
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- status = "okay";
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- status = "okay";
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- dma@7984000 {
- status = "okay";
- };
- };
-
- keys-repeat {
- compatible = "gpio-keys";
- pinctrl-0 = <&keys_pins>;
- pinctrl-names = "default";
- autorepeat;
-
- key-volup {
- label = "volume up";
- linux,code = <KEY_VOLUMEUP>;
- gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
- linux,input-type = <EV_KEY>;
- };
-
- key-voldown {
- label = "volume down";
- linux,code = <KEY_VOLUMEDOWN>;
- gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
- linux,input-type = <EV_KEY>;
- };
-
- key-alexatrigger {
- label = "alexa trigger";
- linux,code = <BTN_0>;
- gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
- linux,input-type = <EV_KEY>;
- };
-
- key-mute {
- label = "mic mute";
- linux,code = <BTN_1>;
- gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_SW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- key-reset {
- label = "reset";
- gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- key-wps {
- label = "setup";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-};
-
-&tlmm {
- pinctrl-0 = <&bt_pins>, <&aud_pins>, <&mcu_pins>;
- pinctrl-names = "default";
-
- /*
- * uart0 is shared for debug console and Z-Wave,
- * use only for debug console in OpenWrt.
- *
- * 1: debug console
- * 0: Z-Wave
- */
- uart0_ctrl_pins: uart0_ctrl_pinmux {
- mux {
- pins = "gpio15";
- function = "gpio";
- output-high;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- /*
- * reset pin for Z-Wave
- * active-low, >= 20ns
- */
- zwave_pins: zwave_pinmux {
- mux {
- pins = "gpio59";
- function = "gpio";
- output-high;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- bt_pins: bt_pinmux {
- mux_reset {
- pins = "gpio66";
- function = "gpio";
- output-high;
- };
-
- mux_pwr {
- pins = "gpio68";
- function = "gpio";
- output-high;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- i2c_1_pins: i2c_1_pinmux {
- mux {
- pins = "gpio12", "gpio13";
- function = "blsp_i2c1";
- bias-disable;
- };
- };
-
- keys_pins: keys_pinmux {
- mux_1 {
- pins = "gpio39", "gpio40", "gpio42", "gpio47";
- function = "gpio";
- bias-disable;
- };
-
- mux_2 {
- pins = "gpio2";
- function = "gpio";
- input;
- };
- };
-
- sd_pins: sd_pins {
- mux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio28", "gpio29", "gpio30", "gpio31";
- drive-strength = <4>;
- };
-
- mux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
-
- mux_sd7 {
- function = "sdio";
- pins = "gpio32";
- drive-strength = <4>;
- bias-disable;
- };
- };
-
- aud_pins: aud_pinmux {
- mux {
- pins = "gpio48", "gpio49", "gpio50", "gpio51";
- function = "aud_pin";
- };
- };
-
- alc1304_pins: alc1304_pinmux {
- mux_1 {
- pins = "gpio44";
- function = "gpio";
- bias-disable;
- };
-
- mux_2 {
- pins = "gpio45";
- function = "gpio";
- bias-disable;
- };
- };
-
- cx2902x_reset: cx2902x_pinmux {
- mux_1 {
- pins = "gpio64";
- function = "gpio";
- bias-disable;
- };
-
- mux_2 {
- pins = "gpio65";
- function = "gpio";
- bias-disable;
- };
- };
-
- lte_pins: lte_pinmux {
- mux_en {
- pins = "gpio20";
- function = "gpio";
- output-high;
- };
-
- mux_reset {
- pins = "gpio35";
- function = "gpio";
- input;
- };
- };
-
- usb3_pins: usb3_pinmux {
- mux_en {
- pins = "gpio36";
- function = "gpio";
- output-high;
- };
-
- mux_flt {
- pins = "gpio4";
- function = "gpio";
- input;
- };
- };
-
- mcu_pins: mcu_pinmux {
- mux_boot {
- pins = "gpio38";
- function = "gpio";
- output-low;
- };
-
- mux_reset {
- pins = "gpio5";
- function = "gpio";
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_i2c4 {
- /*
- * There is no driver for the following devices:
- * - CY8C4014LQI@14 : Touch-Sensor for buttons on top
- * - MINI54FDE@15 : MCU for Fan/RGB LED/Thermal control
- * - ALC5629@18 : I2S/PCM Audio DAC
- * - CX20924@41 : Voice Input Processor
- */
- pinctrl-0 = <&i2c_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- led-controller@32 {
- compatible = "ti,lp55231";
- reg = <0x32>;
- clock-mode = /bits/ 8 <0>;
- enable-gpio = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- chan-name = "green:wan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- };
-
- led@1 {
- chan-name = "blue:wan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x1>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WAN;
- };
-
- led@2 {
- chan-name = "green:lan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- };
-
- led@3 {
- chan-name = "blue:lan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x3>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- };
-
- led@4 {
- chan-name = "green:wlan-2";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x4>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <2>;
- linux,default-trigger = "phy0tpt";
- };
-
- led@5 {
- chan-name = "blue:wlan-2";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x5>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <2>;
- };
-
- led@6 {
- chan-name = "red:wan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x6>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_WAN;
- };
-
- led@7 {
- chan-name = "red:lan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x7>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_LAN;
- };
-
- led@8 {
- chan-name = "red:wlan-2";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x8>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <2>;
- };
- };
-
- led-controller@33 {
- compatible = "ti,lp55231";
- reg = <0x33>;
- clock-mode = /bits/ 8 <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- chan-name = "green:wlan-5";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WLAN;
- linux,default-trigger = "phy1tpt";
- function-enumerator = <5>;
- };
-
- led@1 {
- chan-name = "blue:wlan-5";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x1>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <5>;
- };
-
- led@2 {
- chan-name = "green:wan-4";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN; /* WWAN/LTE/4G */
- function-enumerator = <4>; /* WWAN/LTE/4G */
- };
-
- led@3 {
- chan-name = "blue:wan-4";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x3>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WAN; /* WWAN/LTE/4G */
- function-enumerator = <4>; /* WWAN/LTE/4G */
- };
-
- led_cloud_green: led@4 {
- chan-name = "green:power";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x4>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- };
-
- led@5 {
- chan-name = "blue:power";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x5>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- };
-
- led@6 {
- chan-name = "red:wlan-5";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x6>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <5>;
- };
-
- led@7 {
- chan-name = "red:wan-4";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x7>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_WAN; /* WWAN/LTE/4G */
- function-enumerator = <4>; /* WWAN/LTE/4G */
- };
-
- led_cloud_red: led@8 {
- chan-name = "red:power";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x8>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_POWER;
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>, <&uart0_ctrl_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
-};
-
-&prng {
- status = "okay";
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- vqmmc-supply = <&vqmmc>;
- non-removable;
- #address-cells = <1>;
- #size-cells = <0>;
-
- emmc@0 {
- compatible = "mmc-card";
- reg = <0>;
- };
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-
- pinctrl-0 = <&usb3_pins>, <<e_pins>;
- pinctrl-names = "default";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- device@1 {
- compatible = "usb1bc7,1900";
- reg = <1>;
- };
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
- label = "wan";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Sony-NCP-HG100-Cellular";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Sony-NCP-HG100-Cellular";
-};
-
-&watchdog {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EdgeCore OAP-100";
- compatible = "edgecore,oap100";
-
- aliases {
- led-boot = &led_system;
- led-failsafe = &led_system;
- led-running = &led_system;
- led-upgrade = &led_system;
- };
-
- chosen {
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- soc {
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- key {
- compatible = "gpio-keys";
-
- button@1 {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_system: led_system {
- label = "green:system";
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- };
-
- led_2g {
- label = "blue:wlan2g";
- gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
- };
-
- led_5g {
- label = "blue:wlan5g";
- gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- usb {
- gpio-export,name = "usb-power";
- gpio-export,output = <1>;
- gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
- };
-
- poe {
- gpio-export,name = "poe-power";
- gpio-export,output = <0>;
- gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- linux,modalias = "m25p80", "gd25q256";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition6@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition7@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs";
- reg = <0x00000000 0x4000000>;
- };
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "Edgecore OAP100";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "Edgecore OAP100";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- aliases {
- led-boot = &led_status_white;
- led-failsafe = &led_status_red;
- led-running = &led_status_green;
- led-upgrade = &led_status_blue;
- label-mac-device = &gmac;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- led-1 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_status_green: led-2 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_red: led-3 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_blue: led-4 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_white: led-5 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
-
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vqmmc>;
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- pinmux {
- function = "blsp_i2c0";
- pins = "gpio58", "gpio59";
- bias-disable;
- };
- };
-
- sd_pins: sd_pins {
- pinmux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio28", "gpio29", "gpio30", "gpio31";
- drive-strength = <10>;
- };
-
- pinmux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
-
- pinmux_sd7 {
- function = "sdio";
- pins = "gpio32";
- drive-strength = <10>;
- bias-disable;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_i2c3 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- led-controller@27 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,tlc59108"; /* really is tlc59208f */
- reg = <0x27>;
-
- led0@0 {
- label = "rgb:led0";
- reg = <0x0>;
- linux,default-trigger = "default-on";
- };
-
- led1@1 {
- label = "rgb:led1";
- reg = <0x1>;
- linux,default-trigger = "default-on";
- };
-
- led2@2 {
- label = "rgb:led2";
- reg = <0x2>;
- linux,default-trigger = "default-on";
- };
-
- led3@3 {
- label = "rgb:led3";
- reg = <0x3>;
- linux,default-trigger = "default-on";
- };
-
- led4@4 {
- label = "rgb:led4";
- reg = <0x4>;
- linux,default-trigger = "default-on";
- };
-
- led5@5 {
- label = "rgb:led5";
- reg = <0x5>;
- linux,default-trigger = "default-on";
- };
-
- led6@6 {
- label = "rgb:led6";
- reg = <0x6>;
- linux,default-trigger = "default-on";
- };
-
- led7@7 {
- label = "rgb:led7";
- reg = <0x7>;
- linux,default-trigger = "default-on";
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-
- label = "wan";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan3";
-};
-
-ðphy4 {
- status = "disabled";
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- ieee80211-freq-limit = <5470000 5875000>;
- qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
- };
- };
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>
- * Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Plasma Cloud PA2200";
- compatible = "plasmacloud,pa2200";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART >;
- };
- };
-
- aliases {
- led-boot = &led_power_orange;
- led-failsafe = &led_status_blue;
- led-running = &led_power_orange;
- led-upgrade = &led_status_blue;
- label-mac-device = &swport4;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power_orange: power_orange {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
- };
-
- 2g_blue {
- label = "blue:2g";
- gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- 2g_green {
- label = "green:5g1";
- gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- 5g2_green {
- label = "green:5g2";
- gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy2tpt";
- };
-
- led_status_blue: status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- /* partitions are passed via bootloader */
- partitions {
- partition-art {
- label = "0:ART";
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
- ieee80211-freq-limit = <5170000 5350000>;
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_9000>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "ethernet1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
- status = "okay";
- label = "ethernet2";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
- ieee80211-freq-limit = <5470000 5875000>;
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-r619ac.dtsi"
-
-/ {
- model = "P&W R619AC 128M";
- compatible = "p2w,r619ac-128m";
-};
-
-&nand_rootfs {
- /*
- * Watch out: stock MIBIB is set up for a 64MiB chip.
- * If a 128MiB flash chip is used, make sure to have
- * the right values in MIBIB or the device might not
- * boot.
- */
- reg = <0x0 0x8000000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-r619ac.dtsi"
-
-/ {
- model = "P&W R619AC 64M";
- compatible = "p2w,r619ac-64m";
-};
-
-&nand_rootfs {
- reg = <0x0 0x4000000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- chosen {
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- aliases {
- led-boot = &led_sys;
- led-failsafe = &led_sys;
- led-running = &led_sys;
- led-upgrade = &led_sys;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_sys: led-0 {
- gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- };
-
- led-1 {
- gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <0>;
- };
-
- led-2 {
- gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <1>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- nand_rootfs: partition@0 {
- label = "ubi";
- /* reg defined in 64M/128M variant dts. */
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pins>;
- perst-gpio = <&tlmm 4 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 40 GPIO_ACTIVE_HIGH>;
-
- /* Free slot for use */
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&sdhci {
- pinctrl-0 = <&sd_0_pins>;
- pinctrl-names = "default";
- vqmmc-supply = <&vqmmc>;
- status = "okay";
-};
-
-&tlmm {
- pcie_pins: pcie_pinmux {
- mux {
- pins = "gpio2";
- function = "gpio";
- output-low;
- bias-pull-down;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- sd_0_pins: sd_0_pinmux {
- mux_1 {
- pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio28";
- function = "sdio";
- drive-strength = <10>;
- };
-
- mux_2 {
- pins = "gpio27";
- function = "sdio";
- drive-strength = <16>;
- };
- };
-
- serial_0_pins: serial0-pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-};
-
-ðphy0 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy1 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy2 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy3 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy4 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "P&W-R619AC";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "P&W-R619AC";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR RBR40";
- compatible = "netgear,rbr40";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR RBR50";
- compatible = "netgear,rbr50";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-
- soc {
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR RBS40";
- compatible = "netgear,rbs40";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR RBS50";
- compatible = "netgear,rbs50";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-
- soc {
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "ASUS RT-AC42U";
- compatible = "asus,rt-ac42u";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256MB */
- };
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: led-0 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
- };
-
- led-1 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WAN;
- gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "90000.mdio-1:04:link";
- };
-
- led-2 {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_WAN;
- gpios = <&tlmm 68 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
- };
-
- led-3 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <0>;
- gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- led-4 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <1>;
- gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- led-5 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
- };
-
- led-6 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
- };
-
- led-7 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
- };
-
- led-8 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <4>;
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- serial_0_pins: serial0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio55", "gpio56", "gpio57", "gpio60",
- "gpio62", "gpio63", "gpio64", "gpio65",
- "gpio66", "gpio67", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00080000>;
- read-only;
- };
- partition@80000 {
- label = "MIBIB";
- reg = <0x00080000 0x00080000>;
- read-only;
- };
- partition@100000 {
- label = "QSEE";
- reg = <0x00100000 0x00100000>;
- read-only;
- };
- partition@200000 {
- label = "CDT";
- reg = <0x00200000 0x00080000>;
- read-only;
- };
- partition@280000 {
- label = "APPSBL";
- reg = <0x00280000 0x00140000>;
- read-only;
- };
- partition@3C0000 {
- label = "APPSBLENV";
- reg = <0x003C0000 0x00040000>;
- read-only;
- };
- partition@400000 {
- label = "ubi";
- reg = <0x00400000 0x07C00000>;
- };
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ASUS-RT-AC42U";
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
- clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
-
- qcom,ath10k-calibration-variant = "ASUS-RT-AC42U";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: ISC
-// Copyright (c) 2015, The Linux Foundation. All rights reserved.
-// Copyright (c) 2019, Cezary Jackiewicz <cezary@eko.one.pl>.
-// Copyright (c) 2020, Pawel Dembicki <paweldembicki@gmail.com>.
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Cell C RTL30VW";
- compatible = "cellc,rtl30vw";
-
- aliases {
- led-boot = &led_power_blue;
- led-failsafe = &led_power_red;
- led-running = &led_power_blue;
- led-upgrade = &led_power_red;
- };
-
- chosen {
- bootargs-append = "ubi.mtd=ubifs root=/dev/ubiblock0_0 rootfstype=squashfs ro";
- };
-
- led_spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- num-chipselects = <1>;
-
- mosi-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- cs-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- sck-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
-
- led_gpio: led_gpio@0 {
- compatible = "fairchild,74hc595";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <2>;
- registers-number = <2>;
- spi-max-frequency = <1000000>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power_blue: power_blue {
- gpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- default-state = "on";
- };
-
- led_power_red: power_red {
- gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- };
-
- tp28 {
- gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
- label = "ext:tp28";
- default-state = "keep";
- };
-
- tp27 {
- gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
- label = "ext:tp27";
- default-state = "keep";
- };
-
- wlan2g {
- gpios = <&led_gpio 8 GPIO_ACTIVE_HIGH>;
- label = "blue:wlan2g";
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- gpios = <&led_gpio 9 GPIO_ACTIVE_HIGH>;
- label = "blue:wlan5g";
- linux,default-trigger = "phy1tpt";
- };
-
- wps {
- gpios = <&led_gpio 10 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_BLUE>;
- };
-
- voip {
- gpios = <&led_gpio 11 GPIO_ACTIVE_HIGH>;
- label = "blue:voip";
- };
-
- s1 {
- gpios = <&led_gpio 12 GPIO_ACTIVE_HIGH>;
- label = "blue:s1";
- };
-
- s2 {
- gpios = <&led_gpio 13 GPIO_ACTIVE_HIGH>;
- label = "blue:s2";
- };
-
- s3 {
- gpios = <&led_gpio 14 GPIO_ACTIVE_HIGH>;
- label = "blue:s3";
- };
-
- s4 {
- gpios = <&led_gpio 15 GPIO_ACTIVE_HIGH>;
- label = "blue:s4";
- };
-
- signal {
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- label = "red:signal";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- };
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- /*"n25q128a11" is required for proper nand recognition in u-boot. */
- compatible = "jedec,spi-nor", "n25q128a11";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
- };
-
- partition@180000 {
- label = "0:BOOTCONFIG";
- reg = <0x180000 0x10000>;
- read-only;
- };
- };
- };
-
- flash@1 {
- /*
- * Factory U-boot looks in 0:BOOTCONFIG partition for active
- * partitions settings and mangle partition config. So kernel
- * /kernel_1 and rootfs/rootfs_1 pairs can be swaped.
- * It isn't a problem but we never can be sure where OFW put
- * factory images. "spinand,mt29f" value is required for proper
- * nand recognition in u-boot.
- */
- compatible = "spi-nand","spinand,mt29f";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "kernel";
- reg = <0x0 0x400000>;
- };
-
- partition@400000 {
- label = "rootfs";
- reg = <0x400000 0x2000000>;
- };
-
- partition@2400000 {
- label = "kernel_1";
- reg = <0x2400000 0x400000>;
- };
-
- partition@2800000 {
- label = "rootfs_1";
- reg = <0x2800000 0x2000000>;
- };
-
- partition@4800000 {
- label = "ubifs";
- reg = <0x4800000 0x3800000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "cellc,rtl30vw";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "cellc,rtl30vw";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR SRR60";
- compatible = "netgear,srr60";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_1)ro,256K(0:CDT)ro,256K(0:CDT_1)ro,512K(0:BOOTCONFIG1)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_1)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,64K(cert)ro,3840K(kernel-2)ro,31488K(rootfs-2)ro,35328K@44881K(firmware-2)ro,5M(device_table)ro,17M(cp_file)ro,102737K(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR SRS60";
- compatible = "netgear,srs60";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_1)ro,256K(0:CDT)ro,256K(0:CDT_1)ro,512K(0:BOOTCONFIG1)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_1)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,64K(cert)ro,3840K(kernel-2)ro,31488K(rootfs-2)ro,35328K@44881K(firmware-2)ro,5M(device_table)ro,17M(cp_file)ro,102737K(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-u4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Unielec U4019 (32M)";
- compatible = "unielec,u4019-32m","unielec,u4019","qcom,ipq4019";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- broken-flash-reset;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
- };
- };
- };
-};
-
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- compatible = "unielec,u4019","qcom,ipq4019";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- serial0 = &blsp1_uart1;
- serial1 = &blsp1_uart2;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_status: led2 {
- label = "green:led2";
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_0_pins: serial0-pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- led_pins: led_pinmux {
- mux {
- function = "gpio";
- pins = "gpio68";
- bias-disabled;
- output-low;
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Linksys WHW03 V2 (Velop)";
- compatible = "linksys,whw03v2", "qcom,ipq4019";
-
- aliases {
- led-boot = &led_blue;
- led-failsafe = &led_red;
- led-running = &led_green;
- led-upgrade = &led_red;
- };
-
- // The arguments rootfstype and ro are needed
- // to override the default bootargs
- chosen {
- bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
- stdout-path = &blsp1_uart1;
- };
-
- soc {
- ess-tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-
-&tlmm {
- mdio_pins: mdio-pinmux {
- mux-1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux-2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- i2c_0_pins: i2c-0-pinmux {
- mux {
- function = "blsp_i2c0";
- pins = "gpio20", "gpio21";
- bias-disable;
- };
- };
-
- serial_0_pins: serial0-pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1-pinmux {
- mux {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi-0-pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux-cs {
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- spi_1_pins: spi-1-pinmux {
- mux-1 {
- function = "blsp_spi1";
- pins = "gpio44", "gpio46","gpio47";
- bias-disable;
- };
-
- mux-2 {
- pins = "gpio31", "gpio45", "gpio49";
- function = "gpio";
- bias-pull-up;
- output-high;
- };
-
- host-interrupt {
- pins = "gpio42";
- function = "gpio";
- input;
- };
- };
-
- wifi_0_pins: wifi0-pinmux {
- btcoexist {
- bias-pull-up;
- drive-strength = <6>;
- function = "gpio";
- output-high;
- pins = "gpio52";
- };
- };
-
- zigbee-0 {
- gpio-hog;
- gpios = <29 GPIO_ACTIVE_HIGH>;
- bias-disable;
- output-low;
- };
-
- zigbee-1 {
- gpio-hog;
- gpios = <50 GPIO_ACTIVE_HIGH>;
- bias-disable;
- input;
- };
-
- bluetooth-enable {
- gpio-hog;
- gpios = <32 GPIO_ACTIVE_HIGH>;
- output-high;
- };
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy-reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-ðphy2 {
- status = "disabled";
-};
-
-ðphy3 {
- reg = <0x1b>;
-};
-
-ðphy4 {
- reg = <0x1c>;
-};
-
-&psgmiiphy {
- reg = <0x1d>;
-};
-
-&watchdog {
- status = "okay";
-};
-
-&prng {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- num-channels = <4>;
- qcom,num-ees = <2>;
-
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&blsp1_uart1 {
- status = "okay";
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
-};
-
-&blsp1_uart2 {
- status = "okay";
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
-
- bluetooth {
- compatible = "csr,8811";
-
- enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&blsp1_spi2 {
- pinctrl-0 = <&spi_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- cs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-
- zigbee@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "silabs,em3581";
- reg = <0>;
- spi-max-frequency = <12000000>;
- };
-};
-
-&blsp1_i2c3 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- // RGB LEDs
- pca9633: led-controller@62 {
- compatible = "nxp,pca9633";
- nxp,hw-blink;
- reg = <0x62>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led_red: red@0 {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_INDICATOR;
- linux,default-trigger = "none";
- reg = <0>;
- };
-
- led_green: green@1 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- linux,default-trigger = "none";
- reg = <1>;
- };
-
- led_blue: blue@2 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_INDICATOR;
- linux,default-trigger = "default-on";
- reg = <2>;
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "MIBIB";
- reg = <0x100000 0x100000>;
- read-only;
- };
-
- partition@200000 {
- label = "QSEE";
- reg = <0x200000 0x100000>;
- read-only;
- };
-
- partition@300000 {
- label = "CDT";
- reg = <0x300000 0x80000>;
- read-only;
- };
-
- partition@380000 {
- label = "APPSBL";
- reg = <0x380000 0x200000>;
- read-only;
- };
-
- partition@580000 {
- label = "ART";
- reg = <0x580000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
-
- partition@600000 {
- label = "u_env";
- reg = <0x600000 0x80000>;
- };
-
- partition@680000 {
- label = "s_env";
- reg = <0x680000 0x40000>;
- };
-
- partition@6c0000 {
- label = "devinfo";
- reg = <0x6c0000 0x40000>;
- read-only;
- };
-
- partition@700000 {
- label = "kernel";
- reg = <0x700000 0xa100000>;
- };
-
- partition@d00000 {
- label = "rootfs";
- reg = <0xd00000 0x9b00000>;
- };
-
- partition@a800000 {
- label = "alt_kernel";
- reg = <0xa800000 0xa100000>;
- };
-
- partition@ae00000 {
- label = "alt_rootfs";
- reg = <0xae00000 0x9b00000>;
- };
-
- partition@14900000 {
- label = "sysdiag";
- reg = <0x14900000 0x200000>;
- read-only;
- };
-
- partition@14b00000 {
- label = "syscfg";
- reg = <0x14b00000 0xb500000>;
- read-only;
- };
- };
- };
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
- clkreq-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&swport5 {
- status = "okay";
- label = "wan";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0 0>;
-};
-
-&wifi0 {
- pinctrl-0 = <&wifi_0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- qcom,coexist-support = <1>;
- qcom,coexist-gpio-pin = <0x34>;
-
- ieee80211-freq-limit = <2401000 2473000>;
- qcom,ath10k-calibration-variant = "linksys-whw03v2";
-
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_gmac0 1>;
-};
-
-&wifi1 {
- status = "okay";
-
- ieee80211-freq-limit = <5170000 5250000>;
- qcom,ath10k-calibration-variant = "linksys-whw03v2";
-
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_gmac0 2>;
-};
-
-&wifi2 {
- status = "okay";
-
- ieee80211-freq-limit = <5735000 5835000>;
- qcom,ath10k-calibration-variant = "linksys-whw03v2";
-
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_9000>, <&macaddr_gmac0 3>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2016, 2018 The Linux Foundation. All rights reserved.
- * Copyright (c) 2016 Google, Inc
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Google WiFi (Gale)";
- compatible = "google,wifi", "google,gale-v2", "qcom,ipq4019";
-
- aliases {
- label-mac-device = &gmac0;
- led-boot = &led0_blue;
- led-failsafe = &led0_red;
- led-running = &led0_blue;
- led-upgrade = &led0_red;
- };
-
- chosen {
- /*
- * rootwait: in case we're booting from slow/async USB storage.
- */
- bootargs-append = " rootwait";
- stdout-path = &blsp1_uart1;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>; /* 512MB */
- };
-
- soc {
- edma@c080000 {
- /*
- * Factory bootloader (depthcharge) will fail to boot
- * if this exact path (soc/edma@c080000/gmac0) doesn't
- * exist.
- */
- gmac0: gmac0 {
- };
-
- /*
- * Factory bootloader (depthcharge) will fail to boot
- * if this exact path (soc/edma@c080000/gmac1) doesn't
- * exist.
- */
- gmac1 {
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&fw_pinmux>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&scm {
- qcom,sdi-enabled;
-};
-
-&tlmm {
- fw_pinmux: fw_pinmux {
- wp {
- pins = "gpio53";
- output-low;
- };
- recovery {
- pins = "gpio57";
- function = "gpio";
- bias-none;
- };
- developer {
- pins = "gpio41";
- bias-none;
- };
- };
-
- reset802_15_4 {
- pins = "gpio60";
- };
-
- led_reset {
- pins = "gpio22";
- output-high;
- };
-
- sys_reset {
- pins = "gpio19";
- output-high;
- };
-
- rx_active {
- pins = "gpio43";
- bias-pull,down;
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14","gpio15";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- };
- pinconf {
- pins = "gpio13", "gpio14","gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- spi_1_pins: spi_1_pinmux {
- pinmux {
- function = "blsp_spi1";
- pins = "gpio44", "gpio46","gpio47";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio45";
- };
- pinconf {
- pins = "gpio44", "gpio46","gpio47";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio45";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- serial_0_pins: serial0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- drive-open-drain;
- };
- };
-
- i2c_1_pins: i2c_1_pinmux {
- mux {
- pins = "gpio34", "gpio35";
- function = "blsp_i2c1";
- drive-open-drain;
- };
- };
-
- sd_0_pins: sd_0_pinmux {
- sd0 {
- pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32";
- function = "sdio";
- drive-strength = <10>;
- bias-pull-up;
- pull-up-res = <0>;
- };
- sdclk {
- pins = "gpio27";
- function = "sdio";
- drive-strength = <2>;
- bias-pull-up;
- pull-up-res = <0>;
- };
- sdcmd {
- pins = "gpio28";
- function = "sdio";
- drive-strength = <10>;
- bias-pull-up;
- pull-up-res = <0>;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-disable;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-disable;
- };
- mux_3 {
- pins = "gpio40";
- function = "gpio";
- bias-disable;
- output-high;
- };
- };
-
- wifi1_1_pins: wifi2_pinmux {
- mux {
- pins = "gpio58";
- output-low;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_i2c3 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- tpm@20 {
- compatible = "infineon,slb9645tt";
- reg = <0x20>;
- powered-while-suspended;
- };
-};
-
-&blsp1_i2c4 {
- pinctrl-0 = <&i2c_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- led-controller@32 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "national,lp5523";
- reg = <0x32>;
- clock-mode = /bits/ 8 <1>;
-
-#if 1
- led0_red: led@0 {
- reg = <0>;
- chan-name = "LED0_Red";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_FAULT;
- };
-
- led@1 {
- reg = <1>;
- chan-name = "LED0_Green";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_GREEN>;
- };
-
- led0_blue: led@2 {
- reg = <2>;
- chan-name = "LED0_Blue";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- };
-#else
- /*
- * openwrt isn't ready to handle multi-intensity leds yet
- * # echo 255 255 255 > /sys/class/leds/tricolor/multi_intensity
- * # echo 255 > /sys/class/leds/tricolor/brightness
- */
- multi-led@2 {
- function = LED_FUNCTION_POWER;
- reg = <2>;
- color = <LED_COLOR_ID_RGB>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- chan-name = "tricolor";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_RED>;
- };
-
- led@1 {
- reg = <1>;
- chan-name = "tricolor";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_GREEN>;
- };
-
- led@2 {
- reg = <2>;
- chan-name = "tricolor";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_BLUE>;
- };
- };
-#endif
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- };
-};
-
-&blsp1_spi2 {
- pinctrl-0 = <&spi_1_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-
- /*
- * This "spidev" was included in the manufacturer device tree. I
- * suspect it's the (unused; and removed from later HW spins) Zigbee
- * radio -- SiliconLabs EM3581 Zigbee? There's no driver or binding for
- * this at the moment.
- */
- spidev@0 {
- compatible = "spidev";
- reg = <0>;
- spi-max-frequency = <24000000>;
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-};
-
-&prng {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
- pinctrl-0 = <&sd_0_pins>;
- pinctrl-names = "default";
- clock-frequency = <192000000>;
- vqmmc-supply = <&vqmmc>;
- non-removable;
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "GO_GALE";
-};
-
-&wifi1 {
- status = "okay";
- pinctrl-0 = <&wifi1_1_pins>;
- pinctrl-names = "default";
- qcom,ath10k-calibration-variant = "GO_GALE";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2019, Nguyen Dinh Phi <phi_nguyen@compex.com.sg>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Compex WPJ419";
- compatible = "compex,wpj419", "qcom,ipq4019";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- reserved-memory {
- ranges;
- rsvd1@87000000 {
- /* Reserved for other subsystem */
- reg = <0x87000000 0x500000>;
- no-map;
- };
- wifi_dump@87500000 {
- reg = <0x87500000 0x600000>;
- no-map;
- };
-
- rsvd2@87B00000 {
- /* Reserved for other subsystem */
- reg = <0x87B00000 0x500000>;
- no-map;
- };
- };
-
- chosen {
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- soc {
- pinctrl@1000000 {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- bias-disable;
- output-high;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- led_0_pins: led0_pinmux {
- mux_1 {
- pins = "gpio36";
- function = "led0";
- bias-pull-down;
- };
- mux_2 {
- pins = "gpio40";
- function = "led4";
- bias-pull-down;
- };
- };
- };
-
- blsp_dma: dma@7884000 {
- status = "okay";
- };
-
- spi_0: spi@78b5000 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;
- num-cs = <2>;
-
- flash0@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- broken-flash-reset;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x000000 0x040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x040000 0x020000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x060000 0x060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0x0c0000 0x010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x0d0000 0x010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "u-boot-env";
- reg = <0x0e0000 0x010000>;
- };
-
- partition@f0000 {
- label = "u-boot";
- reg = <0x0f0000 0x080000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- nand@1 {
- reg = <1>;
- status = "okay";
- compatible = "spi-nand";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* The device has 128MB, but we can only address
- * 64MB because of the bootloader's default settings.
- * This is due to the old mt29f driver,
- * which detected the deivce with only 64MB
- */
- partition@0 {
- label = "ubi";
- reg = <0x0000000 0x4000000>;
- };
- };
- };
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <5000>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- i2c_0: i2c@78b7000 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- serial@78af000 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- serial@78b0000 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- usb3_ss_phy: ssphy@9a000 {
- status = "okay";
- };
-
- usb3_hs_phy: hsphy@a6000 {
- status = "okay";
- };
-
- usb3: usb3@8af8800 {
- status = "okay";
- };
-
- usb2_hs_phy: hsphy@a8000 {
- status = "okay";
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- cryptobam: dma@8e04000 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- qpic_bam: dma@7984000 {
- status = "okay";
- };
-
- pcie0: pci@40000000 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: ISC
-/*
- * Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
- * Copyright (c) 2020 Yanase Yuki <dev@zpc.sakura.ne.jp>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Buffalo WTR-M2133HP";
- compatible = "buffalo,wtr-m2133hp", "qcom,ipq4019";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-
- chosen {
- /*
- * U-Boot adds "ubi.mtd=rootfs root=mtd:ubi_rootfs" to
- * kernel command line. But we use different partition names,
- * so we have to set correct parameters.
- */
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- aliases {
- led-boot = &led_power_blue;
- led-failsafe = &led_power_orange;
- led-running = &led_power_white;
- led-upgrade = &led_power_blue;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power_white: power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
- };
-
- led_power_orange: power_orange {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
- };
-
- led_power_blue: power_blue {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
- };
-
- router_white {
- label = "white:router";
- gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
- };
-
- router_orange {
- label = "orange:router";
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- };
-
- internet_white {
- label = "white:internet";
- gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
- };
-
- internet_orange {
- label = "orange:internet";
- gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
- };
-
- wireless_white {
- label = "white:wireless";
- gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
- };
-
- wireless_orange {
- label = "orange:wireless";
- gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- auto_mode {
- label = "auto_mode";
- gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- linux,input-type = <EV_SW>;
- };
-
- router_mode {
- label = "router_mode";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- };
-
- ap_mode {
- label = "ap_mode";
- gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_2>;
- linux,input-type = <EV_SW>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "AOSS Button";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-};
-
-&tlmm {
- serial_0_pins: serial0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- usb_power {
- line-name = "USB power";
- gpios = <34 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@0,0 {
- compatible = "qcom,ath10k";
- reg = <0 0 0 0 0>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_9000>, <&macaddr_orgdata_32>;
- qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0000000 0x0100000>;
- read-only;
- };
-
- partition@100000 {
- label = "MIBIB";
- reg = <0x0100000 0x0100000>;
- read-only;
- };
-
- partition@200000 {
- label = "BOOTCONFIG";
- reg = <0x0200000 0x0100000>;
- read-only;
- };
-
- partition@300000 {
- label = "QSEE";
- reg = <0x0300000 0x0100000>;
- read-only;
- };
-
- partition@400000 {
- label = "QSEE_1";
- reg = <0x0400000 0x0100000>;
- read-only;
- };
-
- partition@500000 {
- label = "CDT";
- reg = <0x0500000 0x0080000>;
- read-only;
- };
-
- partition@580000 {
- label = "CDT_1";
- reg = <0x0580000 0x0080000>;
- read-only;
- };
-
- partition@600000 {
- label = "BOOTCONFIG1";
- reg = <0x0600000 0x0080000>;
- read-only;
- };
-
- partition@680000 {
- label = "APPSBLENV";
- reg = <0x0680000 0x0080000>;
- };
-
- partition@700000 {
- label = "APPSBL";
- reg = <0x0700000 0x0200000>;
- read-only;
- };
-
- partition@900000 {
- label = "APPSBL_1";
- reg = <0x0900000 0x0200000>;
- read-only;
- };
-
- partition@b00000 {
- label = "ART";
- reg = <0x0b00000 0x0080000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@b80000 {
- label = "ART_1";
- reg = <0x0b80000 0x0080000>;
- read-only;
- };
-
- orgdata: partition@c00000 {
- label = "ORGDATA";
- reg = <0x0c00000 0x0080000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_orgdata_20: macaddr@20 {
- reg = <0x20 0x6>;
- };
- macaddr_orgdata_26: macaddr@26 {
- reg = <0x26 0x6>;
- };
- macaddr_orgdata_2c: macaddr@2c {
- reg = <0x2c 0x6>;
- };
- macaddr_orgdata_32: macaddr@32 {
- reg = <0x32 0x6>;
- };
- };
- };
-
- partition@c80000 {
- label = "ORGDATA_1";
- reg = <0x0c80000 0x0080000>;
- read-only;
- };
-
- partition@d00000 {
- label = "ubi";
- reg = <0x0d00000 0x2900000>;
- };
-
- partition@3600000 {
- label = "rootfs_recover";
- reg = <0x3600000 0x2900000>;
- read-only;
- };
-
- partition@5f00000 {
- label = "user_property";
- reg = <0x5f00000 0x1a20000>;
- read-only;
- };
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_orgdata_26>;
- qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
- ieee80211-freq-limit = <2400000 2483000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_orgdata_2c>;
- qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_orgdata_20>;
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-
-#include "qcom-ipq4019-x1pro.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Telco X1 Pro";
- compatible = "tel,x1pro","qcom,ipq4019";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- broken-flash-reset;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
- art: partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- compatible = "tel,x1pro","qcom,ipq4019";
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- serial0 = &blsp1_uart1;
- serial1 = &blsp1_uart2;
- };
-
- soc {
-
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_status: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_0_pins: serial0-pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- led_pins: led_pinmux {
- mux {
- function = "gpio";
- pins = "gpio68";
- bias-disabled;
- output-low;
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/*
- * Device Tree Source for Linksys xx8300 (Dallas)
- *
- * Copyright (C) 2019, 2022 Jeff Kletsky
- * Updated 2020 Hans Geiblinger
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
- //
- // OEM U-Boot provides either
- // init=/sbin/init rootfstype=ubifs ubi.mtd=11,2048 \
- // root=ubi0:ubifs rootwait rw
- // or the same with ubi.mtd=13,2048
- //
-
-/ {
- chosen {
- bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
- };
-
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- regulator-usb-vbus {
- compatible = "regulator-fixed";
- regulator-name = "USB_VBUS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
-};
-
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- status = "okay";
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
-
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "sbl1";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "mibib";
- reg = <0x100000 0x100000>;
- read-only;
- };
-
- partition@200000 {
- label = "qsee";
- reg = <0x200000 0x100000>;
- read-only;
- };
-
- partition@300000 {
- label = "cdt";
- reg = <0x300000 0x80000>;
- read-only;
- };
-
- partition@380000 {
- label = "appsblenv";
- reg = <0x380000 0x80000>;
- read-only;
- };
-
- partition@400000 {
- label = "ART";
- reg = <0x400000 0x80000>;
- read-only;
- };
-
- partition@480000 {
- label = "appsbl";
- reg = <0x480000 0x200000>;
- read-only;
- };
-
- partition@680000 {
- label = "u_env";
- reg = <0x680000 0x80000>;
- // writable -- U-Boot environment
- };
-
- partition@700000 {
- label = "s_env";
- reg = <0x700000 0x40000>;
- // writable -- Boot counter records
- };
-
- partition@740000 {
- label = "devinfo";
- reg = <0x740000 0x40000>;
- read-only;
- };
-
- partition@780000 {
- label = "kernel";
- reg = <0x780000 0x5800000>;
- };
-
- partition@c80000 {
- label = "rootfs";
- reg = <0xc80000 0x5300000>;
- };
-
- partition@5f80000 {
- label = "alt_kernel";
- reg = <0x5f80000 0x5800000>;
- };
-
- partition@6480000 {
- label = "alt_rootfs";
- reg = <0x6480000 0x5300000>;
- };
-
- partition@b780000 {
- label = "sysdiag";
- reg = <0xb780000 0x100000>;
- read-only;
- };
-
- partition@b880000 {
- label = "syscfg";
- reg = <0xb880000 0x4680000>;
- read-only;
- };
- };
- };
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- serial_0_pins: serial0-pinmux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- // gpio61 controls led_usb
-
- pulldowns {
- pins = "gpio55", "gpio56", "gpio57",
- "gpio60", "gpio62", "gpio63",
- "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2017, Christian Mehlis <christian@m3hlis.de>
- * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Compex WPJ428";
- compatible = "compex,wpj428";
-
- chosen {
- /*
- * There's a chance that SPI reads fail even though the data itself is alright.
- * The read result is cached and squashfs can't recover.
- * Just panic when that happens and hope that next time it doesn't.
- */
- bootargs-append = " rootflags=errors=panic";
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- usb3: usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- aliases {
- led-boot = &status;
- led-failsafe = &status;
- led-upgrade = &status;
- };
-
- leds {
- compatible = "gpio-leds";
-
- status: rss4 {
- label = "green:rss4";
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- };
-
- rss3 {
- label = "green:rss3";
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
- };
-
- beeper: beeper {
- compatible = "gpio-beeper";
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "0:APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition5@f0000 {
- label = "0:APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition5@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_e010: mac-address@e010 {
- reg = <0xe010 0x6>;
- };
-
- macaddr_art_e018: mac-address@e018 {
- reg = <0xe018 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition6@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x00180000 0x01e80000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-
- nvmem-cells = <&macaddr_art_e018>;
- nvmem-cell-names = "mac-address";
-};
-
-&swport5 {
- status = "okay";
- label = "lan2";
-
- nvmem-cells = <&macaddr_art_e010>;
- nvmem-cell-names = "mac-address";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4029-aruba-glenmorangie.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Aruba AP-303";
- compatible = "aruba,ap-303";
-
- aliases {
- led-boot = &led_system_green;
- led-failsafe = &led_system_red;
- led-running = &led_system_green;
- led-upgrade = &led_system_red;
- };
-
- leds {
- compatible = "gpio-leds";
-
- wifi_green {
- label = "green:wifi";
- gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wifi_amber {
- label = "amber:wifi";
- gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- led_system_red: system_red {
- label = "red:system";
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- };
-
- led_system_green: system_green {
- label = "green:system";
- gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- /*
- * In addition to the Pins listed below,
- * the following GPIOs have "features":
- * 54 - out - active low to force HW reset
- * 41 - out - active low to reset TPM
- * 43 - out - active low to reset BLE radio
- * 19 - in - active high when DC powered
- */
-
- phy-reset {
- line-name = "PHY-reset";
- gpios = <42 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /*
- * There is no partition map for the NOR flash
- * in the stock firmware.
- *
- * All partitions here are based on offsets
- * found in the U-Boot GPL code and information
- * from smem.
- */
-
- partition@0 {
- label = "sbl1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "mibib";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "qsee";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "cdt";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "ddrparams";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "ART";
- reg = <0xe0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@f0000 {
- label = "appsbl";
- reg = <0xf0000 0xf0000>;
- read-only;
- };
-
- partition@1e0000 {
- label = "mfginfo";
- reg = <0x1e0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mfginfo_1d: macaddr@1d {
- compatible = "mac-base";
- reg = <0x1d 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1f0000 {
- label = "apcd";
- reg = <0x1f0000 0x10000>;
- read-only;
- };
-
- partition@200000 {
- label = "osss";
- reg = <0x200000 0x180000>;
- read-only;
- };
-
- partition@380000 {
- label = "appsblenv";
- reg = <0x380000 0x10000>;
- };
-
- partition@390000 {
- label = "pds";
- reg = <0x390000 0x10000>;
- read-only;
- };
-
- partition@3a0000 {
- label = "fcache";
- reg = <0x3a0000 0x10000>;
- read-only;
- };
-
- partition@3b0000 {
- /* Called osss1 in smem */
- label = "u-boot-env-bak";
- reg = <0x3b0000 0x10000>;
- read-only;
- };
-
- partition@3f0000 {
- label = "u-boot-env";
- reg = <0x3f0000 0x10000>;
- read-only;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Aruba AP-303H";
- compatible = "aruba,ap-303h";
-
- aliases {
- led-boot = &led_system_green;
- led-failsafe = &led_system_red;
- led-running = &led_system_green;
- led-upgrade = &led_system_amber;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- i2c_0: i2c@78b7000 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- tpm@29 {
- /* No Driver */
- compatible = "atmel,at97sc3203";
- reg = <0x29>;
- read-only;
- };
-
- power-monitor@40 {
- /* No driver */
- compatible = "isl,isl28022";
- reg = <0x40>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- wifi_green {
- label = "green:wifi";
- gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wifi_amber {
- label = "amber:wifi";
- gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- pse {
- label = "green:pse";
- gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
- };
-
- led_system_red: system_red {
- label = "red:system";
- gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
- };
-
- led_system_green: system_green {
- label = "green:system";
- gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
- };
-
- led_system_amber: system_amber {
- label = "amber:system";
- gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "Reset button";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- /* Texas Instruments CC2540T BLE radio */
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- /*
- * In addition to the Pins listed below,
- * the following GPIOs have "features":
- * 39 - out - active low to force HW reset
- * 32 - out - active low to reset TPM
- * 43 - out - active low to reset BLE radio
- * 41 - out - pulse to set warm reset status
- * 34 - out - active low to enable PSE port
- * 22 - in - active low when 802.3at powered
- * 29 - in - active high when DC powered
- * 40 - in - active low when reset due to cold HW reset
- * 30 - in - active low when USB overcurrent detected
- * 35 - in - interrupt line for power monitor chip
- * 31 - in - active low when PSE port active
- */
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- drive-strength = <4>;
- bias-disable;
- };
- };
-
- serial_0_pins: serial_0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial_1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- usb-power {
- line-name = "USB-power";
- gpios = <23 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /*
- * There is no partition map for the NOR flash
- * in the stock firmware.
- *
- * All partitions here are based on offsets
- * found in the U-Boot GPL code and information
- * from smem.
- */
-
- partition@0 {
- label = "sbl1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "mibib";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "qsee";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "cdt";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "ddrparams";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "appsblenv";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "appsbl";
- reg = <0xf0000 0x100000>;
- read-only;
- };
-
- partition@1e0000 {
- label = "ART";
- reg = <0x1f0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@1f0000 {
- label = "osss";
- reg = <0x200000 0x170000>;
- read-only;
- };
-
- partition@200000 {
- label = "pds";
- reg = <0x370000 0x10000>;
- read-only;
- };
-
- partition@380000 {
- label = "apcd";
- reg = <0x380000 0x10000>;
- read-only;
- };
-
- partition@390000 {
- label = "mfginfo";
- reg = <0x390000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mfginfo_1d: macaddr@1d {
- reg = <0x1d 0x6>;
- };
-
- macaddr_mfginfo_45: macaddr@45 {
- compatible = "mac-base";
- reg = <0x45 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@3a0000 {
- label = "fcache";
- reg = <0x3a0000 0x10000>;
- read-only;
- };
-
- partition@3b0000 {
- /* Called osss1 in smem */
- label = "u-boot-env-bak";
- reg = <0x3b0000 0x10000>;
- read-only;
- };
-
- partition@3f0000 {
- label = "u-boot-env";
- reg = <0x3c0000 0x40000>;
- read-only;
- };
- };
- };
-
- flash@1 {
- status = "okay";
-
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- /* 'aos0' in Aruba firmware */
- label = "aos0";
- reg = <0x0 0x2000000>;
- read-only;
- };
-
- partition@2000000 {
- /* 'aos1' in Aruba firmware */
- label = "ubi";
- reg = <0x2000000 0x2000000>;
- };
-
- partition@4000000 {
- label = "aruba-ubifs";
- reg = <0x4000000 0x4000000>;
- read-only;
- };
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport5 {
- status = "okay";
-
- label = "wan";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_45 0>;
- qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_45 1>;
- qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4029-aruba-glenmorangie.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Aruba AP-365";
- compatible = "aruba,ap-365";
-
- aliases {
- led-boot = &led_system_green;
- led-failsafe = &led_system_red;
- led-running = &led_system_green;
- led-upgrade = &led_system_red;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_system_red: system_red {
- label = "red:system";
- gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
- };
-
- led_system_green: system_green {
- label = "green:system";
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- };
-
- system_amber {
- label = "amber:system";
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- };
- };
-
- watchdog {
- compatible = "linux,wdt-gpio";
- gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
- hw_algo = "toggle";
- hw_margin_ms = <1000>;
- always-running;
- };
-};
-
-&tlmm {
- /*
- * In addition to the Pins listed below,
- * the following GPIOs have "features":
- * 39 - out - pulse low to reset watchdog status flipflop
- * 40 - out - active high to enable watchdog
- * 41 - out - watchdog poke
- * 42 - out - active low to reset BLE radio
- * 43 - out - active low to reset TPM
- * 47 - out - pulse low to reset warm reset status
- * 54 - out - active low to force HW reset
- * 18 - in - PHY interrupt line
- * 45 - in - power monitor interrupt
- * 48 - in - active low when cold reset
- * 52 - in - active high when watchdog reset
- */
-
- phy-reset {
- line-name = "PHY-reset";
- gpios = <42 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&i2c_0 {
- power-monitor@40 {
- /* No driver */
- compatible = "isl,isl28022";
- reg = <0x40>;
- };
-
- temperature-sensor@48 {
- compatible = "adi,ad7416";
- reg = <0x48>;
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /*
- * There is no partition map for the NOR flash
- * in the stock firmware.
- *
- * All partitions here are based on offsets
- * found in the U-Boot GPL code and information
- * from smem.
- */
-
- partition@0 {
- label = "sbl1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "mibib";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "qsee";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "cdt";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "ddrparams";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "u-boot-env";
- reg = <0xe0000 0x10000>;
- };
-
- partition@f0000 {
- label = "appsbl";
- reg = <0xf0000 0x100000>;
- read-only;
- };
-
- partition@1f0000 {
- label = "ART";
- reg = <0x1f0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@200000 {
- label = "osss";
- reg = <0x200000 0x170000>;
- read-only;
- };
-
- partition@370000 {
- label = "pds";
- reg = <0x370000 0x10000>;
- read-only;
- };
-
- partition@380000 {
- label = "apcd";
- reg = <0x380000 0x10000>;
- read-only;
- };
-
- partition@390000 {
- label = "mfginfo";
- reg = <0x390000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mfginfo_1d: macaddr@1d {
- compatible = "mac-base";
- reg = <0x1d 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@3a0000 {
- label = "fcache";
- reg = <0x3a0000 0x10000>;
- read-only;
- };
-
- partition@3b0000 {
- label = "osss1";
- reg = <0x3b0000 0x50000>;
- read-only;
- };
- };
- };
-};
-
-&wifi0 {
- qcom,ath10k-calibration-variant = "Aruba-AP-365";
-};
-
-&wifi1 {
- qcom,ath10k-calibration-variant = "Aruba-AP-365";
-};
-
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- ethphy: ethernet-phy@5 {
- reg = <0x5>;
- };
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- i2c_0: i2c@78b7000 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- tpm@29 {
- /* No Driver */
- compatible = "atmel,at97sc3203";
- reg = <0x29>;
- read-only;
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "Reset button";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- /* Texas Instruments CC2540T BLE radio */
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio10", "gpio11";
- function = "blsp_i2c0";
- drive-strength = <4>;
- bias-disable;
- };
- };
-
- serial_0_pins: serial_0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial_1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- /* 'aos0' in Aruba firmware */
- label = "aos0";
- reg = <0x0 0x2000000>;
- read-only;
- };
-
- partition@2000000 {
- /* 'aos1' in Aruba firmware */
- label = "ubi";
- reg = <0x2000000 0x2000000>;
- };
-
- partition@4000000 {
- label = "aruba-ubifs";
- reg = <0x4000000 0x4000000>;
- read-only;
- };
- };
- };
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-
- /delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
- phy-handle = <ðphy>;
- phy-mode = "rgmii-id";
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-ðphy2 {
- status = "disabled";
-};
-
-ðphy3 {
- status = "disabled";
-};
-
-ðphy4 {
- status = "disabled";
-};
-
-&psgmiiphy {
- status = "disabled";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_1d 0>;
- qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_1d 1>;
- qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "GL.iNet GL-B1300";
- compatible = "glinet,gl-b1300";
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- label-mac-device = &swport4;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- mesh {
- label = "green:mesh";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- mx25l25635f@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- SBL1@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- MIBIB@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- QSEE@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- CDT@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- DDRPARAMS@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- APPSBLENV@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- APPSBL@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- ART@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- firmware@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio54";
- };
- pinconf {
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0 2>;
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0 0>;
-};
-
-&swport5 {
- status = "okay";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "GL-B1300";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "GL-B1300";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "GL.iNet GL-S1300";
- compatible = "glinet,gl-s1300";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- mesh {
- label = "green:mesh";
- gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
- };
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vqmmc>;
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- SBL1@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- MIBIB@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- QSEE@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- CDT@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- DDRPARAMS@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- APPSBLENV@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- APPSBL@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- ART@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- firmware@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0xe80000>;
- };
- };
- };
-};
-
-&blsp1_spi2 {
- pinctrl-0 = <&spi_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- spidev1: spi@0 {
- compatible = "silabs,si3210";
- reg = <0>;
- spi-max-frequency = <24000000>;
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- };
- pinconf {
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- spi_1_pins: spi_1_pinmux {
- mux {
- pins = "gpio44", "gpio46", "gpio47";
- function = "blsp_spi1";
- bias-disable;
- };
- host_int {
- pins = "gpio42";
- function = "gpio";
- input;
- };
- cs {
- pins = "gpio45";
- function = "gpio";
- bias-pull-up;
- };
- wake {
- pins = "gpio40";
- function = "gpio";
- output-high;
- };
- reset {
- pins = "gpio49";
- function = "gpio";
- output-high;
- };
- };
-
- sd_pins: sd_pins {
- pinmux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio28", "gpio29", "gpio30", "gpio31";
- drive-strength = <10>;
- };
-
- pinmux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
-
- pinmux_sd7 {
- function = "sdio";
- pins = "gpio32";
- drive-strength = <10>;
- bias-disable;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "GL-S1300";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "GL-S1300";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for Meraki "Insect" series
- *
- * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
- * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
- *
- * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- aliases {
- led-boot = &status_green;
- led-failsafe = &status_red;
- led-running = &status_green;
- led-upgrade = &power_orange;
- };
-
- /* Do we really need this defined? */
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- /* It is a 56-bit counter that supplies the count to the ARM arch
- timers and without upstream driver */
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- serial@78b0000 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- bluetooth {
- compatible = "ti,cc2650";
- enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power_orange: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- panic-indicator;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_i2c3 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c64";
- pagesize = <32>;
- reg = <0x50>;
- read-only; /* This holds our MAC & Meraki board-data */
- #address-cells = <1>;
- #size-cells = <1>;
-
- mac_address: mac-address@66 {
- compatible = "mac-base";
- reg = <0x66 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
-};
-
-&blsp1_i2c4 {
- pinctrl-0 = <&i2c_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- tricolor: led-controller@30 {
- compatible = "ti,lp5562";
- reg = <0x30>;
- clock-mode = /bits/8 <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* RGB led */
- status_red: chan@0 {
- chan-name = "red:status";
- led-cur = /bits/ 8 <0x20>;
- max-cur = /bits/ 8 <0x60>;
- reg = <0>;
- color = <LED_COLOR_ID_RED>;
- };
-
- status_green: chan@1 {
- chan-name = "green:status";
- led-cur = /bits/ 8 <0x20>;
- max-cur = /bits/ 8 <0x60>;
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- };
-
- chan@2 {
- chan-name = "blue:status";
- led-cur = /bits/ 8 <0x20>;
- max-cur = /bits/ 8 <0x60>;
- reg = <2>;
- color = <LED_COLOR_ID_BLUE>;
- };
-
- chan@3 {
- chan-name = "white:status";
- led-cur = /bits/ 8 <0x20>;
- max-cur = /bits/ 8 <0x60>;
- reg = <3>;
- color = <LED_COLOR_ID_WHITE>;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "sbl1";
- reg = <0x00000000 0x00100000>;
- read-only;
- };
- partition@100000 {
- label = "mibib";
- reg = <0x00100000 0x00100000>;
- read-only;
- };
- partition@200000 {
- label = "bootconfig";
- reg = <0x00200000 0x00100000>;
- read-only;
- };
- partition@300000 {
- label = "qsee";
- reg = <0x00300000 0x00100000>;
- read-only;
- };
- partition@400000 {
- label = "qsee_alt";
- reg = <0x00400000 0x00100000>;
- read-only;
- };
- partition@500000 {
- label = "cdt";
- reg = <0x00500000 0x00080000>;
- read-only;
- };
- partition@580000 {
- label = "cdt_alt";
- reg = <0x00580000 0x00080000>;
- read-only;
- };
- partition@600000 {
- label = "ddrparams";
- reg = <0x00600000 0x00080000>;
- read-only;
- };
- partition@700000 {
- label = "u-boot";
- reg = <0x00700000 0x00200000>;
- read-only;
- };
- partition@900000 {
- label = "u-boot-backup";
- reg = <0x00900000 0x00200000>;
- read-only;
- };
- partition@b00000 {
- label = "ART";
- reg = <0x00b00000 0x00080000>;
- read-only;
- };
- partition@c00000 {
- label = "ubi";
- reg = <0x00c00000 0x07000000>;
- /*
- * Do not try to allocate the remaining
- * 4 MiB to this ubi partition. It will
- * confuse the u-boot and it might not
- * find the kernel partition anymore.
- */
- };
- };
- };
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- nvmem-cells = <&mac_address 1>;
- nvmem-cell-names = "mac-address";
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- /*
- * GPIO43 should be 0/1 whenever the unit is
- * powered through PoE or AC-Adapter.
- * That said, playing with this seems to
- * reset the AP.
- */
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- /* We use the i2c-0 pins for serial_1 */
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- pinmux {
- function = "blsp_i2c0";
- pins = "gpio20", "gpio21";
- };
- pinconf {
- pins = "gpio20", "gpio21";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- i2c_1_pins: i2c_1_pinmux {
- pinmux {
- function = "blsp_i2c1";
- pins = "gpio34", "gpio35";
- };
- pinconf {
- pins = "gpio34", "gpio35";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- /*
- * There are 18 pins. 15 pins are common between LCD and NAND.
- * The QPIC controller arbitrates between LCD and NAND. Of the
- * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
- *
- * The meraki source hints that the bluetooth module claims
- * pin 52 as well. But sadly, there's no data whenever this
- * is a NAND or LCD exclusive pin or not.
- */
-
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Meraki-MR33";
- nvmem-cells = <&mac_address 2>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Meraki-MR33";
- nvmem-cells = <&mac_address 3>;
- nvmem-cell-names = "mac-address";
-};
-
-&gmac {
- status = "okay";
- nvmem-cells = <&mac_address 0>;
- nvmem-cell-names = "mac-address";
-};
-
-&switch {
- status = "okay";
-
- /delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
- phy-handle = <ðphy1>;
- phy-mode = "rgmii-rxid";
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-ðphy2 {
- status = "disabled";
-};
-
-ðphy3 {
- status = "disabled";
-};
-
-ðphy4 {
- status = "disabled";
-};
-
-&psgmiiphy {
- status = "disabled";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-// Device Tree Source for Meraki MR33 (Stinkbug)
-
-#include "qcom-ipq4029-insect-common.dtsi"
-
-/ {
- model = "Meraki MR33 Access Point";
- compatible = "meraki,mr33";
-};
-
-&tricolor {
- enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-// Device Tree Source for Meraki MR74 (Ladybug)
-
-#include "qcom-ipq4029-insect-common.dtsi"
-
-/ {
- model = "Meraki MR74 Access Point";
- compatible = "meraki,mr74";
-};
-
-&tricolor {
- enable-gpio = <&tlmm 14 GPIO_ACTIVE_LOW>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Extreme Networks WS-AP3915i";
- compatible = "extreme-networks,ws-ap3915i";
-
- aliases {
- led-boot = &led_system_green;
- led-failsafe = &led_system_amber;
- led-running = &led_system_green;
- led-upgrade = &led_system_amber;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_system_green: system_green {
- label = "green:system";
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- };
-
- led_system_amber: system_amber {
- label = "amber:system";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- led_wlan24_green: wlan24_green {
- label = "green:wlan24";
- gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- led_wlan24_amber: wlan24_amber {
- label = "amber:wlan24";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- };
-
- led_wlan5_green: wlan5_green {
- label = "green:wlan5";
- gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- led_wlan5_amber: wlan5_amber {
- label = "amber:wlan5";
- gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
- };
-
- iot {
- label = "blue:iot";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART >;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- serial_pins: serial_0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* Layout for 0x0 - 0xe0000 unknown */
-
- partition@e0000 {
- label = "CFG1";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "BootBAK";
- reg = <0xf0000 0x70000>;
- read-only;
- };
-
- partition@160000 {
- label = "WINGCFG1";
- reg = <0x160000 0x10000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
- };
-
- partition@180000 {
- label = "BootPRI";
- reg = <0x180000 0x70000>;
- read-only;
- };
-
- partition@1f0000 {
- label = "WINGCFG2";
- reg = <0x1f0000 0x10000>;
- read-only;
- };
-
- partition@200000 {
- label = "FS";
- reg = <0x200000 0x80000>;
- read-only;
- };
-
- partition@280000 {
- label = "firmware";
- reg = <0x280000 0x1d60000>;
- };
-
- partition@1fe0000 {
- label = "CFG2";
- reg = <0x1fe0000 0x10000>;
- read-only;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Extreme Networks WS-AP391x";
- compatible = "extreme-networks,ws-ap391x";
-
- aliases {
- led-boot = &led_system_green;
- led-failsafe = &led_system_red;
- led-running = &led_system_green;
- led-upgrade = &led_system_red;
- };
-
- soc {
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_system_green: system_green {
- label = "system:green";
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- };
-
- /*
- * system:amber ==> AP3917
- * system:red ==> AP3916
- * */
- led_system_red: system_red {
- label = "system:red_or_system:amber";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- led_wlan24_green: wlan24_green {
- label = "wlan24:green";
- gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- /*
- * wlan24:amber ==> AP3915/AP3917
- * pse:green ==> AP3912
- * */
- led_wlan24_amber: wlan24_amber {
- label = "wlan24:amber_or_pse:green";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- };
-
- led_wlan5_green: wlan5_green {
- label = "wlan5:green";
- gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- /* iot:blue ==> AP3917 */
- led_iot_green: iot_green {
- label = "iot:green_or_iot:blue";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- };
-
- /* eth:green ==> only AP3912/AP3916 */
- led_eth_green: eth_green {
- label = "eth:green";
- gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
- };
-
- /*
- * eth:amber ==> only AP3912/AP3916
- * usb_enable ==> only AP3915e
- */
- led_eth_amber: eth_amber {
- label = "eth:amber_or_usb_enable";
- gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
- };
-
- /*
- * wlan5:amber ==> AP3915/AP3917
- * cam:green ==> only AP3916
- */
- led_wlan5_amber: wlan5_amber {
- label = "wlan5:amber_or_cam:green";
- gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
- };
-
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART >;
- };
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-};
-
-&crypto {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
- label = "sw-eth1";
-};
-
-&swport2 {
- status = "okay";
- label = "sw-eth2";
-};
-
-&swport3 {
- status = "okay";
- label = "sw-eth3";
-};
-
-/* "GE2" on AP3917/AP3916/WiNG-AP7662 */
-&swport4 {
- status = "okay";
- label = "sw-eth4";
-};
-
-/*
- * "GE1" on AP3917/AP3916/AP3915/AP7662
- * "LAN1" on EXTR-AP3912
- */
-&swport5 {
- status = "okay";
- label = "sw-eth5";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- serial_pins: serial_0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* Layout for 0x0 - 0xe0000 unknown */
-
- partition@e0000 {
- label = "CFG1";
- compatible = "u-boot,env-redundant-bool";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "BootBAK";
- reg = <0xf0000 0x70000>;
- read-only;
- };
-
- partition@160000 {
- label = "WINGCFG1";
- reg = <0x160000 0x10000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
- };
-
- partition@180000 {
- label = "BootPRI";
- reg = <0x180000 0x70000>;
- read-only;
- };
-
- partition@1f0000 {
- label = "WINGCFG2";
- reg = <0x1f0000 0x10000>;
- read-only;
- };
-
- partition@200000 {
- label = "FS";
- reg = <0x200000 0x80000>;
- read-only;
- };
-
- partition@280000 {
- label = "firmware";
- reg = <0x280000 0xeb0000>;
- };
-
- partition@1130000 {
- label = "firmware2";
- reg = <0x1130000 0xeb0000>;
- };
-
- partition@1fe0000 {
- label = "CFG2";
- compatible = "u-boot,env-redundant-bool";
- reg = <0x1fe0000 0x10000>;
- read-only;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Wallystech DR40X9";
- compatible = "wallys,dr40x9";
-
- chosen {
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- soc {
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- wlan2g {
- label = "dr4029:green:wlan2g";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "dr4029:green:wlan5g";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- wlan2g-strength {
- label = "dr4029:green:wlan2g-strength";
- gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
- };
-
- wlan5g-strength {
- label = "dr4029:green:wlan5g-strength";
- gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial0_pins: serial0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56", "gpio57",
- "gpio60", "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67", "gpio68",
- "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- sd_pins: sd_pins {
- pinmux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio28", "gpio29", "gpio30", "gpio31";
- drive-strength = <10>;
- };
- pinmux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
- pinmux_sd7 {
- function = "sdio";
- pins = "gpio32";
- drive-strength = <10>;
- bias-disable;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition5@e0000 {
- label = "0:APPSBLENV"; /* uboot env */
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
-
- partition6@f0000 {
- label = "0:APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition7@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: mac-address@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: mac-address@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- macaddr_art_1006: mac-address@1006 {
- reg = <0x1006 0x6>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- macaddr_art_5006: mac-address@5006 {
- reg = <0x5006 0x6>;
- };
- };
- };
-
- partition8@180000 {
- label = "0:CONFIG";
- reg = <0x00180000 0x00010000>;
- read-only;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x04000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
- pinctrl-0 = <&serial0_pins>;
- pinctrl-names = "default";
-};
-
-&blsp1_uart2 {
- status = "okay";
- pinctrl-0 = <&serial1_pins>;
- pinctrl-names = "default";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- num-channels = <4>;
- qcom,num-ees = <2>;
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
-
- /* Unpolulated slot */
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- };
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vqmmc>;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "wan";
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-};
-
-&swport5 {
- status = "okay";
- label = "lan";
- nvmem-cells = <&macaddr_art_6>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cells = <&precal_art_1000>, <&macaddr_art_1006>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- qcom,ath10k-calibration-variant = "Wallys-DR40X9";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_art_5006>;
- qcom,ath10k-calibration-variant = "Wallys-DR40X9";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&prng {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
compatible = "openmesh,a42";
soc {
- rng@22000 {
- status = "okay";
- };
-
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
+ };
+};
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
+&watchdog {
+ status = "okay";
+};
- crypto@8e3a000 {
- status = "okay";
- };
+&prng {
+ status = "okay";
+};
- watchdog@b017000 {
- status = "okay";
- };
- };
+&crypto {
+ status = "okay";
};
&blsp_dma {
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&usb3_hs_phy {
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ phys = <&usb3_hs_phy>;
+ phy-names = "usb2-phy";
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- reset-delay-us = <5000>;
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
leds {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
status = "okay";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <5000>;
+};
+
&gmac {
status = "okay";
nvmem-cells = <&macaddr_art_0>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- rng@22000 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
leds {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
&usb2_hs_phy {
status = "okay";
};
+
+&usb2 {
+ status = "okay";
+};
compatible = "engenius,eap1300";
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
reg = <0x190000 0x1dc0000>;
};
partition9@1f50000 {
+ compatible = "u-boot,env";
label = "u-boot-env";
reg = <0x01f50000 0x00010000>;
+
+ macaddr_ubootenv_ethaddr: ethaddr {
+ #nvmem-cell-cells = <1>;
+ };
};
partition10@1f60000 {
label = "userconfig";
status = "okay";
};
+&switch {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
+&swport5 {
+ status = "okay";
+ label = "lan";
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
+};
+
+&gmac {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
&wifi0 {
status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
+ nvmem-cell-names = "pre-calibration", "mac-address";
+ nvmem-cells = <&precal_art_1000>, <&macaddr_ubootenv_ethaddr 1>;
qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
};
&wifi1 {
status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
+ nvmem-cell-names = "pre-calibration", "mac-address";
+ nvmem-cells = <&precal_art_5000>, <&macaddr_ubootenv_ethaddr 2>;
qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
+ };
+};
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
+&watchdog {
+ status = "okay";
+};
- crypto@8e3a000 {
- status = "okay";
- };
+&prng {
+ status = "okay";
+};
- watchdog@b017000 {
- status = "okay";
- };
- };
+&crypto {
+ status = "okay";
};
&tlmm {
qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
};
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
&usb3_hs_phy {
status = "okay";
};
-&usb2_hs_phy {
+&usb3 {
status = "okay";
};
+
+&usb3_dwc {
+ phys = <&usb3_hs_phy>;
+ phy-names = "usb2-phy";
+};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
status = "okay";
};
+&mdio {
+ status = "okay";
+};
+
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EMD1";
compatible = "engenius,emr3500";
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2_hs_phy: hsphy@a8000 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
status = "okay";
};
+&mdio {
+ status = "okay";
+};
+
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
};
soc {
- rng@22000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
/*
* Disable the broken restart as a workaround for the buggy
* 3.0.0/3.0.1 U-boots that ship with the device.
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&cryptobam {
status = "okay";
};
compatible = "netgear,ex61x0v2";
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
aliases {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
};
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
status = "okay";
};
+&mdio {
+ status = "okay";
+};
+
ðphy0 {
gpio-controller;
#gpio-cells = <2>;
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
&usb2_hs_phy {
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
&blsp_dma {
status = "okay";
};
+&crypto {
+ status = "okay";
+};
+
&cryptobam {
status = "okay";
};
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&usb3_hs_phy {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ phys = <&usb3_hs_phy>;
+ phy-names = "usb2-phy";
+};
+
&mdio {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
+ };
+};
- crypto@8e3a000 {
- status = "okay";
- };
+&watchdog {
+ status = "okay";
+};
- watchdog@b017000 {
- status = "okay";
- };
- };
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
};
&tlmm {
status = "okay";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
gpio_export {
compatible = "gpio-export";
#size-cells = <0>;
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
spi_0_pins: spi_0_pinmux {
mux {
};
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
status = "okay";
};
+&prng {
+ status = "okay";
+};
+
&watchdog {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
status = "okay";
};
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+};
+
&usb2_hs_phy {
status = "okay";
};
+
+&usb2 {
+ status = "okay";
+
+ usb@6000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+};
compatible = "plasmacloud,pa1200";
soc {
- rng@22000 {
- status = "okay";
- };
-
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&cryptobam {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+};
+
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
};
soc {
- rng@22000 {
- status = "okay";
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&qpic_bam {
status = "okay";
};
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
};
};
&usb3 {
status = "okay";
};
+
+&usb3_dwc {
+ phys = <&usb3_hs_phy>;
+ phy-names = "usb2-phy";
+};
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
};
};
&usb3 {
status = "okay";
};
+
+&usb3_dwc {
+ phys = <&usb3_hs_phy>;
+ phy-names = "usb2-phy";
+};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
leds {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
status = "okay";
};
+&mdio {
+ status = "okay";
+};
+
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
};
soc {
- rng@22000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
+ };
+};
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
+&watchdog {
+ status = "okay";
+};
- crypto@8e3a000 {
- status = "okay";
- };
+&prng {
+ status = "okay";
+};
- watchdog@b017000 {
- status = "okay";
- };
- };
+&crypto {
+ status = "okay";
};
&blsp_dma {
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&usb3_hs_phy {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration";
compatible = "openmesh,a62";
soc {
- rng@22000 {
- status = "okay";
- };
-
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <1000>;
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
led_spi {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&blsp_dma {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+};
+
&usb2_hs_phy {
status = "okay";
};
+&usb2 {
+ status = "okay";
+
+ usb@6000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <1000>;
+};
+
&gmac {
status = "okay";
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
- serial@78af000 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- serial@78b0000 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- i2c@78b7000 { /* BLSP1 QUP2 */
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
leds {
compatible = "gpio-leds";
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
&blsp_dma {
status = "okay";
};
+&crypto {
+ status = "okay";
+};
+
&cryptobam {
status = "okay";
};
};
};
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_uart2 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_i2c3 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&usb3 {
status = "okay";
+};
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
+&usb3_dwc {
+ #address-cells = <1>;
+ #size-cells = <0>;
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
};
};
&usb2 {
status = "okay";
- dwc3@6000000 {
+ usb@6000000 {
#address-cells = <1>;
#size-cells = <0>;
&usb2_hs_phy {
status = "okay";
};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+};
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
};
+};
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
+&watchdog {
+ status = "okay";
+};
- crypto@8e3a000 {
- status = "okay";
- };
+&prng {
+ status = "okay";
+};
- watchdog@b017000 {
- status = "okay";
- };
- };
+&crypto {
+ status = "okay";
};
&blsp_dma {
};
};
+&mdio {
+ status = "okay";
+};
+
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration";
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_0_pins: serial_pinmux {
mux {
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
&qpic_bam {
status = "okay";
};
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- ethphy: ethernet-phy@0 {
- reg = <0x0>;
- };
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
key {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_0_pins: serial_pinmux {
mux {
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ ethphy: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+};
+
&gmac {
status = "okay";
};
phy-mode = "rgmii-id";
};
+&qca807x {
+ status = "disabled";
+};
+
ðphy1 {
status = "disabled";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
key {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_0_pins: serial_pinmux {
mux {
};
};
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
};
keys {
};
};
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&vqmmc {
status = "okay";
};
};
};
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&vqmmc {
status = "okay";
};
};
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
&usb2 {
status = "okay";
- dwc3@6000000 {
+ usb@6000000 {
#address-cells = <1>;
#size-cells = <0>;
&usb3 {
status = "okay";
+};
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
+&usb3_dwc {
+ #address-cells = <1>;
+ #size-cells = <0>;
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
};
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
};
};
+&mdio {
+ status = "okay";
+
+ ar8035: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&qca807x {
+ status = "disabled";
+};
+
+ðphy0 {
+ status = "disabled";
+};
+
ðphy1 {
status = "disabled";
};
status = "okay";
label = "lan";
- phy-handle = <ðphy0>;
+ phy-handle = <&ar8035>;
phy-mode = "rgmii-id";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&blsp1_i2c3 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
};
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
+ };
+};
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
+&watchdog {
+ status = "okay";
+};
- crypto@8e3a000 {
- status = "okay";
- };
+&prng {
+ status = "okay";
+};
- watchdog@b017000 {
- status = "okay";
- };
- };
+&crypto {
+ status = "okay";
};
&blsp_dma {
status = "okay";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+};
+
&gmac {
status = "okay";
nvmem-cell-names = "mac-address";
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&usb3_ss_phy {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration", "mac-address";
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
+ };
+};
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
+&watchdog {
+ status = "okay";
+};
- crypto@8e3a000 {
- status = "okay";
- };
+&prng {
+ status = "okay";
+};
- watchdog@b017000 {
- status = "okay";
- };
- };
+&crypto {
+ status = "okay";
};
&blsp_dma {
status = "okay";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+};
+
&gmac {
status = "okay";
nvmem-cell-names = "mac-address";
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&usb3_ss_phy {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
/*
* The MD5 sum of the board file of the MF286D is identical to the board
* file in the OEM firmware
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
+ };
+};
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
+&watchdog {
+ status = "okay";
+};
- crypto@8e3a000 {
- status = "okay";
- };
+&prng {
+ status = "okay";
+};
- watchdog@b017000 {
- status = "okay";
- };
- };
+&crypto {
+ status = "okay";
};
&blsp_dma {
status = "okay";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+};
+
&gmac {
status = "okay";
nvmem-cell-names = "mac-address";
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&usb3_ss_phy {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration", "mac-address";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- dma@7984000 {
- status = "okay";
- };
};
keys-repeat {
pinctrl-0 = <&usb3_pins>, <<e_pins>;
pinctrl-names = "default";
+};
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
+&usb3_dwc {
+ #address-cells = <1>;
+ #size-cells = <0>;
- device@1 {
- compatible = "usb1bc7,1900";
- reg = <1>;
- };
+ device@1 {
+ compatible = "usb1bc7,1900";
+ reg = <1>;
};
};
};
soc {
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
key {
};
};
+&watchdog {
+ status = "okay";
+};
+
&tlmm {
serial_0_pins: serial_pinmux {
mux {
status = "okay";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+};
+
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration";
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+};
+
+
&usb2_hs_phy {
status = "okay";
};
+
+&usb2 {
+ status = "okay";
+
+ usb@6000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&vqmmc {
status = "okay";
};
status = "okay";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+};
+
&gmac {
status = "okay";
};
compatible = "plasmacloud,pa2200";
soc {
- rng@22000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_pins: serial_pinmux {
mux {
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
leds {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&blsp_dma {
status = "okay";
};
};
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+};
+
ðphy0 {
qcom,single-led-1000;
qcom,single-led-100;
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
&usb2_hs_phy {
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&vqmmc {
status = "okay";
};
chosen {
bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
};
-
- soc {
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
- };
};
&usb3_hs_phy {
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
&usb2_hs_phy {
status = "okay";
};
+
+&usb2 {
+ status = "okay";
+};
chosen {
bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
};
-
- soc {
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
- };
};
&usb3_hs_phy {
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
&usb2_hs_phy {
status = "okay";
};
+
+&usb2 {
+ status = "okay";
+};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&cryptobam {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+};
+
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
+ };
+};
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
+&watchdog {
+ status = "okay";
+};
- crypto@8e3a000 {
- status = "okay";
- };
+&prng {
+ status = "okay";
+};
- watchdog@b017000 {
- status = "okay";
- };
- };
+&crypto {
+ status = "okay";
};
&blsp_dma {
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&usb3_ss_phy {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "cellc,rtl30vw";
qcom,ath10k-calibration-variant = "cellc,rtl30vw";
};
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
compatible = "unielec,u4019","qcom,ipq4019";
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
aliases {
led-boot = &led_status;
led-failsafe = &led_status;
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
&blsp_dma {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+};
+
+
&usb2_hs_phy {
status = "okay";
};
+&usb2 {
+ status = "okay";
+
+ usb@6000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+};
+
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019-whw03.dtsi"
+
+/ {
+ model = "Linksys WHW03 (Velop)";
+ compatible = "linksys,whw03", "qcom,ipq4019";
+
+ // Default bootargs include rootfstype=ext4 and need to be overriden.
+ chosen {
+ bootargs-append = " rootfstype=squashfs";
+ };
+};
+
+&tlmm {
+ sd_pins: sd-pinmux {
+ pins = "gpio23", "gpio24", "gpio25", "gpio26",
+ "gpio27", "gpio28", "gpio29", "gpio30",
+ "gpio31", "gpio32";
+ function = "sdio";
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio58", "gpio59";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+
+ spi_0_pins: spi-0-pinmux {
+ pins = "gpio12", "gpio13", "gpio14", "gpio15";
+ function = "blsp_spi0";
+ bias-disable;
+ };
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
+};
+
+&vqmmc {
+ status = "okay";
+};
+
+&sdhci {
+ status = "okay";
+ pinctrl-0 = <&sd_pins>;
+ pinctrl-names = "default";
+
+ cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
+ sd-ldo-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+
+ vqmmc-supply = <&vqmmc>;
+};
+
+&wifi0 {
+ qcom,ath10k-calibration-variant = "linksys-whw03";
+};
+
+&wifi1 {
+ qcom,ath10k-calibration-variant = "linksys-whw03";
+};
+
+&wifi2 {
+ reg = <0x00000000 0 0 0 0>;
+
+ qcom,ath10k-calibration-variant = "linksys-whw03";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/qcom,tcsr.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ led-boot = &led_blue;
+ led-failsafe = &led_red;
+ led-running = &led_blue;
+ led-upgrade = &led_red;
+ };
+
+ soc {
+ ess-tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@194b000 {
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pinmux {
+ mux-1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
+ };
+
+ mux-2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
+ };
+ };
+
+ serial_0_pins: serial0-pinmux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+
+ spi_1_pins: spi-1-pinmux {
+ mux-1 {
+ pins = "gpio44", "gpio46", "gpio47";
+ function = "blsp_spi1";
+ bias-disable;
+ };
+
+ mux-2 {
+ pins = "gpio45", "gpio49";
+ function = "gpio";
+ bias-pull-up;
+ output-high;
+ };
+
+ host-interrupt {
+ pins = "gpio42";
+ function = "gpio";
+ input;
+ };
+ };
+
+ wifi_0_pins: wifi0-pinmux {
+ pins = "gpio52";
+ function = "gpio";
+ drive-strength = <6>;
+ bias-pull-up;
+ output-high;
+ };
+
+ zigbee-0 {
+ gpio-hog;
+ gpios = <29 GPIO_ACTIVE_HIGH>;
+ bias-disable;
+ output-low;
+ };
+
+ zigbee-1 {
+ gpio-hog;
+ gpios = <50 GPIO_ACTIVE_HIGH>;
+ bias-disable;
+ input;
+ };
+
+ bluetooth-enable {
+ gpio-hog;
+ gpios = <32 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
+ðphy0 {
+ status = "disabled";
+};
+
+ðphy1 {
+ status = "disabled";
+};
+
+ðphy2 {
+ status = "disabled";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&blsp_dma {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+ num-channels = <4>;
+ qcom,num-ees = <2>;
+};
+
+&crypto {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ status = "okay";
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+};
+
+&blsp1_uart2 {
+ status = "okay";
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+
+ bluetooth {
+ compatible = "csr,8811";
+
+ enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&blsp1_spi2 {
+ status = "okay";
+ pinctrl-0 = <&spi_1_pins>;
+ pinctrl-names = "default";
+
+ cs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
+
+ zigbee@0 {
+ compatible = "silabs,em3581";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <12000000>;
+ };
+};
+
+&blsp1_i2c3 {
+ status = "okay";
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+
+ // RGB LEDs
+ pca9633: led-controller@62 {
+ compatible = "nxp,pca9633";
+ nxp,hw-blink;
+ reg = <0x62>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led_red: red@0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_INDICATOR;
+ reg = <0>;
+ };
+
+ led_green: green@1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ reg = <1>;
+ };
+
+ led_blue: blue@2 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_INDICATOR;
+ reg = <2>;
+ };
+ };
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
+ clkreq-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi2: wifi@1,0 {
+ compatible = "qcom,ath10k";
+ };
+ };
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&gmac {
+ status = "okay";
+};
+
+&switch {
+ status = "okay";
+};
+
+&swport4 {
+ status = "okay";
+ label = "lan";
+};
+
+&swport5 {
+ status = "okay";
+ label = "wan";
+};
+
+&wifi0 {
+ status = "okay";
+ pinctrl-0 = <&wifi_0_pins>;
+ pinctrl-names = "default";
+
+ qcom,coexist-support = <1>;
+ qcom,coexist-gpio-pin = <52>;
+};
+
+&wifi1 {
+ status = "okay";
+
+ ieee80211-freq-limit = <5170000 5330000>;
+};
+
+&wifi2 {
+ status = "okay";
+
+ ieee80211-freq-limit = <5490000 5835000>;
+};
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
+#include "qcom-ipq4019-whw03.dtsi"
/ {
model = "Linksys WHW03 V2 (Velop)";
compatible = "linksys,whw03v2", "qcom,ipq4019";
- aliases {
- led-boot = &led_blue;
- led-failsafe = &led_red;
- led-running = &led_green;
- led-upgrade = &led_red;
- };
-
- // The arguments rootfstype and ro are needed
- // to override the default bootargs
+ // Default bootargs include rootfstype=ext4 and need to be overriden.
chosen {
bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
stdout-path = &blsp1_uart1;
};
-
- soc {
- ess-tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
};
-
&tlmm {
- mdio_pins: mdio-pinmux {
- mux-1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux-2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
i2c_0_pins: i2c-0-pinmux {
- mux {
- function = "blsp_i2c0";
- pins = "gpio20", "gpio21";
- bias-disable;
- };
- };
-
- serial_0_pins: serial0-pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1-pinmux {
- mux {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
};
spi_0_pins: spi-0-pinmux {
mux {
- function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
+ function = "blsp_spi0";
drive-strength = <12>;
bias-disable;
};
output-high;
};
};
+};
- spi_1_pins: spi-1-pinmux {
- mux-1 {
- function = "blsp_spi1";
- pins = "gpio44", "gpio46","gpio47";
- bias-disable;
- };
-
- mux-2 {
- pins = "gpio31", "gpio45", "gpio49";
- function = "gpio";
- bias-pull-up;
- output-high;
- };
-
- host-interrupt {
- pins = "gpio42";
- function = "gpio";
- input;
- };
- };
-
- wifi_0_pins: wifi0-pinmux {
- btcoexist {
- bias-pull-up;
- drive-strength = <6>;
- function = "gpio";
- output-high;
- pins = "gpio52";
- };
- };
-
- zigbee-0 {
- gpio-hog;
- gpios = <29 GPIO_ACTIVE_HIGH>;
- bias-disable;
- output-low;
- };
-
- zigbee-1 {
- gpio-hog;
- gpios = <50 GPIO_ACTIVE_HIGH>;
- bias-disable;
- input;
- };
-
- bluetooth-enable {
- gpio-hog;
- gpios = <32 GPIO_ACTIVE_HIGH>;
+&spi_1_pins {
+ mux-wake {
+ pins = "gpio31";
+ function = "gpio";
+ bias-pull-up;
output-high;
};
};
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
- phy-reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
-};
-
-ðphy0 {
- status = "disabled";
-};
-ðphy1 {
- status = "disabled";
-};
-
-ðphy2 {
- status = "disabled";
+ phy-reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
};
ðphy3 {
reg = <0x1d>;
};
-&watchdog {
- status = "okay";
-};
-
-&prng {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- num-channels = <4>;
- qcom,num-ees = <2>;
-
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&blsp1_uart1 {
- status = "okay";
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
-};
-
-&blsp1_uart2 {
- status = "okay";
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
-
- bluetooth {
- compatible = "csr,8811";
-
- enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&blsp1_spi2 {
- pinctrl-0 = <&spi_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- cs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-
- zigbee@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "silabs,em3581";
- reg = <0>;
- spi-max-frequency = <12000000>;
- };
-};
-
-&blsp1_i2c3 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- // RGB LEDs
- pca9633: led-controller@62 {
- compatible = "nxp,pca9633";
- nxp,hw-blink;
- reg = <0x62>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led_red: red@0 {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_INDICATOR;
- linux,default-trigger = "none";
- reg = <0>;
- };
-
- led_green: green@1 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- linux,default-trigger = "none";
- reg = <1>;
- };
-
- led_blue: blue@2 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_INDICATOR;
- linux,default-trigger = "default-on";
- reg = <2>;
- };
- };
-};
-
&usb3_ss_phy {
status = "okay";
};
};
};
-&pcie0 {
- status = "okay";
-
- perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
- clkreq-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
&swport4 {
- status = "okay";
- label = "lan";
-
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_gmac1>;
};
&swport5 {
- status = "okay";
- label = "wan";
-
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_gmac0 0>;
};
&wifi0 {
- pinctrl-0 = <&wifi_0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- qcom,coexist-support = <1>;
- qcom,coexist-gpio-pin = <0x34>;
-
- ieee80211-freq-limit = <2401000 2473000>;
qcom,ath10k-calibration-variant = "linksys-whw03v2";
nvmem-cell-names = "pre-calibration", "mac-address";
};
&wifi1 {
- status = "okay";
-
- ieee80211-freq-limit = <5170000 5250000>;
qcom,ath10k-calibration-variant = "linksys-whw03v2";
nvmem-cell-names = "pre-calibration", "mac-address";
};
&wifi2 {
- status = "okay";
+ reg = <0x00010000 0 0 0 0>;
- ieee80211-freq-limit = <5735000 5835000>;
qcom,ath10k-calibration-variant = "linksys-whw03v2";
nvmem-cell-names = "pre-calibration", "mac-address";
};
soc {
- pinctrl@1000000 {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- bias-disable;
- output-high;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- led_0_pins: led0_pinmux {
- mux_1 {
- pins = "gpio36";
- function = "led0";
- bias-pull-down;
- };
- mux_2 {
- pins = "gpio40";
- function = "led4";
- bias-pull-down;
- };
- };
- };
-
- blsp_dma: dma@7884000 {
- status = "okay";
- };
-
- spi_0: spi@78b5000 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;
- num-cs = <2>;
-
- flash0@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- broken-flash-reset;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x000000 0x040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x040000 0x020000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x060000 0x060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0x0c0000 0x010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x0d0000 0x010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "u-boot-env";
- reg = <0x0e0000 0x010000>;
- };
-
- partition@f0000 {
- label = "u-boot";
- reg = <0x0f0000 0x080000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- nand@1 {
- reg = <1>;
- status = "okay";
- compatible = "spi-nand";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* The device has 128MB, but we can only address
- * 64MB because of the bootloader's default settings.
- * This is due to the old mt29f driver,
- * which detected the deivce with only 64MB
- */
- partition@0 {
- label = "ubi";
- reg = <0x0000000 0x4000000>;
- };
- };
- };
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <5000>;
- };
-
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
+ };
- i2c_0: i2c@78b7000 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
+ keys {
+ compatible = "gpio-keys";
- serial@78af000 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
+ reset {
+ label = "reset";
+ gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
};
+ };
+};
- serial@78b0000 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
+&tlmm {
+ mdio_pins: mdio_pinmux {
+ mux_1 {
+ pins = "gpio6";
+ function = "mdio";
+ bias-pull-up;
};
- usb3_ss_phy: ssphy@9a000 {
- status = "okay";
+ mux_2 {
+ pins = "gpio7";
+ function = "mdc";
+ bias-pull-up;
};
+ };
- usb3_hs_phy: hsphy@a6000 {
- status = "okay";
+ serial_0_pins: serial_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
};
+ };
- usb3: usb3@8af8800 {
- status = "okay";
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
};
+ };
- usb2_hs_phy: hsphy@a8000 {
- status = "okay";
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
};
- usb2: usb2@60f8800 {
- status = "okay";
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
};
+ };
- cryptobam: dma@8e04000 {
- status = "okay";
+ i2c_0_pins: i2c_0_pinmux {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
};
+ };
- crypto@8e3a000 {
- status = "okay";
+ nand_pins: nand_pins {
+ pullups {
+ pins = "gpio52", "gpio53", "gpio58", "gpio59";
+ function = "qpic";
+ bias-pull-up;
};
- watchdog@b017000 {
- status = "okay";
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
};
+ };
- qpic_bam: dma@7984000 {
- status = "okay";
+ led_0_pins: led0_pinmux {
+ mux_1 {
+ pins = "gpio36";
+ function = "led0";
+ bias-pull-down;
};
-
- pcie0: pci@40000000 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
+ mux_2 {
+ pins = "gpio40";
+ function = "led4";
+ bias-pull-down;
};
};
+};
- keys {
- compatible = "gpio-keys";
+&blsp_dma {
+ status = "okay";
+};
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_uart2 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_i2c3 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;
+ num-cs = <2>;
+
+ flash0@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <24000000>;
+ broken-flash-reset;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:SBL1";
+ reg = <0x000000 0x040000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "0:MIBIB";
+ reg = <0x040000 0x020000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "0:QSEE";
+ reg = <0x060000 0x060000>;
+ read-only;
+ };
+
+ partition@c0000 {
+ label = "0:CDT";
+ reg = <0x0c0000 0x010000>;
+ read-only;
+ };
+
+ partition@d0000 {
+ label = "0:DDRPARAMS";
+ reg = <0x0d0000 0x010000>;
+ read-only;
+ };
+
+ partition@e0000 {
+ label = "u-boot-env";
+ reg = <0x0e0000 0x010000>;
+ };
+
+ partition@f0000 {
+ label = "u-boot";
+ reg = <0x0f0000 0x080000>;
+ read-only;
+ };
+
+ partition@170000 {
+ label = "0:ART";
+ reg = <0x170000 0x010000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ precal_art_1000: precal@1000 {
+ reg = <0x1000 0x2f20>;
+ };
+
+ precal_art_5000: precal@5000 {
+ reg = <0x5000 0x2f20>;
+ };
+ };
+ };
+ };
+ };
+
+ nand@1 {
+ reg = <1>;
+ status = "okay";
+ compatible = "spi-nand";
+ spi-max-frequency = <24000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* The device has 128MB, but we can only address
+ * 64MB because of the bootloader's default settings.
+ * This is due to the old mt29f driver,
+ * which detected the deivce with only 64MB
+ */
+ partition@0 {
+ label = "ubi";
+ reg = <0x0000000 0x4000000>;
+ };
};
};
};
+&watchdog {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&usb3_ss_phy {
+ status = "okay";
+};
+
+&usb3_hs_phy {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&usb2_hs_phy {
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
};
+&pcie0 {
+ status = "okay";
+ perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <5000>;
+};
+
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration";
};
soc {
- rng@22000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
};
leds {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
serial_0_pins: serial0_pinmux {
mux {
&usb3_hs_phy {
status = "okay";
};
+
+&usb3 {
+ status = "okay";
+};
};
soc {
-
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
&blsp_dma {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+};
+
&usb2_hs_phy {
status = "okay";
};
+&usb2 {
+ status = "okay";
+
+ usb@6000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+};
+
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration";
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
regulator-usb-vbus {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
&blsp_dma {
status = "okay";
status = "okay";
};
+&usb2 {
+ status = "okay";
+
+ usb@6000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb2_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+};
+
&usb3_hs_phy {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ usb3_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+};
+
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
status = "okay";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- i2c_0: i2c@78b7000 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- tpm@29 {
- /* No Driver */
- compatible = "atmel,at97sc3203";
- reg = <0x29>;
- read-only;
- };
-
- power-monitor@40 {
- /* No driver */
- compatible = "isl,isl28022";
- reg = <0x40>;
- };
- };
};
leds {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&blsp_dma {
status = "okay";
};
pins = "gpio20", "gpio21";
function = "blsp_i2c0";
drive-strength = <4>;
- bias-disable;
+ bias-pull-up;
};
};
};
};
+&blsp1_i2c3 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tpm@29 {
+ /* No Driver */
+ compatible = "atmel,at97sc3203";
+ reg = <0x29>;
+ read-only;
+ };
+
+ power-monitor@40 {
+ /* No driver */
+ /* Device also replies on address 0x3f, see */
+ /* ISL28022 datasheet, "Broadcast Addressing" */
+ compatible = "isl,isl28022";
+ reg = <0x40>;
+ };
+};
+
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
#size-cells = <1>;
macaddr_mfginfo_1d: macaddr@1d {
+ compatible = "mac-base";
reg = <0x1d 0x6>;
+ #nvmem-cell-cells = <1>;
};
macaddr_mfginfo_45: macaddr@45 {
};
};
-&usb2_hs_phy {
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ phys = <&usb3_hs_phy>;
+ phy-names = "usb2-phy";
+};
+
+&usb3_hs_phy {
status = "okay";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+};
+
&gmac {
status = "okay";
+
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_mfginfo_1d 1>;
};
&switch {
status = "okay";
label = "wan";
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_mfginfo_1d 0>;
};
&wifi0 {
};
};
-&i2c_0 {
+&blsp1_i2c3 {
power-monitor@40 {
/* No driver */
compatible = "isl,isl28022";
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- ethphy: ethernet-phy@5 {
- reg = <0x5>;
- };
- };
-
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- i2c_0: i2c@78b7000 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- tpm@29 {
- /* No Driver */
- compatible = "atmel,at97sc3203";
- reg = <0x29>;
- read-only;
- };
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&blsp_dma {
status = "okay";
};
status = "okay";
};
+&blsp1_i2c3 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ tpm@29 {
+ /* No Driver */
+ compatible = "atmel,at97sc3203";
+ reg = <0x29>;
+ read-only;
+ };
+};
+
&cryptobam {
status = "okay";
};
};
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ ethphy: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+};
+
&gmac {
status = "okay";
};
phy-mode = "rgmii-id";
};
+&qca807x {
+ status = "disabled";
+};
+
ðphy0 {
status = "disabled";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&blsp_dma {
status = "okay";
};
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&usb3_hs_phy {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
&gmac {
status = "okay";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&vqmmc {
status = "okay";
};
status = "okay";
};
+&usb2 {
+ status = "okay";
+};
+
&usb3_hs_phy {
status = "okay";
};
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration";
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
/* It is a 56-bit counter that supplies the count to the ARM arch
timers and without upstream driver */
counter@4a1000 {
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- serial@78b0000 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- bluetooth {
- compatible = "ti,cc2650";
- enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
keys {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&blsp_dma {
status = "okay";
};
status = "okay";
};
+&blsp1_uart2 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "ti,cc2650";
+ enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+ };
+};
+
&cryptobam {
status = "okay";
};
nvmem-cell-names = "mac-address";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+
+ ar8035: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&gmac {
status = "okay";
nvmem-cells = <&mac_address 0>;
status = "okay";
label = "lan";
- phy-handle = <ðphy1>;
+ phy-handle = <&ar8035>;
phy-mode = "rgmii-rxid";
};
+&qca807x {
+ status = "disabled";
+};
+
ðphy0 {
status = "disabled";
};
+ðphy1 {
+ status = "disabled";
+};
+
ðphy2 {
status = "disabled";
};
};
soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
};
leds {
};
};
+&watchdog {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
&blsp_dma {
status = "okay";
};
status = "okay";
};
+&mdio {
+ status = "okay";
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+};
+
&gmac {
status = "okay";
};
PROFILES := Default
KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
KERNEL_LOADADDR := 0x80208000
- DEVICE_DTS_DIR = $(if $(CONFIG_TESTING_KERNEL),$$(DTS_DIR)/qcom,$$(DTS_DIR))
+ DEVICE_DTS_DIR = $$(DTS_DIR)/qcom
DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
DEVICE_DTS_CONFIG := config@1
IMAGES := sysupgrade.bin
IMAGE_SIZE := 25344k
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
endef
-# Missing DSA Setup
-#TARGET_DEVICES += engenius_eap1300
+TARGET_DEVICES += engenius_eap1300
define Device/engenius_eap2200
$(call Device/FitImage)
endef
TARGET_DEVICES += linksys_mr8300
+define Device/linksys_whw03
+ $(call Device/FitzImage)
+ DEVICE_VENDOR := Linksys
+ DEVICE_MODEL := WHW03
+ SOC := qcom-ipq4019
+ KERNEL_SIZE := 8192k
+ IMAGE_SIZE := 131072k
+ IMAGES += factory.bin
+ IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | linksys-image type=WHW03
+ DEVICE_PACKAGES := ath10k-firmware-qca9888-ct kmod-leds-pca963x kmod-spi-dev kmod-bluetooth \
+ kmod-fs-ext4 e2fsprogs kmod-fs-f2fs mkf2fs losetup
+endef
+TARGET_DEVICES += linksys_whw03
+
define Device/linksys_whw03v2
$(call Device/FitzImage)
DEVICE_VENDOR := Linksys
+++ /dev/null
-From be59072c6eeb7535bf9a339fb9d5a8bfae17ac22 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 14 Aug 2023 12:40:23 +0200
-Subject: [PATCH] dt-bindings: clock: qcom: ipq4019: add missing networking
- resets
-
-Add bindings for the missing networking resets found in IPQ4019 GCC.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20230814104119.96858-1-robert.marko@sartura.hr
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- include/dt-bindings/clock/qcom,gcc-ipq4019.h | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
-@@ -165,5 +165,11 @@
- #define GCC_QDSS_BCR 69
- #define GCC_MPM_BCR 70
- #define GCC_SPDM_BCR 71
-+#define ESS_MAC1_ARES 72
-+#define ESS_MAC2_ARES 73
-+#define ESS_MAC3_ARES 74
-+#define ESS_MAC4_ARES 75
-+#define ESS_MAC5_ARES 76
-+#define ESS_PSGMII_ARES 77
-
- #endif
+++ /dev/null
-From 20014461691efc9e274c3870357152db7f091820 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 14 Aug 2023 12:40:24 +0200
-Subject: [PATCH] clk: qcom: gcc-ipq4019: add missing networking resets
-
-IPQ4019 has more networking related resets that will be required for future
-wired networking support, so lets add them.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
-Link: https://lore.kernel.org/r/20230814104119.96858-2-robert.marko@sartura.hr
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- drivers/clk/qcom/gcc-ipq4019.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq4019.c
-+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1707,6 +1707,12 @@ static const struct qcom_reset_map gcc_i
- [GCC_TCSR_BCR] = {0x22000, 0},
- [GCC_MPM_BCR] = {0x24000, 0},
- [GCC_SPDM_BCR] = {0x25000, 0},
-+ [ESS_MAC1_ARES] = {0x1200C, 0},
-+ [ESS_MAC2_ARES] = {0x1200C, 1},
-+ [ESS_MAC3_ARES] = {0x1200C, 2},
-+ [ESS_MAC4_ARES] = {0x1200C, 3},
-+ [ESS_MAC5_ARES] = {0x1200C, 4},
-+ [ESS_PSGMII_ARES] = {0x1200C, 5},
- };
-
- static const struct regmap_config gcc_ipq4019_regmap_config = {
+++ /dev/null
-From ff4aa3bc98258a240b9bbab53fd8d2fb8184c485 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Aug 2023 18:45:39 +0200
-Subject: [PATCH] firmware: qcom_scm: disable SDI if required
-
-IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that
-means that WDT being asserted or just trying to reboot will hang the board
-in the debug mode and only pulling the power and repowering will help.
-Some IPQ4019 boards like Google WiFI have it enabled as well.
-
-Luckily, SDI can be disabled via an SCM call.
-
-So, lets use the boolean DT property to identify boards that have SDI
-enabled by default and use the SCM call to disable SDI during SCM probe.
-It is important to disable it as soon as possible as we might have a WDT
-assertion at any time which would then leave the board in debug mode,
-thus disabling it during SCM removal is not enough.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com>
-Link: https://lore.kernel.org/r/20230816164641.3371878-2-robimarko@gmail.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- drivers/firmware/qcom_scm.c | 30 ++++++++++++++++++++++++++++++
- drivers/firmware/qcom_scm.h | 1 +
- 2 files changed, 31 insertions(+)
-
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -407,6 +407,29 @@ int qcom_scm_set_remote_state(u32 state,
- }
- EXPORT_SYMBOL(qcom_scm_set_remote_state);
-
-+static int qcom_scm_disable_sdi(void)
-+{
-+ int ret;
-+ struct qcom_scm_desc desc = {
-+ .svc = QCOM_SCM_SVC_BOOT,
-+ .cmd = QCOM_SCM_BOOT_SDI_CONFIG,
-+ .args[0] = 1, /* Disable watchdog debug */
-+ .args[1] = 0, /* Disable SDI */
-+ .arginfo = QCOM_SCM_ARGS(2),
-+ .owner = ARM_SMCCC_OWNER_SIP,
-+ };
-+ struct qcom_scm_res res;
-+
-+ ret = qcom_scm_clk_enable();
-+ if (ret)
-+ return ret;
-+ ret = qcom_scm_call(__scm->dev, &desc, &res);
-+
-+ qcom_scm_clk_disable();
-+
-+ return ret ? : res.result[0];
-+}
-+
- static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
- {
- struct qcom_scm_desc desc = {
-@@ -1411,6 +1434,13 @@ static int qcom_scm_probe(struct platfor
-
- __get_convention();
-
-+
-+ /*
-+ * Disable SDI if indicated by DT that it is enabled by default.
-+ */
-+ if (of_property_read_bool(pdev->dev.of_node, "qcom,sdi-enabled"))
-+ qcom_scm_disable_sdi();
-+
- /*
- * If requested enable "download mode", from this point on warmboot
- * will cause the boot stages to enter download mode, unless
---- a/drivers/firmware/qcom_scm.h
-+++ b/drivers/firmware/qcom_scm.h
-@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device
- #define QCOM_SCM_SVC_BOOT 0x01
- #define QCOM_SCM_BOOT_SET_ADDR 0x01
- #define QCOM_SCM_BOOT_TERMINATE_PC 0x02
-+#define QCOM_SCM_BOOT_SDI_CONFIG 0x09
- #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
- #define QCOM_SCM_BOOT_SET_ADDR_MC 0x11
- #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
+++ /dev/null
-From ea9fba16d972becc84cd2a82d25030975dc609a5 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 30 Sep 2023 13:09:27 +0200
-Subject: [PATCH] ARM: dts: qcom: ipq4019: add label to SCM
-
-Some IPQ4019 boards require SDI to be disabled by adding a property to the
-SCM node, so lets make that easy by adding a label to the SCM node.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -155,7 +155,7 @@
- };
-
- firmware {
-- scm {
-+ scm: scm {
- compatible = "qcom,scm-ipq4019", "qcom,scm";
- };
- };
+++ /dev/null
-From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@googlemail.com>
-Date: Sun, 11 Mar 2018 14:41:31 +0100
-Subject: [PATCH 2/2] clk: fix apss cpu overclocking
-
-There's an interaction issue between the clk changes:"
-clk: qcom: ipq4019: Add the apss cpu pll divider clock node
-clk: qcom: ipq4019: remove fixed clocks and add pll clocks
-" and the cpufreq-dt.
-
-cpufreq-dt is now spamming the kernel-log with the following:
-
-[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
-for freq 761142857 (-34)
-
-This only happens on certain devices like the Compex WPJ428
-and AVM FritzBox!4040. However, other devices like the Asus
-RT-AC58U and Meraki MR33 work just fine.
-
-The issue stem from the fact that all higher CPU-Clocks
-are achieved by switching the clock-parent to the P_DDRPLLAPSS
-(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
-as part of the DDR calibration.
-
-For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
-at round 533 MHz (ddrpllsdcc = 190285714 Hz).
-
-whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
-clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
-
-This patch attempts to fix the issue by modifying
-clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
-to use a new qcom_find_freq_close() function, which returns the closest
-matching frequency, instead of the next higher. This way, the SoC in
-the FB4040 (with its max clock speed of 710.4 MHz) will no longer
-try to overclock to 761 MHz.
-
-Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
-Signed-off-by: John Crispin <john@phrozen.org>
----
- drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
- 1 file changed, 31 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq4019.c
-+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
- .reg = 0x2f020,
- };
-
-+
-+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
-+ unsigned long rate)
-+{
-+ const struct freq_tbl *last = NULL;
-+
-+ for ( ; f->freq; f++) {
-+ if (rate == f->freq)
-+ return f;
-+
-+ if (f->freq > rate) {
-+ if (!last ||
-+ (f->freq - rate) < (rate - last->freq))
-+ return f;
-+ else
-+ return last;
-+ }
-+ last = f;
-+ }
-+
-+ return last;
-+}
-+
- /*
- * Round rate function for APSS CPU PLL Clock divider.
- * It looks up the frequency table and returns the next higher frequency
-@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
- struct clk_hw *p_hw;
- const struct freq_tbl *f;
-
-- f = qcom_find_freq(pll->freq_tbl, rate);
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
- if (!f)
- return -EINVAL;
-
-@@ -1277,7 +1300,7 @@ static int clk_cpu_div_set_rate(struct c
- const struct freq_tbl *f;
- u32 mask;
-
-- f = qcom_find_freq(pll->freq_tbl, rate);
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
- if (!f)
- return -EINVAL;
-
-@@ -1304,6 +1327,7 @@ static unsigned long
- clk_cpu_div_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
- {
-+ const struct freq_tbl *f;
- struct clk_fepll *pll = to_clk_fepll(hw);
- u32 cdiv, pre_div;
- u64 rate;
-@@ -1324,7 +1348,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
- rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
- do_div(rate, pre_div);
-
-- return rate;
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
-+ if (!f)
-+ return rate;
-+
-+ return f->freq;
- };
-
- static const struct clk_ops clk_regmap_cpu_div_ops = {
+++ /dev/null
-From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 30 Oct 2020 13:36:31 +0100
-Subject: [PATCH] arm: compressed: add appended DTB section
-
-This adds a appended_dtb section to the ARM decompressor
-linker script.
-
-This allows using the existing ARM zImage appended DTB support for
-appending a DTB to the raw ELF kernel.
-
-Its size is set to 1MB max to match the zImage appended DTB size limit.
-
-To use it to pass the DTB to the kernel, objcopy is used:
-
-objcopy --set-section-flags=.appended_dtb=alloc,contents \
- --update-section=.appended_dtb=<target>.dtb vmlinux
-
-This is based off the following patch:
-https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/compressed/vmlinux.lds.S
-+++ b/arch/arm/boot/compressed/vmlinux.lds.S
-@@ -103,6 +103,13 @@ SECTIONS
-
- _edata = .;
-
-+ .appended_dtb : {
-+ /* leave space for appended DTB */
-+ . += 0x100000;
-+ }
-+
-+ _edata_dtb = .;
-+
- /*
- * The image_end section appears after any additional loadable sections
- * that the linker may decide to insert in the binary image. Having
-@@ -140,4 +147,4 @@ SECTIONS
-
- ARM_ASSERTS
- }
--ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
-+ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");
+++ /dev/null
-From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
-From: John Thomson <git@johnthomson.fastmail.com.au>
-Date: Fri, 23 Oct 2020 19:42:36 +1000
-Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
-
-For IPQ40XX systems where the SoC watchdog is activated before linux,
-the watchdog timer may be too small for linux to finish uncompress,
-boot, and watchdog management start.
-If the watchdog is enabled, set the timeout for it to 30 seconds.
-The functionality and offsets were copied from:
-drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
-The watchdog memory address was taken from:
-arch/arm/boot/dts/qcom-ipq4019.dtsi
-
-This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
-RouterBoot bootloader.
-
-Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
----
- arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/arch/arm/boot/compressed/head.S
-+++ b/arch/arm/boot/compressed/head.S
-@@ -620,6 +620,41 @@ not_relocated: mov r0, #0
- bic r4, r4, #1
- blne cache_on
-
-+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
-+ * if it is enabled, so that there is time for kernel
-+ * to decompress, boot, and take over the watchdog.
-+ * data and functionality from drivers/watchdog/qcom-wdt.c
-+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
-+ */
-+#ifdef CONFIG_ARCH_IPQ40XX
-+watchdog_set:
-+ /* offsets:
-+ * 0x04 reset (=1 resets countdown)
-+ * 0x08 enable (=0 disables)
-+ * 0x0c status (=1 when SoC was reset by watchdog)
-+ * 0x10 bark (=timeout warning in ticks)
-+ * 0x14 bite (=timeout reset in ticks)
-+ * clock rate is 1<<15 hertz
-+ */
-+ .equ watchdog, 0x0b017000 @Store watchdog base address
-+ movw r0, #:lower16:watchdog
-+ movt r0, #:upper16:watchdog
-+ ldr r1, [r0, #0x08] @Get enabled?
-+ cmp r1, #1 @If not enabled, do not change
-+ bne watchdog_finished
-+ mov r1, #0
-+ str r1, [r0, #0x08] @Disable the watchdog
-+ mov r1, #1
-+ str r1, [r0, #0x04] @Pet the watchdog
-+ mov r1, #30 @30 seconds timeout
-+ lsl r1, r1, #15 @converted to ticks
-+ str r1, [r0, #0x10] @Set the bark timeout
-+ str r1, [r0, #0x14] @Set the bite timeout
-+ mov r1, #1
-+ str r1, [r0, #0x08] @Enable the watchdog
-+watchdog_finished:
-+#endif /* CONFIG_ARCH_IPQ40XX */
-+
- /*
- * The C runtime environment should now be setup sufficiently.
- * Set up some pointers, and start decompressing.
+++ /dev/null
-From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 14 Dec 2020 13:35:35 +0100
-Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock
-
-When using sdhci_msm_set_clock clock setting will fail, so lets
-use the generic sdhci_set_clock.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/mmc/host/sdhci-msm.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mmc/host/sdhci-msm.c
-+++ b/drivers/mmc/host/sdhci-msm.c
-@@ -2451,7 +2451,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
-
- static const struct sdhci_ops sdhci_msm_ops = {
- .reset = sdhci_msm_reset,
-- .set_clock = sdhci_msm_set_clock,
-+ .set_clock = sdhci_set_clock,
- .get_min_clock = sdhci_msm_get_min_clock,
- .get_max_clock = sdhci_msm_get_max_clock,
- .set_bus_width = sdhci_set_bus_width,
+++ /dev/null
-From 28edd829133766eb3cefaf2e49d3ee701968061b Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 9 May 2023 01:57:17 +0200
-Subject: [PATCH] mmc: sdhci-msm: comment unused sdhci_msm_set_clock
-
-comment unused sdhci_msm_set_clock and __sdhci_msm_set_clock as due to some
-current problem, we are forced to use sdhci_set_clock.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/mmc/host/sdhci-msm.c | 86 ++++++++++++++++++------------------
- 1 file changed, 43 insertions(+), 43 deletions(-)
-
---- a/drivers/mmc/host/sdhci-msm.c
-+++ b/drivers/mmc/host/sdhci-msm.c
-@@ -1751,49 +1751,49 @@ static unsigned int sdhci_msm_get_min_cl
- return SDHCI_MSM_MIN_CLOCK;
- }
-
--/*
-- * __sdhci_msm_set_clock - sdhci_msm clock control.
-- *
-- * Description:
-- * MSM controller does not use internal divider and
-- * instead directly control the GCC clock as per
-- * HW recommendation.
-- **/
--static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
--{
-- u16 clk;
--
-- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
--
-- if (clock == 0)
-- return;
--
-- /*
-- * MSM controller do not use clock divider.
-- * Thus read SDHCI_CLOCK_CONTROL and only enable
-- * clock with no divider value programmed.
-- */
-- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
-- sdhci_enable_clk(host, clk);
--}
--
--/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
--static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
--{
-- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-- struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
--
-- if (!clock) {
-- host->mmc->actual_clock = msm_host->clk_rate = 0;
-- goto out;
-- }
--
-- sdhci_msm_hc_select_mode(host);
--
-- msm_set_clock_rate_for_bus_mode(host, clock);
--out:
-- __sdhci_msm_set_clock(host, clock);
--}
-+// /*
-+// * __sdhci_msm_set_clock - sdhci_msm clock control.
-+// *
-+// * Description:
-+// * MSM controller does not use internal divider and
-+// * instead directly control the GCC clock as per
-+// * HW recommendation.
-+// **/
-+// static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
-+// {
-+// u16 clk;
-+
-+// sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
-+
-+// if (clock == 0)
-+// return;
-+
-+// /*
-+// * MSM controller do not use clock divider.
-+// * Thus read SDHCI_CLOCK_CONTROL and only enable
-+// * clock with no divider value programmed.
-+// */
-+// clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
-+// sdhci_enable_clk(host, clk);
-+// }
-+
-+// /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
-+// static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
-+// {
-+// struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-+// struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
-+
-+// if (!clock) {
-+// host->mmc->actual_clock = msm_host->clk_rate = 0;
-+// goto out;
-+// }
-+
-+// sdhci_msm_hc_select_mode(host);
-+
-+// msm_set_clock_rate_for_bus_mode(host, clock);
-+// out:
-+// __sdhci_msm_set_clock(host, clock);
-+// }
-
- /*****************************************************************************\
- * *
+++ /dev/null
-From aaa675f07e781e248fcf169ce9a917b48bc2cc9b Mon Sep 17 00:00:00 2001
-From: Brian Norris <computersforpeace@gmail.com>
-Date: Fri, 28 Jul 2023 12:06:23 +0200
-Subject: [PATCH 3/3] firmware: qcom: scm: fix SCM cold boot address
-
-This effectively reverts upstream Linux commit 13e77747800e ("firmware:
-qcom: scm: Use atomic SCM for cold boot"), because Google WiFi boot
-firmwares don't support the atomic variant.
-
-This fixes SMP support for Google WiFi.
-
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/firmware/qcom_scm-legacy.c | 62 +++++++++++++++++++++++++-----
- drivers/firmware/qcom_scm.c | 11 ++++++
- 2 files changed, 63 insertions(+), 10 deletions(-)
-
---- a/drivers/firmware/qcom_scm-legacy.c
-+++ b/drivers/firmware/qcom_scm-legacy.c
-@@ -13,6 +13,9 @@
- #include <linux/arm-smccc.h>
- #include <linux/dma-mapping.h>
-
-+#include <asm/cacheflush.h>
-+#include <asm/outercache.h>
-+
- #include "qcom_scm.h"
-
- static DEFINE_MUTEX(qcom_scm_lock);
-@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct
- } while (res->a0 == QCOM_SCM_INTERRUPTED);
- }
-
-+static void qcom_scm_inv_range(unsigned long start, unsigned long end)
-+{
-+ u32 cacheline_size, ctr;
-+
-+ asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
-+ cacheline_size = 4 << ((ctr >> 16) & 0xf);
-+
-+ start = round_down(start, cacheline_size);
-+ end = round_up(end, cacheline_size);
-+ outer_inv_range(start, end);
-+ while (start < end) {
-+ asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
-+ : "memory");
-+ start += cacheline_size;
-+ }
-+ dsb();
-+ isb();
-+}
-+
- /**
- * scm_legacy_call() - Sends a command to the SCM and waits for the command to
- * finish processing.
-@@ -163,10 +185,16 @@ int scm_legacy_call(struct device *dev,
-
- rsp = scm_legacy_command_to_response(cmd);
-
-- cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
-- if (dma_mapping_error(dev, cmd_phys)) {
-- kfree(cmd);
-- return -ENOMEM;
-+ if (dev) {
-+ cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
-+ if (dma_mapping_error(dev, cmd_phys)) {
-+ kfree(cmd);
-+ return -ENOMEM;
-+ }
-+ } else {
-+ cmd_phys = virt_to_phys(cmd);
-+ __cpuc_flush_dcache_area(cmd, alloc_len);
-+ outer_flush_range(cmd_phys, cmd_phys + alloc_len);
- }
-
- smc.args[0] = 1;
-@@ -182,13 +210,26 @@ int scm_legacy_call(struct device *dev,
- goto out;
-
- do {
-- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
-- sizeof(*rsp), DMA_FROM_DEVICE);
-+ if (dev) {
-+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +
-+ cmd_len, sizeof(*rsp),
-+ DMA_FROM_DEVICE);
-+ } else {
-+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) +
-+ cmd_len;
-+ qcom_scm_inv_range(start, start + sizeof(*rsp));
-+ }
- } while (!rsp->is_complete);
-
-- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
-- le32_to_cpu(rsp->buf_offset),
-- resp_len, DMA_FROM_DEVICE);
-+ if (dev) {
-+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
-+ le32_to_cpu(rsp->buf_offset),
-+ resp_len, DMA_FROM_DEVICE);
-+ } else {
-+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +
-+ le32_to_cpu(rsp->buf_offset);
-+ qcom_scm_inv_range(start, start + resp_len);
-+ }
-
- if (res) {
- res_buf = scm_legacy_get_response_buffer(rsp);
-@@ -196,7 +237,8 @@ int scm_legacy_call(struct device *dev,
- res->result[i] = le32_to_cpu(res_buf[i]);
- }
- out:
-- dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
-+ if (dev)
-+ dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
- kfree(cmd);
- return ret;
- }
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -312,6 +312,17 @@ static int qcom_scm_set_boot_addr(void *
- desc.args[0] = flags;
- desc.args[1] = virt_to_phys(entry);
-
-+ /*
-+ * Factory firmware doesn't support the atomic variant. Non-atomic SCMs
-+ * require ugly DMA invalidation support that was dropped upstream a
-+ * while ago. For more info, see:
-+ *
-+ * [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?
-+ * https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/
-+ */
-+ if (of_machine_is_compatible("google,wifi"))
-+ return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);
-+
- return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
- }
-
+++ /dev/null
-From 35ca7e3e6ccd120d694a3425f37fc6374ad2e11e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Andreas=20B=C3=B6hler?= <dev@aboehler.at>
-Date: Wed, 20 Apr 2022 12:08:38 +0200
-Subject: [PATCH] mtd: rawnand: add support for Toshiba TC58NVG0S3HTA00
- NAND flash
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Toshiba TC58NVG0S3HTA00 is detected with 64 byte OOB while the flash
-has 128 bytes OOB. This adds a static NAND ID entry to correct this.
-
-Tested on FRITZ!Box 7530 flashed with OpenWrt.
-
-Signed-off-by: Andreas Böhler <dev@aboehler.at>
-(changed id_len to 8, added comment about possible counterfeits)
----
---- a/drivers/mtd/nand/raw/nand_ids.c
-+++ b/drivers/mtd/nand/raw/nand_ids.c
-@@ -29,6 +29,9 @@ struct nand_flash_dev nand_flash_ids[] =
- {"TC58NVG0S3E 1G 3.3V 8-bit",
- { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
- SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
-+ {"TC58NVG0S3HTA00 1G 3.3V 8-bit", /* possibly counterfeit chip - see commit */
-+ { .id = {0x98, 0xf1, 0x80, 0x15} }, /* should be more bytes */
-+ SZ_2K, SZ_128, SZ_128K, 0, 8, 128, NAND_ECC_INFO(8, SZ_512), },
- {"TC58NVG2S0F 4G 3.3V 8-bit",
- { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
- SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
+++ /dev/null
-From 76e25c1f46456416ba5358be8a0677f1ab8196b6 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:48 +0100
-Subject: [PATCH] net: ipqess: introduce the Qualcomm IPQESS driver
-
-The Qualcomm IPQESS controller is a simple 1G Ethernet controller found
-on the IPQ4019 chip. This controller has some specificities, in that the
-IPQ4019 platform that includes that controller also has an internal
-switch, based on the QCA8K IP.
-
-It is connected to that switch through an internal link, and doesn't
-expose directly any external interface, hence it only supports the
-PHY_INTERFACE_MODE_INTERNAL for now.
-
-It has 16 RX and TX queues, with a very basic RSS fanout configured at
-init time.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
----
- MAINTAINERS | 7 +
- drivers/net/ethernet/qualcomm/Kconfig | 11 +
- drivers/net/ethernet/qualcomm/Makefile | 2 +
- drivers/net/ethernet/qualcomm/ipqess/Makefile | 8 +
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 1246 +++++++++++++++++
- drivers/net/ethernet/qualcomm/ipqess/ipqess.h | 518 +++++++
- .../ethernet/qualcomm/ipqess/ipqess_ethtool.c | 164 +++
- 7 files changed, 1956 insertions(+)
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/Makefile
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/ipqess.c
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/ipqess.h
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/ipqess_ethtool.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -17075,6 +17075,13 @@ L: netdev@vger.kernel.org
- S: Maintained
- F: drivers/net/ethernet/qualcomm/emac/
-
-+QUALCOMM IPQESS ETHERNET DRIVER
-+M: Maxime Chevallier <maxime.chevallier@bootlin.com>
-+L: netdev@vger.kernel.org
-+S: Maintained
-+F: Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml
-+F: drivers/net/ethernet/qualcomm/ipqess/
-+
- QUALCOMM ETHQOS ETHERNET DRIVER
- M: Vinod Koul <vkoul@kernel.org>
- R: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---- a/drivers/net/ethernet/qualcomm/Kconfig
-+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -60,6 +60,17 @@ config QCOM_EMAC
- low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
- Precision Clock Synchronization Protocol.
-
-+config QCOM_IPQ4019_ESS_EDMA
-+ tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
-+ depends on (OF && ARCH_QCOM) || COMPILE_TEST
-+ select PHYLINK
-+ help
-+ This driver supports the Qualcomm Atheros IPQ40xx built-in
-+ ESS EDMA ethernet controller.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called ipqess.
-+
- source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
-
- endif # NET_VENDOR_QUALCOMM
---- a/drivers/net/ethernet/qualcomm/Makefile
-+++ b/drivers/net/ethernet/qualcomm/Makefile
-@@ -11,4 +11,6 @@ qcauart-objs := qca_uart.o
-
- obj-y += emac/
-
-+obj-$(CONFIG_QCOM_IPQ4019_ESS_EDMA) += ipqess/
-+
- obj-$(CONFIG_RMNET) += rmnet/
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/Makefile
-@@ -0,0 +1,8 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+#
-+# Makefile for the IPQ ESS driver
-+#
-+
-+obj-$(CONFIG_QCOM_IPQ4019_ESS_EDMA) += ipq_ess.o
-+
-+ipq_ess-objs := ipqess.o ipqess_ethtool.o
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -0,0 +1,1246 @@
-+// SPDX-License-Identifier: GPL-2.0 OR ISC
-+/* Copyright (c) 2014 - 2017, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
-+ * Copyright (c) 2018 - 2019, Christian Lamparter <chunkeey@gmail.com>
-+ * Copyright (c) 2020 - 2021, Gabor Juhos <j4g8y7@gmail.com>
-+ * Copyright (c) 2021 - 2022, Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ *
-+ */
-+
-+#include <linux/bitfield.h>
-+#include <linux/clk.h>
-+#include <linux/if_vlan.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_mdio.h>
-+#include <linux/of_net.h>
-+#include <linux/phylink.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset.h>
-+#include <linux/skbuff.h>
-+#include <linux/vmalloc.h>
-+#include <net/checksum.h>
-+#include <net/ip6_checksum.h>
-+
-+#include "ipqess.h"
-+
-+#define IPQESS_RRD_SIZE 16
-+#define IPQESS_NEXT_IDX(X, Y) (((X) + 1) & ((Y) - 1))
-+#define IPQESS_TX_DMA_BUF_LEN 0x3fff
-+
-+static void ipqess_w32(struct ipqess *ess, u32 reg, u32 val)
-+{
-+ writel(val, ess->hw_addr + reg);
-+}
-+
-+static u32 ipqess_r32(struct ipqess *ess, u16 reg)
-+{
-+ return readl(ess->hw_addr + reg);
-+}
-+
-+static void ipqess_m32(struct ipqess *ess, u32 mask, u32 val, u16 reg)
-+{
-+ u32 _val = ipqess_r32(ess, reg);
-+
-+ _val &= ~mask;
-+ _val |= val;
-+
-+ ipqess_w32(ess, reg, _val);
-+}
-+
-+void ipqess_update_hw_stats(struct ipqess *ess)
-+{
-+ u32 *p;
-+ u32 stat;
-+ int i;
-+
-+ lockdep_assert_held(&ess->stats_lock);
-+
-+ p = (u32 *)&ess->ipqess_stats;
-+ for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) {
-+ stat = ipqess_r32(ess, IPQESS_REG_TX_STAT_PKT_Q(i));
-+ *p += stat;
-+ p++;
-+ }
-+
-+ for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) {
-+ stat = ipqess_r32(ess, IPQESS_REG_TX_STAT_BYTE_Q(i));
-+ *p += stat;
-+ p++;
-+ }
-+
-+ for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) {
-+ stat = ipqess_r32(ess, IPQESS_REG_RX_STAT_PKT_Q(i));
-+ *p += stat;
-+ p++;
-+ }
-+
-+ for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) {
-+ stat = ipqess_r32(ess, IPQESS_REG_RX_STAT_BYTE_Q(i));
-+ *p += stat;
-+ p++;
-+ }
-+}
-+
-+static int ipqess_tx_ring_alloc(struct ipqess *ess)
-+{
-+ struct device *dev = &ess->pdev->dev;
-+ int i;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ struct ipqess_tx_ring *tx_ring = &ess->tx_ring[i];
-+ size_t size;
-+ u32 idx;
-+
-+ tx_ring->ess = ess;
-+ tx_ring->ring_id = i;
-+ tx_ring->idx = i * 4;
-+ tx_ring->count = IPQESS_TX_RING_SIZE;
-+ tx_ring->nq = netdev_get_tx_queue(ess->netdev, i);
-+
-+ size = sizeof(struct ipqess_buf) * IPQESS_TX_RING_SIZE;
-+ tx_ring->buf = devm_kzalloc(dev, size, GFP_KERNEL);
-+ if (!tx_ring->buf)
-+ return -ENOMEM;
-+
-+ size = sizeof(struct ipqess_tx_desc) * IPQESS_TX_RING_SIZE;
-+ tx_ring->hw_desc = dmam_alloc_coherent(dev, size, &tx_ring->dma,
-+ GFP_KERNEL);
-+ if (!tx_ring->hw_desc)
-+ return -ENOMEM;
-+
-+ ipqess_w32(ess, IPQESS_REG_TPD_BASE_ADDR_Q(tx_ring->idx),
-+ (u32)tx_ring->dma);
-+
-+ idx = ipqess_r32(ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx));
-+ idx >>= IPQESS_TPD_CONS_IDX_SHIFT; /* need u32 here */
-+ idx &= 0xffff;
-+ tx_ring->head = idx;
-+ tx_ring->tail = idx;
-+
-+ ipqess_m32(ess, IPQESS_TPD_PROD_IDX_MASK << IPQESS_TPD_PROD_IDX_SHIFT,
-+ idx, IPQESS_REG_TPD_IDX_Q(tx_ring->idx));
-+ ipqess_w32(ess, IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx), idx);
-+ ipqess_w32(ess, IPQESS_REG_TPD_RING_SIZE, IPQESS_TX_RING_SIZE);
-+ }
-+
-+ return 0;
-+}
-+
-+static int ipqess_tx_unmap_and_free(struct device *dev, struct ipqess_buf *buf)
-+{
-+ int len = 0;
-+
-+ if (buf->flags & IPQESS_DESC_SINGLE)
-+ dma_unmap_single(dev, buf->dma, buf->length, DMA_TO_DEVICE);
-+ else if (buf->flags & IPQESS_DESC_PAGE)
-+ dma_unmap_page(dev, buf->dma, buf->length, DMA_TO_DEVICE);
-+
-+ if (buf->flags & IPQESS_DESC_LAST) {
-+ len = buf->skb->len;
-+ dev_kfree_skb_any(buf->skb);
-+ }
-+
-+ buf->flags = 0;
-+
-+ return len;
-+}
-+
-+static void ipqess_tx_ring_free(struct ipqess *ess)
-+{
-+ int i;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ int j;
-+
-+ if (ess->tx_ring[i].hw_desc)
-+ continue;
-+
-+ for (j = 0; j < IPQESS_TX_RING_SIZE; j++) {
-+ struct ipqess_buf *buf = &ess->tx_ring[i].buf[j];
-+
-+ ipqess_tx_unmap_and_free(&ess->pdev->dev, buf);
-+ }
-+
-+ ess->tx_ring[i].buf = NULL;
-+ }
-+}
-+
-+static int ipqess_rx_buf_prepare(struct ipqess_buf *buf,
-+ struct ipqess_rx_ring *rx_ring)
-+{
-+ memset(buf->skb->data, 0, sizeof(struct ipqess_rx_desc));
-+
-+ buf->dma = dma_map_single(rx_ring->ppdev, buf->skb->data,
-+ IPQESS_RX_HEAD_BUFF_SIZE, DMA_FROM_DEVICE);
-+ if (dma_mapping_error(rx_ring->ppdev, buf->dma)) {
-+ dev_kfree_skb_any(buf->skb);
-+ buf->skb = NULL;
-+ return -EFAULT;
-+ }
-+
-+ buf->length = IPQESS_RX_HEAD_BUFF_SIZE;
-+ rx_ring->hw_desc[rx_ring->head] = (struct ipqess_rx_desc *)buf->dma;
-+ rx_ring->head = (rx_ring->head + 1) % IPQESS_RX_RING_SIZE;
-+
-+ ipqess_m32(rx_ring->ess, IPQESS_RFD_PROD_IDX_BITS,
-+ (rx_ring->head + IPQESS_RX_RING_SIZE - 1) % IPQESS_RX_RING_SIZE,
-+ IPQESS_REG_RFD_IDX_Q(rx_ring->idx));
-+
-+ return 0;
-+}
-+
-+/* locking is handled by the caller */
-+static int ipqess_rx_buf_alloc_napi(struct ipqess_rx_ring *rx_ring)
-+{
-+ struct ipqess_buf *buf = &rx_ring->buf[rx_ring->head];
-+
-+ buf->skb = napi_alloc_skb(&rx_ring->napi_rx, IPQESS_RX_HEAD_BUFF_SIZE);
-+ if (!buf->skb)
-+ return -ENOMEM;
-+
-+ return ipqess_rx_buf_prepare(buf, rx_ring);
-+}
-+
-+static int ipqess_rx_buf_alloc(struct ipqess_rx_ring *rx_ring)
-+{
-+ struct ipqess_buf *buf = &rx_ring->buf[rx_ring->head];
-+
-+ buf->skb = netdev_alloc_skb_ip_align(rx_ring->ess->netdev,
-+ IPQESS_RX_HEAD_BUFF_SIZE);
-+
-+ if (!buf->skb)
-+ return -ENOMEM;
-+
-+ return ipqess_rx_buf_prepare(buf, rx_ring);
-+}
-+
-+static void ipqess_refill_work(struct work_struct *work)
-+{
-+ struct ipqess_rx_ring_refill *rx_refill = container_of(work,
-+ struct ipqess_rx_ring_refill, refill_work);
-+ struct ipqess_rx_ring *rx_ring = rx_refill->rx_ring;
-+ int refill = 0;
-+
-+ /* don't let this loop by accident. */
-+ while (atomic_dec_and_test(&rx_ring->refill_count)) {
-+ napi_disable(&rx_ring->napi_rx);
-+ if (ipqess_rx_buf_alloc(rx_ring)) {
-+ refill++;
-+ dev_dbg(rx_ring->ppdev,
-+ "Not all buffers were reallocated");
-+ }
-+ napi_enable(&rx_ring->napi_rx);
-+ }
-+
-+ if (atomic_add_return(refill, &rx_ring->refill_count))
-+ schedule_work(&rx_refill->refill_work);
-+}
-+
-+static int ipqess_rx_ring_alloc(struct ipqess *ess)
-+{
-+ int i;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ int j;
-+
-+ ess->rx_ring[i].ess = ess;
-+ ess->rx_ring[i].ppdev = &ess->pdev->dev;
-+ ess->rx_ring[i].ring_id = i;
-+ ess->rx_ring[i].idx = i * 2;
-+
-+ ess->rx_ring[i].buf = devm_kzalloc(&ess->pdev->dev,
-+ sizeof(struct ipqess_buf) * IPQESS_RX_RING_SIZE,
-+ GFP_KERNEL);
-+
-+ if (!ess->rx_ring[i].buf)
-+ return -ENOMEM;
-+
-+ ess->rx_ring[i].hw_desc =
-+ dmam_alloc_coherent(&ess->pdev->dev,
-+ sizeof(struct ipqess_rx_desc) * IPQESS_RX_RING_SIZE,
-+ &ess->rx_ring[i].dma, GFP_KERNEL);
-+
-+ if (!ess->rx_ring[i].hw_desc)
-+ return -ENOMEM;
-+
-+ for (j = 0; j < IPQESS_RX_RING_SIZE; j++)
-+ if (ipqess_rx_buf_alloc(&ess->rx_ring[i]) < 0)
-+ return -ENOMEM;
-+
-+ ess->rx_refill[i].rx_ring = &ess->rx_ring[i];
-+ INIT_WORK(&ess->rx_refill[i].refill_work, ipqess_refill_work);
-+
-+ ipqess_w32(ess, IPQESS_REG_RFD_BASE_ADDR_Q(ess->rx_ring[i].idx),
-+ (u32)(ess->rx_ring[i].dma));
-+ }
-+
-+ ipqess_w32(ess, IPQESS_REG_RX_DESC0,
-+ (IPQESS_RX_HEAD_BUFF_SIZE << IPQESS_RX_BUF_SIZE_SHIFT) |
-+ (IPQESS_RX_RING_SIZE << IPQESS_RFD_RING_SIZE_SHIFT));
-+
-+ return 0;
-+}
-+
-+static void ipqess_rx_ring_free(struct ipqess *ess)
-+{
-+ int i;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ int j;
-+
-+ cancel_work_sync(&ess->rx_refill[i].refill_work);
-+ atomic_set(&ess->rx_ring[i].refill_count, 0);
-+
-+ for (j = 0; j < IPQESS_RX_RING_SIZE; j++) {
-+ dma_unmap_single(&ess->pdev->dev,
-+ ess->rx_ring[i].buf[j].dma,
-+ ess->rx_ring[i].buf[j].length,
-+ DMA_FROM_DEVICE);
-+ dev_kfree_skb_any(ess->rx_ring[i].buf[j].skb);
-+ }
-+ }
-+}
-+
-+static struct net_device_stats *ipqess_get_stats(struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ spin_lock(&ess->stats_lock);
-+ ipqess_update_hw_stats(ess);
-+ spin_unlock(&ess->stats_lock);
-+
-+ return &ess->stats;
-+}
-+
-+static int ipqess_rx_poll(struct ipqess_rx_ring *rx_ring, int budget)
-+{
-+ u32 length = 0, num_desc, tail, rx_ring_tail;
-+ int done = 0;
-+
-+ rx_ring_tail = rx_ring->tail;
-+
-+ tail = ipqess_r32(rx_ring->ess, IPQESS_REG_RFD_IDX_Q(rx_ring->idx));
-+ tail >>= IPQESS_RFD_CONS_IDX_SHIFT;
-+ tail &= IPQESS_RFD_CONS_IDX_MASK;
-+
-+ while (done < budget) {
-+ struct ipqess_rx_desc *rd;
-+ struct sk_buff *skb;
-+
-+ if (rx_ring_tail == tail)
-+ break;
-+
-+ dma_unmap_single(rx_ring->ppdev,
-+ rx_ring->buf[rx_ring_tail].dma,
-+ rx_ring->buf[rx_ring_tail].length,
-+ DMA_FROM_DEVICE);
-+
-+ skb = xchg(&rx_ring->buf[rx_ring_tail].skb, NULL);
-+ rd = (struct ipqess_rx_desc *)skb->data;
-+ rx_ring_tail = IPQESS_NEXT_IDX(rx_ring_tail, IPQESS_RX_RING_SIZE);
-+
-+ /* Check if RRD is valid */
-+ if (!(rd->rrd7 & cpu_to_le16(IPQESS_RRD_DESC_VALID))) {
-+ num_desc = 1;
-+ dev_kfree_skb_any(skb);
-+ goto skip;
-+ }
-+
-+ num_desc = le16_to_cpu(rd->rrd1) & IPQESS_RRD_NUM_RFD_MASK;
-+ length = le16_to_cpu(rd->rrd6) & IPQESS_RRD_PKT_SIZE_MASK;
-+
-+ skb_reserve(skb, IPQESS_RRD_SIZE);
-+ if (num_desc > 1) {
-+ struct sk_buff *skb_prev = NULL;
-+ int size_remaining;
-+ int i;
-+
-+ skb->data_len = 0;
-+ skb->tail += (IPQESS_RX_HEAD_BUFF_SIZE - IPQESS_RRD_SIZE);
-+ skb->len = length;
-+ skb->truesize = length;
-+ size_remaining = length - (IPQESS_RX_HEAD_BUFF_SIZE - IPQESS_RRD_SIZE);
-+
-+ for (i = 1; i < num_desc; i++) {
-+ struct sk_buff *skb_temp = rx_ring->buf[rx_ring_tail].skb;
-+
-+ dma_unmap_single(rx_ring->ppdev,
-+ rx_ring->buf[rx_ring_tail].dma,
-+ rx_ring->buf[rx_ring_tail].length,
-+ DMA_FROM_DEVICE);
-+
-+ skb_put(skb_temp, min(size_remaining, IPQESS_RX_HEAD_BUFF_SIZE));
-+ if (skb_prev)
-+ skb_prev->next = rx_ring->buf[rx_ring_tail].skb;
-+ else
-+ skb_shinfo(skb)->frag_list = rx_ring->buf[rx_ring_tail].skb;
-+ skb_prev = rx_ring->buf[rx_ring_tail].skb;
-+ rx_ring->buf[rx_ring_tail].skb->next = NULL;
-+
-+ skb->data_len += rx_ring->buf[rx_ring_tail].skb->len;
-+ size_remaining -= rx_ring->buf[rx_ring_tail].skb->len;
-+
-+ rx_ring_tail = IPQESS_NEXT_IDX(rx_ring_tail, IPQESS_RX_RING_SIZE);
-+ }
-+
-+ } else {
-+ skb_put(skb, length);
-+ }
-+
-+ skb->dev = rx_ring->ess->netdev;
-+ skb->protocol = eth_type_trans(skb, rx_ring->ess->netdev);
-+ skb_record_rx_queue(skb, rx_ring->ring_id);
-+
-+ if (rd->rrd6 & cpu_to_le16(IPQESS_RRD_CSUM_FAIL_MASK))
-+ skb_checksum_none_assert(skb);
-+ else
-+ skb->ip_summed = CHECKSUM_UNNECESSARY;
-+
-+ if (rd->rrd7 & cpu_to_le16(IPQESS_RRD_CVLAN))
-+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
-+ le16_to_cpu(rd->rrd4));
-+ else if (rd->rrd1 & cpu_to_le16(IPQESS_RRD_SVLAN))
-+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
-+ le16_to_cpu(rd->rrd4));
-+
-+ napi_gro_receive(&rx_ring->napi_rx, skb);
-+
-+ rx_ring->ess->stats.rx_packets++;
-+ rx_ring->ess->stats.rx_bytes += length;
-+
-+ done++;
-+skip:
-+
-+ num_desc += atomic_xchg(&rx_ring->refill_count, 0);
-+ while (num_desc) {
-+ if (ipqess_rx_buf_alloc_napi(rx_ring)) {
-+ num_desc = atomic_add_return(num_desc,
-+ &rx_ring->refill_count);
-+ if (num_desc >= DIV_ROUND_UP(IPQESS_RX_RING_SIZE * 4, 7))
-+ schedule_work(&rx_ring->ess->rx_refill[rx_ring->ring_id].refill_work);
-+ break;
-+ }
-+ num_desc--;
-+ }
-+ }
-+
-+ ipqess_w32(rx_ring->ess, IPQESS_REG_RX_SW_CONS_IDX_Q(rx_ring->idx),
-+ rx_ring_tail);
-+ rx_ring->tail = rx_ring_tail;
-+
-+ return done;
-+}
-+
-+static int ipqess_tx_complete(struct ipqess_tx_ring *tx_ring, int budget)
-+{
-+ int total = 0, ret;
-+ int done = 0;
-+ u32 tail;
-+
-+ tail = ipqess_r32(tx_ring->ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx));
-+ tail >>= IPQESS_TPD_CONS_IDX_SHIFT;
-+ tail &= IPQESS_TPD_CONS_IDX_MASK;
-+
-+ do {
-+ ret = ipqess_tx_unmap_and_free(&tx_ring->ess->pdev->dev,
-+ &tx_ring->buf[tx_ring->tail]);
-+ tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count);
-+
-+ total += ret;
-+ } while ((++done < budget) && (tx_ring->tail != tail));
-+
-+ ipqess_w32(tx_ring->ess, IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx),
-+ tx_ring->tail);
-+
-+ if (netif_tx_queue_stopped(tx_ring->nq)) {
-+ netdev_dbg(tx_ring->ess->netdev, "waking up tx queue %d\n",
-+ tx_ring->idx);
-+ netif_tx_wake_queue(tx_ring->nq);
-+ }
-+
-+ netdev_tx_completed_queue(tx_ring->nq, done, total);
-+
-+ return done;
-+}
-+
-+static int ipqess_tx_napi(struct napi_struct *napi, int budget)
-+{
-+ struct ipqess_tx_ring *tx_ring = container_of(napi, struct ipqess_tx_ring,
-+ napi_tx);
-+ int work_done = 0;
-+ u32 tx_status;
-+
-+ tx_status = ipqess_r32(tx_ring->ess, IPQESS_REG_TX_ISR);
-+ tx_status &= BIT(tx_ring->idx);
-+
-+ work_done = ipqess_tx_complete(tx_ring, budget);
-+
-+ ipqess_w32(tx_ring->ess, IPQESS_REG_TX_ISR, tx_status);
-+
-+ if (likely(work_done < budget)) {
-+ if (napi_complete_done(napi, work_done))
-+ ipqess_w32(tx_ring->ess,
-+ IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx), 0x1);
-+ }
-+
-+ return work_done;
-+}
-+
-+static int ipqess_rx_napi(struct napi_struct *napi, int budget)
-+{
-+ struct ipqess_rx_ring *rx_ring = container_of(napi, struct ipqess_rx_ring,
-+ napi_rx);
-+ struct ipqess *ess = rx_ring->ess;
-+ u32 rx_mask = BIT(rx_ring->idx);
-+ int remaining_budget = budget;
-+ int rx_done;
-+ u32 status;
-+
-+ do {
-+ ipqess_w32(ess, IPQESS_REG_RX_ISR, rx_mask);
-+ rx_done = ipqess_rx_poll(rx_ring, remaining_budget);
-+ remaining_budget -= rx_done;
-+
-+ status = ipqess_r32(ess, IPQESS_REG_RX_ISR);
-+ } while (remaining_budget > 0 && (status & rx_mask));
-+
-+ if (remaining_budget <= 0)
-+ return budget;
-+
-+ if (napi_complete_done(napi, budget - remaining_budget))
-+ ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx), 0x1);
-+
-+ return budget - remaining_budget;
-+}
-+
-+static irqreturn_t ipqess_interrupt_tx(int irq, void *priv)
-+{
-+ struct ipqess_tx_ring *tx_ring = (struct ipqess_tx_ring *)priv;
-+
-+ if (likely(napi_schedule_prep(&tx_ring->napi_tx))) {
-+ __napi_schedule(&tx_ring->napi_tx);
-+ ipqess_w32(tx_ring->ess, IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx),
-+ 0x0);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t ipqess_interrupt_rx(int irq, void *priv)
-+{
-+ struct ipqess_rx_ring *rx_ring = (struct ipqess_rx_ring *)priv;
-+
-+ if (likely(napi_schedule_prep(&rx_ring->napi_rx))) {
-+ __napi_schedule(&rx_ring->napi_rx);
-+ ipqess_w32(rx_ring->ess, IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx),
-+ 0x0);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static void ipqess_irq_enable(struct ipqess *ess)
-+{
-+ int i;
-+
-+ ipqess_w32(ess, IPQESS_REG_RX_ISR, 0xff);
-+ ipqess_w32(ess, IPQESS_REG_TX_ISR, 0xffff);
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(ess->rx_ring[i].idx), 1);
-+ ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(ess->tx_ring[i].idx), 1);
-+ }
-+}
-+
-+static void ipqess_irq_disable(struct ipqess *ess)
-+{
-+ int i;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(ess->rx_ring[i].idx), 0);
-+ ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(ess->tx_ring[i].idx), 0);
-+ }
-+}
-+
-+static int __init ipqess_init(struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ struct device_node *of_node = ess->pdev->dev.of_node;
-+ int ret;
-+
-+ ret = of_get_ethdev_address(of_node, netdev);
-+ if (ret)
-+ eth_hw_addr_random(netdev);
-+
-+ return phylink_of_phy_connect(ess->phylink, of_node, 0);
-+}
-+
-+static void ipqess_uninit(struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ phylink_disconnect_phy(ess->phylink);
-+}
-+
-+static int ipqess_open(struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ int i, err;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ int qid;
-+
-+ qid = ess->tx_ring[i].idx;
-+ err = devm_request_irq(&netdev->dev, ess->tx_irq[qid],
-+ ipqess_interrupt_tx, 0,
-+ ess->tx_irq_names[qid],
-+ &ess->tx_ring[i]);
-+ if (err)
-+ return err;
-+
-+ qid = ess->rx_ring[i].idx;
-+ err = devm_request_irq(&netdev->dev, ess->rx_irq[qid],
-+ ipqess_interrupt_rx, 0,
-+ ess->rx_irq_names[qid],
-+ &ess->rx_ring[i]);
-+ if (err)
-+ return err;
-+
-+ napi_enable(&ess->tx_ring[i].napi_tx);
-+ napi_enable(&ess->rx_ring[i].napi_rx);
-+ }
-+
-+ ipqess_irq_enable(ess);
-+ phylink_start(ess->phylink);
-+ netif_tx_start_all_queues(netdev);
-+
-+ return 0;
-+}
-+
-+static int ipqess_stop(struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ int i;
-+
-+ netif_tx_stop_all_queues(netdev);
-+ phylink_stop(ess->phylink);
-+ ipqess_irq_disable(ess);
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ napi_disable(&ess->tx_ring[i].napi_tx);
-+ napi_disable(&ess->rx_ring[i].napi_rx);
-+ }
-+
-+ return 0;
-+}
-+
-+static int ipqess_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ return phylink_mii_ioctl(ess->phylink, ifr, cmd);
-+}
-+
-+static u16 ipqess_tx_desc_available(struct ipqess_tx_ring *tx_ring)
-+{
-+ u16 count = 0;
-+
-+ if (tx_ring->tail <= tx_ring->head)
-+ count = IPQESS_TX_RING_SIZE;
-+
-+ count += tx_ring->tail - tx_ring->head - 1;
-+
-+ return count;
-+}
-+
-+static int ipqess_cal_txd_req(struct sk_buff *skb)
-+{
-+ int tpds;
-+
-+ /* one TPD for the header, and one for each fragments */
-+ tpds = 1 + skb_shinfo(skb)->nr_frags;
-+ if (skb_is_gso(skb) && skb_is_gso_v6(skb)) {
-+ /* for LSOv2 one extra TPD is needed */
-+ tpds++;
-+ }
-+
-+ return tpds;
-+}
-+
-+static struct ipqess_buf *ipqess_get_tx_buffer(struct ipqess_tx_ring *tx_ring,
-+ struct ipqess_tx_desc *desc)
-+{
-+ return &tx_ring->buf[desc - tx_ring->hw_desc];
-+}
-+
-+static struct ipqess_tx_desc *ipqess_tx_desc_next(struct ipqess_tx_ring *tx_ring)
-+{
-+ struct ipqess_tx_desc *desc;
-+
-+ desc = &tx_ring->hw_desc[tx_ring->head];
-+ tx_ring->head = IPQESS_NEXT_IDX(tx_ring->head, tx_ring->count);
-+
-+ return desc;
-+}
-+
-+static void ipqess_rollback_tx(struct ipqess *eth,
-+ struct ipqess_tx_desc *first_desc, int ring_id)
-+{
-+ struct ipqess_tx_ring *tx_ring = ð->tx_ring[ring_id];
-+ struct ipqess_tx_desc *desc = NULL;
-+ struct ipqess_buf *buf;
-+ u16 start_index, index;
-+
-+ start_index = first_desc - tx_ring->hw_desc;
-+
-+ index = start_index;
-+ while (index != tx_ring->head) {
-+ desc = &tx_ring->hw_desc[index];
-+ buf = &tx_ring->buf[index];
-+ ipqess_tx_unmap_and_free(ð->pdev->dev, buf);
-+ memset(desc, 0, sizeof(*desc));
-+ if (++index == tx_ring->count)
-+ index = 0;
-+ }
-+ tx_ring->head = start_index;
-+}
-+
-+static int ipqess_tx_map_and_fill(struct ipqess_tx_ring *tx_ring,
-+ struct sk_buff *skb)
-+{
-+ struct ipqess_tx_desc *desc = NULL, *first_desc = NULL;
-+ u32 word1 = 0, word3 = 0, lso_word1 = 0, svlan_tag = 0;
-+ struct platform_device *pdev = tx_ring->ess->pdev;
-+ struct ipqess_buf *buf = NULL;
-+ u16 len;
-+ int i;
-+
-+ if (skb_is_gso(skb)) {
-+ if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
-+ lso_word1 |= IPQESS_TPD_IPV4_EN;
-+ ip_hdr(skb)->check = 0;
-+ tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
-+ ip_hdr(skb)->daddr,
-+ 0, IPPROTO_TCP, 0);
-+ } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
-+ lso_word1 |= IPQESS_TPD_LSO_V2_EN;
-+ ipv6_hdr(skb)->payload_len = 0;
-+ tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
-+ &ipv6_hdr(skb)->daddr,
-+ 0, IPPROTO_TCP, 0);
-+ }
-+
-+ lso_word1 |= IPQESS_TPD_LSO_EN |
-+ ((skb_shinfo(skb)->gso_size & IPQESS_TPD_MSS_MASK) <<
-+ IPQESS_TPD_MSS_SHIFT) |
-+ (skb_transport_offset(skb) << IPQESS_TPD_HDR_SHIFT);
-+ } else if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
-+ u8 css, cso;
-+
-+ cso = skb_checksum_start_offset(skb);
-+ css = cso + skb->csum_offset;
-+
-+ word1 |= (IPQESS_TPD_CUSTOM_CSUM_EN);
-+ word1 |= (cso >> 1) << IPQESS_TPD_HDR_SHIFT;
-+ word1 |= ((css >> 1) << IPQESS_TPD_CUSTOM_CSUM_SHIFT);
-+ }
-+
-+ if (skb_vlan_tag_present(skb)) {
-+ switch (skb->vlan_proto) {
-+ case htons(ETH_P_8021Q):
-+ word3 |= BIT(IPQESS_TX_INS_CVLAN);
-+ word3 |= skb_vlan_tag_get(skb) << IPQESS_TX_CVLAN_TAG_SHIFT;
-+ break;
-+ case htons(ETH_P_8021AD):
-+ word1 |= BIT(IPQESS_TX_INS_SVLAN);
-+ svlan_tag = skb_vlan_tag_get(skb);
-+ break;
-+ default:
-+ dev_err(&pdev->dev, "no ctag or stag present\n");
-+ goto vlan_tag_error;
-+ }
-+ }
-+
-+ if (eth_type_vlan(skb->protocol))
-+ word1 |= IPQESS_TPD_VLAN_TAGGED;
-+
-+ if (skb->protocol == htons(ETH_P_PPP_SES))
-+ word1 |= IPQESS_TPD_PPPOE_EN;
-+
-+ len = skb_headlen(skb);
-+
-+ first_desc = ipqess_tx_desc_next(tx_ring);
-+ desc = first_desc;
-+ if (lso_word1 & IPQESS_TPD_LSO_V2_EN) {
-+ desc->addr = cpu_to_le32(skb->len);
-+ desc->word1 = cpu_to_le32(word1 | lso_word1);
-+ desc->svlan_tag = cpu_to_le16(svlan_tag);
-+ desc->word3 = cpu_to_le32(word3);
-+ desc = ipqess_tx_desc_next(tx_ring);
-+ }
-+
-+ buf = ipqess_get_tx_buffer(tx_ring, desc);
-+ buf->length = len;
-+ buf->dma = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
-+
-+ if (dma_mapping_error(&pdev->dev, buf->dma))
-+ goto dma_error;
-+
-+ desc->addr = cpu_to_le32(buf->dma);
-+ desc->len = cpu_to_le16(len);
-+
-+ buf->flags |= IPQESS_DESC_SINGLE;
-+ desc->word1 = cpu_to_le32(word1 | lso_word1);
-+ desc->svlan_tag = cpu_to_le16(svlan_tag);
-+ desc->word3 = cpu_to_le32(word3);
-+
-+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
-+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
-+
-+ len = skb_frag_size(frag);
-+ desc = ipqess_tx_desc_next(tx_ring);
-+ buf = ipqess_get_tx_buffer(tx_ring, desc);
-+ buf->length = len;
-+ buf->flags |= IPQESS_DESC_PAGE;
-+ buf->dma = skb_frag_dma_map(&pdev->dev, frag, 0, len,
-+ DMA_TO_DEVICE);
-+
-+ if (dma_mapping_error(&pdev->dev, buf->dma))
-+ goto dma_error;
-+
-+ desc->addr = cpu_to_le32(buf->dma);
-+ desc->len = cpu_to_le16(len);
-+ desc->svlan_tag = cpu_to_le16(svlan_tag);
-+ desc->word1 = cpu_to_le32(word1 | lso_word1);
-+ desc->word3 = cpu_to_le32(word3);
-+ }
-+ desc->word1 |= cpu_to_le32(1 << IPQESS_TPD_EOP_SHIFT);
-+ buf->skb = skb;
-+ buf->flags |= IPQESS_DESC_LAST;
-+
-+ return 0;
-+
-+dma_error:
-+ ipqess_rollback_tx(tx_ring->ess, first_desc, tx_ring->ring_id);
-+ dev_err(&pdev->dev, "TX DMA map failed\n");
-+
-+vlan_tag_error:
-+ return -ENOMEM;
-+}
-+
-+static void ipqess_kick_tx(struct ipqess_tx_ring *tx_ring)
-+{
-+ /* Ensure that all TPDs has been written completely */
-+ dma_wmb();
-+
-+ /* update software producer index */
-+ ipqess_w32(tx_ring->ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx),
-+ tx_ring->head);
-+}
-+
-+static netdev_tx_t ipqess_xmit(struct sk_buff *skb, struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ struct ipqess_tx_ring *tx_ring;
-+ int avail;
-+ int tx_num;
-+ int ret;
-+
-+ tx_ring = &ess->tx_ring[skb_get_queue_mapping(skb)];
-+ tx_num = ipqess_cal_txd_req(skb);
-+ avail = ipqess_tx_desc_available(tx_ring);
-+ if (avail < tx_num) {
-+ netdev_dbg(netdev,
-+ "stopping tx queue %d, avail=%d req=%d im=%x\n",
-+ tx_ring->idx, avail, tx_num,
-+ ipqess_r32(tx_ring->ess,
-+ IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx)));
-+ netif_tx_stop_queue(tx_ring->nq);
-+ ipqess_w32(tx_ring->ess, IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx), 0x1);
-+ ipqess_kick_tx(tx_ring);
-+ return NETDEV_TX_BUSY;
-+ }
-+
-+ ret = ipqess_tx_map_and_fill(tx_ring, skb);
-+ if (ret) {
-+ dev_kfree_skb_any(skb);
-+ ess->stats.tx_errors++;
-+ goto err_out;
-+ }
-+
-+ ess->stats.tx_packets++;
-+ ess->stats.tx_bytes += skb->len;
-+ netdev_tx_sent_queue(tx_ring->nq, skb->len);
-+
-+ if (!netdev_xmit_more() || netif_xmit_stopped(tx_ring->nq))
-+ ipqess_kick_tx(tx_ring);
-+
-+err_out:
-+ return NETDEV_TX_OK;
-+}
-+
-+static int ipqess_set_mac_address(struct net_device *netdev, void *p)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ const char *macaddr = netdev->dev_addr;
-+ int ret = eth_mac_addr(netdev, p);
-+
-+ if (ret)
-+ return ret;
-+
-+ ipqess_w32(ess, IPQESS_REG_MAC_CTRL1, (macaddr[0] << 8) | macaddr[1]);
-+ ipqess_w32(ess, IPQESS_REG_MAC_CTRL0,
-+ (macaddr[2] << 24) | (macaddr[3] << 16) | (macaddr[4] << 8) |
-+ macaddr[5]);
-+
-+ return 0;
-+}
-+
-+static void ipqess_tx_timeout(struct net_device *netdev, unsigned int txq_id)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ struct ipqess_tx_ring *tr = &ess->tx_ring[txq_id];
-+
-+ netdev_warn(netdev, "TX timeout on queue %d\n", tr->idx);
-+}
-+
-+static const struct net_device_ops ipqess_axi_netdev_ops = {
-+ .ndo_init = ipqess_init,
-+ .ndo_uninit = ipqess_uninit,
-+ .ndo_open = ipqess_open,
-+ .ndo_stop = ipqess_stop,
-+ .ndo_do_ioctl = ipqess_do_ioctl,
-+ .ndo_start_xmit = ipqess_xmit,
-+ .ndo_get_stats = ipqess_get_stats,
-+ .ndo_set_mac_address = ipqess_set_mac_address,
-+ .ndo_tx_timeout = ipqess_tx_timeout,
-+};
-+
-+static void ipqess_hw_stop(struct ipqess *ess)
-+{
-+ int i;
-+
-+ /* disable all RX queue IRQs */
-+ for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++)
-+ ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(i), 0);
-+
-+ /* disable all TX queue IRQs */
-+ for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++)
-+ ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(i), 0);
-+
-+ /* disable all other IRQs */
-+ ipqess_w32(ess, IPQESS_REG_MISC_IMR, 0);
-+ ipqess_w32(ess, IPQESS_REG_WOL_IMR, 0);
-+
-+ /* clear the IRQ status registers */
-+ ipqess_w32(ess, IPQESS_REG_RX_ISR, 0xff);
-+ ipqess_w32(ess, IPQESS_REG_TX_ISR, 0xffff);
-+ ipqess_w32(ess, IPQESS_REG_MISC_ISR, 0x1fff);
-+ ipqess_w32(ess, IPQESS_REG_WOL_ISR, 0x1);
-+ ipqess_w32(ess, IPQESS_REG_WOL_CTRL, 0);
-+
-+ /* disable RX and TX queues */
-+ ipqess_m32(ess, IPQESS_RXQ_CTRL_EN_MASK, 0, IPQESS_REG_RXQ_CTRL);
-+ ipqess_m32(ess, IPQESS_TXQ_CTRL_TXQ_EN, 0, IPQESS_REG_TXQ_CTRL);
-+}
-+
-+static int ipqess_hw_init(struct ipqess *ess)
-+{
-+ int i, err;
-+ u32 tmp;
-+
-+ ipqess_hw_stop(ess);
-+
-+ ipqess_m32(ess, BIT(IPQESS_INTR_SW_IDX_W_TYP_SHIFT),
-+ IPQESS_INTR_SW_IDX_W_TYPE << IPQESS_INTR_SW_IDX_W_TYP_SHIFT,
-+ IPQESS_REG_INTR_CTRL);
-+
-+ /* enable IRQ delay slot */
-+ ipqess_w32(ess, IPQESS_REG_IRQ_MODRT_TIMER_INIT,
-+ (IPQESS_TX_IMT << IPQESS_IRQ_MODRT_TX_TIMER_SHIFT) |
-+ (IPQESS_RX_IMT << IPQESS_IRQ_MODRT_RX_TIMER_SHIFT));
-+
-+ /* Set Customer and Service VLAN TPIDs */
-+ ipqess_w32(ess, IPQESS_REG_VLAN_CFG,
-+ (ETH_P_8021Q << IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT) |
-+ (ETH_P_8021AD << IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT));
-+
-+ /* Configure the TX Queue bursting */
-+ ipqess_w32(ess, IPQESS_REG_TXQ_CTRL,
-+ (IPQESS_TPD_BURST << IPQESS_TXQ_NUM_TPD_BURST_SHIFT) |
-+ (IPQESS_TXF_BURST << IPQESS_TXQ_TXF_BURST_NUM_SHIFT) |
-+ IPQESS_TXQ_CTRL_TPD_BURST_EN);
-+
-+ /* Set RSS type */
-+ ipqess_w32(ess, IPQESS_REG_RSS_TYPE,
-+ IPQESS_RSS_TYPE_IPV4TCP | IPQESS_RSS_TYPE_IPV6_TCP |
-+ IPQESS_RSS_TYPE_IPV4_UDP | IPQESS_RSS_TYPE_IPV6UDP |
-+ IPQESS_RSS_TYPE_IPV4 | IPQESS_RSS_TYPE_IPV6);
-+
-+ /* Set RFD ring burst and threshold */
-+ ipqess_w32(ess, IPQESS_REG_RX_DESC1,
-+ (IPQESS_RFD_BURST << IPQESS_RXQ_RFD_BURST_NUM_SHIFT) |
-+ (IPQESS_RFD_THR << IPQESS_RXQ_RFD_PF_THRESH_SHIFT) |
-+ (IPQESS_RFD_LTHR << IPQESS_RXQ_RFD_LOW_THRESH_SHIFT));
-+
-+ /* Set Rx FIFO
-+ * - threshold to start to DMA data to host
-+ */
-+ ipqess_w32(ess, IPQESS_REG_RXQ_CTRL,
-+ IPQESS_FIFO_THRESH_128_BYTE | IPQESS_RXQ_CTRL_RMV_VLAN);
-+
-+ err = ipqess_rx_ring_alloc(ess);
-+ if (err)
-+ return err;
-+
-+ err = ipqess_tx_ring_alloc(ess);
-+ if (err)
-+ goto err_rx_ring_free;
-+
-+ /* Load all of ring base addresses above into the dma engine */
-+ ipqess_m32(ess, 0, BIT(IPQESS_LOAD_PTR_SHIFT), IPQESS_REG_TX_SRAM_PART);
-+
-+ /* Disable TX FIFO low watermark and high watermark */
-+ ipqess_w32(ess, IPQESS_REG_TXF_WATER_MARK, 0);
-+
-+ /* Configure RSS indirection table.
-+ * 128 hash will be configured in the following
-+ * pattern: hash{0,1,2,3} = {Q0,Q2,Q4,Q6} respectively
-+ * and so on
-+ */
-+ for (i = 0; i < IPQESS_NUM_IDT; i++)
-+ ipqess_w32(ess, IPQESS_REG_RSS_IDT(i), IPQESS_RSS_IDT_VALUE);
-+
-+ /* Configure load balance mapping table.
-+ * 4 table entry will be configured according to the
-+ * following pattern: load_balance{0,1,2,3} = {Q0,Q1,Q3,Q4}
-+ * respectively.
-+ */
-+ ipqess_w32(ess, IPQESS_REG_LB_RING, IPQESS_LB_REG_VALUE);
-+
-+ /* Configure Virtual queue for Tx rings */
-+ ipqess_w32(ess, IPQESS_REG_VQ_CTRL0, IPQESS_VQ_REG_VALUE);
-+ ipqess_w32(ess, IPQESS_REG_VQ_CTRL1, IPQESS_VQ_REG_VALUE);
-+
-+ /* Configure Max AXI Burst write size to 128 bytes*/
-+ ipqess_w32(ess, IPQESS_REG_AXIW_CTRL_MAXWRSIZE,
-+ IPQESS_AXIW_MAXWRSIZE_VALUE);
-+
-+ /* Enable TX queues */
-+ ipqess_m32(ess, 0, IPQESS_TXQ_CTRL_TXQ_EN, IPQESS_REG_TXQ_CTRL);
-+
-+ /* Enable RX queues */
-+ tmp = 0;
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++)
-+ tmp |= IPQESS_RXQ_CTRL_EN(ess->rx_ring[i].idx);
-+
-+ ipqess_m32(ess, IPQESS_RXQ_CTRL_EN_MASK, tmp, IPQESS_REG_RXQ_CTRL);
-+
-+ return 0;
-+
-+err_rx_ring_free:
-+
-+ ipqess_rx_ring_free(ess);
-+ return err;
-+}
-+
-+static void ipqess_mac_config(struct phylink_config *config, unsigned int mode,
-+ const struct phylink_link_state *state)
-+{
-+ /* Nothing to do, use fixed Internal mode */
-+}
-+
-+static void ipqess_mac_link_down(struct phylink_config *config,
-+ unsigned int mode,
-+ phy_interface_t interface)
-+{
-+ /* Nothing to do, use fixed Internal mode */
-+}
-+
-+static void ipqess_mac_link_up(struct phylink_config *config,
-+ struct phy_device *phy, unsigned int mode,
-+ phy_interface_t interface,
-+ int speed, int duplex,
-+ bool tx_pause, bool rx_pause)
-+{
-+ /* Nothing to do, use fixed Internal mode */
-+}
-+
-+static struct phylink_mac_ops ipqess_phylink_mac_ops = {
-+ .validate = phylink_generic_validate,
-+ .mac_config = ipqess_mac_config,
-+ .mac_link_up = ipqess_mac_link_up,
-+ .mac_link_down = ipqess_mac_link_down,
-+};
-+
-+static void ipqess_reset(struct ipqess *ess)
-+{
-+ reset_control_assert(ess->ess_rst);
-+
-+ mdelay(10);
-+
-+ reset_control_deassert(ess->ess_rst);
-+
-+ /* Waiting for all inner tables to be flushed and reinitialized.
-+ * This takes between 5 and 10 ms
-+ */
-+
-+ mdelay(10);
-+}
-+
-+static int ipqess_axi_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct net_device *netdev;
-+ phy_interface_t phy_mode;
-+ struct ipqess *ess;
-+ int i, err = 0;
-+
-+ netdev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(*ess),
-+ IPQESS_NETDEV_QUEUES,
-+ IPQESS_NETDEV_QUEUES);
-+ if (!netdev)
-+ return -ENOMEM;
-+
-+ ess = netdev_priv(netdev);
-+ ess->netdev = netdev;
-+ ess->pdev = pdev;
-+ spin_lock_init(&ess->stats_lock);
-+ SET_NETDEV_DEV(netdev, &pdev->dev);
-+ platform_set_drvdata(pdev, netdev);
-+
-+ ess->hw_addr = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
-+ if (IS_ERR(ess->hw_addr))
-+ return PTR_ERR(ess->hw_addr);
-+
-+ err = of_get_phy_mode(np, &phy_mode);
-+ if (err) {
-+ dev_err(&pdev->dev, "incorrect phy-mode\n");
-+ return err;
-+ }
-+
-+ ess->ess_clk = devm_clk_get(&pdev->dev, NULL);
-+ if (!IS_ERR(ess->ess_clk))
-+ clk_prepare_enable(ess->ess_clk);
-+
-+ ess->ess_rst = devm_reset_control_get(&pdev->dev, NULL);
-+ if (IS_ERR(ess->ess_rst))
-+ goto err_clk;
-+
-+ ipqess_reset(ess);
-+
-+ ess->phylink_config.dev = &netdev->dev;
-+ ess->phylink_config.type = PHYLINK_NETDEV;
-+ ess->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 |
-+ MAC_100 | MAC_1000FD;
-+
-+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
-+ ess->phylink_config.supported_interfaces);
-+
-+ ess->phylink = phylink_create(&ess->phylink_config,
-+ of_fwnode_handle(np), phy_mode,
-+ &ipqess_phylink_mac_ops);
-+ if (IS_ERR(ess->phylink)) {
-+ err = PTR_ERR(ess->phylink);
-+ goto err_clk;
-+ }
-+
-+ for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) {
-+ ess->tx_irq[i] = platform_get_irq(pdev, i);
-+ scnprintf(ess->tx_irq_names[i], sizeof(ess->tx_irq_names[i]),
-+ "%s:txq%d", pdev->name, i);
-+ }
-+
-+ for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) {
-+ ess->rx_irq[i] = platform_get_irq(pdev, i + IPQESS_MAX_TX_QUEUE);
-+ scnprintf(ess->rx_irq_names[i], sizeof(ess->rx_irq_names[i]),
-+ "%s:rxq%d", pdev->name, i);
-+ }
-+
-+ netdev->netdev_ops = &ipqess_axi_netdev_ops;
-+ netdev->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
-+ NETIF_F_HW_VLAN_CTAG_RX |
-+ NETIF_F_HW_VLAN_CTAG_TX |
-+ NETIF_F_TSO | NETIF_F_GRO | NETIF_F_SG;
-+ /* feature change is not supported yet */
-+ netdev->hw_features = 0;
-+ netdev->vlan_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_RXCSUM |
-+ NETIF_F_TSO |
-+ NETIF_F_GRO;
-+ netdev->watchdog_timeo = 5 * HZ;
-+ netdev->base_addr = (u32)ess->hw_addr;
-+ netdev->max_mtu = 9000;
-+ netdev->gso_max_segs = IPQESS_TX_RING_SIZE / 2;
-+
-+ ipqess_set_ethtool_ops(netdev);
-+
-+ err = ipqess_hw_init(ess);
-+ if (err)
-+ goto err_phylink;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ netif_napi_add_tx(netdev, &ess->tx_ring[i].napi_tx, ipqess_tx_napi);
-+ netif_napi_add(netdev, &ess->rx_ring[i].napi_rx, ipqess_rx_napi);
-+ }
-+
-+ err = register_netdev(netdev);
-+ if (err)
-+ goto err_hw_stop;
-+
-+ return 0;
-+
-+err_hw_stop:
-+ ipqess_hw_stop(ess);
-+
-+ ipqess_tx_ring_free(ess);
-+ ipqess_rx_ring_free(ess);
-+err_phylink:
-+ phylink_destroy(ess->phylink);
-+
-+err_clk:
-+ clk_disable_unprepare(ess->ess_clk);
-+
-+ return err;
-+}
-+
-+static int ipqess_axi_remove(struct platform_device *pdev)
-+{
-+ const struct net_device *netdev = platform_get_drvdata(pdev);
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ unregister_netdev(ess->netdev);
-+ ipqess_hw_stop(ess);
-+
-+ ipqess_tx_ring_free(ess);
-+ ipqess_rx_ring_free(ess);
-+
-+ phylink_destroy(ess->phylink);
-+ clk_disable_unprepare(ess->ess_clk);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id ipqess_of_mtable[] = {
-+ {.compatible = "qcom,ipq4019-ess-edma" },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, ipqess_of_mtable);
-+
-+static struct platform_driver ipqess_axi_driver = {
-+ .driver = {
-+ .name = "ipqess-edma",
-+ .of_match_table = ipqess_of_mtable,
-+ },
-+ .probe = ipqess_axi_probe,
-+ .remove = ipqess_axi_remove,
-+};
-+
-+module_platform_driver(ipqess_axi_driver);
-+
-+MODULE_AUTHOR("Qualcomm Atheros Inc");
-+MODULE_AUTHOR("John Crispin <john@phrozen.org>");
-+MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
-+MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>");
-+MODULE_AUTHOR("Maxime Chevallier <maxime.chevallier@bootlin.com>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
-@@ -0,0 +1,518 @@
-+/* SPDX-License-Identifier: (GPL-2.0 OR ISC) */
-+/* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
-+ * Copyright (c) 2018 - 2019, Christian Lamparter <chunkeey@gmail.com>
-+ * Copyright (c) 2020 - 2021, Gabor Juhos <j4g8y7@gmail.com>
-+ * Copyright (c) 2021 - 2022, Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ *
-+ */
-+
-+#ifndef _IPQESS_H_
-+#define _IPQESS_H_
-+
-+#define IPQESS_NETDEV_QUEUES 4
-+
-+#define IPQESS_TPD_EOP_SHIFT 31
-+
-+#define IPQESS_PORT_ID_SHIFT 12
-+#define IPQESS_PORT_ID_MASK 0x7
-+
-+/* tpd word 3 bit 18-28 */
-+#define IPQESS_TPD_PORT_BITMAP_SHIFT 18
-+
-+#define IPQESS_TPD_FROM_CPU_SHIFT 25
-+
-+#define IPQESS_RX_RING_SIZE 128
-+#define IPQESS_RX_HEAD_BUFF_SIZE 1540
-+#define IPQESS_TX_RING_SIZE 128
-+#define IPQESS_MAX_RX_QUEUE 8
-+#define IPQESS_MAX_TX_QUEUE 16
-+
-+/* Configurations */
-+#define IPQESS_INTR_CLEAR_TYPE 0
-+#define IPQESS_INTR_SW_IDX_W_TYPE 0
-+#define IPQESS_FIFO_THRESH_TYPE 0
-+#define IPQESS_RSS_TYPE 0
-+#define IPQESS_RX_IMT 0x0020
-+#define IPQESS_TX_IMT 0x0050
-+#define IPQESS_TPD_BURST 5
-+#define IPQESS_TXF_BURST 0x100
-+#define IPQESS_RFD_BURST 8
-+#define IPQESS_RFD_THR 16
-+#define IPQESS_RFD_LTHR 0
-+
-+/* Flags used in transmit direction */
-+#define IPQESS_DESC_LAST 0x1
-+#define IPQESS_DESC_SINGLE 0x2
-+#define IPQESS_DESC_PAGE 0x4
-+
-+struct ipqess_statistics {
-+ u32 tx_q0_pkt;
-+ u32 tx_q1_pkt;
-+ u32 tx_q2_pkt;
-+ u32 tx_q3_pkt;
-+ u32 tx_q4_pkt;
-+ u32 tx_q5_pkt;
-+ u32 tx_q6_pkt;
-+ u32 tx_q7_pkt;
-+ u32 tx_q8_pkt;
-+ u32 tx_q9_pkt;
-+ u32 tx_q10_pkt;
-+ u32 tx_q11_pkt;
-+ u32 tx_q12_pkt;
-+ u32 tx_q13_pkt;
-+ u32 tx_q14_pkt;
-+ u32 tx_q15_pkt;
-+ u32 tx_q0_byte;
-+ u32 tx_q1_byte;
-+ u32 tx_q2_byte;
-+ u32 tx_q3_byte;
-+ u32 tx_q4_byte;
-+ u32 tx_q5_byte;
-+ u32 tx_q6_byte;
-+ u32 tx_q7_byte;
-+ u32 tx_q8_byte;
-+ u32 tx_q9_byte;
-+ u32 tx_q10_byte;
-+ u32 tx_q11_byte;
-+ u32 tx_q12_byte;
-+ u32 tx_q13_byte;
-+ u32 tx_q14_byte;
-+ u32 tx_q15_byte;
-+ u32 rx_q0_pkt;
-+ u32 rx_q1_pkt;
-+ u32 rx_q2_pkt;
-+ u32 rx_q3_pkt;
-+ u32 rx_q4_pkt;
-+ u32 rx_q5_pkt;
-+ u32 rx_q6_pkt;
-+ u32 rx_q7_pkt;
-+ u32 rx_q0_byte;
-+ u32 rx_q1_byte;
-+ u32 rx_q2_byte;
-+ u32 rx_q3_byte;
-+ u32 rx_q4_byte;
-+ u32 rx_q5_byte;
-+ u32 rx_q6_byte;
-+ u32 rx_q7_byte;
-+ u32 tx_desc_error;
-+};
-+
-+struct ipqess_tx_desc {
-+ __le16 len;
-+ __le16 svlan_tag;
-+ __le32 word1;
-+ __le32 addr;
-+ __le32 word3;
-+} __aligned(16) __packed;
-+
-+struct ipqess_rx_desc {
-+ __le16 rrd0;
-+ __le16 rrd1;
-+ __le16 rrd2;
-+ __le16 rrd3;
-+ __le16 rrd4;
-+ __le16 rrd5;
-+ __le16 rrd6;
-+ __le16 rrd7;
-+} __aligned(16) __packed;
-+
-+struct ipqess_buf {
-+ struct sk_buff *skb;
-+ dma_addr_t dma;
-+ u32 flags;
-+ u16 length;
-+};
-+
-+struct ipqess_tx_ring {
-+ struct napi_struct napi_tx;
-+ u32 idx;
-+ int ring_id;
-+ struct ipqess *ess;
-+ struct netdev_queue *nq;
-+ struct ipqess_tx_desc *hw_desc;
-+ struct ipqess_buf *buf;
-+ dma_addr_t dma;
-+ u16 count;
-+ u16 head;
-+ u16 tail;
-+};
-+
-+struct ipqess_rx_ring {
-+ struct napi_struct napi_rx;
-+ u32 idx;
-+ int ring_id;
-+ struct ipqess *ess;
-+ struct device *ppdev;
-+ struct ipqess_rx_desc **hw_desc;
-+ struct ipqess_buf *buf;
-+ dma_addr_t dma;
-+ u16 head;
-+ u16 tail;
-+ atomic_t refill_count;
-+};
-+
-+struct ipqess_rx_ring_refill {
-+ struct ipqess_rx_ring *rx_ring;
-+ struct work_struct refill_work;
-+};
-+
-+#define IPQESS_IRQ_NAME_LEN 32
-+
-+struct ipqess {
-+ struct net_device *netdev;
-+ void __iomem *hw_addr;
-+
-+ struct clk *ess_clk;
-+ struct reset_control *ess_rst;
-+
-+ struct ipqess_rx_ring rx_ring[IPQESS_NETDEV_QUEUES];
-+
-+ struct platform_device *pdev;
-+ struct phylink *phylink;
-+ struct phylink_config phylink_config;
-+ struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES];
-+
-+ struct ipqess_statistics ipqess_stats;
-+
-+ /* Protects stats */
-+ spinlock_t stats_lock;
-+ struct net_device_stats stats;
-+
-+ struct ipqess_rx_ring_refill rx_refill[IPQESS_NETDEV_QUEUES];
-+ u32 tx_irq[IPQESS_MAX_TX_QUEUE];
-+ char tx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
-+ u32 rx_irq[IPQESS_MAX_RX_QUEUE];
-+ char rx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
-+};
-+
-+void ipqess_set_ethtool_ops(struct net_device *netdev);
-+void ipqess_update_hw_stats(struct ipqess *ess);
-+
-+/* register definition */
-+#define IPQESS_REG_MAS_CTRL 0x0
-+#define IPQESS_REG_TIMEOUT_CTRL 0x004
-+#define IPQESS_REG_DBG0 0x008
-+#define IPQESS_REG_DBG1 0x00C
-+#define IPQESS_REG_SW_CTRL0 0x100
-+#define IPQESS_REG_SW_CTRL1 0x104
-+
-+/* Interrupt Status Register */
-+#define IPQESS_REG_RX_ISR 0x200
-+#define IPQESS_REG_TX_ISR 0x208
-+#define IPQESS_REG_MISC_ISR 0x210
-+#define IPQESS_REG_WOL_ISR 0x218
-+
-+#define IPQESS_MISC_ISR_RX_URG_Q(x) (1 << (x))
-+
-+#define IPQESS_MISC_ISR_AXIR_TIMEOUT 0x00000100
-+#define IPQESS_MISC_ISR_AXIR_ERR 0x00000200
-+#define IPQESS_MISC_ISR_TXF_DEAD 0x00000400
-+#define IPQESS_MISC_ISR_AXIW_ERR 0x00000800
-+#define IPQESS_MISC_ISR_AXIW_TIMEOUT 0x00001000
-+
-+#define IPQESS_WOL_ISR 0x00000001
-+
-+/* Interrupt Mask Register */
-+#define IPQESS_REG_MISC_IMR 0x214
-+#define IPQESS_REG_WOL_IMR 0x218
-+
-+#define IPQESS_RX_IMR_NORMAL_MASK 0x1
-+#define IPQESS_TX_IMR_NORMAL_MASK 0x1
-+#define IPQESS_MISC_IMR_NORMAL_MASK 0x80001FFF
-+#define IPQESS_WOL_IMR_NORMAL_MASK 0x1
-+
-+/* Edma receive consumer index */
-+#define IPQESS_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
-+
-+/* Edma transmit consumer index */
-+#define IPQESS_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
-+
-+/* IRQ Moderator Initial Timer Register */
-+#define IPQESS_REG_IRQ_MODRT_TIMER_INIT 0x280
-+#define IPQESS_IRQ_MODRT_TIMER_MASK 0xFFFF
-+#define IPQESS_IRQ_MODRT_RX_TIMER_SHIFT 0
-+#define IPQESS_IRQ_MODRT_TX_TIMER_SHIFT 16
-+
-+/* Interrupt Control Register */
-+#define IPQESS_REG_INTR_CTRL 0x284
-+#define IPQESS_INTR_CLR_TYP_SHIFT 0
-+#define IPQESS_INTR_SW_IDX_W_TYP_SHIFT 1
-+#define IPQESS_INTR_CLEAR_TYPE_W1 0
-+#define IPQESS_INTR_CLEAR_TYPE_R 1
-+
-+/* RX Interrupt Mask Register */
-+#define IPQESS_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
-+
-+/* TX Interrupt mask register */
-+#define IPQESS_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
-+
-+/* Load Ptr Register
-+ * Software sets this bit after the initialization of the head and tail
-+ */
-+#define IPQESS_REG_TX_SRAM_PART 0x400
-+#define IPQESS_LOAD_PTR_SHIFT 16
-+
-+/* TXQ Control Register */
-+#define IPQESS_REG_TXQ_CTRL 0x404
-+#define IPQESS_TXQ_CTRL_IP_OPTION_EN 0x10
-+#define IPQESS_TXQ_CTRL_TXQ_EN 0x20
-+#define IPQESS_TXQ_CTRL_ENH_MODE 0x40
-+#define IPQESS_TXQ_CTRL_LS_8023_EN 0x80
-+#define IPQESS_TXQ_CTRL_TPD_BURST_EN 0x100
-+#define IPQESS_TXQ_CTRL_LSO_BREAK_EN 0x200
-+#define IPQESS_TXQ_NUM_TPD_BURST_MASK 0xF
-+#define IPQESS_TXQ_TXF_BURST_NUM_MASK 0xFFFF
-+#define IPQESS_TXQ_NUM_TPD_BURST_SHIFT 0
-+#define IPQESS_TXQ_TXF_BURST_NUM_SHIFT 16
-+
-+#define IPQESS_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
-+#define IPQESS_TXF_WATER_MARK_MASK 0x0FFF
-+#define IPQESS_TXF_LOW_WATER_MARK_SHIFT 0
-+#define IPQESS_TXF_HIGH_WATER_MARK_SHIFT 16
-+#define IPQESS_TXQ_CTRL_BURST_MODE_EN 0x80000000
-+
-+/* WRR Control Register */
-+#define IPQESS_REG_WRR_CTRL_Q0_Q3 0x40c
-+#define IPQESS_REG_WRR_CTRL_Q4_Q7 0x410
-+#define IPQESS_REG_WRR_CTRL_Q8_Q11 0x414
-+#define IPQESS_REG_WRR_CTRL_Q12_Q15 0x418
-+
-+/* Weight round robin(WRR), it takes queue as input, and computes
-+ * starting bits where we need to write the weight for a particular
-+ * queue
-+ */
-+#define IPQESS_WRR_SHIFT(x) (((x) * 5) % 20)
-+
-+/* Tx Descriptor Control Register */
-+#define IPQESS_REG_TPD_RING_SIZE 0x41C
-+#define IPQESS_TPD_RING_SIZE_SHIFT 0
-+#define IPQESS_TPD_RING_SIZE_MASK 0xFFFF
-+
-+/* Transmit descriptor base address */
-+#define IPQESS_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
-+
-+/* TPD Index Register */
-+#define IPQESS_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
-+
-+#define IPQESS_TPD_PROD_IDX_BITS 0x0000FFFF
-+#define IPQESS_TPD_CONS_IDX_BITS 0xFFFF0000
-+#define IPQESS_TPD_PROD_IDX_MASK 0xFFFF
-+#define IPQESS_TPD_CONS_IDX_MASK 0xFFFF
-+#define IPQESS_TPD_PROD_IDX_SHIFT 0
-+#define IPQESS_TPD_CONS_IDX_SHIFT 16
-+
-+/* TX Virtual Queue Mapping Control Register */
-+#define IPQESS_REG_VQ_CTRL0 0x4A0
-+#define IPQESS_REG_VQ_CTRL1 0x4A4
-+
-+/* Virtual QID shift, it takes queue as input, and computes
-+ * Virtual QID position in virtual qid control register
-+ */
-+#define IPQESS_VQ_ID_SHIFT(i) (((i) * 3) % 24)
-+
-+/* Virtual Queue Default Value */
-+#define IPQESS_VQ_REG_VALUE 0x240240
-+
-+/* Tx side Port Interface Control Register */
-+#define IPQESS_REG_PORT_CTRL 0x4A8
-+#define IPQESS_PAD_EN_SHIFT 15
-+
-+/* Tx side VLAN Configuration Register */
-+#define IPQESS_REG_VLAN_CFG 0x4AC
-+
-+#define IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT 0
-+#define IPQESS_VLAN_CFG_SVLAN_TPID_MASK 0xffff
-+#define IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT 16
-+#define IPQESS_VLAN_CFG_CVLAN_TPID_MASK 0xffff
-+
-+#define IPQESS_TX_CVLAN 16
-+#define IPQESS_TX_INS_CVLAN 17
-+#define IPQESS_TX_CVLAN_TAG_SHIFT 0
-+
-+#define IPQESS_TX_SVLAN 14
-+#define IPQESS_TX_INS_SVLAN 15
-+#define IPQESS_TX_SVLAN_TAG_SHIFT 16
-+
-+/* Tx Queue Packet Statistic Register */
-+#define IPQESS_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
-+
-+#define IPQESS_TX_STAT_PKT_MASK 0xFFFFFF
-+
-+/* Tx Queue Byte Statistic Register */
-+#define IPQESS_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
-+
-+/* Load Balance Based Ring Offset Register */
-+#define IPQESS_REG_LB_RING 0x800
-+#define IPQESS_LB_RING_ENTRY_MASK 0xff
-+#define IPQESS_LB_RING_ID_MASK 0x7
-+#define IPQESS_LB_RING_PROFILE_ID_MASK 0x3
-+#define IPQESS_LB_RING_ENTRY_BIT_OFFSET 8
-+#define IPQESS_LB_RING_ID_OFFSET 0
-+#define IPQESS_LB_RING_PROFILE_ID_OFFSET 3
-+#define IPQESS_LB_REG_VALUE 0x6040200
-+
-+/* Load Balance Priority Mapping Register */
-+#define IPQESS_REG_LB_PRI_START 0x804
-+#define IPQESS_REG_LB_PRI_END 0x810
-+#define IPQESS_LB_PRI_REG_INC 4
-+#define IPQESS_LB_PRI_ENTRY_BIT_OFFSET 4
-+#define IPQESS_LB_PRI_ENTRY_MASK 0xf
-+
-+/* RSS Priority Mapping Register */
-+#define IPQESS_REG_RSS_PRI 0x820
-+#define IPQESS_RSS_PRI_ENTRY_MASK 0xf
-+#define IPQESS_RSS_RING_ID_MASK 0x7
-+#define IPQESS_RSS_PRI_ENTRY_BIT_OFFSET 4
-+
-+/* RSS Indirection Register */
-+#define IPQESS_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
-+#define IPQESS_NUM_IDT 16
-+#define IPQESS_RSS_IDT_VALUE 0x64206420
-+
-+/* Default RSS Ring Register */
-+#define IPQESS_REG_DEF_RSS 0x890
-+#define IPQESS_DEF_RSS_MASK 0x7
-+
-+/* RSS Hash Function Type Register */
-+#define IPQESS_REG_RSS_TYPE 0x894
-+#define IPQESS_RSS_TYPE_NONE 0x01
-+#define IPQESS_RSS_TYPE_IPV4TCP 0x02
-+#define IPQESS_RSS_TYPE_IPV6_TCP 0x04
-+#define IPQESS_RSS_TYPE_IPV4_UDP 0x08
-+#define IPQESS_RSS_TYPE_IPV6UDP 0x10
-+#define IPQESS_RSS_TYPE_IPV4 0x20
-+#define IPQESS_RSS_TYPE_IPV6 0x40
-+#define IPQESS_RSS_HASH_MODE_MASK 0x7f
-+
-+#define IPQESS_REG_RSS_HASH_VALUE 0x8C0
-+
-+#define IPQESS_REG_RSS_TYPE_RESULT 0x8C4
-+
-+#define IPQESS_HASH_TYPE_START 0
-+#define IPQESS_HASH_TYPE_END 5
-+#define IPQESS_HASH_TYPE_SHIFT 12
-+
-+#define IPQESS_RFS_FLOW_ENTRIES 1024
-+#define IPQESS_RFS_FLOW_ENTRIES_MASK (IPQESS_RFS_FLOW_ENTRIES - 1)
-+#define IPQESS_RFS_EXPIRE_COUNT_PER_CALL 128
-+
-+/* RFD Base Address Register */
-+#define IPQESS_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
-+
-+/* RFD Index Register */
-+#define IPQESS_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) /* x = queue id */
-+
-+#define IPQESS_RFD_PROD_IDX_BITS 0x00000FFF
-+#define IPQESS_RFD_CONS_IDX_BITS 0x0FFF0000
-+#define IPQESS_RFD_PROD_IDX_MASK 0xFFF
-+#define IPQESS_RFD_CONS_IDX_MASK 0xFFF
-+#define IPQESS_RFD_PROD_IDX_SHIFT 0
-+#define IPQESS_RFD_CONS_IDX_SHIFT 16
-+
-+/* Rx Descriptor Control Register */
-+#define IPQESS_REG_RX_DESC0 0xA10
-+#define IPQESS_RFD_RING_SIZE_MASK 0xFFF
-+#define IPQESS_RX_BUF_SIZE_MASK 0xFFFF
-+#define IPQESS_RFD_RING_SIZE_SHIFT 0
-+#define IPQESS_RX_BUF_SIZE_SHIFT 16
-+
-+#define IPQESS_REG_RX_DESC1 0xA14
-+#define IPQESS_RXQ_RFD_BURST_NUM_MASK 0x3F
-+#define IPQESS_RXQ_RFD_PF_THRESH_MASK 0x1F
-+#define IPQESS_RXQ_RFD_LOW_THRESH_MASK 0xFFF
-+#define IPQESS_RXQ_RFD_BURST_NUM_SHIFT 0
-+#define IPQESS_RXQ_RFD_PF_THRESH_SHIFT 8
-+#define IPQESS_RXQ_RFD_LOW_THRESH_SHIFT 16
-+
-+/* RXQ Control Register */
-+#define IPQESS_REG_RXQ_CTRL 0xA18
-+#define IPQESS_FIFO_THRESH_TYPE_SHIF 0
-+#define IPQESS_FIFO_THRESH_128_BYTE 0x0
-+#define IPQESS_FIFO_THRESH_64_BYTE 0x1
-+#define IPQESS_RXQ_CTRL_RMV_VLAN 0x00000002
-+#define IPQESS_RXQ_CTRL_EN_MASK GENMASK(15, 8)
-+#define IPQESS_RXQ_CTRL_EN(__qid) BIT(8 + (__qid))
-+
-+/* AXI Burst Size Config */
-+#define IPQESS_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
-+#define IPQESS_AXIW_MAXWRSIZE_VALUE 0x0
-+
-+/* Rx Statistics Register */
-+#define IPQESS_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
-+#define IPQESS_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
-+
-+/* WoL Pattern Length Register */
-+#define IPQESS_REG_WOL_PATTERN_LEN0 0xC00
-+#define IPQESS_WOL_PT_LEN_MASK 0xFF
-+#define IPQESS_WOL_PT0_LEN_SHIFT 0
-+#define IPQESS_WOL_PT1_LEN_SHIFT 8
-+#define IPQESS_WOL_PT2_LEN_SHIFT 16
-+#define IPQESS_WOL_PT3_LEN_SHIFT 24
-+
-+#define IPQESS_REG_WOL_PATTERN_LEN1 0xC04
-+#define IPQESS_WOL_PT4_LEN_SHIFT 0
-+#define IPQESS_WOL_PT5_LEN_SHIFT 8
-+#define IPQESS_WOL_PT6_LEN_SHIFT 16
-+
-+/* WoL Control Register */
-+#define IPQESS_REG_WOL_CTRL 0xC08
-+#define IPQESS_WOL_WK_EN 0x00000001
-+#define IPQESS_WOL_MG_EN 0x00000002
-+#define IPQESS_WOL_PT0_EN 0x00000004
-+#define IPQESS_WOL_PT1_EN 0x00000008
-+#define IPQESS_WOL_PT2_EN 0x00000010
-+#define IPQESS_WOL_PT3_EN 0x00000020
-+#define IPQESS_WOL_PT4_EN 0x00000040
-+#define IPQESS_WOL_PT5_EN 0x00000080
-+#define IPQESS_WOL_PT6_EN 0x00000100
-+
-+/* MAC Control Register */
-+#define IPQESS_REG_MAC_CTRL0 0xC20
-+#define IPQESS_REG_MAC_CTRL1 0xC24
-+
-+/* WoL Pattern Register */
-+#define IPQESS_REG_WOL_PATTERN_START 0x5000
-+#define IPQESS_PATTERN_PART_REG_OFFSET 0x40
-+
-+/* TX descriptor fields */
-+#define IPQESS_TPD_HDR_SHIFT 0
-+#define IPQESS_TPD_PPPOE_EN 0x00000100
-+#define IPQESS_TPD_IP_CSUM_EN 0x00000200
-+#define IPQESS_TPD_TCP_CSUM_EN 0x0000400
-+#define IPQESS_TPD_UDP_CSUM_EN 0x00000800
-+#define IPQESS_TPD_CUSTOM_CSUM_EN 0x00000C00
-+#define IPQESS_TPD_LSO_EN 0x00001000
-+#define IPQESS_TPD_LSO_V2_EN 0x00002000
-+/* The VLAN_TAGGED bit is not used in the publicly available
-+ * drivers. The definition has been stolen from the Atheros
-+ * 'alx' driver (drivers/net/ethernet/atheros/alx/hw.h). It
-+ * seems that it has the same meaning in regard to the EDMA
-+ * hardware.
-+ */
-+#define IPQESS_TPD_VLAN_TAGGED 0x00004000
-+#define IPQESS_TPD_IPV4_EN 0x00010000
-+#define IPQESS_TPD_MSS_MASK 0x1FFF
-+#define IPQESS_TPD_MSS_SHIFT 18
-+#define IPQESS_TPD_CUSTOM_CSUM_SHIFT 18
-+
-+/* RRD descriptor fields */
-+#define IPQESS_RRD_NUM_RFD_MASK 0x000F
-+#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
-+#define IPQESS_RRD_SRC_PORT_NUM_MASK 0x4000
-+#define IPQESS_RRD_SVLAN 0x8000
-+#define IPQESS_RRD_FLOW_COOKIE_MASK 0x07FF
-+
-+#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
-+#define IPQESS_RRD_CSUM_FAIL_MASK 0xC000
-+#define IPQESS_RRD_CVLAN 0x0001
-+#define IPQESS_RRD_DESC_VALID 0x8000
-+
-+#define IPQESS_RRD_PRIORITY_SHIFT 4
-+#define IPQESS_RRD_PRIORITY_MASK 0x7
-+#define IPQESS_RRD_PORT_TYPE_SHIFT 7
-+#define IPQESS_RRD_PORT_TYPE_MASK 0x1F
-+
-+#define IPQESS_RRD_PORT_ID_MASK 0x7000
-+
-+#endif
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess_ethtool.c
-@@ -0,0 +1,164 @@
-+// SPDX-License-Identifier: GPL-2.0 OR ISC
-+/* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
-+ * Copyright (c) 2021 - 2022, Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ *
-+ */
-+
-+#include <linux/ethtool.h>
-+#include <linux/netdevice.h>
-+#include <linux/string.h>
-+#include <linux/phylink.h>
-+
-+#include "ipqess.h"
-+
-+struct ipqess_ethtool_stats {
-+ u8 string[ETH_GSTRING_LEN];
-+ u32 offset;
-+};
-+
-+#define IPQESS_STAT(m) offsetof(struct ipqess_statistics, m)
-+#define DRVINFO_LEN 32
-+
-+static const struct ipqess_ethtool_stats ipqess_stats[] = {
-+ {"tx_q0_pkt", IPQESS_STAT(tx_q0_pkt)},
-+ {"tx_q1_pkt", IPQESS_STAT(tx_q1_pkt)},
-+ {"tx_q2_pkt", IPQESS_STAT(tx_q2_pkt)},
-+ {"tx_q3_pkt", IPQESS_STAT(tx_q3_pkt)},
-+ {"tx_q4_pkt", IPQESS_STAT(tx_q4_pkt)},
-+ {"tx_q5_pkt", IPQESS_STAT(tx_q5_pkt)},
-+ {"tx_q6_pkt", IPQESS_STAT(tx_q6_pkt)},
-+ {"tx_q7_pkt", IPQESS_STAT(tx_q7_pkt)},
-+ {"tx_q8_pkt", IPQESS_STAT(tx_q8_pkt)},
-+ {"tx_q9_pkt", IPQESS_STAT(tx_q9_pkt)},
-+ {"tx_q10_pkt", IPQESS_STAT(tx_q10_pkt)},
-+ {"tx_q11_pkt", IPQESS_STAT(tx_q11_pkt)},
-+ {"tx_q12_pkt", IPQESS_STAT(tx_q12_pkt)},
-+ {"tx_q13_pkt", IPQESS_STAT(tx_q13_pkt)},
-+ {"tx_q14_pkt", IPQESS_STAT(tx_q14_pkt)},
-+ {"tx_q15_pkt", IPQESS_STAT(tx_q15_pkt)},
-+ {"tx_q0_byte", IPQESS_STAT(tx_q0_byte)},
-+ {"tx_q1_byte", IPQESS_STAT(tx_q1_byte)},
-+ {"tx_q2_byte", IPQESS_STAT(tx_q2_byte)},
-+ {"tx_q3_byte", IPQESS_STAT(tx_q3_byte)},
-+ {"tx_q4_byte", IPQESS_STAT(tx_q4_byte)},
-+ {"tx_q5_byte", IPQESS_STAT(tx_q5_byte)},
-+ {"tx_q6_byte", IPQESS_STAT(tx_q6_byte)},
-+ {"tx_q7_byte", IPQESS_STAT(tx_q7_byte)},
-+ {"tx_q8_byte", IPQESS_STAT(tx_q8_byte)},
-+ {"tx_q9_byte", IPQESS_STAT(tx_q9_byte)},
-+ {"tx_q10_byte", IPQESS_STAT(tx_q10_byte)},
-+ {"tx_q11_byte", IPQESS_STAT(tx_q11_byte)},
-+ {"tx_q12_byte", IPQESS_STAT(tx_q12_byte)},
-+ {"tx_q13_byte", IPQESS_STAT(tx_q13_byte)},
-+ {"tx_q14_byte", IPQESS_STAT(tx_q14_byte)},
-+ {"tx_q15_byte", IPQESS_STAT(tx_q15_byte)},
-+ {"rx_q0_pkt", IPQESS_STAT(rx_q0_pkt)},
-+ {"rx_q1_pkt", IPQESS_STAT(rx_q1_pkt)},
-+ {"rx_q2_pkt", IPQESS_STAT(rx_q2_pkt)},
-+ {"rx_q3_pkt", IPQESS_STAT(rx_q3_pkt)},
-+ {"rx_q4_pkt", IPQESS_STAT(rx_q4_pkt)},
-+ {"rx_q5_pkt", IPQESS_STAT(rx_q5_pkt)},
-+ {"rx_q6_pkt", IPQESS_STAT(rx_q6_pkt)},
-+ {"rx_q7_pkt", IPQESS_STAT(rx_q7_pkt)},
-+ {"rx_q0_byte", IPQESS_STAT(rx_q0_byte)},
-+ {"rx_q1_byte", IPQESS_STAT(rx_q1_byte)},
-+ {"rx_q2_byte", IPQESS_STAT(rx_q2_byte)},
-+ {"rx_q3_byte", IPQESS_STAT(rx_q3_byte)},
-+ {"rx_q4_byte", IPQESS_STAT(rx_q4_byte)},
-+ {"rx_q5_byte", IPQESS_STAT(rx_q5_byte)},
-+ {"rx_q6_byte", IPQESS_STAT(rx_q6_byte)},
-+ {"rx_q7_byte", IPQESS_STAT(rx_q7_byte)},
-+ {"tx_desc_error", IPQESS_STAT(tx_desc_error)},
-+};
-+
-+static int ipqess_get_strset_count(struct net_device *netdev, int sset)
-+{
-+ switch (sset) {
-+ case ETH_SS_STATS:
-+ return ARRAY_SIZE(ipqess_stats);
-+ default:
-+ netdev_dbg(netdev, "%s: Unsupported string set", __func__);
-+ return -EOPNOTSUPP;
-+ }
-+}
-+
-+static void ipqess_get_strings(struct net_device *netdev, u32 stringset,
-+ u8 *data)
-+{
-+ u8 *p = data;
-+ u32 i;
-+
-+ switch (stringset) {
-+ case ETH_SS_STATS:
-+ for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++)
-+ ethtool_puts(&p, ipqess_stats[i].string);
-+ break;
-+ }
-+}
-+
-+static void ipqess_get_ethtool_stats(struct net_device *netdev,
-+ struct ethtool_stats *stats,
-+ uint64_t *data)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ u32 *essstats = (u32 *)&ess->ipqess_stats;
-+ int i;
-+
-+ spin_lock(&ess->stats_lock);
-+
-+ ipqess_update_hw_stats(ess);
-+
-+ for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++)
-+ data[i] = *(u32 *)(essstats + (ipqess_stats[i].offset / sizeof(u32)));
-+
-+ spin_unlock(&ess->stats_lock);
-+}
-+
-+static void ipqess_get_drvinfo(struct net_device *dev,
-+ struct ethtool_drvinfo *info)
-+{
-+ strscpy(info->driver, "qca_ipqess", DRVINFO_LEN);
-+ strscpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
-+}
-+
-+static int ipqess_get_link_ksettings(struct net_device *netdev,
-+ struct ethtool_link_ksettings *cmd)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ return phylink_ethtool_ksettings_get(ess->phylink, cmd);
-+}
-+
-+static int ipqess_set_link_ksettings(struct net_device *netdev,
-+ const struct ethtool_link_ksettings *cmd)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ return phylink_ethtool_ksettings_set(ess->phylink, cmd);
-+}
-+
-+static void ipqess_get_ringparam(struct net_device *netdev,
-+ struct ethtool_ringparam *ring,
-+ struct kernel_ethtool_ringparam *kernel_ering,
-+ struct netlink_ext_ack *extack)
-+{
-+ ring->tx_max_pending = IPQESS_TX_RING_SIZE;
-+ ring->rx_max_pending = IPQESS_RX_RING_SIZE;
-+}
-+
-+static const struct ethtool_ops ipqesstool_ops = {
-+ .get_drvinfo = &ipqess_get_drvinfo,
-+ .get_link = ðtool_op_get_link,
-+ .get_link_ksettings = &ipqess_get_link_ksettings,
-+ .set_link_ksettings = &ipqess_set_link_ksettings,
-+ .get_strings = &ipqess_get_strings,
-+ .get_sset_count = &ipqess_get_strset_count,
-+ .get_ethtool_stats = &ipqess_get_ethtool_stats,
-+ .get_ringparam = ipqess_get_ringparam,
-+};
-+
-+void ipqess_set_ethtool_ops(struct net_device *netdev)
-+{
-+ netdev->ethtool_ops = &ipqesstool_ops;
-+}
+++ /dev/null
-From a32e16b3c2fc1954ad6e09737439f60e5890278e Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:49 +0100
-Subject: [PATCH] net: dsa: add out-of-band tagging protocol
-
-This tagging protocol is designed for the situation where the link
-between the MAC and the Switch is designed such that the Destination
-Port, which is usually embedded in some part of the Ethernet Header, is
-sent out-of-band, and isn't present at all in the Ethernet frame.
-
-This can happen when the MAC and Switch are tightly integrated on an
-SoC, as is the case with the Qualcomm IPQ4019 for example, where the DSA
-tag is inserted directly into the DMA descriptors. In that case,
-the MAC driver is responsible for sending the tag to the switch using
-the out-of-band medium. To do so, the MAC driver needs to have the
-information of the destination port for that skb.
-
-Add a new tagging protocol based on SKB extensions to convey the
-information about the destination port to the MAC driver
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
----
- Documentation/networking/dsa/dsa.rst | 13 +++++++-
- MAINTAINERS | 1 +
- include/linux/dsa/oob.h | 16 +++++++++
- include/linux/skbuff.h | 3 ++
- include/net/dsa.h | 2 ++
- net/core/skbuff.c | 10 ++++++
- net/dsa/Kconfig | 9 +++++
- net/dsa/Makefile | 1 +
- net/dsa/tag_oob.c | 49 ++++++++++++++++++++++++++++
- 9 files changed, 103 insertions(+), 1 deletion(-)
- create mode 100644 include/linux/dsa/oob.h
- create mode 100644 net/dsa/tag_oob.c
-
---- a/Documentation/networking/dsa/dsa.rst
-+++ b/Documentation/networking/dsa/dsa.rst
-@@ -66,7 +66,8 @@ Switch tagging protocols
- ------------------------
-
- DSA supports many vendor-specific tagging protocols, one software-defined
--tagging protocol, and a tag-less mode as well (``DSA_TAG_PROTO_NONE``).
-+tagging protocol, a tag-less mode as well (``DSA_TAG_PROTO_NONE``) and an
-+out-of-band tagging protocol (``DSA_TAG_PROTO_OOB``).
-
- The exact format of the tag protocol is vendor specific, but in general, they
- all contain something which:
-@@ -217,6 +218,16 @@ receive all frames regardless of the val
- setting the ``promisc_on_master`` property of the ``struct dsa_device_ops``.
- Note that this assumes a DSA-unaware master driver, which is the norm.
-
-+Some SoCs have a tight integration between the conduit network interface and the
-+embedded switch, such that the DSA tag isn't transmitted in the packet data,
-+but through another media, using so-called out-of-band tagging. In that case,
-+the host MAC driver is in charge of transmitting the tag to the switch.
-+An example is the IPQ4019 SoC, that transmits the tag between the ipqess
-+ethernet controller and the qca8k switch using the DMA descriptor. In that
-+configuration, tag-chaining is permitted, but the OOB tag will always be the
-+top-most switch in the tree. The tagger (``DSA_TAG_PROTO_OOB``) uses skb
-+extensions to transmit the tag to and from the MAC driver.
-+
- Master network devices
- ----------------------
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -17081,6 +17081,7 @@ L: netdev@vger.kernel.org
- S: Maintained
- F: Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml
- F: drivers/net/ethernet/qualcomm/ipqess/
-+F: net/dsa/tag_oob.c
-
- QUALCOMM ETHQOS ETHERNET DRIVER
- M: Vinod Koul <vkoul@kernel.org>
---- /dev/null
-+++ b/include/linux/dsa/oob.h
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only
-+ * Copyright (C) 2022 Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ */
-+
-+#ifndef _NET_DSA_OOB_H
-+#define _NET_DSA_OOB_H
-+
-+#include <linux/skbuff.h>
-+
-+struct dsa_oob_tag_info {
-+ u16 port;
-+};
-+
-+int dsa_oob_tag_push(struct sk_buff *skb, struct dsa_oob_tag_info *ti);
-+int dsa_oob_tag_pop(struct sk_buff *skb, struct dsa_oob_tag_info *ti);
-+#endif
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -4588,6 +4588,9 @@ enum skb_ext_id {
- #if IS_ENABLED(CONFIG_MCTP_FLOWS)
- SKB_EXT_MCTP,
- #endif
-+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
-+ SKB_EXT_DSA_OOB,
-+#endif
- SKB_EXT_NUM, /* must be last */
- };
-
---- a/include/net/dsa.h
-+++ b/include/net/dsa.h
-@@ -55,6 +55,7 @@ struct phylink_link_state;
- #define DSA_TAG_PROTO_RTL8_4T_VALUE 25
- #define DSA_TAG_PROTO_RZN1_A5PSW_VALUE 26
- #define DSA_TAG_PROTO_LAN937X_VALUE 27
-+#define DSA_TAG_PROTO_OOB_VALUE 28
-
- enum dsa_tag_protocol {
- DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
-@@ -85,6 +86,7 @@ enum dsa_tag_protocol {
- DSA_TAG_PROTO_RTL8_4T = DSA_TAG_PROTO_RTL8_4T_VALUE,
- DSA_TAG_PROTO_RZN1_A5PSW = DSA_TAG_PROTO_RZN1_A5PSW_VALUE,
- DSA_TAG_PROTO_LAN937X = DSA_TAG_PROTO_LAN937X_VALUE,
-+ DSA_TAG_PROTO_OOB = DSA_TAG_PROTO_OOB_VALUE,
- };
-
- struct dsa_switch;
---- a/net/core/skbuff.c
-+++ b/net/core/skbuff.c
-@@ -62,8 +62,12 @@
- #include <linux/mpls.h>
- #include <linux/kcov.h>
- #include <linux/if.h>
-+#ifdef CONFIG_NET_DSA_TAG_OOB
-+#include <linux/dsa/oob.h>
-+#endif
-
- #include <net/protocol.h>
-+#include <net/dsa.h>
- #include <net/dst.h>
- #include <net/sock.h>
- #include <net/checksum.h>
-@@ -4517,6 +4521,9 @@ static const u8 skb_ext_type_len[] = {
- #if IS_ENABLED(CONFIG_MCTP_FLOWS)
- [SKB_EXT_MCTP] = SKB_EXT_CHUNKSIZEOF(struct mctp_flow),
- #endif
-+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
-+ [SKB_EXT_DSA_OOB] = SKB_EXT_CHUNKSIZEOF(struct dsa_oob_tag_info),
-+#endif
- };
-
- static __always_inline unsigned int skb_ext_total_length(void)
-@@ -4537,6 +4544,9 @@ static __always_inline unsigned int skb_
- #if IS_ENABLED(CONFIG_MCTP_FLOWS)
- skb_ext_type_len[SKB_EXT_MCTP] +
- #endif
-+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
-+ skb_ext_type_len[SKB_EXT_DSA_OOB] +
-+#endif
- 0;
- }
-
---- a/net/dsa/Kconfig
-+++ b/net/dsa/Kconfig
-@@ -113,6 +113,15 @@ config NET_DSA_TAG_OCELOT_8021Q
- this mode, less TCAM resources (VCAP IS1, IS2, ES0) are available for
- use with tc-flower.
-
-+config NET_DSA_TAG_OOB
-+ select SKB_EXTENSIONS
-+ tristate "Tag driver for Out-of-band tagging drivers"
-+ help
-+ Say Y or M if you want to enable support for pairs of embedded
-+ switches and host MAC drivers which perform demultiplexing and
-+ packet steering to ports using out of band metadata processed
-+ by the DSA master, rather than tags present in the packets.
-+
- config NET_DSA_TAG_QCA
- tristate "Tag driver for Qualcomm Atheros QCA8K switches"
- help
---- a/net/dsa/Makefile
-+++ b/net/dsa/Makefile
-@@ -22,6 +22,7 @@ obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag
- obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
- obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o
- obj-$(CONFIG_NET_DSA_TAG_OCELOT_8021Q) += tag_ocelot_8021q.o
-+obj-$(CONFIG_NET_DSA_TAG_OOB) += tag_oob.o
- obj-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca.o
- obj-$(CONFIG_NET_DSA_TAG_RTL4_A) += tag_rtl4_a.o
- obj-$(CONFIG_NET_DSA_TAG_RTL8_4) += tag_rtl8_4.o
---- /dev/null
-+++ b/net/dsa/tag_oob.c
-@@ -0,0 +1,49 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+/* Copyright (c) 2022, Maxime Chevallier <maxime.chevallier@bootlin.com> */
-+
-+#include <linux/bitfield.h>
-+#include <linux/dsa/oob.h>
-+#include <linux/skbuff.h>
-+
-+#include "dsa_priv.h"
-+
-+static struct sk_buff *oob_tag_xmit(struct sk_buff *skb,
-+ struct net_device *dev)
-+{
-+ struct dsa_oob_tag_info *tag_info = skb_ext_add(skb, SKB_EXT_DSA_OOB);
-+ struct dsa_port *dp = dsa_slave_to_port(dev);
-+
-+ tag_info->port = dp->index;
-+
-+ return skb;
-+}
-+
-+static struct sk_buff *oob_tag_rcv(struct sk_buff *skb,
-+ struct net_device *dev)
-+{
-+ struct dsa_oob_tag_info *tag_info = skb_ext_find(skb, SKB_EXT_DSA_OOB);
-+
-+ if (!tag_info)
-+ return NULL;
-+
-+ skb->dev = dsa_master_find_slave(dev, 0, tag_info->port);
-+ if (!skb->dev)
-+ return NULL;
-+
-+ return skb;
-+}
-+
-+static const struct dsa_device_ops oob_tag_dsa_ops = {
-+ .name = "oob",
-+ .proto = DSA_TAG_PROTO_OOB,
-+ .xmit = oob_tag_xmit,
-+ .rcv = oob_tag_rcv,
-+};
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("DSA tag driver for out-of-band tagging");
-+MODULE_AUTHOR("Maxime Chevallier <maxime.chevallier@bootlin.com>");
-+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_OOB);
-+
-+module_dsa_tag_driver(oob_tag_dsa_ops);
+++ /dev/null
-From 4975e2b3f1d37bba04f262784cef0d5b7e0a30a4 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:50 +0100
-Subject: [PATCH] net: ipqess: Add out-of-band DSA tagging support
-
-On the IPQ4019, there's an 5 ports switch connected to the CPU through
-the IPQESS Ethernet controller. The way the DSA tag is sent-out to that
-switch is through the DMA descriptor, due to how tightly it is
-integrated with the switch.
-
-We use the out-of-band tagging protocol by getting the source
-port from the descriptor, push it into the skb extensions, and have the
-tagger pull it to infer the destination netdev. The reverse process is
-done on the TX side, where the driver pulls the tag from the skb and
-builds the descriptor accordingly.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
----
- drivers/net/ethernet/qualcomm/Kconfig | 1 +
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 64 ++++++++++++++++++-
- drivers/net/ethernet/qualcomm/ipqess/ipqess.h | 4 ++
- 3 files changed, 68 insertions(+), 1 deletion(-)
-
---- a/drivers/net/ethernet/qualcomm/Kconfig
-+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -64,6 +64,7 @@ config QCOM_IPQ4019_ESS_EDMA
- tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
- depends on (OF && ARCH_QCOM) || COMPILE_TEST
- select PHYLINK
-+ select NET_DSA_TAG_OOB
- help
- This driver supports the Qualcomm Atheros IPQ40xx built-in
- ESS EDMA ethernet controller.
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -9,6 +9,7 @@
-
- #include <linux/bitfield.h>
- #include <linux/clk.h>
-+#include <linux/dsa/oob.h>
- #include <linux/if_vlan.h>
- #include <linux/interrupt.h>
- #include <linux/module.h>
-@@ -22,6 +23,7 @@
- #include <linux/skbuff.h>
- #include <linux/vmalloc.h>
- #include <net/checksum.h>
-+#include <net/dsa.h>
- #include <net/ip6_checksum.h>
-
- #include "ipqess.h"
-@@ -327,6 +329,7 @@ static int ipqess_rx_poll(struct ipqess_
- tail &= IPQESS_RFD_CONS_IDX_MASK;
-
- while (done < budget) {
-+ struct dsa_oob_tag_info *tag_info;
- struct ipqess_rx_desc *rd;
- struct sk_buff *skb;
-
-@@ -406,6 +409,12 @@ static int ipqess_rx_poll(struct ipqess_
- __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
- le16_to_cpu(rd->rrd4));
-
-+ if (likely(rx_ring->ess->dsa_ports)) {
-+ tag_info = skb_ext_add(skb, SKB_EXT_DSA_OOB);
-+ tag_info->port = FIELD_GET(IPQESS_RRD_PORT_ID_MASK,
-+ le16_to_cpu(rd->rrd1));
-+ }
-+
- napi_gro_receive(&rx_ring->napi_rx, skb);
-
- rx_ring->ess->stats.rx_packets++;
-@@ -706,6 +715,23 @@ static void ipqess_rollback_tx(struct ip
- tx_ring->head = start_index;
- }
-
-+static void ipqess_process_dsa_tag_sh(struct ipqess *ess, struct sk_buff *skb,
-+ u32 *word3)
-+{
-+ struct dsa_oob_tag_info *tag_info;
-+
-+ if (unlikely(!ess->dsa_ports))
-+ return;
-+
-+ tag_info = skb_ext_find(skb, SKB_EXT_DSA_OOB);
-+ if (!tag_info)
-+ return;
-+
-+ *word3 |= tag_info->port << IPQESS_TPD_PORT_BITMAP_SHIFT;
-+ *word3 |= BIT(IPQESS_TPD_FROM_CPU_SHIFT);
-+ *word3 |= 0x3e << IPQESS_TPD_PORT_BITMAP_SHIFT;
-+}
-+
- static int ipqess_tx_map_and_fill(struct ipqess_tx_ring *tx_ring,
- struct sk_buff *skb)
- {
-@@ -716,6 +742,8 @@ static int ipqess_tx_map_and_fill(struct
- u16 len;
- int i;
-
-+ ipqess_process_dsa_tag_sh(tx_ring->ess, skb, &word3);
-+
- if (skb_is_gso(skb)) {
- if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
- lso_word1 |= IPQESS_TPD_IPV4_EN;
-@@ -917,6 +945,33 @@ static const struct net_device_ops ipqes
- .ndo_tx_timeout = ipqess_tx_timeout,
- };
-
-+static int ipqess_netdevice_event(struct notifier_block *nb,
-+ unsigned long event, void *ptr)
-+{
-+ struct ipqess *ess = container_of(nb, struct ipqess, netdev_notifier);
-+ struct net_device *dev = netdev_notifier_info_to_dev(ptr);
-+ struct netdev_notifier_changeupper_info *info;
-+
-+ if (dev != ess->netdev)
-+ return NOTIFY_DONE;
-+
-+ switch (event) {
-+ case NETDEV_CHANGEUPPER:
-+ info = ptr;
-+
-+ if (!dsa_slave_dev_check(info->upper_dev))
-+ return NOTIFY_DONE;
-+
-+ if (info->linking)
-+ ess->dsa_ports++;
-+ else
-+ ess->dsa_ports--;
-+
-+ return NOTIFY_DONE;
-+ }
-+ return NOTIFY_OK;
-+}
-+
- static void ipqess_hw_stop(struct ipqess *ess)
- {
- int i;
-@@ -1184,12 +1239,19 @@ static int ipqess_axi_probe(struct platf
- netif_napi_add(netdev, &ess->rx_ring[i].napi_rx, ipqess_rx_napi);
- }
-
-- err = register_netdev(netdev);
-+ ess->netdev_notifier.notifier_call = ipqess_netdevice_event;
-+ err = register_netdevice_notifier(&ess->netdev_notifier);
- if (err)
- goto err_hw_stop;
-
-+ err = register_netdev(netdev);
-+ if (err)
-+ goto err_notifier_unregister;
-+
- return 0;
-
-+err_notifier_unregister:
-+ unregister_netdevice_notifier(&ess->netdev_notifier);
- err_hw_stop:
- ipqess_hw_stop(ess);
-
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
-@@ -171,6 +171,10 @@ struct ipqess {
- struct platform_device *pdev;
- struct phylink *phylink;
- struct phylink_config phylink_config;
-+
-+ struct notifier_block netdev_notifier;
-+ int dsa_ports;
-+
- struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES];
-
- struct ipqess_statistics ipqess_stats;
+++ /dev/null
-From 5f15f7f170c76220dfd36cb9037d7848d1fc4aaf Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 15 Aug 2023 14:30:50 +0200
-Subject: [PATCH] net: qualcomm: ipqess: release IRQ-s on network device stop
-
-Currently, IPQESS driver is obtaining the IRQ-s during ndo_open, but they
-are never freed as they are device managed.
-
-However, it is not enough for them to be released when device is removed
-as the same network device can be stopped and started multiple times which
-on the second start would lead to IRQ request to fail with -EBUSY as they
-have already been requested before and are not of the shared type with:
-[ 34.480769] ipqess-edma c080000.ethernet eth0: Link is Down
-[ 34.488070] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.488131] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.494527] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.502892] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.508137] qca8k-ipq4019 c000000.switch lan1: failed to open master eth0
-[ 34.518966] br-lan: port 1(lan1) entered blocking state
-[ 34.525165] br-lan: port 1(lan1) entered disabled state
-[ 34.530633] device lan1 entered promiscuous mode
-[ 34.548598] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.548660] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.553111] qca8k-ipq4019 c000000.switch lan2: failed to open master eth0
-[ 34.563841] br-lan: port 2(lan2) entered blocking state
-[ 34.570083] br-lan: port 2(lan2) entered disabled state
-[ 34.575530] device lan2 entered promiscuous mode
-[ 34.587067] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.587132] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.591579] qca8k-ipq4019 c000000.switch lan3: failed to open master eth0
-[ 34.602451] br-lan: port 3(lan3) entered blocking state
-[ 34.608496] br-lan: port 3(lan3) entered disabled state
-[ 34.614084] device lan3 entered promiscuous mode
-[ 34.626405] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.626468] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.630871] qca8k-ipq4019 c000000.switch lan4: failed to open master eth0
-[ 34.641689] br-lan: port 4(lan4) entered blocking state
-[ 34.647834] br-lan: port 4(lan4) entered disabled state
-[ 34.653455] device lan4 entered promiscuous mode
-[ 34.667282] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.667364] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.671830] qca8k-ipq4019 c000000.switch wan: failed to open master eth0
-
-So, lets free the IRQ-s on ndo_stop after stopping NAPI and HW IRQ-s.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -636,9 +636,22 @@ static int ipqess_stop(struct net_device
- netif_tx_stop_all_queues(netdev);
- phylink_stop(ess->phylink);
- ipqess_irq_disable(ess);
-+
- for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ int qid;
-+
- napi_disable(&ess->tx_ring[i].napi_tx);
- napi_disable(&ess->rx_ring[i].napi_rx);
-+
-+ qid = ess->tx_ring[i].idx;
-+ devm_free_irq(&netdev->dev,
-+ ess->tx_irq[qid],
-+ &ess->tx_ring[i]);
-+
-+ qid = ess->rx_ring[i].idx;
-+ devm_free_irq(&netdev->dev,
-+ ess->rx_irq[qid],
-+ &ess->rx_ring[i]);
- }
-
- return 0;
+++ /dev/null
-From 9fa4a57a65e270e4d579cace4de5c438f46c7d12 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 15 Aug 2023 14:38:44 +0200
-Subject: [PATCH] net: qualcomm: ipqess: enable threaded NAPI by default
-
-Threaded NAPI provides a nice performance boost, so lets enable it by
-default.
-
-We do however need to move the __napi_schedule() after HW IRQ has been
-cleared in order to avoid concurency issues.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -530,9 +530,9 @@ static irqreturn_t ipqess_interrupt_tx(i
- struct ipqess_tx_ring *tx_ring = (struct ipqess_tx_ring *)priv;
-
- if (likely(napi_schedule_prep(&tx_ring->napi_tx))) {
-- __napi_schedule(&tx_ring->napi_tx);
- ipqess_w32(tx_ring->ess, IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx),
- 0x0);
-+ __napi_schedule(&tx_ring->napi_tx);
- }
-
- return IRQ_HANDLED;
-@@ -543,9 +543,9 @@ static irqreturn_t ipqess_interrupt_rx(i
- struct ipqess_rx_ring *rx_ring = (struct ipqess_rx_ring *)priv;
-
- if (likely(napi_schedule_prep(&rx_ring->napi_rx))) {
-- __napi_schedule(&rx_ring->napi_rx);
- ipqess_w32(rx_ring->ess, IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx),
- 0x0);
-+ __napi_schedule(&rx_ring->napi_rx);
- }
-
- return IRQ_HANDLED;
-@@ -1261,6 +1261,8 @@ static int ipqess_axi_probe(struct platf
- if (err)
- goto err_notifier_unregister;
-
-+ dev_set_threaded(netdev, true);
-+
- return 0;
-
- err_notifier_unregister:
+++ /dev/null
-From 5b71dbb867680887d47954ce1cc145cb747cbce6 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:51 +0100
-Subject: [PATCH] ARM: dts: qcom: ipq4019: Add description for the IPQESS
- Ethernet controller
-
-The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
-connected to the CPU through the internal IPQESS Ethernet controller.
-
-Add support for this internal interface, which is internally connected to a
-modified version of the QCA8K Ethernet switch.
-
-This Ethernet controller only support a specific internal interface mode
-for connection to the switch.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
- 1 file changed, 48 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -594,6 +594,54 @@
- status = "disabled";
- };
-
-+ gmac: ethernet@c080000 {
-+ compatible = "qcom,ipq4019-ess-edma";
-+ reg = <0xc080000 0x8000>;
-+ resets = <&gcc ESS_RESET>;
-+ reset-names = "ess";
-+ clocks = <&gcc GCC_ESS_CLK>;
-+ clock-names = "ess";
-+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
-+ phy-mode = "internal";
-+ status = "disabled";
-+ fixed-link {
-+ speed = <1000>;
-+ full-duplex;
-+ pause;
-+ };
-+ };
-+
- mdio: mdio@90000 {
- #address-cells = <1>;
- #size-cells = <0>;
+++ /dev/null
-From a38126870488398932e017dd9d76174b4aadbbbb Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Sat, 10 Sep 2022 15:46:09 +0200
-Subject: [PATCH] net: dsa: qca8k: add IPQ4019 built-in switch support
-
-Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
-
-It shares most of the stuff with its external counterpart, however it is
-modified for the SoC.
-Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
-instead of 7.
-It also has no built-in PHY-s but rather requires external PSGMII based
-companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
-out calibration before using them.
-PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
-unfortunately requires some magic values as the datasheet doesnt document
-the bits that are being set or the register at all.
-
-Since its built-in it is MMIO like other peripherals and doesn't have its
-own MDIO bus but depends on the SoC provided one.
-
-CPU connection is at Port 0 and it uses some kind of a internal connection
-and no traditional RGMII/SGMII.
-
-It also doesn't use in-band tagging like other qca8k switches so a out of
-band based tagger is used.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/net/dsa/qca/Kconfig | 8 +
- drivers/net/dsa/qca/Makefile | 1 +
- drivers/net/dsa/qca/qca8k-common.c | 6 +-
- drivers/net/dsa/qca/qca8k-ipq4019.c | 948 ++++++++++++++++++++++++++++
- drivers/net/dsa/qca/qca8k.h | 56 ++
- 5 files changed, 1016 insertions(+), 3 deletions(-)
- create mode 100644 drivers/net/dsa/qca/qca8k-ipq4019.c
-
---- a/drivers/net/dsa/qca/Kconfig
-+++ b/drivers/net/dsa/qca/Kconfig
-@@ -23,3 +23,11 @@ config NET_DSA_QCA8K_LEDS_SUPPORT
- help
- This enabled support for LEDs present on the Qualcomm Atheros
- QCA8K Ethernet switch chips.
-+
-+config NET_DSA_QCA8K_IPQ4019
-+ tristate "Qualcomm Atheros IPQ4019 Ethernet switch support"
-+ select NET_DSA_TAG_OOB
-+ select REGMAP_MMIO
-+ help
-+ This enables support for the switch built-into Qualcomm Atheros
-+ IPQ4019 SoCs.
---- a/drivers/net/dsa/qca/Makefile
-+++ b/drivers/net/dsa/qca/Makefile
-@@ -5,3 +5,4 @@ qca8k-y += qca8k-common.o qca8k-8xxx.
- ifdef CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT
- qca8k-y += qca8k-leds.o
- endif
-+obj-$(CONFIG_NET_DSA_QCA8K_IPQ4019) += qca8k-ipq4019.o qca8k-common.o
---- a/drivers/net/dsa/qca/qca8k-common.c
-+++ b/drivers/net/dsa/qca/qca8k-common.c
-@@ -412,7 +412,7 @@ static int qca8k_vlan_del(struct qca8k_p
-
- /* Check if we're the last member to be removed */
- del = true;
-- for (i = 0; i < QCA8K_NUM_PORTS; i++) {
-+ for (i = 0; i < priv->ds->num_ports; i++) {
- mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
-
- if ((reg & mask) != mask) {
-@@ -653,7 +653,7 @@ int qca8k_port_bridge_join(struct dsa_sw
- cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
- port_mask = BIT(cpu_port);
-
-- for (i = 0; i < QCA8K_NUM_PORTS; i++) {
-+ for (i = 0; i < ds->num_ports; i++) {
- if (dsa_is_cpu_port(ds, i))
- continue;
- if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
-@@ -685,7 +685,7 @@ void qca8k_port_bridge_leave(struct dsa_
-
- cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
-
-- for (i = 0; i < QCA8K_NUM_PORTS; i++) {
-+ for (i = 0; i < ds->num_ports; i++) {
- if (dsa_is_cpu_port(ds, i))
- continue;
- if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
---- /dev/null
-+++ b/drivers/net/dsa/qca/qca8k-ipq4019.c
-@@ -0,0 +1,948 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
-+ * Copyright (C) 2011-2012, 2020-2021 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2016 John Crispin <john@phrozen.org>
-+ * Copyright (c) 2022 Robert Marko <robert.marko@sartura.hr>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/phy.h>
-+#include <linux/netdevice.h>
-+#include <linux/bitfield.h>
-+#include <linux/regmap.h>
-+#include <net/dsa.h>
-+#include <linux/of_net.h>
-+#include <linux/of_mdio.h>
-+#include <linux/of_platform.h>
-+#include <linux/mdio.h>
-+#include <linux/phylink.h>
-+
-+#include "qca8k.h"
-+
-+static struct regmap_config qca8k_ipq4019_regmap_config = {
-+ .reg_bits = 32,
-+ .val_bits = 32,
-+ .reg_stride = 4,
-+ .max_register = 0x16ac, /* end MIB - Port6 range */
-+ .rd_table = &qca8k_readable_table,
-+};
-+
-+static struct regmap_config qca8k_ipq4019_psgmii_phy_regmap_config = {
-+ .name = "psgmii-phy",
-+ .reg_bits = 32,
-+ .val_bits = 32,
-+ .reg_stride = 4,
-+ .max_register = 0x7fc,
-+};
-+
-+static enum dsa_tag_protocol
-+qca8k_ipq4019_get_tag_protocol(struct dsa_switch *ds, int port,
-+ enum dsa_tag_protocol mp)
-+{
-+ return DSA_TAG_PROTO_OOB;
-+}
-+
-+static struct phylink_pcs *
-+qca8k_ipq4019_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
-+ phy_interface_t interface)
-+{
-+ struct qca8k_priv *priv = ds->priv;
-+ struct phylink_pcs *pcs = NULL;
-+
-+ switch (interface) {
-+ case PHY_INTERFACE_MODE_PSGMII:
-+ switch (port) {
-+ case 0:
-+ pcs = &priv->pcs_port_0.pcs;
-+ break;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ return pcs;
-+}
-+
-+static int qca8k_ipq4019_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
-+ phy_interface_t interface,
-+ const unsigned long *advertising,
-+ bool permit_pause_to_mac)
-+{
-+ return 0;
-+}
-+
-+static void qca8k_ipq4019_pcs_an_restart(struct phylink_pcs *pcs)
-+{
-+}
-+
-+static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs)
-+{
-+ return container_of(pcs, struct qca8k_pcs, pcs);
-+}
-+
-+static void qca8k_ipq4019_pcs_get_state(struct phylink_pcs *pcs,
-+ struct phylink_link_state *state)
-+{
-+ struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
-+ int port = pcs_to_qca8k_pcs(pcs)->port;
-+ u32 reg;
-+ int ret;
-+
-+ ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®);
-+ if (ret < 0) {
-+ state->link = false;
-+ return;
-+ }
-+
-+ state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
-+ state->an_complete = state->link;
-+ state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
-+ DUPLEX_HALF;
-+
-+ switch (reg & QCA8K_PORT_STATUS_SPEED) {
-+ case QCA8K_PORT_STATUS_SPEED_10:
-+ state->speed = SPEED_10;
-+ break;
-+ case QCA8K_PORT_STATUS_SPEED_100:
-+ state->speed = SPEED_100;
-+ break;
-+ case QCA8K_PORT_STATUS_SPEED_1000:
-+ state->speed = SPEED_1000;
-+ break;
-+ default:
-+ state->speed = SPEED_UNKNOWN;
-+ break;
-+ }
-+
-+ if (reg & QCA8K_PORT_STATUS_RXFLOW)
-+ state->pause |= MLO_PAUSE_RX;
-+ if (reg & QCA8K_PORT_STATUS_TXFLOW)
-+ state->pause |= MLO_PAUSE_TX;
-+}
-+
-+static const struct phylink_pcs_ops qca8k_pcs_ops = {
-+ .pcs_get_state = qca8k_ipq4019_pcs_get_state,
-+ .pcs_config = qca8k_ipq4019_pcs_config,
-+ .pcs_an_restart = qca8k_ipq4019_pcs_an_restart,
-+};
-+
-+static void qca8k_ipq4019_setup_pcs(struct qca8k_priv *priv,
-+ struct qca8k_pcs *qpcs,
-+ int port)
-+{
-+ qpcs->pcs.ops = &qca8k_pcs_ops;
-+
-+ /* We don't have interrupts for link changes, so we need to poll */
-+ qpcs->pcs.poll = true;
-+ qpcs->priv = priv;
-+ qpcs->port = port;
-+}
-+
-+static void qca8k_ipq4019_phylink_get_caps(struct dsa_switch *ds, int port,
-+ struct phylink_config *config)
-+{
-+ switch (port) {
-+ case 0: /* CPU port */
-+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
-+ config->supported_interfaces);
-+ break;
-+
-+ case 1:
-+ case 2:
-+ case 3:
-+ __set_bit(PHY_INTERFACE_MODE_PSGMII,
-+ config->supported_interfaces);
-+ break;
-+ case 4:
-+ case 5:
-+ phy_interface_set_rgmii(config->supported_interfaces);
-+ __set_bit(PHY_INTERFACE_MODE_PSGMII,
-+ config->supported_interfaces);
-+ break;
-+ }
-+
-+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
-+ MAC_10 | MAC_100 | MAC_1000FD;
-+
-+ config->legacy_pre_march2020 = false;
-+}
-+
-+static void
-+qca8k_phylink_ipq4019_mac_link_down(struct dsa_switch *ds, int port,
-+ unsigned int mode,
-+ phy_interface_t interface)
-+{
-+ struct qca8k_priv *priv = ds->priv;
-+
-+ qca8k_port_set_status(priv, port, 0);
-+}
-+
-+static void
-+qca8k_phylink_ipq4019_mac_link_up(struct dsa_switch *ds, int port,
-+ unsigned int mode, phy_interface_t interface,
-+ struct phy_device *phydev, int speed,
-+ int duplex, bool tx_pause, bool rx_pause)
-+{
-+ struct qca8k_priv *priv = ds->priv;
-+ u32 reg;
-+
-+ if (phylink_autoneg_inband(mode)) {
-+ reg = QCA8K_PORT_STATUS_LINK_AUTO;
-+ } else {
-+ switch (speed) {
-+ case SPEED_10:
-+ reg = QCA8K_PORT_STATUS_SPEED_10;
-+ break;
-+ case SPEED_100:
-+ reg = QCA8K_PORT_STATUS_SPEED_100;
-+ break;
-+ case SPEED_1000:
-+ reg = QCA8K_PORT_STATUS_SPEED_1000;
-+ break;
-+ default:
-+ reg = QCA8K_PORT_STATUS_LINK_AUTO;
-+ break;
-+ }
-+
-+ if (duplex == DUPLEX_FULL)
-+ reg |= QCA8K_PORT_STATUS_DUPLEX;
-+
-+ if (rx_pause || dsa_is_cpu_port(ds, port))
-+ reg |= QCA8K_PORT_STATUS_RXFLOW;
-+
-+ if (tx_pause || dsa_is_cpu_port(ds, port))
-+ reg |= QCA8K_PORT_STATUS_TXFLOW;
-+ }
-+
-+ reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
-+
-+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
-+}
-+
-+static int psgmii_vco_calibrate(struct qca8k_priv *priv)
-+{
-+ int val, ret;
-+
-+ if (!priv->psgmii_ethphy) {
-+ dev_err(priv->dev, "PSGMII eth PHY missing, calibration failed!\n");
-+ return -ENODEV;
-+ }
-+
-+ /* Fix PSGMII RX 20bit */
-+ ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
-+ /* Reset PHY PSGMII */
-+ ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x1b);
-+ /* Release PHY PSGMII reset */
-+ ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
-+
-+ /* Poll for VCO PLL calibration finish - Malibu(QCA8075) */
-+ ret = phy_read_mmd_poll_timeout(priv->psgmii_ethphy,
-+ MDIO_MMD_PMAPMD,
-+ 0x28, val,
-+ (val & BIT(0)),
-+ 10000, 1000000,
-+ false);
-+ if (ret) {
-+ dev_err(priv->dev, "QCA807x PSGMII VCO calibration PLL not ready\n");
-+ return ret;
-+ }
-+ mdelay(50);
-+
-+ /* Freeze PSGMII RX CDR */
-+ ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x2230);
-+
-+ /* Start PSGMIIPHY VCO PLL calibration */
-+ ret = regmap_set_bits(priv->psgmii,
-+ PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1,
-+ PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART);
-+
-+ /* Poll for PSGMIIPHY PLL calibration finish - Dakota(IPQ40xx) */
-+ ret = regmap_read_poll_timeout(priv->psgmii,
-+ PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2,
-+ val, val & PSGMIIPHY_REG_PLL_VCO_CALIB_READY,
-+ 10000, 1000000);
-+ if (ret) {
-+ dev_err(priv->dev, "IPQ PSGMIIPHY VCO calibration PLL not ready\n");
-+ return ret;
-+ }
-+ mdelay(50);
-+
-+ /* Release PSGMII RX CDR */
-+ ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x3230);
-+ /* Release PSGMII RX 20bit */
-+ ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5f);
-+ mdelay(200);
-+
-+ return ret;
-+}
-+
-+static void
-+qca8k_switch_port_loopback_on_off(struct qca8k_priv *priv, int port, int on)
-+{
-+ u32 val = QCA8K_PORT_LOOKUP_LOOPBACK_EN;
-+
-+ if (on == 0)
-+ val = 0;
-+
-+ qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
-+ QCA8K_PORT_LOOKUP_LOOPBACK_EN, val);
-+}
-+
-+static int
-+qca8k_wait_for_phy_link_state(struct phy_device *phy, int need_status)
-+{
-+ int a;
-+ u16 status;
-+
-+ for (a = 0; a < 100; a++) {
-+ status = phy_read(phy, MII_QCA8075_SSTATUS);
-+ status &= QCA8075_PHY_SPEC_STATUS_LINK;
-+ status = !!status;
-+ if (status == need_status)
-+ return 0;
-+ mdelay(8);
-+ }
-+
-+ return -1;
-+}
-+
-+static void
-+qca8k_phy_loopback_on_off(struct qca8k_priv *priv, struct phy_device *phy,
-+ int sw_port, int on)
-+{
-+ if (on) {
-+ phy_write(phy, MII_BMCR, BMCR_ANENABLE | BMCR_RESET);
-+ phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
-+ qca8k_wait_for_phy_link_state(phy, 0);
-+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
-+ phy_write(phy, MII_BMCR,
-+ BMCR_SPEED1000 |
-+ BMCR_FULLDPLX |
-+ BMCR_LOOPBACK);
-+ qca8k_wait_for_phy_link_state(phy, 1);
-+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port),
-+ QCA8K_PORT_STATUS_SPEED_1000 |
-+ QCA8K_PORT_STATUS_TXMAC |
-+ QCA8K_PORT_STATUS_RXMAC |
-+ QCA8K_PORT_STATUS_DUPLEX);
-+ qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
-+ QCA8K_PORT_LOOKUP_STATE_FORWARD,
-+ QCA8K_PORT_LOOKUP_STATE_FORWARD);
-+ } else { /* off */
-+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
-+ qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
-+ QCA8K_PORT_LOOKUP_STATE_DISABLED,
-+ QCA8K_PORT_LOOKUP_STATE_DISABLED);
-+ phy_write(phy, MII_BMCR, BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_RESET);
-+ /* turn off the power of the phys - so that unused
-+ ports do not raise links */
-+ phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
-+ }
-+}
-+
-+static void
-+qca8k_phy_pkt_gen_prep(struct qca8k_priv *priv, struct phy_device *phy,
-+ int pkts_num, int on)
-+{
-+ if (on) {
-+ /* enable CRC checker and packets counters */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT,
-+ QCA8075_MMD7_CNT_FRAME_CHK_EN | QCA8075_MMD7_CNT_SELFCLR);
-+ qca8k_wait_for_phy_link_state(phy, 1);
-+ /* packet number */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, pkts_num);
-+ /* pkt size - 1504 bytes + 20 bytes */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_SIZE, 1504);
-+ } else { /* off */
-+ /* packet number */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, 0);
-+ /* disable CRC checker and packet counter */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
-+ /* disable traffic gen */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL, 0);
-+ }
-+}
-+
-+static void
-+qca8k_wait_for_phy_pkt_gen_fin(struct qca8k_priv *priv, struct phy_device *phy)
-+{
-+ int val;
-+ /* wait for all traffic end: 4096(pkt num)*1524(size)*8ns(125MHz)=49938us */
-+ phy_read_mmd_poll_timeout(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
-+ val, !(val & QCA8075_MMD7_PKT_GEN_INPROGR),
-+ 50000, 1000000, true);
-+}
-+
-+static void
-+qca8k_start_phy_pkt_gen(struct phy_device *phy)
-+{
-+ /* start traffic gen */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
-+ QCA8075_MMD7_PKT_GEN_START | QCA8075_MMD7_PKT_GEN_INPROGR);
-+}
-+
-+static int
-+qca8k_start_all_phys_pkt_gens(struct qca8k_priv *priv)
-+{
-+ struct phy_device *phy;
-+ phy = phy_device_create(priv->bus, QCA8075_MDIO_BRDCST_PHY_ADDR,
-+ 0, 0, NULL);
-+ if (!phy) {
-+ dev_err(priv->dev, "unable to create mdio broadcast PHY(0x%x)\n",
-+ QCA8075_MDIO_BRDCST_PHY_ADDR);
-+ return -ENODEV;
-+ }
-+
-+ qca8k_start_phy_pkt_gen(phy);
-+
-+ phy_device_free(phy);
-+ return 0;
-+}
-+
-+static int
-+qca8k_get_phy_pkt_gen_test_result(struct phy_device *phy, int pkts_num)
-+{
-+ u32 tx_ok, tx_error;
-+ u32 rx_ok, rx_error;
-+ u32 tx_ok_high16;
-+ u32 rx_ok_high16;
-+ u32 tx_all_ok, rx_all_ok;
-+
-+ /* check counters */
-+ tx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_LO);
-+ tx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_HI);
-+ tx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_ERR_CNT);
-+ rx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_LO);
-+ rx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_HI);
-+ rx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_ERR_CNT);
-+ tx_all_ok = tx_ok + (tx_ok_high16 << 16);
-+ rx_all_ok = rx_ok + (rx_ok_high16 << 16);
-+
-+ if (tx_all_ok < pkts_num)
-+ return -1;
-+ if(rx_all_ok < pkts_num)
-+ return -2;
-+ if(tx_error)
-+ return -3;
-+ if(rx_error)
-+ return -4;
-+ return 0; /* test is ok */
-+}
-+
-+static
-+void qca8k_phy_broadcast_write_on_off(struct qca8k_priv *priv,
-+ struct phy_device *phy, int on)
-+{
-+ u32 val;
-+
-+ val = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE);
-+
-+ if (on == 0)
-+ val &= ~QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
-+ else
-+ val |= QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
-+
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE, val);
-+}
-+
-+static int
-+qca8k_test_dsa_port_for_errors(struct qca8k_priv *priv, struct phy_device *phy,
-+ int port, int test_phase)
-+{
-+ int res = 0;
-+ const int test_pkts_num = QCA8075_PKT_GEN_PKTS_COUNT;
-+
-+ if (test_phase == 1) { /* start test preps */
-+ qca8k_phy_loopback_on_off(priv, phy, port, 1);
-+ qca8k_switch_port_loopback_on_off(priv, port, 1);
-+ qca8k_phy_broadcast_write_on_off(priv, phy, 1);
-+ qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 1);
-+ } else if (test_phase == 2) {
-+ /* wait for test results, collect it and cleanup */
-+ qca8k_wait_for_phy_pkt_gen_fin(priv, phy);
-+ res = qca8k_get_phy_pkt_gen_test_result(phy, test_pkts_num);
-+ qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 0);
-+ qca8k_phy_broadcast_write_on_off(priv, phy, 0);
-+ qca8k_switch_port_loopback_on_off(priv, port, 0);
-+ qca8k_phy_loopback_on_off(priv, phy, port, 0);
-+ }
-+
-+ return res;
-+}
-+
-+static int
-+qca8k_do_dsa_sw_ports_self_test(struct qca8k_priv *priv, int parallel_test)
-+{
-+ struct device_node *dn = priv->dev->of_node;
-+ struct device_node *ports, *port;
-+ struct device_node *phy_dn;
-+ struct phy_device *phy;
-+ int reg, err = 0, test_phase;
-+ u32 tests_result = 0;
-+
-+ ports = of_get_child_by_name(dn, "ports");
-+ if (!ports) {
-+ dev_err(priv->dev, "no ports child node found\n");
-+ return -EINVAL;
-+ }
-+
-+ for (test_phase = 1; test_phase <= 2; test_phase++) {
-+ if (parallel_test && test_phase == 2) {
-+ err = qca8k_start_all_phys_pkt_gens(priv);
-+ if (err)
-+ goto error;
-+ }
-+ for_each_available_child_of_node(ports, port) {
-+ err = of_property_read_u32(port, "reg", ®);
-+ if (err)
-+ goto error;
-+ if (reg >= QCA8K_NUM_PORTS) {
-+ err = -EINVAL;
-+ goto error;
-+ }
-+ phy_dn = of_parse_phandle(port, "phy-handle", 0);
-+ if (phy_dn) {
-+ phy = of_phy_find_device(phy_dn);
-+ of_node_put(phy_dn);
-+ if (phy) {
-+ int result;
-+ result = qca8k_test_dsa_port_for_errors(priv,
-+ phy, reg, test_phase);
-+ if (!parallel_test && test_phase == 1)
-+ qca8k_start_phy_pkt_gen(phy);
-+ put_device(&phy->mdio.dev);
-+ if (test_phase == 2) {
-+ tests_result <<= 1;
-+ if (result)
-+ tests_result |= 1;
-+ }
-+ }
-+ }
-+ }
-+ }
-+
-+end:
-+ of_node_put(ports);
-+ qca8k_fdb_flush(priv);
-+ return tests_result;
-+error:
-+ tests_result |= 0xf000;
-+ goto end;
-+}
-+
-+static int
-+psgmii_vco_calibrate_and_test(struct dsa_switch *ds)
-+{
-+ int ret, a, test_result;
-+ struct qca8k_priv *priv = ds->priv;
-+
-+ for (a = 0; a <= QCA8K_PSGMII_CALB_NUM; a++) {
-+ ret = psgmii_vco_calibrate(priv);
-+ if (ret)
-+ return ret;
-+ /* first we run serial test */
-+ test_result = qca8k_do_dsa_sw_ports_self_test(priv, 0);
-+ /* and if it is ok then we run the test in parallel */
-+ if (!test_result)
-+ test_result = qca8k_do_dsa_sw_ports_self_test(priv, 1);
-+ if (!test_result) {
-+ if (a > 0) {
-+ dev_warn(priv->dev, "PSGMII work was stabilized after %d "
-+ "calibration retries !\n", a);
-+ }
-+ return 0;
-+ } else {
-+ schedule();
-+ if (a > 0 && a % 10 == 0) {
-+ dev_err(priv->dev, "PSGMII work is unstable !!! "
-+ "Let's try to wait a bit ... %d\n", a);
-+ set_current_state(TASK_INTERRUPTIBLE);
-+ schedule_timeout(msecs_to_jiffies(a * 100));
-+ }
-+ }
-+ }
-+
-+ panic("PSGMII work is unstable !!! "
-+ "Repeated recalibration attempts did not help(0x%x) !\n",
-+ test_result);
-+
-+ return -EFAULT;
-+}
-+
-+static int
-+ipq4019_psgmii_configure(struct dsa_switch *ds)
-+{
-+ struct qca8k_priv *priv = ds->priv;
-+ int ret;
-+
-+ if (!priv->psgmii_calibrated) {
-+ dev_info(ds->dev, "PSGMII calibration!\n");
-+ ret = psgmii_vco_calibrate_and_test(ds);
-+
-+ ret = regmap_clear_bits(priv->psgmii, PSGMIIPHY_MODE_CONTROL,
-+ PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M);
-+ ret = regmap_write(priv->psgmii, PSGMIIPHY_TX_CONTROL,
-+ PSGMIIPHY_TX_CONTROL_MAGIC_VALUE);
-+
-+ priv->psgmii_calibrated = true;
-+
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static void
-+qca8k_phylink_ipq4019_mac_config(struct dsa_switch *ds, int port,
-+ unsigned int mode,
-+ const struct phylink_link_state *state)
-+{
-+ struct qca8k_priv *priv = ds->priv;
-+
-+ switch (port) {
-+ case 0:
-+ /* CPU port, no configuration needed */
-+ return;
-+ case 1:
-+ case 2:
-+ case 3:
-+ if (state->interface == PHY_INTERFACE_MODE_PSGMII)
-+ if (ipq4019_psgmii_configure(ds))
-+ dev_err(ds->dev, "PSGMII configuration failed!\n");
-+ return;
-+ case 4:
-+ case 5:
-+ if (state->interface == PHY_INTERFACE_MODE_RGMII ||
-+ state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
-+ state->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
-+ state->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
-+ regmap_set_bits(priv->regmap,
-+ QCA8K_IPQ4019_REG_RGMII_CTRL,
-+ QCA8K_IPQ4019_RGMII_CTRL_CLK);
-+ }
-+
-+ if (state->interface == PHY_INTERFACE_MODE_PSGMII)
-+ if (ipq4019_psgmii_configure(ds))
-+ dev_err(ds->dev, "PSGMII configuration failed!\n");
-+ return;
-+ default:
-+ dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
-+ return;
-+ }
-+}
-+
-+static int
-+qca8k_ipq4019_setup_port(struct dsa_switch *ds, int port)
-+{
-+ struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
-+ int ret;
-+
-+ /* CPU port gets connected to all user ports of the switch */
-+ if (dsa_is_cpu_port(ds, port)) {
-+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
-+ QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
-+ if (ret)
-+ return ret;
-+
-+ /* Disable CPU ARP Auto-learning by default */
-+ ret = regmap_clear_bits(priv->regmap,
-+ QCA8K_PORT_LOOKUP_CTRL(port),
-+ QCA8K_PORT_LOOKUP_LEARN);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ /* Individual user ports get connected to CPU port only */
-+ if (dsa_is_user_port(ds, port)) {
-+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
-+ QCA8K_PORT_LOOKUP_MEMBER,
-+ BIT(QCA8K_IPQ4019_CPU_PORT));
-+ if (ret)
-+ return ret;
-+
-+ /* Enable ARP Auto-learning by default */
-+ ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(port),
-+ QCA8K_PORT_LOOKUP_LEARN);
-+ if (ret)
-+ return ret;
-+
-+ /* For port based vlans to work we need to set the
-+ * default egress vid
-+ */
-+ ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
-+ QCA8K_EGREES_VLAN_PORT_MASK(port),
-+ QCA8K_EGREES_VLAN_PORT(port, QCA8K_PORT_VID_DEF));
-+ if (ret)
-+ return ret;
-+
-+ ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
-+ QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
-+ QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
-+ if (ret)
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int
-+qca8k_ipq4019_setup(struct dsa_switch *ds)
-+{
-+ struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
-+ int ret, i;
-+
-+ /* Make sure that port 0 is the cpu port */
-+ if (!dsa_is_cpu_port(ds, QCA8K_IPQ4019_CPU_PORT)) {
-+ dev_err(priv->dev, "port %d is not the CPU port",
-+ QCA8K_IPQ4019_CPU_PORT);
-+ return -EINVAL;
-+ }
-+
-+ qca8k_ipq4019_setup_pcs(priv, &priv->pcs_port_0, 0);
-+
-+ /* Enable CPU Port */
-+ ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
-+ QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
-+ if (ret) {
-+ dev_err(priv->dev, "failed enabling CPU port");
-+ return ret;
-+ }
-+
-+ /* Enable MIB counters */
-+ ret = qca8k_mib_init(priv);
-+ if (ret)
-+ dev_warn(priv->dev, "MIB init failed");
-+
-+ /* Disable forwarding by default on all ports */
-+ for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
-+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
-+ QCA8K_PORT_LOOKUP_MEMBER, 0);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ /* Enable QCA header mode on the CPU port */
-+ ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_IPQ4019_CPU_PORT),
-+ FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
-+ FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
-+ if (ret) {
-+ dev_err(priv->dev, "failed enabling QCA header mode");
-+ return ret;
-+ }
-+
-+ /* Disable MAC by default on all ports */
-+ for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
-+ if (dsa_is_user_port(ds, i))
-+ qca8k_port_set_status(priv, i, 0);
-+ }
-+
-+ /* Forward all unknown frames to CPU port for Linux processing */
-+ ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
-+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
-+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
-+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
-+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)));
-+ if (ret)
-+ return ret;
-+
-+ /* Setup connection between CPU port & user ports */
-+ for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
-+ ret = qca8k_ipq4019_setup_port(ds, i);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ /* Setup our port MTUs to match power on defaults */
-+ ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
-+ if (ret)
-+ dev_warn(priv->dev, "failed setting MTU settings");
-+
-+ /* Flush the FDB table */
-+ qca8k_fdb_flush(priv);
-+
-+ /* Set min a max ageing value supported */
-+ ds->ageing_time_min = 7000;
-+ ds->ageing_time_max = 458745000;
-+
-+ /* Set max number of LAGs supported */
-+ ds->num_lag_ids = QCA8K_NUM_LAGS;
-+
-+ /* CPU port HW learning doesnt work correctly, so let DSA handle it */
-+ ds->assisted_learning_on_cpu_port = true;
-+
-+ return 0;
-+}
-+
-+static const struct dsa_switch_ops qca8k_ipq4019_switch_ops = {
-+ .get_tag_protocol = qca8k_ipq4019_get_tag_protocol,
-+ .setup = qca8k_ipq4019_setup,
-+ .get_strings = qca8k_get_strings,
-+ .get_ethtool_stats = qca8k_get_ethtool_stats,
-+ .get_sset_count = qca8k_get_sset_count,
-+ .set_ageing_time = qca8k_set_ageing_time,
-+ .get_mac_eee = qca8k_get_mac_eee,
-+ .set_mac_eee = qca8k_set_mac_eee,
-+ .port_enable = qca8k_port_enable,
-+ .port_disable = qca8k_port_disable,
-+ .port_change_mtu = qca8k_port_change_mtu,
-+ .port_max_mtu = qca8k_port_max_mtu,
-+ .port_stp_state_set = qca8k_port_stp_state_set,
-+ .port_bridge_join = qca8k_port_bridge_join,
-+ .port_bridge_leave = qca8k_port_bridge_leave,
-+ .port_fast_age = qca8k_port_fast_age,
-+ .port_fdb_add = qca8k_port_fdb_add,
-+ .port_fdb_del = qca8k_port_fdb_del,
-+ .port_fdb_dump = qca8k_port_fdb_dump,
-+ .port_mdb_add = qca8k_port_mdb_add,
-+ .port_mdb_del = qca8k_port_mdb_del,
-+ .port_mirror_add = qca8k_port_mirror_add,
-+ .port_mirror_del = qca8k_port_mirror_del,
-+ .port_vlan_filtering = qca8k_port_vlan_filtering,
-+ .port_vlan_add = qca8k_port_vlan_add,
-+ .port_vlan_del = qca8k_port_vlan_del,
-+ .phylink_mac_select_pcs = qca8k_ipq4019_phylink_mac_select_pcs,
-+ .phylink_get_caps = qca8k_ipq4019_phylink_get_caps,
-+ .phylink_mac_config = qca8k_phylink_ipq4019_mac_config,
-+ .phylink_mac_link_down = qca8k_phylink_ipq4019_mac_link_down,
-+ .phylink_mac_link_up = qca8k_phylink_ipq4019_mac_link_up,
-+ .port_lag_join = qca8k_port_lag_join,
-+ .port_lag_leave = qca8k_port_lag_leave,
-+};
-+
-+static const struct qca8k_match_data ipq4019 = {
-+ .id = QCA8K_ID_IPQ4019,
-+ .mib_count = QCA8K_QCA833X_MIB_COUNT,
-+};
-+
-+static int
-+qca8k_ipq4019_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct qca8k_priv *priv;
-+ void __iomem *base, *psgmii;
-+ struct device_node *np = dev->of_node, *mdio_np, *psgmii_ethphy_np;
-+ int ret;
-+
-+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->dev = dev;
-+ priv->info = &ipq4019;
-+
-+ /* Start by setting up the register mapping */
-+ base = devm_platform_ioremap_resource_byname(pdev, "base");
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ priv->regmap = devm_regmap_init_mmio(dev, base,
-+ &qca8k_ipq4019_regmap_config);
-+ if (IS_ERR(priv->regmap)) {
-+ ret = PTR_ERR(priv->regmap);
-+ dev_err(dev, "base regmap initialization failed, %d\n", ret);
-+ return ret;
-+ }
-+
-+ psgmii = devm_platform_ioremap_resource_byname(pdev, "psgmii_phy");
-+ if (IS_ERR(psgmii))
-+ return PTR_ERR(psgmii);
-+
-+ priv->psgmii = devm_regmap_init_mmio(dev, psgmii,
-+ &qca8k_ipq4019_psgmii_phy_regmap_config);
-+ if (IS_ERR(priv->psgmii)) {
-+ ret = PTR_ERR(priv->psgmii);
-+ dev_err(dev, "PSGMII regmap initialization failed, %d\n", ret);
-+ return ret;
-+ }
-+
-+ mdio_np = of_parse_phandle(np, "mdio", 0);
-+ if (!mdio_np) {
-+ dev_err(dev, "unable to get MDIO bus phandle\n");
-+ of_node_put(mdio_np);
-+ return -EINVAL;
-+ }
-+
-+ priv->bus = of_mdio_find_bus(mdio_np);
-+ of_node_put(mdio_np);
-+ if (!priv->bus) {
-+ dev_err(dev, "unable to find MDIO bus\n");
-+ return -EPROBE_DEFER;
-+ }
-+
-+ psgmii_ethphy_np = of_parse_phandle(np, "psgmii-ethphy", 0);
-+ if (!psgmii_ethphy_np) {
-+ dev_dbg(dev, "unable to get PSGMII eth PHY phandle\n");
-+ of_node_put(psgmii_ethphy_np);
-+ }
-+
-+ if (psgmii_ethphy_np) {
-+ priv->psgmii_ethphy = of_phy_find_device(psgmii_ethphy_np);
-+ of_node_put(psgmii_ethphy_np);
-+ if (!priv->psgmii_ethphy) {
-+ dev_err(dev, "unable to get PSGMII eth PHY\n");
-+ return -ENODEV;
-+ }
-+ }
-+
-+ /* Check the detected switch id */
-+ ret = qca8k_read_switch_id(priv);
-+ if (ret)
-+ return ret;
-+
-+ priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
-+ if (!priv->ds)
-+ return -ENOMEM;
-+
-+ priv->ds->dev = dev;
-+ priv->ds->num_ports = QCA8K_IPQ4019_NUM_PORTS;
-+ priv->ds->priv = priv;
-+ priv->ds->ops = &qca8k_ipq4019_switch_ops;
-+ mutex_init(&priv->reg_mutex);
-+ platform_set_drvdata(pdev, priv);
-+
-+ return dsa_register_switch(priv->ds);
-+}
-+
-+static int
-+qca8k_ipq4019_remove(struct platform_device *pdev)
-+{
-+ struct qca8k_priv *priv = dev_get_drvdata(&pdev->dev);
-+ int i;
-+
-+ if (!priv)
-+ return 0;
-+
-+ for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++)
-+ qca8k_port_set_status(priv, i, 0);
-+
-+ dsa_unregister_switch(priv->ds);
-+
-+ platform_set_drvdata(pdev, NULL);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qca8k_ipq4019_of_match[] = {
-+ { .compatible = "qca,ipq4019-qca8337n", },
-+ { /* sentinel */ },
-+};
-+
-+static struct platform_driver qca8k_ipq4019_driver = {
-+ .probe = qca8k_ipq4019_probe,
-+ .remove = qca8k_ipq4019_remove,
-+ .driver = {
-+ .name = "qca8k-ipq4019",
-+ .of_match_table = qca8k_ipq4019_of_match,
-+ },
-+};
-+
-+module_platform_driver(qca8k_ipq4019_driver);
-+
-+MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
-+MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>, Robert Marko <robert.marko@sartura.hr>");
-+MODULE_DESCRIPTION("Qualcomm IPQ4019 built-in switch driver");
-+MODULE_LICENSE("GPL");
---- a/drivers/net/dsa/qca/qca8k.h
-+++ b/drivers/net/dsa/qca/qca8k.h
-@@ -19,7 +19,10 @@
- #define QCA8K_ETHERNET_TIMEOUT 5
-
- #define QCA8K_NUM_PORTS 7
-+#define QCA8K_IPQ4019_NUM_PORTS 6
- #define QCA8K_NUM_CPU_PORTS 2
-+#define QCA8K_IPQ4019_NUM_CPU_PORTS 1
-+#define QCA8K_IPQ4019_CPU_PORT 0
- #define QCA8K_MAX_MTU 9000
- #define QCA8K_NUM_LAGS 4
- #define QCA8K_NUM_PORTS_FOR_LAG 4
-@@ -28,6 +31,7 @@
- #define QCA8K_ID_QCA8327 0x12
- #define PHY_ID_QCA8337 0x004dd036
- #define QCA8K_ID_QCA8337 0x13
-+#define QCA8K_ID_IPQ4019 0x14
-
- #define QCA8K_QCA832X_MIB_COUNT 39
- #define QCA8K_QCA833X_MIB_COUNT 41
-@@ -265,6 +269,7 @@
- #define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
- #define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
- #define QCA8K_PORT_LOOKUP_LEARN BIT(20)
-+#define QCA8K_PORT_LOOKUP_LOOPBACK_EN BIT(21)
- #define QCA8K_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
-
- #define QCA8K_REG_GOL_TRUNK_CTRL0 0x700
-@@ -341,6 +346,53 @@
- #define MII_ATH_MMD_ADDR 0x0d
- #define MII_ATH_MMD_DATA 0x0e
-
-+/* IPQ4019 PSGMII PHY registers */
-+#define QCA8K_IPQ4019_REG_RGMII_CTRL 0x004
-+#define QCA8K_IPQ4019_RGMII_CTRL_RGMII_RXC GENMASK(1, 0)
-+#define QCA8K_IPQ4019_RGMII_CTRL_RGMII_TXC GENMASK(9, 8)
-+/* Some kind of CLK selection
-+ * 0: gcc_ess_dly2ns
-+ * 1: gcc_ess_clk
-+ */
-+#define QCA8K_IPQ4019_RGMII_CTRL_CLK BIT(10)
-+#define QCA8K_IPQ4019_RGMII_CTRL_DELAY_RMII0 GENMASK(17, 16)
-+#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII0_REF_CLK BIT(18)
-+#define QCA8K_IPQ4019_RGMII_CTRL_DELAY_RMII1 GENMASK(20, 19)
-+#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII1_REF_CLK BIT(21)
-+#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII0_MASTER_EN BIT(24)
-+#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII1_MASTER_EN BIT(25)
-+
-+#define PSGMIIPHY_MODE_CONTROL 0x1b4
-+#define PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M BIT(0)
-+#define PSGMIIPHY_TX_CONTROL 0x288
-+#define PSGMIIPHY_TX_CONTROL_MAGIC_VALUE 0x8380
-+#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1 0x9c
-+#define PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART BIT(14)
-+#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2 0xa0
-+#define PSGMIIPHY_REG_PLL_VCO_CALIB_READY BIT(0)
-+
-+#define QCA8K_PSGMII_CALB_NUM 100
-+#define MII_QCA8075_SSTATUS 0x11
-+#define QCA8075_PHY_SPEC_STATUS_LINK BIT(10)
-+#define QCA8075_MMD7_CRC_AND_PKTS_COUNT 0x8029
-+#define QCA8075_MMD7_PKT_GEN_PKT_NUMB 0x8021
-+#define QCA8075_MMD7_PKT_GEN_PKT_SIZE 0x8062
-+#define QCA8075_MMD7_PKT_GEN_CTRL 0x8020
-+#define QCA8075_MMD7_CNT_SELFCLR BIT(1)
-+#define QCA8075_MMD7_CNT_FRAME_CHK_EN BIT(0)
-+#define QCA8075_MMD7_PKT_GEN_START BIT(13)
-+#define QCA8075_MMD7_PKT_GEN_INPROGR BIT(15)
-+#define QCA8075_MMD7_IG_FRAME_RECV_CNT_HI 0x802a
-+#define QCA8075_MMD7_IG_FRAME_RECV_CNT_LO 0x802b
-+#define QCA8075_MMD7_IG_FRAME_ERR_CNT 0x802c
-+#define QCA8075_MMD7_EG_FRAME_RECV_CNT_HI 0x802d
-+#define QCA8075_MMD7_EG_FRAME_RECV_CNT_LO 0x802e
-+#define QCA8075_MMD7_EG_FRAME_ERR_CNT 0x802f
-+#define QCA8075_MMD7_MDIO_BRDCST_WRITE 0x8028
-+#define QCA8075_MMD7_MDIO_BRDCST_WRITE_EN BIT(15)
-+#define QCA8075_MDIO_BRDCST_PHY_ADDR 0x1f
-+#define QCA8075_PKT_GEN_PKTS_COUNT 4096
-+
- enum {
- QCA8K_PORT_SPEED_10M = 0,
- QCA8K_PORT_SPEED_100M = 1,
-@@ -466,6 +518,10 @@ struct qca8k_priv {
- struct qca8k_pcs pcs_port_6;
- const struct qca8k_match_data *info;
- struct qca8k_led ports_led[QCA8K_LED_COUNT];
-+ /* IPQ4019 specific */
-+ struct regmap *psgmii;
-+ struct phy_device *psgmii_ethphy;
-+ bool psgmii_calibrated;
- };
-
- struct qca8k_mib_desc {
+++ /dev/null
-From 19c507c3fe4a6fc60317dcae2c55de452aecb7d5 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 1 Nov 2021 18:15:04 +0100
-Subject: [PATCH] arm: dts: ipq4019: add switch node
-
-Since the built-in IPQ40xx switch now has a driver, add the required node
-for it to work.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 76 +++++++++++++++++++++++++++++
- 1 file changed, 76 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -594,6 +594,82 @@
- status = "disabled";
- };
-
-+ switch: switch@c000000 {
-+ compatible = "qca,ipq4019-qca8337n";
-+ reg = <0xc000000 0x80000>, <0x98000 0x800>;
-+ reg-names = "base", "psgmii_phy";
-+ resets = <&gcc ESS_PSGMII_ARES>;
-+ reset-names = "psgmii_rst";
-+ mdio = <&mdio>;
-+ psgmii-ethphy = <&psgmiiphy>;
-+
-+ status = "disabled";
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ port@0 { /* MAC0 */
-+ reg = <0>;
-+ label = "cpu";
-+ ethernet = <&gmac>;
-+ phy-mode = "internal";
-+
-+ fixed-link {
-+ speed = <1000>;
-+ full-duplex;
-+ pause;
-+ asym-pause;
-+ };
-+ };
-+
-+ swport1: port@1 { /* MAC1 */
-+ reg = <1>;
-+ label = "lan1";
-+ phy-handle = <ðphy0>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport2: port@2 { /* MAC2 */
-+ reg = <2>;
-+ label = "lan2";
-+ phy-handle = <ðphy1>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport3: port@3 { /* MAC3 */
-+ reg = <3>;
-+ label = "lan3";
-+ phy-handle = <ðphy2>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport4: port@4 { /* MAC4 */
-+ reg = <4>;
-+ label = "lan4";
-+ phy-handle = <ðphy3>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport5: port@5 { /* MAC5 */
-+ reg = <5>;
-+ label = "wan";
-+ phy-handle = <ðphy4>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
- gmac: ethernet@c080000 {
- compatible = "qcom,ipq4019-ess-edma";
- reg = <0xc080000 0x8000>;
+++ /dev/null
-From 5ac078c8fe18f3e8318547b8ed0ed782730c5039 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 10 Feb 2024 22:28:27 +0100
-Subject: [PATCH] ARM: dts: qcom: ipq4019: add QCA8075 PHY Package nodes
-
-Add QCA8075 PHY Package nodes. The PHY nodes that were previously
-defined never worked and actually never had a driver to correctly setup
-these PHY. Now that we have a correct driver, correctly add the PHY
-Package node and set the default value of 300mw for tx driver strength
-following specification of ipq4019 SoC.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts//qcom-ipq4019.dtsi | 35 +++++++++++++++---------
- 1 file changed, 22 insertions(+), 13 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -725,24 +725,33 @@
- reg = <0x90000 0x64>;
- status = "disabled";
-
-- ethphy0: ethernet-phy@0 {
-+ ethernet-phy-package@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "qcom,qca8075-package";
- reg = <0>;
-- };
--
-- ethphy1: ethernet-phy@1 {
-- reg = <1>;
-- };
-
-- ethphy2: ethernet-phy@2 {
-- reg = <2>;
-- };
--
-- ethphy3: ethernet-phy@3 {
-- reg = <3>;
-- };
-+ qcom,tx-drive-strength-milliwatt = <300>;
-
-- ethphy4: ethernet-phy@4 {
-- reg = <4>;
-+ ethphy0: ethernet-phy@0 {
-+ reg = <0>;
-+ };
-+
-+ ethphy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+
-+ ethphy2: ethernet-phy@2 {
-+ reg = <2>;
-+ };
-+
-+ ethphy3: ethernet-phy@3 {
-+ reg = <3>;
-+ };
-+
-+ ethphy4: ethernet-phy@4 {
-+ reg = <4>;
-+ };
- };
- };
-
+++ /dev/null
-From 79b38b9f85da868ca59b66715c20aa55104b640b Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Fri, 2 Oct 2020 10:43:26 +0200
-Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
-
-This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -752,6 +752,10 @@
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
-+
-+ psgmiiphy: psgmii-phy@5 {
-+ reg = <5>;
-+ };
- };
- };
-
+++ /dev/null
-From d0055b03d9c8d48ad2b971821989b09ba95c39f8 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sun, 17 Sep 2023 20:18:31 +0200
-Subject: [PATCH] net: qualcomm: ipqess: fix TX timeout errors
-
-Currently logic to handle napi tx completion is flawed and on the long
-run on loaded condition cause TX timeout error with the queue not being
-able to handle any new packet.
-
-There are 2 main cause of this:
-- incrementing the packet done value wrongly
-- handling 2 times the tx_ring tail
-
-ipqess_tx_unmap_and_free may return 2 kind values:
-- 0: we are handling first and middle descriptor for the packet
-- packet len: we are at the last descriptor for the packet
-
-Done value was wrongly incremented also for first and intermediate
-descriptor for the packet resulting causing panic and TX timeouts by
-comunicating to the kernel an inconsistent value of packet handling not
-matching the expected ones.
-
-Tx_ring tail was handled twice for ipqess_tx_complete run resulting in
-again done value incremented wrongly and also problem with idx handling
-by actually skipping descriptor for some packets.
-
-Rework the loop logic to fix these 2 problem and also add some comments
-to make sure ipqess_tx_unmap_and_free ret value is better
-understandable.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 13 ++++++++++---
- 1 file changed, 10 insertions(+), 3 deletions(-)
-
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -453,13 +453,22 @@ static int ipqess_tx_complete(struct ipq
- tail >>= IPQESS_TPD_CONS_IDX_SHIFT;
- tail &= IPQESS_TPD_CONS_IDX_MASK;
-
-- do {
-+ while ((tx_ring->tail != tail) && (done < budget)) {
- ret = ipqess_tx_unmap_and_free(&tx_ring->ess->pdev->dev,
- &tx_ring->buf[tx_ring->tail]);
-- tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count);
-+ /* ipqess_tx_unmap_and_free may return 2 kind values:
-+ * - 0: we are handling first and middle descriptor for the packet
-+ * - packet len: we are at the last descriptor for the packet
-+ * Increment total bytes handled and packet done only if we are
-+ * handling the last descriptor for the packet.
-+ */
-+ if (ret) {
-+ total += ret;
-+ done++;
-+ }
-
-- total += ret;
-- } while ((++done < budget) && (tx_ring->tail != tail));
-+ tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count);
-+ };
-
- ipqess_w32(tx_ring->ess, IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx),
- tx_ring->tail);
+++ /dev/null
-From: Christian Lamparter <chunkeey@googlemail.com>
-Subject: SoC: add qualcomm syscon
---- a/drivers/soc/qcom/Kconfig
-+++ b/drivers/soc/qcom/Kconfig
-@@ -248,4 +248,11 @@ config QCOM_ICC_BWMON
- the fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high
- memory throughput even with lower CPU frequencies.
-
-+config QCOM_TCSR
-+ tristate "QCOM Top Control and Status Registers"
-+ depends on ARCH_QCOM
-+ help
-+ Say y here to enable TCSR support. The TCSR provides control
-+ functions for various peripherals.
-+
- endmenu
---- a/drivers/soc/qcom/Makefile
-+++ b/drivers/soc/qcom/Makefile
-@@ -29,3 +29,4 @@ obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
- obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
- obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o
- obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o
-+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
---- /dev/null
-+++ b/drivers/soc/qcom/qcom_tcsr.c
-@@ -0,0 +1,98 @@
-+/*
-+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License rev 2 and
-+ * only rev 2 as published by the free Software foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+
-+#define TCSR_USB_PORT_SEL 0xb0
-+#define TCSR_USB_HSPHY_CONFIG 0xC
-+
-+#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0
-+#define TCSR_ESS_INTERFACE_SEL_MASK 0xf
-+
-+#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0
-+#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4
-+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4
-+
-+static int tcsr_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ const struct device_node *node = pdev->dev.of_node;
-+ void __iomem *base;
-+ u32 val;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
-+ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
-+ writel(val, base + TCSR_USB_PORT_SEL);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
-+ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
-+ writel(val, base + TCSR_USB_HSPHY_CONFIG);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
-+ u32 tmp = 0;
-+ dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
-+ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
-+ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
-+ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
-+ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
-+ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
-+ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
-+ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
-+ dev_info(&pdev->dev,
-+ "setting wifi_noc_memtype_m0_m2 = %x\n", val);
-+ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id tcsr_dt_match[] = {
-+ { .compatible = "qcom,tcsr", },
-+ { },
-+};
-+
-+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
-+
-+static struct platform_driver tcsr_driver = {
-+ .driver = {
-+ .name = "tcsr",
-+ .owner = THIS_MODULE,
-+ .of_match_table = tcsr_dt_match,
-+ },
-+ .probe = tcsr_probe,
-+};
-+
-+module_platform_driver(tcsr_driver);
-+
-+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
-+MODULE_DESCRIPTION("QCOM TCSR driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/include/dt-bindings/soc/qcom,tcsr.h
-@@ -0,0 +1,48 @@
-+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+#ifndef __DT_BINDINGS_QCOM_TCSR_H
-+#define __DT_BINDINGS_QCOM_TCSR_H
-+
-+#define TCSR_USB_SELECT_USB3_P0 0x1
-+#define TCSR_USB_SELECT_USB3_P1 0x2
-+#define TCSR_USB_SELECT_USB3_DUAL 0x3
-+
-+/* IPQ40xx HS PHY Mode Select */
-+#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7
-+#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7
-+
-+/* IPQ40xx ess interface mode select */
-+#define TCSR_ESS_PSGMII 0
-+#define TCSR_ESS_PSGMII_RGMII5 1
-+#define TCSR_ESS_PSGMII_RMII0 2
-+#define TCSR_ESS_PSGMII_RMII1 4
-+#define TCSR_ESS_PSGMII_RMII0_RMII1 6
-+#define TCSR_ESS_PSGMII_RGMII4 9
-+
-+/*
-+ * IPQ40xx WiFi Global Config
-+ * Bit 30:AXID_EN
-+ * Enable AXI master bus Axid translating to confirm all txn submitted by order
-+ * Bit 24: Use locally generated socslv_wxi_bvalid
-+ * 1: use locally generate socslv_wxi_bvalid for performance.
-+ * 0: use SNOC socslv_wxi_bvalid.
-+ */
-+#define TCSR_WIFI_GLB_CFG 0x41000000
-+
-+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
-+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222
-+
-+/* TCSR A/B REG */
-+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
-+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
-+
-+#endif
+++ /dev/null
-From c668fd2c4d9ad4a510fd214a2da83bd9b67a2508 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 13 Aug 2023 18:13:08 +0200
-Subject: [PATCH] Revert "firmware: qcom_scm: Clear download bit during reboot"
-
-This reverts commit a3ea89b5978dbcd0fa55f675c5a1e04611093709.
-
-It is breaking reboot on IPQ4019 boards, so revert until a proper fix
-is found.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/firmware/qcom_scm.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -1466,7 +1466,8 @@ static int qcom_scm_probe(struct platfor
- static void qcom_scm_shutdown(struct platform_device *pdev)
- {
- /* Clean shutdown, disable download mode to allow normal restart */
-- qcom_scm_set_download_mode(false);
-+ if (download_mode)
-+ qcom_scm_set_download_mode(false);
- }
-
- static const struct of_device_id qcom_scm_dt_match[] = {
+++ /dev/null
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 3 Aug 2012 10:27:25 +0200
-Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
---- a/include/uapi/linux/atm.h
-+++ b/include/uapi/linux/atm.h
-@@ -131,8 +131,14 @@
- #define ATM_ABR 4
- #define ATM_ANYCLASS 5 /* compatible with everything */
-
-+#define ATM_VBR_NRT ATM_VBR
-+#define ATM_VBR_RT 6
-+#define ATM_UBR_PLUS 7
-+#define ATM_GFR 8
-+
- #define ATM_MAX_PCR -1 /* maximum available PCR */
-
-+
- struct atm_trafprm {
- unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
- int max_pcr; /* maximum PCR in cells per second */
-@@ -155,6 +161,9 @@ struct atm_trafprm {
- unsigned int adtf :10; /* ACR Decrease Time Factor (10-bit) */
- unsigned int cdf :3; /* Cutoff Decrease Factor (3-bit) */
- unsigned int spare :9; /* spare bits */
-+ int scr; /* sustained rate in cells per second */
-+ int mbs; /* maximum burst size (MBS) in cells */
-+ int cdv; /* Cell delay variation */
- };
-
- struct atm_qos {
---- a/net/atm/proc.c
-+++ b/net/atm/proc.c
-@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil
- static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
- {
- static const char *const class_name[] = {
-- "off", "UBR", "CBR", "VBR", "ABR"};
-+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
- static const char *const aal_name[] = {
- "---", "1", "2", "3/4", /* 0- 3 */
- "???", "5", "???", "???", /* 4- 7 */
+++ /dev/null
-From: Subhra Banerjee <subhrax.banerjee@intel.com>
-Date: Fri, 31 Aug 2018 12:01:19 +0530
-Subject: [PATCH] UGW_SW-29163: ATM oam support
-
---- a/drivers/net/ppp/ppp_generic.c
-+++ b/drivers/net/ppp/ppp_generic.c
-@@ -2953,6 +2953,22 @@ char *ppp_dev_name(struct ppp_channel *c
- return name;
- }
-
-+/*
-+ * Return the PPP device interface pointer
-+ */
-+struct net_device *ppp_device(struct ppp_channel *chan)
-+{
-+ struct channel *pch = chan->ppp;
-+ struct net_device *dev = NULL;
-+
-+ if (pch) {
-+ read_lock_bh(&pch->upl);
-+ if (pch->ppp && pch->ppp->dev)
-+ dev = pch->ppp->dev;
-+ read_unlock_bh(&pch->upl);
-+ }
-+ return dev;
-+}
-
- /*
- * Disconnect a channel from the generic layer.
-@@ -3599,6 +3615,7 @@ EXPORT_SYMBOL(ppp_unregister_channel);
- EXPORT_SYMBOL(ppp_channel_index);
- EXPORT_SYMBOL(ppp_unit_number);
- EXPORT_SYMBOL(ppp_dev_name);
-+EXPORT_SYMBOL(ppp_device);
- EXPORT_SYMBOL(ppp_input);
- EXPORT_SYMBOL(ppp_input_error);
- EXPORT_SYMBOL(ppp_output_wakeup);
---- a/include/linux/ppp_channel.h
-+++ b/include/linux/ppp_channel.h
-@@ -76,6 +76,9 @@ extern int ppp_unit_number(struct ppp_ch
- /* Get the device name associated with a channel, or NULL if none */
- extern char *ppp_dev_name(struct ppp_channel *);
-
-+/* Get the device pointer associated with a channel, or NULL if none */
-+extern struct net_device *ppp_device(struct ppp_channel *);
-+
- /*
- * SMP locking notes:
- * The channel code must ensure that when it calls ppp_unregister_channel,
---- a/net/atm/Kconfig
-+++ b/net/atm/Kconfig
-@@ -56,6 +56,12 @@ config ATM_MPOA
- subnetwork boundaries. These shortcut connections bypass routers
- enhancing overall network performance.
-
-+config ATM_MPOA_INTEL_DSL_PHY_SUPPORT
-+ bool "Intel DSL Phy MPOA support"
-+ depends on ATM && INET && ATM_MPOA!=n
-+ help
-+ Add support for Intel DSL Phy ATM MPOA
-+
- config ATM_BR2684
- tristate "RFC1483/2684 Bridged protocols"
- depends on ATM && INET
---- a/net/atm/br2684.c
-+++ b/net/atm/br2684.c
-@@ -598,6 +598,11 @@ static int br2684_regvcc(struct atm_vcc
- atmvcc->push = br2684_push;
- atmvcc->pop = br2684_pop;
- atmvcc->release_cb = br2684_release_cb;
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+ if (atm_hook_mpoa_setup) /* IPoA or EoA w/o FCS */
-+ atm_hook_mpoa_setup(atmvcc, brdev->payload == p_routed ? 3 : 0,
-+ brvcc->encaps == BR2684_ENCAPS_LLC ? 1 : 0, net_dev);
-+#endif
- atmvcc->owner = THIS_MODULE;
-
- /* initialize netdev carrier state */
---- a/net/atm/common.c
-+++ b/net/atm/common.c
-@@ -137,6 +137,11 @@ static struct proto vcc_proto = {
- .release_cb = vcc_release_cb,
- };
-
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *) = NULL;
-+EXPORT_SYMBOL(atm_hook_mpoa_setup);
-+#endif
-+
- int vcc_create(struct net *net, struct socket *sock, int protocol, int family, int kern)
- {
- struct sock *sk;
---- a/net/atm/common.h
-+++ b/net/atm/common.h
-@@ -53,4 +53,6 @@ int svc_change_qos(struct atm_vcc *vcc,s
-
- void atm_dev_release_vccs(struct atm_dev *dev);
-
-+extern void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *);
-+
- #endif
---- a/net/atm/mpc.c
-+++ b/net/atm/mpc.c
-@@ -31,6 +31,7 @@
- /* Modular too */
- #include <linux/module.h>
-
-+#include "common.h"
- #include "lec.h"
- #include "mpc.h"
- #include "resources.h"
-@@ -645,6 +646,10 @@ static int atm_mpoa_vcc_attach(struct at
- vcc->proto_data = mpc->dev;
- vcc->push = mpc_push;
-
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+ if (atm_hook_mpoa_setup) /* IPoA, LLC */
-+ atm_hook_mpoa_setup(vcc, 3, 1, mpc->dev);
-+#endif
- return 0;
- }
-
---- a/net/atm/pppoatm.c
-+++ b/net/atm/pppoatm.c
-@@ -422,6 +422,12 @@ static int pppoatm_assign_vcc(struct atm
- atmvcc->user_back = pvcc;
- atmvcc->push = pppoatm_push;
- atmvcc->pop = pppoatm_pop;
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+ if (atm_hook_mpoa_setup) /* PPPoA */
-+ atm_hook_mpoa_setup(atmvcc, 2,
-+ pvcc->encaps == e_llc ? 1 : 0,
-+ ppp_device(&pvcc->chan));
-+#endif
- atmvcc->release_cb = pppoatm_release_cb;
- __module_get(THIS_MODULE);
- atmvcc->owner = THIS_MODULE;
+#endif
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -4637,6 +4637,9 @@ enum skb_ext_id {
+@@ -4642,6 +4642,9 @@ enum skb_ext_id {
#if IS_ENABLED(CONFIG_MCTP_FLOWS)
SKB_EXT_MCTP,
#endif
#include <net/dst.h>
#include <net/sock.h>
#include <net/checksum.h>
-@@ -4812,6 +4816,9 @@ static const u8 skb_ext_type_len[] = {
+@@ -4823,6 +4827,9 @@ static const u8 skb_ext_type_len[] = {
#if IS_ENABLED(CONFIG_MCTP_FLOWS)
[SKB_EXT_MCTP] = SKB_EXT_CHUNKSIZEOF(struct mctp_flow),
#endif
status = "disabled";
- ethphy0: ethernet-phy@0 {
-+ ethernet-phy-package@0 {
++ qca807x: ethernet-phy-package@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,qca8075-package";
CPU_SUBTYPE:=neon-vfpv4
SUBTARGETS:=generic chromium
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
KERNELNAME:=zImage Image dtbs
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APQ_GCC_8084 is not set
-# CONFIG_APQ_MMCC_8084 is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-# CONFIG_ARCH_IPQ40XX is not set
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-# CONFIG_ARCH_MDM9615 is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_ARCH_MSM8909 is not set
-# CONFIG_ARCH_MSM8916 is not set
-CONFIG_ARCH_MSM8960=y
-CONFIG_ARCH_MSM8974=y
-CONFIG_ARCH_MSM8X60=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM=y
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_IPQ806X_FAB_DEVFREQ=y
-CONFIG_ARM_KRAIT_CACHE_DEVFREQ=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
-CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
-CONFIG_ARM_QCOM_SPM_CPUIDLE=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_QCOM=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC8=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DEV_QCOM_RNG=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEVFREQ_GOV_PASSIVE=y
-# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
-# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
-# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
-# CONFIG_DEVFREQ_GOV_USERSPACE is not set
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-# CONFIG_DWMAC_GENERIC is not set
-CONFIG_DWMAC_IPQ806X=y
-# CONFIG_DWMAC_QCOM_ETHQOS is not set
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_QCOM=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-# CONFIG_I2C_QCOM_CCI is not set
-CONFIG_I2C_QUP=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IPQ_APSS_PLL is not set
-# CONFIG_IPQ_GCC_4019 is not set
-# CONFIG_IPQ_GCC_6018 is not set
-CONFIG_IPQ_GCC_806X=y
-# CONFIG_IPQ_GCC_8074 is not set
-# CONFIG_IPQ_LCC_806X is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_KPSS_XCC=y
-CONFIG_KRAITCC=y
-CONFIG_KRAIT_CLOCKS=y
-CONFIG_KRAIT_L2_ACCESSORS=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MDIO_IPQ8064=y
-# CONFIG_MDM_GCC_9615 is not set
-# CONFIG_MDM_LCC_9615 is not set
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-CONFIG_MFD_QCOM_RPM=y
-# CONFIG_MFD_SPMI_PMIC is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=16
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_QCOM_DML=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_MSM=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MSM_GCC_8660=y
-# CONFIG_MSM_GCC_8909 is not set
-# CONFIG_MSM_GCC_8916 is not set
-# CONFIG_MSM_GCC_8939 is not set
-# CONFIG_MSM_GCC_8960 is not set
-# CONFIG_MSM_GCC_8974 is not set
-# CONFIG_MSM_GCC_8976 is not set
-# CONFIG_MSM_GCC_8994 is not set
-# CONFIG_MSM_GCC_8996 is not set
-# CONFIG_MSM_GCC_8998 is not set
-# CONFIG_MSM_GPUCC_8998 is not set
-# CONFIG_MSM_IOMMU is not set
-# CONFIG_MSM_LCC_8960 is not set
-# CONFIG_MSM_MMCC_8960 is not set
-# CONFIG_MSM_MMCC_8974 is not set
-# CONFIG_MSM_MMCC_8996 is not set
-# CONFIG_MSM_MMCC_8998 is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_QCOM=y
-CONFIG_MTD_QCOMSMEM_PARTS=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_QCA8K=y
-CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
-CONFIG_NET_DSA_TAG_QCA=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_QCOM_QFPROM=y
-# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_U_BOOT_ENV=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_QCOM=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_XPCS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-# CONFIG_PHY_QCOM_EDP is not set
-# CONFIG_PHY_QCOM_IPQ4019_USB is not set
-CONFIG_PHY_QCOM_IPQ806X_SATA=y
-# CONFIG_PHY_QCOM_IPQ806X_USB is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-# CONFIG_PHY_QCOM_QMP is not set
-# CONFIG_PHY_QCOM_QUSB2 is not set
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_APQ8064 is not set
-# CONFIG_PINCTRL_APQ8084 is not set
-# CONFIG_PINCTRL_IPQ4019 is not set
-CONFIG_PINCTRL_IPQ8064=y
-# CONFIG_PINCTRL_MDM9615 is not set
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_MSM8226 is not set
-# CONFIG_PINCTRL_MSM8660 is not set
-# CONFIG_PINCTRL_MSM8909 is not set
-# CONFIG_PINCTRL_MSM8916 is not set
-# CONFIG_PINCTRL_MSM8960 is not set
-# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_SDX65 is not set
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_MSM=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QCA83XX_PHY=y
-# CONFIG_QCM_DISPCC_2290 is not set
-# CONFIG_QCM_GCC_2290 is not set
-# CONFIG_QCOM_A53PLL is not set
-CONFIG_QCOM_ADM=y
-CONFIG_QCOM_BAM_DMA=y
-CONFIG_QCOM_CLK_RPM=y
-# CONFIG_QCOM_COMMAND_DB is not set
-# CONFIG_QCOM_CPR is not set
-# CONFIG_QCOM_EBI2 is not set
-# CONFIG_QCOM_GENI_SE is not set
-CONFIG_QCOM_GSBI=y
-CONFIG_QCOM_HFPLL=y
-# CONFIG_QCOM_ICC_BWMON is not set
-# CONFIG_QCOM_IOMMU is not set
-# CONFIG_QCOM_LLCC is not set
-CONFIG_QCOM_NET_PHYLIB=y
-# CONFIG_QCOM_OCMEM is not set
-# CONFIG_QCOM_PDC is not set
-# CONFIG_QCOM_RMTFS_MEM is not set
-CONFIG_QCOM_RPMCC=y
-# CONFIG_QCOM_RPMH is not set
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-CONFIG_QCOM_SMEM=y
-# CONFIG_QCOM_SMSM is not set
-CONFIG_QCOM_SOCINFO=y
-CONFIG_QCOM_SPM=y
-# CONFIG_QCOM_STATS is not set
-CONFIG_QCOM_TCSR=y
-CONFIG_QCOM_TSENS=y
-CONFIG_QCOM_WDT=y
-# CONFIG_QCS_GCC_404 is not set
-# CONFIG_QCS_Q6SSTOP_404 is not set
-# CONFIG_QCS_TURING_404 is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-CONFIG_REGULATOR_QCOM_RPM=y
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SC_CAMCC_7280 is not set
-# CONFIG_SC_DISPCC_7180 is not set
-# CONFIG_SC_GCC_7180 is not set
-# CONFIG_SC_GCC_8280XP is not set
-# CONFIG_SC_GPUCC_7180 is not set
-# CONFIG_SC_LPASSCC_7280 is not set
-# CONFIG_SC_LPASS_CORECC_7180 is not set
-# CONFIG_SC_LPASS_CORECC_7280 is not set
-# CONFIG_SC_MSS_7180 is not set
-# CONFIG_SC_VIDEOCC_7180 is not set
-# CONFIG_SDM_CAMCC_845 is not set
-# CONFIG_SDM_DISPCC_845 is not set
-# CONFIG_SDM_GCC_660 is not set
-# CONFIG_SDM_GCC_845 is not set
-# CONFIG_SDM_GPUCC_845 is not set
-# CONFIG_SDM_LPASSCC_845 is not set
-# CONFIG_SDM_VIDEOCC_845 is not set
-# CONFIG_SDX_GCC_65 is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-# CONFIG_SM_CAMCC_8450 is not set
-# CONFIG_SM_GCC_8150 is not set
-# CONFIG_SM_GCC_8250 is not set
-# CONFIG_SM_GCC_8450 is not set
-# CONFIG_SM_GPUCC_6350 is not set
-# CONFIG_SM_GPUCC_8150 is not set
-# CONFIG_SM_GPUCC_8250 is not set
-# CONFIG_SM_GPUCC_8350 is not set
-# CONFIG_SM_VIDEOCC_8150 is not set
-# CONFIG_SM_VIDEOCC_8250 is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_QUP=y
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SPMI_MSM_PMIC_ARB=y
-# CONFIG_SPMI_PMIC_CLKDIV is not set
-CONFIG_SRCU=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8062-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "NEC Platforms Aterm WG2600HP3";
- compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064";
-
- memory {
- device_type = "memory";
- reg = <0x42000000 0x1e000000>;
- };
-
- aliases {
- label-mac-device = &gmac2;
-
- led-boot = &led_power_green;
- led-failsafe = &led_power_red;
- led-running = &led_power_green;
- led-upgrade = &led_power_red;
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&buttons_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- mode0 {
- label = "mode0";
- gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- mode1 {
- label = "mode1";
- gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-0 = <&leds_pins>;
- pinctrl-names = "default";
-
- led_power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
- };
-
- led_power_red: power_red {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>;
- };
-
- active_green {
- label = "green:active";
- gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>;
- };
-
- active_red {
- label = "red:active";
- gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_green {
- label = "green:wlan2g";
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- wlan2g_red {
- label = "red:wlan2g";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g_green {
- label = "green:wlan5g";
- gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g_red {
- label = "red:wlan5g";
- gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
- };
-
- tv_green {
- label = "green:tv";
- gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>;
- };
-
- tv_red {
- label = "red:tv";
- gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>;
- };
-
- converter_green {
- label = "green:converter";
- gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>;
- };
-
- converter_red {
- label = "red:converter";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-/* nand_pins are used for leds_pins, empty the node
- * from ipq8064.dtsi
- */
-&nand_pins {
- /delete-property/ disable;
- /delete-property/ pullups;
- /delete-property/ hold;
-};
-
-&qcom_pinmux {
- pinctrl-0 = <&akro_pins>;
- pinctrl-names = "default";
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- buttons_pins: buttons_pins {
- mux {
- pins = "gpio22", "gpio24", "gpio40",
- "gpio41";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- leds_pins: leds_pins {
- mux {
- pins = "gpio14", "gpio15", "gpio35",
- "gpio36", "gpio38", "gpio42",
- "gpio43", "gpio46", "gpio55",
- "gpio56", "gpio57", "gpio58";
- function = "gpio";
- bias-pull-down;
- };
-
- akro2 {
- pins = "gpio15", "gpio35", "gpio38",
- "gpio42", "gpio43", "gpio46",
- "gpio55", "gpio56", "gpio57",
- "gpio58";
- drive-strength = <2>;
- };
-
- akro4 {
- pins = "gpio14", "gpio36";
- drive-strength = <4>;
- };
- };
-
- /*
- * Stock firmware has the following settings, so let's do the same.
- * I don't sure why these are required.
- */
- akro_pins: akro_pinmux {
- akro {
- pins = "gpio17", "gpio26", "gpio47";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- reset {
- pins = "gpio45";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- output-low;
- };
-
- gmac0_rgmii {
- pins = "gpio25";
- function = "gpio";
- drive-strength = <8>;
- bias-disable;
- };
- };
-};
-
-&gsbi5 {
- status = "okay";
- qcom,mode = <GSBI_PROT_SPI>;
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0000000 0x0020000>;
- read-only;
- };
-
- partition@20000 {
- label = "MIBIB";
- reg = <0x0020000 0x0020000>;
- read-only;
- };
-
- partition@40000 {
- label = "SBL2";
- reg = <0x0040000 0x0040000>;
- read-only;
- };
-
- partition@80000 {
- label = "SBL3";
- reg = <0x0080000 0x0080000>;
- read-only;
- };
-
- partition@100000 {
- label = "DDRCONFIG";
- reg = <0x0100000 0x0010000>;
- read-only;
- };
-
- partition@110000 {
- label = "SSD";
- reg = <0x0110000 0x0010000>;
- read-only;
- };
-
- partition@120000 {
- label = "TZ";
- reg = <0x0120000 0x0080000>;
- read-only;
- };
-
- partition@1a0000 {
- label = "RPM";
- reg = <0x01a0000 0x0080000>;
- read-only;
- };
-
- partition@220000 {
- label = "APPSBL";
- reg = <0x0220000 0x0080000>;
- read-only;
- };
-
- partition@2a0000 {
- label = "APPSBLENV";
- reg = <0x02a0000 0x0010000>;
- read-only;
- };
-
- factory: partition@2b0000 {
- label = "PRODUCTDATA";
- reg = <0x02b0000 0x0030000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_factory_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_factory_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- macaddr_PRODUCTDATA_c: macaddr@c {
- reg = <0xc 0x6>;
- };
-
- macaddr_PRODUCTDATA_12: macaddr@12 {
- reg = <0x12 0x6>;
- };
- };
- };
-
- partition@2e0000 {
- label = "ART";
- reg = <0x02e0000 0x0040000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@320000 {
- label = "TP";
- reg = <0x0320000 0x0040000>;
- read-only;
- };
-
- partition@360000 {
- label = "TINY";
- reg = <0x0360000 0x0500000>;
- read-only;
- };
-
- partition@860000 {
- compatible = "denx,uimage";
- label = "firmware";
- reg = <0x0860000 0x17a0000>;
- };
- };
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
-
- qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
-
- nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- force_gen1 = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
-
- ieee80211-freq-limit = <2400000 2483000>;
- qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
-
- nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- function-enumerator = <1>;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- function-enumerator = <2>;
- default-state = "keep";
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- function-enumerator = <3>;
- default-state = "keep";
- };
- };
- };
-
- port@2 {
- reg = <2>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- default-state = "keep";
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- default-state = "keep";
- };
- };
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- default-state = "keep";
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- default-state = "keep";
- };
- };
- };
-
- port@4 {
- reg = <4>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- default-state = "keep";
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- default-state = "keep";
- };
- };
- };
-
- port@5 {
- reg = <5>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- default-state = "keep";
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- default-state = "keep";
- };
- };
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
- qca,sgmii-rxclk-falling-edge;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
- mdiobus = <&mdio0>;
- nvmem-cells = <&macaddr_factory_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
- mdiobus = <&mdio0>;
- nvmem-cells = <&macaddr_factory_6>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-
-/ {
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- ramoops@42100000 {
- compatible = "ramoops";
- reg = <0x42100000 0x40000>;
- record-size = <0x4000>;
- console-size = <0x4000>;
- ftrace-size = <0x4000>;
- pmsg-size = <0x4000>;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
- label-mac-device = &gmac2;
- };
-};
-
-&qcom_pinmux {
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- usb0_pwr_en_pin: usb0_pwr_en_pin {
- mux {
- pins = "gpio25";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- output-high;
- };
- };
-
- usb1_pwr_en_pin: usb1_pwr_en_pin {
- mux {
- pins = "gpio23";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- output-high;
- };
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- partition@20000 {
- label = "MIBIB";
- reg = <0x20000 0x20000>;
- read-only;
- };
-
- partition@40000 {
- label = "SBL2";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "SBL3";
- reg = <0x60000 0x30000>;
- read-only;
- };
-
- partition@90000 {
- label = "DDRCONFIG";
- reg = <0x90000 0x10000>;
- read-only;
- };
-
- partition@a0000 {
- label = "SSD";
- reg = <0xa0000 0x10000>;
- read-only;
- };
-
- partition@b0000 {
- label = "TZ";
- reg = <0xb0000 0x30000>;
- read-only;
- };
-
- partition@e0000 {
- label = "RPM";
- reg = <0xe0000 0x20000>;
- read-only;
- };
-
- partition@100000 {
- label = "fs-uboot";
- reg = <0x100000 0x70000>;
- read-only;
- };
-
- partition@170000 {
- label = "uboot-env";
- reg = <0x170000 0x40000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "radio";
- reg = <0x1b0000 0x40000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_radio_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_radio_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@1f0000 {
- label = "os-image";
- reg = <0x1f0000 0x400000>;
- };
-
- partition@5f0000 {
- label = "rootfs";
- reg = <0x5f0000 0x1900000>;
- };
-
- defaultmac: partition@1ef0000 {
- label = "default-mac";
- reg = <0x1ef0000 0x00200>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_defaultmac_8: macaddr@8 {
- compatible = "mac-base";
- reg = <0x8 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1ef0200 {
- label = "pin";
- reg = <0x1ef0200 0x00200>;
- read-only;
- };
-
- partition@1ef0400 {
- label = "product-info";
- reg = <0x1ef0400 0x0fc00>;
- read-only;
- };
-
- partition@1f00000 {
- label = "partition-table";
- reg = <0x1f00000 0x10000>;
- read-only;
- };
-
- partition@1f10000 {
- label = "soft-version";
- reg = <0x1f10000 0x10000>;
- read-only;
- };
-
- partition@1f20000 {
- label = "support-list";
- reg = <0x1f20000 0x10000>;
- read-only;
- };
-
- partition@1f30000 {
- label = "profile";
- reg = <0x1f30000 0x10000>;
- read-only;
- };
-
- partition@1f40000 {
- label = "default-config";
- reg = <0x1f40000 0x10000>;
- read-only;
- };
-
- partition@1f50000 {
- label = "user-config";
- reg = <0x1f50000 0x40000>;
- read-only;
- };
-
- partition@1f90000 {
- label = "qos-db";
- reg = <0x1f90000 0x40000>;
- read-only;
- };
-
- partition@1fd0000 {
- label = "usb-config";
- reg = <0x1fd0000 0x10000>;
- read-only;
- };
-
- partition@1fe0000 {
- label = "log";
- reg = <0x1fe0000 0x20000>;
- read-only;
- };
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb0_pwr_en_pin>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb1_pwr_en_pin>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_defaultmac_8 (-1)>, <&precal_radio_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_defaultmac_8 0>, <&precal_radio_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_defaultmac_8 1>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_defaultmac_8 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-ad7200-c2600.dtsi"
-
-/ {
- model = "TP-Link Talon AD7200";
- compatible = "tplink,ad7200", "qcom,ipq8064";
-
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- led_enable {
- label = "led-enable";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_LIGHTS_TOGGLE>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- lan {
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>;
- };
-
- usb1 {
- label = "blue:usb1";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "blue:wlan5g";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
- };
-
- usb3 {
- label = "blue:usb3";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g {
- label = "blue:wlan2g";
- gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
- };
-
- wan_orange {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- wan_blue {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
- };
-
- wlan60g {
- label = "blue:wlan60g";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
- };
-
- led_status: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio53", "gpio54", "gpio67";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio2", "gpio8", "gpio15", "gpio16", "gpio17", "gpio26",
- "gpio33", "gpio55", "gpio56", "gpio66";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-};
-
-&mdio0 {
- switch@10 {
- ports {
- port@1 {
- label = "wan";
- };
-
- port@2 {
- label = "lan1";
- };
-
- port@3 {
- label = "lan2";
- };
-
- port@4 {
- label = "lan3";
- };
-
- port@5 {
- label = "lan4";
- };
- };
- };
-};
-
-&pcie2 {
- status = "okay";
- max-link-speed = <1>;
-};
+++ /dev/null
-#include "qcom-ipq8064-v1.0.dtsi"
-
-/ {
- model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
- compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- rsvd@41200000 {
- reg = <0x41200000 0x300000>;
- no-map;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&flash {
- partitions {
- compatible = "qcom,smem-part";
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- /*
- port@6 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- asym-pause;
- };
- };
- */
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
+++ /dev/null
-#include "qcom-ipq8064-v1.0.dtsi"
-
-/ {
- model = "Qualcomm IPQ8064/AP161";
- compatible = "qcom,ipq8064-ap161", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- rsvd@41200000 {
- reg = <0x41200000 0x300000>;
- no-map;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
- };
-};
-
-&qcom_pinmux {
- rgmii2_pins: rgmii2-pins {
- mux {
- pins = "gpio27", "gpio28", "gpio29",
- "gpio30", "gpio31", "gpio32",
- "gpio51", "gpio52", "gpio59",
- "gpio60", "gpio61", "gpio62",
- "gpio2", "gpio66";
- };
- };
-};
-
-&flash {
- partitions {
- compatible = "qcom,smem-part";
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-};
-
-&pcie2 {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- /*
- port@6 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- asym-pause;
- };
- };
- */
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-
- phy3: ethernet-phy@3 {
- device_type = "ethernet-phy";
- reg = <3>;
- };
-};
-
-&gmac0 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <0>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
- mdiobus = <&mdio0>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
- mdiobus = <&mdio0>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
- mdiobus = <&mdio0>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2014 The ChromiumOS Authors
- */
-
-#include "qcom-ipq8064-onhub.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,gsbi.h>
-
-/ {
- model = "ASUS OnHub";
- compatible = "asus,onhub", "google,arkham", "qcom,ipq8064";
-};
-
-&qcom_pinmux {
- ap3223_pins: ap3223_pinmux {
- pins = "gpio22";
- function = "gpio";
- bias-none;
- };
-
- i2c7_pins: i2c7_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "gsbi7";
- };
- data {
- pins = "gpio8";
- bias-disable;
- };
- clk {
- pins = "gpio9";
- bias-disable;
- };
- };
-};
-
-&gsbi7 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi7_i2c {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c7_pins>;
- pinctrl-names = "default";
-
- ap3223@1c {
- compatible = "dynaimage,ap3223";
- reg = <0x1c>;
-
- pinctrl-0 = <&ap3223_pins>;
- pinctrl-names = "default";
-
- int-gpio = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
- };
-
- led-controller@32 {
- compatible = "national,lp5523";
- reg = <0x32>;
- clock-mode = /bits/ 8 <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@4 {
- reg = <4>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- };
-
- led@5 {
- reg = <5>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- };
-
- led@8 {
- reg = <8>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- };
- };
-};
+++ /dev/null
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-ad7200-c2600.dtsi"
-
-/ {
- model = "TP-Link Archer C2600";
- compatible = "tplink,c2600", "qcom,ipq8064";
-
- aliases {
- led-boot = &power;
- led-failsafe = &general;
- led-running = &power;
- led-upgrade = &general;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- ledswitch {
- label = "ledswitch";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_LIGHTS_TOGGLE>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- lan {
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;
- };
-
- usb4 {
- label = "white:usb_4";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb_2";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- wan_amber {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- wan_white {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- general: general {
- label = "white:general";
- gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio16", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33",
- "gpio53", "gpio66";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-};
+++ /dev/null
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Netgear Nighthawk X4 D7800";
- compatible = "netgear,d7800", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- rsvd@5fe00000 {
- reg = <0x5fe00000 0x200000>;
- reusable;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &power_white;
- led-failsafe = &power_amber;
- led-running = &power_white;
- led-upgrade = &power_amber;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs noinitrd";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- usb1 {
- label = "white:usb1";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb2";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- power_amber: power_amber {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- wan_white {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan_amber {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
-
- esata {
- label = "white:esata";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-
- power_white: power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- wifi {
- label = "white:wifi";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
- "gpio24","gpio26", "gpio53", "gpio64";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- usb0_pwr_en_pins: usb0_pwr_en_pins {
- mux {
- pins = "gpio15";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-
- usb1_pwr_en_pins: usb1_pwr_en_pins {
- mux {
- pins = "gpio16", "gpio68";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-};
-
-&sata_phy {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb0_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb1_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-names = "default";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie1_pins>;
- pinctrl-names = "default";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie2 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie2_pins>;
- pinctrl-names = "default";
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1180000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- qcadata@0 {
- label = "qcadata";
- reg = <0x0000000 0x0c80000>;
- read-only;
- };
-
- APPSBL@c80000 {
- label = "APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- APPSBLENV@1180000 {
- label = "APPSBLENV";
- reg = <0x1180000 0x0080000>;
- read-only;
- };
-
- art@1200000 {
- label = "art";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: macaddr@6 {
- compatible = "mac-base";
- reg = <0x6 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- artbak: art@1340000 {
- label = "artbak";
- reg = <0x1340000 0x0140000>;
- read-only;
- };
-
- kernel@1480000 {
- label = "kernel";
- reg = <0x1480000 0x0400000>;
- };
-
- ubi@1880000 {
- label = "ubi";
- reg = <0x1880000 0x6080000>;
- };
-
- reserve@7900000 {
- label = "reserve";
- reg = <0x7900000 0x0700000>;
- read-only;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_art_6 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8064-v1.0.dtsi"
-
-/ {
- model = "Qualcomm IPQ8064/DB149";
- compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
-
- aliases {
- serial0 = &gsbi2_serial;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- rsvd@41200000 {
- reg = <0x41200000 0x300000>;
- no-map;
- };
- };
-};
-
-&qcom_pinmux {
- rgmii0_pins: rgmii0_pins {
- mux {
- pins = "gpio2", "gpio66";
- drive-strength = <8>;
- bias-disable;
- };
- };
-};
-
-&gsbi2 {
- qcom,mode = <GSBI_PROT_I2C_UART>;
- status = "okay";
-
- gsbi2_serial: serial@12490000 {
- status = "okay";
- };
-};
-
-&gsbi4 {
- status = "disabled";
-};
-
-&gsbi4_serial {
- status = "disabled";
-};
-
-&flash {
- m25p,fast-read;
-
- partition@0 {
- label = "lowlevel_init";
- reg = <0x0 0x1b0000>;
- };
-
- partition@1 {
- label = "u-boot";
- reg = <0x1b0000 0x80000>;
- };
-
- partition@2 {
- label = "u-boot-env";
- reg = <0x230000 0x40000>;
- };
-
- partition@3 {
- label = "caldata";
- reg = <0x270000 0x40000>;
- };
-
- partition@4 {
- label = "firmware";
- reg = <0x2b0000 0x1d50000>;
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
-};
-
-&pcie2 {
- status = "okay";
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- /*
- port@6 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- asym-pause;
- };
- };
- */
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-
- phy6: ethernet-phy@6 {
- reg = <6>;
- };
-
- phy7: ethernet-phy@7 {
- reg = <7>;
- };
-};
-
-&gmac0 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <0>;
-
- pinctrl-0 = <&rgmii0_pins>;
- pinctrl-names = "default";
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <1>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
- phy-handle = <&phy6>;
-};
-
-&gmac3 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <3>;
- phy-handle = <&phy7>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-eax500.dtsi"
-
-/ {
- model = "Linksys EA7500 V1 WiFi Router";
- compatible = "linksys,ea7500-v1", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0xe000000>;
- device_type = "memory";
- };
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- chosen {
- /* look for root deviceblock nbr in this bootarg */
- find-rootblock = "ubi.mtd=";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio65", "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio6";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-};
-
-&partitions {
- partition@5f80000 {
- label = "sysdiag";
- reg = <0x5f80000 0x100000>;
- };
-
- partition@6080000 {
- label = "syscfg";
- reg = <0x6080000 0x1f80000>;
- };
-};
-
-&mdio0 {
- switch@10 {
- ports {
- port@1 {
- label = "wan";
- };
-
- port@2 {
- label = "lan1";
- };
-
- port@3 {
- label = "lan2";
- };
-
- port@4 {
- label = "lan3";
- };
-
- port@5 {
- label = "lan4";
- };
- };
- };
-};
+++ /dev/null
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-eax500.dtsi"
-
-/ {
- model = "Linksys EA8500 WiFi Router";
- compatible = "linksys,ea8500", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- wifi {
- label = "green:wifi";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio65", "gpio67", "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio6", "gpio53", "gpio54";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-};
-
-&sata_phy {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
-&partitions {
- partition@5f80000 {
- label = "syscfg";
- reg = <0x5f80000 0x2080000>;
- };
-};
-
-&gmac1 {
- qcom,phy_mdio_addr = <4>;
- qcom,poll_required = <1>;
- qcom,rgmii_delay = <0>;
- qcom,emulation = <0>;
-};
-
-/* LAN */
-&gmac2 {
- qcom,phy_mdio_addr = <0>; /* none */
- qcom,poll_required = <0>; /* no polling */
- qcom,rgmii_delay = <0>;
- qcom,emulation = <0>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-
-/ {
- chosen {
- bootargs = "console=ttyMSM0,115200n8";
- /* append to bootargs adding the root deviceblock nbr from bootloader */
- append-rootblock = "ubi.mtd=";
- };
-};
-
-&qcom_pinmux {
- /* eax500 routers reuse the pcie2 reset pin for switch reset pin */
- switch_reset: switch_reset_pins {
- mux {
- pins = "gpio63";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-up;
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- max-link-speed = <1>;
-};
-
-&pcie1 {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x0c80000>;
-
- partitions: partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0000000 0x0040000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x0040000 0x0140000>;
- read-only;
- };
-
- partition@180000 {
- label = "SBL2";
- reg = <0x0180000 0x0140000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "SBL3";
- reg = <0x02c0000 0x0280000>;
- read-only;
- };
-
- partition@540000 {
- label = "DDRCONFIG";
- reg = <0x0540000 0x0120000>;
- read-only;
- };
-
- partition@660000 {
- label = "SSD";
- reg = <0x0660000 0x0120000>;
- read-only;
- };
-
- partition@780000 {
- label = "TZ";
- reg = <0x0780000 0x0280000>;
- read-only;
- };
-
- partition@a00000 {
- label = "RPM";
- reg = <0x0a00000 0x0280000>;
- read-only;
- };
-
- art: partition@c80000 {
- label = "art";
- reg = <0x0c80000 0x0140000>;
- read-only;
- };
-
- partition@dc0000 {
- label = "APPSBL";
- reg = <0x0dc0000 0x0100000>;
- read-only;
- };
-
- partition@ec0000 {
- label = "u_env";
- reg = <0x0ec0000 0x0040000>;
- };
-
- partition@f00000 {
- label = "s_env";
- reg = <0x0f00000 0x0040000>;
- };
-
- partition@f40000 {
- label = "devinfo";
- reg = <0x0f40000 0x0040000>;
- };
-
- partition@f80000 {
- label = "kernel1";
- reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */
- };
-
- partition@1380000 {
- label = "rootfs1";
- reg = <0x1380000 0x2400000>;
- };
-
- partition@3780000 {
- label = "kernel2";
- reg = <0x3780000 0x2800000>;
- };
-
- partition@3b80000 {
- label = "rootfs2";
- reg = <0x3b80000 0x2400000>;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- /* Switch from documentation require at least 10ms for reset */
- reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
- reset-post-delay-us = <12000>;
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Fortinet FAP-421E";
- compatible = "fortinet,fap-421e", "qcom,ipq8064";
-
- memory@42000000 {
- device_type = "memory";
- reg = <0x42000000 0xe000000>;
- };
-
- reserved-memory {
- rsvd@41200000 {
- no-map;
- reg = <0x41200000 0x300000>;
- };
- wifi_dump@44000000 {
- no-map;
- reg = <0x44000000 0x600000>;
- };
- };
-
- aliases {
- led-boot = &led_power_yellow;
- led-failsafe = &led_power_yellow;
- led-running = &led_power_yellow;
- led-upgrade = &led_power_yellow;
- label-mac-device = &gmac0;
- };
-
- chosen {
- bootargs-override = "console=ttyMSM0,9600n8";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- eth1-amber {
- label = "amber:eth1";
- gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>;
- };
-
- eth1-yellow {
- label = "yellow:eth1";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- eth2-amber {
- label = "amber:eth2";
- gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>;
- };
-
- eth2-yellow {
- label = "yellow:eth2";
- gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
- };
-
- power-amber {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
- };
-
- led_power_yellow: power-yellow {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
- };
-
- 2g-yellow {
- label = "yellow:2g";
- gpios = <&qcom_pinmux 30 GPIO_ACTIVE_LOW>;
- };
-
- 5g-yellow {
- label = "yellow:5g";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- bias-pull-up;
- drive-strength = <2>;
- pins = "gpio56";
- };
- };
-
- led_pins: led_pins {
- mux {
- bias-pull-down;
- drive-strength = <2>;
- function = "gpio";
- output-low;
- pins = "gpio23";
- };
- };
-
- rgmii2_pins: rgmii2-pins {
- mux {
- bias-disable;
- drive-strength = <16>;
- function = "rgmii2";
- pins = "gpio66";
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- uart0_pins: uart0_pins {
- mux {
- bias-disable;
- drive-strength = <12>;
- function = "gsbi7";
- pins = "gpio6", "gpio7";
- };
- };
-
- usb_pwr_en_pins: usb_pwr_en_pins {
- mux {
- pins = "gpio22";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-low;
- };
- };
-};
-
-&gsbi7 {
- qcom,mode = <GSBI_PROT_I2C_UART>;
-
- status = "okay";
-};
-
-&gsbi7_serial{
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
-
- status = "okay";
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
- m25p,fast-read;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- partition@20000 {
- label = "MIBIB";
- reg = <0x20000 0x20000>;
- read-only;
- };
-
- partition@40000 {
- label = "SBL2";
- reg = <0x40000 0x40000>;
- read-only;
- };
-
- partition@80000 {
- label = "SBL3";
- reg = <0x80000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "DDRCONFIG";
- reg = <0x100000 0x10000>;
- read-only;
- };
-
- partition@110000 {
- label = "SSD";
- reg = <0x110000 0x10000>;
- read-only;
- };
-
- partition@120000 {
- label = "TZ";
- reg = <0x120000 0x80000>;
- read-only;
- };
-
- partition@1a0000 {
- label = "RPM";
- reg = <0x1a0000 0x80000>;
- read-only;
- };
-
- partition@220000 {
- label = "APPSBL";
- reg = <0x220000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_appsbl_7ff80: mac-address@7ff80 {
- compatible = "mac-base";
- reg = <0x7ff80 0xc>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@2a0000 {
- label = "APPSBLENV";
- reg = <0x2a0000 0x40000>;
- };
-
- partition@2e0000 {
- label = "ART";
- reg = <0x2e0000 0x40000>;
- read-only;
- };
-
- partition@320000 {
- label = "kernel";
- reg = <0x320000 0x600000>;
- };
-
- partition@920000 {
- label = "ubi";
- reg = <0x920000 0x1400000>;
- };
-
- partition@1d20000 {
- label = "reserved";
- reg = <0x1d20000 0x260000>;
- read-only;
- };
-
- partition@1f80000 {
- label = "config";
- reg = <0x1f80000 0x80000>;
- read-only;
- };
- };
- };
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_appsbl_7ff80 8>;
- nvmem-cell-names = "mac-address";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_appsbl_7ff80 16>;
- nvmem-cell-names = "mac-address";
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&mdio0 {
- status = "okay";
-
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- phy2: ethernet-phy@2 {
- reg = <2>;
- };
-};
-
-&gmac0 {
- status = "okay";
-
- phy-mode = "rgmii";
- qcom,id = <0>;
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
- nvmem-cells = <&macaddr_appsbl_7ff80 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
- nvmem-cells = <&macaddr_appsbl_7ff80 1>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- compatible = "asrock,g10", "qcom,ipq8064";
- model = "ASRock G10";
-
- aliases {
- ethernet0 = &gmac1;
- ethernet1 = &gmac0;
-
- led-boot = &led_status_blue;
- led-failsafe = &led_status_amber;
- led-running = &led_status_blue;
- led-upgrade = &led_status_amber;
- };
-
- chosen {
- bootargs-override = "console=ttyMSM0,115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- /*
- * this is a bit misleading. Because there are about seven
- * multicolor LEDs connected all wired together in parallel.
- */
-
- status_yellow {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_amber: status_amber {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_blue: status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- /*
- * LED is declared in vendors boardfile but it's not
- * working and the manual doesn't mention anything
- * about the LED being white.
-
- status_white {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
- */
- };
-
- i2c-gpio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "i2c-gpio";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */
- <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */
- i2c-gpio,delay-us = <5>;
- i2c-gpio,scl-output-only;
-
- mcu@50 {
- reg = <0x50>;
- compatible = "sonix,sn8f25e21";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- ir-remote {
- label = "ir-remote";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps5g {
- label = "wps5g";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps2g {
- label = "wps2g";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&gmac1 {
- status = "okay";
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gsbi4_serial {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1200000>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi5g: wifi@1,0 {
- reg = <0x00010000 0 0 0 0>;
- compatible = "qcom,ath10k";
- qcom,ath10k-calibration-variant = "ASRock-G10";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2g: wifi@1,0 {
- reg = <0x00010000 0 0 0 0>;
- compatible = "qcom,ath10k";
- qcom,ath10k-calibration-variant = "ASRock-G10";
- };
- };
-};
-
-&qcom_pinmux {
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio26";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio15", "gpio16", "gpio64", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- uart0_pins: uart0_pins {
- mux {
- pins = "gpio10", "gpio11";
- function = "gsbi4";
- drive-strength = <10>;
- bias-disable;
- };
- };
-};
-
-&rpm {
- pinctrl-0 = <&i2c4_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&tcsr {
- qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
-};
-
-/delete-node/ &pcie2_pins;
-/delete-node/ &pcie2;
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2014 The ChromiumOS Authors
- */
-
-#include "qcom-ipq8064-smb208.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac2;
- mdio-gpio0 = &mdio;
- serial0 = &gsbi4_serial;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- rsvd@41200000 {
- reg = <0x41200000 0x300000>;
- no-map;
- };
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- dev {
- label = "dev";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_CONFIG>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- mdio: mdio {
- compatible = "virtual,mdio-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
- };
- };
- };
-
- soc {
- rng@1a500000 {
- status = "disabled";
- };
-
- sound {
- compatible = "google,storm-audio";
- qcom,model = "ipq806x-storm";
- cpu = <&lpass>;
- codec = <&max98357a>;
- };
-
- lpass: lpass@28100000 {
- status = "okay";
- pinctrl-names = "default", "idle";
- pinctrl-0 = <&mi2s_default>;
- pinctrl-1 = <&mi2s_idle>;
- };
-
- max98357a: max98357a {
- compatible = "maxim,max98357a";
- #sound-dai-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmode_pins>;
- sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- rgmii0_pins: rgmii0_pins {
- mux {
- pins = "gpio2", "gpio66";
- drive-strength = <8>;
- bias-disable;
- };
- };
- mi2s_pins {
- mi2s_default: mi2s_default {
- dout {
- pins = "gpio32";
- function = "mi2s";
- drive-strength = <16>;
- bias-disable;
- };
- sync {
- pins = "gpio27";
- function = "mi2s";
- drive-strength = <16>;
- bias-disable;
- };
- clk {
- pins = "gpio28";
- function = "mi2s";
- drive-strength = <16>;
- bias-disable;
- };
- };
- mi2s_idle: mi2s_idle {
- dout {
- pins = "gpio32";
- function = "mi2s";
- drive-strength = <2>;
- bias-pull-down;
- };
- sync {
- pins = "gpio27";
- function = "mi2s";
- drive-strength = <2>;
- bias-pull-down;
- };
- clk {
- pins = "gpio28";
- function = "mi2s";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
- };
-
- mdio_pins: mdio_pins {
- mux {
- pins = "gpio0", "gpio1";
- function = "gpio";
- drive-strength = <8>;
- bias-disable;
- };
- rst {
- pins = "gpio26";
- output-low;
- };
- };
-
- sdmode_pins: sdmode_pinmux {
- pins = "gpio25";
- function = "gpio";
- drive-strength = <16>;
- bias-disable;
- };
-
- sdcc1_pins: sdcc1_pinmux {
- mux {
- pins = "gpio38", "gpio39", "gpio40",
- "gpio41", "gpio42", "gpio43",
- "gpio44", "gpio45", "gpio46",
- "gpio47";
- function = "sdc1";
- };
- cmd {
- pins = "gpio45";
- drive-strength = <10>;
- bias-pull-up;
- };
- data {
- pins = "gpio38", "gpio39", "gpio40",
- "gpio41", "gpio43", "gpio44",
- "gpio46", "gpio47";
- drive-strength = <10>;
- bias-pull-up;
- };
- clk {
- pins = "gpio42";
- drive-strength = <16>;
- bias-pull-down;
- };
- };
-
- i2c1_pins: i2c1_pinmux {
- pins = "gpio53", "gpio54";
- function = "gsbi1";
- bias-disable;
- };
-
- rpm_i2c_pinmux: rpm_i2c_pinmux {
- mux {
- pins = "gpio12", "gpio13";
- function = "gsbi4";
- drive-strength = <12>;
- bias-disable;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- /delete-property/ bias-none;
- /delete-property/ drive-strength;
- };
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- fw_pinmux {
- wp {
- pins = "gpio17";
- output-low;
- };
- };
-
- button_pins: button_pins {
- recovery {
- pins = "gpio16";
- function = "gpio";
- bias-none;
- };
- developer {
- pins = "gpio15";
- function = "gpio";
- bias-none;
- };
- };
-
- spi6_pins: spi6_pins {
- mux {
- pins = "gpio55", "gpio56", "gpio58";
- function = "gsbi6";
- bias-pull-down;
- };
- data {
- pins = "gpio55", "gpio56";
- drive-strength = <10>;
- };
- cs {
- pins = "gpio57";
- drive-strength = <10>;
- bias-pull-up;
- output-high;
- };
- clk {
- pins = "gpio58";
- drive-strength = <12>;
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&gmac0 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <0>;
-
- pinctrl-0 = <&rgmii0_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gsbi1 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi1_i2c {
- status = "okay";
-
- clock-frequency = <100000>;
-
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
-
- tpm@20 {
- compatible = "infineon,slb9645tt";
- reg = <0x20>;
- powered-while-suspended;
- };
-};
-
-&gsbi4 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi4_serial {
- status = "okay";
-};
-
-&gsbi5 {
- status = "okay";
- qcom,mode = <GSBI_PROT_SPI>;
-
- spi4: spi@1a280000 {
- status = "okay";
- spi-max-frequency = <50000000>;
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 0>;
-
- flash: flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- };
- };
-};
-
-&gsbi6 {
- status = "okay";
- qcom,mode = <GSBI_PROT_SPI>;
-};
-
-&gsbi6_spi {
- status = "okay";
- spi-max-frequency = <25000000>;
-
- pinctrl-0 = <&spi6_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
-
- dmas = <&adm_dma 8 0xb>,
- <&adm_dma 7 0x14>;
- dma-names = "rx", "tx";
-
- /*
- * This "spidev" was included in the manufacturer device tree. I suspect
- * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's
- * no driver or binding for this at the moment.
- */
- spidev@0 {
- compatible = "spidev";
- reg = <0>;
- spi-max-frequency = <25000000>;
- };
-};
-
-&pcie0 {
- status = "okay";
-
- pcie@0 {
- reg = <0 0 0 0 0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- interrupt-controller;
-
- ath10k@0,0 {
- reg = <0 0 0 0 0>;
- device_type = "pci";
- qcom,ath10k-sa-gpio = <2 3 4 0>;
- qcom,ath10k-sa-gpio-func = <5 5 5 0>;
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- pcie@0 {
- reg = <0 0 0 0 0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- interrupt-controller;
-
- ath10k@0,0 {
- reg = <0 0 0 0 0>;
- device_type = "pci";
- qcom,ath10k-sa-gpio = <2 3 4 0>;
- qcom,ath10k-sa-gpio-func = <5 5 5 0>;
- };
- };
-};
-
-&pcie2 {
- status = "okay";
-
- pcie@0 {
- reg = <0 0 0 0 0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- interrupt-controller;
-
- ath10k@0,0 {
- reg = <0 0 0 0 0>;
- device_type = "pci";
- };
- };
-};
-
-&rpm {
- pinctrl-0 = <&rpm_i2c_pinmux>;
- pinctrl-names = "default";
-};
-
-&sdcc1 {
- status = "okay";
- pinctrl-0 = <&sdcc1_pins>;
- pinctrl-names = "default";
- /delete-property/ mmc-ddr-1_8v;
-};
-
-&tcsr {
- compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon";
- qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8064-v1.0.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Netgear Nighthawk X4 R7500";
- compatible = "netgear,r7500", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0xe000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- rsvd@41200000 {
- reg = <0x41200000 0x300000>;
- no-map;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &power_white;
- led-failsafe = &power_amber;
- led-running = &power_white;
- led-upgrade = &power_amber;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs noinitrd";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- usb1 {
- label = "white:usb1";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb2";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- power_amber: power_amber {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- wan_white {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan_amber {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
-
- esata {
- label = "white:esata";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-
- power_white: power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- wifi {
- label = "white:wifi";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
- "gpio24","gpio26", "gpio53", "gpio64";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-};
-
-&gsbi5 {
- status = "disabled";
-
- spi@1a280000 {
- status = "disabled";
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1180000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- qcadata@0 {
- label = "qcadata";
- reg = <0x0000000 0x0c80000>;
- read-only;
- };
-
- APPSBL@c80000 {
- label = "APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- APPSBLENV@1180000 {
- label = "APPSBLENV";
- reg = <0x1180000 0x0080000>;
- read-only;
- };
-
- art: art@1200000 {
- label = "art";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
- };
- };
-
- kernel@1340000 {
- label = "kernel";
- reg = <0x1340000 0x0400000>;
- };
-
- ubi@1740000 {
- label = "ubi";
- reg = <0x1740000 0x1600000>;
- };
-
- netgear@2d40000 {
- label = "netgear";
- reg = <0x2d40000 0x0c00000>;
- read-only;
- };
-
- reserve@3940000 {
- label = "reserve";
- reg = <0x3940000 0x46c0000>;
- read-only;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_art_6>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&tcsr {
- qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
- compatible = "qcom,tcsr";
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Netgear Nighthawk X4 R7500v2";
- compatible = "netgear,r7500v2", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- rsvd@5fe00000 {
- reg = <0x5fe00000 0x200000>;
- reusable;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs noinitrd";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- usb1 {
- label = "amber:usb1";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb3 {
- label = "amber:usb3";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- internet {
- label = "white:internet";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
-
- esata {
- label = "white:esata";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- wifi {
- label = "white:wifi";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
- "gpio24","gpio26", "gpio53", "gpio64";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- usb0_pwr_en_pins: usb0_pwr_en_pins {
- mux {
- pins = "gpio15";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-
- usb1_pwr_en_pins: usb1_pwr_en_pins {
- mux {
- pins = "gpio16", "gpio68";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-};
-
-&sata_phy {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb0_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb1_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-names = "default";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pcie1_pins>;
- pinctrl-names = "default";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1180000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- qcadata@0 {
- label = "qcadata";
- reg = <0x0000000 0x0c80000>;
- read-only;
- };
-
- APPSBL@c80000 {
- label = "APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- APPSBLENV@1180000 {
- label = "APPSBLENV";
- reg = <0x1180000 0x0080000>;
- read-only;
- };
-
- art@1200000 {
- label = "art";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: macaddr@6 {
- compatible = "mac-base";
- reg = <0x6 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- artbak: art@1340000 {
- label = "artbak";
- reg = <0x1340000 0x0140000>;
- read-only;
- };
-
- kernel@1480000 {
- label = "kernel";
- reg = <0x1480000 0x0400000>;
- };
-
- ubi@1880000 {
- label = "ubi";
- reg = <0x1880000 0x6080000>;
- };
-
- reserve@7900000 {
- label = "reserve";
- reg = <0x7900000 0x0700000>;
- read-only;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_art_6 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2014 The ChromiumOS Authors
- */
-
-#include "qcom-ipq8064-onhub.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,gsbi.h>
-
-/ {
- model = "TP-Link OnHub";
- compatible = "tplink,onhub", "google,whirlwind-sp5", "qcom,ipq8064";
-};
-
-&qcom_pinmux {
- i2c7_pins: i2c7_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "gsbi7";
- };
- data {
- pins = "gpio8";
- bias-disable;
- };
- clk {
- pins = "gpio9";
- bias-disable;
- };
- };
-};
-
-&gsbi7 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi7_i2c {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c7_pins>;
- pinctrl-names = "default";
-
- led-controller@32 {
- compatible = "national,lp5523";
- reg = <0x32>;
- clock-mode = /bits/ 8 <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-0";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-0";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-0";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@3 {
- reg = <3>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-1";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@4 {
- reg = <4>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-1";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@5 {
- reg = <5>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-1";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@6 {
- reg = <6>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-2";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@7 {
- reg = <7>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-2";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@8 {
- reg = <8>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-2";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
- };
-
- led-controller@33 {
- compatible = "national,lp5523";
- reg = <0x33>;
- clock-mode = /bits/ 8 <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-3";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-3";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-3";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@3 {
- reg = <3>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-4";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@4 {
- reg = <4>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-4";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@5 {
- reg = <5>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-4";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@6 {
- reg = <6>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-5";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@7 {
- reg = <7>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-5";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@8 {
- reg = <8>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-5";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Ubiquiti UniFi AC HD";
- compatible = "ubnt,unifi-ac-hd", "qcom,ipq8064";
-
- aliases {
- label-mac-device = &gmac2;
- led-boot = &led_dome_white;
- led-failsafe = &led_dome_white;
- led-running = &led_dome_blue;
- led-upgrade = &led_dome_blue;
- mdio-gpio0 = &mdio0;
- ethernet0 = &gmac2;
- ethernet1 = &gmac1;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_dome_blue: dome_blue {
- label = "blue:dome";
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- led_dome_white: dome_white {
- label = "white:dome";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio9", "gpio53";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- output-low;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- drive-strength = <10>;
- bias-none;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <12>;
- };
- };
-};
-
-&CPU_SPC {
- status = "disabled";
-};
-
-&gsbi5 {
- status = "okay";
-
- qcom,mode = <GSBI_PROT_SPI>;
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
- cs-gpios = <&qcom_pinmux 20 0>;
-
- flash@0 {
- compatible = "mx25u25635f", "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- partition@20000 {
- label = "MIBIB";
- reg = <0x20000 0x10000>;
- read-only;
- };
-
- partition@30000 {
- label = "SBL2";
- reg = <0x30000 0x20000>;
- read-only;
- };
-
- partition@50000 {
- label = "SBL3";
- reg = <0x50000 0x30000>;
- read-only;
- };
-
- partition@80000 {
- label = "DDRCONFIG";
- reg = <0x80000 0x10000>;
- read-only;
- };
-
- partition@90000 {
- label = "SSD";
- reg = <0x90000 0x10000>;
- read-only;
- };
-
- partition@a0000 {
- label = "TZ";
- reg = <0xa0000 0x30000>;
- read-only;
- };
-
- partition@d0000 {
- label = "RPM";
- reg = <0xd0000 0x20000>;
- read-only;
- };
-
- partition@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "APPSBLENV";
- reg = <0x1b0000 0x10000>;
- read-only;
- };
-
- eeprom: partition@1c0000 {
- label = "EEPROM";
- reg = <0x1c0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_eeprom_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_eeprom_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
- };
- };
-
- partition@1d0000 {
- label = "bootselect";
- reg = <0x1d0000 0x10000>;
- };
-
- partition@1e0000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x1e0000 0xe70000>;
- };
-
- partition@1050000 {
- label = "kernel1";
- reg = <0x1050000 0xe70000>;
- read-only;
- };
-
- partition@1ec0000 {
- label = "debug";
- reg = <0x1ec0000 0x100000>;
- read-only;
- };
-
- partition@1fc0000 {
- label = "cfg";
- reg = <0x1fc0000 0x40000>;
- read-only;
- };
- };
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- phy4: ethernet-phy@4 {
- reg = <4>;
- };
-
- phy5: ethernet-phy@5 {
- reg = <5>;
- };
-};
-
-&gmac1 {
- status = "okay";
-
- mdiobus = <&mdio0>;
- phy-handle = <&phy5>;
- phy-mode = "sgmii";
- qcom,id = <1>;
-
- nvmem-cells = <&macaddr_eeprom_6>;
- nvmem-cell-names = "mac-address";
-};
-
-&gmac2 {
- status = "okay";
-
- mdiobus = <&mdio0>;
- phy-handle = <&phy4>;
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_eeprom_0>;
- nvmem-cell-names = "mac-address";
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
-};
-
-&tcsr {
- status = "okay";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "TP-Link Archer VR2600v";
- compatible = "tplink,vr2600v", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &power;
- led-failsafe = &general;
- led-running = &power;
- led-upgrade = &general;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- dect {
- label = "dect";
- gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_PHONE>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- ledswitch {
- label = "ledswitch";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_LIGHTS_TOGGLE>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- dsl {
- label = "white:dsl";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- lan {
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g {
- label = "white:wlan2g";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "white:wlan5g";
- gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- phone {
- label = "white:phone";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
- };
-
- general: general {
- label = "white:general";
- gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17",
- "gpio26", "gpio53", "gpio56", "gpio66";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi4: spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- partition@20000 {
- label = "MIBIB";
- reg = <0x20000 0x20000>;
- read-only;
- };
-
- partition@40000 {
- label = "SBL2";
- reg = <0x40000 0x40000>;
- read-only;
- };
-
- partition@80000 {
- label = "SBL3";
- reg = <0x80000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "DDRCONFIG";
- reg = <0x100000 0x10000>;
- read-only;
- };
-
- partition@110000 {
- label = "SSD";
- reg = <0x110000 0x10000>;
- read-only;
- };
-
- partition@120000 {
- label = "TZ";
- reg = <0x120000 0x80000>;
- read-only;
- };
-
- partition@1a0000 {
- label = "RPM";
- reg = <0x1a0000 0x80000>;
- read-only;
- };
-
- partition@220000 {
- label = "APPSBL";
- reg = <0x220000 0x80000>;
- read-only;
- };
-
- partition@2a0000 {
- label = "APPSBLENV";
- reg = <0x2a0000 0x40000>;
- read-only;
- };
-
- partition@2e0000 {
- label = "OLDART";
- reg = <0x2e0000 0x40000>;
- read-only;
- };
-
- partition@320000 {
- label = "firmware";
- reg = <0x320000 0xc60000>;
- compatible = "openwrt,uimage";
- openwrt,offset = <512>; /* account for pad-extra 512 */
- };
-
- /* hole 0xf80000 - 0xfaf100 */
-
- partition@faf100 {
- label = "default-mac";
- reg = <0xfaf100 0x00200>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_defaultmac_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@fc0000 {
- label = "ART";
- reg = <0xfc0000 0x40000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_defaultmac_0 (-1)>, <&precal_ART_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_defaultmac_0 0>, <&precal_ART_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_defaultmac_0 1>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_defaultmac_0 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "NEC Aterm WG2600HP";
- compatible = "nec,wg2600hp", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &power_green;
- led-failsafe = &power_red;
- led-running = &power_green;
- led-upgrade = &power_green;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- bridge {
- label = "bridge";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- converter {
- label = "converter";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- converter_green {
- label = "green:converter";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;
- };
-
- power_red: power_red {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- active_green {
- label = "green:active";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- active_red {
- label = "red:active";
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
- };
-
- converter_red {
- label = "red:converter";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_green {
- label = "green:wlan2g";
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_red {
- label = "red:wlan2g";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g_green {
- label = "green:wlan5g";
- gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g_red {
- label = "red:wlan5g";
- gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
- };
-
- tv_green {
- label = "green:tv";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
-
- tv_red {
- label = "red:tv";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&CPU_SPC {
- status = "disabled";
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
-switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
- qca,sgmii-rxclk-falling-edge;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_PRODUCTDATA_6>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_PRODUCTDATA_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gsbi5 {
- status = "okay";
-
- qcom,mode = <GSBI_PROT_SPI>;
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- SBL1@0 {
- label = "SBL1";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- MIBIB@20000 {
- label = "MIBIB";
- reg = <0x20000 0x20000>;
- read-only;
- };
-
- SBL2@40000 {
- label = "SBL2";
- reg = <0x40000 0x40000>;
- read-only;
- };
-
- SBL3@80000 {
- label = "SBL3";
- reg = <0x80000 0x80000>;
- read-only;
- };
-
- DDRCONFIG@100000 {
- label = "DDRCONFIG";
- reg = <0x100000 0x10000>;
- read-only;
- };
-
- SSD@110000 {
- label = "SSD";
- reg = <0x110000 0x10000>;
- read-only;
- };
-
- TZ@120000 {
- label = "TZ";
- reg = <0x120000 0x80000>;
- read-only;
- };
-
- RPM@1a0000 {
- label = "RPM";
- reg = <0x1a0000 0x80000>;
- read-only;
- };
-
- APPSBL@220000 {
- label = "APPSBL";
- reg = <0x220000 0x80000>;
- read-only;
- };
-
- APPSBLENV@2a0000 {
- label = "APPSBLENV";
- reg = <0x2a0000 0x10000>;
- };
-
- PRODUCTDATA: PRODUCTDATA@2b0000 {
- label = "PRODUCTDATA";
- reg = <0x2b0000 0x30000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_PRODUCTDATA_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_PRODUCTDATA_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- macaddr_PRODUCTDATA_c: macaddr@c {
- reg = <0xc 0x6>;
- };
-
- macaddr_PRODUCTDATA_12: macaddr@12 {
- reg = <0x12 0x6>;
- };
- };
- };
-
- ART@2e0000 {
- label = "ART";
- reg = <0x2e0000 0x40000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- TP@320000 {
- label = "TP";
- reg = <0x320000 0x40000>;
- read-only;
- };
-
- TINY@360000 {
- label = "TINY";
- reg = <0x360000 0x500000>;
- read-only;
- };
-
- firmware@860000 {
- compatible = "denx,uimage";
- label = "firmware";
- reg = <0x860000 0x17a0000>;
- };
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio16", "gpio54", "gpio24", "gpio25";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14",
- "gpio15", "gpio55", "gpio56", "gpio57", "gpio58",
- "gpio64", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- usb_pwr_en_pins: usb_pwr_en_pins {
- mux {
- pins = "gpio22";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- output-high;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright (C) 2017 Christian Mehlis <christian@m3hlis.de>
- * Copyright (C) 2018 Mathias Kresin <dev@kresin.me>
- * All rights reserved.
- */
-
-#include "qcom-ipq8064-v1.0.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- compatible = "compex,wpq864", "qcom,ipq8064";
- model = "Compex WPQ864";
-
- aliases {
- mdio-gpio0 = &mdio0;
- ethernet0 = &gmac1;
- ethernet1 = &gmac0;
-
- led-boot = &led_pass;
- led-failsafe = &led_fail;
- led-running = &led_pass;
- led-upgrade = &led_pass;
- };
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- rss4 {
- label = "green:rss4";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- rss3 {
- label = "green:rss3";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- rss2 {
- label = "orange:rss2";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
- };
-
- rss1 {
- label = "red:rss1";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- led_pass: pass {
- label = "green:pass";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
-
- led_fail: fail {
- label = "green:fail";
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb-pcie {
- label = "green:usb-pcie";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- beeper {
- compatible = "gpio-beeper";
-
- pinctrl-0 = <&beeper_pins>;
- pinctrl-names = "default";
-
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&rpm {
- pinctrl-0 = <&rpm_pins>;
- pinctrl-names = "default";
-};
-
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- mt29f2g08abbeah4@0 {
- compatible = "qcom,nandcs";
-
- reg = <0>;
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0000000 0x0040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x0040000 0x0140000>;
- read-only;
- };
-
- partition@180000 {
- label = "0:SBL2";
- reg = <0x0180000 0x0140000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "0:SBL3";
- reg = <0x02c0000 0x0280000>;
- read-only;
- };
-
- partition@540000 {
- label = "0:DDRCONFIG";
- reg = <0x0540000 0x0120000>;
- read-only;
- };
-
- partition@660000 {
- label = "0:SSD";
- reg = <0x0660000 0x0120000>;
- read-only;
- };
-
- partition@780000 {
- label = "0:TZ";
- reg = <0x0780000 0x0280000>;
- read-only;
- };
-
- partition@a00000 {
- label = "0:RPM";
- reg = <0x0a00000 0x0280000>;
- read-only;
- };
-
- partition@c80000 {
- label = "0:APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- partition@1180000 {
- label = "0:APPSBLENV";
- reg = <0x1180000 0x0080000>;
- };
-
- partition@1200000 {
- label = "0:ART";
- reg = <0x1200000 0x0140000>;
- };
-
- partition@1340000 {
- label = "ubi";
- reg = <0x1340000 0x4000000>;
- };
-
- partition@5340000 {
- label = "0:BOOTCONFIG";
- reg = <0x5340000 0x0060000>;
- };
-
- partition@53a0000 {
- label = "0:SBL2_1";
- reg = <0x53a0000 0x0140000>;
- read-only;
- };
-
- partition@54e0000 {
- label = "0:SBL3_1";
- reg = <0x54e0000 0x0280000>;
- read-only;
- };
-
- partition@5760000 {
- label = "0:DDRCONFIG_1";
- reg = <0x5760000 0x0120000>;
- read-only;
- };
-
- partition@5880000 {
- label = "0:SSD_1";
- reg = <0x5880000 0x0120000>;
- read-only;
- };
-
- partition@59a0000 {
- label = "0:TZ_1";
- reg = <0x59a0000 0x0280000>;
- read-only;
- };
-
- partition@5c20000 {
- label = "0:RPM_1";
- reg = <0x5c20000 0x0280000>;
- read-only;
- };
-
- partition@5ea0000 {
- label = "0:BOOTCONFIG1";
- reg = <0x5ea0000 0x0060000>;
- };
-
- partition@5f00000 {
- label = "0:APPSBL_1";
- reg = <0x5f00000 0x0500000>;
- read-only;
- };
-
- partition@6400000 {
- label = "ubi_1";
- reg = <0x6400000 0x4000000>;
- };
-
- partition@a400000 {
- label = "unused";
- reg = <0xa400000 0x5c00000>;
- };
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gsbi4_serial {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-};
-
-&flash {
- compatible = "jedec,spi-nor";
-};
-
-&sata_phy {
- status = "disabled";
-};
-
-&sata {
- status = "disabled";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-
- rx_eq = <2>;
- tx_deamp_3_5db = <32>;
- mpll = <160>;
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-
- rx_eq = <2>;
- tx_deamp_3_5db = <32>;
- mpll = <160>;
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-};
-
-&pcie1 {
- status = "okay";
-};
-
-&pcie2 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-};
-
-&qcom_pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinctrl0 {
- pcie0_pcie2_perst {
- pins = "gpio3";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio22",
- "gpio23", "gpio24", "gpio25", "gpio53";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio54";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- beeper_pins: beeper_pins {
- mux {
- pins = "gpio55";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- rpm_pins: rpm_pins {
- mux {
- pins = "gpio12", "gpio13";
- function = "gsbi4";
- drive-strength = <10>;
- bias-disable;
- };
- };
-
- uart0_pins: uart0_pins {
- mux {
- pins = "gpio10", "gpio11";
- function = "gsbi4";
- drive-strength = <10>;
- bias-disable;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19";
- function = "gsbi5";
- drive-strength = <10>;
- bias-pull-down;
- };
-
- clk {
- pins = "gpio21";
- function = "gsbi5";
- drive-strength = <12>;
- bias-pull-down;
- };
-
- cs {
- pins = "gpio20";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-};
-
-&tcsr {
- qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Buffalo WXR-2533DHP";
- compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064";
-
- memory@42000000 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- led-boot = &power;
- led-failsafe = &diag;
- led-running = &power;
- led-upgrade = &power;
- };
-
- chosen {
- /* use "ubi_rootfs" volume in "ubi" partition as rootfs */
- bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "usbport";
- trigger-sources = <&hub_port0 &hub_port1>;
- };
-
- guestport {
- label = "green:guestport";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- diag: diag {
- label = "orange:diag";
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- internet_orange {
- label = "orange:internet";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
- };
-
- internet_white {
- label = "white:internet";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- wireless_orange {
- label = "orange:wireless";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- wireless_white {
- label = "white:wireless";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
-
- router_orange {
- label = "orange:router";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
- };
-
- router_white {
- label = "white:router";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- power {
- label = "power";
- gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- eject {
- label = "eject";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_EJECTCD>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- guest {
- label = "guest";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- ap {
- label = "ap";
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- router {
- label = "router";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- auto {
- label = "auto";
- gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- cs@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- ubi@0 {
- label = "ubi";
- reg = <0x0000000 0x4000000>;
- };
-
- rootfs_1@4000000 {
- label = "rootfs_1";
- reg = <0x4000000 0x4000000>;
- };
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_ART_6>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_ART_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gsbi4_serial {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-};
-
-&gsbi5 {
- status = "okay";
- qcom,mode = <GSBI_PROT_SPI>;
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- SBL1@0 {
- label = "SBL1";
- reg = <0x0 0x10000>;
- read-only;
- };
-
- MIBIB@10000 {
- label = "MIBIB";
- reg = <0x10000 0x20000>;
- read-only;
- };
-
- SBL2@30000 {
- label = "SBL2";
- reg = <0x30000 0x30000>;
- read-only;
- };
-
- SBL3@60000 {
- label = "SBL3";
- reg = <0x60000 0x30000>;
- read-only;
- };
-
- DDRCONFIG@90000 {
- label = "DDRCONFIG";
- reg = <0x90000 0x10000>;
- read-only;
- };
-
- SSD@a0000 {
- label = "SSD";
- reg = <0xa0000 0x10000>;
- read-only;
- };
-
- TZ@b0000 {
- label = "TZ";
- reg = <0xb0000 0x30000>;
- read-only;
- };
-
- RPM@e0000 {
- label = "RPM";
- reg = <0xe0000 0x20000>;
- read-only;
- };
-
- APPSBL@100000 {
- label = "APPSBL";
- reg = <0x100000 0x70000>;
- read-only;
- };
-
- APPSBLENV@170000 {
- label = "APPSBLENV";
- reg = <0x170000 0x10000>;
- read-only;
- };
-
- ART@180000 {
- label = "ART";
- reg = <0x180000 0x40000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_ART_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_ART_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- macaddr_ART_18: macaddr@18 {
- reg = <0x18 0x6>;
- };
-
- macaddr_ART_1e: macaddr@1e {
- reg = <0x1e 0x6>;
- };
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- BOOTCONFIG@1c0000 {
- label = "BOOTCONFIG";
- reg = <0x1c0000 0x10000>;
- read-only;
- };
-
- APPSBL_1@1d0000 {
- label = "APPSBL_1";
- reg = <0x1d0000 0x70000>;
- read-only;
- };
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&dwc3_0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- hub_port0: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-};
-
-&dwc3_1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- hub_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57",
- "gpio58", "gpio64", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22",
- "gpio23", "gpio24", "gpio25", "gpio26", "gpio53";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- uart0_pins: uart0_pins {
- mux {
- pins = "gpio10", "gpio11";
- function = "gsbi4";
- drive-strength = <12>;
- bias-disable;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs{
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- usb_pwr_en_pins: usb_pwr_en_pins {
- mux{
- pins = "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- output-high;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8065-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Nokia AC400i";
- compatible = "nokia,ac400i", "qcom,ipq8065", "qcom,ipq8064";
-
- aliases {
- mdio-gpio0 = &mdio0;
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
-
- led-boot = &pwr_red;
- led-failsafe = &pwr_red;
- led-running = &pwr_green;
- led-upgrade = &pwr_green;
- };
-
- chosen {
- bootargs-override = " console=ttyMSM0,115200n8 ubi.mtd=ubi root=/dev/ubiblock0_2";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- 5g_red {
- label = "red:5g";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>;
- };
-
- 5g_green {
- label = "green:5g";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
-
- 2g_red {
- label = "red:2g";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
-
- 2g_green {
- label = "green:2g";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
- };
-
- eth1_red {
- label = "red:eth1";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_HIGH>;
- };
-
- eth1_green {
- label = "green:eth1";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
- };
-
- eth2_red {
- label = "red:eth2";
- gpios = <&qcom_pinmux 67 GPIO_ACTIVE_HIGH>;
- };
-
- eth2_green {
- label = "green:eth2";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
- };
-
- ctrl_red {
- label = "red:ctrl";
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
- };
-
- ctrl_green {
- label = "green:ctrl";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
- };
-
- pwr_red: pwr_red {
- label = "red:pwr";
- gpios = <&qcom_pinmux 2 GPIO_ACTIVE_LOW>;
- };
-
- pwr_green: pwr_green {
- label = "green:pwr";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19";
- function = "gsbi5";
- drive-strength = <10>;
- bias-pull-down;
- };
-
- clk {
- pins = "gpio21";
- function = "gsbi5";
- drive-strength = <12>;
- bias-pull-down;
- };
-
- cs {
- pins = "gpio20";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio65", "gpio64",
- "gpio53", "gpio54",
- "gpio68", "gpio22",
- "gpio67", "gpio23",
- "gpio55", "gpio56",
- "gpio2", "gpio26";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio15";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi4: spi@1a280000 {
- status = "okay";
- spi-max-frequency = <50000000>;
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
- };
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "Nokia-AC400i";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "Nokia-AC400i";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-
-};
-
-//POE
-&gmac0 {
- status = "okay";
- qcom,id = <0>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- mdiobus = <&mdio0>;
- phy-handle = <&phy0>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-//LAN1
-&gmac1 {
- status = "okay";
- qcom,id = <1>;
-
- mdiobus = <&mdio0>;
- phy-handle = <&phy1>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&nand {
- status = "okay";
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- rootfs@0 {
- label = "rootfs";
- reg = <0x0000000 0x4000000>;
- };
-
- rootfs_1@4000000 {
- label = "rootfs_1";
- reg = <0x4000000 0x4000000>;
- };
-
- cfg@8000000 {
- label = "cfg";
- reg = <0x8000000 0x8000000>;
- };
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8065-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ZyXEL NBG6817";
- compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
- sdcc1 = &sdcc1;
-
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1";
- append-rootblock = "root=/dev/mmcblk0p";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- internet {
- label = "white:internet";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- wifi2g {
- label = "amber:wifi2g";
- gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
- };
-
- /* wifi2g amber from the manual is missing */
-
- wifi5g {
- label = "amber:wifi5g";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-
- /* wifi5g amber from the manual is missing */
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio53", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio9", "gpio26", "gpio33", "gpio64";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- mdio0_pins: mdio0-pins {
- clk {
- pins = "gpio1";
- input-disable;
- };
- };
-
- rgmii2_pins: rgmii2-pins {
- tx {
- pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
- input-disable;
- };
- };
-
- spi_pins: spi_pins {
- cs {
- pins = "gpio20";
- drive-strength = <12>;
- };
- };
-
- usb0_pwr_en_pins: usb0_pwr_en_pins {
- mux {
- pins = "gpio16", "gpio17";
- function = "gpio";
- drive-strength = <12>;
- };
-
- pwr {
- pins = "gpio17";
- bias-pull-down;
- output-high;
- };
-
- ovc {
- pins = "gpio16";
- bias-pull-up;
- };
- };
-
- usb1_pwr_en_pins: usb1_pwr_en_pins {
- mux {
- pins = "gpio14", "gpio15";
- function = "gpio";
- drive-strength = <12>;
- };
-
- pwr {
- pins = "gpio14";
- bias-pull-down;
- output-high;
- };
-
- ovc {
- pins = "gpio15";
- bias-pull-up;
- };
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi4: spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <51200000>;
- reg = <0>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb0_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb1_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-names = "default";
-};
-
-&pcie1 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pcie1_pins>;
- pinctrl-names = "default";
- max-link-speed = <1>;
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
- qcom,phy_mdio_addr = <4>;
- qcom,poll_required = <0>;
- qcom,rgmii_delay = <1>;
- qcom,phy_mii_type = <0>;
- qcom,emulation = <0>;
- qcom,irq = <255>;
- mdiobus = <&mdio0>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
- qcom,phy_mdio_addr = <0>; /* none */
- qcom,poll_required = <0>; /* no polling */
- qcom,rgmii_delay = <0>;
- qcom,phy_mii_type = <1>;
- qcom,emulation = <0>;
- qcom,irq = <258>;
- mdiobus = <&mdio0>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&sdcc1 {
- status = "okay";
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8065-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- rsvd@5fe00000 {
- reg = <0x5fe00000 0x200000>;
- reusable;
- };
-
- ramoops@42100000 {
- compatible = "ramoops";
- reg = <0x42100000 0x40000>;
- record-size = <0x4000>;
- console-size = <0x4000>;
- ftrace-size = <0x4000>;
- pmsg-size = <0x4000>;
- };
- };
-
- aliases {
- label-mac-device = &gmac2;
-
- led-boot = &power_white;
- led-failsafe = &power_amber;
- led-running = &power_white;
- led-upgrade = &power_amber;
-
- mdio-gpio0 = &mdio0;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds: leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- power_white: power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- power_amber: power_amber {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- wan_white {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan_amber {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- wifi {
- label = "white:wifi";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9",
- "gpio22", "gpio23", "gpio24",
- "gpio26", "gpio53", "gpio64";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- mdio0_pins: mdio0-pins {
- clk {
- pins = "gpio1";
- input-disable;
- };
- };
-
- rgmii2_pins: rgmii2-pins {
- tx {
- pins = "gpio27", "gpio28", "gpio29",
- "gpio30", "gpio31", "gpio32";
- input-disable;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- spi6_pins: spi6_pins {
- mux {
- pins = "gpio55", "gpio56", "gpio58";
- function = "gsbi6";
- bias-pull-down;
- };
-
- mosi {
- pins = "gpio55";
- drive-strength = <12>;
- };
-
- miso {
- pins = "gpio56";
- drive-strength = <14>;
- };
-
- cs {
- pins = "gpio57";
- drive-strength = <12>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio58";
- drive-strength = <12>;
- };
-
- reset {
- pins = "gpio33";
- drive-strength = <10>;
- bias-pull-down;
- output-high;
- };
- };
-
- usb0_pwr_en_pins: usb0_pwr_en_pins {
- mux {
- pins = "gpio15";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-
- usb1_pwr_en_pins: usb1_pwr_en_pins {
- mux {
- pins = "gpio16", "gpio68";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1180000>;
-
- partitions: partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "qcadata";
- reg = <0x0000000 0x0c80000>;
- read-only;
- };
-
- partition@c80000 {
- label = "APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- partition@1180000 {
- label = "APPSBLENV";
- reg = <0x1180000 0x0080000>;
- read-only;
- };
-
- art: partition@1200000 {
- label = "art";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: macaddr@6 {
- compatible = "mac-base";
- reg = <0x6 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- macaddr_art_c: macaddr@c {
- reg = <0xc 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@1340000 {
- label = "artbak";
- reg = <0x1340000 0x0140000>;
- read-only;
- };
-
- partition@1480000 {
- label = "kernel";
- reg = <0x1480000 0x0400000>;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
- qcom,phy_mdio_addr = <4>;
- qcom,poll_required = <0>;
- qcom,rgmii_delay = <1>;
- qcom,phy_mii_type = <0>;
- qcom,emulation = <0>;
- qcom,irq = <255>;
- mdiobus = <&mdio0>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_art_6 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
- qcom,phy_mdio_addr = <0>; /* none */
- qcom,poll_required = <0>; /* no polling */
- qcom,rgmii_delay = <0>;
- qcom,phy_mii_type = <1>;
- qcom,emulation = <0>;
- qcom,irq = <258>;
- mdiobus = <&mdio0>;
-
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&sata_phy {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb0_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb1_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi0: wifi@1,0 {
- compatible = "pci168c,0046";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi1: wifi@1,0 {
- compatible = "pci168c,0046";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
+++ /dev/null
-#include "qcom-ipq8065-nighthawk.dtsi"
-
-/ {
- model = "Netgear Nighthawk X4S R7800";
- compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064";
-};
-
-&leds {
- usb1 {
- label = "white:usb1";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb2";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- esata {
- label = "white:esata";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&partitions {
- partition@1880000 {
- label = "ubi";
- reg = <0x1880000 0x6080000>;
- };
-
- partition@7900000 {
- label = "reserve";
- reg = <0x7900000 0x0700000>;
- read-only;
- };
-};
-
-&wifi0 {
- nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
-
-&wifi1 {
- nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq8065-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Askey RT4230W REV6";
- compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x3e000000>;
- device_type = "memory";
- };
-
- aliases {
- led-boot = &ledctrl3;
- led-failsafe = &ledctrl1;
- led-running = &ledctrl2;
- led-upgrade = &ledctrl3;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs noinitrd";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- ledctrl1: ledctrl1 {
- label = "ledctrl1";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- ledctrl2: ledctrl2 {
- label = "ledctrl2";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- ledctrl3: ledctrl3 {
- label = "ledctrl3";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio54", "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio22", "gpio23", "gpio24";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- rgmii2_pins: rgmii2-pins {
- mux {
- pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
- "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
- function = "rgmii2";
- drive-strength = <8>;
- bias-disable;
- };
-
- tx {
- pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
- input-disable;
- };
- };
-
- spi_pins: spi_pins {
- cs {
- pins = "gpio20";
- drive-strength = <12>;
- };
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "everspin,mr25h256";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <40000000>;
- reg = <0>;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x10c0000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0000000 0x0040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x0040000 0x0140000>;
- read-only;
- };
-
- partition@180000 {
- label = "0:SBL2";
- reg = <0x0180000 0x0140000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "0:SBL3";
- reg = <0x02c0000 0x0280000>;
- read-only;
- };
-
- partition@540000 {
- label = "0:DDRCONFIG";
- reg = <0x0540000 0x0120000>;
- read-only;
- };
-
- partition@660000 {
- label = "0:SSD";
- reg = <0x0660000 0x0120000>;
- read-only;
- };
-
- partition@780000 {
- label = "0:TZ";
- reg = <0x0780000 0x0280000>;
- read-only;
- };
-
- partition@a00000 {
- label = "0:RPM";
- reg = <0x0a00000 0x0280000>;
- read-only;
- };
-
- partition@c80000 {
- label = "0:APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- partition@1180000 {
- label = "0:APPSBLENV";
- reg = <0x1180000 0x0080000>;
- };
-
- partition@1200000 {
- label = "0:ART";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_ART_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_ART_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@1340000 {
- label = "0:BOOTCONFIG";
- reg = <0x1340000 0x0060000>;
- read-only;
- };
-
- partition@13a0000 {
- label = "0:SBL2_1";
- reg = <0x13a0000 0x0140000>;
- read-only;
- };
-
- partition@14e0000 {
- label = "0:SBL3_1";
- reg = <0x14e0000 0x0280000>;
- read-only;
- };
-
- partition@1760000 {
- label = "0:DDRCONFIG_1";
- reg = <0x1760000 0x0120000>;
- read-only;
- };
-
- partition@1880000 {
- label = "0:SSD_1";
- reg = <0x1880000 0x0120000>;
- read-only;
- };
-
- partition@19a0000 {
- label = "0:TZ_1";
- reg = <0x19a0000 0x0280000>;
- read-only;
- };
-
- partition@1c20000 {
- label = "0:RPM_1";
- reg = <0x1c20000 0x0280000>;
- read-only;
- };
-
- partition@1ea0000 {
- label = "0:BOOTCONFIG1";
- reg = <0x1ea0000 0x0060000>;
- read-only;
- };
-
- partition@1f00000 {
- label = "0:APPSBL_1";
- reg = <0x1f00000 0x0500000>;
- read-only;
- };
-
- partition@2400000 {
- label = "ubi";
- reg = <0x2400000 0x1a000000>;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_WAN;
- default-state = "keep";
- };
- };
- };
-
- port@2 {
- reg = <2>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
- };
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
- };
- };
-
- port@4 {
- reg = <4>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
- };
- };
-
- port@5 {
- reg = <5>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
- };
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac0 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <0>;
-
- nvmem-cells = <&macaddr_ART_0>;
- nvmem-cell-names = "mac-address";
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <1>;
-
- nvmem-cells = <&macaddr_ART_6>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-names = "default";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi0: wifi@1,0 {
- compatible = "pci168c,0046";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&precal_ART_1000>;
- nvmem-cell-names = "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie1_pins>;
- pinctrl-names = "default";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi1: wifi@1,0 {
- compatible = "pci168c,0046";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&precal_ART_5000>;
- nvmem-cell-names = "pre-calibration";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq8065-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Arris TR4400 v2";
- compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- led-boot = &led_status_blue;
- led-failsafe = &led_status_red;
- led-running = &led_status_blue;
- led-upgrade = &led_status_red;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs noinitrd";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_status_red: status_red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_blue: status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- rgmii2_pins: rgmii2-pins {
- tx {
- pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
- input-disable;
- };
- };
-
- spi_pins: spi_pins {
- cs {
- pins = "gpio20";
- drive-strength = <12>;
- };
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "everspin,mr25h256";
- spi-max-frequency = <40000000>;
- reg = <0>;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0000000 0x0040000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x0040000 0x0140000>;
- read-only;
- };
- partition@180000 {
- label = "0:SBL2";
- reg = <0x0180000 0x0140000>;
- read-only;
- };
- partition@2c0000 {
- label = "0:SBL3";
- reg = <0x02c0000 0x0280000>;
- read-only;
- };
- partition@540000 {
- label = "0:DDRCONFIG";
- reg = <0x0540000 0x0120000>;
- read-only;
- };
- partition@660000 {
- label = "0:SSD";
- reg = <0x0660000 0x0120000>;
- read-only;
- };
- partition@780000 {
- label = "0:TZ";
- reg = <0x0780000 0x0280000>;
- read-only;
- };
- partition@a00000 {
- label = "0:RPM";
- reg = <0x0a00000 0x0280000>;
- read-only;
- };
- partition@c80000 {
- label = "0:APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
- partition@1180000 {
- label = "0:APPSBLENV";
- reg = <0x1180000 0x0080000>;
- };
- partition@1200000 {
- label = "0:ART";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- stock_partition@1340000 {
- label = "stock_rootfs";
- reg = <0x1340000 0x4000000>;
-
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "extra";
- reg = <0x0 0x4000000>;
- };
- };
- partition@5340000 {
- label = "0:BOOTCONFIG";
- reg = <0x5340000 0x0060000>;
- read-only;
- };
- partition@53a0000 {
- label = "0:SBL2_1";
- reg = <0x53a0000 0x0140000>;
- read-only;
- };
- partition@54e0000 {
- label = "0:SBL3_1";
- reg = <0x54e0000 0x0280000>;
- read-only;
- };
- partition@5760000 {
- label = "0:DDRCONFIG_1";
- reg = <0x5760000 0x0120000>;
- read-only;
- };
- partition@5880000 {
- label = "0:SSD_1";
- reg = <0x5880000 0x0120000>;
- read-only;
- };
- partition@59a0000 {
- label = "0:TZ_1";
- reg = <0x59a0000 0x0280000>;
- read-only;
- };
- partition@5c20000 {
- label = "0:RPM_1";
- reg = <0x5c20000 0x0280000>;
- read-only;
- };
- partition@5ea0000 {
- label = "0:BOOTCONFIG1";
- reg = <0x5ea0000 0x0060000>;
- read-only;
- };
- partition@5f00000 {
- label = "0:APPSBL_1";
- reg = <0x5f00000 0x0500000>;
- read-only;
- };
- stock_partition@6400000 {
- label = "stock_rootfs_1";
- reg = <0x6400000 0x4000000>;
-
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fw_env";
- reg = <0x0 0x100000>;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_fw_env_0: macaddr@0 {
- reg = <0x00 0x6>;
- };
- macaddr_fw_env_6: macaddr@6 {
- reg = <0x06 0x6>;
- };
- macaddr_fw_env_c: macaddr@c {
- reg = <0x0c 0x6>;
- };
- macaddr_fw_env_12: macaddr@12 {
- reg = <0x12 0x6>;
- };
- macaddr_fw_env_18: macaddr@18 {
- reg = <0x18 0x6>;
- };
- };
- };
-
- partition@100000 {
- label = "ubi";
- reg = <0x100000 0x9b00000>;
- };
- };
- stock_partition@a400000 {
- label = "stock_fw_env";
- reg = <0xa400000 0x0100000>;
- };
- stock_partition@a500000 {
- label = "stock_config";
- reg = <0xa500000 0x0800000>;
- };
- stock_partition@ad00000 {
- label = "stock_PKI";
- reg = <0xad00000 0x0200000>;
- };
- stock_partition@af00000 {
- label = "stock_scfgmgr";
- reg = <0xaf00000 0x0100000>;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
- };
- };
-
- phy7: ethernet-phy@7 {
- reg = <7>;
- };
-};
-
-&gmac0 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <0>;
-
- nvmem-cells = <&macaddr_fw_env_18>;
- nvmem-cell-names = "mac-address";
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <1>;
-
- nvmem-cells = <&macaddr_fw_env_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac3 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <3>;
- phy-handle = <&phy7>;
-
- nvmem-cells = <&macaddr_fw_env_6>;
- nvmem-cell-names = "mac-address";
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-names = "default";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi0: wifi@1,0 {
- compatible = "pci168c,0046";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie1_pins>;
- pinctrl-names = "default";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi1: wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8065-nighthawk.dtsi"
-
-/ {
- model = "Netgear Nighthawk XR450";
- compatible = "netgear,xr450", "qcom,ipq8065", "qcom,ipq8064";
-
-};
-
-&leds {
- usb1 {
- label = "white:usb1";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb2";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&partitions {
- partition@1880000 {
- label = "ubi";
- reg = <0x1880000 0xce00000>;
- };
-
- partition@e680000 {
- label = "reserve";
- reg = <0xe680000 0x0780000>;
- read-only;
- };
-};
-
-&wifi0 {
- nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
-
-&wifi1 {
- nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8065-nighthawk.dtsi"
-
-/ {
- model = "Netgear Nighthawk XR500";
- compatible = "netgear,xr500", "qcom,ipq8065", "qcom,ipq8064";
-
-};
-
-&leds {
- usb1 {
- label = "white:usb1";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb2";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&partitions {
- partition@1880000 {
- label = "ubi";
- reg = <0x1880000 0xce00000>;
- };
-
- partition@e680000 {
- label = "reserve";
- reg = <0xe680000 0x0780000>;
- read-only;
- };
-};
-
-&wifi0 {
- nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
-
-&wifi1 {
- nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Extreme Networks AP3935";
- compatible = "extreme,ap3935", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x41400000 0x3ec00000>;
- device_type = "memory";
- };
-
- aliases {
- serial0 = &gsbi7_serial;
- serial1 = &gsbi2_serial;
- mdio-gpio0 = &mdio0;
- ethernet0 = &gmac0;
- ethernet1 = &gmac2;
-
- led-boot = &led_power_green;
- led-failsafe = &led_power_orange;
- led-running = &led_power_green;
- led-upgrade = &led_power_green;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- bootargs-override = "ubi.block=0,0 root=/dev/ubiblock0_0";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
- };
-
- led_power_orange: power_orange {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
- };
-
- led_wlan2g_green {
- label = "green:wlan2g";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- led_wlan5g_green {
- label = "green:wlan5g";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- led_lan1_green {
- label = "green:lan1";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- led_lan1_orange {
- label = "orange:lan1";
- gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>;
- };
-
- led_lan2_green {
- label = "green:lan2";
- gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
- };
-
- led_lan2_orange {
- label = "orange:lan2";
- gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-
-&qcom_pinmux {
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19";
- function = "gsbi5";
- drive-strength = <10>;
- bias-pull-down;
- };
-
- clk {
- pins = "gpio21";
- function = "gsbi5";
- drive-strength = <12>;
- bias-pull-down;
- };
-
- cs {
- pins = "gpio20";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio22", "gpio23", "gpio24", "gpio25",
- "gpio26", "gpio27", "gpio28", "gpio29";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio56";
- function = "gpio";
- bias-pull-up;
- };
- };
-};
-
-&gsbi2 {
- qcom,mode = <GSBI_PROT_I2C_UART>;
- status = "okay";
-
- gsbi2_serial: serial@12490000 {
- status = "okay";
- };
-};
-
-&gsbi4 {
- qcom,mode = <GSBI_PROT_I2C_UART>;
- status = "okay";
-
- serial@16340000 {
- status = "disabled";
- };
-};
-
-&gsbi7 {
- qcom,mode = <GSBI_PROT_I2C_UART>;
- status = "okay";
-
- gsbi7_serial: serial@16640000 {
- status = "okay";
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi4: spi@1a280000 {
- status = "okay";
- spi-max-frequency = <50000000>;
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cfg1@2a0000 {
- compatible = "u-boot,env-redundant-bool";
- label = "CFG1";
- reg = <0x2a0000 0x0010000>;
-
- ethaddr: ethaddr {
- #nvmem-cell-cells = <1>;
- };
- };
-
- bootpri@2b0000 {
- label = "BootPRI";
- reg = <0x2b0000 0x0080000>;
- };
-
- cfg2@330000 {
- label = "CFG2";
- reg = <0x330000 0x0010000>;
- };
-
- fs@340000 {
- label = "FS";
- reg = <0x340000 0x0080000>;
- };
-
- priimg@3c0000 {
- label = "PriImg";
- reg = <0x3c0000 0x0e10000>;
- };
-
- secimg@11d0000 {
- label = "SecImg";
- reg = <0x11d0000 0x0e10000>;
- };
- };
- };
- };
-};
-
-&pcie0 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- nand@0 {
- compatible = "qcom,nandcs";
-
- reg = <0>;
-
- nand-ecc-strength = <8>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- ubi@0 {
- label = "ubi";
- reg = <0x0000000 0x20000000>;
- };
- };
- };
-};
-
-&soc {
- mdio1: mdio {
- compatible = "virtual,mdio-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- phy2: ethernet-phy@2 {
- reg = <2>;
- };
- };
-};
-
-&gmac0 {
- status = "okay";
-
- qcom,id = <0>;
- mdiobus = <&mdio1>;
-
- phy-mode = "rgmii";
- phy-handle = <&phy1>;
-
- nvmem-cells = <ðaddr 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- qcom,id = <2>;
- mdiobus = <&mdio1>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy2>;
-
- nvmem-cells = <ðaddr 1>;
- nvmem-cell-names = "mac-address";
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-/ {
- memory {
- device_type = "memory";
- linux,usable-memory = <0x41500000 0x1ea00000>;
- reg = <0x40000000 0x20000000>;
- };
-
- cpus {
- idle-states {
- CPU_SPC: spc {
- status = "disabled";
- };
- };
- };
-
- chosen {
- bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art";
- };
-};
-
-&qcom_pinmux {
- mdio0_pins_active: mdio0_pins_active {
- mux {
- pins = "gpio0", "gpio1";
- function = "mdio";
- drive-strength = <2>;
- bias-pull-down;
- output-low;
- };
-
- clk {
- pins = "gpio1";
- input-disable;
- };
- };
-
- phy_active: phy_active {
- phy {
- pins = "gpio6", "gpio7";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- output-high;
- };
- };
-
- uart1_pins: uart1_pins {
- mux {
- pins = "gpio51", "gpio52";
- function = "gsbi1";
- drive-strength = <4>;
- bias-disable;
- };
- };
-};
-
-&gsbi1 {
- status = "okay";
- qcom,mode = <GSBI_PROT_UART_W_FC>;
-
- serial@12450000 {
- status = "okay";
-
- pinctrl-0 = <&uart1_pins>;
- pinctrl-names = "default";
- };
-};
-
-&pcie0 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x0 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi0: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x10000 0 0 0 0>;
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x0 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi1: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x10000 0 0 0 0>;
- };
- };
-};
-
-&pcie2 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x0 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x10000 0 0 0 0>;
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- compatible = "qcom,nandcs";
-
- reg = <0>;
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x2140000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "sbl1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "mibib";
- reg = <0x40000 0x140000>;
- read-only;
- };
-
- partition@180000 {
- label = "sbl2";
- reg = <0x180000 0x140000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "sbl3";
- reg = <0x2c0000 0x280000>;
- read-only;
- };
-
- partition@540000 {
- label = "ddrconfig";
- reg = <0x540000 0x120000>;
- read-only;
- };
-
- partition@660000 {
- label = "ssd";
- reg = <0x660000 0x120000>;
- read-only;
- };
-
- partition@780000 {
- label = "tz";
- reg = <0x780000 0x280000>;
- read-only;
- };
-
- partition@a00000 {
- label = "rpm";
- reg = <0xa00000 0x280000>;
- read-only;
- };
-
- partition@1fc0000 {
- label = "u-boot";
- reg = <0x1fc0000 0x180000>;
- read-only;
- };
-
- partition@21c0000 {
- label = "bootkernel1";
- reg = <0x21c0000 0xa80000>;
- };
-
- partition@2c40000 {
- label = "bootkernel2";
- reg = <0x2c40000 0xa80000>;
- };
-
- partition@36c0000 {
- label = "ubi";
- reg = <0x36c0000 0x46c0000>;
- };
-
- partition@7d80000 {
- label = "art";
- reg = <0x7d80000 0x200000>;
- read-only;
- };
- };
- };
-};
+++ /dev/null
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Edgecore ECW5410";
- compatible = "edgecore,ecw5410", "qcom,ipq8064";
-
- reserved-memory {
- nss@40000000 {
- reg = <0x40000000 0x1000000>;
- no-map;
- };
-
- smem: smem@41000000 {
- reg = <0x41000000 0x200000>;
- no-map;
- };
-
- wifi_dump@44000000 {
- reg = <0x44000000 0x600000>;
- no-map;
- };
- };
-
- cpus {
- idle-states {
- CPU_SPC: spc {
- status = "disabled";
- };
- };
- };
-
- aliases {
- serial1 = &gsbi1_serial;
- ethernet0 = &gmac2;
- ethernet1 = &gmac3;
-
- led-boot = &led_power_green;
- led-failsafe = &led_power_red;
- led-running = &led_power_green;
- led-upgrade = &led_power_green;
- };
-
- chosen {
- bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_green {
- label = "green:wlan2g";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g_yellow {
- label = "yellow:wlan2g";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
- };
-
- wlan5g_green {
- label = "green:wlan5g";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- led_power_red: power_red {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
- };
-
- wlan5g_yellow {
- label = "yellow:wlan5g";
- gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-
-&qcom_pinmux {
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19";
- function = "gsbi5";
- drive-strength = <10>;
- bias-pull-down;
- };
-
- clk {
- pins = "gpio21";
- function = "gsbi5";
- drive-strength = <12>;
- bias-pull-down;
- };
-
- cs {
- pins = "gpio20";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio16", "gpio23", "gpio24", "gpio26",
- "gpio28", "gpio59";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio25";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- uart1_pins: uart1_pins {
- mux {
- pins = "gpio51", "gpio52", "gpio53", "gpio54";
- function = "gsbi1";
- drive-strength = <12>;
- bias-none;
- };
- };
-};
-
-&gsbi1 {
- qcom,mode = <GSBI_PROT_UART_W_FC>;
- status = "okay";
-
- serial@12450000 {
- status = "okay";
-
- pinctrl-0 = <&uart1_pins>;
- pinctrl-names = "default";
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi4: spi@1a280000 {
- status = "okay";
- spi-max-frequency = <50000000>;
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
- };
- };
-};
-
-&pcie2 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- compatible = "qcom,nandcs";
-
- reg = <0>;
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- rootfs1@0 {
- label = "rootfs1";
- reg = <0x0000000 0x4000000>;
- };
-
- rootfs2@4000000 {
- label = "rootfs2";
- reg = <0x4000000 0x4000000>;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- qcom,id = <2>;
- mdiobus = <&mdio0>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy1>;
-};
-
-&gmac3 {
- status = "okay";
-
- qcom,id = <3>;
- mdiobus = <&mdio0>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy0>;
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-
-#include "qcom-ipq8068-cryptid-common.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Meraki MR42";
- compatible = "meraki,mr42", "qcom,ipq8064";
-
- aliases {
- serial1 = &gsbi1_serial;
- ethernet0 = &gmac3;
-
- led-boot = &led_active;
- led-failsafe = &led_power;
- led-running = &led_active;
- led-upgrade = &led_active;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>;
- };
-
- led_active: active {
- label = "white:active";
- gpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&gmac3 {
- status = "okay";
-
- qcom,id = <3>;
- mdiobus = <&mdio0>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy2>;
-
- nvmem-cells = <&mac_address 0>;
- nvmem-cell-names = "mac-address";
-};
-
-&gsbi2 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C>;
-};
-
-&gsbi2_i2c {
- status = "okay";
-
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- ina2xx@40 {
- compatible = "ina219";
- shunt-resistor = <40000>;
- reg = <0x40>;
- };
-
- eeprom@56 {
- compatible = "atmel,24c64";
- pagesize = <32>;
- reg = <0x56>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- mac_address: mac-address@66 {
- compatible = "mac-base";
- reg = <0x66 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-};
-
-&gsbi6 {
- qcom,mode = <GSBI_PROT_I2C>;
- status = "okay";
-};
-
-&gsbi6_i2c {
- status = "okay";
-
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
-
- tlc591xx@40 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,tlc59108";
- reg = <0x40>;
-
- red@0 {
- label = "red:user";
- reg = <0x0>;
- };
-
- green@1 {
- label = "green:user";
- reg = <0x1>;
- };
-
- blue@2 {
- label = "blue:user";
- reg = <0x2>;
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins_active>, <&phy_active>;
- pinctrl-names = "default";
-
- phy2: ethernet-phy2 {
- reg = <2>;
-
- reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- reset-assert-us = <24000>;
-
- eee-broken-100tx;
- eee-broken-1000t;
- };
-};
-
-&qcom_pinmux {
- i2c0_pins: i2c0_pins {
- mux {
- pins = "gpio24", "gpio25";
- function = "gsbi2";
- drive-strength = <2>;
- bias-pull-up;
- input;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio26";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- i2c1_pins: i2c1_pins {
- mux {
- pins = "gpio29", "gpio30";
- function = "gsbi6";
- drive-strength = <2>;
- bias-pull-up;
- input;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio31", "gpio32";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-low;
- };
- };
-};
-
-&wifi0 {
- nvmem-cells = <&mac_address 1>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi1 {
- nvmem-cells = <&mac_address 2>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi2 {
- nvmem-cells = <&mac_address 3>;
- nvmem-cell-names = "mac-address";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-
-#include "qcom-ipq8068-cryptid-common.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Meraki MR52";
- compatible = "meraki,mr52", "qcom,ipq8064";
-
- aliases {
- serial1 = &gsbi1_serial;
- mdio-gpio0 = &mdio_gpio0;
- ethernet0 = &gmac2;
- ethernet1 = &gmac3;
-
- led-boot = &led_active;
- led-failsafe = &led_power;
- led-running = &led_active;
- led-upgrade = &led_active;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>;
- };
-
- lan2_green {
- label = "green:lan2";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- lan1_green {
- label = "green:lan1";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
-
- led_active: active {
- label = "white:active";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- lan2_orange {
- label = "orange:lan2";
- gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>;
- };
-
- lan1_orange {
- label = "orange:lan1";
- gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&gmac2 {
- status = "okay";
-
- qcom,id = <2>;
- mdiobus = <&mdio0>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy0>;
-
- nvmem-cells = <&mac_address 0>;
- nvmem-cell-names = "mac-address";
-};
-
-&gmac3 {
- status = "okay";
-
- qcom,id = <3>;
- mdiobus = <&mdio_gpio0>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy4>;
-
- nvmem-cells = <&mac_address 1>;
- nvmem-cell-names = "mac-address";
-};
-
-&gsbi7 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C>;
-};
-
-&gsbi7_i2c {
- status = "okay";
-
- pinctrl-0 = <&i2c_pins>;
- pinctrl-names = "default";
-
- ina2xx@45 {
- compatible = "ina219";
- shunt-resistor = <80000>;
- reg = <0x45>;
- };
-
- tlc591xx@49 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,tlc59108";
- reg = <0x49>;
-
- red@0 {
- label = "red:user";
- reg = <0x0>;
- };
-
- green@1 {
- label = "green:user";
- reg = <0x1>;
- };
-
- blue@2 {
- label = "blue:user";
- reg = <0x2>;
- };
- };
-
- eeprom@52 {
- compatible = "atmel,24c64";
- pagesize = <32>;
- reg = <0x52>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- mac_address: mac-address@66 {
- compatible = "mac-base";
- reg = <0x66 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-};
-
-&qcom_pinmux {
- i2c_pins: i2c_pins {
- mux {
- pins = "gpio8", "gpio9";
- function = "gsbi7";
- drive-strength = <2>;
- bias-pull-up;
- input;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio19", "gpio26";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-low;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio25";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- input;
- };
- };
-};
-
-&soc {
- mdio_gpio0: mdio {
- compatible = "virtual,mdio-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins_active>, <&phy_active>;
- pinctrl-names = "default";
-
- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH
- &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-
- phy0: ethernet-phy0 {
- reg = <0>;
- reset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>;
- reset-assert-us = <24000>;
- };
-
- phy4: ethernet-phy4 {
- reg = <4>;
- reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- reset-assert-us = <24000>;
- };
- };
-};
-
-&wifi0 {
- nvmem-cells = <&mac_address 4>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi1 {
- nvmem-cells = <&mac_address 3>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi2 {
- nvmem-cells = <&mac_address 2>;
- nvmem-cell-names = "mac-address";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
};
aliases {
- led-boot = &ledctrl3;
+ led-boot = &ledctrl1;
led-failsafe = &ledctrl1;
- led-running = &ledctrl2;
- led-upgrade = &ledctrl3;
+ led-running = &ledctrl3;
+ led-upgrade = &ledctrl1;
};
chosen {
ledctrl2: ledctrl2 {
label = "ledctrl2";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
};
ledctrl3: ledctrl3 {
&pcie0 {
status = "okay";
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
bridge@0,0 {
reg = <0x0 0 0 0 0>;
#address-cells = <3>;
&pcie1 {
status = "okay";
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
bridge@0,0 {
reg = <0x0 0 0 0 0>;
#address-cells = <3>;
&pcie2 {
status = "okay";
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
bridge@0,0 {
reg = <0x0 0 0 0 0>;
#address-cells = <3>;
gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>;
};
- lan2_green {
- label = "green:lan2";
+ lan1_green {
+ label = "green:lan1";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
- lan1_green {
- label = "green:lan1";
+ lan2_green {
+ label = "green:lan2";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
};
- lan2_orange {
- label = "orange:lan2";
+ lan1_orange {
+ label = "orange:lan1";
gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>;
};
- lan1_orange {
- label = "orange:lan1";
+ lan2_orange {
+ label = "orange:lan2";
gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>;
};
};
define Device/Default
PROFILES := Default
KERNEL_LOADADDR = 0x42208000
- DEVICE_DTS_DIR = $(if $(CONFIG_TESTING_KERNEL),$$(DTS_DIR)/qcom,$$(DTS_DIR))
+ DEVICE_DTS_DIR = $$(DTS_DIR)/qcom
DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
DEVICE_DTS_CONFIG := config@1
IMAGES := sysupgrade.bin
+++ /dev/null
-From 09be1a39e685d8c5edd471fd1cac9a8f8280d2de Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 8 Nov 2022 22:17:34 +0100
-Subject: [PATCH] clk: qcom: kpss-xcc: register it as clk provider
-
-krait-cc use this driver for the secondary mux. Register it as a clk
-provider to correctly use this clk in other drivers.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221108211734.3707-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/kpss-xcc.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/kpss-xcc.c
-+++ b/drivers/clk/qcom/kpss-xcc.c
-@@ -31,12 +31,13 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t
-
- static int kpss_xcc_driver_probe(struct platform_device *pdev)
- {
-+ struct device *dev = &pdev->dev;
- const struct of_device_id *id;
- void __iomem *base;
- struct clk_hw *hw;
- const char *name;
-
-- id = of_match_device(kpss_xcc_match_table, &pdev->dev);
-+ id = of_match_device(kpss_xcc_match_table, dev);
- if (!id)
- return -ENODEV;
-
-@@ -45,7 +46,7 @@ static int kpss_xcc_driver_probe(struct
- return PTR_ERR(base);
-
- if (id->data) {
-- if (of_property_read_string_index(pdev->dev.of_node,
-+ if (of_property_read_string_index(dev->of_node,
- "clock-output-names",
- 0, &name))
- return -ENODEV;
-@@ -55,12 +56,16 @@ static int kpss_xcc_driver_probe(struct
- base += 0x28;
- }
-
-- hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents,
-+ hw = devm_clk_hw_register_mux_parent_data_table(dev, name, aux_parents,
- ARRAY_SIZE(aux_parents), 0,
- base, 0, 0x3,
- 0, aux_parent_map, NULL);
-+ if (IS_ERR(hw))
-+ return PTR_ERR(hw);
-
-- return PTR_ERR_OR_ZERO(hw);
-+ of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, hw);
-+
-+ return 0;
- }
-
- static struct platform_driver kpss_xcc_driver = {
+++ /dev/null
-From 3198106a99e73dbc4c02bd5128cec0997c73af82 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 8 Nov 2022 22:58:27 +0100
-Subject: [PATCH 1/6] clk: qcom: krait-cc: use devm variant for clk notifier
- register
-
-Use devm variant for clk notifier register and correctly handle free
-resource on driver remove.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221108215827.30475-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -62,7 +62,7 @@ static int krait_notifier_register(struc
- int ret = 0;
-
- mux->clk_nb.notifier_call = krait_notifier_cb;
-- ret = clk_notifier_register(clk, &mux->clk_nb);
-+ ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb);
- if (ret)
- dev_err(dev, "failed to register clock notifier: %d\n", ret);
-
+++ /dev/null
-From 8e456411abcbf899c04740b9dbb3dcefcd61c946 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:27 +0100
-Subject: [PATCH 2/6] clk: qcom: krait-cc: fix wrong parent order for secondary
- mux
-
-The secondary mux parent order is swapped.
-This currently doesn't cause problems as the secondary mux is used for idle
-clk and as a safe clk source while reprogramming the hfpll.
-
-Each mux have 2 or more output but he always have a safe source to
-switch while reprogramming the connected pll. We use a clk notifier to
-switch to the correct parent before clk core can apply the correct rate.
-The parent to switch is hardcoded in the mux struct.
-
-For the secondary mux the safe source to use is the qsb parent as it's
-the only fixed clk as the acpus_aux is a pll that can source from pxo or
-from pll8.
-
-The hardcoded safe parent for the secondary mux is set to index 0 that
-in the secondary mux map is set to 2.
-
-But the index 0 is actually acpu_aux in the parent list.
-
-Fix the swapped parents to correctly handle idle frequency and output a
-sane clk_summary report.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -116,8 +116,8 @@ krait_add_sec_mux(struct device *dev, in
- int ret;
- struct krait_mux_clk *mux;
- static const char *sec_mux_list[] = {
-- "acpu_aux",
- "qsb",
-+ "acpu_aux",
- };
- struct clk_init_data init = {
- .parent_names = sec_mux_list,
+++ /dev/null
-From 18ae57b1e8abee6c453381470f6e18991d2901a8 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:28 +0100
-Subject: [PATCH 3/6] clk: qcom: krait-cc: also enable secondary mux and div
- clk
-
-clk-krait ignore any rate change if clk is not flagged as enabled.
-Correctly enable the secondary mux and div clk to correctly change rate
-instead of silently ignoring the request.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-2-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 21 ++++++++++++++++++++-
- 1 file changed, 20 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -80,6 +80,7 @@ krait_add_div(struct device *dev, int id
- };
- const char *p_names[1];
- struct clk *clk;
-+ int cpu;
-
- div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
- if (!div)
-@@ -103,6 +104,17 @@ krait_add_div(struct device *dev, int id
- }
-
- clk = devm_clk_register(dev, &div->hw);
-+ if (IS_ERR(clk))
-+ goto err;
-+
-+ /* clk-krait ignore any rate change if mux is not flagged as enabled */
-+ if (id < 0)
-+ for_each_online_cpu(cpu)
-+ clk_prepare_enable(div->hw.clk);
-+ else
-+ clk_prepare_enable(div->hw.clk);
-+
-+err:
- kfree(p_names[0]);
- kfree(init.name);
-
-@@ -113,7 +125,7 @@ static int
- krait_add_sec_mux(struct device *dev, int id, const char *s,
- unsigned int offset, bool unique_aux)
- {
-- int ret;
-+ int cpu, ret;
- struct krait_mux_clk *mux;
- static const char *sec_mux_list[] = {
- "qsb",
-@@ -165,6 +177,13 @@ krait_add_sec_mux(struct device *dev, in
- if (ret)
- goto unique_aux;
-
-+ /* clk-krait ignore any rate change if mux is not flagged as enabled */
-+ if (id < 0)
-+ for_each_online_cpu(cpu)
-+ clk_prepare_enable(mux->hw.clk);
-+ else
-+ clk_prepare_enable(mux->hw.clk);
-+
- unique_aux:
- if (unique_aux)
- kfree(sec_mux_list[0]);
+++ /dev/null
-From e5dc1a4c01510da8438dddfdf4200b79d73990dc Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:29 +0100
-Subject: [PATCH 4/6] clk: qcom: krait-cc: handle secondary mux sourcing out of
- acpu_aux
-
-Some bootloader may leave the system in an even more undefined state
-with the secondary mux of L2 or other cores sourcing out of the acpu_aux
-parent. This results in the clk set to the PXO rate or a PLL8 rate.
-
-The current logic to reset the mux and set them to a defined state only
-handle if the mux are configured to source out of QSB. Change this and
-force a new and defined state if the current clk is lower than the aux
-rate. This way we can handle any wrong configuration where the mux is
-sourcing out of QSB (rate 225MHz, currently set to a virtual rate of 1),
-PXO rate (rate 25MHz) or PLL8 (needs to be configured to run at 384Mhz).
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-3-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -383,8 +383,8 @@ static int krait_cc_probe(struct platfor
- */
- cur_rate = clk_get_rate(l2_pri_mux_clk);
- aux_rate = 384000000;
-- if (cur_rate == 1) {
-- pr_info("L2 @ QSB rate. Forcing new rate.\n");
-+ if (cur_rate < aux_rate) {
-+ pr_info("L2 @ Undefined rate. Forcing new rate.\n");
- cur_rate = aux_rate;
- }
- clk_set_rate(l2_pri_mux_clk, aux_rate);
-@@ -394,8 +394,8 @@ static int krait_cc_probe(struct platfor
- for_each_possible_cpu(cpu) {
- clk = clks[cpu];
- cur_rate = clk_get_rate(clk);
-- if (cur_rate == 1) {
-- pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
-+ if (cur_rate < aux_rate) {
-+ pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
- cur_rate = aux_rate;
- }
-
+++ /dev/null
-From 8ea9fb841a7e528bc8ae79d726ce951dcf7b46e2 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:30 +0100
-Subject: [PATCH 5/6] clk: qcom: krait-cc: convert to devm_clk_hw_register
-
-clk_register is now deprecated. Convert the driver to devm_clk_hw_register.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-4-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 31 +++++++++++++++++++------------
- 1 file changed, 19 insertions(+), 12 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -79,8 +79,7 @@ krait_add_div(struct device *dev, int id
- .flags = CLK_SET_RATE_PARENT,
- };
- const char *p_names[1];
-- struct clk *clk;
-- int cpu;
-+ int cpu, ret;
-
- div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
- if (!div)
-@@ -103,8 +102,8 @@ krait_add_div(struct device *dev, int id
- return -ENOMEM;
- }
-
-- clk = devm_clk_register(dev, &div->hw);
-- if (IS_ERR(clk))
-+ ret = devm_clk_hw_register(dev, &div->hw);
-+ if (ret)
- goto err;
-
- /* clk-krait ignore any rate change if mux is not flagged as enabled */
-@@ -118,7 +117,7 @@ err:
- kfree(p_names[0]);
- kfree(init.name);
-
-- return PTR_ERR_OR_ZERO(clk);
-+ return ret;
- }
-
- static int
-@@ -137,7 +136,6 @@ krait_add_sec_mux(struct device *dev, in
- .ops = &krait_mux_clk_ops,
- .flags = CLK_SET_RATE_PARENT,
- };
-- struct clk *clk;
-
- mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
- if (!mux)
-@@ -166,14 +164,16 @@ krait_add_sec_mux(struct device *dev, in
- if (unique_aux) {
- sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
- if (!sec_mux_list[0]) {
-- clk = ERR_PTR(-ENOMEM);
-+ ret = -ENOMEM;
- goto err_aux;
- }
- }
-
-- clk = devm_clk_register(dev, &mux->hw);
-+ ret = devm_clk_hw_register(dev, &mux->hw);
-+ if (ret)
-+ goto unique_aux;
-
-- ret = krait_notifier_register(dev, clk, mux);
-+ ret = krait_notifier_register(dev, mux->hw.clk, mux);
- if (ret)
- goto unique_aux;
-
-@@ -189,7 +189,7 @@ unique_aux:
- kfree(sec_mux_list[0]);
- err_aux:
- kfree(init.name);
-- return PTR_ERR_OR_ZERO(clk);
-+ return ret;
- }
-
- static struct clk *
-@@ -241,11 +241,18 @@ krait_add_pri_mux(struct device *dev, in
- goto err_p2;
- }
-
-- clk = devm_clk_register(dev, &mux->hw);
-+ ret = devm_clk_hw_register(dev, &mux->hw);
-+ if (ret) {
-+ clk = ERR_PTR(ret);
-+ goto err_p3;
-+ }
-+
-+ clk = mux->hw.clk;
-
- ret = krait_notifier_register(dev, clk, mux);
- if (ret)
-- goto err_p3;
-+ clk = ERR_PTR(ret);
-+
- err_p3:
- kfree(p_names[2]);
- err_p2:
+++ /dev/null
-From 56a655e1c41a86445cf2de656649ad93424b2a63 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:31 +0100
-Subject: [PATCH 6/6] clk: qcom: krait-cc: convert to parent_data API
-
-Modernize the krait-cc driver to parent-data API and refactor to drop
-any use of parent_names. From Documentation all the required clocks should
-be declared in DTS so fw_name can be correctly used to get the parents
-for all the muxes. .name is also declared to save compatibility with old
-DT.
-
-While at it also drop some hardcoded index and introduce an enum to make
-index values more clear.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-5-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 202 ++++++++++++++++++++----------------
- 1 file changed, 112 insertions(+), 90 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -15,6 +15,16 @@
-
- #include "clk-krait.h"
-
-+enum {
-+ cpu0_mux = 0,
-+ cpu1_mux,
-+ cpu2_mux,
-+ cpu3_mux,
-+ l2_mux,
-+
-+ clks_max,
-+};
-+
- static unsigned int sec_mux_map[] = {
- 2,
- 0,
-@@ -69,21 +79,23 @@ static int krait_notifier_register(struc
- return ret;
- }
-
--static int
-+static struct clk_hw *
- krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
- {
- struct krait_div2_clk *div;
-+ static struct clk_parent_data p_data[1];
- struct clk_init_data init = {
-- .num_parents = 1,
-+ .num_parents = ARRAY_SIZE(p_data),
- .ops = &krait_div2_clk_ops,
- .flags = CLK_SET_RATE_PARENT,
- };
-- const char *p_names[1];
-+ struct clk_hw *clk;
-+ char *parent_name;
- int cpu, ret;
-
- div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
- if (!div)
-- return -ENOMEM;
-+ return ERR_PTR(-ENOMEM);
-
- div->width = 2;
- div->shift = 6;
-@@ -93,18 +105,25 @@ krait_add_div(struct device *dev, int id
-
- init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
- if (!init.name)
-- return -ENOMEM;
-+ return ERR_PTR(-ENOMEM);
-
-- init.parent_names = p_names;
-- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
-- if (!p_names[0]) {
-- kfree(init.name);
-- return -ENOMEM;
-+ init.parent_data = p_data;
-+ parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
-+ if (!parent_name) {
-+ clk = ERR_PTR(-ENOMEM);
-+ goto err_parent_name;
- }
-
-+ p_data[0].fw_name = parent_name;
-+ p_data[0].name = parent_name;
-+
- ret = devm_clk_hw_register(dev, &div->hw);
-- if (ret)
-- goto err;
-+ if (ret) {
-+ clk = ERR_PTR(ret);
-+ goto err_clk;
-+ }
-+
-+ clk = &div->hw;
-
- /* clk-krait ignore any rate change if mux is not flagged as enabled */
- if (id < 0)
-@@ -113,33 +132,36 @@ krait_add_div(struct device *dev, int id
- else
- clk_prepare_enable(div->hw.clk);
-
--err:
-- kfree(p_names[0]);
-+err_clk:
-+ kfree(parent_name);
-+err_parent_name:
- kfree(init.name);
-
-- return ret;
-+ return clk;
- }
-
--static int
-+static struct clk_hw *
- krait_add_sec_mux(struct device *dev, int id, const char *s,
- unsigned int offset, bool unique_aux)
- {
- int cpu, ret;
- struct krait_mux_clk *mux;
-- static const char *sec_mux_list[] = {
-- "qsb",
-- "acpu_aux",
-+ static struct clk_parent_data sec_mux_list[2] = {
-+ { .name = "qsb", .fw_name = "qsb" },
-+ {},
- };
- struct clk_init_data init = {
-- .parent_names = sec_mux_list,
-+ .parent_data = sec_mux_list,
- .num_parents = ARRAY_SIZE(sec_mux_list),
- .ops = &krait_mux_clk_ops,
- .flags = CLK_SET_RATE_PARENT,
- };
-+ struct clk_hw *clk;
-+ char *parent_name;
-
- mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
- if (!mux)
-- return -ENOMEM;
-+ return ERR_PTR(-ENOMEM);
-
- mux->offset = offset;
- mux->lpl = id >= 0;
-@@ -159,23 +181,33 @@ krait_add_sec_mux(struct device *dev, in
-
- init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
- if (!init.name)
-- return -ENOMEM;
-+ return ERR_PTR(-ENOMEM);
-
- if (unique_aux) {
-- sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
-- if (!sec_mux_list[0]) {
-- ret = -ENOMEM;
-+ parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
-+ if (!parent_name) {
-+ clk = ERR_PTR(-ENOMEM);
- goto err_aux;
- }
-+ sec_mux_list[1].fw_name = parent_name;
-+ sec_mux_list[1].name = parent_name;
-+ } else {
-+ sec_mux_list[1].name = "apu_aux";
- }
-
- ret = devm_clk_hw_register(dev, &mux->hw);
-- if (ret)
-- goto unique_aux;
-+ if (ret) {
-+ clk = ERR_PTR(ret);
-+ goto err_clk;
-+ }
-+
-+ clk = &mux->hw;
-
- ret = krait_notifier_register(dev, mux->hw.clk, mux);
-- if (ret)
-- goto unique_aux;
-+ if (ret) {
-+ clk = ERR_PTR(ret);
-+ goto err_clk;
-+ }
-
- /* clk-krait ignore any rate change if mux is not flagged as enabled */
- if (id < 0)
-@@ -184,28 +216,29 @@ krait_add_sec_mux(struct device *dev, in
- else
- clk_prepare_enable(mux->hw.clk);
-
--unique_aux:
-+err_clk:
- if (unique_aux)
-- kfree(sec_mux_list[0]);
-+ kfree(parent_name);
- err_aux:
- kfree(init.name);
-- return ret;
-+ return clk;
- }
-
--static struct clk *
--krait_add_pri_mux(struct device *dev, int id, const char *s,
-- unsigned int offset)
-+static struct clk_hw *
-+krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *sec_mux,
-+ int id, const char *s, unsigned int offset)
- {
- int ret;
- struct krait_mux_clk *mux;
-- const char *p_names[3];
-+ static struct clk_parent_data p_data[3];
- struct clk_init_data init = {
-- .parent_names = p_names,
-- .num_parents = ARRAY_SIZE(p_names),
-+ .parent_data = p_data,
-+ .num_parents = ARRAY_SIZE(p_data),
- .ops = &krait_mux_clk_ops,
- .flags = CLK_SET_RATE_PARENT,
- };
-- struct clk *clk;
-+ struct clk_hw *clk;
-+ char *hfpll_name;
-
- mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
- if (!mux)
-@@ -223,55 +256,44 @@ krait_add_pri_mux(struct device *dev, in
- if (!init.name)
- return ERR_PTR(-ENOMEM);
-
-- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
-- if (!p_names[0]) {
-+ hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
-+ if (!hfpll_name) {
- clk = ERR_PTR(-ENOMEM);
-- goto err_p0;
-+ goto err_hfpll;
- }
-
-- p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
-- if (!p_names[1]) {
-- clk = ERR_PTR(-ENOMEM);
-- goto err_p1;
-- }
-+ p_data[0].fw_name = hfpll_name;
-+ p_data[0].name = hfpll_name;
-
-- p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
-- if (!p_names[2]) {
-- clk = ERR_PTR(-ENOMEM);
-- goto err_p2;
-- }
-+ p_data[1].hw = hfpll_div;
-+ p_data[2].hw = sec_mux;
-
- ret = devm_clk_hw_register(dev, &mux->hw);
- if (ret) {
- clk = ERR_PTR(ret);
-- goto err_p3;
-+ goto err_clk;
- }
-
-- clk = mux->hw.clk;
-+ clk = &mux->hw;
-
-- ret = krait_notifier_register(dev, clk, mux);
-+ ret = krait_notifier_register(dev, mux->hw.clk, mux);
- if (ret)
- clk = ERR_PTR(ret);
-
--err_p3:
-- kfree(p_names[2]);
--err_p2:
-- kfree(p_names[1]);
--err_p1:
-- kfree(p_names[0]);
--err_p0:
-+err_clk:
-+ kfree(hfpll_name);
-+err_hfpll:
- kfree(init.name);
- return clk;
- }
-
- /* id < 0 for L2, otherwise id == physical CPU number */
--static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
-+static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux)
- {
-- int ret;
-+ struct clk_hw *hfpll_div, *sec_mux, *pri_mux;
- unsigned int offset;
- void *p = NULL;
- const char *s;
-- struct clk *clk;
-
- if (id >= 0) {
- offset = 0x4501 + (0x1000 * id);
-@@ -283,22 +305,23 @@ static struct clk *krait_add_clks(struct
- s = "_l2";
- }
-
-- ret = krait_add_div(dev, id, s, offset);
-- if (ret) {
-- clk = ERR_PTR(ret);
-+ hfpll_div = krait_add_div(dev, id, s, offset);
-+ if (IS_ERR(hfpll_div)) {
-+ pri_mux = hfpll_div;
- goto err;
- }
-
-- ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
-- if (ret) {
-- clk = ERR_PTR(ret);
-+ sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux);
-+ if (IS_ERR(sec_mux)) {
-+ pri_mux = sec_mux;
- goto err;
- }
-
-- clk = krait_add_pri_mux(dev, id, s, offset);
-+ pri_mux = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset);
-+
- err:
- kfree(p);
-- return clk;
-+ return pri_mux;
- }
-
- static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
-@@ -306,7 +329,7 @@ static struct clk *krait_of_get(struct o
- unsigned int idx = clkspec->args[0];
- struct clk **clks = data;
-
-- if (idx >= 5) {
-+ if (idx >= clks_max) {
- pr_err("%s: invalid clock index %d\n", __func__, idx);
- return ERR_PTR(-EINVAL);
- }
-@@ -327,9 +350,8 @@ static int krait_cc_probe(struct platfor
- const struct of_device_id *id;
- unsigned long cur_rate, aux_rate;
- int cpu;
-- struct clk *clk;
-- struct clk **clks;
-- struct clk *l2_pri_mux_clk;
-+ struct clk_hw *mux, *l2_pri_mux;
-+ struct clk *clk, **clks;
-
- id = of_match_device(krait_cc_match_table, dev);
- if (!id)
-@@ -348,21 +370,21 @@ static int krait_cc_probe(struct platfor
- }
-
- /* Krait configurations have at most 4 CPUs and one L2 */
-- clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
-+ clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL);
- if (!clks)
- return -ENOMEM;
-
- for_each_possible_cpu(cpu) {
-- clk = krait_add_clks(dev, cpu, id->data);
-+ mux = krait_add_clks(dev, cpu, id->data);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-- clks[cpu] = clk;
-+ clks[cpu] = mux->clk;
- }
-
-- l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
-- if (IS_ERR(l2_pri_mux_clk))
-- return PTR_ERR(l2_pri_mux_clk);
-- clks[4] = l2_pri_mux_clk;
-+ l2_pri_mux = krait_add_clks(dev, -1, id->data);
-+ if (IS_ERR(l2_pri_mux))
-+ return PTR_ERR(l2_pri_mux);
-+ clks[l2_mux] = l2_pri_mux->clk;
-
- /*
- * We don't want the CPU or L2 clocks to be turned off at late init
-@@ -372,7 +394,7 @@ static int krait_cc_probe(struct platfor
- * they take over.
- */
- for_each_online_cpu(cpu) {
-- clk_prepare_enable(l2_pri_mux_clk);
-+ clk_prepare_enable(clks[l2_mux]);
- WARN(clk_prepare_enable(clks[cpu]),
- "Unable to turn on CPU%d clock", cpu);
- }
-@@ -388,16 +410,16 @@ static int krait_cc_probe(struct platfor
- * two different rates to force a HFPLL reinit under all
- * circumstances.
- */
-- cur_rate = clk_get_rate(l2_pri_mux_clk);
-+ cur_rate = clk_get_rate(clks[l2_mux]);
- aux_rate = 384000000;
- if (cur_rate < aux_rate) {
- pr_info("L2 @ Undefined rate. Forcing new rate.\n");
- cur_rate = aux_rate;
- }
-- clk_set_rate(l2_pri_mux_clk, aux_rate);
-- clk_set_rate(l2_pri_mux_clk, 2);
-- clk_set_rate(l2_pri_mux_clk, cur_rate);
-- pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
-+ clk_set_rate(clks[l2_mux], aux_rate);
-+ clk_set_rate(clks[l2_mux], 2);
-+ clk_set_rate(clks[l2_mux], cur_rate);
-+ pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
- for_each_possible_cpu(cpu) {
- clk = clks[cpu];
- cur_rate = clk_get_rate(clk);
+++ /dev/null
-From c9713e4ede1e5d044b64fe4d3cbb84223625637f Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 25 Oct 2022 01:38:17 +0200
-Subject: [PATCH] ARM: dts: qcom: ipq8064: disable mmc-ddr-1_8v for sdcc1
-
-It was reported non working mmc with this option enabled.
-Both mmc for ipq8064 are supplied by a fixed 3.3v regulator so mmc can't
-be run at 1.8v.
-Disable it to restore correct functionality of this SoC feature.
-
-Tested-by: Hendrik Koerner <koerhen@web.de>
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221024233817.27410-1-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -756,7 +756,6 @@
- non-removable;
- cap-sd-highspeed;
- cap-mmc-highspeed;
-- mmc-ddr-1_8v;
- vmmc-supply = <&vsdcc_fixed>;
- dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
- dma-names = "tx", "rx";
+++ /dev/null
-From de48d8766afcd97d147699aaff78a338081c9973 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:55 +0200
-Subject: [PATCH 1/3] thermal/drivers/qcom/tsens: Init debugfs only with
- successful probe
-
-Calibrate and tsens_register can fail or PROBE_DEFER. This will cause a
-double or a wrong init of the debugfs information. Init debugfs only
-with successful probe fixing warning about directory already present.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
-Link: https://lore.kernel.org/r/20221022125657.22530-2-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -918,8 +918,6 @@ int __init init_common(struct tsens_priv
- if (tsens_version(priv) >= VER_0_1)
- tsens_enable_irq(priv);
-
-- tsens_debug_init(op);
--
- err_put_device:
- put_device(&op->dev);
- return ret;
-@@ -1156,7 +1154,11 @@ static int tsens_probe(struct platform_d
- }
- }
-
-- return tsens_register(priv);
-+ ret = tsens_register(priv);
-+ if (!ret)
-+ tsens_debug_init(pdev);
-+
-+ return ret;
- }
-
- static int tsens_remove(struct platform_device *pdev)
+++ /dev/null
-From c7e077e921fa94e0c06c8d14af6c0504c8a5f4bd Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:56 +0200
-Subject: [PATCH 2/3] thermal/drivers/qcom/tsens: Fix wrong version id
- dbg_version_show
-
-For VER_0 the version was incorrectly reported as 0.1.0.
-
-Fix that and correctly report the major version for this old tsens
-revision.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20221022125657.22530-3-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -692,7 +692,7 @@ static int dbg_version_show(struct seq_f
- return ret;
- seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver);
- } else {
-- seq_puts(s, "0.1.0\n");
-+ seq_printf(s, "0.%d.0\n", priv->feat->ver_major);
- }
-
- return 0;
+++ /dev/null
-From 89992d95ed1046338c7866ef7bbe6de543a2af91 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:57 +0200
-Subject: [PATCH 3/3] thermal/drivers/qcom/tsens: Rework debugfs file structure
-
-The current tsens debugfs structure is composed by:
-- a tsens dir in debugfs with a version file
-- a directory for each tsens istance with sensors file to dump all the
- sensors value.
-
-This works on the assumption that we have the same version for each
-istance but this assumption seems fragile and with more than one tsens
-istance results in the version file not tracking each of them.
-
-A better approach is to just create a subdirectory for each tsens
-istance and put there version and sensors debugfs file.
-
-Using this new implementation results in less code since debugfs entry
-are created only on successful tsens probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20221022125657.22530-4-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 13 +++----------
- 1 file changed, 3 insertions(+), 10 deletions(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -704,21 +704,14 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors);
- static void tsens_debug_init(struct platform_device *pdev)
- {
- struct tsens_priv *priv = platform_get_drvdata(pdev);
-- struct dentry *root, *file;
-
-- root = debugfs_lookup("tsens", NULL);
-- if (!root)
-+ priv->debug_root = debugfs_lookup("tsens", NULL);
-+ if (!priv->debug_root)
- priv->debug_root = debugfs_create_dir("tsens", NULL);
-- else
-- priv->debug_root = root;
--
-- file = debugfs_lookup("version", priv->debug_root);
-- if (!file)
-- debugfs_create_file("version", 0444, priv->debug_root,
-- pdev, &dbg_version_fops);
-
- /* A directory for each instance of the TSENS IP */
- priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);
-+ debugfs_create_file("version", 0444, priv->debug, pdev, &dbg_version_fops);
- debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops);
- }
- #else
+++ /dev/null
-From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Thu, 9 Mar 2017 09:31:44 +0100
-Subject: [PATCH 61/69] mtd: "rootfs" conflicts with OpenWrt auto mounting
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- drivers/mtd/mtdpart.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/mtd/mtdpart.c
-+++ b/drivers/mtd/mtdpart.c
-@@ -51,7 +51,11 @@ static struct mtd_info *allocate_partiti
-
- /* allocate the partition structure */
- child = kzalloc(sizeof(*child), GFP_KERNEL);
-- name = kstrdup(part->name, GFP_KERNEL);
-+ /* "rootfs" conflicts with OpenWrt auto mounting */
-+ if (mtd_type_is_nand(parent) && !strcmp(part->name, "rootfs"))
-+ name = "ubi";
-+ else
-+ name = kstrdup(part->name, GFP_KERNEL);
- if (!name || !child) {
- printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n",
- parent->name);
+++ /dev/null
-From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Mon, 17 Jan 2022 23:39:34 +0100
-Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for
- ipq8064
-
-Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
-Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
-for the secondary mux.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
- 1 file changed, 32 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -301,6 +301,12 @@
- };
-
- clocks {
-+ qsb: qsb {
-+ compatible = "fixed-clock";
-+ clock-frequency = <225000000>;
-+ #clock-cells = <0>;
-+ };
-+
- cxo_board: cxo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
-@@ -575,15 +581,30 @@
- clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
- clock-names = "pll8_vote", "pxo";
- clock-output-names = "acpu_l2_aux";
-+ #clock-cells = <0>;
-+ };
-+
-+ kraitcc: clock-controller {
-+ compatible = "qcom,krait-cc-v1";
-+ clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
-+ <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
-+ clock-names = "hfpll0", "hfpll1", "hfpll_l2",
-+ "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
-+ "qsb", "pxo";
-+ #clock-cells = <1>;
- };
-
- acc0: clock-controller@2088000 {
- compatible = "qcom,kpss-acc-v1";
- reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
-+ clock-output-names = "acpu0_aux";
-+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
-+ clock-names = "pll8_vote", "pxo";
-+ #clock-cells = <0>;
- };
-
- saw0: regulator@2089000 {
-- compatible = "qcom,saw2";
-+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
- reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
- };
-@@ -591,14 +612,24 @@
- acc1: clock-controller@2098000 {
- compatible = "qcom,kpss-acc-v1";
- reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
-+ clock-output-names = "acpu1_aux";
-+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
-+ clock-names = "pll8_vote", "pxo";
-+ #clock-cells = <0>;
- };
-
- saw1: regulator@2099000 {
-- compatible = "qcom,saw2";
-+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
- reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
- };
-
-+ saw_l2: regulator@02012000 {
-+ compatible = "qcom,saw2", "syscon";
-+ reg = <0x02012000 0x1000>;
-+ regulator;
-+ };
-+
- nss_common: syscon@03000000 {
- compatible = "syscon";
- reg = <0x03000000 0x0000FFFF>;
+++ /dev/null
-From 076ebb6e1799c4c7a1d2e07510d88b9e9b57b551 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 18 Jan 2022 00:03:47 +0100
-Subject: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for
- ipq8064
-
-Add opp table for cpu and l2 cache. While the current cpufreq is
-the generic one that doesn't scale the L2 cache, we add the l2
-cache opp anyway for the sake of completeness. This will be handy in the
-future when a dedicated cpufreq driver is introduced for krait cores
-that will correctly scale l2 cache with the core freq.
-
-Opp-level is set based on the logic of
-0: idle level
-1: normal level
-2: turbo level
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
- 1 file changed, 99 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -48,6 +48,105 @@
- };
- };
-
-+ opp_table_l2: opp_table_l2 {
-+ compatible = "operating-points-v2";
-+
-+ opp-384000000 {
-+ opp-hz = /bits/ 64 <384000000>;
-+ opp-microvolt = <1100000>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <0>;
-+ };
-+
-+ opp-1000000000 {
-+ opp-hz = /bits/ 64 <1000000000>;
-+ opp-microvolt = <1100000>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <1>;
-+ };
-+
-+ opp-1200000000 {
-+ opp-hz = /bits/ 64 <1200000000>;
-+ opp-microvolt = <1150000>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <2>;
-+ };
-+ };
-+
-+ opp_table0: opp_table0 {
-+ compatible = "operating-points-v2-kryo-cpu";
-+ nvmem-cells = <&speedbin_efuse>;
-+
-+ /*
-+ * Voltage thresholds are <target min max>
-+ */
-+ opp-384000000 {
-+ opp-hz = /bits/ 64 <384000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
-+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
-+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <0>;
-+ };
-+
-+ opp-600000000 {
-+ opp-hz = /bits/ 64 <600000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
-+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
-+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <1>;
-+ };
-+
-+ opp-800000000 {
-+ opp-hz = /bits/ 64 <800000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
-+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <1>;
-+ };
-+
-+ opp-1000000000 {
-+ opp-hz = /bits/ 64 <1000000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
-+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <1>;
-+ };
-+
-+ opp-1200000000 {
-+ opp-hz = /bits/ 64 <1200000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
-+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
-+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <2>;
-+ };
-+
-+ opp-1400000000 {
-+ opp-hz = /bits/ 64 <1400000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
-+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
-+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
-+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <2>;
-+ };
-+ };
-+
- thermal-zones {
- sensor0-thermal {
- polling-delay-passive = <0>;
---- a/arch/arm/boot/dts/qcom-ipq8065.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
-@@ -6,3 +6,92 @@
- model = "Qualcomm Technologies, Inc. IPQ8065";
- compatible = "qcom,ipq8065", "qcom,ipq8064";
- };
-+
-+&opp_table_l2 {
-+ /delete-node/opp-1200000000;
-+
-+ opp-1400000000 {
-+ opp-hz = /bits/ 64 <1400000000>;
-+ opp-microvolt = <1150000>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <2>;
-+ };
-+};
-+
-+&opp_table0 {
-+ /*
-+ * On ipq8065 1.2 ghz freq is not present
-+ * Remove it to make cpufreq work and not
-+ * complain for missing definition
-+ */
-+
-+ /delete-node/opp-1200000000;
-+
-+ /*
-+ * Voltage thresholds are <target min max>
-+ */
-+ opp-384000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
-+ opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
-+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
-+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
-+ opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
-+ opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
-+ opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
-+ };
-+
-+ opp-600000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
-+ opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
-+ opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
-+ opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
-+ opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
-+ opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
-+ };
-+
-+ opp-800000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
-+ opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
-+ opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
-+ opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
-+ opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
-+ };
-+
-+ opp-1000000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+ opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
-+ opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
-+ opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
-+ opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
-+ };
-+
-+ opp-1400000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
-+ opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
-+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
-+ opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
-+ opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
-+ opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
-+ opp-level = <1>;
-+ };
-+
-+ opp-1725000000 {
-+ opp-hz = /bits/ 64 <1725000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
-+ opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
-+ opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
-+ opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
-+ opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
-+ opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
-+ opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <2>;
-+ };
-+};
---- a/arch/arm/boot/dts/qcom-ipq8062.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi
-@@ -6,3 +6,39 @@
- model = "Qualcomm Technologies, Inc. IPQ8062";
- compatible = "qcom,ipq8062", "qcom,ipq8064";
- };
-+
-+&opp_table0 {
-+ /delete-node/opp-1200000000;
-+ /delete-node/opp-1400000000;
-+
-+ /*
-+ * Voltage thresholds are <target min max>
-+ */
-+ opp-384000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+ opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>;
-+ opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>;
-+ opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>;
-+ };
-+
-+ opp-600000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+ opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>;
-+ opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>;
-+ opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>;
-+ };
-+
-+ opp-800000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>;
-+ opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>;
-+ };
-+
-+ opp-1000000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
-+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>;
-+ };
-+};
+++ /dev/null
-From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 18 Jan 2022 00:07:57 +0100
-Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu
- and l2 for ipq8064
-
-Add multiple binding for cpu node, l2 node and add idle-states
-definition for ipq8064 dtsi.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -30,6 +30,15 @@
- next-level-cache = <&L2>;
- qcom,acc = <&acc0>;
- qcom,saw = <&saw0>;
-+ clocks = <&kraitcc 0>, <&kraitcc 4>;
-+ clock-names = "cpu", "l2";
-+ clock-latency = <100000>;
-+ operating-points-v2 = <&opp_table0>;
-+ voltage-tolerance = <5>;
-+ cooling-min-state = <0>;
-+ cooling-max-state = <10>;
-+ #cooling-cells = <2>;
-+ cpu-idle-states = <&CPU_SPC>;
- };
-
- cpu1: cpu@1 {
-@@ -40,11 +49,35 @@
- next-level-cache = <&L2>;
- qcom,acc = <&acc1>;
- qcom,saw = <&saw1>;
-+ clocks = <&kraitcc 1>, <&kraitcc 4>;
-+ clock-names = "cpu", "l2";
-+ clock-latency = <100000>;
-+ operating-points-v2 = <&opp_table0>;
-+ voltage-tolerance = <5>;
-+ cooling-min-state = <0>;
-+ cooling-max-state = <10>;
-+ #cooling-cells = <2>;
-+ cpu-idle-states = <&CPU_SPC>;
-+ };
-+
-+ idle-states {
-+ CPU_SPC: spc {
-+ compatible = "qcom,idle-state-spc";
-+ status = "disabled";
-+ entry-latency-us = <400>;
-+ exit-latency-us = <900>;
-+ min-residency-us = <3000>;
-+ };
- };
-
- L2: l2-cache {
- compatible = "cache";
- cache-level = <2>;
-+ qcom,saw = <&saw_l2>;
-+
-+ clocks = <&kraitcc 4>;
-+ clock-names = "l2";
-+ operating-points-v2 = <&opp_table_l2>;
- };
- };
-
---- a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
-@@ -2,6 +2,18 @@
-
- #include "qcom-ipq8064.dtsi"
-
-+&cpu0 {
-+ cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+ l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- smb208_regulators: regulators {
- compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
-@@ -2,6 +2,18 @@
-
- #include "qcom-ipq8064-v2.0.dtsi"
-
-+&cpu0 {
-+ cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+ l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- smb208_regulators: regulators {
- compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
-@@ -2,6 +2,18 @@
-
- #include "qcom-ipq8062.dtsi"
-
-+&cpu0 {
-+ cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+ l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- smb208_regulators: regulators {
- compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
-@@ -2,6 +2,18 @@
-
- #include "qcom-ipq8065.dtsi"
-
-+&cpu0 {
-+ cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+ l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- smb208_regulators: regulators {
- compatible = "qcom,rpm-smb208-regulators";
+++ /dev/null
-From 6c94e0184e56f9e9f1f5d5f54b20758433e498d2 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Wed, 15 Jun 2022 16:47:09 +0200
-Subject: [PATCH 1/2] ARM: dts: qcom: fix wrong nad_pins definition for ipq806x
-
-Fix wrong nand_pings definition for bias-disable pins.
-
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -599,12 +599,9 @@
- };
-
- nand_pins: nand_pins {
-- mux {
-+ disable {
- pins = "gpio34", "gpio35", "gpio36",
-- "gpio37", "gpio38", "gpio39",
-- "gpio40", "gpio41", "gpio42",
-- "gpio43", "gpio44", "gpio45",
-- "gpio46", "gpio47";
-+ "gpio37", "gpio38";
- function = "nand";
- drive-strength = <10>;
- bias-disable;
+++ /dev/null
-From 504188183408fac0f61b59f5ed8ea1773fe43669 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Wed, 15 Jun 2022 16:59:30 +0200
-Subject: [PATCH 2/2] ARM: dts: qcom: add MDIO dedicated controller node for
- ipq806x
-
-Add MDIO dedicated controller attached to gmac0 and fix rb3011 dts to
-correctly use the new tag.
-
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 134 +++++++++++-----------
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 +++
- 2 files changed, 81 insertions(+), 67 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
-+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
-@@ -25,73 +25,6 @@
- device_type = "memory";
- };
-
-- mdio0: mdio-0 {
-- status = "okay";
-- compatible = "virtual,mdio-gpio";
-- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
-- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- pinctrl-0 = <&mdio0_pins>;
-- pinctrl-names = "default";
--
-- switch0: switch@10 {
-- compatible = "qca,qca8337";
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- dsa,member = <0 0>;
--
-- pinctrl-0 = <&sw0_reset_pin>;
-- pinctrl-names = "default";
--
-- reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
-- reg = <0x10>;
--
-- ports {
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- switch0cpu: port@0 {
-- reg = <0>;
-- label = "cpu";
-- ethernet = <&gmac0>;
-- phy-mode = "rgmii-id";
-- fixed-link {
-- speed = <1000>;
-- full-duplex;
-- };
-- };
--
-- port@1 {
-- reg = <1>;
-- label = "sw1";
-- };
--
-- port@2 {
-- reg = <2>;
-- label = "sw2";
-- };
--
-- port@3 {
-- reg = <3>;
-- label = "sw3";
-- };
--
-- port@4 {
-- reg = <4>;
-- label = "sw4";
-- };
--
-- port@5 {
-- reg = <5>;
-- label = "sw5";
-- };
-- };
-- };
-- };
--
- mdio1: mdio-1 {
- status = "okay";
- compatible = "virtual,mdio-gpio";
-@@ -222,6 +155,73 @@
- status = "okay";
- };
-
-+&mdio0 {
-+ status = "okay";
-+ compatible = "virtual,mdio-gpio";
-+ gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
-+ <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pinctrl-0 = <&mdio0_pins>;
-+ pinctrl-names = "default";
-+
-+ switch0: switch@10 {
-+ compatible = "qca,qca8337";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ dsa,member = <0 0>;
-+
-+ pinctrl-0 = <&sw0_reset_pin>;
-+ pinctrl-names = "default";
-+
-+ reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
-+ reg = <0x10>;
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ switch0cpu: port@0 {
-+ reg = <0>;
-+ label = "cpu";
-+ ethernet = <&gmac0>;
-+ phy-mode = "rgmii-id";
-+ fixed-link {
-+ speed = <1000>;
-+ full-duplex;
-+ };
-+ };
-+
-+ port@1 {
-+ reg = <1>;
-+ label = "sw1";
-+ };
-+
-+ port@2 {
-+ reg = <2>;
-+ label = "sw2";
-+ };
-+
-+ port@3 {
-+ reg = <3>;
-+ label = "sw3";
-+ };
-+
-+ port@4 {
-+ reg = <4>;
-+ label = "sw4";
-+ };
-+
-+ port@5 {
-+ reg = <5>;
-+ label = "sw5";
-+ };
-+ };
-+ };
-+};
-+
- &gmac0 {
- status = "okay";
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -476,6 +476,20 @@
- snps,blen = <16 0 0 0 0 0 0>;
- };
-
-+ mdio0: mdio@37000000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ compatible = "qcom,ipq8064-mdio", "syscon";
-+ reg = <0x37000000 0x200000>;
-+ resets = <&gcc GMAC_CORE1_RESET>;
-+ reset-names = "stmmaceth";
-+ clocks = <&gcc GMAC_CORE1_CLK>;
-+ clock-names = "stmmaceth";
-+
-+ status = "disabled";
-+ };
-+
- vsdcc_fixed: vsdcc-regulator {
- compatible = "regulator-fixed";
- regulator-name = "SDCC Power";
+++ /dev/null
-From b044ae89862132a86fb511648e9c52ea3cdf8c30 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 5 Aug 2020 14:19:23 +0200
-Subject: [PATCH 1/4] devfreq: qcom: Add L2 Krait Cache devfreq scaling driver
-
-Qcom L2 Krait CPUs use the generic cpufreq-dt driver and doesn't actually
-scale the Cache frequency when the CPU frequency is changed. This
-devfreq driver register with the cpu notifier and scale the Cache
-based on the max Freq across all core as the CPU cache is shared across
-all of them. If provided this also scale the voltage of the regulator
-attached to the CPU cache. The scaling logic is based on the CPU freq
-and the 3 scaling interval are set by the device dts.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/devfreq/Kconfig | 11 ++
- drivers/devfreq/Makefile | 1 +
- drivers/devfreq/krait-cache-devfreq.c | 188 ++++++++++++++++++++++++++
- 3 files changed, 200 insertions(+)
- create mode 100644 drivers/devfreq/krait-cache-devfreq.c
-
---- a/drivers/devfreq/Kconfig
-+++ b/drivers/devfreq/Kconfig
-@@ -151,6 +151,17 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ
- This adds the DEVFREQ driver for the MBUS controller in some
- Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
-
-+config ARM_KRAIT_CACHE_DEVFREQ
-+ tristate "Scaling support for Krait CPU Cache Devfreq"
-+ depends on ARCH_QCOM || COMPILE_TEST
-+ select DEVFREQ_GOV_PASSIVE
-+ help
-+ This adds the DEVFREQ driver for the Krait CPU L2 Cache shared by all cores.
-+
-+ The driver register with the cpufreq notifier and find the right frequency
-+ based on the max frequency across all core and the range set in the device
-+ dts. If provided this scale also the regulator attached to the l2 cache.
-+
- source "drivers/devfreq/event/Kconfig"
-
- endif # PM_DEVFREQ
---- a/drivers/devfreq/Makefile
-+++ b/drivers/devfreq/Makefile
-@@ -15,6 +15,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) +
- obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
- obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
- obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
-+obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o
-
- # DEVFREQ Event Drivers
- obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/
---- /dev/null
-+++ b/drivers/devfreq/krait-cache-devfreq.c
-@@ -0,0 +1,181 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/cpufreq.h>
-+#include <linux/devfreq.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/slab.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/pm_opp.h>
-+
-+#include "governor.h"
-+
-+struct krait_cache_data {
-+ struct clk *clk;
-+ unsigned long idle_freq;
-+ int token;
-+};
-+
-+static int krait_cache_config_clk(struct device *dev, struct opp_table *opp_table,
-+ struct dev_pm_opp *old_opp, struct dev_pm_opp *opp,
-+ void *data, bool scaling_down)
-+{
-+ struct krait_cache_data *kdata;
-+ unsigned long old_freq, freq;
-+ unsigned long idle_freq;
-+ struct clk *clk;
-+ int ret;
-+
-+ kdata = dev_get_drvdata(dev);
-+ idle_freq = kdata->idle_freq;
-+ clk = kdata->clk;
-+
-+ old_freq = dev_pm_opp_get_freq(old_opp);
-+ freq = dev_pm_opp_get_freq(opp);
-+
-+ /*
-+ * Set to idle bin if switching from normal to high bin
-+ * or vice versa. It has been notice that a bug is triggered
-+ * in cache scaling when more than one bin is scaled, to fix
-+ * this we first need to transition to the base rate and then
-+ * to target rate
-+ */
-+ if (likely(freq != idle_freq && old_freq != idle_freq)) {
-+ ret = clk_set_rate(clk, idle_freq);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ return clk_set_rate(clk, freq);
-+};
-+
-+static int krait_cache_get_cur_freq(struct device *dev, unsigned long *freq)
-+{
-+ struct krait_cache_data *data = dev_get_drvdata(dev);
-+
-+ *freq = clk_get_rate(data->clk);
-+
-+ return 0;
-+};
-+
-+static int krait_cache_target(struct device *dev, unsigned long *freq,
-+ u32 flags)
-+{
-+ struct dev_pm_opp *opp;
-+
-+ opp = dev_pm_opp_find_freq_ceil(dev, freq);
-+ if (unlikely(IS_ERR(opp)))
-+ return PTR_ERR(opp);
-+
-+ dev_pm_opp_put(opp);
-+
-+ return dev_pm_opp_set_rate(dev, *freq);
-+};
-+
-+static int krait_cache_get_dev_status(struct device *dev,
-+ struct devfreq_dev_status *stat)
-+{
-+ struct krait_cache_data *data = dev_get_drvdata(dev);
-+
-+ stat->busy_time = 0;
-+ stat->total_time = 0;
-+ stat->current_frequency = clk_get_rate(data->clk);
-+
-+ return 0;
-+};
-+
-+static struct devfreq_dev_profile krait_cache_devfreq_profile = {
-+ .target = krait_cache_target,
-+ .get_dev_status = krait_cache_get_dev_status,
-+ .get_cur_freq = krait_cache_get_cur_freq
-+};
-+
-+static struct devfreq_passive_data devfreq_gov_data = {
-+ .parent_type = CPUFREQ_PARENT_DEV,
-+};
-+
-+static int krait_cache_probe(struct platform_device *pdev)
-+{
-+ struct dev_pm_opp_config config = { };
-+ struct device *dev = &pdev->dev;
-+ struct krait_cache_data *data;
-+ struct devfreq *devfreq;
-+ struct dev_pm_opp *opp;
-+ struct clk *clk;
-+ int ret, token;
-+
-+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-+ if (!data)
-+ return -ENOMEM;
-+
-+ clk = devm_clk_get(dev, "l2");
-+ if (IS_ERR(clk))
-+ return PTR_ERR(clk);
-+
-+ config.regulator_names = (const char *[]){ "l2", NULL };
-+ config.clk_names = (const char *[]){ "l2", NULL };
-+ config.config_clks = krait_cache_config_clk;
-+
-+ token = dev_pm_opp_set_config(dev, &config);
-+ if (token < 0)
-+ return token;
-+
-+ ret = devm_pm_opp_of_add_table(dev);
-+ if (ret)
-+ goto free_opp;
-+
-+ opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq);
-+ if (IS_ERR(opp)) {
-+ ret = PTR_ERR(opp);
-+ goto free_opp;
-+ }
-+ dev_pm_opp_put(opp);
-+
-+ data->token = token;
-+ data->clk = clk;
-+ dev_set_drvdata(dev, data);
-+ devfreq = devm_devfreq_add_device(dev, &krait_cache_devfreq_profile,
-+ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data);
-+ if (IS_ERR(devfreq)) {
-+ ret = PTR_ERR(devfreq);
-+ goto free_opp;
-+ }
-+
-+ return 0;
-+
-+free_opp:
-+ dev_pm_opp_clear_config(token);
-+ return ret;
-+};
-+
-+static int krait_cache_remove(struct platform_device *pdev)
-+{
-+ struct krait_cache_data *data = dev_get_drvdata(&pdev->dev);
-+
-+ dev_pm_opp_clear_config(data->token);
-+
-+ return 0;
-+};
-+
-+static const struct of_device_id krait_cache_match_table[] = {
-+ { .compatible = "qcom,krait-cache" },
-+ {}
-+};
-+
-+static struct platform_driver krait_cache_driver = {
-+ .probe = krait_cache_probe,
-+ .remove = krait_cache_remove,
-+ .driver = {
-+ .name = "krait-cache-scaling",
-+ .of_match_table = krait_cache_match_table,
-+ },
-+};
-+module_platform_driver(krait_cache_driver);
-+
-+MODULE_DESCRIPTION("Krait CPU Cache Scaling driver");
-+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From ef124ad0ff8abfbf4ebe3fe6d7dcef4541dec13a Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 18:39:21 +0200
-Subject: [PATCH] ARM: dts: qcom: add krait-cache compatible for ipq806x dtsi
-
-Add qcom,krait-cache compatible to enable cache devfreq driver for
-ipq806x SoC and move the L2 node to the soc node to make the devfreq
-driver correctly probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 22 +++++++++++-----------
- 1 file changed, 11 insertions(+), 11 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -69,16 +69,6 @@
- min-residency-us = <3000>;
- };
- };
--
-- L2: l2-cache {
-- compatible = "cache";
-- cache-level = <2>;
-- qcom,saw = <&saw_l2>;
--
-- clocks = <&kraitcc 4>;
-- clock-names = "l2";
-- operating-points-v2 = <&opp_table_l2>;
-- };
- };
-
- opp_table_l2: opp_table_l2 {
-@@ -1409,6 +1399,16 @@
- #reset-cells = <1>;
- };
-
-+ L2: l2-cache {
-+ compatible = "cache", "qcom,krait-cache";
-+ cache-level = <2>;
-+ qcom,saw = <&saw_l2>;
-+
-+ clocks = <&kraitcc 4>;
-+ clock-names = "l2";
-+ operating-points-v2 = <&opp_table_l2>;
-+ };
-+
- lpass@28100000 {
- compatible = "qcom,lpass-cpu";
- status = "disabled";
+++ /dev/null
-From 13f075999935bb696dbab63243923179f06fa05e Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 19:56:08 +0200
-Subject: [PATCH 3/4] devfreq: add ipq806x fabric scaling driver
-
-Add ipq806x fabric scaling driver using the devfreq passive governor.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/devfreq/Kconfig | 11 ++
- drivers/devfreq/Makefile | 1 +
- drivers/devfreq/ipq806x-fab-devfreq.c | 155 ++++++++++++++++++++++++++
- 3 files changed, 167 insertions(+)
- create mode 100644 drivers/devfreq/ipq806x-fab-devfreq.c
-
---- a/drivers/devfreq/Kconfig
-+++ b/drivers/devfreq/Kconfig
-@@ -162,6 +162,17 @@ config ARM_KRAIT_CACHE_DEVFREQ
- based on the max frequency across all core and the range set in the device
- dts. If provided this scale also the regulator attached to the l2 cache.
-
-+config ARM_IPQ806X_FAB_DEVFREQ
-+ tristate "Scaling support for ipq806x Soc Fabric"
-+ depends on ARCH_QCOM || COMPILE_TEST
-+ select DEVFREQ_GOV_PASSIVE
-+ help
-+ This adds the DEVFREQ driver for the ipq806x Soc Fabric.
-+
-+ The driver register with the cpufreq notifier and find the right frequency
-+ based on the max frequency across all core and the range set in the device
-+ dts.
-+
- source "drivers/devfreq/event/Kconfig"
-
- endif # PM_DEVFREQ
---- a/drivers/devfreq/Makefile
-+++ b/drivers/devfreq/Makefile
-@@ -16,6 +16,7 @@ obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) +=
- obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
- obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
- obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o
-+obj-$(CONFIG_ARM_IPQ806X_FAB_DEVFREQ) += ipq806x-fab-devfreq.o
-
- # DEVFREQ Event Drivers
- obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/
---- /dev/null
-+++ b/drivers/devfreq/ipq806x-fab-devfreq.c
-@@ -0,0 +1,155 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/cpufreq.h>
-+#include <linux/devfreq.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/slab.h>
-+#include <linux/pm_opp.h>
-+
-+#include "governor.h"
-+
-+struct ipq806x_fab_data {
-+ struct clk *fab_clk;
-+ struct clk *ddr_clk;
-+};
-+
-+static int ipq806x_fab_get_cur_freq(struct device *dev, unsigned long *freq)
-+{
-+ struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+
-+ *freq = clk_get_rate(data->fab_clk);
-+
-+ return 0;
-+};
-+
-+static int ipq806x_fab_target(struct device *dev, unsigned long *freq,
-+ u32 flags)
-+{
-+ struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+ struct dev_pm_opp *opp;
-+ int ret;
-+
-+ opp = dev_pm_opp_find_freq_ceil(dev, freq);
-+ if (unlikely(IS_ERR(opp)))
-+ return PTR_ERR(opp);
-+
-+ dev_pm_opp_put(opp);
-+
-+ ret = clk_set_rate(data->fab_clk, *freq);
-+ if (ret)
-+ return ret;
-+
-+ return clk_set_rate(data->ddr_clk, *freq);
-+};
-+
-+static int ipq806x_fab_get_dev_status(struct device *dev,
-+ struct devfreq_dev_status *stat)
-+{
-+ struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+
-+ stat->busy_time = 0;
-+ stat->total_time = 0;
-+ stat->current_frequency = clk_get_rate(data->fab_clk);
-+
-+ return 0;
-+};
-+
-+static struct devfreq_dev_profile ipq806x_fab_devfreq_profile = {
-+ .target = ipq806x_fab_target,
-+ .get_dev_status = ipq806x_fab_get_dev_status,
-+ .get_cur_freq = ipq806x_fab_get_cur_freq
-+};
-+
-+static struct devfreq_passive_data devfreq_gov_data = {
-+ .parent_type = CPUFREQ_PARENT_DEV,
-+};
-+
-+static int ipq806x_fab_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct ipq806x_fab_data *data;
-+ struct devfreq *devfreq;
-+ struct clk *clk;
-+ int ret;
-+
-+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-+ if (!data)
-+ return -ENOMEM;
-+
-+ clk = devm_clk_get(dev, "apps-fab-clk");
-+ if (IS_ERR(clk)) {
-+ dev_err_probe(dev, PTR_ERR(clk), "failed to get apps fab clk\n");
-+ return PTR_ERR(clk);
-+ }
-+
-+ clk_prepare_enable(clk);
-+ data->fab_clk = clk;
-+
-+ clk = devm_clk_get(dev, "ddr-fab-clk");
-+ if (IS_ERR(clk)) {
-+ dev_err_probe(dev, PTR_ERR(clk), "failed to get ddr fab clk\n");
-+ goto err_ddr;
-+ }
-+
-+ clk_prepare_enable(clk);
-+ data->ddr_clk = clk;
-+
-+ ret = dev_pm_opp_of_add_table(dev);
-+ if (ret) {
-+ dev_err(dev, "failed to parse fab freq thresholds\n");
-+ return ret;
-+ }
-+
-+ dev_set_drvdata(dev, data);
-+
-+ devfreq = devm_devfreq_add_device(&pdev->dev, &ipq806x_fab_devfreq_profile,
-+ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data);
-+ if (IS_ERR(devfreq))
-+ dev_pm_opp_remove_table(dev);
-+
-+ return PTR_ERR_OR_ZERO(devfreq);
-+
-+err_ddr:
-+ clk_unprepare(data->fab_clk);
-+ clk_put(data->fab_clk);
-+ return PTR_ERR(clk);
-+};
-+
-+static int ipq806x_fab_remove(struct platform_device *pdev)
-+{
-+ struct ipq806x_fab_data *data = dev_get_drvdata(&pdev->dev);
-+
-+ clk_unprepare(data->fab_clk);
-+ clk_put(data->fab_clk);
-+
-+ clk_unprepare(data->ddr_clk);
-+ clk_put(data->ddr_clk);
-+
-+ dev_pm_opp_remove_table(&pdev->dev);
-+
-+ return 0;
-+};
-+
-+static const struct of_device_id ipq806x_fab_match_table[] = {
-+ { .compatible = "qcom,fab-scaling" },
-+ {}
-+};
-+
-+static struct platform_driver ipq806x_fab_driver = {
-+ .probe = ipq806x_fab_probe,
-+ .remove = ipq806x_fab_remove,
-+ .driver = {
-+ .name = "ipq806x-fab-scaling",
-+ .of_match_table = ipq806x_fab_match_table,
-+ },
-+};
-+module_platform_driver(ipq806x_fab_driver);
-+
-+MODULE_DESCRIPTION("ipq806x Fab Scaling driver");
-+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From c3573f0907dadb0a6e9933aae2a46a489abcbd48 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 20:03:05 +0200
-Subject: [PATCH 4/4] ARM: dts: qcom: add fab scaling node for ipq806x
-
-Add fabric scaling node for ipq806x to correctly scale apps and ddr
-fabric clk.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -170,6 +170,18 @@
- };
- };
-
-+ opp_table_fab: opp_table_fab {
-+ compatible = "operating-points-v2";
-+
-+ opp-533000000 {
-+ opp-hz = /bits/ 64 <533000000>;
-+ };
-+
-+ opp-400000000 {
-+ opp-hz = /bits/ 64 <400000000>;
-+ };
-+ };
-+
- thermal-zones {
- sensor0-thermal {
- polling-delay-passive = <0>;
-@@ -1409,6 +1421,13 @@
- operating-points-v2 = <&opp_table_l2>;
- };
-
-+ fab-scaling {
-+ compatible = "qcom,fab-scaling";
-+ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
-+ clock-names = "apps-fab-clk", "ddr-fab-clk";
-+ operating-points-v2 = <&opp_table_fab>;
-+ };
-+
- lpass@28100000 {
- compatible = "qcom,lpass-cpu";
- status = "disabled";
+++ /dev/null
-From 666c1b745e93ccddde841d5057c33f97b29a316a Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 02:19:28 +0200
-Subject: [PATCH 3/9] clk: qcom: krait-cc: handle qsb clock defined in DTS
-
-qsb fixed clk may be defined in DTS and correctly passed in the clocks
-list. Add related code to handle this and modify the logic to
-dynamically read qsb clock frequency.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 14 +++++++++++---
- 1 file changed, 11 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -348,7 +348,7 @@ static int krait_cc_probe(struct platfor
- {
- struct device *dev = &pdev->dev;
- const struct of_device_id *id;
-- unsigned long cur_rate, aux_rate;
-+ unsigned long cur_rate, aux_rate, qsb_rate;
- int cpu;
- struct clk_hw *mux, *l2_pri_mux;
- struct clk *clk, **clks;
-@@ -357,11 +357,19 @@ static int krait_cc_probe(struct platfor
- if (!id)
- return -ENODEV;
-
-- /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
-- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
-+ /*
-+ * Per Documentation qsb should be provided from DTS.
-+ * To address old implementation, register the fixed clock anyway.
-+ * Rate is 1 because 0 causes problems for __clk_mux_determine_rate
-+ */
-+ clk = clk_get(dev, "qsb");
-+ if (IS_ERR(clk))
-+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
-+ qsb_rate = clk_get_rate(clk);
-+
- if (!id->data) {
- clk = clk_register_fixed_factor(dev, "acpu_aux",
- "gpll0_vote", 0, 1, 2);
+++ /dev/null
-From fca6f185a9d9ef0892a719bc6da955b22d326ec7 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 02:24:33 +0200
-Subject: [PATCH 4/9] clk: qcom: krait-cc: register REAL qsb fixed clock
-
-With some tools it was discovered the real frequency of the qsb fixed
-clock. While not 100% correct it's still better than using 1 as a dummy
-frequency.
-Correctly register the qsb fixed clock with the frequency of 225 MHz
-instead of 1.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -25,6 +25,8 @@ enum {
- clks_max,
- };
-
-+#define QSB_RATE 2250000000
-+
- static unsigned int sec_mux_map[] = {
- 2,
- 0,
-@@ -364,7 +366,7 @@ static int krait_cc_probe(struct platfor
- */
- clk = clk_get(dev, "qsb");
- if (IS_ERR(clk))
-- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
-+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, QSB_RATE);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
+++ /dev/null
-From 2399d181557d94ae9a2686926cd25768f132e4b4 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 18 Mar 2022 16:12:14 +0100
-Subject: [PATCH 7/9] clk: qcom: krait-cc: drop pr_info and use dev_info
-
-Replace pr_info() with dev_info() to provide better diagnostics.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -423,25 +423,25 @@ static int krait_cc_probe(struct platfor
- cur_rate = clk_get_rate(clks[l2_mux]);
- aux_rate = 384000000;
- if (cur_rate < aux_rate) {
-- pr_info("L2 @ Undefined rate. Forcing new rate.\n");
-+ dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n");
- cur_rate = aux_rate;
- }
- clk_set_rate(clks[l2_mux], aux_rate);
- clk_set_rate(clks[l2_mux], 2);
- clk_set_rate(clks[l2_mux], cur_rate);
-- pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
-+ dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
- for_each_possible_cpu(cpu) {
- clk = clks[cpu];
- cur_rate = clk_get_rate(clk);
- if (cur_rate < aux_rate) {
-- pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
-+ dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
- cur_rate = aux_rate;
- }
-
- clk_set_rate(clk, aux_rate);
- clk_set_rate(clk, 2);
- clk_set_rate(clk, cur_rate);
-- pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
-+ dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
- }
-
- of_clk_add_provider(dev->of_node, krait_of_get, clks);
+++ /dev/null
-From 6a77cf3f5f95ec0058e1b4d1ada018748cb0b83b Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 03:33:13 +0200
-Subject: [PATCH 9/9] clk: qcom: krait-cc: rework mux reset logic and reset
- hfpll
-
-Rework and clean mux reset logic.
-Compact it to a for loop to handle both CPU and L2 in one place.
-Move hardcoded aux_rate to define and add a new hfpll_rate value to
-reset hfpll settings.
-Change logic to now reset the hfpll to the lowest value of 600 Mhz and
-then restoring the previous frequency. This permits to reset the hfpll if
-the primary mux was set to source out of the secondary mux.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 50 +++++++++++++++++--------------------
- 1 file changed, 23 insertions(+), 27 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -25,7 +25,9 @@ enum {
- clks_max,
- };
-
--#define QSB_RATE 2250000000
-+#define QSB_RATE 225000000
-+#define AUX_RATE 384000000
-+#define HFPLL_RATE 600000000
-
- static unsigned int sec_mux_map[] = {
- 2,
-@@ -350,7 +352,7 @@ static int krait_cc_probe(struct platfor
- {
- struct device *dev = &pdev->dev;
- const struct of_device_id *id;
-- unsigned long cur_rate, aux_rate, qsb_rate;
-+ unsigned long cur_rate, qsb_rate;
- int cpu;
- struct clk_hw *mux, *l2_pri_mux;
- struct clk *clk, **clks;
-@@ -420,28 +422,29 @@ static int krait_cc_probe(struct platfor
- * two different rates to force a HFPLL reinit under all
- * circumstances.
- */
-- cur_rate = clk_get_rate(clks[l2_mux]);
-- aux_rate = 384000000;
-- if (cur_rate < aux_rate) {
-- dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n");
-- cur_rate = aux_rate;
-- }
-- clk_set_rate(clks[l2_mux], aux_rate);
-- clk_set_rate(clks[l2_mux], 2);
-- clk_set_rate(clks[l2_mux], cur_rate);
-- dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
-- for_each_possible_cpu(cpu) {
-+ for (cpu = 0; cpu < 5; cpu++) {
-+ const char *l2_s = "L2";
-+ char cpu_s[5];
-+
- clk = clks[cpu];
-+ if (!clk)
-+ continue;
-+
-+ if (cpu < 4)
-+ snprintf(cpu_s, 5, "CPU%d", cpu);
-+
- cur_rate = clk_get_rate(clk);
-- if (cur_rate < aux_rate) {
-- dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
-- cur_rate = aux_rate;
-+ if (cur_rate < AUX_RATE) {
-+ dev_info(dev, "%s @ Undefined rate. Forcing new rate.\n",
-+ cpu < 4 ? cpu_s : l2_s);
-+ cur_rate = AUX_RATE;
- }
-
-- clk_set_rate(clk, aux_rate);
-- clk_set_rate(clk, 2);
-+ clk_set_rate(clk, AUX_RATE);
-+ clk_set_rate(clk, HFPLL_RATE);
- clk_set_rate(clk, cur_rate);
-- dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
-+ dev_info(dev, "%s @ %lu KHz\n", cpu < 4 ? cpu_s : l2_s,
-+ clk_get_rate(clk) / 1000);
- }
-
- of_clk_add_provider(dev->of_node, krait_of_get, clks);
+++ /dev/null
-From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 23 Sep 2022 19:05:39 +0200
-Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions
-
-Generilize div functions and remove hardcode to a divisor of 2.
-This is just a cleanup and permit to make it more clear the settings of
-the devisor when used by the krait-cc driver.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++----------------
- drivers/clk/qcom/clk-krait.h | 11 ++++---
- drivers/clk/qcom/krait-cc.c | 7 +++--
- 3 files changed, 42 insertions(+), 33 deletions(-)
-
---- a/drivers/clk/qcom/clk-krait.c
-+++ b/drivers/clk/qcom/clk-krait.c
-@@ -97,53 +97,58 @@ const struct clk_ops krait_mux_clk_ops =
- EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
-
- /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
--static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
-+static long krait_div_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
- {
-- *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
-- return DIV_ROUND_UP(*parent_rate, 2);
-+ struct krait_div_clk *d = to_krait_div_clk(hw);
-+
-+ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
-+ rate * d->divisor);
-+
-+ return DIV_ROUND_UP(*parent_rate, d->divisor);
- }
-
--static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
-+static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
- {
-- struct krait_div2_clk *d = to_krait_div2_clk(hw);
-+ struct krait_div_clk *d = to_krait_div_clk(hw);
-+ u8 div_val = krait_div_to_val(d->divisor);
- unsigned long flags;
-- u32 val;
-- u32 mask = BIT(d->width) - 1;
--
-- if (d->lpl)
-- mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
-- else
-- mask <<= d->shift;
-+ u32 regval;
-
- spin_lock_irqsave(&krait_clock_reg_lock, flags);
-- val = krait_get_l2_indirect_reg(d->offset);
-- val &= ~mask;
-- krait_set_l2_indirect_reg(d->offset, val);
-+ regval = krait_get_l2_indirect_reg(d->offset);
-+
-+ regval &= ~(d->mask << d->shift);
-+ regval |= (div_val & d->mask) << d->shift;
-+
-+ if (d->lpl) {
-+ regval &= ~(d->mask << (d->shift + LPL_SHIFT));
-+ regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT);
-+ }
-+
-+ krait_set_l2_indirect_reg(d->offset, regval);
- spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
-
- return 0;
- }
-
- static unsigned long
--krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
- {
-- struct krait_div2_clk *d = to_krait_div2_clk(hw);
-- u32 mask = BIT(d->width) - 1;
-+ struct krait_div_clk *d = to_krait_div_clk(hw);
- u32 div;
-
- div = krait_get_l2_indirect_reg(d->offset);
- div >>= d->shift;
-- div &= mask;
-- div = (div + 1) * 2;
-+ div &= d->mask;
-
-- return DIV_ROUND_UP(parent_rate, div);
-+ return DIV_ROUND_UP(parent_rate, krait_val_to_div(div));
- }
-
--const struct clk_ops krait_div2_clk_ops = {
-- .round_rate = krait_div2_round_rate,
-- .set_rate = krait_div2_set_rate,
-- .recalc_rate = krait_div2_recalc_rate,
-+const struct clk_ops krait_div_clk_ops = {
-+ .round_rate = krait_div_round_rate,
-+ .set_rate = krait_div_set_rate,
-+ .recalc_rate = krait_div_recalc_rate,
- };
--EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
-+EXPORT_SYMBOL_GPL(krait_div_clk_ops);
---- a/drivers/clk/qcom/clk-krait.h
-+++ b/drivers/clk/qcom/clk-krait.h
-@@ -25,17 +25,20 @@ struct krait_mux_clk {
-
- extern const struct clk_ops krait_mux_clk_ops;
-
--struct krait_div2_clk {
-+struct krait_div_clk {
- u32 offset;
-- u8 width;
-+ u32 mask;
-+ u8 divisor;
- u32 shift;
- bool lpl;
-
- struct clk_hw hw;
- };
-
--#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
-+#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw)
-+#define krait_div_to_val(_div) ((_div) / 2) - 1
-+#define krait_val_to_div(_val) ((_val) + 1) * 2
-
--extern const struct clk_ops krait_div2_clk_ops;
-+extern const struct clk_ops krait_div_clk_ops;
-
- #endif
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -86,11 +86,11 @@ static int krait_notifier_register(struc
- static struct clk_hw *
- krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
- {
-- struct krait_div2_clk *div;
-+ struct krait_div_clk *div;
- static struct clk_parent_data p_data[1];
- struct clk_init_data init = {
- .num_parents = ARRAY_SIZE(p_data),
-- .ops = &krait_div2_clk_ops,
-+ .ops = &krait_div_clk_ops,
- .flags = CLK_SET_RATE_PARENT,
- };
- struct clk_hw *clk;
-@@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id
- if (!div)
- return ERR_PTR(-ENOMEM);
-
-- div->width = 2;
-+ div->mask = 0x3;
-+ div->divisor = 2;
- div->shift = 6;
- div->lpl = id >= 0;
- div->offset = offset;
+++ /dev/null
-From ac84ac819a2e8fd3d87122b452c502a386c54437 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 5 Jul 2022 18:30:18 +0200
-Subject: [PATCH v2 4/4] clk: qcom: gcc-ipq806x: remove cc_register_board for
- pxo and cxo
-
-Now that these clock are defined as fixed clk in dts, we can drop the
-register_board_clk for cxo_board and pxo_board in gcc_ipq806x_probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/gcc-ipq806x.c | 8 --------
- 1 file changed, 8 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -3386,14 +3386,6 @@ static int gcc_ipq806x_probe(struct plat
- struct regmap *regmap;
- int ret;
-
-- ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
-- if (ret)
-- return ret;
--
-- ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
-- if (ret)
-- return ret;
--
- if (of_machine_is_compatible("qcom,ipq8065")) {
- ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
- ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
+++ /dev/null
-From: Christian Lamparter <chunkeey@googlemail.com>
-Subject: SoC: add qualcomm syscon
---- a/drivers/soc/qcom/Makefile
-+++ b/drivers/soc/qcom/Makefile
-@@ -23,6 +23,7 @@ obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
- obj-$(CONFIG_QCOM_SPM) += spm.o
- obj-$(CONFIG_QCOM_STATS) += qcom_stats.o
- obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
-+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
- obj-$(CONFIG_QCOM_APR) += apr.o
- obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
- obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
---- a/drivers/soc/qcom/Kconfig
-+++ b/drivers/soc/qcom/Kconfig
-@@ -213,6 +213,13 @@ config QCOM_STATS
- various SoC level low power modes statistics and export to debugfs
- interface.
-
-+config QCOM_TCSR
-+ tristate "QCOM Top Control and Status Registers"
-+ depends on ARCH_QCOM
-+ help
-+ Say y here to enable TCSR support. The TCSR provides control
-+ functions for various peripherals.
-+
- config QCOM_WCNSS_CTRL
- tristate "Qualcomm WCNSS control driver"
- depends on ARCH_QCOM || COMPILE_TEST
---- /dev/null
-+++ b/drivers/soc/qcom/qcom_tcsr.c
-@@ -0,0 +1,64 @@
-+/*
-+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License rev 2 and
-+ * only rev 2 as published by the free Software foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+
-+#define TCSR_USB_PORT_SEL 0xb0
-+
-+static int tcsr_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ const struct device_node *node = pdev->dev.of_node;
-+ void __iomem *base;
-+ u32 val;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
-+ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
-+ writel(val, base + TCSR_USB_PORT_SEL);
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id tcsr_dt_match[] = {
-+ { .compatible = "qcom,tcsr", },
-+ { },
-+};
-+
-+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
-+
-+static struct platform_driver tcsr_driver = {
-+ .driver = {
-+ .name = "tcsr",
-+ .owner = THIS_MODULE,
-+ .of_match_table = tcsr_dt_match,
-+ },
-+ .probe = tcsr_probe,
-+};
-+
-+module_platform_driver(tcsr_driver);
-+
-+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
-+MODULE_DESCRIPTION("QCOM TCSR driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/include/dt-bindings/soc/qcom,tcsr.h
-@@ -0,0 +1,23 @@
-+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+#ifndef __DT_BINDINGS_QCOM_TCSR_H
-+#define __DT_BINDINGS_QCOM_TCSR_H
-+
-+#define TCSR_USB_SELECT_USB3_P0 0x1
-+#define TCSR_USB_SELECT_USB3_P1 0x2
-+#define TCSR_USB_SELECT_USB3_DUAL 0x3
-+
-+/* TCSR A/B REG */
-+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
-+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
-+
-+#endif
+++ /dev/null
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
-
- endchoice
-
-+config CMDLINE_OVERRIDE
-+ bool "Use alternative cmdline from device tree"
-+ help
-+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+ be used, this is not a good option for kernels that are shared across
-+ devices. This setting enables using "chosen/cmdline-override" as the
-+ cmdline if it exists in the device tree.
-+
- config CMDLINE
- string "Default kernel command string"
- default ""
---- a/drivers/of/fdt.c
-+++ b/drivers/of/fdt.c
-@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha
- if (p != NULL && l > 0)
- strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
-
-+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
-+ * device tree option of chosen/bootargs-override. This is
-+ * helpful on boards where u-boot sets bootargs, and is unable
-+ * to be modified.
-+ */
-+#ifdef CONFIG_CMDLINE_OVERRIDE
-+ p = of_get_flat_dt_prop(node, "bootargs-override", &l);
-+ if (p != NULL && l > 0)
-+ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
-+#endif
-+
- handle_cmdline:
- /*
- * CONFIG_CMDLINE is meant to be a default in case nothing else
+++ /dev/null
-From 2f86b9b71a11f86e3d850214ab781ebb17d7260e Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 19 Jan 2024 19:48:30 +0100
-Subject: [PATCH v2 1/2] ARM: decompressor: support memory start validation for
- appended DTB
-
-There is currently a problem with a very specific sets of kernel config
-and AUTO_ZRELADDR.
-
-For the most common case AUTO_ZRELADDR check the PC register and
-calculate the start of the physical memory. Then fdt_check_mem_start is
-called to make sure the detected value makes sense by comparing it with
-what is present in DTB in the memory nodes and if additional fixup are
-required with the use of linux,usable-memory-range in the chosen node to
-hardcode usable memory range in case some reserved space needs to be
-addressed. With the help of this function the right address is
-calculated and the kernel correctly decompress and loads.
-
-Things starts to become problematic when in the mix,
-CONFIG_ARM_APPENDED_DTB is used. This is a particular kernel config is
-used when legacy systems doesn't support passing a DTB directly and a
-DTB is appended at the end of the image.
-
-In such case, fdt_check_mem_start is skipped in AUTO_ZRELADDR iteration
-as the appended DTB can be augumented later with ATAGS passed from the
-bootloader (if CONFIG_ARM_ATAG_DTB_COMPAT is enabled).
-
-The main problem and what this patch address is the fact that
-fdt_check_mem_start is never called later when the appended DTB is
-augumented, hence any fixup and validation is not done making AUTO_ZRELADDR
-detection inconsistent and most of the time wrong.
-
-Add support in head.S for this by checking if AUTO_ZRELADDR is enabled
-and calling fdt_check_mem_start with the appended DTB and the augumented
-values permitting legacy device to provide info in DTB instead of
-disabling AUTO_ZRELADDR and hardcoding the physical address offsets.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/compressed/head.S | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm/boot/compressed/head.S
-+++ b/arch/arm/boot/compressed/head.S
-@@ -443,6 +443,28 @@ restart: adr r0, LC1
- add r6, r6, r5
- add r10, r10, r5
- add sp, sp, r5
-+
-+#ifdef CONFIG_AUTO_ZRELADDR
-+ /*
-+ * Validate calculated start of physical memory with appended DTB.
-+ * In the first iteration for physical memory start calculation,
-+ * we skipped validating it as it could have been augumented by
-+ * ATAGS stored at an offset from the same start of physical memory.
-+ *
-+ * We now have parsed them and augumented the appended DTB if asked
-+ * so we can finally validate the start of physical memory.
-+ *
-+ * This is needed to apply additional fixup with
-+ * linux,usable-memory-range or to make sure AUTO_ZRELADDR detected
-+ * the correct value.
-+ */
-+ sub r0, r4, #TEXT_OFFSET @ revert to base address
-+ mov r1, r8 @ use appended DTB
-+ bl fdt_check_mem_start
-+
-+ /* Determine final kernel image address. */
-+ add r4, r0, #TEXT_OFFSET
-+#endif
- dtb_check_done:
- #endif
-
+++ /dev/null
-From 781d7cd4c3364e9d38fa12a342c5ad4c7e33a5ba Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 19 Jan 2024 20:33:10 +0100
-Subject: [PATCH v2 2/2] ARM: decompressor: add option to ignore MEM ATAGs
-
-Some bootloaders can pass broken MEM ATAGs that provide hardcoded
-information about mounted RAM size and physical location.
-Example booloader provide RAM of size 1.7Gb but actual mounted RAM
-size is 512Mb causing kernel panic.
-
-Add option CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM to ignore these ATAG
-and not augument appended DTB memory node.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/Kconfig | 12 ++++++++++++
- arch/arm/boot/compressed/atags_to_fdt.c | 4 ++++
- 2 files changed, 16 insertions(+)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1570,6 +1570,18 @@ config ARM_ATAG_DTB_COMPAT
- bootloaders, this option allows zImage to extract the information
- from the ATAG list and store it at run time into the appended DTB.
-
-+config ARM_ATAG_DTB_COMPAT_IGNORE_MEM
-+ bool "Ignore MEM ATAG information from bootloader"
-+ depends on ARM_ATAG_DTB_COMPAT
-+ help
-+ Some bootloaders can pass broken MEM ATAGs that provide hardcoded
-+ information about mounted RAM size and physical location.
-+ Example booloader provide RAM of size 1.7Gb but actual mounted RAM
-+ size is 512Mb causing kernel panic.
-+
-+ Enable this option if MEM ATAGs should be ignored and the memory
-+ node in the appended DTB should NOT be augumented.
-+
- choice
- prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
- default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -169,6 +169,10 @@ int atags_to_fdt(void *atag_list, void *
- setprop_string(fdt, "/chosen", "bootargs",
- atag->u.cmdline.cmdline);
- } else if (atag->hdr.tag == ATAG_MEM) {
-+ /* Bootloader MEM ATAG are broken and should be ignored */
-+ if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM))
-+ continue;
-+
- if (memcount >= sizeof(mem_reg_property)/4)
- continue;
- if (!atag->u.mem.size)
+++ /dev/null
-From 13bb6d8dd9138927950a520a288401db82871dc9 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sun, 21 Jan 2024 23:36:57 +0100
-Subject: [PATCH] ARM: decompressor: support for ATAGs rootblock parsing
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
-[ reworked to a cleaner patch ]
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/Kconfig | 10 +++
- arch/arm/boot/compressed/atags_to_fdt.c | 102 ++++++++++++++++++++++--
- init/main.c | 12 +++
- 3 files changed, 117 insertions(+), 7 deletions(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1599,6 +1599,16 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- The command-line arguments provided by the boot loader will be
- appended to the the device tree bootargs property.
-
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+ bool "Append rootblock parsing bootloader's kernel arguments"
-+ help
-+ The command-line arguments provided by the boot loader will be
-+ appended to a new device tree property: bootloader-args.
-+
-+ If there is a property "append-rootblock" in DT under /chosen
-+ and a root= option in bootloaders command line it will be parsed
-+ and added to DT bootargs with the form: <append-rootblock>XX.
-+
- endchoice
-
- config CMDLINE_OVERRIDE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -3,7 +3,8 @@
- #include <asm/setup.h>
- #include <libfdt.h>
-
--#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) || \
-+ defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
- #define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
-@@ -69,6 +70,83 @@ static uint32_t get_cell_size(const void
- return cell_size;
- }
-
-+/**
-+ * taken from arch/x86/boot/string.c
-+ * local_strstr - Find the first substring in a %NUL terminated string
-+ * @s1: The string to be searched
-+ * @s2: The string to search for
-+ */
-+static char *local_strstr(const char *s1, const char *s2)
-+{
-+ size_t l1, l2;
-+
-+ l2 = strlen(s2);
-+ if (!l2)
-+ return (char *)s1;
-+ l1 = strlen(s1);
-+ while (l1 >= l2) {
-+ l1--;
-+ if (!memcmp(s1, s2, l2))
-+ return (char *)s1;
-+ s1++;
-+ }
-+ return NULL;
-+}
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+ char *ptr, *end, *tmp;
-+ const char *root="root=";
-+ const char *find_rootblock;
-+ int i, l;
-+ const char *rootblock;
-+
-+ find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l);
-+ if (!find_rootblock)
-+ find_rootblock = root;
-+
-+ /* ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86 */
-+ ptr = local_strstr(str, find_rootblock);
-+ if (!ptr)
-+ return dest;
-+
-+ end = strchr(ptr, ' ');
-+ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+ /* Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too. */
-+ tmp = strchr(ptr, ',');
-+ if (tmp)
-+ end = end < tmp ? end : tmp - 1;
-+
-+ /*
-+ * find partition number
-+ * (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )
-+ */
-+ for (i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+
-+ ptr = end + 1;
-+
-+ /* if append-rootblock property is set use it to append to command line */
-+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+ if (rootblock != NULL) {
-+ if (*dest != ' ') {
-+ *dest = ' ';
-+ dest++;
-+ len++;
-+ }
-+
-+ if (len + l + i <= COMMAND_LINE_SIZE) {
-+ memcpy(dest, rootblock, l);
-+ dest += l - 1;
-+
-+ memcpy(dest, ptr, i);
-+ dest += i;
-+ }
-+ }
-+
-+ return dest;
-+}
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
- char cmdline[COMMAND_LINE_SIZE];
-@@ -86,13 +164,23 @@ static void merge_fdt_bootargs(void *fdt
- ptr += len - 1;
- }
-
-- /* and append the ATAG_CMDLINE */
- if (fdt_cmdline) {
-- len = strlen(fdt_cmdline);
-- if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
-- *ptr++ = ' ';
-- memcpy(ptr, fdt_cmdline, len);
-- ptr += len;
-+ if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)) {
-+ /*
-+ * save original bootloader args
-+ * and append ubi.mtd with root partition number
-+ * to current cmdline
-+ */
-+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+ } else {
-+ /* and append the ATAG_CMDLINE */
-+ len = strlen(fdt_cmdline);
-+ if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
-+ *ptr++ = ' ';
-+ memcpy(ptr, fdt_cmdline, len);
-+ ptr += len;
-+ }
- }
- }
- *ptr = '\0';
---- a/init/main.c
-+++ b/init/main.c
-@@ -28,6 +28,7 @@
- #include <linux/initrd.h>
- #include <linux/memblock.h>
- #include <linux/acpi.h>
-+#include <linux/of.h>
- #include <linux/bootconfig.h>
- #include <linux/console.h>
- #include <linux/nmi.h>
-@@ -995,6 +996,17 @@ asmlinkage __visible void __init __no_sa
- pr_notice("Kernel command line: %s\n", saved_command_line);
- /* parameters may set static keys */
- jump_label_init();
-+
-+ /* Show bootloader's original command line for reference */
-+ if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) && of_chosen) {
-+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+
-+ if(prop)
-+ pr_notice("Bootloader command line (ignored): %s\n", prop);
-+ else
-+ pr_notice("Bootloader command line not present\n");
-+ }
-+
- parse_early_param();
- after_dashes = parse_args("Booting kernel",
- static_command_line, __start___param,
+++ /dev/null
-From 9732c4f2d93a4a39ffc903c88ab7d531a8bb2e74 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 20 Mar 2024 00:47:58 +0100
-Subject: [PATCH] mtd: rawnand: qcom: Fix broken misc_cmd_type in exec_op
-
-misc_cmd_type in exec_op have multiple problems. With commit a82990c8a409
-("mtd: rawnand: qcom: Add read/read_start ops in exec_op path") it was
-reworked and generalized but actually dropped the handling of the
-RESET_DEVICE command.
-
-Also additional logic was added without clear explaination causing the
-erase command to be broken on testing it on a ipq806x nandc.
-
-Add some additional logic to restore RESET_DEVICE command handling and
-fix erase command.
-
-Fixes: a82990c8a409 ("mtd: rawnand: qcom: Add read/read_start ops in exec_op path")
-Cc: stable@vger.kernel.org
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/mtd/nand/raw/qcom_nandc.c | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
---- a/drivers/mtd/nand/raw/qcom_nandc.c
-+++ b/drivers/mtd/nand/raw/qcom_nandc.c
-@@ -2815,7 +2815,7 @@ static int qcom_misc_cmd_type_exec(struc
- host->cfg0_raw & ~(7 << CW_PER_PAGE));
- nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw);
- instrs = 3;
-- } else {
-+ } else if (q_op.cmd_reg != OP_RESET_DEVICE) {
- return 0;
- }
-
-@@ -2830,9 +2830,8 @@ static int qcom_misc_cmd_type_exec(struc
- nandc_set_reg(chip, NAND_EXEC_CMD, 1);
-
- write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL);
-- (q_op.cmd_reg == OP_BLOCK_ERASE) ? write_reg_dma(nandc, NAND_DEV0_CFG0,
-- 2, NAND_BAM_NEXT_SGL) : read_reg_dma(nandc,
-- NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
-+ if (q_op.cmd_reg == OP_BLOCK_ERASE)
-+ write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
-
- write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
- read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
#include <linux/bootconfig.h>
#include <linux/console.h>
#include <linux/nmi.h>
-@@ -930,6 +931,17 @@ void start_kernel(void)
+@@ -932,6 +933,17 @@ void start_kernel(void)
pr_notice("Kernel command line: %s\n", saved_command_line);
/* parameters may set static keys */
jump_label_init();
CPU_TYPE:=xscale
SUBTARGETS:=generic
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
define Target/Description
Build firmware images for the IXP4xx XScale CPU
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_AMD_PHY=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_IXP4XX=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_CPU_AUTO=y
-# CONFIG_ARCH_MULTI_V4 is not set
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_ENDIAN_BE32=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CPU_XSCALE=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_DEV_IXP4XX=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=m
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0xc8000003
-CONFIG_DEBUG_UART_VIRT=0xfec00003
-CONFIG_DMA_OPS=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-# CONFIG_FARSYNC is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FORCE_PCI=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GW_PLD=y
-CONFIG_GPIO_IXP4XX=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HDLC=y
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_IXP4XX=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_IOP3XX=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INTEL_IXP4XX_EB=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_IWMMXT is not set
-CONFIG_IXP4XX_ETH=y
-CONFIG_IXP4XX_HSS=y
-CONFIG_IXP4XX_IRQ=y
-CONFIG_IXP4XX_NPE=y
-CONFIG_IXP4XX_QMGR=y
-CONFIG_IXP4XX_TIMER=y
-CONFIG_IXP4XX_WATCHDOG=y
-CONFIG_JBD2=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_OTP=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_IXP4XX=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6060=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_VENDOR_XSCALE=y
-CONFIG_NLS=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-# CONFIG_OLD_SIGACTION is not set
-# CONFIG_OLD_SIGSUSPEND3 is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PATA_IXP4XX_CF=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_IXP4XX=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RUST_IS_AVAILABLE=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SERIAL_8250_EXAR is not set
-# CONFIG_SERIAL_8250_FSL is not set
-# CONFIG_SERIAL_8250_PCI is not set
-# CONFIG_SERIAL_8250_PERICOM is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SG_POOL=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
-CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PCI=y
-# CONFIG_USB_OHCI_HCD_PLATFORM is not set
-CONFIG_USB_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_UHCI_HCD=y
-CONFIG_USE_OF=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WAN=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_AMD_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_IXP4XX=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_CPU_AUTO=y
+# CONFIG_ARCH_MULTI_V4 is not set
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V4_V5=y
+CONFIG_ARCH_MULTI_V5=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_ENDIAN_BE32=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_DEV_IXP4XX=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=m
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+CONFIG_DEBUG_UART_8250=y
+CONFIG_DEBUG_UART_8250_SHIFT=2
+CONFIG_DEBUG_UART_PHYS=0xc8000003
+CONFIG_DEBUG_UART_VIRT=0xfec00003
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+# CONFIG_FARSYNC is not set
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FORCE_PCI=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GW_PLD=y
+CONFIG_GPIO_IXP4XX=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HDLC=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_IXP4XX=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_IOP3XX=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INTEL_IXP4XX_EB=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_IWMMXT is not set
+CONFIG_IXP4XX_ETH=y
+CONFIG_IXP4XX_HSS=y
+CONFIG_IXP4XX_IRQ=y
+CONFIG_IXP4XX_NPE=y
+CONFIG_IXP4XX_QMGR=y
+CONFIG_IXP4XX_TIMER=y
+CONFIG_IXP4XX_WATCHDOG=y
+CONFIG_JBD2=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_OTP=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_IXP4XX=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MV88E6060=y
+CONFIG_NET_DSA_TAG_TRAILER=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_VENDOR_XSCALE=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PATA_IXP4XX_CF=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_IXP4XX=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SG_POOL=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWPHY=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+# CONFIG_USB_OHCI_HCD_PLATFORM is not set
+CONFIG_USB_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WAN=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
define Device/Default
PROFILES := Default
+ DEVICE_DTS_DIR = $$(DTS_DIR)/intel/ixp
KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
KERNEL_NAME := zImage
KERNEL := kernel-bin | append-dtb
+++ /dev/null
-From fc58944733a2082e3290eda240eb3247a00ad73a Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Thu, 21 Sep 2023 00:12:42 +0200
-Subject: [PATCH] gpio: ixp4xx: Handle clock output on pin 14 and 15
-
-This makes it possible to provide basic clock output on pins
-14 and 15. The clocks are typically used by random electronics,
-not modeled in the device tree, so they just need to be provided
-on request.
-
-In order to not disturb old systems that require that the
-hardware defaults are kept in the clock setting bits, we only
-manipulate these if either device tree property is present.
-Once we know a device needs one of the clocks we can set it
-in the device tree.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/gpio/gpio-ixp4xx.c | 49 +++++++++++++++++++++++++++++++++++++-
- 1 file changed, 48 insertions(+), 1 deletion(-)
-
---- a/drivers/gpio/gpio-ixp4xx.c
-+++ b/drivers/gpio/gpio-ixp4xx.c
-@@ -38,6 +38,18 @@
- #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)
- #define IXP4XX_GPIO_STYLE_SIZE 3
-
-+/*
-+ * Clock output control register defines.
-+ */
-+#define IXP4XX_GPCLK_CLK0DC_SHIFT 0
-+#define IXP4XX_GPCLK_CLK0TC_SHIFT 4
-+#define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0)
-+#define IXP4XX_GPCLK_MUX14 BIT(8)
-+#define IXP4XX_GPCLK_CLK1DC_SHIFT 16
-+#define IXP4XX_GPCLK_CLK1TC_SHIFT 20
-+#define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16)
-+#define IXP4XX_GPCLK_MUX15 BIT(24)
-+
- /**
- * struct ixp4xx_gpio - IXP4 GPIO state container
- * @dev: containing device for this instance
-@@ -203,6 +215,8 @@ static int ixp4xx_gpio_probe(struct plat
- struct ixp4xx_gpio *g;
- struct gpio_irq_chip *girq;
- struct device_node *irq_parent;
-+ bool clk_14, clk_15;
-+ u32 val;
- int ret;
-
- g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
-@@ -233,7 +247,40 @@ static int ixp4xx_gpio_probe(struct plat
- */
- if (of_machine_is_compatible("dlink,dsm-g600-a") ||
- of_machine_is_compatible("iom,nas-100d"))
-- __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
-+ val = 0;
-+ else
-+ val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
-+
-+ /*
-+ * If either clock output is enabled explicitly in the device tree
-+ * we take full control of the clock by masking off all bits for
-+ * the clock control and selectively enabling them. Otherwise
-+ * we leave the hardware default settings.
-+ *
-+ * Enable clock outputs with default timings of requested clock.
-+ * If you need control over TC and DC, add these to the device
-+ * tree bindings and use them here.
-+ */
-+ clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");
-+ clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");
-+ if (clk_14 || clk_15) {
-+ val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);
-+ val &= ~IXP4XX_GPCLK_CLK0_MASK;
-+ val &= ~IXP4XX_GPCLK_CLK1_MASK;
-+ if (clk_14) {
-+ val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT);
-+ val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);
-+ val |= IXP4XX_GPCLK_MUX14;
-+ }
-+
-+ if (clk_15) {
-+ val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT);
-+ val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);
-+ val |= IXP4XX_GPCLK_MUX15;
-+ }
-+ }
-+
-+ __raw_writel(val, g->base + IXP4XX_REG_GPCLK);
-
- /*
- * This is a very special big-endian ARM issue: when the IXP4xx is
+++ /dev/null
-From 02693ffdb93bffcbe772bd91a399dabd123b8c19 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Tue, 19 Sep 2023 16:02:15 +0200
-Subject: [PATCH 4/4] ARM: dts: ixp4xx: Add USRobotics USR8200 device tree
-
-This is a USRobotics NAS/Firewall/router that has been supported
-by OpenWrt in the past. It had dedicated users so let's get it
-properly supported.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/dts/Makefile | 3 +-
- .../dts/intel-ixp42x-usrobotics-usr8200.dts | 229 ++++++++++++++++++
- 2 files changed, 231 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -292,7 +292,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
- intel-ixp43x-gateworks-gw2358.dtb \
- intel-ixp42x-netgear-wg302v1.dtb \
- intel-ixp42x-arcom-vulcan.dtb \
-- intel-ixp42x-gateway-7001.dtb
-+ intel-ixp42x-gateway-7001.dtb \
-+ intel-ixp42x-usrobotics-usr8200.dtb
- dtb-$(CONFIG_ARCH_KEYSTONE) += \
- keystone-k2hk-evm.dtb \
- keystone-k2l-evm.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-@@ -0,0 +1,229 @@
-+// SPDX-License-Identifier: ISC
-+/*
-+ * Device Tree file for the USRobotics USR8200 firewall
-+ * VPN and NAS. Based on know-how from Peter Denison.
-+ *
-+ * This machine is based on IXP422, the USR internal codename
-+ * is "Jeeves".
-+ */
-+
-+/dts-v1/;
-+
-+#include "intel-ixp42x.dtsi"
-+#include <dt-bindings/input/input.h>
-+
-+/ {
-+ model = "USRobotics USR8200";
-+ compatible = "usr,usr8200", "intel,ixp42x";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x00000000 0x4000000>;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200n8";
-+ stdout-path = "uart1:115200n8";
-+ };
-+
-+ aliases {
-+ /* These are switched around */
-+ serial0 = &uart1;
-+ serial1 = &uart0;
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ ieee1394_led: led-1394 {
-+ label = "usr8200:green:1394";
-+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ usb1_led: led-usb1 {
-+ label = "usr8200:green:usb1";
-+ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ usb2_led: led-usb2 {
-+ label = "usr8200:green:usb2";
-+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ wireless_led: led-wireless {
-+ /*
-+ * This LED is mounted inside the case but cannot be
-+ * seen from the outside: probably USR planned at one
-+ * point for the device to have a wireless card, then
-+ * changed their mind and didn't mount it, leaving the
-+ * LED in place.
-+ */
-+ label = "usr8200:green:wireless";
-+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ pwr_led: led-pwr {
-+ label = "usr8200:green:pwr";
-+ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
-+ default-state = "on";
-+ linux,default-trigger = "heartbeat";
-+ };
-+ };
-+
-+ gpio_keys {
-+ compatible = "gpio-keys";
-+
-+ button-reset {
-+ wakeup-source;
-+ linux,code = <KEY_RESTART>;
-+ label = "reset";
-+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+
-+ soc {
-+ bus@c4000000 {
-+ flash@0,0 {
-+ compatible = "intel,ixp4xx-flash", "cfi-flash";
-+ bank-width = <2>;
-+ /* Enable writes on the expansion bus */
-+ intel,ixp4xx-eb-write-enable = <1>;
-+ /* 16 MB of Flash mapped in at CS0 */
-+ reg = <0 0x00000000 0x1000000>;
-+
-+ partitions {
-+ compatible = "redboot-fis";
-+ /* Eraseblock at 0x0fe0000 */
-+ fis-index-block = <0x7f>;
-+ };
-+ };
-+ rtc@2,0 {
-+ /* EPSON RTC7301 DG DIL-capsule */
-+ compatible = "epson,rtc7301dg";
-+ /*
-+ * These timing settings were found in the boardfile patch:
-+ * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
-+ * IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
-+ */
-+ intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
-+ intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
-+ intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
-+ intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
-+ intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
-+ intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
-+ intel,ixp4xx-eb-byte-access-on-halfword = <0>;
-+ intel,ixp4xx-eb-mux-address-and-data = <0>;
-+ intel,ixp4xx-eb-ahb-split-transfers = <0>;
-+ intel,ixp4xx-eb-write-enable = <1>;
-+ intel,ixp4xx-eb-byte-access = <1>;
-+ /* 512 bytes at CS2 */
-+ reg = <2 0x00000000 0x0000200>;
-+ reg-io-width = <1>;
-+ native-endian;
-+ /* FIXME: try to check if there is an IRQ for the RTC? */
-+ };
-+ };
-+
-+ pci@c0000000 {
-+ status = "okay";
-+
-+ /*
-+ * Taken from USR8200 boardfile from OpenWrt
-+ *
-+ * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
-+ * We assume the same IRQ for all pins on the remaining slots, that
-+ * is what the boardfile was doing.
-+ */
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0xf800 0 0 7>;
-+ interrupt-map =
-+ /* IDSEL 14 used for "Wireless" in the board file */
-+ <0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
-+ /* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
-+ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
-+ /* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
-+ <0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
-+ <0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
-+ <0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
-+ };
-+
-+ gpio@c8004000 {
-+ /* Enable clock out on GPIO 15 */
-+ intel,ixp4xx-gpio15-clkout;
-+ };
-+
-+ /* EthB WAN */
-+ ethernet@c8009000 {
-+ status = "okay";
-+ queue-rx = <&qmgr 3>;
-+ queue-txready = <&qmgr 20>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy9>;
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ phy9: ethernet-phy@9 {
-+ reg = <9>;
-+ };
-+
-+ /* The switch uses MDIO addresses 16 thru 31 */
-+ switch@16 {
-+ compatible = "marvell,mv88e6060";
-+ reg = <16>;
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ port@0 {
-+ reg = <0>;
-+ label = "lan1";
-+ };
-+
-+ port@1 {
-+ reg = <1>;
-+ label = "lan2";
-+ };
-+
-+ port@2 {
-+ reg = <2>;
-+ label = "lan3";
-+ };
-+
-+ port@3 {
-+ reg = <3>;
-+ label = "lan4";
-+ };
-+
-+ port@5 {
-+ /* Port 5 is the CPU port according to the MV88E6060 datasheet */
-+ reg = <5>;
-+ phy-mode = "rgmii-id";
-+ ethernet = <ðc>;
-+ label = "cpu";
-+ fixed-link {
-+ speed = <100>;
-+ full-duplex;
-+ };
-+ };
-+ };
-+ };
-+ };
-+ };
-+
-+ /* EthC LAN connected to the Marvell DSA Switch */
-+ ethc: ethernet@c800a000 {
-+ status = "okay";
-+ queue-rx = <&qmgr 4>;
-+ queue-txready = <&qmgr 21>;
-+ phy-mode = "rgmii";
-+ fixed-link {
-+ speed = <100>;
-+ full-duplex;
-+ };
-+ };
-+ };
-+};
+++ /dev/null
-From 6599df775e2cbb4988bdf8239acf4fbec70e5ef9 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sat, 23 Sep 2023 20:38:22 +0200
-Subject: [PATCH 3/4] net: ixp4xx_eth: Support changing the MTU
-
-As we don't specify the MTU in the driver, the framework
-will fall back to 1500 bytes and this doesn't work very
-well when we try to attach a DSA switch:
-
- eth1: mtu greater than device maximum
- ixp4xx_eth c800a000.ethernet eth1: error -22 setting
- MTU to 1504 to include DSA overhead
-
-After locating an out-of-tree patch in OpenWrt I found
-suitable code to set the MTU on the interface and ported
-it and updated it. Now the MTU gets set properly.
-
-Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/net/ethernet/xscale/ixp4xx_eth.c | 65 +++++++++++++++++++++++-
- 1 file changed, 64 insertions(+), 1 deletion(-)
-
---- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
-+++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
-@@ -24,6 +24,7 @@
- #include <linux/dma-mapping.h>
- #include <linux/dmapool.h>
- #include <linux/etherdevice.h>
-+#include <linux/if_vlan.h>
- #include <linux/io.h>
- #include <linux/kernel.h>
- #include <linux/net_tstamp.h>
-@@ -63,7 +64,15 @@
-
- #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
- #define REGS_SIZE 0x1000
--#define MAX_MRU 1536 /* 0x600 */
-+
-+/* MRU is said to be 14320 in a code dump, the SW manual says that
-+ * MRU/MTU is 16320 and includes VLAN and ethernet headers.
-+ * See "IXP400 Software Programmer's Guide" section 10.3.2, page 161.
-+ *
-+ * FIXME: we have chosen the safe default (14320) but if you can test
-+ * jumboframes, experiment with 16320 and see what happens!
-+ */
-+#define MAX_MRU (14320 - VLAN_ETH_HLEN)
- #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
-
- #define NAPI_WEIGHT 16
-@@ -1182,6 +1191,54 @@ static void destroy_queues(struct port *
- }
- }
-
-+static int ixp4xx_do_change_mtu(struct net_device *dev, int new_mtu)
-+{
-+ struct port *port = netdev_priv(dev);
-+ struct npe *npe = port->npe;
-+ int framesize, chunks;
-+ struct msg msg = {};
-+
-+ /* adjust for ethernet headers */
-+ framesize = new_mtu + VLAN_ETH_HLEN;
-+ /* max rx/tx 64 byte chunks */
-+ chunks = DIV_ROUND_UP(framesize, 64);
-+
-+ msg.cmd = NPE_SETMAXFRAMELENGTHS;
-+ msg.eth_id = port->id;
-+
-+ /* Firmware wants to know buffer size in 64 byte chunks */
-+ msg.byte2 = chunks << 8;
-+ msg.byte3 = chunks << 8;
-+
-+ msg.byte4 = msg.byte6 = framesize >> 8;
-+ msg.byte5 = msg.byte7 = framesize & 0xff;
-+
-+ if (npe_send_recv_message(npe, &msg, "ETH_SET_MAX_FRAME_LENGTH"))
-+ return -EIO;
-+ netdev_dbg(dev, "set MTU on NPE %s to %d bytes\n",
-+ npe_name(npe), new_mtu);
-+
-+ return 0;
-+}
-+
-+static int ixp4xx_eth_change_mtu(struct net_device *dev, int new_mtu)
-+{
-+ int ret;
-+
-+ /* MTU can only be changed when the interface is up. We also
-+ * set the MTU from dev->mtu when opening the device.
-+ */
-+ if (dev->flags & IFF_UP) {
-+ ret = ixp4xx_do_change_mtu(dev, new_mtu);
-+ if (ret < 0)
-+ return ret;
-+ }
-+
-+ dev->mtu = new_mtu;
-+
-+ return 0;
-+}
-+
- static int eth_open(struct net_device *dev)
- {
- struct port *port = netdev_priv(dev);
-@@ -1232,6 +1289,8 @@ static int eth_open(struct net_device *d
- if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
- return -EIO;
-
-+ ixp4xx_do_change_mtu(dev, dev->mtu);
-+
- if ((err = request_queues(port)) != 0)
- return err;
-
-@@ -1374,6 +1433,7 @@ static int eth_close(struct net_device *
- static const struct net_device_ops ixp4xx_netdev_ops = {
- .ndo_open = eth_open,
- .ndo_stop = eth_close,
-+ .ndo_change_mtu = ixp4xx_eth_change_mtu,
- .ndo_start_xmit = eth_xmit,
- .ndo_set_rx_mode = eth_set_mcast_list,
- .ndo_eth_ioctl = eth_ioctl,
-@@ -1488,6 +1548,9 @@ static int ixp4xx_eth_probe(struct platf
- ndev->dev.dma_mask = dev->dma_mask;
- ndev->dev.coherent_dma_mask = dev->coherent_dma_mask;
-
-+ ndev->min_mtu = ETH_MIN_MTU;
-+ ndev->max_mtu = MAX_MRU;
-+
- netif_napi_add_weight(ndev, &port->napi, eth_poll, NAPI_WEIGHT);
-
- if (!(port->npe = npe_request(NPE_ID(port->id))))
+++ /dev/null
-From a1ab45966e5a21841af58742adf27725e523d303 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sat, 14 Oct 2023 19:53:24 +0200
-Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
-
-The MV88E6060 switch has internal PHY registers at MDIO
-addresses 0x00..0x04. Tie each port to the corresponding
-PHY.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- .../dts/intel-ixp42x-usrobotics-usr8200.dts | 22 +++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-+++ b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-@@ -165,6 +165,24 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-+ /*
-+ * PHY 0..4 are internal to the MV88E6060 switch but appear
-+ * as independent devices.
-+ */
-+ phy0: ethernet-phy@0 {
-+ reg = <0>;
-+ };
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ phy2: ethernet-phy@2 {
-+ reg = <2>;
-+ };
-+ phy3: ethernet-phy@3 {
-+ reg = <3>;
-+ };
-+
-+ /* Altima AMI101L used by the WAN port */
- phy9: ethernet-phy@9 {
- reg = <9>;
- };
-@@ -181,21 +199,25 @@
- port@0 {
- reg = <0>;
- label = "lan1";
-+ phy-handle = <&phy0>;
- };
-
- port@1 {
- reg = <1>;
- label = "lan2";
-+ phy-handle = <&phy1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
-+ phy-handle = <&phy2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan4";
-+ phy-handle = <&phy3>;
- };
-
- port@5 {
+++ /dev/null
-From 2792791a19f90b0141ed2e781599ba0a42a8cfd5 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 29 May 2023 23:32:44 +0200
-Subject: [PATCH] ARM: dts: ixp4xx: Boot NSLU2 from harddrive
-
-This enforces harddrive boot on the NSLU2. The flash is too small
-to hold any rootfs these days.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
-+++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
-@@ -21,7 +21,7 @@
- };
-
- chosen {
-- bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
-+ bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
- stdout-path = "uart0:115200n8";
- };
-
--- /dev/null
+From fc58944733a2082e3290eda240eb3247a00ad73a Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 21 Sep 2023 00:12:42 +0200
+Subject: [PATCH] gpio: ixp4xx: Handle clock output on pin 14 and 15
+
+This makes it possible to provide basic clock output on pins
+14 and 15. The clocks are typically used by random electronics,
+not modeled in the device tree, so they just need to be provided
+on request.
+
+In order to not disturb old systems that require that the
+hardware defaults are kept in the clock setting bits, we only
+manipulate these if either device tree property is present.
+Once we know a device needs one of the clocks we can set it
+in the device tree.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/gpio/gpio-ixp4xx.c | 49 +++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 48 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpio/gpio-ixp4xx.c
++++ b/drivers/gpio/gpio-ixp4xx.c
+@@ -38,6 +38,18 @@
+ #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)
+ #define IXP4XX_GPIO_STYLE_SIZE 3
+
++/*
++ * Clock output control register defines.
++ */
++#define IXP4XX_GPCLK_CLK0DC_SHIFT 0
++#define IXP4XX_GPCLK_CLK0TC_SHIFT 4
++#define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0)
++#define IXP4XX_GPCLK_MUX14 BIT(8)
++#define IXP4XX_GPCLK_CLK1DC_SHIFT 16
++#define IXP4XX_GPCLK_CLK1TC_SHIFT 20
++#define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16)
++#define IXP4XX_GPCLK_MUX15 BIT(24)
++
+ /**
+ * struct ixp4xx_gpio - IXP4 GPIO state container
+ * @dev: containing device for this instance
+@@ -202,6 +214,8 @@ static int ixp4xx_gpio_probe(struct plat
+ struct ixp4xx_gpio *g;
+ struct gpio_irq_chip *girq;
+ struct device_node *irq_parent;
++ bool clk_14, clk_15;
++ u32 val;
+ int ret;
+
+ g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
+@@ -231,7 +245,40 @@ static int ixp4xx_gpio_probe(struct plat
+ */
+ if (of_machine_is_compatible("dlink,dsm-g600-a") ||
+ of_machine_is_compatible("iom,nas-100d"))
+- __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
++ val = 0;
++ else
++ val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
++
++ /*
++ * If either clock output is enabled explicitly in the device tree
++ * we take full control of the clock by masking off all bits for
++ * the clock control and selectively enabling them. Otherwise
++ * we leave the hardware default settings.
++ *
++ * Enable clock outputs with default timings of requested clock.
++ * If you need control over TC and DC, add these to the device
++ * tree bindings and use them here.
++ */
++ clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");
++ clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");
++ if (clk_14 || clk_15) {
++ val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);
++ val &= ~IXP4XX_GPCLK_CLK0_MASK;
++ val &= ~IXP4XX_GPCLK_CLK1_MASK;
++ if (clk_14) {
++ val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT);
++ val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);
++ val |= IXP4XX_GPCLK_MUX14;
++ }
++
++ if (clk_15) {
++ val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT);
++ val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);
++ val |= IXP4XX_GPCLK_MUX15;
++ }
++ }
++
++ __raw_writel(val, g->base + IXP4XX_REG_GPCLK);
+
+ /*
+ * This is a very special big-endian ARM issue: when the IXP4xx is
--- /dev/null
+From 6599df775e2cbb4988bdf8239acf4fbec70e5ef9 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 23 Sep 2023 20:38:22 +0200
+Subject: [PATCH 3/4] net: ixp4xx_eth: Support changing the MTU
+
+As we don't specify the MTU in the driver, the framework
+will fall back to 1500 bytes and this doesn't work very
+well when we try to attach a DSA switch:
+
+ eth1: mtu greater than device maximum
+ ixp4xx_eth c800a000.ethernet eth1: error -22 setting
+ MTU to 1504 to include DSA overhead
+
+After locating an out-of-tree patch in OpenWrt I found
+suitable code to set the MTU on the interface and ported
+it and updated it. Now the MTU gets set properly.
+
+Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/xscale/ixp4xx_eth.c | 65 +++++++++++++++++++++++-
+ 1 file changed, 64 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
+@@ -24,6 +24,7 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/dmapool.h>
+ #include <linux/etherdevice.h>
++#include <linux/if_vlan.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+ #include <linux/net_tstamp.h>
+@@ -63,7 +64,15 @@
+
+ #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
+ #define REGS_SIZE 0x1000
+-#define MAX_MRU 1536 /* 0x600 */
++
++/* MRU is said to be 14320 in a code dump, the SW manual says that
++ * MRU/MTU is 16320 and includes VLAN and ethernet headers.
++ * See "IXP400 Software Programmer's Guide" section 10.3.2, page 161.
++ *
++ * FIXME: we have chosen the safe default (14320) but if you can test
++ * jumboframes, experiment with 16320 and see what happens!
++ */
++#define MAX_MRU (14320 - VLAN_ETH_HLEN)
+ #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
+
+ #define NAPI_WEIGHT 16
+@@ -1182,6 +1191,54 @@ static void destroy_queues(struct port *
+ }
+ }
+
++static int ixp4xx_do_change_mtu(struct net_device *dev, int new_mtu)
++{
++ struct port *port = netdev_priv(dev);
++ struct npe *npe = port->npe;
++ int framesize, chunks;
++ struct msg msg = {};
++
++ /* adjust for ethernet headers */
++ framesize = new_mtu + VLAN_ETH_HLEN;
++ /* max rx/tx 64 byte chunks */
++ chunks = DIV_ROUND_UP(framesize, 64);
++
++ msg.cmd = NPE_SETMAXFRAMELENGTHS;
++ msg.eth_id = port->id;
++
++ /* Firmware wants to know buffer size in 64 byte chunks */
++ msg.byte2 = chunks << 8;
++ msg.byte3 = chunks << 8;
++
++ msg.byte4 = msg.byte6 = framesize >> 8;
++ msg.byte5 = msg.byte7 = framesize & 0xff;
++
++ if (npe_send_recv_message(npe, &msg, "ETH_SET_MAX_FRAME_LENGTH"))
++ return -EIO;
++ netdev_dbg(dev, "set MTU on NPE %s to %d bytes\n",
++ npe_name(npe), new_mtu);
++
++ return 0;
++}
++
++static int ixp4xx_eth_change_mtu(struct net_device *dev, int new_mtu)
++{
++ int ret;
++
++ /* MTU can only be changed when the interface is up. We also
++ * set the MTU from dev->mtu when opening the device.
++ */
++ if (dev->flags & IFF_UP) {
++ ret = ixp4xx_do_change_mtu(dev, new_mtu);
++ if (ret < 0)
++ return ret;
++ }
++
++ dev->mtu = new_mtu;
++
++ return 0;
++}
++
+ static int eth_open(struct net_device *dev)
+ {
+ struct port *port = netdev_priv(dev);
+@@ -1232,6 +1289,8 @@ static int eth_open(struct net_device *d
+ if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
+ return -EIO;
+
++ ixp4xx_do_change_mtu(dev, dev->mtu);
++
+ if ((err = request_queues(port)) != 0)
+ return err;
+
+@@ -1374,6 +1433,7 @@ static int eth_close(struct net_device *
+ static const struct net_device_ops ixp4xx_netdev_ops = {
+ .ndo_open = eth_open,
+ .ndo_stop = eth_close,
++ .ndo_change_mtu = ixp4xx_eth_change_mtu,
+ .ndo_start_xmit = eth_xmit,
+ .ndo_set_rx_mode = eth_set_mcast_list,
+ .ndo_eth_ioctl = eth_ioctl,
+@@ -1488,6 +1548,9 @@ static int ixp4xx_eth_probe(struct platf
+ ndev->dev.dma_mask = dev->dma_mask;
+ ndev->dev.coherent_dma_mask = dev->coherent_dma_mask;
+
++ ndev->min_mtu = ETH_MIN_MTU;
++ ndev->max_mtu = MAX_MRU;
++
+ netif_napi_add_weight(ndev, &port->napi, eth_poll, NAPI_WEIGHT);
+
+ if (!(port->npe = npe_request(NPE_ID(port->id))))
--- /dev/null
+From a1490c1e8a12a8286c6a34c3d277a519066fc51e Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 7 Oct 2023 14:32:40 +0200
+Subject: [PATCH] ARM: dts: ixp4xx: Add USRobotics USR8200 device tree
+
+This is a USRobotics NAS/Firewall/router that has been supported
+by OpenWrt in the past. It had dedicated users so let's get it
+properly supported.
+
+Some debugging and fixing was provided by Howard Harte.
+
+Link: https://lore.kernel.org/r/20231007-ixp4xx-usr8200-v1-1-aded3d6ff6f1@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/Makefile | 3 +-
+ .../ixp/intel-ixp42x-usrobotics-usr8200.dts | 229 ++++++++++++++++++
+ 2 files changed, 231 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+
+--- a/arch/arm/boot/dts/intel/ixp/Makefile
++++ b/arch/arm/boot/dts/intel/ixp/Makefile
+@@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
+ intel-ixp43x-gateworks-gw2358.dtb \
+ intel-ixp42x-netgear-wg302v1.dtb \
+ intel-ixp42x-arcom-vulcan.dtb \
+- intel-ixp42x-gateway-7001.dtb
++ intel-ixp42x-gateway-7001.dtb \
++ intel-ixp42x-usrobotics-usr8200.dtb
+--- /dev/null
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+@@ -0,0 +1,229 @@
++// SPDX-License-Identifier: ISC
++/*
++ * Device Tree file for the USRobotics USR8200 firewall
++ * VPN and NAS. Based on know-how from Peter Denison.
++ *
++ * This machine is based on IXP422, the USR internal codename
++ * is "Jeeves".
++ */
++
++/dts-v1/;
++
++#include "intel-ixp42x.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "USRobotics USR8200";
++ compatible = "usr,usr8200", "intel,ixp42x";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x00000000 0x4000000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,115200n8";
++ stdout-path = "uart1:115200n8";
++ };
++
++ aliases {
++ /* These are switched around */
++ serial0 = &uart1;
++ serial1 = &uart0;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ ieee1394_led: led-1394 {
++ label = "usr8200:green:1394";
++ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ usb1_led: led-usb1 {
++ label = "usr8200:green:usb1";
++ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ usb2_led: led-usb2 {
++ label = "usr8200:green:usb2";
++ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ wireless_led: led-wireless {
++ /*
++ * This LED is mounted inside the case but cannot be
++ * seen from the outside: probably USR planned at one
++ * point for the device to have a wireless card, then
++ * changed their mind and didn't mount it, leaving the
++ * LED in place.
++ */
++ label = "usr8200:green:wireless";
++ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ pwr_led: led-pwr {
++ label = "usr8200:green:pwr";
++ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ gpio_keys {
++ compatible = "gpio-keys";
++
++ button-reset {
++ wakeup-source;
++ linux,code = <KEY_RESTART>;
++ label = "reset";
++ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ soc {
++ bus@c4000000 {
++ flash@0,0 {
++ compatible = "intel,ixp4xx-flash", "cfi-flash";
++ bank-width = <2>;
++ /* Enable writes on the expansion bus */
++ intel,ixp4xx-eb-write-enable = <1>;
++ /* 16 MB of Flash mapped in at CS0 */
++ reg = <0 0x00000000 0x1000000>;
++
++ partitions {
++ compatible = "redboot-fis";
++ /* Eraseblock at 0x0fe0000 */
++ fis-index-block = <0x7f>;
++ };
++ };
++ rtc@2,0 {
++ /* EPSON RTC7301 DG DIL-capsule */
++ compatible = "epson,rtc7301dg";
++ /*
++ * These timing settings were found in the boardfile patch:
++ * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
++ * IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
++ */
++ intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
++ intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
++ intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
++ intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
++ intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
++ intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
++ intel,ixp4xx-eb-byte-access-on-halfword = <0>;
++ intel,ixp4xx-eb-mux-address-and-data = <0>;
++ intel,ixp4xx-eb-ahb-split-transfers = <0>;
++ intel,ixp4xx-eb-write-enable = <1>;
++ intel,ixp4xx-eb-byte-access = <1>;
++ /* 512 bytes at CS2 */
++ reg = <2 0x00000000 0x0000200>;
++ reg-io-width = <1>;
++ native-endian;
++ /* FIXME: try to check if there is an IRQ for the RTC? */
++ };
++ };
++
++ pci@c0000000 {
++ status = "okay";
++
++ /*
++ * Taken from USR8200 boardfile from OpenWrt
++ *
++ * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
++ * We assume the same IRQ for all pins on the remaining slots, that
++ * is what the boardfile was doing.
++ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
++ interrupt-map =
++ /* IDSEL 14 used for "Wireless" in the board file */
++ <0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
++ /* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
++ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
++ /* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
++ <0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
++ <0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
++ <0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
++ };
++
++ gpio@c8004000 {
++ /* Enable clock out on GPIO 15 */
++ intel,ixp4xx-gpio15-clkout;
++ };
++
++ /* EthB WAN */
++ ethernet@c8009000 {
++ status = "okay";
++ queue-rx = <&qmgr 3>;
++ queue-txready = <&qmgr 20>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy9>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy9: ethernet-phy@9 {
++ reg = <9>;
++ };
++
++ /* The switch uses MDIO addresses 16 thru 31 */
++ switch@16 {
++ compatible = "marvell,mv88e6060";
++ reg = <16>;
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@5 {
++ /* Port 5 is the CPU port according to the MV88E6060 datasheet */
++ reg = <5>;
++ phy-mode = "rgmii-id";
++ ethernet = <ðc>;
++ label = "cpu";
++ fixed-link {
++ speed = <100>;
++ full-duplex;
++ };
++ };
++ };
++ };
++ };
++ };
++
++ /* EthC LAN connected to the Marvell DSA Switch */
++ ethc: ethernet@c800a000 {
++ status = "okay";
++ queue-rx = <&qmgr 4>;
++ queue-txready = <&qmgr 21>;
++ phy-mode = "rgmii";
++ fixed-link {
++ speed = <100>;
++ full-duplex;
++ };
++ };
++ };
++};
--- /dev/null
+From 98f3b5f44b9ae86c4a80185b57149867472a2570 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 20 Oct 2023 15:11:41 +0200
+Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
+
+The MV88E6060 switch has internal PHY registers at MDIO
+addresses 0x00..0x04. Tie each port to the corresponding
+PHY.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+---
+ .../ixp/intel-ixp42x-usrobotics-usr8200.dts | 22 +++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+@@ -165,6 +165,24 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
++ /*
++ * PHY 0..4 are internal to the MV88E6060 switch but appear
++ * as independent devices.
++ */
++ phy0: ethernet-phy@0 {
++ reg = <0>;
++ };
++ phy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++ phy2: ethernet-phy@2 {
++ reg = <2>;
++ };
++ phy3: ethernet-phy@3 {
++ reg = <3>;
++ };
++
++ /* Altima AMI101L used by the WAN port */
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+@@ -181,21 +199,25 @@
+ port@0 {
+ reg = <0>;
+ label = "lan1";
++ phy-handle = <&phy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
++ phy-handle = <&phy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
++ phy-handle = <&phy2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
++ phy-handle = <&phy3>;
+ };
+
+ port@5 {
--- /dev/null
+From 89eccb6726d93c9c78997e91bd641b0e46bc3c5f Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 8 Sep 2023 12:49:48 +0200
+Subject: [PATCH] ARM: dts: ixp4xx-nslu2: Enable write on flash
+
+To upgrade the firmware and similar, the flash needs write
+access.
+
+Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-1-98d36264ed6d@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
+@@ -101,6 +101,8 @@
+ flash@0,0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
++ /* Enable writes on the expansion bus */
++ intel,ixp4xx-eb-write-enable = <1>;
+ /*
+ * 8 MB of Flash in 0x20000 byte blocks
+ * mapped in at CS0.
--- /dev/null
+From deb93908958e74dffbef1ce6a1cc2f82ac4f96ed Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 8 Sep 2023 12:49:49 +0200
+Subject: [PATCH] ARM: dts: ixp4xx: Use right restart keycode
+
+The "reset" key on a few IXP4xx routers were sending KEY_ESC
+but what we want to send is KEY_RESTART which will make
+OpenWrt and similar userspace do a controlled reboot.
+
+Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-2-98d36264ed6d@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts | 2 +-
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts | 2 +-
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts | 2 +-
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
+@@ -57,7 +57,7 @@
+
+ button-reset {
+ wakeup-source;
+- linux,code = <KEY_ESC>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ };
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
+@@ -44,7 +44,7 @@
+ };
+ button-reset {
+ wakeup-source;
+- linux,code = <KEY_ESC>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
+ };
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
+@@ -63,7 +63,7 @@
+ };
+ button-reset {
+ wakeup-source;
+- linux,code = <KEY_ESC>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ };
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
+@@ -65,7 +65,7 @@
+ };
+ button-reset {
+ wakeup-source;
+- linux,code = <KEY_ESC>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ };
--- /dev/null
+From 6484f966af53447deefcd4b805c201d8624981cb Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 29 May 2023 23:32:44 +0200
+Subject: [PATCH] ARM: dts: ixp4xx: Boot NSLU2 from harddrive
+
+This enforces harddrive boot on the NSLU2. The flash is too small
+to hold any rootfs these days.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
+@@ -21,7 +21,7 @@
+ };
+
+ chosen {
+- bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
++ bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
+ stdout-path = "uart0:115200n8";
+ };
+
+++ /dev/null
-From b3f1a164c7f742503dc7159011f7ad6b092b660e Mon Sep 17 00:00:00 2001
-From: Greg Ungerer <gerg@kernel.org>
-Date: Fri, 24 Nov 2023 14:15:28 +1000
-Subject: [PATCH] net: dsa: mv88e6xxx: fix marvell 6350 switch probing
-
-As of commit de5c9bf40c45 ("net: phylink: require supported_interfaces to
-be filled") Marvell 88e6350 switches fail to be probed:
-
- ...
- mv88e6085 d0072004.mdio-mii:11: switch 0x3710 detected: Marvell 88E6350, revision 2
- mv88e6085 d0072004.mdio-mii:11: phylink: error: empty supported_interfaces
- error creating PHYLINK: -22
- mv88e6085: probe of d0072004.mdio-mii:11 failed with error -22
- ...
-
-The problem stems from the use of mv88e6185_phylink_get_caps() to get
-the device capabilities. Create a new dedicated phylink_get_caps for the
-6351 family (which the 6350 is one of) to properly support their set of
-capabilities.
-
-According to chip.h the 6351 switch family includes the 6171, 6175, 6350
-and 6351 switches, so update each of these to use the correct
-phylink_get_caps.
-
-Fixes: de5c9bf40c45 ("net: phylink: require supported_interfaces to be filled")
-Signed-off-by: Greg Ungerer <gerg@kernel.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mv88e6xxx/chip.c | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
---- a/drivers/net/dsa/mv88e6xxx/chip.c
-+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -652,6 +652,18 @@ static void mv88e6250_phylink_get_caps(s
- config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
- }
-
-+static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
-+ struct phylink_config *config)
-+{
-+ unsigned long *supported = config->supported_interfaces;
-+
-+ /* Translate the default cmode */
-+ mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
-+
-+ config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
-+ MAC_1000FD;
-+}
-+
- static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
- {
- u16 reg, val;
-@@ -4498,7 +4510,7 @@ static const struct mv88e6xxx_ops mv88e6
- .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- .stu_getnext = mv88e6352_g1_stu_getnext,
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6172_ops = {
-@@ -4599,7 +4611,7 @@ static const struct mv88e6xxx_ops mv88e6
- .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- .stu_getnext = mv88e6352_g1_stu_getnext,
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6176_ops = {
-@@ -5256,7 +5268,7 @@ static const struct mv88e6xxx_ops mv88e6
- .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- .stu_getnext = mv88e6352_g1_stu_getnext,
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6351_ops = {
-@@ -5302,7 +5314,7 @@ static const struct mv88e6xxx_ops mv88e6
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
- .avb_ops = &mv88e6352_avb_ops,
- .ptp_ops = &mv88e6352_ptp_ops,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6352_ops = {
SUBTARGETS:=xrx200 xway xway_legacy falcon ase
KERNEL_PATCHVER:=5.15
+KERNEL_TESTING_PATCHVER:=6.1
define Target/Description
Build firmware images for Lantiq SoC
# CONFIG_CPU_MIPS32_R2 is not set
CONFIG_CPU_MIPSR1=y
CONFIG_CRC16=y
-CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_NLS=y
CONFIG_SGL_ALLOC=y
CONFIG_SOC_AMAZON_SE=y
-CONFIG_SOC_TYPE_XWAY=y
+# CONFIG_SOC_XWAY is not set
CONFIG_SWCONFIG=y
CONFIG_TARGET_ISA_REV=1
CONFIG_USB=y
--- /dev/null
+CONFIG_ADM6996_PHY=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+CONFIG_CPU_MIPSR1=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_HW_RANDOM=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+CONFIG_NLS=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SOC_AMAZON_SE=y
+# CONFIG_SOC_XWAY is not set
+CONFIG_SWCONFIG=y
+CONFIG_TARGET_ISA_REV=1
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
-CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
-CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
-CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_MEMREMAP_PROT=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_LOAD_STORE_LR=y
+CONFIG_CPU_HAS_DIEI=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_RIXI=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_CPU_MIPS32_R1 is not set
CONFIG_CPU_MIPS32_R2=y
CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
CONFIG_CPU_R4K_CACHE_TLB=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CSRC_R4K=y
CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
CONFIG_DTC=y
# CONFIG_DT_EASY50712 is not set
CONFIG_EARLY_PRINTK=y
-CONFIG_EFI_EARLYCON=y
CONFIG_FIXED_PHY=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
CONFIG_GPIO_MM_LANTIQ=y
CONFIG_GPIO_STP_XWAY=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_ARCH_COMPILER_H=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_ASM_MODVERSIONS=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_COPY_THREAD_TLS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FAST_GUP=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_VDSO=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IOREMAP_PROT=y
-CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_KVM=y
-CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PCI=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HZ_PERIODIC=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MIPS_CPU=y
CONFIG_IRQ_WORK=y
CONFIG_MIPS=y
CONFIG_MIPS_ASID_BITS=8
CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CBPF_JIT=y
CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_MIPS_CMDLINE_FROM_DTB=y
-# CONFIG_MIPS_ELF_APPENDED_DTB is not set
+CONFIG_MIPS_EBPF_JIT=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_LD_CAN_LINK_VDSO=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_NO_APPENDED_DTB is not set
CONFIG_MIPS_RAW_APPENDED_DTB=y
CONFIG_MIPS_SPRAM=y
-# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_SELFTESTS=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
-CONFIG_OF_NET=y
-# CONFIG_PCIE_LANTIQ is not set
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PINCTRL_XWAY=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_RESET_CONTROLLER=y
CONFIG_SERIAL_LANTIQ_CONSOLE=y
# CONFIG_SOC_AMAZON_SE is not set
# CONFIG_SOC_FALCON is not set
-# CONFIG_SOC_XWAY is not set
+CONFIG_SOC_TYPE_XWAY=y
+CONFIG_SOC_XWAY=y
CONFIG_SPI=y
CONFIG_SPI_LANTIQ_SSC=y
CONFIG_SPI_MASTER=y
--- /dev/null
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+# CONFIG_DT_EASY50712 is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_MM_LANTIQ=y
+CONFIG_GPIO_STP_XWAY=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LANTIQ=y
+CONFIG_LANTIQ_DT_NONE=y
+# CONFIG_LANTIQ_ETOP is not set
+CONFIG_LANTIQ_WDT=y
+# CONFIG_LANTIQ_XRX200 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_LD_CAN_LINK_VDSO=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_LANTIQ=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
+CONFIG_MTD_SPLIT_EVA_FW=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHY_LANTIQ_RCU_USB2=y
+# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_LANTIQ=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL_XWAY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_LANTIQ=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_LANTIQ=y
+CONFIG_SERIAL_LANTIQ_CONSOLE=y
+# CONFIG_SOC_AMAZON_SE is not set
+# CONFIG_SOC_FALCON is not set
+CONFIG_SOC_TYPE_XWAY=y
+CONFIG_SOC_XWAY=y
+CONFIG_SPI=y
+CONFIG_SPI_LANTIQ_SSC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SRCU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_VPE_LOADER=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
-CONFIG_CPU_HAS_DIEI=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
CONFIG_PINCTRL_FALCON=y
CONFIG_SOC_FALCON=y
+# CONFIG_SOC_XWAY is not set
CONFIG_SPI_FALCON=y
--- /dev/null
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
+CONFIG_PINCTRL_FALCON=y
+CONFIG_SOC_FALCON=y
+# CONFIG_SOC_XWAY is not set
+CONFIG_SPI_FALCON=y
compatible = "lantiq,mei-xway";
reg = <0xe116000 0x400>;
interrupt-parent = <&icu0>;
- interrupts = <81>;
+ interrupts = <81 83 92>;
};
usb: usb@e101000 {
compatible = "lantiq,mei-xway";
reg = <0xe116000 0x9c>;
interrupt-parent = <&icu0>;
- interrupts = <63>;
+ interrupts = <63 61 68>;
};
gsw: etop@e180000 {
compatible = "lantiq,mei-xway";
reg = <0xe116000 0x400>;
interrupt-parent = <&icu0>;
- interrupts = <63>;
+ interrupts = <63 61 159>;
};
gsw: etop@e180000 {
reg = <0xd900000 0x1000>;
interrupt-parent = <&icu0>;
- interrupts = <161 144>;
+ interrupts = <161 144 145 146 147>;
phys = <&pcie0_phy LANTIQ_PCIE_PHY_MODE_36MHZ>;
phy-names = "pcie";
(transaction layer end-to-end CRC checking).
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
-@@ -1482,6 +1482,8 @@ void pci_walk_bus(struct pci_bus *top, i
+@@ -1483,6 +1483,8 @@ void pci_walk_bus(struct pci_bus *top, i
void *userdata);
int pci_cfg_space_size(struct pci_dev *dev);
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
obj-y += vmmc.o
--- /dev/null
+++ b/arch/mips/lantiq/xway/timer.c
-@@ -0,0 +1,852 @@
+@@ -0,0 +1,887 @@
+#ifndef CONFIG_SOC_AMAZON_SE
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/sched/signal.h>
+
++#include <linux/of_platform.h>
++
+#include <asm/irq.h>
+#include <asm/div64.h>
+#include "../clk.h"
+ return 0;
+}
+
-+int __init lq_gptu_init(void)
++static int gptu_probe(struct platform_device *pdev)
+{
+ int ret;
-+ unsigned int i;
++ int i;
+
+ ltq_w32(0, LQ_GPTU_IRNEN);
+ ltq_w32(0xfff, LQ_GPTU_IRNCR);
+ }
+
+ for (i = 0; i < timer_dev.number_of_timers; i++) {
-+ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
-+ if (ret) {
-+ for (; i >= 0; i--)
-+ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
++ int irq = platform_get_irq(pdev, i);
++ if (irq < 0) {
++ printk(KERN_ERR "gptu: failed in getting irq (%d), get error %d\n", i, irq);
++ for (i--; i >= 0; i--)
++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
+ misc_deregister(&gptu_miscdev);
++ return irq;
++ }
++
++ ret = request_irq(irq, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
++ if (ret) {
+ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
++ for (i--; i >= 0; i--)
++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
++ misc_deregister(&gptu_miscdev);
+ return ret;
+ } else {
-+ timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
++ timer_dev.timer[i].irq = irq;
+ disable_irq(timer_dev.timer[i].irq);
+ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
+ }
+ return 0;
+}
+
++static const struct of_device_id gptu_match[] = {
++ { .compatible = "lantiq,gptu-xway" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, gptu_match);
++
++static struct platform_driver gptu_driver = {
++ .probe = gptu_probe,
++ .driver = {
++ .name = "gptu-xway",
++ .owner = THIS_MODULE,
++ .of_match_table = gptu_match,
++ },
++};
++
++int __init lq_gptu_init(void)
++{
++ int ret = platform_driver_register(&gptu_driver);
++
++ if (ret)
++ pr_info("gptu: Error registering platform driver\n");
++ return ret;
++}
++
+void __exit lq_gptu_exit(void)
+{
+ unsigned int i;
#include "ifxmips_pcie.h"
#include "ifxmips_pcie_reg.h"
-@@ -40,6 +47,11 @@
+@@ -25,11 +32,6 @@
+ #define IFX_PCIE_ERROR_INT
+ #define IFX_PCIE_IO_32BIT
+
+-#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25)
+-#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8)
+-#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9)
+-#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10)
+-#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11)
+ #define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
+ #define SM(_v, _f) (((_v) << _f##_S) & (_f))
+ #define IFX_REG_SET_BIT(_f, _r) \
+@@ -40,30 +42,30 @@
static DEFINE_SPINLOCK(ifx_pcie_lock);
u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
{
-@@ -82,6 +94,22 @@ void ifx_pcie_debug(const char *fmt, ...
+ .ir_irq = {
+- .irq = IFX_PCIE_IR,
+ .name = "ifx_pcie_rc0",
+ },
+
+ .legacy_irq = {
+ {
+ .irq_bit = PCIE_IRN_INTA,
+- .irq = IFX_PCIE_INTA,
+ },
+ {
+ .irq_bit = PCIE_IRN_INTB,
+- .irq = IFX_PCIE_INTB,
+ },
+ {
+ .irq_bit = PCIE_IRN_INTC,
+- .irq = IFX_PCIE_INTC,
+ },
+ {
+ .irq_bit = PCIE_IRN_INTD,
+- .irq = IFX_PCIE_INTD,
+ },
+ },
+ },
+@@ -82,6 +84,22 @@ void ifx_pcie_debug(const char *fmt, ...
printk("%s", buf);
}
static inline int pcie_ltssm_enable(int pcie_port)
{
-@@ -988,10 +1016,26 @@ int ifx_pcie_bios_plat_dev_init(struct
+@@ -857,7 +875,8 @@ pcie_rc_core_int_init(int pcie_port)
+ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0,
+ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]);
+ if (ret)
+- printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR);
++ printk(KERN_ERR "%s request irq %d failed\n", __func__,
++ pcie_irqs[pcie_port].ir_irq.irq);
+
+ return ret;
+ }
+@@ -988,10 +1007,26 @@ int ifx_pcie_bios_plat_dev_init(struct
static int
pcie_rc_initialize(int pcie_port)
{
pcie_ep_gpio_rst_init(pcie_port);
-@@ -1000,26 +1044,21 @@ pcie_rc_initialize(int pcie_port)
+@@ -1000,26 +1035,21 @@ pcie_rc_initialize(int pcie_port)
* reset PCIe PHY will solve this issue
*/
for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
/* Enable PCIe PHY and Clock */
pcie_core_pmu_setup(pcie_port);
-@@ -1035,6 +1074,10 @@ pcie_rc_initialize(int pcie_port)
+@@ -1035,6 +1065,10 @@ pcie_rc_initialize(int pcie_port)
/* Once link is up, break out */
if (pcie_app_loigc_setup(pcie_port) == 0)
break;
}
if (i >= IFX_PCIE_PHY_LOOP_CNT) {
printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
-@@ -1045,17 +1088,74 @@ pcie_rc_initialize(int pcie_port)
+@@ -1045,17 +1079,73 @@ pcie_rc_initialize(int pcie_port)
return 0;
}
-
+
+ ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie");
-+ if (IS_ERR(ltq_pcie_phy)) {
-+ dev_err(&pdev->dev, "failed to get the PCIe PHY\n");
-+ return PTR_ERR(ltq_pcie_phy);
-+ }
++ if (IS_ERR(ltq_pcie_phy))
++ return dev_err_probe(&pdev->dev, PTR_ERR(ltq_pcie_phy),
++ "failed to get the PCIe PHY\n");
+
+ ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL);
+ if (IS_ERR(ltq_pcie_reset)) {
for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
if (pcie_rc_initialize(pcie_port) == 0) {
IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n",
-@@ -1067,6 +1167,7 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1066,7 +1156,19 @@ static int __init ifx_pcie_bios_init(voi
+ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__);
return -ENOMEM;
}
++ pcie_irqs[pcie_port].ir_irq.irq = platform_get_irq(pdev, 0);
++ if (pcie_irqs[pcie_port].ir_irq.irq < 0)
++ return pcie_irqs[pcie_port].ir_irq.irq;
++
++ for (int i = 0; i <= 3; i++){
++ pcie_irqs[pcie_port].legacy_irq[i].irq = platform_get_irq(pdev, i + 1);
++
++ if (pcie_irqs[pcie_port].legacy_irq[i].irq < 0)
++ return pcie_irqs[pcie_port].legacy_irq[i].irq;
++ }
++
ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
+ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node);
register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
/* XXX, clear error status */
-@@ -1083,6 +1184,30 @@ static int __init ifx_pcie_bios_init(voi
+@@ -1083,6 +1185,30 @@ static int __init ifx_pcie_bios_init(voi
return 0;
}
static inline void pcie_core_pmu_setup(int pcie_port)
{
struct clk *clk;
+--- a/arch/mips/pci/ifxmips_pcie.h
++++ b/arch/mips/pci/ifxmips_pcie.h
+@@ -96,13 +96,13 @@ struct ifx_pci_controller {
+ };
+
+ typedef struct ifx_pcie_ir_irq {
+- const unsigned int irq;
++ unsigned int irq;
+ const char name[16];
+ }ifx_pcie_ir_irq_t;
+
+ typedef struct ifx_pcie_legacy_irq{
+ const u32 irq_bit;
+- const int irq;
++ int irq;
+ }ifx_pcie_legacy_irq_t;
+
+ typedef struct ifx_pcie_irq {
--- /dev/null
+From 2b873c59fd313aee57864f96d64a228f2ea7c208 Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Mon, 13 May 2024 10:42:24 +0200
+Subject: [PATCH] MIPS: lantiq: xway: vmmc: use platform_get_irq to get irqs
+ from dts
+
+Let's fetch the irqs from the dts here and expose them to the voice
+driver like it is done for the cp1 base memory.
+
+ToDo:
+Maybe it is possible to drop this driver completely and merge this
+handling to the voice driver.
+
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ arch/mips/lantiq/xway/vmmc.c | 53 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+--- a/arch/mips/lantiq/xway/vmmc.c
++++ b/arch/mips/lantiq/xway/vmmc.c
+@@ -13,6 +13,10 @@
+
+ static unsigned int *cp1_base;
+
++static int ad0_irq;
++static int ad1_irq;
++static int vc_irq[4];
++
+ unsigned int *ltq_get_cp1_base(void)
+ {
+ if (!cp1_base)
+@@ -22,16 +26,65 @@ unsigned int *ltq_get_cp1_base(void)
+ }
+ EXPORT_SYMBOL(ltq_get_cp1_base);
+
++unsigned int ltq_get_mps_ad0_irq(void)
++{
++ if (!ad0_irq)
++ panic("no ad0 irq was set\n");
++
++ return ad0_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad0_irq);
++
++unsigned int ltq_get_mps_ad1_irq(void)
++{
++ if (!ad1_irq)
++ panic("no ad1 irq was set\n");
++
++ return ad1_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad1_irq);
++
++unsigned int ltq_get_mps_vc_irq(int idx)
++{
++ if (!vc_irq[idx])
++ panic("no vc%d irq was set\n", idx);
++
++ return vc_irq[idx];
++}
++EXPORT_SYMBOL(ltq_get_mps_vc_irq);
++
+ static int vmmc_probe(struct platform_device *pdev)
+ {
+ #define CP1_SIZE (1 << 20)
+ int gpio_count;
+ dma_addr_t dma;
++ int i;
+
+ cp1_base =
+ (void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE,
+ &dma, GFP_KERNEL));
+
++ ad0_irq = platform_get_irq(pdev, 4);
++ if (ad0_irq < 0) {
++ dev_err(&pdev->dev, "failed to get MPS AD0 irq: %d\n", ad0_irq);
++ return ad0_irq;
++ }
++
++ ad1_irq = platform_get_irq(pdev, 5);
++ if (ad1_irq < 0) {
++ dev_err(&pdev->dev, "failed to get MPS AD1 irq: %d\n", ad1_irq);
++ return ad1_irq;
++ }
++
++ for (i = 0; i < 4; i++) {
++ vc_irq[i] = platform_get_irq(pdev, i);
++ if (vc_irq[i] < 0) {
++ dev_err(&pdev->dev, "failed to get MPS VC%d irq: %d\n",
++ i, vc_irq[i]);
++ return vc_irq[i];
++ }
++ }
++
+ gpio_count = of_gpio_count(pdev->dev.of_node);
+ while (gpio_count > 0) {
+ enum of_gpio_flags flags;
--- /dev/null
+From 82ea7c7fb4e90620beba8b6436fc12df2379ef8d Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 10 Oct 2022 16:52:25 +0200
+Subject: [PATCH 731/768] dt-bindings: net: dsa: lantiq_gswip: Add missing
+ phy-mode and fixed-link
+
+The CPU port has to specify a phy-mode and either a phy or a fixed-link.
+Since GSWIP is connected using a SoC internal protocol there's no PHY
+involved. Add phy-mode = "internal" and a fixed-link to describe the
+communication between the PMAC (Ethernet controller) and GSWIP switch.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
++++ b/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
+@@ -97,7 +97,13 @@ switch@e108000 {
+ port@6 {
+ reg = <0x6>;
+ label = "cpu";
++ phy-mode = "internal";
+ ethernet = <ð0>;
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
+ };
+ };
+
--- /dev/null
+From a55b9d802e11baceb35bd312419ad82086065b08 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 10 Oct 2022 16:59:35 +0200
+Subject: [PATCH 732/768] net: dsa: lantiq_gswip: Only allow phy-mode =
+ "internal" on the CPU port
+
+Add the CPU port to gswip_xrx200_phylink_get_caps() and
+gswip_xrx300_phylink_get_caps(). It connects through a SoC-internal bus,
+so the only allowed phy-mode is PHY_INTERFACE_MODE_INTERNAL.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1513,6 +1513,7 @@ static void gswip_xrx200_phylink_validat
+ case 2:
+ case 3:
+ case 4:
++ case 6:
+ if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
+ goto unsupported;
+ break;
+@@ -1552,6 +1553,7 @@ static void gswip_xrx300_phylink_validat
+ case 2:
+ case 3:
+ case 4:
++ case 6:
+ if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
+ goto unsupported;
+ break;
--- /dev/null
+From 4d3dd68a1c56674ff666d0622b545992fac31754 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 31 Jul 2022 22:54:52 +0200
+Subject: [PATCH 733/768] net: dsa: lantiq_gswip: Use dev_err_probe where
+ appropriate
+
+dev_err_probe() can be used to simplify the existing code. Also it means
+we get rid of the following warning which is seen whenever the PMAC
+(Ethernet controller which connects to GSWIP's CPU port) has not been
+probed yet:
+ gswip 1e108000.switch: dsa switch register failed: -517
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 53 ++++++++++++++++------------------
+ 1 file changed, 25 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1939,11 +1939,9 @@ static int gswip_gphy_fw_load(struct gsw
+ msleep(200);
+
+ ret = request_firmware(&fw, gphy_fw->fw_name, dev);
+- if (ret) {
+- dev_err(dev, "failed to load firmware: %s, error: %i\n",
+- gphy_fw->fw_name, ret);
+- return ret;
+- }
++ if (ret)
++ return dev_err_probe(dev, ret, "failed to load firmware: %s\n",
++ gphy_fw->fw_name);
+
+ /* GPHY cores need the firmware code in a persistent and contiguous
+ * memory area with a 16 kB boundary aligned start address.
+@@ -1956,9 +1954,9 @@ static int gswip_gphy_fw_load(struct gsw
+ dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
+ memcpy(fw_addr, fw->data, fw->size);
+ } else {
+- dev_err(dev, "failed to alloc firmware memory\n");
+ release_firmware(fw);
+- return -ENOMEM;
++ return dev_err_probe(dev, -ENOMEM,
++ "failed to alloc firmware memory\n");
+ }
+
+ release_firmware(fw);
+@@ -1985,8 +1983,8 @@ static int gswip_gphy_fw_probe(struct gs
+
+ gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
+ if (IS_ERR(gphy_fw->clk_gate)) {
+- dev_err(dev, "Failed to lookup gate clock\n");
+- return PTR_ERR(gphy_fw->clk_gate);
++ return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate),
++ "Failed to lookup gate clock\n");
+ }
+
+ ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
+@@ -2006,8 +2004,8 @@ static int gswip_gphy_fw_probe(struct gs
+ gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
+ break;
+ default:
+- dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
+- return -EINVAL;
++ return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n",
++ gphy_mode);
+ }
+
+ gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
+@@ -2060,8 +2058,9 @@ static int gswip_gphy_fw_list(struct gsw
+ priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
+ break;
+ default:
+- dev_err(dev, "unknown GSWIP version: 0x%x", version);
+- return -ENOENT;
++ return dev_err_probe(dev, -ENOENT,
++ "unknown GSWIP version: 0x%x",
++ version);
+ }
+ }
+
+@@ -2069,10 +2068,9 @@ static int gswip_gphy_fw_list(struct gsw
+ if (match && match->data)
+ priv->gphy_fw_name_cfg = match->data;
+
+- if (!priv->gphy_fw_name_cfg) {
+- dev_err(dev, "GPHY compatible type not supported");
+- return -ENOENT;
+- }
++ if (!priv->gphy_fw_name_cfg)
++ return dev_err_probe(dev, -ENOENT,
++ "GPHY compatible type not supported");
+
+ priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
+ if (!priv->num_gphy_fw)
+@@ -2171,8 +2169,8 @@ static int gswip_probe(struct platform_d
+ return -EINVAL;
+ break;
+ default:
+- dev_err(dev, "unknown GSWIP version: 0x%x", version);
+- return -ENOENT;
++ return dev_err_probe(dev, -ENOENT,
++ "unknown GSWIP version: 0x%x", version);
+ }
+
+ /* bring up the mdio bus */
+@@ -2180,10 +2178,9 @@ static int gswip_probe(struct platform_d
+ if (gphy_fw_np) {
+ err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
+ of_node_put(gphy_fw_np);
+- if (err) {
+- dev_err(dev, "gphy fw probe failed\n");
+- return err;
+- }
++ if (err)
++ return dev_err_probe(dev, err,
++ "gphy fw probe failed\n");
+ }
+
+ /* bring up the mdio bus */
+@@ -2191,20 +2188,20 @@ static int gswip_probe(struct platform_d
+ if (mdio_np) {
+ err = gswip_mdio(priv, mdio_np);
+ if (err) {
+- dev_err(dev, "mdio probe failed\n");
++ dev_err_probe(dev, err, "mdio probe failed\n");
+ goto put_mdio_node;
+ }
+ }
+
+ err = dsa_register_switch(priv->ds);
+ if (err) {
+- dev_err(dev, "dsa switch register failed: %i\n", err);
++ dev_err_probe(dev, err, "dsa switch registration failed\n");
+ goto mdio_bus;
+ }
+ if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
+- dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
+- priv->hw_info->cpu_port);
+- err = -EINVAL;
++ err = dev_err_probe(dev, -EINVAL,
++ "wrong CPU port defined, HW only supports port: %i",
++ priv->hw_info->cpu_port);
+ goto disable_switch;
+ }
+
--- /dev/null
+From 8cf0b680abc157adeec3fb93a10354c470694535 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Thu, 28 Jul 2022 22:37:11 +0200
+Subject: [PATCH 734/768] net: dsa: lantiq_gswip: Don't manually call
+ gswip_port_enable()
+
+We don't need to manually call gswip_port_enable() from within
+gswip_setup() for the CPU port. DSA does this automatically for us.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -874,8 +874,6 @@ static int gswip_setup(struct dsa_switch
+
+ ds->mtu_enforcement_ingress = true;
+
+- gswip_port_enable(ds, cpu_port, NULL);
+-
+ ds->configure_vlan_while_not_filtering = false;
+
+ return 0;
--- /dev/null
+From 54a2f7f2c134738bd3f4ea0a213138d169f2726e Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Fri, 10 May 2024 13:52:10 +0200
+Subject: [PATCH] net: dsa: lantiq_gswip: do also enable or disable cpu port
+
+Before commit 74be4babe72f ("net: dsa: do not enable or disable non user
+ports"), gswip_port_enable/disable() were also executed for the cpu port
+in gswip_setup() which disabled the cpu port during initialization.
+
+Let's restore this by removing the dsa_is_user_port checks. Also, let's
+clean up the gswip_port_enable() function so that we only have to check
+for the cpu port once.
+
+Fixes: 74be4babe72f ("net: dsa: do not enable or disable non user ports")
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ drivers/net/dsa/lantiq_gswip.c | 24 ++++++++----------------
+ 1 file changed, 8 insertions(+), 16 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -671,13 +671,18 @@ static int gswip_port_enable(struct dsa_
+ struct gswip_priv *priv = ds->priv;
+ int err;
+
+- if (!dsa_is_user_port(ds, port))
+- return 0;
+-
+ if (!dsa_is_cpu_port(ds, port)) {
++ u32 mdio_phy = 0;
++
+ err = gswip_add_single_port_br(priv, port, true);
+ if (err)
+ return err;
++
++ if (phydev)
++ mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
++
++ gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
++ GSWIP_MDIO_PHYp(port));
+ }
+
+ /* RMON Counter Enable for port */
+@@ -690,16 +695,6 @@ static int gswip_port_enable(struct dsa_
+ gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
+ GSWIP_SDMA_PCTRLp(port));
+
+- if (!dsa_is_cpu_port(ds, port)) {
+- u32 mdio_phy = 0;
+-
+- if (phydev)
+- mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
+-
+- gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
+- GSWIP_MDIO_PHYp(port));
+- }
+-
+ return 0;
+ }
+
+@@ -707,9 +702,6 @@ static void gswip_port_disable(struct ds
+ {
+ struct gswip_priv *priv = ds->priv;
+
+- if (!dsa_is_user_port(ds, port))
+- return;
+-
+ gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
+ GSWIP_FDMA_PCTRLp(port));
+ gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
--- /dev/null
+From 8ab55ac9678ca1f50f786c84484599dd675c5a9f Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 18 May 2022 23:53:09 +0200
+Subject: [PATCH 736/768] net: dsa: lantiq_gswip: Use dsa_is_cpu_port() in
+ gswip_port_change_mtu()
+
+Make the check for the CPU port in gswip_port_change_mtu() consistent
+with other areas of the driver by using dsa_is_cpu_port().
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1463,12 +1463,11 @@ static int gswip_port_max_mtu(struct dsa
+ static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
+ {
+ struct gswip_priv *priv = ds->priv;
+- int cpu_port = priv->hw_info->cpu_port;
+
+ /* CPU port always has maximum mtu of user ports, so use it to set
+ * switch frame size, including 8 byte special header.
+ */
+- if (port == cpu_port) {
++ if (dsa_is_cpu_port(ds, port)) {
+ new_mtu += 8;
+ gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN,
+ GSWIP_MAC_FLEN);
--- /dev/null
+From ef98b183d8fc7187a2efcc21c8f54f3cf061d556 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Tue, 17 May 2022 22:39:58 +0200
+Subject: [PATCH 737/768] net: dsa: lantiq_gswip: Change literal 6 to ETH_ALEN
+
+The addr variable in gswip_port_fdb_dump() stores a mac address. Use
+ETH_ALEN to make this consistent across other drivers.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1383,7 +1383,7 @@ static int gswip_port_fdb_dump(struct ds
+ {
+ struct gswip_priv *priv = ds->priv;
+ struct gswip_pce_table_entry mac_bridge = {0,};
+- unsigned char addr[6];
++ unsigned char addr[ETH_ALEN];
+ int i;
+ int err;
+
--- /dev/null
+From 61e9b19f6e6174afa7540f0b468a69bc940b91d4 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 21:23:49 +0200
+Subject: [PATCH 738/768] net: dsa: lantiq_gswip: Consistently use macros for
+ the mac bridge table
+
+Introduce a new GSWIP_TABLE_MAC_BRIDGE_PORT macro and use it throughout
+the driver. Also update GSWIP_TABLE_MAC_BRIDGE_STATIC to use the BIT()
+macro. This makes the driver code easier to understand.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -236,7 +236,8 @@
+ #define GSWIP_TABLE_ACTIVE_VLAN 0x01
+ #define GSWIP_TABLE_VLAN_MAPPING 0x02
+ #define GSWIP_TABLE_MAC_BRIDGE 0x0b
+-#define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */
++#define GSWIP_TABLE_MAC_BRIDGE_STATIC BIT(0) /* Static not, aging entry */
++#define GSWIP_TABLE_MAC_BRIDGE_PORT GENMASK(7, 4) /* Port on learned entries */
+
+ #define XRX200_GPHY_FW_ALIGN (16 * 1024)
+
+@@ -1279,7 +1280,8 @@ static void gswip_port_fast_age(struct d
+ if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
+ continue;
+
+- if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
++ if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT,
++ mac_bridge.val[0]))
+ continue;
+
+ mac_bridge.valid = false;
+@@ -1414,7 +1416,8 @@ static int gswip_port_fdb_dump(struct ds
+ return err;
+ }
+ } else {
+- if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) {
++ if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT,
++ mac_bridge.val[0])) {
+ err = cb(addr, 0, false, data);
+ if (err)
+ return err;
--- /dev/null
+From 7a9e185075ababa827d1d3a33b787ad6d718c8ec Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 22:24:24 +0200
+Subject: [PATCH 739/768] net: dsa: lantiq_gswip: Forbid
+ gswip_add_single_port_br on the CPU port
+
+Calling gswip_add_single_port_br() with the CPU port would be a bug
+because then only the CPU port could talk to itself. Add the CPU port to
+the validation at the beginning of gswip_add_single_port_br().
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -633,7 +633,7 @@ static int gswip_add_single_port_br(stru
+ unsigned int max_ports = priv->hw_info->max_ports;
+ int err;
+
+- if (port >= max_ports) {
++ if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) {
+ dev_err(priv->dev, "single port for %i supported\n", port);
+ return -EIO;
+ }
--- /dev/null
+From 28be6bfb735d851e646abb05b8e24eb6764596f5 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 22:26:20 +0200
+Subject: [PATCH 740/768] net: dsa: lantiq_gswip: Fix error message in
+ gswip_add_single_port_br()
+
+The error message is printed when the port cannot be used. Update the
+error message to reflect that.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -634,7 +634,8 @@ static int gswip_add_single_port_br(stru
+ int err;
+
+ if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) {
+- dev_err(priv->dev, "single port for %i supported\n", port);
++ dev_err(priv->dev, "single port for %i is not supported\n",
++ port);
+ return -EIO;
+ }
+
--- /dev/null
+From 45a0371568b1f050d787564875653f41a1f6fb98 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 14:06:40 +0200
+Subject: [PATCH 741/768] net: dsa: lantiq_gswip: Fix comments in
+ gswip_port_vlan_filtering()
+
+Update the comments in gswip_port_vlan_filtering() so it's clear that
+there are two separate cases, one for "tag based VLAN" and another one
+for "port based VLAN".
+
+Suggested-by: Martin Schiller <ms@dev.tdt.de>
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -762,7 +762,7 @@ static int gswip_port_vlan_filtering(str
+ }
+
+ if (vlan_filtering) {
+- /* Use port based VLAN tag */
++ /* Use tag based VLAN */
+ gswip_switch_mask(priv,
+ GSWIP_PCE_VCTRL_VSR,
+ GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
+@@ -771,7 +771,7 @@ static int gswip_port_vlan_filtering(str
+ gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
+ GSWIP_PCE_PCTRL_0p(port));
+ } else {
+- /* Use port based VLAN tag */
++ /* Use port based VLAN */
+ gswip_switch_mask(priv,
+ GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
+ GSWIP_PCE_VCTRL_VEMR,
--- /dev/null
+From 4775f9543e691d9a2f5dd9aa5d46c66d37928250 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 14:19:05 +0200
+Subject: [PATCH 742/768] net: dsa: lantiq_gswip: Add and use a
+ GSWIP_TABLE_MAC_BRIDGE_FID macro
+
+Only bits [5:0] in mac_bridge.key[3] are reserved for the FID. Add a
+macro so this becomes obvious when reading the driver code.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -238,6 +238,7 @@
+ #define GSWIP_TABLE_MAC_BRIDGE 0x0b
+ #define GSWIP_TABLE_MAC_BRIDGE_STATIC BIT(0) /* Static not, aging entry */
+ #define GSWIP_TABLE_MAC_BRIDGE_PORT GENMASK(7, 4) /* Port on learned entries */
++#define GSWIP_TABLE_MAC_BRIDGE_FID GENMASK(5, 0) /* Filtering identifier */
+
+ #define XRX200_GPHY_FW_ALIGN (16 * 1024)
+
+@@ -1357,7 +1358,7 @@ static int gswip_port_fdb(struct dsa_swi
+ mac_bridge.key[0] = addr[5] | (addr[4] << 8);
+ mac_bridge.key[1] = addr[3] | (addr[2] << 8);
+ mac_bridge.key[2] = addr[1] | (addr[0] << 8);
+- mac_bridge.key[3] = fid;
++ mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_FID, fid);
+ mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
+ mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
+ mac_bridge.valid = add;
--- /dev/null
+From 00b5121435ccd4ce54f79179dd9ee3e2610d7dcf Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 16:31:57 +0200
+Subject: [PATCH 743/768] net: dsa: lantiq_gswip: Improve error message in
+ gswip_port_fdb()
+
+Print the port which is not found to be part of a bridge so it's easier
+to investigate the underlying issue.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1349,7 +1349,8 @@ static int gswip_port_fdb(struct dsa_swi
+ }
+
+ if (fid == -1) {
+- dev_err(priv->dev, "Port not part of a bridge\n");
++ dev_err(priv->dev,
++ "Port %d is not known to be part of bridge\n", port);
+ return -EINVAL;
+ }
+
--- /dev/null
+From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:12:28 +0200
+Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/lantiq/Kconfig | 10 +
+ arch/mips/lantiq/xway/sysctrl.c | 2 +
+ arch/mips/pci/Makefile | 2 +
+ arch/mips/pci/fixup-lantiq-pcie.c | 82 +++
+ arch/mips/pci/fixup-lantiq.c | 5 +-
+ arch/mips/pci/ifxmips_pci_common.h | 57 ++
+ arch/mips/pci/ifxmips_pcie.c | 1099 ++++++++++++++++++++++++++++++
+ arch/mips/pci/ifxmips_pcie.h | 135 ++++
+ arch/mips/pci/ifxmips_pcie_ar10.h | 290 ++++++++
+ arch/mips/pci/ifxmips_pcie_msi.c | 392 +++++++++++
+ arch/mips/pci/ifxmips_pcie_phy.c | 478 +++++++++++++
+ arch/mips/pci/ifxmips_pcie_pm.c | 176 +++++
+ arch/mips/pci/ifxmips_pcie_pm.h | 36 +
+ arch/mips/pci/ifxmips_pcie_reg.h | 1001 +++++++++++++++++++++++++++
+ arch/mips/pci/ifxmips_pcie_vr9.h | 271 ++++++++
+ arch/mips/pci/pci.c | 25 +
+ arch/mips/pci/pcie-lantiq.h | 1305 ++++++++++++++++++++++++++++++++++++
+ drivers/pci/pcie/aer/Kconfig | 2 +-
+ include/linux/pci.h | 2 +
+ include/linux/pci_ids.h | 6 +
+ 20 files changed, 5374 insertions(+), 2 deletions(-)
+ create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c
+ create mode 100644 arch/mips/pci/ifxmips_pci_common.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c
+ create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h
+ create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h
+ create mode 100644 arch/mips/pci/pcie-lantiq.h
+
+--- a/arch/mips/lantiq/Kconfig
++++ b/arch/mips/lantiq/Kconfig
+@@ -20,6 +20,7 @@ config SOC_XWAY
+ bool "XWAY"
+ select SOC_TYPE_XWAY
+ select HAVE_PCI
++ select ARCH_SUPPORTS_MSI
+ select MFD_SYSCON
+ select MFD_CORE
+
+@@ -52,4 +53,13 @@ config PCI_LANTIQ
+ bool "PCI Support"
+ depends on SOC_XWAY && PCI
+
++config PCIE_LANTIQ
++ bool "PCIE Support"
++ depends on SOC_XWAY && PCI
++
++config PCIE_LANTIQ_MSI
++ bool
++ depends on PCIE_LANTIQ && PCI_MSI
++ default y
++
+ endif
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -41,6 +41,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o
+ obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
+ obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o
++obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o
+ obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
+ obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
+ obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
+--- /dev/null
++++ b/arch/mips/pci/fixup-lantiq-pcie.c
+@@ -0,0 +1,74 @@
++/******************************************************************************
++**
++** FILE NAME : ifxmips_fixup_pcie.c
++** PROJECT : IFX UEIP for VRX200
++** MODULES : PCIe
++**
++** DATE : 02 Mar 2009
++** AUTHOR : Lei Chuanhua
++** DESCRIPTION : PCIe Root Complex Driver
++** COPYRIGHT : Copyright (c) 2009
++** Infineon Technologies AG
++** Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++** HISTORY
++** $Version $Date $Author $Comment
++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version
++*******************************************************************************/
++/*!
++ \file ifxmips_fixup_pcie.c
++ \ingroup IFX_PCIE
++ \brief PCIe Fixup functions source file
++*/
++#include <linux/pci.h>
++#include <linux/pci_regs.h>
++#include <linux/pci_ids.h>
++
++#include <lantiq_soc.h>
++
++#include "pcie-lantiq.h"
++
++static void
++ifx_pcie_fixup_resource(struct pci_dev *dev)
++{
++ u32 reg;
++
++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev));
++
++ printk("%s: fixup host controller %s (%04x:%04x)\n",
++ __func__, pci_name(dev), dev->vendor, dev->device);
++
++ /* Setup COMMAND register */
++ reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* |
++ PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR;
++ pci_write_config_word(dev, PCI_COMMAND, reg);
++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev));
++}
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource);
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource);
++
++static void
++ifx_pcie_rc_class_early_fixup(struct pci_dev *dev)
++{
++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev));
++
++ if (dev->devfn == PCI_DEVFN(0, 0) &&
++ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
++
++ dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff);
++
++ printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__);
++ }
++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev));
++ mdelay(10);
++}
++
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE,
++ ifx_pcie_rc_class_early_fixup);
++
++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE,
++ ifx_pcie_rc_class_early_fixup);
+--- a/arch/mips/pci/fixup-lantiq.c
++++ b/arch/mips/pci/fixup-lantiq.c
+@@ -6,12 +6,19 @@
+
+ #include <linux/of_irq.h>
+ #include <linux/of_pci.h>
++#include <linux/pci.h>
++#include "ifxmips_pci_common.h"
+
+ int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL;
+ int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL;
+
+ int pcibios_plat_dev_init(struct pci_dev *dev)
+ {
++#ifdef CONFIG_PCIE_LANTIQ
++ if (pci_find_capability(dev, PCI_CAP_ID_EXP))
++ ifx_pcie_bios_plat_dev_init(dev);
++#endif
++
+ if (ltq_pci_plat_arch_init)
+ return ltq_pci_plat_arch_init(dev);
+
+@@ -23,5 +30,10 @@ int pcibios_plat_dev_init(struct pci_dev
+
+ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ {
++#ifdef CONFIG_PCIE_LANTIQ
++ if (pci_find_capability((struct pci_dev *)dev, PCI_CAP_ID_EXP))
++ return ifx_pcie_bios_map_irq(dev, slot, pin);
++#endif
++
+ return of_irq_parse_and_map_pci(dev, slot, pin);
+ }
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pci_common.h
+@@ -0,0 +1,53 @@
++/******************************************************************************
++**
++** FILE NAME : ifxmips_pci_common.h
++** PROJECT : IFX UEIP
++** MODULES : PCI subsystem
++**
++** DATE : 30 June 2009
++** AUTHOR : Lei Chuanhua
++** DESCRIPTION : PCIe Root Complex Driver
++** COPYRIGHT : Copyright (c) 2009
++** Infineon Technologies AG
++** Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++** HISTORY
++** $Version $Date $Author $Comment
++** 0.0.1 30 June,2009 Lei Chuanhua Initial version
++*******************************************************************************/
++
++#ifndef IFXMIPS_PCI_COMMON_H
++#define IFXMIPS_PCI_COMMON_H
++#include <linux/version.h>
++/*!
++ \defgroup IFX_PCI_COM IFX PCI/PCIe common parts for OS integration
++ \brief PCI/PCIe common parts
++*/
++
++/*!
++ \defgroup IFX_PCI_COM_OS OS APIs
++ \ingroup IFX_PCI_COM
++ \brief PCI/PCIe bus driver OS interface functions
++*/
++/*!
++ \file ifxmips_pci_common.h
++ \ingroup IFX_PCI_COM
++ \brief PCI/PCIe bus driver common OS header file
++*/
++#define IFX_PCI_CONST const
++#ifdef CONFIG_IFX_PCI
++extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin);
++extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev);
++#endif /* COFNIG_IFX_PCI */
++
++#ifdef CONFIG_PCIE_LANTIQ
++extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin);
++extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev);
++#endif
++
++#endif /* IFXMIPS_PCI_COMMON_H */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie.c
+@@ -0,0 +1,1091 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2009 Lei Chuanhua <chuanhua.lei@infineon.com>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/mm.h>
++#include <asm/paccess.h>
++#include <linux/pci.h>
++#include <linux/pci_regs.h>
++#include <linux/module.h>
++
++#include "ifxmips_pcie.h"
++#include "ifxmips_pcie_reg.h"
++
++/* Enable 32bit io due to its mem mapped io nature */
++#define IFX_PCIE_ERROR_INT
++#define IFX_PCIE_IO_32BIT
++
++#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25)
++#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8)
++#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9)
++#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10)
++#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11)
++#define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
++#define SM(_v, _f) (((_v) << _f##_S) & (_f))
++#define IFX_REG_SET_BIT(_f, _r) \
++ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r))
++
++#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10
++
++static DEFINE_SPINLOCK(ifx_pcie_lock);
++
++u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
++
++static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
++ {
++ .ir_irq = {
++ .irq = IFX_PCIE_IR,
++ .name = "ifx_pcie_rc0",
++ },
++
++ .legacy_irq = {
++ {
++ .irq_bit = PCIE_IRN_INTA,
++ .irq = IFX_PCIE_INTA,
++ },
++ {
++ .irq_bit = PCIE_IRN_INTB,
++ .irq = IFX_PCIE_INTB,
++ },
++ {
++ .irq_bit = PCIE_IRN_INTC,
++ .irq = IFX_PCIE_INTC,
++ },
++ {
++ .irq_bit = PCIE_IRN_INTD,
++ .irq = IFX_PCIE_INTD,
++ },
++ },
++ },
++
++};
++
++void ifx_pcie_debug(const char *fmt, ...)
++{
++ static char buf[256] = {0}; /* XXX */
++ va_list ap;
++
++ va_start(ap, fmt);
++ vsnprintf(buf, sizeof(buf), fmt, ap);
++ va_end(ap);
++
++ printk("%s", buf);
++}
++
++
++static inline int pcie_ltssm_enable(int pcie_port)
++{
++ int i;
++
++ /* Enable LTSSM */
++ IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port));
++
++ /* Wait for the link to come up */
++ for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) {
++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING))
++ return 0;
++ udelay(10);
++ }
++
++ printk("%s link timeout!!!!!\n", __func__);
++ return -1;
++}
++
++static inline void pcie_status_register_clear(int pcie_port)
++{
++ IFX_REG_W32(0, PCIE_RC_DR(pcie_port));
++ IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port));
++ IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port));
++ IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port));
++ IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port));
++ IFX_REG_W32(0, PCIE_RSTS(pcie_port));
++ IFX_REG_W32(0, PCIE_UES_R(pcie_port));
++ IFX_REG_W32(0, PCIE_UEMR(pcie_port));
++ IFX_REG_W32(0, PCIE_UESR(pcie_port));
++ IFX_REG_W32(0, PCIE_CESR(pcie_port));
++ IFX_REG_W32(0, PCIE_CEMR(pcie_port));
++ IFX_REG_W32(0, PCIE_RESR(pcie_port));
++ IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port));
++ IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port));
++ IFX_REG_W32(0, PCIE_TPFCS(pcie_port));
++ IFX_REG_W32(0, PCIE_TNPFCS(pcie_port));
++ IFX_REG_W32(0, PCIE_TCFCS(pcie_port));
++ IFX_REG_W32(0, PCIE_QSR(pcie_port));
++ IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port));
++}
++
++static inline int ifx_pcie_link_up(int pcie_port)
++{
++ return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0;
++}
++
++
++static inline void pcie_mem_io_setup(int pcie_port)
++{
++ u32 reg;
++ /*
++ * BAR[0:1] readonly register
++ * RC contains only minimal BARs for packets mapped to this device
++ * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that
++ * reside on the downstream side fo the bridge.
++ */
++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR)
++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR);
++
++ IFX_REG_W32(reg, PCIE_MBML(pcie_port));
++
++
++#ifdef IFX_PCIE_PREFETCH_MEM_64BIT
++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR)
++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT)
++ | PCIE_PMBL_64BIT_ADDR;
++ IFX_REG_W32(reg, PCIE_PMBL(pcie_port));
++
++ /* Must configure upper 32bit */
++ IFX_REG_W32(0, PCIE_PMBU32(pcie_port));
++ IFX_REG_W32(0, PCIE_PMLU32(pcie_port));
++#else
++ /* PCIe_PBML, same as MBML */
++ IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port));
++#endif
++
++ /* IO Address Range */
++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR)
++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR);
++#ifdef IFX_PCIE_IO_32BIT
++ reg |= PCIE_IOBLSECS_32BIT_IO_ADDR;
++#endif /* IFX_PCIE_IO_32BIT */
++ IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port));
++
++#ifdef IFX_PCIE_IO_32BIT
++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT)
++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE);
++ IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port));
++
++#endif /* IFX_PCIE_IO_32BIT */
++}
++
++static inline void
++pcie_device_setup(int pcie_port)
++{
++ u32 reg;
++
++ /* Device capability register, set up Maximum payload size */
++ reg = IFX_REG_R32(PCIE_DCAP(pcie_port));
++ reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT;
++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE);
++
++ /* Only available for EP */
++ reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY);
++ IFX_REG_W32(reg, PCIE_DCAP(pcie_port));
++
++ /* Device control and status register */
++ /* Set Maximum Read Request size for the device as a Requestor */
++ reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port));
++
++ /*
++ * Request size can be larger than the MPS used, but the completions returned
++ * for the read will be bounded by the MPS size.
++ * In our system, Max request size depends on AHB burst size. It is 64 bytes.
++ * but we set it as 128 as minimum one.
++ */
++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE)
++ | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE);
++
++ /* Enable relaxed ordering, no snoop, and all kinds of errors */
++ reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN;
++
++ IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port));
++}
++
++static inline void
++pcie_link_setup(int pcie_port)
++{
++ u32 reg;
++
++ /*
++ * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM
++ * L0s is reported during link training via TS1 order set by N_FTS
++ */
++ reg = IFX_REG_R32(PCIE_LCAP(pcie_port));
++ reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY;
++ reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY);
++ IFX_REG_W32(reg, PCIE_LCAP(pcie_port));
++
++ /* Link control and status register */
++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port));
++
++ /* Link Enable, ASPM enabled */
++ reg &= ~PCIE_LCTLSTS_LINK_DISABLE;
++
++#ifdef CONFIG_PCIEASPM
++ /*
++ * We use the same physical reference clock that the platform provides on the connector
++ * It paved the way for ASPM to calculate the new exit Latency
++ */
++ reg |= PCIE_LCTLSTS_SLOT_CLK_CFG;
++ reg |= PCIE_LCTLSTS_COM_CLK_CFG;
++ /*
++ * We should disable ASPM by default except that we have dedicated power management support
++ * Enable ASPM will cause the system hangup/instability, performance degration
++ */
++ reg |= PCIE_LCTLSTS_ASPM_ENABLE;
++#else
++ reg &= ~PCIE_LCTLSTS_ASPM_ENABLE;
++#endif /* CONFIG_PCIEASPM */
++
++ /*
++ * The maximum size of any completion with data packet is bounded by the MPS setting
++ * in device control register
++ */
++
++ /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */
++ reg &= ~ PCIE_LCTLSTS_RCB128;
++
++ IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port));
++}
++
++static inline void pcie_error_setup(int pcie_port)
++{
++ u32 reg;
++
++ /*
++ * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone
++ * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE
++ */
++ reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port));
++ reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE;
++
++ IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port));
++
++ /* Uncorrectable Error Mask Register, Unmask <enable> all bits in PCIE_UESR */
++ reg = IFX_REG_R32(PCIE_UEMR(pcie_port));
++ reg &= ~PCIE_ALL_UNCORRECTABLE_ERR;
++ IFX_REG_W32(reg, PCIE_UEMR(pcie_port));
++
++ /* Uncorrectable Error Severity Register, ALL errors are FATAL */
++ IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port));
++
++ /* Correctable Error Mask Register, unmask <enable> all bits */
++ reg = IFX_REG_R32(PCIE_CEMR(pcie_port));
++ reg &= ~PCIE_CORRECTABLE_ERR;
++ IFX_REG_W32(reg, PCIE_CEMR(pcie_port));
++
++ /* Advanced Error Capabilities and Control Registr */
++ reg = IFX_REG_R32(PCIE_AECCR(pcie_port));
++ reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN;
++ IFX_REG_W32(reg, PCIE_AECCR(pcie_port));
++
++ /* Root Error Command Register, Report all types of errors */
++ reg = IFX_REG_R32(PCIE_RECR(pcie_port));
++ reg |= PCIE_RECR_ERR_REPORT_EN;
++ IFX_REG_W32(reg, PCIE_RECR(pcie_port));
++
++ /* Clear the Root status register */
++ reg = IFX_REG_R32(PCIE_RESR(pcie_port));
++ IFX_REG_W32(reg, PCIE_RESR(pcie_port));
++}
++
++static inline void pcie_port_logic_setup(int pcie_port)
++{
++ u32 reg;
++
++ /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */
++ reg = IFX_REG_R32(PCIE_AFR(pcie_port));
++ reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM);
++ reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM)
++ | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM);
++ /* L0s and L1 entry latency */
++ reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY);
++ reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY)
++ | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY);
++ IFX_REG_W32(reg, PCIE_AFR(pcie_port));
++
++
++ /* Port Link Control Register */
++ reg = IFX_REG_R32(PCIE_PLCR(pcie_port));
++ reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */
++ IFX_REG_W32(reg, PCIE_PLCR(pcie_port));
++
++ /* Lane Skew Register */
++ reg = IFX_REG_R32(PCIE_LSR(pcie_port));
++ /* Enable ACK/NACK and FC */
++ reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE);
++ IFX_REG_W32(reg, PCIE_LSR(pcie_port));
++
++ /* Symbol Timer Register and Filter Mask Register 1 */
++ reg = IFX_REG_R32(PCIE_STRFMR(pcie_port));
++
++ /* Default SKP interval is very accurate already, 5us */
++ /* Enable IO/CFG transaction */
++ reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE;
++ /* Disable FC WDT */
++ reg &= ~PCIE_STRFMR_FC_WDT_DISABLE;
++ IFX_REG_W32(reg, PCIE_STRFMR(pcie_port));
++
++ /* Filter Masker Register 2 */
++ reg = IFX_REG_R32(PCIE_FMR2(pcie_port));
++ reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1;
++ IFX_REG_W32(reg, PCIE_FMR2(pcie_port));
++
++ /* VC0 Completion Receive Queue Control Register */
++ reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port));
++ reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE;
++ reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE);
++ IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port));
++}
++
++static inline void pcie_rc_cfg_reg_setup(int pcie_port)
++{
++ u32 reg;
++
++ /* Disable LTSSM */
++ IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */
++
++ pcie_mem_io_setup(pcie_port);
++
++ /* XXX, MSI stuff should only apply to EP */
++ /* MSI Capability: Only enable 32-bit addresses */
++ reg = IFX_REG_R32(PCIE_MCAPR(pcie_port));
++ reg &= ~PCIE_MCAPR_ADDR64_CAP;
++
++ reg |= PCIE_MCAPR_MSI_ENABLE;
++
++ /* Disable multiple message */
++ reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE);
++ IFX_REG_W32(reg, PCIE_MCAPR(pcie_port));
++
++
++ /* Enable PME, Soft reset enabled */
++ reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port));
++ reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST;
++ IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port));
++
++ /* setup the bus */
++ reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM);
++ IFX_REG_W32(reg, PCIE_BNR(pcie_port));
++
++
++ pcie_device_setup(pcie_port);
++ pcie_link_setup(pcie_port);
++ pcie_error_setup(pcie_port);
++
++ /* Root control and capabilities register */
++ reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port));
++ reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN;
++ IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port));
++
++ /* Port VC Capability Register 2 */
++ reg = IFX_REG_R32(PCIE_PVC2(pcie_port));
++ reg &= ~PCIE_PVC2_VC_ARB_WRR;
++ reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR;
++ IFX_REG_W32(reg, PCIE_PVC2(pcie_port));
++
++ /* VC0 Resource Capability Register */
++ reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port));
++ reg &= ~PCIE_VC0_RC_REJECT_SNOOP;
++ IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port));
++
++ pcie_port_logic_setup(pcie_port);
++}
++
++static int ifx_pcie_wait_phy_link_up(int pcie_port)
++{
++#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 /* XXX, tunable */
++ int i;
++
++ /* Wait for PHY link is up */
++ for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) {
++ if (ifx_pcie_link_up(pcie_port)) {
++ break;
++ }
++ udelay(100);
++ }
++ if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) {
++ printk(KERN_ERR "%s timeout\n", __func__);
++ return -1;
++ }
++
++ /* Check data link up or not */
++ if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) {
++ printk(KERN_ERR "%s DLL link is still down\n", __func__);
++ return -1;
++ }
++
++ /* Check Data link active or not */
++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) {
++ printk(KERN_ERR "%s DLL is not active\n", __func__);
++ return -1;
++ }
++ return 0;
++}
++
++static inline int pcie_app_loigc_setup(int pcie_port)
++{
++ /* supress ahb bus errrors */
++ IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port));
++
++ /* Pull PCIe EP out of reset */
++ pcie_device_rst_deassert(pcie_port);
++
++ /* Start LTSSM training between RC and EP */
++ pcie_ltssm_enable(pcie_port);
++
++ /* Check PHY status after enabling LTSSM */
++ if (ifx_pcie_wait_phy_link_up(pcie_port) != 0)
++ return -1;
++
++ return 0;
++}
++
++/*
++ * The numbers below are directly from the PCIe spec table 3-4/5.
++ */
++static inline void pcie_replay_time_update(int pcie_port)
++{
++ u32 reg;
++ int nlw;
++ int rtl;
++
++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port));
++
++ nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH);
++ switch (nlw) {
++ case PCIE_MAX_LENGTH_WIDTH_X1:
++ rtl = 1677;
++ break;
++ case PCIE_MAX_LENGTH_WIDTH_X2:
++ rtl = 867;
++ break;
++ case PCIE_MAX_LENGTH_WIDTH_X4:
++ rtl = 462;
++ break;
++ case PCIE_MAX_LENGTH_WIDTH_X8:
++ rtl = 258;
++ break;
++ default:
++ rtl = 1677;
++ break;
++ }
++ reg = IFX_REG_R32(PCIE_ALTRT(pcie_port));
++ reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT;
++ reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT);
++ IFX_REG_W32(reg, PCIE_ALTRT(pcie_port));
++}
++
++/*
++ * Table 359 Enhanced Configuration Address Mapping1)
++ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1
++ * Memory Address PCI Express Configuration Space
++ * A[(20+n-1):20] Bus Number 1 < n < 8
++ * A[19:15] Device Number
++ * A[14:12] Function Number
++ * A[11:8] Extended Register Number
++ * A[7:2] Register Number
++ * A[1:0] Along with size of the access, used to generate Byte Enables
++ * For VR9, only the address bits [22:0] are mapped to the configuration space:
++ * . Address bits [22:20] select the target bus (1-of-8)1)
++ * . Address bits [19:15] select the target device (1-of-32) on the bus
++ * . Address bits [14:12] select the target function (1-of-8) within the device.
++ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space
++ * . Address bits [1:0] define the start byte location within the selected dword.
++ */
++static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where)
++{
++ u32 addr;
++ u8 bus;
++
++ if (!bus_num) {
++ /* type 0 */
++ addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3);
++ } else {
++ bus = bus_num;
++ /* type 1, only support 8 buses */
++ addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) |
++ ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3);
++ }
++ return addr;
++}
++
++static int pcie_valid_config(int pcie_port, int bus, int dev)
++{
++ /* RC itself */
++ if ((bus == 0) && (dev == 0)) {
++ return 1;
++ }
++
++ /* No physical link */
++ if (!ifx_pcie_link_up(pcie_port)) {
++ return 0;
++ }
++
++ /* Bus zero only has RC itself
++ * XXX, check if EP will be integrated
++ */
++ if ((bus == 0) && (dev != 0)) {
++ return 0;
++ }
++
++ /* Maximum 8 buses supported for VRX */
++ if (bus > 9) {
++ return 0;
++ }
++
++ /*
++ * PCIe is PtP link, one bus only supports only one device
++ * except bus zero and PCIe switch which is virtual bus device
++ * The following two conditions really depends on the system design
++ * and attached the device.
++ * XXX, how about more new switch
++ */
++ if ((bus == 1) && (dev != 0)) {
++ return 0;
++ }
++
++ if ((bus >= 3) && (dev != 0)) {
++ return 0;
++ }
++ return 1;
++}
++
++static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg)
++{
++ return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg));
++}
++
++static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val)
++{
++ IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg));
++}
++
++static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg)
++{
++ return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg));
++}
++
++static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val)
++{
++ IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg));
++}
++
++u32 ifx_pcie_bus_enum_read_hack(int where, u32 value)
++{
++ u32 tvalue = value;
++
++ if (where == PCI_PRIMARY_BUS) {
++ u8 primary, secondary, subordinate;
++
++ primary = tvalue & 0xFF;
++ secondary = (tvalue >> 8) & 0xFF;
++ subordinate = (tvalue >> 16) & 0xFF;
++ primary += pcibios_1st_host_bus_nr();
++ secondary += pcibios_1st_host_bus_nr();
++ subordinate += pcibios_1st_host_bus_nr();
++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16);
++ }
++ return tvalue;
++}
++
++u32 ifx_pcie_bus_enum_write_hack(int where, u32 value)
++{
++ u32 tvalue = value;
++
++ if (where == PCI_PRIMARY_BUS) {
++ u8 primary, secondary, subordinate;
++
++ primary = tvalue & 0xFF;
++ secondary = (tvalue >> 8) & 0xFF;
++ subordinate = (tvalue >> 16) & 0xFF;
++ if (primary > 0 && primary != 0xFF) {
++ primary -= pcibios_1st_host_bus_nr();
++ }
++
++ if (secondary > 0 && secondary != 0xFF) {
++ secondary -= pcibios_1st_host_bus_nr();
++ }
++ if (subordinate > 0 && subordinate != 0xFF) {
++ subordinate -= pcibios_1st_host_bus_nr();
++ }
++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16);
++ }
++ else if (where == PCI_SUBORDINATE_BUS) {
++ u8 subordinate = tvalue & 0xFF;
++
++ subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0;
++ tvalue = subordinate;
++ }
++ return tvalue;
++}
++
++static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn,
++ int where, int size, u32 *value)
++{
++ u32 data = 0;
++ int bus_number = bus->number;
++ static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
++ int ret = PCIBIOS_SUCCESSFUL;
++ struct ifx_pci_controller *ctrl = bus->sysdata;
++ int pcie_port = ctrl->port;
++
++ if (unlikely(size != 1 && size != 2 && size != 4)){
++ ret = PCIBIOS_BAD_REGISTER_NUMBER;
++ goto out;
++ }
++
++ /* Make sure the address is aligned to natural boundary */
++ if (unlikely(((size - 1) & where))) {
++ ret = PCIBIOS_BAD_REGISTER_NUMBER;
++ goto out;
++ }
++
++ /*
++ * If we are second controller, we have to cheat OS so that it assume
++ * its bus number starts from 0 in host controller
++ */
++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port);
++
++ /*
++ * We need to force the bus number to be zero on the root
++ * bus. Linux numbers the 2nd root bus to start after all
++ * busses on root 0.
++ */
++ if (bus->parent == NULL) {
++ bus_number = 0;
++ }
++
++ /*
++ * PCIe only has a single device connected to it. It is
++ * always device ID 0. Don't bother doing reads for other
++ * device IDs on the first segment.
++ */
++ if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) {
++ ret = PCIBIOS_FUNC_NOT_SUPPORTED;
++ goto out;
++ }
++
++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) {
++ *value = 0xffffffff;
++ ret = PCIBIOS_DEVICE_NOT_FOUND;
++ goto out;
++ }
++
++ PCIE_IRQ_LOCK(ifx_pcie_lock);
++ if (bus_number == 0) { /* RC itself */
++ u32 t;
++
++ t = (where & ~3);
++ data = ifx_pcie_rc_cfg_rd(pcie_port, t);
++ } else {
++ u32 addr = pcie_bus_addr(bus_number, devfn, where);
++
++ data = ifx_pcie_cfg_rd(pcie_port, addr);
++ #ifdef CONFIG_IFX_PCIE_HW_SWAP
++ data = le32_to_cpu(data);
++ #endif /* CONFIG_IFX_PCIE_HW_SWAP */
++ }
++ /* To get a correct PCI topology, we have to restore the bus number to OS */
++ data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1);
++
++ PCIE_IRQ_UNLOCK(ifx_pcie_lock);
++
++ *value = (data >> (8 * (where & 3))) & mask[size & 7];
++out:
++ return ret;
++}
++
++static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value)
++{
++ u32 shift;
++ u32 tdata = data;
++
++ switch (size) {
++ case 1:
++ shift = (where & 0x3) << 3;
++ tdata &= ~(0xffU << shift);
++ tdata |= ((value & 0xffU) << shift);
++ break;
++ case 2:
++ shift = (where & 3) << 3;
++ tdata &= ~(0xffffU << shift);
++ tdata |= ((value & 0xffffU) << shift);
++ break;
++ case 4:
++ tdata = value;
++ break;
++ }
++ return tdata;
++}
++
++static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn,
++ int where, int size, u32 value)
++{
++ int bus_number = bus->number;
++ int ret = PCIBIOS_SUCCESSFUL;
++ struct ifx_pci_controller *ctrl = bus->sysdata;
++ int pcie_port = ctrl->port;
++ u32 tvalue = value;
++ u32 data;
++
++ /* Make sure the address is aligned to natural boundary */
++ if (unlikely(((size - 1) & where))) {
++ ret = PCIBIOS_BAD_REGISTER_NUMBER;
++ goto out;
++ }
++ /*
++ * If we are second controller, we have to cheat OS so that it assume
++ * its bus number starts from 0 in host controller
++ */
++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port);
++
++ /*
++ * We need to force the bus number to be zero on the root
++ * bus. Linux numbers the 2nd root bus to start after all
++ * busses on root 0.
++ */
++ if (bus->parent == NULL) {
++ bus_number = 0;
++ }
++
++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) {
++ ret = PCIBIOS_DEVICE_NOT_FOUND;
++ goto out;
++ }
++
++ /* XXX, some PCIe device may need some delay */
++ PCIE_IRQ_LOCK(ifx_pcie_lock);
++
++ /*
++ * To configure the correct bus topology using native way, we have to cheat Os so that
++ * it can configure the PCIe hardware correctly.
++ */
++ tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0);
++
++ if (bus_number == 0) { /* RC itself */
++ u32 t;
++
++ t = (where & ~3);
++ data = ifx_pcie_rc_cfg_rd(pcie_port, t);
++
++ data = ifx_pcie_size_to_value(where, size, data, tvalue);
++
++ ifx_pcie_rc_cfg_wr(pcie_port, t, data);
++ } else {
++ u32 addr = pcie_bus_addr(bus_number, devfn, where);
++
++ data = ifx_pcie_cfg_rd(pcie_port, addr);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++ data = le32_to_cpu(data);
++#endif
++
++ data = ifx_pcie_size_to_value(where, size, data, tvalue);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++ data = cpu_to_le32(data);
++#endif
++ ifx_pcie_cfg_wr(pcie_port, addr, data);
++ }
++ PCIE_IRQ_UNLOCK(ifx_pcie_lock);
++out:
++ return ret;
++}
++
++static struct resource ifx_pcie_io_resource = {
++ .name = "PCIe0 I/O space",
++ .start = PCIE_IO_PHY_BASE,
++ .end = PCIE_IO_PHY_END,
++ .flags = IORESOURCE_IO,
++};
++
++static struct resource ifx_pcie_mem_resource = {
++ .name = "PCIe0 Memory space",
++ .start = PCIE_MEM_PHY_BASE,
++ .end = PCIE_MEM_PHY_END,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct pci_ops ifx_pcie_ops = {
++ .read = ifx_pcie_read_config,
++ .write = ifx_pcie_write_config,
++};
++
++static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = {
++ {
++ .pcic = {
++ .pci_ops = &ifx_pcie_ops,
++ .mem_resource = &ifx_pcie_mem_resource,
++ .io_resource = &ifx_pcie_io_resource,
++ },
++ .port = IFX_PCIE_PORT0,
++ },
++};
++
++#ifdef IFX_PCIE_ERROR_INT
++
++static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id)
++{
++ struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id;
++ int pcie_port = ctrl->port;
++ u32 reg;
++
++ pr_debug("PCIe RC error intr %d\n", irq);
++ reg = IFX_REG_R32(PCIE_IRNCR(pcie_port));
++ reg &= PCIE_RC_CORE_COMBINED_INT;
++ IFX_REG_W32(reg, PCIE_IRNCR(pcie_port));
++
++ return IRQ_HANDLED;
++}
++
++static int
++pcie_rc_core_int_init(int pcie_port)
++{
++ int ret;
++
++ /* Enable core interrupt */
++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port));
++
++ /* Clear it first */
++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port));
++ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0,
++ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]);
++ if (ret)
++ printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR);
++
++ return ret;
++}
++#endif
++
++int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin)
++{
++ u32 irq_bit = 0;
++ int irq = 0;
++ struct ifx_pci_controller *ctrl = dev->bus->sysdata;
++ int pcie_port = ctrl->port;
++
++ printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin);
++
++ if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) {
++ printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin);
++ return -1;
++ }
++
++ /* Pin index so minus one */
++ irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit;
++ irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq;
++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port));
++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port));
++ printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq);
++ return irq;
++}
++
++int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev)
++{
++ u16 config;
++#ifdef IFX_PCIE_ERROR_INT
++ u32 dconfig;
++ int pos;
++#endif
++
++ /* Enable reporting System errors and parity errors on all devices */
++ /* Enable parity checking and error reporting */
++ pci_read_config_word(dev, PCI_COMMAND, &config);
++ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE |
++ PCI_COMMAND_FAST_BACK*/;
++ pci_write_config_word(dev, PCI_COMMAND, config);
++
++ if (dev->subordinate) {
++ /* Set latency timers on sub bridges */
++ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */
++ /* More bridge error detection */
++ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
++ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
++ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
++ }
++#ifdef IFX_PCIE_ERROR_INT
++ /* Enable the PCIe normal error reporting */
++ pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
++ if (pos) {
++
++ /* Disable system error generation in response to error messages */
++ pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config);
++ config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE);
++ pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config);
++
++ /* Clear PCIE Capability's Device Status */
++ pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config);
++ pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config);
++
++ /* Update Device Control */
++ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
++ /* Correctable Error Reporting */
++ config |= PCI_EXP_DEVCTL_CERE;
++ /* Non-Fatal Error Reporting */
++ config |= PCI_EXP_DEVCTL_NFERE;
++ /* Fatal Error Reporting */
++ config |= PCI_EXP_DEVCTL_FERE;
++ /* Unsupported Request */
++ config |= PCI_EXP_DEVCTL_URRE;
++ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
++ }
++
++ /* Find the Advanced Error Reporting capability */
++ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
++ if (pos) {
++ /* Clear Uncorrectable Error Status */
++ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig);
++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig);
++ /* Enable reporting of all uncorrectable errors */
++ /* Uncorrectable Error Mask - turned on bits disable errors */
++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
++ /*
++ * Leave severity at HW default. This only controls if
++ * errors are reported as uncorrectable or
++ * correctable, not if the error is reported.
++ */
++ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
++ /* Clear Correctable Error Status */
++ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
++ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
++ /* Enable reporting of all correctable errors */
++ /* Correctable Error Mask - turned on bits disable errors */
++ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
++ /* Advanced Error Capabilities */
++ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
++ /* ECRC Generation Enable */
++ if (dconfig & PCI_ERR_CAP_ECRC_GENC) {
++ dconfig |= PCI_ERR_CAP_ECRC_GENE;
++ }
++ /* ECRC Check Enable */
++ if (dconfig & PCI_ERR_CAP_ECRC_CHKC) {
++ dconfig |= PCI_ERR_CAP_ECRC_CHKE;
++ }
++ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
++
++ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
++ /* Enable Root Port's interrupt in response to error messages */
++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
++ PCI_ERR_ROOT_CMD_COR_EN |
++ PCI_ERR_ROOT_CMD_NONFATAL_EN |
++ PCI_ERR_ROOT_CMD_FATAL_EN);
++ /* Clear the Root status register */
++ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
++ }
++#endif /* IFX_PCIE_ERROR_INT */
++ /* WAR, only 128 MRRS is supported, force all EPs to support this value */
++ pcie_set_readrq(dev, 128);
++ return 0;
++}
++
++static int
++pcie_rc_initialize(int pcie_port)
++{
++ int i;
++#define IFX_PCIE_PHY_LOOP_CNT 5
++
++ pcie_rcu_endian_setup(pcie_port);
++
++ pcie_ep_gpio_rst_init(pcie_port);
++
++ /*
++ * XXX, PCIe elastic buffer bug will cause not to be detected. One more
++ * reset PCIe PHY will solve this issue
++ */
++ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
++ /* Disable PCIe PHY Analog part for sanity check */
++ pcie_phy_pmu_disable(pcie_port);
++
++ pcie_phy_rst_assert(pcie_port);
++ pcie_phy_rst_deassert(pcie_port);
++
++ /* Make sure PHY PLL is stable */
++ udelay(20);
++
++ /* PCIe Core reset enabled, low active, sw programmed */
++ pcie_core_rst_assert(pcie_port);
++
++ /* Put PCIe EP in reset status */
++ pcie_device_rst_assert(pcie_port);
++
++ /* PCI PHY & Core reset disabled, high active, sw programmed */
++ pcie_core_rst_deassert(pcie_port);
++
++ /* Already in a quiet state, program PLL, enable PHY, check ready bit */
++ pcie_phy_clock_mode_setup(pcie_port);
++
++ /* Enable PCIe PHY and Clock */
++ pcie_core_pmu_setup(pcie_port);
++
++ /* Clear status registers */
++ pcie_status_register_clear(pcie_port);
++
++#ifdef CONFIG_PCI_MSI
++ pcie_msi_init(pcie_port);
++#endif /* CONFIG_PCI_MSI */
++ pcie_rc_cfg_reg_setup(pcie_port);
++
++ /* Once link is up, break out */
++ if (pcie_app_loigc_setup(pcie_port) == 0)
++ break;
++ }
++ if (i >= IFX_PCIE_PHY_LOOP_CNT) {
++ printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
++ return -EIO;
++ }
++ /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */
++ pcie_replay_time_update(pcie_port);
++ return 0;
++}
++
++static int __init ifx_pcie_bios_init(void)
++{
++ void __iomem *io_map_base;
++ int pcie_port;
++ int startup_port;
++
++ /* Enable AHB Master/ Slave */
++ pcie_ahb_pmu_setup();
++
++ startup_port = IFX_PCIE_PORT0;
++
++ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
++ if (pcie_rc_initialize(pcie_port) == 0) {
++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n",
++ __func__, PCIE_CFG_PORT_TO_BASE(pcie_port));
++ /* Otherwise, warning will pop up */
++ io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE);
++ if (io_map_base == NULL) {
++ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__);
++ return -ENOMEM;
++ }
++ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
++
++ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
++ /* XXX, clear error status */
++
++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n",
++ __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource,
++ &ifx_pcie_controller[pcie_port].pcic.io_resource);
++
++ #ifdef IFX_PCIE_ERROR_INT
++ pcie_rc_core_int_init(pcie_port);
++ #endif /* IFX_PCIE_ERROR_INT */
++ }
++ }
++
++ return 0;
++}
++arch_initcall(ifx_pcie_bios_init);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Chuanhua.Lei@infineon.com");
++MODULE_DESCRIPTION("Infineon builtin PCIe RC driver");
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie.h
+@@ -0,0 +1,131 @@
++/******************************************************************************
++**
++** FILE NAME : ifxmips_pcie.h
++** PROJECT : IFX UEIP for VRX200
++** MODULES : PCIe module
++**
++** DATE : 02 Mar 2009
++** AUTHOR : Lei Chuanhua
++** DESCRIPTION : PCIe Root Complex Driver
++** COPYRIGHT : Copyright (c) 2009
++** Infineon Technologies AG
++** Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++** HISTORY
++** $Version $Date $Author $Comment
++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version
++*******************************************************************************/
++#ifndef IFXMIPS_PCIE_H
++#define IFXMIPS_PCIE_H
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++#include "ifxmips_pci_common.h"
++#include "ifxmips_pcie_reg.h"
++
++/*!
++ \defgroup IFX_PCIE PCI Express bus driver module
++ \brief PCI Express IP module support VRX200
++*/
++
++/*!
++ \defgroup IFX_PCIE_OS OS APIs
++ \ingroup IFX_PCIE
++ \brief PCIe bus driver OS interface functions
++*/
++
++/*!
++ \file ifxmips_pcie.h
++ \ingroup IFX_PCIE
++ \brief header file for PCIe module common header file
++*/
++#define PCIE_IRQ_LOCK(lock) do { \
++ unsigned long flags; \
++ spin_lock_irqsave(&(lock), flags);
++#define PCIE_IRQ_UNLOCK(lock) \
++ spin_unlock_irqrestore(&(lock), flags); \
++} while (0)
++
++#define PCIE_MSG_MSI 0x00000001
++#define PCIE_MSG_ISR 0x00000002
++#define PCIE_MSG_FIXUP 0x00000004
++#define PCIE_MSG_READ_CFG 0x00000008
++#define PCIE_MSG_WRITE_CFG 0x00000010
++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG)
++#define PCIE_MSG_REG 0x00000020
++#define PCIE_MSG_INIT 0x00000040
++#define PCIE_MSG_ERR 0x00000080
++#define PCIE_MSG_PHY 0x00000100
++#define PCIE_MSG_ANY 0x000001ff
++
++#define IFX_PCIE_PORT0 0
++#define IFX_PCIE_PORT1 1
++
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++#define IFX_PCIE_CORE_NR 2
++#else
++#define IFX_PCIE_CORE_NR 1
++#endif
++
++#define IFX_PCIE_ERROR_INT
++
++//#define IFX_PCIE_DBG
++
++#if defined(IFX_PCIE_DBG)
++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \
++ ifx_pcie_debug((_fmt), ##args); \
++} while (0)
++
++#define INLINE
++#else
++#define IFX_PCIE_PRINT(_m, _fmt, args...) \
++ do {} while(0)
++#define INLINE inline
++#endif
++
++struct ifx_pci_controller {
++ struct pci_controller pcic;
++
++ /* RC specific, per host bus information */
++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */
++};
++
++typedef struct ifx_pcie_ir_irq {
++ const unsigned int irq;
++ const char name[16];
++}ifx_pcie_ir_irq_t;
++
++typedef struct ifx_pcie_legacy_irq{
++ const u32 irq_bit;
++ const int irq;
++}ifx_pcie_legacy_irq_t;
++
++typedef struct ifx_pcie_irq {
++ ifx_pcie_ir_irq_t ir_irq;
++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX];
++}ifx_pcie_irq_t;
++
++extern u32 g_pcie_debug_flag;
++extern void ifx_pcie_debug(const char *fmt, ...);
++extern void pcie_phy_clock_mode_setup(int pcie_port);
++extern void pcie_msi_pic_init(int pcie_port);
++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value);
++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value);
++
++#define CONFIG_VR9
++
++#ifdef CONFIG_VR9
++#include "ifxmips_pcie_vr9.h"
++#elif defined (CONFIG_AR10)
++#include "ifxmips_pcie_ar10.h"
++#else
++#error "PCIE: platform not defined"
++#endif /* CONFIG_VR9 */
++
++#endif /* IFXMIPS_PCIE_H */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_ar10.h
+@@ -0,0 +1,305 @@
++/****************************************************************************
++ Copyright (c) 2010
++ Lantiq Deutschland GmbH
++ Am Campeon 3; 85579 Neubiberg, Germany
++
++ For licensing information, see the file 'LICENSE' in the root folder of
++ this software module.
++
++ *****************************************************************************/
++/*!
++ \file ifxmips_pcie_ar10.h
++ \ingroup IFX_PCIE
++ \brief PCIe RC driver ar10 specific file
++*/
++
++#ifndef IFXMIPS_PCIE_AR10_H
++#define IFXMIPS_PCIE_AR10_H
++#ifndef AUTOCONF_INCLUDED
++#include <linux/config.h>
++#endif /* AUTOCONF_INCLUDED */
++#include <linux/types.h>
++#include <linux/delay.h>
++
++/* Project header file */
++#include <asm/ifx/ifx_types.h>
++#include <asm/ifx/ifx_pmu.h>
++#include <asm/ifx/ifx_gpio.h>
++#include <asm/ifx/ifx_ebu_led.h>
++
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++ ifx_ebu_led_enable();
++ if (pcie_port == 0) {
++ ifx_ebu_led_set_data(11, 1);
++ }
++ else {
++ ifx_ebu_led_set_data(12, 1);
++ }
++}
++
++static inline void pcie_ahb_pmu_setup(void)
++{
++ /* XXX, moved to CGU to control AHBM */
++}
++
++static inline void pcie_rcu_endian_setup(int pcie_port)
++{
++ u32 reg;
++
++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++ /* Inbound, big endian */
++ reg |= IFX_RCU_BE_AHB4S;
++ if (pcie_port == 0) {
++ reg |= IFX_RCU_BE_PCIE0M;
++
++ #ifdef CONFIG_IFX_PCIE_HW_SWAP
++ /* Outbound, software swap needed */
++ reg |= IFX_RCU_BE_AHB3M;
++ reg &= ~IFX_RCU_BE_PCIE0S;
++ #else
++ /* Outbound little endian */
++ reg &= ~IFX_RCU_BE_AHB3M;
++ reg &= ~IFX_RCU_BE_PCIE0S;
++ #endif
++ }
++ else {
++ reg |= IFX_RCU_BE_PCIE1M;
++ #ifdef CONFIG_IFX_PCIE1_HW_SWAP
++ /* Outbound, software swap needed */
++ reg |= IFX_RCU_BE_AHB3M;
++ reg &= ~IFX_RCU_BE_PCIE1S;
++ #else
++ /* Outbound little endian */
++ reg &= ~IFX_RCU_BE_AHB3M;
++ reg &= ~IFX_RCU_BE_PCIE1S;
++ #endif
++ }
++
++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
++}
++
++static inline void pcie_phy_pmu_enable(int pcie_port)
++{
++ if (pcie_port == 0) { /* XXX, should use macro*/
++ PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE);
++ }
++ else {
++ PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE);
++ }
++}
++
++static inline void pcie_phy_pmu_disable(int pcie_port)
++{
++ if (pcie_port == 0) { /* XXX, should use macro*/
++ PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE);
++ }
++ else {
++ PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE);
++ }
++}
++
++static inline void pcie_pdi_big_endian(int pcie_port)
++{
++ u32 reg;
++
++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++ if (pcie_port == 0) {
++ /* Config AHB->PCIe and PDI endianness */
++ reg |= IFX_RCU_BE_PCIE0_PDI;
++ }
++ else {
++ /* Config AHB->PCIe and PDI endianness */
++ reg |= IFX_RCU_BE_PCIE1_PDI;
++ }
++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++}
++
++static inline void pcie_pdi_pmu_enable(int pcie_port)
++{
++ if (pcie_port == 0) {
++ /* Enable PDI to access PCIe PHY register */
++ PDI0_PMU_SETUP(IFX_PMU_ENABLE);
++ }
++ else {
++ PDI1_PMU_SETUP(IFX_PMU_ENABLE);
++ }
++}
++
++static inline void pcie_core_rst_assert(int pcie_port)
++{
++ u32 reg;
++
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++
++ /* Reset Core, bit 22 */
++ if (pcie_port == 0) {
++ reg |= 0x00400000;
++ }
++ else {
++ reg |= 0x08000000; /* Bit 27 */
++ }
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_core_rst_deassert(int pcie_port)
++{
++ u32 reg;
++
++ /* Make sure one micro-second delay */
++ udelay(1);
++
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++ if (pcie_port == 0) {
++ reg &= ~0x00400000; /* bit 22 */
++ }
++ else {
++ reg &= ~0x08000000; /* Bit 27 */
++ }
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_assert(int pcie_port)
++{
++ u32 reg;
++
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++ if (pcie_port == 0) {
++ reg |= 0x00001000; /* Bit 12 */
++ }
++ else {
++ reg |= 0x00002000; /* Bit 13 */
++ }
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_deassert(int pcie_port)
++{
++ u32 reg;
++
++ /* Make sure one micro-second delay */
++ udelay(1);
++
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++ if (pcie_port == 0) {
++ reg &= ~0x00001000; /* Bit 12 */
++ }
++ else {
++ reg &= ~0x00002000; /* Bit 13 */
++ }
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++ if (pcie_port == 0) {
++ ifx_ebu_led_set_data(11, 0);
++ }
++ else {
++ ifx_ebu_led_set_data(12, 0);
++ }
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++ mdelay(100);
++ if (pcie_port == 0) {
++ ifx_ebu_led_set_data(11, 1);
++ }
++ else {
++ ifx_ebu_led_set_data(12, 1);
++ }
++ ifx_ebu_led_disable();
++}
++
++static inline void pcie_core_pmu_setup(int pcie_port)
++{
++ if (pcie_port == 0) {
++ PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
++ }
++ else {
++ PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
++ }
++}
++
++static inline void pcie_msi_init(int pcie_port)
++{
++ pcie_msi_pic_init(pcie_port);
++ if (pcie_port == 0) {
++ MSI0_PMU_SETUP(IFX_PMU_ENABLE);
++ }
++ else {
++ MSI1_PMU_SETUP(IFX_PMU_ENABLE);
++ }
++}
++
++static inline u32
++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)
++{
++ u32 tbus_number = bus_number;
++
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */
++ if (pcibios_host_nr() > 1) {
++ tbus_number -= pcibios_1st_host_bus_nr();
++ }
++ }
++#endif /* CONFIG_IFX_PCI */
++ return tbus_number;
++}
++
++static struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn)
++{
++ struct pci_dev *dev;
++
++ list_for_each_entry(dev, &bus->devices, bus_list) {
++ if (dev->devfn == devfn)
++ goto out;
++ }
++
++ dev = NULL;
++ out:
++ pci_dev_get(dev);
++ return dev;
++}
++
++static inline u32
++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)
++{
++ struct pci_dev *pdev;
++ u32 tvalue = value;
++
++ /* Sanity check */
++ pdev = ifx_pci_get_slot(bus, devfn);
++ if (pdev == NULL) {
++ return tvalue;
++ }
++
++ /* Only care about PCI bridge */
++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
++ return tvalue;
++ }
++
++ if (read) { /* Read hack */
++ #ifdef CONFIG_IFX_PCIE_2ND_CORE
++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */
++ if (pcibios_host_nr() > 1) {
++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);
++ }
++ }
++ #endif /* CONFIG_IFX_PCIE_2ND_CORE */
++ }
++ else { /* Write hack */
++ #ifdef CONFIG_IFX_PCIE_2ND_CORE
++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */
++ if (pcibios_host_nr() > 1) {
++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);
++ }
++ }
++ #endif
++ }
++ return tvalue;
++}
++
++#endif /* IFXMIPS_PCIE_AR10_H */
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_msi.c
+@@ -0,0 +1,391 @@
++/******************************************************************************
++**
++** FILE NAME : ifxmips_pcie_msi.c
++** PROJECT : IFX UEIP for VRX200
++** MODULES : PCI MSI sub module
++**
++** DATE : 02 Mar 2009
++** AUTHOR : Lei Chuanhua
++** DESCRIPTION : PCIe MSI Driver
++** COPYRIGHT : Copyright (c) 2009
++** Infineon Technologies AG
++** Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++** HISTORY
++** $Date $Author $Comment
++** 02 Mar,2009 Lei Chuanhua Initial version
++*******************************************************************************/
++/*!
++ \defgroup IFX_PCIE_MSI MSI OS APIs
++ \ingroup IFX_PCIE
++ \brief PCIe bus driver OS interface functions
++*/
++
++/*!
++ \file ifxmips_pcie_msi.c
++ \ingroup IFX_PCIE
++ \brief PCIe MSI OS interface file
++*/
++
++#ifndef AUTOCONF_INCLUDED
++#include <linux/config.h>
++#endif /* AUTOCONF_INCLUDED */
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/kernel_stat.h>
++#include <linux/pci.h>
++#include <linux/msi.h>
++#include <linux/module.h>
++#include <asm/bootinfo.h>
++#include <asm/irq.h>
++#include <asm/traps.h>
++
++#include <asm/ifx/ifx_types.h>
++#include <asm/ifx/ifx_regs.h>
++#include <asm/ifx/common_routines.h>
++#include <asm/ifx/irq.h>
++
++#include "ifxmips_pcie_reg.h"
++#include "ifxmips_pcie.h"
++
++#define IFX_MSI_IRQ_NUM 16
++
++enum {
++ IFX_PCIE_MSI_IDX0 = 0,
++ IFX_PCIE_MSI_IDX1,
++ IFX_PCIE_MSI_IDX2,
++ IFX_PCIE_MSI_IDX3,
++};
++
++typedef struct ifx_msi_irq_idx {
++ const int irq;
++ const int idx;
++}ifx_msi_irq_idx_t;
++
++struct ifx_msi_pic {
++ volatile u32 pic_table[IFX_MSI_IRQ_NUM];
++ volatile u32 pic_endian; /* 0x40 */
++};
++typedef struct ifx_msi_pic *ifx_msi_pic_t;
++
++typedef struct ifx_msi_irq {
++ const volatile ifx_msi_pic_t msi_pic_p;
++ const u32 msi_phy_base;
++ const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM];
++ /*
++ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
++ * in use.
++ */
++ u16 msi_free_irq_bitmask;
++
++ /*
++ * Each bit in msi_multiple_irq_bitmask tells that the device using
++ * this bit in msi_free_irq_bitmask is also using the next bit. This
++ * is used so we can disable all of the MSI interrupts when a device
++ * uses multiple.
++ */
++ u16 msi_multiple_irq_bitmask;
++}ifx_msi_irq_t;
++
++static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = {
++ {
++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE,
++ .msi_phy_base = PCIE_MSI_PHY_BASE,
++ .msi_irq_idx = {
++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
++ },
++ .msi_free_irq_bitmask = 0,
++ .msi_multiple_irq_bitmask= 0,
++ },
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++ {
++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE,
++ .msi_phy_base = PCIE1_MSI_PHY_BASE,
++ .msi_irq_idx = {
++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
++ },
++ .msi_free_irq_bitmask = 0,
++ .msi_multiple_irq_bitmask= 0,
++
++ },
++#endif /* CONFIG_IFX_PCIE_2ND_CORE */
++};
++
++/*
++ * This lock controls updates to msi_free_irq_bitmask,
++ * msi_multiple_irq_bitmask and pic register settting
++ */
++static DEFINE_SPINLOCK(ifx_pcie_msi_lock);
++
++void pcie_msi_pic_init(int pcie_port)
++{
++ spin_lock(&ifx_pcie_msi_lock);
++ msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN;
++ spin_unlock(&ifx_pcie_msi_lock);
++}
++
++/**
++ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
++ * \brief Called when a driver request MSI interrupts instead of the
++ * legacy INT A-D. This routine will allocate multiple interrupts
++ * for MSI devices that support them. A device can override this by
++ * programming the MSI control bits [6:4] before calling
++ * pci_enable_msi().
++ *
++ * \param[in] pdev Device requesting MSI interrupts
++ * \param[in] desc MSI descriptor
++ *
++ * \return -EINVAL Invalid pcie root port or invalid msi bit
++ * \return 0 OK
++ * \ingroup IFX_PCIE_MSI
++ */
++int
++arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
++{
++ int irq, pos;
++ u16 control;
++ int irq_idx;
++ int irq_step;
++ int configured_private_bits;
++ int request_private_bits;
++ struct msi_msg msg;
++ u16 search_mask;
++ struct ifx_pci_controller *ctrl = pdev->bus->sysdata;
++ int pcie_port = ctrl->port;
++
++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev));
++
++ /* XXX, skip RC MSI itself */
++ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__);
++ return -EINVAL;
++ }
++
++ /*
++ * Read the MSI config to figure out how many IRQs this device
++ * wants. Most devices only want 1, which will give
++ * configured_private_bits and request_private_bits equal 0.
++ */
++ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control);
++
++ /*
++ * If the number of private bits has been configured then use
++ * that value instead of the requested number. This gives the
++ * driver the chance to override the number of interrupts
++ * before calling pci_enable_msi().
++ */
++ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
++ if (configured_private_bits == 0) {
++ /* Nothing is configured, so use the hardware requested size */
++ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
++ }
++ else {
++ /*
++ * Use the number of configured bits, assuming the
++ * driver wanted to override the hardware request
++ * value.
++ */
++ request_private_bits = configured_private_bits;
++ }
++
++ /*
++ * The PCI 2.3 spec mandates that there are at most 32
++ * interrupts. If this device asks for more, only give it one.
++ */
++ if (request_private_bits > 5) {
++ request_private_bits = 0;
++ }
++again:
++ /*
++ * The IRQs have to be aligned on a power of two based on the
++ * number being requested.
++ */
++ irq_step = (1 << request_private_bits);
++
++ /* Mask with one bit for each IRQ */
++ search_mask = (1 << irq_step) - 1;
++
++ /*
++ * We're going to search msi_free_irq_bitmask_lock for zero
++ * bits. This represents an MSI interrupt number that isn't in
++ * use.
++ */
++ spin_lock(&ifx_pcie_msi_lock);
++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) {
++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) {
++ msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos;
++ msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos;
++ break;
++ }
++ }
++ spin_unlock(&ifx_pcie_msi_lock);
++
++ /* Make sure the search for available interrupts didn't fail */
++ if (pos >= IFX_MSI_IRQ_NUM) {
++ if (request_private_bits) {
++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free "
++ "interrupts, trying just one", __func__, 1 << request_private_bits);
++ request_private_bits = 0;
++ goto again;
++ }
++ else {
++ printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__);
++ return -EINVAL;
++ }
++ }
++ irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq;
++ irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx;
++
++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx);
++
++ /*
++ * Initialize MSI. This has to match the memory-write endianess from the device
++ * Address bits [23:12]
++ */
++ spin_lock(&ifx_pcie_msi_lock);
++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) |
++ SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) |
++ SM((1 << pos), IFX_MSI_PIC_MSG_DATA);
++
++ /* Enable this entry */
++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE;
++ spin_unlock(&ifx_pcie_msi_lock);
++
++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n",
++ pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]);
++
++ /* Update the number of IRQs the device has available to it */
++ control &= ~PCI_MSI_FLAGS_QSIZE;
++ control |= (request_private_bits << 4);
++ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control);
++
++ set_irq_msi(irq, desc);
++ msg.address_hi = 0x0;
++ msg.address_lo = msi_irqs[pcie_port].msi_phy_base;
++ msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA);
++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data);
++
++ write_msi_msg(irq, &msg);
++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__);
++ return 0;
++}
++
++static int
++pcie_msi_irq_to_port(unsigned int irq, int *port)
++{
++ int ret = 0;
++
++ if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 ||
++ irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) {
++ *port = IFX_PCIE_PORT0;
++ }
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++ else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 ||
++ irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) {
++ *port = IFX_PCIE_PORT1;
++ }
++#endif /* CONFIG_IFX_PCIE_2ND_CORE */
++ else {
++ printk(KERN_ERR "%s: Attempted to teardown illegal "
++ "MSI interrupt (%d)\n", __func__, irq);
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++/**
++ * \fn void arch_teardown_msi_irq(unsigned int irq)
++ * \brief Called when a device no longer needs its MSI interrupts. All
++ * MSI interrupts for the device are freed.
++ *
++ * \param irq The devices first irq number. There may be multple in sequence.
++ * \return none
++ * \ingroup IFX_PCIE_MSI
++ */
++void
++arch_teardown_msi_irq(unsigned int irq)
++{
++ int pos;
++ int number_irqs;
++ u16 bitmask;
++ int pcie_port;
++
++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__);
++
++ BUG_ON(irq > INT_NUM_IM4_IRL31);
++
++ if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) {
++ return;
++ }
++
++ /* Shift the mask to the correct bit location, not always correct
++ * Probally, the first match will be chosen.
++ */
++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) {
++ if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq)
++ && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) {
++ break;
++ }
++ }
++ if (pos >= IFX_MSI_IRQ_NUM) {
++ printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__);
++ return;
++ }
++ spin_lock(&ifx_pcie_msi_lock);
++ /* Disable this entry */
++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE;
++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA);
++ spin_unlock(&ifx_pcie_msi_lock);
++ /*
++ * Count the number of IRQs we need to free by looking at the
++ * msi_multiple_irq_bitmask. Each bit set means that the next
++ * IRQ is also owned by this device.
++ */
++ number_irqs = 0;
++ while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) &&
++ (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) {
++ number_irqs++;
++ }
++ number_irqs++;
++
++ /* Mask with one bit for each IRQ */
++ bitmask = (1 << number_irqs) - 1;
++
++ bitmask <<= pos;
++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) {
++ printk(KERN_ERR "%s: Attempted to teardown MSI "
++ "interrupt (%d) not in use\n", __func__, irq);
++ return;
++ }
++ /* Checks are done, update the in use bitmask */
++ spin_lock(&ifx_pcie_msi_lock);
++ msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask;
++ msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1);
++ spin_unlock(&ifx_pcie_msi_lock);
++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__);
++}
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Chuanhua.Lei@infineon.com");
++MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver");
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_phy.c
+@@ -0,0 +1,478 @@
++/******************************************************************************
++**
++** FILE NAME : ifxmips_pcie_phy.c
++** PROJECT : IFX UEIP for VRX200
++** MODULES : PCIe PHY sub module
++**
++** DATE : 14 May 2009
++** AUTHOR : Lei Chuanhua
++** DESCRIPTION : PCIe Root Complex Driver
++** COPYRIGHT : Copyright (c) 2009
++** Infineon Technologies AG
++** Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++** HISTORY
++** $Version $Date $Author $Comment
++** 0.0.1 14 May,2009 Lei Chuanhua Initial version
++*******************************************************************************/
++/*!
++ \file ifxmips_pcie_phy.c
++ \ingroup IFX_PCIE
++ \brief PCIe PHY PLL register programming source file
++*/
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <asm/paccess.h>
++#include <linux/delay.h>
++
++#include "ifxmips_pcie_reg.h"
++#include "ifxmips_pcie.h"
++
++/* PCIe PDI only supports 16 bit operation */
++
++#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \
++ ((*(volatile u16 *) (__addr)) = (__data))
++
++#define IFX_PCIE_PHY_REG_READ16(__addr) \
++ (*(volatile u16 *) (__addr))
++
++#define IFX_PCIE_PHY_REG16(__addr) \
++ (*(volatile u16 *) (__addr))
++
++#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \
++ u16 read_data; \
++ u16 write_data; \
++ read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \
++ write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\
++ IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \
++} while (0)
++
++#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */
++
++//#define IFX_PCI_PHY_REG_DUMP
++
++#ifdef IFX_PCI_PHY_REG_DUMP
++static void
++pcie_phy_reg_dump(int pcie_port)
++{
++ printk("PLL REGFILE\n");
++ printk("PCIE_PHY_PLL_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port)));
++ printk("PCIE_PHY_PLL_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port)));
++ printk("PCIE_PHY_PLL_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port)));
++ printk("PCIE_PHY_PLL_CTRL4 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port)));
++ printk("PCIE_PHY_PLL_CTRL5 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port)));
++ printk("PCIE_PHY_PLL_CTRL6 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port)));
++ printk("PCIE_PHY_PLL_CTRL7 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port)));
++ printk("PCIE_PHY_PLL_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port)));
++ printk("PCIE_PHY_PLL_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port)));
++ printk("PCIE_PHY_PLL_A_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port)));
++ printk("PCIE_PHY_PLL_STATUS 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)));
++
++ printk("TX1 REGFILE\n");
++ printk("PCIE_PHY_TX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port)));
++ printk("PCIE_PHY_TX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port)));
++ printk("PCIE_PHY_TX1_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port)));
++ printk("PCIE_PHY_TX1_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port)));
++ printk("PCIE_PHY_TX1_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port)));
++ printk("PCIE_PHY_TX1_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port)));
++ printk("PCIE_PHY_TX1_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port)));
++ printk("PCIE_PHY_TX1_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port)));
++
++ printk("TX2 REGFILE\n");
++ printk("PCIE_PHY_TX2_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port)));
++ printk("PCIE_PHY_TX2_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port)));
++ printk("PCIE_PHY_TX2_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port)));
++ printk("PCIE_PHY_TX2_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port)));
++ printk("PCIE_PHY_TX2_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port)));
++ printk("PCIE_PHY_TX2_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port)));
++ printk("PCIE_PHY_TX2_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port)));
++
++ printk("RX1 REGFILE\n");
++ printk("PCIE_PHY_RX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port)));
++ printk("PCIE_PHY_RX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port)));
++ printk("PCIE_PHY_RX1_CDR 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port)));
++ printk("PCIE_PHY_RX1_EI 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port)));
++ printk("PCIE_PHY_RX1_A_CTRL 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port)));
++}
++#endif /* IFX_PCI_PHY_REG_DUMP */
++
++static void
++pcie_phy_comm_setup(int pcie_port)
++{
++ /* PLL Setting */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF);
++
++ /* increase the bias reference voltage */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF);
++
++ /* Endcnt */
++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF);
++
++ /* force */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008);
++
++ /* predrv_ser_en */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF);
++
++ /* ctrl_lim */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF);
++
++ /* ctrl */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00);
++
++ /* predrv_ser_en */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00);
++
++ /* RTERM*/
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF);
++
++ /* Improved 100MHz clock output */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF);
++
++ /* Reduced CDR BW to avoid glitches */
++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF);
++}
++
++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++static void
++pcie_phy_36mhz_mode_setup(int pcie_port)
++{
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++ pcie_phy_reg_dump(pcie_port);
++#endif
++
++ /* en_ext_mmd_div_ratio */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
++
++ /* ext_mmd_div_ratio*/
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
++
++ /* pll_ensdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
++
++ /* en_const_sdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
++
++ /* mmd */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
++
++ /* lf_mode */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
++
++ /* const_sdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
++
++ /* const sdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
++
++ /* pllmod */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF);
++
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */
++
++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE
++static void
++pcie_phy_36mhz_ssc_mode_setup(int pcie_port)
++{
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++ pcie_phy_reg_dump(pcie_port);
++#endif
++
++ /* PLL Setting */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF);
++
++ /* Increase the bias reference voltage */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF);
++
++ /* Endcnt */
++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF);
++
++ /* Force */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008);
++
++ /* Predrv_ser_en */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF);
++
++ /* ctrl_lim */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF);
++
++ /* ctrl */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00);
++
++ /* predrv_ser_en */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00);
++
++ /* RTERM*/
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF);
++
++ /* en_ext_mmd_div_ratio */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
++
++ /* ext_mmd_div_ratio*/
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
++
++ /* pll_ensdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400);
++
++ /* en_const_sdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
++
++ /* mmd */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
++
++ /* lf_mode */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
++
++ /* const_sdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
++
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100);
++ /* const sdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
++
++ /* pllmod */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF);
++
++ /* improved 100MHz clock output */
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF);
++
++ /* reduced CDR BW to avoid glitches */
++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF);
++
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */
++
++#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE
++static void
++pcie_phy_25mhz_mode_setup(int pcie_port)
++{
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++ pcie_phy_reg_dump(pcie_port);
++#endif
++ /* en_const_sdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
++
++ /* pll_ensdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200);
++
++ /* en_ext_mmd_div_ratio*/
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002);
++
++ /* ext_mmd_div_ratio*/
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070);
++
++ /* mmd */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000);
++
++ /* lf_mode */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000);
++
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */
++
++#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE
++static void
++pcie_phy_100mhz_mode_setup(int pcie_port)
++{
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port);
++#ifdef IFX_PCI_PHY_REG_DUMP
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n");
++ pcie_phy_reg_dump(pcie_port);
++#endif
++ /* en_ext_mmd_div_ratio */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);
++
++ /* ext_mmd_div_ratio*/
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);
++
++ /* pll_ensdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);
++
++ /* en_const_sdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);
++
++ /* mmd */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);
++
++ /* lf_mode */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);
++
++ /* const_sdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);
++
++ /* const sdm */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);
++
++ /* pllmod */
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF);
++
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port);
++}
++#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */
++
++static int
++pcie_phy_wait_startup_ready(int pcie_port)
++{
++ int i;
++
++ for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) {
++ if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) {
++ break;
++ }
++ udelay(10);
++ }
++ if (i >= IFX_PCIE_PLL_TIMEOUT) {
++ printk(KERN_ERR "%s PLL Link timeout\n", __func__);
++ return -1;
++ }
++ return 0;
++}
++
++static void
++pcie_phy_load_enable(int pcie_port, int slice)
++{
++ /* Set the load_en of tx/rx slice to '1' */
++ switch (slice) {
++ case 1:
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010);
++ break;
++ case 2:
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010);
++ break;
++ case 3:
++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002);
++ break;
++ }
++}
++
++static void
++pcie_phy_load_disable(int pcie_port, int slice)
++{
++ /* set the load_en of tx/rx slice to '0' */
++ switch (slice) {
++ case 1:
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010);
++ break;
++ case 2:
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010);
++ break;
++ case 3:
++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002);
++ break;
++ }
++}
++
++static void
++pcie_phy_load_war(int pcie_port)
++{
++ int slice;
++
++ for (slice = 1; slice < 4; slice++) {
++ pcie_phy_load_enable(pcie_port, slice);
++ udelay(1);
++ pcie_phy_load_disable(pcie_port, slice);
++ }
++}
++
++static void
++pcie_phy_tx2_modulation(int pcie_port)
++{
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF);
++ mdelay(1);
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF);
++}
++
++static void
++pcie_phy_tx1_modulation(int pcie_port)
++{
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF);
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF);
++ mdelay(1);
++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF);
++}
++
++static void
++pcie_phy_tx_modulation_war(int pcie_port)
++{
++ int i;
++
++#define PCIE_PHY_MODULATION_NUM 5
++ for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) {
++ pcie_phy_tx2_modulation(pcie_port);
++ pcie_phy_tx1_modulation(pcie_port);
++ }
++#undef PCIE_PHY_MODULATION_NUM
++}
++
++void
++pcie_phy_clock_mode_setup(int pcie_port)
++{
++ pcie_pdi_big_endian(pcie_port);
++
++ /* Enable PDI to access PCIe PHY register */
++ pcie_pdi_pmu_enable(pcie_port);
++
++ /* Configure PLL and PHY clock */
++ pcie_phy_comm_setup(pcie_port);
++
++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++ pcie_phy_36mhz_mode_setup(pcie_port);
++#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE)
++ pcie_phy_36mhz_ssc_mode_setup(pcie_port);
++#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE)
++ pcie_phy_25mhz_mode_setup(pcie_port);
++#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE)
++ pcie_phy_100mhz_mode_setup(pcie_port);
++#else
++ #error "PCIE PHY Clock Mode must be chosen first!!!!"
++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */
++
++ /* Enable PCIe PHY and make PLL setting take effect */
++ pcie_phy_pmu_enable(pcie_port);
++
++ /* Check if we are in startup_ready status */
++ pcie_phy_wait_startup_ready(pcie_port);
++
++ pcie_phy_load_war(pcie_port);
++
++ /* Apply TX modulation workarounds */
++ pcie_phy_tx_modulation_war(pcie_port);
++
++#ifdef IFX_PCI_PHY_REG_DUMP
++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n");
++ pcie_phy_reg_dump(pcie_port);
++#endif
++}
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_pm.c
+@@ -0,0 +1,176 @@
++/******************************************************************************
++**
++** FILE NAME : ifxmips_pcie_pm.c
++** PROJECT : IFX UEIP
++** MODULES : PCIE Root Complex Driver
++**
++** DATE : 21 Dec 2009
++** AUTHOR : Lei Chuanhua
++** DESCRIPTION : PCIE Root Complex Driver Power Managment
++** COPYRIGHT : Copyright (c) 2009
++** Lantiq Deutschland GmbH
++** Am Campeon 3, 85579 Neubiberg, Germany
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++**
++** HISTORY
++** $Date $Author $Comment
++** 21 Dec,2009 Lei Chuanhua First UEIP release
++*******************************************************************************/
++/*!
++ \defgroup IFX_PCIE_PM Power Management functions
++ \ingroup IFX_PCIE
++ \brief IFX PCIE Root Complex Driver power management functions
++*/
++
++/*!
++ \file ifxmips_pcie_pm.c
++ \ingroup IFX_PCIE
++ \brief source file for PCIE Root Complex Driver Power Management
++*/
++
++#ifndef EXPORT_SYMTAB
++#define EXPORT_SYMTAB
++#endif
++#ifndef AUTOCONF_INCLUDED
++#include <linux/config.h>
++#endif /* AUTOCONF_INCLUDED */
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <asm/system.h>
++
++/* Project header */
++#include <asm/ifx/ifx_types.h>
++#include <asm/ifx/ifx_regs.h>
++#include <asm/ifx/common_routines.h>
++#include <asm/ifx/ifx_pmcu.h>
++#include "ifxmips_pcie_pm.h"
++
++/**
++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState)
++ * \brief the callback function to request pmcu state in the power management hardware-dependent module
++ *
++ * \param pmcuState This parameter is a PMCU state.
++ *
++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state.
++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t
++ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState)
++{
++ switch(pmcuState)
++ {
++ case IFX_PMCU_STATE_D0:
++ return IFX_PMCU_RETURN_SUCCESS;
++ case IFX_PMCU_STATE_D1: // Not Applicable
++ return IFX_PMCU_RETURN_DENIED;
++ case IFX_PMCU_STATE_D2: // Not Applicable
++ return IFX_PMCU_RETURN_DENIED;
++ case IFX_PMCU_STATE_D3: // Module clock gating and Power gating
++ return IFX_PMCU_RETURN_SUCCESS;
++ default:
++ return IFX_PMCU_RETURN_DENIED;
++ }
++}
++
++/**
++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState)
++ * \brief the callback function to get pmcu state in the power management hardware-dependent module
++
++ * \param pmcuState Pointer to return power state.
++ *
++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state.
++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t
++ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState)
++{
++ return IFX_PMCU_RETURN_SUCCESS;
++}
++
++/**
++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule
++ *
++ * \param pmcuModule Module
++ * \param newState New state
++ * \param oldState Old state
++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state.
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t
++ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++{
++ return IFX_PMCU_RETURN_SUCCESS;
++}
++
++/**
++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule
++ *
++ * \param pmcuModule Module
++ * \param newState New state
++ * \param oldState Old state
++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully
++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state.
++ * \ingroup IFX_PCIE_PM
++ */
++static IFX_PMCU_RETURN_t
++ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)
++{
++ return IFX_PMCU_RETURN_SUCCESS;
++}
++
++/**
++ * \fn static void ifx_pcie_pmcu_init(void)
++ * \brief Register with central PMCU module
++ * \return none
++ * \ingroup IFX_PCIE_PM
++ */
++void
++ifx_pcie_pmcu_init(void)
++{
++ IFX_PMCU_REGISTER_t pmcuRegister;
++
++ /* XXX, hook driver context */
++
++ /* State function register */
++ memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t));
++ pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE;
++ pmcuRegister.pmcuModuleNr = 0;
++ pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change;
++ pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get;
++ pmcuRegister.pre = ifx_pcie_pmcu_prechange;
++ pmcuRegister.post= ifx_pcie_pmcu_postchange;
++ ifx_pmcu_register(&pmcuRegister);
++}
++
++/**
++ * \fn static void ifx_pcie_pmcu_exit(void)
++ * \brief Unregister with central PMCU module
++ *
++ * \return none
++ * \ingroup IFX_PCIE_PM
++ */
++void
++ifx_pcie_pmcu_exit(void)
++{
++ IFX_PMCU_REGISTER_t pmcuUnRegister;
++
++ /* XXX, hook driver context */
++
++ pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE;
++ pmcuUnRegister.pmcuModuleNr = 0;
++ ifx_pmcu_unregister(&pmcuUnRegister);
++}
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_pm.h
+@@ -0,0 +1,36 @@
++/******************************************************************************
++**
++** FILE NAME : ifxmips_pcie_pm.h
++** PROJECT : IFX UEIP
++** MODULES : PCIe Root Complex Driver
++**
++** DATE : 21 Dec 2009
++** AUTHOR : Lei Chuanhua
++** DESCRIPTION : PCIe Root Complex Driver Power Managment
++** COPYRIGHT : Copyright (c) 2009
++** Lantiq Deutschland GmbH
++** Am Campeon 3, 85579 Neubiberg, Germany
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++**
++** HISTORY
++** $Date $Author $Comment
++** 21 Dec,2009 Lei Chuanhua First UEIP release
++*******************************************************************************/
++/*!
++ \file ifxmips_pcie_pm.h
++ \ingroup IFX_PCIE
++ \brief header file for PCIe Root Complex Driver Power Management
++*/
++
++#ifndef IFXMIPS_PCIE_PM_H
++#define IFXMIPS_PCIE_PM_H
++
++void ifx_pcie_pmcu_init(void);
++void ifx_pcie_pmcu_exit(void);
++
++#endif /* IFXMIPS_PCIE_PM_H */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_reg.h
+@@ -0,0 +1,1001 @@
++/******************************************************************************
++**
++** FILE NAME : ifxmips_pcie_reg.h
++** PROJECT : IFX UEIP for VRX200
++** MODULES : PCIe module
++**
++** DATE : 02 Mar 2009
++** AUTHOR : Lei Chuanhua
++** DESCRIPTION : PCIe Root Complex Driver
++** COPYRIGHT : Copyright (c) 2009
++** Infineon Technologies AG
++** Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++** HISTORY
++** $Version $Date $Author $Comment
++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version
++*******************************************************************************/
++#ifndef IFXMIPS_PCIE_REG_H
++#define IFXMIPS_PCIE_REG_H
++/*!
++ \file ifxmips_pcie_reg.h
++ \ingroup IFX_PCIE
++ \brief header file for PCIe module register definition
++*/
++/* PCIe Address Mapping Base */
++#define PCIE_CFG_PHY_BASE 0x1D000000UL
++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE)
++#define PCIE_CFG_SIZE (8 * 1024 * 1024)
++
++#define PCIE_MEM_PHY_BASE 0x1C000000UL
++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE)
++#define PCIE_MEM_SIZE (16 * 1024 * 1024)
++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1)
++
++#define PCIE_IO_PHY_BASE 0x1D800000UL
++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE)
++#define PCIE_IO_SIZE (1 * 1024 * 1024)
++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1)
++
++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000)
++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900)
++#define PCIE_MSI_PHY_BASE 0x1F600000UL
++
++#define PCIE_PDI_PHY_BASE 0x1F106800UL
++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE)
++#define PCIE_PDI_SIZE 0x400
++
++#define PCIE1_CFG_PHY_BASE 0x19000000UL
++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE)
++#define PCIE1_CFG_SIZE (8 * 1024 * 1024)
++
++#define PCIE1_MEM_PHY_BASE 0x18000000UL
++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE)
++#define PCIE1_MEM_SIZE (16 * 1024 * 1024)
++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1)
++
++#define PCIE1_IO_PHY_BASE 0x19800000UL
++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE)
++#define PCIE1_IO_SIZE (1 * 1024 * 1024)
++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1)
++
++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000)
++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700)
++#define PCIE1_MSI_PHY_BASE 0x1F400000UL
++
++#define PCIE1_PDI_PHY_BASE 0x1F700400UL
++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE)
++#define PCIE1_PDI_SIZE 0x400
++
++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE))
++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE))
++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE))
++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE))
++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END))
++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE))
++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END))
++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG))
++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE))
++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE))
++
++/* PCIe Application Logic Register */
++/* RC Core Control Register */
++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10)
++/* This should be enabled after initializing configuratin registers
++ * Also should check link status retraining bit
++ */
++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */
++
++/* RC Core Debug Register */
++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14)
++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */
++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */
++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4
++
++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */
++#define PCIE_RC_DR_PM_DEV_STATE_S 9
++
++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */
++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */
++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */
++
++/* Current Power State Definition */
++enum {
++ PCIE_RC_DR_D0 = 0,
++ PCIE_RC_DR_D1, /* Not supported */
++ PCIE_RC_DR_D2, /* Not supported */
++ PCIE_RC_DR_D3,
++ PCIE_RC_DR_UN,
++};
++
++/* PHY Link Status Register */
++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18)
++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */
++
++/* Electromechanical Control Register */
++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C)
++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */
++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */
++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */
++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */
++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */
++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */
++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */
++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */
++
++/* Interrupt Status Register */
++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20)
++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */
++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */
++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */
++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */
++#define PCIE_IR_SR_AHB_LU_ERR_S 4
++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */
++#define PCIE_IR_SR_INT_MSG_NUM_S 9
++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */
++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27
++
++/* Message Control Register */
++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30)
++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */
++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */
++
++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34)
++
++/* Vendor-Defined Message Requester ID Register */
++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38)
++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF
++#define PCIE_VDM_RID_VDMRID_S 0
++
++/* ASPM Control Register */
++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40)
++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */
++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */
++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */
++
++/* Vendor Message DW0 Register */
++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50)
++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */
++#define PCIE_VM_MSG_DW0_TYPE_S 0
++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */
++#define PCIE_VM_MSG_DW0_FORMAT_S 5
++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */
++#define PCIE_VM_MSG_DW0_TC_S 12
++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */
++#define PCIE_VM_MSG_DW0_ATTR_S 18
++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */
++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */
++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */
++#define PCIE_VM_MSG_DW0_LEN_S 22
++
++/* Format Definition */
++enum {
++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/
++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */
++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */
++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */
++};
++
++/* Traffic Class Definition */
++enum {
++ PCIE_VM_MSG_TC0 = 0,
++ PCIE_VM_MSG_TC1,
++ PCIE_VM_MSG_TC2,
++ PCIE_VM_MSG_TC3,
++ PCIE_VM_MSG_TC4,
++ PCIE_VM_MSG_TC5,
++ PCIE_VM_MSG_TC6,
++ PCIE_VM_MSG_TC7,
++};
++
++/* Attributes Definition */
++enum {
++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */
++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */
++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/
++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */
++};
++
++/* Payload Size Definition */
++#define PCIE_VM_MSG_LEN_MIN 0
++#define PCIE_VM_MSG_LEN_MAX 1024
++
++/* Vendor Message DW1 Register */
++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54)
++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */
++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8
++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */
++#define PCIE_VM_MSG_DW1_CODE_S 16
++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */
++#define PCIE_VM_MSG_DW1_TAG_S 24
++
++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58)
++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C)
++
++/* Vendor Message Request Register */
++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60)
++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */
++
++
++/* AHB Slave Side Band Control Register */
++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70)
++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */
++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */
++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */
++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */
++#define PCIE_AHB_SSB_REQ_ATTR_S 3
++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */
++#define PCIE_AHB_SSB_REQ_TC_S 5
++
++/* AHB Master SideBand Ctrl Register */
++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74)
++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */
++#define PCIE_AHB_MSB_RESP_ATTR_S 0
++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */
++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */
++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */
++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */
++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */
++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6
++
++/* AHB Control Register, fixed bus enumeration exception */
++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78)
++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001
++
++/* Interrupt Enalbe Register */
++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4)
++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8)
++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC)
++
++/* PCIe interrupt enable/control/capture register definition */
++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */
++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */
++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */
++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */
++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */
++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */
++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */
++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */
++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */
++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */
++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */
++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */
++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */
++#define PCIE_IRN_INTA 0x00002000 /* INTA */
++#define PCIE_IRN_INTB 0x00004000 /* INTB */
++#define PCIE_IRN_INTC 0x00008000 /* INTC */
++#define PCIE_IRN_INTD 0x00010000 /* INTD */
++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */
++
++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \
++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\
++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \
++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \
++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT)
++/* PCIe RC Configuration Register */
++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00)
++
++/* Bit definition from pci_reg.h */
++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04)
++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08)
++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */
++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */
++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/
++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */
++
++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */
++/* Bus Number Register bits */
++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF
++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0
++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00
++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8
++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000
++#define PCIE_PNR_SUB_BUS_NUM_S 16
++
++/* IO Base/Limit Register bits */
++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */
++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001
++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0
++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4
++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12
++
++/* Non-prefetchable Memory Base/Limit Register bit */
++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */
++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0
++#define PCIE_MBML_MEM_BASE_ADDR_S 4
++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000
++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20
++
++/* Prefetchable Memory Base/Limit Register bit */
++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */
++#define PCIE_PMBL_64BIT_ADDR 0x00000001
++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0
++#define PCIE_PMBL_UPPER_12BIT_S 4
++#define PCIE_PMBL_E64MA 0x00010000
++#define PCIE_PMBL_END_ADDR 0xFFF00000
++#define PCIE_PMBL_END_ADDR_S 20
++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */
++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */
++
++/* I/O Base/Limit Upper 16 bits register */
++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16
++
++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34)
++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38)
++
++/* Interrupt and Secondary Bridge Control Register */
++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C)
++
++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF
++#define PCIE_INTRBCTRL_INT_LINE_S 0
++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00
++#define PCIE_INTRBCTRL_INT_PIN_S 8
++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */
++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */
++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */
++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */
++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */
++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */
++/* Others are read only */
++enum {
++ PCIE_INTRBCTRL_INT_NON = 0,
++ PCIE_INTRBCTRL_INTA,
++ PCIE_INTRBCTRL_INTB,
++ PCIE_INTRBCTRL_INTC,
++ PCIE_INTRBCTRL_INTD,
++};
++
++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40)
++
++/* Power Management Control and Status Register */
++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44)
++
++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */
++#define PCIE_PM_CSR_POWER_STATE_S 0
++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */
++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */
++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */
++
++/* MSI Capability Register for EP */
++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50)
++
++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */
++#define PCIE_MCAPR_MSI_CAP_ID_S 0
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8
++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */
++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */
++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17
++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */
++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20
++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */
++
++/* MSI Message Address Register */
++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54)
++
++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */
++
++/* MSI Message Upper Address Register */
++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58)
++
++/* MSI Message Data Register */
++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C)
++
++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */
++#define PCIE_MD_DATA_S 0
++
++/* PCI Express Capability Register */
++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70)
++
++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */
++#define PCIE_XCAP_ID_S 0
++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */
++#define PCIE_XCAP_NEXT_CAP_S 8
++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */
++#define PCIE_XCAP_VER_S 16
++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */
++#define PCIE_XCAP_DEV_PORT_TYPE_S 20
++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */
++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */
++#define PCIE_XCAP_MSG_INT_NUM_S 25
++
++/* Device Capability Register */
++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74)
++
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0
++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */
++#define PCIE_DCAP_PHANTOM_FUNC_S 3
++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */
++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */
++#define PCIE_DCAP_EP_L0S_LATENCY_S 6
++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */
++#define PCIE_DCAP_EP_L1_LATENCY_S 9
++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */
++
++/* Maximum payload size supported */
++enum {
++ PCIE_MAX_PAYLOAD_128 = 0,
++ PCIE_MAX_PAYLOAD_256,
++ PCIE_MAX_PAYLOAD_512,
++ PCIE_MAX_PAYLOAD_1024,
++ PCIE_MAX_PAYLOAD_2048,
++ PCIE_MAX_PAYLOAD_4096,
++};
++
++/* Device Control and Status Register */
++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78)
++
++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */
++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */
++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */
++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */
++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5
++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */
++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */
++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */
++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12
++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */
++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */
++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */
++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */
++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */
++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */
++
++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \
++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \
++ PCIE_DCTLSYS_UR_REQ_EN)
++
++/* Link Capability Register */
++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C)
++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */
++#define PCIE_LCAP_MAX_LINK_SPEED_S 0
++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */
++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4
++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */
++#define PCIE_LCAP_ASPM_LEVEL_S 10
++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */
++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12
++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */
++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15
++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */
++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */
++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */
++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */
++#define PCIE_LCAP_PORT_NUM_S 24
++
++/* Maximum Length width definition */
++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00
++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */
++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02
++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04
++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08
++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C
++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10
++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20
++
++/* Active State Link PM definition */
++enum {
++ PCIE_ASPM_RES0 = 0,
++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */
++ PCIE_ASPM_RES1,
++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */
++};
++
++/* L0s Exit Latency definition */
++enum {
++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */
++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */
++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */
++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */
++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */
++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */
++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */
++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */
++};
++
++/* L1 Exit Latency definition */
++enum {
++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */
++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */
++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */
++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */
++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */
++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */
++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */
++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */
++};
++
++/* Link Control and Status Register */
++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80)
++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */
++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0
++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/
++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */
++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */
++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */
++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */
++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */
++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */
++#define PCIE_LCTLSTS_LINK_SPEED_S 16
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20
++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */
++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */
++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */
++
++/* Slot Capabilities Register */
++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84)
++
++/* Slot Capabilities */
++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88)
++
++/* Root Control and Capability Register */
++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C)
++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */
++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */
++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */
++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */
++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \
++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR)
++/* Root Status Register */
++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90)
++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */
++#define PCIE_RSTS_PME_REQ_ID_S 0
++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */
++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */
++
++/* PCI Express Enhanced Capability Header */
++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100)
++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */
++#define PCIE_ENHANCED_CAP_ID_S 0
++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */
++#define PCIE_ENHANCED_CAP_VER_S 16
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20
++
++/* Uncorrectable Error Status Register */
++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104)
++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */
++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */
++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */
++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */
++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */
++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */
++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */
++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */
++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */
++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */
++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */
++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \
++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \
++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\
++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ)
++
++/* Uncorrectable Error Mask Register, Mask means no report */
++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108)
++
++/* Uncorrectable Error Severity Register */
++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C)
++
++/* Correctable Error Status Register */
++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110)
++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */
++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */
++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */
++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */
++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */
++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */
++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\
++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR)
++
++/* Correctable Error Mask Register */
++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114)
++
++/* Advanced Error Capabilities and Control Register */
++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118)
++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */
++#define PCIE_AECCR_FIRST_ERR_PTR_S 0
++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */
++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */
++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */
++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */
++
++/* Header Log Register 1 */
++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C)
++
++/* Header Log Register 2 */
++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120)
++
++/* Header Log Register 3 */
++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124)
++
++/* Header Log Register 4 */
++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128)
++
++/* Root Error Command Register */
++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C)
++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */
++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */
++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */
++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \
++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN)
++
++/* Root Error Status Register */
++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130)
++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */
++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */
++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */
++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */
++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */
++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */
++#define PCIE_RESR_AER_INT_MSG_NUM_S 27
++
++/* Error Source Indentification Register */
++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134)
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16
++
++/* VC Enhanced Capability Header */
++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140)
++
++/* Port VC Capability Register */
++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144)
++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */
++#define PCIE_PVC1_EXT_VC_CNT_S 0
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4
++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */
++#define PCIE_PVC1_REF_CLK_S 8
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10
++
++/* Extended Virtual Channel Count Defintion */
++#define PCIE_EXT_VC_CNT_MIN 0
++#define PCIE_EXT_VC_CNT_MAX 7
++
++/* Port Arbitration Table Entry Size Definition */
++enum {
++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0,
++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT,
++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT,
++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT,
++};
++
++/* Port VC Capability Register 2 */
++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148)
++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */
++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */
++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */
++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */
++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24
++
++/* Port VC Control and Status Register */
++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C)
++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */
++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */
++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1
++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */
++
++/* VC0 Resource Capability Register */
++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150)
++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */
++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\
++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \
++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR)
++
++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */
++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */
++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24
++
++/* VC0 Resource Control Register */
++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154)
++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */
++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */
++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */
++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */
++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */
++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */
++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */
++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */
++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */
++
++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */
++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */
++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17
++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */
++#define PCIE_VC0_RC0_VC_ID_S 24
++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */
++
++/* VC0 Resource Status Register */
++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158)
++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */
++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */
++
++/* Ack Latency Timer and Replay Timer Register */
++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700)
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16
++
++/* Other Message Register */
++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704)
++
++/* Port Force Link Register */
++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708)
++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */
++#define PCIE_PFLR_LINK_NUM_S 0
++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */
++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */
++#define PCIE_PFLR_LINK_STATE_S 16
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24
++
++/* Ack Frequency Register */
++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C)
++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */
++#define PCIE_AFR_AF_S 0
++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */
++#define PCIE_AFR_FTS_NUM_S 8
++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/
++#define PCIE_AFR_COM_FTS_NUM_S 16
++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */
++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24
++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */
++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27
++#define PCIE_AFR_FTS_NUM_DEFAULT 32
++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7
++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5
++
++/* Port Link Control Register */
++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710)
++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */
++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */
++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */
++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */
++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */
++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */
++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */
++#define PCIE_PLCR_LINK_MODE_S 16
++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */
++
++/* Lane Skew Register */
++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714)
++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */
++#define PCIE_LSR_LANE_SKEW_NUM_S 0
++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */
++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */
++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */
++
++/* Symbol Number Register */
++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718)
++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */
++#define PCIE_SNR_TS_S 0
++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */
++#define PCIE_SNR_SKP_S 8
++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */
++#define PCIE_SNR_REPLAY_TIMER_S 14
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19
++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */
++#define PCIE_SNR_FC_TIMER_S 28
++
++/* Symbol Timer Register and Filter Mask Register 1 */
++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C)
++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */
++#define PCIE_STRFMR_SKP_INTERVAL_S 0
++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */
++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */
++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */
++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */
++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */
++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */
++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */
++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */
++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */
++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */
++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */
++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */
++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */
++
++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */
++
++/* Filter Masker Register 2 */
++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720)
++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */
++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */
++
++/* Debug Register 0 */
++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728)
++
++/* Debug Register 1 */
++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C)
++
++/* Transmit Posted FC Credit Status Register */
++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730)
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12
++
++/* Transmit Non-Posted FC Credit Status */
++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734)
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12
++
++/* Transmit Complete FC Credit Status Register */
++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738)
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12
++
++/* Queue Status Register */
++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C)
++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */
++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */
++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */
++
++/* VC Transmit Arbitration Register 1 */
++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740)
++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */
++
++/* VC Transmit Arbitration Register 2 */
++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744)
++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */
++
++/* VC0 Posted Receive Queue Control Register */
++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748)
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20
++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */
++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */
++
++/* VC0 Non-Posted Receive Queue Control */
++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C)
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20
++
++/* VC0 Completion Receive Queue Control */
++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750)
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21
++
++/* Applicable to the above three registers */
++enum {
++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1,
++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2,
++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4,
++};
++
++/* VC0 Posted Buffer Depth Register */
++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8)
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16
++
++/* VC0 Non-Posted Buffer Depth Register */
++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC)
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16
++
++/* VC0 Completion Buffer Depth Register */
++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0)
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16
++
++/* PHY Status Register, all zeros in VR9 */
++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810)
++
++/* PHY Control Register, all zeros in VR9 */
++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814)
++
++/*
++ * PCIe PDI PHY register definition, suppose all the following
++ * stuff is confidential.
++ * XXX, detailed bit definition
++ */
++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1))
++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1))
++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1))
++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1))
++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1))
++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1))
++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1))
++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1))
++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1))
++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1))
++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1))
++
++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1))
++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1))
++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1))
++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1))
++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1))
++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1))
++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1))
++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1))
++
++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1))
++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1))
++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1))
++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1))
++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1))
++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1))
++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1))
++
++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1))
++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1))
++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1))
++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1))
++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1))
++
++/* Interrupt related stuff */
++#define PCIE_LEGACY_DISABLE 0
++#define PCIE_LEGACY_INTA 1
++#define PCIE_LEGACY_INTB 2
++#define PCIE_LEGACY_INTC 3
++#define PCIE_LEGACY_INTD 4
++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD
++
++#endif /* IFXMIPS_PCIE_REG_H */
++
+--- /dev/null
++++ b/arch/mips/pci/ifxmips_pcie_vr9.h
+@@ -0,0 +1,284 @@
++/****************************************************************************
++ Copyright (c) 2010
++ Lantiq Deutschland GmbH
++ Am Campeon 3; 85579 Neubiberg, Germany
++
++ For licensing information, see the file 'LICENSE' in the root folder of
++ this software module.
++
++ *****************************************************************************/
++/*!
++ \file ifxmips_pcie_vr9.h
++ \ingroup IFX_PCIE
++ \brief PCIe RC driver vr9 specific file
++*/
++
++#ifndef IFXMIPS_PCIE_VR9_H
++#define IFXMIPS_PCIE_VR9_H
++
++#include <linux/types.h>
++#include <linux/delay.h>
++
++#include <linux/gpio.h>
++#include <lantiq_soc.h>
++
++#define IFX_PCIE_GPIO_RESET 494
++
++#define IFX_REG_R32 ltq_r32
++#define IFX_REG_W32 ltq_w32
++#define CONFIG_IFX_PCIE_HW_SWAP
++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C))
++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010))
++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/
++
++#define IFX_RCU (KSEG1 | 0x1F203000)
++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */
++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */
++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */
++#define IFX_RCU_AHB_BE_XBAR_S 0x00000008 /* Configure AHB slave port that connects to XBAR in big endian */
++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++
++#define IFX_PMU1_MODULE_PCIE_PHY (0)
++#define IFX_PMU1_MODULE_PCIE_CTRL (1)
++#define IFX_PMU1_MODULE_PDI (4)
++#define IFX_PMU1_MODULE_MSI (5)
++
++#define IFX_PMU_MODULE_PCIE_L0_CLK (31)
++
++
++#define IFX_GPIO (KSEG1 | 0x1E100B00)
++#define ALT0 ((volatile u32*)(IFX_GPIO + 0x007c))
++#define ALT1 ((volatile u32*)(IFX_GPIO + 0x0080))
++#define OD ((volatile u32*)(IFX_GPIO + 0x0084))
++#define DIR ((volatile u32*)(IFX_GPIO + 0x0078))
++#define OUT ((volatile u32*)(IFX_GPIO + 0x0070))
++
++
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++
++ gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset");
++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
++ gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
++
++/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++ ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++ ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++ ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++ ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++ ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/
++}
++
++static inline void pcie_ahb_pmu_setup(void)
++{
++ /* Enable AHB bus master/slave */
++ struct clk *clk;
++ clk = clk_get_sys("1d900000.pcie", "ahb");
++ clk_enable(clk);
++
++ //AHBM_PMU_SETUP(IFX_PMU_ENABLE);
++ //AHBS_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_rcu_endian_setup(int pcie_port)
++{
++ u32 reg;
++
++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++ reg |= IFX_RCU_AHB_BE_PCIE_M;
++ reg |= IFX_RCU_AHB_BE_PCIE_S;
++ reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#else
++ reg |= IFX_RCU_AHB_BE_PCIE_M;
++ reg &= ~IFX_RCU_AHB_BE_PCIE_S;
++ reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#endif /* CONFIG_IFX_PCIE_HW_SWAP */
++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
++}
++
++static inline void pcie_phy_pmu_enable(int pcie_port)
++{
++ struct clk *clk;
++ clk = clk_get_sys("1d900000.pcie", "phy");
++ clk_enable(clk);
++
++ //PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_phy_pmu_disable(int pcie_port)
++{
++ struct clk *clk;
++ clk = clk_get_sys("1d900000.pcie", "phy");
++ clk_disable(clk);
++
++// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
++}
++
++static inline void pcie_pdi_big_endian(int pcie_port)
++{
++ u32 reg;
++
++ /* SRAM2PDI endianness control. */
++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++ /* Config AHB->PCIe and PDI endianness */
++ reg |= IFX_RCU_AHB_BE_PCIE_PDI;
++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++}
++
++static inline void pcie_pdi_pmu_enable(int pcie_port)
++{
++ /* Enable PDI to access PCIe PHY register */
++ struct clk *clk;
++ clk = clk_get_sys("1d900000.pcie", "pdi");
++ clk_enable(clk);
++ //PDI_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_core_rst_assert(int pcie_port)
++{
++ u32 reg;
++
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++
++ /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */
++ reg |= 0x00400000;
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_core_rst_deassert(int pcie_port)
++{
++ u32 reg;
++
++ /* Make sure one micro-second delay */
++ udelay(1);
++
++ /* Reset PCIe PHY & Core, bit 22 */
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++ reg &= ~0x00400000;
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_assert(int pcie_port)
++{
++ u32 reg;
++
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++ reg |= 0x00001000; /* Bit 12 */
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_deassert(int pcie_port)
++{
++ u32 reg;
++
++ /* Make sure one micro-second delay */
++ udelay(1);
++
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++ reg &= ~0x00001000; /* Bit 12 */
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++ gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
++// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++ mdelay(100);
++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
++// gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
++ //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_core_pmu_setup(int pcie_port)
++{
++ struct clk *clk;
++ clk = clk_get_sys("1d900000.pcie", "ctl");
++ clk_enable(clk);
++ clk = clk_get_sys("1d900000.pcie", "bus");
++ clk_enable(clk);
++
++ /* PCIe Core controller enabled */
++// PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
++
++ /* Enable PCIe L0 Clock */
++// PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline void pcie_msi_init(int pcie_port)
++{
++ struct clk *clk;
++ pcie_msi_pic_init(pcie_port);
++ clk = clk_get_sys("ltq_pcie", "msi");
++ clk_enable(clk);
++// MSI_PMU_SETUP(IFX_PMU_ENABLE);
++}
++
++static inline u32
++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)
++{
++ u32 tbus_number = bus_number;
++
++#ifdef CONFIG_PCI_LANTIQ
++ if (pcibios_host_nr() > 1) {
++ tbus_number -= pcibios_1st_host_bus_nr();
++ }
++#endif /* CONFIG_PCI_LANTIQ */
++ return tbus_number;
++}
++
++static inline struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn)
++{
++ struct pci_dev *dev;
++
++ list_for_each_entry(dev, &bus->devices, bus_list) {
++ if (dev->devfn == devfn)
++ goto out;
++ }
++
++ dev = NULL;
++ out:
++ pci_dev_get(dev);
++ return dev;
++}
++
++static inline u32
++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)
++{
++ struct pci_dev *pdev;
++ u32 tvalue = value;
++
++ /* Sanity check */
++ pdev = ifx_pci_get_slot(bus, devfn);
++ if (pdev == NULL) {
++ return tvalue;
++ }
++
++ /* Only care about PCI bridge */
++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
++ return tvalue;
++ }
++
++ if (read) { /* Read hack */
++ #ifdef CONFIG_PCI_LANTIQ
++ if (pcibios_host_nr() > 1) {
++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);
++ }
++ #endif /* CONFIG_PCI_LANTIQ */
++ }
++ else { /* Write hack */
++ #ifdef CONFIG_PCI_LANTIQ
++ if (pcibios_host_nr() > 1) {
++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);
++ }
++ #endif
++ }
++ return tvalue;
++}
++
++#endif /* IFXMIPS_PCIE_VR9_H */
+--- a/arch/mips/pci/pci-legacy.c
++++ b/arch/mips/pci/pci-legacy.c
+@@ -305,3 +305,30 @@ char *__init pcibios_setup(char *str)
+ return pcibios_plat_setup(str);
+ return str;
+ }
++
++int pcibios_host_nr(void)
++{
++ int count = 0;
++ struct pci_controller *hose;
++ list_for_each_entry(hose, &controllers, list) {
++ count++;
++ }
++ return count;
++}
++EXPORT_SYMBOL(pcibios_host_nr);
++
++int pcibios_1st_host_bus_nr(void)
++{
++ int bus_nr = 0;
++ struct pci_controller *hose;
++
++ hose = list_first_entry_or_null(&controllers, struct pci_controller, list);
++
++ if (hose != NULL) {
++ if (hose->bus != NULL) {
++ bus_nr = hose->bus->number + 1;
++ }
++ }
++ return bus_nr;
++}
++EXPORT_SYMBOL(pcibios_1st_host_bus_nr);
+--- /dev/null
++++ b/arch/mips/pci/pcie-lantiq.h
+@@ -0,0 +1,1316 @@
++/******************************************************************************
++**
++** FILE NAME : ifxmips_pcie_reg.h
++** PROJECT : IFX UEIP for VRX200
++** MODULES : PCIe module
++**
++** DATE : 02 Mar 2009
++** AUTHOR : Lei Chuanhua
++** DESCRIPTION : PCIe Root Complex Driver
++** COPYRIGHT : Copyright (c) 2009
++** Infineon Technologies AG
++** Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++** HISTORY
++** $Version $Date $Author $Comment
++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version
++*******************************************************************************/
++#ifndef IFXMIPS_PCIE_REG_H
++#define IFXMIPS_PCIE_REG_H
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++/*!
++ \file ifxmips_pcie_reg.h
++ \ingroup IFX_PCIE
++ \brief header file for PCIe module register definition
++*/
++/* PCIe Address Mapping Base */
++#define PCIE_CFG_PHY_BASE 0x1D000000UL
++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE)
++#define PCIE_CFG_SIZE (8 * 1024 * 1024)
++
++#define PCIE_MEM_PHY_BASE 0x1C000000UL
++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE)
++#define PCIE_MEM_SIZE (16 * 1024 * 1024)
++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1)
++
++#define PCIE_IO_PHY_BASE 0x1D800000UL
++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE)
++#define PCIE_IO_SIZE (1 * 1024 * 1024)
++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1)
++
++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000)
++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900)
++#define PCIE_MSI_PHY_BASE 0x1F600000UL
++
++#define PCIE_PDI_PHY_BASE 0x1F106800UL
++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE)
++#define PCIE_PDI_SIZE 0x400
++
++#define PCIE1_CFG_PHY_BASE 0x19000000UL
++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE)
++#define PCIE1_CFG_SIZE (8 * 1024 * 1024)
++
++#define PCIE1_MEM_PHY_BASE 0x18000000UL
++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE)
++#define PCIE1_MEM_SIZE (16 * 1024 * 1024)
++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1)
++
++#define PCIE1_IO_PHY_BASE 0x19800000UL
++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE)
++#define PCIE1_IO_SIZE (1 * 1024 * 1024)
++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1)
++
++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000)
++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700)
++#define PCIE1_MSI_PHY_BASE 0x1F400000UL
++
++#define PCIE1_PDI_PHY_BASE 0x1F700400UL
++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE)
++#define PCIE1_PDI_SIZE 0x400
++
++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE))
++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE))
++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE))
++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE))
++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END))
++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE))
++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END))
++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG))
++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE))
++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE))
++
++/* PCIe Application Logic Register */
++/* RC Core Control Register */
++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10)
++/* This should be enabled after initializing configuratin registers
++ * Also should check link status retraining bit
++ */
++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */
++
++/* RC Core Debug Register */
++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14)
++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */
++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */
++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */
++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4
++
++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */
++#define PCIE_RC_DR_PM_DEV_STATE_S 9
++
++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */
++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */
++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */
++
++/* Current Power State Definition */
++enum {
++ PCIE_RC_DR_D0 = 0,
++ PCIE_RC_DR_D1, /* Not supported */
++ PCIE_RC_DR_D2, /* Not supported */
++ PCIE_RC_DR_D3,
++ PCIE_RC_DR_UN,
++};
++
++/* PHY Link Status Register */
++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18)
++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */
++
++/* Electromechanical Control Register */
++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C)
++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */
++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */
++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */
++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */
++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */
++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */
++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */
++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */
++
++/* Interrupt Status Register */
++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20)
++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */
++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */
++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */
++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */
++#define PCIE_IR_SR_AHB_LU_ERR_S 4
++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */
++#define PCIE_IR_SR_INT_MSG_NUM_S 9
++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */
++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27
++
++/* Message Control Register */
++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30)
++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */
++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */
++
++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34)
++
++/* Vendor-Defined Message Requester ID Register */
++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38)
++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF
++#define PCIE_VDM_RID_VDMRID_S 0
++
++/* ASPM Control Register */
++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40)
++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */
++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */
++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */
++
++/* Vendor Message DW0 Register */
++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50)
++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */
++#define PCIE_VM_MSG_DW0_TYPE_S 0
++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */
++#define PCIE_VM_MSG_DW0_FORMAT_S 5
++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */
++#define PCIE_VM_MSG_DW0_TC_S 12
++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */
++#define PCIE_VM_MSG_DW0_ATTR_S 18
++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */
++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */
++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */
++#define PCIE_VM_MSG_DW0_LEN_S 22
++
++/* Format Definition */
++enum {
++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/
++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */
++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */
++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */
++};
++
++/* Traffic Class Definition */
++enum {
++ PCIE_VM_MSG_TC0 = 0,
++ PCIE_VM_MSG_TC1,
++ PCIE_VM_MSG_TC2,
++ PCIE_VM_MSG_TC3,
++ PCIE_VM_MSG_TC4,
++ PCIE_VM_MSG_TC5,
++ PCIE_VM_MSG_TC6,
++ PCIE_VM_MSG_TC7,
++};
++
++/* Attributes Definition */
++enum {
++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */
++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */
++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/
++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */
++};
++
++/* Payload Size Definition */
++#define PCIE_VM_MSG_LEN_MIN 0
++#define PCIE_VM_MSG_LEN_MAX 1024
++
++/* Vendor Message DW1 Register */
++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54)
++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */
++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8
++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */
++#define PCIE_VM_MSG_DW1_CODE_S 16
++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */
++#define PCIE_VM_MSG_DW1_TAG_S 24
++
++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58)
++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C)
++
++/* Vendor Message Request Register */
++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60)
++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */
++
++
++/* AHB Slave Side Band Control Register */
++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70)
++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */
++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */
++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */
++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */
++#define PCIE_AHB_SSB_REQ_ATTR_S 3
++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */
++#define PCIE_AHB_SSB_REQ_TC_S 5
++
++/* AHB Master SideBand Ctrl Register */
++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74)
++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */
++#define PCIE_AHB_MSB_RESP_ATTR_S 0
++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */
++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */
++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */
++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */
++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */
++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6
++
++/* AHB Control Register, fixed bus enumeration exception */
++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78)
++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001
++
++/* Interrupt Enalbe Register */
++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4)
++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8)
++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC)
++
++/* PCIe interrupt enable/control/capture register definition */
++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */
++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */
++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */
++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */
++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */
++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */
++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */
++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */
++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */
++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */
++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */
++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */
++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */
++#define PCIE_IRN_INTA 0x00002000 /* INTA */
++#define PCIE_IRN_INTB 0x00004000 /* INTB */
++#define PCIE_IRN_INTC 0x00008000 /* INTC */
++#define PCIE_IRN_INTD 0x00010000 /* INTD */
++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */
++
++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \
++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\
++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \
++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \
++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT)
++/* PCIe RC Configuration Register */
++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00)
++
++/* Bit definition from pci_reg.h */
++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04)
++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08)
++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */
++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */
++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/
++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */
++
++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */
++/* Bus Number Register bits */
++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF
++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0
++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00
++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8
++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000
++#define PCIE_PNR_SUB_BUS_NUM_S 16
++
++/* IO Base/Limit Register bits */
++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */
++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001
++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0
++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4
++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000
++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12
++
++/* Non-prefetchable Memory Base/Limit Register bit */
++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */
++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0
++#define PCIE_MBML_MEM_BASE_ADDR_S 4
++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000
++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20
++
++/* Prefetchable Memory Base/Limit Register bit */
++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */
++#define PCIE_PMBL_64BIT_ADDR 0x00000001
++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0
++#define PCIE_PMBL_UPPER_12BIT_S 4
++#define PCIE_PMBL_E64MA 0x00010000
++#define PCIE_PMBL_END_ADDR 0xFFF00000
++#define PCIE_PMBL_END_ADDR_S 20
++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */
++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */
++
++/* I/O Base/Limit Upper 16 bits register */
++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000
++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16
++
++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34)
++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38)
++
++/* Interrupt and Secondary Bridge Control Register */
++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C)
++
++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF
++#define PCIE_INTRBCTRL_INT_LINE_S 0
++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00
++#define PCIE_INTRBCTRL_INT_PIN_S 8
++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */
++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */
++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */
++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */
++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */
++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */
++/* Others are read only */
++enum {
++ PCIE_INTRBCTRL_INT_NON = 0,
++ PCIE_INTRBCTRL_INTA,
++ PCIE_INTRBCTRL_INTB,
++ PCIE_INTRBCTRL_INTC,
++ PCIE_INTRBCTRL_INTD,
++};
++
++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40)
++
++/* Power Management Control and Status Register */
++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44)
++
++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */
++#define PCIE_PM_CSR_POWER_STATE_S 0
++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */
++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */
++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */
++
++/* MSI Capability Register for EP */
++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50)
++
++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */
++#define PCIE_MCAPR_MSI_CAP_ID_S 0
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */
++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8
++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */
++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */
++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17
++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */
++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20
++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */
++
++/* MSI Message Address Register */
++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54)
++
++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */
++
++/* MSI Message Upper Address Register */
++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58)
++
++/* MSI Message Data Register */
++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C)
++
++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */
++#define PCIE_MD_DATA_S 0
++
++/* PCI Express Capability Register */
++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70)
++
++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */
++#define PCIE_XCAP_ID_S 0
++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */
++#define PCIE_XCAP_NEXT_CAP_S 8
++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */
++#define PCIE_XCAP_VER_S 16
++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */
++#define PCIE_XCAP_DEV_PORT_TYPE_S 20
++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */
++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */
++#define PCIE_XCAP_MSG_INT_NUM_S 25
++
++/* Device Capability Register */
++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74)
++
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */
++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0
++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */
++#define PCIE_DCAP_PHANTOM_FUNC_S 3
++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */
++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */
++#define PCIE_DCAP_EP_L0S_LATENCY_S 6
++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */
++#define PCIE_DCAP_EP_L1_LATENCY_S 9
++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */
++
++/* Maximum payload size supported */
++enum {
++ PCIE_MAX_PAYLOAD_128 = 0,
++ PCIE_MAX_PAYLOAD_256,
++ PCIE_MAX_PAYLOAD_512,
++ PCIE_MAX_PAYLOAD_1024,
++ PCIE_MAX_PAYLOAD_2048,
++ PCIE_MAX_PAYLOAD_4096,
++};
++
++/* Device Control and Status Register */
++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78)
++
++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */
++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */
++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */
++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */
++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */
++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5
++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */
++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */
++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */
++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/
++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12
++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */
++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */
++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */
++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */
++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */
++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */
++
++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \
++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \
++ PCIE_DCTLSYS_UR_REQ_EN)
++
++/* Link Capability Register */
++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C)
++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */
++#define PCIE_LCAP_MAX_LINK_SPEED_S 0
++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */
++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4
++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */
++#define PCIE_LCAP_ASPM_LEVEL_S 10
++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */
++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12
++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */
++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15
++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */
++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */
++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */
++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */
++#define PCIE_LCAP_PORT_NUM_S 24
++
++/* Maximum Length width definition */
++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00
++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */
++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02
++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04
++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08
++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C
++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10
++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20
++
++/* Active State Link PM definition */
++enum {
++ PCIE_ASPM_RES0 = 0,
++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */
++ PCIE_ASPM_RES1,
++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */
++};
++
++/* L0s Exit Latency definition */
++enum {
++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */
++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */
++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */
++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */
++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */
++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */
++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */
++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */
++};
++
++/* L1 Exit Latency definition */
++enum {
++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */
++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */
++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */
++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */
++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */
++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */
++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */
++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */
++};
++
++/* Link Control and Status Register */
++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80)
++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */
++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0
++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/
++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */
++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */
++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */
++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */
++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */
++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */
++#define PCIE_LCTLSTS_LINK_SPEED_S 16
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */
++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20
++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */
++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */
++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */
++
++/* Slot Capabilities Register */
++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84)
++
++/* Slot Capabilities */
++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88)
++
++/* Root Control and Capability Register */
++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C)
++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */
++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */
++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */
++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */
++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \
++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR)
++/* Root Status Register */
++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90)
++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */
++#define PCIE_RSTS_PME_REQ_ID_S 0
++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */
++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */
++
++/* PCI Express Enhanced Capability Header */
++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100)
++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */
++#define PCIE_ENHANCED_CAP_ID_S 0
++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */
++#define PCIE_ENHANCED_CAP_VER_S 16
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */
++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20
++
++/* Uncorrectable Error Status Register */
++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104)
++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */
++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */
++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */
++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */
++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */
++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */
++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */
++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */
++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */
++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */
++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */
++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \
++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \
++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\
++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ)
++
++/* Uncorrectable Error Mask Register, Mask means no report */
++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108)
++
++/* Uncorrectable Error Severity Register */
++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C)
++
++/* Correctable Error Status Register */
++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110)
++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */
++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */
++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */
++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */
++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */
++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */
++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\
++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR)
++
++/* Correctable Error Mask Register */
++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114)
++
++/* Advanced Error Capabilities and Control Register */
++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118)
++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */
++#define PCIE_AECCR_FIRST_ERR_PTR_S 0
++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */
++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */
++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */
++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */
++
++/* Header Log Register 1 */
++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C)
++
++/* Header Log Register 2 */
++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120)
++
++/* Header Log Register 3 */
++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124)
++
++/* Header Log Register 4 */
++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128)
++
++/* Root Error Command Register */
++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C)
++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */
++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */
++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */
++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \
++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN)
++
++/* Root Error Status Register */
++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130)
++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */
++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */
++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */
++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */
++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */
++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */
++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */
++#define PCIE_RESR_AER_INT_MSG_NUM_S 27
++
++/* Error Source Indentification Register */
++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134)
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF
++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000
++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16
++
++/* VC Enhanced Capability Header */
++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140)
++
++/* Port VC Capability Register */
++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144)
++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */
++#define PCIE_PVC1_EXT_VC_CNT_S 0
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */
++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4
++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */
++#define PCIE_PVC1_REF_CLK_S 8
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */
++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10
++
++/* Extended Virtual Channel Count Defintion */
++#define PCIE_EXT_VC_CNT_MIN 0
++#define PCIE_EXT_VC_CNT_MAX 7
++
++/* Port Arbitration Table Entry Size Definition */
++enum {
++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0,
++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT,
++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT,
++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT,
++};
++
++/* Port VC Capability Register 2 */
++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148)
++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */
++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */
++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */
++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */
++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */
++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24
++
++/* Port VC Control and Status Register */
++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C)
++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */
++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */
++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1
++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */
++
++/* VC0 Resource Capability Register */
++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150)
++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */
++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */
++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\
++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \
++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR)
++
++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */
++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */
++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */
++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24
++
++/* VC0 Resource Control Register */
++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154)
++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */
++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */
++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */
++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */
++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */
++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */
++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */
++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */
++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */
++
++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */
++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */
++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17
++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */
++#define PCIE_VC0_RC0_VC_ID_S 24
++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */
++
++/* VC0 Resource Status Register */
++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158)
++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */
++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */
++
++/* Ack Latency Timer and Replay Timer Register */
++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700)
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */
++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */
++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16
++
++/* Other Message Register */
++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704)
++
++/* Port Force Link Register */
++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708)
++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */
++#define PCIE_PFLR_LINK_NUM_S 0
++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */
++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */
++#define PCIE_PFLR_LINK_STATE_S 16
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */
++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24
++
++/* Ack Frequency Register */
++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C)
++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */
++#define PCIE_AFR_AF_S 0
++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */
++#define PCIE_AFR_FTS_NUM_S 8
++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/
++#define PCIE_AFR_COM_FTS_NUM_S 16
++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */
++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24
++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */
++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27
++#define PCIE_AFR_FTS_NUM_DEFAULT 32
++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7
++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5
++
++/* Port Link Control Register */
++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710)
++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */
++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */
++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */
++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */
++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */
++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */
++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */
++#define PCIE_PLCR_LINK_MODE_S 16
++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */
++
++/* Lane Skew Register */
++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714)
++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */
++#define PCIE_LSR_LANE_SKEW_NUM_S 0
++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */
++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */
++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */
++
++/* Symbol Number Register */
++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718)
++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */
++#define PCIE_SNR_TS_S 0
++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */
++#define PCIE_SNR_SKP_S 8
++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */
++#define PCIE_SNR_REPLAY_TIMER_S 14
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */
++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19
++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */
++#define PCIE_SNR_FC_TIMER_S 28
++
++/* Symbol Timer Register and Filter Mask Register 1 */
++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C)
++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */
++#define PCIE_STRFMR_SKP_INTERVAL_S 0
++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */
++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */
++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */
++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */
++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */
++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */
++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */
++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */
++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */
++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */
++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */
++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */
++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */
++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */
++
++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */
++
++/* Filter Masker Register 2 */
++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720)
++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */
++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */
++
++/* Debug Register 0 */
++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728)
++
++/* Debug Register 1 */
++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C)
++
++/* Transmit Posted FC Credit Status Register */
++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730)
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */
++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */
++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12
++
++/* Transmit Non-Posted FC Credit Status */
++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734)
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */
++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */
++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12
++
++/* Transmit Complete FC Credit Status Register */
++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738)
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */
++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */
++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12
++
++/* Queue Status Register */
++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C)
++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */
++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */
++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */
++
++/* VC Transmit Arbitration Register 1 */
++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740)
++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */
++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */
++
++/* VC Transmit Arbitration Register 2 */
++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744)
++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */
++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */
++
++/* VC0 Posted Receive Queue Control Register */
++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748)
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */
++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */
++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */
++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20
++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */
++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */
++
++/* VC0 Non-Posted Receive Queue Control */
++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C)
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */
++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */
++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */
++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20
++
++/* VC0 Completion Receive Queue Control */
++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750)
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */
++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */
++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */
++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21
++
++/* Applicable to the above three registers */
++enum {
++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1,
++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2,
++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4,
++};
++
++/* VC0 Posted Buffer Depth Register */
++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8)
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */
++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */
++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16
++
++/* VC0 Non-Posted Buffer Depth Register */
++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC)
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */
++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */
++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16
++
++/* VC0 Completion Buffer Depth Register */
++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0)
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */
++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */
++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16
++
++/* PHY Status Register, all zeros in VR9 */
++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810)
++
++/* PHY Control Register, all zeros in VR9 */
++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814)
++
++/*
++ * PCIe PDI PHY register definition, suppose all the following
++ * stuff is confidential.
++ * XXX, detailed bit definition
++ */
++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1))
++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1))
++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1))
++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1))
++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1))
++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1))
++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1))
++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1))
++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1))
++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1))
++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1))
++
++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1))
++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1))
++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1))
++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1))
++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1))
++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1))
++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1))
++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1))
++
++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1))
++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1))
++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1))
++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1))
++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1))
++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1))
++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1))
++
++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1))
++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1))
++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1))
++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1))
++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1))
++
++/* Interrupt related stuff */
++#define PCIE_LEGACY_DISABLE 0
++#define PCIE_LEGACY_INTA 1
++#define PCIE_LEGACY_INTB 2
++#define PCIE_LEGACY_INTC 3
++#define PCIE_LEGACY_INTD 4
++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD
++
++#define PCIE_IRQ_LOCK(lock) do { \
++ unsigned long flags; \
++ spin_lock_irqsave(&(lock), flags);
++#define PCIE_IRQ_UNLOCK(lock) \
++ spin_unlock_irqrestore(&(lock), flags); \
++} while (0)
++
++#define PCIE_MSG_MSI 0x00000001
++#define PCIE_MSG_ISR 0x00000002
++#define PCIE_MSG_FIXUP 0x00000004
++#define PCIE_MSG_READ_CFG 0x00000008
++#define PCIE_MSG_WRITE_CFG 0x00000010
++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG)
++#define PCIE_MSG_REG 0x00000020
++#define PCIE_MSG_INIT 0x00000040
++#define PCIE_MSG_ERR 0x00000080
++#define PCIE_MSG_PHY 0x00000100
++#define PCIE_MSG_ANY 0x000001ff
++
++#define IFX_PCIE_PORT0 0
++#define IFX_PCIE_PORT1 1
++
++#ifdef CONFIG_IFX_PCIE_2ND_CORE
++#define IFX_PCIE_CORE_NR 2
++#else
++#define IFX_PCIE_CORE_NR 1
++#endif
++
++//#define IFX_PCIE_ERROR_INT
++
++//#define IFX_PCIE_DBG
++
++#if defined(IFX_PCIE_DBG)
++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \
++ if (g_pcie_debug_flag & (_m)) { \
++ ifx_pcie_debug((_fmt), ##args); \
++ } \
++} while (0)
++
++#define INLINE
++#else
++#define IFX_PCIE_PRINT(_m, _fmt, args...) \
++ do {} while(0)
++#define INLINE inline
++#endif
++
++struct ifx_pci_controller {
++ struct pci_controller pcic;
++
++ /* RC specific, per host bus information */
++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */
++};
++
++typedef struct ifx_pcie_ir_irq {
++ const unsigned int irq;
++ const char name[16];
++}ifx_pcie_ir_irq_t;
++
++typedef struct ifx_pcie_legacy_irq{
++ const u32 irq_bit;
++ const int irq;
++}ifx_pcie_legacy_irq_t;
++
++typedef struct ifx_pcie_irq {
++ ifx_pcie_ir_irq_t ir_irq;
++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX];
++}ifx_pcie_irq_t;
++
++extern u32 g_pcie_debug_flag;
++extern void ifx_pcie_debug(const char *fmt, ...);
++extern void pcie_phy_clock_mode_setup(int pcie_port);
++extern void pcie_msi_pic_init(int pcie_port);
++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value);
++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value);
++
++
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/clk.h>
++
++#include <lantiq_soc.h>
++
++#define IFX_PCIE_GPIO_RESET 38
++#define IFX_REG_R32 ltq_r32
++#define IFX_REG_W32 ltq_w32
++#define CONFIG_IFX_PCIE_HW_SWAP
++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C))
++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010))
++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/
++
++#define IFX_RCU (KSEG1 | 0x1F203000)
++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */
++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */
++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */
++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE
++
++#define IFX_PMU1_MODULE_PCIE_PHY (0)
++#define IFX_PMU1_MODULE_PCIE_CTRL (1)
++#define IFX_PMU1_MODULE_PDI (4)
++#define IFX_PMU1_MODULE_MSI (5)
++
++#define IFX_PMU_MODULE_PCIE_L0_CLK (31)
++
++
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++}
++
++static inline void pcie_ahb_pmu_setup(void)
++{
++ struct clk *clk;
++ clk = clk_get_sys("ltq_pcie", "ahb");
++ clk_enable(clk);
++ //ltq_pmu_enable(PMU_AHBM | PMU_AHBS);
++}
++
++static inline void pcie_rcu_endian_setup(int pcie_port)
++{
++ u32 reg;
++
++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++ reg |= IFX_RCU_AHB_BE_PCIE_M;
++ reg |= IFX_RCU_AHB_BE_PCIE_S;
++ reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#else
++ reg |= IFX_RCU_AHB_BE_PCIE_M;
++ reg &= ~IFX_RCU_AHB_BE_PCIE_S;
++ reg &= ~IFX_RCU_AHB_BE_XBAR_M;
++#endif /* CONFIG_IFX_PCIE_HW_SWAP */
++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
++}
++
++static inline void pcie_phy_pmu_enable(int pcie_port)
++{
++ struct clk *clk;
++ clk = clk_get_sys("ltq_pcie", "phy");
++ clk_enable(clk);
++ //ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PCIE_PHY);
++}
++
++static inline void pcie_phy_pmu_disable(int pcie_port)
++{
++ struct clk *clk;
++ clk = clk_get_sys("ltq_pcie", "phy");
++ clk_disable(clk);
++ //ltq_pmu1_disable(1<<IFX_PMU1_MODULE_PCIE_PHY);
++}
++
++static inline void pcie_pdi_big_endian(int pcie_port)
++{
++ u32 reg;
++
++ /* SRAM2PDI endianness control. */
++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
++ /* Config AHB->PCIe and PDI endianness */
++ reg |= IFX_RCU_AHB_BE_PCIE_PDI;
++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
++}
++
++static inline void pcie_pdi_pmu_enable(int pcie_port)
++{
++ struct clk *clk;
++ clk = clk_get_sys("ltq_pcie", "pdi");
++ clk_enable(clk);
++ //ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PDI);
++}
++
++static inline void pcie_core_rst_assert(int pcie_port)
++{
++ u32 reg;
++
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++
++ /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */
++ reg |= 0x00400000;
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_core_rst_deassert(int pcie_port)
++{
++ u32 reg;
++
++ /* Make sure one micro-second delay */
++ udelay(1);
++
++ /* Reset PCIe PHY & Core, bit 22 */
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++ reg &= ~0x00400000;
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_assert(int pcie_port)
++{
++ u32 reg;
++
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++ reg |= 0x00001000; /* Bit 12 */
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_phy_rst_deassert(int pcie_port)
++{
++ u32 reg;
++
++ /* Make sure one micro-second delay */
++ udelay(1);
++
++ reg = IFX_REG_R32(IFX_RCU_RST_REQ);
++ reg &= ~0x00001000; /* Bit 12 */
++ IFX_REG_W32(reg, IFX_RCU_RST_REQ);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++ gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
++ // ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++ mdelay(100);
++ gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
++// ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
++}
++
++static inline void pcie_core_pmu_setup(int pcie_port)
++{
++ struct clk *clk;
++ clk = clk_get_sys("ltq_pcie", "ctl");
++ clk_enable(clk);
++ clk = clk_get_sys("ltq_pcie", "bus");
++ clk_enable(clk);
++
++ //ltq_pmu1_enable(1 << IFX_PMU1_MODULE_PCIE_CTRL);
++ //ltq_pmu_enable(1 << IFX_PMU_MODULE_PCIE_L0_CLK);
++}
++
++static inline void pcie_msi_init(int pcie_port)
++{
++ struct clk *clk;
++ pcie_msi_pic_init(pcie_port);
++ clk = clk_get_sys("ltq_pcie", "msi");
++ clk_enable(clk);
++ //ltq_pmu1_enable(1 << IFX_PMU1_MODULE_MSI);
++}
++
++static inline u32
++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)
++{
++ u32 tbus_number = bus_number;
++
++#ifdef CONFIG_PCI_LANTIQ
++ if (pcibios_host_nr() > 1) {
++ tbus_number -= pcibios_1st_host_bus_nr();
++ }
++#endif /* CONFIG_PCI_LANTIQ */
++ return tbus_number;
++}
++
++static struct pci_dev *ifx_pci_get_slot(struct pci_bus *bus, unsigned int devfn)
++{
++ struct pci_dev *dev;
++
++ list_for_each_entry(dev, &bus->devices, bus_list) {
++ if (dev->devfn == devfn)
++ goto out;
++ }
++
++ dev = NULL;
++ out:
++ pci_dev_get(dev);
++ return dev;
++}
++
++static inline u32
++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)
++{
++ struct pci_dev *pdev;
++ u32 tvalue = value;
++
++ /* Sanity check */
++ pdev = ifx_pci_get_slot(bus, devfn);
++ if (pdev == NULL) {
++ return tvalue;
++ }
++
++ /* Only care about PCI bridge */
++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {
++ return tvalue;
++ }
++
++ if (read) { /* Read hack */
++ #ifdef CONFIG_PCI_LANTIQ
++ if (pcibios_host_nr() > 1) {
++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);
++ }
++ #endif /* CONFIG_PCI_LANTIQ */
++ }
++ else { /* Write hack */
++ #ifdef CONFIG_PCI_LANTIQ
++ if (pcibios_host_nr() > 1) {
++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);
++ }
++ #endif
++ }
++ return tvalue;
++}
++
++#endif /* IFXMIPS_PCIE_VR9_H */
++
+--- a/drivers/pci/pcie/Kconfig
++++ b/drivers/pci/pcie/Kconfig
+@@ -51,6 +51,7 @@ config PCIEAER_INJECT
+ config PCIE_ECRC
+ bool "PCI Express ECRC settings control"
+ depends on PCIEAER
++ default n
+ help
+ Used to override firmware/bios settings for PCI Express ECRC
+ (transaction layer end-to-end CRC checking).
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -1558,6 +1558,8 @@ void pci_walk_bus_locked(struct pci_bus
+ void *userdata);
+ int pci_cfg_space_size(struct pci_dev *dev);
+ unsigned char pci_bus_max_busnr(struct pci_bus *bus);
++int pcibios_host_nr(void);
++int pcibios_1st_host_bus_nr(void);
+ void pci_setup_bridge(struct pci_bus *bus);
+ resource_size_t pcibios_window_alignment(struct pci_bus *bus,
+ unsigned long type);
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -1097,6 +1097,12 @@
+ #define PCI_DEVICE_ID_SGI_IOC3 0x0003
+ #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002
+
++#define PCI_VENDOR_ID_INFINEON 0x15D1
++#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F
++#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011
++#define PCI_VENDOR_ID_LANTIQ 0x1BEF
++#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011
++
+ #define PCI_VENDOR_ID_WINBOND 0x10ad
+ #define PCI_DEVICE_ID_WINBOND_82C105 0x0105
+ #define PCI_DEVICE_ID_WINBOND_83C553 0x0565
--- /dev/null
+From f038380835033e376d89c72516f087254792bbad Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Mon, 6 May 2024 09:41:42 +0200
+Subject: [PATCH] MIPS: pci: lantiq: restore reset gpio polarity
+
+Commit 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API") not
+only switched to the gpiod API, but also inverted / changed the polarity
+of the GPIO.
+
+According to the PCI specification, the RST# pin is an active-low
+signal. However, most of the device trees that have been widely used for
+a long time (mainly in the openWrt project) define this GPIO as
+active-high and the old driver code inverted the signal internally.
+
+Apparently there are actually boards where the reset gpio must be
+operated inverted. For this reason, we cannot use the GPIOD_OUT_LOW/HIGH
+flag for initialization. Instead, we must explicitly set the gpio to
+value 1 in order to take into account any "GPIO_ACTIVE_LOW" flag that
+may have been set.
+
+In order to remain compatible with all these existing device trees, we
+should therefore keep the logic as it was before the commit.
+
+Fixes: 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API")
+Cc: stable@vger.kernel.org
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ arch/mips/pci/pci-lantiq.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -124,14 +124,14 @@ static int ltq_pci_startup(struct platfo
+ clk_disable(clk_external);
+
+ /* setup reset gpio used by pci */
+- reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
+- GPIOD_OUT_LOW);
++ reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS);
+ error = PTR_ERR_OR_ZERO(reset_gpio);
+ if (error) {
+ dev_err(&pdev->dev, "failed to request gpio: %d\n", error);
+ return error;
+ }
+ gpiod_set_consumer_name(reset_gpio, "pci_reset");
++ gpiod_direction_output(reset_gpio, 1);
+
+ /* enable auto-switching between PCI and EBU */
+ ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
+@@ -194,10 +194,10 @@ static int ltq_pci_startup(struct platfo
+
+ /* toggle reset pin */
+ if (reset_gpio) {
+- gpiod_set_value_cansleep(reset_gpio, 1);
++ gpiod_set_value_cansleep(reset_gpio, 0);
+ wmb();
+ mdelay(1);
+- gpiod_set_value_cansleep(reset_gpio, 0);
++ gpiod_set_value_cansleep(reset_gpio, 1);
+ }
+ return 0;
+ }
--- /dev/null
+From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 3 Aug 2012 10:27:25 +0200
+Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++
+ arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++
+ arch/mips/lantiq/irq.c | 2 +
+ arch/mips/mm/cache.c | 4 +
+ include/uapi/linux/atm.h | 6 +
+ net/atm/common.c | 6 +
+ net/atm/proc.c | 2 +-
+ 7 files changed, 416 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
+@@ -0,0 +1,196 @@
++/******************************************************************************
++**
++** FILE NAME : ifx_atm.h
++** PROJECT : UEIP
++** MODULES : ATM
++**
++** DATE : 17 Jun 2009
++** AUTHOR : Xu Liang
++** DESCRIPTION : Global ATM driver header file
++** COPYRIGHT : Copyright (c) 2006
++** Infineon Technologies AG
++** Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++**
++** HISTORY
++** $Date $Author $Comment
++** 07 JUL 2009 Xu Liang Init Version
++*******************************************************************************/
++
++#ifndef IFX_ATM_H
++#define IFX_ATM_H
++
++
++
++/*!
++ \defgroup IFX_ATM UEIP Project - ATM driver module
++ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
++ */
++
++/*!
++ \defgroup IFX_ATM_IOCTL IOCTL Commands
++ \ingroup IFX_ATM
++ \brief IOCTL Commands used by user application.
++ */
++
++/*!
++ \defgroup IFX_ATM_STRUCT Structures
++ \ingroup IFX_ATM
++ \brief Structures used by user application.
++ */
++
++/*!
++ \file ifx_atm.h
++ \ingroup IFX_ATM
++ \brief ATM driver header file
++ */
++
++
++
++/*
++ * ####################################
++ * Definition
++ * ####################################
++ */
++
++/*!
++ \addtogroup IFX_ATM_STRUCT
++ */
++/*@{*/
++
++/*
++ * ATM MIB
++ */
++
++/*!
++ \struct atm_cell_ifEntry_t
++ \brief Structure used for Cell Level MIB Counters.
++
++ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
++ */
++typedef struct {
++ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
++ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
++ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
++ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
++ __u32 ifInErrors; /*!< counter of error ingress cells */
++ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
++ __u32 ifOutErrors; /*!< counter of error egress cells */
++} atm_cell_ifEntry_t;
++
++/*!
++ \struct atm_aal5_ifEntry_t
++ \brief Structure used for AAL5 Frame Level MIB Counters.
++
++ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
++ */
++typedef struct {
++ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
++ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
++ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
++ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
++ __u32 ifInUcastPkts; /*!< counter of ingress packets */
++ __u32 ifOutUcastPkts; /*!< counter of egress packets */
++ __u32 ifInErrors; /*!< counter of error ingress packets */
++ __u32 ifInDiscards; /*!< counter of dropped ingress packets */
++ __u32 ifOutErros; /*!< counter of error egress packets */
++ __u32 ifOutDiscards; /*!< counter of dropped egress packets */
++} atm_aal5_ifEntry_t;
++
++/*!
++ \struct atm_aal5_vcc_t
++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
++
++ This structure is a part of structure "atm_aal5_vcc_x_t".
++ */
++typedef struct {
++ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
++ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
++ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
++} atm_aal5_vcc_t;
++
++/*!
++ \struct atm_aal5_vcc_x_t
++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
++
++ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
++ */
++typedef struct {
++ int vpi; /*!< VPI of the VCC to get MIB counters */
++ int vci; /*!< VCI of the VCC to get MIB counters */
++ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
++} atm_aal5_vcc_x_t;
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ * IOCTL
++ * ####################################
++ */
++
++/*!
++ \addtogroup IFX_ATM_IOCTL
++ */
++/*@{*/
++
++/*
++ * ioctl Command
++ */
++/*!
++ \brief ATM IOCTL Magic Number
++ */
++#define PPE_ATM_IOC_MAGIC 'o'
++/*!
++ \brief ATM IOCTL Command - Get Cell Level MIB Counters
++
++ This command is obsolete. User can get cell level MIB from DSL API.
++ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
++ */
++#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
++/*!
++ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
++
++ Get AAL5 packet counters.
++ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
++ */
++#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
++/*!
++ \brief ATM IOCTL Command - Get Per PVC MIB Counters
++
++ Get AAL5 packet counters for each PVC.
++ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
++ */
++#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
++/*!
++ \brief Total Number of ATM IOCTL Commands
++ */
++#define PPE_ATM_IOC_MAXNR 3
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ * API
++ * ####################################
++ */
++
++#ifdef __KERNEL__
++struct port_cell_info {
++ unsigned int port_num;
++ unsigned int tx_link_rate[2];
++};
++#endif
++
++
++
++#endif // IFX_ATM_H
++
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
+@@ -0,0 +1,203 @@
++/******************************************************************************
++**
++** FILE NAME : ifx_ptm.h
++** PROJECT : UEIP
++** MODULES : PTM
++**
++** DATE : 17 Jun 2009
++** AUTHOR : Xu Liang
++** DESCRIPTION : Global PTM driver header file
++** COPYRIGHT : Copyright (c) 2006
++** Infineon Technologies AG
++** Am Campeon 1-12, 85579 Neubiberg, Germany
++**
++** This program is free software; you can redistribute it and/or modify
++** it under the terms of the GNU General Public License as published by
++** the Free Software Foundation; either version 2 of the License, or
++** (at your option) any later version.
++**
++** HISTORY
++** $Date $Author $Comment
++** 07 JUL 2009 Xu Liang Init Version
++*******************************************************************************/
++
++#ifndef IFX_PTM_H
++#define IFX_PTM_H
++
++
++
++/*!
++ \defgroup IFX_PTM UEIP Project - PTM driver module
++ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
++ */
++
++/*!
++ \defgroup IFX_PTM_IOCTL IOCTL Commands
++ \ingroup IFX_PTM
++ \brief IOCTL Commands used by user application.
++ */
++
++/*!
++ \defgroup IFX_PTM_STRUCT Structures
++ \ingroup IFX_PTM
++ \brief Structures used by user application.
++ */
++
++/*!
++ \file ifx_ptm.h
++ \ingroup IFX_PTM
++ \brief PTM driver header file
++ */
++
++
++
++/*
++ * ####################################
++ * Definition
++ * ####################################
++ */
++
++
++
++/*
++ * ####################################
++ * IOCTL
++ * ####################################
++ */
++
++/*!
++ \addtogroup IFX_PTM_IOCTL
++ */
++/*@{*/
++
++/*
++ * ioctl Command
++ */
++/*!
++ \brief PTM IOCTL Command - Get codeword MIB counters.
++
++ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
++ */
++#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1
++/*!
++ \brief PTM IOCTL Command - Get packet MIB counters.
++
++ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
++ */
++#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2
++/*!
++ \brief PTM IOCTL Command - Get firmware configuration (CRC).
++
++ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
++ */
++#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3
++/*!
++ \brief PTM IOCTL Command - Set firmware configuration (CRC).
++
++ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
++ */
++#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4
++/*!
++ \brief PTM IOCTL Command - Program priority value to TX queue mapping.
++
++ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
++ */
++#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14
++
++/*@}*/
++
++
++/*!
++ \addtogroup IFX_PTM_STRUCT
++ */
++/*@{*/
++
++/*
++ * ioctl Data Type
++ */
++
++/*!
++ \typedef PTM_CW_IF_ENTRY_T
++ \brief Wrapping of structure "ptm_cw_ifEntry_t".
++ */
++/*!
++ \struct ptm_cw_ifEntry_t
++ \brief Structure used for CodeWord level MIB counters.
++ */
++typedef struct ptm_cw_ifEntry_t {
++ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */
++ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */
++ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */
++ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */
++ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */
++} PTM_CW_IF_ENTRY_T;
++
++/*!
++ \typedef PTM_FRAME_MIB_T
++ \brief Wrapping of structure "ptm_frame_mib_t".
++ */
++/*!
++ \struct ptm_frame_mib_t
++ \brief Structure used for packet level MIB counters.
++ */
++typedef struct ptm_frame_mib_t {
++ uint32_t RxCorrect; /*!< output, number of ingress packet */
++ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */
++ uint32_t RxDropped; /*!< output, number of dropped ingress packet */
++ uint32_t TxSend; /*!< output, number of egress packet */
++} PTM_FRAME_MIB_T;
++
++/*!
++ \typedef IFX_PTM_CFG_T
++ \brief Wrapping of structure "ptm_cfg_t".
++ */
++/*!
++ \struct ptm_cfg_t
++ \brief Structure used for ETH/TC CRC configuration.
++ */
++typedef struct ptm_cfg_t {
++ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */
++ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */
++ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */
++ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */
++ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */
++ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */
++ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */
++} IFX_PTM_CFG_T;
++
++/*!
++ \typedef IFX_PTM_PRIO_Q_MAP_T
++ \brief Wrapping of structure "ppe_prio_q_map".
++ */
++/*!
++ \struct ppe_prio_q_map
++ \brief Structure used for Priority Value to TX Queue mapping.
++ */
++typedef struct ppe_prio_q_map {
++ int pkt_prio;
++ int qid;
++ int vpi; // ignored in eth interface
++ int vci; // ignored in eth interface
++} IFX_PTM_PRIO_Q_MAP_T;
++
++/*@}*/
++
++
++
++/*
++ * ####################################
++ * API
++ * ####################################
++ */
++
++#ifdef __KERNEL__
++struct port_cell_info {
++ unsigned int port_num;
++ unsigned int tx_link_rate[2];
++};
++#endif
++
++
++
++#endif // IFX_PTM_H
++
+--- a/arch/mips/lantiq/irq.c
++++ b/arch/mips/lantiq/irq.c
+@@ -13,6 +13,7 @@
+ #include <linux/of_platform.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
++#include <linux/module.h>
+
+ #include <asm/bootinfo.h>
+ #include <asm/irq_cpu.h>
+@@ -92,6 +93,7 @@ void ltq_disable_irq(struct irq_data *d)
+ }
+ raw_spin_unlock_irqrestore(<q_icu_lock, flags);
+ }
++EXPORT_SYMBOL(ltq_mask_and_ack_irq);
+
+ void ltq_mask_and_ack_irq(struct irq_data *d)
+ {
+--- a/arch/mips/mm/cache.c
++++ b/arch/mips/mm/cache.c
+@@ -63,6 +63,10 @@ void (*_dma_cache_wback_inv)(unsigned lo
+ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
+ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+
++EXPORT_SYMBOL(_dma_cache_wback_inv);
++EXPORT_SYMBOL(_dma_cache_wback);
++EXPORT_SYMBOL(_dma_cache_inv);
++
+ #endif /* CONFIG_DMA_NONCOHERENT */
+
+ /*
+--- a/include/uapi/linux/atm.h
++++ b/include/uapi/linux/atm.h
+@@ -131,8 +131,14 @@
+ #define ATM_ABR 4
+ #define ATM_ANYCLASS 5 /* compatible with everything */
+
++#define ATM_VBR_NRT ATM_VBR
++#define ATM_VBR_RT 6
++#define ATM_UBR_PLUS 7
++#define ATM_GFR 8
++
+ #define ATM_MAX_PCR -1 /* maximum available PCR */
+
++
+ struct atm_trafprm {
+ unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
+ int max_pcr; /* maximum PCR in cells per second */
+--- a/net/atm/proc.c
++++ b/net/atm/proc.c
+@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil
+ static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
+ {
+ static const char *const class_name[] = {
+- "off", "UBR", "CBR", "VBR", "ABR"};
++ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
+ static const char *const aal_name[] = {
+ "---", "1", "2", "3/4", /* 0- 3 */
+ "???", "5", "???", "???", /* 4- 7 */
--- /dev/null
+From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:30:56 +0200
+Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++
+ arch/mips/lantiq/xway/Makefile | 2 +-
+ arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++
+ 3 files changed, 1001 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
+ create mode 100644 arch/mips/lantiq/xway/timer.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
+@@ -0,0 +1,155 @@
++#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
++#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
++
++
++/******************************************************************************
++ Copyright (c) 2002, Infineon Technologies. All rights reserved.
++
++ No Warranty
++ Because the program is licensed free of charge, there is no warranty for
++ the program, to the extent permitted by applicable law. Except when
++ otherwise stated in writing the copyright holders and/or other parties
++ provide the program "as is" without warranty of any kind, either
++ expressed or implied, including, but not limited to, the implied
++ warranties of merchantability and fitness for a particular purpose. The
++ entire risk as to the quality and performance of the program is with
++ you. should the program prove defective, you assume the cost of all
++ necessary servicing, repair or correction.
++
++ In no event unless required by applicable law or agreed to in writing
++ will any copyright holder, or any other party who may modify and/or
++ redistribute the program as permitted above, be liable to you for
++ damages, including any general, special, incidental or consequential
++ damages arising out of the use or inability to use the program
++ (including but not limited to loss of data or data being rendered
++ inaccurate or losses sustained by you or third parties or a failure of
++ the program to operate with any other programs), even if such holder or
++ other party has been advised of the possibility of such damages.
++******************************************************************************/
++
++
++/*
++ * ####################################
++ * Definition
++ * ####################################
++ */
++
++/*
++ * Available Timer/Counter Index
++ */
++#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
++#define TIMER_ANY 0x00
++#define TIMER1A TIMER(1, 0)
++#define TIMER1B TIMER(1, 1)
++#define TIMER2A TIMER(2, 0)
++#define TIMER2B TIMER(2, 1)
++#define TIMER3A TIMER(3, 0)
++#define TIMER3B TIMER(3, 1)
++
++/*
++ * Flag of Timer/Counter
++ * These flags specify the way in which timer is configured.
++ */
++/* Bit size of timer/counter. */
++#define TIMER_FLAG_16BIT 0x0000
++#define TIMER_FLAG_32BIT 0x0001
++/* Switch between timer and counter. */
++#define TIMER_FLAG_TIMER 0x0000
++#define TIMER_FLAG_COUNTER 0x0002
++/* Stop or continue when overflowing/underflowing. */
++#define TIMER_FLAG_ONCE 0x0000
++#define TIMER_FLAG_CYCLIC 0x0004
++/* Count up or counter down. */
++#define TIMER_FLAG_UP 0x0000
++#define TIMER_FLAG_DOWN 0x0008
++/* Count on specific level or edge. */
++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
++#define TIMER_FLAG_RISE_EDGE 0x0010
++#define TIMER_FLAG_FALL_EDGE 0x0020
++#define TIMER_FLAG_ANY_EDGE 0x0030
++/* Signal is syncronous to module clock or not. */
++#define TIMER_FLAG_UNSYNC 0x0000
++#define TIMER_FLAG_SYNC 0x0080
++/* Different interrupt handle type. */
++#define TIMER_FLAG_NO_HANDLE 0x0000
++#if defined(__KERNEL__)
++ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
++#endif // defined(__KERNEL__)
++#define TIMER_FLAG_SIGNAL 0x0300
++/* Internal clock source or external clock source */
++#define TIMER_FLAG_INT_SRC 0x0000
++#define TIMER_FLAG_EXT_SRC 0x1000
++
++
++/*
++ * ioctl Command
++ */
++#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
++#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
++#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
++#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
++#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
++#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
++#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
++#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
++
++/*
++ * Data Type Used to Call ioctl
++ */
++struct gptu_ioctl_param {
++ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
++ * GPTU_SET_COUNTER, this field is ID of expected *
++ * timer/counter. If it's zero, a timer/counter would *
++ * be dynamically allocated and ID would be stored in *
++ * this field. *
++ * In command GPTU_GET_COUNT_VALUE, this field is *
++ * ignored. *
++ * In other command, this field is ID of timer/counter *
++ * allocated. */
++ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
++ * GPTU_SET_COUNTER, this field contains flags to *
++ * specify how to configure timer/counter. *
++ * In command GPTU_START_TIMER, zero indicate start *
++ * and non-zero indicate resume timer/counter. *
++ * In other command, this field is ignored. */
++ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
++ * init/reload value. *
++ * In command GPTU_SET_TIMER, this field contains *
++ * frequency (0.001Hz) of timer. *
++ * In command GPTU_GET_COUNT_VALUE, current count *
++ * value would be stored in this field. *
++ * In command GPTU_CALCULATE_DIVIDER, this field *
++ * contains frequency wanted, and after calculation, *
++ * divider would be stored in this field to overwrite *
++ * the frequency. *
++ * In other command, this field is ignored. */
++ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
++ * if signal is required, this field contains process *
++ * ID to which signal would be sent. *
++ * In other command, this field is ignored. */
++ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
++ * if signal is required, this field contains signal *
++ * number which would be sent. *
++ * In other command, this field is ignored. */
++};
++
++/*
++ * ####################################
++ * Data Type
++ * ####################################
++ */
++typedef void (*timer_callback)(unsigned long arg);
++
++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
++extern int lq_free_timer(unsigned int);
++extern int lq_start_timer(unsigned int, int);
++extern int lq_stop_timer(unsigned int);
++extern int lq_reset_counter_flags(u32 timer, u32 flags);
++extern int lq_get_count_value(unsigned int, unsigned long *);
++extern u32 lq_cal_divider(unsigned long);
++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
++extern int lq_set_counter(unsigned int timer, unsigned int flag,
++ u32 reload, unsigned long arg1, unsigned long arg2);
++
++#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
+--- a/arch/mips/lantiq/xway/Makefile
++++ b/arch/mips/lantiq/xway/Makefile
+@@ -1,4 +1,10 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+-obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
++obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o
++
++ifdef CONFIG_SOC_AMAZON_SE
++obj-y += gptu.o
++else
++obj-y += timer.o
++endif
+
+ obj-y += vmmc.o
+--- /dev/null
++++ b/arch/mips/lantiq/xway/timer.c
+@@ -0,0 +1,887 @@
++#ifndef CONFIG_SOC_AMAZON_SE
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/version.h>
++#include <linux/types.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <linux/init.h>
++#include <linux/uaccess.h>
++#include <linux/unistd.h>
++#include <linux/errno.h>
++#include <linux/interrupt.h>
++#include <linux/sched.h>
++#include <linux/sched/signal.h>
++
++#include <linux/of_platform.h>
++
++#include <asm/irq.h>
++#include <asm/div64.h>
++#include "../clk.h"
++
++#include <lantiq_soc.h>
++#include <lantiq_irq.h>
++#include <lantiq_timer.h>
++
++#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
++
++#ifdef TIMER1A
++#define FIRST_TIMER TIMER1A
++#else
++#define FIRST_TIMER 2
++#endif
++
++/*
++ * GPTC divider is set or not.
++ */
++#define GPTU_CLC_RMC_IS_SET 0
++
++/*
++ * Timer Interrupt (IRQ)
++ */
++/* Must be adjusted when ICU driver is available */
++#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
++
++/*
++ * Bits Operation
++ */
++#define GET_BITS(x, msb, lsb) \
++ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
++#define SET_BITS(x, msb, lsb, value) \
++ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
++ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
++
++/*
++ * GPTU Register Mapping
++ */
++#define LQ_GPTU (KSEG1 + 0x1E100A00)
++#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000))
++#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008))
++#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
++#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
++#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
++#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
++#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4))
++#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8))
++#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC))
++
++/*
++ * Clock Control Register
++ */
++#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16)
++#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8)
++#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5))
++#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3))
++#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2))
++#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1))
++#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0))
++
++#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
++#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
++#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
++#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
++#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
++#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
++#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
++
++/*
++ * ID Register
++ */
++#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8)
++#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5)
++#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0)
++
++/*
++ * Control Register of Timer/Counter nX
++ * n is the index of block (1 based index)
++ * X is either A or B
++ */
++#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10))
++#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9))
++#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8))
++#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
++#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5))
++#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
++#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3))
++#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2))
++#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1))
++#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0))
++
++#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
++#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
++#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
++#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
++#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
++#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
++#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
++#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
++#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
++
++#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
++#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
++#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
++
++#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
++#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
++
++#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
++#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
++#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
++#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
++#define TIMER_FLAG_NONE_EDGE 0x0000
++#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
++#define TIMER_FLAG_REAL 0x0000
++#define TIMER_FLAG_INVERT 0x0040
++#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
++#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
++#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
++#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
++#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
++#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
++
++struct timer_dev_timer {
++ unsigned int f_irq_on;
++ unsigned int irq;
++ unsigned int flag;
++ unsigned long arg1;
++ unsigned long arg2;
++};
++
++struct timer_dev {
++ struct mutex gptu_mutex;
++ unsigned int number_of_timers;
++ unsigned int occupation;
++ unsigned int f_gptu_on;
++ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
++};
++
++
++unsigned int ltq_get_fpi_bus_clock(int fpi) {
++ struct clk *clk = clk_get_fpi();
++ return clk_get_rate(clk);
++}
++
++
++static long gptu_ioctl(struct file *, unsigned int, unsigned long);
++static int gptu_open(struct inode *, struct file *);
++static int gptu_release(struct inode *, struct file *);
++
++static struct file_operations gptu_fops = {
++ .owner = THIS_MODULE,
++ .unlocked_ioctl = gptu_ioctl,
++ .open = gptu_open,
++ .release = gptu_release
++};
++
++static struct miscdevice gptu_miscdev = {
++ .minor = MISC_DYNAMIC_MINOR,
++ .name = "gptu",
++ .fops = &gptu_fops,
++};
++
++static struct timer_dev timer_dev;
++
++static irqreturn_t timer_irq_handler(int irq, void *p)
++{
++ unsigned int timer;
++ unsigned int flag;
++ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
++
++ timer = irq - TIMER_INTERRUPT;
++ if (timer < timer_dev.number_of_timers
++ && dev_timer == &timer_dev.timer[timer]) {
++ /* Clear interrupt. */
++ ltq_w32(1 << timer, LQ_GPTU_IRNCR);
++
++ /* Call user hanler or signal. */
++ flag = dev_timer->flag;
++ if (!(timer & 0x01)
++ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
++ /* 16-bit timer or timer A of 32-bit timer */
++ switch (TIMER_FLAG_MASK_HANDLE(flag)) {
++ case TIMER_FLAG_CALLBACK_IN_IRQ:
++ case TIMER_FLAG_CALLBACK_IN_HB:
++ if (dev_timer->arg1)
++ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
++ break;
++ case TIMER_FLAG_SIGNAL:
++ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
++ break;
++ }
++ }
++ }
++ return IRQ_HANDLED;
++}
++
++static inline void lq_enable_gptu(void)
++{
++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
++ clk_enable(clk);
++
++ //ltq_pmu_enable(PMU_GPT);
++
++ /* Set divider as 1, disable write protection for SPEN, enable module. */
++ *LQ_GPTU_CLC =
++ GPTU_CLC_SMC_SET(0x00) |
++ GPTU_CLC_RMC_SET(0x01) |
++ GPTU_CLC_FSOE_SET(0) |
++ GPTU_CLC_SBWE_SET(1) |
++ GPTU_CLC_EDIS_SET(0) |
++ GPTU_CLC_SPEN_SET(0) |
++ GPTU_CLC_DISR_SET(0);
++}
++
++static inline void lq_disable_gptu(void)
++{
++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
++ ltq_w32(0x00, LQ_GPTU_IRNEN);
++ ltq_w32(0xfff, LQ_GPTU_IRNCR);
++
++ /* Set divider as 0, enable write protection for SPEN, disable module. */
++ *LQ_GPTU_CLC =
++ GPTU_CLC_SMC_SET(0x00) |
++ GPTU_CLC_RMC_SET(0x00) |
++ GPTU_CLC_FSOE_SET(0) |
++ GPTU_CLC_SBWE_SET(0) |
++ GPTU_CLC_EDIS_SET(0) |
++ GPTU_CLC_SPEN_SET(0) |
++ GPTU_CLC_DISR_SET(1);
++
++ clk_enable(clk);
++}
++
++int lq_request_timer(unsigned int timer, unsigned int flag,
++ unsigned long value, unsigned long arg1, unsigned long arg2)
++{
++ int ret = 0;
++ unsigned int con_reg, irnen_reg;
++ int n, X;
++
++ if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
++ return -EINVAL;
++
++ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
++ timer, flag, value);
++
++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
++ value &= 0xFFFF;
++ else
++ timer &= ~0x01;
++
++ mutex_lock(&timer_dev.gptu_mutex);
++
++ /*
++ * Allocate timer.
++ */
++ if (timer < FIRST_TIMER) {
++ unsigned int mask;
++ unsigned int shift;
++ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
++ unsigned int offset = TIMER2A;
++
++ /*
++ * Pick up a free timer.
++ */
++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
++ mask = 1 << offset;
++ shift = 1;
++ } else {
++ mask = 3 << offset;
++ shift = 2;
++ }
++ for (timer = offset;
++ timer < offset + timer_dev.number_of_timers;
++ timer += shift, mask <<= shift)
++ if (!(timer_dev.occupation & mask)) {
++ timer_dev.occupation |= mask;
++ break;
++ }
++ if (timer >= offset + timer_dev.number_of_timers) {
++ printk("failed![%d]\n", __LINE__);
++ mutex_unlock(&timer_dev.gptu_mutex);
++ return -EINVAL;
++ } else
++ ret = timer;
++ } else {
++ register unsigned int mask;
++
++ /*
++ * Check if the requested timer is free.
++ */
++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++ if ((timer_dev.occupation & mask)) {
++ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
++ __LINE__, mask, timer_dev.occupation);
++ mutex_unlock(&timer_dev.gptu_mutex);
++ return -EBUSY;
++ } else {
++ timer_dev.occupation |= mask;
++ ret = 0;
++ }
++ }
++
++ /*
++ * Prepare control register value.
++ */
++ switch (TIMER_FLAG_MASK_EDGE(flag)) {
++ default:
++ case TIMER_FLAG_NONE_EDGE:
++ con_reg = GPTU_CON_EDGE_SET(0x00);
++ break;
++ case TIMER_FLAG_RISE_EDGE:
++ con_reg = GPTU_CON_EDGE_SET(0x01);
++ break;
++ case TIMER_FLAG_FALL_EDGE:
++ con_reg = GPTU_CON_EDGE_SET(0x02);
++ break;
++ case TIMER_FLAG_ANY_EDGE:
++ con_reg = GPTU_CON_EDGE_SET(0x03);
++ break;
++ }
++ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
++ con_reg |=
++ TIMER_FLAG_MASK_SRC(flag) ==
++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
++ GPTU_CON_SRC_EXT_SET(0);
++ else
++ con_reg |=
++ TIMER_FLAG_MASK_SRC(flag) ==
++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
++ GPTU_CON_SRC_EG_SET(0);
++ con_reg |=
++ TIMER_FLAG_MASK_SYNC(flag) ==
++ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
++ GPTU_CON_SYNC_SET(1);
++ con_reg |=
++ TIMER_FLAG_MASK_INVERT(flag) ==
++ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
++ con_reg |=
++ TIMER_FLAG_MASK_SIZE(flag) ==
++ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
++ GPTU_CON_EXT_SET(1);
++ con_reg |=
++ TIMER_FLAG_MASK_STOP(flag) ==
++ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
++ con_reg |=
++ TIMER_FLAG_MASK_TYPE(flag) ==
++ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
++ GPTU_CON_CNT_SET(1);
++ con_reg |=
++ TIMER_FLAG_MASK_DIR(flag) ==
++ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
++
++ /*
++ * Fill up running data.
++ */
++ timer_dev.timer[timer - FIRST_TIMER].flag = flag;
++ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
++ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
++
++ /*
++ * Enable GPTU module.
++ */
++ if (!timer_dev.f_gptu_on) {
++ lq_enable_gptu();
++ timer_dev.f_gptu_on = 1;
++ }
++
++ /*
++ * Enable IRQ.
++ */
++ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
++ timer_dev.timer[timer - FIRST_TIMER].arg1 =
++ (unsigned long) find_task_by_vpid((int) arg1);
++
++ irnen_reg = 1 << (timer - FIRST_TIMER);
++
++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
++ || (TIMER_FLAG_MASK_HANDLE(flag) ==
++ TIMER_FLAG_CALLBACK_IN_IRQ
++ && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
++ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
++ }
++ } else
++ irnen_reg = 0;
++
++ /*
++ * Write config register, reload value and enable interrupt.
++ */
++ n = timer >> 1;
++ X = timer & 0x01;
++ *LQ_GPTU_CON(n, X) = con_reg;
++ *LQ_GPTU_RELOAD(n, X) = value;
++ /* printk("reload value = %d\n", (u32)value); */
++ *LQ_GPTU_IRNEN |= irnen_reg;
++
++ mutex_unlock(&timer_dev.gptu_mutex);
++ printk("successful!\n");
++ return ret;
++}
++EXPORT_SYMBOL(lq_request_timer);
++
++int lq_free_timer(unsigned int timer)
++{
++ unsigned int flag;
++ unsigned int mask;
++ int n, X;
++
++ if (!timer_dev.f_gptu_on)
++ return -EINVAL;
++
++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++ return -EINVAL;
++
++ mutex_lock(&timer_dev.gptu_mutex);
++
++ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++ timer &= ~0x01;
++
++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++ if (((timer_dev.occupation & mask) ^ mask)) {
++ mutex_unlock(&timer_dev.gptu_mutex);
++ return -EINVAL;
++ }
++
++ n = timer >> 1;
++ X = timer & 0x01;
++
++ if (GPTU_CON_EN(n, X))
++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
++
++ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
++ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
++
++ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
++ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
++ }
++
++ timer_dev.occupation &= ~mask;
++ if (!timer_dev.occupation && timer_dev.f_gptu_on) {
++ lq_disable_gptu();
++ timer_dev.f_gptu_on = 0;
++ }
++
++ mutex_unlock(&timer_dev.gptu_mutex);
++
++ return 0;
++}
++EXPORT_SYMBOL(lq_free_timer);
++
++int lq_start_timer(unsigned int timer, int is_resume)
++{
++ unsigned int flag;
++ unsigned int mask;
++ int n, X;
++
++ if (!timer_dev.f_gptu_on)
++ return -EINVAL;
++
++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++ return -EINVAL;
++
++ mutex_lock(&timer_dev.gptu_mutex);
++
++ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++ timer &= ~0x01;
++
++ mask = (TIMER_FLAG_MASK_SIZE(flag) ==
++ TIMER_FLAG_16BIT ? 1 : 3) << timer;
++ if (((timer_dev.occupation & mask) ^ mask)) {
++ mutex_unlock(&timer_dev.gptu_mutex);
++ return -EINVAL;
++ }
++
++ n = timer >> 1;
++ X = timer & 0x01;
++
++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
++
++
++ mutex_unlock(&timer_dev.gptu_mutex);
++
++ return 0;
++}
++EXPORT_SYMBOL(lq_start_timer);
++
++int lq_stop_timer(unsigned int timer)
++{
++ unsigned int flag;
++ unsigned int mask;
++ int n, X;
++
++ if (!timer_dev.f_gptu_on)
++ return -EINVAL;
++
++ if (timer < FIRST_TIMER
++ || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++ return -EINVAL;
++
++ mutex_lock(&timer_dev.gptu_mutex);
++
++ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++ timer &= ~0x01;
++
++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++ if (((timer_dev.occupation & mask) ^ mask)) {
++ mutex_unlock(&timer_dev.gptu_mutex);
++ return -EINVAL;
++ }
++
++ n = timer >> 1;
++ X = timer & 0x01;
++
++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
++
++ mutex_unlock(&timer_dev.gptu_mutex);
++
++ return 0;
++}
++EXPORT_SYMBOL(lq_stop_timer);
++
++int lq_reset_counter_flags(u32 timer, u32 flags)
++{
++ unsigned int oflag;
++ unsigned int mask, con_reg;
++ int n, X;
++
++ if (!timer_dev.f_gptu_on)
++ return -EINVAL;
++
++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++ return -EINVAL;
++
++ mutex_lock(&timer_dev.gptu_mutex);
++
++ oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
++ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
++ timer &= ~0x01;
++
++ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++ if (((timer_dev.occupation & mask) ^ mask)) {
++ mutex_unlock(&timer_dev.gptu_mutex);
++ return -EINVAL;
++ }
++
++ switch (TIMER_FLAG_MASK_EDGE(flags)) {
++ default:
++ case TIMER_FLAG_NONE_EDGE:
++ con_reg = GPTU_CON_EDGE_SET(0x00);
++ break;
++ case TIMER_FLAG_RISE_EDGE:
++ con_reg = GPTU_CON_EDGE_SET(0x01);
++ break;
++ case TIMER_FLAG_FALL_EDGE:
++ con_reg = GPTU_CON_EDGE_SET(0x02);
++ break;
++ case TIMER_FLAG_ANY_EDGE:
++ con_reg = GPTU_CON_EDGE_SET(0x03);
++ break;
++ }
++ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
++ else
++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
++ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
++ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
++ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
++ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
++ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
++ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
++
++ timer_dev.timer[timer - FIRST_TIMER].flag = flags;
++ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
++
++ n = timer >> 1;
++ X = timer & 0x01;
++
++ *LQ_GPTU_CON(n, X) = con_reg;
++ smp_wmb();
++ mutex_unlock(&timer_dev.gptu_mutex);
++ return 0;
++}
++EXPORT_SYMBOL(lq_reset_counter_flags);
++
++int lq_get_count_value(unsigned int timer, unsigned long *value)
++{
++ unsigned int flag;
++ unsigned int mask;
++ int n, X;
++
++ if (!timer_dev.f_gptu_on)
++ return -EINVAL;
++
++ if (timer < FIRST_TIMER
++ || timer >= FIRST_TIMER + timer_dev.number_of_timers)
++ return -EINVAL;
++
++ mutex_lock(&timer_dev.gptu_mutex);
++
++ flag = timer_dev.timer[timer - FIRST_TIMER].flag;
++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
++ timer &= ~0x01;
++
++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
++ if (((timer_dev.occupation & mask) ^ mask)) {
++ mutex_unlock(&timer_dev.gptu_mutex);
++ return -EINVAL;
++ }
++
++ n = timer >> 1;
++ X = timer & 0x01;
++
++ *value = *LQ_GPTU_COUNT(n, X);
++
++
++ mutex_unlock(&timer_dev.gptu_mutex);
++
++ return 0;
++}
++EXPORT_SYMBOL(lq_get_count_value);
++
++u32 lq_cal_divider(unsigned long freq)
++{
++ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
++ u32 clock_divider = 1;
++ module_freq = fpi * 1000;
++ do_div(module_freq, clock_divider * freq);
++ return module_freq;
++}
++EXPORT_SYMBOL(lq_cal_divider);
++
++int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
++ int is_ext_src, unsigned int handle_flag, unsigned long arg1,
++ unsigned long arg2)
++{
++ unsigned long divider;
++ unsigned int flag;
++
++ divider = lq_cal_divider(freq);
++ if (divider == 0)
++ return -EINVAL;
++ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
++ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
++ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
++ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
++ | TIMER_FLAG_MASK_HANDLE(handle_flag);
++
++ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
++ timer, freq, divider);
++ return lq_request_timer(timer, flag, divider, arg1, arg2);
++}
++EXPORT_SYMBOL(lq_set_timer);
++
++int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
++ unsigned long arg1, unsigned long arg2)
++{
++ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
++ return lq_request_timer(timer, flag, reload, arg1, arg2);
++}
++EXPORT_SYMBOL(lq_set_counter);
++
++static long gptu_ioctl(struct file *file, unsigned int cmd,
++ unsigned long arg)
++{
++ int ret;
++ struct gptu_ioctl_param param;
++
++ if (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param)))
++ return -EFAULT;
++ if (copy_from_user(¶m, (void __user *)arg, sizeof(param)))
++ return -EFAULT;
++
++ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
++ || GPTU_SET_COUNTER) && param.timer < 2)
++ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
++ && !access_ok((void __user *)arg,
++ sizeof(struct gptu_ioctl_param)))
++ return -EFAULT;
++
++ switch (cmd) {
++ case GPTU_REQUEST_TIMER:
++ ret = lq_request_timer(param.timer, param.flag, param.value,
++ (unsigned long) param.pid,
++ (unsigned long) param.sig);
++ if (ret > 0) {
++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++ timer, &ret, sizeof(&ret)))
++ ret = -EFAULT;
++ else
++ ret = 0;
++ }
++ break;
++ case GPTU_FREE_TIMER:
++ ret = lq_free_timer(param.timer);
++ break;
++ case GPTU_START_TIMER:
++ ret = lq_start_timer(param.timer, param.flag);
++ break;
++ case GPTU_STOP_TIMER:
++ ret = lq_stop_timer(param.timer);
++ break;
++ case GPTU_GET_COUNT_VALUE:
++ ret = lq_get_count_value(param.timer, ¶m.value);
++ if (!ret && copy_to_user(&((struct gptu_ioctl_param *) arg)->
++ value, ¶m.value,sizeof(param.value)))
++ ret = -EFAULT;
++ break;
++ case GPTU_CALCULATE_DIVIDER:
++ param.value = lq_cal_divider(param.value);
++ if (param.value == 0)
++ ret = -EINVAL;
++ else if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++ value, ¶m.value,
++ sizeof(param.value)))
++ ret = -EFAULT;
++ else
++ ret = 0;
++ break;
++ case GPTU_SET_TIMER:
++ ret = lq_set_timer(param.timer, param.value,
++ TIMER_FLAG_MASK_STOP(param.flag) !=
++ TIMER_FLAG_ONCE ? 1 : 0,
++ TIMER_FLAG_MASK_SRC(param.flag) ==
++ TIMER_FLAG_EXT_SRC ? 1 : 0,
++ TIMER_FLAG_MASK_HANDLE(param.flag) ==
++ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
++ TIMER_FLAG_NO_HANDLE,
++ (unsigned long) param.pid,
++ (unsigned long) param.sig);
++ if (ret > 0) {
++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++ timer, &ret, sizeof(&ret)))
++ ret = -EFAULT;
++ else
++ ret = 0;
++ }
++ break;
++ case GPTU_SET_COUNTER:
++ lq_set_counter(param.timer, param.flag, param.value, 0, 0);
++ if (ret > 0) {
++ if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
++ timer, &ret, sizeof(&ret)))
++ ret = -EFAULT;
++ else
++ ret = 0;
++ }
++ break;
++ default:
++ ret = -ENOTTY;
++ }
++
++ return ret;
++}
++
++static int gptu_open(struct inode *inode, struct file *file)
++{
++ return 0;
++}
++
++static int gptu_release(struct inode *inode, struct file *file)
++{
++ return 0;
++}
++
++static int gptu_probe(struct platform_device *pdev)
++{
++ int ret;
++ int i;
++
++ ltq_w32(0, LQ_GPTU_IRNEN);
++ ltq_w32(0xfff, LQ_GPTU_IRNCR);
++
++ memset(&timer_dev, 0, sizeof(timer_dev));
++ mutex_init(&timer_dev.gptu_mutex);
++
++ lq_enable_gptu();
++ timer_dev.number_of_timers = GPTU_ID_CFG * 2;
++ lq_disable_gptu();
++ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
++ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
++ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
++
++ ret = misc_register(&gptu_miscdev);
++ if (ret) {
++ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
++ return ret;
++ } else {
++ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
++ }
++
++ for (i = 0; i < timer_dev.number_of_timers; i++) {
++ int irq = platform_get_irq(pdev, i);
++ if (irq < 0) {
++ printk(KERN_ERR "gptu: failed in getting irq (%d), get error %d\n", i, irq);
++ for (i--; i >= 0; i--)
++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
++ misc_deregister(&gptu_miscdev);
++ return irq;
++ }
++
++ ret = request_irq(irq, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
++ if (ret) {
++ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
++ for (i--; i >= 0; i--)
++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
++ misc_deregister(&gptu_miscdev);
++ return ret;
++ } else {
++ timer_dev.timer[i].irq = irq;
++ disable_irq(timer_dev.timer[i].irq);
++ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
++ }
++ }
++
++ return 0;
++}
++
++static const struct of_device_id gptu_match[] = {
++ { .compatible = "lantiq,gptu-xway" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, gptu_match);
++
++static struct platform_driver gptu_driver = {
++ .probe = gptu_probe,
++ .driver = {
++ .name = "gptu-xway",
++ .owner = THIS_MODULE,
++ .of_match_table = gptu_match,
++ },
++};
++
++int __init lq_gptu_init(void)
++{
++ int ret = platform_driver_register(&gptu_driver);
++
++ if (ret)
++ pr_info("gptu: Error registering platform driver\n");
++ return ret;
++}
++
++void __exit lq_gptu_exit(void)
++{
++ unsigned int i;
++
++ for (i = 0; i < timer_dev.number_of_timers; i++) {
++ if (timer_dev.timer[i].f_irq_on)
++ disable_irq(timer_dev.timer[i].irq);
++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
++ }
++ lq_disable_gptu();
++ misc_deregister(&gptu_miscdev);
++}
++
++module_init(lq_gptu_init);
++module_exit(lq_gptu_exit);
++
++#endif
--- /dev/null
+From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 9 Sep 2014 23:12:15 +0200
+Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/nand/raw/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 63 insertions(+)
+
+--- a/drivers/mtd/nand/raw/xway_nand.c
++++ b/drivers/mtd/nand/raw/xway_nand.c
+@@ -61,6 +61,24 @@
+ #define NAND_CON_CSMUX (1 << 1)
+ #define NAND_CON_NANDM 1
+
++#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr))
++#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400)
++#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080)
++
++/*
++ * req_mask provides a mechanism to prevent interference between
++ * nand and pci (probably only relevant for the BT Home Hub 2B).
++ * Setting it causes the corresponding pci req pins to be masked
++ * during nand access, and also moves ebu locking from the read/write
++ * functions to the chip select function to ensure that the whole
++ * operation runs with interrupts disabled.
++ * In addition it switches on some extra waiting in xway_cmd_ctrl().
++ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
++ * which in turn seems to be necessary for the nor chip to be recognised
++ * reliably, on a board (Home Hub 2B again) which has both nor and nand.
++ */
++static __be32 req_mask = 0;
++
+ struct xway_nand_data {
+ struct nand_controller controller;
+ struct nand_chip chip;
+@@ -92,10 +110,22 @@ static void xway_select_chip(struct nand
+ case -1:
+ ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
+ ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
++
++ if (req_mask) {
++ /* Unmask all external PCI request */
++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
++ }
++
+ spin_unlock_irqrestore(&ebu_lock, data->csflags);
+ break;
+ case 0:
+ spin_lock_irqsave(&ebu_lock, data->csflags);
++
++ if (req_mask) {
++ /* Mask all external PCI request */
++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
++ }
++
+ ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
+ ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
+ break;
+@@ -108,6 +138,11 @@ static void xway_cmd_ctrl(struct nand_ch
+ {
+ struct mtd_info *mtd = nand_to_mtd(chip);
+
++ if (req_mask) {
++ if (cmd != NAND_CMD_STATUS)
++ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */
++ }
++
+ if (cmd == NAND_CMD_NONE)
+ return;
+
+@@ -118,6 +153,24 @@ static void xway_cmd_ctrl(struct nand_ch
+
+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
+ ;
++
++ if (req_mask) {
++ /*
++ * program and erase have their own busy handlers
++ * status and sequential in needs no delay
++ */
++ switch (cmd) {
++ case NAND_CMD_ERASE1:
++ case NAND_CMD_SEQIN:
++ case NAND_CMD_STATUS:
++ case NAND_CMD_READID:
++ return;
++ }
++
++ /* wait until command is processed */
++ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
++ ;
++ }
+ }
+
+ static int xway_dev_ready(struct nand_chip *chip)
+@@ -169,6 +222,7 @@ static int xway_nand_probe(struct platfo
+ int err;
+ u32 cs;
+ u32 cs_flag = 0;
++ const __be32 *req_mask_ptr;
+
+ /* Allocate memory for the device structure (and zero it) */
+ data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),
+@@ -204,6 +258,15 @@ static int xway_nand_probe(struct platfo
+ if (!err && cs == 1)
+ cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
+
++ req_mask_ptr = of_get_property(pdev->dev.of_node,
++ "req-mask", NULL);
++
++ /*
++ * Load the PCI req lines to mask from the device tree. If the
++ * property is not present, setting req_mask to 0 disables masking.
++ */
++ req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
++
+ /* setup the EBU to run in NAND mode on our base addr */
+ ltq_ebu_w32(CPHYSADDR(data->nandaddr)
+ | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
--- /dev/null
+From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:18:00 +0200
+Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/maps/lantiq-flash.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/maps/lantiq-flash.c
++++ b/drivers/mtd/maps/lantiq-flash.c
+@@ -129,7 +129,11 @@ ltq_mtd_probe(struct platform_device *pd
+ if (!ltq_mtd->map)
+ return -ENOMEM;
+
+- ltq_mtd->map->phys = ltq_mtd->res->start;
++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
++ ltq_mtd->map->phys = NO_XIP;
++ else
++ ltq_mtd->map->phys = ltq_mtd->res->start;
++ ltq_mtd->res->start;
+ ltq_mtd->map->size = resource_size(ltq_mtd->res);
+ ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res);
+ if (IS_ERR(ltq_mtd->map->virt))
--- /dev/null
+From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:15:36 +0200
+Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/phy/Kconfig | 5 +
+ drivers/net/phy/Makefile | 1 +
+ drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 237 insertions(+)
+ create mode 100644 drivers/net/phy/lantiq.c
+
+--- a/drivers/net/phy/intel-xway.c
++++ b/drivers/net/phy/intel-xway.c
+@@ -229,6 +229,51 @@ static int xway_gphy_rgmii_init(struct p
+ XWAY_MDIO_MIICTRL_TXSKEW_MASK, val);
+ }
+
++#if IS_ENABLED(CONFIG_OF_MDIO)
++static int vr9_gphy_of_reg_init(struct phy_device *phydev)
++{
++ u32 tmp;
++
++ /* store the led values if one was passed by the devicetree */
++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp))
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp);
++
++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp))
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp);
++
++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp))
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp);
++
++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp))
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp);
++
++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp))
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp);
++
++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp))
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp);
++
++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp))
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, tmp);
++
++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp))
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp);
++
++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp))
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp);
++
++ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp))
++ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp);
++
++ return 0;
++}
++#else
++static int vr9_gphy_of_reg_init(struct phy_device *phydev)
++{
++ return 0;
++}
++#endif /* CONFIG_OF_MDIO */
++
+ static int xway_gphy_config_init(struct phy_device *phydev)
+ {
+ int err;
+@@ -280,6 +325,7 @@ static int xway_gphy_config_init(struct
+ if (err)
+ return err;
+
++ vr9_gphy_of_reg_init(phydev);
+ return 0;
+ }
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt
+@@ -0,0 +1,216 @@
++Lanitq PHY binding
++============================================
++
++This devicetree binding controls the lantiq ethernet phys led functionality.
++
++Example:
++ mdio@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "lantiq,xrx200-mdio";
++ phy5: ethernet-phy@5 {
++ reg = <0x1>;
++ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
++ };
++ phy11: ethernet-phy@11 {
++ reg = <0x11>;
++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++ lantiq,led2h = <0x00>;
++ lantiq,led2l = <0x03>;
++ };
++ phy12: ethernet-phy@12 {
++ reg = <0x12>;
++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++ lantiq,led1h = <0x00>;
++ lantiq,led1l = <0x03>;
++ };
++ phy13: ethernet-phy@13 {
++ reg = <0x13>;
++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++ lantiq,led2h = <0x00>;
++ lantiq,led2l = <0x03>;
++ };
++ phy14: ethernet-phy@14 {
++ reg = <0x14>;
++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
++ lantiq,led1h = <0x00>;
++ lantiq,led1l = <0x03>;
++ };
++ };
++
++Register Description
++============================================
++
++LEDCH:
++
++Name Hardware Reset Value
++LEDCH 0x00C5
++
++| 15 | | | | | | | 8 |
++=========================================
++| RES |
++=========================================
++
++| 7 | | | | | | | 0 |
++=========================================
++| FBF | SBF |RES | NACS |
++=========================================
++
++Field Bits Type Description
++FBF 7:6 RW Fast Blink Frequency
++ ---
++ 0x0 (00b) F02HZ 2 Hz blinking frequency
++ 0x1 (01b) F04HZ 4 Hz blinking frequency
++ 0x2 (10b) F08HZ 8 Hz blinking frequency
++ 0x3 (11b) F16HZ 16 Hz blinking frequency
++
++SBF 5:4 RW Slow Blink Frequency
++ ---
++ 0x0 (00b) F02HZ 2 Hz blinking frequency
++ 0x1 (01b) F04HZ 4 Hz blinking frequency
++ 0x2 (10b) F08HZ 8 Hz blinking frequency
++ 0x3 (11b) F16HZ 16 Hz blinking frequency
++
++NACS 2:0 RW Inverse of Scan Function
++ ---
++ 0x0 (000b) NONE No Function
++ 0x1 (001b) LINK Complex function enabled when link is up
++ 0x2 (010b) PDOWN Complex function enabled when device is powered-down
++ 0x3 (011b) EEE Complex function enabled when device is in EEE mode
++ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running
++ 0x5 (101b) ABIST Complex function enabled when analog self-test is running
++ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running
++ 0x7 (111b) TEST Complex function enabled when test mode is running
++
++LEDCL:
++
++Name Hardware Reset Value
++LEDCL 0x0067
++
++| 15 | | | | | | | 8 |
++=========================================
++| RES |
++=========================================
++
++| 7 | | | | | | | 0 |
++=========================================
++|RES | SCAN |RES | CBLINK |
++=========================================
++
++Field Bits Type Description
++SCAN 6:4 RW Complex Scan Configuration
++ ---
++ 000 B NONE No Function
++ 001 B LINK Complex function enabled when link is up
++ 010 B PDOWN Complex function enabled when device is powered-down
++ 011 B EEE Complex function enabled when device is in EEE mode
++ 100 B ANEG Complex function enabled when auto-negotiation is running
++ 101 B ABIST Complex function enabled when analog self-test is running
++ 110 B CDIAG Complex function enabled when cable diagnostics are running
++ 111 B TEST Complex function enabled when test mode is running
++
++CBLINK 2:0 RW Complex Blinking Configuration
++ ---
++ 000 B NONE No Function
++ 001 B LINK Complex function enabled when link is up
++ 010 B PDOWN Complex function enabled when device is powered-down
++ 011 B EEE Complex function enabled when device is in EEE mode
++ 100 B ANEG Complex function enabled when auto-negotiation is running
++ 101 B ABIST Complex function enabled when analog self-test is running
++ 110 B CDIAG Complex function enabled when cable diagnostics are running
++ 111 B TEST Complex function enabled when test mode is running
++
++LEDxH:
++
++Name Hardware Reset Value
++LED0H 0x0070
++LED1H 0x0020
++LED2H 0x0040
++LED3H 0x0040
++
++| 15 | | | | | | | 8 |
++=========================================
++| RES |
++=========================================
++
++| 7 | | | | | | | 0 |
++=========================================
++| CON | BLINKF |
++=========================================
++
++Field Bits Type Description
++CON 7:4 RW Constant On Configuration
++ ---
++ 0x0 (0000b) NONE LED does not light up constantly
++ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s
++ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s
++ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s
++ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s
++ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s
++ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s
++ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s
++ 0x8 (1000b) PDOWN LED is on when device is powered-down
++ 0x9 (1001b) EEE LED is on when device is in EEE mode
++ 0xA (1010b) ANEG LED is on when auto-negotiation is running
++ 0xB (1011b) ABIST LED is on when analog self-test is running
++ 0xC (1100b) CDIAG LED is on when cable diagnostics are running
++
++BLINKF 3:0 RW Fast Blinking Configuration
++ ---
++ 0x0 (0000b) NONE No Blinking
++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
++ 0x8 (1000b) PDOWN Blink when device is powered-down
++ 0x9 (1001b) EEE Blink when device is in EEE mode
++ 0xA (1010b) ANEG Blink when auto-negotiation is running
++ 0xB (1011b) ABIST Blink when analog self-test is running
++ 0xC (1100b) CDIAG Blink when cable diagnostics are running
++
++LEDxL:
++
++Name Hardware Reset Value
++LED0L 0x0003
++LED1L 0x0000
++LED2L 0x0000
++LED3L 0x0020
++
++| 15 | | | | | | | 8 |
++=========================================
++| RES |
++=========================================
++
++| 7 | | | | | | | 0 |
++=========================================
++| BLINKS | PULSE |
++=========================================
++
++Field Bits Type Description
++BLINKS 7:4 RW Slow Blinkin Configuration
++ ---
++ 0x0 (0000b) NONE No Blinking
++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
++ 0x8 (1000b) PDOWN Blink when device is powered-down
++ 0x9 (1001b) EEE Blink when device is in EEE mode
++ 0xA (1010b) ANEG Blink when auto-negotiation is running
++ 0xB (1011b) ABIST Blink when analog self-test is running
++ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning
++
++PULSE 3:0 RW Pulsing Configuration
++ The pulse field is a mask field by which certain events can be combined
++ ---
++ 0x0 (0000b) NONE No pulsing
++ 0x1 (0001b) TXACT Transmit activity
++ 0x2 (0010b) RXACT Receive activity
++ 0x4 (0100b) COL Collision
++ 0x8 (1000b) RES Reserved
--- /dev/null
+From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 9 Sep 2014 22:45:34 +0200
+Subject: [PATCH 28/36] NET: lantiq: various etop fixes
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++-----------
+ 1 file changed, 389 insertions(+), 166 deletions(-)
+
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -1,7 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /*
+ *
+- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
+ */
+
+ #include <linux/kernel.h>
+@@ -20,12 +20,17 @@
+ #include <linux/mm.h>
+ #include <linux/platform_device.h>
+ #include <linux/ethtool.h>
++#include <linux/if_vlan.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/module.h>
+ #include <linux/property.h>
++#include <linux/clk.h>
++#include <linux/of_net.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
+
+ #include <asm/checksum.h>
+
+@@ -33,7 +38,7 @@
+ #include <xway_dma.h>
+ #include <lantiq_platform.h>
+
+-#define LTQ_ETOP_MDIO 0x11804
++#define LTQ_ETOP_MDIO_ACC 0x11804
+ #define MDIO_REQUEST 0x80000000
+ #define MDIO_READ 0x40000000
+ #define MDIO_ADDR_MASK 0x1f
+@@ -42,44 +47,91 @@
+ #define MDIO_REG_OFFSET 0x10
+ #define MDIO_VAL_MASK 0xffff
+
+-#define PPE32_CGEN 0x800
+-#define LQ_PPE32_ENET_MAC_CFG 0x1840
++#define LTQ_ETOP_MDIO_CFG 0x11800
++#define MDIO_CFG_MASK 0x6
++
++#define LTQ_ETOP_CFG 0x11808
++#define LTQ_ETOP_IGPLEN 0x11820
++#define LTQ_ETOP_MAC_CFG 0x11840
+
+ #define LTQ_ETOP_ENETS0 0x11850
+ #define LTQ_ETOP_MAC_DA0 0x1186C
+ #define LTQ_ETOP_MAC_DA1 0x11870
+-#define LTQ_ETOP_CFG 0x16020
+-#define LTQ_ETOP_IGPLEN 0x16080
++
++#define MAC_CFG_MASK 0xfff
++#define MAC_CFG_CGEN (1 << 11)
++#define MAC_CFG_DUPLEX (1 << 2)
++#define MAC_CFG_SPEED (1 << 1)
++#define MAC_CFG_LINK (1 << 0)
+
+ #define MAX_DMA_CHAN 0x8
+ #define MAX_DMA_CRC_LEN 0x4
+ #define MAX_DMA_DATA_LEN 0x600
+
+ #define ETOP_FTCU BIT(28)
+-#define ETOP_MII_MASK 0xf
+-#define ETOP_MII_NORMAL 0xd
+-#define ETOP_MII_REVERSE 0xe
+ #define ETOP_PLEN_UNDER 0x40
+-#define ETOP_CGEN 0x800
++#define ETOP_CFG_MII0 0x01
+
+-/* use 2 static channels for TX/RX */
+-#define LTQ_ETOP_TX_CHANNEL 1
+-#define LTQ_ETOP_RX_CHANNEL 6
+-#define IS_TX(x) ((x) == LTQ_ETOP_TX_CHANNEL)
+-#define IS_RX(x) ((x) == LTQ_ETOP_RX_CHANNEL)
++#define ETOP_CFG_MASK 0xfff
++#define ETOP_CFG_FEN0 (1 << 8)
++#define ETOP_CFG_SEN0 (1 << 6)
++#define ETOP_CFG_OFF1 (1 << 3)
++#define ETOP_CFG_REMII0 (1 << 1)
++#define ETOP_CFG_OFF0 (1 << 0)
++
++#define LTQ_GBIT_MDIO_CTL 0xCC
++#define LTQ_GBIT_MDIO_DATA 0xd0
++#define LTQ_GBIT_GCTL0 0x68
++#define LTQ_GBIT_PMAC_HD_CTL 0x8c
++#define LTQ_GBIT_P0_CTL 0x4
++#define LTQ_GBIT_PMAC_RX_IPG 0xa8
++#define LTQ_GBIT_RGMII_CTL 0x78
++
++#define PMAC_HD_CTL_AS (1 << 19)
++#define PMAC_HD_CTL_RXSH (1 << 22)
++
++/* Switch Enable (0=disable, 1=enable) */
++#define GCTL0_SE 0x80000000
++/* Disable MDIO auto polling (0=disable, 1=enable) */
++#define PX_CTL_DMDIO 0x00400000
++
++/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
++#define MDC_CLOCK_MASK 0xff000000
++#define MDC_CLOCK_OFFSET 24
++
++/* register information for the gbit's MDIO bus */
++#define MDIO_XR9_REQUEST 0x00008000
++#define MDIO_XR9_READ 0x00000800
++#define MDIO_XR9_WRITE 0x00000400
++#define MDIO_XR9_REG_MASK 0x1f
++#define MDIO_XR9_ADDR_MASK 0x1f
++#define MDIO_XR9_RD_MASK 0xffff
++#define MDIO_XR9_REG_OFFSET 0
++#define MDIO_XR9_ADDR_OFFSET 5
++#define MDIO_XR9_WR_OFFSET 16
+
++#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
++ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
++
++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
+ #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
+ #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
+ #define ltq_etop_w32_mask(x, y, z) \
+ ltq_w32_mask(x, y, ltq_etop_membase + (z))
+
+-#define DRV_VERSION "1.0"
++#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
++#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
++#define ltq_gbit_w32_mask(x, y, z) \
++ ltq_w32_mask(x, y, ltq_gbit_membase + (z))
++
++#define DRV_VERSION "1.2"
+
+ static void __iomem *ltq_etop_membase;
++static void __iomem *ltq_gbit_membase;
+
+ struct ltq_etop_chan {
+- int idx;
+ int tx_free;
++ int irq;
+ struct net_device *netdev;
+ struct napi_struct napi;
+ struct ltq_dma_channel dma;
+@@ -89,26 +141,39 @@ struct ltq_etop_chan {
+ struct ltq_etop_priv {
+ struct net_device *netdev;
+ struct platform_device *pdev;
+- struct ltq_eth_data *pldata;
+ struct resource *res;
+
+ struct mii_bus *mii_bus;
+
+- struct ltq_etop_chan ch[MAX_DMA_CHAN];
+- int tx_free[MAX_DMA_CHAN >> 1];
++ struct ltq_etop_chan txch;
++ struct ltq_etop_chan rxch;
+
+ int tx_burst_len;
+ int rx_burst_len;
+
+- spinlock_t lock;
++ int tx_irq;
++ int rx_irq;
++
++ unsigned char mac[6];
++ phy_interface_t mii_mode;
++
++ spinlock_t lock;
++
++ struct clk *clk_ppe;
++ struct clk *clk_switch;
++ struct clk *clk_ephy;
++ struct clk *clk_ephycgu;
+ };
+
++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
++ int phy_reg, u16 phy_data);
++
+ static int
+ ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
+ {
+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+
+- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
++ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
+ if (!ch->skb[ch->dma.desc])
+ return -ENOMEM;
+ ch->dma.desc_base[ch->dma.desc].addr =
+@@ -143,8 +208,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ skb_put(skb, len);
++ skb->dev = ch->netdev;
+ skb->protocol = eth_type_trans(skb, ch->netdev);
+ netif_receive_skb(skb);
++ ch->netdev->stats.rx_packets++;
++ ch->netdev->stats.rx_bytes += len;
+ }
+
+ static int
+@@ -152,7 +220,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
+ {
+ struct ltq_etop_chan *ch = container_of(napi,
+ struct ltq_etop_chan, napi);
++ struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ int work_done = 0;
++ unsigned long flags;
+
+ while (work_done < budget) {
+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+@@ -164,7 +234,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
+ }
+ if (work_done < budget) {
+ napi_complete_done(&ch->napi, work_done);
++ spin_lock_irqsave(&priv->lock, flags);
+ ltq_dma_ack_irq(&ch->dma);
++ spin_unlock_irqrestore(&priv->lock, flags);
+ }
+ return work_done;
+ }
+@@ -176,12 +248,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
+ container_of(napi, struct ltq_etop_chan, napi);
+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
+ struct netdev_queue *txq =
+- netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
++ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ while ((ch->dma.desc_base[ch->tx_free].ctl &
+ (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
++ ch->netdev->stats.tx_packets++;
++ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
+ dev_kfree_skb_any(ch->skb[ch->tx_free]);
+ ch->skb[ch->tx_free] = NULL;
+ memset(&ch->dma.desc_base[ch->tx_free], 0,
+@@ -194,7 +268,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
+ if (netif_tx_queue_stopped(txq))
+ netif_tx_start_queue(txq);
+ napi_complete(&ch->napi);
++ spin_lock_irqsave(&priv->lock, flags);
+ ltq_dma_ack_irq(&ch->dma);
++ spin_unlock_irqrestore(&priv->lock, flags);
+ return 1;
+ }
+
+@@ -202,9 +278,10 @@ static irqreturn_t
+ ltq_etop_dma_irq(int irq, void *_priv)
+ {
+ struct ltq_etop_priv *priv = _priv;
+- int ch = irq - LTQ_DMA_CH0_INT;
+-
+- napi_schedule(&priv->ch[ch].napi);
++ if (irq == priv->txch.dma.irq)
++ napi_schedule(&priv->txch.napi);
++ else
++ napi_schedule(&priv->rxch.napi);
+ return IRQ_HANDLED;
+ }
+
+@@ -216,7 +293,7 @@ ltq_etop_free_channel(struct net_device
+ ltq_dma_free(&ch->dma);
+ if (ch->dma.irq)
+ free_irq(ch->dma.irq, priv);
+- if (IS_RX(ch->idx)) {
++ if (ch == &priv->txch) {
+ int desc;
+
+ for (desc = 0; desc < LTQ_DESC_NUM; desc++)
+@@ -228,80 +305,135 @@ static void
+ ltq_etop_hw_exit(struct net_device *dev)
+ {
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+- int i;
+
+- ltq_pmu_disable(PMU_PPE);
+- for (i = 0; i < MAX_DMA_CHAN; i++)
+- if (IS_TX(i) || IS_RX(i))
+- ltq_etop_free_channel(dev, &priv->ch[i]);
++ clk_disable(priv->clk_ppe);
++
++ if (of_machine_is_compatible("lantiq,ar9"))
++ clk_disable(priv->clk_switch);
++
++ if (of_machine_is_compatible("lantiq,ase")) {
++ clk_disable(priv->clk_ephy);
++ clk_disable(priv->clk_ephycgu);
++ }
++
++ ltq_etop_free_channel(dev, &priv->txch);
++ ltq_etop_free_channel(dev, &priv->rxch);
++}
++
++static void
++ltq_etop_gbit_init(struct net_device *dev)
++{
++ struct ltq_etop_priv *priv = netdev_priv(dev);
++
++ clk_enable(priv->clk_switch);
++
++ /* enable gbit port0 on the SoC */
++ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
++
++ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
++ /* disable MDIO auto polling mode */
++ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
++ /* set 1522 packet size */
++ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
++ /* disable pmac & dmac headers */
++ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
++ LTQ_GBIT_PMAC_HD_CTL);
++ /* Due to traffic halt when burst length 8,
++ replace default IPG value with 0x3B */
++ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
++ /* set mdc clock to 2.5 MHz */
++ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
++ LTQ_GBIT_RGMII_CTL);
+ }
+
+ static int
+ ltq_etop_hw_init(struct net_device *dev)
+ {
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+- int i;
+- int err;
++ phy_interface_t mii_mode = priv->mii_mode;
+
+- ltq_pmu_enable(PMU_PPE);
++ clk_enable(priv->clk_ppe);
+
+- switch (priv->pldata->mii_mode) {
++ if (of_machine_is_compatible("lantiq,ar9")) {
++ ltq_etop_gbit_init(dev);
++ /* force the etops link to the gbit to MII */
++ mii_mode = PHY_INTERFACE_MODE_MII;
++ }
++ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
++ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
++ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
++
++ switch (mii_mode) {
+ case PHY_INTERFACE_MODE_RMII:
+- ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_REVERSE,
+- LTQ_ETOP_CFG);
++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
+ break;
+
+ case PHY_INTERFACE_MODE_MII:
+- ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_NORMAL,
+- LTQ_ETOP_CFG);
++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
+ break;
+
+ default:
++ if (of_machine_is_compatible("lantiq,ase")) {
++ clk_enable(priv->clk_ephy);
++ /* disable external MII */
++ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
++ /* enable clock for internal PHY */
++ clk_enable(priv->clk_ephycgu);
++ /* we need to write this magic to the internal phy to
++ make it work */
++ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
++ pr_info("Selected EPHY mode\n");
++ break;
++ }
+ netdev_err(dev, "unknown mii mode %d\n",
+- priv->pldata->mii_mode);
++ mii_mode);
+ return -ENOTSUPP;
+ }
+
+- /* enable crc generation */
+- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
++ return 0;
++}
++
++static int
++ltq_etop_dma_init(struct net_device *dev)
++{
++ struct ltq_etop_priv *priv = netdev_priv(dev);
++ int tx = priv->tx_irq - LTQ_DMA_ETOP;
++ int rx = priv->rx_irq - LTQ_DMA_ETOP;
++ int err;
+
+ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len);
+
+- for (i = 0; i < MAX_DMA_CHAN; i++) {
+- int irq = LTQ_DMA_CH0_INT + i;
+- struct ltq_etop_chan *ch = &priv->ch[i];
+-
+- ch->dma.nr = i;
+- ch->idx = ch->dma.nr;
+- ch->dma.dev = &priv->pdev->dev;
+-
+- if (IS_TX(i)) {
+- ltq_dma_alloc_tx(&ch->dma);
+- err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
+- if (err) {
+- netdev_err(dev,
+- "Unable to get Tx DMA IRQ %d\n",
+- irq);
+- return err;
+- }
+- } else if (IS_RX(i)) {
+- ltq_dma_alloc_rx(&ch->dma);
+- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
+- ch->dma.desc++)
+- if (ltq_etop_alloc_skb(ch))
+- return -ENOMEM;
+- ch->dma.desc = 0;
+- err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
+- if (err) {
+- netdev_err(dev,
+- "Unable to get Rx DMA IRQ %d\n",
+- irq);
+- return err;
+- }
++ priv->txch.dma.nr = tx;
++ priv->txch.dma.dev = &priv->pdev->dev;
++ ltq_dma_alloc_tx(&priv->txch.dma);
++ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
++ if (err) {
++ netdev_err(dev, "failed to allocate tx irq\n");
++ goto err_out;
++ }
++ priv->txch.dma.irq = priv->tx_irq;
++
++ priv->rxch.dma.nr = rx;
++ priv->rxch.dma.dev = &priv->pdev->dev;
++ ltq_dma_alloc_rx(&priv->rxch.dma);
++ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
++ priv->rxch.dma.desc++) {
++ if (ltq_etop_alloc_skb(&priv->rxch)) {
++ netdev_err(dev, "failed to allocate skbs\n");
++ err = -ENOMEM;
++ goto err_out;
+ }
+- ch->dma.irq = irq;
+ }
+- return 0;
++ priv->rxch.dma.desc = 0;
++ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
++ if (err)
++ netdev_err(dev, "failed to allocate rx irq\n");
++ else
++ priv->rxch.dma.irq = priv->rx_irq;
++err_out:
++ return err;
+ }
+
+ static void
+@@ -320,6 +452,39 @@ static const struct ethtool_ops ltq_etop
+ };
+
+ static int
++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
++ int phy_reg, u16 phy_data)
++{
++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
++ (phy_data << MDIO_XR9_WR_OFFSET) |
++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
++
++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++ ;
++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++ ;
++ return 0;
++}
++
++static int
++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
++{
++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
++
++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++ ;
++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++ ;
++ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
++ return val;
++}
++
++static int
+ ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
+ {
+ u32 val = MDIO_REQUEST |
+@@ -327,9 +492,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
+ ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
+ phy_data;
+
+- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ ;
+- ltq_etop_w32(val, LTQ_ETOP_MDIO);
++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
+ return 0;
+ }
+
+@@ -340,12 +505,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
+ ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
+ ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
+
+- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ ;
+- ltq_etop_w32(val, LTQ_ETOP_MDIO);
+- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
+ ;
+- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
++ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
+ return val;
+ }
+
+@@ -361,7 +526,10 @@ ltq_etop_mdio_probe(struct net_device *d
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+ struct phy_device *phydev;
+
+- phydev = phy_find_first(priv->mii_bus);
++ if (of_machine_is_compatible("lantiq,ase"))
++ phydev = mdiobus_get_phy(priv->mii_bus, 8);
++ else
++ phydev = mdiobus_get_phy(priv->mii_bus, 0);
+
+ if (!phydev) {
+ netdev_err(dev, "no PHY found\n");
+@@ -369,14 +537,17 @@ ltq_etop_mdio_probe(struct net_device *d
+ }
+
+ phydev = phy_connect(dev, phydev_name(phydev),
+- <q_etop_mdio_link, priv->pldata->mii_mode);
++ <q_etop_mdio_link, priv->mii_mode);
+
+ if (IS_ERR(phydev)) {
+ netdev_err(dev, "Could not attach to PHY\n");
+ return PTR_ERR(phydev);
+ }
+
+- phy_set_max_speed(phydev, SPEED_100);
++ if (of_machine_is_compatible("lantiq,ar9"))
++ phy_set_max_speed(phydev, SPEED_1000);
++ else
++ phy_set_max_speed(phydev, SPEED_100);
+
+ phy_attached_info(phydev);
+
+@@ -397,8 +568,13 @@ ltq_etop_mdio_init(struct net_device *de
+ }
+
+ priv->mii_bus->priv = dev;
+- priv->mii_bus->read = ltq_etop_mdio_rd;
+- priv->mii_bus->write = ltq_etop_mdio_wr;
++ if (of_machine_is_compatible("lantiq,ar9")) {
++ priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
++ priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
++ } else {
++ priv->mii_bus->read = ltq_etop_mdio_rd;
++ priv->mii_bus->write = ltq_etop_mdio_wr;
++ }
+ priv->mii_bus->name = "ltq_mii";
+ snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+ priv->pdev->name, priv->pdev->id);
+@@ -435,18 +611,21 @@ static int
+ ltq_etop_open(struct net_device *dev)
+ {
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+- int i;
++ unsigned long flags;
+
+- for (i = 0; i < MAX_DMA_CHAN; i++) {
+- struct ltq_etop_chan *ch = &priv->ch[i];
++ napi_enable(&priv->txch.napi);
++ napi_enable(&priv->rxch.napi);
++
++ spin_lock_irqsave(&priv->lock, flags);
++ ltq_dma_open(&priv->txch.dma);
++ ltq_dma_enable_irq(&priv->txch.dma);
++ ltq_dma_open(&priv->rxch.dma);
++ ltq_dma_enable_irq(&priv->rxch.dma);
++ spin_unlock_irqrestore(&priv->lock, flags);
++
++ if (dev->phydev)
++ phy_start(dev->phydev);
+
+- if (!IS_TX(i) && (!IS_RX(i)))
+- continue;
+- ltq_dma_open(&ch->dma);
+- ltq_dma_enable_irq(&ch->dma);
+- napi_enable(&ch->napi);
+- }
+- phy_start(dev->phydev);
+ netif_tx_start_all_queues(dev);
+ return 0;
+ }
+@@ -455,18 +634,19 @@ static int
+ ltq_etop_stop(struct net_device *dev)
+ {
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+- int i;
++ unsigned long flags;
+
+ netif_tx_stop_all_queues(dev);
+- phy_stop(dev->phydev);
+- for (i = 0; i < MAX_DMA_CHAN; i++) {
+- struct ltq_etop_chan *ch = &priv->ch[i];
+-
+- if (!IS_RX(i) && !IS_TX(i))
+- continue;
+- napi_disable(&ch->napi);
+- ltq_dma_close(&ch->dma);
+- }
++ if (dev->phydev)
++ phy_stop(dev->phydev);
++ napi_disable(&priv->txch.napi);
++ napi_disable(&priv->rxch.napi);
++
++ spin_lock_irqsave(&priv->lock, flags);
++ ltq_dma_close(&priv->txch.dma);
++ ltq_dma_close(&priv->rxch.dma);
++ spin_unlock_irqrestore(&priv->lock, flags);
++
+ return 0;
+ }
+
+@@ -476,15 +656,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
+ int queue = skb_get_queue_mapping(skb);
+ struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
+- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+- int len;
++ struct ltq_dma_desc *desc =
++ &priv->txch.dma.desc_base[priv->txch.dma.desc];
+ unsigned long flags;
+ u32 byte_offset;
++ int len;
+
+ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+
+- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
++ priv->txch.skb[priv->txch.dma.desc]) {
+ netdev_err(dev, "tx ring full\n");
+ netif_tx_stop_queue(txq);
+ return NETDEV_TX_BUSY;
+@@ -492,7 +673,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
+
+ /* dma needs to start on a burst length value aligned address */
+ byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4);
+- ch->skb[ch->dma.desc] = skb;
++ priv->txch.skb[priv->txch.dma.desc] = skb;
+
+ netif_trans_update(dev);
+
+@@ -503,11 +684,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
+ wmb();
+ desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
+ LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
+- ch->dma.desc++;
+- ch->dma.desc %= LTQ_DESC_NUM;
++ priv->txch.dma.desc++;
++ priv->txch.dma.desc %= LTQ_DESC_NUM;
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
++ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
+ netif_tx_stop_queue(txq);
+
+ return NETDEV_TX_OK;
+@@ -518,11 +699,14 @@ ltq_etop_change_mtu(struct net_device *d
+ {
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+ unsigned long flags;
++ int max;
+
+ dev->mtu = new_mtu;
+
++ max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
++
+ spin_lock_irqsave(&priv->lock, flags);
+- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
++ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return 0;
+@@ -575,6 +759,9 @@ ltq_etop_init(struct net_device *dev)
+ if (err)
+ goto err_hw;
+ ltq_etop_change_mtu(dev, 1500);
++ err = ltq_etop_dma_init(dev);
++ if (err)
++ goto err_hw;
+
+ memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
+ if (!is_valid_ether_addr(mac.sa_data)) {
+@@ -592,9 +779,10 @@ ltq_etop_init(struct net_device *dev)
+ dev->addr_assign_type = NET_ADDR_RANDOM;
+
+ ltq_etop_set_multicast_list(dev);
+- err = ltq_etop_mdio_init(dev);
+- if (err)
+- goto err_netdev;
++ if (!ltq_etop_mdio_init(dev))
++ dev->ethtool_ops = <q_etop_ethtool_ops;
++ else
++ pr_warn("etop: mdio probe failed\n");;
+ return 0;
+
+ err_netdev:
+@@ -614,6 +802,9 @@ ltq_etop_tx_timeout(struct net_device *d
+ err = ltq_etop_hw_init(dev);
+ if (err)
+ goto err_hw;
++ err = ltq_etop_dma_init(dev);
++ if (err)
++ goto err_hw;
+ netif_trans_update(dev);
+ netif_wake_queue(dev);
+ return;
+@@ -637,14 +828,18 @@ static const struct net_device_ops ltq_e
+ .ndo_tx_timeout = ltq_etop_tx_timeout,
+ };
+
+-static int __init
+-ltq_etop_probe(struct platform_device *pdev)
++static int ltq_etop_probe(struct platform_device *pdev)
+ {
+ struct net_device *dev;
+ struct ltq_etop_priv *priv;
+- struct resource *res;
++ struct resource *res, *gbit_res, irqres[2];
+ int err;
+- int i;
++
++ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
++ if (err != 2) {
++ dev_err(&pdev->dev, "failed to get etop irqs\n");
++ return -EINVAL;
++ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+@@ -670,19 +865,55 @@ ltq_etop_probe(struct platform_device *p
+ goto err_out;
+ }
+
+- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
+- if (!dev) {
+- err = -ENOMEM;
+- goto err_out;
++ if (of_machine_is_compatible("lantiq,ar9")) {
++ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ if (!gbit_res) {
++ dev_err(&pdev->dev, "failed to get gbit resource\n");
++ err = -ENOENT;
++ goto err_out;
++ }
++ ltq_gbit_membase = devm_ioremap(&pdev->dev,
++ gbit_res->start, resource_size(gbit_res));
++ if (!ltq_gbit_membase) {
++ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
++ pdev->id);
++ err = -ENOMEM;
++ goto err_out;
++ }
+ }
++
++ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
+ strcpy(dev->name, "eth%d");
+ dev->netdev_ops = <q_eth_netdev_ops;
+- dev->ethtool_ops = <q_etop_ethtool_ops;
+ priv = netdev_priv(dev);
+ priv->res = res;
+ priv->pdev = pdev;
+- priv->pldata = dev_get_platdata(&pdev->dev);
+ priv->netdev = dev;
++ priv->tx_irq = irqres[0].start;
++ priv->rx_irq = irqres[1].start;
++ err = of_get_phy_mode(pdev->dev.of_node, &priv->mii_mode);
++ if (err)
++ pr_err("Can't find phy-mode for port\n");
++
++ of_get_mac_address(pdev->dev.of_node, priv->mac);
++
++ priv->clk_ppe = clk_get(&pdev->dev, NULL);
++ if (IS_ERR(priv->clk_ppe))
++ return PTR_ERR(priv->clk_ppe);
++ if (of_machine_is_compatible("lantiq,ar9")) {
++ priv->clk_switch = clk_get(&pdev->dev, "switch");
++ if (IS_ERR(priv->clk_switch))
++ return PTR_ERR(priv->clk_switch);
++ }
++ if (of_machine_is_compatible("lantiq,ase")) {
++ priv->clk_ephy = clk_get(&pdev->dev, "ephy");
++ if (IS_ERR(priv->clk_ephy))
++ return PTR_ERR(priv->clk_ephy);
++ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
++ if (IS_ERR(priv->clk_ephycgu))
++ return PTR_ERR(priv->clk_ephycgu);
++ }
++
+ spin_lock_init(&priv->lock);
+ SET_NETDEV_DEV(dev, &pdev->dev);
+
+@@ -698,15 +929,10 @@ ltq_etop_probe(struct platform_device *p
+ goto err_free;
+ }
+
+- for (i = 0; i < MAX_DMA_CHAN; i++) {
+- if (IS_TX(i))
+- netif_napi_add_weight(dev, &priv->ch[i].napi,
+- ltq_etop_poll_tx, 8);
+- else if (IS_RX(i))
+- netif_napi_add_weight(dev, &priv->ch[i].napi,
+- ltq_etop_poll_rx, 32);
+- priv->ch[i].netdev = dev;
+- }
++ netif_napi_add_weight(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
++ netif_napi_add_weight(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
++ priv->txch.netdev = dev;
++ priv->rxch.netdev = dev;
+
+ err = register_netdev(dev);
+ if (err)
+@@ -735,31 +961,22 @@ ltq_etop_remove(struct platform_device *
+ return 0;
+ }
+
++static const struct of_device_id ltq_etop_match[] = {
++ { .compatible = "lantiq,etop-xway" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, ltq_etop_match);
++
+ static struct platform_driver ltq_mii_driver = {
++ .probe = ltq_etop_probe,
+ .remove = ltq_etop_remove,
+ .driver = {
+ .name = "ltq_etop",
++ .of_match_table = ltq_etop_match,
+ },
+ };
+
+-static int __init
+-init_ltq_etop(void)
+-{
+- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe);
+-
+- if (ret)
+- pr_err("ltq_etop: Error registering platform driver!");
+- return ret;
+-}
+-
+-static void __exit
+-exit_ltq_etop(void)
+-{
+- platform_driver_unregister(<q_mii_driver);
+-}
+-
+-module_init(init_ltq_etop);
+-module_exit(exit_ltq_etop);
++module_platform_driver(ltq_mii_driver);
+
+ MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+ MODULE_DESCRIPTION("Lantiq SoC ETOP");
--- /dev/null
+From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 7 Aug 2014 18:26:42 +0200
+Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master
+
+This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/i2c/busses/Kconfig | 10 +
+ drivers/i2c/busses/Makefile | 1 +
+ drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++
+ drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++
+ 4 files changed, 992 insertions(+)
+ create mode 100644 drivers/i2c/busses/i2c-lantiq.c
+ create mode 100644 drivers/i2c/busses/i2c-lantiq.h
+
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -795,6 +795,16 @@ config I2C_MICROCHIP_CORE
+ This driver can also be built as a module. If so, the module will be
+ called i2c-microchip-core.
+
++config I2C_LANTIQ
++ tristate "Lantiq I2C interface"
++ depends on LANTIQ && SOC_FALCON
++ help
++ If you say yes to this option, support will be included for the
++ Lantiq I2C core.
++
++ This driver can also be built as a module. If so, the module
++ will be called i2c-lantiq.
++
+ config I2C_MPC
+ tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
+ depends on PPC
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-l
+ obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
+ obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
+ obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
++obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o
+ obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o
+ obj-$(CONFIG_I2C_MESON) += i2c-meson.o
+ obj-$(CONFIG_I2C_MICROCHIP_CORE) += i2c-microchip-corei2c.o
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-lantiq.c
+@@ -0,0 +1,747 @@
++
++/*
++ * Lantiq I2C bus adapter
++ *
++ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/slab.h> /* for kzalloc, kfree */
++#include <linux/i2c.h>
++#include <linux/errno.h>
++#include <linux/completion.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/of_irq.h>
++
++#include <lantiq_soc.h>
++#include "i2c-lantiq.h"
++
++/*
++ * CURRENT ISSUES:
++ * - no high speed support
++ * - ten bit mode is not tested (no slave devices)
++ */
++
++/* access macros */
++#define i2c_r32(reg) \
++ __raw_readl(&(priv->membase)->reg)
++#define i2c_w32(val, reg) \
++ __raw_writel(val, &(priv->membase)->reg)
++#define i2c_w32_mask(clear, set, reg) \
++ i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg)
++
++#define DRV_NAME "i2c-lantiq"
++#define DRV_VERSION "1.00"
++
++#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */
++
++#ifdef DEBUG
++#define LTQ_I2C_XFER_TIMEOUT (25*HZ)
++#else
++#define LTQ_I2C_XFER_TIMEOUT HZ
++#endif
++
++#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \
++ I2C_IMSC_I2C_ERR_INT_EN)
++
++#define LTQ_I2C_ARB_LOST (1 << 0)
++#define LTQ_I2C_NACK (1 << 1)
++#define LTQ_I2C_RX_UFL (1 << 2)
++#define LTQ_I2C_RX_OFL (1 << 3)
++#define LTQ_I2C_TX_UFL (1 << 4)
++#define LTQ_I2C_TX_OFL (1 << 5)
++
++struct ltq_i2c {
++ struct mutex mutex;
++
++
++ /* active clock settings */
++ unsigned int input_clock; /* clock input for i2c hardware block */
++ unsigned int i2c_clock; /* approximated bus clock in kHz */
++
++ struct clk *clk_gate;
++ struct clk *clk_input;
++
++
++ /* resources (memory and interrupts) */
++ int irq_lb; /* last burst irq */
++
++ struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */
++
++ struct i2c_adapter adap;
++ struct device *dev;
++
++ struct completion cmd_complete;
++
++
++ /* message transfer data */
++ struct i2c_msg *current_msg; /* current message */
++ int msgs_num; /* number of messages to handle */
++ u8 *msg_buf; /* current buffer */
++ u32 msg_buf_len; /* remaining length of current buffer */
++ int msg_err; /* error status of the current transfer */
++
++
++ /* master status codes */
++ enum {
++ STATUS_IDLE,
++ STATUS_ADDR, /* address phase */
++ STATUS_WRITE,
++ STATUS_READ,
++ STATUS_READ_END,
++ STATUS_STOP
++ } status;
++};
++
++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id);
++
++static inline void enable_burst_irq(struct ltq_i2c *priv)
++{
++ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
++}
++static inline void disable_burst_irq(struct ltq_i2c *priv)
++{
++ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
++}
++
++static void prepare_msg_send_addr(struct ltq_i2c *priv)
++{
++ struct i2c_msg *msg = priv->current_msg;
++ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */
++ u16 addr = msg->addr;
++
++ /* new i2c_msg */
++ priv->msg_buf = msg->buf;
++ priv->msg_buf_len = msg->len;
++ if (rd)
++ priv->status = STATUS_READ;
++ else
++ priv->status = STATUS_WRITE;
++
++ /* send slave address */
++ if (msg->flags & I2C_M_TEN) {
++ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd);
++ i2c_w32(addr & 0xff, txd);
++ } else {
++ i2c_w32((addr & 0x7f) << 1 | rd, txd);
++ }
++}
++
++static void ltq_i2c_set_tx_len(struct ltq_i2c *priv)
++{
++ struct i2c_msg *msg = priv->current_msg;
++ int len = (msg->flags & I2C_M_TEN) ? 2 : 1;
++
++ pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T');
++
++ priv->status = STATUS_ADDR;
++
++ if (!(msg->flags & I2C_M_RD))
++ len += msg->len;
++ else
++ /* set maximum received packet size (before rx int!) */
++ i2c_w32(msg->len, mrps_ctrl);
++ i2c_w32(len, tps_ctrl);
++ enable_burst_irq(priv);
++}
++
++static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap)
++{
++ struct ltq_i2c *priv = i2c_get_adapdata(adap);
++ unsigned int input_clock = clk_get_rate(priv->clk_input);
++ u32 dec, inc = 1;
++
++ /* clock changed? */
++ if (priv->input_clock == input_clock)
++ return 0;
++
++ /*
++ * this formula is only an approximation, found by the recommended
++ * values in the "I2C Architecture Specification 1.7.1"
++ */
++ dec = input_clock / (priv->i2c_clock * 2);
++ if (dec <= 6)
++ return -ENXIO;
++
++ i2c_w32(0, fdiv_high_cfg);
++ i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) |
++ (dec << I2C_FDIV_CFG_DEC_OFFSET),
++ fdiv_cfg);
++
++ dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n",
++ input_clock, priv->i2c_clock, dec);
++
++ priv->input_clock = input_clock;
++ return 0;
++}
++
++static int ltq_i2c_hw_init(struct i2c_adapter *adap)
++{
++ int ret = 0;
++ struct ltq_i2c *priv = i2c_get_adapdata(adap);
++
++ /* disable bus */
++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
++
++#ifndef DEBUG
++ /* set normal operation clock divider */
++ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
++#else
++ /* for debugging a higher divider value! */
++ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc);
++#endif
++
++ /* setup clock */
++ ret = ltq_i2c_hw_set_clock(adap);
++ if (ret != 0) {
++ dev_warn(priv->dev, "invalid clock settings\n");
++ return ret;
++ }
++
++ /* configure fifo */
++ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */
++ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */
++ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */
++ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */
++ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */
++ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */
++ fifo_cfg);
++
++ /* configure address */
++ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in
++ the fifo */
++ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */
++ I2C_ADDR_CFG_MnS_EN | /* we are master device */
++ 0, /* our slave address (not used!) */
++ addr_cfg);
++
++ /* enable bus */
++ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
++
++ return 0;
++}
++
++static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv)
++{
++ unsigned long timeout;
++
++ timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT);
++
++ do {
++ u32 stat = i2c_r32(bus_stat);
++
++ if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE)
++ return 0;
++
++ cond_resched();
++ } while (!time_after_eq(jiffies, timeout));
++
++ dev_err(priv->dev, "timeout waiting for bus ready\n");
++ return -ETIMEDOUT;
++}
++
++static void ltq_i2c_tx(struct ltq_i2c *priv, int last)
++{
++ if (priv->msg_buf_len && priv->msg_buf) {
++ i2c_w32(*priv->msg_buf, txd);
++
++ if (--priv->msg_buf_len)
++ priv->msg_buf++;
++ else
++ priv->msg_buf = NULL;
++ } else {
++ last = 1;
++ }
++
++ if (last)
++ disable_burst_irq(priv);
++}
++
++static void ltq_i2c_rx(struct ltq_i2c *priv, int last)
++{
++ u32 fifo_stat, timeout;
++ if (priv->msg_buf_len && priv->msg_buf) {
++ timeout = 5000000;
++ do {
++ fifo_stat = i2c_r32(ffs_stat);
++ } while (!fifo_stat && --timeout);
++ if (!timeout) {
++ last = 1;
++ pr_debug("\nrx timeout\n");
++ goto err;
++ }
++ while (fifo_stat) {
++ *priv->msg_buf = i2c_r32(rxd);
++ if (--priv->msg_buf_len) {
++ priv->msg_buf++;
++ } else {
++ priv->msg_buf = NULL;
++ last = 1;
++ break;
++ }
++ /*
++ * do not read more than burst size, otherwise no "last
++ * burst" is generated and the transaction is blocked!
++ */
++ fifo_stat = 0;
++ }
++ } else {
++ last = 1;
++ }
++err:
++ if (last) {
++ disable_burst_irq(priv);
++
++ if (priv->status == STATUS_READ_END) {
++ /*
++ * do the STATUS_STOP and complete() here, as sometimes
++ * the tx_end is already seen before this is finished
++ */
++ priv->status = STATUS_STOP;
++ complete(&priv->cmd_complete);
++ } else {
++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
++ priv->status = STATUS_READ_END;
++ }
++ }
++}
++
++static void ltq_i2c_xfer_init(struct ltq_i2c *priv)
++{
++ /* enable interrupts */
++ i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc);
++
++ /* trigger transfer of first msg */
++ ltq_i2c_set_tx_len(priv);
++}
++
++static void dump_msgs(struct i2c_msg msgs[], int num, int rx)
++{
++#if defined(DEBUG)
++ int i, j;
++ pr_debug("Messages %d %s\n", num, rx ? "out" : "in");
++ for (i = 0; i < num; i++) {
++ pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i,
++ (msgs[i].flags & I2C_M_RD) ? 'R' : 'T',
++ msgs[i].len, msgs[i].addr);
++ if (!(msgs[i].flags & I2C_M_RD) || rx) {
++ for (j = 0; j < msgs[i].len; j++)
++ pr_debug("%02X ", msgs[i].buf[j]);
++ }
++ pr_debug("\n");
++ }
++#endif
++}
++
++static void ltq_i2c_release_bus(struct ltq_i2c *priv)
++{
++ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM)
++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
++}
++
++static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
++ int num)
++{
++ struct ltq_i2c *priv = i2c_get_adapdata(adap);
++ int ret;
++
++ dev_dbg(priv->dev, "xfer %u messages\n", num);
++ dump_msgs(msgs, num, 0);
++
++ mutex_lock(&priv->mutex);
++
++ init_completion(&priv->cmd_complete);
++ priv->current_msg = msgs;
++ priv->msgs_num = num;
++ priv->msg_err = 0;
++ priv->status = STATUS_IDLE;
++
++ /* wait for the bus to become ready */
++ ret = ltq_i2c_wait_bus_not_busy(priv);
++ if (ret)
++ goto done;
++
++ while (priv->msgs_num) {
++ /* start the transfers */
++ ltq_i2c_xfer_init(priv);
++
++ /* wait for transfers to complete */
++ ret = wait_for_completion_interruptible_timeout(
++ &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT);
++ if (ret == 0) {
++ dev_err(priv->dev, "controller timed out\n");
++ ltq_i2c_hw_init(adap);
++ ret = -ETIMEDOUT;
++ goto done;
++ } else if (ret < 0)
++ goto done;
++
++ if (priv->msg_err) {
++ if (priv->msg_err & LTQ_I2C_NACK)
++ ret = -ENXIO;
++ else
++ ret = -EREMOTEIO;
++ goto done;
++ }
++ if (--priv->msgs_num)
++ priv->current_msg++;
++ }
++ /* no error? */
++ ret = num;
++
++done:
++ ltq_i2c_release_bus(priv);
++
++ mutex_unlock(&priv->mutex);
++
++ if (ret >= 0)
++ dump_msgs(msgs, num, 1);
++
++ pr_debug("XFER ret %d\n", ret);
++ return ret;
++}
++
++static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id)
++{
++ struct ltq_i2c *priv = dev_id;
++ struct i2c_msg *msg = priv->current_msg;
++ int last = (irq == priv->irq_lb);
++
++ if (last)
++ pr_debug("LB ");
++ else
++ pr_debug("B ");
++
++ if (msg->flags & I2C_M_RD) {
++ switch (priv->status) {
++ case STATUS_ADDR:
++ pr_debug("X");
++ prepare_msg_send_addr(priv);
++ disable_burst_irq(priv);
++ break;
++ case STATUS_READ:
++ case STATUS_READ_END:
++ pr_debug("R");
++ ltq_i2c_rx(priv, last);
++ break;
++ default:
++ disable_burst_irq(priv);
++ pr_warn("Status R %d\n", priv->status);
++ break;
++ }
++ } else {
++ switch (priv->status) {
++ case STATUS_ADDR:
++ pr_debug("x");
++ prepare_msg_send_addr(priv);
++ break;
++ case STATUS_WRITE:
++ pr_debug("w");
++ ltq_i2c_tx(priv, last);
++ break;
++ default:
++ disable_burst_irq(priv);
++ pr_warn("Status W %d\n", priv->status);
++ break;
++ }
++ }
++
++ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr);
++ return IRQ_HANDLED;
++}
++
++static void ltq_i2c_isr_prot(struct ltq_i2c *priv)
++{
++ u32 i_pro = i2c_r32(p_irqss);
++
++ pr_debug("i2c-p");
++
++ /* not acknowledge */
++ if (i_pro & I2C_P_IRQSS_NACK) {
++ priv->msg_err |= LTQ_I2C_NACK;
++ pr_debug(" nack");
++ }
++
++ /* arbitration lost */
++ if (i_pro & I2C_P_IRQSS_AL) {
++ priv->msg_err |= LTQ_I2C_ARB_LOST;
++ pr_debug(" arb-lost");
++ }
++ /* tx -> rx switch */
++ if (i_pro & I2C_P_IRQSS_RX)
++ pr_debug(" rx");
++
++ /* tx end */
++ if (i_pro & I2C_P_IRQSS_TX_END)
++ pr_debug(" txend");
++ pr_debug("\n");
++
++ if (!priv->msg_err) {
++ /* tx -> rx switch */
++ if (i_pro & I2C_P_IRQSS_RX) {
++ priv->status = STATUS_READ;
++ enable_burst_irq(priv);
++ }
++ if (i_pro & I2C_P_IRQSS_TX_END) {
++ if (priv->status == STATUS_READ)
++ priv->status = STATUS_READ_END;
++ else {
++ disable_burst_irq(priv);
++ priv->status = STATUS_STOP;
++ }
++ }
++ }
++
++ i2c_w32(i_pro, p_irqsc);
++}
++
++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id)
++{
++ u32 i_raw, i_err = 0;
++ struct ltq_i2c *priv = dev_id;
++
++ i_raw = i2c_r32(mis);
++ pr_debug("i_raw 0x%08X\n", i_raw);
++
++ /* error interrupt */
++ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
++ i_err = i2c_r32(err_irqss);
++ pr_debug("i_err 0x%08X bus_stat 0x%04X\n",
++ i_err, i2c_r32(bus_stat));
++
++ /* tx fifo overflow (8) */
++ if (i_err & I2C_ERR_IRQSS_TXF_OFL)
++ priv->msg_err |= LTQ_I2C_TX_OFL;
++
++ /* tx fifo underflow (4) */
++ if (i_err & I2C_ERR_IRQSS_TXF_UFL)
++ priv->msg_err |= LTQ_I2C_TX_UFL;
++
++ /* rx fifo overflow (2) */
++ if (i_err & I2C_ERR_IRQSS_RXF_OFL)
++ priv->msg_err |= LTQ_I2C_RX_OFL;
++
++ /* rx fifo underflow (1) */
++ if (i_err & I2C_ERR_IRQSS_RXF_UFL)
++ priv->msg_err |= LTQ_I2C_RX_UFL;
++
++ i2c_w32(i_err, err_irqsc);
++ }
++
++ /* protocol interrupt */
++ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC)
++ ltq_i2c_isr_prot(priv);
++
++ if ((priv->msg_err) || (priv->status == STATUS_STOP))
++ complete(&priv->cmd_complete);
++
++ return IRQ_HANDLED;
++}
++
++static u32 ltq_i2c_functionality(struct i2c_adapter *adap)
++{
++ return I2C_FUNC_I2C |
++ I2C_FUNC_10BIT_ADDR |
++ I2C_FUNC_SMBUS_EMUL;
++}
++
++static struct i2c_algorithm ltq_i2c_algorithm = {
++ .master_xfer = ltq_i2c_xfer,
++ .functionality = ltq_i2c_functionality,
++};
++
++static int ltq_i2c_probe(struct platform_device *pdev)
++{
++ struct device_node *node = pdev->dev.of_node;
++ struct ltq_i2c *priv;
++ struct i2c_adapter *adap;
++ struct resource *mmres, irqres[4];
++ int ret = 0;
++
++ dev_dbg(&pdev->dev, "probing\n");
++
++ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ ret = of_irq_to_resource_table(node, irqres, 4);
++ if (!mmres || (ret != 4)) {
++ dev_err(&pdev->dev, "no resources\n");
++ return -ENODEV;
++ }
++
++ /* allocate private data */
++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv) {
++ dev_err(&pdev->dev, "can't allocate private data\n");
++ return -ENOMEM;
++ }
++
++ adap = &priv->adap;
++ i2c_set_adapdata(adap, priv);
++ adap->owner = THIS_MODULE;
++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
++ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
++ adap->algo = <q_i2c_algorithm;
++ adap->dev.parent = &pdev->dev;
++ adap->dev.of_node = pdev->dev.of_node;
++
++ if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) {
++ dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n");
++ priv->i2c_clock = 100000;
++ }
++
++ init_completion(&priv->cmd_complete);
++ mutex_init(&priv->mutex);
++
++ priv->membase = devm_ioremap_resource(&pdev->dev, mmres);
++ if (IS_ERR(priv->membase))
++ return PTR_ERR(priv->membase);
++
++ priv->dev = &pdev->dev;
++ priv->irq_lb = irqres[0].start;
++
++ ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst,
++ 0x0, "i2c lb", priv);
++ if (ret) {
++ dev_err(&pdev->dev, "can't get last burst IRQ %d\n",
++ irqres[0].start);
++ return -ENODEV;
++ }
++
++ ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst,
++ 0x0, "i2c b", priv);
++ if (ret) {
++ dev_err(&pdev->dev, "can't get burst IRQ %d\n",
++ irqres[1].start);
++ return -ENODEV;
++ }
++
++ ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr,
++ 0x0, "i2c err", priv);
++ if (ret) {
++ dev_err(&pdev->dev, "can't get error IRQ %d\n",
++ irqres[2].start);
++ return -ENODEV;
++ }
++
++ ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr,
++ 0x0, "i2c p", priv);
++ if (ret) {
++ dev_err(&pdev->dev, "can't get protocol IRQ %d\n",
++ irqres[3].start);
++ return -ENODEV;
++ }
++
++ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
++ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start,
++ irqres[1].start, irqres[2].start, irqres[3].start);
++
++ priv->clk_gate = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(priv->clk_gate)) {
++ dev_err(&pdev->dev, "failed to get i2c clk\n");
++ return -ENOENT;
++ }
++
++ /* this is a static clock, which has no refcounting */
++ priv->clk_input = clk_get_fpi();
++ if (IS_ERR(priv->clk_input)) {
++ dev_err(&pdev->dev, "failed to get fpi clk\n");
++ return -ENOENT;
++ }
++
++ clk_activate(priv->clk_gate);
++
++ /* add our adapter to the i2c stack */
++ ret = i2c_add_numbered_adapter(adap);
++ if (ret) {
++ dev_err(&pdev->dev, "can't register I2C adapter\n");
++ goto out;
++ }
++
++ platform_set_drvdata(pdev, priv);
++ i2c_set_adapdata(adap, priv);
++
++ /* print module version information */
++ dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
++ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
++ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
++
++ /* initialize HW */
++ ret = ltq_i2c_hw_init(adap);
++ if (ret) {
++ dev_err(&pdev->dev, "can't configure adapter\n");
++ i2c_del_adapter(adap);
++ platform_set_drvdata(pdev, NULL);
++ goto out;
++ } else {
++ dev_info(&pdev->dev, "version %s\n", DRV_VERSION);
++ }
++
++out:
++ /* if init failed, we need to deactivate the clock gate */
++ if (ret)
++ clk_deactivate(priv->clk_gate);
++
++ return ret;
++}
++
++static int ltq_i2c_remove(struct platform_device *pdev)
++{
++ struct ltq_i2c *priv = platform_get_drvdata(pdev);
++
++ /* disable bus */
++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
++
++ /* power down the core */
++ clk_deactivate(priv->clk_gate);
++
++ /* remove driver */
++ i2c_del_adapter(&priv->adap);
++ kfree(priv);
++
++ dev_dbg(&pdev->dev, "removed\n");
++ platform_set_drvdata(pdev, NULL);
++
++ return 0;
++}
++static const struct of_device_id ltq_i2c_match[] = {
++ { .compatible = "lantiq,lantiq-i2c" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, ltq_i2c_match);
++
++static struct platform_driver ltq_i2c_driver = {
++ .probe = ltq_i2c_probe,
++ .remove = ltq_i2c_remove,
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = ltq_i2c_match,
++ },
++};
++
++module_platform_driver(ltq_i2c_driver);
++
++MODULE_DESCRIPTION("Lantiq I2C bus adapter");
++MODULE_AUTHOR("Thomas Langer <thomas.langer@lantiq.com>");
++MODULE_ALIAS("platform:" DRV_NAME);
++MODULE_LICENSE("GPL");
++MODULE_VERSION(DRV_VERSION);
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-lantiq.h
+@@ -0,0 +1,234 @@
++#ifndef I2C_LANTIQ_H
++#define I2C_LANTIQ_H
++
++/* I2C register structure */
++struct lantiq_reg_i2c {
++ /* I2C Kernel Clock Control Register */
++ unsigned int clc; /* 0x00000000 */
++ /* Reserved */
++ unsigned int res_0; /* 0x00000004 */
++ /* I2C Identification Register */
++ unsigned int id; /* 0x00000008 */
++ /* Reserved */
++ unsigned int res_1; /* 0x0000000C */
++ /*
++ * I2C RUN Control Register
++ * This register enables and disables the I2C peripheral. Before
++ * enabling, the I2C has to be configured properly. After enabling
++ * no configuration is possible
++ */
++ unsigned int run_ctrl; /* 0x00000010 */
++ /*
++ * I2C End Data Control Register
++ * This register is used to either turn around the data transmission
++ * direction or to address another slave without sending a stop
++ * condition. Also the software can stop the slave-transmitter by
++ * sending a not-accolade when working as master-receiver or even
++ * stop data transmission immediately when operating as
++ * master-transmitter. The writing to the bits of this control
++ * register is only effective when in MASTER RECEIVES BYTES, MASTER
++ * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state
++ */
++ unsigned int endd_ctrl; /* 0x00000014 */
++ /*
++ * I2C Fractional Divider Configuration Register
++ * These register is used to program the fractional divider of the I2C
++ * bus. Before the peripheral is switched on by setting the RUN-bit the
++ * two (fixed) values for the two operating frequencies are programmed
++ * into these (configuration) registers. The Register FDIV_HIGH_CFG has
++ * the same layout as I2C_FDIV_CFG.
++ */
++ unsigned int fdiv_cfg; /* 0x00000018 */
++ /*
++ * I2C Fractional Divider (highspeed mode) Configuration Register
++ * These register is used to program the fractional divider of the I2C
++ * bus. Before the peripheral is switched on by setting the RUN-bit the
++ * two (fixed) values for the two operating frequencies are programmed
++ * into these (configuration) registers. The Register FDIV_CFG has the
++ * same layout as I2C_FDIV_CFG.
++ */
++ unsigned int fdiv_high_cfg; /* 0x0000001C */
++ /* I2C Address Configuration Register */
++ unsigned int addr_cfg; /* 0x00000020 */
++ /* I2C Bus Status Register
++ * This register gives a status information of the I2C. This additional
++ * information can be used by the software to start proper actions.
++ */
++ unsigned int bus_stat; /* 0x00000024 */
++ /* I2C FIFO Configuration Register */
++ unsigned int fifo_cfg; /* 0x00000028 */
++ /* I2C Maximum Received Packet Size Register */
++ unsigned int mrps_ctrl; /* 0x0000002C */
++ /* I2C Received Packet Size Status Register */
++ unsigned int rps_stat; /* 0x00000030 */
++ /* I2C Transmit Packet Size Register */
++ unsigned int tps_ctrl; /* 0x00000034 */
++ /* I2C Filled FIFO Stages Status Register */
++ unsigned int ffs_stat; /* 0x00000038 */
++ /* Reserved */
++ unsigned int res_2; /* 0x0000003C */
++ /* I2C Timing Configuration Register */
++ unsigned int tim_cfg; /* 0x00000040 */
++ /* Reserved */
++ unsigned int res_3[7]; /* 0x00000044 */
++ /* I2C Error Interrupt Request Source Mask Register */
++ unsigned int err_irqsm; /* 0x00000060 */
++ /* I2C Error Interrupt Request Source Status Register */
++ unsigned int err_irqss; /* 0x00000064 */
++ /* I2C Error Interrupt Request Source Clear Register */
++ unsigned int err_irqsc; /* 0x00000068 */
++ /* Reserved */
++ unsigned int res_4; /* 0x0000006C */
++ /* I2C Protocol Interrupt Request Source Mask Register */
++ unsigned int p_irqsm; /* 0x00000070 */
++ /* I2C Protocol Interrupt Request Source Status Register */
++ unsigned int p_irqss; /* 0x00000074 */
++ /* I2C Protocol Interrupt Request Source Clear Register */
++ unsigned int p_irqsc; /* 0x00000078 */
++ /* Reserved */
++ unsigned int res_5; /* 0x0000007C */
++ /* I2C Raw Interrupt Status Register */
++ unsigned int ris; /* 0x00000080 */
++ /* I2C Interrupt Mask Control Register */
++ unsigned int imsc; /* 0x00000084 */
++ /* I2C Masked Interrupt Status Register */
++ unsigned int mis; /* 0x00000088 */
++ /* I2C Interrupt Clear Register */
++ unsigned int icr; /* 0x0000008C */
++ /* I2C Interrupt Set Register */
++ unsigned int isr; /* 0x00000090 */
++ /* I2C DMA Enable Register */
++ unsigned int dmae; /* 0x00000094 */
++ /* Reserved */
++ unsigned int res_6[8154]; /* 0x00000098 */
++ /* I2C Transmit Data Register */
++ unsigned int txd; /* 0x00008000 */
++ /* Reserved */
++ unsigned int res_7[4095]; /* 0x00008004 */
++ /* I2C Receive Data Register */
++ unsigned int rxd; /* 0x0000C000 */
++ /* Reserved */
++ unsigned int res_8[4095]; /* 0x0000C004 */
++};
++
++/*
++ * Clock Divider for Normal Run Mode
++ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long
++ * as the new divider value RMC is not valid, the register returns 0x0000 00xx
++ * on reading.
++ */
++#define I2C_CLC_RMC_MASK 0x0000FF00
++/* field offset */
++#define I2C_CLC_RMC_OFFSET 8
++
++/* Fields of "I2C Identification Register" */
++/* Module ID */
++#define I2C_ID_ID_MASK 0x0000FF00
++/* field offset */
++#define I2C_ID_ID_OFFSET 8
++/* Revision */
++#define I2C_ID_REV_MASK 0x000000FF
++/* field offset */
++#define I2C_ID_REV_OFFSET 0
++
++/* Fields of "I2C Interrupt Mask Control Register" */
++/* Enable */
++#define I2C_IMSC_BREQ_INT_EN 0x00000008
++/* Enable */
++#define I2C_IMSC_LBREQ_INT_EN 0x00000004
++
++/* Fields of "I2C Fractional Divider Configuration Register" */
++/* field offset */
++#define I2C_FDIV_CFG_INC_OFFSET 16
++
++/* Fields of "I2C Interrupt Mask Control Register" */
++/* Enable */
++#define I2C_IMSC_I2C_P_INT_EN 0x00000020
++/* Enable */
++#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
++
++/* Fields of "I2C Error Interrupt Request Source Status Register" */
++/* TXF_OFL */
++#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
++/* TXF_UFL */
++#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
++/* RXF_OFL */
++#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
++/* RXF_UFL */
++#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
++
++/* Fields of "I2C Raw Interrupt Status Register" */
++/* Read: Interrupt occurred. */
++#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
++/* Read: Interrupt occurred. */
++#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
++
++/* Fields of "I2C FIFO Configuration Register" */
++/* TX FIFO Flow Control */
++#define I2C_FIFO_CFG_TXFC 0x00020000
++/* RX FIFO Flow Control */
++#define I2C_FIFO_CFG_RXFC 0x00010000
++/* Word aligned (character alignment of four characters) */
++#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
++/* Word aligned (character alignment of four characters) */
++#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
++/* 1 word */
++#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
++
++/* Fields of "I2C FIFO Configuration Register" */
++/* 1 word */
++#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
++/* Stop on Packet End Enable */
++#define I2C_ADDR_CFG_SOPE_EN 0x00200000
++/* Stop on Not Acknowledge Enable */
++#define I2C_ADDR_CFG_SONA_EN 0x00100000
++/* Enable */
++#define I2C_ADDR_CFG_MnS_EN 0x00080000
++
++/* Fields of "I2C Interrupt Clear Register" */
++/* Clear */
++#define I2C_ICR_BREQ_INT_CLR 0x00000008
++/* Clear */
++#define I2C_ICR_LBREQ_INT_CLR 0x00000004
++
++/* Fields of "I2C Fractional Divider Configuration Register" */
++/* field offset */
++#define I2C_FDIV_CFG_DEC_OFFSET 0
++
++/* Fields of "I2C Bus Status Register" */
++/* Bus Status */
++#define I2C_BUS_STAT_BS_MASK 0x00000003
++/* Read from I2C Bus. */
++#define I2C_BUS_STAT_RNW_READ 0x00000004
++/* I2C Bus is free. */
++#define I2C_BUS_STAT_BS_FREE 0x00000000
++/*
++ * The device is working as master and has claimed the control on the
++ * I2C-bus (busy master).
++ */
++#define I2C_BUS_STAT_BS_BM 0x00000002
++
++/* Fields of "I2C RUN Control Register" */
++/* Enable */
++#define I2C_RUN_CTRL_RUN_EN 0x00000001
++
++/* Fields of "I2C End Data Control Register" */
++/*
++ * Set End of Transmission
++ * Note:Do not write '1' to this bit when bus is free. This will cause an
++ * abort after the first byte when a new transfer is started.
++ */
++#define I2C_ENDD_CTRL_SETEND 0x00000002
++
++/* Fields of "I2C Protocol Interrupt Request Source Status Register" */
++/* NACK */
++#define I2C_P_IRQSS_NACK 0x00000010
++/* AL */
++#define I2C_P_IRQSS_AL 0x00000008
++/* RX */
++#define I2C_P_IRQSS_RX 0x00000040
++/* TX_END */
++#define I2C_P_IRQSS_TX_END 0x00000020
++
++
++#endif /* I2C_LANTIQ_H */
--- /dev/null
+From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 10 Sep 2014 22:42:14 +0200
+Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +
+ arch/mips/lantiq/xway/Makefile | 3 +
+ arch/mips/lantiq/xway/ath5k_eep.c | 136 +++++++++++++++++++++
+ arch/mips/lantiq/xway/eth_mac.c | 25 ++++
+ drivers/net/ethernet/lantiq_etop.c | 6 +-
+ 5 files changed, 172 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c
+ create mode 100644 arch/mips/lantiq/xway/eth_mac.c
+
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -102,5 +102,8 @@ int xrx200_gphy_boot(struct device *dev,
+ extern void ltq_pmu_enable(unsigned int module);
+ extern void ltq_pmu_disable(unsigned int module);
+
++/* allow the ethernet driver to load a flash mapped mac addr */
++const u8* ltq_get_eth_mac(void);
++
+ #endif /* CONFIG_SOC_TYPE_XWAY */
+ #endif /* _LTQ_XWAY_H__ */
+--- a/arch/mips/lantiq/xway/Makefile
++++ b/arch/mips/lantiq/xway/Makefile
+@@ -8,3 +8,6 @@ obj-y += timer.o
+ endif
+
+ obj-y += vmmc.o
++
++obj-y += eth_mac.o
++obj-$(CONFIG_PCI) += ath5k_eep.o
+--- /dev/null
++++ b/arch/mips/lantiq/xway/ath5k_eep.c
+@@ -0,0 +1,136 @@
++/*
++ * Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>
++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ * Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>
++ * Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>
++ * Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
++ * Copyright (C) 2015 Vittorio Gambaletta <openwrt@vittgam.net>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/etherdevice.h>
++#include <linux/ath5k_platform.h>
++#include <linux/pci.h>
++#include <linux/err.h>
++#include <linux/mtd/mtd.h>
++#include <lantiq_soc.h>
++
++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);
++struct ath5k_platform_data ath5k_pdata;
++static u8 athxk_eeprom_mac[6];
++
++static int ath5k_pci_plat_dev_init(struct pci_dev *dev)
++{
++ dev->dev.platform_data = &ath5k_pdata;
++ return 0;
++}
++
++static int ath5k_eep_load;
++int __init of_ath5k_eeprom_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node, *mtd_np = NULL;
++ int mac_offset;
++ u32 mac_inc = 0;
++ int i;
++ struct mtd_info *the_mtd;
++ size_t flash_readlen;
++ const __be32 *list;
++ const char *part;
++ phandle phandle;
++
++ list = of_get_property(np, "ath,eep-flash", &i);
++ if (!list || (i != (2 * sizeof(*list))))
++ return -ENODEV;
++
++ phandle = be32_to_cpup(list++);
++ if (phandle)
++ mtd_np = of_find_node_by_phandle(phandle);
++
++ if (!mtd_np)
++ return -ENODEV;
++
++ part = of_get_property(mtd_np, "label", NULL);
++ if (!part)
++ part = mtd_np->name;
++
++ the_mtd = get_mtd_device_nm(part);
++ if (IS_ERR(the_mtd))
++ return -ENODEV;
++
++ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL);
++
++ i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1,
++ &flash_readlen, (void *) ath5k_pdata.eeprom_data);
++
++ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) {
++ size_t mac_readlen;
++ mtd_read(the_mtd, mac_offset, 6, &mac_readlen,
++ (void *) athxk_eeprom_mac);
++ }
++ put_mtd_device(the_mtd);
++
++ if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) {
++ dev_err(&pdev->dev, "failed to load eeprom from mtd\n");
++ return -ENODEV;
++ }
++
++ if (of_find_property(np, "ath,eep-swap", NULL))
++ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)
++ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]);
++
++ if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac())
++ ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac());
++
++ if (!is_valid_ether_addr(athxk_eeprom_mac)) {
++ dev_warn(&pdev->dev, "using random mac\n");
++ eth_random_addr(athxk_eeprom_mac);
++ }
++
++ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc))
++ athxk_eeprom_mac[5] += mac_inc;
++
++ ath5k_pdata.macaddr = athxk_eeprom_mac;
++ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;
++
++ dev_info(&pdev->dev, "loaded ath5k eeprom\n");
++
++ return 0;
++}
++
++static struct of_device_id ath5k_eeprom_ids[] = {
++ { .compatible = "ath5k,eeprom" },
++ { }
++};
++
++static struct platform_driver ath5k_eeprom_driver = {
++ .driver = {
++ .name = "ath5k,eeprom",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(ath5k_eeprom_ids),
++ },
++};
++
++static int __init of_ath5k_eeprom_init(void)
++{
++ int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
++
++ if (ret)
++ ath5k_eep_load = 1;
++
++ return ret;
++}
++
++static int __init of_ath5k_eeprom_init_late(void)
++{
++ if (!ath5k_eep_load)
++ return 0;
++
++ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);
++}
++late_initcall(of_ath5k_eeprom_init_late);
++subsys_initcall(of_ath5k_eeprom_init);
+--- /dev/null
++++ b/arch/mips/lantiq/xway/eth_mac.c
+@@ -0,0 +1,25 @@
++/*
++ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/if_ether.h>
++
++static u8 eth_mac[6];
++static int eth_mac_set;
++
++const u8* ltq_get_eth_mac(void)
++{
++ return eth_mac;
++}
++
++static int __init setup_ethaddr(char *str)
++{
++ eth_mac_set = mac_pton(str, eth_mac);
++ return !eth_mac_set;
++}
++early_param("ethaddr", setup_ethaddr);
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -763,7 +763,11 @@ ltq_etop_init(struct net_device *dev)
+ if (err)
+ goto err_hw;
+
+- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
++ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN);
++
++ if (!is_valid_ether_addr(mac.sa_data))
++ memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
++
+ if (!is_valid_ether_addr(mac.sa_data)) {
+ pr_warn("etop: invalid MAC, using random\n");
+ eth_random_addr(mac.sa_data);
--- /dev/null
+From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Fri, 3 Jun 2016 13:12:20 +0200
+Subject: [PATCH] arch: mips: increase io_space_limit
+
+this value comes from x86 and breaks some pci devices
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/mips/include/asm/mach-lantiq/spaces.h | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/spaces.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/spaces.h
+@@ -0,0 +1,8 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef __ASM_MACH_LANTIQ_SPACES_H_
++#define __ASM_MACH_LANTIQ_SPACES_H_
++
++#define IO_SPACE_LIMIT 0xffffffff
++
++#include <asm/mach-generic/spaces.h>
++#endif
--- /dev/null
+From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Fri, 6 Jan 2017 17:55:24 +0100
+Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs
+
+The size of the internal RAM of the DesignWare USB controller changed
+between the different Lantiq SoCs. We have the following sizes:
+
+Amazon + Danube: 8 KByte
+Amazon SE + arx100: 2 KByte
+xrx200 + xrx300: 2.5 KByte
+
+For Danube SoC we do not provide the params and let the driver decide
+to use sane defaults, for the Amazon SE and arx100 we use small fifos
+and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo.
+The auto detection of max_transfer_size and max_packet_count should
+work, so remove it.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++-------
+ 1 file changed, 39 insertions(+), 7 deletions(-)
+
+--- a/drivers/usb/dwc2/params.c
++++ b/drivers/usb/dwc2/params.c
+@@ -115,7 +115,15 @@ static void dwc2_set_rk_params(struct dw
+ p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+ }
+
+-static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
++static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg)
++{
++ struct dwc2_core_params *p = &hsotg->params;
++
++ p->otg_caps.hnp_support = false;
++ p->otg_caps.srp_support = false;
++}
++
++static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg)
+ {
+ struct dwc2_core_params *p = &hsotg->params;
+
+@@ -124,12 +132,21 @@ static void dwc2_set_ltq_params(struct d
+ p->host_rx_fifo_size = 288;
+ p->host_nperio_tx_fifo_size = 128;
+ p->host_perio_tx_fifo_size = 96;
+- p->max_transfer_size = 65535;
+- p->max_packet_count = 511;
+ p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
+ GAHBCFG_HBSTLEN_SHIFT;
+ }
+
++static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg)
++{
++ struct dwc2_core_params *p = &hsotg->params;
++
++ p->otg_caps.hnp_support = false;
++ p->otg_caps.srp_support = false;
++ p->host_rx_fifo_size = 288;
++ p->host_nperio_tx_fifo_size = 128;
++ p->host_perio_tx_fifo_size = 136;
++}
++
+ static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
+ {
+ struct dwc2_core_params *p = &hsotg->params;
+@@ -241,8 +258,11 @@ const struct of_device_id dwc2_of_match_
+ { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
+ { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
+ { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
+- { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
+- { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
++ { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params },
++ { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params },
++ { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params },
++ { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params },
++ { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params },
+ { .compatible = "snps,dwc2" },
+ { .compatible = "samsung,s3c6400-hsotg",
+ .data = dwc2_set_s3c6400_params },
--- /dev/null
+From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Fri, 6 Jan 2017 17:40:12 +0100
+Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
+
+This adds code to initialize the USB controller and PHY also on Danube,
+Amazon SE and AR10. This code is based on the Vendor driver from
+different UGW versions and compared to the hardware documentation.
+
+Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
+---
+ arch/mips/lantiq/xway/sysctrl.c | 20 +++++++
+ 2 files changed, 110 insertions(+), 30 deletions(-)
+
+
+--- a/arch/mips/lantiq/xway/sysctrl.c
++++ b/arch/mips/lantiq/xway/sysctrl.c
+@@ -248,6 +248,25 @@ static void pmu_disable(struct clk *clk)
+ pr_warn("deactivating PMU module failed!");
+ }
+
++static void usb_set_clock(void)
++{
++ unsigned int val = ltq_cgu_r32(ifccr);
++
++ if (of_machine_is_compatible("lantiq,ar10") ||
++ of_machine_is_compatible("lantiq,grx390")) {
++ val &= ~0x03; /* XTAL divided by 3 */
++ } else if (of_machine_is_compatible("lantiq,ar9") ||
++ of_machine_is_compatible("lantiq,vr9")) {
++ /* TODO: this depends on the XTAL frequency */
++ val |= 0x03; /* XTAL divided by 3 */
++ } else if (of_machine_is_compatible("lantiq,ase")) {
++ val |= 0x20; /* from XTAL */
++ } else if (of_machine_is_compatible("lantiq,danube")) {
++ val |= 0x30; /* 12 MHz, generated from 36 MHz */
++ }
++ ltq_cgu_w32(val, ifccr);
++}
++
+ /* the pci enable helper */
+ static int pci_enable(struct clk *clk)
+ {
+@@ -589,4 +608,5 @@ void __init ltq_soc_init(void)
+ clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
+ clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
+ }
++ usb_set_clock();
+ }
--- /dev/null
+From 2c82524000cca691c89c9fda251b55ef04eabcb6 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <openwrt@kresin.me>
+Date: Mon, 2 May 2016 18:50:00 +0000
+Subject: [PATCH] find active root
+
+Signed-off-by: Mathias Kresin <openwrt@kresin.me>
+---
+ drivers/mtd/parsers/ofpart_core.c | 49 ++++++++++++++++++++++++++++++-
+ 1 file changed, 48 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/parsers/ofpart_core.c
++++ b/drivers/mtd/parsers/ofpart_core.c
+@@ -38,6 +38,38 @@ static bool node_has_compatible(struct d
+ return of_get_property(pp, "compatible", NULL);
+ }
+
++static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master,
++ loff_t offset)
++{
++ static uint8_t root_id;
++ int err, len;
++
++ err = mtd_read(master, offset, 0x01, &len, &root_id);
++
++ if (mtd_is_bitflip(err) || !err)
++ return &root_id;
++
++ return NULL;
++}
++
++static void brnboot_set_active_root_part(struct mtd_partition *pparts,
++ struct device_node **part_nodes,
++ int nr_parts,
++ uint8_t *root_id)
++{
++ int i;
++
++ for (i = 0; i < nr_parts; i++) {
++ int part_root_id;
++
++ if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id)
++ && part_root_id == *root_id) {
++ pparts[i].name = "firmware";
++ break;
++ }
++ }
++}
++
+ static int parse_fixed_partitions(struct mtd_info *master,
+ const struct mtd_partition **pparts,
+ struct mtd_part_parser_data *data)
+@@ -51,6 +83,8 @@ static int parse_fixed_partitions(struct
+ struct device_node *pp;
+ int nr_parts, i, ret = 0;
+ bool dedicated = true;
++ uint8_t *proot_id = NULL;
++ struct device_node **part_nodes;
+
+ /* Pull of_node from the master device node */
+ mtd_node = mtd_get_of_node(master);
+@@ -95,7 +129,9 @@ static int parse_fixed_partitions(struct
+ return 0;
+
+ parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
+- if (!parts)
++ part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL);
++
++ if (!parts || !part_nodes)
+ return -ENOMEM;
+
+ i = 0;
+@@ -166,6 +202,11 @@ static int parse_fixed_partitions(struct
+ if (of_property_read_bool(pp, "slc-mode"))
+ parts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION;
+
++ if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector"))
++ proot_id = brnboot_get_selected_root_part(master, parts[i].offset);
++
++ part_nodes[i] = pp;
++
+ i++;
+ }
+
+@@ -175,6 +216,11 @@ static int parse_fixed_partitions(struct
+ if (quirks && quirks->post_parse)
+ quirks->post_parse(master, parts, nr_parts);
+
++ if (proot_id)
++ brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id);
++
++ kfree(part_nodes);
++
+ *pparts = parts;
+ return nr_parts;
+
+@@ -185,6 +231,7 @@ ofpart_fail:
+ ofpart_none:
+ of_node_put(pp);
+ kfree(parts);
++ kfree(part_nodes);
+ return ret;
+ }
+
--- /dev/null
+From 1d1885f4a7abd7272f47b835b03d8662fb981d19 Mon Sep 17 00:00:00 2001
+From: Eddi De Pieri <eddi@depieri.net>
+Date: Tue, 14 Oct 2014 11:04:00 +0000
+Subject: [PATCH] MIPS: lantiq: ifxmips_pcie: use of
+
+Signed-off-by: Eddi De Pieri <eddi@depieri.net>
+---
+ arch/mips/pci/Makefile | 2 +-
+ arch/mips/pci/ifxmips_pcie.c | 151 +++++++++++++++++++++++++++----
+ arch/mips/pci/ifxmips_pcie_vr9.h | 105 ---------------------
+ 3 files changed, 133 insertions(+), 125 deletions(-)
+
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -41,7 +41,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o
+ obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
+ obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
+-obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o
++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie.o fixup-lantiq-pcie.o
+ obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o
+ obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
+ obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
+--- a/arch/mips/pci/ifxmips_pcie.c
++++ b/arch/mips/pci/ifxmips_pcie.c
+@@ -16,8 +16,15 @@
+ #include <asm/paccess.h>
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
++#include <linux/phy/phy.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+
++#include <linux/of_gpio.h>
++#include <linux/of_platform.h>
++
+ #include "ifxmips_pcie.h"
+ #include "ifxmips_pcie_reg.h"
+
+@@ -25,11 +32,6 @@
+ #define IFX_PCIE_ERROR_INT
+ #define IFX_PCIE_IO_32BIT
+
+-#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25)
+-#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8)
+-#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9)
+-#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10)
+-#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11)
+ #define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
+ #define SM(_v, _f) (((_v) << _f##_S) & (_f))
+ #define IFX_REG_SET_BIT(_f, _r) \
+@@ -40,30 +42,30 @@
+ static DEFINE_SPINLOCK(ifx_pcie_lock);
+
+ u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);
++static int pcie_reset_gpio;
++static struct phy *ltq_pcie_phy;
++static struct reset_control *ltq_pcie_reset;
++static struct regmap *ltq_rcu_regmap;
++static bool switch_pcie_endianess;
+
+ static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {
+ {
+ .ir_irq = {
+- .irq = IFX_PCIE_IR,
+ .name = "ifx_pcie_rc0",
+ },
+
+ .legacy_irq = {
+ {
+ .irq_bit = PCIE_IRN_INTA,
+- .irq = IFX_PCIE_INTA,
+ },
+ {
+ .irq_bit = PCIE_IRN_INTB,
+- .irq = IFX_PCIE_INTB,
+ },
+ {
+ .irq_bit = PCIE_IRN_INTC,
+- .irq = IFX_PCIE_INTC,
+ },
+ {
+ .irq_bit = PCIE_IRN_INTD,
+- .irq = IFX_PCIE_INTD,
+ },
+ },
+ },
+@@ -82,6 +84,22 @@ void ifx_pcie_debug(const char *fmt, ...
+ printk("%s", buf);
+ }
+
++static inline void pcie_ep_gpio_rst_init(int pcie_port)
++{
++ gpio_direction_output(pcie_reset_gpio, 1);
++ gpio_set_value(pcie_reset_gpio, 1);
++}
++
++static inline void pcie_device_rst_assert(int pcie_port)
++{
++ gpio_set_value(pcie_reset_gpio, 0);
++}
++
++static inline void pcie_device_rst_deassert(int pcie_port)
++{
++ mdelay(100);
++ gpio_direction_output(pcie_reset_gpio, 1);
++}
+
+ static inline int pcie_ltssm_enable(int pcie_port)
+ {
+@@ -857,7 +875,8 @@ pcie_rc_core_int_init(int pcie_port)
+ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0,
+ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]);
+ if (ret)
+- printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR);
++ printk(KERN_ERR "%s request irq %d failed\n", __func__,
++ pcie_irqs[pcie_port].ir_irq.irq);
+
+ return ret;
+ }
+@@ -988,10 +1007,26 @@ int ifx_pcie_bios_plat_dev_init(struct
+ static int
+ pcie_rc_initialize(int pcie_port)
+ {
+- int i;
++ int i, ret;
+ #define IFX_PCIE_PHY_LOOP_CNT 5
+
+- pcie_rcu_endian_setup(pcie_port);
++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M,
++ IFX_RCU_AHB_BE_PCIE_M);
++
++#ifdef CONFIG_IFX_PCIE_HW_SWAP
++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
++ IFX_RCU_AHB_BE_PCIE_S);
++ if (switch_pcie_endianess) {
++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_S,
++ IFX_RCU_AHB_BE_XBAR_S);
++ }
++#else
++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,
++ 0x0);
++#endif
++
++ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M,
++ 0x0);
+
+ pcie_ep_gpio_rst_init(pcie_port);
+
+@@ -1000,26 +1035,21 @@ pcie_rc_initialize(int pcie_port)
+ * reset PCIe PHY will solve this issue
+ */
+ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {
+- /* Disable PCIe PHY Analog part for sanity check */
+- pcie_phy_pmu_disable(pcie_port);
+-
+- pcie_phy_rst_assert(pcie_port);
+- pcie_phy_rst_deassert(pcie_port);
+-
+- /* Make sure PHY PLL is stable */
+- udelay(20);
+-
+- /* PCIe Core reset enabled, low active, sw programmed */
+- pcie_core_rst_assert(pcie_port);
++ ret = phy_init(ltq_pcie_phy);
++ if (ret)
++ continue;
+
+ /* Put PCIe EP in reset status */
+ pcie_device_rst_assert(pcie_port);
+
+- /* PCI PHY & Core reset disabled, high active, sw programmed */
+- pcie_core_rst_deassert(pcie_port);
++ udelay(1);
++ reset_control_deassert(ltq_pcie_reset);
+
+- /* Already in a quiet state, program PLL, enable PHY, check ready bit */
+- pcie_phy_clock_mode_setup(pcie_port);
++ ret = phy_power_on(ltq_pcie_phy);
++ if (ret) {
++ phy_exit(ltq_pcie_phy);
++ continue;
++ }
+
+ /* Enable PCIe PHY and Clock */
+ pcie_core_pmu_setup(pcie_port);
+@@ -1035,6 +1065,10 @@ pcie_rc_initialize(int pcie_port)
+ /* Once link is up, break out */
+ if (pcie_app_loigc_setup(pcie_port) == 0)
+ break;
++
++ phy_power_off(ltq_pcie_phy);
++ reset_control_assert(ltq_pcie_reset);
++ phy_exit(ltq_pcie_phy);
+ }
+ if (i >= IFX_PCIE_PHY_LOOP_CNT) {
+ printk(KERN_ERR "%s link up failed!!!!!\n", __func__);
+@@ -1045,17 +1079,73 @@ pcie_rc_initialize(int pcie_port)
+ return 0;
+ }
+
+-static int __init ifx_pcie_bios_init(void)
++static int ifx_pcie_bios_probe(struct platform_device *pdev)
+ {
++ struct device_node *node = pdev->dev.of_node;
+ void __iomem *io_map_base;
+ int pcie_port;
+ int startup_port;
++ struct device_node *np;
++ struct pci_bus *bus;
++
++ /*
++ * In case a PCI device is physical present, the Lantiq PCI driver need
++ * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them
++ * will work.
++ *
++ * In case the lantiq PCI driver is enabled in the device tree, check if
++ * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already
++ * registered.
++ *
++ * It will fail if there is another PCI controller, this controller is
++ * registered before the Lantiq PCIe driver is probe and the lantiq PCI
++ */
++ np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway");
++
++ if (of_device_is_available(np)) {
++ bus = pci_find_next_bus(bus);
++
++ if (!bus)
++ return -EPROBE_DEFER;
++ }
+
+ /* Enable AHB Master/ Slave */
+ pcie_ahb_pmu_setup();
+
+ startup_port = IFX_PCIE_PORT0;
+-
++
++ ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie");
++ if (IS_ERR(ltq_pcie_phy))
++ return dev_err_probe(&pdev->dev, PTR_ERR(ltq_pcie_phy),
++ "failed to get the PCIe PHY\n");
++
++ ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL);
++ if (IS_ERR(ltq_pcie_reset)) {
++ dev_err(&pdev->dev, "failed to get the PCIe reset line\n");
++ return PTR_ERR(ltq_pcie_reset);
++ }
++
++ if (of_property_read_bool(node, "lantiq,switch-pcie-endianess")) {
++ switch_pcie_endianess = true;
++ dev_info(&pdev->dev, "switch pcie endianess requested\n");
++ } else {
++ switch_pcie_endianess = false;
++ }
++
++ ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu");
++ if (IS_ERR(ltq_rcu_regmap))
++ return PTR_ERR(ltq_rcu_regmap);
++
++ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
++ if (gpio_is_valid(pcie_reset_gpio)) {
++ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset");
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio);
++ return ret;
++ }
++ gpio_direction_output(pcie_reset_gpio, 1);
++ }
++
+ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){
+ if (pcie_rc_initialize(pcie_port) == 0) {
+ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n",
+@@ -1066,7 +1156,19 @@ static int __init ifx_pcie_bios_init(voi
+ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__);
+ return -ENOMEM;
+ }
++ pcie_irqs[pcie_port].ir_irq.irq = platform_get_irq(pdev, 0);
++ if (pcie_irqs[pcie_port].ir_irq.irq < 0)
++ return pcie_irqs[pcie_port].ir_irq.irq;
++
++ for (int i = 0; i <= 3; i++){
++ pcie_irqs[pcie_port].legacy_irq[i].irq = platform_get_irq(pdev, i + 1);
++
++ if (pcie_irqs[pcie_port].legacy_irq[i].irq < 0)
++ return pcie_irqs[pcie_port].legacy_irq[i].irq;
++ }
++
+ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;
++ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node);
+
+ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);
+ /* XXX, clear error status */
+@@ -1083,6 +1185,30 @@ static int __init ifx_pcie_bios_init(voi
+
+ return 0;
+ }
++
++static const struct of_device_id ifxmips_pcie_match[] = {
++ { .compatible = "lantiq,pcie-xrx200" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, ifxmips_pcie_match);
++
++static struct platform_driver ltq_pci_driver = {
++ .probe = ifx_pcie_bios_probe,
++ .driver = {
++ .name = "pcie-xrx200",
++ .owner = THIS_MODULE,
++ .of_match_table = ifxmips_pcie_match,
++ },
++};
++
++int __init ifx_pcie_bios_init(void)
++{
++ int ret = platform_driver_register(<q_pci_driver);
++ if (ret)
++ pr_info("pcie-xrx200: Error registering platform driver!");
++ return ret;
++}
++
+ arch_initcall(ifx_pcie_bios_init);
+
+ MODULE_LICENSE("GPL");
+--- a/arch/mips/pci/ifxmips_pcie_vr9.h
++++ b/arch/mips/pci/ifxmips_pcie_vr9.h
+@@ -22,8 +22,6 @@
+ #include <linux/gpio.h>
+ #include <lantiq_soc.h>
+
+-#define IFX_PCIE_GPIO_RESET 494
+-
+ #define IFX_REG_R32 ltq_r32
+ #define IFX_REG_W32 ltq_w32
+ #define CONFIG_IFX_PCIE_HW_SWAP
+@@ -54,21 +52,6 @@
+ #define OUT ((volatile u32*)(IFX_GPIO + 0x0070))
+
+
+-static inline void pcie_ep_gpio_rst_init(int pcie_port)
+-{
+-
+- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset");
+- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
+- gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
+-
+-/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/
+-}
+-
+ static inline void pcie_ahb_pmu_setup(void)
+ {
+ /* Enable AHB bus master/slave */
+@@ -80,24 +63,6 @@ static inline void pcie_ahb_pmu_setup(vo
+ //AHBS_PMU_SETUP(IFX_PMU_ENABLE);
+ }
+
+-static inline void pcie_rcu_endian_setup(int pcie_port)
+-{
+- u32 reg;
+-
+- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
+-#ifdef CONFIG_IFX_PCIE_HW_SWAP
+- reg |= IFX_RCU_AHB_BE_PCIE_M;
+- reg |= IFX_RCU_AHB_BE_PCIE_S;
+- reg &= ~IFX_RCU_AHB_BE_XBAR_M;
+-#else
+- reg |= IFX_RCU_AHB_BE_PCIE_M;
+- reg &= ~IFX_RCU_AHB_BE_PCIE_S;
+- reg &= ~IFX_RCU_AHB_BE_XBAR_M;
+-#endif /* CONFIG_IFX_PCIE_HW_SWAP */
+- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
+- IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));
+-}
+-
+ static inline void pcie_phy_pmu_enable(int pcie_port)
+ {
+ struct clk *clk;
+@@ -116,17 +81,6 @@ static inline void pcie_phy_pmu_disable(
+ // PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);
+ }
+
+-static inline void pcie_pdi_big_endian(int pcie_port)
+-{
+- u32 reg;
+-
+- /* SRAM2PDI endianness control. */
+- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);
+- /* Config AHB->PCIe and PDI endianness */
+- reg |= IFX_RCU_AHB_BE_PCIE_PDI;
+- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);
+-}
+-
+ static inline void pcie_pdi_pmu_enable(int pcie_port)
+ {
+ /* Enable PDI to access PCIe PHY register */
+@@ -136,65 +90,6 @@ static inline void pcie_pdi_pmu_enable(i
+ //PDI_PMU_SETUP(IFX_PMU_ENABLE);
+ }
+
+-static inline void pcie_core_rst_assert(int pcie_port)
+-{
+- u32 reg;
+-
+- reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+-
+- /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */
+- reg |= 0x00400000;
+- IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_core_rst_deassert(int pcie_port)
+-{
+- u32 reg;
+-
+- /* Make sure one micro-second delay */
+- udelay(1);
+-
+- /* Reset PCIe PHY & Core, bit 22 */
+- reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+- reg &= ~0x00400000;
+- IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_phy_rst_assert(int pcie_port)
+-{
+- u32 reg;
+-
+- reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+- reg |= 0x00001000; /* Bit 12 */
+- IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_phy_rst_deassert(int pcie_port)
+-{
+- u32 reg;
+-
+- /* Make sure one micro-second delay */
+- udelay(1);
+-
+- reg = IFX_REG_R32(IFX_RCU_RST_REQ);
+- reg &= ~0x00001000; /* Bit 12 */
+- IFX_REG_W32(reg, IFX_RCU_RST_REQ);
+-}
+-
+-static inline void pcie_device_rst_assert(int pcie_port)
+-{
+- gpio_set_value(IFX_PCIE_GPIO_RESET, 0);
+-// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-}
+-
+-static inline void pcie_device_rst_deassert(int pcie_port)
+-{
+- mdelay(100);
+- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1);
+-// gpio_set_value(IFX_PCIE_GPIO_RESET, 1);
+- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);
+-}
+-
+ static inline void pcie_core_pmu_setup(int pcie_port)
+ {
+ struct clk *clk;
+--- a/arch/mips/pci/ifxmips_pcie.h
++++ b/arch/mips/pci/ifxmips_pcie.h
+@@ -96,13 +96,13 @@ struct ifx_pci_controller {
+ };
+
+ typedef struct ifx_pcie_ir_irq {
+- const unsigned int irq;
++ unsigned int irq;
+ const char name[16];
+ }ifx_pcie_ir_irq_t;
+
+ typedef struct ifx_pcie_legacy_irq{
+ const u32 irq_bit;
+- const int irq;
++ int irq;
+ }ifx_pcie_legacy_irq_t;
+
+ typedef struct ifx_pcie_irq {
--- /dev/null
+From 4d48a3d1ef6f8d036bd926e3c1f70b56fcc679b2 Mon Sep 17 00:00:00 2001
+From: Stefan Koch <stefan.koch10@gmail.com>
+Date: Thu, 20 Oct 2016 21:32:00 +0200
+Subject: [PATCH] lantiq: vpe
+
+Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
+---
+ arch/mips/Kconfig | 6 ++++
+ arch/mips/include/asm/mipsmtregs.h | 5 ++++
+ arch/mips/include/asm/vpe.h | 9 ++++++
+ arch/mips/kernel/vpe-mt.c | 47 ++++++++++++++++++++++++++++++
+ arch/mips/kernel/vpe.c | 35 ++++++++++++++++++++++
+ arch/mips/lantiq/prom.c | 4 +++
+ 6 files changed, 106 insertions(+)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -2306,6 +2306,12 @@ config MIPS_VPE_LOADER
+ Includes a loader for loading an elf relocatable object
+ onto another VPE and running it.
+
++config IFX_VPE_EXT
++ bool "IFX APRP Extensions"
++ depends on MIPS_VPE_LOADER
++ help
++ IFX included extensions in APRP
++
+ config MIPS_VPE_LOADER_CMP
+ bool
+ default "y"
+--- a/arch/mips/include/asm/mipsmtregs.h
++++ b/arch/mips/include/asm/mipsmtregs.h
+@@ -31,6 +31,9 @@
+ #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3)
+ #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val)
+
++#define read_c0_vpeopt() __read_32bit_c0_register($1, 7)
++#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val)
++
+ #define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
+ #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
+
+@@ -377,6 +380,8 @@ do { \
+ #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
+ #define read_vpe_c0_vpeconf1() mftc0(1, 3)
+ #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val)
++#define read_vpe_c0_vpeopt() mftc0(1, 7)
++#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val)
+ #define read_vpe_c0_count() mftc0(9, 0)
+ #define write_vpe_c0_count(val) mttc0(9, 0, val)
+ #define read_vpe_c0_status() mftc0(12, 0)
+--- a/arch/mips/include/asm/vpe.h
++++ b/arch/mips/include/asm/vpe.h
+@@ -124,4 +124,13 @@ void cleanup_tc(struct tc *tc);
+
+ int __init vpe_module_init(void);
+ void __exit vpe_module_exit(void);
++
++/* For the explanation of the APIs please refer the section "MT APRP Kernel
++ * Programming" in AR9 SW Architecture Specification
++ */
++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags);
++int32_t vpe1_sw_stop(uint32_t flags);
++uint32_t vpe1_get_load_addr(uint32_t flags);
++uint32_t vpe1_get_max_mem(uint32_t flags);
++
+ #endif /* _ASM_VPE_H */
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -416,6 +416,8 @@ int __init vpe_module_init(void)
+ }
+
+ v->ntcs = hw_tcs - aprp_cpu_index();
++ write_tc_c0_tcbind((read_tc_c0_tcbind() &
++ ~TCBIND_CURVPE) | 1);
+
+ /* add the tc to the list of this vpe's tc's. */
+ list_add(&t->tc, &v->tc);
+@@ -519,3 +521,47 @@ void __exit vpe_module_exit(void)
+ release_vpe(v);
+ }
+ }
++
++#ifdef CONFIG_IFX_VPE_EXT
++int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags)
++{
++ enum vpe_state state;
++ struct vpe *v = get_vpe(tclimit);
++ struct vpe_notifications *not;
++
++ if (tcmask || flags) {
++ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n");
++ return -1;
++ }
++
++ state = xchg(&v->state, VPE_STATE_INUSE);
++ if (state != VPE_STATE_UNUSED) {
++ vpe_stop(v);
++
++ list_for_each_entry(not, &v->notify, list) {
++ not->stop(tclimit);
++ }
++ }
++
++ v->__start = (unsigned long)sw_start_addr;
++
++ if (!vpe_run(v)) {
++ pr_debug("VPE loader: VPE1 running successfully\n");
++ return 0;
++ }
++ return -1;
++}
++EXPORT_SYMBOL(vpe1_sw_start);
++
++int32_t vpe1_sw_stop(uint32_t flags)
++{
++ struct vpe *v = get_vpe(tclimit);
++
++ if (!vpe_free(v)) {
++ pr_debug("RP Stopped\n");
++ return 0;
++ } else
++ return -1;
++}
++EXPORT_SYMBOL(vpe1_sw_stop);
++#endif
+--- a/arch/mips/kernel/vpe.c
++++ b/arch/mips/kernel/vpe.c
+@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = {
+ .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list)
+ };
+
++#ifdef CONFIG_IFX_VPE_EXT
++unsigned int vpe1_load_addr;
++
++static int __init load_address(char *str)
++{
++ get_option(&str, &vpe1_load_addr);
++ return 1;
++}
++__setup("vpe1_load_addr=", load_address);
++
++static unsigned int vpe1_mem;
++static int __init vpe1mem(char *str)
++{
++ vpe1_mem = memparse(str, &str);
++ return 1;
++}
++__setup("vpe1_mem=", vpe1mem);
++
++uint32_t vpe1_get_load_addr(uint32_t flags)
++{
++ return vpe1_load_addr;
++}
++EXPORT_SYMBOL(vpe1_get_load_addr);
++
++uint32_t vpe1_get_max_mem(uint32_t flags)
++{
++ if (!vpe1_mem)
++ return P_SIZE;
++ else
++ return vpe1_mem;
++}
++EXPORT_SYMBOL(vpe1_get_max_mem);
++
++#endif
++
+ /* get the vpe associated with this minor */
+ struct vpe *get_vpe(int minor)
+ {
+--- a/arch/mips/lantiq/prom.c
++++ b/arch/mips/lantiq/prom.c
+@@ -42,10 +42,14 @@ extern const struct plat_smp_ops vsmp_sm
+ static struct plat_smp_ops lantiq_smp_ops;
+ #endif
+
++/* for Multithreading (APRP), vpe.c will use it */
++unsigned long cp0_memsize;
++
+ const char *get_system_type(void)
+ {
+ return soc_info.sys_type;
+ }
++EXPORT_SYMBOL(ltq_soc_type);
+
+ int ltq_soc_type(void)
+ {
--- /dev/null
+From 3c92a781de062064e36b867c0ab22f9aba48f3d3 Mon Sep 17 00:00:00 2001
+From: Eddi De Pieri <eddi@depieri.net>
+Date: Tue, 8 Nov 2016 17:38:00 +0100
+Subject: [PATCH] lantiq: pci: bar11mask fix
+
+Signed-off-by: Eddi De Pieri <eddi@depieri.net>
+---
+ arch/mips/pci/pci-lantiq.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -59,6 +59,8 @@
+ #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
+ #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
+
++extern u32 max_low_pfn;
++
+ __iomem void *ltq_pci_mapped_cfg;
+ static __iomem void *ltq_pci_membase;
+
+@@ -84,8 +86,8 @@ static inline u32 ltq_calc_bar11mask(voi
+ u32 mem, bar11mask;
+
+ /* BAR11MASK value depends on available memory on system. */
+- mem = get_num_physpages() * PAGE_SIZE;
+- bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
++ mem = max_low_pfn << PAGE_SHIFT;
++ bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8;
+
+ return bar11mask;
+ }
--- /dev/null
+From 07ce9e9bc4dcd5ac4728e587901112eef95bbe7b Mon Sep 17 00:00:00 2001
+From: Stefan Koch <stefan.koch10@gmail.com>
+Date: Mon, 13 Mar 2017 23:42:00 +0100
+Subject: [PATCH] lantiq: vpe nosmp
+
+Signed-off-by: Stefan Koch <stefan.koch10@gmail.com>
+---
+ arch/mips/kernel/vpe-mt.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/kernel/vpe-mt.c
++++ b/arch/mips/kernel/vpe-mt.c
+@@ -131,7 +131,10 @@ int vpe_run(struct vpe *v)
+ * kernels need to turn it on, even if that wasn't the pre-dvpe() state.
+ */
+ #ifdef CONFIG_SMP
+- evpe(vpeflags);
++ if (!setup_max_cpus) /* nosmp is set */
++ evpe(EVPE_ENABLE);
++ else
++ evpe(vpeflags);
+ #else
+ evpe(EVPE_ENABLE);
+ #endif
--- /dev/null
+From ebaae1cd68cd79c7eee67c9c5c0fa45809e84525 Mon Sep 17 00:00:00 2001
+From: Maikel Bloemendal <openwrt@maikelenyvonne.nl>
+Date: Fri, 14 Nov 2014 17:06:00 +0000
+Subject: [PATCH] owrt: lantiq: multiple flash
+
+Signed-off-by: Maikel Bloemendal <openwrt@maikelenyvonne.nl>
+---
+ drivers/mtd/maps/lantiq-flash.c | 168 +++++++++++++++++++++-----------
+ 1 file changed, 109 insertions(+), 59 deletions(-)
+
+--- a/drivers/mtd/maps/lantiq-flash.c
++++ b/drivers/mtd/maps/lantiq-flash.c
+@@ -17,6 +17,7 @@
+ #include <linux/mtd/cfi.h>
+ #include <linux/platform_device.h>
+ #include <linux/mtd/physmap.h>
++#include <linux/mtd/concat.h>
+ #include <linux/of.h>
+
+ #include <lantiq_soc.h>
+@@ -36,13 +37,16 @@ enum {
+ LTQ_NOR_NORMAL
+ };
+
++#define MAX_RESOURCES 4
++
+ struct ltq_mtd {
+- struct resource *res;
+- struct mtd_info *mtd;
+- struct map_info *map;
++ struct mtd_info *mtd[MAX_RESOURCES];
++ struct mtd_info *cmtd;
++ struct map_info map[MAX_RESOURCES];
+ };
+
+ static const char ltq_map_name[] = "ltq_nor";
++static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL };
+
+ static map_word
+ ltq_read16(struct map_info *map, unsigned long adr)
+@@ -106,11 +110,43 @@ ltq_copy_to(struct map_info *map, unsign
+ }
+
+ static int
++ltq_mtd_remove(struct platform_device *pdev)
++{
++ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);
++ int i;
++
++ if (ltq_mtd == NULL)
++ return 0;
++
++ if (ltq_mtd->cmtd) {
++ mtd_device_unregister(ltq_mtd->cmtd);
++ if (ltq_mtd->cmtd != ltq_mtd->mtd[0])
++ mtd_concat_destroy(ltq_mtd->cmtd);
++ }
++
++ for (i = 0; i < MAX_RESOURCES; i++) {
++ if (ltq_mtd->mtd[i] != NULL)
++ map_destroy(ltq_mtd->mtd[i]);
++ }
++
++ kfree(ltq_mtd);
++
++ return 0;
++}
++
++static int
+ ltq_mtd_probe(struct platform_device *pdev)
+ {
+ struct ltq_mtd *ltq_mtd;
+ struct cfi_private *cfi;
+- int err;
++ int err = 0;
++ int i;
++ int devices_found = 0;
++
++ static const char *rom_probe_types[] = {
++ "cfi_probe", "jedec_probe", NULL
++ };
++ const char **type;
+
+ ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);
+ if (!ltq_mtd)
+@@ -118,75 +154,89 @@ ltq_mtd_probe(struct platform_device *pd
+
+ platform_set_drvdata(pdev, ltq_mtd);
+
+- ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!ltq_mtd->res) {
+- dev_err(&pdev->dev, "failed to get memory resource\n");
+- return -ENOENT;
++ for (i = 0; i < pdev->num_resources; i++) {
++ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n",
++ (unsigned long long)resource_size(&pdev->resource[i]),
++ (unsigned long long)pdev->resource[i].start);
++
++ if (!devm_request_mem_region(&pdev->dev,
++ pdev->resource[i].start,
++ resource_size(&pdev->resource[i]),
++ dev_name(&pdev->dev))) {
++ dev_err(&pdev->dev, "Could not reserve memory region\n");
++ return -ENOMEM;
++ }
++
++ ltq_mtd->map[i].name = ltq_map_name;
++ ltq_mtd->map[i].bankwidth = 2;
++ ltq_mtd->map[i].read = ltq_read16;
++ ltq_mtd->map[i].write = ltq_write16;
++ ltq_mtd->map[i].copy_from = ltq_copy_from;
++ ltq_mtd->map[i].copy_to = ltq_copy_to;
++
++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
++ ltq_mtd->map[i].phys = NO_XIP;
++ else
++ ltq_mtd->map[i].phys = pdev->resource[i].start;
++ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]);
++ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start,
++ ltq_mtd->map[i].size);
++ if (IS_ERR(ltq_mtd->map[i].virt))
++ return PTR_ERR(ltq_mtd->map[i].virt);
++
++ if (ltq_mtd->map[i].virt == NULL) {
++ dev_err(&pdev->dev, "Failed to ioremap flash region\n");
++ err = PTR_ERR(ltq_mtd->map[i].virt);
++ goto err_out;
++ }
++
++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING;
++ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++)
++ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]);
++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL;
++
++ if (!ltq_mtd->mtd[i]) {
++ dev_err(&pdev->dev, "probing failed\n");
++ return -ENXIO;
++ } else {
++ devices_found++;
++ }
++
++ ltq_mtd->mtd[i]->owner = THIS_MODULE;
++ ltq_mtd->mtd[i]->dev.parent = &pdev->dev;
++
++ cfi = ltq_mtd->map[i].fldrv_priv;
++ cfi->addr_unlock1 ^= 1;
++ cfi->addr_unlock2 ^= 1;
+ }
+
+- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info),
+- GFP_KERNEL);
+- if (!ltq_mtd->map)
+- return -ENOMEM;
+-
+- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
+- ltq_mtd->map->phys = NO_XIP;
+- else
+- ltq_mtd->map->phys = ltq_mtd->res->start;
+- ltq_mtd->res->start;
+- ltq_mtd->map->size = resource_size(ltq_mtd->res);
+- ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res);
+- if (IS_ERR(ltq_mtd->map->virt))
+- return PTR_ERR(ltq_mtd->map->virt);
+-
+- ltq_mtd->map->name = ltq_map_name;
+- ltq_mtd->map->bankwidth = 2;
+- ltq_mtd->map->read = ltq_read16;
+- ltq_mtd->map->write = ltq_write16;
+- ltq_mtd->map->copy_from = ltq_copy_from;
+- ltq_mtd->map->copy_to = ltq_copy_to;
+-
+- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING;
+- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map);
+- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL;
+-
+- if (!ltq_mtd->mtd) {
+- dev_err(&pdev->dev, "probing failed\n");
+- return -ENXIO;
++ if (devices_found == 1) {
++ ltq_mtd->cmtd = ltq_mtd->mtd[0];
++ } else if (devices_found > 1) {
++ /*
++ * We detected multiple devices. Concatenate them together.
++ */
++ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev));
++ if (ltq_mtd->cmtd == NULL)
++ err = -ENXIO;
+ }
+
+- ltq_mtd->mtd->dev.parent = &pdev->dev;
+- mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node);
+-
+- cfi = ltq_mtd->map->fldrv_priv;
+- cfi->addr_unlock1 ^= 1;
+- cfi->addr_unlock2 ^= 1;
++ ltq_mtd->cmtd->dev.parent = &pdev->dev;
++ mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node);
+
+- err = mtd_device_register(ltq_mtd->mtd, NULL, 0);
++ err = mtd_device_register(ltq_mtd->cmtd, NULL, 0);
+ if (err) {
+ dev_err(&pdev->dev, "failed to add partitions\n");
+- goto err_destroy;
++ goto err_out;
+ }
+
+ return 0;
+
+-err_destroy:
+- map_destroy(ltq_mtd->mtd);
++err_out:
++ ltq_mtd_remove(pdev);
+ return err;
+ }
+
+-static int
+-ltq_mtd_remove(struct platform_device *pdev)
+-{
+- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);
+-
+- if (ltq_mtd && ltq_mtd->mtd) {
+- mtd_device_unregister(ltq_mtd->mtd);
+- map_destroy(ltq_mtd->mtd);
+- }
+- return 0;
+-}
+-
+ static const struct of_device_id ltq_mtd_match[] = {
+ { .compatible = "lantiq,nor" },
+ {},
--- /dev/null
+From 2b873c59fd313aee57864f96d64a228f2ea7c208 Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Mon, 13 May 2024 10:42:24 +0200
+Subject: [PATCH] MIPS: lantiq: xway: vmmc: use platform_get_irq to get irqs
+ from dts
+
+Let's fetch the irqs from the dts here and expose them to the voice
+driver like it is done for the cp1 base memory.
+
+ToDo:
+Maybe it is possible to drop this driver completely and merge this
+handling to the voice driver.
+
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ arch/mips/lantiq/xway/vmmc.c | 53 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+--- a/arch/mips/lantiq/xway/vmmc.c
++++ b/arch/mips/lantiq/xway/vmmc.c
+@@ -14,6 +14,10 @@
+
+ static unsigned int *cp1_base;
+
++static int ad0_irq;
++static int ad1_irq;
++static int vc_irq[4];
++
+ unsigned int *ltq_get_cp1_base(void)
+ {
+ if (!cp1_base)
+@@ -23,6 +27,33 @@ unsigned int *ltq_get_cp1_base(void)
+ }
+ EXPORT_SYMBOL(ltq_get_cp1_base);
+
++unsigned int ltq_get_mps_ad0_irq(void)
++{
++ if (!ad0_irq)
++ panic("no ad0 irq was set\n");
++
++ return ad0_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad0_irq);
++
++unsigned int ltq_get_mps_ad1_irq(void)
++{
++ if (!ad1_irq)
++ panic("no ad1 irq was set\n");
++
++ return ad1_irq;
++}
++EXPORT_SYMBOL(ltq_get_mps_ad1_irq);
++
++unsigned int ltq_get_mps_vc_irq(int idx)
++{
++ if (!vc_irq[idx])
++ panic("no vc%d irq was set\n", idx);
++
++ return vc_irq[idx];
++}
++EXPORT_SYMBOL(ltq_get_mps_vc_irq);
++
+ static int vmmc_probe(struct platform_device *pdev)
+ {
+ #define CP1_SIZE (1 << 20)
+@@ -30,11 +61,33 @@ static int vmmc_probe(struct platform_de
+ int gpio_count;
+ dma_addr_t dma;
+ int error;
++ int i;
+
+ cp1_base =
+ (void *) CPHYSADDR(dma_alloc_coherent(&pdev->dev, CP1_SIZE,
+ &dma, GFP_KERNEL));
+
++ ad0_irq = platform_get_irq(pdev, 4);
++ if (ad0_irq < 0) {
++ dev_err(&pdev->dev, "failed to get MPS AD0 irq: %d\n", ad0_irq);
++ return ad0_irq;
++ }
++
++ ad1_irq = platform_get_irq(pdev, 5);
++ if (ad1_irq < 0) {
++ dev_err(&pdev->dev, "failed to get MPS AD1 irq: %d\n", ad1_irq);
++ return ad1_irq;
++ }
++
++ for (i = 0; i < 4; i++) {
++ vc_irq[i] = platform_get_irq(pdev, i);
++ if (vc_irq[i] < 0) {
++ dev_err(&pdev->dev, "failed to get MPS VC%d irq: %d\n",
++ i, vc_irq[i]);
++ return vc_irq[i];
++ }
++ }
++
+ gpio_count = gpiod_count(&pdev->dev, NULL);
+ while (gpio_count > 0) {
+ gpio = devm_gpiod_get_index(&pdev->dev,
--- /dev/null
+From 5e93c85ac3e5626d1aa7e7f9c0a008b2a4224f04 Mon Sep 17 00:00:00 2001
+From: Matti Laakso <malaakso@elisanet.fi>
+Date: Sat, 14 Feb 2015 20:48:00 +0000
+Subject: [PATCH] MTD: cfi_cmdset_0001: disable buffered writes
+
+Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
+---
+ drivers/mtd/chips/cfi_cmdset_0001.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0001.c
++++ b/drivers/mtd/chips/cfi_cmdset_0001.c
+@@ -39,7 +39,7 @@
+ /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */
+
+ // debugging, turns off buffer write mode if set to 1
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+
+ /* Intel chips */
+ #define I82802AB 0x00ad
--- /dev/null
+From 5502ef9d40ab20b2ac683660d1565a7c4968bcc8 Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <openwrt@kresin.me>
+Date: Mon, 2 May 2016 18:50:00 +0000
+Subject: [PATCH] xrx200: add gphy clk src device tree binding
+
+Signed-off-by: Mathias Kresin <openwrt@kresin.me>
+---
+ arch/mips/lantiq/xway/sysctrl.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/mips/lantiq/xway/sysctrl.c
++++ b/arch/mips/lantiq/xway/sysctrl.c
+@@ -440,6 +440,20 @@ static void clkdev_add_clkout(void)
+ }
+ }
+
++static void set_phy_clock_source(struct device_node *np_cgu)
++{
++ u32 phy_clk_src, ifcc;
++
++ if (!np_cgu)
++ return;
++
++ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
++ return;
++
++ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
++ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
++}
++
+ /* bring up all register ranges that we need for basic system control */
+ void __init ltq_soc_init(void)
+ {
+@@ -609,4 +623,6 @@ void __init ltq_soc_init(void)
+ clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
+ }
+ usb_set_clock();
++
++ set_phy_clock_source(np_cgu);
+ }
--- /dev/null
+From 118fe2c88b35482711adeee0d8758bddfe958701 Mon Sep 17 00:00:00 2001
+From: Aleksander Jan Bajkowski <olek2@wp.pl>
+Date: Sat, 6 May 2023 14:32:00 +0200
+Subject: [PATCH] mtd: cfi_cmdset_0001: Disable write buffer functions if
+ FORCE_WORD_WRITE is 1
+
+Some write buffer functions are not used when FORCE_WORD_WRITE is set to 1.
+So the compile warning messages are output if FORCE_WORD_WRITE is 1. To
+resolve this disable the write buffer functions if FORCE_WORD_WRITE is 1.
+
+This is similar fix to: 557c759036fc3976a5358cef23e65a263853b93f.
+
+Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
+---
+ drivers/mtd/chips/cfi_cmdset_0001.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0001.c
++++ b/drivers/mtd/chips/cfi_cmdset_0001.c
+@@ -61,8 +61,10 @@
+
+ static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#if !FORCE_WORD_WRITE
+ static int cfi_intelext_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
+ static int cfi_intelext_writev(struct mtd_info *, const struct kvec *, unsigned long, loff_t, size_t *);
++#endif
+ static int cfi_intelext_erase_varsize(struct mtd_info *, struct erase_info *);
+ static void cfi_intelext_sync (struct mtd_info *);
+ static int cfi_intelext_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+@@ -304,6 +306,7 @@ static void fixup_use_point(struct mtd_i
+ }
+ }
+
++#if !FORCE_WORD_WRITE
+ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ {
+ struct map_info *map = mtd->priv;
+@@ -314,6 +317,7 @@ static void fixup_use_write_buffers(stru
+ mtd->_writev = cfi_intelext_writev;
+ }
+ }
++#endif /* !FORCE_WORD_WRITE */
+
+ /*
+ * Some chips power-up with all sectors locked by default.
+@@ -1719,6 +1723,7 @@ static int cfi_intelext_write_words (str
+ }
+
+
++#if !FORCE_WORD_WRITE
+ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+ unsigned long adr, const struct kvec **pvec,
+ unsigned long *pvec_seek, int len)
+@@ -1947,6 +1952,7 @@ static int cfi_intelext_write_buffers (s
+
+ return cfi_intelext_writev(mtd, &vec, 1, to, retlen);
+ }
++#endif /* !FORCE_WORD_WRITE */
+
+ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip,
+ unsigned long adr, int len, void *thunk)
--- /dev/null
+From 416f25a948d11ef15733f2e31658d31b5cc7bef6 Mon Sep 17 00:00:00 2001
+From: Thomas Nixon <tom@tomn.co.uk>
+Date: Sun, 26 Mar 2023 11:08:49 +0100
+Subject: [PATCH] mtd: rawnand: xway: don't yield while holding spinlock
+
+The nand driver normally while waiting for the device to become ready;
+this is normally fine, but xway_nand holds the ebu_lock spinlock, and
+this can cause lockups if other threads which use ebu_lock are
+interleaved. Fix this by waiting instead of polling.
+
+This mainly showed up as crashes in ath9k_pci_owl_loader (see
+https://github.com/openwrt/openwrt/issues/9829 ), but turning on
+spinlock debugging shows this happening in other places too.
+
+This doesn't seem to measurably impact boot time.
+
+Signed-off-by: Thomas Nixon <tom@tomn.co.uk>
+---
+ drivers/mtd/nand/raw/xway_nand.c | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/raw/xway_nand.c
++++ b/drivers/mtd/nand/raw/xway_nand.c
+@@ -175,7 +175,13 @@ static void xway_cmd_ctrl(struct nand_ch
+
+ static int xway_dev_ready(struct nand_chip *chip)
+ {
+- return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
++ /*
++ * wait until ready, as otherwise the driver will yield in nand_wait or
++ * nand_wait_ready, which is a bad idea when we're holding ebu_lock
++ */
++ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
++ cpu_relax();
++ return 1;
+ }
+
+ static unsigned char xway_read_byte(struct nand_chip *chip)
--- /dev/null
+From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
+From: Johann Neuhauser <johann@it-neuhauser.de>
+Date: Thu, 17 May 2018 19:12:35 +0200
+Subject: [PATCH] net: lantiq_etop: of mdio
+
+Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
+---
+ drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++-----------
+ 1 file changed, 389 insertions(+), 166 deletions(-)
+
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -31,6 +31,7 @@
+ #include <linux/of_net.h>
+ #include <linux/of_irq.h>
+ #include <linux/of_platform.h>
++#include <linux/of_mdio.h>
+
+ #include <asm/checksum.h>
+
+@@ -558,7 +559,8 @@ static int
+ ltq_etop_mdio_init(struct net_device *dev)
+ {
+ struct ltq_etop_priv *priv = netdev_priv(dev);
+- int err;
++ struct device_node *mdio_np = NULL;
++ int err, ret;
+
+ priv->mii_bus = mdiobus_alloc();
+ if (!priv->mii_bus) {
+@@ -578,7 +580,15 @@ ltq_etop_mdio_init(struct net_device *de
+ priv->mii_bus->name = "ltq_mii";
+ snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+ priv->pdev->name, priv->pdev->id);
+- if (mdiobus_register(priv->mii_bus)) {
++
++ mdio_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus");
++
++ if (mdio_np)
++ ret = of_mdiobus_register(priv->mii_bus, mdio_np);
++ else
++ ret = mdiobus_register(priv->mii_bus);
++
++ if (ret) {
+ err = -ENXIO;
+ goto err_out_free_mdiobus;
+ }
--- /dev/null
+From 82ea7c7fb4e90620beba8b6436fc12df2379ef8d Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 10 Oct 2022 16:52:25 +0200
+Subject: [PATCH 731/768] dt-bindings: net: dsa: lantiq_gswip: Add missing
+ phy-mode and fixed-link
+
+The CPU port has to specify a phy-mode and either a phy or a fixed-link.
+Since GSWIP is connected using a SoC internal protocol there's no PHY
+involved. Add phy-mode = "internal" and a fixed-link to describe the
+communication between the PMAC (Ethernet controller) and GSWIP switch.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
++++ b/Documentation/devicetree/bindings/net/dsa/lantiq-gswip.txt
+@@ -96,7 +96,13 @@ switch@e108000 {
+
+ port@6 {
+ reg = <0x6>;
++ phy-mode = "internal";
+ ethernet = <ð0>;
++
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
+ };
+ };
+
--- /dev/null
+From a55b9d802e11baceb35bd312419ad82086065b08 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 10 Oct 2022 16:59:35 +0200
+Subject: [PATCH 732/768] net: dsa: lantiq_gswip: Only allow phy-mode =
+ "internal" on the CPU port
+
+Add the CPU port to gswip_xrx200_phylink_get_caps() and
+gswip_xrx300_phylink_get_caps(). It connects through a SoC-internal bus,
+so the only allowed phy-mode is PHY_INTERFACE_MODE_INTERNAL.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1509,6 +1509,7 @@ static void gswip_xrx200_phylink_get_cap
+ case 2:
+ case 3:
+ case 4:
++ case 6:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ break;
+@@ -1540,6 +1541,7 @@ static void gswip_xrx300_phylink_get_cap
+ case 2:
+ case 3:
+ case 4:
++ case 6:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ break;
--- /dev/null
+From 4d3dd68a1c56674ff666d0622b545992fac31754 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Sun, 31 Jul 2022 22:54:52 +0200
+Subject: [PATCH 733/768] net: dsa: lantiq_gswip: Use dev_err_probe where
+ appropriate
+
+dev_err_probe() can be used to simplify the existing code. Also it means
+we get rid of the following warning which is seen whenever the PMAC
+(Ethernet controller which connects to GSWIP's CPU port) has not been
+probed yet:
+ gswip 1e108000.switch: dsa switch register failed: -517
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 53 ++++++++++++++++------------------
+ 1 file changed, 25 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1919,11 +1919,9 @@ static int gswip_gphy_fw_load(struct gsw
+ msleep(200);
+
+ ret = request_firmware(&fw, gphy_fw->fw_name, dev);
+- if (ret) {
+- dev_err(dev, "failed to load firmware: %s, error: %i\n",
+- gphy_fw->fw_name, ret);
+- return ret;
+- }
++ if (ret)
++ return dev_err_probe(dev, ret, "failed to load firmware: %s\n",
++ gphy_fw->fw_name);
+
+ /* GPHY cores need the firmware code in a persistent and contiguous
+ * memory area with a 16 kB boundary aligned start address.
+@@ -1936,9 +1934,9 @@ static int gswip_gphy_fw_load(struct gsw
+ dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
+ memcpy(fw_addr, fw->data, fw->size);
+ } else {
+- dev_err(dev, "failed to alloc firmware memory\n");
+ release_firmware(fw);
+- return -ENOMEM;
++ return dev_err_probe(dev, -ENOMEM,
++ "failed to alloc firmware memory\n");
+ }
+
+ release_firmware(fw);
+@@ -1965,8 +1963,8 @@ static int gswip_gphy_fw_probe(struct gs
+
+ gphy_fw->clk_gate = devm_clk_get(dev, gphyname);
+ if (IS_ERR(gphy_fw->clk_gate)) {
+- dev_err(dev, "Failed to lookup gate clock\n");
+- return PTR_ERR(gphy_fw->clk_gate);
++ return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate),
++ "Failed to lookup gate clock\n");
+ }
+
+ ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset);
+@@ -1986,8 +1984,8 @@ static int gswip_gphy_fw_probe(struct gs
+ gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name;
+ break;
+ default:
+- dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
+- return -EINVAL;
++ return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n",
++ gphy_mode);
+ }
+
+ gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np);
+@@ -2038,8 +2036,9 @@ static int gswip_gphy_fw_list(struct gsw
+ priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data;
+ break;
+ default:
+- dev_err(dev, "unknown GSWIP version: 0x%x", version);
+- return -ENOENT;
++ return dev_err_probe(dev, -ENOENT,
++ "unknown GSWIP version: 0x%x",
++ version);
+ }
+ }
+
+@@ -2047,10 +2046,9 @@ static int gswip_gphy_fw_list(struct gsw
+ if (match && match->data)
+ priv->gphy_fw_name_cfg = match->data;
+
+- if (!priv->gphy_fw_name_cfg) {
+- dev_err(dev, "GPHY compatible type not supported");
+- return -ENOENT;
+- }
++ if (!priv->gphy_fw_name_cfg)
++ return dev_err_probe(dev, -ENOENT,
++ "GPHY compatible type not supported");
+
+ priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np);
+ if (!priv->num_gphy_fw)
+@@ -2150,8 +2148,8 @@ static int gswip_probe(struct platform_d
+ return -EINVAL;
+ break;
+ default:
+- dev_err(dev, "unknown GSWIP version: 0x%x", version);
+- return -ENOENT;
++ return dev_err_probe(dev, -ENOENT,
++ "unknown GSWIP version: 0x%x", version);
+ }
+
+ /* bring up the mdio bus */
+@@ -2159,10 +2157,9 @@ static int gswip_probe(struct platform_d
+ if (gphy_fw_np) {
+ err = gswip_gphy_fw_list(priv, gphy_fw_np, version);
+ of_node_put(gphy_fw_np);
+- if (err) {
+- dev_err(dev, "gphy fw probe failed\n");
+- return err;
+- }
++ if (err)
++ return dev_err_probe(dev, err,
++ "gphy fw probe failed\n");
+ }
+
+ /* bring up the mdio bus */
+@@ -2170,20 +2167,20 @@ static int gswip_probe(struct platform_d
+ if (mdio_np) {
+ err = gswip_mdio(priv, mdio_np);
+ if (err) {
+- dev_err(dev, "mdio probe failed\n");
++ dev_err_probe(dev, err, "mdio probe failed\n");
+ goto put_mdio_node;
+ }
+ }
+
+ err = dsa_register_switch(priv->ds);
+ if (err) {
+- dev_err(dev, "dsa switch register failed: %i\n", err);
++ dev_err_probe(dev, err, "dsa switch registration failed\n");
+ goto mdio_bus;
+ }
+ if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
+- dev_err(dev, "wrong CPU port defined, HW only supports port: %i",
+- priv->hw_info->cpu_port);
+- err = -EINVAL;
++ err = dev_err_probe(dev, -EINVAL,
++ "wrong CPU port defined, HW only supports port: %i",
++ priv->hw_info->cpu_port);
+ goto disable_switch;
+ }
+
--- /dev/null
+From 8cf0b680abc157adeec3fb93a10354c470694535 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Thu, 28 Jul 2022 22:37:11 +0200
+Subject: [PATCH 734/768] net: dsa: lantiq_gswip: Don't manually call
+ gswip_port_enable()
+
+We don't need to manually call gswip_port_enable() from within
+gswip_setup() for the CPU port. DSA does this automatically for us.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -891,8 +891,6 @@ static int gswip_setup(struct dsa_switch
+
+ ds->mtu_enforcement_ingress = true;
+
+- gswip_port_enable(ds, cpu_port, NULL);
+-
+ ds->configure_vlan_while_not_filtering = false;
+
+ return 0;
--- /dev/null
+From 54a2f7f2c134738bd3f4ea0a213138d169f2726e Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Fri, 10 May 2024 13:52:10 +0200
+Subject: [PATCH] net: dsa: lantiq_gswip: do also enable or disable cpu port
+
+Before commit 74be4babe72f ("net: dsa: do not enable or disable non user
+ports"), gswip_port_enable/disable() were also executed for the cpu port
+in gswip_setup() which disabled the cpu port during initialization.
+
+Let's restore this by removing the dsa_is_user_port checks. Also, let's
+clean up the gswip_port_enable() function so that we only have to check
+for the cpu port once.
+
+Fixes: 74be4babe72f ("net: dsa: do not enable or disable non user ports")
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ drivers/net/dsa/lantiq_gswip.c | 24 ++++++++----------------
+ 1 file changed, 8 insertions(+), 16 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -688,13 +688,18 @@ static int gswip_port_enable(struct dsa_
+ struct gswip_priv *priv = ds->priv;
+ int err;
+
+- if (!dsa_is_user_port(ds, port))
+- return 0;
+-
+ if (!dsa_is_cpu_port(ds, port)) {
++ u32 mdio_phy = 0;
++
+ err = gswip_add_single_port_br(priv, port, true);
+ if (err)
+ return err;
++
++ if (phydev)
++ mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
++
++ gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
++ GSWIP_MDIO_PHYp(port));
+ }
+
+ /* RMON Counter Enable for port */
+@@ -707,16 +712,6 @@ static int gswip_port_enable(struct dsa_
+ gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN,
+ GSWIP_SDMA_PCTRLp(port));
+
+- if (!dsa_is_cpu_port(ds, port)) {
+- u32 mdio_phy = 0;
+-
+- if (phydev)
+- mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK;
+-
+- gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy,
+- GSWIP_MDIO_PHYp(port));
+- }
+-
+ return 0;
+ }
+
+@@ -724,9 +719,6 @@ static void gswip_port_disable(struct ds
+ {
+ struct gswip_priv *priv = ds->priv;
+
+- if (!dsa_is_user_port(ds, port))
+- return;
+-
+ gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0,
+ GSWIP_FDMA_PCTRLp(port));
+ gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0,
--- /dev/null
+From 8ab55ac9678ca1f50f786c84484599dd675c5a9f Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Wed, 18 May 2022 23:53:09 +0200
+Subject: [PATCH 736/768] net: dsa: lantiq_gswip: Use dsa_is_cpu_port() in
+ gswip_port_change_mtu()
+
+Make the check for the CPU port in gswip_port_change_mtu() consistent
+with other areas of the driver by using dsa_is_cpu_port().
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1457,12 +1457,11 @@ static int gswip_port_max_mtu(struct dsa
+ static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
+ {
+ struct gswip_priv *priv = ds->priv;
+- int cpu_port = priv->hw_info->cpu_port;
+
+ /* CPU port always has maximum mtu of user ports, so use it to set
+ * switch frame size, including 8 byte special header.
+ */
+- if (port == cpu_port) {
++ if (dsa_is_cpu_port(ds, port)) {
+ new_mtu += 8;
+ gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN,
+ GSWIP_MAC_FLEN);
--- /dev/null
+From ef98b183d8fc7187a2efcc21c8f54f3cf061d556 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Tue, 17 May 2022 22:39:58 +0200
+Subject: [PATCH 737/768] net: dsa: lantiq_gswip: Change literal 6 to ETH_ALEN
+
+The addr variable in gswip_port_fdb_dump() stores a mac address. Use
+ETH_ALEN to make this consistent across other drivers.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1406,7 +1406,7 @@ static int gswip_port_fdb_dump(struct ds
+ {
+ struct gswip_priv *priv = ds->priv;
+ struct gswip_pce_table_entry mac_bridge = {0,};
+- unsigned char addr[6];
++ unsigned char addr[ETH_ALEN];
+ int i;
+ int err;
+
--- /dev/null
+From 61e9b19f6e6174afa7540f0b468a69bc940b91d4 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 21:23:49 +0200
+Subject: [PATCH 738/768] net: dsa: lantiq_gswip: Consistently use macros for
+ the mac bridge table
+
+Introduce a new GSWIP_TABLE_MAC_BRIDGE_PORT macro and use it throughout
+the driver. Also update GSWIP_TABLE_MAC_BRIDGE_STATIC to use the BIT()
+macro. This makes the driver code easier to understand.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -236,7 +236,8 @@
+ #define GSWIP_TABLE_ACTIVE_VLAN 0x01
+ #define GSWIP_TABLE_VLAN_MAPPING 0x02
+ #define GSWIP_TABLE_MAC_BRIDGE 0x0b
+-#define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */
++#define GSWIP_TABLE_MAC_BRIDGE_STATIC BIT(0) /* Static not, aging entry */
++#define GSWIP_TABLE_MAC_BRIDGE_PORT GENMASK(7, 4) /* Port on learned entries */
+
+ #define XRX200_GPHY_FW_ALIGN (16 * 1024)
+
+@@ -1300,7 +1301,8 @@ static void gswip_port_fast_age(struct d
+ if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC)
+ continue;
+
+- if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port)
++ if (port != FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT,
++ mac_bridge.val[0]))
+ continue;
+
+ mac_bridge.valid = false;
+@@ -1438,7 +1440,8 @@ static int gswip_port_fdb_dump(struct ds
+ return err;
+ }
+ } else {
+- if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) {
++ if (port == FIELD_GET(GSWIP_TABLE_MAC_BRIDGE_PORT,
++ mac_bridge.val[0])) {
+ err = cb(addr, 0, false, data);
+ if (err)
+ return err;
--- /dev/null
+From 7a9e185075ababa827d1d3a33b787ad6d718c8ec Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 22:24:24 +0200
+Subject: [PATCH 739/768] net: dsa: lantiq_gswip: Forbid
+ gswip_add_single_port_br on the CPU port
+
+Calling gswip_add_single_port_br() with the CPU port would be a bug
+because then only the CPU port could talk to itself. Add the CPU port to
+the validation at the beginning of gswip_add_single_port_br().
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -650,7 +650,7 @@ static int gswip_add_single_port_br(stru
+ unsigned int max_ports = priv->hw_info->max_ports;
+ int err;
+
+- if (port >= max_ports) {
++ if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) {
+ dev_err(priv->dev, "single port for %i supported\n", port);
+ return -EIO;
+ }
--- /dev/null
+From 28be6bfb735d851e646abb05b8e24eb6764596f5 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Mon, 1 Aug 2022 22:26:20 +0200
+Subject: [PATCH 740/768] net: dsa: lantiq_gswip: Fix error message in
+ gswip_add_single_port_br()
+
+The error message is printed when the port cannot be used. Update the
+error message to reflect that.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -651,7 +651,8 @@ static int gswip_add_single_port_br(stru
+ int err;
+
+ if (port >= max_ports || dsa_is_cpu_port(priv->ds, port)) {
+- dev_err(priv->dev, "single port for %i supported\n", port);
++ dev_err(priv->dev, "single port for %i is not supported\n",
++ port);
+ return -EIO;
+ }
+
--- /dev/null
+From 45a0371568b1f050d787564875653f41a1f6fb98 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 14:06:40 +0200
+Subject: [PATCH 741/768] net: dsa: lantiq_gswip: Fix comments in
+ gswip_port_vlan_filtering()
+
+Update the comments in gswip_port_vlan_filtering() so it's clear that
+there are two separate cases, one for "tag based VLAN" and another one
+for "port based VLAN".
+
+Suggested-by: Martin Schiller <ms@dev.tdt.de>
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -779,7 +779,7 @@ static int gswip_port_vlan_filtering(str
+ }
+
+ if (vlan_filtering) {
+- /* Use port based VLAN tag */
++ /* Use tag based VLAN */
+ gswip_switch_mask(priv,
+ GSWIP_PCE_VCTRL_VSR,
+ GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
+@@ -788,7 +788,7 @@ static int gswip_port_vlan_filtering(str
+ gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0,
+ GSWIP_PCE_PCTRL_0p(port));
+ } else {
+- /* Use port based VLAN tag */
++ /* Use port based VLAN */
+ gswip_switch_mask(priv,
+ GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR |
+ GSWIP_PCE_VCTRL_VEMR,
--- /dev/null
+From 4775f9543e691d9a2f5dd9aa5d46c66d37928250 Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 14:19:05 +0200
+Subject: [PATCH 742/768] net: dsa: lantiq_gswip: Add and use a
+ GSWIP_TABLE_MAC_BRIDGE_FID macro
+
+Only bits [5:0] in mac_bridge.key[3] are reserved for the FID. Add a
+macro so this becomes obvious when reading the driver code.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -238,6 +238,7 @@
+ #define GSWIP_TABLE_MAC_BRIDGE 0x0b
+ #define GSWIP_TABLE_MAC_BRIDGE_STATIC BIT(0) /* Static not, aging entry */
+ #define GSWIP_TABLE_MAC_BRIDGE_PORT GENMASK(7, 4) /* Port on learned entries */
++#define GSWIP_TABLE_MAC_BRIDGE_FID GENMASK(5, 0) /* Filtering identifier */
+
+ #define XRX200_GPHY_FW_ALIGN (16 * 1024)
+
+@@ -1378,7 +1379,7 @@ static int gswip_port_fdb(struct dsa_swi
+ mac_bridge.key[0] = addr[5] | (addr[4] << 8);
+ mac_bridge.key[1] = addr[3] | (addr[2] << 8);
+ mac_bridge.key[2] = addr[1] | (addr[0] << 8);
+- mac_bridge.key[3] = fid;
++ mac_bridge.key[3] = FIELD_PREP(GSWIP_TABLE_MAC_BRIDGE_FID, fid);
+ mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */
+ mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC;
+ mac_bridge.valid = add;
--- /dev/null
+From 00b5121435ccd4ce54f79179dd9ee3e2610d7dcf Mon Sep 17 00:00:00 2001
+From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Date: Fri, 14 Oct 2022 16:31:57 +0200
+Subject: [PATCH 743/768] net: dsa: lantiq_gswip: Improve error message in
+ gswip_port_fdb()
+
+Print the port which is not found to be part of a bridge so it's easier
+to investigate the underlying issue.
+
+Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+---
+ drivers/net/dsa/lantiq_gswip.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/lantiq_gswip.c
++++ b/drivers/net/dsa/lantiq_gswip.c
+@@ -1370,7 +1370,8 @@ static int gswip_port_fdb(struct dsa_swi
+ }
+
+ if (fid == -1) {
+- dev_err(priv->dev, "Port not part of a bridge\n");
++ dev_err(priv->dev,
++ "Port %d is not known to be part of bridge\n", port);
+ return -EINVAL;
+ }
+
CONFIG_AT803X_PHY=y
CONFIG_BLK_MQ_PCI=y
-CONFIG_CPU_HAS_DIEI=y
CONFIG_CPU_MIPSR2_IRQ_EI=y
CONFIG_CPU_MIPSR2_IRQ_VI=y
CONFIG_CPU_RMAP=y
CONFIG_CRC16=y
-CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_LZO=y
CONFIG_IFX_VPE_EXT=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_POLLDEV=y
CONFIG_INTEL_XWAY_PHY=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
# CONFIG_ISDN is not set
CONFIG_LANTIQ_XRX200=y
CONFIG_LZO_COMPRESS=y
CONFIG_PCIE_LANTIQ=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_LANTIQ=y
+CONFIG_PHYLINK=y
CONFIG_PHY_LANTIQ_VRX200_PCIE=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_SUPPLY=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_UP=y
-CONFIG_SOC_TYPE_XWAY=y
-CONFIG_SOC_XWAY=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SYNC_R4K=y
CONFIG_SYS_SUPPORTS_SCHED_SMT=y
CONFIG_SYS_SUPPORTS_SMP=y
--- /dev/null
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin"
+CONFIG_EXTRA_FIRMWARE_DIR="firmware"
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GRO_CELLS=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_IFX_VPE_EXT=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INTEL_XWAY_PHY=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_XRX200=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MIPS_MT=y
+# CONFIG_MIPS_MT_FPAFF is not set
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MIPS_VPE_APSP_API=y
+CONFIG_MIPS_VPE_APSP_API_MT=y
+CONFIG_MIPS_VPE_LOADER=y
+CONFIG_MIPS_VPE_LOADER_MT=y
+CONFIG_MIPS_VPE_LOADER_TOM=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_NAND_XWAY=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_LANTIQ_GSWIP=y
+CONFIG_NET_DSA_TAG_GSWIP=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=2
+CONFIG_PADATA=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_LANTIQ=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_PHYLINK=y
+CONFIG_PHY_LANTIQ_VRX200_PCIE=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_SENSORS_LTQ_CPUTEMP=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
CONFIG_ADM6996_PHY=y
CONFIG_AR8216_PHY=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_AT803X_PHY=y
CONFIG_BLK_MQ_PCI=y
-CONFIG_CPU_HAS_DIEI=y
CONFIG_CPU_MIPSR2_IRQ_EI=y
CONFIG_CPU_MIPSR2_IRQ_VI=y
CONFIG_CPU_RMAP=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_FWNODE_MDIO=y
CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GPIO_CDEV=y
CONFIG_HW_RANDOM=y
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
# CONFIG_ISDN is not set
CONFIG_LANTIQ_ETOP=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
-CONFIG_MIPS_EBPF_JIT=y
CONFIG_MIPS_MT=y
CONFIG_MIPS_MT_FPAFF=y
CONFIG_MIPS_MT_SMP=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_SELFTESTS=y
CONFIG_NLS=y
CONFIG_NR_CPUS=2
CONFIG_PADATA=y
CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_LANTIQ=y
CONFIG_PSB6970_PHY=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_REGULATOR=y
CONFIG_SMP=y
CONFIG_SMP_UP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_TYPE_XWAY=y
-CONFIG_SOC_XWAY=y
CONFIG_SWCONFIG=y
CONFIG_SYNC_R4K=y
CONFIG_SYS_SUPPORTS_SCHED_SMT=y
--- /dev/null
+CONFIG_ADM6996_PHY=y
+CONFIG_AR8216_PHY=y
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_HW_RANDOM=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MIPS_MT=y
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_XWAY=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=2
+CONFIG_PADATA=y
+CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_PSB6970_PHY=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTL8306_PHY=y
+CONFIG_RTL8366RB_PHY=y
+CONFIG_RTL8366_SMI=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_SMT=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SWCONFIG=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
CONFIG_ADM6996_PHY=y
CONFIG_BLK_MQ_PCI=y
-CONFIG_CPU_HAS_DIEI=y
CONFIG_CRC16=y
-CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_GENERIC_ALLOCATOR=y
+# CONFIG_GPIO_CDEV is not set
# CONFIG_GPIO_SYSFS is not set
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_POLLDEV=y
# CONFIG_ISDN is not set
CONFIG_LANTIQ_ETOP=y
# CONFIG_LEDS_TRIGGER_TIMER is not set
CONFIG_LZO_DECOMPRESS=y
CONFIG_NLS=y
CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_LANTIQ=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_RTL8306_PHY=y
CONFIG_SGL_ALLOC=y
-CONFIG_SOC_TYPE_XWAY=y
-CONFIG_SOC_XWAY=y
CONFIG_SWCONFIG=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
--- /dev/null
+CONFIG_ADM6996_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_GENERIC_ALLOCATOR=y
+# CONFIG_GPIO_CDEV is not set
+# CONFIG_GPIO_SYSFS is not set
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_ISDN is not set
+CONFIG_LANTIQ_ETOP=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_NLS=y
+CONFIG_PCI=y
+# CONFIG_PCIE_LANTIQ is not set
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_LANTIQ=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RTL8306_PHY=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SWCONFIG=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2024 Weijie Gao <hackpascal@gmail.com>
+
+include $(TOPDIR)/rules.mk
+
+ARCH:=loongarch64
+BOARD:=loongarch64
+BOARDNAME:=Loongson LoongArch
+FEATURES:=audio display ext4 pcie boot-part rootfs-part rtc usb targz
+SUBTARGETS:=generic
+
+KERNEL_PATCHVER:=6.6
+
+KERNELNAME:=vmlinuz.efi dtbs
+
+include $(INCLUDE_DIR)/target.mk
+
+DEFAULT_PACKAGES += \
+ partx-utils blkid e2fsprogs grub2-efi-loongarch64
+
+$(eval $(call BuildTarget))
--- /dev/null
+GRUB_SERIAL:=$(call qstrip,$(CONFIG_TARGET_SERIAL))
+ifeq ($(GRUB_SERIAL),)
+$(error This platform requires CONFIG_TARGET_SERIAL be set!)
+endif
+
+define Package/base-files/install-target
+ $(SED) "s#@GRUB_SERIAL@#$(GRUB_SERIAL)#" $(1)/etc/inittab
+endef
--- /dev/null
+::sysinit:/etc/init.d/rcS S boot
+::shutdown:/etc/init.d/rcS K shutdown
+@GRUB_SERIAL@::askfirst:/usr/libexec/login.sh
+tty0::askfirst:/usr/libexec/login.sh
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+sanitize_name_loongarch64() {
+ sed -e '
+ y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/;
+ s/[^a-z0-9_-]\+/-/g;
+ s/^-//;
+ s/-$//;
+ ' "$@"
+}
+
+do_sysinfo_loongarch64() {
+ local vendor product file
+
+ for file in sys_vendor board_vendor; do
+ vendor="$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)"
+ case "$vendor" in
+ empty | \
+ System\ manufacturer | \
+ To\ [bB]e\ [fF]illed\ [bB]y\ O\.E\.M\.)
+ continue
+ ;;
+ esac
+ [ -n "$vendor" ] && break
+ done
+
+ for file in product_name board_name; do
+ product="$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)"
+ case "$vendor:$product" in
+ ?*:empty | \
+ ?*:System\ Product\ Name | \
+ ?*:To\ [bB]e\ [fF]illed\ [bB]y\ O\.E\.M\.)
+ continue
+ ;;
+ ?*:?*)
+ break
+ ;;
+ esac
+ done
+
+ [ -d "/sys/firmware/devicetree/base" ] && return
+
+ [ -n "$vendor" -a -n "$product" ] || return
+
+ mkdir -p /tmp/sysinfo
+
+ echo "$vendor $product" > /tmp/sysinfo/model
+
+ sanitize_name_loongarch64 /tmp/sysinfo/model > /tmp/sysinfo/board_name
+}
+
+boot_hook_add preinit_main do_sysinfo_loongarch64
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only
+
+move_config() {
+ local partdev parttype=ext4
+
+ . /lib/upgrade/common.sh
+
+ if export_bootdevice && export_partdevice partdev 1; then
+ part_magic_fat "/dev/$partdev" && parttype=vfat
+ if mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt; then
+ if [ -f "/mnt/$BACKUP_FILE" ]; then
+ mv -f "/mnt/$BACKUP_FILE" /
+ fi
+ umount /mnt
+ fi
+ fi
+}
+
+boot_hook_add preinit_mount_root move_config
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+RAMFS_COPY_BIN="/usr/sbin/blkid"
+
+platform_check_image() {
+ local board=$(board_name)
+ local diskdev partdev diff
+ [ "$#" -gt 1 ] && return 1
+
+ v "Board is ${board}"
+
+ export_bootdevice && export_partdevice diskdev 0 || {
+ v "platform_check_image: Unable to determine upgrade device"
+ return 1
+ }
+
+ get_partitions "/dev/$diskdev" bootdisk
+
+ v "Extract boot sector from the image"
+ get_image_dd "$1" of=/tmp/image.bs count=63 bs=512b
+
+ get_partitions /tmp/image.bs image
+
+ #compare tables
+ diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
+
+ rm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image
+
+ if [ -n "$diff" ]; then
+ v "Partition layout has changed. Full image will be written."
+ ask_bool 0 "Abort" && exit 1
+ return 0
+ fi
+}
+
+platform_copy_config() {
+ local partdev parttype=ext4
+
+ if export_partdevice partdev 1; then
+ part_magic_fat "/dev/$partdev" && parttype=vfat
+ mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt
+ cp -af "$UPGRADE_BACKUP" "/mnt/$BACKUP_FILE"
+ umount /mnt
+ else
+ v "ERROR: Unable to find partition to copy config data to"
+ fi
+
+ sleep 5
+}
+
+# To avoid writing over any firmware
+# files (e.g ubootefi.var or firmware/X/ aka EBBR)
+# Copy efi/openwrt and efi/boot from the new image
+# to the existing ESP
+platform_do_upgrade_efi_system_partition() {
+ local image_file=$1
+ local target_partdev=$2
+ local image_efisp_start=$3
+ local image_efisp_size=$4
+
+ v "Updating ESP on ${target_partdev}"
+ NEW_ESP_DIR="/mnt/new_esp_loop"
+ CUR_ESP_DIR="/mnt/cur_esp"
+ mkdir "${NEW_ESP_DIR}"
+ mkdir "${CUR_ESP_DIR}"
+
+ get_image_dd "$image_file" of="/tmp/new_efi_sys_part.img" \
+ skip="$image_efisp_start" count="$image_efisp_size"
+
+ mount -t vfat -o loop -o ro /tmp/new_efi_sys_part.img "${NEW_ESP_DIR}"
+ if [ ! -d "${NEW_ESP_DIR}/efi/boot" ]; then
+ v "ERROR: Image does not contain EFI boot files (/efi/boot)"
+ return 1
+ fi
+
+ mount -t vfat "/dev/$partdev" "${CUR_ESP_DIR}"
+
+ for d in $(find "${NEW_ESP_DIR}/efi/" -mindepth 1 -maxdepth 1 -type d); do
+ v "Copying ${d}"
+ newdir_bname=$(basename "${d}")
+ rm -rf "${CUR_ESP_DIR}/efi/${newdir_bname}"
+ cp -r "${d}" "${CUR_ESP_DIR}/efi"
+ v "rm -rf \"${CUR_ESP_DIR}/efi/${newdir_bname}\""
+ v "cp -r \"${d}\" \"${CUR_ESP_DIR}/efi\""
+ done
+
+ umount "${NEW_ESP_DIR}"
+ umount "${CUR_ESP_DIR}"
+}
+
+platform_do_upgrade() {
+ local board=$(board_name)
+ local diskdev partdev diff
+
+ export_bootdevice && export_partdevice diskdev 0 || {
+ v "platform_do_upgrade: Unable to determine upgrade device"
+ return 1
+ }
+
+ sync
+
+ if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
+ get_partitions "/dev/$diskdev" bootdisk
+
+ v "Extract boot sector from the image"
+ get_image_dd "$1" of=/tmp/image.bs count=63 bs=512b
+
+ get_partitions /tmp/image.bs image
+
+ #compare tables
+ diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
+ else
+ diff=1
+ fi
+
+ # Only change the partition table if sysupgrade -p is set,
+ # otherwise doing so could interfere with embedded "single storage"
+ # (e.g SoC boot from SD card) setups, as well as other user
+ # created storage (like uvol)
+ if [ -n "$diff" ] && [ "${UPGRADE_OPT_SAVE_PARTITIONS}" = "0" ]; then
+ # Need to remove partitions before dd, otherwise the partitions
+ # that are added after will have minor numbers offset
+ partx -d - "/dev/$diskdev"
+
+ get_image_dd "$1" of="/dev/$diskdev" bs=4096 conv=fsync
+
+ # Separate removal and addtion is necessary; otherwise, partition 1
+ # will be missing if it overlaps with the old partition 2
+ partx -a - "/dev/$diskdev"
+
+ return 0
+ fi
+
+ #iterate over each partition from the image and write it to the boot disk
+ while read part start size; do
+ if export_partdevice partdev $part; then
+ v "Writing image to /dev/$partdev..."
+ if [ "$part" = "1" ]; then
+ platform_do_upgrade_efi_system_partition \
+ $1 $partdev $start $size || return 1
+ else
+ v "Normal partition, doing DD"
+ get_image_dd "$1" of="/dev/$partdev" ibs=512 obs=1M skip="$start" \
+ count="$size" conv=fsync
+ fi
+ else
+ v "Unable to find partition $part device, skipped."
+ fi
+ done < /tmp/partmap.image
+
+ local parttype=ext4
+
+ if (blkid > /dev/null) && export_partdevice partdev 1; then
+ part_magic_fat "/dev/$partdev" && parttype=vfat
+ mount -t $parttype -o rw,noatime "/dev/$partdev" /mnt
+ if export_partdevice partdev 2; then
+ THIS_PART_BLKID=$(blkid -o value -s PARTUUID "/dev/${partdev}")
+ v "Setting rootfs PARTUUID=${THIS_PART_BLKID}"
+ sed -i "s/\(PARTUUID=\)[a-f0-9-]\+/\1${THIS_PART_BLKID}/ig" \
+ /mnt/efi/openwrt/grub.cfg
+ fi
+ umount /mnt
+ fi
+ # Provide time for the storage medium to flush before system reset
+ # (despite the sync/umount it appears NVMe etc. do it in the background)
+ sleep 5
+}
--- /dev/null
+# CONFIG_16KB_2LEVEL is not set
+CONFIG_16KB_3LEVEL=y
+# CONFIG_4KB_3LEVEL is not set
+# CONFIG_4KB_4LEVEL is not set
+CONFIG_64BIT=y
+# CONFIG_64KB_2LEVEL is not set
+# CONFIG_64KB_3LEVEL is not set
+CONFIG_AC97_BUS=y
+CONFIG_ACPI=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_BATTERY=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_CPU_FREQ_PSS=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+# CONFIG_ACPI_FFH is not set
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_MCFG=y
+# CONFIG_ACPI_PCI_SLOT is not set
+# CONFIG_ACPI_PFRUT is not set
+CONFIG_ACPI_PPTT=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_SLEEP=y
+# CONFIG_ACPI_SPCR_TABLE is not set
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+# CONFIG_ACPI_TAD is not set
+CONFIG_ACPI_THERMAL=y
+CONFIG_ACPI_VIDEO=y
+CONFIG_APERTURE_HELPERS=y
+CONFIG_ARCH_DISABLE_KASAN_INLINE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_ARCH_IOREMAP is not set
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS=12
+CONFIG_ARCH_MMAP_RND_BITS_MAX=18
+CONFIG_ARCH_MMAP_RND_BITS_MIN=12
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_STRICT_ALIGN=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+# CONFIG_ARCH_WRITECOMBINE is not set
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ATA=y
+CONFIG_ATA_ACPI=y
+CONFIG_ATA_FORCE=y
+# CONFIG_ATA_SFF is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_KTZ8866 is not set
+CONFIG_BLK_CGROUP=y
+CONFIG_BLK_CGROUP_IOCOST=y
+CONFIG_BLK_CGROUP_RWSTAT=y
+CONFIG_BLK_DEBUG_FS=y
+CONFIG_BLK_DEBUG_FS_ZONED=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_THROTTLING=y
+# CONFIG_BLK_DEV_THROTTLING_LOW is not set
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BLK_RQ_ALLOC_TIME=y
+CONFIG_BLK_SED_OPAL=y
+CONFIG_BLK_WBT=y
+CONFIG_BLK_WBT_MQ=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUG_ON_DATA_CORRUPTION=y
+CONFIG_CACHESTAT_SYSCALL=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CDROM=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_BPF is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_HUGETLB is not set
+# CONFIG_CGROUP_NET_CLASSID is not set
+# CONFIG_CGROUP_NET_PRIO is not set
+# CONFIG_CGROUP_PIDS is not set
+# CONFIG_CGROUP_RDMA is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMDLINE_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+# CONFIG_COMMON_CLK_LOONGSON2 is not set
+# CONFIG_COMMON_CLK_SI521XX is not set
+# CONFIG_COMMON_CLK_VC3 is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPUSETS=y
+CONFIG_CPU_HAS_FPU=y
+CONFIG_CPU_HAS_LASX=y
+CONFIG_CPU_HAS_LBT=y
+CONFIG_CPU_HAS_LSX=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRC64=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32_LOONGARCH is not set
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_DCB=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_COMPRESSED_NONE=y
+# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set
+# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set
+CONFIG_DEBUG_LIST=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_MISC=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_DEVMEM=y
+CONFIG_DEVTMPFS=y
+# CONFIG_DMAPOOL_TEST is not set
+CONFIG_DMA_CMA=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMI=y
+CONFIG_DMIID=y
+CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
+CONFIG_DMI_SYSFS=y
+CONFIG_DRM=y
+# CONFIG_DRM_ACCEL is not set
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_LOONGSON=y
+CONFIG_DRM_PANEL=y
+# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set
+# CONFIG_DRM_SAMSUNG_DSIM is not set
+CONFIG_DRM_TTM=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_COCO_SECRET is not set
+CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+CONFIG_EFI_ZBOOT=y
+CONFIG_ELF_CORE=y
+CONFIG_ENCRYPTED_KEYS=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_FAILOVER=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FANOTIFY=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
+CONFIG_FB_EFI=y
+CONFIG_FB_IOMEM_HELPERS=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FHANDLE=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FLATMEM_MANUAL is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_10x18 is not set
+# CONFIG_FONT_6x10 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_SUN8x16 is not set
+CONFIG_FONT_SUPPORT=y
+CONFIG_FONT_TER16x32=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FW_CACHE=y
+# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_ENTRY=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIO_ACPI=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
+# CONFIG_GPIO_DS4520 is not set
+# CONFIG_GPIO_FXL6408 is not set
+# CONFIG_GPIO_LATCH is not set
+# CONFIG_GPIO_LOONGSON_64BIT is not set
+CONFIG_HAMRADIO=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HDMI=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_AMD_MP2 is not set
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_LS2X is not set
+CONFIG_INITRAMFS_PRESERVE_MTIME=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INIT_STACK_ALL_ZERO=y
+# CONFIG_INIT_STACK_NONE is not set
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+# CONFIG_INPUT_MISC is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_SPARSEKMAP=y
+# CONFIG_IOMMUFD is not set
+# CONFIG_IOMMU_DEBUGFS is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IO_URING=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_LOONGARCH_CPU=y
+CONFIG_IRQ_POLL=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISCSI_IBFT is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JBD2=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_SELFTEST is not set
+CONFIG_KCMP=y
+CONFIG_KEYS=y
+CONFIG_KSM=y
+CONFIG_L1_CACHE_SHIFT=6
+# CONFIG_LEDS_AW200XX is not set
+# CONFIG_LEDS_BD2606MVV is not set
+# CONFIG_LEDS_GROUP_MULTICOLOR is not set
+# CONFIG_LEDS_LM3697 is not set
+# CONFIG_LEDS_PCA995X is not set
+CONFIG_LEDS_TRIGGER_AUDIO=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_MTD=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEGACY_TIOCSTI=y
+CONFIG_LIBFDT=y
+CONFIG_LIST_HARDENED=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOONGARCH=y
+CONFIG_LOONGARCH_PLATFORM_DEVICES=y
+# CONFIG_LOONGSON2_GUTS is not set
+# CONFIG_LOONGSON2_PM is not set
+# CONFIG_LOONGSON2_THERMAL is not set
+CONFIG_LOONGSON_EIOINTC=y
+CONFIG_LOONGSON_HTVEC=y
+CONFIG_LOONGSON_LAPTOP=y
+CONFIG_LOONGSON_LIOINTC=y
+CONFIG_LOONGSON_PCH_LPC=y
+CONFIG_LOONGSON_PCH_MSI=y
+CONFIG_LOONGSON_PCH_PIC=y
+CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,apparmor,selinux,smack,tomoyo,bpf"
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACH_LOONGSON64=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01b6
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+# CONFIG_MAX31827 is not set
+CONFIG_MAX_SKB_FRAGS=17
+# CONFIG_MEMCG is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+# CONFIG_MFD_CS42L43_I2C is not set
+# CONFIG_MFD_INTEL_M10_BMC_SPI is not set
+# CONFIG_MFD_MAX5970 is not set
+# CONFIG_MFD_MAX77541 is not set
+# CONFIG_MFD_RK8XX_I2C is not set
+# CONFIG_MFD_RK8XX_SPI is not set
+# CONFIG_MFD_SMPRO is not set
+# CONFIG_MFD_TPS65219 is not set
+# CONFIG_MFD_TPS6594_I2C is not set
+# CONFIG_MFD_TPS6594_SPI is not set
+CONFIG_MIGRATION=y
+CONFIG_MMU_GATHER_MERGE_VMAS=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_RELA=y
+# CONFIG_MODULE_DEBUG is not set
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOXA_INTELLIO is not set
+# CONFIG_MOXA_SMARTIO is not set
+CONFIG_MPILIB=y
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=64
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVME_CORE=y
+CONFIG_NVME_HWMON=y
+CONFIG_NVME_MULTIPATH=y
+CONFIG_NVME_VERBOSE_ERRORS=y
+# CONFIG_N_HDLC is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OID_REGISTRY=y
+# CONFIG_OVERLAY_FS_DEBUG is not set
+CONFIG_PADATA=y
+CONFIG_PAGE_EXTENSION=y
+CONFIG_PAGE_POISONING=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PATA_TIMINGS=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DPC=y
+# CONFIG_PCIE_EDR is not set
+CONFIG_PCIE_PME=y
+CONFIG_PCIE_PTM=y
+CONFIG_PCI_ATS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+# CONFIG_PCI_DYNAMIC_OF_NODES is not set
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_LOONGSON=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_ARCH_FALLBACKS=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCPU_DEV_REFCNT=y
+# CONFIG_PDS_CORE is not set
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_3LEVEL=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PM=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_DEBUG=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_STD_PARTITION=""
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+# CONFIG_PNP_DEBUG_MESSAGES is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PPS=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_PREEMPT_VOLUNTARY_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_PTP_1588_CLOCK=y
+# CONFIG_PTP_1588_CLOCK_MOCK is not set
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+# CONFIG_RANDOM_KMALLOC_CACHES is not set
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+# CONFIG_RCU_CPU_STALL_CPUTIME is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_RELAY=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_ATTACK_MITIGATION=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_EFI is not set
+CONFIG_RTC_DRV_LOONGSON=y
+CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_HOST=y
+# CONFIG_SATA_ZPODD is not set
+CONFIG_SCHEDSTATS=y
+CONFIG_SCHED_AUTOGROUP=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MM_CID=y
+CONFIG_SCHED_SMT=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SENSORS_HS3001 is not set
+# CONFIG_SENSORS_MC34VR500 is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+# CONFIG_SERIAL_8250_PCI1XXXX is not set
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PERICOM=y
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+# CONFIG_SLAB_DEPRECATED is not set
+# CONFIG_SLUB_TINY is not set
+CONFIG_SMP=y
+CONFIG_SND=y
+CONFIG_SND_AC97_CODEC=y
+CONFIG_SND_COMPRESS_OFFLOAD=y
+CONFIG_SND_CTL_LED=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_HDA=y
+# CONFIG_SND_HDA_CODEC_ANALOG is not set
+# CONFIG_SND_HDA_CODEC_CA0110 is not set
+# CONFIG_SND_HDA_CODEC_CA0132 is not set
+# CONFIG_SND_HDA_CODEC_CIRRUS is not set
+# CONFIG_SND_HDA_CODEC_CMEDIA is not set
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_HDMI=y
+# CONFIG_SND_HDA_CODEC_REALTEK is not set
+# CONFIG_SND_HDA_CODEC_SI3054 is not set
+# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
+# CONFIG_SND_HDA_CODEC_VIA is not set
+CONFIG_SND_HDA_CORE=y
+# CONFIG_SND_HDA_CTL_DEV_ID is not set
+CONFIG_SND_HDA_GENERIC=y
+CONFIG_SND_HDA_GENERIC_LEDS=y
+CONFIG_SND_HDA_HWDEP=y
+# CONFIG_SND_HDA_INPUT_BEEP is not set
+CONFIG_SND_HDA_INTEL=y
+# CONFIG_SND_HDA_PATCH_LOADER is not set
+# CONFIG_SND_HDA_RECONFIG is not set
+# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
+# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
+# CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set
+# CONFIG_SND_HDA_SCODEC_CS35L56_SPI is not set
+# CONFIG_SND_HDA_SCODEC_TAS2781_I2C is not set
+CONFIG_SND_HWDEP=y
+CONFIG_SND_INTEL_DSP_CONFIG=y
+CONFIG_SND_INTEL_NHLT=y
+CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SEQ_DEVICE=y
+CONFIG_SND_SEQ_DUMMY=y
+CONFIG_SND_SEQ_MIDI=y
+CONFIG_SND_SEQ_MIDI_EVENT=y
+CONFIG_SND_SEQ_VIRMIDI=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AC97_CODEC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_LOONGSON_CARD=y
+CONFIG_SND_SOC_LOONGSON_I2S_PCI=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_VIRMIDI=y
+CONFIG_SND_VMASTER=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_LOONGSON_CORE=y
+CONFIG_SPI_LOONGSON_PCI=y
+CONFIG_SPI_LOONGSON_PLATFORM=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_PCI1XXXX is not set
+# CONFIG_SPI_SN_F_OSPI is not set
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKTRACE=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+# CONFIG_SWIOTLB_DYNAMIC is not set
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_ARCH_UNALIGN_ALLOW=y
+CONFIG_SYSCTL_ARCH_UNALIGN_NO_WARN=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFB=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASK_XACCT=y
+# CONFIG_TEST_DHRY is not set
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_BANG_BANG=y
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TMPFS_INODE64=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TMPFS_QUOTA is not set
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UCS2_STRING=y
+# CONFIG_UEVENT_HELPER is not set
+# CONFIG_UNWINDER_GUESS is not set
+CONFIG_UNWINDER_PROLOGUE=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_HID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+# CONFIG_USB_OHCI_HCD_PLATFORM is not set
+CONFIG_USB_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_UAS=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_USERFAULTFD=y
+CONFIG_USER_STACKTRACE_SUPPORT=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+# CONFIG_VCAP is not set
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VGA_CONSOLE=y
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VIRTIO_VSOCKETS_COMMON=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VSOCKETS=y
+CONFIG_VSOCKETS_LOOPBACK=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_WPCM450_SOC is not set
+# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set
+CONFIG_XARRAY_MULTI=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+# CONFIG_ZONEFS_FS is not set
+CONFIG_ZONE_DMA32=y
--- /dev/null
+BOARDNAME:=Generic
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2024 Weijie Gao <hackpascal@gmail.com>
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+GRUB2_VARIANT =
+GRUB_TERMINALS =
+GRUB_SERIAL_CONFIG =
+GRUB_TERMINAL_CONFIG =
+GRUB_CONSOLE_CMDLINE =
+
+ifneq ($(CONFIG_GRUB_CONSOLE),)
+ GRUB_CONSOLE_CMDLINE += console=tty0
+ GRUB_TERMINALS += console
+endif
+
+GRUB_SERIAL:=$(call qstrip,$(CONFIG_TARGET_SERIAL))
+
+GRUB_CONSOLE_CMDLINE += console=$(GRUB_SERIAL),$(CONFIG_GRUB_BAUDRATE)n8$(if $(CONFIG_GRUB_FLOWCONTROL),r,)
+GRUB_SERIAL_CONFIG := serial --unit=0 --speed=$(CONFIG_GRUB_BAUDRATE) --word=8 --parity=no --stop=1 --rtscts=$(if $(CONFIG_GRUB_FLOWCONTROL),on,off)
+GRUB_TERMINALS += serial
+
+GRUB_TERMINAL_CONFIG := terminal_input $(GRUB_TERMINALS); terminal_output $(GRUB_TERMINALS)
+
+ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME))
+ROOTPART:=$(if $(ROOTPART),$(ROOTPART),PARTUUID=$(IMG_PART_SIGNATURE)-02)
+GPT_ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME))
+GPT_ROOTPART:=$(if $(GPT_ROOTPART),$(GPT_ROOTPART),PARTUUID=$(shell echo $(IMG_PART_DISKGUID) | sed 's/00$$/02/'))
+
+GRUB_TIMEOUT:=$(call qstrip,$(CONFIG_GRUB_TIMEOUT))
+GRUB_TITLE:=$(call qstrip,$(CONFIG_GRUB_TITLE))
+
+BOOTOPTS:=$(call qstrip,$(CONFIG_GRUB_BOOTOPTS))
+
+define Build/combined
+ $(INSTALL_DIR) $@.boot/
+ $(CP) $(KDIR)/$(KERNEL_NAME) $@.boot/efi/openwrt/
+ $(INSTALL_DIR) $@.boot/efi/boot
+ $(CP) $(STAGING_DIR_IMAGE)/grub2/bootloongarch64.efi $@.boot/efi/boot/
+ KERNELPARTTYPE=ef FAT_TYPE="32" PADDING="1" SIGNATURE="$(IMG_PART_SIGNATURE)" \
+ GUID="$(IMG_PART_DISKGUID)" $(SCRIPT_DIR)/gen_image_generic.sh \
+ $@ \
+ $(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
+ $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
+ 256
+endef
+
+define Build/grub-config
+ rm -fR $@.boot
+ $(INSTALL_DIR) $@.boot/efi/openwrt/
+ sed \
+ -e 's#@SERIAL_CONFIG@#$(strip $(GRUB_SERIAL_CONFIG))#g' \
+ -e 's#@TERMINAL_CONFIG@#$(strip $(GRUB_TERMINAL_CONFIG))#g' \
+ -e 's#@ROOTPART@#root=$(ROOTPART) rootwait#g' \
+ -e 's#@GPT_ROOTPART@#root=$(GPT_ROOTPART) rootwait#g' \
+ -e 's#@CMDLINE@#$(BOOTOPTS) $(GRUB_CONSOLE_CMDLINE)#g' \
+ -e 's#@TIMEOUT@#$(GRUB_TIMEOUT)#g' \
+ -e 's#@TITLE@#$(GRUB_TITLE)#g' \
+ -e 's#@KERNEL_NAME@#$(KERNEL_NAME)#g' \
+ ./grub-$(1).cfg > $@.boot/efi/openwrt/grub.cfg
+endef
+
+define Device/Default
+ KERNEL_INSTALL := 1
+ ARTIFACTS := $$(ARTIFACTS-y)
+ SUPPORTED_DEVICES :=
+endef
+
+define Device/generic
+ DEVICE_VENDOR := Generic
+ DEVICE_MODEL := LoongArch64
+ DEVICE_PACKAGES += kmod-r8169 kmod-drm-amdgpu
+ KERNEL := kernel-bin
+ KERNEL_NAME := vmlinuz.efi
+ IMAGE/rootfs.img := append-rootfs | pad-to $(ROOTFS_PARTSIZE)
+ IMAGE/rootfs.img.gz := append-rootfs | pad-to $(ROOTFS_PARTSIZE) | gzip
+ IMAGE/combined-efi.img := grub-config efi | combined | append-metadata
+ IMAGE/combined-efi.img.gz := grub-config efi | combined | gzip | append-metadata
+ ifeq ($(CONFIG_TARGET_IMAGES_GZIP),y)
+ IMAGES-y := rootfs.img.gz
+ IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.img.gz
+ else
+ IMAGES-y := rootfs.img
+ IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.img
+ endif
+ IMAGES := $$(IMAGES-y)
+endef
+TARGET_DEVICES += generic
+
+$(eval $(call BuildImage))
--- /dev/null
+@SERIAL_CONFIG@
+@TERMINAL_CONFIG@
+
+set default="0"
+set timeout="@TIMEOUT@"
+
+menuentry "@TITLE@" {
+ search --set=root --label kernel
+ linux /efi/openwrt/@KERNEL_NAME@ @GPT_ROOTPART@ @CMDLINE@ noinitrd
+}
+menuentry "@TITLE@ (failsafe)" {
+ search --set=root --label kernel
+ linux /efi/openwrt/@KERNEL_NAME@ failsafe=true @GPT_ROOTPART@ @CMDLINE@ noinitrd
+}
FEATURES:=cpiogz ext4 ramdisk squashfs targz
KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
--- /dev/null
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ATA=y
+CONFIG_ATA_PIIX=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOARD_SCACHE=y
+CONFIG_BOOT_ELF32=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUILTIN_DTB=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKBLD_I8253=y
+CONFIG_CLKEVT_I8253=y
+CONFIG_CLKSRC_I8253=y
+CONFIG_CLKSRC_MIPS_GIC=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_CPU_HAS_SMARTMIPS is not set
+CONFIG_CPU_HAS_SYNC=y
+# CONFIG_CPU_MICROMIPS is not set
+# CONFIG_CPU_MIPS32 is not set
+# CONFIG_CPU_MIPS32_3_5_FEATURES is not set
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS32_R5 is not set
+# CONFIG_CPU_MIPS32_R5_FEATURES is not set
+# CONFIG_CPU_MIPS32_R6 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_MIPS64_R6 is not set
+# CONFIG_CPU_MIPSR1 is not set
+# CONFIG_CPU_MIPSR2 is not set
+# CONFIG_CPU_MIPSR2_IRQ_EI is not set
+# CONFIG_CPU_MIPSR2_IRQ_VI is not set
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+# CONFIG_CPU_NEVADA is not set
+CONFIG_CPU_R4K_CACHE_TLB=y
+# CONFIG_CPU_RM7000 is not set
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_F2FS_FS=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIO_CDEV=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_I8253=y
+CONFIG_I8253_LOCK=y
+CONFIG_I8259=y
+CONFIG_INPUT=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_ISA_DMA_API=y
+CONFIG_JBD2=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_KALLSYMS=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MD=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_BONITO64=y
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+CONFIG_MIPS_CM=y
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_MIPS_CPC=y
+CONFIG_MIPS_CPU_SCACHE=y
+CONFIG_MIPS_EXTERNAL_TIMER=y
+CONFIG_MIPS_GIC=y
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+CONFIG_MIPS_L1_CACHE_SHIFT_6=y
+CONFIG_MIPS_MALTA=y
+CONFIG_MIPS_MSC=y
+CONFIG_MIPS_MT=y
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NO_APPENDED_DTB=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MTD_CFI_STAA=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PATA_LEGACY=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PCI_GT64XXX_PCI0=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QFMT_V2=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_QUOTA_TREE=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_SATA_HOST=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y
+CONFIG_SYS_HAS_CPU_MIPS32_R5=y
+CONFIG_SYS_HAS_CPU_MIPS32_R6=y
+CONFIG_SYS_HAS_CPU_MIPS64_R1=y
+CONFIG_SYS_HAS_CPU_MIPS64_R2=y
+CONFIG_SYS_HAS_CPU_MIPS64_R6=y
+CONFIG_SYS_HAS_CPU_NEVADA=y
+CONFIG_SYS_HAS_CPU_RM7000=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MICROMIPS=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_MIPS_CPS=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_RELOCATABLE=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMARTMIPS=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_SYS_SUPPORTS_VPE_LOADER=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=1
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_VXFS_FS=y
+CONFIG_WAR_ICACHE_REFILLS=y
+CONFIG_XPS=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
SUBTARGETS:=mt7622 mt7623 mt7629 filogic
FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += \
fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)"
;;
bananapi,bpi-r3|\
-bananapi,bpi-r3-mini)
+bananapi,bpi-r3-mini|\
+bananapi,bpi-r4|\
+bananapi,bpi-r4-poe)
[ -z "$(fw_printenv -n ethaddr 2>/dev/null)" ] &&
fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)"
[ -z "$(fw_printenv -n eth1addr 2>/dev/null)" ] &&
set_preinit_iface() {
case $(board_name) in
- smartrg,sdg-8622|\
- smartrg,sdg-8632)
- ip link set lan up
- ifname=lan
- ;;
+ cudy,m3000-v1|\
+ cudy,tr3000-v1|\
glinet,gl-mt3000)
ip link set eth1 up
ifname=eth1
ip link set eth0 up
ifname=eth0
;;
+ smartrg,sdg-8622|\
+ smartrg,sdg-8632)
+ ip link set lan up
+ ifname=lan
+ ;;
xiaomi,mi-router-ax3000t|\
xiaomi,mi-router-ax3000t-ubootmod|\
xiaomi,mi-router-wr30u-stock|\
&mdio {
switch@1f {
compatible = "mediatek,mt7531";
- reg = <0x1f>;
+ reg = <31>;
reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
- switch: switch@0 {
+ switch: switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch@1f {
compatible = "mediatek,mt7531";
+ reg = <31>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&pio>;
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0>;
reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
#address-cells = <1>;
#size-cells = <0>;
- mt7530: switch@0 {
- compatible = "mediatek,mt7530";
+ mt7530: switch@1f {
};
};
};
&mt7530 {
compatible = "mediatek,mt7530";
+ reg = <31>;
#address-cells = <1>;
#size-cells = <0>;
- reg = <0>;
pinctrl-names = "default";
mediatek,mcm;
resets = <ðsys 2>;
reg = <0>;
};
- switch@2 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <2>;
+ reg = <31>;
reset-gpios = <&pio 28 0>;
interrupt-controller;
#interrupt-cells = <1>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "mt7981.dtsi"
+
+/ {
+ model = "Edgecore EAP111";
+ compatible = "edgecore,eap111", "mediatek,mt7981";
+
+ aliases {
+ serial0 = &uart0;
+ led-boot = &led_green;
+ led-failsafe = &led_green;
+ led-running = &led_green;
+ led-upgrade = &led_green;
+ };
+
+ chosen {
+ bootargs-override = "console=ttyS0,115200n8";
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_green: led-green {
+ gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led_orange: led-orange {
+ gpios = <&pio 34 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_ORANGE>;
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led_blue: led-blue {
+ gpios = <&pio 35 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_INDICATOR;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&pio {
+ spi0_flash_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ cs-gpios = <0>, <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+
+ spi-cal-enable;
+ spi-cal-mode = "read-data";
+ spi-cal-datalen = <7>;
+ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
+ spi-cal-addrlen = <5>;
+ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
+
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ mediatek,nmbm;
+ mediatek,bmt-max-ratio = <1>;
+ mediatek,bmt-max-reserved-blocks = <64>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "BL2";
+ reg = <0x00000 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u-boot-env";
+ reg = <0x100000 0x80000>;
+ };
+
+ partition@180000 {
+ label = "Factory";
+ reg = <0x180000 0x200000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory: eeprom@0 {
+ reg = <0x0 0x1000>;
+ };
+
+ macaddr_wan: macaddr@2a {
+ reg = <0x2a 0x6>;
+ };
+
+ macaddr_lan: macaddr@24 {
+ reg = <0x24 0x6>;
+ };
+ };
+ };
+
+ partition@380000 {
+ label = "FIP";
+ reg = <0x380000 0x200000>;
+ read-only;
+ };
+
+ partition@580000 {
+ label = "ubi";
+ reg = <0x580000 0x4000000>;
+ compatible = "linux,ubi";
+ };
+ };
+ };
+};
+
+&mdio_bus {
+ reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <10000>;
+ reset-post-delay-us = <10000>;
+
+ en8801sc: ethernet-phy@24 {
+ reg = <24>;
+ compatible = "ethernet-phy-id03a2.9471";
+ phy-mode = "sgmii";
+ };
+};
+
+ð {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "sgmii";
+ phy-handle = <&en8801sc>;
+ managed = "in-band-status";
+ nvmem-cells = <&macaddr_lan>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "gmii";
+ phy-handle = <&int_gbe_phy>;
+ nvmem-cells = <&macaddr_wan>;
+ nvmem-cell-names = "mac-address";
+ };
+};
+
+&wifi {
+ nvmem-cells = <&eeprom_factory>;
+ nvmem-cell-names = "eeprom";
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "mt7981.dtsi"
+
+/ {
+ model = "Cudy M3000 v1";
+ compatible = "cudy,m3000-v1", "mediatek,mt7981-spim-snand-rfb";
+
+ aliases {
+ ethernet0 = &gmac0;
+ label-mac-device = &gmac0;
+ led-boot = &led_status;
+ led-failsafe = &led_status;
+ led-running = &led_status;
+ led-upgrade = &led_status;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status: internet-white {
+ function = LED_FUNCTION_WAN_ONLINE;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+
+ internet-red {
+ function = LED_FUNCTION_WAN_ONLINE;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 4 GPIO_ACTIVE_LOW>;
+ };
+
+ wan {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+ };
+
+ lan {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+ð {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+ phy-handle = <&rtl8221b_phy>;
+
+ /* the MAC address assignment using nvmem-cells doesn't work, so it's done through 02_network */
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "gmii";
+ phy-handle = <&int_gbe_phy>;
+
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_bdinfo_de00 0>;
+ };
+};
+
+&mdio_bus {
+ rtl8221b_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <1>;
+
+ reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+
+ interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
+ reset-assert-us = <100000>;
+ reset-deassert-us = <100000>;
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+
+ status = "okay";
+
+ spi_nand: spi_nand@0 {
+ compatible = "spi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+
+ spi-max-frequency = <52000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mediatek,nmbm;
+ mediatek,bmt-max-ratio = <1>;
+ mediatek,bmt-max-reserved-blocks = <64>;
+
+ partition@0 {
+ label = "BL2";
+ reg = <0x0000000 0x0100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u-boot-env";
+ reg = <0x0100000 0x0080000>;
+ };
+
+ factory: partition@180000 {
+ label = "Factory";
+ reg = <0x0180000 0x0200000>;
+ read-only;
+ };
+
+ bdinfo: partition@380000 {
+ label = "bdinfo";
+ reg = <0x0380000 0x0040000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_bdinfo_de00: macaddr@de00 {
+ #nvmem-cell-cells = <1>;
+ compatible = "mac-base";
+ reg = <0xde00 0x6>;
+ };
+ };
+ };
+
+ partition@3c0000 {
+ label = "FIP";
+ reg = <0x03c0000 0x0200000>;
+ };
+
+ partition@5c0000 {
+ label = "ubi";
+ reg = <0x05c0000 0x4000000>;
+ };
+ };
+ };
+};
+
+&pio {
+ spi0_flash_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+
+ conf-pu {
+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
+ };
+};
+
+&wifi {
+ status = "okay";
+ mediatek,mtd-eeprom = <&factory 0x0>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+
+#include "mt7981.dtsi"
+
+/ {
+ model = "Cudy TR3000 v1";
+ compatible = "cudy,tr3000-v1", "mediatek,mt7981-spim-snand-rfb";
+
+ aliases {
+ label-mac-device = &gmac1;
+ led-boot = &led_status;
+ led-failsafe = &led_status;
+ led-running = &led_status;
+ led-upgrade = &led_status;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ mode {
+ label = "mode";
+ linux,input-type = <EV_SW>;
+ linux,code = <BTN_0>;
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+ debounce-interval = <60>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status: led_0 {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+ };
+
+ led_1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+ };
+
+ };
+
+ usb_vbus: regulator-usb {
+ compatible = "regulator-fixed";
+
+ regulator-name = "usb-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&pio 9 GPIO_ACTIVE_LOW>;
+ regulator-boot-on;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+ð {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+ phy-handle = <&phy1>;
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_bdinfo_de00 1>;
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "gmii";
+ phy-handle = <&int_gbe_phy>;
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_bdinfo_de00 0>;
+ };
+};
+
+&mdio_bus {
+ phy1: phy@1 {
+ reg = <1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ phy-mode = "2500base-x";
+ reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+ interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
+ reset-assert-us = <100000>;
+ reset-deassert-us = <100000>;
+ realtek,aldps-enable;
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ status = "okay";
+
+ spi_nand: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+
+ spi-cal-enable;
+ spi-cal-mode = "read-data";
+ spi-cal-datalen = <7>;
+ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
+ spi-cal-addrlen = <5>;
+ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
+
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ mediatek,nmbm;
+ mediatek,bmt-max-ratio = <1>;
+ mediatek,bmt-max-reserved-blocks = <64>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "BL2";
+ reg = <0x00000 0x0100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u-boot-env";
+ reg = <0x0100000 0x0080000>;
+ read-only;
+ };
+
+ factory: partition@180000 {
+ label = "Factory";
+ reg = <0x180000 0x0200000>;
+ read-only;
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory_0: eeprom@0 {
+ reg = <0x0 0x1000>;
+ };
+ };
+ };
+
+ partition@380000 {
+ label = "bdinfo";
+ reg = <0x380000 0x0040000>;
+ read-only;
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_bdinfo_de00: macaddr@de00 {
+ compatible = "mac-base";
+ reg = <0xde00 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+
+ };
+
+ partition@3C0000 {
+ label = "FIP";
+ reg = <0x3C0000 0x0200000>;
+ read-only;
+ };
+
+ partition@580000 {
+ label = "ubi";
+ reg = <0x5C0000 0x4000000>;
+ compatible = "linux,ubi";
+ };
+ };
+ };
+};
+
+
+&pio {
+ spi0_flash_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&xhci {
+ status = "okay";
+ vbus-supply = <&usb_vbus>;
+};
+
+&wifi {
+ status = "okay";
+ nvmem-cells = <&eeprom_factory_0>;
+ nvmem-cell-names = "eeprom";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+#include "mt7981.dtsi"
+
+/ {
+ model = "OpenWrt One";
+ compatible = "openwrt,one", "mediatek,mt7981";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ serial0 = &uart0;
+ led-boot = &led_status_white;
+ led-failsafe = &led_status_red;
+ led-running = &led_status_green;
+ led-upgrade = &led_status_green;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ rootdisk = <&ubi_fit_volume>;
+ };
+
+ memory {
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user {
+ label = "user";
+ linux,code = <BTN_0>;
+ gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led_status_white: led-0 {
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_STATUS;
+ pwms = <&pwm 0 10000>;
+ linux,default-trigger = "pattern";
+ led-pattern = <0 500 25 500>;
+ };
+
+ led_status_green: led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ pwms = <&pwm 1 10000>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led_status_red: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&pio 34 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 35 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-export {
+ compatible = "gpio-export";
+
+ gpio-0 {
+ gpio-export,name = "mikrobus-reset";
+ gpio-export,output = <1>;
+ gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-1 {
+ gpio-export,name = "watchdog-enable";
+ gpio-export,output = <1>;
+ gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-2 {
+ gpio-export,name = "usb-enable";
+ gpio-export,output = <1>;
+ gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-watchdog {
+ compatible = "linux,wdt-gpio";
+ gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+ hw_algo = "toggle";
+ hw_margin_ms = <25000>;
+ always-running;
+ };
+};
+
+ð {
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-handle = <&phy15>;
+ phy-mode = "2500base-x";
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_factory_4>;
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "gmii";
+ phy-handle = <&int_gbe_phy>;
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_factory_a>;
+ };
+};
+
+&mdio_bus {
+ phy15: phy@f {
+ reg = <0xf>;
+
+ airoha,pnswap-rx;
+
+ interrupt-parent = <&pio>;
+ interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <20000>;
+
+ phy-mode = "2500base-x";
+ full-duplex;
+ pause;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ };
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+&pio {
+ spi0_flash_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+
+ conf-pu {
+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
+ };
+
+ spi1_flash_pins: spi1-pins {
+ mux {
+ function = "spi";
+ groups = "spi1_1";
+ };
+
+ conf-pu {
+ pins = "SPI1_CS";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
+ };
+
+ spi2_flash_pins: spi2-pins {
+ mux {
+ function = "spi";
+ groups = "spi2";
+ };
+
+ conf-pu {
+ pins = "SPI2_CS", "SPI2_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
+ };
+
+ i2c_pins: i2c-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c0_0";
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_0_tx_rx";
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0_0", "pwm1_1";
+ };
+ };
+
+ pcie_pins: pcie-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_pereset";
+ };
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_pins>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ cs-gpios = <0>, <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <52000000>;
+
+ spi-cal-enable;
+ spi-cal-mode = "read-data";
+ spi-cal-datalen = <7>;
+ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
+ spi-cal-addrlen = <5>;
+ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@580000 {
+ label = "ubi";
+ reg = <0x100000 0x7F00000>;
+ compatible = "linux,ubi";
+
+ volumes {
+ ubi_fit_volume: ubi-volume-fit {
+ volname = "fit";
+ };
+ };
+ };
+ };
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_flash_pins>;
+ status = "okay";
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_flash_pins>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ spi-max-frequency = <52000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2-nor";
+ reg = <0x00000 0x40000>;
+ };
+
+ partition@40000 {
+ label = "factory";
+ reg = <0x40000 0xc0000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory_0: eeprom@0 {
+ reg = <0x0 0x1000>;
+ };
+
+ macaddr_factory_4: macaddr@4 {
+ compatible = "mac-base";
+ reg = <0x24 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ macaddr_factory_a: macaddr@a {
+ compatible = "mac-base";
+ reg = <0x2a 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ partition@100000 {
+ label = "fip-nor";
+ reg = <0x100000 0x80000>;
+ };
+
+ partition@180000 {
+ label = "recovery";
+ reg = <0x180000 0xc80000>;
+ };
+ };
+ };
+};
+
+&xhci {
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ vusb33-supply = <®_3p3v>;
+ vbus-supply = <®_5v>;
+ mediatek,u3p-dis-msk = <0x01>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&wifi {
+ nvmem-cells = <&eeprom_factory_0>;
+ nvmem-cell-names = "eeprom";
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
+};
+
+&sgmiisys0 {
+ /delete-node/ mediatek,pnswap;
+};
&mdio_bus {
switch: switch@1f {
compatible = "mediatek,mt7531";
- reg = <0x1f>;
+ reg = <31>;
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
port@0 {
reg = <0>;
label = "game";
+ phy-handle = <&swphy0>;
};
port@1 {
reg = <1>;
label = "lan1";
+ phy-handle = <&swphy1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-handle = <&swphy2>;
};
port@3 {
reg = <3>;
label = "lan3";
+ phy-handle = <&swphy3>;
};
port@6 {
#address-cells = <1>;
#size-cells = <0>;
- phy@0 {
+ swphy0: phy@0 {
reg = <0>;
mediatek,led-config = <
>;
};
- phy@1 {
+ swphy1: phy@1 {
reg = <1>;
mediatek,led-config = <
>;
};
- phy@2 {
+ swphy2: phy@2 {
reg = <2>;
mediatek,led-config = <
>;
};
- phy@3 {
+ swphy3: phy@3 {
reg = <3>;
mediatek,led-config = <
port@1 {
reg = <1>;
label = "lan1";
+ phy-handle = <&swphy1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-handle = <&swphy2>;
};
port@3 {
reg = <3>;
label = "lan3";
+ phy-handle = <&swphy3>;
};
port@4 {
reg = <4>;
label = "lan4";
+ phy-handle = <&swphy4>;
};
port@6 {
#address-cells = <1>;
#size-cells = <0>;
- phy@1 {
+ swphy1: phy@1 {
reg = <1>;
mediatek,led-config = <
>;
};
- phy@2 {
+ swphy2: phy@2 {
reg = <2>;
mediatek,led-config = <
>;
};
- phy@3 {
+ swphy3: phy@3 {
reg = <3>;
mediatek,led-config = <
>;
};
- phy@4 {
+ swphy4: phy@4 {
reg = <4>;
mediatek,led-config = <
#size-cells = <0>;
port@1 {
- reg = <4>;
- label = "lan1";
+ reg = <1>;
+ label = "lan4";
+ phy-handle = <&swphy1>;
};
port@2 {
- reg = <3>;
- label = "lan2";
+ reg = <2>;
+ label = "lan3";
+ phy-handle = <&swphy2>;
};
port@3 {
- reg = <2>;
- label = "lan3";
+ reg = <3>;
+ label = "lan2";
+ phy-handle = <&swphy3>;
};
port@4 {
- reg = <1>;
- label = "lan4";
+ reg = <4>;
+ label = "lan1";
+ phy-handle = <&swphy4>;
};
port@5 {
#address-cells = <1>;
#size-cells = <0>;
- phy@1 {
+ swphy1: phy@1 {
reg = <1>;
mediatek,led-config = <
>;
};
- phy@2 {
+ swphy2: phy@2 {
reg = <2>;
mediatek,led-config = <
>;
};
- phy@3 {
+ swphy3: phy@3 {
reg = <3>;
mediatek,led-config = <
>;
};
- phy@4 {
+ swphy4: phy@4 {
reg = <4>;
mediatek,led-config = <
};
chosen {
+ bootargs-override = "root=/dev/fit0 rootwait";
stdout-path = "serial0:115200n8";
+ rootdisk = <&emmc_rootdisk>;
};
memory@40000000 {
vmmc-supply = <®_3p3v>;
vqmmc-supply = <®_1p8v>;
status = "okay";
+
+ card@0 {
+ compatible = "mmc-card";
+ reg = <0>;
+
+ block {
+ compatible = "block-device";
+ partitions {
+ emmc_rootdisk: block-partition-production {
+ partname = "production";
+ };
+ };
+ };
+ };
};
&pio {
};
chosen {
+ bootargs = "root=/dev/fit0 rootwait";
+ rootdisk = <&ubi_rootdisk>;
stdout-path = "serial0:115200n8";
};
};
partition@580000 {
- label = "ubi";
+ compatible = "linux,ubi";
reg = <0x580000 0x7800000>;
+ label = "ubi";
+
+ volumes {
+ ubi_rootdisk: ubi-volume-fit {
+ volname = "fit";
+ };
+ };
};
};
};
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
- fragment@0 {
- target = <&gmac1>;
- __overlay__ {
- phy-mode = "2500base-x";
- phy-handle = <&phy5>;
- };
- };
-
- fragment@1 {
- target = <&mdio_bus>;
- __overlay__ {
- reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
- reset-delay-us = <600>;
- reset-post-delay-us = <20000>;
-
- phy5: ethernet-phy@5 {
- reg = <5>;
- compatible = "ethernet-phy-ieee802.3-c45";
- phy-mode = "2500base-x";
- };
- };
- };
-};
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
- fragment@0 {
- target = <&sw_p5>;
- __overlay__ {
- phy-mode = "2500base-x";
- phy-handle = <&phy5>;
- status = "okay";
- };
- };
-
- fragment@1 {
- target = <&mdio_bus>;
- __overlay__ {
- reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
- reset-delay-us = <600>;
- reset-post-delay-us = <20000>;
-
- phy5: ethernet-phy@5 {
- reg = <5>;
- compatible = "ethernet-phy-ieee802.3-c45";
- phy-mode = "2500base-x";
- };
- };
- };
-};
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
- fragment@0 {
- target = <&spi0>;
- __overlay__ {
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- spi_nand: spi_nand@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <10000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "BL2";
- reg = <0x00000 0x0100000>;
- read-only;
- };
-
- partition@100000 {
- label = "u-boot-env";
- reg = <0x0100000 0x0080000>;
- };
-
- factory: partition@180000 {
- label = "Factory";
- reg = <0x180000 0x0200000>;
- };
-
- partition@380000 {
- label = "FIP";
- reg = <0x380000 0x0200000>;
- };
-
- partition@580000 {
- label = "ubi";
- reg = <0x580000 0x4000000>;
- };
- };
- };
- };
- };
-
- fragment@1 {
- target = <&wifi>;
- __overlay__ {
- mediatek,mtd-eeprom = <&factory 0x0>;
- status = "okay";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7981.dtsi"
-
-/ {
- model = "MediaTek MT7981 RFB";
- compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- reg = <0 0x40000000 0 0x20000000>;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_5v: regulator-5v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&pio 1 GPIO_ACTIVE_LOW>;
- };
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-ð {
- status = "okay";
-
- gmac0: mac@0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
-
- gmac1: mac@1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- phy-mode = "gmii";
- phy-handle = <&int_gbe_phy>;
- };
-};
-
-&mdio_bus {
- switch: switch@1f {
- compatible = "mediatek,mt7531";
- reg = <31>;
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&pio>;
- interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
- reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&crypto {
- status = "okay";
-};
-
-&pio {
- spi0_flash_pins: spi0-pins {
- mux {
- function = "spi";
- groups = "spi0", "spi0_wp_hold";
- };
- conf-pu {
- pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
- drive-strength = <MTK_DRIVE_8mA>;
- bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
- };
- conf-pd {
- pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
- drive-strength = <MTK_DRIVE_8mA>;
- bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
- };
- };
-
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_flash_pins>;
- cs-gpios = <0>, <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-};
-
-&switch {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan1";
- };
-
- port@1 {
- reg = <1>;
- label = "lan2";
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- };
-
- port@3 {
- reg = <3>;
- label = "lan4";
- };
-
- sw_p5: port@5 {
- reg = <5>;
- label = "lan5";
- status = "disabled";
- };
-
- port@6 {
- reg = <6>;
- ethernet = <&gmac0>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
- };
-};
-
-&xhci {
- vusb33-supply = <®_3p3v>;
- vbus-supply = <®_5v>;
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (c) 2020 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- * Author: Jianhui Zhao <zhaojh329@gmail.com>
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-#include <dt-bindings/reset/mt7986-resets.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/mux/mux.h>
-
-/ {
- compatible = "mediatek,mt7981";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- device_type = "cpu";
- enable-method = "psci";
- };
-
- cpu@1 {
- compatible = "arm,cortex-a53";
- reg = <0x1>;
- device_type = "cpu";
- enable-method = "psci";
- };
- };
-
- ice: ice_debug {
- compatible = "mediatek,mt7981-ice_debug", "mediatek,mt2701-ice_debug";
- clocks = <&infracfg CLK_INFRA_DBG_CK>;
- clock-names = "ice_dbg";
- };
-
- clk40m: oscillator-40m {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- clock-output-names = "clkxtal";
- #clock-cells = <0>;
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- fan: pwm-fan {
- compatible = "pwm-fan";
- /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
- cooling-levels = <0 63 95 127 159 191 223 255>;
- #cooling-cells = <2>;
- status = "disabled";
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reserved-memory {
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
-
- /* 64 KiB reserved for ramoops/pstore */
- ramoops@42ff0000 {
- compatible = "ramoops";
- reg = <0 0x42ff0000 0 0x10000>;
- record-size = <0x1000>;
- };
-
- /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- secmon_reserved: secmon@43000000 {
- reg = <0 0x43000000 0 0x30000>;
- no-map;
- };
-
- wmcpu_emi: wmcpu-reserved@47c80000 {
- reg = <0 0x47c80000 0 0x100000>;
- no-map;
- };
-
- wo_emi0: wo-emi@47d80000 {
- reg = <0 0x47d80000 0 0x40000>;
- no-map;
- };
-
- wo_data: wo-data@47dc0000 {
- reg = <0 0x47dc0000 0 0x240000>;
- no-map;
- };
- };
-
- soc {
- compatible = "simple-bus";
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
-
- gic: interrupt-controller@c000000 {
- compatible = "arm,gic-v3";
- reg = <0 0x0c000000 0 0x40000>, /* GICD */
- <0 0x0c080000 0 0x200000>; /* GICR */
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <3>;
- };
-
- consys: consys@10000000 {
- compatible = "mediatek,mt7981-consys";
- reg = <0 0x10000000 0 0x8600000>;
- memory-region = <&wmcpu_emi>;
- };
-
- infracfg: clock-controller@10001000 {
- compatible = "mediatek,mt7981-infracfg", "syscon";
- reg = <0 0x10001000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- wed_pcie: wed_pcie@10003000 {
- compatible = "mediatek,wed_pcie";
- reg = <0 0x10003000 0 0x10>;
- };
-
- topckgen: clock-controller@1001b000 {
- compatible = "mediatek,mt7981-topckgen", "syscon";
- reg = <0 0x1001b000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- watchdog: watchdog@1001c000 {
- compatible = "mediatek,mt7986-wdt",
- "mediatek,mt6589-wdt";
- reg = <0 0x1001c000 0 0x1000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- #reset-cells = <1>;
- status = "disabled";
- };
-
- apmixedsys: clock-controller@1001e000 {
- compatible = "mediatek,mt7981-apmixedsys", "syscon";
- reg = <0 0x1001e000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- pwm: pwm@10048000 {
- compatible = "mediatek,mt7981-pwm";
- reg = <0 0x10048000 0 0x1000>;
- clocks = <&infracfg CLK_INFRA_PWM_STA>,
- <&infracfg CLK_INFRA_PWM_HCK>,
- <&infracfg CLK_INFRA_PWM1_CK>,
- <&infracfg CLK_INFRA_PWM2_CK>,
- <&infracfg CLK_INFRA_PWM3_CK>;
- clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
- #pwm-cells = <2>;
- };
-
- sgmiisys0: syscon@10060000 {
- compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
- reg = <0 0x10060000 0 0x1000>;
- mediatek,pnswap;
- #clock-cells = <1>;
- };
-
- sgmiisys1: syscon@10070000 {
- compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
- reg = <0 0x10070000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- crypto: crypto@10320000 {
- compatible = "inside-secure,safexcel-eip97";
- reg = <0 0x10320000 0 0x40000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ring0", "ring1", "ring2", "ring3";
- clocks = <&topckgen CLK_TOP_EIP97B>;
- clock-names = "top_eip97_ck";
- assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
- };
-
- uart0: serial@11002000 {
- compatible = "mediatek,mt6577-uart";
- reg = <0 0x11002000 0 0x400>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_UART0_SEL>,
- <&infracfg CLK_INFRA_UART0_CK>;
- clock-names = "baud", "bus";
- assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&infracfg CLK_INFRA_UART0_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
- <&topckgen CLK_TOP_UART_SEL>;
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- uart1: serial@11003000 {
- compatible = "mediatek,mt6577-uart";
- reg = <0 0x11003000 0 0x400>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_UART1_SEL>,
- <&infracfg CLK_INFRA_UART1_CK>;
- clock-names = "baud", "bus";
- assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&infracfg CLK_INFRA_UART1_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
- <&topckgen CLK_TOP_UART_SEL>;
- status = "disabled";
- };
-
- uart2: serial@11004000 {
- compatible = "mediatek,mt6577-uart";
- reg = <0 0x11004000 0 0x400>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_UART2_SEL>,
- <&infracfg CLK_INFRA_UART2_CK>;
- clock-names = "baud", "bus";
- assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&infracfg CLK_INFRA_UART2_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
- <&topckgen CLK_TOP_UART_SEL>;
- status = "disabled";
- };
-
- snand: snfi@11005000 {
- compatible = "mediatek,mt7986-snand";
- reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
- reg-names = "nfi", "ecc";
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
- <&infracfg CLK_INFRA_NFI1_CK>,
- <&infracfg CLK_INFRA_NFI_HCK_CK>;
- clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
- <&topckgen CLK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
- <&topckgen CLK_TOP_CB_M_D8>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c0: i2c@11007000 {
- compatible = "mediatek,mt7981-i2c";
- reg = <0 0x11007000 0 0x1000>,
- <0 0x10217080 0 0x80>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clock-div = <1>;
- clocks = <&infracfg CLK_INFRA_I2C0_CK>,
- <&infracfg CLK_INFRA_AP_DMA_CK>,
- <&infracfg CLK_INFRA_I2C_MCK_CK>,
- <&infracfg CLK_INFRA_I2C_PCK_CK>;
- clock-names = "main", "dma", "arb", "pmic";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi2: spi@11009000 {
- compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
- reg = <0 0x11009000 0 0x100>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_CB_M_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
- <&infracfg CLK_INFRA_SPI2_CK>,
- <&infracfg CLK_INFRA_SPI2_HCK_CK>;
- clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi0: spi@1100a000 {
- compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
- reg = <0 0x1100a000 0 0x100>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_CB_M_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
- <&infracfg CLK_INFRA_SPI0_CK>,
- <&infracfg CLK_INFRA_SPI0_HCK_CK>;
- clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@1100b000 {
- compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
- reg = <0 0x1100b000 0 0x100>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_CB_M_D2>,
- <&topckgen CLK_TOP_SPIM_MST_SEL>,
- <&infracfg CLK_INFRA_SPI1_CK>,
- <&infracfg CLK_INFRA_SPI1_HCK_CK>;
- clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- thermal: thermal@1100c800 {
- compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
- reg = <0 0x1100c800 0 0x800>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_THERM_CK>,
- <&infracfg CLK_INFRA_ADC_26M_CK>;
- clock-names = "therm", "auxadc";
- nvmem-cells = <&thermal_calibration>;
- nvmem-cell-names = "calibration-data";
- #thermal-sensor-cells = <1>;
- mediatek,auxadc = <&auxadc>;
- mediatek,apmixedsys = <&apmixedsys>;
- };
-
- auxadc: adc@1100d000 {
- compatible = "mediatek,mt7981-auxadc",
- "mediatek,mt7986-auxadc",
- "mediatek,mt7622-auxadc";
- reg = <0 0x1100d000 0 0x1000>;
- clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
- <&infracfg CLK_INFRA_ADC_FRC_CK>;
- clock-names = "main", "32k";
- #io-channel-cells = <1>;
- };
-
- xhci: usb@11200000 {
- compatible = "mediatek,mt7986-xhci",
- "mediatek,mtk-xhci";
- reg = <0 0x11200000 0 0x2e00>,
- <0 0x11203e00 0 0x0100>;
- reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
- <&infracfg CLK_INFRA_IUSB_CK>,
- <&infracfg CLK_INFRA_IUSB_133_CK>,
- <&infracfg CLK_INFRA_IUSB_66M_CK>,
- <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
- clock-names = "sys_ck",
- "ref_ck",
- "mcu_ck",
- "dma_ck",
- "xhci_ck";
- phys = <&u2port0 PHY_TYPE_USB2>,
- <&u3port0 PHY_TYPE_USB3>;
- vusb33-supply = <®_3p3v>;
- status = "disabled";
- };
-
- afe: audio-controller@11210000 {
- compatible = "mediatek,mt79xx-audio";
- reg = <0 0x11210000 0 0x9000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
- <&infracfg CLK_INFRA_AUD_26M_CK>,
- <&infracfg CLK_INFRA_AUD_L_CK>,
- <&infracfg CLK_INFRA_AUD_AUD_CK>,
- <&infracfg CLK_INFRA_AUD_EG2_CK>,
- <&topckgen CLK_TOP_AUD_SEL>;
- clock-names = "aud_bus_ck",
- "aud_26m_ck",
- "aud_l_ck",
- "aud_aud_ck",
- "aud_eg2_ck",
- "aud_sel";
- assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
- <&topckgen CLK_TOP_A1SYS_SEL>,
- <&topckgen CLK_TOP_AUD_L_SEL>,
- <&topckgen CLK_TOP_A_TUNER_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
- <&topckgen CLK_TOP_APLL2_D4>,
- <&topckgen CLK_TOP_CB_APLL2_196M>,
- <&topckgen CLK_TOP_APLL2_D4>;
- status = "disabled";
- };
-
- mmc0: mmc@11230000 {
- compatible = "mediatek,mt7986-mmc", "mediatek,mt7981-mmc";
- reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_MSDC_CK>,
- <&infracfg CLK_INFRA_MSDC_HCK_CK>,
- <&infracfg CLK_INFRA_MSDC_66M_CK>,
- <&infracfg CLK_INFRA_MSDC_133M_CK>;
- assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
- <&topckgen CLK_TOP_EMMC_400M_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
- <&topckgen CLK_TOP_CB_NET2_D2>;
- clock-names = "source", "hclk", "axi_cg", "ahb_cg";
- status = "disabled";
- };
-
- pcie: pcie@11280000 {
- compatible = "mediatek,mt7981-pcie",
- "mediatek,mt7986-pcie";
- reg = <0 0x11280000 0 0x4000>;
- reg-names = "pcie-mac";
- ranges = <0x82000000 0 0x20000000
- 0x0 0x20000000 0 0x10000000>;
- device_type = "pci";
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- bus-range = <0x00 0xff>;
- clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
- <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
- <&infracfg CLK_INFRA_IPCIER_CK>,
- <&infracfg CLK_INFRA_IPCIEB_CK>;
- phys = <&u3port0 PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc 0>,
- <0 0 0 2 &pcie_intc 1>,
- <0 0 0 3 &pcie_intc 2>,
- <0 0 0 4 &pcie_intc 3>;
- #interrupt-cells = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie_intc: interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- };
- };
-
- pio: pinctrl@11d00000 {
- compatible = "mediatek,mt7981-pinctrl";
- reg = <0 0x11d00000 0 0x1000>,
- <0 0x11c00000 0 0x1000>,
- <0 0x11c10000 0 0x1000>,
- <0 0x11d20000 0 0x1000>,
- <0 0x11e00000 0 0x1000>,
- <0 0x11e20000 0 0x1000>,
- <0 0x11f00000 0 0x1000>,
- <0 0x11f10000 0 0x1000>,
- <0 0x1000b000 0 0x1000>;
- reg-names = "gpio", "iocfg_rt", "iocfg_rm",
- "iocfg_rb", "iocfg_lb", "iocfg_bl",
- "iocfg_tm", "iocfg_tl", "eint";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pio 0 0 56>;
- interrupt-controller;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- #interrupt-cells = <2>;
-
- mdio_pins: mdc-mdio-pins {
- mux {
- function = "eth";
- groups = "smi_mdc_mdio";
- };
- };
-
- uart0_pins: uart0-pins {
- mux {
- function = "uart";
- groups = "uart0";
- };
- };
-
- wifi_dbdc_pins: wifi-dbdc-pins {
- mux {
- function = "eth";
- groups = "wf0_mode1";
- };
-
- conf {
- pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
- "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
- "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
- "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
- "WF_CBA_RESETB", "WF_DIG_RESETB";
- drive-strength = <4>;
- };
- };
-
- gbe_led0_pins: gbe-led0-pins {
- mux {
- function = "led";
- groups = "gbe_led0";
- };
- };
-
- gbe_led1_pins: gbe-led1-pins {
- mux {
- function = "led";
- groups = "gbe_led1";
- };
- };
- };
-
- topmisc: topmisc@11d10000 {
- compatible = "mediatek,mt7981-topmisc", "syscon";
- reg = <0 0x11d10000 0 0x10000>;
- #clock-cells = <1>;
- };
-
- usb_phy: usb-phy@11e10000 {
- compatible = "mediatek,mt7981",
- "mediatek,generic-tphy-v2";
- ranges = <0 0 0x11e10000 0x1700>;
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
-
- u2port0: usb-phy@0 {
- reg = <0x0 0x700>;
- clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
-
- u3port0: usb-phy@700 {
- reg = <0x700 0x900>;
- clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
- clock-names = "ref";
- #phy-cells = <1>;
- mediatek,syscon-type = <&topmisc 0x218 0>;
- status = "okay";
- };
- };
-
- efuse: efuse@11f20000 {
- compatible = "mediatek,mt7981-efuse",
- "mediatek,efuse";
- reg = <0 0x11f20000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- status = "okay";
-
- thermal_calibration: thermal-calib@274 {
- reg = <0x274 0xc>;
- };
-
- phy_calibration: phy-calib@8dc {
- reg = <0x8dc 0x10>;
- };
-
- comb_rx_imp_p0: usb3-rx-imp@8c8 {
- reg = <0x8c8 1>;
- bits = <0 5>;
- };
-
- comb_tx_imp_p0: usb3-tx-imp@8c8 {
- reg = <0x8c8 2>;
- bits = <5 5>;
- };
-
- comb_intr_p0: usb3-intr@8c9 {
- reg = <0x8c9 1>;
- bits = <2 6>;
- };
- };
-
- ethsys: clock-controller@15000000 {
- compatible = "mediatek,mt7981-ethsys",
- "syscon";
- reg = <0 0x15000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- wed: wed@15010000 {
- compatible = "mediatek,mt7981-wed",
- "mediatek,mt7986-wed",
- "syscon";
- reg = <0 0x15010000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- memory-region = <&wo_emi0>, <&wo_data>;
- memory-region-names = "wo-emi", "wo-data";
- mediatek,wo-ccif = <&wo_ccif0>;
- mediatek,wo-ilm = <&wo_ilm0>;
- mediatek,wo-dlm = <&wo_dlm0>;
- mediatek,wo-cpuboot = <&wo_cpuboot>;
- };
-
- eth: ethernet@15100000 {
- compatible = "mediatek,mt7981-eth";
- reg = <0 0x15100000 0 0x80000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <ðsys CLK_ETH_FE_EN>,
- <ðsys CLK_ETH_GP2_EN>,
- <ðsys CLK_ETH_GP1_EN>,
- <ðsys CLK_ETH_WOCPU0_EN>,
- <&sgmiisys0 CLK_SGM0_TX_EN>,
- <&sgmiisys0 CLK_SGM0_RX_EN>,
- <&sgmiisys0 CLK_SGM0_CK0_EN>,
- <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
- <&sgmiisys1 CLK_SGM1_TX_EN>,
- <&sgmiisys1 CLK_SGM1_RX_EN>,
- <&sgmiisys1 CLK_SGM1_CK1_EN>,
- <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
- <&topckgen CLK_TOP_SGM_REG>,
- <&topckgen CLK_TOP_NETSYS_SEL>,
- <&topckgen CLK_TOP_NETSYS_500M_SEL>;
- clock-names = "fe", "gp2", "gp1", "wocpu0",
- "sgmii_tx250m", "sgmii_rx250m",
- "sgmii_cdr_ref", "sgmii_cdr_fb",
- "sgmii2_tx250m", "sgmii2_rx250m",
- "sgmii2_cdr_ref", "sgmii2_cdr_fb",
- "sgmii_ck", "netsys0", "netsys1";
- assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
- <&topckgen CLK_TOP_SGM_325M_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
- <&topckgen CLK_TOP_CB_SGM_325M>;
- mediatek,ethsys = <ðsys>;
- mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
- mediatek,infracfg = <&topmisc>;
- mediatek,wed = <&wed>;
- #reset-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- mdio_bus: mdio-bus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- int_gbe_phy: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- phy-mode = "gmii";
- phy-is-integrated;
- nvmem-cells = <&phy_calibration>;
- nvmem-cell-names = "phy-cal-data";
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- int_gbe_phy_led0: int-gbe-phy-led0@0 {
- reg = <0>;
- function = LED_FUNCTION_LAN;
- status = "disabled";
- };
-
- int_gbe_phy_led1: int-gbe-phy-led1@1 {
- reg = <1>;
- function = LED_FUNCTION_LAN;
- status = "disabled";
- };
- };
- };
- };
- };
-
- wdma: wdma@15104800 {
- compatible = "mediatek,wed-wdma";
- reg = <0 0x15104800 0 0x400>,
- <0 0x15104c00 0 0x400>;
- };
-
- wo_cpuboot: syscon@15194000 {
- compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
- reg = <0 0x15194000 0 0x1000>;
- };
-
- ap2woccif: ap2woccif@151a5000 {
- compatible = "mediatek,ap2woccif";
- reg = <0 0x151a5000 0 0x1000>,
- <0 0x151ad000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wo_ccif0: syscon@151a5000 {
- compatible = "mediatek,mt7986-wo-ccif", "syscon";
- reg = <0 0x151a5000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- wo_ilm0: syscon@151e0000 {
- compatible = "mediatek,mt7986-wo-ilm", "syscon";
- reg = <0 0x151e0000 0 0x8000>;
- };
-
- wo_dlm0: syscon@151e8000 {
- compatible = "mediatek,mt7986-wo-dlm", "syscon";
- reg = <0 0x151e8000 0 0x2000>;
- };
-
- wifi: wifi@18000000 {
- compatible = "mediatek,mt7981-wmac";
- reg = <0 0x18000000 0 0x1000000>,
- <0 0x10003000 0 0x1000>,
- <0 0x11d10000 0 0x1000>;
- resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
- reset-names = "consys";
- pinctrl-0 = <&wifi_dbdc_pins>;
- pinctrl-names = "dbdc";
- clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
- <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
- clock-names = "mcu", "ap2conn";
- interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
- memory-region = <&wmcpu_emi>;
- status = "disabled";
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <1000>;
- thermal-sensors = <&thermal 0>;
-
- trips {
- cpu_trip_active_highest: active-highest {
- temperature = <70000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- cpu_trip_active_high: active-high {
- temperature = <60000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- cpu_trip_active_med: active-med {
- temperature = <50000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- cpu_trip_active_low: active-low {
- temperature = <45000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- cpu_trip_active_lowest: active-lowest {
- temperature = <40000>;
- hysteresis = <2000>;
- type = "active";
- };
- };
-
- cooling-maps {
- cpu-active-highest {
- /* active: set fan to cooling level 7 */
- cooling-device = <&fan 7 7>;
- trip = <&cpu_trip_active_highest>;
- };
-
- cpu-active-high {
- /* active: set fan to cooling level 5 */
- cooling-device = <&fan 5 5>;
- trip = <&cpu_trip_active_high>;
- };
-
- cpu-active-med {
- /* active: set fan to cooling level 3 */
- cooling-device = <&fan 3 3>;
- trip = <&cpu_trip_active_med>;
- };
-
- cpu-active-low {
- /* active: set fan to cooling level 2 */
- cooling-device = <&fan 2 2>;
- trip = <&cpu_trip_active_low>;
- };
-
- cpu-active-lowest {
- /* active: set fan to cooling level 1 */
- cooling-device = <&fan 1 1>;
- trip = <&cpu_trip_active_lowest>;
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&gic>;
- clock-frequency = <13000000>;
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-
- };
-
- trng {
- compatible = "mediatek,mt7981-rng";
- };
-};
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
- compatible = "mediatek,mt7986a-rfb-snand";
-};
-
-&spi0 {
- status = "okay";
-
- spi_nand: spi_nand@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <10000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "BL2";
- reg = <0x00000 0x0100000>;
- read-only;
- };
- partition@100000 {
- label = "u-boot-env";
- reg = <0x0100000 0x0080000>;
- };
- factory: partition@180000 {
- label = "Factory";
- reg = <0x180000 0x0200000>;
- };
- partition@380000 {
- label = "FIP";
- reg = <0x380000 0x0200000>;
- };
- partition@580000 {
- label = "ubi";
- reg = <0x580000 0x4000000>;
- };
- };
- };
-};
-
-&wifi {
- mediatek,mtd-eeprom = <&factory 0>;
-};
+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-
-#include "mt7986a-rfb.dtsi"
-
-/ {
- compatible = "mediatek,mt7986a-rfb-snor";
-};
-
-&spi0 {
- status = "okay";
-
- spi_nor: spi_nor@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <52000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@00000 {
- label = "BL2";
- reg = <0x00000 0x0040000>;
- };
- partition@40000 {
- label = "u-boot-env";
- reg = <0x40000 0x0010000>;
- };
- factory: partition@50000 {
- label = "Factory";
- reg = <0x50000 0x00B0000>;
- };
- partition@100000 {
- label = "FIP";
- reg = <0x100000 0x0080000>;
- };
- partition@180000 {
- label = "firmware";
- reg = <0x180000 0xE00000>;
- };
- };
- };
-};
-
-&wifi {
- mediatek,mtd-eeprom = <&factory 0>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7986a.dtsi"
-
-/ {
- model = "MediaTek MT7986a RFB";
- compatible = "mediatek,mt7986a-rfb";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_5v: regulator-5v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-ð {
- status = "okay";
-
- gmac0: mac@0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
-
- gmac1: mac@1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- phy-mode = "2500base-x";
- };
-
- mdio: mdio-bus {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-};
-
-&wifi {
- status = "okay";
- pinctrl-names = "default", "dbdc";
- pinctrl-0 = <&wf_2g_5g_pins>;
- pinctrl-1 = <&wf_dbdc_pins>;
-};
-
-&mdio {
- phy5: phy@5 {
- compatible = "ethernet-phy-id67c9.de0a";
- reg = <5>;
-
- reset-gpios = <&pio 6 1>;
- reset-deassert-us = <20000>;
- };
-
- phy6: phy@6 {
- compatible = "ethernet-phy-id67c9.de0a";
- reg = <6>;
- };
-
- switch: switch@1f {
- compatible = "mediatek,mt7531";
- reg = <31>;
- reset-gpios = <&pio 5 0>;
- };
-};
-
-&crypto {
- status = "okay";
-};
-
-&mmc0 {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&mmc0_pins_default>;
- pinctrl-1 = <&mmc0_pins_uhs>;
- bus-width = <8>;
- max-frequency = <200000000>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- hs400-ds-delay = <0x14014>;
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- non-removable;
- no-sd;
- no-sdio;
- status = "okay";
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pins>;
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pio {
- mmc0_pins_default: mmc0-pins {
- mux {
- function = "emmc";
- groups = "emmc_51";
- };
- conf-cmd-dat {
- pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
- "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
- "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
- input-enable;
- drive-strength = <4>;
- mediatek,pull-up-adv = <1>; /* pull-up 10K */
- };
- conf-clk {
- pins = "EMMC_CK";
- drive-strength = <6>;
- mediatek,pull-down-adv = <2>; /* pull-down 50K */
- };
- conf-ds {
- pins = "EMMC_DSL";
- mediatek,pull-down-adv = <2>; /* pull-down 50K */
- };
- conf-rst {
- pins = "EMMC_RSTB";
- drive-strength = <4>;
- mediatek,pull-up-adv = <1>; /* pull-up 10K */
- };
- };
-
- mmc0_pins_uhs: mmc0-uhs-pins {
- mux {
- function = "emmc";
- groups = "emmc_51";
- };
- conf-cmd-dat {
- pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
- "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
- "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
- input-enable;
- drive-strength = <4>;
- mediatek,pull-up-adv = <1>; /* pull-up 10K */
- };
- conf-clk {
- pins = "EMMC_CK";
- drive-strength = <6>;
- mediatek,pull-down-adv = <2>; /* pull-down 50K */
- };
- conf-ds {
- pins = "EMMC_DSL";
- mediatek,pull-down-adv = <2>; /* pull-down 50K */
- };
- conf-rst {
- pins = "EMMC_RSTB";
- drive-strength = <4>;
- mediatek,pull-up-adv = <1>; /* pull-up 10K */
- };
- };
-
- pcie_pins: pcie-pins {
- mux {
- function = "pcie";
- groups = "pcie_clk", "pcie_wake", "pcie_pereset";
- };
- };
-
- spic_pins_g2: spic-pins-29-to-32 {
- mux {
- function = "spi";
- groups = "spi1_2";
- };
- };
-
- spi_flash_pins: spi-flash-pins-33-to-38 {
- mux {
- function = "spi";
- groups = "spi0", "spi0_wp_hold";
- };
- conf-pu {
- pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
- drive-strength = <8>;
- mediatek,pull-up-adv = <0>; /* bias-disable */
- };
- conf-pd {
- pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
- drive-strength = <8>;
- mediatek,pull-down-adv = <0>; /* bias-disable */
- };
- };
-
- uart1_pins: uart1-pins {
- mux {
- function = "uart";
- groups = "uart1";
- };
- };
-
- uart2_pins: uart2-pins {
- mux {
- function = "uart";
- groups = "uart2";
- };
- };
-
- wf_2g_5g_pins: wf_2g_5g-pins {
- mux {
- function = "wifi";
- groups = "wf_2g", "wf_5g";
- };
- conf {
- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
- "WF1_TOP_CLK", "WF1_TOP_DATA";
- drive-strength = <4>;
- };
- };
-
- wf_dbdc_pins: wf_dbdc-pins {
- mux {
- function = "wifi";
- groups = "wf_dbdc";
- };
- conf {
- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
- "WF1_TOP_CLK", "WF1_TOP_DATA";
- drive-strength = <4>;
- };
- };
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi_flash_pins>;
- cs-gpios = <0>, <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic_pins_g2>;
- status = "okay";
-
- proslic_spi: proslic_spi@0 {
- compatible = "silabs,proslic_spi";
- reg = <0>;
- spi-max-frequency = <10000000>;
- spi-cpha = <1>;
- spi-cpol = <1>;
- channel_count = <1>;
- debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
- reset_gpio = <&pio 7 0>;
- ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
- };
-};
-
-&gmac1 {
- phy-mode = "2500base-x";
- phy-connection-type = "2500base-x";
- phy-handle = <&phy6>;
-};
-
-&switch {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan1";
- };
-
- port@1 {
- reg = <1>;
- label = "lan2";
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- };
-
- port@3 {
- reg = <3>;
- label = "lan4";
- };
-
- port@4 {
- reg = <4>;
- label = "wan";
- };
-
- port@5 {
- reg = <5>;
- label = "lan6";
-
- phy-mode = "2500base-x";
- phy-handle = <&phy5>;
- };
-
- port@6 {
- reg = <6>;
- ethernet = <&gmac0>;
- phy-mode = "2500base-x";
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- pause;
- };
- };
- };
-};
-
-&ssusb {
- vusb33-supply = <®_3p3v>;
- vbus-supply = <®_5v>;
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- status = "okay";
-};
-
-&usb_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
- fragment@0 {
- target-path = "/soc/mmc@11230000";
- __overlay__ {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&mmc0_pins_emmc_51>;
- pinctrl-1 = <&mmc0_pins_emmc_51>;
- bus-width = <8>;
- max-frequency = <200000000>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- hs400-ds-delay = <0x12814>;
- vqmmc-supply = <®_1p8v>;
- vmmc-supply = <®_3p3v>;
- non-removable;
- no-sd;
- no-sdio;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- card@0 {
- compatible = "mmc-card";
- reg = <0>;
-
- block {
- compatible = "block-device";
- partitions {
- block-partition-env {
- partname = "ubootenv";
- nvmem-layout {
- compatible = "u-boot,env-layout";
- };
- };
- emmc_rootfs: block-partition-production {
- partname = "production";
- };
- };
- };
- };
- };
- };
-
- fragment@2 {
- target-path = "/chosen";
- __overlay__ {
- rootdisk-emmc = <&emmc_rootfs>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023
- * Author: Daniel Golle <daniel@makrotopia.org>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&pcf8563>;
- __overlay__ {
- status = "okay";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
- fragment@1 {
- target-path = "/soc/mmc@11230000";
- __overlay__ {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&mmc0_pins_sdcard>;
- pinctrl-1 = <&mmc0_pins_sdcard>;
- cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- max-frequency = <52000000>;
- cap-sd-highspeed;
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_3p3v>;
- no-mmc;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- card@0 {
- compatible = "mmc-card";
- reg = <0>;
-
- block {
- compatible = "block-device";
- partitions {
- block-partition-env {
- partname = "ubootenv";
- nvmem-layout {
- compatible = "u-boot,env-layout";
- };
- };
- sd_rootfs: block-partition-production {
- partname = "production";
- };
- };
- };
- };
- };
- };
-
- fragment@2 {
- target-path = "/chosen";
- __overlay__ {
- rootdisk-sd = <&sd_rootfs>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
-
- fragment@0 {
- target-path = "/";
- __overlay__ {
- wifi_12v: regulator-wifi-12v {
- compatible = "regulator-fixed";
- regulator-name = "wifi";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- gpio = <&pio 4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
- };
- };
-
- fragment@1 {
- target = <&i2c_wifi>;
- __overlay__ {
- // 5G WIFI MAC Address EEPROM
- wifi_eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- address-bits = <8>;
- page-size = <8>;
- size = <256>;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_5g: macaddr@0 {
- reg = <0x0 0x6>;
- };
- };
- };
-
- // 6G WIFI MAC Address EEPROM
- wifi_eeprom@52 {
- compatible = "atmel,24c02";
- reg = <0x52>;
- address-bits = <8>;
- page-size = <8>;
- size = <256>;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_6g: macaddr@0 {
- reg = <0x0 0x6>;
- };
- };
- };
- };
- };
-
- fragment@2 {
- target = <&pcie0>;
- __overlay__ {
- pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
-
- wifi@0,0 {
- compatible = "mediatek,mt76";
- reg = <0x0000 0 0 0 0>;
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_5g>;
- };
- };
- };
- };
-
- fragment@3 {
- target = <&pcie1>;
- __overlay__ {
- pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
-
- wifi@0,0 {
- compatible = "mediatek,mt76";
- reg = <0x0000 0 0 0 0>;
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_6g>;
- };
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7988a.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-
-/ {
- model = "Bananapi BPI-R4";
- compatible = "bananapi,bpi-r4",
- "mediatek,mt7988";
-
- aliases {
- serial0 = &uart0;
- led-boot = &led_green;
- led-failsafe = &led_green;
- led-running = &led_green;
- led-upgrade = &led_green;
- };
-
- chosen {
- stdout-path = &uart0;
- bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait";
- rootdisk-spim-nand = <&ubi_rootfs>;
- };
-
- memory {
- reg = <0x00 0x40000000 0x00 0x10000000>;
- };
-
- /* SFP1 cage (WAN) */
- sfp1: sfp1 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp1>;
- los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
- tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
- tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
- rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
- maximum-power-milliwatt = <3000>;
- };
-
- /* SFP2 cage (LAN) */
- sfp2: sfp2 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp2>;
- los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
- tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
- tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
- rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
- maximum-power-milliwatt = <3000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- wps {
- label = "WPS";
- linux,code = <KEY_RESTART>;
- gpios = <&pio 14 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- led_green: led-green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- led_blue: led-blue {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-};
-
-ð {
- status = "okay";
-};
-
-&gmac0 {
- status = "okay";
-};
-
-&gmac1 {
- sfp = <&sfp2>;
- managed = "in-band-status";
- phy-mode = "usxgmii";
- status = "okay";
-};
-
-&gmac2 {
- sfp = <&sfp1>;
- managed = "in-band-status";
- phy-mode = "usxgmii";
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&gsw_phy0 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe0_led0_pins>;
-};
-
-&gsw_port0 {
- label = "wan";
-};
-
-&gsw_phy0_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy1 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe1_led0_pins>;
-};
-
-&gsw_phy1_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy2 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe2_led0_pins>;
-};
-
-&gsw_phy2_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy3 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe3_led0_pins>;
-};
-
-&gsw_phy3_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&cpu0 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cpu1 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cpu2 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cpu3 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cci {
- proc-supply = <&rt5190_buck3>;
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
-
- rt5190a_64: rt5190a@64 {
- compatible = "richtek,rt5190a";
- reg = <0x64>;
- vin2-supply = <&rt5190_buck1>;
- vin3-supply = <&rt5190_buck1>;
- vin4-supply = <&rt5190_buck1>;
-
- regulators {
- rt5190_buck1: buck1 {
- regulator-name = "rt5190a-buck1";
- regulator-min-microvolt = <5090000>;
- regulator-max-microvolt = <5090000>;
- regulator-allowed-modes =
- <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
- regulator-boot-on;
- regulator-always-on;
- };
- buck2 {
- regulator-name = "vcore";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
- rt5190_buck3: buck3 {
- regulator-name = "vproc";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- };
- buck4 {
- regulator-name = "rt5190a-buck4";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-allowed-modes =
- <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
- regulator-boot-on;
- regulator-always-on;
- };
- ldo {
- regulator-name = "rt5190a-ldo";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_1_pins>;
- status = "okay";
-
- pca9545: i2c-switch@70 {
- reg = <0x70>;
- compatible = "nxp,pca9545";
- reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c_rtc: i2c@0 { //eeprom,rtc,ngff
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- address-bits = <8>;
- page-size = <8>;
- size = <256>;
- };
-
- eeprom@57 {
- compatible = "atmel,24c02";
- reg = <0x57>;
- address-bits = <8>;
- page-size = <8>;
- size = <256>;
- };
-
- pcf8563: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- status = "disabled";
- };
- };
-
- i2c_sfp1: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
-
- i2c_sfp2: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- i2c_wifi: i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
- };
-};
-
-/* mPCIe SIM2 */
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_pins>;
- status = "okay";
-};
-
-/* mPCIe SIM3 */
-&pcie1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie1_pins>;
- status = "okay";
-};
-
-/* M.2 key-B SIM1 */
-&pcie2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_pins>;
- status = "okay";
-};
-
-/* M.2 key-M SSD */
-&pcie3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie3_pins>;
- status = "okay";
-};
-
-&ssusb1 {
- status = "okay";
-};
-
-&tphy {
- status = "okay";
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_flash_pins>;
- status = "okay";
-
- spi_nand: spi_nand@0 {
- compatible = "spi-nand";
- reg = <0>;
- spi-max-frequency = <52000000>;
- spi-tx-buswidth = <4>;
- spi-rx-buswidth = <4>;
- };
-};
-
-&spi_nand {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bl2";
- reg = <0x0 0x200000>;
- read-only;
- };
-
- partition@200000 {
- label = "ubi";
- reg = <0x200000 0x7e00000>;
- compatible = "linux,ubi";
-
- volumes {
- ubi-volume-ubootenv {
- volname = "ubootenv";
- nvmem-layout {
- compatible = "u-boot,env-redundant-bool-layout";
- };
- };
-
- ubi-volume-ubootenv2 {
- volname = "ubootenv2";
- nvmem-layout {
- compatible = "u-boot,env-redundant-bool-layout";
- };
- };
-
- ubi_rootfs: ubi-volume-fit {
- volname = "fit";
- };
- };
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_2_lite_pins>;
-};
-
-&uart2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_3_pins>;
-};
-
-&watchdog {
- status = "okay";
-};
-
-&xphy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2021 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&mmc0>;
- __overlay__ {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&mmc0_pins_emmc_51>;
- pinctrl-1 = <&mmc0_pins_emmc_51>;
- bus-width = <8>;
- max-frequency = <200000000>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- hs400-ds-delay = <0x12814>;
- vqmmc-supply = <®_1p8v>;
- vmmc-supply = <®_3p3v>;
- non-removable;
- no-sd;
- no-sdio;
- status = "okay";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&mdio_bus>;
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* external Aquantia AQR113C */
- phy0: ethernet-phy@0 {
- reg = <0>;
- compatible = "ethernet-phy-ieee802.3-c45";
- reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
- reset-assert-us = <100000>;
- reset-deassert-us = <221000>;
- };
- };
- };
-
- fragment@1 {
- target = <&gmac1>;
- __overlay__ {
- phy-mode = "usxgmii";
- phy-connection-type = "usxgmii";
- phy = <&phy0>;
- status = "okay";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&gmac1>;
- __overlay__ {
- phy-mode = "internal";
- phy-connection-type = "internal";
- phy = <&int_2p5g_phy>;
- status = "okay";
- };
- };
-
- fragment@1 {
- target = <&int_2p5g_phy>;
- __overlay__ {
- pinctrl-names = "i2p5gbe-led";
- pinctrl-0 = <&i2p5gbe_led0_pins>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&mdio_bus>;
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* external Maxlinear GPY211C */
- phy13: ethernet-phy@13 {
- reg = <13>;
- compatible = "ethernet-phy-ieee802.3-c45";
- phy-mode = "2500base-x";
- };
- };
- };
-
- fragment@1 {
- target = <&gmac1>;
- __overlay__ {
- phy-mode = "2500base-x";
- phy-connection-type = "2500base-x";
- phy = <&phy13>;
- status = "okay";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&i2c2>;
- __overlay__ {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_0_pins>;
- status = "okay";
- };
- };
-
- fragment@1 {
- target-path = "/";
- __overlay__ {
- sfp_esp1: sfp@1 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c2>;
- mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
- los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
- tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
- maximum-power-milliwatt = <3000>;
- };
- };
- };
-
- fragment@2 {
- target = <&gmac1>;
- __overlay__ {
- phy-mode = "10gbase-r";
- managed = "in-band-status";
- sfp = <&sfp_esp1>;
- status = "okay";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&mdio_bus>;
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* external Aquantia AQR113C */
- phy8: ethernet-phy@8 {
- reg = <8>;
- compatible = "ethernet-phy-ieee802.3-c45";
- reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
- reset-assert-us = <100000>;
- reset-deassert-us = <221000>;
- };
- };
- };
-
- fragment@1 {
- target = <&gmac2>;
- __overlay__ {
- phy-mode = "usxgmii";
- phy-connection-type = "usxgmii";
- phy = <&phy8>;
- status = "okay";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&mdio_bus>;
- __overlay__ {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* external Maxlinear GPY211C */
- phy5: ethernet-phy@5 {
- reg = <5>;
- compatible = "ethernet-phy-ieee802.3-c45";
- phy-mode = "2500base-x";
- };
- };
- };
-
- fragment@1 {
- target = <&gmac2>;
- __overlay__ {
- phy-mode = "2500base-x";
- phy-connection-type = "2500base-x";
- phy = <&phy5>;
- status = "okay";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&i2c1>;
- __overlay__ {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_sfp_pins>;
- status = "okay";
- };
- };
-
- fragment@1 {
- target-path = "/";
- __overlay__ {
- sfp_esp0: sfp@0 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
- los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
- tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
- maximum-power-milliwatt = <3000>;
- };
- };
- };
-
- fragment@2 {
- target = <&gmac2>;
- __overlay__ {
- phy-mode = "10gbase-r";
- managed = "in-band-status";
- sfp = <&sfp_esp0>;
- status = "okay";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Frank Wunderlich <frank-w@public-files.de>
- */
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@1 {
- target-path = <&mmc0>;
- __overlay__ {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&mmc0_pins_sdcard>;
- pinctrl-1 = <&mmc0_pins_sdcard>;
- cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- max-frequency = <52000000>;
- cap-sd-highspeed;
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_3p3v>;
- no-mmc;
- status = "okay";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&snand>;
- __overlay__ {
- status = "okay";
-
- flash@0 {
- compatible = "spi-nand";
- reg = <0>;
- spi-max-frequency = <52000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- mediatek,nmbm;
- mediatek,bmt-max-ratio = <1>;
- mediatek,bmt-max-reserved-blocks = <64>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "BL2";
- reg = <0x00000 0x0100000>;
- read-only;
- };
-
- partition@100000 {
- label = "u-boot-env";
- reg = <0x0100000 0x0080000>;
- };
-
- partition@180000 {
- label = "Factory";
- reg = <0x180000 0x0400000>;
- };
-
- partition@580000 {
- label = "FIP";
- reg = <0x580000 0x0200000>;
- };
-
- partition@780000 {
- label = "ubi";
- reg = <0x780000 0x7080000>;
- };
- };
- };
- };
- };
-
- fragment@1 {
- target = <&bch>;
- __overlay__ {
- status = "okay";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&spi0>;
- __overlay__ {
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_flash_pins>;
- status = "okay";
-
- flash@0 {
- compatible = "spi-nand";
- reg = <0>;
- spi-max-frequency = <52000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- mediatek,nmbm;
- mediatek,bmt-max-ratio = <1>;
- mediatek,bmt-max-reserved-blocks = <64>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "BL2";
- reg = <0x00000 0x0100000>;
- read-only;
- };
-
- partition@100000 {
- label = "u-boot-env";
- reg = <0x0100000 0x0080000>;
- };
-
- partition@180000 {
- label = "Factory";
- reg = <0x180000 0x0400000>;
- };
-
- partition@580000 {
- label = "FIP";
- reg = <0x580000 0x0200000>;
- };
-
- partition@780000 {
- label = "ubi";
- reg = <0x780000 0x7080000>;
- };
- };
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-/plugin/;
-
-/ {
- compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
-
- fragment@0 {
- target = <&spi2>;
- __overlay__ {
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_flash_pins>;
- status = "okay";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-cal-enable;
- spi-cal-mode = "read-data";
- spi-cal-datalen = <7>;
- spi-cal-data = /bits/ 8 <
- 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
- spi-cal-addrlen = <1>;
- spi-cal-addr = /bits/ 32 <0x0>;
- reg = <0>;
- spi-max-frequency = <52000000>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
-
- partition@00000 {
- label = "BL2";
- reg = <0x00000 0x0040000>;
- };
- partition@40000 {
- label = "u-boot-env";
- reg = <0x40000 0x0010000>;
- };
- partition@50000 {
- label = "Factory";
- reg = <0x50000 0x0200000>;
- };
- partition@250000 {
- label = "FIP";
- reg = <0x250000 0x0080000>;
- };
- partition@2D0000 {
- label = "firmware";
- reg = <0x2D0000 0x1D30000>;
- };
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2022 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-/dts-v1/;
-#include "mt7988a.dtsi"
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
-
-/ {
- model = "MediaTek MT7988A Reference Board";
- compatible = "mediatek,mt7988a-rfb",
- "mediatek,mt7988";
-
- chosen {
- bootargs = "console=ttyS0,115200n1 loglevel=8 \
- earlycon=uart8250,mmio32,0x11000000 \
- pci=pcie_bus_perf";
- };
-
- memory {
- reg = <0 0x40000000 0 0x40000000>;
- };
-};
-
-ð {
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-};
-
-&gmac0 {
- status = "okay";
-};
-
-&cpu0 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cpu1 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cpu2 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cpu3 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cci {
- proc-supply = <&rt5190_buck3>;
-};
-
-ð {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&gsw_phy0 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe0_led0_pins>;
-};
-
-&gsw_phy0_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy1 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe1_led0_pins>;
-};
-
-&gsw_phy1_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy2 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe2_led0_pins>;
-};
-
-&gsw_phy2_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy3 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe3_led0_pins>;
-};
-
-&gsw_phy3_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
-
- rt5190a_64: rt5190a@64 {
- compatible = "richtek,rt5190a";
- reg = <0x64>;
- /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
- vin2-supply = <&rt5190_buck1>;
- vin3-supply = <&rt5190_buck1>;
- vin4-supply = <&rt5190_buck1>;
-
- regulators {
- rt5190_buck1: buck1 {
- regulator-name = "rt5190a-buck1";
- regulator-min-microvolt = <5090000>;
- regulator-max-microvolt = <5090000>;
- regulator-allowed-modes =
- <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
- regulator-boot-on;
- regulator-always-on;
- };
- buck2 {
- regulator-name = "vcore";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
- rt5190_buck3: buck3 {
- regulator-name = "vproc";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- };
- buck4 {
- regulator-name = "rt5190a-buck4";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-allowed-modes =
- <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
- regulator-boot-on;
- regulator-always-on;
- };
- ldo {
- regulator-name = "rt5190a-ldo";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
-};
-
-&pcie2 {
- status = "disabled";
-};
-
-&pcie3 {
- status = "okay";
-};
-
-&ssusb0 {
- status = "okay";
-};
-
-&ssusb1 {
- status = "okay";
-};
-
-&tphy {
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&xphy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (C) 2023 MediaTek Inc.
- * Author: Sam.Shih <sam.shih@mediatek.com>
- */
-
-#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/reset/mediatek,mt7988-resets.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/* TOPRGU resets */
-#define MT7988_TOPRGU_SGMII0_GRST 1
-#define MT7988_TOPRGU_SGMII1_GRST 2
-#define MT7988_TOPRGU_XFI0_GRST 12
-#define MT7988_TOPRGU_XFI1_GRST 13
-#define MT7988_TOPRGU_XFI_PEXTP0_GRST 14
-#define MT7988_TOPRGU_XFI_PEXTP1_GRST 15
-#define MT7988_TOPRGU_XFI_PLL_GRST 16
-
-/ {
- compatible = "mediatek,mt7988";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- cci: cci {
- compatible = "mediatek,mt7988-cci",
- "mediatek,mt8183-cci";
- clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
- <&topckgen CLK_TOP_XTAL>;
- clock-names = "cci", "intermediate";
- operating-points-v2 = <&cci_opp>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a73";
- reg = <0x0>;
- device_type = "cpu";
- enable-method = "psci";
- clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
- <&topckgen CLK_TOP_XTAL>;
- clock-names = "cpu", "intermediate";
- operating-points-v2 = <&cluster0_opp>;
- mediatek,cci = <&cci>;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a73";
- reg = <0x1>;
- device_type = "cpu";
- enable-method = "psci";
- clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
- <&topckgen CLK_TOP_XTAL>;
- clock-names = "cpu", "intermediate";
- operating-points-v2 = <&cluster0_opp>;
- mediatek,cci = <&cci>;
- };
-
- cpu2: cpu@2 {
- compatible = "arm,cortex-a73";
- reg = <0x2>;
- device_type = "cpu";
- enable-method = "psci";
- clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
- <&topckgen CLK_TOP_XTAL>;
- clock-names = "cpu", "intermediate";
- operating-points-v2 = <&cluster0_opp>;
- mediatek,cci = <&cci>;
- };
-
- cpu3: cpu@3 {
- compatible = "arm,cortex-a73";
- reg = <0x3>;
- device_type = "cpu";
- enable-method = "psci";
- clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
- <&topckgen CLK_TOP_XTAL>;
- clock-names = "cpu", "intermediate";
- operating-points-v2 = <&cluster0_opp>;
- mediatek,cci = <&cci>;
- };
-
- cluster0_opp: opp_table0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <850000>;
- };
-
- opp01 {
- opp-hz = /bits/ 64 <1100000000>;
- opp-microvolt = <850000>;
- };
-
- opp02 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <850000>;
- };
-
- opp03 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <900000>;
- };
- };
- };
-
- cci_opp: opp_table_cci {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <480000000>;
- opp-microvolt = <850000>;
- };
-
- opp01 {
- opp-hz = /bits/ 64 <660000000>;
- opp-microvolt = <850000>;
- };
-
- opp02 {
- opp-hz = /bits/ 64 <900000000>;
- opp-microvolt = <850000>;
- };
-
- opp03 {
- opp-hz = /bits/ 64 <1080000000>;
- opp-microvolt = <900000>;
- };
- };
-
- clk40m: oscillator@0 {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- #clock-cells = <0>;
- clock-output-names = "clkxtal";
- };
-
- fan: pwm-fan {
- compatible = "pwm-fan";
- /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
- cooling-levels = <0 128 255>;
- #cooling-cells = <2>;
- #thermal-sensor-cells = <1>;
- status = "disabled";
- };
-
- pmu {
- compatible = "arm,cortex-a73-pmu";
- interrupt-parent = <&gic>;
- interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reserved-memory {
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
-
- /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
- secmon_reserved: secmon@43000000 {
- reg = <0 0x43000000 0 0x50000>;
- no-map;
- };
- };
-
- soc {
- compatible = "simple-bus";
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
-
- gic: interrupt-controller@c000000 {
- compatible = "arm,gic-v3";
- reg = <0 0x0c000000 0 0x40000>, /* GICD */
- <0 0x0c080000 0 0x200000>, /* GICR */
- <0 0x0c400000 0 0x2000>, /* GICC */
- <0 0x0c410000 0 0x1000>, /* GICH */
- <0 0x0c420000 0 0x2000>; /* GICV */
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <3>;
- };
-
- phyfw: phy-firmware@f000000 {
- compatible = "mediatek,2p5gphy-fw";
- reg = <0 0x0f100000 0 0x20000>,
- <0 0x0f0f0018 0 0x20>;
- };
-
- infracfg: infracfg@10001000 {
- compatible = "mediatek,mt7988-infracfg", "syscon";
- reg = <0 0x10001000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- topckgen: topckgen@1001b000 {
- compatible = "mediatek,mt7988-topckgen", "syscon";
- reg = <0 0x1001b000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- watchdog: watchdog@1001c000 {
- compatible = "mediatek,mt7988-wdt",
- "mediatek,mt6589-wdt",
- "syscon";
- reg = <0 0x1001c000 0 0x1000>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- #reset-cells = <1>;
- };
-
- apmixedsys: apmixedsys@1001e000 {
- compatible = "mediatek,mt7988-apmixedsys";
- reg = <0 0x1001e000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- pio: pinctrl@1001f000 {
- compatible = "mediatek,mt7988-pinctrl", "syscon";
- reg = <0 0x1001f000 0 0x1000>,
- <0 0x11c10000 0 0x1000>,
- <0 0x11d00000 0 0x1000>,
- <0 0x11d20000 0 0x1000>,
- <0 0x11e00000 0 0x1000>,
- <0 0x11f00000 0 0x1000>,
- <0 0x1000b000 0 0x1000>;
- reg-names = "gpio_base", "iocfg_tr_base",
- "iocfg_br_base", "iocfg_rb_base",
- "iocfg_lb_base", "iocfg_tl_base", "eint";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pio 0 0 84>;
- interrupt-controller;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- #interrupt-cells = <2>;
-
- mdio0_pins: mdio0-pins {
- mux {
- function = "eth";
- groups = "mdc_mdio0";
- };
-
- conf {
- groups = "mdc_mdio0";
- drive-strength = <MTK_DRIVE_8mA>;
- };
- };
-
- i2c0_pins: i2c0-pins-g0 {
- mux {
- function = "i2c";
- groups = "i2c0_1";
- };
- };
-
- i2c1_pins: i2c1-pins-g0 {
- mux {
- function = "i2c";
- groups = "i2c1_0";
- };
- };
-
- i2c1_sfp_pins: i2c1-sfp-pins-g0 {
- mux {
- function = "i2c";
- groups = "i2c1_sfp";
- };
- };
-
- i2c2_pins: i2c2-pins {
- mux {
- function = "i2c";
- groups = "i2c2";
- };
- };
-
- i2c2_0_pins: i2c2-pins-g0 {
- mux {
- function = "i2c";
- groups = "i2c2_0";
- };
- };
-
- i2c2_1_pins: i2c2-pins-g1 {
- mux {
- function = "i2c";
- groups = "i2c2_1";
- };
- };
-
- gbe0_led0_pins: gbe0-led0-pins {
- mux {
- function = "led";
- groups = "gbe0_led0";
- };
- };
-
- gbe1_led0_pins: gbe1-led0-pins {
- mux {
- function = "led";
- groups = "gbe1_led0";
- };
- };
-
- gbe2_led0_pins: gbe2-led0-pins {
- mux {
- function = "led";
- groups = "gbe2_led0";
- };
- };
-
- gbe3_led0_pins: gbe3-led0-pins {
- mux {
- function = "led";
- groups = "gbe3_led0";
- };
- };
-
- gbe0_led1_pins: gbe0-led1-pins {
- mux {
- function = "led";
- groups = "gbe0_led1";
- };
- };
-
- gbe1_led1_pins: gbe1-led1-pins {
- mux {
- function = "led";
- groups = "gbe1_led1";
- };
- };
-
- gbe2_led1_pins: gbe2-led1-pins {
- mux {
- function = "led";
- groups = "gbe2_led1";
- };
- };
-
- gbe3_led1_pins: gbe3-led1-pins {
- mux {
- function = "led";
- groups = "gbe3_led1";
- };
- };
-
- i2p5gbe_led0_pins: 2p5gbe-led0-pins {
- mux {
- function = "led";
- groups = "2p5gbe_led0";
- };
- };
-
- i2p5gbe_led1_pins: 2p5gbe-led1-pins {
- mux {
- function = "led";
- groups = "2p5gbe_led1";
- };
- };
-
- mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
- mux {
- function = "flash";
- groups = "emmc_45";
- };
- };
-
- mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
- mux {
- function = "flash";
- groups = "emmc_51";
- };
- };
-
- mmc0_pins_sdcard: mmc0-pins-sdcard {
- mux {
- function = "flash";
- groups = "sdcard";
- };
- };
-
- uart0_pins: uart0-pins {
- mux {
- function = "uart";
- groups = "uart0";
- };
- };
-
- uart1_0_pins: uart1-0-pins {
- mux {
- function = "uart";
- groups = "uart1_0";
- };
- };
-
- uart1_1_pins: uart1-1-pins {
- mux {
- function = "uart";
- groups = "uart1_1";
- };
- };
-
- uart1_2_pins: uart1-2-pins {
- mux {
- function = "uart";
- groups = "uart1_2";
- };
- };
-
- uart1_2_lite_pins: uart1-2-lite-pins {
- mux {
- function = "uart";
- groups = "uart1_2_lite";
- };
- };
-
- uart2_pins: uart2-pins {
- mux {
- function = "uart";
- groups = "uart2";
- };
- };
-
- uart2_0_pins: uart2-0-pins {
- mux {
- function = "uart";
- groups = "uart2_0";
- };
- };
-
- uart2_1_pins: uart2-1-pins {
- mux {
- function = "uart";
- groups = "uart2_1";
- };
- };
-
- uart2_2_pins: uart2-2-pins {
- mux {
- function = "uart";
- groups = "uart2_2";
- };
- };
-
- uart2_3_pins: uart2-3-pins {
- mux {
- function = "uart";
- groups = "uart2_3";
- };
- };
-
- snfi_pins: snfi-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- spi0_pins: spi0-pins {
- mux {
- function = "spi";
- groups = "spi0";
- };
- };
-
- spi0_flash_pins: spi0-flash-pins {
- mux {
- function = "spi";
- groups = "spi0", "spi0_wp_hold";
- };
- };
-
- spi1_pins: spi1-pins {
- mux {
- function = "spi";
- groups = "spi1";
- };
- };
-
- spi2_pins: spi2-pins {
- mux {
- function = "spi";
- groups = "spi2";
- };
- };
-
- spi2_flash_pins: spi2-flash-pins {
- mux {
- function = "spi";
- groups = "spi2", "spi2_wp_hold";
- };
- };
-
- pcie0_pins: pcie0-pins {
- mux {
- function = "pcie";
- groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
- "pcie_wake_n0_0";
- };
- };
-
- pcie1_pins: pcie1-pins {
- mux {
- function = "pcie";
- groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
- "pcie_wake_n1_0";
- };
- };
-
- pcie2_pins: pcie2-pins {
- mux {
- function = "pcie";
- groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
- "pcie_wake_n2_0";
- };
- };
-
- pcie3_pins: pcie3-pins {
- mux {
- function = "pcie";
- groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
- "pcie_wake_n3_0";
- };
- };
- };
-
- pwm: pwm@10048000 {
- compatible = "mediatek,mt7988-pwm";
- reg = <0 0x10048000 0 0x1000>;
- #pwm-cells = <2>;
- clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
- <&infracfg CLK_INFRA_66M_PWM_HCK>,
- <&infracfg CLK_INFRA_66M_PWM_CK1>,
- <&infracfg CLK_INFRA_66M_PWM_CK2>,
- <&infracfg CLK_INFRA_66M_PWM_CK3>,
- <&infracfg CLK_INFRA_66M_PWM_CK4>,
- <&infracfg CLK_INFRA_66M_PWM_CK5>,
- <&infracfg CLK_INFRA_66M_PWM_CK6>,
- <&infracfg CLK_INFRA_66M_PWM_CK7>,
- <&infracfg CLK_INFRA_66M_PWM_CK8>;
- clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
- "pwm4","pwm5","pwm6","pwm7","pwm8";
- status = "disabled";
- };
-
- sgmiisys0: syscon@10060000 {
- compatible = "mediatek,mt7988-sgmiisys",
- "mediatek,mt7988-sgmiisys0",
- "syscon",
- "simple-mfd";
- reg = <0 0x10060000 0 0x1000>;
- resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
- #clock-cells = <1>;
-
- sgmiipcs0: pcs {
- compatible = "mediatek,mt7988-sgmii";
- clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
- <&sgmiisys0 CLK_SGM0_TX_EN>,
- <&sgmiisys0 CLK_SGM0_RX_EN>;
- clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
- };
- };
-
- sgmiisys1: syscon@10070000 {
- compatible = "mediatek,mt7988-sgmiisys",
- "mediatek,mt7988-sgmiisys1",
- "syscon",
- "simple-mfd";
- reg = <0 0x10070000 0 0x1000>;
- resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
- #clock-cells = <1>;
-
- sgmiipcs1: pcs {
- compatible = "mediatek,mt7988-sgmii";
- clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
- <&sgmiisys1 CLK_SGM1_TX_EN>,
- <&sgmiisys1 CLK_SGM1_RX_EN>;
- clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
- };
- };
-
- usxgmiisys0: pcs@10080000 {
- compatible = "mediatek,mt7988-usxgmiisys";
- reg = <0 0x10080000 0 0x1000>;
- resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
- clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
- };
-
- usxgmiisys1: pcs@10081000 {
- compatible = "mediatek,mt7988-usxgmiisys";
- reg = <0 0x10081000 0 0x1000>;
- resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
- clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
- };
-
- mcusys: mcusys@100e0000 {
- compatible = "mediatek,mt7988-mcusys", "syscon";
- reg = <0 0x100e0000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- uart0: serial@11000000 {
- compatible = "mediatek,mt7986-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11000000 0 0x100>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- /*
- * 8250-mtk driver don't control "baud" clock since commit
- * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
- * still need to be passed to the driver to prevent probe fail
- */
- clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&infracfg CLK_INFRA_52M_UART0_CK>;
- clock-names = "baud", "bus";
- assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&infracfg CLK_INFRA_MUX_UART0_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
- <&topckgen CLK_TOP_UART_SEL>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "disabled";
- };
-
- uart1: serial@11000100 {
- compatible = "mediatek,mt7986-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11000100 0 0x100>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- /*
- * 8250-mtk driver don't control "baud" clock since commit
- * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
- * still need to be passed to the driver to prevent probe fail
- */
- clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&infracfg CLK_INFRA_52M_UART1_CK>;
- clock-names = "baud", "bus";
- assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&infracfg CLK_INFRA_MUX_UART1_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
- <&topckgen CLK_TOP_UART_SEL>;
- status = "disabled";
- };
-
- uart2: serial@11000200 {
- compatible = "mediatek,mt7986-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11000200 0 0x100>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- /*
- * 8250-mtk driver don't control "baud" clock since commit
- * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
- * still need to be passed to the driver to prevent probe fail
- */
- clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&infracfg CLK_INFRA_52M_UART2_CK>;
- clock-names = "baud", "bus";
- assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&infracfg CLK_INFRA_MUX_UART2_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
- <&topckgen CLK_TOP_UART_SEL>;
- status = "disabled";
- };
-
- snand: spi@11001000 {
- compatible = "mediatek,mt7986-snand";
- reg = <0 0x11001000 0 0x1000>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_SPINFI>,
- <&infracfg CLK_INFRA_NFI>;
- clock-names = "pad_clk", "nfi_clk";
- assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
- <&topckgen CLK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
- <&topckgen CLK_TOP_MPLL_D8>;
- nand-ecc-engine = <&bch>;
- mediatek,quad-spi;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&snfi_pins>;
- status = "disabled";
- };
-
- bch: ecc@11002000 {
- compatible = "mediatek,mt7686-ecc";
- reg = <0 0x11002000 0 0x1000>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
- clock-names = "nfiecc_clk";
- status = "disabled";
- };
-
- i2c0: i2c@11003000 {
- compatible = "mediatek,mt7988-i2c",
- "mediatek,mt7981-i2c";
- reg = <0 0x11003000 0 0x1000>,
- <0 0x10217080 0 0x80>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clock-div = <1>;
- clocks = <&infracfg CLK_INFRA_I2C_BCK>,
- <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
- clock-names = "main", "dma";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@11004000 {
- compatible = "mediatek,mt7988-i2c",
- "mediatek,mt7981-i2c";
- reg = <0 0x11004000 0 0x1000>,
- <0 0x10217100 0 0x80>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clock-div = <1>;
- clocks = <&infracfg CLK_INFRA_I2C_BCK>,
- <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
- clock-names = "main", "dma";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@11005000 {
- compatible = "mediatek,mt7988-i2c",
- "mediatek,mt7981-i2c";
- reg = <0 0x11005000 0 0x1000>,
- <0 0x10217180 0 0x80>;
- interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- clock-div = <1>;
- clocks = <&infracfg CLK_INFRA_I2C_BCK>,
- <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
- clock-names = "main", "dma";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi0: spi@11007000 {
- compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
- reg = <0 0x11007000 0 0x100>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_MPLL_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
- <&infracfg CLK_INFRA_104M_SPI0>,
- <&infracfg CLK_INFRA_66M_SPI0_HCK>;
- clock-names = "parent-clk", "sel-clk", "spi-clk",
- "spi-hclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@11008000 {
- compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
- reg = <0 0x11008000 0 0x100>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_MPLL_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
- <&infracfg CLK_INFRA_104M_SPI1>,
- <&infracfg CLK_INFRA_66M_SPI1_HCK>;
- clock-names = "parent-clk", "sel-clk", "spi-clk",
- "spi-hclk";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins>;
- status = "disabled";
- };
-
- spi2: spi@11009000 {
- compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
- reg = <0 0x11009000 0 0x100>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CLK_TOP_MPLL_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
- <&infracfg CLK_INFRA_104M_SPI2_BCK>,
- <&infracfg CLK_INFRA_66M_SPI2_HCK>;
- clock-names = "parent-clk", "sel-clk", "spi-clk",
- "spi-hclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- lvts: lvts@1100a000 {
- compatible = "mediatek,mt7988-lvts-ap";
- reg = <0 0x1100a000 0 0x1000>;
- clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
- clock-names = "lvts_clk";
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
- nvmem-cells = <&lvts_calibration>;
- nvmem-cell-names = "lvts-calib-data-1";
- #thermal-sensor-cells = <1>;
- };
-
- ssusb0: usb@11190000 {
- compatible = "mediatek,mt7988-xhci",
- "mediatek,mtk-xhci";
- reg = <0 0x11190000 0 0x2e00>,
- <0 0x11193e00 0 0x0100>;
- reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&xphyu2port0 PHY_TYPE_USB2>,
- <&xphyu3port0 PHY_TYPE_USB3>;
- clocks = <&infracfg CLK_INFRA_USB_SYS>,
- <&infracfg CLK_INFRA_USB_XHCI>,
- <&infracfg CLK_INFRA_USB_REF>,
- <&infracfg CLK_INFRA_66M_USB_HCK>,
- <&infracfg CLK_INFRA_133M_USB_HCK>;
- clock-names = "sys_ck",
- "xhci_ck",
- "ref_ck",
- "mcu_ck",
- "dma_ck";
- #address-cells = <2>;
- #size-cells = <2>;
- mediatek,p0_speed_fixup;
- status = "disabled";
- };
-
- ssusb1: usb@11200000 {
- compatible = "mediatek,mt7988-xhci",
- "mediatek,mtk-xhci";
- reg = <0 0x11200000 0 0x2e00>,
- <0 0x11203e00 0 0x0100>;
- reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&tphyu2port0 PHY_TYPE_USB2>,
- <&tphyu3port0 PHY_TYPE_USB3>;
- clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
- <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
- <&infracfg CLK_INFRA_USB_CK_P1>,
- <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
- <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
- clock-names = "sys_ck",
- "xhci_ck",
- "ref_ck",
- "mcu_ck",
- "dma_ck";
- #address-cells = <2>;
- #size-cells = <2>;
- status = "disabled";
- };
-
- afe: audio-controller@11210000 {
- compatible = "mediatek,mt79xx-audio";
- reg = <0 0x11210000 0 0x9000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
- <&infracfg CLK_INFRA_AUD_26M>,
- <&infracfg CLK_INFRA_AUD_L>,
- <&infracfg CLK_INFRA_AUD_AUD>,
- <&infracfg CLK_INFRA_AUD_EG2>,
- <&topckgen CLK_TOP_AUD_SEL>,
- <&topckgen CLK_TOP_AUD_I2S_M>;
- clock-names = "aud_bus_ck",
- "aud_26m_ck",
- "aud_l_ck",
- "aud_aud_ck",
- "aud_eg2_ck",
- "aud_sel",
- "aud_i2s_m";
- assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
- <&topckgen CLK_TOP_A1SYS_SEL>,
- <&topckgen CLK_TOP_AUD_L_SEL>,
- <&topckgen CLK_TOP_A_TUNER_SEL>;
- assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
- <&topckgen CLK_TOP_APLL2_D4>,
- <&apmixedsys CLK_APMIXED_APLL2>,
- <&topckgen CLK_TOP_APLL2_D4>;
- status = "disabled";
- };
-
- mmc0: mmc@11230000 {
- compatible = "mediatek,mt7986-mmc",
- "mediatek,mt7981-mmc";
- reg = <0 0x11230000 0 0x1000>,
- <0 0x11D60000 0 0x1000>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CLK_INFRA_MSDC400>,
- <&infracfg CLK_INFRA_MSDC2_HCK>,
- <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
- <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
- assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
- <&topckgen CLK_TOP_EMMC_400M_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
- <&apmixedsys CLK_APMIXED_MSDCPLL>;
- clock-names = "source",
- "hclk",
- "axi_cg",
- "ahb_cg";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pcie2: pcie@11280000 {
- compatible = "mediatek,mt7988-pcie",
- "mediatek,mt7986-pcie",
- "mediatek,mt8192-pcie";
- reg = <0 0x11280000 0 0x2000>;
- reg-names = "pcie-mac";
- ranges = <0x81000000 0x00 0x20000000 0x00
- 0x20000000 0x00 0x00200000>,
- <0x82000000 0x00 0x20200000 0x00
- 0x20200000 0x00 0x07e00000>;
- device_type = "pci";
- linux,pci-domain = <3>;
- interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
- bus-range = <0x00 0xff>;
- clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
- <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
- <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
- <&infracfg CLK_INFRA_133M_PCIE_CK_P2>,
- <&topckgen CLK_TOP_PEXTP_P2_SEL>;
- clock-names = "pl_250m", "tl_26m", "peri_26m",
- "top_133m", "pextp_clk";
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_pins>;
- phys = <&xphyu3port0 PHY_TYPE_PCIE>;
- phy-names = "pcie-phy";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &pcie_intc2 0>,
- <0 0 0 2 &pcie_intc2 1>,
- <0 0 0 3 &pcie_intc2 2>,
- <0 0 0 4 &pcie_intc2 3>;
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie_intc2: interrupt-controller {
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
- };
-
- pcie3: pcie@11290000 {
- compatible = "mediatek,mt7988-pcie",
- "mediatek,mt7986-pcie",
- "mediatek,mt8192-pcie";
- reg = <0 0x11290000 0 0x2000>;
- reg-names = "pcie-mac";
- ranges = <0x81000000 0x00 0x28000000 0x00
- 0x28000000 0x00 0x00200000>,
- <0x82000000 0x00 0x28200000 0x00
- 0x28200000 0x00 0x07e00000>;
- device_type = "pci";
- linux,pci-domain = <2>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
- bus-range = <0x00 0xff>;
- clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
- <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
- <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
- <&infracfg CLK_INFRA_133M_PCIE_CK_P3>,
- <&topckgen CLK_TOP_PEXTP_P3_SEL>;
- clock-names = "pl_250m", "tl_26m", "peri_26m",
- "top_133m", "pextp_clk";
- pinctrl-names = "default";
- pinctrl-0 = <&pcie3_pins>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &pcie_intc3 0>,
- <0 0 0 2 &pcie_intc3 1>,
- <0 0 0 3 &pcie_intc3 2>,
- <0 0 0 4 &pcie_intc3 3>;
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie_intc3: interrupt-controller {
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
- };
-
- pcie0: pcie@11300000 {
- compatible = "mediatek,mt7988-pcie",
- "mediatek,mt7986-pcie",
- "mediatek,mt8192-pcie";
- reg = <0 0x11300000 0 0x2000>;
- reg-names = "pcie-mac";
- ranges = <0x81000000 0x00 0x30000000 0x00
- 0x30000000 0x00 0x00200000>,
- <0x82000000 0x00 0x30200000 0x00
- 0x30200000 0x00 0x07e00000>;
- device_type = "pci";
- linux,pci-domain = <0>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- bus-range = <0x00 0xff>;
- clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
- <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
- <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
- <&infracfg CLK_INFRA_133M_PCIE_CK_P0>,
- <&topckgen CLK_TOP_PEXTP_P0_SEL>;
- clock-names = "pl_250m", "tl_26m", "peri_26m",
- "top_133m", "pextp_clk";
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_pins>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
- <0 0 0 2 &pcie_intc0 1>,
- <0 0 0 3 &pcie_intc0 2>,
- <0 0 0 4 &pcie_intc0 3>;
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie_intc0: interrupt-controller {
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
- };
-
- pcie1: pcie@11310000 {
- compatible = "mediatek,mt7988-pcie",
- "mediatek,mt7986-pcie",
- "mediatek,mt8192-pcie";
- reg = <0 0x11310000 0 0x2000>;
- reg-names = "pcie-mac";
- ranges = <0x81000000 0x00 0x38000000 0x00
- 0x38000000 0x00 0x00200000>,
- <0x82000000 0x00 0x38200000 0x00
- 0x38200000 0x00 0x07e00000>;
- device_type = "pci";
- linux,pci-domain = <1>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- bus-range = <0x00 0xff>;
- clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
- <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
- <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
- <&infracfg CLK_INFRA_133M_PCIE_CK_P1>,
- <&topckgen CLK_TOP_PEXTP_P1_SEL>;
- clock-names = "pl_250m", "tl_26m", "peri_26m",
- "top_133m", "pextp_clk";
- pinctrl-names = "default";
- pinctrl-0 = <&pcie1_pins>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
- <0 0 0 2 &pcie_intc1 1>,
- <0 0 0 3 &pcie_intc1 2>,
- <0 0 0 4 &pcie_intc1 3>;
- #address-cells = <3>;
- #size-cells = <2>;
- status = "disabled";
-
- pcie_intc1: interrupt-controller {
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
- };
-
- tphy: tphy@11c50000 {
- compatible = "mediatek,mt7988",
- "mediatek,generic-tphy-v2";
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
- status = "disabled";
-
- tphyu2port0: usb-phy@11c50000 {
- reg = <0 0x11c50000 0 0x700>;
- clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
-
- tphyu3port0: usb-phy@11c50700 {
- reg = <0 0x11c50700 0 0x900>;
- clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
- clock-names = "ref";
- #phy-cells = <1>;
- mediatek,usb3-pll-ssc-delta;
- mediatek,usb3-pll-ssc-delta1;
- };
- };
-
- topmisc: topmisc@11d10000 {
- compatible = "mediatek,mt7988-topmisc", "syscon",
- "mediatek,mt7988-power-controller";
- reg = <0 0x11d10000 0 0x10000>;
- #clock-cells = <1>;
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- xphy: xphy@11e10000 {
- compatible = "mediatek,mt7988",
- "mediatek,xsphy";
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
- status = "disabled";
-
- xphyu2port0: usb-phy@11e10000 {
- reg = <0 0x11e10000 0 0x400>;
- clocks = <&infracfg CLK_INFRA_USB_UTMI>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
-
- xphyu3port0: usb-phy@11e13000 {
- reg = <0 0x11e13400 0 0x500>;
- clocks = <&infracfg CLK_INFRA_USB_PIPE>;
- clock-names = "ref";
- #phy-cells = <1>;
- mediatek,syscon-type = <&topmisc 0x218 0>;
- };
- };
-
- xfi_tphy0: phy@11f20000 {
- compatible = "mediatek,mt7988-xfi-tphy";
- reg = <0 0x11f20000 0 0x10000>;
- resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
- clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
- clock-names = "xfipll", "topxtal";
- mediatek,usxgmii-performance-errata;
- #phy-cells = <0>;
- };
-
- xfi_tphy1: phy@11f30000 {
- compatible = "mediatek,mt7988-xfi-tphy";
- reg = <0 0x11f30000 0 0x10000>;
- resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
- clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
- clock-names = "xfipll", "topxtal";
- #phy-cells = <0>;
- };
-
- xfi_pll: clock-controller@11f40000 {
- compatible = "mediatek,mt7988-xfi-pll";
- reg = <0 0x11f40000 0 0x1000>;
- resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
- #clock-cells = <1>;
- };
-
- efuse: efuse@11f50000 {
- compatible = "mediatek,efuse";
- reg = <0 0x11f50000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- lvts_calibration: calib@918 {
- reg = <0x918 0x28>;
- };
-
- phy_calibration_p0: calib@940 {
- reg = <0x940 0x10>;
- };
-
- phy_calibration_p1: calib@954 {
- reg = <0x954 0x10>;
- };
-
- phy_calibration_p2: calib@968 {
- reg = <0x968 0x10>;
- };
-
- phy_calibration_p3: calib@97c {
- reg = <0x97c 0x10>;
- };
-
- cpufreq_calibration: calib@278 {
- reg = <0x278 0x1>;
- };
- };
-
- ethsys: syscon@15000000 {
- compatible = "mediatek,mt7988-ethsys", "syscon";
- reg = <0 0x15000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- switch: switch@15020000 {
- compatible = "mediatek,mt7988-switch";
- reg = <0 0x15020000 0 0x8000>;
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
- resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- gsw_port0: port@0 {
- reg = <0>;
- label = "lan0";
- phy-mode = "internal";
- phy-handle = <&gsw_phy0>;
- };
-
- gsw_port1: port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&gsw_phy1>;
- };
-
- gsw_port2: port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&gsw_phy2>;
- };
-
- gsw_port3: port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&gsw_phy3>;
- };
-
- port@6 {
- reg = <6>;
- ethernet = <&gmac0>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <10000>;
- full-duplex;
- pause;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- mediatek,pio = <&pio>;
-
- gsw_phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- phy-mode = "internal";
- nvmem-cells = <&phy_calibration_p0>;
- nvmem-cell-names = "phy-cal-data";
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- gsw_phy0_led0: gsw-phy0-led0@0 {
- reg = <0>;
- function = LED_FUNCTION_LAN;
- status = "disabled";
- };
-
- gsw_phy0_led1: gsw-phy0-led1@1 {
- reg = <1>;
- function = LED_FUNCTION_LAN;
- status = "disabled";
- };
- };
- };
-
- gsw_phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- phy-mode = "internal";
- nvmem-cells = <&phy_calibration_p1>;
- nvmem-cell-names = "phy-cal-data";
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- gsw_phy1_led0: gsw-phy1-led0@0 {
- reg = <0>;
- function = LED_FUNCTION_LAN;
- status = "disabled";
- };
-
- gsw_phy1_led1: gsw-phy1-led1@1 {
- reg = <1>;
- function = LED_FUNCTION_LAN;
- status = "disabled";
- };
- };
- };
-
- gsw_phy2: ethernet-phy@2 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <2>;
- phy-mode = "internal";
- nvmem-cells = <&phy_calibration_p2>;
- nvmem-cell-names = "phy-cal-data";
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- gsw_phy2_led0: gsw-phy2-led0@0 {
- reg = <0>;
- function = LED_FUNCTION_LAN;
- status = "disabled";
- };
-
- gsw_phy2_led1: gsw-phy2-led1@1 {
- reg = <1>;
- function = LED_FUNCTION_LAN;
- status = "disabled";
- };
- };
- };
-
- gsw_phy3: ethernet-phy@3 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <3>;
- phy-mode = "internal";
- nvmem-cells = <&phy_calibration_p3>;
- nvmem-cell-names = "phy-cal-data";
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- gsw_phy3_led0: gsw-phy3-led0@0 {
- reg = <0>;
- function = LED_FUNCTION_LAN;
- status = "disabled";
- };
-
- gsw_phy3_led1: gsw-phy3-led1@1 {
- reg = <1>;
- function = LED_FUNCTION_LAN;
- status = "disabled";
- };
- };
- };
- };
- };
-
- ethwarp: clock-controller@15031000 {
- compatible = "mediatek,mt7988-ethwarp";
- reg = <0 0x15031000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- eth: ethernet@15100000 {
- compatible = "mediatek,mt7988-eth";
- reg = <0 0x15100000 0 0x80000>,
- <0 0x15400000 0 0x380000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <ðsys CLK_ETHDMA_XGP1_EN>,
- <ðsys CLK_ETHDMA_XGP2_EN>,
- <ðsys CLK_ETHDMA_XGP3_EN>,
- <ðsys CLK_ETHDMA_FE_EN>,
- <ðsys CLK_ETHDMA_GP2_EN>,
- <ðsys CLK_ETHDMA_GP1_EN>,
- <ðsys CLK_ETHDMA_GP3_EN>,
- <ðsys CLK_ETHDMA_ESW_EN>,
- <ðsys CLK_ETHDMA_CRYPT0_EN>,
- <ðwarp CLK_ETHWARP_WOCPU2_EN>,
- <ðwarp CLK_ETHWARP_WOCPU1_EN>,
- <ðwarp CLK_ETHWARP_WOCPU0_EN>,
- <&topckgen CLK_TOP_ETH_GMII_SEL>,
- <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
- <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
- <&topckgen CLK_TOP_ETH_SYS_SEL>,
- <&topckgen CLK_TOP_ETH_XGMII_SEL>,
- <&topckgen CLK_TOP_ETH_MII_SEL>,
- <&topckgen CLK_TOP_NETSYS_SEL>,
- <&topckgen CLK_TOP_NETSYS_500M_SEL>,
- <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
- <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
- <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
- <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
- clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
- "gp3", "esw", "crypto",
- "ethwarp_wocpu2", "ethwarp_wocpu1",
- "ethwarp_wocpu0", "top_eth_gmii_sel",
- "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
- "top_eth_sys_sel", "top_eth_xgmii_sel",
- "top_eth_mii_sel", "top_netsys_sel",
- "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
- "top_netsys_sync_250m_sel",
- "top_netsys_ppefb_250m_sel",
- "top_netsys_warp_sel";
- assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
- <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
- <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
- <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
- <&topckgen CLK_TOP_SGM_0_SEL>,
- <&topckgen CLK_TOP_SGM_1_SEL>;
- assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
- <&topckgen CLK_TOP_NET1PLL_D4>,
- <&topckgen CLK_TOP_NET1PLL_D8_D4>,
- <&topckgen CLK_TOP_NET1PLL_D8_D4>,
- <&apmixedsys CLK_APMIXED_SGMPLL>,
- <&apmixedsys CLK_APMIXED_SGMPLL>;
- mediatek,ethsys = <ðsys>;
- mediatek,infracfg = <&topmisc>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gmac0: mac@0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "internal";
- status = "disabled";
-
- fixed-link {
- speed = <10000>;
- full-duplex;
- pause;
- };
- };
-
- gmac1: mac@1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- status = "disabled";
- pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
- phys = <&xfi_tphy1>;
- };
-
- gmac2: mac@2 {
- compatible = "mediatek,eth-mac";
- reg = <2>;
- status = "disabled";
- pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
- phys = <&xfi_tphy0>;
- };
-
- mdio_bus: mdio-bus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* internal 2.5G PHY */
- int_2p5g_phy: ethernet-phy@15 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <15>;
- phy-mode = "internal";
- };
- };
- };
-
- crypto: crypto@15600000 {
- compatible = "inside-secure,safexcel-eip197b";
- reg = <0 0x15600000 0 0x180000>;
- interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "ring0", "ring1", "ring2", "ring3";
- status = "okay";
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <1000>;
- thermal-sensors = <&lvts 0>;
-
- trips {
- cpu_trip_crit: crit {
- temperature = <125000>;
- hysteresis = <2000>;
- type = "critical";
- };
-
- cpu_trip_hot: hot {
- temperature = <120000>;
- hysteresis = <2000>;
- type = "hot";
- };
-
- cpu_trip_active_high: active-high {
- temperature = <115000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- cpu_trip_active_med: active-med {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- cpu_trip_active_low: active-low {
- temperature = <40000>;
- hysteresis = <2000>;
- type = "active";
- };
- };
-
- cooling-maps {
- cpu-active-high {
- /* active: set fan to cooling level 2 */
- cooling-device = <&fan 3 3>;
- trip = <&cpu_trip_active_high>;
- };
-
- cpu-active-low {
- /* active: set fan to cooling level 1 */
- cooling-device = <&fan 2 2>;
- trip = <&cpu_trip_active_med>;
- };
-
- cpu-passive {
- /* passive: set fan to cooling level 0 */
- cooling-device = <&fan 1 1>;
- trip = <&cpu_trip_active_low>;
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-#include <linux/bitfield.h>
-#include <linux/firmware.h>
-#include <linux/module.h>
-#include <linux/nvmem-consumer.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/phy.h>
-#include <linux/pm_domain.h>
-#include <linux/pm_runtime.h>
-
-#define MT7988_2P5GE_PMB "mediatek/mt7988/i2p5ge-phy-pmb.bin"
-
-#define MD32_EN BIT(0)
-#define PMEM_PRIORITY BIT(8)
-#define DMEM_PRIORITY BIT(16)
-
-#define BASE100T_STATUS_EXTEND 0x10
-#define BASE1000T_STATUS_EXTEND 0x11
-#define EXTEND_CTRL_AND_STATUS 0x16
-
-#define PHY_AUX_CTRL_STATUS 0x1d
-#define PHY_AUX_DPX_MASK GENMASK(5, 5)
-#define PHY_AUX_SPEED_MASK GENMASK(4, 2)
-
-/* Registers on MDIO_MMD_VEND1 */
-#define MTK_PHY_LINK_STATUS_MISC 0xa2
-#define MTK_PHY_FDX_ENABLE BIT(5)
-
-#define MTK_PHY_LPI_PCS_DSP_CTRL 0x121
-#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8)
-
-/* Registers on MDIO_MMD_VEND2 */
-#define MTK_PHY_LED0_ON_CTRL 0x24
-#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
-#define MTK_PHY_LED0_ON_LINK100 BIT(1)
-#define MTK_PHY_LED0_ON_LINK10 BIT(2)
-#define MTK_PHY_LED0_ON_LINK2500 BIT(7)
-#define MTK_PHY_LED0_POLARITY BIT(14)
-
-#define MTK_PHY_LED1_ON_CTRL 0x26
-#define MTK_PHY_LED1_ON_FDX BIT(4)
-#define MTK_PHY_LED1_ON_HDX BIT(5)
-#define MTK_PHY_LED1_POLARITY BIT(14)
-
-#define MTK_EXT_PAGE_ACCESS 0x1f
-#define MTK_PHY_PAGE_STANDARD 0x0000
-#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
-
-struct mtk_i2p5ge_phy_priv {
- bool fw_loaded;
-};
-
-enum {
- PHY_AUX_SPD_10 = 0,
- PHY_AUX_SPD_100,
- PHY_AUX_SPD_1000,
- PHY_AUX_SPD_2500,
-};
-
-static int mtk_2p5ge_phy_read_page(struct phy_device *phydev)
-{
- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-}
-
-static int mtk_2p5ge_phy_write_page(struct phy_device *phydev, int page)
-{
- return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
-}
-
-static int mt7988_2p5ge_phy_probe(struct phy_device *phydev)
-{
- struct mtk_i2p5ge_phy_priv *phy_priv;
-
- phy_priv = devm_kzalloc(&phydev->mdio.dev,
- sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL);
- if (!phy_priv)
- return -ENOMEM;
-
- phydev->priv = phy_priv;
-
- return 0;
-}
-
-static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev)
-{
- int ret, i;
- const struct firmware *fw;
- struct device *dev = &phydev->mdio.dev;
- struct device_node *np;
- void __iomem *pmb_addr;
- void __iomem *md32_en_cfg_base;
- struct mtk_i2p5ge_phy_priv *phy_priv = phydev->priv;
- u16 reg;
- struct pinctrl *pinctrl;
-
- if (!phy_priv->fw_loaded) {
- np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
- if (!np)
- return -ENOENT;
- pmb_addr = of_iomap(np, 0);
- if (!pmb_addr)
- return -ENOMEM;
- md32_en_cfg_base = of_iomap(np, 1);
- if (!md32_en_cfg_base)
- return -ENOMEM;
-
- ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev);
- if (ret) {
- dev_err(dev, "failed to load firmware: %s, ret: %d\n",
- MT7988_2P5GE_PMB, ret);
- return ret;
- }
-
- reg = readw(md32_en_cfg_base);
- if (reg & MD32_EN) {
- phy_set_bits(phydev, 0, BIT(15));
- usleep_range(10000, 11000);
- }
- phy_set_bits(phydev, 0, BIT(11));
-
- /* Write magic number to safely stall MCU */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100);
- phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df);
-
- for (i = 0; i < fw->size - 1; i += 4)
- writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
- release_firmware(fw);
-
- writew(reg & ~MD32_EN, md32_en_cfg_base);
- writew(reg | MD32_EN, md32_en_cfg_base);
- phy_set_bits(phydev, 0, BIT(15));
- dev_info(dev, "Firmware loading/trigger ok.\n");
-
- phy_priv->fw_loaded = true;
- }
-
- /* Setup LED */
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
- MTK_PHY_LED0_ON_LINK10 |
- MTK_PHY_LED0_ON_LINK100 |
- MTK_PHY_LED0_ON_LINK1000 |
- MTK_PHY_LED0_ON_LINK2500);
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
- MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
-
- pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
- if (IS_ERR(pinctrl)) {
- dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
- return PTR_ERR(pinctrl);
- }
-
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
- MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
-
- /* Enable 16-bit next page exchange bit if 1000-BT isn't advertizing */
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- __phy_write(phydev, 0x11, 0xfbfa);
- __phy_write(phydev, 0x12, 0xc3);
- __phy_write(phydev, 0x10, 0x87f8);
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
- return 0;
-}
-
-static int mt7988_2p5ge_phy_config_aneg(struct phy_device *phydev)
-{
- bool changed = false;
- u32 adv;
- int ret;
-
- if (phydev->autoneg == AUTONEG_DISABLE) {
- /* Configure half duplex with genphy_setup_forced,
- * because genphy_c45_pma_setup_forced does not support.
- */
- return phydev->duplex != DUPLEX_FULL
- ? genphy_setup_forced(phydev)
- : genphy_c45_pma_setup_forced(phydev);
- }
-
- ret = genphy_c45_an_config_aneg(phydev);
- if (ret < 0)
- return ret;
- if (ret > 0)
- changed = true;
-
- adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
- ret = phy_modify_changed(phydev, MII_CTRL1000,
- ADVERTISE_1000FULL | ADVERTISE_1000HALF,
- adv);
- if (ret < 0)
- return ret;
- if (ret > 0)
- changed = true;
-
- return genphy_c45_check_and_restart_aneg(phydev, changed);
-}
-
-static int mt7988_2p5ge_phy_get_features(struct phy_device *phydev)
-{
- int ret;
-
- ret = genphy_read_abilities(phydev);
- if (ret)
- return ret;
-
- /* We don't support HDX at MAC layer on mt7988.
- * So mask phy's HDX capabilities, too.
- */
- linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
- phydev->supported);
- linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
- phydev->supported);
- linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
- phydev->supported);
- linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
- phydev->supported);
- linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
-
- return 0;
-}
-
-static int mt7988_2p5ge_phy_read_status(struct phy_device *phydev)
-{
- int ret;
-
- ret = genphy_update_link(phydev);
- if (ret)
- return ret;
-
- phydev->speed = SPEED_UNKNOWN;
- phydev->duplex = DUPLEX_UNKNOWN;
- phydev->pause = 0;
- phydev->asym_pause = 0;
-
- if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
- ret = genphy_c45_read_lpa(phydev);
- if (ret < 0)
- return ret;
-
- /* Read the link partner's 1G advertisement */
- ret = phy_read(phydev, MII_STAT1000);
- if (ret < 0)
- return ret;
- mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
- } else if (phydev->autoneg == AUTONEG_DISABLE) {
- linkmode_zero(phydev->lp_advertising);
- }
-
- ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
- if (ret < 0)
- return ret;
-
- switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
- case PHY_AUX_SPD_10:
- phydev->speed = SPEED_10;
- break;
- case PHY_AUX_SPD_100:
- phydev->speed = SPEED_100;
- break;
- case PHY_AUX_SPD_1000:
- phydev->speed = SPEED_1000;
- break;
- case PHY_AUX_SPD_2500:
- phydev->speed = SPEED_2500;
- break;
- }
-
- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
- if (ret < 0)
- return ret;
-
- phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
- /* FIXME: The current firmware always enables rate adaptation mode. */
- phydev->rate_matching = RATE_MATCH_PAUSE;
-
- return 0;
-}
-
-static int mt7988_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
- phy_interface_t iface)
-{
- return RATE_MATCH_PAUSE;
-}
-
-static struct phy_driver mtk_gephy_driver[] = {
- {
- PHY_ID_MATCH_MODEL(0x00339c11),
- .name = "MediaTek MT798x 2.5GbE PHY",
- .probe = mt7988_2p5ge_phy_probe,
- .config_init = mt7988_2p5ge_phy_config_init,
- .config_aneg = mt7988_2p5ge_phy_config_aneg,
- .get_features = mt7988_2p5ge_phy_get_features,
- .read_status = mt7988_2p5ge_phy_read_status,
- .get_rate_matching = mt7988_2p5ge_phy_get_rate_matching,
- .suspend = genphy_suspend,
- .resume = genphy_resume,
- .read_page = mtk_2p5ge_phy_read_page,
- .write_page = mtk_2p5ge_phy_write_page,
- },
-};
-
-module_phy_driver(mtk_gephy_driver);
-
-static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
- { PHY_ID_MATCH_VENDOR(0x00339c00) },
- { }
-};
-
-MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
-MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
-MODULE_LICENSE("GPL");
-
-MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
-MODULE_FIRMWARE(MT7988_2P5GE_PMB);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * The MT7988 driver based on Linux generic pinctrl binding.
- *
- * Copyright (C) 2020 MediaTek Inc.
- * Author: Sam Shih <sam.shih@mediatek.com>
- */
-
-#include "pinctrl-moore.h"
-
-enum MT7988_PINCTRL_REG_PAGE {
- GPIO_BASE,
- IOCFG_TR_BASE,
- IOCFG_BR_BASE,
- IOCFG_RB_BASE,
- IOCFG_LB_BASE,
- IOCFG_TL_BASE,
-};
-
-#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-
-#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
- _x_bits) \
- PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
- _x_bits, 32, 0)
-
-#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
- _x_bits) \
- PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
- _x_bits, 32, 1)
-
-static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
- PIN_FIELD(0, 83, 0x300, 0x10, 0, 4),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
- PIN_FIELD(0, 83, 0x0, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
- PIN_FIELD(0, 83, 0x200, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
- PIN_FIELD(0, 83, 0x100, 0x10, 0, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
- PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
- PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
- PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
- PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
- PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
- PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
-
- PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
- PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
- PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
- PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
-
- PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
- PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
- PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
-
- PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
- PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
- PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
- PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
-
- PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
- PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
-
- PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
- PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
- PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
- PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
- PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
- PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
- PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
- PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
- PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
- PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
- PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
- PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
- PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
- PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
- PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
- PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
- PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
- PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
- PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
- PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
- PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
- PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
- PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
- PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1),
- PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1),
- PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1),
- PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
- PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
- PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
- PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
- PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
- PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
- PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
-
- PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
- PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
- PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
- PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
- PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
- PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
- PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
- PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
- PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
- PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
- PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
- PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
- PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
- PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
-
- PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
- PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
- PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
-
- PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
- PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
- PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
- PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1),
- PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
- PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
- PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
-
- PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
- PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
- PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
- PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
- PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
- PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
- PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
- PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
- PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
- PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
- PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
-
- PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
- PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
- PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
- PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
-
- PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
- PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
- PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
- PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
-
- PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
- PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
- PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
- PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
-
- PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
- PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
-
- PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
- PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
- PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
- PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
- PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
- PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
- PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
- PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
- PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
- PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
- PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
- PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
- PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
- PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
- PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
- PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
- PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
- PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
- PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
- PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
- PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
- PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
- PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
- PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
- PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1),
- PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1),
- PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1),
- PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
- PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
- PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
- PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
- PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
- PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
- PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
-
- PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
- PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
- PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
- PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
- PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
- PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
- PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
- PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
- PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
- PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
- PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
- PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
- PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
- PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
-
- PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
- PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
- PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
- PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
-
- PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
- PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
- PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
- PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1),
- PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
- PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
- PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
-
- PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
- PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
- PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
- PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
- PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1),
- PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
- PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
- PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
-
- PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
- PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
- PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
-
- PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
- PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
- PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
- PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1),
- PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
- PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1),
- PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
- PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
- PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
-
- PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
-
- PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
- PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
- PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
-
- PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
- PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
- PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
-
- PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
- PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
- PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
- PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1),
- PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
- PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
- PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
- PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
- PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
- PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
- PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
-
- PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
- PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
- PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
- PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
-
- PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
- PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
-
- PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
- PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
-
- PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
- PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
- PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
- PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
- PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
- PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
- PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
- PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
- PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
- PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
- PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
- PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
- PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
- PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3),
- PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3),
- PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3),
- PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
- PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
- PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
- PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
- PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
- PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
- PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3),
- PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3),
- PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3),
- PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
- PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
- PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
- PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
- PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
- PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
- PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
-
- PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
- PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
- PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
- PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
- PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
- PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
- PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
- PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
- PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
- PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
- PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
- PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
- PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
- PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
-
- PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
-
- PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
- PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
- PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
- PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3),
- PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
- PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
- PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
-
- PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
- PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
- PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
- PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
- PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
- PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
- PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
- PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
- PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
- PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
- PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
-
- PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
- PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
-
- PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
- PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
-
- PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
- PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
- PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
- PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
- PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
- PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
- PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
- PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
- PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
- PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
- PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
- PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
- PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
- PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
- PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
- PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
- PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
- PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
- PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
- PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
- PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
- PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
- PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
- PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
- PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1),
- PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1),
- PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1),
- PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
- PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
- PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
- PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
- PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
- PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
- PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
-
- PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
- PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
- PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
- PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
- PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
- PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
- PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
- PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
- PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
- PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
- PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
- PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
- PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
-
- PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
- PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
-
- PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
- PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
-
- PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
- PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
- PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
- PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
- PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
- PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
- PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
- PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
- PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
- PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
- PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
-
- PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
- PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
-
- PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
- PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
-
- PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
- PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
- PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
- PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
- PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
- PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
- PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
- PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
- PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
- PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
- PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
- PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
- PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
- PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
- PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
- PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
- PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
- PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
- PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
- PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
- PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
- PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
- PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
- PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
- PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1),
- PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1),
- PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1),
- PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
- PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
- PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
- PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
- PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
- PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
- PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
-
- PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
- PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
- PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
- PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
- PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
- PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
- PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
- PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
- PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
- PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
- PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
- PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
- PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
-
- PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
- PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
-
- PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
- PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
-
- PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
- PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
- PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
- PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
-};
-
-static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
- PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
- PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
- PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
- PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
- PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
- PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
- PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
-
- PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
- PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
-
- PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
- PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
-
- PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
- PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
- PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
- PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
- PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
- PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
- PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
- PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
- PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
- PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
- PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
- PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
- PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
- PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
- PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
- PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
- PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
- PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
- PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
- PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
- PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
- PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
- PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
- PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
- PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1),
- PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1),
- PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1),
- PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
- PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
- PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
- PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
- PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
- PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
- PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
-
- PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
- PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
- PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
- PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
- PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
- PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
- PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
- PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
- PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
- PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
- PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
- PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
- PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
-
- PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
- PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
-
- PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
- PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
-
- PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
- PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
- PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
- PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
-};
-
-static const unsigned int mt7988_pull_type[] = {
- MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
- MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
- MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
- MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE, /*7*/
- MTK_PULL_PU_PD_TYPE, /*8*/ MTK_PULL_PU_PD_TYPE, /*9*/
- MTK_PULL_PU_PD_TYPE, /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
- MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE, /*13*/
- MTK_PULL_PU_PD_TYPE, /*14*/ MTK_PULL_PD_TYPE, /*15*/
- MTK_PULL_PD_TYPE, /*16*/ MTK_PULL_PD_TYPE, /*17*/
- MTK_PULL_PD_TYPE, /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
- MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
- MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
- MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
- MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
- MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
- MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
- MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
- MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
- MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
- MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
- MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
- MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
- MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
- MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
- MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
- MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
- MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
- MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
- MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
- MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
- MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
- MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE, /*63*/
- MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
- MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
- MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
- MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE, /*71*/
- MTK_PULL_PD_TYPE, /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
- MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE, /*75*/
- MTK_PULL_PU_PD_TYPE, /*76*/ MTK_PULL_PU_PD_TYPE, /*77*/
- MTK_PULL_PU_PD_TYPE, /*78*/ MTK_PULL_PU_PD_TYPE, /*79*/
- MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/
- MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/
-};
-
-static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
- [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
- [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
- [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
- [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
- [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
- [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
- [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
- [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
- [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
- [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
- [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
- [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
-};
-
-static const struct mtk_pin_desc mt7988_pins[] = {
- MT7988_PIN(0, "UART2_RXD"),
- MT7988_PIN(1, "UART2_TXD"),
- MT7988_PIN(2, "UART2_CTS"),
- MT7988_PIN(3, "UART2_RTS"),
- MT7988_PIN(4, "GPIO_A"),
- MT7988_PIN(5, "SMI_0_MDC"),
- MT7988_PIN(6, "SMI_0_MDIO"),
- MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"),
- MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
- MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"),
- MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
- MT7988_PIN(11, "GPIO_P"),
- MT7988_PIN(12, "WATCHDOG"),
- MT7988_PIN(13, "GPIO_RESET"),
- MT7988_PIN(14, "GPIO_WPS"),
- MT7988_PIN(15, "PMIC_I2C_SCL"),
- MT7988_PIN(16, "PMIC_I2C_SDA"),
- MT7988_PIN(17, "I2C_1_SCL"),
- MT7988_PIN(18, "I2C_1_SDA"),
- MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"),
- MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"),
- MT7988_PIN(21, "PWMD1"),
- MT7988_PIN(22, "SPI0_WP"),
- MT7988_PIN(23, "SPI0_HOLD"),
- MT7988_PIN(24, "SPI0_CSB"),
- MT7988_PIN(25, "SPI0_MISO"),
- MT7988_PIN(26, "SPI0_MOSI"),
- MT7988_PIN(27, "SPI0_CLK"),
- MT7988_PIN(28, "SPI1_CSB"),
- MT7988_PIN(29, "SPI1_MISO"),
- MT7988_PIN(30, "SPI1_MOSI"),
- MT7988_PIN(31, "SPI1_CLK"),
- MT7988_PIN(32, "SPI2_CLK"),
- MT7988_PIN(33, "SPI2_MOSI"),
- MT7988_PIN(34, "SPI2_MISO"),
- MT7988_PIN(35, "SPI2_CSB"),
- MT7988_PIN(36, "SPI2_HOLD"),
- MT7988_PIN(37, "SPI2_WP"),
- MT7988_PIN(38, "EMMC_RSTB"),
- MT7988_PIN(39, "EMMC_DSL"),
- MT7988_PIN(40, "EMMC_CK"),
- MT7988_PIN(41, "EMMC_CMD"),
- MT7988_PIN(42, "EMMC_DATA_7"),
- MT7988_PIN(43, "EMMC_DATA_6"),
- MT7988_PIN(44, "EMMC_DATA_5"),
- MT7988_PIN(45, "EMMC_DATA_4"),
- MT7988_PIN(46, "EMMC_DATA_3"),
- MT7988_PIN(47, "EMMC_DATA_2"),
- MT7988_PIN(48, "EMMC_DATA_1"),
- MT7988_PIN(49, "EMMC_DATA_0"),
- MT7988_PIN(50, "PCM_FS_I2S_LRCK"),
- MT7988_PIN(51, "PCM_CLK_I2S_BCLK"),
- MT7988_PIN(52, "PCM_DRX_I2S_DIN"),
- MT7988_PIN(53, "PCM_DTX_I2S_DOUT"),
- MT7988_PIN(54, "PCM_MCK_I2S_MCLK"),
- MT7988_PIN(55, "UART0_RXD"),
- MT7988_PIN(56, "UART0_TXD"),
- MT7988_PIN(57, "PWMD0"),
- MT7988_PIN(58, "JTAG_JTDI"),
- MT7988_PIN(59, "JTAG_JTDO"),
- MT7988_PIN(60, "JTAG_JTMS"),
- MT7988_PIN(61, "JTAG_JTCLK"),
- MT7988_PIN(62, "JTAG_JTRST_N"),
- MT7988_PIN(63, "USB_DRV_VBUS_P1"),
- MT7988_PIN(64, "LED_A"),
- MT7988_PIN(65, "LED_B"),
- MT7988_PIN(66, "LED_C"),
- MT7988_PIN(67, "LED_D"),
- MT7988_PIN(68, "LED_E"),
- MT7988_PIN(69, "GPIO_B"),
- MT7988_PIN(70, "GPIO_C"),
- MT7988_PIN(71, "I2C_2_SCL"),
- MT7988_PIN(72, "I2C_2_SDA"),
- MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"),
- MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"),
- MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"),
- MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
- MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"),
- MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
- MT7988_PIN(79, "USB_DRV_VBUS_P0"),
- MT7988_PIN(80, "UART1_RXD"),
- MT7988_PIN(81, "UART1_TXD"),
- MT7988_PIN(82, "UART1_CTS"),
- MT7988_PIN(83, "UART1_RTS"),
-};
-
-/* jtag */
-static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
-static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
-
-static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
-
-static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
-
-static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
-
-static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
-static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
-
-static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
-static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* int_usxgmii */
-static int mt7988_int_usxgmii_pins[] = { 2, 3 };
-static int mt7988_int_usxgmii_funcs[] = { 3, 3 };
-
-/* pwm */
-static int mt7988_pwm0_pins[] = { 57 };
-static int mt7988_pwm0_funcs[] = { 1 };
-
-static int mt7988_pwm1_pins[] = { 21 };
-static int mt7988_pwm1_funcs[] = { 1 };
-
-static int mt7988_pwm2_pins[] = { 80 };
-static int mt7988_pwm2_funcs[] = { 2 };
-
-static int mt7988_pwm3_pins[] = { 81 };
-static int mt7988_pwm3_funcs[] = { 2 };
-
-static int mt7988_pwm4_pins[] = { 82 };
-static int mt7988_pwm4_funcs[] = { 2 };
-
-static int mt7988_pwm5_pins[] = { 83 };
-static int mt7988_pwm5_funcs[] = { 2 };
-
-static int mt7988_pwm6_pins[] = { 69 };
-static int mt7988_pwm6_funcs[] = { 3 };
-
-static int mt7988_pwm7_pins[] = { 70 };
-static int mt7988_pwm7_funcs[] = { 3 };
-
-/* dfd */
-static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
-static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* i2c */
-static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
-static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
-static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
-
-static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
-static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
-static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
-
-static int mt7988_i2c0_0_pins[] = { 5, 6 };
-static int mt7988_i2c0_0_funcs[] = { 2, 2 };
-
-static int mt7988_i2c1_sfp_pins[] = { 5, 6 };
-static int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
-
-static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
-static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
-static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
-
-static int mt7988_i2c0_1_pins[] = { 15, 16 };
-static int mt7988_i2c0_1_funcs[] = { 1, 1 };
-
-static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
-static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
-
-static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
-static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
-
-static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
-static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
-
-static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
-static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
-
-static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
-static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
-
-static int mt7988_i2c1_0_pins[] = { 17, 18 };
-static int mt7988_i2c1_0_funcs[] = { 1, 1 };
-
-static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
-static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
-
-static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
-static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
-
-static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
-static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
-
-static int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
-static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
-static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
-
-static int mt7988_i2c1_2_pins[] = { 69, 70 };
-static int mt7988_i2c1_2_funcs[] = { 2, 2 };
-
-static int mt7988_i2c2_0_pins[] = { 69, 70 };
-static int mt7988_i2c2_0_funcs[] = { 4, 4 };
-
-static int mt7988_i2c2_1_pins[] = { 71, 72 };
-static int mt7988_i2c2_1_funcs[] = { 1, 1 };
-
-/* eth */
-static int mt7988_mdc_mdio0_pins[] = { 5, 6 };
-static int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
-
-static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
-static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
-
-static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
-static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
-
-static int mt7988_mdc_mdio1_pins[] = { 69, 70 };
-static int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
-
-/* pcie */
-static int mt7988_pcie_wake_n0_0_pins[] = { 7 };
-static int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
-static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n3_0_pins[] = { 9 };
-static int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n3_pins[] = { 10 };
-static int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
-static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
-
-static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
-
-static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
-
-static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
-static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
-
-static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
-static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
-static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
-
-static int mt7988_pcie_wake_n0_1_pins[] = { 13 };
-static int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
-
-static int mt7988_pcie_wake_n3_1_pins[] = { 14 };
-static int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
-
-static int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
-static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
-static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
-static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
-
-static int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
-static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
-static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n1_0_pins[] = { 75 };
-static int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n1_pins[] = { 76 };
-static int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n2_0_pins[] = { 77 };
-static int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
-
-static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
-static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
-
-static int mt7988_pcie_wake_n2_1_pins[] = { 79 };
-static int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
-
-/* pmic */
-static int mt7988_pmic_pins[] = { 11 };
-static int mt7988_pmic_funcs[] = { 1 };
-
-/* watchdog */
-static int mt7988_watchdog_pins[] = { 12 };
-static int mt7988_watchdog_funcs[] = { 1 };
-
-/* spi */
-static int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
-static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
-
-static int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
-static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
-static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
-static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
-static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
-
-/* flash */
-static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
-static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
-
-static int mt7988_emmc_45_pins[] = {
- 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37
-};
-static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
-
-static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 };
-static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 };
-
-static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43,
- 44, 45, 46, 47, 48, 49 };
-static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-
-/* uart */
-static int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
-static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_tops_uart0_0_pins[] = { 22, 23 };
-static int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
-
-static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
-static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
-static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
-static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
-
-static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
-static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
-static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
-static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
-
-static int mt7988_tops_uart1_0_pins[] = { 28, 29 };
-static int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
-
-static int mt7988_tops_uart0_1_pins[] = { 30, 31 };
-static int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
-
-static int mt7988_tops_uart1_1_pins[] = { 36, 37 };
-static int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
-
-static int mt7988_uart0_pins[] = { 55, 56 };
-static int mt7988_uart0_funcs[] = { 1, 1 };
-
-static int mt7988_tops_uart0_2_pins[] = { 55, 56 };
-static int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
-
-static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
-static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
-static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
-
-static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
-static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
-
-static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
-static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
-
-static int mt7988_uart1_2_lite_pins[] = { 80, 81 };
-static int mt7988_uart1_2_lite_funcs[] = { 1, 1 };
-
-static int mt7988_tops_uart1_2_pins[] = { 80, 81 };
-static int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
-
-static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
-static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
-
-static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
-static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
-
-static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
-static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
-
-/* udi */
-static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
-static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
-
-/* i2s */
-static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 };
-static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 };
-
-/* pcm */
-static int mt7988_pcm_pins[] = { 50, 51, 52, 53 };
-static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 };
-
-/* led */
-static int mt7988_gbe0_led1_pins[] = { 58 };
-static int mt7988_gbe0_led1_funcs[] = { 6 };
-static int mt7988_gbe1_led1_pins[] = { 59 };
-static int mt7988_gbe1_led1_funcs[] = { 6 };
-static int mt7988_gbe2_led1_pins[] = { 60 };
-static int mt7988_gbe2_led1_funcs[] = { 6 };
-static int mt7988_gbe3_led1_pins[] = { 61 };
-static int mt7988_gbe3_led1_funcs[] = { 6 };
-
-static int mt7988_2p5gbe_led1_pins[] = { 62 };
-static int mt7988_2p5gbe_led1_funcs[] = { 6 };
-
-static int mt7988_gbe0_led0_pins[] = { 64 };
-static int mt7988_gbe0_led0_funcs[] = { 1 };
-static int mt7988_gbe1_led0_pins[] = { 65 };
-static int mt7988_gbe1_led0_funcs[] = { 1 };
-static int mt7988_gbe2_led0_pins[] = { 66 };
-static int mt7988_gbe2_led0_funcs[] = { 1 };
-static int mt7988_gbe3_led0_pins[] = { 67 };
-static int mt7988_gbe3_led0_funcs[] = { 1 };
-
-static int mt7988_2p5gbe_led0_pins[] = { 68 };
-static int mt7988_2p5gbe_led0_funcs[] = { 1 };
-
-/* usb */
-static int mt7988_drv_vbus_p1_pins[] = { 63 };
-static int mt7988_drv_vbus_p1_funcs[] = { 1 };
-
-static int mt7988_drv_vbus_pins[] = { 79 };
-static int mt7988_drv_vbus_funcs[] = { 1 };
-
-static const struct group_desc mt7988_groups[] = {
- /* @GPIO(0,1,2,3): uart2 */
- PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
- /* @GPIO(0,1,2,3,4): tops_jtag0_0 */
- PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
- /* @GPIO(2,3): int_usxgmii */
- PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
- /* @GPIO(0,1,2,3,4): dfd */
- PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
- /* @GPIO(0,1): xfi_phy0_i2c0 */
- PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
- /* @GPIO(0,1): xfi_phy1_i2c0 */
- PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
- /* @GPIO(3,4): xfi_phy_pll_i2c0 */
- PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
- /* @GPIO(3,4): xfi_phy_pll_i2c1 */
- PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
- /* @GPIO(5,6) i2c0_0 */
- PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
- /* @GPIO(5,6) i2c1_sfp */
- PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
- /* @GPIO(5,6) xfi_pextp_phy0_i2c */
- PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
- /* @GPIO(5,6) xfi_pextp_phy1_i2c */
- PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
- /* @GPIO(5,6) mdc_mdio0 */
- PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
- /* @GPIO(7): pcie_wake_n0_0 */
- PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
- /* @GPIO(8): pcie_clk_req_n0_0 */
- PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
- /* @GPIO(9): pcie_wake_n3_0 */
- PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
- /* @GPIO(10): pcie_clk_req_n3 */
- PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
- /* @GPIO(10): pcie_clk_req_n0_1 */
- PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
- /* @GPIO(7,8) pcie_p0_phy_i2c */
- PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
- /* @GPIO(7,8) pcie_p1_phy_i2c */
- PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
- /* @GPIO(7,8) pcie_p2_phy_i2c */
- PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
- /* @GPIO(9,10) pcie_p3_phy_i2c */
- PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
- /* @GPIO(9,10) ckm_phy_i2c */
- PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
- /* @GPIO(11): pmic */
- PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
- /* @GPIO(12): watchdog */
- PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
- /* @GPIO(13): pcie_wake_n0_1 */
- PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
- /* @GPIO(14): pcie_wake_n3_1 */
- PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
- /* @GPIO(15,16) i2c0_1 */
- PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
- /* @GPIO(15,16) u30_phy_i2c0 */
- PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
- /* @GPIO(15,16) u32_phy_i2c0 */
- PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
- /* @GPIO(15,16) xfi_phy0_i2c1 */
- PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
- /* @GPIO(15,16) xfi_phy1_i2c1 */
- PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
- /* @GPIO(15,16) xfi_phy_pll_i2c2 */
- PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
- /* @GPIO(17,18) i2c1_0 */
- PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
- /* @GPIO(17,18) u30_phy_i2c1 */
- PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
- /* @GPIO(17,18) u32_phy_i2c1 */
- PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
- /* @GPIO(17,18) xfi_phy_pll_i2c3 */
- PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
- /* @GPIO(17,18) sgmii0_i2c */
- PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
- /* @GPIO(17,18) sgmii1_i2c */
- PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
- /* @GPIO(19): pcie_2l_0_pereset */
- PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
- /* @GPIO(20): pcie_1l_1_pereset */
- PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
- /* @GPIO(21): pwm1 */
- PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
- /* @GPIO(22,23) spi0_wp_hold */
- PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
- /* @GPIO(24,25,26,27) spi0 */
- PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
- /* @GPIO(28,29,30,31) spi1 */
- PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
- /* @GPIO(32,33,34,35) spi2 */
- PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
- /* @GPIO(36,37) spi2_wp_hold */
- PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
- /* @GPIO(22,23,24,25,26,27) snfi */
- PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
- /* @GPIO(22,23) tops_uart0_0 */
- PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
- /* @GPIO(28,29,30,31) uart2_0 */
- PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
- /* @GPIO(32,33,34,35) uart1_0 */
- PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
- /* @GPIO(32,33,34,35) uart2_1 */
- PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
- /* @GPIO(28) net_wo0_uart_txd_0 */
- PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
- /* @GPIO(29) net_wo1_uart_txd_0 */
- PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
- /* @GPIO(30) net_wo2_uart_txd_0 */
- PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
- /* @GPIO(28,29) tops_uart1_0 */
- PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
- /* @GPIO(30,31) tops_uart0_1 */
- PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
- /* @GPIO(36,37) tops_uart1_1 */
- PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
- /* @GPIO(32,33,34,35,36) udi */
- PINCTRL_PIN_GROUP("udi", mt7988_udi),
- /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */
- PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
- /* @GPIO(32,33,34,35,36,37) sdcard */
- PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard),
- /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */
- PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
- /* @GPIO(28,29) 2p5g_ext_mdio */
- PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
- /* @GPIO(30,31) gbe_ext_mdio */
- PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
- /* @GPIO(50,51,52,53,54) i2s */
- PINCTRL_PIN_GROUP("i2s", mt7988_i2s),
- /* @GPIO(50,51,52,53) pcm */
- PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
- /* @GPIO(55,56) uart0 */
- PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
- /* @GPIO(55,56) tops_uart0_2 */
- PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
- /* @GPIO(50,51,52,53) uart2_2 */
- PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
- /* @GPIO(50,51,52,53,54) wo0_jtag */
- PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
- /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */
- PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
- /* @GPIO(50,51,52,53,54) wo2_jtag */
- PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
- /* @GPIO(57) pwm0 */
- PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
- /* @GPIO(58,59,60,61,62) jtag */
- PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
- /* @GPIO(58,59,60,61,62) tops_jtag0_1 */
- PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
- /* @GPIO(58,59,60,61) uart2_3 */
- PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
- /* @GPIO(58,59,60,61) uart1_1 */
- PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
- /* @GPIO(58,59,60,61) gbe_led1 */
- PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1),
- PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1),
- PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1),
- PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1),
- /* @GPIO(62) 2p5gbe_led1 */
- PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
- /* @GPIO(64,65,66,67) gbe_led0 */
- PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0),
- PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0),
- PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0),
- PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0),
- /* @GPIO(68) 2p5gbe_led0 */
- PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
- /* @GPIO(63) drv_vbus_p1 */
- PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
- /* @GPIO(63) pcie_clk_req_n2_1 */
- PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
- /* @GPIO(69, 70) mdc_mdio1 */
- PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
- /* @GPIO(69, 70) i2c1_2 */
- PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
- /* @GPIO(69) pwm6 */
- PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
- /* @GPIO(70) pwm7 */
- PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
- /* @GPIO(69,70) i2c2_0 */
- PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
- /* @GPIO(71,72) i2c2_1 */
- PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
- /* @GPIO(73) pcie_2l_1_pereset */
- PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
- /* @GPIO(74) pcie_1l_0_pereset */
- PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
- /* @GPIO(75) pcie_wake_n1_0 */
- PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
- /* @GPIO(76) pcie_clk_req_n1 */
- PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
- /* @GPIO(77) pcie_wake_n2_0 */
- PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
- /* @GPIO(78) pcie_clk_req_n2_0 */
- PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
- /* @GPIO(79) drv_vbus */
- PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
- /* @GPIO(79) pcie_wake_n2_1 */
- PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
- /* @GPIO(80,81,82,83) uart1_2 */
- PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
- /* @GPIO(80,81) uart1_2_lite */
- PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite),
- /* @GPIO(80) pwm2 */
- PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
- /* @GPIO(81) pwm3 */
- PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
- /* @GPIO(82) pwm4 */
- PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
- /* @GPIO(83) pwm5 */
- PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
- /* @GPIO(80) net_wo0_uart_txd_0 */
- PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
- /* @GPIO(81) net_wo1_uart_txd_0 */
- PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
- /* @GPIO(82) net_wo2_uart_txd_0 */
- PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
- /* @GPIO(80,81) tops_uart1_2 */
- PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
- /* @GPIO(80) net_wo0_uart_txd_1 */
- PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
- /* @GPIO(81) net_wo1_uart_txd_1 */
- PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
- /* @GPIO(82) net_wo2_uart_txd_1 */
- PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
-};
-
-/* Joint those groups owning the same capability in user point of view which
- * allows that people tend to use through the device tree.
- */
-static const char * const mt7988_jtag_groups[] = {
- "tops_jtag0_0", "wo0_jtag", "wo1_jtag",
- "wo2_jtag", "jtag", "tops_jtag0_1",
-};
-static const char * const mt7988_int_usxgmii_groups[] = {
- "int_usxgmii",
-};
-static const char * const mt7988_pwm_groups[] = {
- "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7"
-};
-static const char * const mt7988_dfd_groups[] = {
- "dfd",
-};
-static const char * const mt7988_i2c_groups[] = {
- "xfi_phy0_i2c0",
- "xfi_phy1_i2c0",
- "xfi_phy_pll_i2c0",
- "xfi_phy_pll_i2c1",
- "i2c0_0",
- "i2c1_sfp",
- "xfi_pextp_phy0_i2c",
- "xfi_pextp_phy1_i2c",
- "i2c0_1",
- "u30_phy_i2c0",
- "u32_phy_i2c0",
- "xfi_phy0_i2c1",
- "xfi_phy1_i2c1",
- "xfi_phy_pll_i2c2",
- "i2c1_0",
- "u30_phy_i2c1",
- "u32_phy_i2c1",
- "xfi_phy_pll_i2c3",
- "sgmii0_i2c",
- "sgmii1_i2c",
- "i2c1_2",
- "i2c2_0",
- "i2c2_1",
-};
-static const char * const mt7988_ethernet_groups[] = {
- "mdc_mdio0",
- "2p5g_ext_mdio",
- "gbe_ext_mdio",
- "mdc_mdio1",
-};
-static const char * const mt7988_pcie_groups[] = {
- "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0",
- "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c",
- "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c",
- "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset",
- "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset",
- "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1",
- "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1",
- "pcie_clk_req_n0_1"
-};
-static const char * const mt7988_pmic_groups[] = {
- "pmic",
-};
-static const char * const mt7988_wdt_groups[] = {
- "watchdog",
-};
-static const char * const mt7988_spi_groups[] = {
- "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold",
-};
-static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi",
- "emmc_51" };
-static const char * const mt7988_uart_groups[] = {
- "uart2",
- "tops_uart0_0",
- "uart2_0",
- "uart1_0",
- "uart2_1",
- "net_wo0_uart_txd_0",
- "net_wo1_uart_txd_0",
- "net_wo2_uart_txd_0",
- "tops_uart1_0",
- "ops_uart0_1",
- "ops_uart1_1",
- "uart0",
- "tops_uart0_2",
- "uart1_1",
- "uart2_3",
- "uart1_2",
- "uart1_2_lite",
- "tops_uart1_2",
- "net_wo0_uart_txd_1",
- "net_wo1_uart_txd_1",
- "net_wo2_uart_txd_1",
-};
-static const char * const mt7988_udi_groups[] = {
- "udi",
-};
-static const char * const mt7988_audio_groups[] = {
- "i2s", "pcm",
-};
-static const char * const mt7988_led_groups[] = {
- "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1",
- "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0",
- "wf5g_led0", "wf5g_led1",
-};
-static const char * const mt7988_usb_groups[] = {
- "drv_vbus",
- "drv_vbus_p1",
-};
-
-static const struct function_desc mt7988_functions[] = {
- { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) },
- { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) },
- { "int_usxgmii", mt7988_int_usxgmii_groups,
- ARRAY_SIZE(mt7988_int_usxgmii_groups) },
- { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) },
- { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) },
- { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) },
- { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) },
- { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) },
- { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) },
- { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) },
- { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) },
- { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) },
- { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) },
- { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) },
- { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) },
- { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) },
-};
-
-static const struct mtk_eint_hw mt7988_eint_hw = {
- .port_mask = 7,
- .ports = 7,
- .ap_num = ARRAY_SIZE(mt7988_pins),
- .db_cnt = 16,
-};
-
-static const char * const mt7988_pinctrl_register_base_names[] = {
- "gpio_base", "iocfg_tr_base", "iocfg_br_base",
- "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
-};
-
-static struct mtk_pin_soc mt7988_data = {
- .reg_cal = mt7988_reg_cals,
- .pins = mt7988_pins,
- .npins = ARRAY_SIZE(mt7988_pins),
- .grps = mt7988_groups,
- .ngrps = ARRAY_SIZE(mt7988_groups),
- .funcs = mt7988_functions,
- .nfuncs = ARRAY_SIZE(mt7988_functions),
- .eint_hw = &mt7988_eint_hw,
- .gpio_m = 0,
- .ies_present = false,
- .base_names = mt7988_pinctrl_register_base_names,
- .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
- .bias_disable_set = mtk_pinconf_bias_disable_set,
- .bias_disable_get = mtk_pinconf_bias_disable_get,
- .bias_set = mtk_pinconf_bias_set,
- .bias_get = mtk_pinconf_bias_get,
- .pull_type = mt7988_pull_type,
- .bias_set_combo = mtk_pinconf_bias_set_combo,
- .bias_get_combo = mtk_pinconf_bias_get_combo,
- .drive_set = mtk_pinconf_drive_set_rev1,
- .drive_get = mtk_pinconf_drive_get_rev1,
- .adv_pull_get = mtk_pinconf_adv_pull_get,
- .adv_pull_set = mtk_pinconf_adv_pull_set,
-};
-
-static const struct of_device_id mt7988_pinctrl_of_match[] = {
- {
- .compatible = "mediatek,mt7988-pinctrl",
- },
- {}
-};
-
-static int mt7988_pinctrl_probe(struct platform_device *pdev)
-{
- return mtk_moore_pinctrl_probe(pdev, &mt7988_data);
-}
-
-static struct platform_driver mt7988_pinctrl_driver = {
- .driver = {
- .name = "mt7988-pinctrl",
- .of_match_table = mt7988_pinctrl_of_match,
- },
- .probe = mt7988_pinctrl_probe,
-};
-
-static int __init mt7988_pinctrl_init(void)
-{
- return platform_driver_register(&mt7988_pinctrl_driver);
-}
-arch_initcall(mt7988_pinctrl_init);
pcie: pcie@11280000 {
compatible = "mediatek,mt7981-pcie",
- "mediatek,mt7986-pcie";
+ "mediatek,mt8192-pcie";
reg = <0 0x11280000 0 0x4000>;
reg-names = "pcie-mac";
ranges = <0x82000000 0 0x20000000
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+#include "mt7988a-bananapi-bpi-r4.dtsi"
+
+/ {
+ model = "Bananapi BPI-R4 2.5GE PoE";
+ compatible = "bananapi,bpi-r4-poe",
+ "mediatek,mt7988a";
+};
+
+&gmac1 {
+ phy-mode = "internal";
+ phy-connection-type = "internal";
+ phy = <&int_2p5g_phy>;
+ status = "okay";
+};
+
+&int_2p5g_phy {
+ pinctrl-names = "i2p5gbe-led";
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+};
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
-/dts-v1/;
-#include "mt7988a.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+#include "mt7988a-bananapi-bpi-r4.dtsi"
/ {
model = "Bananapi BPI-R4";
compatible = "bananapi,bpi-r4",
- "mediatek,mt7988";
-
- aliases {
- serial0 = &uart0;
- led-boot = &led_green;
- led-failsafe = &led_green;
- led-running = &led_green;
- led-upgrade = &led_green;
- };
-
- chosen {
- stdout-path = &uart0;
- bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0";
- rootdisk-spim-nand = <&ubi_rootfs>;
- };
-
- memory {
- reg = <0x00 0x40000000 0x00 0x10000000>;
- };
-
- /* SFP1 cage (WAN) */
- sfp1: sfp1 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp1>;
- los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
- tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
- tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
- rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
- maximum-power-milliwatt = <3000>;
- };
+ "mediatek,mt7988a";
/* SFP2 cage (LAN) */
sfp2: sfp2 {
rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <3000>;
};
-
- gpio-keys {
- compatible = "gpio-keys";
-
- wps {
- label = "WPS";
- linux,code = <KEY_RESTART>;
- gpios = <&pio 14 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- led_green: led-green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- led_blue: led-blue {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-};
-
-ð {
- status = "okay";
-};
-
-&gmac0 {
- status = "okay";
};
&gmac1 {
status = "okay";
};
-&gmac2 {
- sfp = <&sfp1>;
- managed = "in-band-status";
- phy-mode = "usxgmii";
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&gsw_phy0 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe0_led0_pins>;
-};
-
-&gsw_port0 {
- label = "wan";
-};
-
-&gsw_phy0_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy1 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe1_led0_pins>;
-};
-
-&gsw_phy1_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy2 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe2_led0_pins>;
-};
-
-&gsw_phy2_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&gsw_phy3 {
- pinctrl-names = "gbe-led";
- pinctrl-0 = <&gbe3_led0_pins>;
-};
-
-&gsw_phy3_led0 {
- status = "okay";
- color = <LED_COLOR_ID_GREEN>;
-};
-
-&cpu0 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cpu1 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cpu2 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cpu3 {
- proc-supply = <&rt5190_buck3>;
-};
-
-&cci {
- proc-supply = <&rt5190_buck3>;
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
-
- rt5190a_64: rt5190a@64 {
- compatible = "richtek,rt5190a";
- reg = <0x64>;
- vin2-supply = <&rt5190_buck1>;
- vin3-supply = <&rt5190_buck1>;
- vin4-supply = <&rt5190_buck1>;
-
- regulators {
- rt5190_buck1: buck1 {
- regulator-name = "rt5190a-buck1";
- regulator-min-microvolt = <5090000>;
- regulator-max-microvolt = <5090000>;
- regulator-allowed-modes =
- <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
- regulator-boot-on;
- regulator-always-on;
- };
- buck2 {
- regulator-name = "vcore";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
- rt5190_buck3: buck3 {
- regulator-name = "vproc";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- };
- buck4 {
- regulator-name = "rt5190a-buck4";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <850000>;
- regulator-allowed-modes =
- <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
- regulator-boot-on;
- regulator-always-on;
- };
- ldo {
- regulator-name = "rt5190a-ldo";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_1_pins>;
- status = "okay";
-
- pca9545: i2c-switch@70 {
- reg = <0x70>;
- compatible = "nxp,pca9545";
- reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+&pca9545 {
+ i2c_sfp2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
-
- i2c_rtc: i2c@0 { //eeprom,rtc,ngff
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- address-bits = <8>;
- page-size = <8>;
- size = <256>;
- };
-
- eeprom@57 {
- compatible = "atmel,24c02";
- reg = <0x57>;
- address-bits = <8>;
- page-size = <8>;
- size = <256>;
- };
-
- pcf8563: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- status = "disabled";
- };
- };
-
- i2c_sfp1: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
-
- i2c_sfp2: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- i2c_wifi: i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
- };
-};
-
-/* mPCIe SIM2 */
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_pins>;
- status = "okay";
-};
-
-/* mPCIe SIM3 */
-&pcie1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie1_pins>;
- status = "okay";
-};
-
-/* M.2 key-B SIM1 */
-&pcie2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_pins>;
- status = "okay";
-};
-
-/* M.2 key-M SSD */
-&pcie3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie3_pins>;
- status = "okay";
-};
-
-&ssusb1 {
- status = "okay";
-};
-
-&tphy {
- status = "okay";
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_flash_pins>;
- status = "okay";
-
- spi_nand: spi_nand@0 {
- compatible = "spi-nand";
- reg = <0>;
- spi-max-frequency = <52000000>;
- spi-tx-buswidth = <4>;
- spi-rx-buswidth = <4>;
- };
-};
-
-&spi_nand {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bl2";
- reg = <0x0 0x200000>;
- read-only;
- };
-
- partition@200000 {
- label = "ubi";
- reg = <0x200000 0x7e00000>;
- compatible = "linux,ubi";
-
- volumes {
- ubi-volume-ubootenv {
- volname = "ubootenv";
- nvmem-layout {
- compatible = "u-boot,env-redundant-bool-layout";
- };
- };
-
- ubi-volume-ubootenv2 {
- volname = "ubootenv2";
- nvmem-layout {
- compatible = "u-boot,env-redundant-bool-layout";
- };
- };
-
- ubi_rootfs: ubi-volume-fit {
- volname = "fit";
- };
- };
- };
+ reg = <2>;
};
};
-
-&uart0 {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_2_lite_pins>;
-};
-
-&uart2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_3_pins>;
-};
-
-&watchdog {
- status = "okay";
-};
-
-&xphy {
- status = "okay";
-};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
+/ {
+ model = "Bananapi BPI-R4";
+ compatible = "bananapi,bpi-r4",
+ "mediatek,mt7988a";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ led-boot = &led_green;
+ led-failsafe = &led_green;
+ led-running = &led_green;
+ led-upgrade = &led_green;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait";
+ rootdisk-spim-nand = <&ubi_rootfs>;
+ };
+
+ memory {
+ reg = <0x00 0x40000000 0x00 0x10000000>;
+ };
+
+ /* SFP1 cage (WAN) */
+ sfp1: sfp1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
+ rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
+ maximum-power-milliwatt = <3000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led_green: led-green {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led_blue: led-blue {
+ function = LED_FUNCTION_WPS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+ð {
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gmac2 {
+ sfp = <&sfp1>;
+ managed = "in-band-status";
+ phy-mode = "usxgmii";
+ status = "okay";
+};
+
+&switch {
+ status = "okay";
+};
+
+&gsw_phy0 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe0_led0_pins>;
+};
+
+&gsw_port0 {
+ label = "wan";
+};
+
+&gsw_phy0_led0 {
+ status = "okay";
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy1 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe1_led0_pins>;
+};
+
+&gsw_phy1_led0 {
+ status = "okay";
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy2 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe2_led0_pins>;
+};
+
+&gsw_phy2_led0 {
+ status = "okay";
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy3 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe3_led0_pins>;
+};
+
+&gsw_phy3_led0 {
+ status = "okay";
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&cpu0 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cci {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+
+ rt5190a_64: rt5190a@64 {
+ compatible = "richtek,rt5190a";
+ reg = <0x64>;
+ vin2-supply = <&rt5190_buck1>;
+ vin3-supply = <&rt5190_buck1>;
+ vin4-supply = <&rt5190_buck1>;
+
+ regulators {
+ rt5190_buck1: buck1 {
+ regulator-name = "rt5190a-buck1";
+ regulator-min-microvolt = <5090000>;
+ regulator-max-microvolt = <5090000>;
+ regulator-allowed-modes =
+ <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ buck2 {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ rt5190_buck3: buck3 {
+ regulator-name = "vproc";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ };
+ buck4 {
+ regulator-name = "rt5190a-buck4";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-allowed-modes =
+ <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ ldo {
+ regulator-name = "rt5190a-ldo";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_1_pins>;
+ status = "okay";
+
+ pca9545: i2c-switch@70 {
+ reg = <0x70>;
+ compatible = "nxp,pca9545";
+ reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c_rtc: i2c@0 { //eeprom,rtc,ngff
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ address-bits = <8>;
+ page-size = <8>;
+ size = <256>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ address-bits = <8>;
+ page-size = <8>;
+ size = <256>;
+ };
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ status = "disabled";
+ };
+ };
+
+ i2c_sfp1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c_wifi: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+};
+
+/* mPCIe SIM2 */
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_pins>;
+ status = "okay";
+};
+
+/* mPCIe SIM3 */
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ status = "okay";
+};
+
+/* M.2 key-B SIM1 */
+&pcie2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_pins>;
+ status = "okay";
+};
+
+/* M.2 key-M SSD */
+&pcie3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3_pins>;
+ status = "okay";
+};
+
+&pwm {
+ status = "okay";
+};
+
+&fan {
+ pwms = <&pwm 0 50000>;
+ status = "okay";
+};
+
+&ssusb1 {
+ status = "okay";
+};
+
+&tphy {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ status = "okay";
+
+ spi_nand: spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+ };
+};
+
+&spi_nand {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x200000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "ubi";
+ reg = <0x200000 0x7e00000>;
+ compatible = "linux,ubi";
+
+ volumes {
+ ubi-volume-ubootenv {
+ volname = "ubootenv";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool-layout";
+ };
+ };
+
+ ubi-volume-ubootenv2 {
+ volname = "ubootenv2";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool-layout";
+ };
+ };
+
+ ubi_rootfs: ubi-volume-fit {
+ volname = "fit";
+ };
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_2_lite_pins>;
+};
+
+&uart2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_3_pins>;
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&xphy {
+ status = "okay";
+};
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
+ firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
phy8: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
+ firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&ubi_part>;
+
+ __overlay__ {
+ volumes {
+ ubi_factory: ubi-volume-factory {
+ volname = "factory";
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_wmac: eeprom@0 {
+ reg = <0x0 0x1e00>;
+ };
+
+ gmac2_mac: eeprom@fffee {
+ reg = <0xfffee 0x6>;
+ };
+
+ gmac1_mac: eeprom@ffff4 {
+ reg = <0xffff4 0x6>;
+ };
+
+ gmac0_mac: eeprom@ffffa {
+ reg = <0xffffa 0x6>;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&pcie0>;
+ __overlay__ {
+ pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+
+ wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cell-names = "eeprom";
+ nvmem-cells = <&eeprom_wmac>;
+ };
+ };
+ };
+ };
+
+ fragment@2 {
+ target = <&gmac0>;
+ __overlay__ {
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&gmac0_mac>;
+ };
+ };
+
+ fragment@3 {
+ target = <&gmac1>;
+ __overlay__ {
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&gmac1_mac>;
+ };
+ };
+
+ fragment@4 {
+ target = <&gmac2>;
+ __overlay__ {
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&gmac2_mac>;
+ };
+ };
+};
spi-max-frequency = <52000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
- mediatek,nmbm;
- mediatek,bmt-max-ratio = <1>;
- mediatek,bmt-max-reserved-blocks = <64>;
partitions {
compatible = "fixed-partitions";
partition@0 {
label = "BL2";
- reg = <0x00000 0x0100000>;
+ reg = <0x00000 0x0200000>;
read-only;
};
- partition@100000 {
- label = "u-boot-env";
- reg = <0x0100000 0x0080000>;
- };
+ ubi_part: partition@200000 {
+ label = "ubi";
+ reg = <0x0200000 0x7e00000>;
+ compatible = "linux,ubi";
- partition@180000 {
- label = "Factory";
- reg = <0x180000 0x0400000>;
- };
+ volumes {
+ ubi-volume-ubootenv {
+ volname = "ubootenv";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool-layout";
+ };
+ };
- partition@580000 {
- label = "FIP";
- reg = <0x580000 0x0200000>;
- };
+ ubi-volume-ubootenv2 {
+ volname = "ubootenv2";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool-layout";
+ };
+ };
- partition@780000 {
- label = "ubi";
- reg = <0x780000 0x7080000>;
+ ubi_root: ubi-volume-fit {
+ volname = "fit";
+ };
+
+ };
};
};
};
};
};
+
+ fragment@1 {
+ target-path = "/chosen";
+ __overlay__ {
+ rootdisk-spim-nand = <&ubi_root>;
+ };
+ };
};
/ {
model = "MediaTek MT7988A Reference Board";
compatible = "mediatek,mt7988a-rfb",
- "mediatek,mt7988";
+ "mediatek,mt7988a";
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
#define MT7988_TOPRGU_XFI_PLL_GRST 16
/ {
- compatible = "mediatek,mt7988";
+ compatible = "mediatek,mt7988a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
fan: pwm-fan {
compatible = "pwm-fan";
- /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
- cooling-levels = <0 128 255>;
+ /* cooling level (0, 1, 2, 3) : (0% duty, 30% duty, 50% duty, 100% duty) */
+ cooling-levels = <0 80 128 255>;
#cooling-cells = <2>;
#thermal-sensor-cells = <1>;
status = "disabled";
pmu {
compatible = "arm,cortex-a73-pmu";
interrupt-parent = <&gic>;
- interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
gsw_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
+ interrupts = <0>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p0>;
nvmem-cell-names = "phy-cal-data";
gsw_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+ interrupts = <1>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p1>;
nvmem-cell-names = "phy-cal-data";
gsw_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
+ interrupts = <2>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p2>;
nvmem-cell-names = "phy-cal-data";
gsw_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
+ interrupts = <3>;
phy-mode = "internal";
nvmem-cells = <&phy_calibration_p3>;
nvmem-cell-names = "phy-cal-data";
}
/* Setup LED */
+
+ /* Set polarity of led0 to active-high for BPI-R4 */
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
+ MTK_PHY_LED0_POLARITY);
+
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
MTK_PHY_LED0_ON_LINK10 |
MTK_PHY_LED0_ON_LINK100 |
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
-#include <linux/version.h>
/**
* Driver for SmartRG RGBW LED microcontroller.
static int
-#if LINUX_VERSION_CODE < KERNEL_VERSION(6,6,0)
-srg_led_probe(struct i2c_client *client, const struct i2c_device_id *id)
-#else
srg_led_probe(struct i2c_client *client)
-#endif
{
struct device_node *np = client->dev.of_node, *child;
struct srg_led_ctrl *sysled_ctrl;
srg_led_i2c_write(sysled_ctrl, i, 0);
}
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,16,0)
static void
-#else
-static int
-#endif
srg_led_remove(struct i2c_client *client)
{
struct srg_led_ctrl *sysled_ctrl = i2c_get_clientdata(client);
srg_led_disable(client);
mutex_destroy(&sysled_ctrl->lock);
-
-#if LINUX_VERSION_CODE < KERNEL_VERSION(5,16,0)
- return 0;
-#endif
}
static const struct i2c_device_id srg_led_id[] = {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/* FILE NAME: en8801sc.c
+ * PURPOSE:
+ * EN8801SC phy driver for Linux
+ * NOTES:
+ *
+ */
+
+/* INCLUDE FILE DECLARATIONS
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/unistd.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/phy.h>
+#include <linux/delay.h>
+
+#include <linux/uaccess.h>
+#include <linux/version.h>
+
+#include "en8801sc.h"
+
+MODULE_DESCRIPTION("Airoha EN8801S PHY drivers for MediaTek SoC");
+MODULE_AUTHOR("Airoha");
+MODULE_LICENSE("GPL");
+
+#define airoha_mdio_lock(bus) mutex_lock(&((bus)->mdio_lock))
+#define airoha_mdio_unlock(bus) mutex_unlock(&((bus)->mdio_lock))
+
+#define phydev_mdio_bus(_dev) (_dev->mdio.bus)
+#define phydev_phy_addr(_dev) (_dev->mdio.addr)
+#define phydev_dev(_dev) (&_dev->mdio.dev)
+#define phydev_pbus_addr(dev) ((dev)->mdio.addr + 1)
+
+enum {
+ PHY_STATE_DONE = 0,
+ PHY_STATE_INIT = 1,
+ PHY_STATE_PROCESS = 2,
+ PHY_STATE_FAIL = 3,
+};
+
+struct en8801s_priv {
+ bool first_init;
+ u16 count;
+ u16 pro_version;
+};
+
+/*
+The following led_cfg example is for reference only.
+LED5 1000M/LINK/ACT (GPIO5) <-> BASE_T_LED0,
+LED6 10/100M/LINK/ACT (GPIO9) <-> BASE_T_LED1,
+LED4 100M/LINK/ACT (GPIO8) <-> BASE_T_LED2,
+*/
+/* User-defined.B */
+#define AIR_LED_SUPPORT
+#ifdef AIR_LED_SUPPORT
+static const struct AIR_BASE_T_LED_CFG_S led_cfg[4] = {
+/*
+* {LED Enable, GPIO, LED Polarity, LED ON, LED Blink}
+*/
+ /* BASE-T LED0 */
+ {LED_ENABLE, 5, AIR_ACTIVE_LOW,
+ BASE_T_LED0_ON_CFG, BASE_T_LED0_BLK_CFG},
+ /* BASE-T LED1 */
+ {LED_ENABLE, 9, AIR_ACTIVE_LOW,
+ BASE_T_LED1_ON_CFG, BASE_T_LED1_BLK_CFG},
+ /* BASE-T LED2 */
+ {LED_ENABLE, 8, AIR_ACTIVE_LOW,
+ BASE_T_LED2_ON_CFG, BASE_T_LED2_BLK_CFG},
+ /* BASE-T LED3 */
+ {LED_DISABLE, 1, AIR_ACTIVE_LOW,
+ BASE_T_LED3_ON_CFG, BASE_T_LED3_BLK_CFG},
+};
+static const u16 led_dur = UNIT_LED_BLINK_DURATION << AIR_LED_BLK_DUR_64M;
+#endif
+
+/* User-defined.E */
+
+/************************************************************************
+* F U N C T I O N S
+************************************************************************/
+static int en8801s_phase2_init(struct phy_device *phydev);
+
+static int __airoha_cl45_write(struct mii_bus *bus, int port,
+ u32 devad, u32 reg, u16 val)
+{
+ int ret = 0;
+ struct device *dev = &bus->dev;
+
+ ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, devad);
+ if (ret < 0) {
+ dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
+ return ret;
+ }
+ ret = __mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, reg);
+ if (ret < 0) {
+ dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
+ return ret;
+ }
+ ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG,
+ MMD_OP_MODE_DATA | devad);
+ if (ret < 0) {
+ dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
+ return ret;
+ }
+ ret = __mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, val);
+ if (ret < 0) {
+ dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
+ return ret;
+ }
+
+ return ret;
+}
+
+static int __airoha_cl45_read(struct mii_bus *bus, int port,
+ u32 devad, u32 reg, u16 *read_data)
+{
+ int ret = 0;
+ struct device *dev = &bus->dev;
+
+ ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG, devad);
+ if (ret < 0) {
+ dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
+ return ret;
+ }
+ ret = __mdiobus_write(bus, port, MII_MMD_ADDR_DATA_REG, reg);
+ if (ret < 0) {
+ dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
+ return ret;
+ }
+ ret = __mdiobus_write(bus, port, MII_MMD_ACC_CTL_REG,
+ MMD_OP_MODE_DATA | devad);
+ if (ret < 0) {
+ dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
+ return ret;
+ }
+ *read_data = __mdiobus_read(bus, port, MII_MMD_ADDR_DATA_REG);
+
+ return ret;
+}
+
+static int airoha_cl45_write(struct mii_bus *bus, int port,
+ u32 devad, u32 reg, u16 val)
+{
+ int ret = 0;
+
+ airoha_mdio_lock(bus);
+ ret = __airoha_cl45_write(bus, port, devad, reg, val);
+ airoha_mdio_unlock(bus);
+
+ return ret;
+}
+
+static int airoha_cl45_read(struct mii_bus *bus, int port,
+ u32 devad, u32 reg, u16 *read_data)
+{
+ int ret = 0;
+
+ airoha_mdio_lock(bus);
+ ret = __airoha_cl45_read(bus, port, devad, reg, read_data);
+ airoha_mdio_unlock(bus);
+
+ return ret;
+}
+
+static int __airoha_pbus_write(struct mii_bus *ebus, int pbus_id,
+ unsigned long pbus_address, unsigned long pbus_data)
+{
+ int ret = 0;
+
+ ret = __mdiobus_write(ebus, pbus_id, 0x1F,
+ (unsigned int)(pbus_address >> 6));
+ if (ret < 0)
+ return ret;
+ ret = __mdiobus_write(ebus, pbus_id,
+ (unsigned int)((pbus_address >> 2) & 0xf),
+ (unsigned int)(pbus_data & 0xFFFF));
+ if (ret < 0)
+ return ret;
+ ret = __mdiobus_write(ebus, pbus_id, 0x10,
+ (unsigned int)(pbus_data >> 16));
+ if (ret < 0)
+ return ret;
+ return ret;
+}
+
+static unsigned long __airoha_pbus_read(struct mii_bus *ebus, int pbus_id,
+ unsigned long pbus_address)
+{
+ unsigned long pbus_data;
+ unsigned int pbus_data_low, pbus_data_high;
+ int ret = 0;
+ struct device *dev = &ebus->dev;
+
+ ret = __mdiobus_write(ebus, pbus_id, 0x1F,
+ (unsigned int)(pbus_address >> 6));
+ if (ret < 0) {
+ dev_err(dev, "%s fail. (ret=%d)\n", __func__, ret);
+ return INVALID_DATA;
+ }
+ pbus_data_low = __mdiobus_read(ebus, pbus_id,
+ (unsigned int)((pbus_address >> 2) & 0xf));
+ pbus_data_high = __mdiobus_read(ebus, pbus_id, 0x10);
+ pbus_data = (pbus_data_high << 16) + pbus_data_low;
+ return pbus_data;
+}
+
+static int airoha_pbus_write(struct mii_bus *ebus, int pbus_id,
+ unsigned long pbus_address, unsigned long pbus_data)
+{
+ int ret = 0;
+
+ airoha_mdio_lock(ebus);
+ ret = __airoha_pbus_write(ebus, pbus_id, pbus_address, pbus_data);
+ airoha_mdio_unlock(ebus);
+
+ return ret;
+}
+
+static unsigned long airoha_pbus_read(struct mii_bus *ebus, int pbus_id,
+ unsigned long pbus_address)
+{
+ unsigned long pbus_data;
+
+ airoha_mdio_lock(ebus);
+ pbus_data = __airoha_pbus_read(ebus, pbus_id, pbus_address);
+ airoha_mdio_unlock(ebus);
+
+ return pbus_data;
+}
+
+/* Airoha Token Ring Write function */
+static int airoha_tr_reg_write(struct phy_device *phydev,
+ unsigned long tr_address, unsigned long tr_data)
+{
+ int ret = 0;
+ int phy_addr = phydev_phy_addr(phydev);
+ struct mii_bus *ebus = phydev_mdio_bus(phydev);
+
+ airoha_mdio_lock(ebus);
+ ret = __mdiobus_write(ebus, phy_addr, 0x1F, 0x52b5); /* page select */
+ ret = __mdiobus_write(ebus, phy_addr, 0x11,
+ (unsigned int)(tr_data & 0xffff));
+ ret = __mdiobus_write(ebus, phy_addr, 0x12,
+ (unsigned int)(tr_data >> 16));
+ ret = __mdiobus_write(ebus, phy_addr, 0x10,
+ (unsigned int)(tr_address | TrReg_WR));
+ ret = __mdiobus_write(ebus, phy_addr, 0x1F, 0x0); /* page resetore */
+ airoha_mdio_unlock(ebus);
+
+ return ret;
+}
+
+#ifdef AIR_LED_SUPPORT
+static int airoha_led_set_usr_def(struct phy_device *phydev, u8 entity,
+ int polar, u16 on_evt, u16 blk_evt)
+{
+ int ret = 0;
+ int phy_addr = phydev_phy_addr(phydev);
+ struct mii_bus *mbus = phydev_mdio_bus(phydev);
+
+ if (polar == AIR_ACTIVE_HIGH)
+ on_evt |= LED_ON_POL;
+ else
+ on_evt &= ~LED_ON_POL;
+
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1f,
+ LED_ON_CTRL(entity), on_evt | LED_ON_EN);
+ if (ret < 0)
+ return ret;
+
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1f,
+ LED_BLK_CTRL(entity), blk_evt);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int airoha_led_set_mode(struct phy_device *phydev, u8 mode)
+{
+ u16 cl45_data;
+ int err = 0;
+ int phy_addr = phydev_phy_addr(phydev);
+ struct mii_bus *mbus = phydev_mdio_bus(phydev);
+
+ err = airoha_cl45_read(mbus, phy_addr, 0x1f, LED_BCR, &cl45_data);
+ if (err < 0)
+ return err;
+
+ switch (mode) {
+ case AIR_LED_MODE_DISABLE:
+ cl45_data &= ~LED_BCR_EXT_CTRL;
+ cl45_data &= ~LED_BCR_MODE_MASK;
+ cl45_data |= LED_BCR_MODE_DISABLE;
+ break;
+ case AIR_LED_MODE_USER_DEFINE:
+ cl45_data |= LED_BCR_EXT_CTRL;
+ cl45_data |= LED_BCR_CLK_EN;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ err = airoha_cl45_write(mbus, phy_addr, 0x1f, LED_BCR, cl45_data);
+ if (err < 0)
+ return err;
+ return 0;
+}
+
+static int airoha_led_set_state(struct phy_device *phydev, u8 entity, u8 state)
+{
+ u16 cl45_data;
+ int err;
+ int phy_addr = phydev_phy_addr(phydev);
+ struct mii_bus *mbus = phydev_mdio_bus(phydev);
+
+ err = airoha_cl45_read(mbus, phy_addr, 0x1f,
+ LED_ON_CTRL(entity), &cl45_data);
+ if (err < 0)
+ return err;
+ if (state == LED_ENABLE)
+ cl45_data |= LED_ON_EN;
+ else
+ cl45_data &= ~LED_ON_EN;
+
+ err = airoha_cl45_write(mbus, phy_addr, 0x1f,
+ LED_ON_CTRL(entity), cl45_data);
+ if (err < 0)
+ return err;
+ return 0;
+}
+
+static int en8801s_led_init(struct phy_device *phydev)
+{
+
+ unsigned long led_gpio = 0, reg_value = 0;
+ int ret = 0, led_id;
+ struct mii_bus *mbus = phydev_mdio_bus(phydev);
+ int gpio_led_rg[3] = {0x1870, 0x1874, 0x1878};
+ u16 cl45_data = led_dur;
+ struct device *dev = phydev_dev(phydev);
+ int phy_addr = phydev_phy_addr(phydev);
+ int pbus_addr = phydev_pbus_addr(phydev);
+
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1f, LED_BLK_DUR, cl45_data);
+ if (ret < 0)
+ return ret;
+ cl45_data >>= 1;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1f, LED_ON_DUR, cl45_data);
+ if (ret < 0)
+ return ret;
+ ret = airoha_led_set_mode(phydev, AIR_LED_MODE_USER_DEFINE);
+ if (ret != 0) {
+ dev_err(dev, "LED fail to set mode, ret %d !\n", ret);
+ return ret;
+ }
+ for (led_id = 0; led_id < EN8801S_LED_COUNT; led_id++) {
+ reg_value = 0;
+ ret = airoha_led_set_state(phydev, led_id, led_cfg[led_id].en);
+ if (ret != 0) {
+ dev_err(dev, "LED fail to set state, ret %d !\n", ret);
+ return ret;
+ }
+ if (led_cfg[led_id].en == LED_ENABLE) {
+ if ((led_cfg[led_id].gpio < 0)
+ || led_cfg[led_id].gpio > 9) {
+ dev_err(dev, "GPIO%d is out of range!! GPIO number is 0~9.\n",
+ led_cfg[led_id].gpio);
+ return -EIO;
+ }
+ led_gpio |= BIT(led_cfg[led_id].gpio);
+ reg_value = airoha_pbus_read(mbus, pbus_addr,
+ gpio_led_rg[led_cfg[led_id].gpio / 4]);
+ LED_SET_GPIO_SEL(led_cfg[led_id].gpio,
+ led_id, reg_value);
+ dev_dbg(dev, "[Airoha] gpio%d, reg_value 0x%lx\n",
+ led_cfg[led_id].gpio, reg_value);
+ ret = airoha_pbus_write(mbus, pbus_addr,
+ gpio_led_rg[led_cfg[led_id].gpio / 4],
+ reg_value);
+ if (ret < 0)
+ return ret;
+ ret = airoha_led_set_usr_def(phydev, led_id,
+ led_cfg[led_id].pol,
+ led_cfg[led_id].on_cfg,
+ led_cfg[led_id].blk_cfg);
+ if (ret != 0) {
+ dev_err(dev, "LED fail to set usr def, ret %d !\n",
+ ret);
+ return ret;
+ }
+ }
+ }
+ reg_value = (airoha_pbus_read(mbus, pbus_addr, 0x1880) & ~led_gpio);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1880, reg_value);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x186c, led_gpio);
+ if (ret < 0)
+ return ret;
+ dev_info(dev, "LED initialize OK !\n");
+ return 0;
+}
+#endif
+static int en8801s_phy_process(struct phy_device *phydev)
+{
+ struct mii_bus *mbus = phydev_mdio_bus(phydev);
+ unsigned long reg_value = 0;
+ int ret = 0;
+ int pbus_addr = phydev_pbus_addr(phydev);
+
+ reg_value = airoha_pbus_read(mbus, pbus_addr, 0x19e0);
+ reg_value |= BIT(0);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x19e0, reg_value);
+ if (ret < 0)
+ return ret;
+ reg_value = airoha_pbus_read(mbus, pbus_addr, 0x19e0);
+ reg_value &= ~BIT(0);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x19e0, reg_value);
+ if (ret < 0)
+ return ret;
+ return ret;
+}
+
+static int en8801s_phase1_init(struct phy_device *phydev)
+{
+ unsigned long pbus_data;
+ int pbus_addr = EN8801S_PBUS_DEFAULT_ADDR;
+ u16 reg_value;
+ int retry, ret = 0;
+ struct mii_bus *mbus = phydev_mdio_bus(phydev);
+ struct device *dev = phydev_dev(phydev);
+ struct en8801s_priv *priv = phydev->priv;
+
+ priv->count = 1;
+ msleep(1000);
+
+ retry = MAX_OUI_CHECK;
+ while (1) {
+ pbus_data = airoha_pbus_read(mbus, pbus_addr,
+ EN8801S_RG_ETHER_PHY_OUI); /* PHY OUI */
+ if (pbus_data == EN8801S_PBUS_OUI) {
+ dev_info(dev, "PBUS addr 0x%x: Start initialized.\n",
+ pbus_addr);
+ break;
+ }
+ pbus_addr = phydev_pbus_addr(phydev);
+ if (0 == --retry) {
+ dev_err(dev, "Probe fail !\n");
+ return 0;
+ }
+ }
+
+ ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_BUCK_CTL, 0x03);
+ if (ret < 0)
+ return ret;
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_PROD_VER);
+ priv->pro_version = pbus_data & 0xf;
+ dev_info(dev, "EN8801S Procduct Version :E%d\n", priv->pro_version);
+ mdelay(10);
+ pbus_data = (airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_LTR_CTL)
+ & 0xfffffffc) | BIT(2);
+ ret = airoha_pbus_write(mbus, pbus_addr,
+ EN8801S_RG_LTR_CTL, pbus_data);
+ if (ret < 0)
+ return ret;
+ mdelay(500);
+ pbus_data = (pbus_data & ~BIT(2)) |
+ EN8801S_RX_POLARITY_NORMAL |
+ EN8801S_TX_POLARITY_NORMAL;
+ ret = airoha_pbus_write(mbus, pbus_addr,
+ EN8801S_RG_LTR_CTL, pbus_data);
+ if (ret < 0)
+ return ret;
+ mdelay(500);
+ if (priv->pro_version == 4) {
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1900);
+ dev_dbg(dev, "Before 0x1900 0x%lx\n", pbus_data);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1900, 0x101009f);
+ if (ret < 0)
+ return ret;
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1900);
+ dev_dbg(dev, "After 0x1900 0x%lx\n", pbus_data);
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x19a8);
+ dev_dbg(dev, "Before 19a8 0x%lx\n", pbus_data);
+ ret = airoha_pbus_write(mbus, pbus_addr,
+ 0x19a8, pbus_data & ~BIT(16));
+ if (ret < 0)
+ return ret;
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x19a8);
+ dev_dbg(dev, "After 19a8 0x%lx\n", pbus_data);
+ }
+ pbus_data = airoha_pbus_read(mbus, pbus_addr,
+ EN8801S_RG_SMI_ADDR); /* SMI ADDR */
+ pbus_data = (pbus_data & 0xffff0000) |
+ (unsigned long)(phydev_pbus_addr(phydev) << 8) |
+ (unsigned long)(phydev_phy_addr(phydev));
+ dev_info(phydev_dev(phydev), "SMI_ADDR=%lx (renew)\n", pbus_data);
+ ret = airoha_pbus_write(mbus, pbus_addr,
+ EN8801S_RG_SMI_ADDR, pbus_data);
+ mdelay(10);
+
+ retry = MAX_RETRY;
+ while (1) {
+ mdelay(10);
+ reg_value = phy_read(phydev, MII_PHYSID2);
+ if (reg_value == EN8801S_PHY_ID2)
+ break; /* wait GPHY ready */
+
+ retry--;
+ if (retry == 0) {
+ dev_err(dev, "Initialize fail !\n");
+ return 0;
+ }
+ }
+ /* Software Reset PHY */
+ reg_value = phy_read(phydev, MII_BMCR);
+ reg_value |= BMCR_RESET;
+ ret = phy_write(phydev, MII_BMCR, reg_value);
+ if (ret < 0)
+ return ret;
+ retry = MAX_RETRY;
+ do {
+ mdelay(10);
+ reg_value = phy_read(phydev, MII_BMCR);
+ retry--;
+ if (retry == 0) {
+ dev_err(dev, "Reset fail !\n");
+ return 0;
+ }
+ } while (reg_value & BMCR_RESET);
+
+ phydev->dev_flags = PHY_STATE_INIT;
+
+ dev_info(dev, "Phase1 initialize OK ! (%s)\n", EN8801S_DRIVER_VERSION);
+ if (priv->pro_version == 4) {
+ ret = en8801s_phase2_init(phydev);
+ if (ret != 0) {
+ dev_info(dev, "en8801_phase2_init failed\n");
+ phydev->dev_flags = PHY_STATE_FAIL;
+ return 0;
+ }
+ phydev->dev_flags = PHY_STATE_PROCESS;
+ }
+
+ return 0;
+}
+
+static int en8801s_phase2_init(struct phy_device *phydev)
+{
+ union gephy_all_REG_LpiReg1Ch GPHY_RG_LPI_1C;
+ union gephy_all_REG_dev1Eh_reg324h GPHY_RG_1E_324;
+ union gephy_all_REG_dev1Eh_reg012h GPHY_RG_1E_012;
+ union gephy_all_REG_dev1Eh_reg017h GPHY_RG_1E_017;
+ unsigned long pbus_data;
+ int phy_addr = phydev_phy_addr(phydev);
+ int pbus_addr = phydev_pbus_addr(phydev);
+ u16 cl45_value;
+ int retry, ret = 0;
+ struct mii_bus *mbus = phydev_mdio_bus(phydev);
+ struct device *dev = phydev_dev(phydev);
+ struct en8801s_priv *priv = phydev->priv;
+
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1690);
+ pbus_data |= BIT(31);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1690, pbus_data);
+ if (ret < 0)
+ return ret;
+
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x10, 0xD801);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0, 0x9140);
+ if (ret < 0)
+ return ret;
+
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, 0x0003);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00);
+ if (ret < 0)
+ return ret;
+ /* Set FCM control */
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, 0x004b);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, 0x0007);
+ if (ret < 0)
+ return ret;
+
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x142c, 0x05050505);
+ if (ret < 0)
+ return ret;
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1440);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1440, pbus_data & ~BIT(11));
+ if (ret < 0)
+ return ret;
+
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1408);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1408, pbus_data | BIT(5));
+ if (ret < 0)
+ return ret;
+
+ /* Set GPHY Perfomance*/
+ /* Token Ring */
+ ret = airoha_tr_reg_write(phydev, RgAddr_R1000DEC_15h, 0x0055A0);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_R1000DEC_17h, 0x07FF3F);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_PMA_00h, 0x00001E);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_PMA_01h, 0x6FB90A);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_PMA_17h, 0x060671);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_PMA_18h, 0x0E2F00);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_TR_26h, 0x444444);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_03h, 0x000000);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_06h, 0x2EBAEF);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_08h, 0x00000B);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Ch, 0x00504D);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Dh, 0x02314F);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Fh, 0x003028);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_10h, 0x005010);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_11h, 0x040001);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_13h, 0x018670);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_14h, 0x00024A);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_1Bh, 0x000072);
+ if (ret < 0)
+ return ret;
+ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_1Ch, 0x003210);
+ if (ret < 0)
+ return ret;
+
+ /* CL22 & CL45 */
+ ret = phy_write(phydev, 0x1f, 0x03);
+ if (ret < 0)
+ return ret;
+ GPHY_RG_LPI_1C.DATA = phy_read(phydev, RgAddr_LPI_1Ch);
+ GPHY_RG_LPI_1C.DataBitField.smi_deton_th = 0x0C;
+ ret = phy_write(phydev, RgAddr_LPI_1Ch, GPHY_RG_LPI_1C.DATA);
+ if (ret < 0)
+ return ret;
+ ret = phy_write(phydev, RgAddr_LPI_1Ch, 0xC92);
+ if (ret < 0)
+ return ret;
+ ret = phy_write(phydev, RgAddr_AUXILIARY_1Dh, 0x1);
+ if (ret < 0)
+ return ret;
+ ret = phy_write(phydev, 0x1f, 0x0);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x120, 0x8014);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x122, 0xffff);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x123, 0xffff);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x144, 0x0200);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x14A, 0xEE20);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x189, 0x0110);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x19B, 0x0111);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x234, 0x0181);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x238, 0x0120);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x239, 0x0117);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x268, 0x07F4);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x2D1, 0x0733);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x323, 0x0011);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x324, 0x013F);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x326, 0x0037);
+ if (ret < 0)
+ return ret;
+
+ ret = airoha_cl45_read(mbus, phy_addr, 0x1E, 0x324, &cl45_value);
+ if (ret < 0)
+ return ret;
+ GPHY_RG_1E_324.DATA = cl45_value;
+ GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off = 0;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x324,
+ GPHY_RG_1E_324.DATA);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x19E, 0xC2);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x013, 0x0);
+ if (ret < 0)
+ return ret;
+
+ /* EFUSE */
+ airoha_pbus_write(mbus, pbus_addr, 0x1C08, 0x40000040);
+ retry = MAX_RETRY;
+ while (retry != 0) {
+ mdelay(1);
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C08);
+ if ((pbus_data & BIT(30)) == 0)
+ break;
+
+ retry--;
+ }
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C38); /* RAW#2 */
+ ret = airoha_cl45_read(mbus, phy_addr, 0x1E, 0x12, &cl45_value);
+ if (ret < 0)
+ return ret;
+ GPHY_RG_1E_012.DATA = cl45_value;
+ GPHY_RG_1E_012.DataBitField.da_tx_i2mpb_a_tbt =
+ (u16)(pbus_data & 0x03f);
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x12,
+ GPHY_RG_1E_012.DATA);
+ if (ret < 0)
+ return ret;
+ ret = airoha_cl45_read(mbus, phy_addr, 0x1E, 0x17, &cl45_value);
+ if (ret < 0)
+ return ret;
+ GPHY_RG_1E_017.DATA = cl45_value;
+ GPHY_RG_1E_017.DataBitField.da_tx_i2mpb_b_tbt =
+ (u16)((pbus_data >> 8) & 0x03f);
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x17,
+ GPHY_RG_1E_017.DATA);
+ if (ret < 0)
+ return ret;
+
+ airoha_pbus_write(mbus, pbus_addr, 0x1C08, 0x40400040);
+ retry = MAX_RETRY;
+ while (retry != 0) {
+ mdelay(1);
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C08);
+ if ((pbus_data & BIT(30)) == 0)
+ break;
+
+ retry--;
+ }
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C30); /* RAW#16 */
+ GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off =
+ (u16)((pbus_data >> 12) & 0x01);
+ ret = airoha_cl45_write(mbus, phy_addr, 0x1E, 0x324,
+ GPHY_RG_1E_324.DATA);
+ if (ret < 0)
+ return ret;
+#ifdef AIR_LED_SUPPORT
+ ret = en8801s_led_init(phydev);
+ if (ret != 0)
+ dev_err(dev, "en8801s_led_init fail (ret:%d) !\n", ret);
+#endif
+
+ ret = airoha_cl45_read(mbus, phy_addr, MDIO_MMD_AN,
+ MDIO_AN_EEE_ADV, &cl45_value);
+ if (ret < 0)
+ return ret;
+ if (cl45_value == 0) {
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1960);
+ if (0xA == ((pbus_data & 0x07c00000) >> 22)) {
+ pbus_data = (pbus_data & 0xf83fffff) | (0xC << 22);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1960,
+ pbus_data);
+ if (ret < 0)
+ return ret;
+ mdelay(10);
+ pbus_data = (pbus_data & 0xf83fffff) | (0xE << 22);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1960,
+ pbus_data);
+ if (ret < 0)
+ return ret;
+ mdelay(10);
+ }
+ } else {
+ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1960);
+ if (0xE == ((pbus_data & 0x07c00000) >> 22)) {
+ pbus_data = (pbus_data & 0xf83fffff) | (0xC << 22);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1960,
+ pbus_data);
+ if (ret < 0)
+ return ret;
+ mdelay(10);
+ pbus_data = (pbus_data & 0xf83fffff) | (0xA << 22);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1960,
+ pbus_data);
+ if (ret < 0)
+ return ret;
+ mdelay(10);
+ }
+ }
+
+ priv->first_init = false;
+ dev_info(phydev_dev(phydev), "Phase2 initialize OK !\n");
+ return 0;
+}
+
+static int en8801s_read_status(struct phy_device *phydev)
+{
+ int ret = 0, preSpeed = phydev->speed;
+ struct mii_bus *mbus = phydev_mdio_bus(phydev);
+ u32 reg_value;
+ struct device *dev = phydev_dev(phydev);
+ int pbus_addr = phydev_pbus_addr(phydev);
+ struct en8801s_priv *priv = phydev->priv;
+
+ ret = genphy_read_status(phydev);
+ if (phydev->link == LINK_DOWN)
+ preSpeed = phydev->speed = 0;
+
+ if (phydev->dev_flags == PHY_STATE_PROCESS) {
+ en8801s_phy_process(phydev);
+ phydev->dev_flags = PHY_STATE_DONE;
+ }
+
+ if (phydev->dev_flags == PHY_STATE_INIT) {
+ dev_dbg(dev, "phydev->link %d, count %d\n",
+ phydev->link, priv->count);
+ if ((phydev->link) || (priv->count == 5)) {
+ if (priv->pro_version != 4) {
+ ret = en8801s_phase2_init(phydev);
+ if (ret != 0) {
+ dev_info(dev, "en8801_phase2_init failed\n");
+ phydev->dev_flags = PHY_STATE_FAIL;
+ return 0;
+ }
+ phydev->dev_flags = PHY_STATE_PROCESS;
+ }
+ }
+ priv->count++;
+ }
+
+ if ((preSpeed != phydev->speed) && (phydev->link == LINK_UP)) {
+ preSpeed = phydev->speed;
+
+ if (preSpeed == SPEED_10) {
+ reg_value = airoha_pbus_read(mbus, pbus_addr, 0x1694);
+ reg_value |= BIT(31);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1694,
+ reg_value);
+ if (ret < 0)
+ return ret;
+ phydev->dev_flags = PHY_STATE_PROCESS;
+ } else {
+ reg_value = airoha_pbus_read(mbus, pbus_addr, 0x1694);
+ reg_value &= ~BIT(31);
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1694,
+ reg_value);
+ if (ret < 0)
+ return ret;
+ phydev->dev_flags = PHY_STATE_PROCESS;
+ }
+
+ airoha_pbus_write(mbus, pbus_addr, 0x0600,
+ 0x0c000c00);
+ if (preSpeed == SPEED_1000) {
+ dev_dbg(dev, "SPEED_1000\n");
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x10,
+ 0xD801);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0,
+ 0x9140);
+ if (ret < 0)
+ return ret;
+
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14,
+ 0x0003);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0600,
+ 0x0c000c00);
+ if (ret < 0)
+ return ret;
+ mdelay(2); /* delay 2 ms */
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1404,
+ 0x004b);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x140c,
+ 0x0007);
+ if (ret < 0)
+ return ret;
+ } else if (preSpeed == SPEED_100) {
+ dev_dbg(dev, "SPEED_100\n");
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x10,
+ 0xD401);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0,
+ 0x9140);
+ if (ret < 0)
+ return ret;
+
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14,
+ 0x0007);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0600,
+ 0x0c11);
+ if (ret < 0)
+ return ret;
+ mdelay(2); /* delay 2 ms */
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1404,
+ 0x0027);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x140c,
+ 0x0007);
+ if (ret < 0)
+ return ret;
+ } else if (preSpeed == SPEED_10) {
+ dev_dbg(dev, "SPEED_10\n");
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x10,
+ 0xD001);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0,
+ 0x9140);
+ if (ret < 0)
+ return ret;
+
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14,
+ 0x000b);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x0600,
+ 0x0c11);
+ if (ret < 0)
+ return ret;
+ mdelay(2); /* delay 2 ms */
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x1404,
+ 0x0027);
+ if (ret < 0)
+ return ret;
+ ret = airoha_pbus_write(mbus, pbus_addr, 0x140c,
+ 0x0007);
+ if (ret < 0)
+ return ret;
+ }
+ }
+ return ret;
+}
+
+static int en8801s_probe(struct phy_device *phydev)
+{
+ struct en8801s_priv *priv;
+ unsigned long phy_addr = phydev_phy_addr(phydev);
+ struct mdio_device *mdiodev = &phydev->mdio;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->count = 0;
+ priv->first_init = true;
+
+ if (mdiodev->reset_gpio) {
+ dev_dbg(phydev_dev(phydev),
+ "Assert PHY %lx HWRST until phy_init_hw\n",
+ phy_addr);
+ phy_device_reset(phydev, 1);
+ }
+
+ phydev->priv = priv;
+
+ return 0;
+}
+
+static int airoha_mmd_read(struct phy_device *phydev,
+ int devad, u16 reg)
+{
+ struct mii_bus *mbus = phydev_mdio_bus(phydev);
+ int phy_addr = phydev_phy_addr(phydev);
+ int ret = 0;
+ u16 cl45_value;
+
+ ret = __airoha_cl45_read(mbus, phy_addr, devad, reg, &cl45_value);
+ if (ret < 0)
+ return ret;
+
+ return cl45_value;
+}
+
+static int airoha_mmd_write(struct phy_device *phydev,
+ int devad, u16 reg, u16 val)
+{
+ struct mii_bus *mbus = phydev_mdio_bus(phydev);
+ int phy_addr = phydev_phy_addr(phydev);
+ int pbus_addr = phydev_pbus_addr(phydev);
+ unsigned long pbus_data;
+ int ret = 0;
+
+ if (MDIO_MMD_AN == devad && MDIO_AN_EEE_ADV == reg) {
+ if (val == 0) {
+ pbus_data = __airoha_pbus_read(mbus, pbus_addr, 0x1960);
+ if (0xA == ((pbus_data & 0x07c00000) >> 22)) {
+ pbus_data = (pbus_data & 0xf83fffff) |
+ (0xC << 22);
+ __airoha_pbus_write(mbus, pbus_addr, 0x1960,
+ pbus_data);
+ mdelay(10);
+ pbus_data = (pbus_data & 0xf83fffff) |
+ (0xE << 22);
+ __airoha_pbus_write(mbus, pbus_addr, 0x1960,
+ pbus_data);
+ mdelay(10);
+ }
+ } else {
+ pbus_data = __airoha_pbus_read(mbus, pbus_addr, 0x1960);
+ if (0xE == ((pbus_data & 0x07c00000) >> 22)) {
+ pbus_data = (pbus_data & 0xf83fffff) |
+ (0xC << 22);
+ __airoha_pbus_write(mbus, pbus_addr, 0x1960,
+ pbus_data);
+ mdelay(10);
+ pbus_data = (pbus_data & 0xf83fffff) |
+ (0xA << 22);
+ __airoha_pbus_write(mbus, pbus_addr, 0x1960,
+ pbus_data);
+ mdelay(10);
+ }
+ }
+ }
+ ret = __airoha_cl45_write(mbus, phy_addr, devad, reg, val);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static struct phy_driver Airoha_driver[] = {
+ {
+ .phy_id = EN8801SC_PHY_ID,
+ .name = "Airoha EN8801SC",
+ .phy_id_mask = 0x0ffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .probe = en8801s_probe,
+ .config_init = en8801s_phase1_init,
+ .config_aneg = genphy_config_aneg,
+ .read_status = en8801s_read_status,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ .read_mmd = airoha_mmd_read,
+ .write_mmd = airoha_mmd_write,
+ }
+};
+
+module_phy_driver(Airoha_driver);
+
+static struct mdio_device_id __maybe_unused Airoha_tbl[] = {
+ { EN8801SC_PHY_ID, 0x0ffffff0 },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, Airoha_tbl);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/* FILE NAME: en8801sc.h
+ * PURPOSE:
+ * Define EN8801SC driver function
+ *
+ * NOTES:
+ *
+ */
+
+#ifndef __EN8801SC_H
+#define __EN8801SC_H
+
+/* NAMING DECLARATIONS
+ */
+#define EN8801S_DRIVER_VERSION "1.1.8_Generic"
+#define EN8801S_PBUS_DEFAULT_ADDR 0x1e
+#define EN8801S_PHY_DEFAULT_ADDR 0x1d
+#define EN8801S_RG_ETHER_PHY_OUI 0x19a4
+#define EN8801S_RG_SMI_ADDR 0x19a8
+#define EN8801S_RG_BUCK_CTL 0x1a20
+#define EN8801S_RG_LTR_CTL 0x0cf8
+#define EN8801S_RG_PROD_VER 0x18e0
+
+#define EN8801S_PBUS_OUI 0x17a5
+#define EN8801S_PHY_ID1 0x03a2
+#define EN8801S_PHY_ID2 0x9461
+#define EN8801SC_PHY_ID 0x03a29471
+
+#define LED_ON_CTRL(i) (0x024 + ((i)*2))
+#define LED_ON_EN (1 << 15)
+#define LED_ON_POL (1 << 14)
+#define LED_ON_EVT_MASK (0x7f)
+/* LED ON Event Option.B */
+#define LED_ON_EVT_FORCE (1 << 6)
+#define LED_ON_EVT_LINK_DOWN (1 << 3)
+#define LED_ON_EVT_LINK_10M (1 << 2)
+#define LED_ON_EVT_LINK_100M (1 << 1)
+#define LED_ON_EVT_LINK_1000M (1 << 0)
+/* LED ON Event Option.E */
+
+#define LED_BLK_CTRL(i) (0x025 + ((i)*2))
+#define LED_BLK_EVT_MASK (0x3ff)
+/* LED Blinking Event Option.B*/
+#define LED_BLK_EVT_FORCE (1 << 9)
+#define LED_BLK_EVT_10M_RX_ACT (1 << 5)
+#define LED_BLK_EVT_10M_TX_ACT (1 << 4)
+#define LED_BLK_EVT_100M_RX_ACT (1 << 3)
+#define LED_BLK_EVT_100M_TX_ACT (1 << 2)
+#define LED_BLK_EVT_1000M_RX_ACT (1 << 1)
+#define LED_BLK_EVT_1000M_TX_ACT (1 << 0)
+/* LED Blinking Event Option.E*/
+#define LED_ENABLE 1
+#define LED_DISABLE 0
+
+#define LINK_UP 1
+#define LINK_DOWN 0
+
+/*
+SFP Sample for verification
+Tx Reverse, Rx Reverse
+*/
+#define EN8801S_TX_POLARITY_NORMAL 0x0
+#define EN8801S_TX_POLARITY_REVERSE 0x1
+
+#define EN8801S_RX_POLARITY_NORMAL (0x1 << 1)
+#define EN8801S_RX_POLARITY_REVERSE (0x0 << 1)
+
+/*
+The following led_cfg example is for reference only.
+LED5 1000M/LINK/ACT (GPIO5) <-> BASE_T_LED0,
+LED6 10/100M/LINK/ACT(GPIO9) <-> BASE_T_LED1,
+LED4 100M/LINK/ACT (GPIO8) <-> BASE_T_LED2,
+*/
+/* User-defined.B */
+#define BASE_T_LED0_ON_CFG (LED_ON_EVT_LINK_1000M)
+#define BASE_T_LED0_BLK_CFG \
+ (LED_BLK_EVT_1000M_TX_ACT | \
+ LED_BLK_EVT_1000M_RX_ACT)
+#define BASE_T_LED1_ON_CFG \
+ (LED_ON_EVT_LINK_100M | \
+ LED_ON_EVT_LINK_10M)
+#define BASE_T_LED1_BLK_CFG \
+ (LED_BLK_EVT_100M_TX_ACT | \
+ LED_BLK_EVT_100M_RX_ACT | \
+ LED_BLK_EVT_10M_TX_ACT | \
+ LED_BLK_EVT_10M_RX_ACT)
+#define BASE_T_LED2_ON_CFG \
+ (LED_ON_EVT_LINK_100M)
+#define BASE_T_LED2_BLK_CFG \
+ (LED_BLK_EVT_100M_TX_ACT | \
+ LED_BLK_EVT_100M_RX_ACT)
+#define BASE_T_LED3_ON_CFG (0x0)
+#define BASE_T_LED3_BLK_CFG (0x0)
+/* User-defined.E */
+
+#define EN8801S_LED_COUNT 4
+
+#define MAX_RETRY 5
+#define MAX_OUI_CHECK 2
+/* CL45 MDIO control */
+#define MII_MMD_ACC_CTL_REG 0x0d
+#define MII_MMD_ADDR_DATA_REG 0x0e
+#define MMD_OP_MODE_DATA BIT(14)
+
+#define MAX_TRG_COUNTER 5
+
+/* CL22 Reg Support Page Select */
+#define RgAddr_Reg1Fh 0x1f
+#define CL22_Page_Reg 0x0000
+#define CL22_Page_ExtReg 0x0001
+#define CL22_Page_MiscReg 0x0002
+#define CL22_Page_LpiReg 0x0003
+#define CL22_Page_tReg 0x02A3
+#define CL22_Page_TrReg 0x52B5
+
+/* CL45 Reg Support DEVID */
+#define DEVID_03 0x03
+#define DEVID_07 0x07
+#define DEVID_1E 0x1E
+#define DEVID_1F 0x1F
+
+/* TokenRing Reg Access */
+#define TrReg_PKT_XMT_STA 0x8000
+#define TrReg_WR 0x8000
+#define TrReg_RD 0xA000
+
+#define RgAddr_LPI_1Ch 0x1c
+#define RgAddr_AUXILIARY_1Dh 0x1d
+#define RgAddr_PMA_00h 0x0f80
+#define RgAddr_PMA_01h 0x0f82
+#define RgAddr_PMA_17h 0x0fae
+#define RgAddr_PMA_18h 0x0fb0
+#define RgAddr_DSPF_03h 0x1686
+#define RgAddr_DSPF_06h 0x168c
+#define RgAddr_DSPF_08h 0x1690
+#define RgAddr_DSPF_0Ch 0x1698
+#define RgAddr_DSPF_0Dh 0x169a
+#define RgAddr_DSPF_0Fh 0x169e
+#define RgAddr_DSPF_10h 0x16a0
+#define RgAddr_DSPF_11h 0x16a2
+#define RgAddr_DSPF_13h 0x16a6
+#define RgAddr_DSPF_14h 0x16a8
+#define RgAddr_DSPF_1Bh 0x16b6
+#define RgAddr_DSPF_1Ch 0x16b8
+#define RgAddr_TR_26h 0x0ecc
+#define RgAddr_R1000DEC_15h 0x03aa
+#define RgAddr_R1000DEC_17h 0x03ae
+
+#define LED_BCR (0x021)
+#define LED_BCR_EXT_CTRL (1 << 15)
+#define LED_BCR_CLK_EN (1 << 3)
+#define LED_BCR_TIME_TEST (1 << 2)
+#define LED_BCR_MODE_MASK (3)
+#define LED_BCR_MODE_DISABLE (0)
+
+#define LED_ON_DUR (0x022)
+#define LED_ON_DUR_MASK (0xffff)
+
+#define LED_BLK_DUR (0x023)
+#define LED_BLK_DUR_MASK (0xffff)
+
+#define LED_GPIO_SEL_MASK 0x7FFFFFF
+
+#define UNIT_LED_BLINK_DURATION 1024
+
+/* Invalid data */
+#define INVALID_DATA 0xffffffff
+
+#define LED_SET_GPIO_SEL(gpio, led, val) \
+ (val |= (led << (8 * (gpio % 4)))) \
+
+#define GET_BIT(val, bit) ((val & BIT(bit)) >> bit)
+/* DATA TYPE DECLARATIONS
+ */
+struct AIR_BASE_T_LED_CFG_S {
+ u16 en;
+ u16 gpio;
+ u16 pol;
+ u16 on_cfg;
+ u16 blk_cfg;
+};
+
+union gephy_all_REG_LpiReg1Ch {
+ struct {
+ /* b[15:00] */
+ u16 smi_deton_wt : 3;
+ u16 smi_det_mdi_inv : 1;
+ u16 smi_detoff_wt : 3;
+ u16 smi_sigdet_debouncing_en : 1;
+ u16 smi_deton_th : 6;
+ u16 rsv_14 : 2;
+ } DataBitField;
+ u16 DATA;
+};
+
+union gephy_all_REG_dev1Eh_reg324h {
+ struct {
+ /* b[15:00] */
+ u16 rg_smi_detcnt_max : 6;
+ u16 rsv_6 : 2;
+ u16 rg_smi_det_max_en : 1;
+ u16 smi_det_deglitch_off : 1;
+ u16 rsv_10 : 6;
+ } DataBitField;
+ u16 DATA;
+};
+
+union gephy_all_REG_dev1Eh_reg012h {
+ struct {
+ /* b[15:00] */
+ u16 da_tx_i2mpb_a_tbt : 6;
+ u16 rsv_6 : 4;
+ u16 da_tx_i2mpb_a_gbe : 6;
+ } DataBitField;
+ u16 DATA;
+};
+
+union gephy_all_REG_dev1Eh_reg017h {
+ struct {
+ /* b[15:00] */
+ u16 da_tx_i2mpb_b_tbt : 6;
+ u16 rsv_6 : 2;
+ u16 da_tx_i2mpb_b_gbe : 6;
+ u16 rsv_14 : 2;
+ } DataBitField;
+ u16 DATA;
+};
+
+enum {
+ AIR_LED_BLK_DUR_32M,
+ AIR_LED_BLK_DUR_64M,
+ AIR_LED_BLK_DUR_128M,
+ AIR_LED_BLK_DUR_256M,
+ AIR_LED_BLK_DUR_512M,
+ AIR_LED_BLK_DUR_1024M,
+ AIR_LED_BLK_DUR_LAST
+};
+
+enum {
+ AIR_ACTIVE_LOW,
+ AIR_ACTIVE_HIGH,
+};
+
+enum {
+ AIR_LED_MODE_DISABLE,
+ AIR_LED_MODE_USER_DEFINE,
+ AIR_LED_MODE_LAST
+};
+
+#endif /* End of __EN8801SC_H */
* RT_ERR_SMI - SMI access error
* RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL.
* Note:
- * This function enable and intialize ACL function
+ * This function enable and initialize ACL function
*/
rtk_api_ret_t rtk_filter_igrAcl_init(void)
{
* This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg).
* Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL
* comparison rules by means of linked list. Pointer pFilter_field will be added to linked
- * list keeped by structure that pFilter_cfg points to.
+ * list kept by structure that pFilter_cfg points to.
*/
rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t* pFilter_cfg, rtk_filter_field_t* pFilter_field)
{
}
else
{
- /*default acl template for ipv6 address supports MSB 32-bits and LSB 32-bits only*/
+ /*default ACL template for ipv6 address supports MSB 32-bits and LSB 32-bits only*/
aclRule[tempIdx].data_bits.field[fieldIdx] = ((ip6addr[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16));
aclRule[tempIdx].care_bits.field[fieldIdx] = ((ip6mask[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16));
}
* pFilter_cfg - The ACL configuration that this function will add comparison rule
* pFilter_action - Action(s) of ACL configuration.
* Output:
- * ruleNum - number of rules written in acl table
+ * ruleNum - number of rules written in ACL table
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
/* Function Name:
* rtk_filter_igrAcl_cfg_get
* Description:
- * Get one ingress acl configuration from ASIC.
+ * Get one ingress ACL configuration from ASIC.
* Input:
* filter_id - Start index of ACL configuration.
* Output:
- * pFilter_cfg - buffer pointer of ingress acl data
- * pFilter_action - buffer pointer of ingress acl action
+ * pFilter_cfg - buffer pointer of ingress ACL data
+ * pFilter_action - buffer pointer of ingress ACL action
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * This function sets action of packets when no ACL configruation matches.
+ * This function sets action of packets when no ACL configuration matches.
*/
rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action)
{
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * This function gets action of packets when no ACL configruation matches.
+ * This function gets action of packets when no ACL configuration matches.
*/
rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state)
{
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * This function gets action of packets when no ACL configruation matches.
+ * This function gets action of packets when no ACL configuration matches.
*/
rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* pState)
{
* RT_ERR_FAILED - Failed
* RT_ERR_SMI - SMI access error
* Note:
- * System support 16 user defined field selctors.
+ * System support 16 user defined field selectors.
* Each selector can be enabled or disable.
* User can defined retrieving 16-bits in many predefiend
* standard l2/l3/l4 payload.
* Set Port Range check
* Input:
* index - index of Port Range 0-15
- * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port
+ * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port
* upperPort - The upper bound of Port range
* lowerPort - The lower Bound of Port range
* Output:
* Input:
* index - index of Port Range 0-15
* Output:
- * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port
+ * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port
* pUpperPort - The upper bound of Port range
* pLowerPort - The lower Bound of Port range
* Return:
/* Function Name:
* rtk_filter_igrAclPolarity_set
* Description:
- * Set ACL Goip control palarity
+ * Set ACL Goip control polarity
* Input:
* polarity - 1: High, 0: Low
* Output:
/* Function Name:
* rtk_filter_igrAclPolarity_get
* Description:
- * Get ACL Goip control palarity
+ * Get ACL Goip control polarity
* Input:
* pPolarity - 1: High, 0: Low
* Output:
* Note:
* The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899)
* to the frame that transmitting to CPU port.
- * The inset cpu tag mode is as following:
+ * The insert CPU tag mode is as following:
* - CPU_INSERT_TO_ALL
* - CPU_INSERT_TO_TRAPPING
* - CPU_INSERT_TO_NONE
* RT_ERR_L2_NO_CPU_PORT - CPU port is not exist
* Note:
* The API can get configured CPU port and its setting.
- * The inset cpu tag mode is as following:
+ * The insert CPU tag mode is as following:
* - CPU_INSERT_TO_ALL
* - CPU_INSERT_TO_TRAPPING
* - CPU_INSERT_TO_NONE
* Input:
* port - Port ID
* protocol - IGMP/MLD protocol
- * action - Per-port and per-protocol IGMP action seeting
+ * action - Per-port and per-protocol IGMP action setting
* Output:
* None.
* Return:
* Input:
* port - Port ID
* protocol - IGMP/MLD protocol
- * action - Per-port and per-protocol IGMP action seeting
+ * action - Per-port and per-protocol IGMP action setting
* Output:
* None.
* Return:
* Description:
* Get IGMP/MLD Group database
* Input:
- * indes - Index (0~255)
+ * index - Index (0~255)
* Output:
* pGroup - Group database information.
* Return:
/* Function Name:
* rtk_igmp_dropLeaveZeroEnable_set
* Description:
- * Set the function of droppping Leave packet with group IP = 0.0.0.0
+ * Set the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* enabled - Action 1: drop, 0:pass
* Output:
/* Function Name:
* rtk_igmp_dropLeaveZeroEnable_get
* Description:
- * Get the function of droppping Leave packet with group IP = 0.0.0.0
+ * Get the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* None
* Output:
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes ACL module high-layer API defination
+ * Feature : The file includes ACL module high-layer API definition
*
*/
* RT_ERR_SMI - SMI access error
* RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL.
* Note:
- * This function enable and intialize ACL function
+ * This function enable and initialize ACL function
*/
extern rtk_api_ret_t rtk_filter_igrAcl_init(void);
* This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg).
* Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL
* comparison rules by means of linked list. Pointer pFilter_field will be added to linked
- * list keeped by structure that pFilter_cfg points to.
+ * list kept by structure that pFilter_cfg points to.
*/
extern rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg, rtk_filter_field_t *pFilter_field);
* pFilter_cfg - The ACL configuration that this function will add comparison rule
* pFilter_action - Action(s) of ACL configuration.
* Output:
- * ruleNum - number of rules written in acl table
+ * ruleNum - number of rules written in ACL table
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
/* Function Name:
* rtk_filter_igrAcl_cfg_get
* Description:
- * Get one ingress acl configuration from ASIC.
+ * Get one ingress ACL configuration from ASIC.
* Input:
* filter_id - Start index of ACL configuration.
* Output:
- * pFilter_cfg - buffer pointer of ingress acl data
- * pFilter_action - buffer pointer of ingress acl action
+ * pFilter_cfg - buffer pointer of ingress ACL data
+ * pFilter_action - buffer pointer of ingress ACL action
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * This function sets action of packets when no ACL configruation matches.
+ * This function sets action of packets when no ACL configuration matches.
*/
extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action);
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * This function gets action of packets when no ACL configruation matches.
+ * This function gets action of packets when no ACL configuration matches.
*/
extern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* action);
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * This function gets action of packets when no ACL configruation matches.
+ * This function gets action of packets when no ACL configuration matches.
*/
extern rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state);
* RT_ERR_PORT_ID - Invalid port id.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * This function gets action of packets when no ACL configruation matches.
+ * This function gets action of packets when no ACL configuration matches.
*/
extern rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* state);
* RT_ERR_FAILED - Failed
* RT_ERR_SMI - SMI access error
* Note:
- * System support 16 user defined field selctors.
+ * System support 16 user defined field selectors.
* Each selector can be enabled or disable.
* User can defined retrieving 16-bits in many predefiend
* standard l2/l3/l4 payload.
* Set Port Range check
* Input:
* index - index of Port Range 0-15
- * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port
+ * type - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port
* upperPort - The upper bound of Port range
* lowerPort - The lower Bound of Port range
* Output:
* Input:
* index - index of Port Range 0-15
* Output:
- * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port
+ * pType - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destination Port
* pUpperPort - The upper bound of Port range
* pLowerPort - The lower Bound of Port range
* Return:
/* Function Name:
* rtk_filter_igrAclPolarity_set
* Description:
- * Set ACL Goip control palarity
+ * Set ACL Goip control polarity
* Input:
* polarity - 1: High, 0: Low
* Output:
/* Function Name:
* rtk_filter_igrAclPolarity_get
* Description:
- * Get ACL Goip control palarity
+ * Get ACL Goip control polarity
* Input:
* pPolarity - 1: High, 0: Low
* Output:
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes CPU module high-layer API defination
+ * Feature : The file includes CPU module high-layer API definition
*
*/
* Note:
* The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899)
* to the frame that transmitting to CPU port.
- * The inset cpu tag mode is as following:
+ * The insert CPU tag mode is as following:
* - CPU_INSERT_TO_ALL
* - CPU_INSERT_TO_TRAPPING
* - CPU_INSERT_TO_NONE
* RT_ERR_L2_NO_CPU_PORT - CPU port is not exist
* Note:
* The API can get configured CPU port and its setting.
- * The inset cpu tag mode is as following:
+ * The insert CPU tag mode is as following:
* - CPU_INSERT_TO_ALL
* - CPU_INSERT_TO_TRAPPING
* - CPU_INSERT_TO_NONE
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes 1X module high-layer API defination
+ * Feature : The file includes 1X module high-layer API definition
*
*/
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes EEE module high-layer API defination
+ * Feature : The file includes EEE module high-layer API definition
*
*/
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes I2C module high-layer API defination
+ * Feature : The file includes I2C module high-layer API definition
*
*/
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes IGMP module high-layer API defination
+ * Feature : The file includes IGMP module high-layer API definition
*
*/
* Input:
* port - Port ID
* protocol - IGMP/MLD protocol
- * action - Per-port and per-protocol IGMP action seeting
+ * action - Per-port and per-protocol IGMP action setting
* Output:
* None.
* Return:
* Input:
* port - Port ID
* protocol - IGMP/MLD protocol
- * action - Per-port and per-protocol IGMP action seeting
+ * action - Per-port and per-protocol IGMP action setting
* Output:
* None.
* Return:
* Description:
* Get IGMP/MLD Group database
* Input:
- * indes - Index (0~255)
+ * index - Index (0~255)
* Output:
* pGroup - Group database information.
* Return:
/* Function Name:
* rtk_igmp_dropLeaveZeroEnable_set
* Description:
- * Set the function of droppping Leave packet with group IP = 0.0.0.0
+ * Set the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* enabled - Action 1: drop, 0:pass
* Output:
/* Function Name:
* rtk_igmp_dropLeaveZeroEnable_get
* Description:
- * Get the function of droppping Leave packet with group IP = 0.0.0.0
+ * Get the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* None
* Output:
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes Interrupt module high-layer API defination
+ * Feature : The file includes Interrupt module high-layer API definition
*
*/
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes L2 module high-layer API defination
+ * Feature : The file includes L2 module high-layer API definition
*
*/
* RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * If the unicast mac address already existed in LUT, it will udpate the status of the entry.
+ * If the unicast mac address already existed in LUT, it will update the status of the entry.
* Otherwise, it will find an empty or asic auto learned entry to write. If all the entries
* with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.
*/
* RT_ERR_PORT_MASK - Invalid portmask.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * If the multicast mac address already existed in the LUT, it will udpate the
+ * If the multicast mac address already existed in the LUT, it will update the
* port mask of the entry. Otherwise, it will find an empty or asic auto learned
* entry to write. If all the entries with the same hash value can't be replaced,
* ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.
/* Function Name:
* rtk_l2_ipMcastAddr_add
* Description:
- * Add Lut IP multicast entry
+ * Add LUT IP multicast entry
* Input:
* pIpMcastAddr - IP Multicast entry
* Output:
* RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * The API can get Lut table of IP multicast entry.
+ * The API can get LUT table of IP multicast entry.
*/
extern rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr);
/* Function Name:
* rtk_l2_ipVidMcastAddr_add
* Description:
- * Add Lut IP multicast+VID entry
+ * Add LUT IP multicast+VID entry
* Input:
* pIpVidMcastAddr - IP & VID multicast Entry
* Output:
* Set flooding portmask
* Input:
* type - flooding type.
- * pFlood_portmask - flooding porkmask
+ * pFlood_portmask - flooding portmask
* Output:
* None
* Return:
* Input:
* type - flooding type.
* Output:
- * pFlood_portmask - flooding porkmask
+ * pFlood_portmask - flooding portmask
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
/* Function Name:
* rtk_l2_localPktPermit_set
* Description:
- * Set permittion of frames if source port and destination port are the same.
+ * Set permission of frames if source port and destination port are the same.
* Input:
* port - Port id.
- * permit - permittion status
+ * permit - permission status
* Output:
* None
* Return:
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_ENABLE - Invalid permit value.
* Note:
- * This API is setted to permit frame if its source port is equal to destination port.
+ * This API is set to permit frame if its source port is equal to destination port.
*/
extern rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit);
/* Function Name:
* rtk_l2_localPktPermit_get
* Description:
- * Get permittion of frames if source port and destination port are the same.
+ * Get permission of frames if source port and destination port are the same.
* Input:
* port - Port id.
* Output:
- * pPermit - permittion status
+ * pPermit - permission status
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
- * This API is to get permittion status for frames if its source port is equal to destination port.
+ * This API is to get permission status for frames if its source port is equal to destination port.
*/
extern rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit);
/* Function Name:
* rtk_l2_aging_set
* Description:
- * Set LUT agging out speed
+ * Set LUT ageing out speed
* Input:
- * aging_time - Agging out time.
+ * aging_time - Ageing out time.
* Output:
* None
* Return:
* RT_ERR_SMI - SMI access error
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
- * The API can set LUT agging out period for each entry and the range is from 14s to 800s.
+ * The API can set LUT ageing out period for each entry and the range is from 14s to 800s.
*/
extern rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time);
/* Function Name:
* rtk_l2_aging_get
* Description:
- * Get LUT agging out time
+ * Get LUT ageing out time
* Input:
* None
* Output:
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
- * The API can get LUT agging out period for each entry.
+ * The API can get LUT ageing out period for each entry.
*/
extern rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time);
/* Function Name:
* rtk_l2_ipMcastAddrLookup_set
* Description:
- * Set Lut IP multicast lookup function
+ * Set LUT IP multicast lookup function
* Input:
* type - Lookup type for IPMC packet.
* Output:
/* Function Name:
* rtk_l2_ipMcastAddrLookup_get
* Description:
- * Get Lut IP multicast lookup function
+ * Get LUT IP multicast lookup function
* Input:
* None.
* Output:
/* Function Name:
* rtk_l2_ipMcastForwardRouterPort_set
* Description:
- * Set IPMC packet forward to rounter port also or not
+ * Set IPMC packet forward to router port also or not
* Input:
- * enabled - 1: Inlcude router port, 0, exclude router port
+ * enabled - 1: Include router port, 0, exclude router port
* Output:
* None.
* Return:
/* Function Name:
* rtk_l2_ipMcastForwardRouterPort_get
* Description:
- * Get IPMC packet forward to rounter port also or not
+ * Get IPMC packet forward to router port also or not
* Input:
* None.
* Output:
- * pEnabled - 1: Inlcude router port, 0, exclude router port
+ * pEnabled - 1: Include router port, 0, exclude router port
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes Leaky module high-layer API defination
+ * Feature : The file includes Leaky module high-layer API definition
*
*/
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes LED module high-layer API defination
+ * Feature : The file includes LED module high-layer API definition
*
*/
/* Function Name:
* rtk_led_enable_set
* Description:
- * Set Led enable congiuration
+ * Set Led enable configuration
* Input:
* group - LED group id.
* pPortmask - LED enable port mask.
/* Function Name:
* rtk_led_enable_get
* Description:
- * Get Led enable congiuration
+ * Get Led enable configuration
* Input:
* group - LED group id.
* Output:
/* Function Name:
* rtk_led_modeForce_set
* Description:
- * Set Led group to congiuration force mode
+ * Set Led group to configuration force mode
* Input:
* port - port ID
* group - Support LED group id.
/* Function Name:
* rtk_led_modeForce_get
* Description:
- * Get Led group to congiuration force mode
+ * Get Led group to configuration force mode
* Input:
* port - port ID
* group - Support LED group id.
/* Function Name:
* rtk_led_groupConfig_set
* Description:
- * Set per group Led to congiuration mode
+ * Set per group Led to configuration mode
* Input:
* group - LED group.
* config - LED configuration
/* Function Name:
* rtk_led_groupConfig_get
* Description:
- * Get Led group congiuration mode
+ * Get Led group configuration mode
* Input:
* group - LED group.
* Output:
/* Function Name:
* rtk_led_serialMode_set
* Description:
- * Set Led serial mode active congiuration
+ * Set Led serial mode active configuration
* Input:
* active - LED group.
* Output:
* RT_ERR_SMI - SMI access error
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * The API can set LED serial mode active congiuration.
+ * The API can set LED serial mode active configuration.
*/
extern rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active);
/* Function Name:
* rtk_led_serialMode_get
* Description:
- * Get Led group congiuration mode
+ * Get Led group configuration mode
* Input:
* group - LED group.
* Output:
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes Mirror module high-layer API defination
+ * Feature : The file includes Mirror module high-layer API definition
*
*/
* RT_ERR_SMI - SMI access error
* RT_ERR_ENABLE - Invalid enable input
* Note:
- * The API is to set mirror isolation function that prevent normal forwarding packets to miror port.
+ * The API is to set mirror isolation function that prevent normal forwarding packets to mirror port.
*/
extern rtk_api_ret_t rtk_mirror_portIso_set(rtk_enable_t enable);
* RT_ERR_SMI - SMI access error
* RT_ERR_ENABLE - Invalid enable input
* Note:
- * The API is to set mirror VLAN leaky function forwarding packets to miror port.
+ * The API is to set mirror VLAN leaky function forwarding packets to mirror port.
*/
extern rtk_api_ret_t rtk_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable);
* RT_ERR_SMI - SMI access error
* RT_ERR_ENABLE - Invalid enable input
* Note:
- * The API is to set mirror VLAN leaky function forwarding packets to miror port.
+ * The API is to set mirror VLAN leaky function forwarding packets to mirror port.
*/
extern rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable);
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes port module high-layer API defination
+ * Feature : The file includes port module high-layer API definition
*
*/
/* Function Name:
* rtk_port_phyAutoNegoAbility_set
* Description:
- * Set ethernet PHY auto-negotiation desired ability.
+ * Set Ethernet PHY auto-negotiation desired ability.
* Input:
* port - port id.
* pAbility - Ability structure
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy
* Note:
- * Get the capablity of specified PHY.
+ * Get the capability of specified PHY.
*/
extern rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility);
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy
* Note:
- * Get the capablity of specified PHY.
+ * Get the capability of specified PHY.
*/
extern rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility);
/* Function Name:
* rtk_port_phyStatus_get
* Description:
- * Get ethernet PHY linking status
+ * Get Ethernet PHY linking status
* Input:
* port - Port id.
* Output:
* For UTP port, This API will also enable the digital
* loopback bit in PHY register for sync of speed between
* PHY and MAC. For EXT port, users need to force the
- * link state by themself.
+ * link state by themselves.
*/
extern rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable);
/* Function Name:
* rtk_port_backpressureEnable_set
* Description:
- * Set the half duplex backpressure enable status of the specific port.
+ * Set the half duplex back-pressure enable status of the specific port.
* Input:
* port - port id.
* enable - Back pressure status.
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_ENABLE - Invalid enable input.
* Note:
- * This API can set the half duplex backpressure enable status of the specific port.
- * The half duplex backpressure enable status of the port is as following:
+ * This API can set the half duplex back-pressure enable status of the specific port.
+ * The half duplex back-pressure enable status of the port is as following:
* - DISABLE
* - ENABLE
*/
/* Function Name:
* rtk_port_backpressureEnable_get
* Description:
- * Get the half duplex backpressure enable status of the specific port.
+ * Get the half duplex back-pressure enable status of the specific port.
* Input:
* port - Port id.
* Output:
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
- * This API can get the half duplex backpressure enable status of the specific port.
- * The half duplex backpressure enable status of the port is as following:
+ * This API can get the half duplex back-pressure enable status of the specific port.
+ * The half duplex back-pressure enable status of the port is as following:
* - DISABLE
* - ENABLE
*/
/* Function Name:
* rtk_port_adminEnable_get
* Description:
- * Get port admin configurationof the specific port.
+ * Get port admin configuration of the specific port.
* Input:
* port - Port id.
* Output:
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_PORT_MASK - Invalid portmask.
* Note:
- * This API set the port mask that a port can trasmit packet to of each port
+ * This API set the port mask that a port can transmit packet to of each port
* A port can only transmit packet to ports included in permitted portmask
*/
extern rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask);
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
- * This API get the port mask that a port can trasmit packet to of each port
+ * This API get the port mask that a port can transmit packet to of each port
* A port can only transmit packet to ports included in permitted portmask
*/
extern rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask);
* Note:
* This API can set external interface 2 RGMII delay.
* In TX delay, there are 2 selection: no-delay and 2ns delay.
- * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay.
+ * In RX delay, there are 8 steps for delay tuning. 0 for no-delay, and 7 for maximum delay.
*/
extern rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay);
* Note:
* This API can set external interface 2 RGMII delay.
* In TX delay, there are 2 selection: no-delay and 2ns delay.
- * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay.
+ * In RX delay, there are 8 steps for delay tuning. 0 for n0-delay, and 7 for maximum delay.
*/
extern rtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay);
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes time module high-layer API defination
+ * Feature : The file includes time module high-layer API definition
*
*/
/* Function Name:
* rtk_ptp_portTimestamp_get
* Description:
- * Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device.
+ * Get PTP timestamp according to the PTP identifier on the dedicated port from the specified device.
* Input:
* unit - unit id
* port - port id
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes QoS module high-layer API defination
+ * Feature : The file includes QoS module high-layer API definition
*
*/
/* Function Name:
* rtk_qos_init
* Description:
- * Configure Qos default settings with queue number assigment to each port.
+ * Configure QoS default settings with queue number assignment to each port.
* Input:
* queueNum - Queue number of each port.
* Output:
* RT_ERR_QUEUE_NUM - Invalid queue number.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * This API will initialize related Qos setting with queue number assigment.
+ * This API will initialize related QoS setting with queue number assignment.
* The queue number is from 1 to 8.
*/
extern rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum);
* RT_ERR_VLAN_PRIORITY - Invalid priority.
* RT_ERR_QOS_INT_PRIORITY - Invalid priority.
* Note:
- * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling.
+ * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling.
*/
extern rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri);
*
* Purpose : RTL8367/RTL8367C switch high-level API
*
- * Feature : The file includes rate module high-layer API defination
+ * Feature : The file includes rate module high-layer API definition
*
*/
RT_ERR_NULL_POINTER, /* 0x00000007, input parameter is null pointer */
RT_ERR_QUEUE_ID, /* 0x00000008, invalid queue id */
RT_ERR_QUEUE_NUM, /* 0x00000009, invalid queue number */
- RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy watting time out */
+ RT_ERR_BUSYWAIT_TIMEOUT, /* 0x0000000a, busy waiting time out */
RT_ERR_MAC, /* 0x0000000b, invalid mac address */
RT_ERR_OUT_OF_RANGE, /* 0x0000000c, input parameter out of range */
RT_ERR_CHIP_NOT_SUPPORTED, /* 0x0000000d, functions not supported by this chip model */
/* 0x0001xxxx for vlan */
RT_ERR_VLAN_VID = 0x00010000, /* 0x00010000, invalid vid */
RT_ERR_VLAN_PRIORITY, /* 0x00010001, invalid 1p priority */
- RT_ERR_VLAN_EMPTY_ENTRY, /* 0x00010002, emtpy entry of vlan table */
+ RT_ERR_VLAN_EMPTY_ENTRY, /* 0x00010002, empty entry of vlan table */
RT_ERR_VLAN_ACCEPT_FRAME_TYPE, /* 0x00010003, invalid accept frame type */
RT_ERR_VLAN_EXIST, /* 0x00010004, vlan is exist */
RT_ERR_VLAN_ENTRY_NOT_FOUND, /* 0x00010005, specified vlan entry not found */
RT_ERR_INBW_TOKEN_AMOUNT, /* 0x000c0001, invalid amount of token for input bandwidth control */
RT_ERR_INBW_FCON_VALUE, /* 0x000c0002, invalid flow control ON threshold value for input bandwidth control */
RT_ERR_INBW_FCOFF_VALUE, /* 0x000c0003, invalid flow control OFF threshold value for input bandwidth control */
- RT_ERR_INBW_FC_ALLOWANCE, /* 0x000c0004, invalid allowance of incomming packet for input bandwidth control */
+ RT_ERR_INBW_FC_ALLOWANCE, /* 0x000c0004, invalid allowance of incoming packet for input bandwidth control */
RT_ERR_INBW_RATE, /* 0x000c0005, invalid input bandwidth */
/* 0x000dxxxx for QoS */
RT_ERR_DOT1X_PROC, /* 0x00110006, unauthorized behavior error */
RT_ERR_DOT1X_GVLANIDX, /* 0x00110007, guest vlan index error */
RT_ERR_DOT1X_GVLANTALK, /* 0x00110008, guest vlan OPDIR error */
- RT_ERR_DOT1X_MAC_PORT_MISMATCH, /* 0x00110009, Auth MAC and port mismatch eror */
+ RT_ERR_DOT1X_MAC_PORT_MISMATCH, /* 0x00110009, Auth MAC and port mismatch error */
RT_ERR_END /* The symbol is the latest symbol */
} rt_error_code_t;
#define RTK_SCAN_ALL_LOG_PORT(__port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if( rtk_switch_logicalPortCheck(__port__) == RT_ERR_OK)
#define RTK_SCAN_ALL_LOG_PORTMASK(__portmask__) for((__portmask__).bits[0] = 0; (__portmask__).bits[0] < 0x7FFFF; (__portmask__).bits[0]++) if( rtk_switch_isPortMaskValid(&__portmask__) == RT_ERR_OK)
-/* Port mask defination */
+/* Port mask definition */
#define RTK_PHY_PORTMASK_ALL (rtk_switch_phyPortMask_get())
-/* Port defination*/
+/* Port definition*/
#define RTK_MAX_LOGICAL_PORT_ID (rtk_switch_maxLogicalPort_get())
/* Function Name:
/* Function Name:
* rtk_switch_portmask_L2P_get
* Description:
- * Get physicl portmask from logical portmask
+ * Get physical portmask from logical portmask
* Input:
* pLogicalPmask - logical port mask
* Output:
/* Function Name:
* rtk_switch_init
* Description:
- * Set chip to default configuration enviroment
+ * Set chip to default configuration environment
* Input:
* None
* Output:
#define ETHER_ADDR_LEN 6
#endif
-/* ethernet address type */
+/* Ethernet address type */
typedef struct rtk_mac_s
{
rtk_uint8 octet[ETHER_ADDR_LEN];
} rtk_mac_t;
-typedef rtk_uint32 rtk_pri_t; /* priority vlaue */
+typedef rtk_uint32 rtk_pri_t; /* priority value */
typedef rtk_uint32 rtk_qid_t; /* queue id type */
typedef rtk_uint32 rtk_data_t;
typedef rtk_uint32 rtk_dscp_t; /* dscp vlaue */
extern ret_t rtl8367c_getAsicCputagInsertMode(rtk_uint32 *pMode);
extern ret_t rtl8367c_setAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 newPri);
extern ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNewPri);
-extern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion);
+extern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 position);
extern ret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion);
extern ret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode);
extern ret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode);
* $Date: 2017-03-08 15:13:58 +0800 (¶g¤T, 08 ¤T¤ë 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
- * Feature : Green ethernet related functions
+ * Feature : Green Ethernet related functions
*
*/
* $Date: 2017-03-08 15:13:58 +0800 (¶g¤T, 08 ¤T¤ë 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
- * Feature : Qos related functions
+ * Feature : QoS related functions
*
*/
* $Date: 2017-03-08 15:13:58 +0800 (¶g¤T, 08 ¤T¤ë 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
- * Feature : Unkown multicast related functions
+ * Feature : Unknown multicast related functions
*
*/
* $Date: 2017-03-08 15:13:58 +0800 (¶g¤T, 08 ¤T¤ë 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
- * Feature : Regsiter MACRO related definition
+ * Feature : Register MACRO related definition
*
*/
#define RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_MASK 0x2000
#define RTL8367C_REPORT_FORWARD_OFFSET 12
#define RTL8367C_REPORT_FORWARD_MASK 0x1000
-#define RTL8367C_ROBURSTNESS_VAR_OFFSET 9
-#define RTL8367C_ROBURSTNESS_VAR_MASK 0xE00
+#define RTL8367C_ROBUSTNESS_VAR_OFFSET 9
+#define RTL8367C_ROBUSTNESS_VAR_MASK 0xE00
#define RTL8367C_LEAVE_SUPPRESSION_OFFSET 8
#define RTL8367C_LEAVE_SUPPRESSION_MASK 0x100
#define RTL8367C_REPORT_SUPPRESSION_OFFSET 7
* RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * If the unicast mac address already existed in LUT, it will udpate the status of the entry.
+ * If the unicast mac address already existed in LUT, it will update the status of the entry.
* Otherwise, it will find an empty or asic auto learned entry to write. If all the entries
* with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.
*/
* RT_ERR_PORT_MASK - Invalid portmask.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * If the multicast mac address already existed in the LUT, it will udpate the
+ * If the multicast mac address already existed in the LUT, it will update the
* port mask of the entry. Otherwise, it will find an empty or asic auto learned
* entry to write. If all the entries with the same hash value can't be replaced,
* ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.
/* Function Name:
* rtk_l2_ipMcastAddr_add
* Description:
- * Add Lut IP multicast entry
+ * Add LUT IP multicast entry
* Input:
* pIpMcastAddr - IP Multicast entry
* Output:
* RT_ERR_L2_ENTRY_NOTFOUND - No such LUT entry.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * The API can get Lut table of IP multicast entry.
+ * The API can get LUT table of IP multicast entry.
*/
rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr)
{
/* Function Name:
* rtk_l2_ipVidMcastAddr_add
* Description:
- * Add Lut IP multicast+VID entry
+ * Add LUT IP multicast+VID entry
* Input:
* pIpVidMcastAddr - IP & VID multicast Entry
* Output:
* Set flooding portmask
* Input:
* type - flooding type.
- * pFlood_portmask - flooding porkmask
+ * pFlood_portmask - flooding portmask
* Output:
* None
* Return:
* Input:
* type - flooding type.
* Output:
- * pFlood_portmask - flooding porkmask
+ * pFlood_portmask - flooding portmask
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
/* Function Name:
* rtk_l2_localPktPermit_set
* Description:
- * Set permittion of frames if source port and destination port are the same.
+ * Set permission of frames if source port and destination port are the same.
* Input:
* port - Port id.
- * permit - permittion status
+ * permit - permission status
* Output:
* None
* Return:
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_ENABLE - Invalid permit value.
* Note:
- * This API is setted to permit frame if its source port is equal to destination port.
+ * This API is set to permit frame if its source port is equal to destination port.
*/
rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit)
{
/* Function Name:
* rtk_l2_localPktPermit_get
* Description:
- * Get permittion of frames if source port and destination port are the same.
+ * Get permission of frames if source port and destination port are the same.
* Input:
* port - Port id.
* Output:
- * pPermit - permittion status
+ * pPermit - permission status
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
- * This API is to get permittion status for frames if its source port is equal to destination port.
+ * This API is to get permission status for frames if its source port is equal to destination port.
*/
rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit)
{
/* Function Name:
* rtk_l2_aging_set
* Description:
- * Set LUT agging out speed
+ * Set LUT ageing out speed
* Input:
- * aging_time - Agging out time.
+ * aging_time - Ageing out time.
* Output:
* None
* Return:
* RT_ERR_SMI - SMI access error
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
- * The API can set LUT agging out period for each entry and the range is from 45s to 458s.
+ * The API can set LUT ageing out period for each entry and the range is from 45s to 458s.
*/
rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time)
{
/* Function Name:
* rtk_l2_aging_get
* Description:
- * Get LUT agging out time
+ * Get LUT ageing out time
* Input:
* None
* Output:
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
- * The API can get LUT agging out period for each entry.
+ * The API can get LUT ageing out period for each entry.
*/
rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time)
{
/* Function Name:
* rtk_l2_ipMcastAddrLookup_set
* Description:
- * Set Lut IP multicast lookup function
+ * Set LUT IP multicast lookup function
* Input:
* type - Lookup type for IPMC packet.
* Output:
/* Function Name:
* rtk_l2_ipMcastAddrLookup_get
* Description:
- * Get Lut IP multicast lookup function
+ * Get LUT IP multicast lookup function
* Input:
* None.
* Output:
/* Function Name:
* rtk_l2_ipMcastForwardRouterPort_set
* Description:
- * Set IPMC packet forward to rounter port also or not
+ * Set IPMC packet forward to router port also or not
* Input:
- * enabled - 1: Inlcude router port, 0, exclude router port
+ * enabled - 1: Include router port, 0, exclude router port
* Output:
* None.
* Return:
/* Function Name:
* rtk_l2_ipMcastForwardRouterPort_get
* Description:
- * Get IPMC packet forward to rounter port also or not
+ * Get IPMC packet forward to router port also or not
* Input:
* None.
* Output:
- * pEnabled - 1: Inlcude router port, 0, exclude router port
+ * pEnabled - 1: Include router port, 0, exclude router port
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
/* Function Name:
* rtk_led_enable_set
* Description:
- * Set Led enable congiuration
+ * Set Led enable configuration
* Input:
* group - LED group id.
* pPortmask - LED enable port mask.
/* Function Name:
* rtk_led_enable_get
* Description:
- * Get Led enable congiuration
+ * Get Led enable configuration
* Input:
* group - LED group id.
* Output:
/* Function Name:
* rtk_led_modeForce_set
* Description:
- * Set Led group to congiuration force mode
+ * Set Led group to configuration force mode
* Input:
* port - port ID
* group - Support LED group id.
/* Function Name:
* rtk_led_modeForce_get
* Description:
- * Get Led group to congiuration force mode
+ * Get Led group to configuration force mode
* Input:
* port - port ID
* group - Support LED group id.
/* Function Name:
* rtk_led_groupConfig_set
* Description:
- * Set per group Led to congiuration mode
+ * Set per group Led to configuration mode
* Input:
* group - LED group.
* config - LED configuration
/* Function Name:
* rtk_led_groupConfig_get
* Description:
- * Get Led group congiuration mode
+ * Get Led group configuration mode
* Input:
* group - LED group.
* Output:
/* Function Name:
* rtk_led_serialMode_set
* Description:
- * Set Led serial mode active congiuration
+ * Set Led serial mode active configuration
* Input:
* active - LED group.
* Output:
* RT_ERR_SMI - SMI access error
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * The API can set LED serial mode active congiuration.
+ * The API can set LED serial mode active configuration.
*/
rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active)
{
RTK_CHK_PORTMASK_VALID(pMirrored_tx_portmask);
- /*Mirror Sorce Port Mask Check*/
+ /*Mirror Source Port Mask Check*/
if (pMirrored_tx_portmask->bits[0]!=pMirrored_rx_portmask->bits[0]&&pMirrored_tx_portmask->bits[0]!=0&&pMirrored_rx_portmask->bits[0]!=0)
return RT_ERR_PORT_MASK;
* RT_ERR_SMI - SMI access error
* RT_ERR_ENABLE - Invalid enable input
* Note:
- * The API is to set mirror VLAN leaky function forwarding packets to miror port.
+ * The API is to set mirror VLAN leaky function forwarding packets to mirror port.
*/
rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable)
{
/* Function Name:
* rtk_port_phyAutoNegoAbility_set
* Description:
- * Set ethernet PHY auto-negotiation desired ability.
+ * Set Ethernet PHY auto-negotiation desired ability.
* Input:
* port - port id.
* pAbility - Ability structure
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy
* Note:
- * Get the capablity of specified PHY.
+ * Get the capability of specified PHY.
*/
rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility)
{
if (1 == pAbility->AsyFC)
{
- /*Asymetric flow control in reg 4.11*/
+ /*Asymmetric flow control in reg 4.11*/
phyEnMsk4 = phyEnMsk4 | (1 << 11);
}
if (1 == pAbility->FC)
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy
* Note:
- * Get the capablity of specified PHY.
+ * Get the capability of specified PHY.
*/
rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility)
{
/* Function Name:
* rtk_port_phyStatus_get
* Description:
- * Get ethernet PHY linking status
+ * Get Ethernet PHY linking status
* Input:
* port - Port id.
* Output:
* For UTP port, This API will also enable the digital
* loopback bit in PHY register for sync of speed between
* PHY and MAC. For EXT port, users need to force the
- * link state by themself.
+ * link state by themselves.
*/
rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable)
{
/* Function Name:
* rtk_port_backpressureEnable_set
* Description:
- * Set the half duplex backpressure enable status of the specific port.
+ * Set the half duplex back-pressure enable status of the specific port.
* Input:
* port - port id.
* enable - Back pressure status.
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_ENABLE - Invalid enable input.
* Note:
- * This API can set the half duplex backpressure enable status of the specific port.
- * The half duplex backpressure enable status of the port is as following:
+ * This API can set the half duplex back-pressure enable status of the specific port.
+ * The half duplex back-pressure enable status of the port is as following:
* - DISABLE(Defer)
- * - ENABLE (Backpressure)
+ * - ENABLE (Back-pressure)
*/
rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable)
{
/* Function Name:
* rtk_port_backpressureEnable_get
* Description:
- * Get the half duplex backpressure enable status of the specific port.
+ * Get the half duplex back-pressure enable status of the specific port.
* Input:
* port - Port id.
* Output:
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
- * This API can get the half duplex backpressure enable status of the specific port.
- * The half duplex backpressure enable status of the port is as following:
+ * This API can get the half duplex back-pressure enable status of the specific port.
+ * The half duplex back-pressure enable status of the port is as following:
* - DISABLE(Defer)
- * - ENABLE (Backpressure)
+ * - ENABLE (Back-pressure)
*/
rtk_api_ret_t rtk_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable)
{
/* Function Name:
* rtk_port_adminEnable_get
* Description:
- * Get port admin configurationof the specific port.
+ * Get port admin configuration of the specific port.
* Input:
* port - Port id.
* Output:
* RT_ERR_PORT_ID - Invalid port number.
* RT_ERR_PORT_MASK - Invalid portmask.
* Note:
- * This API set the port mask that a port can trasmit packet to of each port
+ * This API set the port mask that a port can transmit packet to of each port
* A port can only transmit packet to ports included in permitted portmask
*/
rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask)
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number.
* Note:
- * This API get the port mask that a port can trasmit packet to of each port
+ * This API get the port mask that a port can transmit packet to of each port
* A port can only transmit packet to ports included in permitted portmask
*/
rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask)
* Note:
* This API can set external interface 2 RGMII delay.
* In TX delay, there are 2 selection: no-delay and 2ns delay.
- * In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay.
+ * In RX delay, there are 8 steps for delay tuning. 0 for no-delay, and 7 for maximum delay.
*/
rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay)
{
* Note:
* This API can set external interface 2 RGMII delay.
* In TX delay, there are 2 selection: no-delay and 2ns delay.
- * In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay.
+ * In RX delay, there are 8 steps for delay tuning. 0 for n0-delay, and 7 for maximum delay.
*/
rtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay)
{
/* Function Name:
* rtk_ptp_portTimestamp_get
* Description:
- * Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device.
+ * Get PTP timestamp according to the PTP identifier on the dedicated port from the specified device.
* Input:
* unit - unit id
* port - port id
/* Function Name:
* rtk_qos_init
* Description:
- * Configure Qos default settings with queue number assigment to each port.
+ * Configure QoS default settings with queue number assignment to each port.
* Input:
* queueNum - Queue number of each port.
* Output:
* RT_ERR_QUEUE_NUM - Invalid queue number.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * This API will initialize related Qos setting with queue number assigment.
+ * This API will initialize related QoS setting with queue number assignment.
* The queue number is from 1 to 8.
*/
rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum)
return retVal;
}
- /* Finetune B/T value */
+ /* Fine-tune B/T value */
if((retVal = rtl8367c_setAsicReg(0x1722, 0x1158)) != RT_ERR_OK)
return retVal;
* RT_ERR_VLAN_PRIORITY - Invalid priority.
* RT_ERR_QOS_INT_PRIORITY - Invalid priority.
* Note:
- * Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling.
+ * Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling.
*/
rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri)
{
* available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
*
* $Revision: 76306 $
- * $Date: 2017-03-08 15:13:58 +0800 (¶g¤T, 08 ¤T¤ë 2017) $
+ * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : Declaration of RLDP and RLPP API
*
* RT_ERR_NULL_POINTER
* Note:
* Clear operation effect loop_enter and loop_leave only, other field in
- * the structure are don't care. Loop status cab't be clean.
+ * the structure are don't care. Loop status can't be clean.
*/
rtk_api_ret_t rtk_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus)
{
/* Minimum physical port number */
0,
- /* Maxmum physical port number */
+ /* Maximum physical port number */
10,
/* Physical port mask */
/* Minimum physical port number */
0,
- /* Maxmum physical port number */
+ /* Maximum physical port number */
7,
/* Physical port mask */
/* Minimum physical port number */
0,
- /* Maxmum physical port number */
+ /* Maximum physical port number */
7,
/* Physical port mask */
/* Function Name:
* rtk_switch_portmask_L2P_get
* Description:
- * Get physicl portmask from logical portmask
+ * Get physical portmask from logical portmask
* Input:
* pLogicalPmask - logical port mask
* Output:
/* Function Name:
* rtk_switch_init
* Description:
- * Set chip to default configuration enviroment
+ * Set chip to default configuration environment
* Input:
* None
* Output:
/* Function Name:
* rtl8367c_setAsicAcl
* Description:
- * Set port acl function enable/disable
+ * Set port ACL function enable/disable
* Input:
* port - Physical port number (0~10)
* enabled - 1: enabled, 0: disabled
/* Function Name:
* rtl8367c_getAsicAcl
* Description:
- * Get port acl function enable/disable
+ * Get port ACL function enable/disable
* Input:
* port - Physical port number (0~10)
* enabled - 1: enabled, 0: disabled
/* Function Name:
* rtl8367c_setAsicAclUnmatchedPermit
* Description:
- * Set port acl function unmatched permit action
+ * Set port ACL function unmatched permit action
* Input:
* port - Physical port number (0~10)
* enabled - 1: enabled, 0: disabled
/* Function Name:
* rtl8367c_getAsicAclUnmatchedPermit
* Description:
- * Get port acl function unmatched permit action
+ * Get port ACL function unmatched permit action
* Input:
* port - Physical port number (0~10)
* enabled - 1: enabled, 0: disabled
/* Function Name:
* rtl8367c_setAsicAclRule
* Description:
- * Set acl rule content
+ * Set ACL rule content
* Input:
* index - ACL rule index (0-95) of 96 ACL rules
- * pAclRule - ACL rule stucture for setting
+ * pAclRule - ACL rule structure for setting
* Output:
* None
* Return:
* RT_ERR_OUT_OF_RANGE - Invalid ACL rule index (0-95)
* Note:
* System supported 95 shared 289-bit ACL ingress rule. Index was available at range 0-95 only.
- * If software want to modify ACL rule, the ACL function should be disable at first or unspecify
- * acl action will be executed.
+ * If software want to modify ACL rule, the ACL function should be disabled at first or unspecified
+ * ACL action will be executed.
* One ACL rule structure has three parts setting:
* Bit 0-147 Data Bits of this Rule
* Bit 148 Valid Bit
/* Function Name:
* rtl8367c_getAsicAclRule
* Description:
- * Get acl rule content
+ * Get ACL rule content
* Input:
* index - ACL rule index (0-63) of 64 ACL rules
- * pAclRule - ACL rule stucture for setting
+ * pAclRule - ACL rule structure for setting
* Output:
* None
* Return:
* Set fields of a ACL Template
* Input:
* index - ACL template index(0~4)
- * pAclType - ACL type stucture for setting
+ * pAclType - ACL type structure for setting
* Output:
* None
* Return:
* Note:
* The API can set type field of the 5 ACL rule templates.
* Each type has 8 fields. One field means what data in one field of a ACL rule means
- * 8 fields of ACL rule 0~95 is descripted by one type in ACL group
+ * 8 fields of ACL rule 0~95 is described by one type in ACL group
*/
ret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAclType)
{
* Get fields of a ACL Template
* Input:
* index - ACL template index(0~4)
- * pAclType - ACL type stucture for setting
+ * pAclType - ACL type structure for setting
* Output:
* None
* Return:
* Set ACL rule matched Action
* Input:
* index - ACL rule index (0-95) of 96 ACL rules
- * pAclAct - ACL action stucture for setting
+ * pAclAct - ACL action structure for setting
* Output:
* None
* Return:
* Get ACL rule matched Action
* Input:
* index - ACL rule index (0-95) of 96 ACL rules
- * pAclAct - ACL action stucture for setting
+ * pAclAct - ACL action structure for setting
* Output:
* None
* Return:
/* Function Name:
* rtl8367c_setAsicAclGpioPolarity
* Description:
- * Set ACL Goip control palarity
+ * Set ACL Goip control polarity
* Input:
* polarity - 1: High, 0: Low
* Output:
/* Function Name:
* rtl8367c_getAsicAclGpioPolarity
* Description:
- * Get ACL Goip control palarity
+ * Get ACL Goip control polarity
* Input:
* pPolarity - 1: High, 0: Low
* Output:
/* Function Name:
* rtl8367c_setAsicCputagEnable
* Description:
- * Set cpu tag function enable/disable
+ * Set CPU tag function enable/disable
* Input:
* enabled - 1: enabled, 0: disabled
* Output:
/* Function Name:
* rtl8367c_getAsicCputagEnable
* Description:
- * Get cpu tag function enable/disable
+ * Get CPU tag function enable/disable
* Input:
* pEnabled - 1: enabled, 0: disabled
* Output:
/* Function Name:
* rtl8367c_setAsicCputagTrapPort
* Description:
- * Set cpu tag trap port
+ * Set CPU tag trap port
* Input:
* port - port number
* Output:
/* Function Name:
* rtl8367c_getAsicCputagTrapPort
* Description:
- * Get cpu tag trap port
+ * Get CPU tag trap port
* Input:
* pPort - port number
* Output:
/* Function Name:
* rtl8367c_setAsicCputagPosition
* Description:
- * Set cpu tag insert position
+ * Set CPU tag insert position
* Input:
- * postion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default)
+ * position - 1: After entire packet(before CRC field), 0: After MAC_SA (Default)
* Output:
* None
* Return:
* Note:
* None
*/
-ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion)
+ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 position)
{
- return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, postion);
+ return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, position);
}
/* Function Name:
* rtl8367c_getAsicCputagPosition
* Description:
- * Get cpu tag insert position
+ * Get CPU tag insert position
* Input:
* pPostion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default)
* Output:
/* Function Name:
* rtl8367c_setAsicCputagMode
* Description:
- * Set cpu tag mode
+ * Set CPU tag mode
* Input:
* mode - 1: 4bytes mode, 0: 8bytes mode
* Output:
/* Function Name:
* rtl8367c_getAsicCputagMode
* Description:
- * Get cpu tag mode
+ * Get CPU tag mode
* Input:
* pMode - 1: 4bytes mode, 0: 8bytes mode
* Output:
/* Function Name:
* rtl8367c_setAsicCputagRxMinLength
* Description:
- * Set cpu tag mode
+ * Set CPU tag mode
* Input:
* mode - 1: 64bytes, 0: 72bytes
* Output:
/* Function Name:
* rtl8367c_getAsicCputagRxMinLength
* Description:
- * Get cpu tag mode
+ * Get CPU tag mode
* Input:
* pMode - 1: 64bytes, 0: 72bytes
* Output:
* Description:
* Set PTP parser tag TPID.
* Input:
- * outerTag - outter tag TPID
+ * outerTag - outer tag TPID
* innerTag - inner tag TPID
* Output:
* None
* Input:
* None
* Output:
- * pOuterTag - outter tag TPID
+ * pOuterTag - outer tag TPID
* pInnerTag - inner tag TPID
* Return:
* RT_ERR_OK - Success
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
- * The time granuality is 8 nano seconds.
+ * The time granularity is 8 nano seconds.
*/
ret_t rtl8367c_setAsicEavSysTime(rtk_uint32 second, rtk_uint32 nanoSecond)
{
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
- * The time granuality is 8 nano seconds.
+ * The time granularity is 8 nano seconds.
*/
ret_t rtl8367c_getAsicEavSysTime(rtk_uint32* pSecond, rtk_uint32* pNanoSecond)
{
* Description:
* Set PTP system time adjust
* Input:
- * type - incresae or decrease
+ * type - increase or decrease
* second - seconds
* nanoSecond - nano seconds
* Output:
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
- * This API can be used to clear ASIC interrupt status and register will be cleared by writting 1.
+ * This API can be used to clear ASIC interrupt status and register will be cleared by writing 1.
* [0]:TX_SYNC,
* [1]:TX_DELAY,
* [2]:TX_PDELAY_REQ,
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number
* Note:
- * If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping
+ * If EAV function is enabled, PTP event message packet will be attached PTP timestamp for trapping
*/
ret_t rtl8367c_setAsicEavPortEnable(rtk_uint32 port, rtk_uint32 enabled)
{
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
- * The time granuality is 8 nano seconds.
+ * The time granularity is 8 nano seconds.
*/
ret_t rtl8367c_getAsicEavPortTimeStamp(rtk_uint32 port, rtk_uint32 type, rtl8367c_ptp_time_stamp_t* timeStamp)
{
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number
* Note:
- * If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping
+ * If EAV function is enabled, PTP event message packet will be attached PTP timestamp for trapping
*/
ret_t rtl8367c_setAsicEavEnable(rtk_uint32 port, rtk_uint32 enabled)
{
/* Function Name:
* rtl8367c_setAsicFlowControlJumboMode
* Description:
- * Set Jumbo threhsold for flow control
+ * Set Jumbo threshold for flow control
* Input:
* enabled - Jumbo mode flow control 1: Enable 0:Disable
* Output:
/* Function Name:
* rtl8367c_getAsicFlowControlJumboMode
* Description:
- * Get Jumbo threhsold for flow control
+ * Get Jumbo threshold for flow control
* Input:
* pEnabled - Jumbo mode flow control 1: Enable 0:Disable
* Output:
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
- * Feature : Green ethernet related functions
+ * Feature : Green Ethernet related functions
*
*/
#include <rtl8367c_asicdrv_green.h>
* Get per-Port ingress page usage per second
* Input:
* port - Physical port number (0~7)
- * pPage - page number of ingress packet occuping per second
+ * pPage - page number of ingress packet occurring per second
* Output:
* None
* Return:
* RT_ERR_SMI - SMI access error
* RT_ERR_PORT_ID - Invalid port number
* Note:
- * Ingress traffic occuping page number per second for high layer green feature usage
+ * Ingress traffic occurring page number per second for high layer green feature usage
*/
ret_t rtl8367c_getAsicGreenPortPage(rtk_uint32 port, rtk_uint32* pPage)
{
* Get indicator which ASIC had received high priority traffic or not
* Input:
* port - Physical port number (0~7)
- * pIndicator - Have received high priority traffic indicator. If 1 means ASCI had received high priority in 1second checking priod
+ * pIndicator - Have received high priority traffic indicator. If 1 means ASCI had received high priority in 1second checking period
* Output:
* None
* Return:
}
/*
-@func rtk_int32 | rtl8367c_setAsicGreenEthernet | Set green ethernet function.
+@func rtk_int32 | rtl8367c_setAsicGreenEthernet | Set green Ethernet function.
@parm rtk_uint32 | green | Green feature function usage 1:enable 0:disable.
@rvalue RT_ERR_OK | Success.
@rvalue RT_ERR_SMI | SMI access error.
@comm
The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic
detect the cable length and then select different power mode for best performance with minimums power consumption. Link down
- ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled.
+ ports will enter power saving mode in 10 seconds after the cable disconnected if power saving function is enabled.
*/
ret_t rtl8367c_setAsicGreenEthernet(rtk_uint32 port, rtk_uint32 green)
{
}
/*
-@func rtk_int32 | rtl8367c_getAsicGreenEthernet | Get green ethernet function.
+@func rtk_int32 | rtl8367c_getAsicGreenEthernet | Get green Ethernet function.
@parm rtk_uint32 | *green | Green feature function usage 1:enable 0:disable.
@rvalue RT_ERR_OK | Success.
@rvalue RT_ERR_SMI | SMI access error.
@comm
The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic
detect the cable length and then select different power mode for best performance with minimums power consumption. Link down
- ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled.
+ ports will enter power saving mode in 10 seconds after the cable disconnected if power saving function is enabled.
*/
ret_t rtl8367c_getAsicGreenEthernet(rtk_uint32 port, rtk_uint32* green)
{
* RT_ERR_SMI - SMI access error
* RT_ERR_OUT_OF_RANGE - input parameter out of range
* Note:
- * System support 16 user defined field selctors.
+ * System support 16 user defined field selectors.
* Each selector can be enabled or disable. User can defined retrieving 16-bits in many predefiend
* standard l2/l3/l4 payload.
*/
if(rob_var > RTL8367C_MAX_ROB_VAR)
return RT_ERR_OUT_OF_RANGE;
- /* Bourstness variable */
- retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, rob_var);
+ /* Robustness variable */
+ retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBUSTNESS_VAR_MASK, rob_var);
if(retVal != RT_ERR_OK)
return retVal;
ret_t retVal;
rtk_uint32 value;
- /* Bourstness variable */
- retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, &value);
+ /* Robustness variable */
+ retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBUSTNESS_VAR_MASK, &value);
if(retVal != RT_ERR_OK)
return retVal;
/* Function Name:
* rtl8367c_setAsicIGMPDropLeaveZero
* Description:
- * Set the function of droppping Leave packet with group IP = 0.0.0.0
+ * Set the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* drop - 1: Drop, 0:Bypass
* Output:
/* Function Name:
* rtl8367c_getAsicIGMPDropLeaveZero
* Description:
- * Get the function of droppping Leave packet with group IP = 0.0.0.0
+ * Get the function of dropping Leave packet with group IP = 0.0.0.0
* Input:
* None
* Output:
/* Function Name:
* rtl8367c_setAsicIGMPBypassStormCTRL
* Description:
- * Set the function of bypass strom control for IGMP/MLD packet
+ * Set the function of bypass storm control for IGMP/MLD packet
* Input:
* bypass - 1: Bypass, 0:not bypass
* Output:
/* Function Name:
* rtl8367c_getAsicIGMPBypassStormCTRL
* Description:
- * Set the function of bypass strom control for IGMP/MLD packet
+ * Set the function of bypass storm control for IGMP/MLD packet
* Input:
* None
* Output:
* Description:
* Get Port Isolation leaky for IGMP/MLD packet
* Input:
- * Noen
+ * None
* Output:
* pLeaky - 1: Leaky, 0:not leaky
* Return:
* Description:
* Get VLAN leaky for IGMP/MLD packet
* Input:
- * Noen
+ * None
* Output:
* pLeaky - 1: Leaky, 0:not leaky
* Return:
/* Function Name:
* rtl8367c_setAsicPortIngressBandwidthBypass
* Description:
- * Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP
+ * Set ingress bandwidth control bypass 8899, RMA 01-80-C2-00-00-xx and IGMP
* Input:
* enabled - 1: enabled, 0: disabled
* Output:
/* Function Name:
* rtl8367c_getAsicPortIngressBandwidthBypass
* Description:
- * Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP
+ * Set ingress bandwidth control bypass 8899, RMA 01-80-C2-00-00-xx and IGMP
* Input:
* pEnabled - 1: enabled, 0: disabled
* Output:
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
- * This API can be used to clear ASIC interrupt status and register will be cleared by writting 1.
+ * This API can be used to clear ASIC interrupt status and register will be cleared by writing 1.
* [0]:Link change,
* [1]:Share meter exceed,
- * [2]:Learn number overed,
+ * [2]:Learn number over,
* [3]:Speed Change,
* [4]:Tx special congestion
* [5]:1 second green feature
/*
@func ret_t | rtl8367c_setAsicLedOutputEnable | Set LED output enable
-@parm rtk_uint32 | enabled | enable or disalbe.
+@parm rtk_uint32 | enabled | enable or disable.
@rvalue RT_ERR_OK | Success.
@rvalue RT_ERR_SMI | SMI access error.
@rvalue RT_ERR_INPUT | Invalid input value.
/* Function Name:
* rtl8367c_setAsicLutIpMulticastLookup
* Description:
- * Set Lut IP multicast lookup function
+ * Set LUT IP multicast lookup function
* Input:
* enabled - 1: enabled, 0: disabled
* Output:
/* Function Name:
* rtl8367c_getAsicLutIpMulticastLookup
* Description:
- * Get Lut IP multicast lookup function
+ * Get LUT IP multicast lookup function
* Input:
* pEnabled - 1: enabled, 0: disabled
* Output:
/* Function Name:
* rtl8367c_setAsicLutIpMulticastLookup
* Description:
- * Set Lut IP multicast + VID lookup function
+ * Set LUT IP multicast + VID lookup function
* Input:
* enabled - 1: enabled, 0: disabled
* Output:
/* Function Name:
* rtl8367c_getAsicLutIpMulticastVidLookup
* Description:
- * Get Lut IP multicast lookup function
+ * Get LUT IP multicast lookup function
* Input:
* pEnabled - 1: enabled, 0: disabled
* Output:
/* Function Name:
* rtl8367c_setAsicLutIpLookupMethod
* Description:
- * Set Lut IP lookup hash with DIP or {DIP,SIP} pair
+ * Set LUT IP lookup hash with DIP or {DIP,SIP} pair
* Input:
* type - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash.
* 0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash.
/* Function Name:
* rtl8367c_getAsicLutIpLookupMethod
* Description:
- * Get Lut IP lookup hash with DIP or {DIP,SIP} pair
+ * Get LUT IP lookup hash with DIP or {DIP,SIP} pair
* Input:
* pType - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash.
* 0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash.
/* Function Name:
* rtl8367c_setAsicLutAgeTimerSpeed
* Description:
- * Set LUT agging out speed
+ * Set LUT ageing out speed
* Input:
- * timer - Agging out timer 0:Has been aged out
- * speed - Agging out speed 0-fastest 3-slowest
+ * timer - Ageing out timer 0:Has been aged out
+ * speed - Ageing out speed 0-fastest 3-slowest
* Output:
* None
* Return:
/* Function Name:
* rtl8367c_getAsicLutAgeTimerSpeed
* Description:
- * Get LUT agging out speed
+ * Get LUT ageing out speed
* Input:
- * pTimer - Agging out timer 0:Has been aged out
- * pSpeed - Agging out speed 0-fastest 3-slowest
+ * pTimer - Ageing out timer 0:Has been aged out
+ * pSpeed - Ageing out speed 0-fastest 3-slowest
* Output:
* None
* Return:
/* Function Name:
* rtl8367c_setAsicLutCamTbUsage
* Description:
- * Configure Lut CAM table usage
+ * Configure LUT CAM table usage
* Input:
* enabled - L2 CAM table usage 1: enabled, 0: disabled
* Output:
/* Function Name:
* rtl8367c_getAsicLutCamTbUsage
* Description:
- * Get Lut CAM table usage
+ * Get LUT CAM table usage
* Input:
* pEnabled - L2 CAM table usage 1: enabled, 0: disabled
* Output:
* Note:
* None
*/
- /*ÐÞ¸Ä: RTL8367C_PORTIDMAX, RTL8367C_LUT_LEARNLIMITMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/
+ /*modification: RTL8367C_PORTIDMAX, RTL8367C_LUT_LEARNLIMITMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/
ret_t rtl8367c_setAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32 number)
{
if(port > RTL8367C_PORTIDMAX)
* Note:
* None
*/
- /*ÐÞ¸Ä: RTL8367C_PORTIDMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/
+ /*modification: RTL8367C_PORTIDMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/
ret_t rtl8367c_getAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32* pNumber)
{
if(port > RTL8367C_PORTIDMAX)
* Note:
* None
*/
- /*ÐÞ¸Ä: RTL8367C_LUT_LEARNLIMITMAX*/
+ /*modification: RTL8367C_LUT_LEARNLIMITMAX*/
ret_t rtl8367c_setAsicSystemLutLearnLimitNo(rtk_uint32 number)
{
if(number > RTL8367C_LUT_LEARNLIMITMAX)
* Note:
* None
*/
- /*ÐÞ¸Ä: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/
+ /*modification: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/
ret_t rtl8367c_setAsicSystemLutLearnPortMask(rtk_uint32 portmask)
{
ret_t retVal;
* Note:
* None
*/
- /*ÐÞ¸Ä: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/
+ /*modification: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/
ret_t rtl8367c_getAsicSystemLutLearnPortMask(rtk_uint32 *pPortmask)
{
rtk_uint32 tmpmask;
* Note:
* None
*/
- /*ÐÞ¸ÄRTL8367C_PORTIDMAX, RTL8367C_REG_L2_LRN_CNT_REG, port10 reg is not contnious, wait for updating of base.h*/
+ /*modification:RTL8367C_PORTIDMAX, RTL8367C_REG_L2_LRN_CNT_REG, port10 reg is not continuous, wait for updating of base.h*/
ret_t rtl8367c_getAsicLutLearnNo(rtk_uint32 port, rtk_uint32* pNumber)
{
ret_t retVal;
* Note:
* None
*/
- /*port8~port10µÄÉèÖÃÔÚÁíÍâÒ»¸öregister, wait for updating of base.h, reg.h*/
+ /*port8~port10 setup is done in a separate register, wait for updating of base.h, reg.h*/
ret_t rtl8367c_setAsicLutForceFlush(rtk_uint32 portmask)
{
ret_t retVal;
* Note:
* None
*/
- /*port8~port10µÄÉèÖÃÔÚÁíÍâÒ»¸öregister, wait for updating of base.h, reg.h*/
+ /*port8~port10 setup is done in a separate register, wait for updating of base.h, reg.h*/
ret_t rtl8367c_getAsicLutForceFlushStatus(rtk_uint32 *pPortmask)
{
rtk_uint32 tmpMask;
* Description:
* Get L2 LUT flush type
* Input:
- * type - 0: dynamice unicast; 1: both dynamic and static unicast entry
+ * type - 0: dynamic unicast; 1: both dynamic and static unicast entry
* Output:
* None
* Return:
* Description:
* Set L2 LUT flush type
* Input:
- * pType - 0: dynamice unicast; 1: both dynamic and static unicast entry
+ * pType - 0: dynamic unicast; 1: both dynamic and static unicast entry
* Output:
* None
* Return:
* Note:
* None
*/
- /*ÐÞ¸ÄRTL8367C_PORTIDMAX*/
+ /*modification:RTL8367C_PORTIDMAX*/
ret_t rtl8367c_setAsicLutDisableAging(rtk_uint32 port, rtk_uint32 disabled)
{
if(port > RTL8367C_PORTIDMAX)
* Note:
* None
*/
- /*ÐÞ¸ÄRTL8367C_PORTIDMAX*/
+ /*modification:RTL8367C_PORTIDMAX*/
ret_t rtl8367c_getAsicLutDisableAging(rtk_uint32 port, rtk_uint32 *pDisabled)
{
if(port > RTL8367C_PORTIDMAX)
/* Function Name:
* rtl8367c_setAsicLutIpmcFwdRouterPort
* Description:
- * Set IPMC packet forward to rounter port also or not
+ * Set IPMC packet forward to router port also or not
* Input:
- * enable - 1: Inlcude router port, 0, exclude router port
+ * enable - 1: Include router port, 0, exclude router port
* Output:
* None
* Return:
/* Function Name:
* rtl8367c_getAsicLutIpmcFwdRouterPort
* Description:
- * Get IPMC packet forward to rounter port also or not
+ * Get IPMC packet forward to router port also or not
* Input:
* None
* Output:
- * pEnable - 1: Inlcude router port, 0, exclude router port
+ * pEnable - 1: Include router port, 0, exclude router port
* Return:
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Reset global/queue manage or per-port MIB counter
* Input:
* greset - Global reset
- * qmreset - Queue maganement reset
+ * qmreset - Queue management reset
* portmask - Port reset mask
* Output:
* None
* Input:
* port - Physical port number (0~7)
* mibIdx - MIB counter index
- * pCounter - MIB retrived counter
+ * pCounter - MIB retrieved counter
* Output:
* None
* Return:
* RT_ERR_BUSYWAIT_TIMEOUT - MIB is busy at retrieving
* RT_ERR_STAT_CNTR_FAIL - MIB is resetting
* Note:
- * Before MIBs counter retrieving, writting accessing address to ASIC at first and check the MIB
+ * Before MIBs counter retrieving, writing accessing address to ASIC at first and check the MIB
* control register status. If busy bit of MIB control is set, that means MIB counter have been
- * waiting for preparing, then software must wait atfer this busy flag reset by ASIC. This driver
+ * waiting for preparing, then software must wait after this busy flag reset by ASIC. This driver
* did not recycle reading user desired counter. Software must use driver again to get MIB counter
* if return value is not RT_ERR_OK.
*/
/*writing access counter address first*/
/*This address is SRAM address, and SRAM address = MIB register address >> 2*/
- /*then ASIC will prepare 64bits counter wait for being retrived*/
+ /*then ASIC will prepare 64bits counter wait for being retrieved*/
/*Write Mib related address to access control register*/
retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_ADDRESS, (mibAddr >> 2));
if(retVal != RT_ERR_OK)
/* Function Name:
* rtl8367c_getAsicMIBsLogCounter
* Description:
- * Get MIBs Loggin counter
+ * Get MIBs Logging counter
* Input:
* index - The index of 32 logging counter (0 ~ 31)
* Output:
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
* Note:
- * Software need to check this control register atfer doing port resetting or global resetting
+ * Software need to check this control register after doing port resetting or global resetting
*/
ret_t rtl8367c_getAsicMIBsControl(rtk_uint32* pMask)
{
/* Function Name:
* rtl8367c_setAsicMIBsLength
* Description:
- * Set MIB length couting mode
+ * Set MIB length counting mode
* Input:
* txLengthMode - 0: tag length doesn't be counted. 1: tag length is counted.
* rxLengthMode - 0: tag length doesn't be counted. 1: tag length is counted.
/* Function Name:
* rtl8367c_setAsicMIBsLength
* Description:
- * Set MIB length couting mode
+ * Set MIB length counting mode
* Input:
* None.
* Output:
* Set UNDA behavior
* Input:
* port - port ID
- * behavior - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding
+ * behavior - 0: flooding to unknown DA portmask; 1: drop; 2:trap; 3: flooding
* Output:
* None
* Return:
* Input:
* port - port ID
* Output:
- * pBehavior - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding
+ * pBehavior - 0: flooding to unknown DA portmask; 1: drop; 2:trap; 3: flooding
* Return:
* RT_ERR_OK - Success
* RT_ERR_SMI - SMI access error
return retVal;
/*
1: MAC link = SGMII SerDes link
- 0: MAC link = SGMII config link £¨cfg_sgmii_link£©
+ 0: MAC link = SGMII config link (cfg_sgmii_link)
*/
if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK)
return retVal;
if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK)
return retVal;
- /*select MAC link source when port6/7 be set sgmii mode £¨cfg_sgmii_link£©*/
+ /*select MAC link source when port6/7 be set sgmii mode (cfg_sgmii_link)*/
if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK)
return retVal;
}
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
- * Feature : Qos related functions
+ * Feature : QoS related functions
*
*/
/* Function Name:
* rtl8367c_setAsicLeakyBucketParameter
* Description:
- * Set Leaky Bucket Paramters
+ * Set Leaky Bucket Parameters
* Input:
* tick - Tick is used for time slot size unit
* token - Token is used for adding budget in each time slot
/* Function Name:
* rtl8367c_getAsicLeakyBucketParameter
* Description:
- * Get Leaky Bucket Paramters
+ * Get Leaky Bucket Parameters
* Input:
* tick - Tick is used for time slot size unit
* token - Token is used for adding budget in each time slot
* Set per-port APR enable
* Input:
* port - Physical port number (0~7)
- * aprEnable - APR enable seting 1:enable 0:disable
+ * aprEnable - APR enable setting 1:enable 0:disable
* Output:
* None
* Return:
* Get per-port APR enable
* Input:
* port - Physical port number (0~7)
- * aprEnable - APR enable seting 1:enable 0:disable
+ * aprEnable - APR enable setting 1:enable 0:disable
* Output:
* None
* Return:
* RT_ERR_SMI - SMI access error
* Note:
* Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200
- * for Q-in-Q SLAN design. User can set mathced ether type as service provider supported protocol
+ * for Q-in-Q SLAN design. User can set matched ether type as service provider supported protocol
*/
ret_t rtl8367c_setAsicSvlanTpid(rtk_uint32 protocolType)
{
/* Function Name:
* rtl8367c_setAsicSvlanIngressUntag
* Description:
- * Set action received un-Stag frame from unplink port
+ * Set action received un-Stag frame from uplink port
* Input:
* mode - 0:Drop 1:Trap 2:Assign SVLAN
* Output:
/* Function Name:
* rtl8367c_getAsicSvlanIngressUntag
* Description:
- * Get action received un-Stag frame from unplink port
+ * Get action received un-Stag frame from uplink port
* Input:
* pMode - 0:Drop 1:Trap 2:Assign SVLAN
* Output:
/* Function Name:
* rtl8367c_setAsicSvlanIngressUnmatch
* Description:
- * Set action received unmatched Stag frame from unplink port
+ * Set action received unmatched Stag frame from uplink port
* Input:
* mode - 0:Drop 1:Trap 2:Assign SVLAN
* Output:
/* Function Name:
* rtl8367c_getAsicSvlanIngressUnmatch
* Description:
- * Get action received unmatched Stag frame from unplink port
+ * Get action received unmatched Stag frame from uplink port
* Input:
* pMode - 0:Drop 1:Trap 2:Assign SVLAN
* Output:
/* Function Name:
* rtl8367c_setAsicSvlanEgressUnassign
* Description:
- * Set unplink stream without egress SVID action
+ * Set uplink stream without egress SVID action
* Input:
* enabled - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID
* Output:
/* Function Name:
* rtl8367c_getAsicSvlanEgressUnassign
* Description:
- * Get unplink stream without egress SVID action
+ * Get uplink stream without egress SVID action
* Input:
* pEnabled - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID
* Output:
* RT_ERR_SMI - SMI access error
* RT_ERR_ENTRY_INDEX - Invalid entry index
* Note:
- * ASIC will check upstream's VID and assign related SVID to mathed packet
+ * ASIC will check upstream's VID and assign related SVID to matched packet
*/
ret_t rtl8367c_setAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32 evid, rtk_uint32 portmask, rtk_uint32 svidx)
{
* $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $
*
* Purpose : RTL8367C switch high-level API for RTL8367C
- * Feature : Unkown multicast related functions
+ * Feature : Unknown multicast related functions
*
*/
con = 0;
do {
con++;
- _smi_readBit(1, &ACK); /* ACK for writting data [7:0] */
+ _smi_readBit(1, &ACK); /* ACK for writing data [7:0] */
} while ((ACK != 0) && (con < ack_timer));
if (ACK != 0) ret = RT_ERR_FAILED;
con = 0;
do {
con++;
- _smi_readBit(1, &ACK); /* ACK for writting data [15:8] */
+ _smi_readBit(1, &ACK); /* ACK for writing data [15:8] */
} while ((ACK != 0) && (con < ack_timer));
if (ACK != 0) ret = RT_ERR_FAILED;
* port - port id.
* cntr_idx - port counter index.
* Output:
- * pCntr - MIB retrived counter.
+ * pCntr - MIB retrieved counter.
* Return:
* RT_ERR_OK - OK
* RT_ERR_FAILED - Failed
/* Function Name:
* rtk_stat_lengthMode_get
* Description:
- * Get Legnth mode.
+ * Get Length mode.
* Input:
* None.
* Output:
* RT_ERR_ENABLE - Invalid IFG parameter
* Note:
*
- * This API can set per-port bypass stomr filter control frame type including RMA and igmp.
+ * This API can set per-port bypass storm filter control frame type including RMA and IGMP.
* The bypass frame type is as following:
* - BYPASS_BRG_GROUP,
* - BYPASS_FD_PAUSE,
* RT_ERR_SMI - SMI access error
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * This API can get per-port bypass stomr filter control frame type including RMA and igmp.
+ * This API can get per-port bypass storm filter control frame type including RMA and IGMP.
* The bypass frame type is as following:
* - BYPASS_BRG_GROUP,
* - BYPASS_FD_PAUSE,
/* Function Name:
* rtk_rate_stormControlExtPortmask_set
* Description:
- * Set externsion storm control port mask
+ * Set extension storm control port mask
* Input:
* pPortmask - port mask
* Output:
/* Function Name:
* rtk_rate_stormControlExtPortmask_get
* Description:
- * Set externsion storm control port mask
+ * Set extension storm control port mask
* Input:
* None
* Output:
/* Function Name:
* rtk_rate_stormControlExtEnable_set
* Description:
- * Set externsion storm control state
+ * Set extension storm control state
* Input:
* stormType - storm group type
- * enable - externsion storm control state
+ * enable - extension storm control state
* Output:
* None
* Return:
/* Function Name:
* rtk_rate_stormControlExtEnable_get
* Description:
- * Get externsion storm control state
+ * Get extension storm control state
* Input:
* stormType - storm group type
* Output:
- * pEnable - externsion storm control state
+ * pEnable - extension storm control state
* Return:
* RT_ERR_OK
* RT_ERR_FAILED
/* Function Name:
* rtk_rate_stormControlExtMeterIdx_set
* Description:
- * Set externsion storm control meter index
+ * Set extension storm control meter index
* Input:
* stormType - storm group type
- * index - externsion storm control state
+ * index - extension storm control state
* Output:
* None
* Return:
/* Function Name:
* rtk_rate_stormControlExtMeterIdx_get
* Description:
- * Get externsion storm control meter index
+ * Get extension storm control meter index
* Input:
* stormType - storm group type
- * pIndex - externsion storm control state
+ * pIndex - extension storm control state
* Output:
* None
* Return:
* RT_ERR_SMI - SMI access error
* Note:
* Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design.
- * User can set mathced ether type as service provider supported protocol.
+ * User can set matched ether type as service provider supported protocol.
*/
rtk_api_ret_t rtk_svlan_init(void)
{
* RT_ERR_INPUT - Invalid input parameter.
* Note:
* Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design.
- * User can set mathced ether type as service provider supported protocol.
+ * User can set matched ether type as service provider supported protocol.
*/
rtk_api_ret_t rtk_svlan_tpidEntry_set(rtk_svlan_tpid_t svlan_tag_id)
{
* RT_ERR_PORT_MASK - Invalid portmask.
* RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full.
* Note:
- * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted
- * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup.
+ * The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted
+ * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped by default setup.
* - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration.
* - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration.
* - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration.
* RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted
- * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped.
+ * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted
+ * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped.
*/
rtk_api_ret_t rtk_svlan_memberPortEntry_get(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg)
{
* RT_ERR_SVLAN_ENTRY_NOT_FOUND - specified svlan entry not found.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted
- * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped.
+ * The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accepted
+ * to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be dropped.
*/
rtk_api_ret_t rtk_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg)
{
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can set system C2S configuration. ASIC will check upstream's VID and assign related
- * SVID to mathed packet. There are 128 SVLAN C2S configurations.
+ * SVID to matched packet. There are 128 SVLAN C2S configurations.
*/
rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid)
{
}
else
{
- /* New svidx, remove src_port and find a new slot to add a new enrty */
+ /* New svidx, remove src_port and find a new slot to add a new entry */
pmsk = pmsk & ~(1 << phyPort);
if(pmsk == 0)
c2s_svidx = 0;
* Note:
* The API can Get action of downstream Un-Stag packet. A SVID assigned
* to the un-stag is also retrieved by this API. The parameter pSvid is
- * only refernced when the action is UNTAG_ASSIGN
+ * only referenced when the action is UNTAG_ASSIGN
*/
rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid)
{
* RT_ERR_INPUT - Invalid input parameters.
* Note:
* The API can configure action of downstream Un-match packet. A SVID assigned
- * to the un-match is also supported by this API. The parameter od svid is
- * only refernced when the action is set to UNMATCH_ASSIGN
+ * to the un-match is also supported by this API. The parameter of svid is
+ * only referenced when the action is set to UNMATCH_ASSIGN
*/
rtk_api_ret_t rtk_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rtk_vlan_t svid)
{
* Note:
* The API can Get action of downstream Un-match packet. A SVID assigned
* to the un-match is also retrieved by this API. The parameter pSvid is
- * only refernced when the action is UNMATCH_ASSIGN
+ * only referenced when the action is UNMATCH_ASSIGN
*/
rtk_api_ret_t rtk_svlan_unmatch_action_get(rtk_svlan_unmatch_action_t *pAction, rtk_vlan_t *pSvid)
{
* RT_ERR_OUT_OF_RANGE - input out of range.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * The API can set IP mutlicast to SVID configuration. If upstream packet is IPv4 multicast
+ * The API can set IP multicast to SVID configuration. If upstream packet is IPv4 multicast
* packet and DIP is matched MC2S configuration, ASIC will assign egress SVID to the packet.
* There are 32 SVLAN multicast configurations for IP and L2 multicast.
*/
* RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter.
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
- * The API can delete IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
+ * The API can delete IP multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
*/
rtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk)
{
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
- * The API can get IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
+ * The API can get IP multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
*/
rtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t *pSvid)
{
* RT_ERR_OUT_OF_RANGE - input out of range.
* RT_ERR_INPUT - Invalid input parameters.
* Note:
- * The API can set L2 Mutlicast to SVID configuration. If upstream packet is L2 multicast
+ * The API can set L2 Multicast to SVID configuration. If upstream packet is L2 multicast
* packet and DMAC is matched, ASIC will assign egress SVID to the packet. There are 32
* SVLAN multicast configurations for IP and L2 multicast.
*/
* RT_ERR_SVLAN_VID - Invalid SVLAN VID parameter.
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
- * The API can delete Mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
+ * The API can delete Multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
*/
rtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk)
{
* RT_ERR_INPUT - Invalid input parameters.
* RT_ERR_OUT_OF_RANGE - input out of range.
* Note:
- * The API can get L2 mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
+ * The API can get L2 multicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.
*/
rtk_api_ret_t rtk_svlan_l2mc2s_get(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t *pSvid)
{
return retVal;
}
- /* Updata Databse */
+ /* Update Database */
vlan_mbrCfgUsage[0] = MBRCFG_USED_BY_VLAN;
vlan_mbrCfgVid[0] = 1;
* Set port-based filtering database
* Input:
* port - Port id.
- * enable - ebable port-based FID
+ * enable - enable port-based FID
* fid - Specified filtering database.
* Output:
* None
* Input:
* port - Port id.
* Output:
- * pEnable - ebable port-based FID
+ * pEnable - enable port-based FID
* pFid - Specified filtering database.
* Return:
* RT_ERR_OK - OK
set_rtl8367s_rgmii();
}
-// bleow are platform driver
+// below are platform driver
static const struct of_device_id rtk_gsw_match[] = {
{ .compatible = "mediatek,rtk-gsw" },
{},
init_gsw();
- //init default vlan or init swocnfig
+ //init default vlan or init swconfig
if(!of_property_read_string(pdev->dev.of_node,
"mediatek,port_map", &pm)) {
ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan-1" "phy0-ap0"
ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan-2" "phy1-ap0"
;;
-bananapi,bpi-r4)
+bananapi,bpi-r4|\
+bananapi,bpi-r4-poe)
ucidef_set_led_netdev "wan" "wan" "mt7530-0:00:green:lan" "wan" "link tx rx"
ucidef_set_led_netdev "lan1" "lan1" "mt7530-0:01:green:lan" "lan1" "link tx rx"
ucidef_set_led_netdev "lan2" "lan2" "mt7530-0:02:green:lan" "lan2" "link tx rx"
ucidef_set_led_netdev "lanact" "LANACT" "green:lan" "eth1" "rx tx"
ucidef_set_led_netdev "lanlink" "LANLINK" "amber:lan" "eth1" "link"
;;
+openwrt,one)
+ ucidef_set_led_netdev "wanact" "WANACT" "mdio-bus:0f:green:wan" "eth0" "rx tx"
+ ucidef_set_led_netdev "wanlink" "WANLINK" "mdio-bus:0f:amber:wan" "eth0" "link"
+ ucidef_set_led_netdev "lanact" "LANACT" "green:lan" "eth1" "rx tx"
+ ucidef_set_led_netdev "lanlink" "LANLINK" "amber:lan" "eth1" "link"
+ ;;
routerich,ax3000)
ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-1" "lan1" "link tx rx"
ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-2" "lan2" "link tx rx"
bananapi,bpi-r3)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 sfp2" "eth1 wan"
;;
- bananapi,bpi-r3-mini)
+ bananapi,bpi-r3-mini|\
+ edgecore,eap111)
ucidef_set_interfaces_lan_wan eth0 eth1
;;
- bananapi,bpi-r4)
+ bananapi,bpi-r4|\
+ bananapi,bpi-r4-poe)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 eth1" "wan eth2"
;;
cmcc,rax3000m|\
comfast,cf-e393ax)
ucidef_set_interfaces_lan_wan "lan1" eth1
;;
- dlink,aquila-pro-ai-m30-a1)
- ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" internet
- ;;
+ cudy,m3000-v1|\
+ cudy,tr3000-v1|\
glinet,gl-mt2500|\
glinet,gl-mt3000|\
glinet,gl-x3000|\
glinet,gl-xe3000|\
- openembed,som7981)
+ openembed,som7981|\
+ openwrt,one)
ucidef_set_interfaces_lan_wan eth1 eth0
;;
+ dlink,aquila-pro-ai-m30-a1)
+ ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" internet
+ ;;
glinet,gl-mt6000|\
tplink,tl-xdr4288|\
tplink,tl-xdr6088)
local label_mac=""
case $board in
- bananapi,bpi-r3)
+ bananapi,bpi-r3|\
+ bananapi,bpi-r3-mini|\
+ bananapi,bpi-r4)
wan_mac=$(macaddr_add $(cat /sys/class/net/eth0/address) 1)
;;
cmcc,rax3000m)
;;
esac
;;
+ cudy,m3000-v1)
+ wan_mac=$(macaddr_add $(cat /sys/class/net/eth1/address) 1)
+ ;;
h3c,magic-nx30-pro)
wan_mac=$(mtd_get_mac_ascii pdt_data_1 ethaddr)
lan_mac=$(macaddr_add "$wan_mac" 1)
;;
esac
;;
+ openwrt,one)
+ caldata_extract "factory" 0x0 0x1000
+ ;;
ubnt,unifi-6-plus)
caldata_extract_mmc "factory" 0x0 0x1000
;;
[ "$PHYNBR" = "0" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && echo "$addr" > /sys${DEVPATH}/macaddress
;;
- bananapi,bpi-r3)
+ bananapi,bpi-r3|\
+ bananapi,bpi-r3-mini)
addr=$(cat /sys/class/net/eth0/address)
[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
;;
+ bananapi,bpi-r4|\
+ bananapi,bpi-r4-poe)
+ addr=$(cat /sys/class/net/eth0/address)
+ [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
+ [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
+ [ "$PHYNBR" = "2" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress
+ ;;
cetron,ct3003)
addr=$(mtd_get_mac_binary "art" 0)
[ "$PHYNBR" = "0" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
addr=$(mtd_get_mac_binary "Factory" 0x8000)
[ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
;;
+ cudy,tr3000-v1|\
cudy,re3000-v1)
addr=$(mtd_get_mac_binary bdinfo 0xde00)
[ "$PHYNBR" = "0" ] && echo "$addr" > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress
;;
+ cudy,m3000-v1|\
cudy,wr3000-v1)
addr=$(mtd_get_mac_binary bdinfo 0xde00)
# Originally, phy0 is phy1 mac with LA bit set. However, this would conflict
bananapi,bpi-r3|\
bananapi,bpi-r3-mini|\
bananapi,bpi-r4|\
+ bananapi,bpi-r4-poe|\
+ mediatek,mt7988a-rfb|\
+ jdcloud,re-cp-03|\
+ openwrt,one|\
+ tplink,tl-xdr4288|\
+ tplink,tl-xdr6086|\
+ tplink,tl-xdr6088|\
xiaomi,redmi-router-ax6000-ubootmod)
[ -e /dev/fit0 ] && fitblk /dev/fit0
[ -e /dev/fitrw ] && fitblk /dev/fitrw
mediatek,mt7981-rfb|\
netcore,n60|\
qihoo,360t7|\
- tplink,tl-xdr4288|\
- tplink,tl-xdr6086|\
- tplink,tl-xdr6088|\
xiaomi,mi-router-ax3000t-ubootmod|\
xiaomi,mi-router-wr30u-ubootmod)
CI_KERNPART="fit"
nand_do_upgrade "$1"
;;
- jdcloud,re-cp-03)
- CI_KERNPART="production"
- emmc_do_upgrade "$1"
- ;;
mercusys,mr90x-v1)
CI_UBIPART="ubi0"
nand_do_upgrade "$1"
case "$board" in
bananapi,bpi-r3|\
bananapi,bpi-r4|\
+ bananapi,bpi-r4-poe|\
cmcc,rax3000m)
[ "$magic" != "d00dfeed" ] && {
echo "Invalid image type."
;;
bananapi,bpi-r3|\
bananapi,bpi-r3-mini|\
- bananapi,bpi-r4)
+ bananapi,bpi-r4|\
+ bananapi,bpi-r4-poe)
case "$(fitblk_get_bootdev)" in
mmcblk*)
emmc_copy_config
+++ /dev/null
-CONFIG_64BIT=y
-# CONFIG_AHCI_MTK is not set
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_NVMEM=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-# CONFIG_COMMON_CLK_MT2712 is not set
-# CONFIG_COMMON_CLK_MT6779 is not set
-# CONFIG_COMMON_CLK_MT6795 is not set
-# CONFIG_COMMON_CLK_MT6797 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-CONFIG_COMMON_CLK_MT7981=y
-CONFIG_COMMON_CLK_MT7981_ETHSYS=y
-CONFIG_COMMON_CLK_MT7986=y
-CONFIG_COMMON_CLK_MT7986_ETHSYS=y
-CONFIG_COMMON_CLK_MT7988=y
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8183 is not set
-# CONFIG_COMMON_CLK_MT8186 is not set
-# CONFIG_COMMON_CLK_MT8195 is not set
-# CONFIG_COMMON_CLK_MT8365 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA3=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_MISC=y
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FIT_PARTITION=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_WATCHDOG=y
-CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JUMP_LABEL=y
-CONFIG_LEDS_SMARTRG_LED=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAXLINEAR_GPHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_2P5G_PHY=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_GE_SOC_PHY=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_NVMEM=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-# CONFIG_MTK_CQDMA is not set
-CONFIG_MTK_HSDMA=y
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-# CONFIG_MTK_SVS is not set
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_SOC_THERMAL=y
-CONFIG_MTK_LVTS_THERMAL=y
-CONFIG_MTK_LVTS_THERMAL_DEBUGFS=y
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-CONFIG_NET_DSA_MT7530_MMIO=y
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_MTK_EFUSE=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEFAULT is not set
-CONFIG_PCIEASPM_PERFORMANCE=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-# CONFIG_PCIE_MEDIATEK is not set
-CONFIG_PCIE_MEDIATEK_GEN3=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PCS_MTK_USXGMII=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PHY_MTK_DP is not set
-# CONFIG_PHY_MTK_PCIE is not set
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-CONFIG_PHY_MTK_XFI_TPHY=y
-CONFIG_PHY_MTK_XSPHY=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_MT2712 is not set
-# CONFIG_PINCTRL_MT6765 is not set
-# CONFIG_PINCTRL_MT6795 is not set
-# CONFIG_PINCTRL_MT6797 is not set
-# CONFIG_PINCTRL_MT7622 is not set
-CONFIG_PINCTRL_MT7981=y
-CONFIG_PINCTRL_MT7986=y
-CONFIG_PINCTRL_MT7988=y
-# CONFIG_PINCTRL_MT8173 is not set
-# CONFIG_PINCTRL_MT8183 is not set
-# CONFIG_PINCTRL_MT8186 is not set
-# CONFIG_PINCTRL_MT8188 is not set
-# CONFIG_PINCTRL_MT8516 is not set
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POLYNOMIAL=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REALTEK_PHY=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MT6380=y
-CONFIG_REGULATOR_RT5190A=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_TI_SYSCON=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MT7622=y
-CONFIG_RTC_I2C_AND_SPI=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-# CONFIG_SPI_MTK_NOR is not set
-CONFIG_SPI_MTK_SNFI=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_DECOMP_SINGLE=y
-CONFIG_SRCU=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UIMAGE_FIT_BLK=y
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
CONFIG_64BIT=y
# CONFIG_AHCI_MTK is not set
+CONFIG_AIROHA_EN8801SC_PHY=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_JUMP_LABEL=y
+CONFIG_LEDS_PWM=y
CONFIG_LEDS_SMARTRG_LED=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
endef
TARGET_DEVICES += bananapi_bpi-r3-mini
-define Device/bananapi_bpi-r4
+define Device/bananapi_bpi-r4-common
DEVICE_VENDOR := Bananapi
- DEVICE_MODEL := BPi-R4
- DEVICE_DTS := mt7988a-bananapi-bpi-r4
- DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4
DEVICE_DTS_DIR := $(DTS_DIR)/
DEVICE_DTS_LOADADDR := 0x45f00000
DEVICE_DTS_OVERLAY:= mt7988a-bananapi-bpi-r4-emmc mt7988a-bananapi-bpi-r4-rtc mt7988a-bananapi-bpi-r4-sd mt7988a-bananapi-bpi-r4-wifi-mt7996a
sdcard.img.gz \
snand-preloader.bin snand-bl31-uboot.fip
ARTIFACT/emmc-preloader.bin := mt7988-bl2 emmc-comb
- ARTIFACT/emmc-bl31-uboot.fip := mt7988-bl31-uboot bananapi_bpi-r4-emmc
+ ARTIFACT/emmc-bl31-uboot.fip := mt7988-bl31-uboot $$(DEVICE_NAME)-emmc
ARTIFACT/snand-preloader.bin := mt7988-bl2 spim-nand-ubi-comb
- ARTIFACT/snand-bl31-uboot.fip := mt7988-bl31-uboot bananapi_bpi-r4-snand
+ ARTIFACT/snand-bl31-uboot.fip := mt7988-bl31-uboot $$(DEVICE_NAME)-snand
ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\
pad-to 17k | mt7988-bl2 sdmmc-comb |\
- pad-to 6656k | mt7988-bl31-uboot bananapi_bpi-r4-sdmmc |\
+ pad-to 6656k | mt7988-bl31-uboot $$(DEVICE_NAME)-sdmmc |\
$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
pad-to 12M | append-image-stage initramfs-recovery.itb | check-size 44m |\
) \
pad-to 44M | mt7988-bl2 spim-nand-ubi-comb |\
- pad-to 45M | mt7988-bl31-uboot bananapi_bpi-r4-snand |\
+ pad-to 45M | mt7988-bl31-uboot $$(DEVICE_NAME)-snand |\
pad-to 51M | mt7988-bl2 emmc-comb |\
- pad-to 52M | mt7988-bl31-uboot bananapi_bpi-r4-emmc |\
+ pad-to 52M | mt7988-bl31-uboot $$(DEVICE_NAME)-emmc |\
pad-to 56M | mt798x-gpt emmc |\
$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\
pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
endef
+
+define Device/bananapi_bpi-r4
+ DEVICE_MODEL := BPi-R4
+ DEVICE_DTS := mt7988a-bananapi-bpi-r4
+ DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4
+ $(call Device/bananapi_bpi-r4-common)
+endef
TARGET_DEVICES += bananapi_bpi-r4
+define Device/bananapi_bpi-r4-poe
+ DEVICE_MODEL := BPi-R4 2.5GE
+ DEVICE_DTS := mt7988a-bananapi-bpi-r4-poe
+ DEVICE_DTS_CONFIG := config-mt7988a-bananapi-bpi-r4-poe
+ $(call Device/bananapi_bpi-r4-common)
+ DEVICE_PACKAGES += mt7988-2p5g-phy-firmware
+endef
+TARGET_DEVICES += bananapi_bpi-r4-poe
+
define Device/cetron_ct3003
DEVICE_VENDOR := Cetron
DEVICE_MODEL := CT3003
endef
TARGET_DEVICES += confiabits_mt7981
+define Device/cudy_m3000-v1
+ DEVICE_VENDOR := Cudy
+ DEVICE_MODEL := M3000
+ DEVICE_VARIANT := v1
+ DEVICE_DTS := mt7981b-cudy-m3000-v1
+ DEVICE_DTS_DIR := ../dts
+ SUPPORTED_DEVICES += R37
+ DEVICE_DTS_LOADADDR := 0x44000000
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
+ IMAGE_SIZE := 65536k
+ KERNEL_IN_UBI := 1
+ KERNEL := kernel-bin | lzma | \
+ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
+ KERNEL_INITRAMFS := kernel-bin | lzma | \
+ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+ IMAGES := sysupgrade.bin
+ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+ DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+endef
+TARGET_DEVICES += cudy_m3000-v1
+
define Device/cudy_re3000-v1
DEVICE_VENDOR := Cudy
DEVICE_MODEL := RE3000
endef
TARGET_DEVICES += cudy_re3000-v1
+define Device/cudy_tr3000-v1
+ DEVICE_VENDOR := Cudy
+ DEVICE_MODEL := TR3000
+ DEVICE_VARIANT := v1
+ DEVICE_DTS := mt7981b-cudy-tr3000-v1
+ DEVICE_DTS_DIR := ../dts
+ SUPPORTED_DEVICES += R47
+ UBINIZE_OPTS := -E 5
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
+ IMAGE_SIZE := 65536k
+ KERNEL_IN_UBI := 1
+ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+ DEVICE_PACKAGES := kmod-usb3 kmod-mt7981-firmware mt7981-wo-firmware
+endef
+TARGET_DEVICES += cudy_tr3000-v1
+
define Device/cudy_wr3000-v1
DEVICE_VENDOR := Cudy
DEVICE_MODEL := WR3000
endef
TARGET_DEVICES += dlink_aquila-pro-ai-m30-a1
+define Device/edgecore_eap111
+ DEVICE_VENDOR := Edgecore
+ DEVICE_MODEL := EAP111
+ DEVICE_DTS := mt7981a-edgecore-eap111
+ DEVICE_DTS_DIR := ../dts
+ DEVICE_DTS_LOADADDR := 0x47000000
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
+ UBINIZE_OPTS := -E 5
+ KERNEL_IN_UBI := 1
+ IMAGE_SIZE := 65536k
+ IMAGES := sysupgrade.bin factory.bin
+ IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
+ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+ DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+endef
+TARGET_DEVICES += edgecore_eap111
+
define Device/glinet_gl-mt2500
DEVICE_VENDOR := GL.iNet
DEVICE_MODEL := GL-MT2500
mt7988a-rfb-sd \
mt7988a-rfb-snfi-nand \
mt7988a-rfb-spim-nand \
+ mt7988a-rfb-spim-nand-factory \
mt7988a-rfb-spim-nor \
mt7988a-rfb-eth1-aqr \
mt7988a-rfb-eth1-i2p5g-phy \
ARTIFACT/emmc-bl31-uboot.fip := mt7988-bl31-uboot rfb-emmc
ARTIFACT/nor-preloader.bin := mt7988-bl2 nor-comb
ARTIFACT/nor-bl31-uboot.fip := mt7988-bl31-uboot rfb-nor
- ARTIFACT/snand-preloader.bin := mt7988-bl2 spim-nand-comb
+ ARTIFACT/snand-preloader.bin := mt7988-bl2 spim-nand-ubi-comb
ARTIFACT/snand-bl31-uboot.fip := mt7988-bl31-uboot rfb-snand
ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\
pad-to 17k | mt7988-bl2 sdmmc-comb |\
endef
TARGET_DEVICES += openembed_som7981
+define Build/append-openwrt-one-eeprom
+ dd if=$(STAGING_DIR_IMAGE)/mt7981_eeprom_mt7976_dbdc.bin >> $@
+endef
+
+define Device/openwrt_one
+ DEVICE_VENDOR := OpenWrt
+ DEVICE_MODEL := One
+ DEVICE_DTS := mt7981b-openwrt-one
+ DEVICE_DTS_DIR := ../dts
+ DEVICE_DTC_FLAGS := --pad 4096
+ DEVICE_DTS_LOADADDR := 0x43f00000
+ DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-rtc-pcf8563 kmod-usb3 kmod-nvme kmod-phy-airoha-en8811h
+ KERNEL_LOADADDR := 0x44000000
+ KERNEL := kernel-bin | gzip
+ KERNEL_INITRAMFS := kernel-bin | lzma | \
+ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+ KERNEL_INITRAMFS_SUFFIX := .itb
+ KERNEL_IN_UBI := 1
+ UBOOTENV_IN_UBI := 1
+ IMAGES := sysupgrade.itb
+ IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
+ IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
+ ARTIFACTS := \
+ nor-preloader.bin nor-bl31-uboot.fip \
+ snand-preloader.bin snand-bl31-uboot.fip \
+ factory.ubi snand-factory.bin nor-factory.bin
+ ARTIFACT/nor-preloader.bin := mt7981-bl2 nor-ddr4
+ ARTIFACT/nor-bl31-uboot.fip := mt7981-bl31-uboot openwrt_one-nor
+ ARTIFACT/snand-preloader.bin := mt7981-bl2 spim-nand-ubi-ddr4
+ ARTIFACT/snand-bl31-uboot.fip := mt7981-bl31-uboot openwrt_one-snand
+ ARTIFACT/factory.ubi := ubinize-image fit squashfs-sysupgrade.itb
+ ARTIFACT/snand-factory.bin := mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 256k | \
+ mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 512k | \
+ mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 768k | \
+ mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 1024k | \
+ ubinize-image fit squashfs-sysupgrade.itb
+ ARTIFACT/nor-factory.bin := mt7981-bl2 nor-ddr4 | pad-to 256k | \
+ append-openwrt-one-eeprom | pad-to 1024k | \
+ mt7981-bl31-uboot openwrt_one-nor | pad-to 512k | \
+ append-image-stage initramfs.itb
+ UBINIZE_OPTS := -E 5
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
+ UBINIZE_PARTS := fip=:$(STAGING_DIR_IMAGE)/mt7981_openwrt_one-snand-u-boot.fip recovery=:$(KDIR)/tmp/openwrt-mediatek-filogic-openwrt_one-initramfs.itb \
+ $(if $(wildcard $(TOPDIR)/openwrt-mediatek-filogic-openwrt_one-calibration.itb), calibration=:$(TOPDIR)/openwrt-mediatek-filogic-openwrt_one-calibration.itb)
+endef
+TARGET_DEVICES += openwrt_one
+
define Device/qihoo_360t7
DEVICE_VENDOR := Qihoo
DEVICE_MODEL := 360T7
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.itb := append-kernel | \
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | append-metadata
- DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := fitblk kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
ARTIFACTS := preloader.bin bl31-uboot.fip
ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr3
endef
+++ /dev/null
-CONFIG_64BIT=y
-# CONFIG_AHCI_MTK is not set
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PMU=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2712=y
-# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set
-# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set
-# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set
-# CONFIG_COMMON_CLK_MT2712_MMSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set
-# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set
-# CONFIG_COMMON_CLK_MT6779 is not set
-# CONFIG_COMMON_CLK_MT6795 is not set
-# CONFIG_COMMON_CLK_MT6797 is not set
-CONFIG_COMMON_CLK_MT7622=y
-CONFIG_COMMON_CLK_MT7622_AUDSYS=y
-CONFIG_COMMON_CLK_MT7622_ETHSYS=y
-CONFIG_COMMON_CLK_MT7622_HIFSYS=y
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8183 is not set
-# CONFIG_COMMON_CLK_MT8186 is not set
-# CONFIG_COMMON_CLK_MT8195 is not set
-# CONFIG_COMMON_CLK_MT8365 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_MISC=y
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-# CONFIG_FIT_PARTITION is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JUMP_LABEL=y
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAXLINEAR_GPHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MEDIATEK_2P5G_PHY is not set
-CONFIG_MEDIATEK_GE_PHY=y
-# CONFIG_MEDIATEK_GE_SOC_PHY is not set
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_NVMEM=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-# CONFIG_MTK_CQDMA is not set
-CONFIG_MTK_HSDMA=y
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-# CONFIG_MTK_SVS is not set
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_SOC_THERMAL=y
-# CONFIG_MTK_LVTS_THERMAL is not set
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-# CONFIG_NET_MEDIATEK_SOC_USXGMII is not set
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_MTK_EFUSE=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-# CONFIG_PCIEASPM_DEFAULT is not set
-CONFIG_PCIEASPM_PERFORMANCE=y
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_EVENTS=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PHY_MTK_DP is not set
-# CONFIG_PHY_MTK_PCIE is not set
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_MT2712 is not set
-# CONFIG_PINCTRL_MT6765 is not set
-# CONFIG_PINCTRL_MT6795 is not set
-# CONFIG_PINCTRL_MT6797 is not set
-CONFIG_PINCTRL_MT7622=y
-# CONFIG_PINCTRL_MT7981 is not set
-# CONFIG_PINCTRL_MT7986 is not set
-# CONFIG_PINCTRL_MT7988 is not set
-# CONFIG_PINCTRL_MT8173 is not set
-# CONFIG_PINCTRL_MT8183 is not set
-# CONFIG_PINCTRL_MT8186 is not set
-# CONFIG_PINCTRL_MT8188 is not set
-# CONFIG_PINCTRL_MT8516 is not set
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PSTORE=y
-CONFIG_PSTORE_COMPRESS=y
-CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
-CONFIG_PSTORE_CONSOLE=y
-CONFIG_PSTORE_DEFLATE_COMPRESS=y
-CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
-CONFIG_PSTORE_PMSG=y
-CONFIG_PSTORE_RAM=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REALTEK_PHY=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC8=y
-CONFIG_REED_SOLOMON_ENC8=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MT6380=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_MT7622=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTL8367S_GSW=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_EMULATION=y
-CONFIG_THERMAL_GOV_BANG_BANG=y
-CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UIMAGE_FIT_BLK=y
-# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
-# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
-CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
CONFIG_64BIT=y
# CONFIG_AHCI_MTK is not set
+# CONFIG_AIROHA_EN8801SC_PHY is not set
CONFIG_AQUANTIA_PHY=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+++ /dev/null
-# CONFIG_AIO is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_FORCE_MAX_ORDER=11
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPU_SUSPEND=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
-CONFIG_ARM_DMA_USE_IOMMU=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set
-CONFIG_ARM_MEDIATEK_CPUFREQ=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_BACKLIGHT_LED=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-CONFIG_COMMON_CLK_MT2701=y
-CONFIG_COMMON_CLK_MT2701_AUDSYS=y
-CONFIG_COMMON_CLK_MT2701_BDPSYS=y
-CONFIG_COMMON_CLK_MT2701_ETHSYS=y
-CONFIG_COMMON_CLK_MT2701_G3DSYS=y
-CONFIG_COMMON_CLK_MT2701_HIFSYS=y
-CONFIG_COMMON_CLK_MT2701_IMGSYS=y
-CONFIG_COMMON_CLK_MT2701_MMSYS=y
-CONFIG_COMMON_CLK_MT2701_VDECSYS=y
-# CONFIG_COMMON_CLK_MT6795 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-# CONFIG_COMMON_CLK_MT7629 is not set
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8365 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_COREDUMP=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DEBUG_MT6589_UART0=y
-# CONFIG_DEBUG_MT8127_UART0 is not set
-# CONFIG_DEBUG_MT8135_UART3 is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0x11004000
-CONFIG_DEBUG_UART_VIRT=0xf1004000
-# CONFIG_DEVFREQ_GOV_PASSIVE is not set
-# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
-# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-# CONFIG_DEVFREQ_GOV_USERSPACE is not set
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DIMLIB=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DRM=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_DISPLAY_CONNECTOR=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_DMA_HELPER=y
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_LIMA=y
-CONFIG_DRM_LVDS_CODEC=y
-CONFIG_DRM_MEDIATEK=y
-# CONFIG_DRM_MEDIATEK_DP is not set
-CONFIG_DRM_MEDIATEK_HDMI=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_NOMODESET=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y
-CONFIG_DRM_SCHED=y
-CONFIG_DRM_SIMPLE_BRIDGE=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_ELF_CORE=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-# CONFIG_FIT_PARTITION is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAME_WARN=1024
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HDMI=y
-CONFIG_HID=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MT65XX=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_IIO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_IOMMU_IO_PGTABLE=y
-CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KCMP=y
-# CONFIG_KEYBOARD_MT6779 is not set
-CONFIG_KEYBOARD_MTK_PMIC=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_LEDS_MT6323=y
-# CONFIG_LEDS_QCOM_LPG is not set
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_MT2701 is not set
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-CONFIG_MACH_MT7623=y
-# CONFIG_MACH_MT7629 is not set
-# CONFIG_MACH_MT8127 is not set
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_MT6577_AUXADC=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-CONFIG_MFD_MT6397=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_MTK=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_NAND_ECC_MEDIATEK is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_ADSP_MBOX is not set
-CONFIG_MTK_CMDQ=y
-CONFIG_MTK_CMDQ_MBOX=y
-CONFIG_MTK_CQDMA=y
-# CONFIG_MTK_HSDMA is not set
-CONFIG_MTK_INFRACFG=y
-CONFIG_MTK_IOMMU=y
-CONFIG_MTK_IOMMU_V1=y
-CONFIG_MTK_MMSYS=y
-CONFIG_MTK_PMIC_WRAP=y
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_SMI=y
-# CONFIG_MTK_SVS is not set
-CONFIG_MTK_THERMAL=y
-CONFIG_MTK_SOC_THERMAL=y
-# CONFIG_MTK_LVTS_THERMAL is not set
-CONFIG_MTK_TIMER=y
-# CONFIG_MTK_UART_APDMA is not set
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_NLS=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_MTK_EFUSE=y
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_MTK_DP is not set
-CONFIG_PHY_MTK_HDMI=y
-CONFIG_PHY_MTK_MIPI_DSI=y
-# CONFIG_PHY_MTK_PCIE is not set
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT2701=y
-# CONFIG_PINCTRL_MT6397 is not set
-CONFIG_PINCTRL_MT7623=y
-CONFIG_PINCTRL_MTK=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_MT6323 is not set
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_BUILD=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_MT6323=y
-# CONFIG_REGULATOR_MT6331 is not set
-# CONFIG_REGULATOR_MT6332 is not set
-# CONFIG_REGULATOR_MT6358 is not set
-# CONFIG_REGULATOR_MT6380 is not set
-# CONFIG_REGULATOR_MT6397 is not set
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_MT6397 is not set
-# CONFIG_RTC_DRV_MT7622 is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SERIAL_8250_DMA is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-# CONFIG_SMP_ON_UP is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-# CONFIG_SPI_MTK_NOR is not set
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-# CONFIG_SPMI_MTK_PMIF is not set
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TOUCHSCREEN_EDT_FT5X06=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UACCE is not set
-CONFIG_UBIFS_FS=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UIMAGE_FIT_BLK=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_F_ACM=y
-CONFIG_USB_F_ECM=y
-CONFIG_USB_F_MASS_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GPIO_VBUS=y
-CONFIG_USB_G_MULTI=y
-CONFIG_USB_G_MULTI_CDC=y
-# CONFIG_USB_G_MULTI_RNDIS is not set
-CONFIG_USB_HID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_INVENTRA_DMA=y
-CONFIG_USB_LIBCOMPOSITE=y
-CONFIG_USB_MUSB_DUAL_ROLE=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_MEDIATEK=y
-CONFIG_USB_OTG=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_U_ETHER=y
-CONFIG_USB_U_SERIAL=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
# CONFIG_AIO is not set
+# CONFIG_AIROHA_EN8801SC_PHY is not set
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_FORCE_MAX_ORDER=11
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MEDIATEK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CHR_DEV_SCH=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_MEDIATEK=y
-# CONFIG_COMMON_CLK_MT2701 is not set
-# CONFIG_COMMON_CLK_MT6795 is not set
-# CONFIG_COMMON_CLK_MT7622 is not set
-CONFIG_COMMON_CLK_MT7629=y
-CONFIG_COMMON_CLK_MT7629_ETHSYS=y
-CONFIG_COMMON_CLK_MT7629_HIFSYS=y
-# CONFIG_COMMON_CLK_MT7981 is not set
-# CONFIG_COMMON_CLK_MT7986 is not set
-# CONFIG_COMMON_CLK_MT7988 is not set
-# CONFIG_COMMON_CLK_MT8135 is not set
-# CONFIG_COMMON_CLK_MT8173 is not set
-# CONFIG_COMMON_CLK_MT8365 is not set
-# CONFIG_COMMON_CLK_MT8516 is not set
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DEFAULT_HOSTNAME="(mt7629)"
-CONFIG_DIMLIB=y
-CONFIG_DMA_OPS=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EINT_MTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-# CONFIG_FIT_PARTITION is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_WARN=1024
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_MTK=y
-CONFIG_HZ_FIXED=0
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-CONFIG_LIBFDT=y
-# CONFIG_LEDS_SMARTRG_LED is not set
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_MT2701 is not set
-# CONFIG_MACH_MT6589 is not set
-# CONFIG_MACH_MT6592 is not set
-# CONFIG_MACH_MT7623 is not set
-CONFIG_MACH_MT7629=y
-# CONFIG_MACH_MT8127 is not set
-# CONFIG_MACH_MT8135 is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEDIATEK_WATCHDOG=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_MEDIATEK=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MTK_BMT=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-# CONFIG_MTK_CMDQ is not set
-CONFIG_MTK_INFRACFG=y
-# CONFIG_MTK_PMIC_WRAP is not set
-CONFIG_MTK_SCPSYS=y
-CONFIG_MTK_SCPSYS_PM_DOMAINS=y
-CONFIG_MTK_TIMER=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NETFILTER=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_WED=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MTK_EFUSE is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_MEDIATEK=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_MTK_DP is not set
-# CONFIG_PHY_MTK_PCIE is not set
-CONFIG_PHY_MTK_TPHY=y
-# CONFIG_PHY_MTK_UFS is not set
-# CONFIG_PHY_MTK_XSPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_MT7629=y
-CONFIG_PINCTRL_MTK_MOORE=y
-CONFIG_PINCTRL_MTK_V2=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_MEDIATEK=y
-# CONFIG_PWM_MTK_DISP is not set
-CONFIG_PWM_SYSFS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-# CONFIG_RTL8367S_GSW is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_MT6577=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT65XX=y
-CONFIG_SPI_MTK_NOR=y
-CONFIG_SPI_MTK_SNFI=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-# CONFIG_SWAP is not set
-CONFIG_SWCONFIG=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MTK=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
+# CONFIG_AIROHA_EN8801SC_PHY is not set
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+++ /dev/null
-From 363547d2191cbc32ca954ba75d72908712398ff2 Mon Sep 17 00:00:00 2001
-From: Andrew Davis <afd@ti.com>
-Date: Mon, 24 Oct 2022 12:34:28 -0500
-Subject: [PATCH] kbuild: Allow DTB overlays to built from .dtso named source
- files
-
-Currently DTB Overlays (.dtbo) are build from source files with the same
-extension (.dts) as the base DTs (.dtb). This may become confusing and
-even lead to wrong results. For example, a composite DTB (created from a
-base DTB and a set of overlays) might have the same name as one of the
-overlays that create it.
-
-Different files should be generated from differently named sources.
- .dtb <-> .dts
- .dtbo <-> .dtso
-
-We do not remove the ability to compile DTBO files from .dts files here,
-only add a new rule allowing the .dtso file name. The current .dts named
-overlays can be renamed with time. After all have been renamed we can
-remove the other rule.
-
-Signed-off-by: Andrew Davis <afd@ti.com>
-Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Reviewed-by: Frank Rowand <frowand.list@gmail.com>
-Tested-by: Frank Rowand <frowand.list@gmail.com>
-Link: https://lore.kernel.org/r/20221024173434.32518-2-afd@ti.com
-Signed-off-by: Rob Herring <robh@kernel.org>
----
- scripts/Makefile.lib | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/scripts/Makefile.lib
-+++ b/scripts/Makefile.lib
-@@ -408,6 +408,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T
- $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE
- $(call if_changed_dep,dtc)
-
-+$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE
-+ $(call if_changed_dep,dtc)
-+
- dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
-
- # Bzip2
+++ /dev/null
-From 2c4daed9580164522859fa100128be408cc69be2 Mon Sep 17 00:00:00 2001
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sat, 5 Nov 2022 23:36:16 +0100
-Subject: [PATCH 01/19] arm64: dts: mediatek: mt7986: add support for RX
- Wireless Ethernet Dispatch
-
-Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet
-Dispatch to offload traffic received by the wlan interface to lan/wan
-one.
-
-Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
-Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 65 +++++++++++++++++++++++
- 1 file changed, 65 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -76,6 +76,47 @@
- no-map;
- reg = <0 0x4fc00000 0 0x00100000>;
- };
-+
-+ wo_emi0: wo-emi@4fd00000 {
-+ reg = <0 0x4fd00000 0 0x40000>;
-+ no-map;
-+ };
-+
-+ wo_emi1: wo-emi@4fd40000 {
-+ reg = <0 0x4fd40000 0 0x40000>;
-+ no-map;
-+ };
-+
-+ wo_ilm0: wo-ilm@151e0000 {
-+ reg = <0 0x151e0000 0 0x8000>;
-+ no-map;
-+ };
-+
-+ wo_ilm1: wo-ilm@151f0000 {
-+ reg = <0 0x151f0000 0 0x8000>;
-+ no-map;
-+ };
-+
-+ wo_data: wo-data@4fd80000 {
-+ reg = <0 0x4fd80000 0 0x240000>;
-+ no-map;
-+ };
-+
-+ wo_dlm0: wo-dlm@151e8000 {
-+ reg = <0 0x151e8000 0 0x2000>;
-+ no-map;
-+ };
-+
-+ wo_dlm1: wo-dlm@151f8000 {
-+ reg = <0 0x151f8000 0 0x2000>;
-+ no-map;
-+ };
-+
-+ wo_boot: wo-boot@15194000 {
-+ reg = <0 0x15194000 0 0x1000>;
-+ no-map;
-+ };
-+
- };
-
- timer {
-@@ -239,6 +280,11 @@
- reg = <0 0x15010000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-+ memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
-+ <&wo_data>, <&wo_boot>;
-+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-+ "wo-data", "wo-boot";
-+ mediatek,wo-ccif = <&wo_ccif0>;
- };
-
- wed1: wed@15011000 {
-@@ -247,6 +293,25 @@
- reg = <0 0x15011000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-+ memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
-+ <&wo_data>, <&wo_boot>;
-+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-+ "wo-data", "wo-boot";
-+ mediatek,wo-ccif = <&wo_ccif1>;
-+ };
-+
-+ wo_ccif0: syscon@151a5000 {
-+ compatible = "mediatek,mt7986-wo-ccif", "syscon";
-+ reg = <0 0x151a5000 0 0x1000>;
-+ interrupt-parent = <&gic>;
-+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-+ };
-+
-+ wo_ccif1: syscon@151ad000 {
-+ compatible = "mediatek,mt7986-wo-ccif", "syscon";
-+ reg = <0 0x151ad000 0 0x1000>;
-+ interrupt-parent = <&gic>;
-+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- eth: ethernet@15100000 {
+++ /dev/null
-From 438e53828c08cf0e8a65b61cf6ce1e4b6620551a Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 6 Nov 2022 09:50:24 +0100
-Subject: [PATCH 02/19] arm64: dts: mt7986: harmonize device node order
-
-This arrange device tree nodes in alphabetical order.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221106085034.12582-2-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++----------
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++---
- 2 files changed, 58 insertions(+), 58 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -54,6 +54,53 @@
- };
- };
-
-+&pio {
-+ uart1_pins: uart1-pins {
-+ mux {
-+ function = "uart";
-+ groups = "uart1";
-+ };
-+ };
-+
-+ uart2_pins: uart2-pins {
-+ mux {
-+ function = "uart";
-+ groups = "uart2";
-+ };
-+ };
-+
-+ wf_2g_5g_pins: wf-2g-5g-pins {
-+ mux {
-+ function = "wifi";
-+ groups = "wf_2g", "wf_5g";
-+ };
-+ conf {
-+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-+ "WF1_TOP_CLK", "WF1_TOP_DATA";
-+ drive-strength = <4>;
-+ };
-+ };
-+
-+ wf_dbdc_pins: wf-dbdc-pins {
-+ mux {
-+ function = "wifi";
-+ groups = "wf_dbdc";
-+ };
-+ conf {
-+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-+ "WF0_TOP_CLK", "WF0_TOP_DATA";
-+ drive-strength = <4>;
-+ };
-+ };
-+};
-+
- &switch {
- ports {
- #address-cells = <1>;
-@@ -121,50 +168,3 @@
- pinctrl-0 = <&wf_2g_5g_pins>;
- pinctrl-1 = <&wf_dbdc_pins>;
- };
--
--&pio {
-- uart1_pins: uart1-pins {
-- mux {
-- function = "uart";
-- groups = "uart1";
-- };
-- };
--
-- uart2_pins: uart2-pins {
-- mux {
-- function = "uart";
-- groups = "uart2";
-- };
-- };
--
-- wf_2g_5g_pins: wf-2g-5g-pins {
-- mux {
-- function = "wifi";
-- groups = "wf_2g", "wf_5g";
-- };
-- conf {
-- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-- "WF1_TOP_CLK", "WF1_TOP_DATA";
-- drive-strength = <4>;
-- };
-- };
--
-- wf_dbdc_pins: wf-dbdc-pins {
-- mux {
-- function = "wifi";
-- groups = "wf_dbdc";
-- };
-- conf {
-- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-- "WF0_TOP_CLK", "WF0_TOP_DATA";
-- drive-strength = <4>;
-- };
-- };
--};
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -25,10 +25,6 @@
- };
- };
-
--&uart0 {
-- status = "okay";
--};
--
- ð {
- status = "okay";
-
-@@ -99,13 +95,6 @@
- };
- };
-
--&wifi {
-- status = "okay";
-- pinctrl-names = "default", "dbdc";
-- pinctrl-0 = <&wf_2g_5g_pins>;
-- pinctrl-1 = <&wf_dbdc_pins>;
--};
--
- &pio {
- wf_2g_5g_pins: wf-2g-5g-pins {
- mux {
-@@ -138,3 +127,14 @@
- };
- };
- };
-+
-+&uart0 {
-+ status = "okay";
-+};
-+
-+&wifi {
-+ status = "okay";
-+ pinctrl-names = "default", "dbdc";
-+ pinctrl-0 = <&wf_2g_5g_pins>;
-+ pinctrl-1 = <&wf_dbdc_pins>;
-+};
+++ /dev/null
-From ffb05357b47f06b2b4d1e14ba89169e28feb727b Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 6 Nov 2022 09:50:27 +0100
-Subject: [PATCH 03/19] arm64: dts: mt7986: add crypto related device nodes
-
-This patch adds crypto engine support for MT7986.
-
-Signed-off-by: Vic Wu <vic.wu@mediatek.com>
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20221106085034.12582-5-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 4 ++++
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++++++++++++++
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 4 ++++
- 3 files changed, 23 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -25,6 +25,10 @@
- };
- };
-
-+&crypto {
-+ status = "okay";
-+};
-+
- ð {
- status = "okay";
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -223,6 +223,21 @@
- status = "disabled";
- };
-
-+ crypto: crypto@10320000 {
-+ compatible = "inside-secure,safexcel-eip97";
-+ reg = <0 0x10320000 0 0x40000>;
-+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
-+ clocks = <&infracfg CLK_INFRA_EIP97_CK>;
-+ clock-names = "infra_eip97_ck";
-+ assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
-+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
-+ status = "disabled";
-+ };
-+
- uart0: serial@11002000 {
- compatible = "mediatek,mt7986-uart",
- "mediatek,mt6577-uart";
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -25,6 +25,10 @@
- };
- };
-
-+&crypto {
-+ status = "okay";
-+};
-+
- ð {
- status = "okay";
-
+++ /dev/null
-From b49b7dc404ded1d89cbc568d875009a5c1ed4ef6 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 6 Nov 2022 09:50:29 +0100
-Subject: [PATCH 04/19] arm64: dts: mt7986: add i2c node
-
-Add i2c Node to mt7986 devicetree.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20221106085034.12582-7-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -279,6 +279,20 @@
- status = "disabled";
- };
-
-+ i2c0: i2c@11008000 {
-+ compatible = "mediatek,mt7986-i2c";
-+ reg = <0 0x11008000 0 0x90>,
-+ <0 0x10217080 0 0x80>;
-+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-+ clock-div = <5>;
-+ clocks = <&infracfg CLK_INFRA_I2C0_CK>,
-+ <&infracfg CLK_INFRA_AP_DMA_CK>;
-+ clock-names = "main", "dma";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
- ethsys: syscon@15000000 {
- #address-cells = <1>;
- #size-cells = <1>;
+++ /dev/null
-From 2cd6022800d6da7822e169f3e6f7f790c1431445 Mon Sep 17 00:00:00 2001
-From: Matthias Brugger <mbrugger@suse.com>
-Date: Mon, 14 Nov 2022 13:16:53 +0100
-Subject: [PATCH 05/19] arm64: dts: mediatek: mt7986: Add SoC compatible
-
-Missing SoC compatible in the board file causes dt bindings check.
-
-Signed-off-by: Matthias Brugger <mbrugger@suse.com>
-Link: https://lore.kernel.org/r/20221114121653.14739-1-matthias.bgg@kernel.org
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 2 +-
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 1 +
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 2 +-
- arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 3 +++
- 4 files changed, 6 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -9,7 +9,7 @@
-
- / {
- model = "MediaTek MT7986a RFB";
-- compatible = "mediatek,mt7986a-rfb";
-+ compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
-
- aliases {
- serial0 = &uart0;
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -10,6 +10,7 @@
- #include <dt-bindings/reset/mt7986-resets.h>
-
- / {
-+ compatible = "mediatek,mt7986a";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -9,7 +9,7 @@
-
- / {
- model = "MediaTek MT7986b RFB";
-- compatible = "mediatek,mt7986b-rfb";
-+ compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
-
- aliases {
- serial0 = &uart0;
---- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
-@@ -5,6 +5,9 @@
- */
-
- #include "mt7986a.dtsi"
-+/ {
-+ compatible = "mediatek,mt7986b";
-+};
-
- &pio {
- compatible = "mediatek,mt7986b-pinctrl";
+++ /dev/null
-From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 18 Nov 2022 20:01:21 +0100
-Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes
-
-This patch adds spi support for MT7986.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++
- 3 files changed, 98 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -59,6 +59,20 @@
- };
-
- &pio {
-+ spi_flash_pins: spi-flash-pins {
-+ mux {
-+ function = "spi";
-+ groups = "spi0", "spi0_wp_hold";
-+ };
-+ };
-+
-+ spic_pins: spic-pins {
-+ mux {
-+ function = "spi";
-+ groups = "spi1_2";
-+ };
-+ };
-+
- uart1_pins: uart1-pins {
- mux {
- function = "uart";
-@@ -105,6 +119,27 @@
- };
- };
-
-+&spi0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi_flash_pins>;
-+ cs-gpios = <0>, <0>;
-+ status = "okay";
-+ spi_nand: spi_nand@0 {
-+ compatible = "spi-nand";
-+ reg = <0>;
-+ spi-max-frequency = <10000000>;
-+ spi-tx-bus-width = <4>;
-+ spi-rx-bus-width = <4>;
-+ };
-+};
-+
-+&spi1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spic_pins>;
-+ cs-gpios = <0>, <0>;
-+ status = "okay";
-+};
-+
- &switch {
- ports {
- #address-cells = <1>;
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -294,6 +294,34 @@
- status = "disabled";
- };
-
-+ spi0: spi@1100a000 {
-+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0 0x1100a000 0 0x100>;
-+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
-+ <&topckgen CLK_TOP_SPI_SEL>,
-+ <&infracfg CLK_INFRA_SPI0_CK>,
-+ <&infracfg CLK_INFRA_SPI0_HCK_CK>;
-+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-+ status = "disabled";
-+ };
-+
-+ spi1: spi@1100b000 {
-+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0 0x1100b000 0 0x100>;
-+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
-+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
-+ <&infracfg CLK_INFRA_SPI1_CK>,
-+ <&infracfg CLK_INFRA_SPI1_HCK_CK>;
-+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
-+ status = "disabled";
-+ };
-+
- ethsys: syscon@15000000 {
- #address-cells = <1>;
- #size-cells = <1>;
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -100,6 +100,20 @@
- };
-
- &pio {
-+ spi_flash_pins: spi-flash-pins {
-+ mux {
-+ function = "spi";
-+ groups = "spi0", "spi0_wp_hold";
-+ };
-+ };
-+
-+ spic_pins: spic-pins {
-+ mux {
-+ function = "spi";
-+ groups = "spi1_2";
-+ };
-+ };
-+
- wf_2g_5g_pins: wf-2g-5g-pins {
- mux {
- function = "wifi";
-@@ -132,6 +146,27 @@
- };
- };
-
-+&spi0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi_flash_pins>;
-+ cs-gpios = <0>, <0>;
-+ status = "okay";
-+ spi_nand: spi_nand@0 {
-+ compatible = "spi-nand";
-+ reg = <0>;
-+ spi-max-frequency = <10000000>;
-+ spi-tx-bus-width = <4>;
-+ spi-rx-bus-width = <4>;
-+ };
-+};
-+
-+&spi1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spic_pins>;
-+ cs-gpios = <0>, <0>;
-+ status = "okay";
-+};
-+
- &uart0 {
- status = "okay";
- };
+++ /dev/null
-From 9e8e24ab716098e617195ce29b88e84608bf2108 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 6 Jan 2023 16:28:42 +0100
-Subject: [PATCH 07/19] arm64: dts: mt7986: add usb related device nodes
-
-This patch adds USB support for MT7986.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
-Link: https://lore.kernel.org/r/20230106152845.88717-3-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 8 +++
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 55 ++++++++++++++++++++
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 8 +++
- 3 files changed, 71 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -140,6 +140,10 @@
- status = "okay";
- };
-
-+&ssusb {
-+ status = "okay";
-+};
-+
- &switch {
- ports {
- #address-cells = <1>;
-@@ -201,6 +205,10 @@
- status = "okay";
- };
-
-+&usb_phy {
-+ status = "okay";
-+};
-+
- &wifi {
- status = "okay";
- pinctrl-names = "default", "dbdc";
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -322,6 +322,61 @@
- status = "disabled";
- };
-
-+ ssusb: usb@11200000 {
-+ compatible = "mediatek,mt7986-xhci",
-+ "mediatek,mtk-xhci";
-+ reg = <0 0x11200000 0 0x2e00>,
-+ <0 0x11203e00 0 0x0100>;
-+ reg-names = "mac", "ippc";
-+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
-+ <&infracfg CLK_INFRA_IUSB_CK>,
-+ <&infracfg CLK_INFRA_IUSB_133_CK>,
-+ <&infracfg CLK_INFRA_IUSB_66M_CK>,
-+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
-+ clock-names = "sys_ck",
-+ "ref_ck",
-+ "mcu_ck",
-+ "dma_ck",
-+ "xhci_ck";
-+ phys = <&u2port0 PHY_TYPE_USB2>,
-+ <&u3port0 PHY_TYPE_USB3>,
-+ <&u2port1 PHY_TYPE_USB2>;
-+ status = "disabled";
-+ };
-+
-+ usb_phy: t-phy@11e10000 {
-+ compatible = "mediatek,mt7986-tphy",
-+ "mediatek,generic-tphy-v2";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0 0 0x11e10000 0x1700>;
-+ status = "disabled";
-+
-+ u2port0: usb-phy@0 {
-+ reg = <0x0 0x700>;
-+ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-+ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-+ clock-names = "ref", "da_ref";
-+ #phy-cells = <1>;
-+ };
-+
-+ u3port0: usb-phy@700 {
-+ reg = <0x700 0x900>;
-+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
-+ clock-names = "ref";
-+ #phy-cells = <1>;
-+ };
-+
-+ u2port1: usb-phy@1000 {
-+ reg = <0x1000 0x700>;
-+ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
-+ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
-+ clock-names = "ref", "da_ref";
-+ #phy-cells = <1>;
-+ };
-+ };
-+
- ethsys: syscon@15000000 {
- #address-cells = <1>;
- #size-cells = <1>;
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -167,10 +167,18 @@
- status = "okay";
- };
-
-+&ssusb {
-+ status = "okay";
-+};
-+
- &uart0 {
- status = "okay";
- };
-
-+&usb_phy {
-+ status = "okay";
-+};
-+
- &wifi {
- status = "okay";
- pinctrl-names = "default", "dbdc";
+++ /dev/null
-From c1744e9e75a6a8abc7c893f349bcbf725b9c0d74 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 6 Jan 2023 16:28:43 +0100
-Subject: [PATCH 08/19] arm64: dts: mt7986: add mmc related device nodes
-
-This patch adds mmc support for MT7986.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20230106152845.88717-4-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 96 ++++++++++++++++++++
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++
- 2 files changed, 111 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -5,6 +5,8 @@
- */
-
- /dts-v1/;
-+#include <dt-bindings/pinctrl/mt65xx.h>
-+
- #include "mt7986a.dtsi"
-
- / {
-@@ -23,6 +25,24 @@
- device_type = "memory";
- reg = <0 0x40000000 0 0x40000000>;
- };
-+
-+ reg_1p8v: regulator-1p8v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "fixed-1.8V";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+ };
-+
-+ reg_3p3v: regulator-3p3v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "fixed-3.3V";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+ };
- };
-
- &crypto {
-@@ -58,7 +78,83 @@
- };
- };
-
-+&mmc0 {
-+ pinctrl-names = "default", "state_uhs";
-+ pinctrl-0 = <&mmc0_pins_default>;
-+ pinctrl-1 = <&mmc0_pins_uhs>;
-+ bus-width = <8>;
-+ max-frequency = <200000000>;
-+ cap-mmc-highspeed;
-+ mmc-hs200-1_8v;
-+ mmc-hs400-1_8v;
-+ hs400-ds-delay = <0x14014>;
-+ vmmc-supply = <®_3p3v>;
-+ vqmmc-supply = <®_1p8v>;
-+ non-removable;
-+ no-sd;
-+ no-sdio;
-+ status = "okay";
-+};
-+
- &pio {
-+ mmc0_pins_default: mmc0-pins {
-+ mux {
-+ function = "emmc";
-+ groups = "emmc_51";
-+ };
-+ conf-cmd-dat {
-+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+ input-enable;
-+ drive-strength = <4>;
-+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+ };
-+ conf-clk {
-+ pins = "EMMC_CK";
-+ drive-strength = <6>;
-+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+ };
-+ conf-ds {
-+ pins = "EMMC_DSL";
-+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+ };
-+ conf-rst {
-+ pins = "EMMC_RSTB";
-+ drive-strength = <4>;
-+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+ };
-+ };
-+
-+ mmc0_pins_uhs: mmc0-uhs-pins {
-+ mux {
-+ function = "emmc";
-+ groups = "emmc_51";
-+ };
-+ conf-cmd-dat {
-+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+ input-enable;
-+ drive-strength = <4>;
-+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+ };
-+ conf-clk {
-+ pins = "EMMC_CK";
-+ drive-strength = <6>;
-+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+ };
-+ conf-ds {
-+ pins = "EMMC_DSL";
-+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+ };
-+ conf-rst {
-+ pins = "EMMC_RSTB";
-+ drive-strength = <4>;
-+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+ };
-+ };
-+
- spi_flash_pins: spi-flash-pins {
- mux {
- function = "spi";
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -345,6 +345,21 @@
- status = "disabled";
- };
-
-+ mmc0: mmc@11230000 {
-+ compatible = "mediatek,mt7986-mmc";
-+ reg = <0 0x11230000 0 0x1000>,
-+ <0 0x11c20000 0 0x1000>;
-+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
-+ <&infracfg CLK_INFRA_MSDC_HCK_CK>,
-+ <&infracfg CLK_INFRA_MSDC_CK>,
-+ <&infracfg CLK_INFRA_MSDC_133M_CK>,
-+ <&infracfg CLK_INFRA_MSDC_66M_CK>;
-+ clock-names = "source", "hclk", "source_cg", "bus_clk",
-+ "sys_cg";
-+ status = "disabled";
-+ };
-+
- usb_phy: t-phy@11e10000 {
- compatible = "mediatek,mt7986-tphy",
- "mediatek,generic-tphy-v2";
+++ /dev/null
-From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Fri, 6 Jan 2023 16:28:44 +0100
-Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes
-
-This patch adds PCIe support for MT7986.
-
-Signed-off-by: Jieyy Yang <jieyy.yang@mediatek.com>
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230106152845.88717-5-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 52 ++++++++++++++++++++
- 2 files changed, 68 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -93,6 +93,15 @@
- non-removable;
- no-sd;
- no-sdio;
-+};
-+
-+&pcie {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_pins>;
-+ status = "okay";
-+};
-+
-+&pcie_phy {
- status = "okay";
- };
-
-@@ -155,6 +164,13 @@
- };
- };
-
-+ pcie_pins: pcie-pins {
-+ mux {
-+ function = "pcie";
-+ groups = "pcie_clk", "pcie_wake", "pcie_pereset";
-+ };
-+ };
-+
- spi_flash_pins: spi-flash-pins {
- mux {
- function = "spi";
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -8,6 +8,7 @@
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt7986-clk.h>
- #include <dt-bindings/reset/mt7986-resets.h>
-+#include <dt-bindings/phy/phy.h>
-
- / {
- compatible = "mediatek,mt7986a";
-@@ -360,6 +361,57 @@
- status = "disabled";
- };
-
-+ pcie: pcie@11280000 {
-+ compatible = "mediatek,mt7986-pcie",
-+ "mediatek,mt8192-pcie";
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ reg = <0x00 0x11280000 0x00 0x4000>;
-+ reg-names = "pcie-mac";
-+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-+ bus-range = <0x00 0xff>;
-+ ranges = <0x82000000 0x00 0x20000000 0x00
-+ 0x20000000 0x00 0x10000000>;
-+ clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
-+ <&infracfg CLK_INFRA_IPCIE_CK>,
-+ <&infracfg CLK_INFRA_IPCIER_CK>,
-+ <&infracfg CLK_INFRA_IPCIEB_CK>;
-+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
-+ status = "disabled";
-+
-+ phys = <&pcie_port PHY_TYPE_PCIE>;
-+ phy-names = "pcie-phy";
-+
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 0x7>;
-+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
-+ <0 0 0 2 &pcie_intc 1>,
-+ <0 0 0 3 &pcie_intc 2>,
-+ <0 0 0 4 &pcie_intc 3>;
-+ pcie_intc: interrupt-controller {
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ interrupt-controller;
-+ };
-+ };
-+
-+ pcie_phy: t-phy@11c00000 {
-+ compatible = "mediatek,mt7986-tphy",
-+ "mediatek,generic-tphy-v2";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+ status = "disabled";
-+
-+ pcie_port: pcie-phy@11c00000 {
-+ reg = <0 0x11c00000 0 0x20000>;
-+ clocks = <&clk40m>;
-+ clock-names = "ref";
-+ #phy-cells = <1>;
-+ };
-+ };
-+
- usb_phy: t-phy@11e10000 {
- compatible = "mediatek,mt7986-tphy",
- "mediatek,generic-tphy-v2";
+++ /dev/null
-From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Fri, 6 Jan 2023 16:28:45 +0100
-Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3
-
-Add support for Bananapi R3 SBC.
-
-- SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
-- SPI-NAND/NOR support (switched CS by sw5/C)
-- all rj45 ports and both SFP working (eth1/lan4)
-- all USB-Ports + SIM-Slot tested
-- i2c and all uarts tested
-- wifi tested (with eeprom calibration data)
-
-The device can boot from all 4 storage options. Both, SPI and MMC, can
-be switched using hardware switches on the board, see
-https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/Makefile | 5 +
- .../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 ++
- .../mt7986a-bananapi-bpi-r3-nand.dtso | 55 +++
- .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 68 +++
- .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 +
- .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 450 ++++++++++++++++++
- 6 files changed, 630 insertions(+)
- create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
- create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
- create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
- create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
- create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-
---- a/arch/arm64/boot/dts/mediatek/Makefile
-+++ b/arch/arm64/boot/dts/mediatek/Makefile
-@@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
-@@ -0,0 +1,29 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+/*
-+ * Copyright (C) 2021 MediaTek Inc.
-+ * Author: Sam.Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+ fragment@0 {
-+ target-path = "/soc/mmc@11230000";
-+ __overlay__ {
-+ bus-width = <8>;
-+ max-frequency = <200000000>;
-+ cap-mmc-highspeed;
-+ mmc-hs200-1_8v;
-+ mmc-hs400-1_8v;
-+ hs400-ds-delay = <0x14014>;
-+ non-removable;
-+ no-sd;
-+ no-sdio;
-+ status = "okay";
-+ };
-+ };
-+};
-+
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
-@@ -0,0 +1,55 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+/*
-+ * Authors: Daniel Golle <daniel@makrotopia.org>
-+ * Frank Wunderlich <frank-w@public-files.de>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+ fragment@0 {
-+ target-path = "/soc/spi@1100a000";
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ spi_nand: spi_nand@0 {
-+ compatible = "spi-nand";
-+ reg = <0>;
-+ spi-max-frequency = <10000000>;
-+ spi-tx-bus-width = <4>;
-+ spi-rx-bus-width = <4>;
-+
-+ partitions {
-+ compatible = "fixed-partitions";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "bl2";
-+ reg = <0x0 0x80000>;
-+ read-only;
-+ };
-+
-+ partition@80000 {
-+ label = "reserved";
-+ reg = <0x80000 0x300000>;
-+ };
-+
-+ partition@380000 {
-+ label = "fip";
-+ reg = <0x380000 0x200000>;
-+ read-only;
-+ };
-+
-+ partition@580000 {
-+ label = "ubi";
-+ reg = <0x580000 0x7a80000>;
-+ };
-+ };
-+ };
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-@@ -0,0 +1,68 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+/*
-+ * Authors: Daniel Golle <daniel@makrotopia.org>
-+ * Frank Wunderlich <frank-w@public-files.de>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+ fragment@0 {
-+ target-path = "/soc/spi@1100a000";
-+ __overlay__ {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ flash@0 {
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <10000000>;
-+
-+ partitions {
-+ compatible = "fixed-partitions";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "bl2";
-+ reg = <0x0 0x20000>;
-+ read-only;
-+ };
-+
-+ partition@20000 {
-+ label = "reserved";
-+ reg = <0x20000 0x20000>;
-+ };
-+
-+ partition@40000 {
-+ label = "u-boot-env";
-+ reg = <0x40000 0x40000>;
-+ };
-+
-+ partition@80000 {
-+ label = "reserved2";
-+ reg = <0x80000 0x80000>;
-+ };
-+
-+ partition@100000 {
-+ label = "fip";
-+ reg = <0x100000 0x80000>;
-+ read-only;
-+ };
-+
-+ partition@180000 {
-+ label = "recovery";
-+ reg = <0x180000 0xa80000>;
-+ };
-+
-+ partition@c00000 {
-+ label = "fit";
-+ reg = <0xc00000 0x1400000>;
-+ };
-+ };
-+ };
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
-@@ -0,0 +1,23 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+/*
-+ * Copyright (C) 2021 MediaTek Inc.
-+ * Author: Sam.Shih <sam.shih@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+ fragment@0 {
-+ target-path = "/soc/mmc@11230000";
-+ __overlay__ {
-+ bus-width = <4>;
-+ max-frequency = <52000000>;
-+ cap-sd-highspeed;
-+ status = "okay";
-+ };
-+ };
-+};
-+
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -0,0 +1,450 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+/*
-+ * Copyright (C) 2021 MediaTek Inc.
-+ * Authors: Sam.Shih <sam.shih@mediatek.com>
-+ * Frank Wunderlich <frank-w@public-files.de>
-+ * Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/mt65xx.h>
-+
-+#include "mt7986a.dtsi"
-+
-+/ {
-+ model = "Bananapi BPI-R3";
-+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+ aliases {
-+ serial0 = &uart0;
-+ ethernet0 = &gmac0;
-+ ethernet1 = &gmac1;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ dcin: regulator-12vd {
-+ compatible = "regulator-fixed";
-+ regulator-name = "12vd";
-+ regulator-min-microvolt = <12000000>;
-+ regulator-max-microvolt = <12000000>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+ };
-+
-+ gpio-keys {
-+ compatible = "gpio-keys";
-+
-+ reset-key {
-+ label = "reset";
-+ linux,code = <KEY_RESTART>;
-+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
-+ };
-+
-+ wps-key {
-+ label = "wps";
-+ linux,code = <KEY_WPS_BUTTON>;
-+ gpios = <&pio 10 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+
-+ /* i2c of the left SFP cage (wan) */
-+ i2c_sfp1: i2c-gpio-0 {
-+ compatible = "i2c-gpio";
-+ sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-+ scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-+ i2c-gpio,delay-us = <2>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ /* i2c of the right SFP cage (lan) */
-+ i2c_sfp2: i2c-gpio-1 {
-+ compatible = "i2c-gpio";
-+ sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-+ scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-+ i2c-gpio,delay-us = <2>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ green_led: led-0 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_POWER;
-+ gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
-+ default-state = "on";
-+ };
-+
-+ blue_led: led-1 {
-+ color = <LED_COLOR_ID_BLUE>;
-+ function = LED_FUNCTION_STATUS;
-+ gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
-+ default-state = "off";
-+ };
-+ };
-+
-+ reg_1p8v: regulator-1p8v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "1.8vd";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+ vin-supply = <&dcin>;
-+ };
-+
-+ reg_3p3v: regulator-3p3v {
-+ compatible = "regulator-fixed";
-+ regulator-name = "3.3vd";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-boot-on;
-+ regulator-always-on;
-+ vin-supply = <&dcin>;
-+ };
-+
-+ /* left SFP cage (wan) */
-+ sfp1: sfp-1 {
-+ compatible = "sff,sfp";
-+ i2c-bus = <&i2c_sfp1>;
-+ los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
-+ mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
-+ tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
-+ tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ /* right SFP cage (lan) */
-+ sfp2: sfp-2 {
-+ compatible = "sff,sfp";
-+ i2c-bus = <&i2c_sfp2>;
-+ los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
-+ mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
-+ tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
-+ tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
-+ };
-+};
-+
-+&crypto {
-+ status = "okay";
-+};
-+
-+ð {
-+ status = "okay";
-+
-+ gmac0: mac@0 {
-+ compatible = "mediatek,eth-mac";
-+ reg = <0>;
-+ phy-mode = "2500base-x";
-+
-+ fixed-link {
-+ speed = <2500>;
-+ full-duplex;
-+ pause;
-+ };
-+ };
-+
-+ gmac1: mac@1 {
-+ compatible = "mediatek,eth-mac";
-+ reg = <1>;
-+ phy-mode = "2500base-x";
-+ sfp = <&sfp1>;
-+ managed = "in-band-status";
-+ };
-+
-+ mdio: mdio-bus {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+};
-+
-+&mdio {
-+ switch: switch@1f {
-+ compatible = "mediatek,mt7531";
-+ reg = <31>;
-+ interrupt-controller;
-+ #interrupt-cells = <1>;
-+ interrupt-parent = <&pio>;
-+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
-+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
-+ };
-+};
-+
-+&mmc0 {
-+ pinctrl-names = "default", "state_uhs";
-+ pinctrl-0 = <&mmc0_pins_default>;
-+ pinctrl-1 = <&mmc0_pins_uhs>;
-+ vmmc-supply = <®_3p3v>;
-+ vqmmc-supply = <®_1p8v>;
-+};
-+
-+&i2c0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c_pins>;
-+ status = "okay";
-+};
-+
-+&pcie {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_pins>;
-+ status = "okay";
-+};
-+
-+&pcie_phy {
-+ status = "okay";
-+};
-+
-+&pio {
-+ i2c_pins: i2c-pins {
-+ mux {
-+ function = "i2c";
-+ groups = "i2c";
-+ };
-+ };
-+
-+ mmc0_pins_default: mmc0-pins {
-+ mux {
-+ function = "emmc";
-+ groups = "emmc_51";
-+ };
-+ conf-cmd-dat {
-+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+ input-enable;
-+ drive-strength = <4>;
-+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+ };
-+ conf-clk {
-+ pins = "EMMC_CK";
-+ drive-strength = <6>;
-+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+ };
-+ conf-ds {
-+ pins = "EMMC_DSL";
-+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+ };
-+ conf-rst {
-+ pins = "EMMC_RSTB";
-+ drive-strength = <4>;
-+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+ };
-+ };
-+
-+ mmc0_pins_uhs: mmc0-uhs-pins {
-+ mux {
-+ function = "emmc";
-+ groups = "emmc_51";
-+ };
-+ conf-cmd-dat {
-+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
-+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
-+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
-+ input-enable;
-+ drive-strength = <4>;
-+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+ };
-+ conf-clk {
-+ pins = "EMMC_CK";
-+ drive-strength = <6>;
-+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+ };
-+ conf-ds {
-+ pins = "EMMC_DSL";
-+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
-+ };
-+ conf-rst {
-+ pins = "EMMC_RSTB";
-+ drive-strength = <4>;
-+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
-+ };
-+ };
-+
-+ pcie_pins: pcie-pins {
-+ mux {
-+ function = "pcie";
-+ groups = "pcie_clk", "pcie_pereset";
-+ };
-+ };
-+
-+ spi_flash_pins: spi-flash-pins {
-+ mux {
-+ function = "spi";
-+ groups = "spi0", "spi0_wp_hold";
-+ };
-+ };
-+
-+ spic_pins: spic-pins {
-+ mux {
-+ function = "spi";
-+ groups = "spi1_0";
-+ };
-+ };
-+
-+ uart1_pins: uart1-pins {
-+ mux {
-+ function = "uart";
-+ groups = "uart1_rx_tx";
-+ };
-+ };
-+
-+ uart2_pins: uart2-pins {
-+ mux {
-+ function = "uart";
-+ groups = "uart2_0_rx_tx";
-+ };
-+ };
-+
-+ wf_2g_5g_pins: wf-2g-5g-pins {
-+ mux {
-+ function = "wifi";
-+ groups = "wf_2g", "wf_5g";
-+ };
-+ conf {
-+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-+ "WF1_TOP_CLK", "WF1_TOP_DATA";
-+ drive-strength = <4>;
-+ };
-+ };
-+
-+ wf_dbdc_pins: wf-dbdc-pins {
-+ mux {
-+ function = "wifi";
-+ groups = "wf_dbdc";
-+ };
-+ conf {
-+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
-+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
-+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
-+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
-+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
-+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
-+ "WF1_TOP_CLK", "WF1_TOP_DATA";
-+ drive-strength = <4>;
-+ };
-+ };
-+
-+ wf_led_pins: wf-led-pins {
-+ mux {
-+ function = "led";
-+ groups = "wifi_led";
-+ };
-+ };
-+};
-+
-+&spi0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi_flash_pins>;
-+ status = "okay";
-+};
-+
-+&spi1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spic_pins>;
-+ status = "okay";
-+};
-+
-+&ssusb {
-+ status = "okay";
-+};
-+
-+&switch {
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ port@0 {
-+ reg = <0>;
-+ label = "wan";
-+ };
-+
-+ port@1 {
-+ reg = <1>;
-+ label = "lan0";
-+ };
-+
-+ port@2 {
-+ reg = <2>;
-+ label = "lan1";
-+ };
-+
-+ port@3 {
-+ reg = <3>;
-+ label = "lan2";
-+ };
-+
-+ port@4 {
-+ reg = <4>;
-+ label = "lan3";
-+ };
-+
-+ port5: port@5 {
-+ reg = <5>;
-+ label = "lan4";
-+ phy-mode = "2500base-x";
-+ sfp = <&sfp2>;
-+ managed = "in-band-status";
-+ };
-+
-+ port@6 {
-+ reg = <6>;
-+ label = "cpu";
-+ ethernet = <&gmac0>;
-+ phy-mode = "2500base-x";
-+
-+ fixed-link {
-+ speed = <2500>;
-+ full-duplex;
-+ pause;
-+ };
-+ };
-+ };
-+};
-+
-+&trng {
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
-+
-+&uart1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart1_pins>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart2_pins>;
-+ status = "okay";
-+};
-+
-+&usb_phy {
-+ status = "okay";
-+};
-+
-+&watchdog {
-+ status = "okay";
-+};
-+
-+&wifi {
-+ status = "okay";
-+ pinctrl-names = "default", "dbdc";
-+ pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
-+ pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-+};
-+
+++ /dev/null
-From 4c2d5411f4b101f7aa0fd74f80109e3afd6dc967 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Wed, 17 May 2023 12:11:08 +0200
-Subject: [PATCH 11/19] arm64: mediatek: Propagate chassis-type where possible
-
-The chassis-type string identifies the form-factor of the system:
-add this property to all device trees of devices for which the form
-factor is known.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230517101108.205654-1-angelogioacchino.delregno@collabora.com
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt6755-evb.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt6795-evb.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt6797-evb.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8173-elm.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts | 1 +
- .../boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts | 1 +
- arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 1 +
- 28 files changed, 28 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
-@@ -11,6 +11,7 @@
-
- / {
- model = "MediaTek MT2712 evaluation board";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts
-@@ -9,6 +9,7 @@
-
- / {
- model = "MediaTek MT6755 EVB";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt6755-evb", "mediatek,mt6755";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
-@@ -10,6 +10,7 @@
-
- / {
- model = "MediaTek MT6779 EVB";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts
-@@ -9,6 +9,7 @@
-
- / {
- model = "MediaTek MT6795 Evaluation Board";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts
-@@ -9,6 +9,7 @@
-
- / {
- model = "MediaTek MT6797 Evaluation Board";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts
-@@ -12,6 +12,7 @@
-
- / {
- model = "Mediatek X20 Development Board";
-+ chassis-type = "embedded";
- compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -15,6 +15,7 @@
-
- / {
- model = "Bananapi BPI-R64";
-+ chassis-type = "embedded";
- compatible = "bananapi,bpi-r64", "mediatek,mt7622";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -15,6 +15,7 @@
-
- / {
- model = "MediaTek MT7622 RFB1 board";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -16,6 +16,7 @@
-
- / {
- model = "Bananapi BPI-R3";
-+ chassis-type = "embedded";
- compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
-@@ -11,6 +11,7 @@
-
- / {
- model = "MediaTek MT7986a RFB";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
-@@ -9,6 +9,7 @@
-
- / {
- model = "MediaTek MT7986b RFB";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts
-@@ -11,6 +11,7 @@
-
- / {
- model = "Pumpkin MT8167";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";
-
- memory@40000000 {
---- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts
-@@ -8,6 +8,7 @@
-
- / {
- model = "Google Hanawl";
-+ chassis-type = "laptop";
- compatible = "google,hana-rev7", "mediatek,mt8173";
- };
-
---- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts
-@@ -8,6 +8,7 @@
-
- / {
- model = "Google Hana";
-+ chassis-type = "laptop";
- compatible = "google,hana-rev6", "google,hana-rev5",
- "google,hana-rev4", "google,hana-rev3",
- "google,hana", "mediatek,mt8173";
---- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts
-@@ -8,6 +8,7 @@
-
- / {
- model = "Google Elm";
-+ chassis-type = "laptop";
- compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6",
- "google,elm-rev5", "google,elm-rev4", "google,elm-rev3",
- "google,elm", "mediatek,mt8173";
---- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
-@@ -10,6 +10,7 @@
-
- / {
- model = "MediaTek MT8173 evaluation board";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
-@@ -11,6 +11,7 @@
-
- / {
- model = "MediaTek MT8183 evaluation board";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
-
- aliases {
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts
-@@ -9,6 +9,7 @@
-
- / {
- model = "Google burnet board";
-+ chassis-type = "convertible";
- compatible = "google,burnet", "mediatek,mt8183";
- };
-
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
-@@ -9,6 +9,7 @@
-
- / {
- model = "Google damu board";
-+ chassis-type = "convertible";
- compatible = "google,damu", "mediatek,mt8183";
- };
-
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts
-@@ -9,6 +9,7 @@
-
- / {
- model = "Google juniper sku16 board";
-+ chassis-type = "convertible";
- compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183";
- };
-
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts
-@@ -9,6 +9,7 @@
-
- / {
- model = "MediaTek kakadu board sku22";
-+ chassis-type = "tablet";
- compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22",
- "google,kakadu", "mediatek,mt8183";
- };
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts
-@@ -9,6 +9,7 @@
-
- / {
- model = "MediaTek kakadu board";
-+ chassis-type = "tablet";
- compatible = "google,kakadu-rev3", "google,kakadu-rev2",
- "google,kakadu", "mediatek,mt8183";
- };
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts
-@@ -12,6 +12,7 @@
-
- / {
- model = "MediaTek kodama sku16 board";
-+ chassis-type = "tablet";
- compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183";
- };
-
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts
-@@ -12,6 +12,7 @@
-
- / {
- model = "MediaTek kodama sku272 board";
-+ chassis-type = "tablet";
- compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183";
- };
-
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts
-@@ -12,6 +12,7 @@
-
- / {
- model = "MediaTek kodama sku288 board";
-+ chassis-type = "tablet";
- compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183";
- };
-
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts
-@@ -14,6 +14,7 @@
-
- / {
- model = "MediaTek krane sku0 board";
-+ chassis-type = "tablet";
- compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183";
- };
-
---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
-@@ -14,6 +14,7 @@
-
- / {
- model = "MediaTek krane sku176 board";
-+ chassis-type = "tablet";
- compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";
- };
-
---- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
-@@ -7,6 +7,7 @@
-
- / {
- model = "MediaTek MT8186 evaluation board";
-+ chassis-type = "embedded";
- compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
-
- aliases {
+++ /dev/null
-From 3b92c547e3d4a35c6214b3e7fa1103d0749d83b1 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 21 Apr 2023 15:20:44 +0200
-Subject: [PATCH 12/19] arm64: dts: mt7986: add PWM
-
-This adds pwm node to mt7986.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20230421132047.42166-5-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -240,6 +240,20 @@
- status = "disabled";
- };
-
-+ pwm: pwm@10048000 {
-+ compatible = "mediatek,mt7986-pwm";
-+ reg = <0 0x10048000 0 0x1000>;
-+ #clock-cells = <1>;
-+ #pwm-cells = <2>;
-+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
-+ <&infracfg CLK_INFRA_PWM_STA>,
-+ <&infracfg CLK_INFRA_PWM1_CK>,
-+ <&infracfg CLK_INFRA_PWM2_CK>;
-+ clock-names = "top", "main", "pwm1", "pwm2";
-+ status = "disabled";
-+ };
-+
- uart0: serial@11002000 {
- compatible = "mediatek,mt7986-uart",
- "mediatek,mt6577-uart";
+++ /dev/null
-From 35e482bb599df010b4869017ff576dbb7a4d4c2e Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Fri, 21 Apr 2023 15:20:45 +0200
-Subject: [PATCH 13/19] arm64: dts: mt7986: add PWM to BPI-R3
-
-Add pwm node and pinctrl to BananaPi R3 devicetree.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Link: https://lore.kernel.org/r/20230421132047.42166-6-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -275,6 +275,13 @@
- };
- };
-
-+ pwm_pins: pwm-pins {
-+ mux {
-+ function = "pwm";
-+ groups = "pwm0", "pwm1_0";
-+ };
-+ };
-+
- spi_flash_pins: spi-flash-pins {
- mux {
- function = "spi";
-@@ -345,6 +352,12 @@
- };
- };
-
-+&pwm {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pwm_pins>;
-+ status = "okay";
-+};
-+
- &spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi_flash_pins>;
+++ /dev/null
-From ccdda5714446db8690505371442f7807f5d7c6fc Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 5 Feb 2023 18:48:33 +0100
-Subject: [PATCH 14/19] arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3
-
-Leds for Wifi are low-active, so add property to devicetree.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230205174833.107050-1-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -460,5 +460,9 @@
- pinctrl-names = "default", "dbdc";
- pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-+
-+ led {
-+ led-active-low;
-+ };
- };
-
+++ /dev/null
-From 1423b4b780adcf3994e63a5988a62d5d1d509bb1 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 28 May 2023 13:33:42 +0200
-Subject: [PATCH 15/19] arm64: dts: mt7986: use size of reserved partition for
- bl2
-
-To store uncompressed bl2 more space is required than partition is
-actually defined.
-
-There is currently no known usage of this reserved partition.
-Openwrt uses same partition layout.
-
-We added same change to u-boot with commit d7bb1099 [1].
-
-[1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e
-
-Cc: stable@vger.kernel.org
-Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3")
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/20230528113343.7649-1-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 7 +------
- 1 file changed, 1 insertion(+), 6 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-@@ -27,15 +27,10 @@
-
- partition@0 {
- label = "bl2";
-- reg = <0x0 0x20000>;
-+ reg = <0x0 0x40000>;
- read-only;
- };
-
-- partition@20000 {
-- label = "reserved";
-- reg = <0x20000 0x20000>;
-- };
--
- partition@40000 {
- label = "u-boot-env";
- reg = <0x40000 0x40000>;
+++ /dev/null
-From 40a5a767d698ef7a71f8be851ea18b0a7a8b47bd Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 30 May 2023 22:12:33 +0200
-Subject: [PATCH 16/19] arm64: dts: mt7986: add thermal and efuse
-
-Add thermal related nodes to mt7986 devicetree.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230530201235.22330-3-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 36 ++++++++++++++++++++++-
- 1 file changed, 35 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -337,6 +337,15 @@
- status = "disabled";
- };
-
-+ auxadc: adc@1100d000 {
-+ compatible = "mediatek,mt7986-auxadc";
-+ reg = <0 0x1100d000 0 0x1000>;
-+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
-+ clock-names = "main";
-+ #io-channel-cells = <1>;
-+ status = "disabled";
-+ };
-+
- ssusb: usb@11200000 {
- compatible = "mediatek,mt7986-xhci",
- "mediatek,mtk-xhci";
-@@ -375,6 +384,21 @@
- status = "disabled";
- };
-
-+ thermal: thermal@1100c800 {
-+ #thermal-sensor-cells = <1>;
-+ compatible = "mediatek,mt7986-thermal";
-+ reg = <0 0x1100c800 0 0x800>;
-+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&infracfg CLK_INFRA_THERM_CK>,
-+ <&infracfg CLK_INFRA_ADC_26M_CK>,
-+ <&infracfg CLK_INFRA_ADC_FRC_CK>;
-+ clock-names = "therm", "auxadc", "adc_32k";
-+ mediatek,auxadc = <&auxadc>;
-+ mediatek,apmixedsys = <&apmixedsys>;
-+ nvmem-cells = <&thermal_calibration>;
-+ nvmem-cell-names = "calibration-data";
-+ };
-+
- pcie: pcie@11280000 {
- compatible = "mediatek,mt7986-pcie",
- "mediatek,mt8192-pcie";
-@@ -426,6 +450,17 @@
- };
- };
-
-+ efuse: efuse@11d00000 {
-+ compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
-+ reg = <0 0x11d00000 0 0x1000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ thermal_calibration: calib@274 {
-+ reg = <0x274 0xc>;
-+ };
-+ };
-+
- usb_phy: t-phy@11e10000 {
- compatible = "mediatek,mt7986-tphy",
- "mediatek,generic-tphy-v2";
-@@ -567,5 +602,4 @@
- memory-region = <&wmcpu_emi>;
- };
- };
--
- };
+++ /dev/null
-From bb78d0cf5117517f1ed296ae71048945d9107675 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 30 May 2023 22:12:34 +0200
-Subject: [PATCH 17/19] arm64: dts: mt7986: add thermal-zones
-
-Add thermal-zones to mt7986 devicetree.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230530201235.22330-4-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 +++++++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -602,4 +602,32 @@
- memory-region = <&wmcpu_emi>;
- };
- };
-+
-+ thermal-zones {
-+ cpu_thermal: cpu-thermal {
-+ polling-delay-passive = <1000>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&thermal 0>;
-+
-+ trips {
-+ cpu_trip_active_high: active-high {
-+ temperature = <115000>;
-+ hysteresis = <2000>;
-+ type = "active";
-+ };
-+
-+ cpu_trip_active_low: active-low {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "active";
-+ };
-+
-+ cpu_trip_passive: passive {
-+ temperature = <40000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+ };
-+ };
-+ };
- };
+++ /dev/null
-From 5d90603b09e5814ffc38c47e79ccf9bc564f9296 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 30 May 2023 22:12:35 +0200
-Subject: [PATCH 18/19] arm64: dts: mt7986: add pwm-fan and cooling-maps to
- BPI-R3 dts
-
-Add pwm-fan and cooling-maps to BananaPi-R3 devicetree.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230530201235.22330-5-linux@fw-web.de
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 31 +++++++++++++++++++
- 1 file changed, 31 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -38,6 +38,15 @@
- regulator-always-on;
- };
-
-+ fan: pwm-fan {
-+ compatible = "pwm-fan";
-+ #cooling-cells = <2>;
-+ /* cooling level (0, 1, 2) - pwm inverted */
-+ cooling-levels = <255 96 0>;
-+ pwms = <&pwm 0 10000 0>;
-+ status = "okay";
-+ };
-+
- gpio-keys {
- compatible = "gpio-keys";
-
-@@ -133,6 +142,28 @@
- };
- };
-
-+&cpu_thermal {
-+ cooling-maps {
-+ cpu-active-high {
-+ /* active: set fan to cooling level 2 */
-+ cooling-device = <&fan 2 2>;
-+ trip = <&cpu_trip_active_high>;
-+ };
-+
-+ cpu-active-low {
-+ /* active: set fan to cooling level 1 */
-+ cooling-device = <&fan 1 1>;
-+ trip = <&cpu_trip_active_low>;
-+ };
-+
-+ cpu-passive {
-+ /* passive: set fan to cooling level 0 */
-+ cooling-device = <&fan 0 0>;
-+ trip = <&cpu_trip_passive>;
-+ };
-+ };
-+};
-+
- &crypto {
- status = "okay";
- };
+++ /dev/null
-From 6dd3b939370094eb79529683be84500f3c757404 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 6 Jun 2023 16:43:20 +0100
-Subject: [PATCH 19/19] arm64: dts: mt7986: increase bl2 partition on NAND of
- Bananapi R3
-
-The bootrom burned into the MT7986 SoC will try multiple locations on
-the SPI-NAND flash to load bl2 in case the bl2 image located at the the
-previously attempted offset is corrupt.
-
-Use 0x100000 instead of 0x80000 as partition size for bl2 on SPI-NAND,
-allowing for up to four redundant copies of bl2 (typically sized a
-bit less than 0x40000).
-
-Fixes: 8e01fb15b8157 ("arm64: dts: mt7986: add Bananapi R3")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/ZH9UGF99RgzrHZ88@makrotopia.org
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
-@@ -29,13 +29,13 @@
-
- partition@0 {
- label = "bl2";
-- reg = <0x0 0x80000>;
-+ reg = <0x0 0x100000>;
- read-only;
- };
-
-- partition@80000 {
-+ partition@100000 {
- label = "reserved";
-- reg = <0x80000 0x300000>;
-+ reg = <0x100000 0x280000>;
- };
-
- partition@380000 {
+++ /dev/null
-From f8ed4088ed9c61ae92193da6130d04c37e7b19f2 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 20 Aug 2023 17:31:33 +0200
-Subject: [PATCH 20/22] arm64: dts: mt7986: define 3W max power to both SFP on
- BPI-R3
-
-All SFP power supplies are connected to the system VDD33 which is 3v3/8A.
-Set 3A per SFP slot to allow SFPs work which need more power than the
-default 1W.
-
-Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3")
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -126,6 +126,7 @@
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp1>;
- los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
-+ maximum-power-milliwatt = <3000>;
- mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
- tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
- tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-@@ -137,6 +138,7 @@
- i2c-bus = <&i2c_sfp2>;
- los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
-+ maximum-power-milliwatt = <3000>;
- tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
- tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
- };
+++ /dev/null
-From aa3d6df9803c267725dc72286bb91602b7579882 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 20 Aug 2023 17:31:34 +0200
-Subject: [PATCH 21/22] arm64: dts: mt7986: change cooling trips
-
-Add Critical and hot trips for emergency system shutdown and limiting
-system load.
-
-Change passive trip to active to make sure fan is activated on the
-lowest trip.
-
-Fixes: 1f5be05132f3 ("arm64: dts: mt7986: add thermal-zones")
-Suggested-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -610,22 +610,34 @@
- thermal-sensors = <&thermal 0>;
-
- trips {
-+ cpu_trip_crit: crit {
-+ temperature = <125000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+
-+ cpu_trip_hot: hot {
-+ temperature = <120000>;
-+ hysteresis = <2000>;
-+ type = "hot";
-+ };
-+
- cpu_trip_active_high: active-high {
- temperature = <115000>;
- hysteresis = <2000>;
- type = "active";
- };
-
-- cpu_trip_active_low: active-low {
-+ cpu_trip_active_med: active-med {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "active";
- };
-
-- cpu_trip_passive: passive {
-- temperature = <40000>;
-+ cpu_trip_active_low: active-low {
-+ temperature = <60000>;
- hysteresis = <2000>;
-- type = "passive";
-+ type = "active";
- };
- };
- };
+++ /dev/null
-From 6ddf23526955b8dbedfeaa57e691261fd73f9d4e Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 20 Aug 2023 17:31:35 +0200
-Subject: [PATCH 22/22] arm64: dts: mt7986: change thermal trips on BPI-R3
-
-Apply new naming after mt7986 thermal trips were changed.
-
-Fixes: c26f779a2295 ("arm64: dts: mt7986: add pwm-fan and cooling-maps to BPI-R3 dts")
-Suggested-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -152,16 +152,16 @@
- trip = <&cpu_trip_active_high>;
- };
-
-- cpu-active-low {
-+ cpu-active-med {
- /* active: set fan to cooling level 1 */
- cooling-device = <&fan 1 1>;
-- trip = <&cpu_trip_active_low>;
-+ trip = <&cpu_trip_active_med>;
- };
-
-- cpu-passive {
-- /* passive: set fan to cooling level 0 */
-+ cpu-active-low {
-+ /* active: set fan to cooling level 0 */
- cooling-device = <&fan 0 0>;
-- trip = <&cpu_trip_passive>;
-+ trip = <&cpu_trip_active_low>;
- };
- };
- };
+++ /dev/null
-From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
-From: OpenWrt community <openwrt-devel@lists.openwrt.org>
-Date: Wed, 13 Jul 2022 13:37:33 +0200
-Subject: [PATCH] kernel: add block fit partition parser
-
----
- block/blk.h | 2 ++
- block/partitions/Kconfig | 7 +++++++
- block/partitions/Makefile | 1 +
- block/partitions/check.h | 3 +++
- block/partitions/core.c | 17 +++++++++++++++++
- block/partitions/efi.c | 8 ++++++++
- block/partitions/efi.h | 3 +++
- block/partitions/msdos.c | 10 ++++++++++
- drivers/mtd/mtd_blkdevs.c | 2 ++
- drivers/mtd/ubi/block.c | 3 +++
- include/linux/msdos_partition.h | 1 +
- 11 files changed, 57 insertions(+)
-
---- a/block/blk.h
-+++ b/block/blk.h
-@@ -414,6 +414,8 @@ void blk_free_ext_minor(unsigned int min
- #define ADDPART_FLAG_NONE 0
- #define ADDPART_FLAG_RAID 1
- #define ADDPART_FLAG_WHOLEDISK 2
-+#define ADDPART_FLAG_READONLY 4
-+#define ADDPART_FLAG_ROOTDEV 8
- int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
- sector_t length);
- int bdev_del_partition(struct gendisk *disk, int partno);
---- a/block/partitions/Kconfig
-+++ b/block/partitions/Kconfig
-@@ -103,6 +103,13 @@ config ATARI_PARTITION
- Say Y here if you would like to use hard disks under Linux which
- were partitioned under the Atari OS.
-
-+config FIT_PARTITION
-+ bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
-+ default n
-+ help
-+ Say Y here if your system needs to mount the filesystem part of
-+ a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
-+
- config IBM_PARTITION
- bool "IBM disk label and partition support"
- depends on PARTITION_ADVANCED && S390
---- a/block/partitions/Makefile
-+++ b/block/partitions/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
- obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
- obj-$(CONFIG_ATARI_PARTITION) += atari.o
- obj-$(CONFIG_AIX_PARTITION) += aix.o
-+obj-$(CONFIG_FIT_PARTITION) += fit.o
- obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
- obj-$(CONFIG_MAC_PARTITION) += mac.o
- obj-$(CONFIG_LDM_PARTITION) += ldm.o
---- a/block/partitions/check.h
-+++ b/block/partitions/check.h
-@@ -57,6 +57,7 @@ int amiga_partition(struct parsed_partit
- int atari_partition(struct parsed_partitions *state);
- int cmdline_partition(struct parsed_partitions *state);
- int efi_partition(struct parsed_partitions *state);
-+int fit_partition(struct parsed_partitions *state);
- int ibm_partition(struct parsed_partitions *);
- int karma_partition(struct parsed_partitions *state);
- int ldm_partition(struct parsed_partitions *state);
-@@ -67,3 +68,5 @@ int sgi_partition(struct parsed_partitio
- int sun_partition(struct parsed_partitions *state);
- int sysv68_partition(struct parsed_partitions *state);
- int ultrix_partition(struct parsed_partitions *state);
-+
-+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
---- a/block/partitions/core.c
-+++ b/block/partitions/core.c
-@@ -11,6 +11,9 @@
- #include <linux/vmalloc.h>
- #include <linux/raid/detect.h>
- #include <linux/property.h>
-+#ifdef CONFIG_FIT_PARTITION
-+#include <linux/root_dev.h>
-+#endif
-
- #include "check.h"
-
-@@ -48,6 +51,9 @@ static int (*check_part[])(struct parsed
- #ifdef CONFIG_EFI_PARTITION
- efi_partition, /* this must come before msdos */
- #endif
-+#ifdef CONFIG_FIT_PARTITION
-+ fit_partition,
-+#endif
- #ifdef CONFIG_SGI_PARTITION
- sgi_partition,
- #endif
-@@ -439,6 +445,11 @@ static struct block_device *add_partitio
- goto out_del;
- }
-
-+#ifdef CONFIG_FIT_PARTITION
-+ if (flags & ADDPART_FLAG_READONLY)
-+ bdev->bd_read_only = true;
-+#endif
-+
- /* everything is up and running, commence */
- err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
- if (err)
-@@ -631,6 +642,11 @@ static bool blk_add_partition(struct gen
- (state->parts[p].flags & ADDPART_FLAG_RAID))
- md_autodetect_dev(part->bd_dev);
-
-+#ifdef CONFIG_FIT_PARTITION
-+ if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
-+ ROOT_DEV = part->bd_dev;
-+#endif
-+
- return true;
- }
-
---- a/block/partitions/efi.c
-+++ b/block/partitions/efi.c
-@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
- gpt_entry *ptes = NULL;
- u32 i;
- unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
-+#ifdef CONFIG_FIT_PARTITION
-+ u32 extra_slot = 64;
-+#endif
-
- if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
- kfree(gpt);
-@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
- ARRAY_SIZE(ptes[i].partition_name));
- utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
- state->parts[i + 1].has_info = true;
-+#ifdef CONFIG_FIT_PARTITION
-+ /* If this is a U-Boot FIT volume it may have subpartitions */
-+ if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
-+ (void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
-+#endif
- }
- kfree(ptes);
- kfree(gpt);
---- a/block/partitions/efi.h
-+++ b/block/partitions/efi.h
-@@ -51,6 +51,9 @@
- #define PARTITION_LINUX_LVM_GUID \
- EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
- 0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
-+#define PARTITION_LINUX_FIT_GUID \
-+ EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
-+ 0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
-
- typedef struct _gpt_header {
- __le64 signature;
---- a/block/partitions/msdos.c
-+++ b/block/partitions/msdos.c
-@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
- #endif /* CONFIG_MINIX_SUBPARTITION */
- }
-
-+static void parse_fit_mbr(struct parsed_partitions *state,
-+ sector_t offset, sector_t size, int origin)
-+{
-+#ifdef CONFIG_FIT_PARTITION
-+ u32 extra_slot = 64;
-+ (void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
-+#endif /* CONFIG_FIT_PARTITION */
-+}
-+
- static struct {
- unsigned char id;
- void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
-@@ -575,6 +584,7 @@ static struct {
- {UNIXWARE_PARTITION, parse_unixware},
- {SOLARIS_X86_PARTITION, parse_solaris_x86},
- {NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
-+ {FIT_PARTITION, parse_fit_mbr},
- {0, NULL},
- };
-
---- a/drivers/mtd/mtd_blkdevs.c
-+++ b/drivers/mtd/mtd_blkdevs.c
-@@ -359,7 +359,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt
- } else {
- snprintf(gd->disk_name, sizeof(gd->disk_name),
- "%s%d", tr->name, new->devnum);
-- gd->flags |= GENHD_FL_NO_PART;
-+
-+ if (!IS_ENABLED(CONFIG_FIT_PARTITION) || mtd_type_is_nand(new->mtd))
-+ gd->flags |= GENHD_FL_NO_PART;
- }
-
- set_capacity(gd, ((u64)new->size * tr->blksize) >> 9);
---- a/drivers/mtd/ubi/block.c
-+++ b/drivers/mtd/ubi/block.c
-@@ -432,7 +432,9 @@ int ubiblock_create(struct ubi_volume_in
- ret = -ENODEV;
- goto out_cleanup_disk;
- }
-- gd->flags |= GENHD_FL_NO_PART;
-+ if (!IS_ENABLED(CONFIG_FIT_PARTITION))
-+ gd->flags |= GENHD_FL_NO_PART;
-+
- gd->private_data = dev;
- sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
- set_capacity(gd, disk_capacity);
---- a/include/linux/msdos_partition.h
-+++ b/include/linux/msdos_partition.h
-@@ -31,6 +31,7 @@ enum msdos_sys_ind {
- LINUX_LVM_PARTITION = 0x8e,
- LINUX_RAID_PARTITION = 0xfd, /* autodetect RAID partition */
-
-+ FIT_PARTITION = 0x2e, /* U-Boot uImage.FIT */
- SOLARIS_X86_PARTITION = 0x82, /* also Linux swap partitions */
- NEW_SOLARIS_X86_PARTITION = 0xbf,
-
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -1,7 +1,6 @@
- /*
-- * Copyright (c) 2017 MediaTek Inc.
-- * Author: Ming Huang <ming.huang@mediatek.com>
-- * Sean Wang <sean.wang@mediatek.com>
-+ * Copyright (c) 2018 MediaTek Inc.
-+ * Author: Ryder Lee <ryder.lee@mediatek.com>
- *
- * SPDX-License-Identifier: (GPL-2.0 OR MIT)
- */
-@@ -24,7 +23,7 @@
-
- chosen {
- stdout-path = "serial0:115200n8";
-- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- };
-
- cpus {
-@@ -45,18 +44,18 @@
- key-factory {
- label = "factory";
- linux,code = <BTN_0>;
-- gpios = <&pio 0 0>;
-+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
- };
-
- key-wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
-- gpios = <&pio 102 0>;
-+ gpios = <&pio 102 GPIO_ACTIVE_LOW>;
- };
- };
-
- memory@40000000 {
-- reg = <0 0x40000000 0 0x20000000>;
-+ reg = <0 0x40000000 0 0x40000000>;
- };
-
- reg_1p8v: regulator-1p8v {
-@@ -132,22 +131,22 @@
-
- port@0 {
- reg = <0>;
-- label = "lan0";
-+ label = "lan1";
- };
-
- port@1 {
- reg = <1>;
-- label = "lan1";
-+ label = "lan2";
- };
-
- port@2 {
- reg = <2>;
-- label = "lan2";
-+ label = "lan3";
- };
-
- port@3 {
- reg = <3>;
-- label = "lan3";
-+ label = "lan4";
- };
-
- port@4 {
-@@ -240,7 +239,22 @@
- status = "okay";
- };
-
-+&pcie1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie1_pins>;
-+ status = "okay";
-+};
-+
- &pio {
-+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
-+ * SATA functions. i.e. output-high: PCIe, output-low: SATA
-+ */
-+ asm_sel {
-+ gpio-hog;
-+ gpios = <90 GPIO_ACTIVE_HIGH>;
-+ output-high;
-+ };
-+
- /* eMMC is shared pin with parallel NAND */
- emmc_pins_default: emmc-pins-default {
- mux {
-@@ -517,11 +531,11 @@
- };
-
- &sata {
-- status = "okay";
-+ status = "disabled";
- };
-
- &sata_phy {
-- status = "okay";
-+ status = "disabled";
- };
-
- &spi0 {
+++ /dev/null
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -18,6 +18,7 @@
-
- chosen {
- stdout-path = "serial0:115200n8";
-+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
- };
-
- gpio-keys {
-@@ -70,6 +71,10 @@
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "2500base-x";
-+
-+ nvmem-cells = <&macaddr_factory_2a>;
-+ nvmem-cell-names = "mac-address";
-+
- fixed-link {
- speed = <2500>;
- full-duplex;
-@@ -82,6 +87,9 @@
- reg = <1>;
- phy-mode = "gmii";
- phy-handle = <&phy0>;
-+
-+ nvmem-cells = <&macaddr_factory_24>;
-+ nvmem-cell-names = "mac-address";
- };
-
- mdio: mdio-bus {
-@@ -133,8 +141,9 @@
- };
-
- partition@b0000 {
-- label = "kernel";
-+ label = "firmware";
- reg = <0xb0000 0xb50000>;
-+ compatible = "denx,fit";
- };
- };
- };
-@@ -273,3 +282,17 @@
- pinctrl-0 = <&watchdog_pins>;
- status = "okay";
- };
-+
-+&factory {
-+ compatible = "nvmem-cells";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ macaddr_factory_24: macaddr@24 {
-+ reg = <0x24 0x6>;
-+ };
-+
-+ macaddr_factory_2a: macaddr@2a {
-+ reg = <0x2a 0x6>;
-+ };
-+};
+++ /dev/null
-From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001
-From: Chuanhong Guo <gch981213@gmail.com>
-Date: Fri, 29 Apr 2022 10:40:56 +0800
-Subject: [PATCH] arm: mediatek: select arch timer for mt7623
-
-Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
----
- arch/arm/mach-mediatek/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/mach-mediatek/Kconfig
-+++ b/arch/arm/mach-mediatek/Kconfig
-@@ -26,6 +26,7 @@ config MACH_MT6592
- config MACH_MT7623
- bool "MediaTek MT7623 SoCs support"
- default ARCH_MEDIATEK
-+ select HAVE_ARM_ARCH_TIMER
-
- config MACH_MT7629
- bool "MediaTek MT7629 SoCs support"
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -578,6 +578,7 @@
- compatible = "mediatek,mt7622-nor",
- "mediatek,mt8173-nor";
- reg = <0 0x11014000 0 0xe0>;
-+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_FLASH_PD>,
- <&topckgen CLK_TOP_FLASH_SEL>;
- clock-names = "spi", "sf";
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -134,6 +134,13 @@
- #size-cells = <2>;
- ranges;
-
-+ /* 64 KiB reserved for ramoops/pstore */
-+ ramoops@42ff0000 {
-+ compatible = "ramoops";
-+ reg = <0 0x42ff0000 0 0x10000>;
-+ record-size = <0x1000>;
-+ };
-+
- /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- secmon_reserved: secmon@43000000 {
- reg = <0 0x43000000 0 0x30000>;
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -108,10 +108,6 @@
- status = "disabled";
- };
-
--&btif {
-- status = "okay";
--};
--
- &cir {
- pinctrl-names = "default";
- pinctrl-0 = <&irrx_pins>;
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -89,10 +89,6 @@
- status = "disabled";
- };
-
--&btif {
-- status = "okay";
--};
--
- &cir {
- pinctrl-names = "default";
- pinctrl-0 = <&irrx_pins>;
+++ /dev/null
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -19,6 +19,7 @@
-
- chosen {
- stdout-path = "serial2:115200n8";
-+ bootargs = "console=ttyS2,115200n8 console=tty1";
- };
-
- connector {
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -24,7 +24,7 @@
-
- chosen {
- stdout-path = "serial0:115200n8";
-- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
-+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- };
-
- cpus {
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -20,6 +20,7 @@
-
- aliases {
- serial0 = &uart0;
-+ ethernet0 = &gmac0;
- };
-
- chosen {
-@@ -160,22 +161,22 @@
-
- port@1 {
- reg = <1>;
-- label = "lan0";
-+ label = "lan1";
- };
-
- port@2 {
- reg = <2>;
-- label = "lan1";
-+ label = "lan2";
- };
-
- port@3 {
- reg = <3>;
-- label = "lan2";
-+ label = "lan3";
- };
-
- port@4 {
- reg = <4>;
-- label = "lan3";
-+ label = "lan4";
- };
-
- port@6 {
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -21,6 +21,12 @@
- aliases {
- serial0 = &uart0;
- ethernet0 = &gmac0;
-+ led-boot = &led_system_green;
-+ led-failsafe = &led_system_blue;
-+ led-running = &led_system_green;
-+ led-upgrade = &led_system_blue;
-+ mmc0 = &mmc0;
-+ mmc1 = &mmc1;
- };
-
- chosen {
-@@ -44,8 +50,8 @@
- compatible = "gpio-keys";
-
- factory-key {
-- label = "factory";
-- linux,code = <BTN_0>;
-+ label = "reset";
-+ linux,code = <KEY_RESTART>;
- gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
- };
-
-@@ -59,17 +65,17 @@
- leds {
- compatible = "gpio-leds";
-
-- led-0 {
-+ led_system_green: led-0 {
- label = "bpi-r64:pio:green";
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
-- led-1 {
-- label = "bpi-r64:pio:red";
-- color = <LED_COLOR_ID_RED>;
-- gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
-+ led_system_blue: led-1 {
-+ label = "bpi-r64:pio:blue";
-+ color = <LED_COLOR_ID_BLUE>;
-+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -556,12 +556,16 @@
- status = "okay";
- };
-
-+&rtc {
-+ status = "disabled";
-+};
-+
- &sata {
-- status = "disable";
-+ status = "disabled";
- };
-
- &sata_phy {
-- status = "disable";
-+ status = "disabled";
- };
-
- &spi0 {
+++ /dev/null
-From d278f43f25beedfd0cb784d1dd0a9e7e8c8f123f Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 19 Apr 2023 20:15:53 +0100
-Subject: [PATCH] arm64: dts: mt7622: declare SPI-NAND present on BPI-R64
-
-The SPI-NOR node in the device tree of the BananaPi R64 has most likely
-been copied from the reference board's device tree even though the R64
-comes with an SPI-NAND chip rather than SPI-NOR.
-
-Setup the Serial NAND Flash Interface (SNFI) controller, enable
-hardware BCH error detection and correction engine and add the SPI-NAND
-chip including basic partitions,
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/ZEA96dmaXqTpk8u8@makrotopia.org
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 38 ++++++++++++++++---
- 1 file changed, 33 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -253,14 +253,42 @@
- status = "disabled";
- };
-
--&nor_flash {
-- pinctrl-names = "default";
-- pinctrl-0 = <&spi_nor_pins>;
-- status = "disabled";
-+&bch {
-+ status = "okay";
-+};
-
-+&snfi {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&serial_nand_pins>;
-+ status = "okay";
- flash@0 {
-- compatible = "jedec,spi-nor";
-+ compatible = "spi-nand";
- reg = <0>;
-+ spi-tx-bus-width = <4>;
-+ spi-rx-bus-width = <4>;
-+ nand-ecc-engine = <&snfi>;
-+ partitions {
-+ compatible = "fixed-partitions";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "bl2";
-+ reg = <0x0 0x80000>;
-+ read-only;
-+ };
-+
-+ partition@80000 {
-+ label = "fip";
-+ reg = <0x80000 0x200000>;
-+ read-only;
-+ };
-+
-+ ubi: partition@280000 {
-+ label = "ubi";
-+ reg = <0x280000 0x7d80000>;
-+ };
-+ };
- };
- };
-
+++ /dev/null
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_
- static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
- {
- struct spinand_device *spinand = nand_to_spinand(nand);
-- u8 marker[2] = { };
-+ u8 marker[1] = { };
- struct nand_page_io_req req = {
- .pos = *pos,
- .ooblen = sizeof(marker),
-@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de
-
- spinand_select_target(spinand, pos->target);
- spinand_read_page(spinand, &req);
-- if (marker[0] != 0xff || marker[1] != 0xff)
-+ if (marker[0] != 0xff)
- return true;
-
- return false;
+++ /dev/null
-From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
-From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
-Date: Thu, 6 Jun 2019 16:29:04 +0800
-Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
-
-Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
----
- arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7629.dtsi | 22 ++++++++++++++++
- 3 files changed, 79 insertions(+)
-
---- a/arch/arm/boot/dts/mt7629.dtsi
-+++ b/arch/arm/boot/dts/mt7629.dtsi
-@@ -272,6 +272,27 @@
- status = "disabled";
- };
-
-+ snfi: spi@1100d000 {
-+ compatible = "mediatek,mt7629-snand";
-+ reg = <0x1100d000 0x1000>;
-+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
-+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
-+ clock-names = "nfi_clk", "pad_clk";
-+ nand-ecc-engine = <&bch>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ status = "disabled";
-+ };
-+
-+ bch: ecc@1100e000 {
-+ compatible = "mediatek,mt7622-ecc";
-+ reg = <0x1100e000 0x1000>;
-+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
-+ clocks = <&pericfg CLK_PERI_NFIECC_PD>;
-+ clock-names = "nfiecc_clk";
-+ status = "disabled";
-+ };
-+
- spi: spi@1100a000 {
- compatible = "mediatek,mt7629-spi",
- "mediatek,mt7622-spi";
---- a/arch/arm/boot/dts/mt7629-rfb.dts
-+++ b/arch/arm/boot/dts/mt7629-rfb.dts
-@@ -255,6 +255,50 @@
- };
- };
-
-+&bch {
-+ status = "okay";
-+};
-+
-+&snfi {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&serial_nand_pins>;
-+ status = "okay";
-+ flash@0 {
-+ compatible = "spi-nand";
-+ reg = <0>;
-+ spi-tx-bus-width = <4>;
-+ spi-rx-bus-width = <4>;
-+ nand-ecc-engine = <&snfi>;
-+
-+ partitions {
-+ compatible = "fixed-partitions";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "Bootloader";
-+ reg = <0x00000 0x0100000>;
-+ read-only;
-+ };
-+
-+ partition@100000 {
-+ label = "Config";
-+ reg = <0x100000 0x0040000>;
-+ };
-+
-+ partition@140000 {
-+ label = "factory";
-+ reg = <0x140000 0x0080000>;
-+ };
-+
-+ partition@1c0000 {
-+ label = "firmware";
-+ reg = <0x1c0000 0x1000000>;
-+ };
-+ };
-+ };
-+};
-+
- &spi {
- pinctrl-names = "default";
- pinctrl-0 = <&spi_pins>;
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -534,6 +534,65 @@
- status = "disabled";
- };
-
-+&bch {
-+ status = "okay";
-+};
-+
-+&snfi {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&serial_nand_pins>;
-+ status = "okay";
-+ flash@0 {
-+ compatible = "spi-nand";
-+ reg = <0>;
-+ spi-tx-bus-width = <4>;
-+ spi-rx-bus-width = <4>;
-+ nand-ecc-engine = <&snfi>;
-+
-+ partitions {
-+ compatible = "fixed-partitions";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "Preloader";
-+ reg = <0x00000 0x0080000>;
-+ read-only;
-+ };
-+
-+ partition@80000 {
-+ label = "ATF";
-+ reg = <0x80000 0x0040000>;
-+ };
-+
-+ partition@c0000 {
-+ label = "Bootloader";
-+ reg = <0xc0000 0x0080000>;
-+ };
-+
-+ partition@140000 {
-+ label = "Config";
-+ reg = <0x140000 0x0080000>;
-+ };
-+
-+ partition@1c0000 {
-+ label = "Factory";
-+ reg = <0x1c0000 0x0100000>;
-+ };
-+
-+ partition@200000 {
-+ label = "firmware";
-+ reg = <0x2c0000 0x2000000>;
-+ };
-+
-+ partition@2200000 {
-+ label = "User_data";
-+ reg = <0x22c0000 0x4000000>;
-+ };
-+ };
-+ };
-+};
-+
- &spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic0_pins>;
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -575,7 +575,7 @@
- reg = <0x140000 0x0080000>;
- };
-
-- partition@1c0000 {
-+ factory: partition@1c0000 {
- label = "Factory";
- reg = <0x1c0000 0x0100000>;
- };
-@@ -636,5 +636,6 @@
- &wmac {
- pinctrl-names = "default";
- pinctrl-0 = <&wmac_pins>;
-+ mediatek,mtd-eeprom = <&factory 0x0000>;
- status = "okay";
- };
+++ /dev/null
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -984,17 +984,15 @@
- };
-
- crypto: crypto@1b240000 {
-- compatible = "mediatek,eip97-crypto";
-+ compatible = "inside-secure,safexcel-eip97";
- reg = <0 0x1b240000 0 0x20000>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
-- <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
-- <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
-+ <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
- clocks = <ðsys CLK_ETHSYS_CRYPTO>;
-- clock-names = "cryp";
-- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
-- status = "disabled";
-+ status = "okay";
- };
-
- bdpsys: syscon@1c000000 {
+++ /dev/null
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -19,7 +19,7 @@
-
- chosen {
- stdout-path = "serial2:115200n8";
-- bootargs = "console=ttyS2,115200n8 console=tty1";
-+ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
- };
-
- connector {
+++ /dev/null
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -15,6 +15,8 @@
-
- aliases {
- serial2 = &uart2;
-+ mmc0 = &mmc0;
-+ mmc1 = &mmc1;
- };
-
- chosen {
+++ /dev/null
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -17,6 +17,10 @@
- serial2 = &uart2;
- mmc0 = &mmc0;
- mmc1 = &mmc1;
-+ led-boot = &led_system_green;
-+ led-failsafe = &led_system_blue;
-+ led-running = &led_system_green;
-+ led-upgrade = &led_system_blue;
- };
-
- chosen {
-@@ -112,13 +116,13 @@
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_a>;
-
-- blue {
-+ led_system_blue: blue {
- label = "bpi-r2:pio:blue";
- gpios = <&pio 240 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
-- green {
-+ led_system_green: green {
- label = "bpi-r2:pio:green";
- gpios = <&pio 241 GPIO_ACTIVE_LOW>;
- default-state = "off";
+++ /dev/null
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -15,6 +15,7 @@
-
- aliases {
- serial2 = &uart2;
-+ ethernet0 = &gmac0;
- mmc0 = &mmc0;
- mmc1 = &mmc1;
- led-boot = &led_system_green;
+++ /dev/null
---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
-@@ -26,7 +26,9 @@
-
- chosen {
- stdout-path = "serial2:115200n8";
-- bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
-+ bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
-+ rootdisk-emmc = <&emmc_rootdisk>;
-+ rootdisk-sd = <&sd_rootdisk>;
- };
-
- connector {
-@@ -315,6 +317,20 @@
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- non-removable;
-+
-+ card@0 {
-+ compatible = "mmc-card";
-+ reg = <0>;
-+
-+ block {
-+ compatible = "block-device";
-+ partitions {
-+ emmc_rootdisk: block-partition-fit {
-+ partno = <3>;
-+ };
-+ };
-+ };
-+ };
- };
-
- &mmc1 {
-@@ -328,6 +344,20 @@
- cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_3p3v>;
-+
-+ card@0 {
-+ compatible = "mmc-card";
-+ reg = <0>;
-+
-+ block {
-+ compatible = "block-device";
-+ partitions {
-+ sd_rootdisk: block-partition-fit {
-+ partno = <3>;
-+ };
-+ };
-+ };
-+ };
- };
-
- &mt6323_leds {
+++ /dev/null
-From 983f37ee08acb60435744f1b1e2afea2d2a09c48 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 19 Apr 2023 20:16:29 +0100
-Subject: [PATCH] arm64: dts: mt7622: handle interrupts from MT7531 switch on
- BPI-R64
-
-Since commit ba751e28d442 ("net: dsa: mt7530: add interrupt support")
-the mt7530 driver can act as an interrupt controller. Wire up irq line
-of the MT7531 switch on the BananaPi BPi-R64 board, so the status of
-the PHYs of the five 1000Base-T ports doesn't need to be polled any
-more.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/ZEA-DV_OsmFg5egL@makrotopia.org
-Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
----
- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -154,6 +154,10 @@
- switch@0 {
- compatible = "mediatek,mt7531";
- reg = <0>;
-+ interrupt-controller;
-+ #interrupt-cells = <1>;
-+ interrupt-parent = <&pio>;
-+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- reset-gpios = <&pio 54 0>;
-
- ports {
+++ /dev/null
-From patchwork Tue Apr 26 19:51:36 2022
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
-X-Patchwork-Id: 12827872
-Return-Path:
- <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>
-X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
- aws-us-west-2-korg-lkml-1.web.codeaurora.org
-Received: from bombadil.infradead.org (bombadil.infradead.org
- [198.137.202.133])
- (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
- (No client certificate requested)
- by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF
- for <linux-arm-kernel@archiver.kernel.org>;
- Tue, 26 Apr 2022 19:53:05 +0000 (UTC)
-DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
- d=lists.infradead.org; s=bombadil.20210309; h=Sender:
- Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:
- List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To:
- From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:
- Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:
- List-Owner; bh=OWGSxvlKoyPWz6b629RNINucULo6oOdFssAIiJETWRg=; b=T0HEjee0FX3hlb
- x5jl7xLK5sKM0pkE2oRgwzthbFlNg8ST1j/2GkgcgT0S2Bi0vRfFxHeu/RKzS9RmiVnKJnPGL8ctg
- WoBLyO5i+NcmosGoy6MmoOjGTNhj/+3q3Z1jRLBSJ4ySSP22X77YeuJTmVzySPUllQhWvDhjMVCR9
- QBRmQdc6gCAg3IYGEbWwS2TG+UHveDCeZRWxMzrwI8UPadNCRFROwugmiQ3mdU41lHCTDpnlfuRJh
- o1igLKfMBLz+D8rFYvDh7FfkcKkY6lNoswA2HKUun1MEzgoyQKmITPnG2maX/BvJJuj/B3ZJShh4k
- AZHmXoQxq1mrsm2FxfnQ==;
-Received: from localhost ([::1] helo=bombadil.infradead.org)
- by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux))
- id 1njRE5-00G05D-9z; Tue, 26 Apr 2022 19:51:57 +0000
-Received: from fudo.makrotopia.org ([2a07:2ec0:3002::71])
- by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux))
- id 1njRE1-00G03h-9H; Tue, 26 Apr 2022 19:51:55 +0000
-Received: from local
- by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256)
- (Exim 4.94.2) (envelope-from <daniel@makrotopia.org>)
- id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200
-Date: Tue, 26 Apr 2022 20:51:36 +0100
-From: Daniel Golle <daniel@makrotopia.org>
-To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org,
- linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
-Cc: Rob Herring <robh+dt@kernel.org>,
- Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
- Matthias Brugger <matthias.bgg@gmail.com>
-Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range
-Message-ID: <YmhNSLgp/yg8Vr1F@makrotopia.org>
-MIME-Version: 1.0
-Content-Disposition: inline
-X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3
-X-CRM114-CacheID: sfid-20220426_125153_359242_EA3D452C
-X-CRM114-Status: GOOD ( 12.45 )
-X-BeenThere: linux-arm-kernel@lists.infradead.org
-X-Mailman-Version: 2.1.34
-Precedence: list
-List-Id: <linux-arm-kernel.lists.infradead.org>
-List-Unsubscribe:
- <http://lists.infradead.org/mailman/options/linux-arm-kernel>,
- <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>
-List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/>
-List-Post: <mailto:linux-arm-kernel@lists.infradead.org>
-List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>
-List-Subscribe:
- <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,
- <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>
-Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
-Errors-To:
- linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
-
-With the current range specified for the CPU interface there is an
-error message at boot:
-
-GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
-
-Setting irqchip.gicv2_force_probe=1 in bootargs results in:
-
-GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB
-GIC: Adjusting CPU interface base to 0x000000001032f000
-GIC: Using split EOI/Deactivate mode
-
-Using the adjusted CPU interface base and 8K size results in only the
-final line remaining and fully working system as well as /proc/interrupts
-showing additional IPI3,4,5,6:
-
-IPI3: 0 0 CPU stop (for crash dump) interrupts
-IPI4: 0 0 Timer broadcast interrupts
-IPI5: 0 0 IRQ work interrupts
-IPI6: 0 0 CPU wake-up interrupts
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -346,7 +346,7 @@
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- reg = <0 0x10310000 0 0x1000>,
-- <0 0x10320000 0 0x1000>,
-+ <0 0x1032f000 0 0x2000>,
- <0 0x10340000 0 0x2000>,
- <0 0x10360000 0 0x2000>;
- };
+++ /dev/null
-From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001
-From: Bruno Umuarama <anonimou_eu@hotmail.com>
-Date: Thu, 13 Oct 2022 21:18:21 +0000
-Subject: [PATCH] mediatek: mt7623: fix thermal zone
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Raising the temperatures for passive and active trips. @VA1DER
-proposed at issue 9396 to remove passive trip. This commit relates to
-his suggestion.
-
-Without this patch. the CPU will be throttled all the way down to 98MHz
-if the temperature rises even a degree above the trip point, and it was
-further discovered that if the internal temperature of the device is
-above the first trip point temperature when it boots then it will start
-in a throttled state and even
-$ echo disabled > /sys/class/thermal/thermal_zone0/mode
-will have no effect.
-
-The patch increases the passive trip point and active cooling map. The
-throttling temperature will then be at 77°C and 82°C, which is still a
-low enough temperature for ARM devices to not be in the real danger
-zone, and gives some operational headroom.
-
-Signed-off-by: Bruno Umuarama <anonimou_eu@hotmail.com>
----
- arch/arm/boot/dts/mt7623.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/mt7623.dtsi
-+++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -160,13 +160,13 @@
-
- trips {
- cpu_passive: cpu-passive {
-- temperature = <57000>;
-+ temperature = <77000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_active: cpu-active {
-- temperature = <67000>;
-+ temperature = <82000>;
- hysteresis = <2000>;
- type = "active";
- };
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -68,6 +68,14 @@
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-+
-+ /* 64 KiB reserved for ramoops/pstore */
-+ ramoops@42ff0000 {
-+ compatible = "ramoops";
-+ reg = <0 0x42ff0000 0 0x10000>;
-+ record-size = <0x1000>;
-+ };
-+
- /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- secmon_reserved: secmon@43000000 {
- reg = <0 0x43000000 0 0x30000>;
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -23,6 +23,10 @@
- serial0 = &uart0;
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
-+ led-boot = &green_led;
-+ led-failsafe = &green_led;
-+ led-running = &green_led;
-+ led-upgrade = &blue_led;
- };
-
- chosen {
-@@ -419,27 +423,27 @@
-
- port@1 {
- reg = <1>;
-- label = "lan0";
-+ label = "lan1";
- };
-
- port@2 {
- reg = <2>;
-- label = "lan1";
-+ label = "lan2";
- };
-
- port@3 {
- reg = <3>;
-- label = "lan2";
-+ label = "lan3";
- };
-
- port@4 {
- reg = <4>;
-- label = "lan3";
-+ label = "lan4";
- };
-
- port5: port@5 {
- reg = <5>;
-- label = "lan4";
-+ label = "sfp2";
- phy-mode = "2500base-x";
- sfp = <&sfp2>;
- managed = "in-band-status";
-@@ -490,9 +494,137 @@
-
- &wifi {
- status = "okay";
-- pinctrl-names = "default", "dbdc";
-+ pinctrl-names = "default";
- pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
-- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
-+
-+ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7
-+ 0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182
-+ 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
-+ 0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
-+ 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3
-+ 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
-+ 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
-+ 0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
-+ 0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a
-+ 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
-+ 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00
-+ 0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
-+ 0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb
-+ 0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
-+ 0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
-+ 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc
-+ 0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
-+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
-+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
-+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
-+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
-+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
-+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
-+ 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x06000100 0x01050002 0x00ff0300
-+ 0xf900fe03 0x00000000 0x00000000 0x0000009b 0x6e370000 0x00000000 0x00fc0009 0x0a00fe00
-+ 0x060700fe 0x00070800 0x05000b0a 0x00000000 0x00000000 0x000000e2 0x96460000 0x00000000
-+ 0x000400f7 0xf8000300 0xfcfe0003 0x00fbfc00 0xee00e3f2 0x00000000 0x00000000 0x00000011
-+ 0xbb550000 0x00000000 0x000600f6 0xfc000300 0xfbfe0004 0x00fafe00 0xf600ecf2 0x00000000
-+ 0x00000000 0x0000001f 0xbf580000 0x00000000 0x000600f5 0xf6000400 0xf8f90004 0x00f7f800
-+ 0xf700f0f4 0x00000000 0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600
-+ 0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000
-+ 0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026
-+ 0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000
-+ 0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700
-+ 0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
-+ 0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
-+ 0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000
-+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
-+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
-+ 0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
-+ 0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
-+ 0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
-+ 0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
-+ 0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
-+ 0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
-+ 0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
-+ 0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
-+ 0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
-+ 0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
-+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
-
- led {
- led-active-low;
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-@@ -55,6 +55,7 @@
- partition@c00000 {
- label = "fit";
- reg = <0xc00000 0x1400000>;
-+ compatible = "denx,fit";
- };
- };
- };
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
-@@ -23,7 +23,27 @@
- no-sd;
- no-sdio;
- status = "okay";
-+
-+ card@0 {
-+ compatible = "mmc-card";
-+ reg = <0>;
-+
-+ block {
-+ compatible = "block-device";
-+ partitions {
-+ emmc_rootdisk: block-partition-production {
-+ partname = "production";
-+ };
-+ };
-+ };
-+ };
- };
- };
--};
-
-+ fragment@1 {
-+ target-path = "/chosen";
-+ __overlay__ {
-+ rootdisk-emmc = <&emmc_rootdisk>;
-+ };
-+ };
-+};
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
-@@ -29,27 +29,30 @@
-
- partition@0 {
- label = "bl2";
-- reg = <0x0 0x100000>;
-+ reg = <0x0 0x200000>;
- read-only;
- };
-
-- partition@100000 {
-- label = "reserved";
-- reg = <0x100000 0x280000>;
-- };
--
-- partition@380000 {
-- label = "fip";
-- reg = <0x380000 0x200000>;
-- read-only;
-- };
--
-- partition@580000 {
-+ partition@200000 {
- label = "ubi";
-- reg = <0x580000 0x7a80000>;
-+ reg = <0x200000 0x7e00000>;
-+ compatible = "linux,ubi";
-+
-+ volumes {
-+ nand_rootdisk: ubi-volume-fit {
-+ volname = "fit";
-+ };
-+ };
- };
- };
- };
- };
- };
-+
-+ fragment@1 {
-+ target-path = "/chosen";
-+ __overlay__ {
-+ rootdisk-spim-nand = <&nand_rootdisk>;
-+ };
-+ };
- };
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
-@@ -52,7 +52,7 @@
- reg = <0x180000 0xa80000>;
- };
-
-- partition@c00000 {
-+ nor_rootdisk: partition@c00000 {
- label = "fit";
- reg = <0xc00000 0x1400000>;
- compatible = "denx,fit";
-@@ -61,4 +61,11 @@
- };
- };
- };
-+
-+ fragment@1 {
-+ target-path = "/chosen";
-+ __overlay__ {
-+ rootdisk-nor = <&nor_rootdisk>;
-+ };
-+ };
- };
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
-@@ -17,6 +17,27 @@
- max-frequency = <52000000>;
- cap-sd-highspeed;
- status = "okay";
-+
-+ card@0 {
-+ compatible = "mmc-card";
-+ reg = <0>;
-+
-+ block {
-+ compatible = "block-device";
-+ partitions {
-+ sd_rootdisk: block-partition-production {
-+ partname = "production";
-+ };
-+ };
-+ };
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target-path = "/chosen";
-+ __overlay__ {
-+ rootdisk-sd = <&sd_rootdisk>;
- };
- };
- };
+++ /dev/null
-From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
-From: Kristian Evensen <kristian.evensen@gmail.com>
-Date: Mon, 30 Apr 2018 14:38:01 +0200
-Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
-
----
- drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
-
---- a/drivers/phy/mediatek/phy-mtk-tphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
-@@ -17,6 +17,8 @@
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/regmap.h>
-
- #include "phy-mtk-io.h"
-
-@@ -264,6 +266,9 @@
-
- #define TPHY_CLKS_CNT 2
-
-+#define HIF_SYSCFG1 0x14
-+#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20)
-+
- enum mtk_phy_version {
- MTK_PHY_V1 = 1,
- MTK_PHY_V2,
-@@ -331,6 +336,7 @@ struct mtk_tphy {
- void __iomem *sif_base; /* only shared sif */
- const struct mtk_phy_pdata *pdata;
- struct mtk_phy_instance **phys;
-+ struct regmap *hif;
- int nphys;
- int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
- int src_coef; /* coefficient for slew rate calibrate */
-@@ -596,6 +602,10 @@ static void pcie_phy_instance_init(struc
- if (tphy->pdata->version != MTK_PHY_V1)
- return;
-
-+ if (tphy->hif)
-+ regmap_update_bits(tphy->hif, HIF_SYSCFG1,
-+ HIF_SYSCFG1_PHY2_MASK, 0);
-+
- mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
- P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
- FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
-@@ -1241,6 +1251,16 @@ static int mtk_tphy_probe(struct platfor
- &tphy->src_coef);
- }
-
-+ if (of_find_property(np, "mediatek,phy-switch", NULL)) {
-+ tphy->hif = syscon_regmap_lookup_by_phandle(np,
-+ "mediatek,phy-switch");
-+ if (IS_ERR(tphy->hif)) {
-+ dev_err(&pdev->dev,
-+ "missing \"mediatek,phy-switch\" phandle\n");
-+ return PTR_ERR(tphy->hif);
-+ }
-+ }
-+
- port = 0;
- for_each_child_of_node(np, child_np) {
- struct mtk_phy_instance *instance;
+++ /dev/null
-From f76e8bc416bebb0f7b9f57b1247eae945421c0b9 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sat, 8 Oct 2022 18:48:06 +0200
-Subject: [PATCH 1/2] pinctrl: mt7986: allow configuring uart rx/tx and rts/cts
- separately
-
-Some mt7986 boards use uart rts/cts pins as gpio,
-This patch allows to change rts/cts to gpio mode, but keep
-rx/tx as UART function.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Link: https://lore.kernel.org/r/20221008164807.113590-1-linux@fw-web.de
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++-----
- 1 file changed, 25 insertions(+), 7 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-@@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4,
- static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
- static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
-
--static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
--static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
-+static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, };
-+static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, };
-
--static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
--static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
-+static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, };
-+static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, };
-+
-+static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, };
-+static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, };
-+
-+static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, };
-+static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, };
-
- static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
- static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
-@@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = {
- static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
- static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
-
-+static int mt7986_uart1_rx_tx_pins[] = { 42, 43, };
-+static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, };
-+
-+static int mt7986_uart1_cts_rts_pins[] = { 44, 45, };
-+static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, };
-+
- static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
- static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
-
-@@ -749,6 +761,8 @@ static const struct group_desc mt7986_gr
- PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
- PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
- PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
-+ PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx),
-+ PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts),
- PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
- PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
- PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
-@@ -760,8 +774,10 @@ static const struct group_desc mt7986_gr
- PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
- PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
- PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
-- PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
-- PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
-+ PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx),
-+ PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts),
-+ PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx),
-+ PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts),
- PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
- PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
- PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
-@@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] =
- static const char *mt7986_spi_groups[] = {
- "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
- static const char *mt7986_uart_groups[] = {
-- "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts",
-+ "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts",
-+ "uart1_2_rx_tx", "uart1_2_cts_rts",
-+ "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts",
- "uart2_0", "uart2_1", "uart0", "uart1", "uart2",
- };
- static const char *mt7986_wdt_groups[] = { "watchdog", };
+++ /dev/null
-From 822d774abbcc66b811e28c68b59b40b964ba5b46 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 6 Nov 2022 09:01:13 +0100
-Subject: [PATCH 2/2] pinctrl: mediatek: add pull_type attribute for mediatek
- MT7986 SoC
-
-Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
-add SoC specify 'pull_type' attribute for bias configuration.
-
-This patch add pull_type attribute to pinctrl-mt7986.c, and make
-bias_set_combo and bias_get_combo available to mediatek MT7986 SoC.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++
- 1 file changed, 56 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-@@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc m
- PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
- };
-
-+static const unsigned int mt7986_pull_type[] = {
-+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
-+ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
-+ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
-+ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
-+ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
-+ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
-+ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
-+ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
-+ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
-+ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
-+ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
-+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
-+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
-+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
-+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
-+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
-+ MTK_PULL_PU_PD_TYPE,/*100*/
-+};
-+
- static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
- [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
- [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
-@@ -868,6 +922,7 @@ static struct mtk_pin_soc mt7986a_data =
- .ies_present = false,
- .base_names = mt7986_pinctrl_register_base_names,
- .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-+ .pull_type = mt7986_pull_type,
- .bias_set_combo = mtk_pinconf_bias_set_combo,
- .bias_get_combo = mtk_pinconf_bias_get_combo,
- .drive_set = mtk_pinconf_drive_set_rev1,
-@@ -889,6 +944,7 @@ static struct mtk_pin_soc mt7986b_data =
- .ies_present = false,
- .base_names = mt7986_pinctrl_register_base_names,
- .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-+ .pull_type = mt7986_pull_type,
- .bias_set_combo = mtk_pinconf_bias_set_combo,
- .bias_get_combo = mtk_pinconf_bias_get_combo,
- .drive_set = mtk_pinconf_drive_set_rev1,
+++ /dev/null
-From 6c83b2d94fcca735cf7d8aa7a55a4957eb404a9d Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 26 Jan 2023 00:34:56 +0000
-Subject: [PATCH] pinctrl: add mt7981 pinctrl driver
-
-Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver
-which can also be found the SDK.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/Kconfig | 5 +
- drivers/pinctrl/mediatek/Makefile | 1 +
- drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++++++++++++
- 3 files changed, 1054 insertions(+)
- create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c
-
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -127,6 +127,11 @@ config PINCTRL_MT7622
- default ARM64 && ARCH_MEDIATEK
- select PINCTRL_MTK_MOORE
-
-+config PINCTRL_MT7981
-+ bool "Mediatek MT7981 pin control"
-+ depends on OF
-+ select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT7986
- bool "Mediatek MT7986 pin control"
- depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-
- obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
- obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
- obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
-+obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
- obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
---- /dev/null
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -0,0 +1,1048 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * The MT7981 driver based on Linux generic pinctrl binding.
-+ *
-+ * Copyright (C) 2020 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ */
-+
-+#include "pinctrl-moore.h"
-+
-+#define MT7981_PIN(_number, _name) \
-+ MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
-+
-+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
-+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
-+ _x_bits, 32, 0)
-+
-+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
-+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
-+ _x_bits, 32, 1)
-+
-+static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
-+ PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
-+ PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
-+ PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
-+ PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
-+ PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
-+ PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
-+ PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
-+ PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
-+ PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
-+ PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
-+ PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
-+ PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
-+ PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
-+
-+ PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
-+ PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
-+ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-+ PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
-+ PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
-+
-+ PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
-+
-+ PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
-+ PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
-+ PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
-+ PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
-+ PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
-+ PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
-+ PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
-+ PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
-+ PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
-+ PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
-+ PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
-+
-+ PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
-+ PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
-+ PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
-+ PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
-+ PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
-+ PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
-+
-+ PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
-+ PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
-+
-+ PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
-+ PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
-+
-+ PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
-+ PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
-+ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
-+ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
-+
-+ PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
-+ PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
-+ PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
-+ PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
-+ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-+ PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
-+ PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
-+ PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
-+ PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
-+ PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
-+
-+ PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
-+ PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
-+ PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
-+ PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
-+ PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
-+ PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
-+ PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
-+ PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
-+ PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
-+ PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
-+ PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
-+ PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
-+ PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
-+ PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
-+ PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
-+ PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
-+
-+ PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
-+ PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
-+ PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
-+ PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
-+ PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
-+
-+ PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
-+
-+ PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
-+ PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
-+ PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
-+ PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
-+ PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
-+ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-+ PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
-+ PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
-+ PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
-+ PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
-+ PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
-+
-+ PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
-+ PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
-+ PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
-+ PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
-+ PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
-+ PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
-+
-+ PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
-+ PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
-+
-+ PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
-+ PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
-+
-+ PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
-+ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
-+ PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
-+ PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
-+
-+ PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
-+ PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
-+ PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
-+ PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
-+ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
-+ PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
-+ PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
-+ PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
-+ PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
-+ PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
-+
-+ PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
-+ PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
-+ PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
-+ PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
-+ PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
-+ PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
-+ PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
-+ PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
-+ PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
-+ PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
-+ PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
-+ PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
-+ PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
-+ PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
-+ PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
-+ PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
-+ PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
-+
-+ PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
-+ PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
-+ PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
-+ PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
-+ PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
-+ PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
-+ PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
-+ PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
-+ PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
-+ PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
-+ PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
-+ PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
-+ PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
-+ PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
-+ PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
-+ PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
-+ PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
-+
-+ PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
-+ PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
-+ PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
-+ PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
-+ PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
-+ PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
-+ PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
-+ PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
-+ PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
-+
-+ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
-+
-+ PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
-+ PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
-+ PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
-+ PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
-+ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
-+ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
-+
-+ PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
-+ PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
-+ PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
-+ PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
-+ PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
-+
-+ PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
-+
-+ PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
-+ PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
-+ PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
-+ PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
-+ PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
-+ PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
-+ PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
-+ PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
-+ PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
-+ PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
-+ PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
-+
-+ PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
-+ PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
-+ PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
-+ PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
-+ PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
-+ PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
-+
-+ PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
-+ PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
-+
-+ PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
-+ PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
-+
-+ PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
-+ PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
-+ PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
-+ PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
-+
-+ PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
-+ PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
-+ PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
-+ PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
-+ PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
-+ PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
-+ PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
-+ PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
-+ PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
-+ PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
-+
-+ PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
-+ PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
-+ PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
-+ PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
-+ PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
-+ PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
-+ PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
-+ PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
-+ PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
-+ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
-+ PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
-+ PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
-+ PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
-+ PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
-+ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
-+ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
-+
-+ PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
-+ PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
-+ PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
-+ PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
-+ PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
-+
-+ PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
-+
-+ PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
-+ PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
-+ PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
-+ PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
-+ PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
-+ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
-+ PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
-+ PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
-+ PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
-+ PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
-+ PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
-+
-+ PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
-+ PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
-+ PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
-+ PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
-+ PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
-+ PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
-+
-+ PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
-+ PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
-+
-+ PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
-+ PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
-+
-+ PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
-+ PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
-+ PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
-+ PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
-+ PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
-+ PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
-+ PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
-+ PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
-+ PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
-+ PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
-+ PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
-+ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
-+ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
-+
-+ PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
-+ PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
-+ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
-+ PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
-+ PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
-+
-+ PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
-+
-+ PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
-+ PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
-+ PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
-+ PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
-+ PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
-+ PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
-+ PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
-+ PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
-+ PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
-+ PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
-+ PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
-+
-+ PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
-+ PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
-+ PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
-+ PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
-+ PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
-+ PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
-+
-+ PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
-+ PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
-+
-+ PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
-+ PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
-+
-+ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
-+ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
-+ PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
-+ PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
-+};
-+
-+static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
-+ PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
-+ PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
-+ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
-+ PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
-+ PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
-+ PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
-+ PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
-+ PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
-+ PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
-+
-+ PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
-+ PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
-+ PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
-+ PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
-+ PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
-+
-+ PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
-+
-+ PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
-+ PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
-+ PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
-+ PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
-+ PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
-+ PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
-+ PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
-+ PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
-+ PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
-+ PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
-+ PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
-+
-+ PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
-+ PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
-+ PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
-+ PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
-+ PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
-+ PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
-+
-+ PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
-+ PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
-+
-+ PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
-+ PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
-+
-+ PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
-+ PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
-+ PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
-+ PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
-+};
-+
-+static const unsigned int mt7981_pull_type[] = {
-+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
-+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
-+ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
-+ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
-+ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
-+ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
-+ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
-+ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
-+ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
-+ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
-+ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
-+ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
-+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
-+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
-+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
-+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
-+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
-+ MTK_PULL_PU_PD_TYPE,/*100*/
-+};
-+
-+static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
-+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
-+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
-+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
-+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
-+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
-+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
-+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
-+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
-+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
-+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
-+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
-+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
-+};
-+
-+static const struct mtk_pin_desc mt7981_pins[] = {
-+ MT7981_PIN(0, "GPIO_WPS"),
-+ MT7981_PIN(1, "GPIO_RESET"),
-+ MT7981_PIN(2, "SYS_WATCHDOG"),
-+ MT7981_PIN(3, "PCIE_PERESET_N"),
-+ MT7981_PIN(4, "JTAG_JTDO"),
-+ MT7981_PIN(5, "JTAG_JTDI"),
-+ MT7981_PIN(6, "JTAG_JTMS"),
-+ MT7981_PIN(7, "JTAG_JTCLK"),
-+ MT7981_PIN(8, "JTAG_JTRST_N"),
-+ MT7981_PIN(9, "WO_JTAG_JTDO"),
-+ MT7981_PIN(10, "WO_JTAG_JTDI"),
-+ MT7981_PIN(11, "WO_JTAG_JTMS"),
-+ MT7981_PIN(12, "WO_JTAG_JTCLK"),
-+ MT7981_PIN(13, "WO_JTAG_JTRST_N"),
-+ MT7981_PIN(14, "USB_VBUS"),
-+ MT7981_PIN(15, "PWM0"),
-+ MT7981_PIN(16, "SPI0_CLK"),
-+ MT7981_PIN(17, "SPI0_MOSI"),
-+ MT7981_PIN(18, "SPI0_MISO"),
-+ MT7981_PIN(19, "SPI0_CS"),
-+ MT7981_PIN(20, "SPI0_HOLD"),
-+ MT7981_PIN(21, "SPI0_WP"),
-+ MT7981_PIN(22, "SPI1_CLK"),
-+ MT7981_PIN(23, "SPI1_MOSI"),
-+ MT7981_PIN(24, "SPI1_MISO"),
-+ MT7981_PIN(25, "SPI1_CS"),
-+ MT7981_PIN(26, "SPI2_CLK"),
-+ MT7981_PIN(27, "SPI2_MOSI"),
-+ MT7981_PIN(28, "SPI2_MISO"),
-+ MT7981_PIN(29, "SPI2_CS"),
-+ MT7981_PIN(30, "SPI2_HOLD"),
-+ MT7981_PIN(31, "SPI2_WP"),
-+ MT7981_PIN(32, "UART0_RXD"),
-+ MT7981_PIN(33, "UART0_TXD"),
-+ MT7981_PIN(34, "PCIE_CLK_REQ"),
-+ MT7981_PIN(35, "PCIE_WAKE_N"),
-+ MT7981_PIN(36, "SMI_MDC"),
-+ MT7981_PIN(37, "SMI_MDIO"),
-+ MT7981_PIN(38, "GBE_INT"),
-+ MT7981_PIN(39, "GBE_RESET"),
-+ MT7981_PIN(40, "WF_DIG_RESETB"),
-+ MT7981_PIN(41, "WF_CBA_RESETB"),
-+ MT7981_PIN(42, "WF_XO_REQ"),
-+ MT7981_PIN(43, "WF_TOP_CLK"),
-+ MT7981_PIN(44, "WF_TOP_DATA"),
-+ MT7981_PIN(45, "WF_HB1"),
-+ MT7981_PIN(46, "WF_HB2"),
-+ MT7981_PIN(47, "WF_HB3"),
-+ MT7981_PIN(48, "WF_HB4"),
-+ MT7981_PIN(49, "WF_HB0"),
-+ MT7981_PIN(50, "WF_HB0_B"),
-+ MT7981_PIN(51, "WF_HB5"),
-+ MT7981_PIN(52, "WF_HB6"),
-+ MT7981_PIN(53, "WF_HB7"),
-+ MT7981_PIN(54, "WF_HB8"),
-+ MT7981_PIN(55, "WF_HB9"),
-+ MT7981_PIN(56, "WF_HB10"),
-+};
-+
-+/* List all groups consisting of these pins dedicated to the enablement of
-+ * certain hardware block and the corresponding mode for all of the pins.
-+ * The hardware probably has multiple combinations of these pinouts.
-+ */
-+
-+/* WA_AICE */
-+static int mt7981_wa_aice1_pins[] = { 0, 1, };
-+static int mt7981_wa_aice1_funcs[] = { 2, 2, };
-+
-+static int mt7981_wa_aice2_pins[] = { 0, 1, };
-+static int mt7981_wa_aice2_funcs[] = { 3, 3, };
-+
-+static int mt7981_wa_aice3_pins[] = { 28, 29, };
-+static int mt7981_wa_aice3_funcs[] = { 3, 3, };
-+
-+static int mt7981_wm_aice1_pins[] = { 9, 10, };
-+static int mt7981_wm_aice1_funcs[] = { 2, 2, };
-+
-+static int mt7981_wm_aice2_pins[] = { 30, 31, };
-+static int mt7981_wm_aice2_funcs[] = { 5, 5, };
-+
-+/* WM_UART */
-+static int mt7981_wm_uart_0_pins[] = { 0, 1, };
-+static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
-+
-+static int mt7981_wm_uart_1_pins[] = { 20, 21, };
-+static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
-+
-+static int mt7981_wm_uart_2_pins[] = { 30, 31, };
-+static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
-+
-+/* DFD */
-+static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
-+static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
-+
-+/* SYS_WATCHDOG */
-+static int mt7981_watchdog_pins[] = { 2, };
-+static int mt7981_watchdog_funcs[] = { 1, };
-+
-+static int mt7981_watchdog1_pins[] = { 13, };
-+static int mt7981_watchdog1_funcs[] = { 5, };
-+
-+/* PCIE_PERESET_N */
-+static int mt7981_pcie_pereset_pins[] = { 3, };
-+static int mt7981_pcie_pereset_funcs[] = { 1, };
-+
-+/* JTAG */
-+static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
-+static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
-+
-+/* WM_JTAG */
-+static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
-+static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
-+
-+static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
-+static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-+
-+/* WO0_JTAG */
-+static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
-+static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
-+
-+static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
-+static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
-+
-+/* UART2 */
-+static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
-+static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
-+
-+/* GBE_LED0 */
-+static int mt7981_gbe_led0_pins[] = { 8, };
-+static int mt7981_gbe_led0_funcs[] = { 3, };
-+
-+/* PTA_EXT */
-+static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
-+static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
-+
-+static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
-+static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
-+
-+/* PWM2 */
-+static int mt7981_pwm2_pins[] = { 7, };
-+static int mt7981_pwm2_funcs[] = { 4, };
-+
-+/* NET_WO0_UART_TXD */
-+static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
-+static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
-+
-+static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
-+static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
-+
-+static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
-+static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
-+
-+/* SPI1 */
-+static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
-+static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
-+
-+/* I2C */
-+static int mt7981_i2c0_0_pins[] = { 6, 7, };
-+static int mt7981_i2c0_0_funcs[] = { 6, 6, };
-+
-+static int mt7981_i2c0_1_pins[] = { 30, 31, };
-+static int mt7981_i2c0_1_funcs[] = { 4, 4, };
-+
-+static int mt7981_i2c0_2_pins[] = { 36, 37, };
-+static int mt7981_i2c0_2_funcs[] = { 2, 2, };
-+
-+static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
-+static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
-+
-+static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
-+static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
-+
-+static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
-+static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
-+
-+static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
-+static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
-+
-+/* DFD_NTRST */
-+static int mt7981_dfd_ntrst_pins[] = { 8, };
-+static int mt7981_dfd_ntrst_funcs[] = { 6, };
-+
-+/* PWM0 */
-+static int mt7981_pwm0_0_pins[] = { 13, };
-+static int mt7981_pwm0_0_funcs[] = { 2, };
-+
-+static int mt7981_pwm0_1_pins[] = { 15, };
-+static int mt7981_pwm0_1_funcs[] = { 1, };
-+
-+/* PWM1 */
-+static int mt7981_pwm1_0_pins[] = { 14, };
-+static int mt7981_pwm1_0_funcs[] = { 2, };
-+
-+static int mt7981_pwm1_1_pins[] = { 15, };
-+static int mt7981_pwm1_1_funcs[] = { 3, };
-+
-+/* GBE_LED1 */
-+static int mt7981_gbe_led1_pins[] = { 13, };
-+static int mt7981_gbe_led1_funcs[] = { 3, };
-+
-+/* PCM */
-+static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
-+static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
-+
-+/* UDI */
-+static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
-+static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
-+
-+/* DRV_VBUS */
-+static int mt7981_drv_vbus_pins[] = { 14, };
-+static int mt7981_drv_vbus_funcs[] = { 1, };
-+
-+/* EMMC */
-+static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-+static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-+
-+/* SNFI */
-+static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
-+static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
-+
-+/* SPI0 */
-+static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
-+static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
-+
-+/* SPI0 */
-+static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
-+static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
-+
-+/* SPI1 */
-+static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
-+static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
-+
-+/* SPI2 */
-+static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
-+static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
-+
-+/* SPI2 */
-+static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
-+static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
-+
-+/* UART1 */
-+static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
-+static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
-+
-+static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
-+static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
-+
-+/* UART2 */
-+static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
-+static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-+
-+/* UART0 */
-+static int mt7981_uart0_pins[] = { 32, 33, };
-+static int mt7981_uart0_funcs[] = { 1, 1, };
-+
-+/* PCIE_CLK_REQ */
-+static int mt7981_pcie_clk_pins[] = { 34, };
-+static int mt7981_pcie_clk_funcs[] = { 2, };
-+
-+/* PCIE_WAKE_N */
-+static int mt7981_pcie_wake_pins[] = { 35, };
-+static int mt7981_pcie_wake_funcs[] = { 2, };
-+
-+/* MDC_MDIO */
-+static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
-+static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
-+
-+static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
-+static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
-+
-+/* WF0_MODE1 */
-+static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
-+static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
-+
-+/* WF0_MODE3 */
-+static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
-+static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
-+
-+/* WF2G_LED */
-+static int mt7981_wf2g_led0_pins[] = { 30, };
-+static int mt7981_wf2g_led0_funcs[] = { 2, };
-+
-+static int mt7981_wf2g_led1_pins[] = { 34, };
-+static int mt7981_wf2g_led1_funcs[] = { 1, };
-+
-+/* WF5G_LED */
-+static int mt7981_wf5g_led0_pins[] = { 31, };
-+static int mt7981_wf5g_led0_funcs[] = { 2, };
-+
-+static int mt7981_wf5g_led1_pins[] = { 35, };
-+static int mt7981_wf5g_led1_funcs[] = { 1, };
-+
-+/* MT7531_INT */
-+static int mt7981_mt7531_int_pins[] = { 38, };
-+static int mt7981_mt7531_int_funcs[] = { 1, };
-+
-+/* ANT_SEL */
-+static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
-+static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
-+
-+static const struct group_desc mt7981_groups[] = {
-+ /* @GPIO(0,1): WA_AICE(2) */
-+ PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
-+ /* @GPIO(0,1): WA_AICE(3) */
-+ PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
-+ /* @GPIO(0,1): WM_UART(5) */
-+ PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
-+ /* @GPIO(0,1,4,5): DFD(6) */
-+ PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
-+ /* @GPIO(2): SYS_WATCHDOG(1) */
-+ PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
-+ /* @GPIO(3): PCIE_PERESET_N(1) */
-+ PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
-+ /* @GPIO(4,8) JTAG(1) */
-+ PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
-+ /* @GPIO(4,8) WM_JTAG(2) */
-+ PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
-+ /* @GPIO(9,13) WO0_JTAG(1) */
-+ PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
-+ /* @GPIO(4,7) WM_JTAG(3) */
-+ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
-+ /* @GPIO(8) GBE_LED0(3) */
-+ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
-+ /* @GPIO(4,6) PTA_EXT(4) */
-+ PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
-+ /* @GPIO(7) PWM2(4) */
-+ PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
-+ /* @GPIO(8) NET_WO0_UART_TXD(4) */
-+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
-+ /* @GPIO(4,7) SPI1(5) */
-+ PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
-+ /* @GPIO(6,7) I2C(5) */
-+ PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
-+ /* @GPIO(0,1,4,5): DFD_NTRST(6) */
-+ PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
-+ /* @GPIO(9,10): WM_AICE(2) */
-+ PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
-+ /* @GPIO(13): PWM0(2) */
-+ PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
-+ /* @GPIO(15): PWM0(1) */
-+ PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
-+ /* @GPIO(14): PWM1(2) */
-+ PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
-+ /* @GPIO(15): PWM1(3) */
-+ PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
-+ /* @GPIO(14) NET_WO0_UART_TXD(3) */
-+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
-+ /* @GPIO(15) NET_WO0_UART_TXD(4) */
-+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
-+ /* @GPIO(13) GBE_LED0(3) */
-+ PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
-+ /* @GPIO(9,13) PCM(4) */
-+ PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
-+ /* @GPIO(13): SYS_WATCHDOG1(5) */
-+ PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
-+ /* @GPIO(9,13) UDI(4) */
-+ PINCTRL_PIN_GROUP("udi", mt7981_udi),
-+ /* @GPIO(14) DRV_VBUS(1) */
-+ PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
-+ /* @GPIO(15,25): EMMC(2) */
-+ PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
-+ /* @GPIO(16,21): SNFI(3) */
-+ PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
-+ /* @GPIO(16,19): SPI0(1) */
-+ PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
-+ /* @GPIO(20,21): SPI0(1) */
-+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
-+ /* @GPIO(22,25) SPI1(1) */
-+ PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
-+ /* @GPIO(26,29): SPI2(1) */
-+ PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
-+ /* @GPIO(30,31): SPI0(1) */
-+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
-+ /* @GPIO(16,19): UART1(4) */
-+ PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
-+ /* @GPIO(26,29): UART1(2) */
-+ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
-+ /* @GPIO(22,25): UART1(3) */
-+ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
-+ /* @GPIO(22,24) PTA_EXT(4) */
-+ PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
-+ /* @GPIO(20,21): WM_UART(4) */
-+ PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
-+ /* @GPIO(30,31): WM_UART(3) */
-+ PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
-+ /* @GPIO(20,24) WM_JTAG(5) */
-+ PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
-+ /* @GPIO(25,29) WO0_JTAG(5) */
-+ PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
-+ /* @GPIO(28,29): WA_AICE(3) */
-+ PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
-+ /* @GPIO(30,31): WM_AICE(5) */
-+ PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
-+ /* @GPIO(30,31): I2C(4) */
-+ PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
-+ /* @GPIO(30,31): I2C(6) */
-+ PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
-+ /* @GPIO(32,33): I2C(1) */
-+ PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
-+ /* @GPIO(32,33): I2C(2) */
-+ PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
-+ /* @GPIO(32,33): I2C(3) */
-+ PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
-+ /* @GPIO(32,33): I2C(5) */
-+ PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
-+ /* @GPIO(34): PCIE_CLK_REQ(2) */
-+ PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
-+ /* @GPIO(35): PCIE_WAKE_N(2) */
-+ PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
-+ /* @GPIO(36,37): I2C(2) */
-+ PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
-+ /* @GPIO(36,37): MDC_MDIO(1) */
-+ PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
-+ /* @GPIO(36,37): MDC_MDIO(3) */
-+ PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
-+ /* @GPIO(69,85): WF0_MODE1(1) */
-+ PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
-+ /* @GPIO(74,80): WF0_MODE3(3) */
-+ PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
-+ /* @GPIO(30): WF2G_LED(2) */
-+ PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
-+ /* @GPIO(34): WF2G_LED(1) */
-+ PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
-+ /* @GPIO(31): WF5G_LED(2) */
-+ PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
-+ /* @GPIO(35): WF5G_LED(1) */
-+ PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
-+ /* @GPIO(38): MT7531_INT(1) */
-+ PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
-+ /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
-+ PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
-+};
-+
-+/* Joint those groups owning the same capability in user point of view which
-+ * allows that people tend to use through the device tree.
-+ */
-+static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
-+ "wa_aice3", "wm_aice1_2", };
-+static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
-+ "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
-+ "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
-+static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
-+static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
-+static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
-+static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
-+ "wo0_jtag_1", "wm_jtag_1", };
-+static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
-+ "wf2g_led1", "wf5g_led0", "wf5g_led1", };
-+static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
-+static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
-+ "pwm1_0", "pwm1_1", };
-+static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
-+ "spi2_wp_hold", };
-+static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
-+ "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
-+static const char *mt7981_pcm_groups[] = { "pcm", };
-+static const char *mt7981_udi_groups[] = { "udi", };
-+static const char *mt7981_usb_groups[] = { "drv_vbus", };
-+static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
-+static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
-+ "wf0_mode1", "wf0_mode3", "mt7531_int", };
-+static const char *mt7981_ant_groups[] = { "ant_sel", };
-+
-+static const struct function_desc mt7981_functions[] = {
-+ {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
-+ {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
-+ {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
-+ {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
-+ {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
-+ {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
-+ {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
-+ {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
-+ {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
-+ {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
-+ {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
-+ {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
-+ {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
-+ {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
-+ {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
-+ {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
-+ {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
-+};
-+
-+static const struct mtk_eint_hw mt7981_eint_hw = {
-+ .port_mask = 7,
-+ .ports = 7,
-+ .ap_num = ARRAY_SIZE(mt7981_pins),
-+ .db_cnt = 16,
-+};
-+
-+static const char * const mt7981_pinctrl_register_base_names[] = {
-+ "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
-+ "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
-+};
-+
-+static struct mtk_pin_soc mt7981_data = {
-+ .reg_cal = mt7981_reg_cals,
-+ .pins = mt7981_pins,
-+ .npins = ARRAY_SIZE(mt7981_pins),
-+ .grps = mt7981_groups,
-+ .ngrps = ARRAY_SIZE(mt7981_groups),
-+ .funcs = mt7981_functions,
-+ .nfuncs = ARRAY_SIZE(mt7981_functions),
-+ .eint_hw = &mt7981_eint_hw,
-+ .gpio_m = 0,
-+ .ies_present = false,
-+ .base_names = mt7981_pinctrl_register_base_names,
-+ .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
-+ .pull_type = mt7981_pull_type,
-+ .bias_set_combo = mtk_pinconf_bias_set_combo,
-+ .bias_get_combo = mtk_pinconf_bias_get_combo,
-+ .drive_set = mtk_pinconf_drive_set_rev1,
-+ .drive_get = mtk_pinconf_drive_get_rev1,
-+ .adv_pull_get = mtk_pinconf_adv_pull_get,
-+ .adv_pull_set = mtk_pinconf_adv_pull_set,
-+};
-+
-+static const struct of_device_id mt7981_pinctrl_of_match[] = {
-+ { .compatible = "mediatek,mt7981-pinctrl", },
-+ {}
-+};
-+
-+static int mt7981_pinctrl_probe(struct platform_device *pdev)
-+{
-+ return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
-+}
-+
-+static struct platform_driver mt7981_pinctrl_driver = {
-+ .driver = {
-+ .name = "mt7981-pinctrl",
-+ .of_match_table = mt7981_pinctrl_of_match,
-+ },
-+ .probe = mt7981_pinctrl_probe,
-+};
-+
-+static int __init mt7981_pinctrl_init(void)
-+{
-+ return platform_driver_register(&mt7981_pinctrl_driver);
-+}
-+arch_initcall(mt7981_pinctrl_init);
+++ /dev/null
-From c0ad453e94e5c404efbcf668648d07eaa1a71ed7 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Sat, 18 Feb 2023 09:51:06 +0300
-Subject: [PATCH] pinctrl: mediatek: add missing options to PINCTRL_MT7981
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There are options missing from PINCTRL_MT7981 whilst being on every other
-pin controller. Add them.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Acked-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/20230218065108.8958-1-arinc.unal@arinc9.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/Kconfig | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -130,6 +130,8 @@ config PINCTRL_MT7622
- config PINCTRL_MT7981
- bool "Mediatek MT7981 pin control"
- depends on OF
-+ depends on ARM64 || COMPILE_TEST
-+ default ARM64 && ARCH_MEDIATEK
- select PINCTRL_MTK_MOORE
-
- config PINCTRL_MT7986
+++ /dev/null
-From 8f6f16fe1553ce63edfb98a39ef9d4754a0c39bf Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 18 Aug 2023 04:02:35 +0100
-Subject: [PATCH] pinctrl: mediatek: fix pull_type data for MT7981
-
-MediaTek has released pull_type data for MT7981 in their SDK.
-Use it and set functions to configure pin bias.
-
-Fixes: 6c83b2d94fcc ("pinctrl: add mt7981 pinctrl driver")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/7bcc8ead25dbfabc7f5a85d066224a926fbb4941.1692327317.git.daniel@makrotopia.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7981.c | 44 +++++++----------------
- 1 file changed, 13 insertions(+), 31 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -457,37 +457,15 @@ static const unsigned int mt7981_pull_ty
- MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
- MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
- MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
-- MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
-- MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
-- MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
-- MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
-- MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
-- MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
-- MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
-- MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
-- MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
-- MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
-- MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
-- MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
-- MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
-- MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
-- MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
-- MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
-- MTK_PULL_PU_PD_TYPE,/*100*/
-+ MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/
-+ MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/
-+ MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/
-+ MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/
-+ MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/
-+ MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/
-+ MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/
-+ MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/
-+ MTK_PULL_PU_PD_TYPE,/*56*/
- };
-
- static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
-@@ -1014,6 +992,10 @@ static struct mtk_pin_soc mt7981_data =
- .ies_present = false,
- .base_names = mt7981_pinctrl_register_base_names,
- .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
-+ .bias_disable_set = mtk_pinconf_bias_disable_set,
-+ .bias_disable_get = mtk_pinconf_bias_disable_get,
-+ .bias_set = mtk_pinconf_bias_set,
-+ .bias_get = mtk_pinconf_bias_get,
- .pull_type = mt7981_pull_type,
- .bias_set_combo = mtk_pinconf_bias_set_combo,
- .bias_get_combo = mtk_pinconf_bias_get_combo,
+++ /dev/null
-From 11db447f257231e08065989100311df57b7f1f1c Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sat, 26 Aug 2023 21:06:14 +0100
-Subject: [PATCH] pinctrl: mediatek: mt7981: add additional uart groups
-
-Add uart2_0_tx_rx (pin 4, 5) and uart1_2 (pins 9, 10) groups.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 +++++++++++++---
- 1 file changed, 13 insertions(+), 3 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = {
- static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
- static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
-
-+static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
-+static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
-+
- /* GBE_LED0 */
- static int mt7981_gbe_led0_pins[] = { 8, };
- static int mt7981_gbe_led0_funcs[] = { 3, };
-@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4,
- static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
- static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
-
-+static int mt7981_uart1_2_pins[] = { 9, 10, };
-+static int mt7981_uart1_2_funcs[] = { 2, 2, };
-+
- /* UART2 */
- static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
- static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-@@ -805,6 +811,8 @@ static const struct group_desc mt7981_gr
- PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
- /* @GPIO(4,7) WM_JTAG(3) */
- PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
-+ /* @GPIO(4,5) WM_JTAG(4) */
-+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
- /* @GPIO(8) GBE_LED0(3) */
- PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
- /* @GPIO(4,6) PTA_EXT(4) */
-@@ -861,6 +869,8 @@ static const struct group_desc mt7981_gr
- PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
- /* @GPIO(26,29): UART1(2) */
- PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
-+ /* @GPIO(9,10): UART1(2) */
-+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
- /* @GPIO(22,25): UART1(3) */
- PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
- /* @GPIO(22,24) PTA_EXT(4) */
-@@ -922,9 +932,9 @@ static const struct group_desc mt7981_gr
- */
- static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
- "wa_aice3", "wm_aice1_2", };
--static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
-- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
-- "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
-+static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
-+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
-+ "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
- static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
- static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
- static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
+++ /dev/null
-From 0d8387fba9f151220e48dc3dcdc2335539708f13 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 18 Aug 2023 04:03:26 +0100
-Subject: [PATCH] pinctrl: mediatek: assign functions to configure pin bias on
- MT7986
-
-Assign bias_disable_get/set and bias_get/set functions to allow
-configuring pin bias on MT7986.
-
-Fixes: 2c58d8dc9cd0 ("pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/47f72372354312a839b9337e09476aadcc206e8b.1692327317.git.daniel@makrotopia.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
-@@ -922,6 +922,10 @@ static struct mtk_pin_soc mt7986a_data =
- .ies_present = false,
- .base_names = mt7986_pinctrl_register_base_names,
- .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-+ .bias_disable_set = mtk_pinconf_bias_disable_set,
-+ .bias_disable_get = mtk_pinconf_bias_disable_get,
-+ .bias_set = mtk_pinconf_bias_set,
-+ .bias_get = mtk_pinconf_bias_get,
- .pull_type = mt7986_pull_type,
- .bias_set_combo = mtk_pinconf_bias_set_combo,
- .bias_get_combo = mtk_pinconf_bias_get_combo,
-@@ -944,6 +948,10 @@ static struct mtk_pin_soc mt7986b_data =
- .ies_present = false,
- .base_names = mt7986_pinctrl_register_base_names,
- .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
-+ .bias_disable_set = mtk_pinconf_bias_disable_set,
-+ .bias_disable_get = mtk_pinconf_bias_disable_get,
-+ .bias_set = mtk_pinconf_bias_set,
-+ .bias_get = mtk_pinconf_bias_get,
- .pull_type = mt7986_pull_type,
- .bias_set_combo = mtk_pinconf_bias_set_combo,
- .bias_get_combo = mtk_pinconf_bias_get_combo,
+++ /dev/null
-From fe5c8d03f3de89ae058e365b783f8c1314f47490 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:33 +0100
-Subject: [PATCH 01/15] clk: mediatek: clk-gate: Propagate struct device with
- mtk_clk_register_gates()
-
-Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device")
-introduces a helper function for the sole purpose of propagating a
-struct device pointer to the clk API when registering the mtk-gate
-clocks to take advantage of Runtime PM when/where needed and where
-a power domain is defined in devicetree.
-
-Function mtk_clk_register_gates() then becomes a wrapper around the
-new mtk_clk_register_gates_with_dev() function that will simply pass
-NULL as struct device: this is essential when registering drivers
-with CLK_OF_DECLARE instead of as a platform device, as there will
-be no struct device to pass... but we can as well simply have only
-one function that always takes such pointer as a param and pass NULL
-when unavoidable.
-
-This commit removes the mtk_clk_register_gates() wrapper and renames
-mtk_clk_register_gates_with_dev() to the former and all of the calls
-to either of the two functions were fixed in all drivers in order to
-reflect this change; also, to improve consistency with other kernel
-functions, the pointer to struct device was moved as the first param.
-
-Since a lot of MediaTek clock drivers are actually registering as a
-platform device, but were still registering the mtk-gate clocks
-without passing any struct device to the clock framework, they've
-been changed to pass a valid one now, as to make all those platforms
-able to use runtime power management where available.
-
-While at it, some much needed indentation changes were also done.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-
-[daniel@makrotopia.org: dropped parts not relevant for OpenWrt]
----
- drivers/clk/mediatek/clk-gate.c | 23 +++++++---------------
- drivers/clk/mediatek/clk-gate.h | 7 +------
- drivers/clk/mediatek/clk-mt2701-aud.c | 4 ++--
- drivers/clk/mediatek/clk-mt2701-eth.c | 4 ++--
- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +-
- drivers/clk/mediatek/clk-mt2701-hif.c | 4 ++--
- drivers/clk/mediatek/clk-mt2701-mm.c | 4 ++--
- drivers/clk/mediatek/clk-mt2701.c | 12 +++++------
- drivers/clk/mediatek/clk-mt2712-mm.c | 4 ++--
- drivers/clk/mediatek/clk-mt2712.c | 12 +++++------
- drivers/clk/mediatek/clk-mt7622-aud.c | 4 ++--
- drivers/clk/mediatek/clk-mt7622-eth.c | 8 ++++----
- drivers/clk/mediatek/clk-mt7622-hif.c | 8 ++++----
- drivers/clk/mediatek/clk-mt7622.c | 14 ++++++-------
- drivers/clk/mediatek/clk-mt7629-eth.c | 7 ++++---
- drivers/clk/mediatek/clk-mt7629-hif.c | 8 ++++----
- drivers/clk/mediatek/clk-mt7629.c | 10 +++++-----
- drivers/clk/mediatek/clk-mt7986-eth.c | 10 +++++-----
- drivers/clk/mediatek/clk-mt7986-infracfg.c | 4 ++--
- 19 files changed, 68 insertions(+), 81 deletions(-)
-
---- a/drivers/clk/mediatek/clk-gate.c
-+++ b/drivers/clk/mediatek/clk-gate.c
-@@ -152,12 +152,12 @@ const struct clk_ops mtk_clk_gate_ops_no
- };
- EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
-
--static struct clk_hw *mtk_clk_register_gate(const char *name,
-+static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name,
- const char *parent_name,
- struct regmap *regmap, int set_ofs,
- int clr_ofs, int sta_ofs, u8 bit,
- const struct clk_ops *ops,
-- unsigned long flags, struct device *dev)
-+ unsigned long flags)
- {
- struct mtk_clk_gate *cg;
- int ret;
-@@ -202,10 +202,9 @@ static void mtk_clk_unregister_gate(stru
- kfree(cg);
- }
-
--int mtk_clk_register_gates_with_dev(struct device_node *node,
-- const struct mtk_gate *clks, int num,
-- struct clk_hw_onecell_data *clk_data,
-- struct device *dev)
-+int mtk_clk_register_gates(struct device *dev, struct device_node *node,
-+ const struct mtk_gate *clks, int num,
-+ struct clk_hw_onecell_data *clk_data)
- {
- int i;
- struct clk_hw *hw;
-@@ -229,13 +228,13 @@ int mtk_clk_register_gates_with_dev(stru
- continue;
- }
-
-- hw = mtk_clk_register_gate(gate->name, gate->parent_name,
-+ hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name,
- regmap,
- gate->regs->set_ofs,
- gate->regs->clr_ofs,
- gate->regs->sta_ofs,
- gate->shift, gate->ops,
-- gate->flags, dev);
-+ gate->flags);
-
- if (IS_ERR(hw)) {
- pr_err("Failed to register clk %s: %pe\n", gate->name,
-@@ -261,14 +260,6 @@ err:
-
- return PTR_ERR(hw);
- }
--EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev);
--
--int mtk_clk_register_gates(struct device_node *node,
-- const struct mtk_gate *clks, int num,
-- struct clk_hw_onecell_data *clk_data)
--{
-- return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
--}
- EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
-
- void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
---- a/drivers/clk/mediatek/clk-gate.h
-+++ b/drivers/clk/mediatek/clk-gate.h
-@@ -50,15 +50,10 @@ struct mtk_gate {
- #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \
- GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
-
--int mtk_clk_register_gates(struct device_node *node,
-+int mtk_clk_register_gates(struct device *dev, struct device_node *node,
- const struct mtk_gate *clks, int num,
- struct clk_hw_onecell_data *clk_data);
-
--int mtk_clk_register_gates_with_dev(struct device_node *node,
-- const struct mtk_gate *clks, int num,
-- struct clk_hw_onecell_data *clk_data,
-- struct device *dev);
--
- void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
- struct clk_hw_onecell_data *clk_data);
-
---- a/drivers/clk/mediatek/clk-mt2701-aud.c
-+++ b/drivers/clk/mediatek/clk-mt2701-aud.c
-@@ -127,8 +127,8 @@ static int clk_mt2701_aud_probe(struct p
-
- clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
-
-- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, audio_clks,
-+ ARRAY_SIZE(audio_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r) {
---- a/drivers/clk/mediatek/clk-mt2701-eth.c
-+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
-@@ -51,8 +51,8 @@ static int clk_mt2701_eth_probe(struct p
-
- clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
-
-- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, eth_clks,
-+ ARRAY_SIZE(eth_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
---- a/drivers/clk/mediatek/clk-mt2701-g3d.c
-+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
-@@ -45,7 +45,7 @@ static int clk_mt2701_g3dsys_init(struct
-
- clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
-
-- mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
-+ mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
- clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
---- a/drivers/clk/mediatek/clk-mt2701-hif.c
-+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
-@@ -48,8 +48,8 @@ static int clk_mt2701_hif_probe(struct p
-
- clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
-
-- mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, hif_clks,
-+ ARRAY_SIZE(hif_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r) {
---- a/drivers/clk/mediatek/clk-mt2701-mm.c
-+++ b/drivers/clk/mediatek/clk-mt2701-mm.c
-@@ -76,8 +76,8 @@ static int clk_mt2701_mm_probe(struct pl
-
- clk_data = mtk_alloc_clk_data(CLK_MM_NR);
-
-- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, mm_clks,
-+ ARRAY_SIZE(mm_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
---- a/drivers/clk/mediatek/clk-mt2701.c
-+++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -685,8 +685,8 @@ static int mtk_topckgen_init(struct plat
- mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
- base, &mt2701_clk_lock, clk_data);
-
-- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, top_clks,
-+ ARRAY_SIZE(top_clks), clk_data);
-
- return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- }
-@@ -789,8 +789,8 @@ static int mtk_infrasys_init(struct plat
- }
- }
-
-- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-- infra_clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
-+ ARRAY_SIZE(infra_clks), infra_clk_data);
- mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
- infra_clk_data);
-
-@@ -902,8 +902,8 @@ static int mtk_pericfg_init(struct platf
- if (!clk_data)
- return -ENOMEM;
-
-- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
-+ ARRAY_SIZE(peri_clks), clk_data);
-
- mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
- &mt2701_clk_lock, clk_data);
---- a/drivers/clk/mediatek/clk-mt2712-mm.c
-+++ b/drivers/clk/mediatek/clk-mt2712-mm.c
-@@ -117,8 +117,8 @@ static int clk_mt2712_mm_probe(struct pl
-
- clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
-
-- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, mm_clks,
-+ ARRAY_SIZE(mm_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-
---- a/drivers/clk/mediatek/clk-mt2712.c
-+++ b/drivers/clk/mediatek/clk-mt2712.c
-@@ -1324,8 +1324,8 @@ static int clk_mt2712_top_probe(struct p
- &mt2712_clk_lock, top_clk_data);
- mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
- &mt2712_clk_lock, top_clk_data);
-- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
-- top_clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, top_clks,
-+ ARRAY_SIZE(top_clks), top_clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
-
-@@ -1344,8 +1344,8 @@ static int clk_mt2712_infra_probe(struct
-
- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
-
-- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
-+ ARRAY_SIZE(infra_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-
-@@ -1366,8 +1366,8 @@ static int clk_mt2712_peri_probe(struct
-
- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
-
-- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
-+ ARRAY_SIZE(peri_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-
---- a/drivers/clk/mediatek/clk-mt7622-aud.c
-+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
-@@ -114,8 +114,8 @@ static int clk_mt7622_audiosys_init(stru
-
- clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
-
-- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, audio_clks,
-+ ARRAY_SIZE(audio_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r) {
---- a/drivers/clk/mediatek/clk-mt7622-eth.c
-+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
-@@ -69,8 +69,8 @@ static int clk_mt7622_ethsys_init(struct
-
- clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
-
-- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, eth_clks,
-+ ARRAY_SIZE(eth_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
-@@ -91,8 +91,8 @@ static int clk_mt7622_sgmiisys_init(stru
-
- clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
-
-- mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
-+ ARRAY_SIZE(sgmii_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
---- a/drivers/clk/mediatek/clk-mt7622-hif.c
-+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
-@@ -80,8 +80,8 @@ static int clk_mt7622_ssusbsys_init(stru
-
- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
-
-- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
-+ ARRAY_SIZE(ssusb_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
-@@ -102,8 +102,8 @@ static int clk_mt7622_pciesys_init(struc
-
- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
-
-- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
-+ ARRAY_SIZE(pcie_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
---- a/drivers/clk/mediatek/clk-mt7622.c
-+++ b/drivers/clk/mediatek/clk-mt7622.c
-@@ -621,8 +621,8 @@ static int mtk_topckgen_init(struct plat
- mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
- base, &mt7622_clk_lock, clk_data);
-
-- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, top_clks,
-+ ARRAY_SIZE(top_clks), clk_data);
-
- return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- }
-@@ -635,8 +635,8 @@ static int mtk_infrasys_init(struct plat
-
- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
-
-- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
-+ ARRAY_SIZE(infra_clks), clk_data);
-
- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
- clk_data);
-@@ -663,7 +663,7 @@ static int mtk_apmixedsys_init(struct pl
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
- clk_data);
-
-- mtk_clk_register_gates(node, apmixed_clks,
-+ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
- ARRAY_SIZE(apmixed_clks), clk_data);
-
- return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-@@ -682,8 +682,8 @@ static int mtk_pericfg_init(struct platf
-
- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
-
-- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
-+ ARRAY_SIZE(peri_clks), clk_data);
-
- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
- &mt7622_clk_lock, clk_data);
---- a/drivers/clk/mediatek/clk-mt7629-eth.c
-+++ b/drivers/clk/mediatek/clk-mt7629-eth.c
-@@ -82,7 +82,8 @@ static int clk_mt7629_ethsys_init(struct
- if (!clk_data)
- return -ENOMEM;
-
-- mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, eth_clks,
-+ CLK_ETH_NR_CLK, clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
-@@ -106,8 +107,8 @@ static int clk_mt7629_sgmiisys_init(stru
- if (!clk_data)
- return -ENOMEM;
-
-- mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
-+ CLK_SGMII_NR_CLK, clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
---- a/drivers/clk/mediatek/clk-mt7629-hif.c
-+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
-@@ -75,8 +75,8 @@ static int clk_mt7629_ssusbsys_init(stru
-
- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
-
-- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
-+ ARRAY_SIZE(ssusb_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
-@@ -97,8 +97,8 @@ static int clk_mt7629_pciesys_init(struc
-
- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
-
-- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
-+ ARRAY_SIZE(pcie_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
---- a/drivers/clk/mediatek/clk-mt7629.c
-+++ b/drivers/clk/mediatek/clk-mt7629.c
-@@ -585,8 +585,8 @@ static int mtk_infrasys_init(struct plat
- if (!clk_data)
- return -ENOMEM;
-
-- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
-+ ARRAY_SIZE(infra_clks), clk_data);
-
- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
- clk_data);
-@@ -610,8 +610,8 @@ static int mtk_pericfg_init(struct platf
- if (!clk_data)
- return -ENOMEM;
-
-- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, peri_clks,
-+ ARRAY_SIZE(peri_clks), clk_data);
-
- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
- &mt7629_clk_lock, clk_data);
-@@ -637,7 +637,7 @@ static int mtk_apmixedsys_init(struct pl
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
- clk_data);
-
-- mtk_clk_register_gates(node, apmixed_clks,
-+ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
- ARRAY_SIZE(apmixed_clks), clk_data);
-
- clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
---- a/drivers/clk/mediatek/clk-mt7986-eth.c
-+++ b/drivers/clk/mediatek/clk-mt7986-eth.c
-@@ -72,8 +72,8 @@ static void __init mtk_sgmiisys_0_init(s
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
-
-- mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
-- clk_data);
-+ mtk_clk_register_gates(NULL, node, sgmii0_clks,
-+ ARRAY_SIZE(sgmii0_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
-@@ -90,8 +90,8 @@ static void __init mtk_sgmiisys_1_init(s
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
-
-- mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
-- clk_data);
-+ mtk_clk_register_gates(NULL, node, sgmii1_clks,
-+ ARRAY_SIZE(sgmii1_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-
-@@ -109,7 +109,7 @@ static void __init mtk_ethsys_init(struc
-
- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
-
-- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-+ mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-
---- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
-+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
-@@ -180,8 +180,8 @@ static int clk_mt7986_infracfg_probe(str
- mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
- mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
- &mt7986_clk_lock, clk_data);
-- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
-- clk_data);
-+ mtk_clk_register_gates(&pdev->dev, node, infra_clks,
-+ ARRAY_SIZE(infra_clks), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r) {
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform
- if (!clk_data)
- return -ENOMEM;
-
-- r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks,
-- clk_data, &pdev->dev);
-+ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
-+ clk_data);
- if (r)
- goto free_data;
-
+++ /dev/null
-From b888303c7d23d7bd0c8667cfc657669e5d153fea Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:34 +0100
-Subject: [PATCH 02/15] clk: mediatek: cpumux: Propagate struct device where
- possible
-
-Take a pointer to a struct device in mtk_clk_register_cpumuxes() and
-propagate the same to mtk_clk_register_cpumux() => clk_hw_register().
-Even though runtime pm is unlikely to be used with CPU muxes, this
-helps with code consistency and possibly opens to commonization of
-some mtk_clk_register_(x) functions.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-5-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-cpumux.c | 8 ++++----
- drivers/clk/mediatek/clk-cpumux.h | 2 +-
- drivers/clk/mediatek/clk-mt2701.c | 2 +-
- drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++-
- drivers/clk/mediatek/clk-mt7622.c | 4 ++--
- drivers/clk/mediatek/clk-mt7629.c | 4 ++--
- drivers/clk/mediatek/clk-mt8173.c | 4 ++--
- 7 files changed, 14 insertions(+), 13 deletions(-)
-
---- a/drivers/clk/mediatek/clk-cpumux.c
-+++ b/drivers/clk/mediatek/clk-cpumux.c
-@@ -58,7 +58,7 @@ static const struct clk_ops clk_cpumux_o
- };
-
- static struct clk_hw *
--mtk_clk_register_cpumux(const struct mtk_composite *mux,
-+mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux,
- struct regmap *regmap)
- {
- struct mtk_clk_cpumux *cpumux;
-@@ -81,7 +81,7 @@ mtk_clk_register_cpumux(const struct mtk
- cpumux->regmap = regmap;
- cpumux->hw.init = &init;
-
-- ret = clk_hw_register(NULL, &cpumux->hw);
-+ ret = clk_hw_register(dev, &cpumux->hw);
- if (ret) {
- kfree(cpumux);
- return ERR_PTR(ret);
-@@ -102,7 +102,7 @@ static void mtk_clk_unregister_cpumux(st
- kfree(cpumux);
- }
-
--int mtk_clk_register_cpumuxes(struct device_node *node,
-+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
- const struct mtk_composite *clks, int num,
- struct clk_hw_onecell_data *clk_data)
- {
-@@ -125,7 +125,7 @@ int mtk_clk_register_cpumuxes(struct dev
- continue;
- }
-
-- hw = mtk_clk_register_cpumux(mux, regmap);
-+ hw = mtk_clk_register_cpumux(dev, mux, regmap);
- if (IS_ERR(hw)) {
- pr_err("Failed to register clk %s: %pe\n", mux->name,
- hw);
---- a/drivers/clk/mediatek/clk-cpumux.h
-+++ b/drivers/clk/mediatek/clk-cpumux.h
-@@ -11,7 +11,7 @@ struct clk_hw_onecell_data;
- struct device_node;
- struct mtk_composite;
-
--int mtk_clk_register_cpumuxes(struct device_node *node,
-+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node,
- const struct mtk_composite *clks, int num,
- struct clk_hw_onecell_data *clk_data);
-
---- a/drivers/clk/mediatek/clk-mt2701.c
-+++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -761,7 +761,7 @@ static void __init mtk_infrasys_init_ear
- mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
- infra_clk_data);
-
-- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
-+ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
- infra_clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
---- a/drivers/clk/mediatek/clk-mt6795-infracfg.c
-+++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c
-@@ -105,7 +105,8 @@ static int clk_mt6795_infracfg_probe(str
- if (ret)
- goto free_clk_data;
-
-- ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
-+ ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
-+ ARRAY_SIZE(cpu_muxes), clk_data);
- if (ret)
- goto unregister_gates;
-
---- a/drivers/clk/mediatek/clk-mt7622.c
-+++ b/drivers/clk/mediatek/clk-mt7622.c
-@@ -638,8 +638,8 @@ static int mtk_infrasys_init(struct plat
- mtk_clk_register_gates(&pdev->dev, node, infra_clks,
- ARRAY_SIZE(infra_clks), clk_data);
-
-- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
-- clk_data);
-+ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
-+ ARRAY_SIZE(infra_muxes), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
- clk_data);
---- a/drivers/clk/mediatek/clk-mt7629.c
-+++ b/drivers/clk/mediatek/clk-mt7629.c
-@@ -588,8 +588,8 @@ static int mtk_infrasys_init(struct plat
- mtk_clk_register_gates(&pdev->dev, node, infra_clks,
- ARRAY_SIZE(infra_clks), clk_data);
-
-- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
-- clk_data);
-+ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes,
-+ ARRAY_SIZE(infra_muxes), clk_data);
-
- return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
- clk_data);
---- a/drivers/clk/mediatek/clk-mt8173.c
-+++ b/drivers/clk/mediatek/clk-mt8173.c
-@@ -892,8 +892,8 @@ static void __init mtk_infrasys_init(str
- clk_data);
- mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
-
-- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
-- clk_data);
-+ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes,
-+ ARRAY_SIZE(cpu_muxes), clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
+++ /dev/null
-From f23375db001ec0fe9f565be75eff43adde15407e Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:35 +0100
-Subject: [PATCH 03/15] clk: mediatek: clk-mtk: Propagate struct device for
- composites
-
-Like done for cpumux clocks, propagate struct device for composite
-clocks registered through clk-mtk helpers to be able to get runtime
-pm support for MTK clocks.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-6-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-
-[daniel@makrotopia.org: remove parts not relevant for OpenWrt]
----
- drivers/clk/mediatek/clk-mt2701.c | 10 ++++++----
- drivers/clk/mediatek/clk-mt2712.c | 12 ++++++++----
- drivers/clk/mediatek/clk-mt7622.c | 8 +++++---
- drivers/clk/mediatek/clk-mt7629.c | 8 +++++---
- drivers/clk/mediatek/clk-mtk.c | 11 ++++++-----
- drivers/clk/mediatek/clk-mtk.h | 3 ++-
- 6 files changed, 32 insertions(+), 20 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt2701.c
-+++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -679,8 +679,9 @@ static int mtk_topckgen_init(struct plat
- mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
- clk_data);
-
-- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
-- base, &mt2701_clk_lock, clk_data);
-+ mtk_clk_register_composites(&pdev->dev, top_muxes,
-+ ARRAY_SIZE(top_muxes), base,
-+ &mt2701_clk_lock, clk_data);
-
- mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
- base, &mt2701_clk_lock, clk_data);
-@@ -905,8 +906,9 @@ static int mtk_pericfg_init(struct platf
- mtk_clk_register_gates(&pdev->dev, node, peri_clks,
- ARRAY_SIZE(peri_clks), clk_data);
-
-- mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
-- &mt2701_clk_lock, clk_data);
-+ mtk_clk_register_composites(&pdev->dev, peri_muxs,
-+ ARRAY_SIZE(peri_muxs), base,
-+ &mt2701_clk_lock, clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
---- a/drivers/clk/mediatek/clk-mt2712.c
-+++ b/drivers/clk/mediatek/clk-mt2712.c
-@@ -1320,8 +1320,9 @@ static int clk_mt2712_top_probe(struct p
- mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
- top_clk_data);
- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
-- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
-- &mt2712_clk_lock, top_clk_data);
-+ mtk_clk_register_composites(&pdev->dev, top_muxes,
-+ ARRAY_SIZE(top_muxes), base,
-+ &mt2712_clk_lock, top_clk_data);
- mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
- &mt2712_clk_lock, top_clk_data);
- mtk_clk_register_gates(&pdev->dev, node, top_clks,
-@@ -1395,8 +1396,11 @@ static int clk_mt2712_mcu_probe(struct p
-
- clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
-
-- mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
-- &mt2712_clk_lock, clk_data);
-+ r = mtk_clk_register_composites(&pdev->dev, mcu_muxes,
-+ ARRAY_SIZE(mcu_muxes), base,
-+ &mt2712_clk_lock, clk_data);
-+ if (r)
-+ dev_err(&pdev->dev, "Could not register composites: %d\n", r);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-
---- a/drivers/clk/mediatek/clk-mt7622.c
-+++ b/drivers/clk/mediatek/clk-mt7622.c
-@@ -615,8 +615,9 @@ static int mtk_topckgen_init(struct plat
- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
- clk_data);
-
-- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
-- base, &mt7622_clk_lock, clk_data);
-+ mtk_clk_register_composites(&pdev->dev, top_muxes,
-+ ARRAY_SIZE(top_muxes), base,
-+ &mt7622_clk_lock, clk_data);
-
- mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
- base, &mt7622_clk_lock, clk_data);
-@@ -685,7 +686,8 @@ static int mtk_pericfg_init(struct platf
- mtk_clk_register_gates(&pdev->dev, node, peri_clks,
- ARRAY_SIZE(peri_clks), clk_data);
-
-- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
-+ mtk_clk_register_composites(&pdev->dev, peri_muxes,
-+ ARRAY_SIZE(peri_muxes), base,
- &mt7622_clk_lock, clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
---- a/drivers/clk/mediatek/clk-mt7629.c
-+++ b/drivers/clk/mediatek/clk-mt7629.c
-@@ -566,8 +566,9 @@ static int mtk_topckgen_init(struct plat
- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
- clk_data);
-
-- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
-- base, &mt7629_clk_lock, clk_data);
-+ mtk_clk_register_composites(&pdev->dev, top_muxes,
-+ ARRAY_SIZE(top_muxes), base,
-+ &mt7629_clk_lock, clk_data);
-
- clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
- clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
-@@ -613,7 +614,8 @@ static int mtk_pericfg_init(struct platf
- mtk_clk_register_gates(&pdev->dev, node, peri_clks,
- ARRAY_SIZE(peri_clks), clk_data);
-
-- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
-+ mtk_clk_register_composites(&pdev->dev, peri_muxes,
-+ ARRAY_SIZE(peri_muxes), base,
- &mt7629_clk_lock, clk_data);
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -197,8 +197,8 @@ void mtk_clk_unregister_factors(const st
- }
- EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors);
-
--static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc,
-- void __iomem *base, spinlock_t *lock)
-+static struct clk_hw *mtk_clk_register_composite(struct device *dev,
-+ const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock)
- {
- struct clk_hw *hw;
- struct clk_mux *mux = NULL;
-@@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_c
- div_ops = &clk_divider_ops;
- }
-
-- hw = clk_hw_register_composite(NULL, mc->name, parent_names, num_parents,
-+ hw = clk_hw_register_composite(dev, mc->name, parent_names, num_parents,
- mux_hw, mux_ops,
- div_hw, div_ops,
- gate_hw, gate_ops,
-@@ -308,7 +308,8 @@ static void mtk_clk_unregister_composite
- kfree(mux);
- }
-
--int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
-+int mtk_clk_register_composites(struct device *dev,
-+ const struct mtk_composite *mcs, int num,
- void __iomem *base, spinlock_t *lock,
- struct clk_hw_onecell_data *clk_data)
- {
-@@ -327,7 +328,7 @@ int mtk_clk_register_composites(const st
- continue;
- }
-
-- hw = mtk_clk_register_composite(mc, base, lock);
-+ hw = mtk_clk_register_composite(dev, mc, base, lock);
-
- if (IS_ERR(hw)) {
- pr_err("Failed to register clk %s: %pe\n", mc->name,
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -149,7 +149,8 @@ struct mtk_composite {
- .flags = 0, \
- }
-
--int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
-+int mtk_clk_register_composites(struct device *dev,
-+ const struct mtk_composite *mcs, int num,
- void __iomem *base, spinlock_t *lock,
- struct clk_hw_onecell_data *clk_data);
- void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,
+++ /dev/null
-From 5d911479e4c732729bfa798e4a9e3e5aec3e30a7 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:36 +0100
-Subject: [PATCH 04/15] clk: mediatek: clk-mux: Propagate struct device for
- mtk-mux
-
-Like done for other clocks, propagate struct device for mtk mux clocks
-registered through clk-mux helpers to enable runtime pm support.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-7-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-
-[daniel@makrotopia.org: removed parts not relevant for OpenWrt]
----
- drivers/clk/mediatek/clk-mt7986-infracfg.c | 3 ++-
- drivers/clk/mediatek/clk-mt7986-topckgen.c | 3 ++-
- drivers/clk/mediatek/clk-mux.c | 14 ++++++++------
- drivers/clk/mediatek/clk-mux.h | 3 ++-
- 4 files changed, 14 insertions(+), 9 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt7986-infracfg.c
-+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c
-@@ -178,7 +178,8 @@ static int clk_mt7986_infracfg_probe(str
- return -ENOMEM;
-
- mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
-- mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
-+ mtk_clk_register_muxes(&pdev->dev, infra_muxes,
-+ ARRAY_SIZE(infra_muxes), node,
- &mt7986_clk_lock, clk_data);
- mtk_clk_register_gates(&pdev->dev, node, infra_clks,
- ARRAY_SIZE(infra_clks), clk_data);
---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
-+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
-@@ -303,7 +303,8 @@ static int clk_mt7986_topckgen_probe(str
- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
- clk_data);
- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-- mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
-+ mtk_clk_register_muxes(&pdev->dev, top_muxes,
-+ ARRAY_SIZE(top_muxes), node,
- &mt7986_clk_lock, clk_data);
-
- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
---- a/drivers/clk/mediatek/clk-mux.c
-+++ b/drivers/clk/mediatek/clk-mux.c
-@@ -154,9 +154,10 @@ const struct clk_ops mtk_mux_gate_clr_se
- };
- EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops);
-
--static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux,
-- struct regmap *regmap,
-- spinlock_t *lock)
-+static struct clk_hw *mtk_clk_register_mux(struct device *dev,
-+ const struct mtk_mux *mux,
-+ struct regmap *regmap,
-+ spinlock_t *lock)
- {
- struct mtk_clk_mux *clk_mux;
- struct clk_init_data init = {};
-@@ -177,7 +178,7 @@ static struct clk_hw *mtk_clk_register_m
- clk_mux->lock = lock;
- clk_mux->hw.init = &init;
-
-- ret = clk_hw_register(NULL, &clk_mux->hw);
-+ ret = clk_hw_register(dev, &clk_mux->hw);
- if (ret) {
- kfree(clk_mux);
- return ERR_PTR(ret);
-@@ -198,7 +199,8 @@ static void mtk_clk_unregister_mux(struc
- kfree(mux);
- }
-
--int mtk_clk_register_muxes(const struct mtk_mux *muxes,
-+int mtk_clk_register_muxes(struct device *dev,
-+ const struct mtk_mux *muxes,
- int num, struct device_node *node,
- spinlock_t *lock,
- struct clk_hw_onecell_data *clk_data)
-@@ -222,7 +224,7 @@ int mtk_clk_register_muxes(const struct
- continue;
- }
-
-- hw = mtk_clk_register_mux(mux, regmap, lock);
-+ hw = mtk_clk_register_mux(dev, mux, regmap, lock);
-
- if (IS_ERR(hw)) {
- pr_err("Failed to register clk %s: %pe\n", mux->name,
---- a/drivers/clk/mediatek/clk-mux.h
-+++ b/drivers/clk/mediatek/clk-mux.h
-@@ -83,7 +83,8 @@ extern const struct clk_ops mtk_mux_gate
- 0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
- mtk_mux_clr_set_upd_ops)
-
--int mtk_clk_register_muxes(const struct mtk_mux *muxes,
-+int mtk_clk_register_muxes(struct device *dev,
-+ const struct mtk_mux *muxes,
- int num, struct device_node *node,
- spinlock_t *lock,
- struct clk_hw_onecell_data *clk_data);
+++ /dev/null
-From b8eb1081d267708ba976525a1fe2162901b34f3a Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:37 +0100
-Subject: [PATCH] clk: mediatek: clk-mtk: Add dummy clock ops
-
-In order to migrate some (few) old clock drivers to the common
-mtk_clk_simple_probe() function, add dummy clock ops to be able
-to insert a dummy clock with ID 0 at the beginning of the list.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Miles Chen <miles.chen@mediatek.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-8-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++
- drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++
- 2 files changed, 35 insertions(+)
-
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -18,6 +18,22 @@
- #include "clk-mtk.h"
- #include "clk-gate.h"
-
-+const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
-+EXPORT_SYMBOL_GPL(cg_regs_dummy);
-+
-+static int mtk_clk_dummy_enable(struct clk_hw *hw)
-+{
-+ return 0;
-+}
-+
-+static void mtk_clk_dummy_disable(struct clk_hw *hw) { }
-+
-+const struct clk_ops mtk_clk_dummy_ops = {
-+ .enable = mtk_clk_dummy_enable,
-+ .disable = mtk_clk_dummy_disable,
-+};
-+EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops);
-+
- static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data,
- unsigned int clk_num)
- {
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -22,6 +22,25 @@
-
- struct platform_device;
-
-+/*
-+ * We need the clock IDs to start from zero but to maintain devicetree
-+ * backwards compatibility we can't change bindings to start from zero.
-+ * Only a few platforms are affected, so we solve issues given by the
-+ * commonized MTK clocks probe function(s) by adding a dummy clock at
-+ * the beginning where needed.
-+ */
-+#define CLK_DUMMY 0
-+
-+extern const struct clk_ops mtk_clk_dummy_ops;
-+extern const struct mtk_gate_regs cg_regs_dummy;
-+
-+#define GATE_DUMMY(_id, _name) { \
-+ .id = _id, \
-+ .name = _name, \
-+ .regs = &cg_regs_dummy, \
-+ .ops = &mtk_clk_dummy_ops, \
-+ }
-+
- struct mtk_fixed_clk {
- int id;
- const char *name;
+++ /dev/null
-From c26e28015b74af73e0b299f6ad3ff22931e600b4 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:41 +0100
-Subject: [PATCH 05/15] clk: mediatek: Switch to mtk_clk_simple_probe() where
- possible
-
-mtk_clk_simple_probe() is a function that registers mtk gate clocks
-and, if reset data is present, a reset controller and across all of
-the MTK clock drivers, such a function is duplicated many times:
-switch to the common mtk_clk_simple_probe() function for all of the
-clock drivers that are registering as platform drivers.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Miles Chen <miles.chen@mediatek.com>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-
-[daniel@makrotopia.org: removed parts not relevant for OpenWrt]
----
- drivers/clk/mediatek/clk-mt2701-aud.c | 31 ++++++----
- drivers/clk/mediatek/clk-mt2701-eth.c | 36 ++++--------
- drivers/clk/mediatek/clk-mt2701-g3d.c | 56 ++++--------------
- drivers/clk/mediatek/clk-mt2701-hif.c | 38 ++++--------
- drivers/clk/mediatek/clk-mt2712.c | 83 ++++++++++----------------
- drivers/clk/mediatek/clk-mt7622-aud.c | 54 ++++++-----------
- drivers/clk/mediatek/clk-mt7622-eth.c | 82 +++++---------------------
- drivers/clk/mediatek/clk-mt7622-hif.c | 85 +++++----------------------
- drivers/clk/mediatek/clk-mt7629-hif.c | 85 +++++----------------------
- 9 files changed, 144 insertions(+), 406 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt2701-aud.c
-+++ b/drivers/clk/mediatek/clk-mt2701-aud.c
-@@ -52,6 +52,7 @@ static const struct mtk_gate_regs audio3
- };
-
- static const struct mtk_gate audio_clks[] = {
-+ GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
- /* AUDIO0 */
- GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
- GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
-@@ -114,29 +115,27 @@ static const struct mtk_gate audio_clks[
- GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
- };
-
-+static const struct mtk_clk_desc audio_desc = {
-+ .clks = audio_clks,
-+ .num_clks = ARRAY_SIZE(audio_clks),
-+};
-+
- static const struct of_device_id of_match_clk_mt2701_aud[] = {
-- { .compatible = "mediatek,mt2701-audsys", },
-- {}
-+ { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc },
-+ { /* sentinel */ }
- };
-
- static int clk_mt2701_aud_probe(struct platform_device *pdev)
- {
-- struct clk_hw_onecell_data *clk_data;
-- struct device_node *node = pdev->dev.of_node;
- int r;
-
-- clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
--
-- mtk_clk_register_gates(&pdev->dev, node, audio_clks,
-- ARRAY_SIZE(audio_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-+ r = mtk_clk_simple_probe(pdev);
- if (r) {
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
-- goto err_clk_provider;
-+ return r;
- }
-
- r = devm_of_platform_populate(&pdev->dev);
-@@ -146,13 +145,19 @@ static int clk_mt2701_aud_probe(struct p
- return 0;
-
- err_plat_populate:
-- of_clk_del_provider(node);
--err_clk_provider:
-+ mtk_clk_simple_remove(pdev);
- return r;
- }
-
-+static int clk_mt2701_aud_remove(struct platform_device *pdev)
-+{
-+ of_platform_depopulate(&pdev->dev);
-+ return mtk_clk_simple_remove(pdev);
-+}
-+
- static struct platform_driver clk_mt2701_aud_drv = {
- .probe = clk_mt2701_aud_probe,
-+ .remove = clk_mt2701_aud_remove,
- .driver = {
- .name = "clk-mt2701-aud",
- .of_match_table = of_match_clk_mt2701_aud,
---- a/drivers/clk/mediatek/clk-mt2701-eth.c
-+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
-@@ -20,6 +20,7 @@ static const struct mtk_gate_regs eth_cg
- GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
-
- static const struct mtk_gate eth_clks[] = {
-+ GATE_DUMMY(CLK_DUMMY, "eth_dummy"),
- GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
- GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
- GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
-@@ -38,35 +39,20 @@ static const struct mtk_clk_rst_desc clk
- .rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
-
--static const struct of_device_id of_match_clk_mt2701_eth[] = {
-- { .compatible = "mediatek,mt2701-ethsys", },
-- {}
-+static const struct mtk_clk_desc eth_desc = {
-+ .clks = eth_clks,
-+ .num_clks = ARRAY_SIZE(eth_clks),
-+ .rst_desc = &clk_rst_desc,
- };
-
--static int clk_mt2701_eth_probe(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- int r;
-- struct device_node *node = pdev->dev.of_node;
--
-- clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
--
-- mtk_clk_register_gates(&pdev->dev, node, eth_clks,
-- ARRAY_SIZE(eth_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
-- return r;
--}
-+static const struct of_device_id of_match_clk_mt2701_eth[] = {
-+ { .compatible = "mediatek,mt2701-ethsys", .data = ð_desc },
-+ { /* sentinel */ }
-+};
-
- static struct platform_driver clk_mt2701_eth_drv = {
-- .probe = clk_mt2701_eth_probe,
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
- .driver = {
- .name = "clk-mt2701-eth",
- .of_match_table = of_match_clk_mt2701_eth,
---- a/drivers/clk/mediatek/clk-mt2701-g3d.c
-+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
-@@ -26,6 +26,7 @@ static const struct mtk_gate_regs g3d_cg
- };
-
- static const struct mtk_gate g3d_clks[] = {
-+ GATE_DUMMY(CLK_DUMMY, "g3d_dummy"),
- GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
- };
-
-@@ -37,57 +38,20 @@ static const struct mtk_clk_rst_desc clk
- .rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
-
--static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- struct device_node *node = pdev->dev.of_node;
-- int r;
--
-- clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
--
-- mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks),
-- clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
-- return r;
--}
-+static const struct mtk_clk_desc g3d_desc = {
-+ .clks = g3d_clks,
-+ .num_clks = ARRAY_SIZE(g3d_clks),
-+ .rst_desc = &clk_rst_desc,
-+};
-
- static const struct of_device_id of_match_clk_mt2701_g3d[] = {
-- {
-- .compatible = "mediatek,mt2701-g3dsys",
-- .data = clk_mt2701_g3dsys_init,
-- }, {
-- /* sentinel */
-- }
-+ { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc },
-+ { /* sentinel */ }
- };
-
--static int clk_mt2701_g3d_probe(struct platform_device *pdev)
--{
-- int (*clk_init)(struct platform_device *);
-- int r;
--
-- clk_init = of_device_get_match_data(&pdev->dev);
-- if (!clk_init)
-- return -EINVAL;
--
-- r = clk_init(pdev);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- return r;
--}
--
- static struct platform_driver clk_mt2701_g3d_drv = {
-- .probe = clk_mt2701_g3d_probe,
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
- .driver = {
- .name = "clk-mt2701-g3d",
- .of_match_table = of_match_clk_mt2701_g3d,
---- a/drivers/clk/mediatek/clk-mt2701-hif.c
-+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
-@@ -20,6 +20,7 @@ static const struct mtk_gate_regs hif_cg
- GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
-
- static const struct mtk_gate hif_clks[] = {
-+ GATE_DUMMY(CLK_DUMMY, "hif_dummy"),
- GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
- GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
- GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
-@@ -35,37 +36,20 @@ static const struct mtk_clk_rst_desc clk
- .rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
-
--static const struct of_device_id of_match_clk_mt2701_hif[] = {
-- { .compatible = "mediatek,mt2701-hifsys", },
-- {}
-+static const struct mtk_clk_desc hif_desc = {
-+ .clks = hif_clks,
-+ .num_clks = ARRAY_SIZE(hif_clks),
-+ .rst_desc = &clk_rst_desc,
- };
-
--static int clk_mt2701_hif_probe(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- int r;
-- struct device_node *node = pdev->dev.of_node;
--
-- clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
--
-- mtk_clk_register_gates(&pdev->dev, node, hif_clks,
-- ARRAY_SIZE(hif_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-- if (r) {
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
-- return r;
-- }
--
-- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
-- return 0;
--}
-+static const struct of_device_id of_match_clk_mt2701_hif[] = {
-+ { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc },
-+ { /* sentinel */ }
-+};
-
- static struct platform_driver clk_mt2701_hif_drv = {
-- .probe = clk_mt2701_hif_probe,
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
- .driver = {
- .name = "clk-mt2701-hif",
- .of_match_table = of_match_clk_mt2701_hif,
---- a/drivers/clk/mediatek/clk-mt2712.c
-+++ b/drivers/clk/mediatek/clk-mt2712.c
-@@ -1337,50 +1337,6 @@ static int clk_mt2712_top_probe(struct p
- return r;
- }
-
--static int clk_mt2712_infra_probe(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- int r;
-- struct device_node *node = pdev->dev.of_node;
--
-- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
--
-- mtk_clk_register_gates(&pdev->dev, node, infra_clks,
-- ARRAY_SIZE(infra_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--
-- if (r != 0)
-- pr_err("%s(): could not register clock provider: %d\n",
-- __func__, r);
--
-- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
--
-- return r;
--}
--
--static int clk_mt2712_peri_probe(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- int r;
-- struct device_node *node = pdev->dev.of_node;
--
-- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
--
-- mtk_clk_register_gates(&pdev->dev, node, peri_clks,
-- ARRAY_SIZE(peri_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--
-- if (r != 0)
-- pr_err("%s(): could not register clock provider: %d\n",
-- __func__, r);
--
-- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
--
-- return r;
--}
--
- static int clk_mt2712_mcu_probe(struct platform_device *pdev)
- {
- struct clk_hw_onecell_data *clk_data;
-@@ -1419,12 +1375,6 @@ static const struct of_device_id of_matc
- .compatible = "mediatek,mt2712-topckgen",
- .data = clk_mt2712_top_probe,
- }, {
-- .compatible = "mediatek,mt2712-infracfg",
-- .data = clk_mt2712_infra_probe,
-- }, {
-- .compatible = "mediatek,mt2712-pericfg",
-- .data = clk_mt2712_peri_probe,
-- }, {
- .compatible = "mediatek,mt2712-mcucfg",
- .data = clk_mt2712_mcu_probe,
- }, {
-@@ -1450,6 +1400,33 @@ static int clk_mt2712_probe(struct platf
- return r;
- }
-
-+static const struct mtk_clk_desc infra_desc = {
-+ .clks = infra_clks,
-+ .num_clks = ARRAY_SIZE(infra_clks),
-+ .rst_desc = &clk_rst_desc[0],
-+};
-+
-+static const struct mtk_clk_desc peri_desc = {
-+ .clks = peri_clks,
-+ .num_clks = ARRAY_SIZE(peri_clks),
-+ .rst_desc = &clk_rst_desc[1],
-+};
-+
-+static const struct of_device_id of_match_clk_mt2712_simple[] = {
-+ { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc },
-+ { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, },
-+ { /* sentinel */ }
-+};
-+
-+static struct platform_driver clk_mt2712_simple_drv = {
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
-+ .driver = {
-+ .name = "clk-mt2712-simple",
-+ .of_match_table = of_match_clk_mt2712_simple,
-+ },
-+};
-+
- static struct platform_driver clk_mt2712_drv = {
- .probe = clk_mt2712_probe,
- .driver = {
-@@ -1460,7 +1437,11 @@ static struct platform_driver clk_mt2712
-
- static int __init clk_mt2712_init(void)
- {
-- return platform_driver_register(&clk_mt2712_drv);
-+ int ret = platform_driver_register(&clk_mt2712_drv);
-+
-+ if (ret)
-+ return ret;
-+ return platform_driver_register(&clk_mt2712_simple_drv);
- }
-
- arch_initcall(clk_mt2712_init);
---- a/drivers/clk/mediatek/clk-mt7622-aud.c
-+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
-@@ -106,24 +106,22 @@ static const struct mtk_gate audio_clks[
- GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
- };
-
--static int clk_mt7622_audiosys_init(struct platform_device *pdev)
-+static const struct mtk_clk_desc audio_desc = {
-+ .clks = audio_clks,
-+ .num_clks = ARRAY_SIZE(audio_clks),
-+};
-+
-+static int clk_mt7622_aud_probe(struct platform_device *pdev)
- {
-- struct clk_hw_onecell_data *clk_data;
-- struct device_node *node = pdev->dev.of_node;
- int r;
-
-- clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
--
-- mtk_clk_register_gates(&pdev->dev, node, audio_clks,
-- ARRAY_SIZE(audio_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-+ r = mtk_clk_simple_probe(pdev);
- if (r) {
- dev_err(&pdev->dev,
- "could not register clock provider: %s: %d\n",
- pdev->name, r);
-
-- goto err_clk_provider;
-+ return r;
- }
-
- r = devm_of_platform_populate(&pdev->dev);
-@@ -133,40 +131,24 @@ static int clk_mt7622_audiosys_init(stru
- return 0;
-
- err_plat_populate:
-- of_clk_del_provider(node);
--err_clk_provider:
-+ mtk_clk_simple_remove(pdev);
- return r;
- }
-
--static const struct of_device_id of_match_clk_mt7622_aud[] = {
-- {
-- .compatible = "mediatek,mt7622-audsys",
-- .data = clk_mt7622_audiosys_init,
-- }, {
-- /* sentinel */
-- }
--};
--
--static int clk_mt7622_aud_probe(struct platform_device *pdev)
-+static int clk_mt7622_aud_remove(struct platform_device *pdev)
- {
-- int (*clk_init)(struct platform_device *);
-- int r;
--
-- clk_init = of_device_get_match_data(&pdev->dev);
-- if (!clk_init)
-- return -EINVAL;
--
-- r = clk_init(pdev);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- return r;
-+ of_platform_depopulate(&pdev->dev);
-+ return mtk_clk_simple_remove(pdev);
- }
-
-+static const struct of_device_id of_match_clk_mt7622_aud[] = {
-+ { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc },
-+ { /* sentinel */ }
-+};
-+
- static struct platform_driver clk_mt7622_aud_drv = {
- .probe = clk_mt7622_aud_probe,
-+ .remove = clk_mt7622_aud_remove,
- .driver = {
- .name = "clk-mt7622-aud",
- .of_match_table = of_match_clk_mt7622_aud,
---- a/drivers/clk/mediatek/clk-mt7622-eth.c
-+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
-@@ -61,80 +61,26 @@ static const struct mtk_clk_rst_desc clk
- .rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
-
--static int clk_mt7622_ethsys_init(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- struct device_node *node = pdev->dev.of_node;
-- int r;
--
-- clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
--
-- mtk_clk_register_gates(&pdev->dev, node, eth_clks,
-- ARRAY_SIZE(eth_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
-- return r;
--}
--
--static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- struct device_node *node = pdev->dev.of_node;
-- int r;
--
-- clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
--
-- mtk_clk_register_gates(&pdev->dev, node, sgmii_clks,
-- ARRAY_SIZE(sgmii_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
-+static const struct mtk_clk_desc eth_desc = {
-+ .clks = eth_clks,
-+ .num_clks = ARRAY_SIZE(eth_clks),
-+ .rst_desc = &clk_rst_desc,
-+};
-
-- return r;
--}
-+static const struct mtk_clk_desc sgmii_desc = {
-+ .clks = sgmii_clks,
-+ .num_clks = ARRAY_SIZE(sgmii_clks),
-+};
-
- static const struct of_device_id of_match_clk_mt7622_eth[] = {
-- {
-- .compatible = "mediatek,mt7622-ethsys",
-- .data = clk_mt7622_ethsys_init,
-- }, {
-- .compatible = "mediatek,mt7622-sgmiisys",
-- .data = clk_mt7622_sgmiisys_init,
-- }, {
-- /* sentinel */
-- }
-+ { .compatible = "mediatek,mt7622-ethsys", .data = ð_desc },
-+ { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
-+ { /* sentinel */ }
- };
-
--static int clk_mt7622_eth_probe(struct platform_device *pdev)
--{
-- int (*clk_init)(struct platform_device *);
-- int r;
--
-- clk_init = of_device_get_match_data(&pdev->dev);
-- if (!clk_init)
-- return -EINVAL;
--
-- r = clk_init(pdev);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- return r;
--}
--
- static struct platform_driver clk_mt7622_eth_drv = {
-- .probe = clk_mt7622_eth_probe,
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
- .driver = {
- .name = "clk-mt7622-eth",
- .of_match_table = of_match_clk_mt7622_eth,
---- a/drivers/clk/mediatek/clk-mt7622-hif.c
-+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
-@@ -72,82 +72,27 @@ static const struct mtk_clk_rst_desc clk
- .rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
-
--static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- struct device_node *node = pdev->dev.of_node;
-- int r;
--
-- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
--
-- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
-- ARRAY_SIZE(ssusb_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
-- return r;
--}
--
--static int clk_mt7622_pciesys_init(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- struct device_node *node = pdev->dev.of_node;
-- int r;
--
-- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
--
-- mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
-- ARRAY_SIZE(pcie_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
-+static const struct mtk_clk_desc ssusb_desc = {
-+ .clks = ssusb_clks,
-+ .num_clks = ARRAY_SIZE(ssusb_clks),
-+ .rst_desc = &clk_rst_desc,
-+};
-
-- return r;
--}
-+static const struct mtk_clk_desc pcie_desc = {
-+ .clks = pcie_clks,
-+ .num_clks = ARRAY_SIZE(pcie_clks),
-+ .rst_desc = &clk_rst_desc,
-+};
-
- static const struct of_device_id of_match_clk_mt7622_hif[] = {
-- {
-- .compatible = "mediatek,mt7622-pciesys",
-- .data = clk_mt7622_pciesys_init,
-- }, {
-- .compatible = "mediatek,mt7622-ssusbsys",
-- .data = clk_mt7622_ssusbsys_init,
-- }, {
-- /* sentinel */
-- }
-+ { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc },
-+ { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc },
-+ { /* sentinel */ }
- };
-
--static int clk_mt7622_hif_probe(struct platform_device *pdev)
--{
-- int (*clk_init)(struct platform_device *);
-- int r;
--
-- clk_init = of_device_get_match_data(&pdev->dev);
-- if (!clk_init)
-- return -EINVAL;
--
-- r = clk_init(pdev);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- return r;
--}
--
- static struct platform_driver clk_mt7622_hif_drv = {
-- .probe = clk_mt7622_hif_probe,
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
- .driver = {
- .name = "clk-mt7622-hif",
- .of_match_table = of_match_clk_mt7622_hif,
---- a/drivers/clk/mediatek/clk-mt7629-hif.c
-+++ b/drivers/clk/mediatek/clk-mt7629-hif.c
-@@ -67,82 +67,27 @@ static const struct mtk_clk_rst_desc clk
- .rst_bank_nr = ARRAY_SIZE(rst_ofs),
- };
-
--static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- struct device_node *node = pdev->dev.of_node;
-- int r;
--
-- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
--
-- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks,
-- ARRAY_SIZE(ssusb_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
--
-- return r;
--}
--
--static int clk_mt7629_pciesys_init(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- struct device_node *node = pdev->dev.of_node;
-- int r;
--
-- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
--
-- mtk_clk_register_gates(&pdev->dev, node, pcie_clks,
-- ARRAY_SIZE(pcie_clks), clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
-+static const struct mtk_clk_desc ssusb_desc = {
-+ .clks = ssusb_clks,
-+ .num_clks = ARRAY_SIZE(ssusb_clks),
-+ .rst_desc = &clk_rst_desc,
-+};
-
-- return r;
--}
-+static const struct mtk_clk_desc pcie_desc = {
-+ .clks = pcie_clks,
-+ .num_clks = ARRAY_SIZE(pcie_clks),
-+ .rst_desc = &clk_rst_desc,
-+};
-
- static const struct of_device_id of_match_clk_mt7629_hif[] = {
-- {
-- .compatible = "mediatek,mt7629-pciesys",
-- .data = clk_mt7629_pciesys_init,
-- }, {
-- .compatible = "mediatek,mt7629-ssusbsys",
-- .data = clk_mt7629_ssusbsys_init,
-- }, {
-- /* sentinel */
-- }
-+ { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc },
-+ { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc },
-+ { /* sentinel */ }
- };
-
--static int clk_mt7629_hif_probe(struct platform_device *pdev)
--{
-- int (*clk_init)(struct platform_device *);
-- int r;
--
-- clk_init = of_device_get_match_data(&pdev->dev);
-- if (!clk_init)
-- return -EINVAL;
--
-- r = clk_init(pdev);
-- if (r)
-- dev_err(&pdev->dev,
-- "could not register clock provider: %s: %d\n",
-- pdev->name, r);
--
-- return r;
--}
--
- static struct platform_driver clk_mt7629_hif_drv = {
-- .probe = clk_mt7629_hif_probe,
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
- .driver = {
- .name = "clk-mt7629-hif",
- .of_match_table = of_match_clk_mt7629_hif,
+++ /dev/null
-From 7b6183108c8ccf0dc295f39cdf78bd8078455636 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:42 +0100
-Subject: [PATCH] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe()
-
-As a preparation to increase probe functions commonization across
-various MediaTek SoC clock controller drivers, extend function
-mtk_clk_simple_probe() to be able to register not only gates, but
-also fixed clocks, factors, muxes and composites.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Miles Chen <miles.chen@mediatek.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-13-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-mtk.c | 101 ++++++++++++++++++++++++++++++---
- drivers/clk/mediatek/clk-mtk.h | 10 ++++
- 2 files changed, 103 insertions(+), 8 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mtk.c
-+++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -11,12 +11,14 @@
- #include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/of.h>
-+#include <linux/of_address.h>
- #include <linux/of_device.h>
- #include <linux/platform_device.h>
- #include <linux/slab.h>
-
- #include "clk-mtk.h"
- #include "clk-gate.h"
-+#include "clk-mux.h"
-
- const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 };
- EXPORT_SYMBOL_GPL(cg_regs_dummy);
-@@ -466,20 +468,71 @@ int mtk_clk_simple_probe(struct platform
- const struct mtk_clk_desc *mcd;
- struct clk_hw_onecell_data *clk_data;
- struct device_node *node = pdev->dev.of_node;
-- int r;
-+ void __iomem *base;
-+ int num_clks, r;
-
- mcd = of_device_get_match_data(&pdev->dev);
- if (!mcd)
- return -EINVAL;
-
-- clk_data = mtk_alloc_clk_data(mcd->num_clks);
-+ /* Composite clocks needs us to pass iomem pointer */
-+ if (mcd->composite_clks) {
-+ if (!mcd->shared_io)
-+ base = devm_platform_ioremap_resource(pdev, 0);
-+ else
-+ base = of_iomap(node, 0);
-+
-+ if (IS_ERR_OR_NULL(base))
-+ return IS_ERR(base) ? PTR_ERR(base) : -ENOMEM;
-+ }
-+
-+ /* Calculate how many clk_hw_onecell_data entries to allocate */
-+ num_clks = mcd->num_clks + mcd->num_composite_clks;
-+ num_clks += mcd->num_fixed_clks + mcd->num_factor_clks;
-+ num_clks += mcd->num_mux_clks;
-+
-+ clk_data = mtk_alloc_clk_data(num_clks);
- if (!clk_data)
- return -ENOMEM;
-
-- r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks,
-- clk_data);
-- if (r)
-- goto free_data;
-+ if (mcd->fixed_clks) {
-+ r = mtk_clk_register_fixed_clks(mcd->fixed_clks,
-+ mcd->num_fixed_clks, clk_data);
-+ if (r)
-+ goto free_data;
-+ }
-+
-+ if (mcd->factor_clks) {
-+ r = mtk_clk_register_factors(mcd->factor_clks,
-+ mcd->num_factor_clks, clk_data);
-+ if (r)
-+ goto unregister_fixed_clks;
-+ }
-+
-+ if (mcd->mux_clks) {
-+ r = mtk_clk_register_muxes(&pdev->dev, mcd->mux_clks,
-+ mcd->num_mux_clks, node,
-+ mcd->clk_lock, clk_data);
-+ if (r)
-+ goto unregister_factors;
-+ };
-+
-+ if (mcd->composite_clks) {
-+ /* We don't check composite_lock because it's optional */
-+ r = mtk_clk_register_composites(&pdev->dev,
-+ mcd->composite_clks,
-+ mcd->num_composite_clks,
-+ base, mcd->clk_lock, clk_data);
-+ if (r)
-+ goto unregister_muxes;
-+ }
-+
-+ if (mcd->clks) {
-+ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks,
-+ mcd->num_clks, clk_data);
-+ if (r)
-+ goto unregister_composites;
-+ }
-
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r)
-@@ -497,9 +550,28 @@ int mtk_clk_simple_probe(struct platform
- return r;
-
- unregister_clks:
-- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
-+ if (mcd->clks)
-+ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
-+unregister_composites:
-+ if (mcd->composite_clks)
-+ mtk_clk_unregister_composites(mcd->composite_clks,
-+ mcd->num_composite_clks, clk_data);
-+unregister_muxes:
-+ if (mcd->mux_clks)
-+ mtk_clk_unregister_muxes(mcd->mux_clks,
-+ mcd->num_mux_clks, clk_data);
-+unregister_factors:
-+ if (mcd->factor_clks)
-+ mtk_clk_unregister_factors(mcd->factor_clks,
-+ mcd->num_factor_clks, clk_data);
-+unregister_fixed_clks:
-+ if (mcd->fixed_clks)
-+ mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
-+ mcd->num_fixed_clks, clk_data);
- free_data:
- mtk_free_clk_data(clk_data);
-+ if (mcd->shared_io && base)
-+ iounmap(base);
- return r;
- }
- EXPORT_SYMBOL_GPL(mtk_clk_simple_probe);
-@@ -511,7 +583,20 @@ int mtk_clk_simple_remove(struct platfor
- struct device_node *node = pdev->dev.of_node;
-
- of_clk_del_provider(node);
-- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
-+ if (mcd->clks)
-+ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data);
-+ if (mcd->composite_clks)
-+ mtk_clk_unregister_composites(mcd->composite_clks,
-+ mcd->num_composite_clks, clk_data);
-+ if (mcd->mux_clks)
-+ mtk_clk_unregister_muxes(mcd->mux_clks,
-+ mcd->num_mux_clks, clk_data);
-+ if (mcd->factor_clks)
-+ mtk_clk_unregister_factors(mcd->factor_clks,
-+ mcd->num_factor_clks, clk_data);
-+ if (mcd->fixed_clks)
-+ mtk_clk_unregister_fixed_clks(mcd->fixed_clks,
-+ mcd->num_fixed_clks, clk_data);
- mtk_free_clk_data(clk_data);
-
- return 0;
---- a/drivers/clk/mediatek/clk-mtk.h
-+++ b/drivers/clk/mediatek/clk-mtk.h
-@@ -215,7 +215,17 @@ void mtk_clk_unregister_ref2usb_tx(struc
- struct mtk_clk_desc {
- const struct mtk_gate *clks;
- size_t num_clks;
-+ const struct mtk_composite *composite_clks;
-+ size_t num_composite_clks;
-+ const struct mtk_fixed_clk *fixed_clks;
-+ size_t num_fixed_clks;
-+ const struct mtk_fixed_factor *factor_clks;
-+ size_t num_factor_clks;
-+ const struct mtk_mux *mux_clks;
-+ size_t num_mux_clks;
- const struct mtk_clk_rst_desc *rst_desc;
-+ spinlock_t *clk_lock;
-+ bool shared_io;
- };
-
- int mtk_clk_simple_probe(struct platform_device *pdev);
+++ /dev/null
-From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:52 +0100
-Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some
- clocks enabled
-
-Instead of calling clk_prepare_enable() on a bunch of clocks at probe
-time, set the CLK_IS_CRITICAL flag to the same as these are required
-to be always on, and this is the right way of achieving that.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Reviewed-by: Miles Chen <miles.chen@mediatek.com>
-Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++-----------
- 1 file changed, 24 insertions(+), 22 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
-+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
-@@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[]
- MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
- f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
- 0x1C0, 10),
-- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
-- 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-+ f_26m_adc_parents, 0x020, 0x024, 0x028,
-+ 24, 1, 31, 0x1C0, 11,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- /* CLK_CFG_3 */
-- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-- dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
-- 0x1C0, 12),
-- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
-- 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
-- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
-- 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-+ dramc_md32_parents, 0x030, 0x034, 0x038,
-+ 0, 1, 7, 0x1C0, 12,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-+ sysaxi_parents, 0x030, 0x034, 0x038,
-+ 8, 2, 15, 0x1C0, 13,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-+ sysapb_parents, 0x030, 0x034, 0x038,
-+ 16, 2, 23, 0x1C0, 14,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
- arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
- 31, 0x1C0, 15),
-@@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[]
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
- sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
- 0x1C0, 21),
-- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
-- sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
-- 0x1C0, 22),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
-+ sgm_reg_parents, 0x050, 0x054, 0x058,
-+ 16, 1, 23, 0x1C0, 22,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
- 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
- /* CLK_CFG_6 */
-@@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[]
- f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
- 0x1C0, 27),
- /* CLK_CFG_7 */
-- MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-- f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
-- 0x1C0, 28),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-+ f_26m_adc_parents, 0x070, 0x074, 0x078,
-+ 0, 1, 7, 0x1C0, 28,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
- 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-@@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str
- ARRAY_SIZE(top_muxes), node,
- &mt7986_clk_lock, clk_data);
-
-- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
-- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
-- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
-- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
-- clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
-- clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);
--
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-
- if (r) {
+++ /dev/null
-From 9ce3b4e4719d4eec38b2c8da939c073835573d1d Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Fri, 20 Jan 2023 10:20:53 +0100
-Subject: [PATCH 07/15] clk: mediatek: clk-mt7986-topckgen: Migrate to
- mtk_clk_simple_probe()
-
-There are no more non-common calls in clk_mt7986_topckgen_probe():
-migrate this driver to mtk_clk_simple_probe().
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Miles Chen <miles.chen@mediatek.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Link: https://lore.kernel.org/r/20230120092053.182923-24-angelogioacchino.delregno@collabora.com
-Tested-by: Mingming Su <mingming.su@mediatek.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-mt7986-topckgen.c | 55 +++++-----------------
- 1 file changed, 13 insertions(+), 42 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
-+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
-@@ -290,53 +290,24 @@ static const struct mtk_mux top_muxes[]
- 0x1C4, 5),
- };
-
--static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
--{
-- struct clk_hw_onecell_data *clk_data;
-- struct device_node *node = pdev->dev.of_node;
-- int r;
-- void __iomem *base;
-- int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
-- ARRAY_SIZE(top_muxes);
--
-- base = of_iomap(node, 0);
-- if (!base) {
-- pr_err("%s(): ioremap failed\n", __func__);
-- return -ENOMEM;
-- }
--
-- clk_data = mtk_alloc_clk_data(nr);
-- if (!clk_data)
-- return -ENOMEM;
--
-- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
-- clk_data);
-- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
-- mtk_clk_register_muxes(&pdev->dev, top_muxes,
-- ARRAY_SIZE(top_muxes), node,
-- &mt7986_clk_lock, clk_data);
--
-- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
--
-- if (r) {
-- pr_err("%s(): could not register clock provider: %d\n",
-- __func__, r);
-- goto free_topckgen_data;
-- }
-- return r;
--
--free_topckgen_data:
-- mtk_free_clk_data(clk_data);
-- return r;
--}
-+static const struct mtk_clk_desc topck_desc = {
-+ .fixed_clks = top_fixed_clks,
-+ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
-+ .factor_clks = top_divs,
-+ .num_factor_clks = ARRAY_SIZE(top_divs),
-+ .mux_clks = top_muxes,
-+ .num_mux_clks = ARRAY_SIZE(top_muxes),
-+ .clk_lock = &mt7986_clk_lock,
-+};
-
- static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
-- { .compatible = "mediatek,mt7986-topckgen", },
-- {}
-+ { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc },
-+ { /* sentinel */ }
- };
-
- static struct platform_driver clk_mt7986_topckgen_drv = {
-- .probe = clk_mt7986_topckgen_probe,
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
- .driver = {
- .name = "clk-mt7986-topckgen",
- .of_match_table = of_match_clk_mt7986_topckgen,
+++ /dev/null
-From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Mon, 6 Mar 2023 15:05:21 +0100
-Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set
- critical clock
-
-Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
-flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
-+++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
-@@ -42,7 +42,7 @@
- "clkxtal")
-
- static const struct mtk_pll_data plls[] = {
-- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,
-+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
- 0x0200, 4, 0, 0x0204, 0),
- PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
- 0x0210, 4, 0, 0x0214, 0),
-@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru
-
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
-- clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
--
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
+++ /dev/null
-From a6473d0f9f07b1196f3a67099826f50a2a4e84e8 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 26 Jan 2023 03:34:05 +0000
-Subject: [PATCH] dt-bindings: clock: mediatek: add mt7981 clock IDs
-
-Add MT7981 clock dt-bindings, include topckgen, apmixedsys,
-infracfg, and ethernet subsystem clocks.
-
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/e353d32b5a4481766519a037afe1ed44e31ece1a.1674703830.git.daniel@makrotopia.org
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../dt-bindings/clock/mediatek,mt7981-clk.h | 215 ++++++++++++++++++
- 1 file changed, 215 insertions(+)
- create mode 100644 include/dt-bindings/clock/mediatek,mt7981-clk.h
-
---- /dev/null
-+++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h
-@@ -0,0 +1,215 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Wenzhen.Yu <wenzhen.yu@mediatek.com>
-+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
-+ * Author: Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_MT7981_H
-+#define _DT_BINDINGS_CLK_MT7981_H
-+
-+/* TOPCKGEN */
-+#define CLK_TOP_CB_CKSQ_40M 0
-+#define CLK_TOP_CB_M_416M 1
-+#define CLK_TOP_CB_M_D2 2
-+#define CLK_TOP_CB_M_D3 3
-+#define CLK_TOP_M_D3_D2 4
-+#define CLK_TOP_CB_M_D4 5
-+#define CLK_TOP_CB_M_D8 6
-+#define CLK_TOP_M_D8_D2 7
-+#define CLK_TOP_CB_MM_720M 8
-+#define CLK_TOP_CB_MM_D2 9
-+#define CLK_TOP_CB_MM_D3 10
-+#define CLK_TOP_CB_MM_D3_D5 11
-+#define CLK_TOP_CB_MM_D4 12
-+#define CLK_TOP_CB_MM_D6 13
-+#define CLK_TOP_MM_D6_D2 14
-+#define CLK_TOP_CB_MM_D8 15
-+#define CLK_TOP_CB_APLL2_196M 16
-+#define CLK_TOP_APLL2_D2 17
-+#define CLK_TOP_APLL2_D4 18
-+#define CLK_TOP_NET1_2500M 19
-+#define CLK_TOP_CB_NET1_D4 20
-+#define CLK_TOP_CB_NET1_D5 21
-+#define CLK_TOP_NET1_D5_D2 22
-+#define CLK_TOP_NET1_D5_D4 23
-+#define CLK_TOP_CB_NET1_D8 24
-+#define CLK_TOP_NET1_D8_D2 25
-+#define CLK_TOP_NET1_D8_D4 26
-+#define CLK_TOP_CB_NET2_800M 27
-+#define CLK_TOP_CB_NET2_D2 28
-+#define CLK_TOP_CB_NET2_D4 29
-+#define CLK_TOP_NET2_D4_D2 30
-+#define CLK_TOP_NET2_D4_D4 31
-+#define CLK_TOP_CB_NET2_D6 32
-+#define CLK_TOP_CB_WEDMCU_208M 33
-+#define CLK_TOP_CB_SGM_325M 34
-+#define CLK_TOP_CKSQ_40M_D2 35
-+#define CLK_TOP_CB_RTC_32K 36
-+#define CLK_TOP_CB_RTC_32P7K 37
-+#define CLK_TOP_USB_TX250M 38
-+#define CLK_TOP_FAUD 39
-+#define CLK_TOP_NFI1X 40
-+#define CLK_TOP_USB_EQ_RX250M 41
-+#define CLK_TOP_USB_CDR_CK 42
-+#define CLK_TOP_USB_LN0_CK 43
-+#define CLK_TOP_SPINFI_BCK 44
-+#define CLK_TOP_SPI 45
-+#define CLK_TOP_SPIM_MST 46
-+#define CLK_TOP_UART_BCK 47
-+#define CLK_TOP_PWM_BCK 48
-+#define CLK_TOP_I2C_BCK 49
-+#define CLK_TOP_PEXTP_TL 50
-+#define CLK_TOP_EMMC_208M 51
-+#define CLK_TOP_EMMC_400M 52
-+#define CLK_TOP_DRAMC_REF 53
-+#define CLK_TOP_DRAMC_MD32 54
-+#define CLK_TOP_SYSAXI 55
-+#define CLK_TOP_SYSAPB 56
-+#define CLK_TOP_ARM_DB_MAIN 57
-+#define CLK_TOP_AP2CNN_HOST 58
-+#define CLK_TOP_NETSYS 59
-+#define CLK_TOP_NETSYS_500M 60
-+#define CLK_TOP_NETSYS_WED_MCU 61
-+#define CLK_TOP_NETSYS_2X 62
-+#define CLK_TOP_SGM_325M 63
-+#define CLK_TOP_SGM_REG 64
-+#define CLK_TOP_F26M 65
-+#define CLK_TOP_EIP97B 66
-+#define CLK_TOP_USB3_PHY 67
-+#define CLK_TOP_AUD 68
-+#define CLK_TOP_A1SYS 69
-+#define CLK_TOP_AUD_L 70
-+#define CLK_TOP_A_TUNER 71
-+#define CLK_TOP_U2U3_REF 72
-+#define CLK_TOP_U2U3_SYS 73
-+#define CLK_TOP_U2U3_XHCI 74
-+#define CLK_TOP_USB_FRMCNT 75
-+#define CLK_TOP_NFI1X_SEL 76
-+#define CLK_TOP_SPINFI_SEL 77
-+#define CLK_TOP_SPI_SEL 78
-+#define CLK_TOP_SPIM_MST_SEL 79
-+#define CLK_TOP_UART_SEL 80
-+#define CLK_TOP_PWM_SEL 81
-+#define CLK_TOP_I2C_SEL 82
-+#define CLK_TOP_PEXTP_TL_SEL 83
-+#define CLK_TOP_EMMC_208M_SEL 84
-+#define CLK_TOP_EMMC_400M_SEL 85
-+#define CLK_TOP_F26M_SEL 86
-+#define CLK_TOP_DRAMC_SEL 87
-+#define CLK_TOP_DRAMC_MD32_SEL 88
-+#define CLK_TOP_SYSAXI_SEL 89
-+#define CLK_TOP_SYSAPB_SEL 90
-+#define CLK_TOP_ARM_DB_MAIN_SEL 91
-+#define CLK_TOP_AP2CNN_HOST_SEL 92
-+#define CLK_TOP_NETSYS_SEL 93
-+#define CLK_TOP_NETSYS_500M_SEL 94
-+#define CLK_TOP_NETSYS_MCU_SEL 95
-+#define CLK_TOP_NETSYS_2X_SEL 96
-+#define CLK_TOP_SGM_325M_SEL 97
-+#define CLK_TOP_SGM_REG_SEL 98
-+#define CLK_TOP_EIP97B_SEL 99
-+#define CLK_TOP_USB3_PHY_SEL 100
-+#define CLK_TOP_AUD_SEL 101
-+#define CLK_TOP_A1SYS_SEL 102
-+#define CLK_TOP_AUD_L_SEL 103
-+#define CLK_TOP_A_TUNER_SEL 104
-+#define CLK_TOP_U2U3_SEL 105
-+#define CLK_TOP_U2U3_SYS_SEL 106
-+#define CLK_TOP_U2U3_XHCI_SEL 107
-+#define CLK_TOP_USB_FRMCNT_SEL 108
-+#define CLK_TOP_AUD_I2S_M 109
-+
-+/* INFRACFG */
-+#define CLK_INFRA_66M_MCK 0
-+#define CLK_INFRA_UART0_SEL 1
-+#define CLK_INFRA_UART1_SEL 2
-+#define CLK_INFRA_UART2_SEL 3
-+#define CLK_INFRA_SPI0_SEL 4
-+#define CLK_INFRA_SPI1_SEL 5
-+#define CLK_INFRA_SPI2_SEL 6
-+#define CLK_INFRA_PWM1_SEL 7
-+#define CLK_INFRA_PWM2_SEL 8
-+#define CLK_INFRA_PWM3_SEL 9
-+#define CLK_INFRA_PWM_BSEL 10
-+#define CLK_INFRA_PCIE_SEL 11
-+#define CLK_INFRA_GPT_STA 12
-+#define CLK_INFRA_PWM_HCK 13
-+#define CLK_INFRA_PWM_STA 14
-+#define CLK_INFRA_PWM1_CK 15
-+#define CLK_INFRA_PWM2_CK 16
-+#define CLK_INFRA_PWM3_CK 17
-+#define CLK_INFRA_CQ_DMA_CK 18
-+#define CLK_INFRA_AUD_BUS_CK 19
-+#define CLK_INFRA_AUD_26M_CK 20
-+#define CLK_INFRA_AUD_L_CK 21
-+#define CLK_INFRA_AUD_AUD_CK 22
-+#define CLK_INFRA_AUD_EG2_CK 23
-+#define CLK_INFRA_DRAMC_26M_CK 24
-+#define CLK_INFRA_DBG_CK 25
-+#define CLK_INFRA_AP_DMA_CK 26
-+#define CLK_INFRA_SEJ_CK 27
-+#define CLK_INFRA_SEJ_13M_CK 28
-+#define CLK_INFRA_THERM_CK 29
-+#define CLK_INFRA_I2C0_CK 30
-+#define CLK_INFRA_UART0_CK 31
-+#define CLK_INFRA_UART1_CK 32
-+#define CLK_INFRA_UART2_CK 33
-+#define CLK_INFRA_SPI2_CK 34
-+#define CLK_INFRA_SPI2_HCK_CK 35
-+#define CLK_INFRA_NFI1_CK 36
-+#define CLK_INFRA_SPINFI1_CK 37
-+#define CLK_INFRA_NFI_HCK_CK 38
-+#define CLK_INFRA_SPI0_CK 39
-+#define CLK_INFRA_SPI1_CK 40
-+#define CLK_INFRA_SPI0_HCK_CK 41
-+#define CLK_INFRA_SPI1_HCK_CK 42
-+#define CLK_INFRA_FRTC_CK 43
-+#define CLK_INFRA_MSDC_CK 44
-+#define CLK_INFRA_MSDC_HCK_CK 45
-+#define CLK_INFRA_MSDC_133M_CK 46
-+#define CLK_INFRA_MSDC_66M_CK 47
-+#define CLK_INFRA_ADC_26M_CK 48
-+#define CLK_INFRA_ADC_FRC_CK 49
-+#define CLK_INFRA_FBIST2FPC_CK 50
-+#define CLK_INFRA_I2C_MCK_CK 51
-+#define CLK_INFRA_I2C_PCK_CK 52
-+#define CLK_INFRA_IUSB_133_CK 53
-+#define CLK_INFRA_IUSB_66M_CK 54
-+#define CLK_INFRA_IUSB_SYS_CK 55
-+#define CLK_INFRA_IUSB_CK 56
-+#define CLK_INFRA_IPCIE_CK 57
-+#define CLK_INFRA_IPCIE_PIPE_CK 58
-+#define CLK_INFRA_IPCIER_CK 59
-+#define CLK_INFRA_IPCIEB_CK 60
-+
-+/* APMIXEDSYS */
-+#define CLK_APMIXED_ARMPLL 0
-+#define CLK_APMIXED_NET2PLL 1
-+#define CLK_APMIXED_MMPLL 2
-+#define CLK_APMIXED_SGMPLL 3
-+#define CLK_APMIXED_WEDMCUPLL 4
-+#define CLK_APMIXED_NET1PLL 5
-+#define CLK_APMIXED_MPLL 6
-+#define CLK_APMIXED_APLL2 7
-+
-+/* SGMIISYS_0 */
-+#define CLK_SGM0_TX_EN 0
-+#define CLK_SGM0_RX_EN 1
-+#define CLK_SGM0_CK0_EN 2
-+#define CLK_SGM0_CDR_CK0_EN 3
-+
-+/* SGMIISYS_1 */
-+#define CLK_SGM1_TX_EN 0
-+#define CLK_SGM1_RX_EN 1
-+#define CLK_SGM1_CK1_EN 2
-+#define CLK_SGM1_CDR_CK1_EN 3
-+
-+/* ETHSYS */
-+#define CLK_ETH_FE_EN 0
-+#define CLK_ETH_GP2_EN 1
-+#define CLK_ETH_GP1_EN 2
-+#define CLK_ETH_WOCPU0_EN 3
-+
-+#endif /* _DT_BINDINGS_CLK_MT7981_H */
+++ /dev/null
-From 8efeeb9c8b4ecf4fb4a74be9403aba951403bbaa Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 26 Jan 2023 03:34:24 +0000
-Subject: [PATCH] clk: mediatek: add MT7981 clock support
-
-Add MT7981 clock support, include topckgen, apmixedsys, infracfg and
-ethernet subsystem clocks.
-
-The drivers are based on clk-mt7981.c which can be found in MediaTek's
-SDK sources. To be fit for upstream inclusion the driver has been split
-into clock domains and the infracfg part has been significantly
-de-bloated by removing all the 1:1 factors (aliases).
-
-Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-[sboyd@kernel.org: Add module license]
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/Kconfig | 17 +
- drivers/clk/mediatek/Makefile | 4 +
- drivers/clk/mediatek/clk-mt7981-apmixed.c | 102 +++++
- drivers/clk/mediatek/clk-mt7981-eth.c | 118 ++++++
- drivers/clk/mediatek/clk-mt7981-infracfg.c | 207 ++++++++++
- drivers/clk/mediatek/clk-mt7981-topckgen.c | 422 +++++++++++++++++++++
- 6 files changed, 870 insertions(+)
- create mode 100644 drivers/clk/mediatek/clk-mt7981-apmixed.c
- create mode 100644 drivers/clk/mediatek/clk-mt7981-eth.c
- create mode 100644 drivers/clk/mediatek/clk-mt7981-infracfg.c
- create mode 100644 drivers/clk/mediatek/clk-mt7981-topckgen.c
-
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -381,6 +381,23 @@ config COMMON_CLK_MT7629_HIFSYS
- This driver supports MediaTek MT7629 HIFSYS clocks providing
- to PCI-E and USB.
-
-+config COMMON_CLK_MT7981
-+ bool "Clock driver for MediaTek MT7981"
-+ depends on ARCH_MEDIATEK || COMPILE_TEST
-+ select COMMON_CLK_MEDIATEK
-+ default ARCH_MEDIATEK
-+ help
-+ This driver supports MediaTek MT7981 basic clocks and clocks
-+ required for various peripherals found on this SoC.
-+
-+config COMMON_CLK_MT7981_ETHSYS
-+ tristate "Clock driver for MediaTek MT7981 ETHSYS"
-+ depends on COMMON_CLK_MT7981
-+ default COMMON_CLK_MT7981
-+ help
-+ This driver adds support for clocks for Ethernet and SGMII
-+ required on MediaTek MT7981 SoC.
-+
- config COMMON_CLK_MT7986
- bool "Clock driver for MediaTek MT7986"
- depends on ARCH_MEDIATEK || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -52,6 +52,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) +
- obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
- obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c
-@@ -0,0 +1,102 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
-+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
-+ * Author: Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-gate.h"
-+#include "clk-mtk.h"
-+#include "clk-mux.h"
-+#include "clk-pll.h"
-+
-+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-+#include <linux/clk.h>
-+
-+#define MT7981_PLL_FMAX (2500UL * MHZ)
-+#define CON0_MT7981_RST_BAR BIT(27)
-+
-+#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
-+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
-+ _div_table, _parent_name) \
-+ { \
-+ .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
-+ .en_mask = _en_mask, .flags = _flags, \
-+ .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \
-+ .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
-+ .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
-+ .pcw_shift = _pcw_shift, .div_table = _div_table, \
-+ .parent_name = _parent_name, \
-+ }
-+
-+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
-+ _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
-+ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
-+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
-+ "clkxtal")
-+
-+static const struct mtk_pll_data plls[] = {
-+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
-+ 32, 0x0200, 4, 0, 0x0204, 0),
-+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
-+ 0x0210, 4, 0, 0x0214, 0),
-+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
-+ 0x0220, 4, 0, 0x0224, 0),
-+ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
-+ 0x0230, 4, 0, 0x0234, 0),
-+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
-+ 0x0240, 4, 0, 0x0244, 0),
-+ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
-+ 0x0250, 4, 0, 0x0254, 0),
-+ PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
-+ 0x0260, 4, 0, 0x0264, 0),
-+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
-+ 0x0278, 4, 0, 0x027C, 0),
-+};
-+
-+static const struct of_device_id of_match_clk_mt7981_apmixed[] = {
-+ { .compatible = "mediatek,mt7981-apmixedsys", },
-+ { /* sentinel */ }
-+};
-+
-+static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
-+{
-+ struct clk_hw_onecell_data *clk_data;
-+ struct device_node *node = pdev->dev.of_node;
-+ int r;
-+
-+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-+ if (!clk_data)
-+ return -ENOMEM;
-+
-+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-+
-+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-+ if (r) {
-+ pr_err("%s(): could not register clock provider: %d\n",
-+ __func__, r);
-+ goto free_apmixed_data;
-+ }
-+ return r;
-+
-+free_apmixed_data:
-+ mtk_free_clk_data(clk_data);
-+ return r;
-+}
-+
-+static struct platform_driver clk_mt7981_apmixed_drv = {
-+ .probe = clk_mt7981_apmixed_probe,
-+ .driver = {
-+ .name = "clk-mt7981-apmixed",
-+ .of_match_table = of_match_clk_mt7981_apmixed,
-+ },
-+};
-+builtin_platform_driver(clk_mt7981_apmixed_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7981-eth.c
-@@ -0,0 +1,118 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
-+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
-+ * Author: Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+
-+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-+
-+static const struct mtk_gate_regs sgmii0_cg_regs = {
-+ .set_ofs = 0xE4,
-+ .clr_ofs = 0xE4,
-+ .sta_ofs = 0xE4,
-+};
-+
-+#define GATE_SGMII0(_id, _name, _parent, _shift) { \
-+ .id = _id, \
-+ .name = _name, \
-+ .parent_name = _parent, \
-+ .regs = &sgmii0_cg_regs, \
-+ .shift = _shift, \
-+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
-+ }
-+
-+static const struct mtk_gate sgmii0_clks[] __initconst = {
-+ GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
-+ GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
-+ GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
-+ GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
-+};
-+
-+static const struct mtk_gate_regs sgmii1_cg_regs = {
-+ .set_ofs = 0xE4,
-+ .clr_ofs = 0xE4,
-+ .sta_ofs = 0xE4,
-+};
-+
-+#define GATE_SGMII1(_id, _name, _parent, _shift) { \
-+ .id = _id, \
-+ .name = _name, \
-+ .parent_name = _parent, \
-+ .regs = &sgmii1_cg_regs, \
-+ .shift = _shift, \
-+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
-+ }
-+
-+static const struct mtk_gate sgmii1_clks[] __initconst = {
-+ GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
-+ GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
-+ GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
-+ GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
-+};
-+
-+static const struct mtk_gate_regs eth_cg_regs = {
-+ .set_ofs = 0x30,
-+ .clr_ofs = 0x30,
-+ .sta_ofs = 0x30,
-+};
-+
-+#define GATE_ETH(_id, _name, _parent, _shift) { \
-+ .id = _id, \
-+ .name = _name, \
-+ .parent_name = _parent, \
-+ .regs = ð_cg_regs, \
-+ .shift = _shift, \
-+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
-+ }
-+
-+static const struct mtk_gate eth_clks[] __initconst = {
-+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
-+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
-+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
-+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
-+};
-+
-+static const struct mtk_clk_desc eth_desc = {
-+ .clks = eth_clks,
-+ .num_clks = ARRAY_SIZE(eth_clks),
-+};
-+
-+static const struct mtk_clk_desc sgmii0_desc = {
-+ .clks = sgmii0_clks,
-+ .num_clks = ARRAY_SIZE(sgmii0_clks),
-+};
-+
-+static const struct mtk_clk_desc sgmii1_desc = {
-+ .clks = sgmii1_clks,
-+ .num_clks = ARRAY_SIZE(sgmii1_clks),
-+};
-+
-+static const struct of_device_id of_match_clk_mt7981_eth[] = {
-+ { .compatible = "mediatek,mt7981-ethsys", .data = ð_desc },
-+ { .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc },
-+ { .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc },
-+ { /* sentinel */ }
-+};
-+
-+static struct platform_driver clk_mt7981_eth_drv = {
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
-+ .driver = {
-+ .name = "clk-mt7981-eth",
-+ .of_match_table = of_match_clk_mt7981_eth,
-+ },
-+};
-+module_platform_driver(clk_mt7981_eth_drv);
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c
-@@ -0,0 +1,207 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
-+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
-+ * Author: Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "clk-mux.h"
-+
-+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-+#include <linux/clk.h>
-+
-+static DEFINE_SPINLOCK(mt7981_clk_lock);
-+
-+static const struct mtk_fixed_factor infra_divs[] = {
-+ FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
-+};
-+
-+static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
-+ "uart_sel" };
-+
-+static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",
-+ "spi_sel" };
-+
-+static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",
-+ "spim_mst_sel" };
-+
-+static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };
-+
-+static const char *const infra_pwm_bsel_parents[] __initconst = {
-+ "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"
-+};
-+
-+static const char *const infra_pcie_parents[] __initconst = {
-+ "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"
-+};
-+
-+static const struct mtk_mux infra_muxes[] = {
-+ /* MODULE_CLK_SEL_0 */
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
-+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
-+ -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
-+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
-+ -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
-+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
-+ -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
-+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
-+ -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
-+ infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
-+ -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",
-+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,
-+ -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
-+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,
-+ -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
-+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,
-+ -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",
-+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,
-+ -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
-+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
-+ 2, -1, -1, -1),
-+ /* MODULE_CLK_SEL_1 */
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
-+ infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
-+ -1, -1, -1),
-+};
-+
-+static const struct mtk_gate_regs infra0_cg_regs = {
-+ .set_ofs = 0x40,
-+ .clr_ofs = 0x44,
-+ .sta_ofs = 0x48,
-+};
-+
-+static const struct mtk_gate_regs infra1_cg_regs = {
-+ .set_ofs = 0x50,
-+ .clr_ofs = 0x54,
-+ .sta_ofs = 0x58,
-+};
-+
-+static const struct mtk_gate_regs infra2_cg_regs = {
-+ .set_ofs = 0x60,
-+ .clr_ofs = 0x64,
-+ .sta_ofs = 0x68,
-+};
-+
-+#define GATE_INFRA0(_id, _name, _parent, _shift) \
-+ { \
-+ .id = _id, .name = _name, .parent_name = _parent, \
-+ .regs = &infra0_cg_regs, .shift = _shift, \
-+ .ops = &mtk_clk_gate_ops_setclr, \
-+ }
-+
-+#define GATE_INFRA1(_id, _name, _parent, _shift) \
-+ { \
-+ .id = _id, .name = _name, .parent_name = _parent, \
-+ .regs = &infra1_cg_regs, .shift = _shift, \
-+ .ops = &mtk_clk_gate_ops_setclr, \
-+ }
-+
-+#define GATE_INFRA2(_id, _name, _parent, _shift) \
-+ { \
-+ .id = _id, .name = _name, .parent_name = _parent, \
-+ .regs = &infra2_cg_regs, .shift = _shift, \
-+ .ops = &mtk_clk_gate_ops_setclr, \
-+ }
-+
-+static const struct mtk_gate infra_clks[] = {
-+ /* INFRA0 */
-+ GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
-+ GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
-+ GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
-+ GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
-+ GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
-+ GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),
-+
-+ GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),
-+ GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
-+ GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),
-+ GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),
-+ GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),
-+ GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
-+ 14),
-+ GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
-+ GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
-+ GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
-+ GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
-+ GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),
-+ /* INFRA1 */
-+ GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
-+ GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),
-+ GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
-+ GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
-+ GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
-+ GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),
-+ GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),
-+ GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),
-+ GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),
-+ GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
-+ GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
-+ GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
-+ GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
-+ 13),
-+ GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
-+ 14),
-+ GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
-+ GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
-+ GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
-+ GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
-+ GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),
-+ GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
-+ GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
-+ GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),
-+ GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),
-+ GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),
-+ /* INFRA2 */
-+ GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),
-+ GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),
-+ GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),
-+ GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),
-+ GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),
-+ GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
-+ 13),
-+ GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),
-+ GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),
-+};
-+
-+static const struct mtk_clk_desc infracfg_desc = {
-+ .factor_clks = infra_divs,
-+ .num_factor_clks = ARRAY_SIZE(infra_divs),
-+ .mux_clks = infra_muxes,
-+ .num_mux_clks = ARRAY_SIZE(infra_muxes),
-+ .clks = infra_clks,
-+ .num_clks = ARRAY_SIZE(infra_clks),
-+ .clk_lock = &mt7981_clk_lock,
-+};
-+
-+static const struct of_device_id of_match_clk_mt7981_infracfg[] = {
-+ { .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc },
-+ { /* sentinel */ }
-+};
-+
-+static struct platform_driver clk_mt7981_infracfg_drv = {
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
-+ .driver = {
-+ .name = "clk-mt7981-infracfg",
-+ .of_match_table = of_match_clk_mt7981_infracfg,
-+ },
-+};
-+builtin_platform_driver(clk_mt7981_infracfg_drv);
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
-@@ -0,0 +1,422 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2021 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
-+ * Author: Jianhui Zhao <zhaojh329@gmail.com>
-+ */
-+
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "clk-mux.h"
-+
-+#include <dt-bindings/clock/mediatek,mt7981-clk.h>
-+#include <linux/clk.h>
-+
-+static DEFINE_SPINLOCK(mt7981_clk_lock);
-+
-+static const struct mtk_fixed_factor top_divs[] = {
-+ FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
-+ FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
-+ FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
-+ FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
-+ FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
-+ FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
-+ FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
-+ FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
-+ FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1),
-+ FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
-+ FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3),
-+ FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15),
-+ FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
-+ FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6),
-+ FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12),
-+ FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
-+ FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
-+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
-+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-+ FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1),
-+ FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
-+ FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
-+ FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
-+ FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
-+ FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8),
-+ FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
-+ FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
-+ FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
-+ FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2),
-+ FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
-+ FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
-+ FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16),
-+ FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6),
-+ FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1),
-+ FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
-+ FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2),
-+ FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
-+ FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
-+ FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
-+ FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1),
-+ FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
-+ FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
-+ FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
-+ FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
-+ FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
-+ FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1),
-+ FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1),
-+ FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
-+ FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1),
-+ FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
-+ FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
-+ FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1),
-+ FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1),
-+ FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1),
-+ FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1),
-+ FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
-+ FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1),
-+ FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1),
-+ FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
-+ FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1),
-+ FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1),
-+ FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
-+ FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
-+ FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
-+ FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1),
-+ FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
-+ FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1),
-+ FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1),
-+ FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1),
-+ FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
-+ FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
-+ FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
-+ FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
-+ FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
-+ FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
-+ FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1),
-+};
-+
-+static const char * const nfi1x_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_mm_d4",
-+ "net1_d8_d2",
-+ "cb_net2_d6",
-+ "cb_m_d4",
-+ "cb_mm_d8",
-+ "net1_d8_d4",
-+ "cb_m_d8"
-+};
-+
-+static const char * const spinfi_parents[] __initconst = {
-+ "cksq_40m_d2",
-+ "cb_cksq_40m",
-+ "net1_d5_d4",
-+ "cb_m_d4",
-+ "cb_mm_d8",
-+ "net1_d8_d4",
-+ "mm_d6_d2",
-+ "cb_m_d8"
-+};
-+
-+static const char * const spi_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_m_d2",
-+ "cb_mm_d4",
-+ "net1_d8_d2",
-+ "cb_net2_d6",
-+ "net1_d5_d4",
-+ "cb_m_d4",
-+ "net1_d8_d4"
-+};
-+
-+static const char * const uart_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_m_d8",
-+ "m_d8_d2"
-+};
-+
-+static const char * const pwm_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "net1_d8_d2",
-+ "net1_d5_d4",
-+ "cb_m_d4",
-+ "m_d8_d2",
-+ "cb_rtc_32k"
-+};
-+
-+static const char * const i2c_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "net1_d5_d4",
-+ "cb_m_d4",
-+ "net1_d8_d4"
-+};
-+
-+static const char * const pextp_tl_ck_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "net1_d5_d4",
-+ "cb_m_d4",
-+ "cb_rtc_32k"
-+};
-+
-+static const char * const emmc_208m_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_m_d2",
-+ "cb_net2_d4",
-+ "cb_apll2_196m",
-+ "cb_mm_d4",
-+ "net1_d8_d2",
-+ "cb_mm_d6"
-+};
-+
-+static const char * const emmc_400m_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_net2_d2",
-+ "cb_mm_d2",
-+ "cb_net2_d2"
-+};
-+
-+static const char * const csw_f26m_parents[] __initconst = {
-+ "cksq_40m_d2",
-+ "m_d8_d2"
-+};
-+
-+static const char * const dramc_md32_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_m_d2",
-+ "cb_wedmcu_208m"
-+};
-+
-+static const char * const sysaxi_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "net1_d8_d2"
-+};
-+
-+static const char * const sysapb_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "m_d3_d2"
-+};
-+
-+static const char * const arm_db_main_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_net2_d6"
-+};
-+
-+static const char * const ap2cnn_host_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "net1_d8_d4"
-+};
-+
-+static const char * const netsys_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_mm_d2"
-+};
-+
-+static const char * const netsys_500m_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_net1_d5"
-+};
-+
-+static const char * const netsys_mcu_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_mm_720m",
-+ "cb_net1_d4",
-+ "cb_net1_d5",
-+ "cb_m_416m"
-+};
-+
-+static const char * const netsys_2x_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_net2_800m",
-+ "cb_mm_720m"
-+};
-+
-+static const char * const sgm_325m_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_sgm_325m"
-+};
-+
-+static const char * const sgm_reg_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_net2_d4"
-+};
-+
-+static const char * const eip97b_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_net1_d5",
-+ "cb_m_416m",
-+ "cb_mm_d2",
-+ "net1_d5_d2"
-+};
-+
-+static const char * const aud_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_apll2_196m"
-+};
-+
-+static const char * const a1sys_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "apll2_d4"
-+};
-+
-+static const char * const aud_l_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_apll2_196m",
-+ "m_d8_d2"
-+};
-+
-+static const char * const a_tuner_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "apll2_d4",
-+ "m_d8_d2"
-+};
-+
-+static const char * const u2u3_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "m_d8_d2"
-+};
-+
-+static const char * const u2u3_sys_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "net1_d5_d4"
-+};
-+
-+static const char * const usb_frmcnt_parents[] __initconst = {
-+ "cb_cksq_40m",
-+ "cb_mm_d3_d5"
-+};
-+
-+static const struct mtk_mux top_muxes[] = {
-+ /* CLK_CFG_0 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
-+ 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
-+ 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
-+ 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
-+ 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
-+ /* CLK_CFG_1 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
-+ 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
-+ 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
-+ 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
-+ pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
-+ 0x1C0, 7),
-+ /* CLK_CFG_2 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel",
-+ emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
-+ 0x1C0, 8),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
-+ emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15,
-+ 0x1C0, 9),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
-+ csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23,
-+ 0x1C0, 10,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
-+ csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1,
-+ 31, 0x1C0, 11,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+ /* CLK_CFG_3 */
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
-+ dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2,
-+ 7, 0x1C0, 12,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
-+ sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15,
-+ 0x1C0, 13,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
-+ sysapb_parents, 0x030, 0x034, 0x038, 16, 1,
-+ 23, 0x1C0, 14,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
-+ arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31,
-+ 0x1C0, 15),
-+ /* CLK_CFG_4 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
-+ ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7,
-+ 0x1C0, 16),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
-+ 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
-+ netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23,
-+ 0x1C0, 18),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
-+ netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
-+ 0x1C0, 19),
-+ /* CLK_CFG_5 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
-+ netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
-+ 0x1C0, 20),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
-+ sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
-+ 0x1C0, 21),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
-+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
-+ 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
-+ /* CLK_CFG_6 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
-+ csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1,
-+ 7, 0x1C0, 24),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060,
-+ 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
-+ 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
-+ 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27),
-+ /* CLK_CFG_7 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
-+ a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7,
-+ 0x1C0, 28),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070,
-+ 0x074, 0x078, 8, 1, 15, 0x1C0, 29),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
-+ u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23,
-+ 0x1C0, 30),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
-+ u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31,
-+ 0x1C4, 0),
-+ /* CLK_CFG_8 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
-+ usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7,
-+ 0x1C4, 1),
-+};
-+
-+static struct mtk_composite top_aud_divs[] = {
-+ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud",
-+ 0x0420, 0, 0x0420, 8, 8),
-+};
-+
-+static const struct mtk_clk_desc topck_desc = {
-+ .factor_clks = top_divs,
-+ .num_factor_clks = ARRAY_SIZE(top_divs),
-+ .mux_clks = top_muxes,
-+ .num_mux_clks = ARRAY_SIZE(top_muxes),
-+ .composite_clks = top_aud_divs,
-+ .num_composite_clks = ARRAY_SIZE(top_aud_divs),
-+ .clk_lock = &mt7981_clk_lock,
-+};
-+
-+static const struct of_device_id of_match_clk_mt7981_topckgen[] = {
-+ { .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc },
-+ { /* sentinel */ }
-+};
-+
-+static struct platform_driver clk_mt7981_topckgen_drv = {
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
-+ .driver = {
-+ .name = "clk-mt7981-topckgen",
-+ .of_match_table = of_match_clk_mt7981_topckgen,
-+ },
-+};
-+builtin_platform_driver(clk_mt7981_topckgen_drv);
+++ /dev/null
-From fc157139e6b7f8dfb6430ac7191ba754027705e8 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 18 Feb 2024 01:59:59 +0000
-Subject: [PATCH] clk: mediatek: mt7981-topckgen: flag SGM_REG_SEL as critical
-
-Without the SGM_REG_SEL clock enabled the system freezes if trying to
-access registers used by MT7981 clock drivers itself.
-Mark SGM_REG_SEL as critical to make sure it is always enabled to
-prevent freezes on boot depending on probe order.
-
-Fixes: 813c3b53b55ba ("clk: mediatek: add MT7981 clock support")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/clk/mediatek/clk-mt7981-topckgen.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/mediatek/clk-mt7981-topckgen.c
-+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c
-@@ -359,8 +359,9 @@ static const struct mtk_mux top_muxes[]
- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
- sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
- 0x1C0, 21),
-- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
-- 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
-+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22,
-+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
- MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents,
- 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23),
- /* CLK_CFG_6 */
+++ /dev/null
---- a/drivers/pinctrl/mediatek/Kconfig
-+++ b/drivers/pinctrl/mediatek/Kconfig
-@@ -141,6 +141,13 @@ config PINCTRL_MT7986
- default ARM64 && ARCH_MEDIATEK
- select PINCTRL_MTK_MOORE
-
-+config PINCTRL_MT7988
-+ bool "Mediatek MT7988 pin control"
-+ depends on OF
-+ depends on ARM64 || COMPILE_TEST
-+ default ARCH_MEDIATEK
-+ select PINCTRL_MTK_MOORE
-+
- config PINCTRL_MT8167
- bool "Mediatek MT8167 pin control"
- depends on OF
---- a/drivers/pinctrl/mediatek/Makefile
-+++ b/drivers/pinctrl/mediatek/Makefile
-@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-
- obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
- obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
- obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
-+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
- obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
- obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
- obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
+++ /dev/null
-From cc4d9e0c77494fcf6bccbc57e23db0007cf681b7 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 26 Jan 2023 03:33:46 +0000
-Subject: [PATCH] dt-bindings: clock: Add compatibles for MT7981
-
-Add compatible string for MT7981 to existing bindings at
- - mediatek,apmixedsys.yaml
- - mediatek,topckgen.yaml
- - mediatek,ethsys.txt
- - mediatek,infracfg.yaml
- - mediatek,sgmiisys.txt
-
-Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Link: https://lore.kernel.org/r/cc85ee470c781ff4013f6c21c92c0a21574b12b2.1674703830.git.daniel@makrotopia.org
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
- .../devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml | 1 +
- .../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt | 2 ++
- .../devicetree/bindings/clock/mediatek,apmixedsys.yaml | 1 +
- Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml | 1 +
- 5 files changed, 6 insertions(+)
-
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
-@@ -10,6 +10,7 @@ Required Properties:
- - "mediatek,mt7622-ethsys", "syscon"
- - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
- - "mediatek,mt7629-ethsys", "syscon"
-+ - "mediatek,mt7981-ethsys", "syscon"
- - "mediatek,mt7986-ethsys", "syscon"
- - #clock-cells: Must be 1
- - #reset-cells: Must be 1
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
-@@ -28,6 +28,7 @@ properties:
- - mediatek,mt6797-infracfg
- - mediatek,mt7622-infracfg
- - mediatek,mt7629-infracfg
-+ - mediatek,mt7981-infracfg
- - mediatek,mt7986-infracfg
- - mediatek,mt8135-infracfg
- - mediatek,mt8167-infracfg
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
-@@ -8,6 +8,8 @@ Required Properties:
- - compatible: Should be:
- - "mediatek,mt7622-sgmiisys", "syscon"
- - "mediatek,mt7629-sgmiisys", "syscon"
-+ - "mediatek,mt7981-sgmiisys_0", "syscon"
-+ - "mediatek,mt7981-sgmiisys_1", "syscon"
- - "mediatek,mt7986-sgmiisys_0", "syscon"
- - "mediatek,mt7986-sgmiisys_1", "syscon"
- - #clock-cells: Must be 1
---- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
-+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
-@@ -20,6 +20,7 @@ properties:
- - enum:
- - mediatek,mt6797-apmixedsys
- - mediatek,mt7622-apmixedsys
-+ - mediatek,mt7981-apmixedsys
- - mediatek,mt7986-apmixedsys
- - mediatek,mt8135-apmixedsys
- - mediatek,mt8173-apmixedsys
---- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
-+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
-@@ -35,6 +35,7 @@ properties:
- - mediatek,mt6779-topckgen
- - mediatek,mt6795-topckgen
- - mediatek,mt7629-topckgen
-+ - mediatek,mt7981-topckgen
- - mediatek,mt7986-topckgen
- - mediatek,mt8167-topckgen
- - mediatek,mt8183-topckgen
+++ /dev/null
-From d4f08a703565abf47baa5a77d05365cf4598d55c Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 19 Mar 2023 12:56:52 +0000
-Subject: [PATCH 1/2] dt-bindings: arm: mediatek: sgmiisys: Convert to DT
- schema
-
-Convert mediatek,sgmiiisys bindings to DT schema format.
-Add maintainer Matthias Brugger, no maintainers were listed in the
-original documentation.
-As this node is also referenced by the Ethernet controller and used
-as SGMII PCS add this fact to the description.
-Move the file to Documentation/devicetree/bindings/net/pcs/ which seems
-more appropriate given that the great majority of registers are related
-to SGMII PCS functionality and only one register represents clock bits.
-
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- .../arm/mediatek/mediatek,sgmiisys.txt | 27 ----------
- .../bindings/net/pcs/mediatek,sgmiisys.yaml | 49 +++++++++++++++++++
- 2 files changed, 49 insertions(+), 27 deletions(-)
- delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
- create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
-+++ /dev/null
-@@ -1,27 +0,0 @@
--MediaTek SGMIISYS controller
--============================
--
--The MediaTek SGMIISYS controller provides various clocks to the system.
--
--Required Properties:
--
--- compatible: Should be:
-- - "mediatek,mt7622-sgmiisys", "syscon"
-- - "mediatek,mt7629-sgmiisys", "syscon"
-- - "mediatek,mt7981-sgmiisys_0", "syscon"
-- - "mediatek,mt7981-sgmiisys_1", "syscon"
-- - "mediatek,mt7986-sgmiisys_0", "syscon"
-- - "mediatek,mt7986-sgmiisys_1", "syscon"
--- #clock-cells: Must be 1
--
--The SGMIISYS controller uses the common clk binding from
--Documentation/devicetree/bindings/clock/clock-bindings.txt
--The available clocks are defined in dt-bindings/clock/mt*-clk.h.
--
--Example:
--
--sgmiisys: sgmiisys@1b128000 {
-- compatible = "mediatek,mt7622-sgmiisys", "syscon";
-- reg = <0 0x1b128000 0 0x1000>;
-- #clock-cells = <1>;
--};
---- /dev/null
-+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-@@ -0,0 +1,49 @@
-+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek SGMIISYS Controller
-+
-+maintainers:
-+ - Matthias Brugger <matthias.bgg@gmail.com>
-+
-+description:
-+ The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
-+ to the ethernet subsystem to which it is attached.
-+
-+properties:
-+ compatible:
-+ items:
-+ - enum:
-+ - mediatek,mt7622-sgmiisys
-+ - mediatek,mt7629-sgmiisys
-+ - mediatek,mt7986-sgmiisys_0
-+ - mediatek,mt7986-sgmiisys_1
-+ - const: syscon
-+
-+ reg:
-+ maxItems: 1
-+
-+ '#clock-cells':
-+ const: 1
-+
-+required:
-+ - compatible
-+ - reg
-+ - '#clock-cells'
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ soc {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ sgmiisys: syscon@1b128000 {
-+ compatible = "mediatek,mt7622-sgmiisys", "syscon";
-+ reg = <0 0x1b128000 0 0x1000>;
-+ #clock-cells = <1>;
-+ };
-+ };
+++ /dev/null
-From 4f7eb19c4f44078100659f6ba073b0cc7191bc91 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 19 Mar 2023 12:57:04 +0000
-Subject: [PATCH 2/2] dt-bindings: net: pcs: mediatek,sgmiisys: add MT7981 SoC
-
-Add mediatek,pnswap boolean property needed on many boards using the
-MediaTek MT7981 SoC.
-
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- .../devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-@@ -19,6 +19,8 @@ properties:
- - enum:
- - mediatek,mt7622-sgmiisys
- - mediatek,mt7629-sgmiisys
-+ - mediatek,mt7981-sgmiisys_0
-+ - mediatek,mt7981-sgmiisys_1
- - mediatek,mt7986-sgmiisys_0
- - mediatek,mt7986-sgmiisys_1
- - const: syscon
-@@ -29,6 +31,10 @@ properties:
- '#clock-cells':
- const: 1
-
-+ mediatek,pnswap:
-+ description: Invert polarity of the SGMII data lanes
-+ type: boolean
-+
- required:
- - compatible
- - reg
+++ /dev/null
-From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Sun, 19 Nov 2023 22:24:16 +0100
-Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert
- to DT schema
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-DT schema helps validating DTS files. Binding was moved to clock/ as
-this hardware is a clock provider. Example required a small fix for
-"reg" value (1 address cell + 1 size cell).
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ----------
- .../bindings/clock/mediatek,ethsys.yaml | 54 +++++++++++++++++++
- 2 files changed, 54 insertions(+), 29 deletions(-)
- delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
- create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
-
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
-+++ /dev/null
-@@ -1,29 +0,0 @@
--Mediatek ethsys controller
--============================
--
--The Mediatek ethsys controller provides various clocks to the system.
--
--Required Properties:
--
--- compatible: Should be:
-- - "mediatek,mt2701-ethsys", "syscon"
-- - "mediatek,mt7622-ethsys", "syscon"
-- - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
-- - "mediatek,mt7629-ethsys", "syscon"
-- - "mediatek,mt7981-ethsys", "syscon"
-- - "mediatek,mt7986-ethsys", "syscon"
--- #clock-cells: Must be 1
--- #reset-cells: Must be 1
--
--The ethsys controller uses the common clk binding from
--Documentation/devicetree/bindings/clock/clock-bindings.txt
--The available clocks are defined in dt-bindings/clock/mt*-clk.h.
--
--Example:
--
--ethsys: clock-controller@1b000000 {
-- compatible = "mediatek,mt2701-ethsys", "syscon";
-- reg = <0 0x1b000000 0 0x1000>;
-- #clock-cells = <1>;
-- #reset-cells = <1>;
--};
---- /dev/null
-+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
-@@ -0,0 +1,54 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Mediatek ethsys controller
-+
-+description:
-+ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-+
-+maintainers:
-+ - James Liao <jamesjj.liao@mediatek.com>
-+
-+properties:
-+ compatible:
-+ oneOf:
-+ - items:
-+ - enum:
-+ - mediatek,mt2701-ethsys
-+ - mediatek,mt7622-ethsys
-+ - mediatek,mt7629-ethsys
-+ - mediatek,mt7981-ethsys
-+ - mediatek,mt7986-ethsys
-+ - const: syscon
-+ - items:
-+ - const: mediatek,mt7623-ethsys
-+ - const: mediatek,mt2701-ethsys
-+ - const: syscon
-+
-+ reg:
-+ maxItems: 1
-+
-+ "#clock-cells":
-+ const: 1
-+
-+ "#reset-cells":
-+ const: 1
-+
-+required:
-+ - reg
-+ - "#clock-cells"
-+ - "#reset-cells"
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ clock-controller@1b000000 {
-+ compatible = "mediatek,mt2701-ethsys", "syscon";
-+ reg = <0x1b000000 0x1000>;
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ };
+++ /dev/null
-From 5cfa3beb7761cb84be77225902e018d9d3f9b973 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 17 Dec 2023 21:49:45 +0000
-Subject: [PATCH 1/4] dt-bindings: reset: mediatek: add MT7988 ethwarp reset
- IDs
-
-Add reset ID for ethwarp subsystem allowing to reset the built-in
-Ethernet switch of the MediaTek MT7988 SoC.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- include/dt-bindings/reset/mediatek,mt7988-resets.h | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
- create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h
-
---- /dev/null
-+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
-@@ -0,0 +1,13 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
-+ * Author: Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988
-+#define _DT_BINDINGS_RESET_CONTROLLER_MT7988
-+
-+/* ETHWARP resets */
-+#define MT7988_ETHWARP_RST_SWITCH 0
-+
-+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
+++ /dev/null
-From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 17 Dec 2023 21:49:33 +0000
-Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs
-
-Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg,
-ethernet and xfipll subsystem clocks.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../dt-bindings/clock/mediatek,mt7988-clk.h | 280 ++++++++++++++++++
- 1 file changed, 280 insertions(+)
- create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h
-
---- /dev/null
-+++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h
-@@ -0,0 +1,280 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
-+ */
-+
-+#ifndef _DT_BINDINGS_CLK_MT7988_H
-+#define _DT_BINDINGS_CLK_MT7988_H
-+
-+/* APMIXEDSYS */
-+
-+#define CLK_APMIXED_NETSYSPLL 0
-+#define CLK_APMIXED_MPLL 1
-+#define CLK_APMIXED_MMPLL 2
-+#define CLK_APMIXED_APLL2 3
-+#define CLK_APMIXED_NET1PLL 4
-+#define CLK_APMIXED_NET2PLL 5
-+#define CLK_APMIXED_WEDMCUPLL 6
-+#define CLK_APMIXED_SGMPLL 7
-+#define CLK_APMIXED_ARM_B 8
-+#define CLK_APMIXED_CCIPLL2_B 9
-+#define CLK_APMIXED_USXGMIIPLL 10
-+#define CLK_APMIXED_MSDCPLL 11
-+
-+/* TOPCKGEN */
-+
-+#define CLK_TOP_XTAL 0
-+#define CLK_TOP_XTAL_D2 1
-+#define CLK_TOP_RTC_32K 2
-+#define CLK_TOP_RTC_32P7K 3
-+#define CLK_TOP_MPLL_D2 4
-+#define CLK_TOP_MPLL_D3_D2 5
-+#define CLK_TOP_MPLL_D4 6
-+#define CLK_TOP_MPLL_D8 7
-+#define CLK_TOP_MPLL_D8_D2 8
-+#define CLK_TOP_MMPLL_D2 9
-+#define CLK_TOP_MMPLL_D3_D5 10
-+#define CLK_TOP_MMPLL_D4 11
-+#define CLK_TOP_MMPLL_D6_D2 12
-+#define CLK_TOP_MMPLL_D8 13
-+#define CLK_TOP_APLL2_D4 14
-+#define CLK_TOP_NET1PLL_D4 15
-+#define CLK_TOP_NET1PLL_D5 16
-+#define CLK_TOP_NET1PLL_D5_D2 17
-+#define CLK_TOP_NET1PLL_D5_D4 18
-+#define CLK_TOP_NET1PLL_D8 19
-+#define CLK_TOP_NET1PLL_D8_D2 20
-+#define CLK_TOP_NET1PLL_D8_D4 21
-+#define CLK_TOP_NET1PLL_D8_D8 22
-+#define CLK_TOP_NET1PLL_D8_D16 23
-+#define CLK_TOP_NET2PLL_D2 24
-+#define CLK_TOP_NET2PLL_D4 25
-+#define CLK_TOP_NET2PLL_D4_D4 26
-+#define CLK_TOP_NET2PLL_D4_D8 27
-+#define CLK_TOP_NET2PLL_D6 28
-+#define CLK_TOP_NET2PLL_D8 29
-+#define CLK_TOP_NETSYS_SEL 30
-+#define CLK_TOP_NETSYS_500M_SEL 31
-+#define CLK_TOP_NETSYS_2X_SEL 32
-+#define CLK_TOP_NETSYS_GSW_SEL 33
-+#define CLK_TOP_ETH_GMII_SEL 34
-+#define CLK_TOP_NETSYS_MCU_SEL 35
-+#define CLK_TOP_NETSYS_PAO_2X_SEL 36
-+#define CLK_TOP_EIP197_SEL 37
-+#define CLK_TOP_AXI_INFRA_SEL 38
-+#define CLK_TOP_UART_SEL 39
-+#define CLK_TOP_EMMC_250M_SEL 40
-+#define CLK_TOP_EMMC_400M_SEL 41
-+#define CLK_TOP_SPI_SEL 42
-+#define CLK_TOP_SPIM_MST_SEL 43
-+#define CLK_TOP_NFI1X_SEL 44
-+#define CLK_TOP_SPINFI_SEL 45
-+#define CLK_TOP_PWM_SEL 46
-+#define CLK_TOP_I2C_SEL 47
-+#define CLK_TOP_PCIE_MBIST_250M_SEL 48
-+#define CLK_TOP_PEXTP_TL_SEL 49
-+#define CLK_TOP_PEXTP_TL_P1_SEL 50
-+#define CLK_TOP_PEXTP_TL_P2_SEL 51
-+#define CLK_TOP_PEXTP_TL_P3_SEL 52
-+#define CLK_TOP_USB_SYS_SEL 53
-+#define CLK_TOP_USB_SYS_P1_SEL 54
-+#define CLK_TOP_USB_XHCI_SEL 55
-+#define CLK_TOP_USB_XHCI_P1_SEL 56
-+#define CLK_TOP_USB_FRMCNT_SEL 57
-+#define CLK_TOP_USB_FRMCNT_P1_SEL 58
-+#define CLK_TOP_AUD_SEL 59
-+#define CLK_TOP_A1SYS_SEL 60
-+#define CLK_TOP_AUD_L_SEL 61
-+#define CLK_TOP_A_TUNER_SEL 62
-+#define CLK_TOP_SSPXTP_SEL 63
-+#define CLK_TOP_USB_PHY_SEL 64
-+#define CLK_TOP_USXGMII_SBUS_0_SEL 65
-+#define CLK_TOP_USXGMII_SBUS_1_SEL 66
-+#define CLK_TOP_SGM_0_SEL 67
-+#define CLK_TOP_SGM_SBUS_0_SEL 68
-+#define CLK_TOP_SGM_1_SEL 69
-+#define CLK_TOP_SGM_SBUS_1_SEL 70
-+#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
-+#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
-+#define CLK_TOP_SYSAXI_SEL 73
-+#define CLK_TOP_SYSAPB_SEL 74
-+#define CLK_TOP_ETH_REFCK_50M_SEL 75
-+#define CLK_TOP_ETH_SYS_200M_SEL 76
-+#define CLK_TOP_ETH_SYS_SEL 77
-+#define CLK_TOP_ETH_XGMII_SEL 78
-+#define CLK_TOP_BUS_TOPS_SEL 79
-+#define CLK_TOP_NPU_TOPS_SEL 80
-+#define CLK_TOP_DRAMC_SEL 81
-+#define CLK_TOP_DRAMC_MD32_SEL 82
-+#define CLK_TOP_INFRA_F26M_SEL 83
-+#define CLK_TOP_PEXTP_P0_SEL 84
-+#define CLK_TOP_PEXTP_P1_SEL 85
-+#define CLK_TOP_PEXTP_P2_SEL 86
-+#define CLK_TOP_PEXTP_P3_SEL 87
-+#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
-+#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
-+#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
-+#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
-+#define CLK_TOP_CKM_SEL 92
-+#define CLK_TOP_DA_SEL 93
-+#define CLK_TOP_PEXTP_SEL 94
-+#define CLK_TOP_TOPS_P2_26M_SEL 95
-+#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
-+#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
-+#define CLK_TOP_MACSEC_SEL 98
-+#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
-+#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
-+#define CLK_TOP_NETSYS_WARP_SEL 101
-+#define CLK_TOP_ETH_MII_SEL 102
-+#define CLK_TOP_NPU_SEL 103
-+#define CLK_TOP_AUD_I2S_M 104
-+
-+/* MCUSYS */
-+
-+#define CLK_MCU_BUS_DIV_SEL 0
-+#define CLK_MCU_ARM_DIV_SEL 1
-+
-+/* INFRACFG_AO */
-+
-+#define CLK_INFRA_MUX_UART0_SEL 0
-+#define CLK_INFRA_MUX_UART1_SEL 1
-+#define CLK_INFRA_MUX_UART2_SEL 2
-+#define CLK_INFRA_MUX_SPI0_SEL 3
-+#define CLK_INFRA_MUX_SPI1_SEL 4
-+#define CLK_INFRA_MUX_SPI2_SEL 5
-+#define CLK_INFRA_PWM_SEL 6
-+#define CLK_INFRA_PWM_CK1_SEL 7
-+#define CLK_INFRA_PWM_CK2_SEL 8
-+#define CLK_INFRA_PWM_CK3_SEL 9
-+#define CLK_INFRA_PWM_CK4_SEL 10
-+#define CLK_INFRA_PWM_CK5_SEL 11
-+#define CLK_INFRA_PWM_CK6_SEL 12
-+#define CLK_INFRA_PWM_CK7_SEL 13
-+#define CLK_INFRA_PWM_CK8_SEL 14
-+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
-+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
-+#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
-+#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
-+
-+/* INFRACFG */
-+
-+#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
-+#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
-+#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
-+#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
-+#define CLK_INFRA_66M_GPT_BCK 23
-+#define CLK_INFRA_66M_PWM_HCK 24
-+#define CLK_INFRA_66M_PWM_BCK 25
-+#define CLK_INFRA_66M_PWM_CK1 26
-+#define CLK_INFRA_66M_PWM_CK2 27
-+#define CLK_INFRA_66M_PWM_CK3 28
-+#define CLK_INFRA_66M_PWM_CK4 29
-+#define CLK_INFRA_66M_PWM_CK5 30
-+#define CLK_INFRA_66M_PWM_CK6 31
-+#define CLK_INFRA_66M_PWM_CK7 32
-+#define CLK_INFRA_66M_PWM_CK8 33
-+#define CLK_INFRA_133M_CQDMA_BCK 34
-+#define CLK_INFRA_66M_AUD_SLV_BCK 35
-+#define CLK_INFRA_AUD_26M 36
-+#define CLK_INFRA_AUD_L 37
-+#define CLK_INFRA_AUD_AUD 38
-+#define CLK_INFRA_AUD_EG2 39
-+#define CLK_INFRA_DRAMC_F26M 40
-+#define CLK_INFRA_133M_DBG_ACKM 41
-+#define CLK_INFRA_66M_AP_DMA_BCK 42
-+#define CLK_INFRA_66M_SEJ_BCK 43
-+#define CLK_INFRA_PRE_CK_SEJ_F13M 44
-+#define CLK_INFRA_26M_THERM_SYSTEM 45
-+#define CLK_INFRA_I2C_BCK 46
-+#define CLK_INFRA_52M_UART0_CK 47
-+#define CLK_INFRA_52M_UART1_CK 48
-+#define CLK_INFRA_52M_UART2_CK 49
-+#define CLK_INFRA_NFI 50
-+#define CLK_INFRA_SPINFI 51
-+#define CLK_INFRA_66M_NFI_HCK 52
-+#define CLK_INFRA_104M_SPI0 53
-+#define CLK_INFRA_104M_SPI1 54
-+#define CLK_INFRA_104M_SPI2_BCK 55
-+#define CLK_INFRA_66M_SPI0_HCK 56
-+#define CLK_INFRA_66M_SPI1_HCK 57
-+#define CLK_INFRA_66M_SPI2_HCK 58
-+#define CLK_INFRA_66M_FLASHIF_AXI 59
-+#define CLK_INFRA_RTC 60
-+#define CLK_INFRA_26M_ADC_BCK 61
-+#define CLK_INFRA_RC_ADC 62
-+#define CLK_INFRA_MSDC400 63
-+#define CLK_INFRA_MSDC2_HCK 64
-+#define CLK_INFRA_133M_MSDC_0_HCK 65
-+#define CLK_INFRA_66M_MSDC_0_HCK 66
-+#define CLK_INFRA_133M_CPUM_BCK 67
-+#define CLK_INFRA_BIST2FPC 68
-+#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
-+#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
-+#define CLK_INFRA_133M_USB_HCK 71
-+#define CLK_INFRA_133M_USB_HCK_CK_P1 72
-+#define CLK_INFRA_66M_USB_HCK 73
-+#define CLK_INFRA_66M_USB_HCK_CK_P1 74
-+#define CLK_INFRA_USB_SYS 75
-+#define CLK_INFRA_USB_SYS_CK_P1 76
-+#define CLK_INFRA_USB_REF 77
-+#define CLK_INFRA_USB_CK_P1 78
-+#define CLK_INFRA_USB_FRMCNT 79
-+#define CLK_INFRA_USB_FRMCNT_CK_P1 80
-+#define CLK_INFRA_USB_PIPE 81
-+#define CLK_INFRA_USB_PIPE_CK_P1 82
-+#define CLK_INFRA_USB_UTMI 83
-+#define CLK_INFRA_USB_UTMI_CK_P1 84
-+#define CLK_INFRA_USB_XHCI 85
-+#define CLK_INFRA_USB_XHCI_CK_P1 86
-+#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
-+#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
-+#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
-+#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
-+#define CLK_INFRA_PCIE_PIPE_P0 91
-+#define CLK_INFRA_PCIE_PIPE_P1 92
-+#define CLK_INFRA_PCIE_PIPE_P2 93
-+#define CLK_INFRA_PCIE_PIPE_P3 94
-+#define CLK_INFRA_133M_PCIE_CK_P0 95
-+#define CLK_INFRA_133M_PCIE_CK_P1 96
-+#define CLK_INFRA_133M_PCIE_CK_P2 97
-+#define CLK_INFRA_133M_PCIE_CK_P3 98
-+
-+/* ETHDMA */
-+
-+#define CLK_ETHDMA_XGP1_EN 0
-+#define CLK_ETHDMA_XGP2_EN 1
-+#define CLK_ETHDMA_XGP3_EN 2
-+#define CLK_ETHDMA_FE_EN 3
-+#define CLK_ETHDMA_GP2_EN 4
-+#define CLK_ETHDMA_GP1_EN 5
-+#define CLK_ETHDMA_GP3_EN 6
-+#define CLK_ETHDMA_ESW_EN 7
-+#define CLK_ETHDMA_CRYPT0_EN 8
-+#define CLK_ETHDMA_NR_CLK 9
-+
-+/* SGMIISYS_0 */
-+
-+#define CLK_SGM0_TX_EN 0
-+#define CLK_SGM0_RX_EN 1
-+#define CLK_SGMII0_NR_CLK 2
-+
-+/* SGMIISYS_1 */
-+
-+#define CLK_SGM1_TX_EN 0
-+#define CLK_SGM1_RX_EN 1
-+#define CLK_SGMII1_NR_CLK 2
-+
-+/* ETHWARP */
-+
-+#define CLK_ETHWARP_WOCPU2_EN 0
-+#define CLK_ETHWARP_WOCPU1_EN 1
-+#define CLK_ETHWARP_WOCPU0_EN 2
-+#define CLK_ETHWARP_NR_CLK 3
-+
-+/* XFIPLL */
-+#define CLK_XFIPLL_PLL 0
-+#define CLK_XFIPLL_PLL_EN 1
-+
-+#endif /* _DT_BINDINGS_CLK_MT7988_H */
+++ /dev/null
-From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 17 Dec 2023 21:49:55 +0000
-Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of
- MT7988
-
-Add various clock controllers found in the MT7988 SoC to existing
-bindings (if applicable) and add files for the new ethwarp, mcusys
-and xfi-pll clock controllers not previously present in any SoC.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- .../arm/mediatek/mediatek,infracfg.yaml | 1 +
- .../bindings/clock/mediatek,apmixedsys.yaml | 1 +
- .../bindings/clock/mediatek,ethsys.yaml | 1 +
- .../clock/mediatek,mt7988-ethwarp.yaml | 52 +++++++++++++++
- .../clock/mediatek,mt7988-xfi-pll.yaml | 48 ++++++++++++++
- .../bindings/clock/mediatek,topckgen.yaml | 2 +
- .../bindings/net/pcs/mediatek,sgmiisys.yaml | 65 ++++++++++++++++---
- 7 files changed, 161 insertions(+), 9 deletions(-)
- create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
- create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
-
---- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
-+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
-@@ -30,6 +30,7 @@ properties:
- - mediatek,mt7629-infracfg
- - mediatek,mt7981-infracfg
- - mediatek,mt7986-infracfg
-+ - mediatek,mt7988-infracfg
- - mediatek,mt8135-infracfg
- - mediatek,mt8167-infracfg
- - mediatek,mt8173-infracfg
---- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
-+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
-@@ -22,6 +22,7 @@ properties:
- - mediatek,mt7622-apmixedsys
- - mediatek,mt7981-apmixedsys
- - mediatek,mt7986-apmixedsys
-+ - mediatek,mt7988-apmixedsys
- - mediatek,mt8135-apmixedsys
- - mediatek,mt8173-apmixedsys
- - mediatek,mt8516-apmixedsys
---- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
-+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
-@@ -22,6 +22,7 @@ properties:
- - mediatek,mt7629-ethsys
- - mediatek,mt7981-ethsys
- - mediatek,mt7986-ethsys
-+ - mediatek,mt7988-ethsys
- - const: syscon
- - items:
- - const: mediatek,mt7623-ethsys
---- /dev/null
-+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
-@@ -0,0 +1,52 @@
-+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek MT7988 ethwarp Controller
-+
-+maintainers:
-+ - Daniel Golle <daniel@makrotopia.org>
-+
-+description:
-+ The Mediatek MT7988 ethwarp controller provides clocks and resets for the
-+ Ethernet related subsystems found the MT7988 SoC.
-+ The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
-+
-+properties:
-+ compatible:
-+ items:
-+ - const: mediatek,mt7988-ethwarp
-+
-+ reg:
-+ maxItems: 1
-+
-+ '#clock-cells':
-+ const: 1
-+
-+ '#reset-cells':
-+ const: 1
-+
-+required:
-+ - compatible
-+ - reg
-+ - '#clock-cells'
-+ - '#reset-cells'
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ #include <dt-bindings/reset/ti-syscon.h>
-+ soc {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
-+ clock-controller@15031000 {
-+ compatible = "mediatek,mt7988-ethwarp";
-+ reg = <0 0x15031000 0 0x1000>;
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ };
-+ };
---- /dev/null
-+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
-@@ -0,0 +1,48 @@
-+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek MT7988 XFI PLL Clock Controller
-+
-+maintainers:
-+ - Daniel Golle <daniel@makrotopia.org>
-+
-+description:
-+ The MediaTek XFI PLL controller provides the 156.25MHz clock for the
-+ Ethernet SerDes PHY from the 40MHz top_xtal clock.
-+
-+properties:
-+ compatible:
-+ const: mediatek,mt7988-xfi-pll
-+
-+ reg:
-+ maxItems: 1
-+
-+ resets:
-+ maxItems: 1
-+
-+ '#clock-cells':
-+ const: 1
-+
-+required:
-+ - compatible
-+ - reg
-+ - resets
-+ - '#clock-cells'
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ soc {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ clock-controller@11f40000 {
-+ compatible = "mediatek,mt7988-xfi-pll";
-+ reg = <0 0x11f40000 0 0x1000>;
-+ resets = <&watchdog 16>;
-+ #clock-cells = <1>;
-+ };
-+ };
---- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
-+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
-@@ -37,6 +37,8 @@ properties:
- - mediatek,mt7629-topckgen
- - mediatek,mt7981-topckgen
- - mediatek,mt7986-topckgen
-+ - mediatek,mt7988-mcusys
-+ - mediatek,mt7988-topckgen
- - mediatek,mt8167-topckgen
- - mediatek,mt8183-topckgen
- - const: syscon
---- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
-@@ -15,15 +15,22 @@ description:
-
- properties:
- compatible:
-- items:
-- - enum:
-- - mediatek,mt7622-sgmiisys
-- - mediatek,mt7629-sgmiisys
-- - mediatek,mt7981-sgmiisys_0
-- - mediatek,mt7981-sgmiisys_1
-- - mediatek,mt7986-sgmiisys_0
-- - mediatek,mt7986-sgmiisys_1
-- - const: syscon
-+ oneOf:
-+ - items:
-+ - enum:
-+ - mediatek,mt7622-sgmiisys
-+ - mediatek,mt7629-sgmiisys
-+ - mediatek,mt7981-sgmiisys_0
-+ - mediatek,mt7981-sgmiisys_1
-+ - mediatek,mt7986-sgmiisys_0
-+ - mediatek,mt7986-sgmiisys_1
-+ - const: syscon
-+ - items:
-+ - enum:
-+ - mediatek,mt7988-sgmiisys0
-+ - mediatek,mt7988-sgmiisys1
-+ - const: simple-mfd
-+ - const: syscon
-
- reg:
- maxItems: 1
-@@ -35,11 +42,51 @@ properties:
- description: Invert polarity of the SGMII data lanes
- type: boolean
-
-+ pcs:
-+ type: object
-+ description: MediaTek LynxI HSGMII PCS
-+ properties:
-+ compatible:
-+ const: mediatek,mt7988-sgmii
-+
-+ clocks:
-+ maxItems: 3
-+
-+ clock-names:
-+ items:
-+ - const: sgmii_sel
-+ - const: sgmii_tx
-+ - const: sgmii_rx
-+
-+ required:
-+ - compatible
-+ - clocks
-+ - clock-names
-+
-+ additionalProperties: false
-+
- required:
- - compatible
- - reg
- - '#clock-cells'
-
-+allOf:
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ enum:
-+ - mediatek,mt7988-sgmiisys0
-+ - mediatek,mt7988-sgmiisys1
-+
-+ then:
-+ required:
-+ - pcs
-+
-+ else:
-+ properties:
-+ pcs: false
-+
- additionalProperties: false
-
- examples:
+++ /dev/null
-From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 17 Dec 2023 21:50:07 +0000
-Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
-
-Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
-of the previously hardcoded PCW_CHG_MASK macro if set.
-This will needed for clocks on the MT7988 SoC.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/clk-pll.c | 5 +++--
- drivers/clk/mediatek/clk-pll.h | 1 +
- 2 files changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/mediatek/clk-pll.c
-+++ b/drivers/clk/mediatek/clk-pll.c
-@@ -23,7 +23,7 @@
- #define CON0_BASE_EN BIT(0)
- #define CON0_PWR_ON BIT(0)
- #define CON0_ISO_EN BIT(1)
--#define PCW_CHG_MASK BIT(31)
-+#define PCW_CHG_BIT 31
-
- #define AUDPLL_TUNER_EN BIT(31)
-
-@@ -141,7 +141,8 @@ static void mtk_pll_set_rate_regs(struct
- pll->data->pcw_shift);
- val |= pcw << pll->data->pcw_shift;
- writel(val, pll->pcw_addr);
-- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
-+ chg = readl(pll->pcw_chg_addr) |
-+ BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
- writel(chg, pll->pcw_chg_addr);
- if (pll->tuner_addr)
- writel(val + 1, pll->tuner_addr);
---- a/drivers/clk/mediatek/clk-pll.h
-+++ b/drivers/clk/mediatek/clk-pll.h
-@@ -46,6 +46,7 @@ struct mtk_pll_data {
- const char *parent_name;
- u32 en_reg;
- u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
-+ u8 pcw_chg_bit;
- };
-
- int mtk_clk_register_plls(struct device_node *node,
+++ /dev/null
-From 4b4719437d85f0173d344f2c76fa1a5b7f7d184b Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 17 Dec 2023 21:50:15 +0000
-Subject: [PATCH 4/4] clk: mediatek: add drivers for MT7988 SoC
-
-Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
-typical MediaTek designs.
-
-Also add driver for XFIPLL clock generating the 156.25MHz clock for
-the XFI SerDes. It needs an undocumented software workaround and has
-an unknown internal design.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org
-[sboyd@kernel.org: Add module license to infracfg file]
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mediatek/Kconfig | 9 +
- drivers/clk/mediatek/Makefile | 5 +
- drivers/clk/mediatek/clk-mt7988-apmixed.c | 114 ++++++++
- drivers/clk/mediatek/clk-mt7988-eth.c | 150 ++++++++++
- drivers/clk/mediatek/clk-mt7988-infracfg.c | 275 +++++++++++++++++
- drivers/clk/mediatek/clk-mt7988-topckgen.c | 325 +++++++++++++++++++++
- drivers/clk/mediatek/clk-mt7988-xfipll.c | 82 ++++++
- 7 files changed, 960 insertions(+)
- create mode 100644 drivers/clk/mediatek/clk-mt7988-apmixed.c
- create mode 100644 drivers/clk/mediatek/clk-mt7988-eth.c
- create mode 100644 drivers/clk/mediatek/clk-mt7988-infracfg.c
- create mode 100644 drivers/clk/mediatek/clk-mt7988-topckgen.c
- create mode 100644 drivers/clk/mediatek/clk-mt7988-xfipll.c
-
---- a/drivers/clk/mediatek/Kconfig
-+++ b/drivers/clk/mediatek/Kconfig
-@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS
- This driver adds support for clocks for Ethernet and SGMII
- required on MediaTek MT7986 SoC.
-
-+config COMMON_CLK_MT7988
-+ tristate "Clock driver for MediaTek MT7988"
-+ depends on ARCH_MEDIATEK || COMPILE_TEST
-+ select COMMON_CLK_MEDIATEK
-+ default ARCH_MEDIATEK
-+ help
-+ This driver supports MediaTek MT7988 basic clocks and clocks
-+ required for various periperals found on this SoC.
-+
- config COMMON_CLK_MT8135
- bool "Clock driver for MediaTek MT8135"
- depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
---- a/drivers/clk/mediatek/Makefile
-+++ b/drivers/clk/mediatek/Makefile
-@@ -60,6 +60,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
- obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
- obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
-+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o
- obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
- obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
- obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988-apmixed.c
-@@ -0,0 +1,114 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "clk-mux.h"
-+#include "clk-pll.h"
-+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+
-+#define MT7988_PLL_FMAX (2500UL * MHZ)
-+#define MT7988_PCW_CHG_BIT 2
-+
-+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \
-+ _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift, \
-+ _pcw_chg_reg) \
-+ { \
-+ .id = _id, \
-+ .name = _name, \
-+ .reg = _reg, \
-+ .pwr_reg = _pwr_reg, \
-+ .en_mask = _en_mask, \
-+ .flags = _flags, \
-+ .rst_bar_mask = BIT(_rst_bar_mask), \
-+ .fmax = MT7988_PLL_FMAX, \
-+ .pcwbits = _pcwbits, \
-+ .pd_reg = _pd_reg, \
-+ .pd_shift = _pd_shift, \
-+ .tuner_reg = _tuner_reg, \
-+ .tuner_en_reg = _tuner_en_reg, \
-+ .tuner_en_bit = _tuner_en_bit, \
-+ .pcw_reg = _pcw_reg, \
-+ .pcw_shift = _pcw_shift, \
-+ .pcw_chg_reg = _pcw_chg_reg, \
-+ .pcw_chg_bit = MT7988_PCW_CHG_BIT, \
-+ .parent_name = "clkxtal", \
-+ }
-+
-+static const struct mtk_pll_data plls[] = {
-+ PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
-+ 0, 0, 0x0108, 0, 0x0104),
-+ PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
-+ 0, 0, 0, 0x0118, 0, 0x0114),
-+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
-+ 0, 0, 0, 0x0128, 0, 0x0124),
-+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
-+ 0x0700, 1, 0x0138, 0, 0x0134),
-+ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
-+ 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
-+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23,
-+ 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154),
-+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,
-+ 0, 0, 0x0168, 0, 0x0164),
-+ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,
-+ 0x0178, 0, 0x0174),
-+ PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32,
-+ 0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204),
-+ PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,
-+ 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
-+ PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,
-+ 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
-+ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0,
-+ 0, 0x0318, 0, 0x0314),
-+};
-+
-+static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
-+ { .compatible = "mediatek,mt7988-apmixedsys" },
-+ { /* sentinel */ }
-+};
-+
-+static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
-+{
-+ struct clk_hw_onecell_data *clk_data;
-+ struct device_node *node = pdev->dev.of_node;
-+ int r;
-+
-+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
-+ if (!clk_data)
-+ return -ENOMEM;
-+
-+ r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-+ if (r)
-+ goto free_apmixed_data;
-+
-+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-+ if (r)
-+ goto unregister_plls;
-+
-+ return r;
-+
-+unregister_plls:
-+ mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
-+free_apmixed_data:
-+ mtk_free_clk_data(clk_data);
-+ return r;
-+}
-+
-+static struct platform_driver clk_mt7988_apmixed_drv = {
-+ .probe = clk_mt7988_apmixed_probe,
-+ .driver = {
-+ .name = "clk-mt7988-apmixed",
-+ .of_match_table = of_match_clk_mt7988_apmixed,
-+ },
-+};
-+builtin_platform_driver(clk_mt7988_apmixed_drv);
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988-eth.c
-@@ -0,0 +1,150 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "reset.h"
-+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
-+
-+static const struct mtk_gate_regs ethdma_cg_regs = {
-+ .set_ofs = 0x30,
-+ .clr_ofs = 0x30,
-+ .sta_ofs = 0x30,
-+};
-+
-+#define GATE_ETHDMA(_id, _name, _parent, _shift) \
-+ { \
-+ .id = _id, \
-+ .name = _name, \
-+ .parent_name = _parent, \
-+ .regs = ðdma_cg_regs, \
-+ .shift = _shift, \
-+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
-+ }
-+
-+static const struct mtk_gate ethdma_clks[] = {
-+ GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
-+ GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
-+ GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
-+ GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
-+ GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
-+ GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
-+ GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
-+ GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
-+ GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29),
-+};
-+
-+static const struct mtk_clk_desc ethdma_desc = {
-+ .clks = ethdma_clks,
-+ .num_clks = ARRAY_SIZE(ethdma_clks),
-+};
-+
-+static const struct mtk_gate_regs sgmii_cg_regs = {
-+ .set_ofs = 0xe4,
-+ .clr_ofs = 0xe4,
-+ .sta_ofs = 0xe4,
-+};
-+
-+#define GATE_SGMII(_id, _name, _parent, _shift) \
-+ { \
-+ .id = _id, \
-+ .name = _name, \
-+ .parent_name = _parent, \
-+ .regs = &sgmii_cg_regs, \
-+ .shift = _shift, \
-+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
-+ }
-+
-+static const struct mtk_gate sgmii0_clks[] = {
-+ GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
-+ GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
-+};
-+
-+static const struct mtk_clk_desc sgmii0_desc = {
-+ .clks = sgmii0_clks,
-+ .num_clks = ARRAY_SIZE(sgmii0_clks),
-+};
-+
-+static const struct mtk_gate sgmii1_clks[] = {
-+ GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
-+ GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
-+};
-+
-+static const struct mtk_clk_desc sgmii1_desc = {
-+ .clks = sgmii1_clks,
-+ .num_clks = ARRAY_SIZE(sgmii1_clks),
-+};
-+
-+static const struct mtk_gate_regs ethwarp_cg_regs = {
-+ .set_ofs = 0x14,
-+ .clr_ofs = 0x14,
-+ .sta_ofs = 0x14,
-+};
-+
-+#define GATE_ETHWARP(_id, _name, _parent, _shift) \
-+ { \
-+ .id = _id, \
-+ .name = _name, \
-+ .parent_name = _parent, \
-+ .regs = ðwarp_cg_regs, \
-+ .shift = _shift, \
-+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
-+ }
-+
-+static const struct mtk_gate ethwarp_clks[] = {
-+ GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13),
-+ GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14),
-+ GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15),
-+};
-+
-+static u16 ethwarp_rst_ofs[] = { 0x8 };
-+
-+static u16 ethwarp_idx_map[] = {
-+ [MT7988_ETHWARP_RST_SWITCH] = 9,
-+};
-+
-+static const struct mtk_clk_rst_desc ethwarp_rst_desc = {
-+ .version = MTK_RST_SIMPLE,
-+ .rst_bank_ofs = ethwarp_rst_ofs,
-+ .rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs),
-+ .rst_idx_map = ethwarp_idx_map,
-+ .rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map),
-+};
-+
-+static const struct mtk_clk_desc ethwarp_desc = {
-+ .clks = ethwarp_clks,
-+ .num_clks = ARRAY_SIZE(ethwarp_clks),
-+ .rst_desc = ðwarp_rst_desc,
-+};
-+
-+static const struct of_device_id of_match_clk_mt7988_eth[] = {
-+ { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc },
-+ { .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc },
-+ { .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc },
-+ { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
-+
-+static struct platform_driver clk_mt7988_eth_drv = {
-+ .driver = {
-+ .name = "clk-mt7988-eth",
-+ .of_match_table = of_match_clk_mt7988_eth,
-+ },
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
-+};
-+module_platform_driver(clk_mt7988_eth_drv);
-+
-+MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
-@@ -0,0 +1,275 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "clk-mux.h"
-+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+
-+static DEFINE_SPINLOCK(mt7988_clk_lock);
-+
-+static const char *const infra_mux_uart0_parents[] __initconst = { "csw_infra_f26m_sel",
-+ "uart_sel" };
-+
-+static const char *const infra_mux_uart1_parents[] __initconst = { "csw_infra_f26m_sel",
-+ "uart_sel" };
-+
-+static const char *const infra_mux_uart2_parents[] __initconst = { "csw_infra_f26m_sel",
-+ "uart_sel" };
-+
-+static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", "spi_sel" };
-+
-+static const char *const infra_mux_spi1_parents[] __initconst = { "i2c_sel", "spim_mst_sel" };
-+
-+static const char *const infra_pwm_bck_parents[] __initconst = { "top_rtc_32p7k",
-+ "csw_infra_f26m_sel", "sysaxi_sel",
-+ "pwm_sel" };
-+
-+static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
-+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_sel"
-+};
-+
-+static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
-+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p1_sel"
-+};
-+
-+static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
-+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p2_sel"
-+};
-+
-+static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
-+ "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", "pextp_tl_p3_sel"
-+};
-+
-+static const struct mtk_mux infra_muxes[] = {
-+ /* MODULE_CLK_SEL_0 */
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
-+ infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
-+ infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
-+ infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
-+ 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
-+ 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
-+ 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
-+ 0x0010, 0x0014, 14, 2, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
-+ 0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
-+ 0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
-+ 0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
-+ 0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
-+ 0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
-+ 0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
-+ 0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
-+ 0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
-+ /* MODULE_CLK_SEL_1 */
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
-+ infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,
-+ -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
-+ infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,
-+ -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
-+ infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,
-+ -1, -1),
-+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
-+ infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,
-+ -1, -1),
-+};
-+
-+static const struct mtk_gate_regs infra0_cg_regs = {
-+ .set_ofs = 0x10,
-+ .clr_ofs = 0x14,
-+ .sta_ofs = 0x18,
-+};
-+
-+static const struct mtk_gate_regs infra1_cg_regs = {
-+ .set_ofs = 0x40,
-+ .clr_ofs = 0x44,
-+ .sta_ofs = 0x48,
-+};
-+
-+static const struct mtk_gate_regs infra2_cg_regs = {
-+ .set_ofs = 0x50,
-+ .clr_ofs = 0x54,
-+ .sta_ofs = 0x58,
-+};
-+
-+static const struct mtk_gate_regs infra3_cg_regs = {
-+ .set_ofs = 0x60,
-+ .clr_ofs = 0x64,
-+ .sta_ofs = 0x68,
-+};
-+
-+#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \
-+ GATE_MTK_FLAGS(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
-+ _flags)
-+
-+#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \
-+ GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
-+ _flags)
-+
-+#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \
-+ GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
-+ _flags)
-+
-+#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \
-+ GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, &mtk_clk_gate_ops_setclr, \
-+ _flags)
-+
-+#define GATE_INFRA0(_id, _name, _parent, _shift) GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
-+
-+#define GATE_INFRA1(_id, _name, _parent, _shift) GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
-+
-+#define GATE_INFRA2(_id, _name, _parent, _shift) GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
-+
-+#define GATE_INFRA3(_id, _name, _parent, _shift) GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
-+
-+static const struct mtk_gate infra_clks[] = {
-+ /* INFRA0 */
-+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, "infra_pcie_peri_ck_26m_ck_p0",
-+ "csw_infra_f26m_sel", 7),
-+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
-+ "csw_infra_f26m_sel", 8),
-+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
-+ "csw_infra_f26m_sel", 9),
-+ GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
-+ "csw_infra_f26m_sel", 10),
-+ /* INFRA1 */
-+ GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", "sysaxi_sel", 0),
-+ GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", "sysaxi_sel", 1),
-+ GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", "infra_pwm_sel", 2),
-+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", "infra_pwm_ck1_sel", 3),
-+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", "infra_pwm_ck2_sel", 4),
-+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", "infra_pwm_ck3_sel", 5),
-+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", "infra_pwm_ck4_sel", 6),
-+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", "infra_pwm_ck5_sel", 7),
-+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", "infra_pwm_ck6_sel", 8),
-+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", "infra_pwm_ck7_sel", 9),
-+ GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", "infra_pwm_ck8_sel", 10),
-+ GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", "sysaxi_sel", 12),
-+ GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", "sysaxi_sel", 13),
-+ GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", "csw_infra_f26m_sel", 14),
-+ GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
-+ GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
-+ GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
-+ GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "csw_infra_f26m_sel", 19,
-+ CLK_IS_CRITICAL),
-+ /* JTAG */
-+ GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", "sysaxi_sel", 20,
-+ CLK_IS_CRITICAL),
-+ GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", "sysaxi_sel", 21),
-+ GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", "sysaxi_sel", 29),
-+ GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", "csw_infra_f26m_sel", 30),
-+ /* INFRA2 */
-+ GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", "csw_infra_f26m_sel",
-+ 0),
-+ GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
-+ GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", "infra_mux_uart0_sel", 3),
-+ GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", "infra_mux_uart1_sel", 4),
-+ GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", "infra_mux_uart2_sel", 5),
-+ GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
-+ GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
-+ GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
-+ CLK_IS_CRITICAL),
-+ GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
-+ CLK_IS_CRITICAL),
-+ GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
-+ GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
-+ GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
-+ CLK_IS_CRITICAL),
-+ GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
-+ GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
-+ GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
-+ GATE_INFRA2_FLAGS(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19, CLK_IS_CRITICAL),
-+ GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", "csw_infra_f26m_sel", 20),
-+ GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", 21),
-+ GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", 22),
-+ GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", 23),
-+ GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", "sysaxi_sel", 24),
-+ GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", "sysaxi_sel", 25),
-+ GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", "sysaxi_sel", 26),
-+ GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
-+ GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
-+ GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
-+ /* INFRA3 */
-+ GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", 0),
-+ GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", "sysaxi_sel", 1),
-+ GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", 2),
-+ GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", "sysaxi_sel", 3),
-+ GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
-+ GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", "usb_sys_p1_sel", 5),
-+ GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
-+ GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
-+ GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", "usb_frmcnt_sel", 8,
-+ CLK_IS_CRITICAL),
-+ GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel",
-+ 9, CLK_IS_CRITICAL),
-+ GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
-+ GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11),
-+ GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
-+ GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13),
-+ GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
-+ GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", "usb_xhci_p1_sel", 15),
-+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
-+ "infra_pcie_gfmux_tl_o_p0_sel", 20),
-+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
-+ "infra_pcie_gfmux_tl_o_p1_sel", 21),
-+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
-+ "infra_pcie_gfmux_tl_o_p2_sel", 22),
-+ GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
-+ "infra_pcie_gfmux_tl_o_p3_sel", 23),
-+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", "top_xtal", 24),
-+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", "top_xtal", 25),
-+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", "top_xtal", 26),
-+ GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", "top_xtal", 27),
-+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", "sysaxi_sel", 28),
-+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", "sysaxi_sel", 29),
-+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", "sysaxi_sel", 30),
-+ GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
-+};
-+
-+static const struct mtk_clk_desc infra_desc = {
-+ .clks = infra_clks,
-+ .num_clks = ARRAY_SIZE(infra_clks),
-+ .mux_clks = infra_muxes,
-+ .num_mux_clks = ARRAY_SIZE(infra_muxes),
-+ .clk_lock = &mt7988_clk_lock,
-+};
-+
-+static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
-+ { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
-+
-+static struct platform_driver clk_mt7988_infracfg_drv = {
-+ .driver = {
-+ .name = "clk-mt7988-infracfg",
-+ .of_match_table = of_match_clk_mt7988_infracfg,
-+ },
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
-+};
-+module_platform_driver(clk_mt7988_infracfg_drv);
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988-topckgen.c
-@@ -0,0 +1,325 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Sam Shih <sam.shih@mediatek.com>
-+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include "clk-mux.h"
-+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+
-+static DEFINE_SPINLOCK(mt7988_clk_lock);
-+
-+static const struct mtk_fixed_clk top_fixed_clks[] = {
-+ FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
-+};
-+
-+static const struct mtk_fixed_factor top_divs[] = {
-+ FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
-+ FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
-+ FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
-+ FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
-+ FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
-+ FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
-+ FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
-+ FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
-+ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
-+ FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
-+ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
-+ FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
-+ FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
-+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
-+ FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
-+ FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
-+ FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
-+ FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
-+ FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
-+ FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
-+ FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
-+ FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
-+ FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
-+ FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
-+ FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
-+ FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
-+ FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
-+ FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
-+ FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
-+};
-+
-+static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", "mmpll_d2" };
-+static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", "net1pll_d5_d2" };
-+static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", "mmpll" };
-+static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", "net1pll_d5" };
-+static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
-+static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", "mmpll",
-+ "net1pll_d4", "net1pll_d5", "mpll" };
-+static const char *const eip197_parents[] = { "top_xtal", "netsyspll", "net2pll",
-+ "mmpll", "net1pll_d4", "net1pll_d5" };
-+static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
-+static const char *const uart_parents[] = { "top_xtal", "mpll_d8", "mpll_d8_d2" };
-+static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", "mmpll_d4" };
-+static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", "mmpll_d2",
-+ "mpll_d2", "mmpll_d4", "net1pll_d8_d2" };
-+static const char *const spi_parents[] = { "top_xtal", "mpll_d2", "mmpll_d4",
-+ "net1pll_d8_d2", "net2pll_d6", "net1pll_d5_d4",
-+ "mpll_d4", "net1pll_d8_d4" };
-+static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", "net1pll_d8_d2", "net2pll_d6",
-+ "mpll_d4", "mmpll_d8", "net1pll_d8_d4", "mpll_d8" };
-+static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", "net1pll_d5_d4",
-+ "mpll_d4", "mmpll_d8", "net1pll_d8_d4",
-+ "mmpll_d6_d2", "mpll_d8" };
-+static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", "net1pll_d5_d4",
-+ "mpll_d4", "mpll_d8_d2", "top_rtc_32k" };
-+static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", "mpll_d4",
-+ "net1pll_d8_d4" };
-+static const char *const pcie_mbist_250m_parents[] = { "top_xtal", "net1pll_d5_d2" };
-+static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", "mmpll_d8",
-+ "mpll_d8_d2", "top_rtc_32k" };
-+static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
-+static const char *const aud_parents[] = { "top_xtal", "apll2" };
-+static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
-+static const char *const aud_l_parents[] = { "top_xtal", "apll2", "mpll_d8_d2" };
-+static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
-+static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", "net1pll_d8_d4" };
-+static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
-+static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
-+static const char *const eth_refck_50m_parents[] = { "top_xtal", "net2pll_d4_d4" };
-+static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
-+static const char *const eth_xgmii_parents[] = { "top_xtal_d2", "net1pll_d8_d8", "net1pll_d8_d16" };
-+static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", "net2pll_d2" };
-+static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
-+static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", "wedmcupll" };
-+static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", "net2pll_d8" };
-+static const char *const mcusys_backup_625m_parents[] = { "top_xtal", "net1pll_d4" };
-+static const char *const macsec_parents[] = { "top_xtal", "sgmpll", "net1pll_d8" };
-+static const char *const netsys_tops_400m_parents[] = { "top_xtal", "net2pll_d2" };
-+static const char *const eth_mii_parents[] = { "top_xtal_d2", "net2pll_d4_d8" };
-+
-+static const struct mtk_mux top_muxes[] = {
-+ /* CLK_CFG_0 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
-+ 0, 2, 7, 0x1c0, 0),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
-+ 0x004, 0x008, 8, 2, 15, 0x1C0, 1),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
-+ 0x004, 0x008, 16, 2, 23, 0x1C0, 2),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
-+ 0x004, 0x008, 24, 2, 31, 0x1C0, 3),
-+ /* CLK_CFG_1 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
-+ 0x018, 0, 1, 7, 0x1C0, 4),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x010,
-+ 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents,
-+ 0x010, 0x014, 0x018, 16, 3, 23, 0x1C0, 6),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x010, 0x014, 0x018,
-+ 24, 3, 31, 0x1c0, 7),
-+ /* CLK_CFG_2 */
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x020,
-+ 0x024, 0x028, 0, 1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, 0x024, 0x028, 8, 2,
-+ 15, 0x1c0, 9),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
-+ 0x024, 0x028, 16, 2, 23, 0x1C0, 10),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x020,
-+ 0x024, 0x028, 24, 3, 31, 0x1C0, 11),
-+ /* CLK_CFG_3 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, 0x034, 0x038, 0, 3, 7,
-+ 0x1c0, 12),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x030, 0x034, 0x038,
-+ 8, 3, 15, 0x1c0, 13),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x030, 0x034, 0x038, 16,
-+ 3, 23, 0x1c0, 14),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x030, 0x034, 0x038,
-+ 24, 3, 31, 0x1c0, 15),
-+ /* CLK_CFG_4 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, 0x044, 0x048, 0, 3, 7,
-+ 0x1c0, 16),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, 0x044, 0x048, 8, 2, 15,
-+ 0x1c0, 17),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
-+ pcie_mbist_250m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", pextp_tl_ck_parents, 0x040,
-+ 0x044, 0x048, 24, 3, 31, 0x1C0, 19),
-+ /* CLK_CFG_5 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", pextp_tl_ck_parents, 0x050,
-+ 0x054, 0x058, 0, 3, 7, 0x1C0, 20),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", pextp_tl_ck_parents, 0x050,
-+ 0x054, 0x058, 8, 3, 15, 0x1C0, 21),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", pextp_tl_ck_parents, 0x050,
-+ 0x054, 0x058, 16, 3, 23, 0x1C0, 22),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x050, 0x054,
-+ 0x058, 24, 1, 31, 0x1C0, 23),
-+ /* CLK_CFG_6 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x060,
-+ 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x060, 0x064,
-+ 0x068, 8, 1, 15, 0x1C0, 25),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x060,
-+ 0x064, 0x068, 16, 1, 23, 0x1C0, 26),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x060,
-+ 0x064, 0x068, 24, 1, 31, 0x1C0, 27),
-+ /* CLK_CFG_7 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents,
-+ 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, 0x074, 0x078, 8, 1, 15,
-+ 0x1c0, 29),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x070, 0x074, 0x078, 16,
-+ 1, 23, 0x1c0, 30),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 24,
-+ 2, 31, 0x1c4, 0),
-+ /* CLK_CFG_8 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x080, 0x084, 0x088,
-+ 0, 1, 7, 0x1c4, 1),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x080, 0x084, 0x088,
-+ 8, 1, 15, 0x1c4, 2),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x080, 0x084,
-+ 0x088, 16, 1, 23, 0x1c4, 3),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
-+ usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
-+ /* CLK_CFG_9 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
-+ usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x090, 0x094, 0x098, 8,
-+ 1, 15, 0x1c4, 6),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
-+ 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x090, 0x094, 0x098, 24,
-+ 1, 31, 0x1c4, 8),
-+ /* CLK_CFG_10 */
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
-+ 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
-+ 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x1C4, 10),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
-+ 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, 0x1C4, 11),
-+ /* CLK_CFG_11 */
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0x0a0,
-+ 0x0a4, 0x0a8, 24, 1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x0b0, 0x0b4,
-+ 0x0b8, 0, 1, 7, 0x1c4, 13, CLK_IS_CRITICAL),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents,
-+ 0x0b0, 0x0b4, 0x0b8, 8, 1, 15, 0x1C4, 14),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents,
-+ 0x0b0, 0x0b4, 0x0b8, 16, 1, 23, 0x1C4, 15),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0x0b0,
-+ 0x0b4, 0x0b8, 24, 1, 31, 0x1C4, 16),
-+ /* CLK_CFG_12 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0x0c0,
-+ 0x0c4, 0x0c8, 0, 2, 7, 0x1C4, 17),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0x0c0, 0x0c4,
-+ 0x0c8, 8, 2, 15, 0x1C4, 18),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0x0c0, 0x0c4,
-+ 0x0c8, 16, 1, 23, 0x1C4, 19),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0x0c0, 0x0c4,
-+ 0x0c8, 24, 1, 31, 0x1C4, 20, CLK_IS_CRITICAL),
-+ /* CLK_CFG_13 */
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
-+ 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
-+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
-+ 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0x0d0, 0x0d4,
-+ 0x0d8, 16, 1, 23, 0x1C4, 23),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0x0d0, 0x0d4,
-+ 0x0d8, 24, 1, 31, 0x1C4, 24),
-+ /* CLK_CFG_14 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0x0e0, 0x0e4,
-+ 0x0e8, 0, 1, 7, 0x1C4, 25),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0x0e0, 0x0e4,
-+ 0x0e8, 8, 1, 15, 0x1C4, 26),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents,
-+ 0x0e0, 0x0e4, 0x0e8, 16, 1, 23, 0x1C4, 27),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents,
-+ 0x0e0, 0x0e4, 0x0e8, 24, 1, 31, 0x1C4, 28),
-+ /* CLK_CFG_15 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents,
-+ 0x0f0, 0x0f4, 0x0f8, 0, 1, 7, 0x1C4, 29),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents,
-+ 0x0f0, 0x0f4, 0x0f8, 8, 1, 15, 0x1C4, 30),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, 0x0f4, 0x0f8, 16, 1,
-+ 23, 0x1c8, 0),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1,
-+ 31, 0x1C8, 1),
-+ /* CLK_CFG_16 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x0100, 0x104, 0x108,
-+ 0, 1, 7, 0x1c8, 2),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x0100,
-+ 0x104, 0x108, 8, 1, 15, 0x1C8, 3),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
-+ mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, 16, 1, 23, 0x1C8, 4),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
-+ pcie_mbist_250m_parents, 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
-+ /* CLK_CFG_17 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x0110, 0x114, 0x118,
-+ 0, 2, 7, 0x1c8, 6),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
-+ netsys_tops_400m_parents, 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
-+ pcie_mbist_250m_parents, 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x0110,
-+ 0x114, 0x118, 24, 2, 31, 0x1C8, 9),
-+ /* CLK_CFG_18 */
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x0120, 0x124,
-+ 0x128, 0, 1, 7, 0x1c8, 10),
-+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x0120, 0x124, 0x128,
-+ 8, 2, 15, 0x1c8, 11),
-+};
-+
-+static const struct mtk_composite top_aud_divs[] = {
-+ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, 8, 8),
-+};
-+
-+static const struct mtk_clk_desc topck_desc = {
-+ .fixed_clks = top_fixed_clks,
-+ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
-+ .factor_clks = top_divs,
-+ .num_factor_clks = ARRAY_SIZE(top_divs),
-+ .mux_clks = top_muxes,
-+ .num_mux_clks = ARRAY_SIZE(top_muxes),
-+ .composite_clks = top_aud_divs,
-+ .num_composite_clks = ARRAY_SIZE(top_aud_divs),
-+ .clk_lock = &mt7988_clk_lock,
-+};
-+
-+static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", "net1pll_d4" };
-+
-+static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", "net1pll_d4" };
-+
-+static struct mtk_composite mcu_muxes[] = {
-+ /* bus_pll_divider_cfg */
-+ MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", mcu_bus_div_parents, 0x7C0, 9, 2, -1,
-+ CLK_IS_CRITICAL),
-+ /* mp2_pll_divider_cfg */
-+ MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", mcu_arm_div_parents, 0x7A8, 9, 2, -1,
-+ CLK_IS_CRITICAL),
-+};
-+
-+static const struct mtk_clk_desc mcusys_desc = {
-+ .composite_clks = mcu_muxes,
-+ .num_composite_clks = ARRAY_SIZE(mcu_muxes),
-+};
-+
-+static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
-+ { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
-+ { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
-+
-+static struct platform_driver clk_mt7988_topckgen_drv = {
-+ .probe = mtk_clk_simple_probe,
-+ .remove = mtk_clk_simple_remove,
-+ .driver = {
-+ .name = "clk-mt7988-topckgen",
-+ .of_match_table = of_match_clk_mt7988_topckgen,
-+ },
-+};
-+module_platform_driver(clk_mt7988_topckgen_drv);
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/clk/mediatek/clk-mt7988-xfipll.c
-@@ -0,0 +1,82 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/clk-provider.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include "clk-mtk.h"
-+#include "clk-gate.h"
-+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+
-+/* Register to control USXGMII XFI PLL analog */
-+#define XFI_PLL_ANA_GLB8 0x108
-+#define RG_XFI_PLL_ANA_SWWA 0x02283248
-+
-+static const struct mtk_gate_regs xfipll_cg_regs = {
-+ .set_ofs = 0x8,
-+ .clr_ofs = 0x8,
-+ .sta_ofs = 0x8,
-+};
-+
-+#define GATE_XFIPLL(_id, _name, _parent, _shift) \
-+ { \
-+ .id = _id, \
-+ .name = _name, \
-+ .parent_name = _parent, \
-+ .regs = &xfipll_cg_regs, \
-+ .shift = _shift, \
-+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
-+ }
-+
-+static const struct mtk_fixed_factor xfipll_divs[] = {
-+ FACTOR(CLK_XFIPLL_PLL, "xfipll_pll", "top_xtal", 125, 32),
-+};
-+
-+static const struct mtk_gate xfipll_clks[] = {
-+ GATE_XFIPLL(CLK_XFIPLL_PLL_EN, "xfipll_pll_en", "xfipll_pll", 31),
-+};
-+
-+static const struct mtk_clk_desc xfipll_desc = {
-+ .clks = xfipll_clks,
-+ .num_clks = ARRAY_SIZE(xfipll_clks),
-+ .factor_clks = xfipll_divs,
-+ .num_factor_clks = ARRAY_SIZE(xfipll_divs),
-+};
-+
-+static int clk_mt7988_xfipll_probe(struct platform_device *pdev)
-+{
-+ struct device_node *node = pdev->dev.of_node;
-+ void __iomem *base = of_iomap(node, 0);
-+
-+ if (!base)
-+ return -ENOMEM;
-+
-+ /* Apply software workaround for USXGMII PLL TCL issue */
-+ writel(RG_XFI_PLL_ANA_SWWA, base + XFI_PLL_ANA_GLB8);
-+ iounmap(base);
-+
-+ return mtk_clk_simple_probe(pdev);
-+};
-+
-+static const struct of_device_id of_match_clk_mt7988_xfipll[] = {
-+ { .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_xfipll);
-+
-+static struct platform_driver clk_mt7988_xfipll_drv = {
-+ .driver = {
-+ .name = "clk-mt7988-xfipll",
-+ .of_match_table = of_match_clk_mt7988_xfipll,
-+ },
-+ .probe = clk_mt7988_xfipll_probe,
-+ .remove = mtk_clk_simple_remove,
-+};
-+module_platform_driver(clk_mt7988_xfipll_drv);
-+
-+MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Wed, 17 Jan 2024 19:41:11 +0100
-Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988
-
-Infracfg can also operate as reset controller, add support for it.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
---- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
-+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
-@@ -14,6 +14,10 @@
- #include "clk-gate.h"
- #include "clk-mux.h"
- #include <dt-bindings/clock/mediatek,mt7988-clk.h>
-+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
-+
-+#define MT7988_INFRA_RST0_SET_OFFSET 0x70
-+#define MT7988_INFRA_RST1_SET_OFFSET 0x80
-
- static DEFINE_SPINLOCK(mt7988_clk_lock);
-
-@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[
- GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
- };
-
-+static u16 infra_rst_ofs[] = {
-+ MT7988_INFRA_RST0_SET_OFFSET,
-+ MT7988_INFRA_RST1_SET_OFFSET,
-+};
-+
-+static u16 infra_idx_map[] = {
-+ [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
-+ [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
-+};
-+
-+static struct mtk_clk_rst_desc infra_rst_desc = {
-+ .version = MTK_RST_SET_CLR,
-+ .rst_bank_ofs = infra_rst_ofs,
-+ .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
-+ .rst_idx_map = infra_idx_map,
-+ .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map),
-+};
-+
- static const struct mtk_clk_desc infra_desc = {
- .clks = infra_clks,
- .num_clks = ARRAY_SIZE(infra_clks),
- .mux_clks = infra_muxes,
- .num_mux_clks = ARRAY_SIZE(infra_muxes),
- .clk_lock = &mt7988_clk_lock,
-+ .rst_desc = &infra_rst_desc,
- };
-
- static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
+++ /dev/null
-From 3c810da3206f2e52c92f9f15a87f05db4bbba734 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Wed, 17 Jan 2024 19:41:10 +0100
-Subject: [PATCH] dt-bindings: reset: mediatek: add MT7988 reset IDs
-
-Add reset constants for using as index in driver and dts.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/include/dt-bindings/reset/mediatek,mt7988-resets.h
-+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
-@@ -10,4 +10,10 @@
- /* ETHWARP resets */
- #define MT7988_ETHWARP_RST_SWITCH 0
-
-+/* INFRA resets */
-+#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0
-+#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1
-+
-+
- #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
-+
+++ /dev/null
-From 137c9e08e5e542d58aa606b0bb4f0990117309a0 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 20 Nov 2023 18:22:31 +0000
-Subject: [PATCH] watchdog: mediatek: mt7988: add wdt support
-
-Add support for watchdog and reset generator unit of the MediaTek
-MT7988 SoC.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/mtk_wdt.c | 42 ++++++++++++++++++++++++++++++++++++++
- 1 file changed, 42 insertions(+)
-
---- a/drivers/watchdog/mtk_wdt.c
-+++ b/drivers/watchdog/mtk_wdt.c
-@@ -56,9 +56,13 @@
- #define WDT_SWSYSRST 0x18U
- #define WDT_SWSYS_RST_KEY 0x88000000
-
-+#define WDT_SWSYSRST_EN 0xfc
-+
- #define DRV_NAME "mtk-wdt"
- #define DRV_VERSION "1.0"
-
-+#define MT7988_TOPRGU_SW_RST_NUM 24
-+
- static bool nowayout = WATCHDOG_NOWAYOUT;
- static unsigned int timeout;
-
-@@ -68,10 +72,12 @@ struct mtk_wdt_dev {
- spinlock_t lock; /* protects WDT_SWSYSRST reg */
- struct reset_controller_dev rcdev;
- bool disable_wdt_extrst;
-+ bool has_swsysrst_en;
- };
-
- struct mtk_wdt_data {
- int toprgu_sw_rst_num;
-+ bool has_swsysrst_en;
- };
-
- static const struct mtk_wdt_data mt2712_data = {
-@@ -82,6 +88,11 @@ static const struct mtk_wdt_data mt7986_
- .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
- };
-
-+static const struct mtk_wdt_data mt7988_data = {
-+ .toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM,
-+ .has_swsysrst_en = true,
-+};
-+
- static const struct mtk_wdt_data mt8183_data = {
- .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
- };
-@@ -98,6 +109,28 @@ static const struct mtk_wdt_data mt8195_
- .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
- };
-
-+/**
-+ * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
-+ * @data: Pointer to instance of driver data.
-+ * @id: Bit number identifying the reset to be enabled or disabled.
-+ * @enable: If true, enable software control for that bit, disable otherwise.
-+ *
-+ * Context: The caller must hold lock of struct mtk_wdt_dev.
-+ */
-+static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data,
-+ unsigned long id, bool enable)
-+{
-+ u32 tmp;
-+
-+ tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);
-+ if (enable)
-+ tmp |= BIT(id);
-+ else
-+ tmp &= ~BIT(id);
-+
-+ writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
-+}
-+
- static int toprgu_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
- {
-@@ -108,6 +141,9 @@ static int toprgu_reset_update(struct re
-
- spin_lock_irqsave(&data->lock, flags);
-
-+ if (assert && data->has_swsysrst_en)
-+ toprgu_reset_sw_en_unlocked(data, id, true);
-+
- tmp = readl(data->wdt_base + WDT_SWSYSRST);
- if (assert)
- tmp |= BIT(id);
-@@ -116,6 +152,9 @@ static int toprgu_reset_update(struct re
- tmp |= WDT_SWSYS_RST_KEY;
- writel(tmp, data->wdt_base + WDT_SWSYSRST);
-
-+ if (!assert && data->has_swsysrst_en)
-+ toprgu_reset_sw_en_unlocked(data, id, false);
-+
- spin_unlock_irqrestore(&data->lock, flags);
-
- return 0;
-@@ -393,6 +432,8 @@ static int mtk_wdt_probe(struct platform
- wdt_data->toprgu_sw_rst_num);
- if (err)
- return err;
-+
-+ mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
- }
-
- mtk_wdt->disable_wdt_extrst =
-@@ -427,6 +468,7 @@ static const struct of_device_id mtk_wdt
- { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
- { .compatible = "mediatek,mt6589-wdt" },
- { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
-+ { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
- { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
- { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
- { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
+++ /dev/null
-From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 11 Mar 2024 17:14:19 +0000
-Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port
-
-Due to what seems to be an undocumented oddity in MediaTek's MT7988
-SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
-CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.
-
-This currently leads to PCIe port 2 not working in Linux.
-
-Reflect the apparent relationship in the clk driver to make sure PCIe
-port 2 of the MT7988 SoC works.
-
-Suggested-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
-+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
-@@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[
- GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
- "csw_infra_f26m_sel", 8),
- GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
-- "csw_infra_f26m_sel", 9),
-+ "infra_pcie_peri_ck_26m_ck_p3", 9),
- GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
- "csw_infra_f26m_sel", 10),
- /* INFRA1 */
+++ /dev/null
-From patchwork Wed Jan 17 12:42:33 2024
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Jean Thomas <jean.thomas@wifirst.fr>
-X-Patchwork-Id: 13521682
-Return-Path:
- <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
-From: Jean Thomas <jean.thomas@wifirst.fr>
-To: sean.wang@kernel.org,
- linus.walleij@linaro.org,
- matthias.bgg@gmail.com,
- angelogioacchino.delregno@collabora.com,
- linux-mediatek@lists.infradead.org,
- linux-gpio@vger.kernel.org,
- linux-kernel@vger.kernel.org,
- linux-arm-kernel@lists.infradead.org
-Cc: Jean Thomas <jean.thomas@wifirst.fr>
-Subject: [PATCH 1/2] pinctrl: mediatek: mt7981: add additional uart group
-Date: Wed, 17 Jan 2024 13:42:33 +0100
-Message-Id: <20240117124234.3137050-1-jean.thomas@wifirst.fr>
-MIME-Version: 1.0
-List-Id: <linux-mediatek.lists.infradead.org>
-
-Add uart1_3 (pins 26, 27) group to the pinctrl driver for the
-MediaTek MT7981 SoC.
-
-Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr>
-Reviewed-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7981.c | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -737,6 +737,9 @@ static int mt7981_uart1_1_funcs[] = { 2,
- static int mt7981_uart1_2_pins[] = { 9, 10, };
- static int mt7981_uart1_2_funcs[] = { 2, 2, };
-
-+static int mt7981_uart1_3_pins[] = { 26, 27, };
-+static int mt7981_uart1_3_funcs[] = { 2, 2, };
-+
- /* UART2 */
- static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
- static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
-@@ -871,6 +874,8 @@ static const struct group_desc mt7981_gr
- PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
- /* @GPIO(9,10): UART1(2) */
- PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
-+ /* @GPIO(26,27): UART1(2) */
-+ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3),
- /* @GPIO(22,25): UART1(3) */
- PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
- /* @GPIO(22,24) PTA_EXT(4) */
-@@ -933,7 +938,7 @@ static const struct group_desc mt7981_gr
- static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
- "wa_aice3", "wm_aice1_2", };
- static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
-- "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
-+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart1_3", "uart2_0",
- "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
- static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
- static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
+++ /dev/null
-From patchwork Wed Jan 17 14:55:47 2024
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Jean Thomas <jean.thomas@wifirst.fr>
-X-Patchwork-Id: 13521855
-Return-Path:
- <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
-From: Jean Thomas <jean.thomas@wifirst.fr>
-To: sean.wang@kernel.org,
- linus.walleij@linaro.org,
- matthias.bgg@gmail.com,
- angelogioacchino.delregno@collabora.com,
- linux-mediatek@lists.infradead.org,
- linux-gpio@vger.kernel.org,
- linux-kernel@vger.kernel.org,
- linux-arm-kernel@lists.infradead.org
-Cc: Jean Thomas <jean.thomas@wifirst.fr>,
- Daniel Golle <daniel@makrotopia.org>
-Subject: [PATCH v2 2/2] pinctrl: mediatek: mt7981: add additional emmc groups
-Date: Wed, 17 Jan 2024 15:55:47 +0100
-Message-Id: <20240117145547.3354242-1-jean.thomas@wifirst.fr>
-List-Id: <linux-mediatek.lists.infradead.org>
-
-Add new emmc groups in the pinctrl driver for the
-MediaTek MT7981 SoC:
-* emmc reset, with pin 15.
-* emmc 4-bit bus-width, with pins 16 to 19, and 24 to 25.
-* emmc 8-bit bus-width, with pins 16 to 25.
-
-The existing emmc_45 group is kept for legacy reasons, even
-if this is the union of emmc_reset and emmc_8 groups.
-
-Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr>
-Reviewed-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/pinctrl/mediatek/pinctrl-mt7981.c | 17 ++++++++++++++++-
- 1 file changed, 16 insertions(+), 1 deletion(-)
-
---
-2.39.2
-
---- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
-@@ -700,6 +700,15 @@ static int mt7981_drv_vbus_pins[] = { 14
- static int mt7981_drv_vbus_funcs[] = { 1, };
-
- /* EMMC */
-+static int mt7981_emmc_reset_pins[] = { 15, };
-+static int mt7981_emmc_reset_funcs[] = { 2, };
-+
-+static int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, };
-+static int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, };
-+
-+static int mt7981_emmc_8_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
-+static int mt7981_emmc_8_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-+
- static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
- static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
-
-@@ -854,6 +863,12 @@ static const struct group_desc mt7981_gr
- PINCTRL_PIN_GROUP("udi", mt7981_udi),
- /* @GPIO(14) DRV_VBUS(1) */
- PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
-+ /* @GPIO(15): EMMC_RSTB(2) */
-+ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset),
-+ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
-+ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4),
-+ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
-+ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8),
- /* @GPIO(15,25): EMMC(2) */
- PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
- /* @GPIO(16,21): SNFI(3) */
-@@ -957,7 +972,7 @@ static const char *mt7981_i2c_groups[] =
- static const char *mt7981_pcm_groups[] = { "pcm", };
- static const char *mt7981_udi_groups[] = { "udi", };
- static const char *mt7981_usb_groups[] = { "drv_vbus", };
--static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
-+static const char *mt7981_flash_groups[] = { "emmc_reset", "emmc_4", "emmc_8", "emmc_45", "snfi", };
- static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
- "wf0_mode1", "wf0_mode3", "mt7531_int", };
- static const char *mt7981_ant_groups[] = { "ant_sel", };
+++ /dev/null
-From 24e961b93d292d0dd6380213d22a071a99ea787d Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Tue, 25 Oct 2022 15:29:53 +0200
-Subject: [PATCH 1/6] mmc: mediatek: add support for MT7986 SoC
-
-Adding mt7986 own characteristics and of_device_id to have support
-of MT7986 SoC.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221025132953.81286-7-linux@fw-web.de
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -552,6 +552,19 @@ static const struct mtk_mmc_compatible m
- .support_64g = false,
- };
-
-+static const struct mtk_mmc_compatible mt7986_compat = {
-+ .clk_div_bits = 12,
-+ .recheck_sdio_irq = true,
-+ .hs400_tune = false,
-+ .pad_tune_reg = MSDC_PAD_TUNE0,
-+ .async_fifo = true,
-+ .data_tune = true,
-+ .busy_check = true,
-+ .stop_clk_fix = true,
-+ .enhance_rx = true,
-+ .support_64g = true,
-+};
-+
- static const struct mtk_mmc_compatible mt8135_compat = {
- .clk_div_bits = 8,
- .recheck_sdio_irq = true,
-@@ -609,6 +622,7 @@ static const struct of_device_id msdc_of
- { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
- { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
- { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
-+ { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
- { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
- { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
- { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
+++ /dev/null
-From 7b438d0377fbd520b475a68bdd9de1692393f22d Mon Sep 17 00:00:00 2001
-From: Mengqi Zhang <mengqi.zhang@mediatek.com>
-Date: Sun, 6 Nov 2022 11:39:24 +0800
-Subject: [PATCH 2/6] mmc: mtk-sd: add Inline Crypto Engine clock control
-
-Add crypto clock control and ungate it before CQHCI init.
-
-Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221106033924.9854-2-mengqi.zhang@mediatek.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/mtk-sd.c | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -452,6 +452,7 @@ struct msdc_host {
- struct clk *bus_clk; /* bus clock which used to access register */
- struct clk *src_clk_cg; /* msdc source clock control gate */
- struct clk *sys_clk_cg; /* msdc subsys clock control gate */
-+ struct clk *crypto_clk; /* msdc crypto clock control gate */
- struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
- u32 mclk; /* mmc subsystem clock frequency */
- u32 src_clk_freq; /* source clock frequency */
-@@ -840,6 +841,7 @@ static void msdc_set_busy_timeout(struct
- static void msdc_gate_clock(struct msdc_host *host)
- {
- clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
-+ clk_disable_unprepare(host->crypto_clk);
- clk_disable_unprepare(host->src_clk_cg);
- clk_disable_unprepare(host->src_clk);
- clk_disable_unprepare(host->bus_clk);
-@@ -855,6 +857,7 @@ static int msdc_ungate_clock(struct msdc
- clk_prepare_enable(host->bus_clk);
- clk_prepare_enable(host->src_clk);
- clk_prepare_enable(host->src_clk_cg);
-+ clk_prepare_enable(host->crypto_clk);
- ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
- if (ret) {
- dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
-@@ -2670,6 +2673,15 @@ static int msdc_drv_probe(struct platfor
- goto host_free;
- }
-
-+ /* only eMMC has crypto property */
-+ if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
-+ host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
-+ if (IS_ERR(host->crypto_clk))
-+ host->crypto_clk = NULL;
-+ else
-+ mmc->caps2 |= MMC_CAP2_CRYPTO;
-+ }
-+
- host->irq = platform_get_irq(pdev, 0);
- if (host->irq < 0) {
- ret = host->irq;
+++ /dev/null
-From 4b323f02b6e8df1b04292635ef829e7f723bf50e Mon Sep 17 00:00:00 2001
-From: Yu Zhe <yuzhe@nfschina.com>
-Date: Thu, 10 Nov 2022 15:28:19 +0800
-Subject: [PATCH 3/6] mmc: mtk-sd: fix two spelling mistakes in comment
-
-spelling mistake fix : "alreay" -> "already"
- "checksume" -> "checksum"
-
-Signed-off-by: Yu Zhe <yuzhe@nfschina.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221110072819.11530-1-yuzhe@nfschina.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/mtk-sd.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -750,7 +750,7 @@ static inline void msdc_dma_setup(struct
- else
- bd[j].bd_info &= ~BDMA_DESC_EOL;
-
-- /* checksume need to clear first */
-+ /* checksum need to clear first */
- bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
- bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
- }
-@@ -1229,7 +1229,7 @@ static bool msdc_cmd_done(struct msdc_ho
- !host->hs400_tuning))
- /*
- * should not clear fifo/interrupt as the tune data
-- * may have alreay come when cmd19/cmd21 gets response
-+ * may have already come when cmd19/cmd21 gets response
- * CRC error.
- */
- msdc_reset_hw(host);
+++ /dev/null
-From b98e7e8daf0ebab9dcc36812378a71e1be0b5089 Mon Sep 17 00:00:00 2001
-From: ChanWoo Lee <cw9316.lee@samsung.com>
-Date: Thu, 24 Nov 2022 17:00:31 +0900
-Subject: [PATCH 4/6] mmc: Avoid open coding by using mmc_op_tuning()
-
-Replace code with the already defined function. No functional changes.
-
-Signed-off-by: ChanWoo Lee <cw9316.lee@samsung.com>
-Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
-Link: https://lore.kernel.org/r/20221124080031.14690-1-cw9316.lee@samsung.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/mtk-sd.c | 8 ++------
- 1 file changed, 2 insertions(+), 6 deletions(-)
-
---- a/drivers/mmc/host/mtk-sd.c
-+++ b/drivers/mmc/host/mtk-sd.c
-@@ -1224,9 +1224,7 @@ static bool msdc_cmd_done(struct msdc_ho
-
- if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
- if (events & MSDC_INT_CMDTMO ||
-- (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
-- cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 &&
-- !host->hs400_tuning))
-+ (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
- /*
- * should not clear fifo/interrupt as the tune data
- * may have already come when cmd19/cmd21 gets response
-@@ -1320,9 +1318,7 @@ static void msdc_cmd_next(struct msdc_ho
- {
- if ((cmd->error &&
- !(cmd->error == -EILSEQ &&
-- (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
-- cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 ||
-- host->hs400_tuning))) ||
-+ (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) ||
- (mrq->sbc && mrq->sbc->error))
- msdc_request_done(host, mrq);
- else if (cmd == mrq->sbc)
+++ /dev/null
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -19,6 +19,7 @@
- #include <linux/string.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/spi-mem.h>
-+#include <linux/mtd/mtk_bmt.h>
-
- static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
- {
-@@ -1344,6 +1345,7 @@ static int spinand_probe(struct spi_mem
- if (ret)
- return ret;
-
-+ mtk_bmt_attach(mtd);
- ret = mtd_device_register(mtd, NULL, 0);
- if (ret)
- goto err_spinand_cleanup;
-@@ -1351,6 +1353,7 @@ static int spinand_probe(struct spi_mem
- return 0;
-
- err_spinand_cleanup:
-+ mtk_bmt_detach(mtd);
- spinand_cleanup(spinand);
-
- return ret;
-@@ -1369,6 +1372,7 @@ static int spinand_remove(struct spi_mem
- if (ret)
- return ret;
-
-+ mtk_bmt_detach(mtd);
- spinand_cleanup(spinand);
-
- return 0;
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -548,6 +548,7 @@
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- nand-ecc-engine = <&snfi>;
-+ mediatek,bmt-v2;
-
- partitions {
- compatible = "fixed-partitions";
+++ /dev/null
-From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001
-From: Davide Fioravanti <pantanastyle@gmail.com>
-Date: Fri, 8 Jan 2021 15:35:24 +0100
-Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA
-
-Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf
-
-Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
----
- drivers/mtd/nand/spi/Makefile | 2 +-
- drivers/mtd/nand/spi/core.c | 1 +
- drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++
- include/linux/mtd/spinand.h | 1 +
- 4 files changed, 79 insertions(+), 1 deletion(-)
- create mode 100644 drivers/mtd/nand/spi/fidelix.c
-
---- a/drivers/mtd/nand/spi/Makefile
-+++ b/drivers/mtd/nand/spi/Makefile
-@@ -1,3 +1,3 @@
- # SPDX-License-Identifier: GPL-2.0
--spinand-objs := core.o ato.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
-+spinand-objs := core.o ato.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
- obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -940,6 +940,7 @@ static const struct nand_ops spinand_ops
- static const struct spinand_manufacturer *spinand_manufacturers[] = {
- &ato_spinand_manufacturer,
- &esmt_c8_spinand_manufacturer,
-+ &fidelix_spinand_manufacturer,
- &etron_spinand_manufacturer,
- &gigadevice_spinand_manufacturer,
- ¯onix_spinand_manufacturer,
---- /dev/null
-+++ b/drivers/mtd/nand/spi/fidelix.c
-@@ -0,0 +1,76 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2020 Davide Fioravanti <pantanastyle@gmail.com>
-+ */
-+
-+#include <linux/device.h>
-+#include <linux/kernel.h>
-+#include <linux/mtd/spinand.h>
-+
-+#define SPINAND_MFR_FIDELIX 0xE5
-+#define FIDELIX_ECCSR_MASK 0x0F
-+
-+static SPINAND_OP_VARIANTS(read_cache_variants,
-+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
-+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(write_cache_variants,
-+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
-+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
-+
-+static SPINAND_OP_VARIANTS(update_cache_variants,
-+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
-+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
-+
-+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *region)
-+{
-+ if (section > 3)
-+ return -ERANGE;
-+
-+ region->offset = (16 * section) + 8;
-+ region->length = 8;
-+
-+ return 0;
-+}
-+
-+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *region)
-+{
-+ if (section > 3)
-+ return -ERANGE;
-+
-+ region->offset = (16 * section) + 2;
-+ region->length = 6;
-+
-+ return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = {
-+ .ecc = fm35x1ga_ooblayout_ecc,
-+ .free = fm35x1ga_ooblayout_free,
-+};
-+
-+static const struct spinand_info fidelix_spinand_table[] = {
-+ SPINAND_INFO("FM35X1GA",
-+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),
-+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+ NAND_ECCREQ(4, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)),
-+};
-+
-+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = {
-+};
-+
-+const struct spinand_manufacturer fidelix_spinand_manufacturer = {
-+ .id = SPINAND_MFR_FIDELIX,
-+ .name = "Fidelix",
-+ .chips = fidelix_spinand_table,
-+ .nchips = ARRAY_SIZE(fidelix_spinand_table),
-+ .ops = &fidelix_spinand_manuf_ops,
-+};
---- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -263,6 +263,7 @@ struct spinand_manufacturer {
- extern const struct spinand_manufacturer ato_spinand_manufacturer;
- extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
- extern const struct spinand_manufacturer etron_spinand_manufacturer;
-+extern const struct spinand_manufacturer fidelix_spinand_manufacturer;
- extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
- extern const struct spinand_manufacturer macronix_spinand_manufacturer;
- extern const struct spinand_manufacturer micron_spinand_manufacturer;
+++ /dev/null
-From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Tue, 28 Feb 2023 19:59:22 +0800
-Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988
-
-This add cpufreq support for mediatek MT7988 SoC.
-
-The platform data of MT7988 is different from previous MediaTek SoCs,
-so we add a new compatible and platform data for it.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
----
- drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/cpufreq/mediatek-cpufreq.c
-+++ b/drivers/cpufreq/mediatek-cpufreq.c
-@@ -709,6 +709,15 @@ static const struct mtk_cpufreq_platform
- .ccifreq_supported = false,
- };
-
-+static const struct mtk_cpufreq_platform_data mt7988_platform_data = {
-+ .min_volt_shift = 100000,
-+ .max_volt_shift = 200000,
-+ .proc_max_volt = 900000,
-+ .sram_min_volt = 0,
-+ .sram_max_volt = 1150000,
-+ .ccifreq_supported = true,
-+};
-+
- static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
- .min_volt_shift = 100000,
- .max_volt_shift = 200000,
-@@ -742,6 +751,7 @@ static const struct of_device_id mtk_cpu
- { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
- { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
-+ { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
- { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
- { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
+++ /dev/null
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
-@@ -601,6 +601,30 @@ out:
- return err;
- }
-
-+static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 pullup, u32 arg)
-+{
-+ int err, pd;
-+
-+ if (arg == MTK_DISABLE)
-+ pd = 0;
-+ else if ((arg == MTK_ENABLE) && pullup)
-+ pd = 0;
-+ else if ((arg == MTK_ENABLE) && !pullup)
-+ pd = 1;
-+ else {
-+ err = -EINVAL;
-+ goto out;
-+ }
-+
-+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
-+
-+out:
-+ return err;
-+
-+}
-+
- static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
- const struct mtk_pin_desc *desc,
- u32 pullup, u32 arg)
-@@ -755,6 +779,12 @@ int mtk_pinconf_bias_set_combo(struct mt
- return err;
- }
-
-+ if (try_all_type & MTK_PULL_PD_TYPE) {
-+ err = mtk_pinconf_bias_set_pd(hw, desc, pullup, arg);
-+ if (!err)
-+ return err;
-+ }
-+
- if (try_all_type & MTK_PULL_PU_PD_TYPE) {
- err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
- if (!err)
-@@ -875,6 +905,29 @@ out:
- return err;
- }
-
-+static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw,
-+ const struct mtk_pin_desc *desc,
-+ u32 *pullup, u32 *enable)
-+{
-+ int err, pd;
-+
-+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
-+ if (err)
-+ goto out;
-+
-+ if (pd == 0) {
-+ *pullup = 0;
-+ *enable = MTK_DISABLE;
-+ } else if (pd == 1) {
-+ *pullup = 0;
-+ *enable = MTK_ENABLE;
-+ } else
-+ err = -EINVAL;
-+
-+out:
-+ return err;
-+}
-+
- static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
- const struct mtk_pin_desc *desc,
- u32 *pullup, u32 *enable)
-@@ -943,6 +996,12 @@ int mtk_pinconf_bias_get_combo(struct mt
- if (!err)
- return err;
- }
-+
-+ if (try_all_type & MTK_PULL_PD_TYPE) {
-+ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable);
-+ if (!err)
-+ return err;
-+ }
-
- if (try_all_type & MTK_PULL_PU_PD_TYPE) {
- err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
-+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
-@@ -24,6 +24,7 @@
- * turned on/off itself. But it can't be selected pull up/down
- */
- #define MTK_PULL_RSEL_TYPE BIT(3)
-+#define MTK_PULL_PD_TYPE BIT(4)
- /* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
- * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
- */
+++ /dev/null
---- a/drivers/crypto/inside-secure/safexcel.c
-+++ b/drivers/crypto/inside-secure/safexcel.c
-@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex
- val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
- writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
- }
-+ /*
-+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
-+ */
-+ else {
-+ val = 0;
-+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
-+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
-+ }
-
- /* Configure wr/rd cache values */
- writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
---- a/drivers/crypto/inside-secure/safexcel.h
-+++ b/drivers/crypto/inside-secure/safexcel.h
-@@ -315,6 +315,7 @@
- #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
- #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
- #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
-+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4)
- #define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
- #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
- #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
+++ /dev/null
---- a/drivers/crypto/inside-secure/safexcel.h
-+++ b/drivers/crypto/inside-secure/safexcel.h
-@@ -737,6 +737,9 @@ enum safexcel_eip_version {
- /* Priority we use for advertising our algorithms */
- #define SAFEXCEL_CRA_PRIORITY 300
-
-+/* System cache line size */
-+#define SYSTEM_CACHELINE_SIZE 64
-+
- /* SM3 digest result for zero length message */
- #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
- "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
---- a/drivers/crypto/inside-secure/safexcel_hash.c
-+++ b/drivers/crypto/inside-secure/safexcel_hash.c
-@@ -55,9 +55,9 @@ struct safexcel_ahash_req {
- u8 block_sz; /* block size, only set once */
- u8 digest_sz; /* output digest size, only set once */
- __le32 state[SHA3_512_BLOCK_SIZE /
-- sizeof(__le32)] __aligned(sizeof(__le32));
-+ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE);
-
-- u64 len;
-+ u64 len __aligned(SYSTEM_CACHELINE_SIZE);
- u64 processed;
-
- u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));
+++ /dev/null
-From f1da27b7c4191f78ed81d3dabf64c769f896296c Mon Sep 17 00:00:00 2001
-From: "Mingming.Su" <Mingming.Su@mediatek.com>
-Date: Sat, 8 Oct 2022 18:45:53 +0200
-Subject: [PATCH] hwrng: mtk - add mt7986 support
-
-1. Add trng compatible name for MT7986
-2. Fix mtk_rng_wait_ready() function
-
-Signed-off-by: Mingming.Su <Mingming.Su@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
----
- drivers/char/hw_random/mtk-rng.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/char/hw_random/mtk-rng.c
-+++ b/drivers/char/hw_random/mtk-rng.c
-@@ -22,7 +22,7 @@
- #define RNG_AUTOSUSPEND_TIMEOUT 100
-
- #define USEC_POLL 2
--#define TIMEOUT_POLL 20
-+#define TIMEOUT_POLL 60
-
- #define RNG_CTRL 0x00
- #define RNG_EN BIT(0)
-@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw
- readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready,
- ready & RNG_READY, USEC_POLL,
- TIMEOUT_POLL);
-- return !!ready;
-+ return !!(ready & RNG_READY);
- }
-
- static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p
- #endif /* CONFIG_PM */
-
- static const struct of_device_id mtk_rng_match[] = {
-+ { .compatible = "mediatek,mt7986-rng" },
- { .compatible = "mediatek,mt7623-rng" },
- {},
- };
+++ /dev/null
---- a/drivers/tty/serial/8250/8250.h
-+++ b/drivers/tty/serial/8250/8250.h
-@@ -86,6 +86,7 @@ struct serial8250_config {
- * STOP PARITY EPAR SPAR WLEN5 WLEN6
- */
- #define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */
-+#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */
-
- #define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */
- #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */
---- a/drivers/tty/serial/8250/8250_port.c
-+++ b/drivers/tty/serial/8250/8250_port.c
-@@ -287,7 +287,7 @@ static const struct serial8250_config ua
- .tx_loadsz = 16,
- .fcr = UART_FCR_ENABLE_FIFO |
- UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
-- .flags = UART_CAP_FIFO,
-+ .flags = UART_CAP_FIFO | UART_CAP_NMOD,
- },
- [PORT_NPCM] = {
- .name = "Nuvoton 16550",
-@@ -2773,6 +2773,11 @@ serial8250_do_set_termios(struct uart_po
- unsigned long flags;
- unsigned int baud, quot, frac = 0;
-
-+ if (up->capabilities & UART_CAP_NMOD) {
-+ termios->c_cflag = 0;
-+ return;
-+ }
-+
- if (up->capabilities & UART_CAP_MINI) {
- termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
- if ((termios->c_cflag & CSIZE) == CS5 ||
+++ /dev/null
-From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:29:51 +0800
-Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private
- data
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mt65xx.c | 29 +++++++++---------------
- include/linux/platform_data/spi-mt65xx.h | 17 --------------
- 2 files changed, 11 insertions(+), 35 deletions(-)
- delete mode 100644 include/linux/platform_data/spi-mt65xx.h
-
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -14,7 +14,6 @@
- #include <linux/of.h>
- #include <linux/gpio/consumer.h>
- #include <linux/platform_device.h>
--#include <linux/platform_data/spi-mt65xx.h>
- #include <linux/pm_runtime.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/spi-mem.h>
-@@ -171,6 +170,8 @@ struct mtk_spi {
- struct device *dev;
- dma_addr_t tx_dma;
- dma_addr_t rx_dma;
-+ u32 sample_sel;
-+ u32 get_tick_dly;
- };
-
- static const struct mtk_spi_compatible mtk_common_compat;
-@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m
- .no_need_unprepare = true,
- };
-
--/*
-- * A piece of default chip info unless the platform
-- * supplies it.
-- */
--static const struct mtk_chip_config mtk_default_chip_info = {
-- .sample_sel = 0,
-- .tick_delay = 0,
--};
--
- static const struct of_device_id mtk_spi_of_match[] = {
- { .compatible = "mediatek,spi-ipm",
- .data = (void *)&mtk_ipm_compat,
-@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma
- {
- u16 cpha, cpol;
- u32 reg_val;
-- struct mtk_chip_config *chip_config = spi->controller_data;
- struct mtk_spi *mdata = spi_master_get_devdata(master);
-
- cpha = spi->mode & SPI_CPHA ? 1 : 0;
-@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma
- else
- reg_val &= ~SPI_CMD_CS_POL;
-
-- if (chip_config->sample_sel)
-+ if (mdata->sample_sel)
- reg_val |= SPI_CMD_SAMPLE_SEL;
- else
- reg_val &= ~SPI_CMD_SAMPLE_SEL;
-@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma
- if (mdata->dev_comp->ipm_design) {
- reg_val = readl(mdata->base + SPI_CMD_REG);
- reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
-- reg_val |= ((chip_config->tick_delay & 0x7)
-+ reg_val |= ((mdata->get_tick_dly & 0x7)
- << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
- writel(reg_val, mdata->base + SPI_CMD_REG);
- } else {
- reg_val = readl(mdata->base + SPI_CFG1_REG);
- reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
-- reg_val |= ((chip_config->tick_delay & 0x7)
-+ reg_val |= ((mdata->get_tick_dly & 0x7)
- << SPI_CFG1_GET_TICK_DLY_OFFSET);
- writel(reg_val, mdata->base + SPI_CFG1_REG);
- }
- } else {
- reg_val = readl(mdata->base + SPI_CFG1_REG);
- reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
-- reg_val |= ((chip_config->tick_delay & 0x3)
-+ reg_val |= ((mdata->get_tick_dly & 0x3)
- << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
- writel(reg_val, mdata->base + SPI_CFG1_REG);
- }
-@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi
- {
- struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
-
-- if (!spi->controller_data)
-- spi->controller_data = (void *)&mtk_default_chip_info;
--
- if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod)
- /* CS de-asserted, gpiolib will handle inversion */
- gpiod_direction_output(spi->cs_gpiod, 0);
-@@ -1138,6 +1126,10 @@ static int mtk_spi_probe(struct platform
- mdata = spi_master_get_devdata(master);
- mdata->dev_comp = device_get_match_data(dev);
-
-+ /* Set device configs to default first. Calibrate it later. */
-+ mdata->sample_sel = 0;
-+ mdata->get_tick_dly = 2;
-+
- if (mdata->dev_comp->enhance_timing)
- master->mode_bits |= SPI_CS_HIGH;
-
---- a/include/linux/platform_data/spi-mt65xx.h
-+++ /dev/null
-@@ -1,17 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0-only */
--/*
-- * MTK SPI bus driver definitions
-- *
-- * Copyright (c) 2015 MediaTek Inc.
-- * Author: Leilk Liu <leilk.liu@mediatek.com>
-- */
--
--#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
--#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
--
--/* Board specific platform_data */
--struct mtk_chip_config {
-- u32 sample_sel;
-- u32 tick_delay;
--};
--#endif
+++ /dev/null
-From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:35:52 +0800
-Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++
- include/linux/spi/spi.h | 42 ++++++++++++
- 2 files changed, 179 insertions(+)
-
---- a/drivers/spi/spi.c
-+++ b/drivers/spi/spi.c
-@@ -1385,6 +1385,70 @@ static int spi_transfer_wait(struct spi_
- return 0;
- }
-
-+int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi,
-+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv)
-+{
-+ int datalen = ctlr->cal_rule->datalen;
-+ int addrlen = ctlr->cal_rule->addrlen;
-+ u8 *buf;
-+ int ret;
-+ int i;
-+ struct list_head *cal_head, *listptr;
-+ struct spi_cal_target *target;
-+
-+ /* Calculate calibration result */
-+ int hit_val, total_hit, origin;
-+ bool hit;
-+
-+ /* Make sure we can start calibration */
-+ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata)
-+ return 0;
-+
-+ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL);
-+ if(!buf)
-+ return -ENOMEM;
-+
-+ ret = ctlr->append_caldata(ctlr);
-+ if (ret)
-+ goto cal_end;
-+
-+ cal_head = ctlr->cal_target;
-+ list_for_each(listptr, cal_head) {
-+ target = list_entry(listptr, struct spi_cal_target, list);
-+
-+ hit = false;
-+ hit_val = 0;
-+ total_hit = 0;
-+ origin = *target->cal_item;
-+
-+ for(i=target->cal_min; i<=target->cal_max; i+=target->step) {
-+ *target->cal_item = i;
-+ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen);
-+ if(ret)
-+ break;
-+ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i);
-+ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) {
-+ hit = true;
-+ hit_val += i;
-+ total_hit++;
-+ dev_dbg(&spi->dev, "golden data matches data read!\n");
-+ }
-+ }
-+ if(hit) {
-+ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit);
-+ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item);
-+ } else {
-+ *target->cal_item = origin;
-+ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin);
-+ }
-+ }
-+
-+cal_end:
-+ kfree(buf);
-+ return ret? ret: 0;
-+}
-+EXPORT_SYMBOL_GPL(spi_do_calibration);
-+
- static void _spi_transfer_delay_ns(u32 ns)
- {
- if (!ns)
-@@ -2223,6 +2287,75 @@ void spi_flush_queue(struct spi_controll
- /*-------------------------------------------------------------------------*/
-
- #if defined(CONFIG_OF)
-+static inline void alloc_cal_data(struct list_head **cal_target,
-+ struct spi_cal_rule **cal_rule, bool enable)
-+{
-+ if(enable) {
-+ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL);
-+ INIT_LIST_HEAD(*cal_target);
-+ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL);
-+ } else {
-+ kfree(*cal_target);
-+ kfree(*cal_rule);
-+ }
-+}
-+
-+static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi,
-+ struct device_node *nc)
-+{
-+ u32 value;
-+ int rc;
-+ const char *cal_mode;
-+
-+ rc = of_property_read_bool(nc, "spi-cal-enable");
-+ if (rc)
-+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true);
-+ else
-+ return 0;
-+
-+ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode);
-+ if(!rc) {
-+ if(strcmp("read-data", cal_mode) == 0){
-+ ctlr->cal_rule->mode = SPI_CAL_READ_DATA;
-+ } else if(strcmp("read-pp", cal_mode) == 0) {
-+ ctlr->cal_rule->mode = SPI_CAL_READ_PP;
-+ return 0;
-+ } else if(strcmp("read-sfdp", cal_mode) == 0){
-+ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP;
-+ return 0;
-+ }
-+ } else
-+ goto err;
-+
-+ ctlr->cal_rule->datalen = 0;
-+ rc = of_property_read_u32(nc, "spi-cal-datalen", &value);
-+ if(!rc && value > 0) {
-+ ctlr->cal_rule->datalen = value;
-+
-+ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL);
-+ rc = of_property_read_u8_array(nc, "spi-cal-data",
-+ ctlr->cal_rule->match_data, value);
-+ if(rc)
-+ kfree(ctlr->cal_rule->match_data);
-+ }
-+
-+ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value);
-+ if(!rc && value > 0) {
-+ ctlr->cal_rule->addrlen = value;
-+
-+ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL);
-+ rc = of_property_read_u32_array(nc, "spi-cal-addr",
-+ ctlr->cal_rule->addr, value);
-+ if(rc)
-+ kfree(ctlr->cal_rule->addr);
-+ }
-+ return 0;
-+
-+err:
-+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false);
-+ return 0;
-+}
-+
- static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
- struct device_node *nc)
- {
-@@ -2341,6 +2474,10 @@ of_register_spi_device(struct spi_contro
- if (rc)
- goto err_out;
-
-+ rc = of_spi_parse_cal_dt(ctlr, spi, nc);
-+ if (rc)
-+ goto err_out;
-+
- /* Store a pointer to the node in the device structure */
- of_node_get(nc);
- spi->dev.of_node = nc;
---- a/include/linux/spi/spi.h
-+++ b/include/linux/spi/spi.h
-@@ -318,6 +318,40 @@ struct spi_driver {
- struct device_driver driver;
- };
-
-+enum {
-+ SPI_CAL_READ_DATA = 0,
-+ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */
-+ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */
-+};
-+
-+struct nand_addr {
-+ unsigned int lun;
-+ unsigned int plane;
-+ unsigned int eraseblock;
-+ unsigned int page;
-+ unsigned int dataoffs;
-+};
-+
-+/**
-+ * Read calibration rule from device dts node.
-+ * Once calibration result matches the rule, we regard is as success.
-+ */
-+struct spi_cal_rule {
-+ int datalen;
-+ u8 *match_data;
-+ int addrlen;
-+ u32 *addr;
-+ int mode;
-+};
-+
-+struct spi_cal_target {
-+ u32 *cal_item;
-+ int cal_min; /* min of cal_item */
-+ int cal_max; /* max of cal_item */
-+ int step; /* Increase/decrease cal_item */
-+ struct list_head list;
-+};
-+
- static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
- {
- return drv ? container_of(drv, struct spi_driver, driver) : NULL;
-@@ -703,6 +737,11 @@ struct spi_controller {
- void *dummy_rx;
- void *dummy_tx;
-
-+ /* For calibration */
-+ int (*append_caldata)(struct spi_controller *ctlr);
-+ struct list_head *cal_target;
-+ struct spi_cal_rule *cal_rule;
-+
- int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
-
- /*
-@@ -1510,6 +1549,9 @@ spi_register_board_info(struct spi_board
- { return 0; }
- #endif
-
-+extern int spi_do_calibration(struct spi_controller *ctlr,
-+ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv);
-+
- /* If you're hotplugging an adapter with devices (parport, usb, etc)
- * use spi_new_device() to describe each device. You can also call
- * spi_unregister_device() to start making that device vanish, but
+++ /dev/null
-From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:37:55 +0800
-Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mem.c | 8 ++++++++
- include/linux/spi/spi-mem.h | 4 ++++
- 2 files changed, 12 insertions(+)
-
---- a/drivers/spi/spi-mem.c
-+++ b/drivers/spi/spi-mem.c
-@@ -419,6 +419,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
- }
- EXPORT_SYMBOL_GPL(spi_mem_exec_op);
-
-+int spi_mem_do_calibration(struct spi_mem *mem,
-+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen),
-+ void *priv)
-+{
-+ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv);
-+}
-+EXPORT_SYMBOL_GPL(spi_mem_do_calibration);
-+
- /**
- * spi_mem_get_name() - Return the SPI mem device name to be used by the
- * upper layer if necessary
---- a/include/linux/spi/spi-mem.h
-+++ b/include/linux/spi/spi-mem.h
-@@ -366,6 +366,10 @@ bool spi_mem_supports_op(struct spi_mem
- int spi_mem_exec_op(struct spi_mem *mem,
- const struct spi_mem_op *op);
-
-+int spi_mem_do_calibration(struct spi_mem *mem,
-+ int (*cal_read)(void *, u32 *, int, u8 *, int),
-+ void *priv);
-+
- const char *spi_mem_get_name(struct spi_mem *mem);
-
- struct spi_mem_dirmap_desc *
+++ /dev/null
-From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:39:03 +0800
-Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration
- paramter
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -832,6 +832,21 @@ static irqreturn_t mtk_spi_interrupt(int
- return IRQ_HANDLED;
- }
-
-+static int mtk_spi_append_caldata(struct spi_controller *ctlr)
-+{
-+ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL);
-+ struct mtk_spi *mdata = spi_master_get_devdata(ctlr);
-+
-+ cal_target->cal_item = &mdata->get_tick_dly;
-+ cal_target->cal_min = 0;
-+ cal_target->cal_max = 7;
-+ cal_target->step = 1;
-+
-+ list_add(&cal_target->list, ctlr->cal_target);
-+
-+ return 0;
-+}
-+
- static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
- struct spi_mem_op *op)
- {
-@@ -1122,6 +1137,7 @@ static int mtk_spi_probe(struct platform
- master->setup = mtk_spi_setup;
- master->set_cs_timing = mtk_spi_set_hw_cs_timing;
- master->use_gpio_descriptors = true;
-+ master->append_caldata = mtk_spi_append_caldata;
-
- mdata = spi_master_get_devdata(master);
- mdata->dev_comp = device_get_match_data(dev);
+++ /dev/null
-From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:39:56 +0800
-Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for
- spinand
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 54 insertions(+)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -978,6 +978,56 @@ static int spinand_manufacturer_match(st
- return -ENOTSUPP;
- }
-
-+int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) {
-+ struct spinand_device *spinand = (struct spinand_device *)priv;
-+ struct device *dev = &spinand->spimem->spi->dev;
-+ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen);
-+ struct nand_pos pos;
-+ struct nand_page_io_req req;
-+ u8 status;
-+ int ret;
-+
-+ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) {
-+ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n");
-+ return -EINVAL;
-+ }
-+
-+ ret = spinand_reset_op(spinand);
-+ if (ret)
-+ return ret;
-+
-+ /* We should store our golden data in first target because
-+ * we can't switch target at this moment.
-+ */
-+ pos = (struct nand_pos){
-+ .target = 0,
-+ .lun = *addr,
-+ .plane = *(addr+1),
-+ .eraseblock = *(addr+2),
-+ .page = *(addr+3),
-+ };
-+
-+ req = (struct nand_page_io_req){
-+ .pos = pos,
-+ .dataoffs = *(addr+4),
-+ .datalen = readlen,
-+ .databuf.in = buf,
-+ .mode = MTD_OPS_AUTO_OOB,
-+ };
-+
-+ ret = spinand_load_page_op(spinand, &req);
-+ if (ret)
-+ return ret;
-+
-+ ret = spinand_wait(spinand, &status);
-+ if (ret < 0)
-+ return ret;
-+
-+ ret = spi_mem_exec_op(spinand->spimem, &op);
-+
-+ return 0;
-+}
-+
- static int spinand_id_detect(struct spinand_device *spinand)
- {
- u8 *id = spinand->id.data;
-@@ -1228,6 +1278,10 @@ static int spinand_init(struct spinand_d
- if (!spinand->scratchbuf)
- return -ENOMEM;
-
-+ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand);
-+ if (ret)
-+ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret);
-+
- ret = spinand_detect(spinand);
- if (ret)
- goto err_free_bufs;
+++ /dev/null
-From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001
-From: "SkyLake.Huang" <skylake.huang@mediatek.com>
-Date: Thu, 23 Jun 2022 18:40:59 +0800
-Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for
- spi-nor
-
-Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
----
- drivers/mtd/nand/spi/core.c | 5 ++++-
- drivers/mtd/spi-nor/core.c | 15 +++++++++++++++
- 2 files changed, 19 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -1019,7 +1019,10 @@ int spinand_cal_read(void *priv, u32 *ad
- if (ret)
- return ret;
-
-- ret = spinand_wait(spinand, &status);
-+ ret = spinand_wait(spinand,
-+ SPINAND_READ_INITIAL_DELAY_US,
-+ SPINAND_READ_POLL_DELAY_US,
-+ &status);
- if (ret < 0)
- return ret;
-
---- a/drivers/mtd/spi-nor/core.c
-+++ b/drivers/mtd/spi-nor/core.c
-@@ -2900,6 +2900,18 @@ static const struct flash_info *spi_nor_
- return NULL;
- }
-
-+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen)
-+{
-+ struct spi_nor *nor = (struct spi_nor *)priv;
-+
-+ nor->reg_proto = SNOR_PROTO_1_1_1;
-+ nor->read_proto = SNOR_PROTO_1_1_1;
-+ nor->read_opcode = SPINOR_OP_READ;
-+ nor->read_dummy = 0;
-+
-+ return nor->controller_ops->read(nor, *addr, readlen, buf);
-+}
-+
- static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
- const char *name)
- {
-@@ -3003,6 +3015,9 @@ int spi_nor_scan(struct spi_nor *nor, co
- if (!nor->bouncebuf)
- return -ENOMEM;
-
-+ if(nor->spimem)
-+ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor);
-+
- info = spi_nor_get_flash_info(nor, name);
- if (IS_ERR(info))
- return PTR_ERR(info);
+++ /dev/null
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -384,6 +384,12 @@ config ROCKCHIP_PHY
- help
- Currently supports the integrated Ethernet PHY.
-
-+config RTL8367S_GSW
-+ tristate "rtl8367 Gigabit Switch support for mt7622"
-+ depends on NET_VENDOR_MEDIATEK
-+ help
-+ This driver supports rtl8367s in mt7622
-+
- config SMSC_PHY
- tristate "SMSC PHYs"
- help
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
- obj-$(CONFIG_REALTEK_PHY) += realtek.o
- obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
- obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
-+obj-$(CONFIG_RTL8367S_GSW) += rtk/
- obj-$(CONFIG_SMSC_PHY) += smsc.o
- obj-$(CONFIG_STE10XP) += ste10Xp.o
- obj-$(CONFIG_TERANETICS_PHY) += teranetics.o
+++ /dev/null
-From: qizhong cheng <qizhong.cheng@mediatek.com>
-Date: Mon, 27 Dec 2021 21:31:10 +0800
-Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
- stabilize
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
-2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
-be delayed 100ms (TPVPERL) for the power and clock to become stable.
-
-Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
-Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Acked-by: Pali Rohár <pali@kernel.org>
----
-
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru
- */
- msleep(100);
-
-+ /*
-+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
-+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
-+ * be delayed 100ms (TPVPERL) for the power and clock to become stable.
-+ */
-+ msleep(100);
-+
- /* De-assert PHY, PE, PIPE, MAC and configuration reset */
- val = readl(port->base + PCIE_RST_CTRL);
- val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -849,6 +849,12 @@
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
-+
-+ slot0: pcie@0,0 {
-+ reg = <0x0000 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ };
- };
-
- pcie1: pcie@1a145000 {
-@@ -887,6 +893,12 @@
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
-+
-+ slot1: pcie@1,0 {
-+ reg = <0x0800 0 0 0 0>;
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ };
- };
-
- sata: sata@1a200000 {
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Fri, 4 Sep 2020 18:33:27 +0200
-Subject: [PATCH] pcie-mediatek: fix clearing interrupt status
-
-Clearing the status needs to happen after running the handler, otherwise
-we will get an extra spurious interrupt after the cause has been cleared
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -607,9 +607,9 @@ static void mtk_pcie_intr_handler(struct
- if (status & INTX_MASK) {
- for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
- /* Clear the INTx */
-- writel(1 << bit, port->base + PCIE_INT_STATUS);
- generic_handle_domain_irq(port->irq_domain,
- bit - INTX_SHIFT);
-+ writel(1 << bit, port->base + PCIE_INT_STATUS);
- }
- }
-
+++ /dev/null
---- a/drivers/pci/controller/pcie-mediatek-gen3.c
-+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -375,7 +375,13 @@ static int mtk_pcie_startup_port(struct
- msleep(100);
-
- /* De-assert reset signals */
-- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
-+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
-+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
-+
-+ msleep(100);
-+
-+ /* De-assert PERST# signals */
-+ val &= ~(PCIE_PE_RSTB);
- writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
-
- /* Check if the link is up or not */
+++ /dev/null
-From 50cefacc6c001eea1d9b1c78ba27304566f304f1 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 2 Jun 2023 13:06:26 +0800
-Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg
-
-Patch from Sam Shih <sam.shih@mediatek.com> found in MediaTek SDK
-released under GPL.
-
-Get syscon and use it to set the PHY type.
-Extend support to PCIe and SGMII mode in addition to USB2 and USB3.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/phy/mediatek/phy-mtk-xsphy.c | 81 +++++++++++++++++++++++++++-
- 1 file changed, 80 insertions(+), 1 deletion(-)
-
---- a/drivers/phy/mediatek/phy-mtk-xsphy.c
-+++ b/drivers/phy/mediatek/phy-mtk-xsphy.c
-@@ -11,10 +11,12 @@
- #include <linux/clk.h>
- #include <linux/delay.h>
- #include <linux/iopoll.h>
-+#include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/of_address.h>
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
-+#include <linux/regmap.h>
-
- #include "phy-mtk-io.h"
-
-@@ -81,12 +83,22 @@
- #define XSP_SR_COEF_DIVISOR 1000
- #define XSP_FM_DET_CYCLE_CNT 1024
-
-+/* PHY switch between pcie/usb3/sgmii */
-+#define USB_PHY_SWITCH_CTRL 0x0
-+#define RG_PHY_SW_TYPE GENMASK(3, 0)
-+#define RG_PHY_SW_PCIE 0x0
-+#define RG_PHY_SW_USB3 0x1
-+#define RG_PHY_SW_SGMII 0x2
-+
- struct xsphy_instance {
- struct phy *phy;
- void __iomem *port_base;
- struct clk *ref_clk; /* reference clock of anolog phy */
- u32 index;
- u32 type;
-+ struct regmap *type_sw;
-+ u32 type_sw_reg;
-+ u32 type_sw_index;
- /* only for HQA test */
- int efuse_intr;
- int efuse_tx_imp;
-@@ -259,6 +271,10 @@ static void phy_parse_property(struct mt
- inst->efuse_intr, inst->efuse_tx_imp,
- inst->efuse_rx_imp);
- break;
-+ case PHY_TYPE_PCIE:
-+ case PHY_TYPE_SGMII:
-+ /* nothing to do */
-+ break;
- default:
- dev_err(xsphy->dev, "incompatible phy type\n");
- return;
-@@ -305,6 +321,62 @@ static void u3_phy_props_set(struct mtk_
- RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);
- }
-
-+/* type switch for usb3/pcie/sgmii */
-+static int phy_type_syscon_get(struct xsphy_instance *instance,
-+ struct device_node *dn)
-+{
-+ struct of_phandle_args args;
-+ int ret;
-+
-+ /* type switch function is optional */
-+ if (!of_property_read_bool(dn, "mediatek,syscon-type"))
-+ return 0;
-+
-+ ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
-+ 2, 0, &args);
-+ if (ret)
-+ return ret;
-+
-+ instance->type_sw_reg = args.args[0];
-+ instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
-+ instance->type_sw = syscon_node_to_regmap(args.np);
-+ of_node_put(args.np);
-+ dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
-+ instance->type_sw_reg, instance->type_sw_index);
-+
-+ return PTR_ERR_OR_ZERO(instance->type_sw);
-+}
-+
-+static int phy_type_set(struct xsphy_instance *instance)
-+{
-+ int type;
-+ u32 offset;
-+
-+ if (!instance->type_sw)
-+ return 0;
-+
-+ switch (instance->type) {
-+ case PHY_TYPE_USB3:
-+ type = RG_PHY_SW_USB3;
-+ break;
-+ case PHY_TYPE_PCIE:
-+ type = RG_PHY_SW_PCIE;
-+ break;
-+ case PHY_TYPE_SGMII:
-+ type = RG_PHY_SW_SGMII;
-+ break;
-+ case PHY_TYPE_USB2:
-+ default:
-+ return 0;
-+ }
-+
-+ offset = instance->type_sw_index * BITS_PER_BYTE;
-+ regmap_update_bits(instance->type_sw, instance->type_sw_reg,
-+ RG_PHY_SW_TYPE << offset, type << offset);
-+
-+ return 0;
-+}
-+
- static int mtk_phy_init(struct phy *phy)
- {
- struct xsphy_instance *inst = phy_get_drvdata(phy);
-@@ -325,6 +397,10 @@ static int mtk_phy_init(struct phy *phy)
- case PHY_TYPE_USB3:
- u3_phy_props_set(xsphy, inst);
- break;
-+ case PHY_TYPE_PCIE:
-+ case PHY_TYPE_SGMII:
-+ /* nothing to do, only used to set type */
-+ break;
- default:
- dev_err(xsphy->dev, "incompatible phy type\n");
- clk_disable_unprepare(inst->ref_clk);
-@@ -403,12 +479,15 @@ static struct phy *mtk_phy_xlate(struct
-
- inst->type = args->args[0];
- if (!(inst->type == PHY_TYPE_USB2 ||
-- inst->type == PHY_TYPE_USB3)) {
-+ inst->type == PHY_TYPE_USB3 ||
-+ inst->type == PHY_TYPE_PCIE ||
-+ inst->type == PHY_TYPE_SGMII)) {
- dev_err(dev, "unsupported phy type: %d\n", inst->type);
- return ERR_PTR(-EINVAL);
- }
-
- phy_parse_property(xsphy, inst);
-+ phy_type_set(inst);
-
- return inst->phy;
- }
-@@ -515,6 +594,10 @@ static int mtk_xsphy_probe(struct platfo
- retval = PTR_ERR(inst->ref_clk);
- goto put_child;
- }
-+
-+ retval = phy_type_syscon_get(inst, child_np);
-+ if (retval)
-+ goto put_child;
- }
-
- provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Fri, 4 Sep 2020 18:42:42 +0200
-Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
-
-It improves performance by eliminating the need for a cache flush for DMA on
-attached devices
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -837,6 +837,9 @@
- bus-range = <0x00 0xff>;
- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
- status = "disabled";
-+ dma-coherent;
-+ mediatek,hifsys = <&hifsys>;
-+ mediatek,cci-control = <&cci_control2>;
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
-@@ -881,6 +884,9 @@
- bus-range = <0x00 0xff>;
- ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
- status = "disabled";
-+ dma-coherent;
-+ mediatek,hifsys = <&hifsys>;
-+ mediatek,cci-control = <&cci_control2>;
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
---- a/drivers/pci/controller/pcie-mediatek.c
-+++ b/drivers/pci/controller/pcie-mediatek.c
-@@ -20,6 +20,7 @@
- #include <linux/of_address.h>
- #include <linux/of_pci.h>
- #include <linux/of_platform.h>
-+#include <linux/of_address.h>
- #include <linux/pci.h>
- #include <linux/phy/phy.h>
- #include <linux/platform_device.h>
-@@ -139,6 +140,11 @@
- #define PCIE_LINK_STATUS_V2 0x804
- #define PCIE_PORT_LINKUP_V2 BIT(10)
-
-+/* DMA channel mapping */
-+#define HIFSYS_DMA_AG_MAP 0x008
-+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0)
-+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1)
-+
- struct mtk_pcie_port;
-
- /**
-@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci
- struct mtk_pcie_port *port, *tmp;
- int err, slot;
-
-+ if (of_dma_is_coherent(node)) {
-+ struct regmap *con;
-+ u32 mask;
-+
-+ con = syscon_regmap_lookup_by_phandle(node,
-+ "mediatek,cci-control");
-+ /* enable CPU/bus coherency */
-+ if (!IS_ERR(con))
-+ regmap_write(con, 0, 3);
-+
-+ con = syscon_regmap_lookup_by_phandle(node,
-+ "mediatek,hifsys");
-+ if (IS_ERR(con)) {
-+ dev_err(dev, "missing hifsys node\n");
-+ return PTR_ERR(con);
-+ }
-+
-+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
-+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
-+ }
-+
- slot = of_get_pci_domain_nr(dev->of_node);
- if (slot < 0) {
- for_each_available_child_of_node(node, child) {
+++ /dev/null
-From: Jip de Beer <gpk6x3591g0l@opayq.com>
-Date: Sun, 9 Jan 2022 13:14:04 +0100
-Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts
-
-The lowest frequency should be 300MHz, since that is the label
-assigned to the OPP in the mt7622.dtsi device tree, while there is one
-missing zero in the actual value.
-
-To be clear, the lowest frequency should be 300MHz instead of 30MHz.
-
-As mentioned @dangowrt on the OpenWrt forum there is no benefit in
-leaving 30MHz as the lowest frequency.
-
-Signed-off-by: Jip de Beer <gpk6x3591g0l@opayq.com>
-Signed-off-by: Fritz D. Ansel <fdansel@yandex.ru>
----
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -24,7 +24,7 @@
- compatible = "operating-points-v2";
- opp-shared;
- opp-300000000 {
-- opp-hz = /bits/ 64 <30000000>;
-+ opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <950000>;
- };
-
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -23,11 +23,17 @@
- cpu_opp_table: opp-table {
- compatible = "operating-points-v2";
- opp-shared;
-- opp-300000000 {
-- opp-hz = /bits/ 64 <300000000>;
-- opp-microvolt = <950000>;
-- };
--
-+ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low
-+ * voltage condition that can cause a hang when rebooting the RT3200/E8450.
-+ *
-+ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490
-+ *
-+ * opp-300000000 {
-+ * opp-hz = /bits/ 64 <300000000>;
-+ * opp-microvolt = <950000>;
-+ * };
-+ *
-+ */
- opp-437500000 {
- opp-hz = /bits/ 64 <437500000>;
- opp-microvolt = <1000000>;
+++ /dev/null
-From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 11 Jun 2023 00:48:10 +0100
-Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs
-
-Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet
-PHYs which require calibration data from the SoC's efuse.
-Despite the similar design the driver doesn't share any code with the
-existing mediatek-ge.c.
-Add support for such PHYs by introducing a new driver with basic
-support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- MAINTAINERS | 9 +
- drivers/net/phy/Kconfig | 12 +
- drivers/net/phy/Makefile | 1 +
- drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++
- drivers/net/phy/mediatek-ge.c | 3 +-
- 5 files changed, 1140 insertions(+), 1 deletion(-)
- create mode 100644 drivers/net/phy/mediatek-ge-soc.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -12945,6 +12945,15 @@ F: drivers/net/pcs/pcs-mtk-usxgmii.c
- F: include/linux/pcs/pcs-mtk-lynxi.h
- F: include/linux/pcs/pcs-mtk-usxgmii.h
-
-+MEDIATEK ETHERNET PHY DRIVERS
-+M: Daniel Golle <daniel@makrotopia.org>
-+M: Qingfang Deng <dqfext@gmail.com>
-+M: SkyLake Huang <SkyLake.Huang@mediatek.com>
-+L: netdev@vger.kernel.org
-+S: Maintained
-+F: drivers/net/phy/mediatek-ge-soc.c
-+F: drivers/net/phy/mediatek-ge.c
-+
- MEDIATEK I2C CONTROLLER DRIVER
- M: Qii Wang <qii.wang@mediatek.com>
- L: linux-i2c@vger.kernel.org
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -314,6 +314,18 @@ config MEDIATEK_GE_PHY
- help
- Supports the MediaTek Gigabit Ethernet PHYs.
-
-+config MEDIATEK_GE_SOC_PHY
-+ tristate "MediaTek SoC Ethernet PHYs"
-+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
-+ select NVMEM_MTK_EFUSE
-+ help
-+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
-+
-+ Include support for built-in Ethernet PHYs which are present in
-+ the MT7981 and MT7988 SoCs. These PHYs need calibration data
-+ present in the SoCs efuse and will dynamically calibrate VCM
-+ (common-mode voltage) during startup.
-+
- config MICREL_PHY
- tristate "Micrel PHYs"
- depends on PTP_1588_CLOCK_OPTIONAL
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -80,6 +80,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
- obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
- obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
- obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
-+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
- obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
- obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
- obj-$(CONFIG_MICREL_PHY) += micrel.o
---- /dev/null
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -0,0 +1,1116 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+#include <linux/bitfield.h>
-+#include <linux/module.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/of_address.h>
-+#include <linux/of_platform.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/phy.h>
-+
-+#define MTK_GPHY_ID_MT7981 0x03a29461
-+#define MTK_GPHY_ID_MT7988 0x03a29481
-+
-+#define MTK_EXT_PAGE_ACCESS 0x1f
-+#define MTK_PHY_PAGE_STANDARD 0x0000
-+#define MTK_PHY_PAGE_EXTENDED_3 0x0003
-+
-+#define MTK_PHY_LPI_REG_14 0x14
-+#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
-+
-+#define MTK_PHY_LPI_REG_1c 0x1c
-+#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
-+
-+#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
-+#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
-+
-+#define ANALOG_INTERNAL_OPERATION_MAX_US 20
-+#define TXRESERVE_MIN 0
-+#define TXRESERVE_MAX 7
-+
-+#define MTK_PHY_ANARG_RG 0x10
-+#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
-+
-+/* Registers on MDIO_MMD_VEND1 */
-+#define MTK_PHY_TXVLD_DA_RG 0x12
-+#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
-+#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
-+#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
-+#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
-+#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
-+#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
-+#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
-+#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
-+#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
-+#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
-+#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
-+#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
-+#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
-+#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
-+
-+#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
-+#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
-+#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
-+
-+#define MTK_PHY_RXADC_CTRL_RG7 0xc6
-+#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
-+
-+#define MTK_PHY_RXADC_CTRL_RG9 0xc8
-+#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
-+#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
-+#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
-+#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
-+
-+#define MTK_PHY_LDO_OUTPUT_V 0xd7
-+
-+#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
-+#define MTK_PHY_RG_CAL_CKINV BIT(12)
-+#define MTK_PHY_RG_ANA_CALEN BIT(8)
-+#define MTK_PHY_RG_ZCALEN_A BIT(0)
-+
-+#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
-+#define MTK_PHY_RG_ZCALEN_B BIT(12)
-+#define MTK_PHY_RG_ZCALEN_C BIT(8)
-+#define MTK_PHY_RG_ZCALEN_D BIT(4)
-+#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
-+
-+#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
-+#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
-+
-+#define MTK_PHY_RG_TX_FILTER 0xfe
-+
-+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
-+#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
-+#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
-+
-+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
-+#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
-+
-+#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
-+#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
-+
-+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
-+#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
-+#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
-+
-+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
-+#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
-+#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
-+
-+#define MTK_PHY_RG_AD_CAL_COMP 0x17a
-+#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8)
-+
-+#define MTK_PHY_RG_AD_CAL_CLK 0x17b
-+#define MTK_PHY_DA_CAL_CLK BIT(0)
-+
-+#define MTK_PHY_RG_AD_CALIN 0x17c
-+#define MTK_PHY_DA_CALIN_FLAG BIT(0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
-+#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
-+#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
-+#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
-+#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
-+#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
-+#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
-+#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
-+#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
-+
-+#define MTK_PHY_RG_DEV1E_REG19b 0x19b
-+#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
-+
-+#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
-+#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
-+#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
-+#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
-+#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
-+#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
-+#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
-+#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
-+#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
-+#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
-+
-+#define MTK_PHY_RG_DEV1E_REG234 0x234
-+#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
-+#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
-+#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
-+
-+#define MTK_PHY_RG_LPF_CNT_VAL 0x235
-+
-+#define MTK_PHY_RG_DEV1E_REG238 0x238
-+#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
-+#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
-+
-+#define MTK_PHY_RG_DEV1E_REG239 0x239
-+#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
-+#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
-+
-+#define MTK_PHY_RG_DEV1E_REG27C 0x27c
-+#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
-+#define MTK_PHY_RG_DEV1E_REG27D 0x27d
-+#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
-+
-+#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
-+#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
-+#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
-+
-+#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
-+#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
-+#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
-+#define MTK_PHY_LPI_TR_READY BIT(9)
-+#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
-+
-+#define MTK_PHY_RG_DEV1E_REG323 0x323
-+#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
-+#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
-+
-+#define MTK_PHY_RG_DEV1E_REG324 0x324
-+#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
-+#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
-+
-+#define MTK_PHY_RG_DEV1E_REG326 0x326
-+#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
-+#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
-+#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
-+#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
-+#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
-+
-+#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
-+#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
-+
-+#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
-+#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
-+#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
-+#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
-+
-+#define MTK_PHY_RG_BG_RASEL 0x115
-+#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
-+
-+/* These macro privides efuse parsing for internal phy. */
-+#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
-+#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
-+
-+#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
-+#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
-+
-+#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
-+#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
-+
-+#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
-+#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
-+
-+enum {
-+ NO_PAIR,
-+ PAIR_A,
-+ PAIR_B,
-+ PAIR_C,
-+ PAIR_D,
-+};
-+
-+enum {
-+ GPHY_PORT0,
-+ GPHY_PORT1,
-+ GPHY_PORT2,
-+ GPHY_PORT3,
-+};
-+
-+enum calibration_mode {
-+ EFUSE_K,
-+ SW_K
-+};
-+
-+enum CAL_ITEM {
-+ REXT,
-+ TX_OFFSET,
-+ TX_AMP,
-+ TX_R50,
-+ TX_VCM
-+};
-+
-+enum CAL_MODE {
-+ EFUSE_M,
-+ SW_M
-+};
-+
-+static int mtk_socphy_read_page(struct phy_device *phydev)
-+{
-+ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-+}
-+
-+static int mtk_socphy_write_page(struct phy_device *phydev, int page)
-+{
-+ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
-+}
-+
-+/* One calibration cycle consists of:
-+ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
-+ * until AD_CAL_COMP is ready to output calibration result.
-+ * 2.Wait until DA_CAL_CLK is available.
-+ * 3.Fetch AD_CAL_COMP_OUT.
-+ */
-+static int cal_cycle(struct phy_device *phydev, int devad,
-+ u32 regnum, u16 mask, u16 cal_val)
-+{
-+ int reg_val;
-+ int ret;
-+
-+ phy_modify_mmd(phydev, devad, regnum,
-+ mask, cal_val);
-+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
-+ MTK_PHY_DA_CALIN_FLAG);
-+
-+ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_AD_CAL_CLK, reg_val,
-+ reg_val & MTK_PHY_DA_CAL_CLK, 500,
-+ ANALOG_INTERNAL_OPERATION_MAX_US, false);
-+ if (ret) {
-+ phydev_err(phydev, "Calibration cycle timeout\n");
-+ return ret;
-+ }
-+
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
-+ MTK_PHY_DA_CALIN_FLAG);
-+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >>
-+ MTK_PHY_AD_CAL_COMP_OUT_SHIFT;
-+ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
-+
-+ return ret;
-+}
-+
-+static int rext_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
-+ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
-+ MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
-+
-+ return 0;
-+}
-+
-+static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+ u16 rext_cal_val[2];
-+
-+ rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
-+ rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
-+ rext_fill_result(phydev, rext_cal_val);
-+
-+ return 0;
-+}
-+
-+static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
-+ MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
-+ MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
-+ MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
-+ MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
-+
-+ return 0;
-+}
-+
-+static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+ u16 tx_offset_cal_val[4];
-+
-+ tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
-+ tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
-+ tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
-+ tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
-+
-+ tx_offset_fill_result(phydev, tx_offset_cal_val);
-+
-+ return 0;
-+}
-+
-+static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
-+{
-+ int i;
-+ int bias[16] = {};
-+ const int vals_9461[16] = { 7, 1, 4, 7,
-+ 7, 1, 4, 7,
-+ 7, 1, 4, 7,
-+ 7, 1, 4, 7 };
-+ const int vals_9481[16] = { 10, 6, 6, 10,
-+ 10, 6, 6, 10,
-+ 10, 6, 6, 10,
-+ 10, 6, 6, 10 };
-+ switch (phydev->drv->phy_id) {
-+ case MTK_GPHY_ID_MT7981:
-+ /* We add some calibration to efuse values
-+ * due to board level influence.
-+ * GBE: +7, TBT: +1, HBT: +4, TST: +7
-+ */
-+ memcpy(bias, (const void *)vals_9461, sizeof(bias));
-+ break;
-+ case MTK_GPHY_ID_MT7988:
-+ memcpy(bias, (const void *)vals_9481, sizeof(bias));
-+ break;
-+ }
-+
-+ /* Prevent overflow */
-+ for (i = 0; i < 12; i++) {
-+ if (buf[i >> 2] + bias[i] > 63) {
-+ buf[i >> 2] = 63;
-+ bias[i] = 0;
-+ }
-+ }
-+
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
-+ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
-+ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
-+ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
-+ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]);
-+
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
-+ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
-+ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
-+ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
-+ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]);
-+
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
-+ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
-+ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
-+ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
-+ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]);
-+
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
-+ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
-+ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
-+ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
-+ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]);
-+
-+ return 0;
-+}
-+
-+static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
-+{
-+ u16 tx_amp_cal_val[4];
-+
-+ tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
-+ tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
-+ tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
-+ tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
-+ tx_amp_fill_result(phydev, tx_amp_cal_val);
-+
-+ return 0;
-+}
-+
-+static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
-+ u8 txg_calen_x)
-+{
-+ int bias = 0;
-+ u16 reg, val;
-+
-+ if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
-+ bias = -2;
-+
-+ val = clamp_val(bias + tx_r50_cal_val, 0, 63);
-+
-+ switch (txg_calen_x) {
-+ case PAIR_A:
-+ reg = MTK_PHY_DA_TX_R50_PAIR_A;
-+ break;
-+ case PAIR_B:
-+ reg = MTK_PHY_DA_TX_R50_PAIR_B;
-+ break;
-+ case PAIR_C:
-+ reg = MTK_PHY_DA_TX_R50_PAIR_C;
-+ break;
-+ case PAIR_D:
-+ reg = MTK_PHY_DA_TX_R50_PAIR_D;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
-+
-+ return 0;
-+}
-+
-+static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
-+ u8 txg_calen_x)
-+{
-+ u16 tx_r50_cal_val;
-+
-+ switch (txg_calen_x) {
-+ case PAIR_A:
-+ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
-+ break;
-+ case PAIR_B:
-+ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
-+ break;
-+ case PAIR_C:
-+ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
-+ break;
-+ case PAIR_D:
-+ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
-+
-+ return 0;
-+}
-+
-+static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
-+{
-+ u8 lower_idx, upper_idx, txreserve_val;
-+ u8 lower_ret, upper_ret;
-+ int ret;
-+
-+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+ MTK_PHY_RG_ANA_CALEN);
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+ MTK_PHY_RG_CAL_CKINV);
-+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+ MTK_PHY_RG_TXVOS_CALEN);
-+
-+ switch (rg_txreserve_x) {
-+ case PAIR_A:
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_DASN_DAC_IN0_A,
-+ MTK_PHY_DASN_DAC_IN0_A_MASK);
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_DASN_DAC_IN1_A,
-+ MTK_PHY_DASN_DAC_IN1_A_MASK);
-+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_ANA_CAL_RG0,
-+ MTK_PHY_RG_ZCALEN_A);
-+ break;
-+ case PAIR_B:
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_DASN_DAC_IN0_B,
-+ MTK_PHY_DASN_DAC_IN0_B_MASK);
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_DASN_DAC_IN1_B,
-+ MTK_PHY_DASN_DAC_IN1_B_MASK);
-+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_ANA_CAL_RG1,
-+ MTK_PHY_RG_ZCALEN_B);
-+ break;
-+ case PAIR_C:
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_DASN_DAC_IN0_C,
-+ MTK_PHY_DASN_DAC_IN0_C_MASK);
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_DASN_DAC_IN1_C,
-+ MTK_PHY_DASN_DAC_IN1_C_MASK);
-+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_ANA_CAL_RG1,
-+ MTK_PHY_RG_ZCALEN_C);
-+ break;
-+ case PAIR_D:
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_DASN_DAC_IN0_D,
-+ MTK_PHY_DASN_DAC_IN0_D_MASK);
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_DASN_DAC_IN1_D,
-+ MTK_PHY_DASN_DAC_IN1_D_MASK);
-+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_ANA_CAL_RG1,
-+ MTK_PHY_RG_ZCALEN_D);
-+ break;
-+ default:
-+ ret = -EINVAL;
-+ goto restore;
-+ }
-+
-+ lower_idx = TXRESERVE_MIN;
-+ upper_idx = TXRESERVE_MAX;
-+
-+ phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
-+ while ((upper_idx - lower_idx) > 1) {
-+ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
-+ ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+ MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+ MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+ MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+ MTK_PHY_DA_RX_PSBN_LP_MASK,
-+ txreserve_val << 12 | txreserve_val << 8 |
-+ txreserve_val << 4 | txreserve_val);
-+ if (ret == 1) {
-+ upper_idx = txreserve_val;
-+ upper_ret = ret;
-+ } else if (ret == 0) {
-+ lower_idx = txreserve_val;
-+ lower_ret = ret;
-+ } else {
-+ goto restore;
-+ }
-+ }
-+
-+ if (lower_idx == TXRESERVE_MIN) {
-+ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RXADC_CTRL_RG9,
-+ MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+ MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+ MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+ MTK_PHY_DA_RX_PSBN_LP_MASK,
-+ lower_idx << 12 | lower_idx << 8 |
-+ lower_idx << 4 | lower_idx);
-+ ret = lower_ret;
-+ } else if (upper_idx == TXRESERVE_MAX) {
-+ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RXADC_CTRL_RG9,
-+ MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+ MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+ MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+ MTK_PHY_DA_RX_PSBN_LP_MASK,
-+ upper_idx << 12 | upper_idx << 8 |
-+ upper_idx << 4 | upper_idx);
-+ ret = upper_ret;
-+ }
-+ if (ret < 0)
-+ goto restore;
-+
-+ /* We calibrate TX-VCM in different logic. Check upper index and then
-+ * lower index. If this calibration is valid, apply lower index's result.
-+ */
-+ ret = upper_ret - lower_ret;
-+ if (ret == 1) {
-+ ret = 0;
-+ /* Make sure we use upper_idx in our calibration system */
-+ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+ MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+ MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+ MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+ MTK_PHY_DA_RX_PSBN_LP_MASK,
-+ upper_idx << 12 | upper_idx << 8 |
-+ upper_idx << 4 | upper_idx);
-+ phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
-+ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
-+ lower_ret == 1) {
-+ ret = 0;
-+ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
-+ MTK_PHY_DA_RX_PSBN_TBT_MASK |
-+ MTK_PHY_DA_RX_PSBN_HBT_MASK |
-+ MTK_PHY_DA_RX_PSBN_GBE_MASK |
-+ MTK_PHY_DA_RX_PSBN_LP_MASK,
-+ lower_idx << 12 | lower_idx << 8 |
-+ lower_idx << 4 | lower_idx);
-+ phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
-+ lower_idx);
-+ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
-+ lower_ret == 0) {
-+ ret = 0;
-+ phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n",
-+ upper_idx);
-+ } else {
-+ ret = -EINVAL;
-+ }
-+
-+restore:
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+ MTK_PHY_RG_ANA_CALEN);
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+ MTK_PHY_RG_TXVOS_CALEN);
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
-+ MTK_PHY_RG_ZCALEN_A);
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
-+ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
-+ MTK_PHY_RG_ZCALEN_D);
-+
-+ return ret;
-+}
-+
-+static void mt798x_phy_common_finetune(struct phy_device *phydev)
-+{
-+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+ /* EnabRandUpdTrig = 1 */
-+ __phy_write(phydev, 0x11, 0x2f00);
-+ __phy_write(phydev, 0x12, 0xe);
-+ __phy_write(phydev, 0x10, 0x8fb0);
-+
-+ /* NormMseLoThresh = 85 */
-+ __phy_write(phydev, 0x11, 0x55a0);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x83aa);
-+
-+ /* TrFreeze = 0 */
-+ __phy_write(phydev, 0x11, 0x0);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x9686);
-+
-+ /* SSTrKp1000Slv = 5 */
-+ __phy_write(phydev, 0x11, 0xbaef);
-+ __phy_write(phydev, 0x12, 0x2e);
-+ __phy_write(phydev, 0x10, 0x968c);
-+
-+ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
-+ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
-+ */
-+ __phy_write(phydev, 0x11, 0xd10a);
-+ __phy_write(phydev, 0x12, 0x34);
-+ __phy_write(phydev, 0x10, 0x8f82);
-+
-+ /* VcoSlicerThreshBitsHigh */
-+ __phy_write(phydev, 0x11, 0x5555);
-+ __phy_write(phydev, 0x12, 0x55);
-+ __phy_write(phydev, 0x10, 0x8ec0);
-+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
-+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
-+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-+
-+ /* rg_tr_lpf_cnt_val = 512 */
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
-+
-+ /* IIR2 related */
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
-+
-+ /* FFE peaking */
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
-+ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
-+ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
-+
-+ /* Disable LDO pump */
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
-+ /* Adjust LDO output voltage */
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
-+}
-+
-+static void mt7981_phy_finetune(struct phy_device *phydev)
-+{
-+ u16 val[8] = { 0x01ce, 0x01c1,
-+ 0x020f, 0x0202,
-+ 0x03d0, 0x03c0,
-+ 0x0013, 0x0005 };
-+ int i, k;
-+
-+ /* 100M eye finetune:
-+ * Keep middle level of TX MLT3 shapper as default.
-+ * Only change TX MLT3 overshoot level here.
-+ */
-+ for (k = 0, i = 1; i < 12; i++) {
-+ if (i % 3 == 0)
-+ continue;
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
-+ }
-+
-+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
-+ __phy_write(phydev, 0x11, 0xc71);
-+ __phy_write(phydev, 0x12, 0xc);
-+ __phy_write(phydev, 0x10, 0x8fae);
-+
-+ /* ResetSyncOffset = 6 */
-+ __phy_write(phydev, 0x11, 0x600);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x8fc0);
-+
-+ /* VgaDecRate = 1 */
-+ __phy_write(phydev, 0x11, 0x4c2a);
-+ __phy_write(phydev, 0x12, 0x3e);
-+ __phy_write(phydev, 0x10, 0x8fa4);
-+
-+ /* FfeUpdGainForce = 4 */
-+ __phy_write(phydev, 0x11, 0x240);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x9680);
-+
-+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt7988_phy_finetune(struct phy_device *phydev)
-+{
-+ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
-+ 0x020d, 0x0206, 0x0384, 0x03d0,
-+ 0x03c6, 0x030a, 0x0011, 0x0005 };
-+ int i;
-+
-+ /* Set default MLT3 shaper first */
-+ for (i = 0; i < 12; i++)
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
-+
-+ /* TCT finetune */
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
-+
-+ /* Disable TX power saving */
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
-+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-+
-+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+
-+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
-+ __phy_write(phydev, 0x11, 0x671);
-+ __phy_write(phydev, 0x12, 0xc);
-+ __phy_write(phydev, 0x10, 0x8fae);
-+
-+ /* ResetSyncOffset = 5 */
-+ __phy_write(phydev, 0x11, 0x500);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x8fc0);
-+
-+ /* VgaDecRate is 1 at default on mt7988 */
-+
-+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
-+ /* TxClkOffset = 2 */
-+ __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
-+ FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
-+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt798x_phy_eee(struct phy_device *phydev)
-+{
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
-+ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
-+ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
-+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
-+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
-+
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
-+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+ 0xff));
-+
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_TESTMUX_ADC_CTRL,
-+ MTK_PHY_RG_TXEN_DIG_MASK);
-+
-+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
-+
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
-+
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
-+ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
-+ MTK_PHY_LPI_SLV_SEND_TX_EN,
-+ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
-+
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
-+ MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
-+ MTK_PHY_LPI_TXPCS_LOC_RCV,
-+ FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
-+
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
-+ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
-+ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
-+ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
-+
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
-+ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
-+ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
-+ 0x33) |
-+ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
-+ MTK_PHY_LPI_VCO_EEE_STG0_EN);
-+
-+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
-+ MTK_PHY_EEE_WAKE_MAS_INT_DC |
-+ MTK_PHY_EEE_WAKE_SLV_INT_DC);
-+
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
-+ MTK_PHY_SMI_DETCNT_MAX_MASK,
-+ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
-+ MTK_PHY_SMI_DET_MAX_EN);
-+
-+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
-+ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
-+ MTK_PHY_TREC_UPDATE_ENAB_CLR |
-+ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
-+ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
-+
-+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+ /* Regsigdet_sel_1000 = 0 */
-+ __phy_write(phydev, 0x11, 0xb);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x9690);
-+
-+ /* REG_EEE_st2TrKf1000 = 3 */
-+ __phy_write(phydev, 0x11, 0x114f);
-+ __phy_write(phydev, 0x12, 0x2);
-+ __phy_write(phydev, 0x10, 0x969a);
-+
-+ /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
-+ __phy_write(phydev, 0x11, 0x3028);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x969e);
-+
-+ /* RegEEE_slv_wake_int_timer_tar = 8 */
-+ __phy_write(phydev, 0x11, 0x5010);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x96a0);
-+
-+ /* RegEEE_trfreeze_timer2 = 586 */
-+ __phy_write(phydev, 0x11, 0x24a);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x96a8);
-+
-+ /* RegEEE100Stg1_tar = 16 */
-+ __phy_write(phydev, 0x11, 0x3210);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x96b8);
-+
-+ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
-+ __phy_write(phydev, 0x11, 0x1463);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x96ca);
-+
-+ /* DfeTailEnableVgaThresh1000 = 27 */
-+ __phy_write(phydev, 0x11, 0x36);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x8f80);
-+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
-+ __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
-+ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
-+
-+ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
-+ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
-+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1,
-+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
-+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
-+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff));
-+}
-+
-+static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+ u8 start_pair, u8 end_pair)
-+{
-+ u8 pair_n;
-+ int ret;
-+
-+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
-+ /* TX_OFFSET & TX_AMP have no SW calibration. */
-+ switch (cal_item) {
-+ case TX_VCM:
-+ ret = tx_vcm_cal_sw(phydev, pair_n);
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+ if (ret)
-+ return ret;
-+ }
-+ return 0;
-+}
-+
-+static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+ u8 start_pair, u8 end_pair, u32 *buf)
-+{
-+ u8 pair_n;
-+ int ret;
-+
-+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
-+ /* TX_VCM has no efuse calibration. */
-+ switch (cal_item) {
-+ case REXT:
-+ ret = rext_cal_efuse(phydev, buf);
-+ break;
-+ case TX_OFFSET:
-+ ret = tx_offset_cal_efuse(phydev, buf);
-+ break;
-+ case TX_AMP:
-+ ret = tx_amp_cal_efuse(phydev, buf);
-+ break;
-+ case TX_R50:
-+ ret = tx_r50_cal_efuse(phydev, buf, pair_n);
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+ if (ret)
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
-+ enum CAL_MODE cal_mode, u8 start_pair,
-+ u8 end_pair, u32 *buf)
-+{
-+ int ret;
-+
-+ switch (cal_mode) {
-+ case EFUSE_M:
-+ ret = cal_efuse(phydev, cal_item, start_pair,
-+ end_pair, buf);
-+ break;
-+ case SW_M:
-+ ret = cal_sw(phydev, cal_item, start_pair, end_pair);
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ if (ret) {
-+ phydev_err(phydev, "cal %d failed\n", cal_item);
-+ return -EIO;
-+ }
-+
-+ return 0;
-+}
-+
-+static int mt798x_phy_calibration(struct phy_device *phydev)
-+{
-+ int ret = 0;
-+ u32 *buf;
-+ size_t len;
-+ struct nvmem_cell *cell;
-+
-+ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
-+ if (IS_ERR(cell)) {
-+ if (PTR_ERR(cell) == -EPROBE_DEFER)
-+ return PTR_ERR(cell);
-+ return 0;
-+ }
-+
-+ buf = (u32 *)nvmem_cell_read(cell, &len);
-+ if (IS_ERR(buf))
-+ return PTR_ERR(buf);
-+ nvmem_cell_put(cell);
-+
-+ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
-+ phydev_err(phydev, "invalid efuse data\n");
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+
-+ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+ if (ret)
-+ goto out;
-+ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+ if (ret)
-+ goto out;
-+ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
-+ if (ret)
-+ goto out;
-+ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
-+ if (ret)
-+ goto out;
-+ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
-+ if (ret)
-+ goto out;
-+
-+out:
-+ kfree(buf);
-+ return ret;
-+}
-+
-+static int mt798x_phy_config_init(struct phy_device *phydev)
-+{
-+ switch (phydev->drv->phy_id) {
-+ case MTK_GPHY_ID_MT7981:
-+ mt7981_phy_finetune(phydev);
-+ break;
-+ case MTK_GPHY_ID_MT7988:
-+ mt7988_phy_finetune(phydev);
-+ break;
-+ }
-+
-+ mt798x_phy_common_finetune(phydev);
-+ mt798x_phy_eee(phydev);
-+
-+ return mt798x_phy_calibration(phydev);
-+}
-+
-+static struct phy_driver mtk_socphy_driver[] = {
-+ {
-+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
-+ .name = "MediaTek MT7981 PHY",
-+ .config_init = mt798x_phy_config_init,
-+ .config_intr = genphy_no_config_intr,
-+ .handle_interrupt = genphy_handle_interrupt_no_ack,
-+ .probe = mt798x_phy_calibration,
-+ .suspend = genphy_suspend,
-+ .resume = genphy_resume,
-+ .read_page = mtk_socphy_read_page,
-+ .write_page = mtk_socphy_write_page,
-+ },
-+ {
-+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
-+ .name = "MediaTek MT7988 PHY",
-+ .config_init = mt798x_phy_config_init,
-+ .config_intr = genphy_no_config_intr,
-+ .handle_interrupt = genphy_handle_interrupt_no_ack,
-+ .probe = mt798x_phy_calibration,
-+ .suspend = genphy_suspend,
-+ .resume = genphy_resume,
-+ .read_page = mtk_socphy_read_page,
-+ .write_page = mtk_socphy_write_page,
-+ },
-+};
-+
-+module_phy_driver(mtk_socphy_driver);
-+
-+static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
-+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
-+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
-+ { }
-+};
-+
-+MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
-+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
-+MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
-+MODULE_LICENSE("GPL");
-+
-+MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
---- a/drivers/net/phy/mediatek-ge.c
-+++ b/drivers/net/phy/mediatek-ge.c
-@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive
- module_phy_driver(mtk_gephy_driver);
-
- static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
-- { PHY_ID_MATCH_VENDOR(0x03a29400) },
-+ { PHY_ID_MATCH_EXACT(0x03a29441) },
-+ { PHY_ID_MATCH_EXACT(0x03a29412) },
- { }
- };
-
+++ /dev/null
-From c66937b0f8dbb4c6c043663c702b1053fb47fab2 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 14 Aug 2023 02:58:14 +0100
-Subject: [PATCH] net: phy: mediatek-ge-soc: support PHY LEDs
-
-Implement netdev trigger and primitive bliking offloading as well as
-simple set_brigthness function for both PHY LEDs of the in-SoC PHYs
-found in MT7981 and MT7988.
-
-For MT7988, read boottrap register and apply LED polarities accordingly
-to get uniform behavior from all LEDs on MT7988.
-This requires syscon phandle 'mediatek,pio' present in parenting MDIO bus
-which should point to the syscon holding the boottrap register.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Link: https://lore.kernel.org/r/dc324d48c00cd7350f3a506eaa785324cae97372.1691977904.git.daniel@makrotopia.org
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/phy/mediatek-ge-soc.c | 435 +++++++++++++++++++++++++++++-
- 1 file changed, 426 insertions(+), 9 deletions(-)
-
---- a/drivers/net/phy/mediatek-ge-soc.c
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -1,11 +1,14 @@
- // SPDX-License-Identifier: GPL-2.0+
- #include <linux/bitfield.h>
-+#include <linux/bitmap.h>
-+#include <linux/mfd/syscon.h>
- #include <linux/module.h>
- #include <linux/nvmem-consumer.h>
- #include <linux/of_address.h>
- #include <linux/of_platform.h>
- #include <linux/pinctrl/consumer.h>
- #include <linux/phy.h>
-+#include <linux/regmap.h>
-
- #define MTK_GPHY_ID_MT7981 0x03a29461
- #define MTK_GPHY_ID_MT7988 0x03a29481
-@@ -208,9 +211,42 @@
- #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
- #define MTK_PHY_DA_TX_R50_PAIR_D 0x540
-
-+/* Registers on MDIO_MMD_VEND2 */
-+#define MTK_PHY_LED0_ON_CTRL 0x24
-+#define MTK_PHY_LED1_ON_CTRL 0x26
-+#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
-+#define MTK_PHY_LED_ON_LINK1000 BIT(0)
-+#define MTK_PHY_LED_ON_LINK100 BIT(1)
-+#define MTK_PHY_LED_ON_LINK10 BIT(2)
-+#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
-+#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
-+#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
-+#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
-+#define MTK_PHY_LED_ON_POLARITY BIT(14)
-+#define MTK_PHY_LED_ON_ENABLE BIT(15)
-+
-+#define MTK_PHY_LED0_BLINK_CTRL 0x25
-+#define MTK_PHY_LED1_BLINK_CTRL 0x27
-+#define MTK_PHY_LED_BLINK_1000TX BIT(0)
-+#define MTK_PHY_LED_BLINK_1000RX BIT(1)
-+#define MTK_PHY_LED_BLINK_100TX BIT(2)
-+#define MTK_PHY_LED_BLINK_100RX BIT(3)
-+#define MTK_PHY_LED_BLINK_10TX BIT(4)
-+#define MTK_PHY_LED_BLINK_10RX BIT(5)
-+#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
-+#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
-+#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
-+#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
-+
-+#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
-+
- #define MTK_PHY_RG_BG_RASEL 0x115
- #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
-
-+/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
-+#define RG_GPIO_MISC_TPBANK0 0x6f0
-+#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
-+
- /* These macro privides efuse parsing for internal phy. */
- #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
- #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
-@@ -238,13 +274,6 @@ enum {
- PAIR_D,
- };
-
--enum {
-- GPHY_PORT0,
-- GPHY_PORT1,
-- GPHY_PORT2,
-- GPHY_PORT3,
--};
--
- enum calibration_mode {
- EFUSE_K,
- SW_K
-@@ -263,6 +292,19 @@ enum CAL_MODE {
- SW_M
- };
-
-+#define MTK_PHY_LED_STATE_FORCE_ON 0
-+#define MTK_PHY_LED_STATE_FORCE_BLINK 1
-+#define MTK_PHY_LED_STATE_NETDEV 2
-+
-+struct mtk_socphy_priv {
-+ unsigned long led_state;
-+};
-+
-+struct mtk_socphy_shared {
-+ u32 boottrap;
-+ struct mtk_socphy_priv priv[4];
-+};
-+
- static int mtk_socphy_read_page(struct phy_device *phydev)
- {
- return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
-@@ -1073,6 +1115,371 @@ static int mt798x_phy_config_init(struct
- return mt798x_phy_calibration(phydev);
- }
-
-+static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
-+ bool on)
-+{
-+ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
-+ struct mtk_socphy_priv *priv = phydev->priv;
-+ bool changed;
-+
-+ if (on)
-+ changed = !test_and_set_bit(bit_on, &priv->led_state);
-+ else
-+ changed = !!test_and_clear_bit(bit_on, &priv->led_state);
-+
-+ changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
-+ (index ? 16 : 0), &priv->led_state);
-+ if (changed)
-+ return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
-+ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
-+ MTK_PHY_LED_ON_MASK,
-+ on ? MTK_PHY_LED_ON_FORCE_ON : 0);
-+ else
-+ return 0;
-+}
-+
-+static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
-+ bool blinking)
-+{
-+ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
-+ struct mtk_socphy_priv *priv = phydev->priv;
-+ bool changed;
-+
-+ if (blinking)
-+ changed = !test_and_set_bit(bit_blink, &priv->led_state);
-+ else
-+ changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
-+
-+ changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
-+ (index ? 16 : 0), &priv->led_state);
-+ if (changed)
-+ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
-+ MTK_PHY_LED1_BLINK_CTRL : MTK_PHY_LED0_BLINK_CTRL,
-+ blinking ? MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
-+ else
-+ return 0;
-+}
-+
-+static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
-+ unsigned long *delay_on,
-+ unsigned long *delay_off)
-+{
-+ bool blinking = false;
-+ int err = 0;
-+
-+ if (index > 1)
-+ return -EINVAL;
-+
-+ if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
-+ blinking = true;
-+ *delay_on = 50;
-+ *delay_off = 50;
-+ }
-+
-+ err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
-+ if (err)
-+ return err;
-+
-+ return mt798x_phy_hw_led_on_set(phydev, index, false);
-+}
-+
-+static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
-+ u8 index, enum led_brightness value)
-+{
-+ int err;
-+
-+ err = mt798x_phy_hw_led_blink_set(phydev, index, false);
-+ if (err)
-+ return err;
-+
-+ return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
-+}
-+
-+static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
-+ BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
-+ BIT(TRIGGER_NETDEV_LINK) |
-+ BIT(TRIGGER_NETDEV_LINK_10) |
-+ BIT(TRIGGER_NETDEV_LINK_100) |
-+ BIT(TRIGGER_NETDEV_LINK_1000) |
-+ BIT(TRIGGER_NETDEV_RX) |
-+ BIT(TRIGGER_NETDEV_TX));
-+
-+static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
-+ unsigned long rules)
-+{
-+ if (index > 1)
-+ return -EINVAL;
-+
-+ /* All combinations of the supported triggers are allowed */
-+ if (rules & ~supported_triggers)
-+ return -EOPNOTSUPP;
-+
-+ return 0;
-+};
-+
-+static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
-+ unsigned long *rules)
-+{
-+ unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK + (index ? 16 : 0);
-+ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
-+ unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
-+ struct mtk_socphy_priv *priv = phydev->priv;
-+ int on, blink;
-+
-+ if (index > 1)
-+ return -EINVAL;
-+
-+ on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
-+ index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
-+
-+ if (on < 0)
-+ return -EIO;
-+
-+ blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
-+ index ? MTK_PHY_LED1_BLINK_CTRL :
-+ MTK_PHY_LED0_BLINK_CTRL);
-+ if (blink < 0)
-+ return -EIO;
-+
-+ if ((on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 |
-+ MTK_PHY_LED_ON_LINK10)) ||
-+ (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX |
-+ MTK_PHY_LED_BLINK_10RX | MTK_PHY_LED_BLINK_1000TX |
-+ MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX)))
-+ set_bit(bit_netdev, &priv->led_state);
-+ else
-+ clear_bit(bit_netdev, &priv->led_state);
-+
-+ if (on & MTK_PHY_LED_ON_FORCE_ON)
-+ set_bit(bit_on, &priv->led_state);
-+ else
-+ clear_bit(bit_on, &priv->led_state);
-+
-+ if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
-+ set_bit(bit_blink, &priv->led_state);
-+ else
-+ clear_bit(bit_blink, &priv->led_state);
-+
-+ if (!rules)
-+ return 0;
-+
-+ if (on & (MTK_PHY_LED_ON_LINK1000 | MTK_PHY_LED_ON_LINK100 | MTK_PHY_LED_ON_LINK10))
-+ *rules |= BIT(TRIGGER_NETDEV_LINK);
-+
-+ if (on & MTK_PHY_LED_ON_LINK10)
-+ *rules |= BIT(TRIGGER_NETDEV_LINK_10);
-+
-+ if (on & MTK_PHY_LED_ON_LINK100)
-+ *rules |= BIT(TRIGGER_NETDEV_LINK_100);
-+
-+ if (on & MTK_PHY_LED_ON_LINK1000)
-+ *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
-+
-+ if (on & MTK_PHY_LED_ON_FDX)
-+ *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
-+
-+ if (on & MTK_PHY_LED_ON_HDX)
-+ *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
-+
-+ if (blink & (MTK_PHY_LED_BLINK_1000RX | MTK_PHY_LED_BLINK_100RX | MTK_PHY_LED_BLINK_10RX))
-+ *rules |= BIT(TRIGGER_NETDEV_RX);
-+
-+ if (blink & (MTK_PHY_LED_BLINK_1000TX | MTK_PHY_LED_BLINK_100TX | MTK_PHY_LED_BLINK_10TX))
-+ *rules |= BIT(TRIGGER_NETDEV_TX);
-+
-+ return 0;
-+};
-+
-+static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
-+ unsigned long rules)
-+{
-+ unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
-+ struct mtk_socphy_priv *priv = phydev->priv;
-+ u16 on = 0, blink = 0;
-+ int ret;
-+
-+ if (index > 1)
-+ return -EINVAL;
-+
-+ if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
-+ on |= MTK_PHY_LED_ON_FDX;
-+
-+ if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
-+ on |= MTK_PHY_LED_ON_HDX;
-+
-+ if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
-+ on |= MTK_PHY_LED_ON_LINK10;
-+
-+ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
-+ on |= MTK_PHY_LED_ON_LINK100;
-+
-+ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
-+ on |= MTK_PHY_LED_ON_LINK1000;
-+
-+ if (rules & BIT(TRIGGER_NETDEV_RX)) {
-+ blink |= MTK_PHY_LED_BLINK_10RX |
-+ MTK_PHY_LED_BLINK_100RX |
-+ MTK_PHY_LED_BLINK_1000RX;
-+ }
-+
-+ if (rules & BIT(TRIGGER_NETDEV_TX)) {
-+ blink |= MTK_PHY_LED_BLINK_10TX |
-+ MTK_PHY_LED_BLINK_100TX |
-+ MTK_PHY_LED_BLINK_1000TX;
-+ }
-+
-+ if (blink || on)
-+ set_bit(bit_netdev, &priv->led_state);
-+ else
-+ clear_bit(bit_netdev, &priv->led_state);
-+
-+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
-+ MTK_PHY_LED1_ON_CTRL :
-+ MTK_PHY_LED0_ON_CTRL,
-+ MTK_PHY_LED_ON_FDX |
-+ MTK_PHY_LED_ON_HDX |
-+ MTK_PHY_LED_ON_LINK10 |
-+ MTK_PHY_LED_ON_LINK100 |
-+ MTK_PHY_LED_ON_LINK1000,
-+ on);
-+
-+ if (ret)
-+ return ret;
-+
-+ return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
-+ MTK_PHY_LED1_BLINK_CTRL :
-+ MTK_PHY_LED0_BLINK_CTRL, blink);
-+};
-+
-+static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
-+{
-+ struct mtk_socphy_shared *priv = phydev->shared->priv;
-+ u32 polarities;
-+
-+ if (led_num == 0)
-+ polarities = ~(priv->boottrap);
-+ else
-+ polarities = MTK_PHY_LED1_DEFAULT_POLARITIES;
-+
-+ if (polarities & BIT(phydev->mdio.addr))
-+ return true;
-+
-+ return false;
-+}
-+
-+static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
-+{
-+ struct pinctrl *pinctrl;
-+ int index;
-+
-+ /* Setup LED polarity according to bootstrap use of LED pins */
-+ for (index = 0; index < 2; ++index)
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
-+ MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
-+ MTK_PHY_LED_ON_POLARITY,
-+ mt7988_phy_led_get_polarity(phydev, index) ?
-+ MTK_PHY_LED_ON_POLARITY : 0);
-+
-+ /* Only now setup pinctrl to avoid bogus blinking */
-+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
-+ if (IS_ERR(pinctrl))
-+ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n");
-+
-+ return 0;
-+}
-+
-+static int mt7988_phy_probe_shared(struct phy_device *phydev)
-+{
-+ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
-+ struct mtk_socphy_shared *shared = phydev->shared->priv;
-+ struct regmap *regmap;
-+ u32 reg;
-+ int ret;
-+
-+ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
-+ * LED_C and LED_D respectively. At the same time those pins are used to
-+ * bootstrap configuration of the reference clock source (LED_A),
-+ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
-+ * In practise this is done using a LED and a resistor pulling the pin
-+ * either to GND or to VIO.
-+ * The detected value at boot time is accessible at run-time using the
-+ * TPBANK0 register located in the gpio base of the pinctrl, in order
-+ * to read it here it needs to be referenced by a phandle called
-+ * 'mediatek,pio' in the MDIO bus hosting the PHY.
-+ * The 4 bits in TPBANK0 are kept as package shared data and are used to
-+ * set LED polarity for each of the LED0.
-+ */
-+ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
-+ if (IS_ERR(regmap))
-+ return PTR_ERR(regmap);
-+
-+ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®);
-+ if (ret)
-+ return ret;
-+
-+ shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
-+
-+ return 0;
-+}
-+
-+static void mt798x_phy_leds_state_init(struct phy_device *phydev)
-+{
-+ int i;
-+
-+ for (i = 0; i < 2; ++i)
-+ mt798x_phy_led_hw_control_get(phydev, i, NULL);
-+}
-+
-+static int mt7988_phy_probe(struct phy_device *phydev)
-+{
-+ struct mtk_socphy_shared *shared;
-+ struct mtk_socphy_priv *priv;
-+ int err;
-+
-+ if (phydev->mdio.addr > 3)
-+ return -EINVAL;
-+
-+ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
-+ sizeof(struct mtk_socphy_shared));
-+ if (err)
-+ return err;
-+
-+ if (phy_package_probe_once(phydev)) {
-+ err = mt7988_phy_probe_shared(phydev);
-+ if (err)
-+ return err;
-+ }
-+
-+ shared = phydev->shared->priv;
-+ priv = &shared->priv[phydev->mdio.addr];
-+
-+ phydev->priv = priv;
-+
-+ mt798x_phy_leds_state_init(phydev);
-+
-+ err = mt7988_phy_fix_leds_polarities(phydev);
-+ if (err)
-+ return err;
-+
-+ return mt798x_phy_calibration(phydev);
-+}
-+
-+static int mt7981_phy_probe(struct phy_device *phydev)
-+{
-+ struct mtk_socphy_priv *priv;
-+
-+ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
-+ GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ phydev->priv = priv;
-+
-+ mt798x_phy_leds_state_init(phydev);
-+
-+ return mt798x_phy_calibration(phydev);
-+}
-+
- static struct phy_driver mtk_socphy_driver[] = {
- {
- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
-@@ -1080,11 +1487,16 @@ static struct phy_driver mtk_socphy_driv
- .config_init = mt798x_phy_config_init,
- .config_intr = genphy_no_config_intr,
- .handle_interrupt = genphy_handle_interrupt_no_ack,
-- .probe = mt798x_phy_calibration,
-+ .probe = mt7981_phy_probe,
- .suspend = genphy_suspend,
- .resume = genphy_resume,
- .read_page = mtk_socphy_read_page,
- .write_page = mtk_socphy_write_page,
-+ .led_blink_set = mt798x_phy_led_blink_set,
-+ .led_brightness_set = mt798x_phy_led_brightness_set,
-+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
-+ .led_hw_control_set = mt798x_phy_led_hw_control_set,
-+ .led_hw_control_get = mt798x_phy_led_hw_control_get,
- },
- {
- PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
-@@ -1092,11 +1504,16 @@ static struct phy_driver mtk_socphy_driv
- .config_init = mt798x_phy_config_init,
- .config_intr = genphy_no_config_intr,
- .handle_interrupt = genphy_handle_interrupt_no_ack,
-- .probe = mt798x_phy_calibration,
-+ .probe = mt7988_phy_probe,
- .suspend = genphy_suspend,
- .resume = genphy_resume,
- .read_page = mtk_socphy_read_page,
- .write_page = mtk_socphy_write_page,
-+ .led_blink_set = mt798x_phy_led_blink_set,
-+ .led_brightness_set = mt798x_phy_led_brightness_set,
-+ .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
-+ .led_hw_control_set = mt798x_phy_led_hw_control_set,
-+ .led_hw_control_get = mt798x_phy_led_hw_control_get,
- },
- };
-
+++ /dev/null
-From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 6 Apr 2023 23:36:50 +0100
-Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
-
-MAC drivers using phylink expect SGMII in-band-status to be switched off
-when attached to a PHY. Make sure this is the case also for mxl-gpy which
-keeps SGMII in-band-status in case of SGMII interface mode is used.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
- 1 file changed, 16 insertions(+), 3 deletions(-)
-
---- a/drivers/net/phy/mxl-gpy.c
-+++ b/drivers/net/phy/mxl-gpy.c
-@@ -371,8 +371,11 @@ static bool gpy_2500basex_chk(struct phy
-
- phydev->speed = SPEED_2500;
- phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-- VSPEC1_SGMII_CTRL_ANEN, 0);
-+
-+ if (!phydev->phylink)
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+ VSPEC1_SGMII_CTRL_ANEN, 0);
-+
- return true;
- }
-
-@@ -396,6 +399,14 @@ static int gpy_config_aneg(struct phy_de
- u32 adv;
- int ret;
-
-+ /* Disable SGMII auto-negotiation if using phylink */
-+ if (phydev->phylink) {
-+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
-+ VSPEC1_SGMII_CTRL_ANEN, 0);
-+ if (ret < 0)
-+ return ret;
-+ }
-+
- if (phydev->autoneg == AUTONEG_DISABLE) {
- /* Configure half duplex with genphy_setup_forced,
- * because genphy_c45_pma_setup_forced does not support.
-@@ -486,6 +497,8 @@ static void gpy_update_interface(struct
- switch (phydev->speed) {
- case SPEED_2500:
- phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
-+ if (phydev->phylink)
-+ break;
- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
- VSPEC1_SGMII_CTRL_ANEN, 0);
- if (ret < 0)
-@@ -497,7 +510,7 @@ static void gpy_update_interface(struct
- case SPEED_100:
- case SPEED_10:
- phydev->interface = PHY_INTERFACE_MODE_SGMII;
-- if (gpy_sgmii_aneg_en(phydev))
-+ if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
- break;
- /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
- * if ANEG is disabled (in 2500-BaseX mode).
+++ /dev/null
-From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 28 Feb 2023 17:53:37 +0000
-Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/Kconfig | 7 ++
- drivers/net/phy/Makefile | 1 +
- drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++
- 3 files changed, 226 insertions(+)
- create mode 100644 drivers/net/phy/mediatek-2p5ge.c
-
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -326,6 +326,13 @@ config MEDIATEK_GE_SOC_PHY
- present in the SoCs efuse and will dynamically calibrate VCM
- (common-mode voltage) during startup.
-
-+config MEDIATEK_2P5G_PHY
-+ tristate "MediaTek 2.5G Ethernet PHY"
-+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
-+ default NET_MEDIATEK_SOC
-+ help
-+ Supports the MediaTek 2.5G Ethernet PHY.
-+
- config MICREL_PHY
- tristate "Micrel PHYs"
- depends on PTP_1588_CLOCK_OPTIONAL
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -79,6 +79,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell
- obj-$(CONFIG_MARVELL_PHY) += marvell.o
- obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
- obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
-+obj-$(CONFIG_MEDIATEK_2P5G_PHY) += mediatek-2p5ge.o
- obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
- obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
- obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
+++ /dev/null
-From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001
-Message-ID: <f2195279c234c0f618946424b8236026126bc595.1706071311.git.daniel@makrotopia.org>
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 24 Jan 2024 02:27:04 +0000
-Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK
-To: Daniel Golle <daniel@makrotopia.org>,
- Qingfang Deng <dqfext@gmail.com>,
- SkyLake Huang <SkyLake.Huang@mediatek.com>,
- Andrew Lunn <andrew@lunn.ch>,
- Heiner Kallweit <hkallweit1@gmail.com>,
- Russell King <linux@armlinux.org.uk>,
- David S. Miller <davem@davemloft.net>,
- Eric Dumazet <edumazet@google.com>,
- Jakub Kicinski <kuba@kernel.org>,
- Paolo Abeni <pabeni@redhat.com>,
- Matthias Brugger <matthias.bgg@gmail.com>,
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
- netdev@vger.kernel.org,
- linux-kernel@vger.kernel.org,
- linux-arm-kernel@lists.infradead.org,
- linux-mediatek@lists.infradead.org
-
-Sync initialization and calibration routines with MediaTek's reference
-driver. Improves compliance and resolves link stability issues with
-CH340 IoT devices connected to MT798x built-in PHYs.
-
-Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++--------------
- 1 file changed, 81 insertions(+), 66 deletions(-)
-
---- a/drivers/net/phy/mediatek-ge-soc.c
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -491,7 +491,7 @@ static int tx_r50_fill_result(struct phy
- u16 reg, val;
-
- if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
-- bias = -2;
-+ bias = -1;
-
- val = clamp_val(bias + tx_r50_cal_val, 0, 63);
-
-@@ -707,6 +707,11 @@ restore:
- static void mt798x_phy_common_finetune(struct phy_device *phydev)
- {
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
-+ __phy_write(phydev, 0x11, 0xc71);
-+ __phy_write(phydev, 0x12, 0xc);
-+ __phy_write(phydev, 0x10, 0x8fae);
-+
- /* EnabRandUpdTrig = 1 */
- __phy_write(phydev, 0x11, 0x2f00);
- __phy_write(phydev, 0x12, 0xe);
-@@ -717,15 +722,56 @@ static void mt798x_phy_common_finetune(s
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x83aa);
-
-- /* TrFreeze = 0 */
-+ /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
-+ __phy_write(phydev, 0x11, 0x240);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x9680);
-+
-+ /* TrFreeze = 0 (mt7988 default) */
- __phy_write(phydev, 0x11, 0x0);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9686);
-
-+ /* SSTrKp100 = 5 */
-+ /* SSTrKf100 = 6 */
-+ /* SSTrKp1000Mas = 5 */
-+ /* SSTrKf1000Mas = 6 */
- /* SSTrKp1000Slv = 5 */
-+ /* SSTrKf1000Slv = 6 */
- __phy_write(phydev, 0x11, 0xbaef);
- __phy_write(phydev, 0x12, 0x2e);
- __phy_write(phydev, 0x10, 0x968c);
-+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt7981_phy_finetune(struct phy_device *phydev)
-+{
-+ u16 val[8] = { 0x01ce, 0x01c1,
-+ 0x020f, 0x0202,
-+ 0x03d0, 0x03c0,
-+ 0x0013, 0x0005 };
-+ int i, k;
-+
-+ /* 100M eye finetune:
-+ * Keep middle level of TX MLT3 shapper as default.
-+ * Only change TX MLT3 overshoot level here.
-+ */
-+ for (k = 0, i = 1; i < 12; i++) {
-+ if (i % 3 == 0)
-+ continue;
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
-+ }
-+
-+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+ /* ResetSyncOffset = 6 */
-+ __phy_write(phydev, 0x11, 0x600);
-+ __phy_write(phydev, 0x12, 0x0);
-+ __phy_write(phydev, 0x10, 0x8fc0);
-+
-+ /* VgaDecRate = 1 */
-+ __phy_write(phydev, 0x11, 0x4c2a);
-+ __phy_write(phydev, 0x12, 0x3e);
-+ __phy_write(phydev, 0x10, 0x8fa4);
-
- /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
- * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
-@@ -740,7 +786,7 @@ static void mt798x_phy_common_finetune(s
- __phy_write(phydev, 0x10, 0x8ec0);
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-
-- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
-+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
- MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
- BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-@@ -773,48 +819,6 @@ static void mt798x_phy_common_finetune(s
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
- }
-
--static void mt7981_phy_finetune(struct phy_device *phydev)
--{
-- u16 val[8] = { 0x01ce, 0x01c1,
-- 0x020f, 0x0202,
-- 0x03d0, 0x03c0,
-- 0x0013, 0x0005 };
-- int i, k;
--
-- /* 100M eye finetune:
-- * Keep middle level of TX MLT3 shapper as default.
-- * Only change TX MLT3 overshoot level here.
-- */
-- for (k = 0, i = 1; i < 12; i++) {
-- if (i % 3 == 0)
-- continue;
-- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
-- }
--
-- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
-- __phy_write(phydev, 0x11, 0xc71);
-- __phy_write(phydev, 0x12, 0xc);
-- __phy_write(phydev, 0x10, 0x8fae);
--
-- /* ResetSyncOffset = 6 */
-- __phy_write(phydev, 0x11, 0x600);
-- __phy_write(phydev, 0x12, 0x0);
-- __phy_write(phydev, 0x10, 0x8fc0);
--
-- /* VgaDecRate = 1 */
-- __phy_write(phydev, 0x11, 0x4c2a);
-- __phy_write(phydev, 0x12, 0x3e);
-- __phy_write(phydev, 0x10, 0x8fa4);
--
-- /* FfeUpdGainForce = 4 */
-- __phy_write(phydev, 0x11, 0x240);
-- __phy_write(phydev, 0x12, 0x0);
-- __phy_write(phydev, 0x10, 0x9680);
--
-- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
--}
--
- static void mt7988_phy_finetune(struct phy_device *phydev)
- {
- u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
-@@ -829,17 +833,7 @@ static void mt7988_phy_finetune(struct p
- /* TCT finetune */
- phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
-
-- /* Disable TX power saving */
-- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
-- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
--
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
--
-- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
-- __phy_write(phydev, 0x11, 0x671);
-- __phy_write(phydev, 0x12, 0xc);
-- __phy_write(phydev, 0x10, 0x8fae);
--
- /* ResetSyncOffset = 5 */
- __phy_write(phydev, 0x11, 0x500);
- __phy_write(phydev, 0x12, 0x0);
-@@ -847,13 +841,27 @@ static void mt7988_phy_finetune(struct p
-
- /* VgaDecRate is 1 at default on mt7988 */
-
-- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+ /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
-+ * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
-+ */
-+ __phy_write(phydev, 0x11, 0xb90a);
-+ __phy_write(phydev, 0x12, 0x6f);
-+ __phy_write(phydev, 0x10, 0x8f82);
-+
-+ /* RemAckCntLimitCtrl = 1 */
-+ __phy_write(phydev, 0x11, 0xfbba);
-+ __phy_write(phydev, 0x12, 0xc3);
-+ __phy_write(phydev, 0x10, 0x87f8);
-
-- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
-- /* TxClkOffset = 2 */
-- __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
-- FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
-+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
-+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
-+
-+ /* rg_tr_lpf_cnt_val = 1023 */
-+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
- }
-
- static void mt798x_phy_eee(struct phy_device *phydev)
-@@ -886,11 +894,11 @@ static void mt798x_phy_eee(struct phy_de
- MTK_PHY_LPI_SLV_SEND_TX_EN,
- FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
-
-- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
-- MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
-- MTK_PHY_LPI_TXPCS_LOC_RCV,
-- FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
-+ /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
-+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
-+ MTK_PHY_LPI_TXPCS_LOC_RCV);
-
-+ /* This also fixes some IoT issues, such as CH340 */
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
- MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
- FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
-@@ -924,7 +932,7 @@ static void mt798x_phy_eee(struct phy_de
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9690);
-
-- /* REG_EEE_st2TrKf1000 = 3 */
-+ /* REG_EEE_st2TrKf1000 = 2 */
- __phy_write(phydev, 0x11, 0x114f);
- __phy_write(phydev, 0x12, 0x2);
- __phy_write(phydev, 0x10, 0x969a);
-@@ -949,7 +957,7 @@ static void mt798x_phy_eee(struct phy_de
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x96b8);
-
-- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
-+ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
- __phy_write(phydev, 0x11, 0x1463);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x96ca);
-@@ -1461,6 +1469,13 @@ static int mt7988_phy_probe(struct phy_d
- if (err)
- return err;
-
-+ /* Disable TX power saving at probing to:
-+ * 1. Meet common mode compliance test criteria
-+ * 2. Make sure that TX-VCM calibration works fine
-+ */
-+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
-+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-+
- return mt798x_phy_calibration(phydev);
- }
-
+++ /dev/null
---- a/drivers/pwm/pwm-mediatek.c
-+++ b/drivers/pwm/pwm-mediatek.c
-@@ -329,6 +329,12 @@ static const struct pwm_mediatek_of_data
- .has_ck_26m_sel = true,
- };
-
-+static const struct pwm_mediatek_of_data mt7986_pwm_data = {
-+ .num_pwms = 2,
-+ .pwm45_fixup = false,
-+ .has_ck_26m_sel = true,
-+};
-+
- static const struct pwm_mediatek_of_data mt8516_pwm_data = {
- .num_pwms = 5,
- .pwm45_fixup = false,
-@@ -342,6 +348,7 @@ static const struct of_device_id pwm_med
- { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
- { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
- { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
-+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
- { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
- { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
- { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
+++ /dev/null
-From fae82621ac33e2a4a96220c56e90d1ec6237d394 Mon Sep 17 00:00:00 2001
-From: Sam Shih <sam.shih@mediatek.com>
-Date: Sun, 6 Nov 2022 09:01:12 +0100
-Subject: [PATCH] pinctrl: mediatek: extend pinctrl-moore to support new bias
- functions
-
-Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature")
-introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo
-and mtk_pinconf_bias_get_combo, and make the functions able to support
-almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c.
-
-This patch enables pinctrl_moore to support these functions.
-
-Signed-off-by: Sam Shih <sam.shih@mediatek.com>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/mediatek/pinctrl-moore.c | 49 ++++++++++++++++++++----
- 1 file changed, 42 insertions(+), 7 deletions(-)
-
---- a/drivers/pinctrl/mediatek/pinctrl-moore.c
-+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
-@@ -8,6 +8,7 @@
- *
- */
-
-+#include <dt-bindings/pinctrl/mt65xx.h>
- #include <linux/gpio/driver.h>
- #include "pinctrl-moore.h"
-
-@@ -105,7 +106,7 @@ static int mtk_pinconf_get(struct pinctr
- {
- struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
- u32 param = pinconf_to_config_param(*config);
-- int val, val2, err, reg, ret = 1;
-+ int val, val2, err, pullup, reg, ret = 1;
- const struct mtk_pin_desc *desc;
-
- desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
-@@ -114,7 +115,13 @@ static int mtk_pinconf_get(struct pinctr
-
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
-- if (hw->soc->bias_disable_get) {
-+ if (hw->soc->bias_get_combo) {
-+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+ if (err)
-+ return err;
-+ if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE)
-+ return -EINVAL;
-+ } else if (hw->soc->bias_disable_get) {
- err = hw->soc->bias_disable_get(hw, desc, &ret);
- if (err)
- return err;
-@@ -123,7 +130,15 @@ static int mtk_pinconf_get(struct pinctr
- }
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
-- if (hw->soc->bias_get) {
-+ if (hw->soc->bias_get_combo) {
-+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+ if (err)
-+ return err;
-+ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
-+ return -EINVAL;
-+ if (!pullup)
-+ return -EINVAL;
-+ } else if (hw->soc->bias_get) {
- err = hw->soc->bias_get(hw, desc, 1, &ret);
- if (err)
- return err;
-@@ -132,7 +147,15 @@ static int mtk_pinconf_get(struct pinctr
- }
- break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
-- if (hw->soc->bias_get) {
-+ if (hw->soc->bias_get_combo) {
-+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
-+ if (err)
-+ return err;
-+ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE)
-+ return -EINVAL;
-+ if (pullup)
-+ return -EINVAL;
-+ } else if (hw->soc->bias_get) {
- err = hw->soc->bias_get(hw, desc, 0, &ret);
- if (err)
- return err;
-@@ -235,7 +258,11 @@ static int mtk_pinconf_set(struct pinctr
-
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
-- if (hw->soc->bias_disable_set) {
-+ if (hw->soc->bias_set_combo) {
-+ err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
-+ if (err)
-+ return err;
-+ } else if (hw->soc->bias_disable_set) {
- err = hw->soc->bias_disable_set(hw, desc);
- if (err)
- return err;
-@@ -244,7 +271,11 @@ static int mtk_pinconf_set(struct pinctr
- }
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
-- if (hw->soc->bias_set) {
-+ if (hw->soc->bias_set_combo) {
-+ err = hw->soc->bias_set_combo(hw, desc, 1, arg);
-+ if (err)
-+ return err;
-+ } else if (hw->soc->bias_set) {
- err = hw->soc->bias_set(hw, desc, 1);
- if (err)
- return err;
-@@ -253,7 +284,11 @@ static int mtk_pinconf_set(struct pinctr
- }
- break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
-- if (hw->soc->bias_set) {
-+ if (hw->soc->bias_set_combo) {
-+ err = hw->soc->bias_set_combo(hw, desc, 0, arg);
-+ if (err)
-+ return err;
-+ } else if (hw->soc->bias_set) {
- err = hw->soc->bias_set(hw, desc, 0);
- if (err)
- return err;
+++ /dev/null
-From f167da186acf90847e1a6d3716e253825a6218ec Mon Sep 17 00:00:00 2001
-From: Randy Dunlap <rdunlap@infradead.org>
-Date: Thu, 12 Jan 2023 22:44:49 -0800
-Subject: [PATCH 01/42] thermal/drivers/mtk_thermal: Fix kernel-doc function
- name
-
-Use the correct function name in a kernel-doc comment to prevent
-a warning:
-
-drivers/thermal/mtk_thermal.c:562: warning: expecting prototype for raw_to_mcelsius(). Prototype was for raw_to_mcelsius_v1() instead
-
-Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
-Cc: "Rafael J. Wysocki" <rafael@kernel.org>
-Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
-Cc: Amit Kucheria <amitk@kernel.org>
-Cc: Zhang Rui <rui.zhang@intel.com>
-Cc: Matthias Brugger <matthias.bgg@gmail.com>
-Cc: linux-pm@vger.kernel.org
-Cc: linux-arm-kernel@lists.infradead.org
-Cc: linux-mediatek@lists.infradead.org
-Link: https://lore.kernel.org/r/20230113064449.15061-1-rdunlap@infradead.org
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mtk_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -550,7 +550,7 @@ static const struct mtk_thermal_data mt8
- };
-
- /**
-- * raw_to_mcelsius - convert a raw ADC value to mcelsius
-+ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
- * @mt: The thermal controller
- * @sensno: sensor number
- * @raw: raw ADC value
+++ /dev/null
-From 255509232417ee71fd606cb957d44cf6544f0c43 Mon Sep 17 00:00:00 2001
-From: ye xingchen <ye.xingchen@zte.com.cn>
-Date: Wed, 18 Jan 2023 16:37:47 +0800
-Subject: [PATCH 02/42] thermal/drivers/mtk_thermal: Use
- devm_platform_get_and_ioremap_resource()
-
-Convert platform_get_resource(), devm_ioremap_resource() to a single
-call to devm_platform_get_and_ioremap_resource(), as this is exactly
-what this function does.
-
-Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
-Link: https://lore.kernel.org/r/202301181637472073620@zte.com.cn
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mtk_thermal.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -990,7 +990,6 @@ static int mtk_thermal_probe(struct plat
- int ret, i, ctrl_id;
- struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
- struct mtk_thermal *mt;
-- struct resource *res;
- u64 auxadc_phys_base, apmixed_phys_base;
- struct thermal_zone_device *tzdev;
- void __iomem *apmixed_base, *auxadc_base;
-@@ -1009,8 +1008,7 @@ static int mtk_thermal_probe(struct plat
- if (IS_ERR(mt->clk_auxadc))
- return PTR_ERR(mt->clk_auxadc);
-
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
-+ mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
- if (IS_ERR(mt->thermal_base))
- return PTR_ERR(mt->thermal_base);
-
+++ /dev/null
-From ca86dbd309ba03bef38ae91f037e2030bb671ab7 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 18 Jan 2023 15:40:39 +0000
-Subject: [PATCH 03/42] thermal/drivers/mtk: Use function pointer for
- raw_to_mcelsius
-
-Instead of having if-else logic selecting either raw_to_mcelsius_v1 or
-raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function
-pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the
-probe function.
-
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Link: https://lore.kernel.org/r/69c17529e8418da3eec703dde31e1b01e5b0f7e8.1674055882.git.daniel@makrotopia.org
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mtk_thermal.c | 17 ++++++++++-------
- 1 file changed, 10 insertions(+), 7 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -292,6 +292,8 @@ struct mtk_thermal {
-
- const struct mtk_thermal_data *conf;
- struct mtk_thermal_bank banks[MAX_NUM_ZONES];
-+
-+ int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
- };
-
- /* MT8183 thermal sensor data */
-@@ -656,13 +658,9 @@ static int mtk_thermal_bank_temperature(
- for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
- raw = readl(mt->thermal_base + conf->msr[i]);
-
-- if (mt->conf->version == MTK_THERMAL_V1) {
-- temp = raw_to_mcelsius_v1(
-- mt, conf->bank_data[bank->id].sensors[i], raw);
-- } else {
-- temp = raw_to_mcelsius_v2(
-- mt, conf->bank_data[bank->id].sensors[i], raw);
-- }
-+ temp = mt->raw_to_mcelsius(
-+ mt, conf->bank_data[bank->id].sensors[i], raw);
-+
-
- /*
- * The first read of a sensor often contains very high bogus
-@@ -1073,6 +1071,11 @@ static int mtk_thermal_probe(struct plat
- mtk_thermal_release_periodic_ts(mt, auxadc_base);
- }
-
-+ if (mt->conf->version == MTK_THERMAL_V1)
-+ mt->raw_to_mcelsius = raw_to_mcelsius_v1;
-+ else
-+ mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+
- for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
- for (i = 0; i < mt->conf->num_banks; i++)
- mtk_thermal_init_bank(mt, i, apmixed_phys_base,
+++ /dev/null
-From aec1d89dccc7cba04fdb3e52dfda328f3302ba17 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 18 Jan 2023 15:40:58 +0000
-Subject: [PATCH 04/42] thermal/drivers/mtk: Add support for MT7986 and MT7981
-
-Add support for V3 generation thermal found in MT7986 and MT7981 SoCs.
-Brings code to assign values from efuse as well as new function to
-convert raw temperature to millidegree celsius, as found in MediaTek's
-SDK sources (but cleaned up and de-duplicated)
-
-[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/2d341fc45266217249586eb4bd3be3ac4ca83a12.1674055882.git.daniel@makrotopia.org
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mtk_thermal.c | 128 ++++++++++++++++++++++++++++++++--
- 1 file changed, 124 insertions(+), 4 deletions(-)
-
---- a/drivers/thermal/mtk_thermal.c
-+++ b/drivers/thermal/mtk_thermal.c
-@@ -150,6 +150,20 @@
- #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
- #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
-
-+/*
-+ * Layout of the fuses providing the calibration data
-+ * These macros can be used for MT7981 and MT7986.
-+ */
-+#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff)
-+#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f)
-+#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff)
-+#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff)
-+#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff)
-+#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1)
-+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1)
-+#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1)
-+
- enum {
- VTS1,
- VTS2,
-@@ -163,6 +177,7 @@ enum {
- enum mtk_thermal_version {
- MTK_THERMAL_V1 = 1,
- MTK_THERMAL_V2,
-+ MTK_THERMAL_V3,
- };
-
- /* MT2701 thermal sensors */
-@@ -245,6 +260,27 @@ enum mtk_thermal_version {
- /* The calibration coefficient of sensor */
- #define MT8183_CALIBRATION 153
-
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT7986_TEMP_AUXADC_CHANNEL 11
-+
-+/* The total number of temperature sensors in the MT7986 */
-+#define MT7986_NUM_SENSORS 1
-+
-+/* The number of banks in the MT7986 */
-+#define MT7986_NUM_ZONES 1
-+
-+/* The number of sensing points per bank */
-+#define MT7986_NUM_SENSORS_PER_ZONE 1
-+
-+/* MT7986 thermal sensors */
-+#define MT7986_TS1 0
-+
-+/* The number of controller in the MT7986 */
-+#define MT7986_NUM_CONTROLLER 1
-+
-+/* The calibration coefficient of sensor */
-+#define MT7986_CALIBRATION 165
-+
- struct mtk_thermal;
-
- struct thermal_bank_cfg {
-@@ -388,6 +424,14 @@ static const int mt7622_mux_values[MT762
- static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
- static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
-
-+/* MT7986 thermal sensor data */
-+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
-+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
-+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
-+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
-+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
-+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
-+
- /*
- * The MT8173 thermal controller has four banks. Each bank can read up to
- * four temperature sensors simultaneously. The MT8173 has a total of 5
-@@ -551,6 +595,30 @@ static const struct mtk_thermal_data mt8
- .version = MTK_THERMAL_V1,
- };
-
-+/*
-+ * MT7986 uses AUXADC Channel 11 for raw data access.
-+ */
-+static const struct mtk_thermal_data mt7986_thermal_data = {
-+ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
-+ .num_banks = MT7986_NUM_ZONES,
-+ .num_sensors = MT7986_NUM_SENSORS,
-+ .vts_index = mt7986_vts_index,
-+ .cali_val = MT7986_CALIBRATION,
-+ .num_controller = MT7986_NUM_CONTROLLER,
-+ .controller_offset = mt7986_tc_offset,
-+ .need_switch_bank = true,
-+ .bank_data = {
-+ {
-+ .num_sensors = 1,
-+ .sensors = mt7986_bank_data,
-+ },
-+ },
-+ .msr = mt7986_msr,
-+ .adcpnp = mt7986_adcpnp,
-+ .sensor_mux_values = mt7986_mux_values,
-+ .version = MTK_THERMAL_V3,
-+};
-+
- /**
- * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
- * @mt: The thermal controller
-@@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk
- return (format_2 - tmp) * 100;
- }
-
-+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
-+{
-+ s32 tmp;
-+
-+ if (raw == 0)
-+ return 0;
-+
-+ raw &= 0xfff;
-+ tmp = 100000 * 15 / 16 * 10000;
-+ tmp /= 4096 - 512 + mt->adc_ge;
-+ tmp /= 1490;
-+ tmp *= raw - mt->vts[sensno] - 2900;
-+
-+ return mt->degc_cali * 500 - tmp;
-+}
-+
- /**
- * mtk_thermal_get_bank - get bank
- * @bank: The bank
-@@ -885,6 +969,25 @@ static int mtk_thermal_extract_efuse_v2(
- return 0;
- }
-
-+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
-+{
-+ if (!CALIB_BUF1_VALID_V3(buf[1]))
-+ return -EINVAL;
-+
-+ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
-+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
-+ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
-+ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
-+ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
-+ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
-+ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
-+
-+ if (CALIB_BUF1_ID_V3(buf[1]) == 0)
-+ mt->o_slope = 0;
-+
-+ return 0;
-+}
-+
- static int mtk_thermal_get_calibration_data(struct device *dev,
- struct mtk_thermal *mt)
- {
-@@ -895,6 +998,7 @@ static int mtk_thermal_get_calibration_d
-
- /* Start with default values */
- mt->adc_ge = 512;
-+ mt->adc_oe = 512;
- for (i = 0; i < mt->conf->num_sensors; i++)
- mt->vts[i] = 260;
- mt->degc_cali = 40;
-@@ -920,10 +1024,20 @@ static int mtk_thermal_get_calibration_d
- goto out;
- }
-
-- if (mt->conf->version == MTK_THERMAL_V1)
-+ switch (mt->conf->version) {
-+ case MTK_THERMAL_V1:
- ret = mtk_thermal_extract_efuse_v1(mt, buf);
-- else
-+ break;
-+ case MTK_THERMAL_V2:
- ret = mtk_thermal_extract_efuse_v2(mt, buf);
-+ break;
-+ case MTK_THERMAL_V3:
-+ ret = mtk_thermal_extract_efuse_v3(mt, buf);
-+ break;
-+ default:
-+ ret = -EINVAL;
-+ break;
-+ }
-
- if (ret) {
- dev_info(dev, "Device not calibrated, using default calibration values\n");
-@@ -954,6 +1068,10 @@ static const struct of_device_id mtk_the
- .data = (void *)&mt7622_thermal_data,
- },
- {
-+ .compatible = "mediatek,mt7986-thermal",
-+ .data = (void *)&mt7986_thermal_data,
-+ },
-+ {
- .compatible = "mediatek,mt8183-thermal",
- .data = (void *)&mt8183_thermal_data,
- }, {
-@@ -1066,15 +1184,17 @@ static int mtk_thermal_probe(struct plat
- goto err_disable_clk_auxadc;
- }
-
-- if (mt->conf->version == MTK_THERMAL_V2) {
-+ if (mt->conf->version != MTK_THERMAL_V1) {
- mtk_thermal_turn_on_buffer(apmixed_base);
- mtk_thermal_release_periodic_ts(mt, auxadc_base);
- }
-
- if (mt->conf->version == MTK_THERMAL_V1)
- mt->raw_to_mcelsius = raw_to_mcelsius_v1;
-- else
-+ else if (mt->conf->version == MTK_THERMAL_V2)
- mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+ else
-+ mt->raw_to_mcelsius = raw_to_mcelsius_v3;
-
- for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
- for (i = 0; i < mt->conf->num_banks; i++)
+++ /dev/null
-From 5e3aac197a74914ccec2732a89c29d960730d28f Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Thu, 9 Feb 2023 11:56:23 +0100
-Subject: [PATCH 05/42] thermal/drivers/mediatek: Relocate driver to mediatek
- folder
-
-Add MediaTek proprietary folder to upstream more thermal zone and cooler
-drivers, relocate the original thermal controller driver to it, and rename it
-as "auxadc_thermal.c" to show its purpose more clearly.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230209105628.50294-2-bchihi@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/Kconfig | 14 ++++---------
- drivers/thermal/Makefile | 2 +-
- drivers/thermal/mediatek/Kconfig | 21 +++++++++++++++++++
- drivers/thermal/mediatek/Makefile | 1 +
- .../auxadc_thermal.c} | 2 +-
- 5 files changed, 28 insertions(+), 12 deletions(-)
- create mode 100644 drivers/thermal/mediatek/Kconfig
- create mode 100644 drivers/thermal/mediatek/Makefile
- rename drivers/thermal/{mtk_thermal.c => mediatek/auxadc_thermal.c} (99%)
-
---- a/drivers/thermal/Kconfig
-+++ b/drivers/thermal/Kconfig
-@@ -412,16 +412,10 @@ config DA9062_THERMAL
- zone.
- Compatible with the DA9062 and DA9061 PMICs.
-
--config MTK_THERMAL
-- tristate "Temperature sensor driver for mediatek SoCs"
-- depends on ARCH_MEDIATEK || COMPILE_TEST
-- depends on HAS_IOMEM
-- depends on NVMEM || NVMEM=n
-- depends on RESET_CONTROLLER
-- default y
-- help
-- Enable this option if you want to have support for thermal management
-- controller present in Mediatek SoCs
-+menu "Mediatek thermal drivers"
-+depends on ARCH_MEDIATEK || COMPILE_TEST
-+source "drivers/thermal/mediatek/Kconfig"
-+endmenu
-
- config AMLOGIC_THERMAL
- tristate "Amlogic Thermal Support"
---- a/drivers/thermal/Makefile
-+++ b/drivers/thermal/Makefile
-@@ -55,7 +55,7 @@ obj-y += st/
- obj-y += qcom/
- obj-y += tegra/
- obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
--obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
-+obj-y += mediatek/
- obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o
- obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o
- obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o
---- /dev/null
-+++ b/drivers/thermal/mediatek/Kconfig
-@@ -0,0 +1,21 @@
-+config MTK_THERMAL
-+ tristate "MediaTek thermal drivers"
-+ depends on THERMAL_OF
-+ help
-+ This is the option for MediaTek thermal software solutions.
-+ Please enable corresponding options to get temperature
-+ information from thermal sensors or turn on throttle
-+ mechaisms for thermal mitigation.
-+
-+if MTK_THERMAL
-+
-+config MTK_SOC_THERMAL
-+ tristate "AUXADC temperature sensor driver for MediaTek SoCs"
-+ depends on HAS_IOMEM
-+ help
-+ Enable this option if you want to get SoC temperature
-+ information for MediaTek platforms.
-+ This driver configures thermal controllers to collect
-+ temperature via AUXADC interface.
-+
-+endif
---- /dev/null
-+++ b/drivers/thermal/mediatek/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o
---- a/drivers/thermal/mtk_thermal.c
-+++ /dev/null
-@@ -1,1254 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0-only
--/*
-- * Copyright (c) 2015 MediaTek Inc.
-- * Author: Hanyi Wu <hanyi.wu@mediatek.com>
-- * Sascha Hauer <s.hauer@pengutronix.de>
-- * Dawei Chien <dawei.chien@mediatek.com>
-- * Louis Yu <louis.yu@mediatek.com>
-- */
--
--#include <linux/clk.h>
--#include <linux/delay.h>
--#include <linux/interrupt.h>
--#include <linux/kernel.h>
--#include <linux/module.h>
--#include <linux/nvmem-consumer.h>
--#include <linux/of.h>
--#include <linux/of_address.h>
--#include <linux/of_device.h>
--#include <linux/platform_device.h>
--#include <linux/slab.h>
--#include <linux/io.h>
--#include <linux/thermal.h>
--#include <linux/reset.h>
--#include <linux/types.h>
--
--#include "thermal_hwmon.h"
--
--/* AUXADC Registers */
--#define AUXADC_CON1_SET_V 0x008
--#define AUXADC_CON1_CLR_V 0x00c
--#define AUXADC_CON2_V 0x010
--#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
--
--#define APMIXED_SYS_TS_CON1 0x604
--
--/* Thermal Controller Registers */
--#define TEMP_MONCTL0 0x000
--#define TEMP_MONCTL1 0x004
--#define TEMP_MONCTL2 0x008
--#define TEMP_MONIDET0 0x014
--#define TEMP_MONIDET1 0x018
--#define TEMP_MSRCTL0 0x038
--#define TEMP_MSRCTL1 0x03c
--#define TEMP_AHBPOLL 0x040
--#define TEMP_AHBTO 0x044
--#define TEMP_ADCPNP0 0x048
--#define TEMP_ADCPNP1 0x04c
--#define TEMP_ADCPNP2 0x050
--#define TEMP_ADCPNP3 0x0b4
--
--#define TEMP_ADCMUX 0x054
--#define TEMP_ADCEN 0x060
--#define TEMP_PNPMUXADDR 0x064
--#define TEMP_ADCMUXADDR 0x068
--#define TEMP_ADCENADDR 0x074
--#define TEMP_ADCVALIDADDR 0x078
--#define TEMP_ADCVOLTADDR 0x07c
--#define TEMP_RDCTRL 0x080
--#define TEMP_ADCVALIDMASK 0x084
--#define TEMP_ADCVOLTAGESHIFT 0x088
--#define TEMP_ADCWRITECTRL 0x08c
--#define TEMP_MSR0 0x090
--#define TEMP_MSR1 0x094
--#define TEMP_MSR2 0x098
--#define TEMP_MSR3 0x0B8
--
--#define TEMP_SPARE0 0x0f0
--
--#define TEMP_ADCPNP0_1 0x148
--#define TEMP_ADCPNP1_1 0x14c
--#define TEMP_ADCPNP2_1 0x150
--#define TEMP_MSR0_1 0x190
--#define TEMP_MSR1_1 0x194
--#define TEMP_MSR2_1 0x198
--#define TEMP_ADCPNP3_1 0x1b4
--#define TEMP_MSR3_1 0x1B8
--
--#define PTPCORESEL 0x400
--
--#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
--
--#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
--#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
--
--#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
--
--#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
--#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
--
--#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
--#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
--
--/* MT8173 thermal sensors */
--#define MT8173_TS1 0
--#define MT8173_TS2 1
--#define MT8173_TS3 2
--#define MT8173_TS4 3
--#define MT8173_TSABB 4
--
--/* AUXADC channel 11 is used for the temperature sensors */
--#define MT8173_TEMP_AUXADC_CHANNEL 11
--
--/* The total number of temperature sensors in the MT8173 */
--#define MT8173_NUM_SENSORS 5
--
--/* The number of banks in the MT8173 */
--#define MT8173_NUM_ZONES 4
--
--/* The number of sensing points per bank */
--#define MT8173_NUM_SENSORS_PER_ZONE 4
--
--/* The number of controller in the MT8173 */
--#define MT8173_NUM_CONTROLLER 1
--
--/* The calibration coefficient of sensor */
--#define MT8173_CALIBRATION 165
--
--/*
-- * Layout of the fuses providing the calibration data
-- * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
-- * MT8183 has 6 sensors and needs 6 VTS calibration data.
-- * MT8173 has 5 sensors and needs 5 VTS calibration data.
-- * MT2701 has 3 sensors and needs 3 VTS calibration data.
-- * MT2712 has 4 sensors and needs 4 VTS calibration data.
-- */
--#define CALIB_BUF0_VALID_V1 BIT(0)
--#define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff)
--#define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff)
--#define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff)
--#define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff)
--#define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff)
--#define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff)
--#define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff)
--#define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f)
--#define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f)
--#define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1)
--#define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1)
--
--/*
-- * Layout of the fuses providing the calibration data
-- * These macros could be used for MT7622.
-- */
--#define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff)
--#define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff)
--#define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f)
--#define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f)
--#define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff)
--#define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff)
--#define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff)
--#define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
--#define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
--
--/*
-- * Layout of the fuses providing the calibration data
-- * These macros can be used for MT7981 and MT7986.
-- */
--#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff)
--#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f)
--#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f)
--#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff)
--#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff)
--#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff)
--#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1)
--#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1)
--#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1)
--
--enum {
-- VTS1,
-- VTS2,
-- VTS3,
-- VTS4,
-- VTS5,
-- VTSABB,
-- MAX_NUM_VTS,
--};
--
--enum mtk_thermal_version {
-- MTK_THERMAL_V1 = 1,
-- MTK_THERMAL_V2,
-- MTK_THERMAL_V3,
--};
--
--/* MT2701 thermal sensors */
--#define MT2701_TS1 0
--#define MT2701_TS2 1
--#define MT2701_TSABB 2
--
--/* AUXADC channel 11 is used for the temperature sensors */
--#define MT2701_TEMP_AUXADC_CHANNEL 11
--
--/* The total number of temperature sensors in the MT2701 */
--#define MT2701_NUM_SENSORS 3
--
--/* The number of sensing points per bank */
--#define MT2701_NUM_SENSORS_PER_ZONE 3
--
--/* The number of controller in the MT2701 */
--#define MT2701_NUM_CONTROLLER 1
--
--/* The calibration coefficient of sensor */
--#define MT2701_CALIBRATION 165
--
--/* MT2712 thermal sensors */
--#define MT2712_TS1 0
--#define MT2712_TS2 1
--#define MT2712_TS3 2
--#define MT2712_TS4 3
--
--/* AUXADC channel 11 is used for the temperature sensors */
--#define MT2712_TEMP_AUXADC_CHANNEL 11
--
--/* The total number of temperature sensors in the MT2712 */
--#define MT2712_NUM_SENSORS 4
--
--/* The number of sensing points per bank */
--#define MT2712_NUM_SENSORS_PER_ZONE 4
--
--/* The number of controller in the MT2712 */
--#define MT2712_NUM_CONTROLLER 1
--
--/* The calibration coefficient of sensor */
--#define MT2712_CALIBRATION 165
--
--#define MT7622_TEMP_AUXADC_CHANNEL 11
--#define MT7622_NUM_SENSORS 1
--#define MT7622_NUM_ZONES 1
--#define MT7622_NUM_SENSORS_PER_ZONE 1
--#define MT7622_TS1 0
--#define MT7622_NUM_CONTROLLER 1
--
--/* The maximum number of banks */
--#define MAX_NUM_ZONES 8
--
--/* The calibration coefficient of sensor */
--#define MT7622_CALIBRATION 165
--
--/* MT8183 thermal sensors */
--#define MT8183_TS1 0
--#define MT8183_TS2 1
--#define MT8183_TS3 2
--#define MT8183_TS4 3
--#define MT8183_TS5 4
--#define MT8183_TSABB 5
--
--/* AUXADC channel is used for the temperature sensors */
--#define MT8183_TEMP_AUXADC_CHANNEL 11
--
--/* The total number of temperature sensors in the MT8183 */
--#define MT8183_NUM_SENSORS 6
--
--/* The number of banks in the MT8183 */
--#define MT8183_NUM_ZONES 1
--
--/* The number of sensing points per bank */
--#define MT8183_NUM_SENSORS_PER_ZONE 6
--
--/* The number of controller in the MT8183 */
--#define MT8183_NUM_CONTROLLER 2
--
--/* The calibration coefficient of sensor */
--#define MT8183_CALIBRATION 153
--
--/* AUXADC channel 11 is used for the temperature sensors */
--#define MT7986_TEMP_AUXADC_CHANNEL 11
--
--/* The total number of temperature sensors in the MT7986 */
--#define MT7986_NUM_SENSORS 1
--
--/* The number of banks in the MT7986 */
--#define MT7986_NUM_ZONES 1
--
--/* The number of sensing points per bank */
--#define MT7986_NUM_SENSORS_PER_ZONE 1
--
--/* MT7986 thermal sensors */
--#define MT7986_TS1 0
--
--/* The number of controller in the MT7986 */
--#define MT7986_NUM_CONTROLLER 1
--
--/* The calibration coefficient of sensor */
--#define MT7986_CALIBRATION 165
--
--struct mtk_thermal;
--
--struct thermal_bank_cfg {
-- unsigned int num_sensors;
-- const int *sensors;
--};
--
--struct mtk_thermal_bank {
-- struct mtk_thermal *mt;
-- int id;
--};
--
--struct mtk_thermal_data {
-- s32 num_banks;
-- s32 num_sensors;
-- s32 auxadc_channel;
-- const int *vts_index;
-- const int *sensor_mux_values;
-- const int *msr;
-- const int *adcpnp;
-- const int cali_val;
-- const int num_controller;
-- const int *controller_offset;
-- bool need_switch_bank;
-- struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
-- enum mtk_thermal_version version;
--};
--
--struct mtk_thermal {
-- struct device *dev;
-- void __iomem *thermal_base;
--
-- struct clk *clk_peri_therm;
-- struct clk *clk_auxadc;
-- /* lock: for getting and putting banks */
-- struct mutex lock;
--
-- /* Calibration values */
-- s32 adc_ge;
-- s32 adc_oe;
-- s32 degc_cali;
-- s32 o_slope;
-- s32 o_slope_sign;
-- s32 vts[MAX_NUM_VTS];
--
-- const struct mtk_thermal_data *conf;
-- struct mtk_thermal_bank banks[MAX_NUM_ZONES];
--
-- int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
--};
--
--/* MT8183 thermal sensor data */
--static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
-- MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
--};
--
--static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
-- TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
--};
--
--static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
-- TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
-- TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
--};
--
--static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
--static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
--
--static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
-- VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
--};
--
--/* MT8173 thermal sensor data */
--static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
-- { MT8173_TS2, MT8173_TS3 },
-- { MT8173_TS2, MT8173_TS4 },
-- { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
-- { MT8173_TS2 },
--};
--
--static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
-- TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
--};
--
--static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
-- TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
--};
--
--static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
--static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
--
--static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
-- VTS1, VTS2, VTS3, VTS4, VTSABB
--};
--
--/* MT2701 thermal sensor data */
--static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
-- MT2701_TS1, MT2701_TS2, MT2701_TSABB
--};
--
--static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
-- TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
--};
--
--static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
-- TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
--};
--
--static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
--static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
--
--static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
-- VTS1, VTS2, VTS3
--};
--
--/* MT2712 thermal sensor data */
--static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
-- MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
--};
--
--static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
-- TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
--};
--
--static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
-- TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
--};
--
--static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
--static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
--
--static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
-- VTS1, VTS2, VTS3, VTS4
--};
--
--/* MT7622 thermal sensor data */
--static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
--static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
--static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
--static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
--static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
--static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
--
--/* MT7986 thermal sensor data */
--static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
--static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
--static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
--static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
--static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
--static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
--
--/*
-- * The MT8173 thermal controller has four banks. Each bank can read up to
-- * four temperature sensors simultaneously. The MT8173 has a total of 5
-- * temperature sensors. We use each bank to measure a certain area of the
-- * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
-- * areas, hence is used in different banks.
-- *
-- * The thermal core only gets the maximum temperature of all banks, so
-- * the bank concept wouldn't be necessary here. However, the SVS (Smart
-- * Voltage Scaling) unit makes its decisions based on the same bank
-- * data, and this indeed needs the temperatures of the individual banks
-- * for making better decisions.
-- */
--static const struct mtk_thermal_data mt8173_thermal_data = {
-- .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
-- .num_banks = MT8173_NUM_ZONES,
-- .num_sensors = MT8173_NUM_SENSORS,
-- .vts_index = mt8173_vts_index,
-- .cali_val = MT8173_CALIBRATION,
-- .num_controller = MT8173_NUM_CONTROLLER,
-- .controller_offset = mt8173_tc_offset,
-- .need_switch_bank = true,
-- .bank_data = {
-- {
-- .num_sensors = 2,
-- .sensors = mt8173_bank_data[0],
-- }, {
-- .num_sensors = 2,
-- .sensors = mt8173_bank_data[1],
-- }, {
-- .num_sensors = 3,
-- .sensors = mt8173_bank_data[2],
-- }, {
-- .num_sensors = 1,
-- .sensors = mt8173_bank_data[3],
-- },
-- },
-- .msr = mt8173_msr,
-- .adcpnp = mt8173_adcpnp,
-- .sensor_mux_values = mt8173_mux_values,
-- .version = MTK_THERMAL_V1,
--};
--
--/*
-- * The MT2701 thermal controller has one bank, which can read up to
-- * three temperature sensors simultaneously. The MT2701 has a total of 3
-- * temperature sensors.
-- *
-- * The thermal core only gets the maximum temperature of this one bank,
-- * so the bank concept wouldn't be necessary here. However, the SVS (Smart
-- * Voltage Scaling) unit makes its decisions based on the same bank
-- * data.
-- */
--static const struct mtk_thermal_data mt2701_thermal_data = {
-- .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
-- .num_banks = 1,
-- .num_sensors = MT2701_NUM_SENSORS,
-- .vts_index = mt2701_vts_index,
-- .cali_val = MT2701_CALIBRATION,
-- .num_controller = MT2701_NUM_CONTROLLER,
-- .controller_offset = mt2701_tc_offset,
-- .need_switch_bank = true,
-- .bank_data = {
-- {
-- .num_sensors = 3,
-- .sensors = mt2701_bank_data,
-- },
-- },
-- .msr = mt2701_msr,
-- .adcpnp = mt2701_adcpnp,
-- .sensor_mux_values = mt2701_mux_values,
-- .version = MTK_THERMAL_V1,
--};
--
--/*
-- * The MT2712 thermal controller has one bank, which can read up to
-- * four temperature sensors simultaneously. The MT2712 has a total of 4
-- * temperature sensors.
-- *
-- * The thermal core only gets the maximum temperature of this one bank,
-- * so the bank concept wouldn't be necessary here. However, the SVS (Smart
-- * Voltage Scaling) unit makes its decisions based on the same bank
-- * data.
-- */
--static const struct mtk_thermal_data mt2712_thermal_data = {
-- .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
-- .num_banks = 1,
-- .num_sensors = MT2712_NUM_SENSORS,
-- .vts_index = mt2712_vts_index,
-- .cali_val = MT2712_CALIBRATION,
-- .num_controller = MT2712_NUM_CONTROLLER,
-- .controller_offset = mt2712_tc_offset,
-- .need_switch_bank = true,
-- .bank_data = {
-- {
-- .num_sensors = 4,
-- .sensors = mt2712_bank_data,
-- },
-- },
-- .msr = mt2712_msr,
-- .adcpnp = mt2712_adcpnp,
-- .sensor_mux_values = mt2712_mux_values,
-- .version = MTK_THERMAL_V1,
--};
--
--/*
-- * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
-- * access.
-- */
--static const struct mtk_thermal_data mt7622_thermal_data = {
-- .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
-- .num_banks = MT7622_NUM_ZONES,
-- .num_sensors = MT7622_NUM_SENSORS,
-- .vts_index = mt7622_vts_index,
-- .cali_val = MT7622_CALIBRATION,
-- .num_controller = MT7622_NUM_CONTROLLER,
-- .controller_offset = mt7622_tc_offset,
-- .need_switch_bank = true,
-- .bank_data = {
-- {
-- .num_sensors = 1,
-- .sensors = mt7622_bank_data,
-- },
-- },
-- .msr = mt7622_msr,
-- .adcpnp = mt7622_adcpnp,
-- .sensor_mux_values = mt7622_mux_values,
-- .version = MTK_THERMAL_V2,
--};
--
--/*
-- * The MT8183 thermal controller has one bank for the current SW framework.
-- * The MT8183 has a total of 6 temperature sensors.
-- * There are two thermal controller to control the six sensor.
-- * The first one bind 2 sensor, and the other bind 4 sensors.
-- * The thermal core only gets the maximum temperature of all sensor, so
-- * the bank concept wouldn't be necessary here. However, the SVS (Smart
-- * Voltage Scaling) unit makes its decisions based on the same bank
-- * data, and this indeed needs the temperatures of the individual banks
-- * for making better decisions.
-- */
--static const struct mtk_thermal_data mt8183_thermal_data = {
-- .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
-- .num_banks = MT8183_NUM_ZONES,
-- .num_sensors = MT8183_NUM_SENSORS,
-- .vts_index = mt8183_vts_index,
-- .cali_val = MT8183_CALIBRATION,
-- .num_controller = MT8183_NUM_CONTROLLER,
-- .controller_offset = mt8183_tc_offset,
-- .need_switch_bank = false,
-- .bank_data = {
-- {
-- .num_sensors = 6,
-- .sensors = mt8183_bank_data,
-- },
-- },
--
-- .msr = mt8183_msr,
-- .adcpnp = mt8183_adcpnp,
-- .sensor_mux_values = mt8183_mux_values,
-- .version = MTK_THERMAL_V1,
--};
--
--/*
-- * MT7986 uses AUXADC Channel 11 for raw data access.
-- */
--static const struct mtk_thermal_data mt7986_thermal_data = {
-- .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
-- .num_banks = MT7986_NUM_ZONES,
-- .num_sensors = MT7986_NUM_SENSORS,
-- .vts_index = mt7986_vts_index,
-- .cali_val = MT7986_CALIBRATION,
-- .num_controller = MT7986_NUM_CONTROLLER,
-- .controller_offset = mt7986_tc_offset,
-- .need_switch_bank = true,
-- .bank_data = {
-- {
-- .num_sensors = 1,
-- .sensors = mt7986_bank_data,
-- },
-- },
-- .msr = mt7986_msr,
-- .adcpnp = mt7986_adcpnp,
-- .sensor_mux_values = mt7986_mux_values,
-- .version = MTK_THERMAL_V3,
--};
--
--/**
-- * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
-- * @mt: The thermal controller
-- * @sensno: sensor number
-- * @raw: raw ADC value
-- *
-- * This converts the raw ADC value to mcelsius using the SoC specific
-- * calibration constants
-- */
--static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
--{
-- s32 tmp;
--
-- raw &= 0xfff;
--
-- tmp = 203450520 << 3;
-- tmp /= mt->conf->cali_val + mt->o_slope;
-- tmp /= 10000 + mt->adc_ge;
-- tmp *= raw - mt->vts[sensno] - 3350;
-- tmp >>= 3;
--
-- return mt->degc_cali * 500 - tmp;
--}
--
--static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
--{
-- s32 format_1;
-- s32 format_2;
-- s32 g_oe;
-- s32 g_gain;
-- s32 g_x_roomt;
-- s32 tmp;
--
-- if (raw == 0)
-- return 0;
--
-- raw &= 0xfff;
-- g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
-- g_oe = mt->adc_oe - 512;
-- format_1 = mt->vts[VTS2] + 3105 - g_oe;
-- format_2 = (mt->degc_cali * 10) >> 1;
-- g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
--
-- tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
-- tmp = tmp * 10 * 100 / 11;
--
-- if (mt->o_slope_sign == 0)
-- tmp = tmp / (165 - mt->o_slope);
-- else
-- tmp = tmp / (165 + mt->o_slope);
--
-- return (format_2 - tmp) * 100;
--}
--
--static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
--{
-- s32 tmp;
--
-- if (raw == 0)
-- return 0;
--
-- raw &= 0xfff;
-- tmp = 100000 * 15 / 16 * 10000;
-- tmp /= 4096 - 512 + mt->adc_ge;
-- tmp /= 1490;
-- tmp *= raw - mt->vts[sensno] - 2900;
--
-- return mt->degc_cali * 500 - tmp;
--}
--
--/**
-- * mtk_thermal_get_bank - get bank
-- * @bank: The bank
-- *
-- * The bank registers are banked, we have to select a bank in the
-- * PTPCORESEL register to access it.
-- */
--static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
--{
-- struct mtk_thermal *mt = bank->mt;
-- u32 val;
--
-- if (mt->conf->need_switch_bank) {
-- mutex_lock(&mt->lock);
--
-- val = readl(mt->thermal_base + PTPCORESEL);
-- val &= ~0xf;
-- val |= bank->id;
-- writel(val, mt->thermal_base + PTPCORESEL);
-- }
--}
--
--/**
-- * mtk_thermal_put_bank - release bank
-- * @bank: The bank
-- *
-- * release a bank previously taken with mtk_thermal_get_bank,
-- */
--static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
--{
-- struct mtk_thermal *mt = bank->mt;
--
-- if (mt->conf->need_switch_bank)
-- mutex_unlock(&mt->lock);
--}
--
--/**
-- * mtk_thermal_bank_temperature - get the temperature of a bank
-- * @bank: The bank
-- *
-- * The temperature of a bank is considered the maximum temperature of
-- * the sensors associated to the bank.
-- */
--static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
--{
-- struct mtk_thermal *mt = bank->mt;
-- const struct mtk_thermal_data *conf = mt->conf;
-- int i, temp = INT_MIN, max = INT_MIN;
-- u32 raw;
--
-- for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
-- raw = readl(mt->thermal_base + conf->msr[i]);
--
-- temp = mt->raw_to_mcelsius(
-- mt, conf->bank_data[bank->id].sensors[i], raw);
--
--
-- /*
-- * The first read of a sensor often contains very high bogus
-- * temperature value. Filter these out so that the system does
-- * not immediately shut down.
-- */
-- if (temp > 200000)
-- temp = 0;
--
-- if (temp > max)
-- max = temp;
-- }
--
-- return max;
--}
--
--static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
--{
-- struct mtk_thermal *mt = tz->devdata;
-- int i;
-- int tempmax = INT_MIN;
--
-- for (i = 0; i < mt->conf->num_banks; i++) {
-- struct mtk_thermal_bank *bank = &mt->banks[i];
--
-- mtk_thermal_get_bank(bank);
--
-- tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
--
-- mtk_thermal_put_bank(bank);
-- }
--
-- *temperature = tempmax;
--
-- return 0;
--}
--
--static const struct thermal_zone_device_ops mtk_thermal_ops = {
-- .get_temp = mtk_read_temp,
--};
--
--static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
-- u32 apmixed_phys_base, u32 auxadc_phys_base,
-- int ctrl_id)
--{
-- struct mtk_thermal_bank *bank = &mt->banks[num];
-- const struct mtk_thermal_data *conf = mt->conf;
-- int i;
--
-- int offset = mt->conf->controller_offset[ctrl_id];
-- void __iomem *controller_base = mt->thermal_base + offset;
--
-- bank->id = num;
-- bank->mt = mt;
--
-- mtk_thermal_get_bank(bank);
--
-- /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
-- writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
--
-- /*
-- * filt interval is 1 * 46.540us = 46.54us,
-- * sen interval is 429 * 46.540us = 19.96ms
-- */
-- writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
-- TEMP_MONCTL2_SENSOR_INTERVAL(429),
-- controller_base + TEMP_MONCTL2);
--
-- /* poll is set to 10u */
-- writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
-- controller_base + TEMP_AHBPOLL);
--
-- /* temperature sampling control, 1 sample */
-- writel(0x0, controller_base + TEMP_MSRCTL0);
--
-- /* exceed this polling time, IRQ would be inserted */
-- writel(0xffffffff, controller_base + TEMP_AHBTO);
--
-- /* number of interrupts per event, 1 is enough */
-- writel(0x0, controller_base + TEMP_MONIDET0);
-- writel(0x0, controller_base + TEMP_MONIDET1);
--
-- /*
-- * The MT8173 thermal controller does not have its own ADC. Instead it
-- * uses AHB bus accesses to control the AUXADC. To do this the thermal
-- * controller has to be programmed with the physical addresses of the
-- * AUXADC registers and with the various bit positions in the AUXADC.
-- * Also the thermal controller controls a mux in the APMIXEDSYS register
-- * space.
-- */
--
-- /*
-- * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
-- * automatically by hw
-- */
-- writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
--
-- /* AHB address for auxadc mux selection */
-- writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
-- controller_base + TEMP_ADCMUXADDR);
--
-- if (mt->conf->version == MTK_THERMAL_V1) {
-- /* AHB address for pnp sensor mux selection */
-- writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
-- controller_base + TEMP_PNPMUXADDR);
-- }
--
-- /* AHB value for auxadc enable */
-- writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
--
-- /* AHB address for auxadc enable (channel 0 immediate mode selected) */
-- writel(auxadc_phys_base + AUXADC_CON1_SET_V,
-- controller_base + TEMP_ADCENADDR);
--
-- /* AHB address for auxadc valid bit */
-- writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
-- controller_base + TEMP_ADCVALIDADDR);
--
-- /* AHB address for auxadc voltage output */
-- writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
-- controller_base + TEMP_ADCVOLTADDR);
--
-- /* read valid & voltage are at the same register */
-- writel(0x0, controller_base + TEMP_RDCTRL);
--
-- /* indicate where the valid bit is */
-- writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
-- controller_base + TEMP_ADCVALIDMASK);
--
-- /* no shift */
-- writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
--
-- /* enable auxadc mux write transaction */
-- writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
-- controller_base + TEMP_ADCWRITECTRL);
--
-- for (i = 0; i < conf->bank_data[num].num_sensors; i++)
-- writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
-- mt->thermal_base + conf->adcpnp[i]);
--
-- writel((1 << conf->bank_data[num].num_sensors) - 1,
-- controller_base + TEMP_MONCTL0);
--
-- writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
-- TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
-- controller_base + TEMP_ADCWRITECTRL);
--
-- mtk_thermal_put_bank(bank);
--}
--
--static u64 of_get_phys_base(struct device_node *np)
--{
-- u64 size64;
-- const __be32 *regaddr_p;
--
-- regaddr_p = of_get_address(np, 0, &size64, NULL);
-- if (!regaddr_p)
-- return OF_BAD_ADDR;
--
-- return of_translate_address(np, regaddr_p);
--}
--
--static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
--{
-- int i;
--
-- if (!(buf[0] & CALIB_BUF0_VALID_V1))
-- return -EINVAL;
--
-- mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
--
-- for (i = 0; i < mt->conf->num_sensors; i++) {
-- switch (mt->conf->vts_index[i]) {
-- case VTS1:
-- mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
-- break;
-- case VTS2:
-- mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
-- break;
-- case VTS3:
-- mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
-- break;
-- case VTS4:
-- mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
-- break;
-- case VTS5:
-- mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
-- break;
-- case VTSABB:
-- mt->vts[VTSABB] =
-- CALIB_BUF2_VTS_TSABB_V1(buf[2]);
-- break;
-- default:
-- break;
-- }
-- }
--
-- mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
-- if (CALIB_BUF1_ID_V1(buf[1]) &
-- CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
-- mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
-- else
-- mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
--
-- return 0;
--}
--
--static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
--{
-- if (!CALIB_BUF1_VALID_V2(buf[1]))
-- return -EINVAL;
--
-- mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
-- mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
-- mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
-- mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
-- mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
-- mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
-- mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
-- mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
--
-- return 0;
--}
--
--static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
--{
-- if (!CALIB_BUF1_VALID_V3(buf[1]))
-- return -EINVAL;
--
-- mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
-- mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
-- mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
-- mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
-- mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
-- mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
-- mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
--
-- if (CALIB_BUF1_ID_V3(buf[1]) == 0)
-- mt->o_slope = 0;
--
-- return 0;
--}
--
--static int mtk_thermal_get_calibration_data(struct device *dev,
-- struct mtk_thermal *mt)
--{
-- struct nvmem_cell *cell;
-- u32 *buf;
-- size_t len;
-- int i, ret = 0;
--
-- /* Start with default values */
-- mt->adc_ge = 512;
-- mt->adc_oe = 512;
-- for (i = 0; i < mt->conf->num_sensors; i++)
-- mt->vts[i] = 260;
-- mt->degc_cali = 40;
-- mt->o_slope = 0;
--
-- cell = nvmem_cell_get(dev, "calibration-data");
-- if (IS_ERR(cell)) {
-- if (PTR_ERR(cell) == -EPROBE_DEFER)
-- return PTR_ERR(cell);
-- return 0;
-- }
--
-- buf = (u32 *)nvmem_cell_read(cell, &len);
--
-- nvmem_cell_put(cell);
--
-- if (IS_ERR(buf))
-- return PTR_ERR(buf);
--
-- if (len < 3 * sizeof(u32)) {
-- dev_warn(dev, "invalid calibration data\n");
-- ret = -EINVAL;
-- goto out;
-- }
--
-- switch (mt->conf->version) {
-- case MTK_THERMAL_V1:
-- ret = mtk_thermal_extract_efuse_v1(mt, buf);
-- break;
-- case MTK_THERMAL_V2:
-- ret = mtk_thermal_extract_efuse_v2(mt, buf);
-- break;
-- case MTK_THERMAL_V3:
-- ret = mtk_thermal_extract_efuse_v3(mt, buf);
-- break;
-- default:
-- ret = -EINVAL;
-- break;
-- }
--
-- if (ret) {
-- dev_info(dev, "Device not calibrated, using default calibration values\n");
-- ret = 0;
-- }
--
--out:
-- kfree(buf);
--
-- return ret;
--}
--
--static const struct of_device_id mtk_thermal_of_match[] = {
-- {
-- .compatible = "mediatek,mt8173-thermal",
-- .data = (void *)&mt8173_thermal_data,
-- },
-- {
-- .compatible = "mediatek,mt2701-thermal",
-- .data = (void *)&mt2701_thermal_data,
-- },
-- {
-- .compatible = "mediatek,mt2712-thermal",
-- .data = (void *)&mt2712_thermal_data,
-- },
-- {
-- .compatible = "mediatek,mt7622-thermal",
-- .data = (void *)&mt7622_thermal_data,
-- },
-- {
-- .compatible = "mediatek,mt7986-thermal",
-- .data = (void *)&mt7986_thermal_data,
-- },
-- {
-- .compatible = "mediatek,mt8183-thermal",
-- .data = (void *)&mt8183_thermal_data,
-- }, {
-- },
--};
--MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
--
--static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
--{
-- int tmp;
--
-- tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
-- tmp &= ~(0x37);
-- tmp |= 0x1;
-- writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
-- udelay(200);
--}
--
--static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
-- void __iomem *auxadc_base)
--{
-- int tmp;
--
-- writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
-- writel(0x1, mt->thermal_base + TEMP_MONCTL0);
-- tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
-- writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
--}
--
--static int mtk_thermal_probe(struct platform_device *pdev)
--{
-- int ret, i, ctrl_id;
-- struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
-- struct mtk_thermal *mt;
-- u64 auxadc_phys_base, apmixed_phys_base;
-- struct thermal_zone_device *tzdev;
-- void __iomem *apmixed_base, *auxadc_base;
--
-- mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
-- if (!mt)
-- return -ENOMEM;
--
-- mt->conf = of_device_get_match_data(&pdev->dev);
--
-- mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
-- if (IS_ERR(mt->clk_peri_therm))
-- return PTR_ERR(mt->clk_peri_therm);
--
-- mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
-- if (IS_ERR(mt->clk_auxadc))
-- return PTR_ERR(mt->clk_auxadc);
--
-- mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
-- if (IS_ERR(mt->thermal_base))
-- return PTR_ERR(mt->thermal_base);
--
-- ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
-- if (ret)
-- return ret;
--
-- mutex_init(&mt->lock);
--
-- mt->dev = &pdev->dev;
--
-- auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
-- if (!auxadc) {
-- dev_err(&pdev->dev, "missing auxadc node\n");
-- return -ENODEV;
-- }
--
-- auxadc_base = of_iomap(auxadc, 0);
-- auxadc_phys_base = of_get_phys_base(auxadc);
--
-- of_node_put(auxadc);
--
-- if (auxadc_phys_base == OF_BAD_ADDR) {
-- dev_err(&pdev->dev, "Can't get auxadc phys address\n");
-- return -EINVAL;
-- }
--
-- apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
-- if (!apmixedsys) {
-- dev_err(&pdev->dev, "missing apmixedsys node\n");
-- return -ENODEV;
-- }
--
-- apmixed_base = of_iomap(apmixedsys, 0);
-- apmixed_phys_base = of_get_phys_base(apmixedsys);
--
-- of_node_put(apmixedsys);
--
-- if (apmixed_phys_base == OF_BAD_ADDR) {
-- dev_err(&pdev->dev, "Can't get auxadc phys address\n");
-- return -EINVAL;
-- }
--
-- ret = device_reset_optional(&pdev->dev);
-- if (ret)
-- return ret;
--
-- ret = clk_prepare_enable(mt->clk_auxadc);
-- if (ret) {
-- dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
-- return ret;
-- }
--
-- ret = clk_prepare_enable(mt->clk_peri_therm);
-- if (ret) {
-- dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
-- goto err_disable_clk_auxadc;
-- }
--
-- if (mt->conf->version != MTK_THERMAL_V1) {
-- mtk_thermal_turn_on_buffer(apmixed_base);
-- mtk_thermal_release_periodic_ts(mt, auxadc_base);
-- }
--
-- if (mt->conf->version == MTK_THERMAL_V1)
-- mt->raw_to_mcelsius = raw_to_mcelsius_v1;
-- else if (mt->conf->version == MTK_THERMAL_V2)
-- mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-- else
-- mt->raw_to_mcelsius = raw_to_mcelsius_v3;
--
-- for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
-- for (i = 0; i < mt->conf->num_banks; i++)
-- mtk_thermal_init_bank(mt, i, apmixed_phys_base,
-- auxadc_phys_base, ctrl_id);
--
-- platform_set_drvdata(pdev, mt);
--
-- tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
-- &mtk_thermal_ops);
-- if (IS_ERR(tzdev)) {
-- ret = PTR_ERR(tzdev);
-- goto err_disable_clk_peri_therm;
-- }
--
-- ret = devm_thermal_add_hwmon_sysfs(tzdev);
-- if (ret)
-- dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
--
-- return 0;
--
--err_disable_clk_peri_therm:
-- clk_disable_unprepare(mt->clk_peri_therm);
--err_disable_clk_auxadc:
-- clk_disable_unprepare(mt->clk_auxadc);
--
-- return ret;
--}
--
--static int mtk_thermal_remove(struct platform_device *pdev)
--{
-- struct mtk_thermal *mt = platform_get_drvdata(pdev);
--
-- clk_disable_unprepare(mt->clk_peri_therm);
-- clk_disable_unprepare(mt->clk_auxadc);
--
-- return 0;
--}
--
--static struct platform_driver mtk_thermal_driver = {
-- .probe = mtk_thermal_probe,
-- .remove = mtk_thermal_remove,
-- .driver = {
-- .name = "mtk-thermal",
-- .of_match_table = mtk_thermal_of_match,
-- },
--};
--
--module_platform_driver(mtk_thermal_driver);
--
--MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
--MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
--MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
--MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
--MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
--MODULE_DESCRIPTION("Mediatek thermal driver");
--MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -0,0 +1,1254 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (c) 2015 MediaTek Inc.
-+ * Author: Hanyi Wu <hanyi.wu@mediatek.com>
-+ * Sascha Hauer <s.hauer@pengutronix.de>
-+ * Dawei Chien <dawei.chien@mediatek.com>
-+ * Louis Yu <louis.yu@mediatek.com>
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+#include <linux/thermal.h>
-+#include <linux/reset.h>
-+#include <linux/types.h>
-+
-+#include "../thermal_hwmon.h"
-+
-+/* AUXADC Registers */
-+#define AUXADC_CON1_SET_V 0x008
-+#define AUXADC_CON1_CLR_V 0x00c
-+#define AUXADC_CON2_V 0x010
-+#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
-+
-+#define APMIXED_SYS_TS_CON1 0x604
-+
-+/* Thermal Controller Registers */
-+#define TEMP_MONCTL0 0x000
-+#define TEMP_MONCTL1 0x004
-+#define TEMP_MONCTL2 0x008
-+#define TEMP_MONIDET0 0x014
-+#define TEMP_MONIDET1 0x018
-+#define TEMP_MSRCTL0 0x038
-+#define TEMP_MSRCTL1 0x03c
-+#define TEMP_AHBPOLL 0x040
-+#define TEMP_AHBTO 0x044
-+#define TEMP_ADCPNP0 0x048
-+#define TEMP_ADCPNP1 0x04c
-+#define TEMP_ADCPNP2 0x050
-+#define TEMP_ADCPNP3 0x0b4
-+
-+#define TEMP_ADCMUX 0x054
-+#define TEMP_ADCEN 0x060
-+#define TEMP_PNPMUXADDR 0x064
-+#define TEMP_ADCMUXADDR 0x068
-+#define TEMP_ADCENADDR 0x074
-+#define TEMP_ADCVALIDADDR 0x078
-+#define TEMP_ADCVOLTADDR 0x07c
-+#define TEMP_RDCTRL 0x080
-+#define TEMP_ADCVALIDMASK 0x084
-+#define TEMP_ADCVOLTAGESHIFT 0x088
-+#define TEMP_ADCWRITECTRL 0x08c
-+#define TEMP_MSR0 0x090
-+#define TEMP_MSR1 0x094
-+#define TEMP_MSR2 0x098
-+#define TEMP_MSR3 0x0B8
-+
-+#define TEMP_SPARE0 0x0f0
-+
-+#define TEMP_ADCPNP0_1 0x148
-+#define TEMP_ADCPNP1_1 0x14c
-+#define TEMP_ADCPNP2_1 0x150
-+#define TEMP_MSR0_1 0x190
-+#define TEMP_MSR1_1 0x194
-+#define TEMP_MSR2_1 0x198
-+#define TEMP_ADCPNP3_1 0x1b4
-+#define TEMP_MSR3_1 0x1B8
-+
-+#define PTPCORESEL 0x400
-+
-+#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
-+
-+#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
-+#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
-+
-+#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
-+
-+#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
-+#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
-+
-+#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
-+#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
-+
-+/* MT8173 thermal sensors */
-+#define MT8173_TS1 0
-+#define MT8173_TS2 1
-+#define MT8173_TS3 2
-+#define MT8173_TS4 3
-+#define MT8173_TSABB 4
-+
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT8173_TEMP_AUXADC_CHANNEL 11
-+
-+/* The total number of temperature sensors in the MT8173 */
-+#define MT8173_NUM_SENSORS 5
-+
-+/* The number of banks in the MT8173 */
-+#define MT8173_NUM_ZONES 4
-+
-+/* The number of sensing points per bank */
-+#define MT8173_NUM_SENSORS_PER_ZONE 4
-+
-+/* The number of controller in the MT8173 */
-+#define MT8173_NUM_CONTROLLER 1
-+
-+/* The calibration coefficient of sensor */
-+#define MT8173_CALIBRATION 165
-+
-+/*
-+ * Layout of the fuses providing the calibration data
-+ * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
-+ * MT8183 has 6 sensors and needs 6 VTS calibration data.
-+ * MT8173 has 5 sensors and needs 5 VTS calibration data.
-+ * MT2701 has 3 sensors and needs 3 VTS calibration data.
-+ * MT2712 has 4 sensors and needs 4 VTS calibration data.
-+ */
-+#define CALIB_BUF0_VALID_V1 BIT(0)
-+#define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff)
-+#define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff)
-+#define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff)
-+#define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff)
-+#define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff)
-+#define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff)
-+#define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff)
-+#define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1)
-+#define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1)
-+
-+/*
-+ * Layout of the fuses providing the calibration data
-+ * These macros could be used for MT7622.
-+ */
-+#define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff)
-+#define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff)
-+#define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f)
-+#define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff)
-+#define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff)
-+#define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff)
-+#define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
-+#define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
-+
-+/*
-+ * Layout of the fuses providing the calibration data
-+ * These macros can be used for MT7981 and MT7986.
-+ */
-+#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff)
-+#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f)
-+#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f)
-+#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff)
-+#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff)
-+#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff)
-+#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1)
-+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1)
-+#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1)
-+
-+enum {
-+ VTS1,
-+ VTS2,
-+ VTS3,
-+ VTS4,
-+ VTS5,
-+ VTSABB,
-+ MAX_NUM_VTS,
-+};
-+
-+enum mtk_thermal_version {
-+ MTK_THERMAL_V1 = 1,
-+ MTK_THERMAL_V2,
-+ MTK_THERMAL_V3,
-+};
-+
-+/* MT2701 thermal sensors */
-+#define MT2701_TS1 0
-+#define MT2701_TS2 1
-+#define MT2701_TSABB 2
-+
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT2701_TEMP_AUXADC_CHANNEL 11
-+
-+/* The total number of temperature sensors in the MT2701 */
-+#define MT2701_NUM_SENSORS 3
-+
-+/* The number of sensing points per bank */
-+#define MT2701_NUM_SENSORS_PER_ZONE 3
-+
-+/* The number of controller in the MT2701 */
-+#define MT2701_NUM_CONTROLLER 1
-+
-+/* The calibration coefficient of sensor */
-+#define MT2701_CALIBRATION 165
-+
-+/* MT2712 thermal sensors */
-+#define MT2712_TS1 0
-+#define MT2712_TS2 1
-+#define MT2712_TS3 2
-+#define MT2712_TS4 3
-+
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT2712_TEMP_AUXADC_CHANNEL 11
-+
-+/* The total number of temperature sensors in the MT2712 */
-+#define MT2712_NUM_SENSORS 4
-+
-+/* The number of sensing points per bank */
-+#define MT2712_NUM_SENSORS_PER_ZONE 4
-+
-+/* The number of controller in the MT2712 */
-+#define MT2712_NUM_CONTROLLER 1
-+
-+/* The calibration coefficient of sensor */
-+#define MT2712_CALIBRATION 165
-+
-+#define MT7622_TEMP_AUXADC_CHANNEL 11
-+#define MT7622_NUM_SENSORS 1
-+#define MT7622_NUM_ZONES 1
-+#define MT7622_NUM_SENSORS_PER_ZONE 1
-+#define MT7622_TS1 0
-+#define MT7622_NUM_CONTROLLER 1
-+
-+/* The maximum number of banks */
-+#define MAX_NUM_ZONES 8
-+
-+/* The calibration coefficient of sensor */
-+#define MT7622_CALIBRATION 165
-+
-+/* MT8183 thermal sensors */
-+#define MT8183_TS1 0
-+#define MT8183_TS2 1
-+#define MT8183_TS3 2
-+#define MT8183_TS4 3
-+#define MT8183_TS5 4
-+#define MT8183_TSABB 5
-+
-+/* AUXADC channel is used for the temperature sensors */
-+#define MT8183_TEMP_AUXADC_CHANNEL 11
-+
-+/* The total number of temperature sensors in the MT8183 */
-+#define MT8183_NUM_SENSORS 6
-+
-+/* The number of banks in the MT8183 */
-+#define MT8183_NUM_ZONES 1
-+
-+/* The number of sensing points per bank */
-+#define MT8183_NUM_SENSORS_PER_ZONE 6
-+
-+/* The number of controller in the MT8183 */
-+#define MT8183_NUM_CONTROLLER 2
-+
-+/* The calibration coefficient of sensor */
-+#define MT8183_CALIBRATION 153
-+
-+/* AUXADC channel 11 is used for the temperature sensors */
-+#define MT7986_TEMP_AUXADC_CHANNEL 11
-+
-+/* The total number of temperature sensors in the MT7986 */
-+#define MT7986_NUM_SENSORS 1
-+
-+/* The number of banks in the MT7986 */
-+#define MT7986_NUM_ZONES 1
-+
-+/* The number of sensing points per bank */
-+#define MT7986_NUM_SENSORS_PER_ZONE 1
-+
-+/* MT7986 thermal sensors */
-+#define MT7986_TS1 0
-+
-+/* The number of controller in the MT7986 */
-+#define MT7986_NUM_CONTROLLER 1
-+
-+/* The calibration coefficient of sensor */
-+#define MT7986_CALIBRATION 165
-+
-+struct mtk_thermal;
-+
-+struct thermal_bank_cfg {
-+ unsigned int num_sensors;
-+ const int *sensors;
-+};
-+
-+struct mtk_thermal_bank {
-+ struct mtk_thermal *mt;
-+ int id;
-+};
-+
-+struct mtk_thermal_data {
-+ s32 num_banks;
-+ s32 num_sensors;
-+ s32 auxadc_channel;
-+ const int *vts_index;
-+ const int *sensor_mux_values;
-+ const int *msr;
-+ const int *adcpnp;
-+ const int cali_val;
-+ const int num_controller;
-+ const int *controller_offset;
-+ bool need_switch_bank;
-+ struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
-+ enum mtk_thermal_version version;
-+};
-+
-+struct mtk_thermal {
-+ struct device *dev;
-+ void __iomem *thermal_base;
-+
-+ struct clk *clk_peri_therm;
-+ struct clk *clk_auxadc;
-+ /* lock: for getting and putting banks */
-+ struct mutex lock;
-+
-+ /* Calibration values */
-+ s32 adc_ge;
-+ s32 adc_oe;
-+ s32 degc_cali;
-+ s32 o_slope;
-+ s32 o_slope_sign;
-+ s32 vts[MAX_NUM_VTS];
-+
-+ const struct mtk_thermal_data *conf;
-+ struct mtk_thermal_bank banks[MAX_NUM_ZONES];
-+
-+ int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
-+};
-+
-+/* MT8183 thermal sensor data */
-+static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
-+ MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
-+};
-+
-+static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
-+ TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
-+};
-+
-+static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
-+ TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
-+ TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
-+};
-+
-+static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
-+static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
-+
-+static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
-+ VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
-+};
-+
-+/* MT8173 thermal sensor data */
-+static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
-+ { MT8173_TS2, MT8173_TS3 },
-+ { MT8173_TS2, MT8173_TS4 },
-+ { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
-+ { MT8173_TS2 },
-+};
-+
-+static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
-+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
-+};
-+
-+static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
-+ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
-+};
-+
-+static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
-+static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
-+
-+static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
-+ VTS1, VTS2, VTS3, VTS4, VTSABB
-+};
-+
-+/* MT2701 thermal sensor data */
-+static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
-+ MT2701_TS1, MT2701_TS2, MT2701_TSABB
-+};
-+
-+static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
-+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
-+};
-+
-+static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
-+ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
-+};
-+
-+static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
-+static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
-+
-+static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
-+ VTS1, VTS2, VTS3
-+};
-+
-+/* MT2712 thermal sensor data */
-+static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
-+ MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
-+};
-+
-+static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
-+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
-+};
-+
-+static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
-+ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
-+};
-+
-+static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
-+static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
-+
-+static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
-+ VTS1, VTS2, VTS3, VTS4
-+};
-+
-+/* MT7622 thermal sensor data */
-+static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
-+static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
-+static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
-+static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
-+static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
-+static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
-+
-+/* MT7986 thermal sensor data */
-+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
-+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
-+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
-+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
-+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
-+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
-+
-+/*
-+ * The MT8173 thermal controller has four banks. Each bank can read up to
-+ * four temperature sensors simultaneously. The MT8173 has a total of 5
-+ * temperature sensors. We use each bank to measure a certain area of the
-+ * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
-+ * areas, hence is used in different banks.
-+ *
-+ * The thermal core only gets the maximum temperature of all banks, so
-+ * the bank concept wouldn't be necessary here. However, the SVS (Smart
-+ * Voltage Scaling) unit makes its decisions based on the same bank
-+ * data, and this indeed needs the temperatures of the individual banks
-+ * for making better decisions.
-+ */
-+static const struct mtk_thermal_data mt8173_thermal_data = {
-+ .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
-+ .num_banks = MT8173_NUM_ZONES,
-+ .num_sensors = MT8173_NUM_SENSORS,
-+ .vts_index = mt8173_vts_index,
-+ .cali_val = MT8173_CALIBRATION,
-+ .num_controller = MT8173_NUM_CONTROLLER,
-+ .controller_offset = mt8173_tc_offset,
-+ .need_switch_bank = true,
-+ .bank_data = {
-+ {
-+ .num_sensors = 2,
-+ .sensors = mt8173_bank_data[0],
-+ }, {
-+ .num_sensors = 2,
-+ .sensors = mt8173_bank_data[1],
-+ }, {
-+ .num_sensors = 3,
-+ .sensors = mt8173_bank_data[2],
-+ }, {
-+ .num_sensors = 1,
-+ .sensors = mt8173_bank_data[3],
-+ },
-+ },
-+ .msr = mt8173_msr,
-+ .adcpnp = mt8173_adcpnp,
-+ .sensor_mux_values = mt8173_mux_values,
-+ .version = MTK_THERMAL_V1,
-+};
-+
-+/*
-+ * The MT2701 thermal controller has one bank, which can read up to
-+ * three temperature sensors simultaneously. The MT2701 has a total of 3
-+ * temperature sensors.
-+ *
-+ * The thermal core only gets the maximum temperature of this one bank,
-+ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
-+ * Voltage Scaling) unit makes its decisions based on the same bank
-+ * data.
-+ */
-+static const struct mtk_thermal_data mt2701_thermal_data = {
-+ .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
-+ .num_banks = 1,
-+ .num_sensors = MT2701_NUM_SENSORS,
-+ .vts_index = mt2701_vts_index,
-+ .cali_val = MT2701_CALIBRATION,
-+ .num_controller = MT2701_NUM_CONTROLLER,
-+ .controller_offset = mt2701_tc_offset,
-+ .need_switch_bank = true,
-+ .bank_data = {
-+ {
-+ .num_sensors = 3,
-+ .sensors = mt2701_bank_data,
-+ },
-+ },
-+ .msr = mt2701_msr,
-+ .adcpnp = mt2701_adcpnp,
-+ .sensor_mux_values = mt2701_mux_values,
-+ .version = MTK_THERMAL_V1,
-+};
-+
-+/*
-+ * The MT2712 thermal controller has one bank, which can read up to
-+ * four temperature sensors simultaneously. The MT2712 has a total of 4
-+ * temperature sensors.
-+ *
-+ * The thermal core only gets the maximum temperature of this one bank,
-+ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
-+ * Voltage Scaling) unit makes its decisions based on the same bank
-+ * data.
-+ */
-+static const struct mtk_thermal_data mt2712_thermal_data = {
-+ .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
-+ .num_banks = 1,
-+ .num_sensors = MT2712_NUM_SENSORS,
-+ .vts_index = mt2712_vts_index,
-+ .cali_val = MT2712_CALIBRATION,
-+ .num_controller = MT2712_NUM_CONTROLLER,
-+ .controller_offset = mt2712_tc_offset,
-+ .need_switch_bank = true,
-+ .bank_data = {
-+ {
-+ .num_sensors = 4,
-+ .sensors = mt2712_bank_data,
-+ },
-+ },
-+ .msr = mt2712_msr,
-+ .adcpnp = mt2712_adcpnp,
-+ .sensor_mux_values = mt2712_mux_values,
-+ .version = MTK_THERMAL_V1,
-+};
-+
-+/*
-+ * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
-+ * access.
-+ */
-+static const struct mtk_thermal_data mt7622_thermal_data = {
-+ .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
-+ .num_banks = MT7622_NUM_ZONES,
-+ .num_sensors = MT7622_NUM_SENSORS,
-+ .vts_index = mt7622_vts_index,
-+ .cali_val = MT7622_CALIBRATION,
-+ .num_controller = MT7622_NUM_CONTROLLER,
-+ .controller_offset = mt7622_tc_offset,
-+ .need_switch_bank = true,
-+ .bank_data = {
-+ {
-+ .num_sensors = 1,
-+ .sensors = mt7622_bank_data,
-+ },
-+ },
-+ .msr = mt7622_msr,
-+ .adcpnp = mt7622_adcpnp,
-+ .sensor_mux_values = mt7622_mux_values,
-+ .version = MTK_THERMAL_V2,
-+};
-+
-+/*
-+ * The MT8183 thermal controller has one bank for the current SW framework.
-+ * The MT8183 has a total of 6 temperature sensors.
-+ * There are two thermal controller to control the six sensor.
-+ * The first one bind 2 sensor, and the other bind 4 sensors.
-+ * The thermal core only gets the maximum temperature of all sensor, so
-+ * the bank concept wouldn't be necessary here. However, the SVS (Smart
-+ * Voltage Scaling) unit makes its decisions based on the same bank
-+ * data, and this indeed needs the temperatures of the individual banks
-+ * for making better decisions.
-+ */
-+static const struct mtk_thermal_data mt8183_thermal_data = {
-+ .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
-+ .num_banks = MT8183_NUM_ZONES,
-+ .num_sensors = MT8183_NUM_SENSORS,
-+ .vts_index = mt8183_vts_index,
-+ .cali_val = MT8183_CALIBRATION,
-+ .num_controller = MT8183_NUM_CONTROLLER,
-+ .controller_offset = mt8183_tc_offset,
-+ .need_switch_bank = false,
-+ .bank_data = {
-+ {
-+ .num_sensors = 6,
-+ .sensors = mt8183_bank_data,
-+ },
-+ },
-+
-+ .msr = mt8183_msr,
-+ .adcpnp = mt8183_adcpnp,
-+ .sensor_mux_values = mt8183_mux_values,
-+ .version = MTK_THERMAL_V1,
-+};
-+
-+/*
-+ * MT7986 uses AUXADC Channel 11 for raw data access.
-+ */
-+static const struct mtk_thermal_data mt7986_thermal_data = {
-+ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
-+ .num_banks = MT7986_NUM_ZONES,
-+ .num_sensors = MT7986_NUM_SENSORS,
-+ .vts_index = mt7986_vts_index,
-+ .cali_val = MT7986_CALIBRATION,
-+ .num_controller = MT7986_NUM_CONTROLLER,
-+ .controller_offset = mt7986_tc_offset,
-+ .need_switch_bank = true,
-+ .bank_data = {
-+ {
-+ .num_sensors = 1,
-+ .sensors = mt7986_bank_data,
-+ },
-+ },
-+ .msr = mt7986_msr,
-+ .adcpnp = mt7986_adcpnp,
-+ .sensor_mux_values = mt7986_mux_values,
-+ .version = MTK_THERMAL_V3,
-+};
-+
-+/**
-+ * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
-+ * @mt: The thermal controller
-+ * @sensno: sensor number
-+ * @raw: raw ADC value
-+ *
-+ * This converts the raw ADC value to mcelsius using the SoC specific
-+ * calibration constants
-+ */
-+static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
-+{
-+ s32 tmp;
-+
-+ raw &= 0xfff;
-+
-+ tmp = 203450520 << 3;
-+ tmp /= mt->conf->cali_val + mt->o_slope;
-+ tmp /= 10000 + mt->adc_ge;
-+ tmp *= raw - mt->vts[sensno] - 3350;
-+ tmp >>= 3;
-+
-+ return mt->degc_cali * 500 - tmp;
-+}
-+
-+static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
-+{
-+ s32 format_1;
-+ s32 format_2;
-+ s32 g_oe;
-+ s32 g_gain;
-+ s32 g_x_roomt;
-+ s32 tmp;
-+
-+ if (raw == 0)
-+ return 0;
-+
-+ raw &= 0xfff;
-+ g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
-+ g_oe = mt->adc_oe - 512;
-+ format_1 = mt->vts[VTS2] + 3105 - g_oe;
-+ format_2 = (mt->degc_cali * 10) >> 1;
-+ g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
-+
-+ tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
-+ tmp = tmp * 10 * 100 / 11;
-+
-+ if (mt->o_slope_sign == 0)
-+ tmp = tmp / (165 - mt->o_slope);
-+ else
-+ tmp = tmp / (165 + mt->o_slope);
-+
-+ return (format_2 - tmp) * 100;
-+}
-+
-+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
-+{
-+ s32 tmp;
-+
-+ if (raw == 0)
-+ return 0;
-+
-+ raw &= 0xfff;
-+ tmp = 100000 * 15 / 16 * 10000;
-+ tmp /= 4096 - 512 + mt->adc_ge;
-+ tmp /= 1490;
-+ tmp *= raw - mt->vts[sensno] - 2900;
-+
-+ return mt->degc_cali * 500 - tmp;
-+}
-+
-+/**
-+ * mtk_thermal_get_bank - get bank
-+ * @bank: The bank
-+ *
-+ * The bank registers are banked, we have to select a bank in the
-+ * PTPCORESEL register to access it.
-+ */
-+static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
-+{
-+ struct mtk_thermal *mt = bank->mt;
-+ u32 val;
-+
-+ if (mt->conf->need_switch_bank) {
-+ mutex_lock(&mt->lock);
-+
-+ val = readl(mt->thermal_base + PTPCORESEL);
-+ val &= ~0xf;
-+ val |= bank->id;
-+ writel(val, mt->thermal_base + PTPCORESEL);
-+ }
-+}
-+
-+/**
-+ * mtk_thermal_put_bank - release bank
-+ * @bank: The bank
-+ *
-+ * release a bank previously taken with mtk_thermal_get_bank,
-+ */
-+static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
-+{
-+ struct mtk_thermal *mt = bank->mt;
-+
-+ if (mt->conf->need_switch_bank)
-+ mutex_unlock(&mt->lock);
-+}
-+
-+/**
-+ * mtk_thermal_bank_temperature - get the temperature of a bank
-+ * @bank: The bank
-+ *
-+ * The temperature of a bank is considered the maximum temperature of
-+ * the sensors associated to the bank.
-+ */
-+static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
-+{
-+ struct mtk_thermal *mt = bank->mt;
-+ const struct mtk_thermal_data *conf = mt->conf;
-+ int i, temp = INT_MIN, max = INT_MIN;
-+ u32 raw;
-+
-+ for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
-+ raw = readl(mt->thermal_base + conf->msr[i]);
-+
-+ temp = mt->raw_to_mcelsius(
-+ mt, conf->bank_data[bank->id].sensors[i], raw);
-+
-+
-+ /*
-+ * The first read of a sensor often contains very high bogus
-+ * temperature value. Filter these out so that the system does
-+ * not immediately shut down.
-+ */
-+ if (temp > 200000)
-+ temp = 0;
-+
-+ if (temp > max)
-+ max = temp;
-+ }
-+
-+ return max;
-+}
-+
-+static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
-+{
-+ struct mtk_thermal *mt = tz->devdata;
-+ int i;
-+ int tempmax = INT_MIN;
-+
-+ for (i = 0; i < mt->conf->num_banks; i++) {
-+ struct mtk_thermal_bank *bank = &mt->banks[i];
-+
-+ mtk_thermal_get_bank(bank);
-+
-+ tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
-+
-+ mtk_thermal_put_bank(bank);
-+ }
-+
-+ *temperature = tempmax;
-+
-+ return 0;
-+}
-+
-+static const struct thermal_zone_device_ops mtk_thermal_ops = {
-+ .get_temp = mtk_read_temp,
-+};
-+
-+static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
-+ u32 apmixed_phys_base, u32 auxadc_phys_base,
-+ int ctrl_id)
-+{
-+ struct mtk_thermal_bank *bank = &mt->banks[num];
-+ const struct mtk_thermal_data *conf = mt->conf;
-+ int i;
-+
-+ int offset = mt->conf->controller_offset[ctrl_id];
-+ void __iomem *controller_base = mt->thermal_base + offset;
-+
-+ bank->id = num;
-+ bank->mt = mt;
-+
-+ mtk_thermal_get_bank(bank);
-+
-+ /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
-+ writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
-+
-+ /*
-+ * filt interval is 1 * 46.540us = 46.54us,
-+ * sen interval is 429 * 46.540us = 19.96ms
-+ */
-+ writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
-+ TEMP_MONCTL2_SENSOR_INTERVAL(429),
-+ controller_base + TEMP_MONCTL2);
-+
-+ /* poll is set to 10u */
-+ writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
-+ controller_base + TEMP_AHBPOLL);
-+
-+ /* temperature sampling control, 1 sample */
-+ writel(0x0, controller_base + TEMP_MSRCTL0);
-+
-+ /* exceed this polling time, IRQ would be inserted */
-+ writel(0xffffffff, controller_base + TEMP_AHBTO);
-+
-+ /* number of interrupts per event, 1 is enough */
-+ writel(0x0, controller_base + TEMP_MONIDET0);
-+ writel(0x0, controller_base + TEMP_MONIDET1);
-+
-+ /*
-+ * The MT8173 thermal controller does not have its own ADC. Instead it
-+ * uses AHB bus accesses to control the AUXADC. To do this the thermal
-+ * controller has to be programmed with the physical addresses of the
-+ * AUXADC registers and with the various bit positions in the AUXADC.
-+ * Also the thermal controller controls a mux in the APMIXEDSYS register
-+ * space.
-+ */
-+
-+ /*
-+ * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
-+ * automatically by hw
-+ */
-+ writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
-+
-+ /* AHB address for auxadc mux selection */
-+ writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
-+ controller_base + TEMP_ADCMUXADDR);
-+
-+ if (mt->conf->version == MTK_THERMAL_V1) {
-+ /* AHB address for pnp sensor mux selection */
-+ writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
-+ controller_base + TEMP_PNPMUXADDR);
-+ }
-+
-+ /* AHB value for auxadc enable */
-+ writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
-+
-+ /* AHB address for auxadc enable (channel 0 immediate mode selected) */
-+ writel(auxadc_phys_base + AUXADC_CON1_SET_V,
-+ controller_base + TEMP_ADCENADDR);
-+
-+ /* AHB address for auxadc valid bit */
-+ writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
-+ controller_base + TEMP_ADCVALIDADDR);
-+
-+ /* AHB address for auxadc voltage output */
-+ writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
-+ controller_base + TEMP_ADCVOLTADDR);
-+
-+ /* read valid & voltage are at the same register */
-+ writel(0x0, controller_base + TEMP_RDCTRL);
-+
-+ /* indicate where the valid bit is */
-+ writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
-+ controller_base + TEMP_ADCVALIDMASK);
-+
-+ /* no shift */
-+ writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
-+
-+ /* enable auxadc mux write transaction */
-+ writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
-+ controller_base + TEMP_ADCWRITECTRL);
-+
-+ for (i = 0; i < conf->bank_data[num].num_sensors; i++)
-+ writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
-+ mt->thermal_base + conf->adcpnp[i]);
-+
-+ writel((1 << conf->bank_data[num].num_sensors) - 1,
-+ controller_base + TEMP_MONCTL0);
-+
-+ writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
-+ TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
-+ controller_base + TEMP_ADCWRITECTRL);
-+
-+ mtk_thermal_put_bank(bank);
-+}
-+
-+static u64 of_get_phys_base(struct device_node *np)
-+{
-+ u64 size64;
-+ const __be32 *regaddr_p;
-+
-+ regaddr_p = of_get_address(np, 0, &size64, NULL);
-+ if (!regaddr_p)
-+ return OF_BAD_ADDR;
-+
-+ return of_translate_address(np, regaddr_p);
-+}
-+
-+static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
-+{
-+ int i;
-+
-+ if (!(buf[0] & CALIB_BUF0_VALID_V1))
-+ return -EINVAL;
-+
-+ mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
-+
-+ for (i = 0; i < mt->conf->num_sensors; i++) {
-+ switch (mt->conf->vts_index[i]) {
-+ case VTS1:
-+ mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
-+ break;
-+ case VTS2:
-+ mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
-+ break;
-+ case VTS3:
-+ mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
-+ break;
-+ case VTS4:
-+ mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
-+ break;
-+ case VTS5:
-+ mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
-+ break;
-+ case VTSABB:
-+ mt->vts[VTSABB] =
-+ CALIB_BUF2_VTS_TSABB_V1(buf[2]);
-+ break;
-+ default:
-+ break;
-+ }
-+ }
-+
-+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
-+ if (CALIB_BUF1_ID_V1(buf[1]) &
-+ CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
-+ mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
-+ else
-+ mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
-+
-+ return 0;
-+}
-+
-+static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
-+{
-+ if (!CALIB_BUF1_VALID_V2(buf[1]))
-+ return -EINVAL;
-+
-+ mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
-+ mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
-+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
-+ mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
-+ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
-+ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
-+ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
-+ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
-+
-+ return 0;
-+}
-+
-+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
-+{
-+ if (!CALIB_BUF1_VALID_V3(buf[1]))
-+ return -EINVAL;
-+
-+ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
-+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
-+ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
-+ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
-+ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
-+ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
-+ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
-+
-+ if (CALIB_BUF1_ID_V3(buf[1]) == 0)
-+ mt->o_slope = 0;
-+
-+ return 0;
-+}
-+
-+static int mtk_thermal_get_calibration_data(struct device *dev,
-+ struct mtk_thermal *mt)
-+{
-+ struct nvmem_cell *cell;
-+ u32 *buf;
-+ size_t len;
-+ int i, ret = 0;
-+
-+ /* Start with default values */
-+ mt->adc_ge = 512;
-+ mt->adc_oe = 512;
-+ for (i = 0; i < mt->conf->num_sensors; i++)
-+ mt->vts[i] = 260;
-+ mt->degc_cali = 40;
-+ mt->o_slope = 0;
-+
-+ cell = nvmem_cell_get(dev, "calibration-data");
-+ if (IS_ERR(cell)) {
-+ if (PTR_ERR(cell) == -EPROBE_DEFER)
-+ return PTR_ERR(cell);
-+ return 0;
-+ }
-+
-+ buf = (u32 *)nvmem_cell_read(cell, &len);
-+
-+ nvmem_cell_put(cell);
-+
-+ if (IS_ERR(buf))
-+ return PTR_ERR(buf);
-+
-+ if (len < 3 * sizeof(u32)) {
-+ dev_warn(dev, "invalid calibration data\n");
-+ ret = -EINVAL;
-+ goto out;
-+ }
-+
-+ switch (mt->conf->version) {
-+ case MTK_THERMAL_V1:
-+ ret = mtk_thermal_extract_efuse_v1(mt, buf);
-+ break;
-+ case MTK_THERMAL_V2:
-+ ret = mtk_thermal_extract_efuse_v2(mt, buf);
-+ break;
-+ case MTK_THERMAL_V3:
-+ ret = mtk_thermal_extract_efuse_v3(mt, buf);
-+ break;
-+ default:
-+ ret = -EINVAL;
-+ break;
-+ }
-+
-+ if (ret) {
-+ dev_info(dev, "Device not calibrated, using default calibration values\n");
-+ ret = 0;
-+ }
-+
-+out:
-+ kfree(buf);
-+
-+ return ret;
-+}
-+
-+static const struct of_device_id mtk_thermal_of_match[] = {
-+ {
-+ .compatible = "mediatek,mt8173-thermal",
-+ .data = (void *)&mt8173_thermal_data,
-+ },
-+ {
-+ .compatible = "mediatek,mt2701-thermal",
-+ .data = (void *)&mt2701_thermal_data,
-+ },
-+ {
-+ .compatible = "mediatek,mt2712-thermal",
-+ .data = (void *)&mt2712_thermal_data,
-+ },
-+ {
-+ .compatible = "mediatek,mt7622-thermal",
-+ .data = (void *)&mt7622_thermal_data,
-+ },
-+ {
-+ .compatible = "mediatek,mt7986-thermal",
-+ .data = (void *)&mt7986_thermal_data,
-+ },
-+ {
-+ .compatible = "mediatek,mt8183-thermal",
-+ .data = (void *)&mt8183_thermal_data,
-+ }, {
-+ },
-+};
-+MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
-+
-+static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
-+{
-+ int tmp;
-+
-+ tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
-+ tmp &= ~(0x37);
-+ tmp |= 0x1;
-+ writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
-+ udelay(200);
-+}
-+
-+static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
-+ void __iomem *auxadc_base)
-+{
-+ int tmp;
-+
-+ writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
-+ writel(0x1, mt->thermal_base + TEMP_MONCTL0);
-+ tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
-+ writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
-+}
-+
-+static int mtk_thermal_probe(struct platform_device *pdev)
-+{
-+ int ret, i, ctrl_id;
-+ struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
-+ struct mtk_thermal *mt;
-+ u64 auxadc_phys_base, apmixed_phys_base;
-+ struct thermal_zone_device *tzdev;
-+ void __iomem *apmixed_base, *auxadc_base;
-+
-+ mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
-+ if (!mt)
-+ return -ENOMEM;
-+
-+ mt->conf = of_device_get_match_data(&pdev->dev);
-+
-+ mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
-+ if (IS_ERR(mt->clk_peri_therm))
-+ return PTR_ERR(mt->clk_peri_therm);
-+
-+ mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
-+ if (IS_ERR(mt->clk_auxadc))
-+ return PTR_ERR(mt->clk_auxadc);
-+
-+ mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
-+ if (IS_ERR(mt->thermal_base))
-+ return PTR_ERR(mt->thermal_base);
-+
-+ ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
-+ if (ret)
-+ return ret;
-+
-+ mutex_init(&mt->lock);
-+
-+ mt->dev = &pdev->dev;
-+
-+ auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
-+ if (!auxadc) {
-+ dev_err(&pdev->dev, "missing auxadc node\n");
-+ return -ENODEV;
-+ }
-+
-+ auxadc_base = of_iomap(auxadc, 0);
-+ auxadc_phys_base = of_get_phys_base(auxadc);
-+
-+ of_node_put(auxadc);
-+
-+ if (auxadc_phys_base == OF_BAD_ADDR) {
-+ dev_err(&pdev->dev, "Can't get auxadc phys address\n");
-+ return -EINVAL;
-+ }
-+
-+ apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
-+ if (!apmixedsys) {
-+ dev_err(&pdev->dev, "missing apmixedsys node\n");
-+ return -ENODEV;
-+ }
-+
-+ apmixed_base = of_iomap(apmixedsys, 0);
-+ apmixed_phys_base = of_get_phys_base(apmixedsys);
-+
-+ of_node_put(apmixedsys);
-+
-+ if (apmixed_phys_base == OF_BAD_ADDR) {
-+ dev_err(&pdev->dev, "Can't get auxadc phys address\n");
-+ return -EINVAL;
-+ }
-+
-+ ret = device_reset_optional(&pdev->dev);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(mt->clk_auxadc);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
-+ return ret;
-+ }
-+
-+ ret = clk_prepare_enable(mt->clk_peri_therm);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
-+ goto err_disable_clk_auxadc;
-+ }
-+
-+ if (mt->conf->version != MTK_THERMAL_V1) {
-+ mtk_thermal_turn_on_buffer(apmixed_base);
-+ mtk_thermal_release_periodic_ts(mt, auxadc_base);
-+ }
-+
-+ if (mt->conf->version == MTK_THERMAL_V1)
-+ mt->raw_to_mcelsius = raw_to_mcelsius_v1;
-+ else if (mt->conf->version == MTK_THERMAL_V2)
-+ mt->raw_to_mcelsius = raw_to_mcelsius_v2;
-+ else
-+ mt->raw_to_mcelsius = raw_to_mcelsius_v3;
-+
-+ for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
-+ for (i = 0; i < mt->conf->num_banks; i++)
-+ mtk_thermal_init_bank(mt, i, apmixed_phys_base,
-+ auxadc_phys_base, ctrl_id);
-+
-+ platform_set_drvdata(pdev, mt);
-+
-+ tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
-+ &mtk_thermal_ops);
-+ if (IS_ERR(tzdev)) {
-+ ret = PTR_ERR(tzdev);
-+ goto err_disable_clk_peri_therm;
-+ }
-+
-+ ret = devm_thermal_add_hwmon_sysfs(tzdev);
-+ if (ret)
-+ dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
-+
-+ return 0;
-+
-+err_disable_clk_peri_therm:
-+ clk_disable_unprepare(mt->clk_peri_therm);
-+err_disable_clk_auxadc:
-+ clk_disable_unprepare(mt->clk_auxadc);
-+
-+ return ret;
-+}
-+
-+static int mtk_thermal_remove(struct platform_device *pdev)
-+{
-+ struct mtk_thermal *mt = platform_get_drvdata(pdev);
-+
-+ clk_disable_unprepare(mt->clk_peri_therm);
-+ clk_disable_unprepare(mt->clk_auxadc);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver mtk_thermal_driver = {
-+ .probe = mtk_thermal_probe,
-+ .remove = mtk_thermal_remove,
-+ .driver = {
-+ .name = "mtk-thermal",
-+ .of_match_table = mtk_thermal_of_match,
-+ },
-+};
-+
-+module_platform_driver(mtk_thermal_driver);
-+
-+MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
-+MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
-+MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
-+MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
-+MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
-+MODULE_DESCRIPTION("Mediatek thermal driver");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From 325fadf27b21f7d79843c3cc282b7f3e6620ad3d Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Thu, 9 Feb 2023 11:56:26 +0100
-Subject: [PATCH 06/42] thermal/drivers/mediatek: Add the Low Voltage Thermal
- Sensor driver
-
-The Low Voltage Thermal Sensor (LVTS) is a multiple sensors, multi
-controllers contained in a thermal domain.
-
-A thermal domains can be the MCU or the AP.
-
-Each thermal domains contain up to seven controllers, each thermal
-controller handle up to four thermal sensors.
-
-The LVTS has two Finite State Machines (FSM), one to handle the
-functionin temperatures range like hot or cold temperature and another
-one to handle monitoring trip point. The FSM notifies via interrupts
-when a trip point is crossed.
-
-The interrupt is managed at the thermal controller level, so when an
-interrupt occurs, the driver has to find out which sensor triggered
-such an interrupt.
-
-The sampling of the thermal can be filtered or immediate. For the
-former, the LVTS measures several points and applies a low pass
-filter.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-
-On MT8195 Tomato Chromebook:
-
-Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230209105628.50294-5-bchihi@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/mediatek/Kconfig | 16 +
- drivers/thermal/mediatek/Makefile | 1 +
- drivers/thermal/mediatek/lvts_thermal.c | 1224 +++++++++++++++++++++++
- 3 files changed, 1241 insertions(+)
- create mode 100644 drivers/thermal/mediatek/lvts_thermal.c
-
---- a/drivers/thermal/mediatek/Kconfig
-+++ b/drivers/thermal/mediatek/Kconfig
-@@ -18,4 +18,20 @@ config MTK_SOC_THERMAL
- This driver configures thermal controllers to collect
- temperature via AUXADC interface.
-
-+config MTK_LVTS_THERMAL
-+ tristate "LVTS Thermal Driver for MediaTek SoCs"
-+ depends on HAS_IOMEM
-+ help
-+ Enable this option if you want to get SoC temperature
-+ information for supported MediaTek platforms.
-+ This driver configures LVTS (Low Voltage Thermal Sensor)
-+ thermal controllers to collect temperatures via ASIF
-+ (Analog Serial Interface).
-+
-+config MTK_LVTS_THERMAL_DEBUGFS
-+ bool "LVTS thermal debugfs"
-+ depends on MTK_LVTS_THERMAL && DEBUG_FS
-+ help
-+ Enable this option to debug the internals of the device driver.
-+
- endif
---- a/drivers/thermal/mediatek/Makefile
-+++ b/drivers/thermal/mediatek/Makefile
-@@ -1 +1,2 @@
- obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o
-+obj-$(CONFIG_MTK_LVTS_THERMAL) += lvts_thermal.o
---- /dev/null
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -0,0 +1,1224 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Balsam CHIHI <bchihi@baylibre.com>
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/debugfs.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset.h>
-+#include <linux/thermal.h>
-+#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
-+
-+#define LVTS_MONCTL0(__base) (__base + 0x0000)
-+#define LVTS_MONCTL1(__base) (__base + 0x0004)
-+#define LVTS_MONCTL2(__base) (__base + 0x0008)
-+#define LVTS_MONINT(__base) (__base + 0x000C)
-+#define LVTS_MONINTSTS(__base) (__base + 0x0010)
-+#define LVTS_MONIDET0(__base) (__base + 0x0014)
-+#define LVTS_MONIDET1(__base) (__base + 0x0018)
-+#define LVTS_MONIDET2(__base) (__base + 0x001C)
-+#define LVTS_MONIDET3(__base) (__base + 0x0020)
-+#define LVTS_H2NTHRE(__base) (__base + 0x0024)
-+#define LVTS_HTHRE(__base) (__base + 0x0028)
-+#define LVTS_OFFSETH(__base) (__base + 0x0030)
-+#define LVTS_OFFSETL(__base) (__base + 0x0034)
-+#define LVTS_MSRCTL0(__base) (__base + 0x0038)
-+#define LVTS_MSRCTL1(__base) (__base + 0x003C)
-+#define LVTS_TSSEL(__base) (__base + 0x0040)
-+#define LVTS_CALSCALE(__base) (__base + 0x0048)
-+#define LVTS_ID(__base) (__base + 0x004C)
-+#define LVTS_CONFIG(__base) (__base + 0x0050)
-+#define LVTS_EDATA00(__base) (__base + 0x0054)
-+#define LVTS_EDATA01(__base) (__base + 0x0058)
-+#define LVTS_EDATA02(__base) (__base + 0x005C)
-+#define LVTS_EDATA03(__base) (__base + 0x0060)
-+#define LVTS_MSR0(__base) (__base + 0x0090)
-+#define LVTS_MSR1(__base) (__base + 0x0094)
-+#define LVTS_MSR2(__base) (__base + 0x0098)
-+#define LVTS_MSR3(__base) (__base + 0x009C)
-+#define LVTS_IMMD0(__base) (__base + 0x00A0)
-+#define LVTS_IMMD1(__base) (__base + 0x00A4)
-+#define LVTS_IMMD2(__base) (__base + 0x00A8)
-+#define LVTS_IMMD3(__base) (__base + 0x00AC)
-+#define LVTS_PROTCTL(__base) (__base + 0x00C0)
-+#define LVTS_PROTTA(__base) (__base + 0x00C4)
-+#define LVTS_PROTTB(__base) (__base + 0x00C8)
-+#define LVTS_PROTTC(__base) (__base + 0x00CC)
-+#define LVTS_CLKEN(__base) (__base + 0x00E4)
-+
-+#define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38))
-+#define LVTS_GROUP_INTERVAL 1
-+#define LVTS_FILTER_INTERVAL 1
-+#define LVTS_SENSOR_INTERVAL 1
-+#define LVTS_HW_FILTER 0x2
-+#define LVTS_TSSEL_CONF 0x13121110
-+#define LVTS_CALSCALE_CONF 0x300
-+#define LVTS_MONINT_CONF 0x9FBF7BDE
-+
-+#define LVTS_INT_SENSOR0 0x0009001F
-+#define LVTS_INT_SENSOR1 0X000881F0
-+#define LVTS_INT_SENSOR2 0x00247C00
-+#define LVTS_INT_SENSOR3 0x1FC00000
-+
-+#define LVTS_SENSOR_MAX 4
-+#define LVTS_GOLDEN_TEMP_MAX 62
-+#define LVTS_GOLDEN_TEMP_DEFAULT 50
-+#define LVTS_COEFF_A -250460
-+#define LVTS_COEFF_B 250460
-+
-+#define LVTS_MSR_IMMEDIATE_MODE 0
-+#define LVTS_MSR_FILTERED_MODE 1
-+
-+#define LVTS_HW_SHUTDOWN_MT8195 105000
-+
-+static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
-+static int coeff_b = LVTS_COEFF_B;
-+
-+struct lvts_sensor_data {
-+ int dt_id;
-+};
-+
-+struct lvts_ctrl_data {
-+ struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX];
-+ int cal_offset[LVTS_SENSOR_MAX];
-+ int hw_tshut_temp;
-+ int num_lvts_sensor;
-+ int offset;
-+ int mode;
-+};
-+
-+struct lvts_data {
-+ const struct lvts_ctrl_data *lvts_ctrl;
-+ int num_lvts_ctrl;
-+};
-+
-+struct lvts_sensor {
-+ struct thermal_zone_device *tz;
-+ void __iomem *msr;
-+ void __iomem *base;
-+ int id;
-+ int dt_id;
-+};
-+
-+struct lvts_ctrl {
-+ struct lvts_sensor sensors[LVTS_SENSOR_MAX];
-+ u32 calibration[LVTS_SENSOR_MAX];
-+ u32 hw_tshut_raw_temp;
-+ int num_lvts_sensor;
-+ int mode;
-+ void __iomem *base;
-+};
-+
-+struct lvts_domain {
-+ struct lvts_ctrl *lvts_ctrl;
-+ struct reset_control *reset;
-+ struct clk *clk;
-+ int num_lvts_ctrl;
-+ void __iomem *base;
-+ size_t calib_len;
-+ u8 *calib;
-+#ifdef CONFIG_DEBUG_FS
-+ struct dentry *dom_dentry;
-+#endif
-+};
-+
-+#ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS
-+
-+#define LVTS_DEBUG_FS_REGS(__reg) \
-+{ \
-+ .name = __stringify(__reg), \
-+ .offset = __reg(0), \
-+}
-+
-+static const struct debugfs_reg32 lvts_regs[] = {
-+ LVTS_DEBUG_FS_REGS(LVTS_MONCTL0),
-+ LVTS_DEBUG_FS_REGS(LVTS_MONCTL1),
-+ LVTS_DEBUG_FS_REGS(LVTS_MONCTL2),
-+ LVTS_DEBUG_FS_REGS(LVTS_MONINT),
-+ LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS),
-+ LVTS_DEBUG_FS_REGS(LVTS_MONIDET0),
-+ LVTS_DEBUG_FS_REGS(LVTS_MONIDET1),
-+ LVTS_DEBUG_FS_REGS(LVTS_MONIDET2),
-+ LVTS_DEBUG_FS_REGS(LVTS_MONIDET3),
-+ LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE),
-+ LVTS_DEBUG_FS_REGS(LVTS_HTHRE),
-+ LVTS_DEBUG_FS_REGS(LVTS_OFFSETH),
-+ LVTS_DEBUG_FS_REGS(LVTS_OFFSETL),
-+ LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0),
-+ LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1),
-+ LVTS_DEBUG_FS_REGS(LVTS_TSSEL),
-+ LVTS_DEBUG_FS_REGS(LVTS_CALSCALE),
-+ LVTS_DEBUG_FS_REGS(LVTS_ID),
-+ LVTS_DEBUG_FS_REGS(LVTS_CONFIG),
-+ LVTS_DEBUG_FS_REGS(LVTS_EDATA00),
-+ LVTS_DEBUG_FS_REGS(LVTS_EDATA01),
-+ LVTS_DEBUG_FS_REGS(LVTS_EDATA02),
-+ LVTS_DEBUG_FS_REGS(LVTS_EDATA03),
-+ LVTS_DEBUG_FS_REGS(LVTS_MSR0),
-+ LVTS_DEBUG_FS_REGS(LVTS_MSR1),
-+ LVTS_DEBUG_FS_REGS(LVTS_MSR2),
-+ LVTS_DEBUG_FS_REGS(LVTS_MSR3),
-+ LVTS_DEBUG_FS_REGS(LVTS_IMMD0),
-+ LVTS_DEBUG_FS_REGS(LVTS_IMMD1),
-+ LVTS_DEBUG_FS_REGS(LVTS_IMMD2),
-+ LVTS_DEBUG_FS_REGS(LVTS_IMMD3),
-+ LVTS_DEBUG_FS_REGS(LVTS_PROTCTL),
-+ LVTS_DEBUG_FS_REGS(LVTS_PROTTA),
-+ LVTS_DEBUG_FS_REGS(LVTS_PROTTB),
-+ LVTS_DEBUG_FS_REGS(LVTS_PROTTC),
-+ LVTS_DEBUG_FS_REGS(LVTS_CLKEN),
-+};
-+
-+static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td)
-+{
-+ struct debugfs_regset32 *regset;
-+ struct lvts_ctrl *lvts_ctrl;
-+ struct dentry *dentry;
-+ char name[64];
-+ int i;
-+
-+ lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
-+ if (!lvts_td->dom_dentry)
-+ return 0;
-+
-+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
-+
-+ lvts_ctrl = &lvts_td->lvts_ctrl[i];
-+
-+ sprintf(name, "controller%d", i);
-+ dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
-+ if (!dentry)
-+ continue;
-+
-+ regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
-+ if (!regset)
-+ continue;
-+
-+ regset->base = lvts_ctrl->base;
-+ regset->regs = lvts_regs;
-+ regset->nregs = ARRAY_SIZE(lvts_regs);
-+
-+ debugfs_create_regset32("registers", 0400, dentry, regset);
-+ }
-+
-+ return 0;
-+}
-+
-+static void lvts_debugfs_exit(struct lvts_domain *lvts_td)
-+{
-+ debugfs_remove_recursive(lvts_td->dom_dentry);
-+}
-+
-+#else
-+
-+static inline int lvts_debugfs_init(struct device *dev,
-+ struct lvts_domain *lvts_td)
-+{
-+ return 0;
-+}
-+
-+static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
-+
-+#endif
-+
-+static int lvts_raw_to_temp(u32 raw_temp)
-+{
-+ int temperature;
-+
-+ temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
-+ temperature += coeff_b;
-+
-+ return temperature;
-+}
-+
-+static u32 lvts_temp_to_raw(int temperature)
-+{
-+ u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
-+
-+ raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
-+
-+ return raw_temp;
-+}
-+
-+static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
-+{
-+ struct lvts_sensor *lvts_sensor = tz->devdata;
-+ void __iomem *msr = lvts_sensor->msr;
-+ u32 value;
-+
-+ /*
-+ * Measurement registers:
-+ *
-+ * LVTS_MSR[0-3] / LVTS_IMMD[0-3]
-+ *
-+ * Bits:
-+ *
-+ * 32-17: Unused
-+ * 16 : Valid temperature
-+ * 15-0 : Raw temperature
-+ */
-+ value = readl(msr);
-+
-+ /*
-+ * As the thermal zone temperature will read before the
-+ * hardware sensor is fully initialized, we have to check the
-+ * validity of the temperature returned when reading the
-+ * measurement register. The thermal controller will set the
-+ * valid bit temperature only when it is totally initialized.
-+ *
-+ * Otherwise, we may end up with garbage values out of the
-+ * functionning temperature and directly jump to a system
-+ * shutdown.
-+ */
-+ if (!(value & BIT(16)))
-+ return -EAGAIN;
-+
-+ *temp = lvts_raw_to_temp(value & 0xFFFF);
-+
-+ return 0;
-+}
-+
-+static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
-+{
-+ struct lvts_sensor *lvts_sensor = tz->devdata;
-+ void __iomem *base = lvts_sensor->base;
-+ u32 raw_low = lvts_temp_to_raw(low);
-+ u32 raw_high = lvts_temp_to_raw(high);
-+
-+ /*
-+ * Hot to normal temperature threshold
-+ *
-+ * LVTS_H2NTHRE
-+ *
-+ * Bits:
-+ *
-+ * 14-0 : Raw temperature for threshold
-+ */
-+ if (low != -INT_MAX) {
-+ dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low);
-+ writel(raw_low, LVTS_H2NTHRE(base));
-+ }
-+
-+ /*
-+ * Hot temperature threshold
-+ *
-+ * LVTS_HTHRE
-+ *
-+ * Bits:
-+ *
-+ * 14-0 : Raw temperature for threshold
-+ */
-+ dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high);
-+ writel(raw_high, LVTS_HTHRE(base));
-+
-+ return 0;
-+}
-+
-+static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl)
-+{
-+ irqreturn_t iret = IRQ_NONE;
-+ u32 value;
-+ u32 masks[] = {
-+ LVTS_INT_SENSOR0,
-+ LVTS_INT_SENSOR1,
-+ LVTS_INT_SENSOR2,
-+ LVTS_INT_SENSOR3
-+ };
-+ int i;
-+
-+ /*
-+ * Interrupt monitoring status
-+ *
-+ * LVTS_MONINTST
-+ *
-+ * Bits:
-+ *
-+ * 31 : Interrupt for stage 3
-+ * 30 : Interrupt for stage 2
-+ * 29 : Interrupt for state 1
-+ * 28 : Interrupt using filter on sensor 3
-+ *
-+ * 27 : Interrupt using immediate on sensor 3
-+ * 26 : Interrupt normal to hot on sensor 3
-+ * 25 : Interrupt high offset on sensor 3
-+ * 24 : Interrupt low offset on sensor 3
-+ *
-+ * 23 : Interrupt hot threshold on sensor 3
-+ * 22 : Interrupt cold threshold on sensor 3
-+ * 21 : Interrupt using filter on sensor 2
-+ * 20 : Interrupt using filter on sensor 1
-+ *
-+ * 19 : Interrupt using filter on sensor 0
-+ * 18 : Interrupt using immediate on sensor 2
-+ * 17 : Interrupt using immediate on sensor 1
-+ * 16 : Interrupt using immediate on sensor 0
-+ *
-+ * 15 : Interrupt device access timeout interrupt
-+ * 14 : Interrupt normal to hot on sensor 2
-+ * 13 : Interrupt high offset interrupt on sensor 2
-+ * 12 : Interrupt low offset interrupt on sensor 2
-+ *
-+ * 11 : Interrupt hot threshold on sensor 2
-+ * 10 : Interrupt cold threshold on sensor 2
-+ * 9 : Interrupt normal to hot on sensor 1
-+ * 8 : Interrupt high offset interrupt on sensor 1
-+ *
-+ * 7 : Interrupt low offset interrupt on sensor 1
-+ * 6 : Interrupt hot threshold on sensor 1
-+ * 5 : Interrupt cold threshold on sensor 1
-+ * 4 : Interrupt normal to hot on sensor 0
-+ *
-+ * 3 : Interrupt high offset interrupt on sensor 0
-+ * 2 : Interrupt low offset interrupt on sensor 0
-+ * 1 : Interrupt hot threshold on sensor 0
-+ * 0 : Interrupt cold threshold on sensor 0
-+ *
-+ * We are interested in the sensor(s) responsible of the
-+ * interrupt event. We update the thermal framework with the
-+ * thermal zone associated with the sensor. The framework will
-+ * take care of the rest whatever the kind of interrupt, we
-+ * are only interested in which sensor raised the interrupt.
-+ *
-+ * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000
-+ * => 0x1FC00000
-+ * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
-+ * => 0x00247C00
-+ * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000
-+ * => 0X000881F0
-+ * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
-+ * => 0x0009001F
-+ */
-+ value = readl(LVTS_MONINTSTS(lvts_ctrl->base));
-+
-+ /*
-+ * Let's figure out which sensors raised the interrupt
-+ *
-+ * NOTE: the masks array must be ordered with the index
-+ * corresponding to the sensor id eg. index=0, mask for
-+ * sensor0.
-+ */
-+ for (i = 0; i < ARRAY_SIZE(masks); i++) {
-+
-+ if (!(value & masks[i]))
-+ continue;
-+
-+ thermal_zone_device_update(lvts_ctrl->sensors[i].tz,
-+ THERMAL_TRIP_VIOLATED);
-+ iret = IRQ_HANDLED;
-+ }
-+
-+ /*
-+ * Write back to clear the interrupt status (W1C)
-+ */
-+ writel(value, LVTS_MONINTSTS(lvts_ctrl->base));
-+
-+ return iret;
-+}
-+
-+/*
-+ * Temperature interrupt handler. Even if the driver supports more
-+ * interrupt modes, we use the interrupt when the temperature crosses
-+ * the hot threshold the way up and the way down (modulo the
-+ * hysteresis).
-+ *
-+ * Each thermal domain has a couple of interrupts, one for hardware
-+ * reset and another one for all the thermal events happening on the
-+ * different sensors.
-+ *
-+ * The interrupt is configured for thermal events when crossing the
-+ * hot temperature limit. At each interrupt, we check in every
-+ * controller if there is an interrupt pending.
-+ */
-+static irqreturn_t lvts_irq_handler(int irq, void *data)
-+{
-+ struct lvts_domain *lvts_td = data;
-+ irqreturn_t aux, iret = IRQ_NONE;
-+ int i;
-+
-+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
-+
-+ aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl);
-+ if (aux != IRQ_HANDLED)
-+ continue;
-+
-+ iret = IRQ_HANDLED;
-+ }
-+
-+ return iret;
-+}
-+
-+static struct thermal_zone_device_ops lvts_ops = {
-+ .get_temp = lvts_get_temp,
-+ .set_trips = lvts_set_trips,
-+};
-+
-+static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
-+ const struct lvts_ctrl_data *lvts_ctrl_data)
-+{
-+ struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors;
-+ void __iomem *msr_regs[] = {
-+ LVTS_MSR0(lvts_ctrl->base),
-+ LVTS_MSR1(lvts_ctrl->base),
-+ LVTS_MSR2(lvts_ctrl->base),
-+ LVTS_MSR3(lvts_ctrl->base)
-+ };
-+
-+ void __iomem *imm_regs[] = {
-+ LVTS_IMMD0(lvts_ctrl->base),
-+ LVTS_IMMD1(lvts_ctrl->base),
-+ LVTS_IMMD2(lvts_ctrl->base),
-+ LVTS_IMMD3(lvts_ctrl->base)
-+ };
-+
-+ int i;
-+
-+ for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) {
-+
-+ int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id;
-+
-+ /*
-+ * At this point, we don't know which id matches which
-+ * sensor. Let's set arbitrally the id from the index.
-+ */
-+ lvts_sensor[i].id = i;
-+
-+ /*
-+ * The thermal zone registration will set the trip
-+ * point interrupt in the thermal controller
-+ * register. But this one will be reset in the
-+ * initialization after. So we need to post pone the
-+ * thermal zone creation after the controller is
-+ * setup. For this reason, we store the device tree
-+ * node id from the data in the sensor structure
-+ */
-+ lvts_sensor[i].dt_id = dt_id;
-+
-+ /*
-+ * We assign the base address of the thermal
-+ * controller as a back pointer. So it will be
-+ * accessible from the different thermal framework ops
-+ * as we pass the lvts_sensor pointer as thermal zone
-+ * private data.
-+ */
-+ lvts_sensor[i].base = lvts_ctrl->base;
-+
-+ /*
-+ * Each sensor has its own register address to read from.
-+ */
-+ lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
-+ imm_regs[i] : msr_regs[i];
-+ };
-+
-+ lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor;
-+
-+ return 0;
-+}
-+
-+/*
-+ * The efuse blob values follows the sensor enumeration per thermal
-+ * controller. The decoding of the stream is as follow:
-+ *
-+ * <--?-> <----big0 ???---> <-sensor0-> <-0->
-+ * ------------------------------------------
-+ * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 |
-+ * ------------------------------------------
-+ *
-+ * <--sensor1--><-0-> <----big1 ???---> <-sen
-+ * ------------------------------------------
-+ * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
-+ * ------------------------------------------
-+ *
-+ * sor0-> <-0-> <-sensor1-> <-0-> ..........
-+ * ------------------------------------------
-+ * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
-+ * ------------------------------------------
-+ *
-+ * And so on ...
-+ *
-+ * The data description gives the offset of the calibration data in
-+ * this bytes stream for each sensor.
-+ *
-+ * Each thermal controller can handle up to 4 sensors max, we don't
-+ * care if there are less as the array of calibration is sized to 4
-+ * anyway. The unused sensor slot will be zeroed.
-+ */
-+static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
-+ const struct lvts_ctrl_data *lvts_ctrl_data,
-+ u8 *efuse_calibration)
-+{
-+ int i;
-+
-+ for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++)
-+ memcpy(&lvts_ctrl->calibration[i],
-+ efuse_calibration + lvts_ctrl_data->cal_offset[i], 2);
-+
-+ return 0;
-+}
-+
-+/*
-+ * The efuse bytes stream can be split into different chunk of
-+ * nvmems. This function reads and concatenate those into a single
-+ * buffer so it can be read sequentially when initializing the
-+ * calibration data.
-+ */
-+static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td,
-+ const struct lvts_data *lvts_data)
-+{
-+ struct device_node *np = dev_of_node(dev);
-+ struct nvmem_cell *cell;
-+ struct property *prop;
-+ const char *cell_name;
-+
-+ of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) {
-+ size_t len;
-+ u8 *efuse;
-+
-+ cell = of_nvmem_cell_get(np, cell_name);
-+ if (IS_ERR(cell)) {
-+ dev_err(dev, "Failed to get cell '%s'\n", cell_name);
-+ return PTR_ERR(cell);
-+ }
-+
-+ efuse = nvmem_cell_read(cell, &len);
-+
-+ nvmem_cell_put(cell);
-+
-+ if (IS_ERR(efuse)) {
-+ dev_err(dev, "Failed to read cell '%s'\n", cell_name);
-+ return PTR_ERR(efuse);
-+ }
-+
-+ lvts_td->calib = devm_krealloc(dev, lvts_td->calib,
-+ lvts_td->calib_len + len, GFP_KERNEL);
-+ if (!lvts_td->calib)
-+ return -ENOMEM;
-+
-+ memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len);
-+
-+ lvts_td->calib_len += len;
-+
-+ kfree(efuse);
-+ }
-+
-+ return 0;
-+}
-+
-+static int lvts_golden_temp_init(struct device *dev, u32 *value)
-+{
-+ u32 gt;
-+
-+ gt = (*value) >> 24;
-+
-+ if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
-+ golden_temp = gt;
-+
-+ coeff_b = golden_temp * 500 + LVTS_COEFF_B;
-+
-+ return 0;
-+}
-+
-+static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
-+ const struct lvts_data *lvts_data)
-+{
-+ size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl;
-+ struct lvts_ctrl *lvts_ctrl;
-+ int i, ret;
-+
-+ /*
-+ * Create the calibration bytes stream from efuse data
-+ */
-+ ret = lvts_calibration_read(dev, lvts_td, lvts_data);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * The golden temp information is contained in the first chunk
-+ * of efuse data.
-+ */
-+ ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
-+ if (ret)
-+ return ret;
-+
-+ lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL);
-+ if (!lvts_ctrl)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
-+
-+ lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
-+
-+ ret = lvts_sensor_init(dev, &lvts_ctrl[i],
-+ &lvts_data->lvts_ctrl[i]);
-+ if (ret)
-+ return ret;
-+
-+ ret = lvts_calibration_init(dev, &lvts_ctrl[i],
-+ &lvts_data->lvts_ctrl[i],
-+ lvts_td->calib);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * The mode the ctrl will use to read the temperature
-+ * (filtered or immediate)
-+ */
-+ lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode;
-+
-+ /*
-+ * The temperature to raw temperature must be done
-+ * after initializing the calibration.
-+ */
-+ lvts_ctrl[i].hw_tshut_raw_temp =
-+ lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
-+ }
-+
-+ /*
-+ * We no longer need the efuse bytes stream, let's free it
-+ */
-+ devm_kfree(dev, lvts_td->calib);
-+
-+ lvts_td->lvts_ctrl = lvts_ctrl;
-+ lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl;
-+
-+ return 0;
-+}
-+
-+/*
-+ * At this point the configuration register is the only place in the
-+ * driver where we write multiple values. Per hardware constraint,
-+ * each write in the configuration register must be separated by a
-+ * delay of 2 us.
-+ */
-+static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds)
-+{
-+ int i;
-+
-+ /*
-+ * Configuration register
-+ */
-+ for (i = 0; i < nr_cmds; i++) {
-+ writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base));
-+ usleep_range(2, 4);
-+ }
-+}
-+
-+static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
-+{
-+ /*
-+ * LVTS_PROTCTL : Thermal Protection Sensor Selection
-+ *
-+ * Bits:
-+ *
-+ * 19-18 : Sensor to base the protection on
-+ * 17-16 : Strategy:
-+ * 00 : Average of 4 sensors
-+ * 01 : Max of 4 sensors
-+ * 10 : Selected sensor with bits 19-18
-+ * 11 : Reserved
-+ */
-+ writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base));
-+
-+ /*
-+ * LVTS_PROTTA : Stage 1 temperature threshold
-+ * LVTS_PROTTB : Stage 2 temperature threshold
-+ * LVTS_PROTTC : Stage 3 temperature threshold
-+ *
-+ * Bits:
-+ *
-+ * 14-0: Raw temperature threshold
-+ *
-+ * writel(0x0, LVTS_PROTTA(lvts_ctrl->base));
-+ * writel(0x0, LVTS_PROTTB(lvts_ctrl->base));
-+ */
-+ writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base));
-+
-+ /*
-+ * LVTS_MONINT : Interrupt configuration register
-+ *
-+ * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
-+ * register, except we set the bits to enable the interrupt.
-+ */
-+ writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base));
-+
-+ return 0;
-+}
-+
-+static int lvts_domain_reset(struct device *dev, struct reset_control *reset)
-+{
-+ int ret;
-+
-+ ret = reset_control_assert(reset);
-+ if (ret)
-+ return ret;
-+
-+ return reset_control_deassert(reset);
-+}
-+
-+/*
-+ * Enable or disable the clocks of a specified thermal controller
-+ */
-+static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
-+{
-+ /*
-+ * LVTS_CLKEN : Internal LVTS clock
-+ *
-+ * Bits:
-+ *
-+ * 0 : enable / disable clock
-+ */
-+ writel(enable, LVTS_CLKEN(lvts_ctrl->base));
-+
-+ return 0;
-+}
-+
-+static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
-+{
-+ u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 };
-+
-+ lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
-+
-+ /*
-+ * LVTS_ID : Get ID and status of the thermal controller
-+ *
-+ * Bits:
-+ *
-+ * 0-5 : thermal controller id
-+ * 7 : thermal controller connection is valid
-+ */
-+ id = readl(LVTS_ID(lvts_ctrl->base));
-+ if (!(id & BIT(7)))
-+ return -EIO;
-+
-+ return 0;
-+}
-+
-+static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
-+{
-+ /*
-+ * Write device mask: 0xC1030000
-+ */
-+ u32 cmds[] = {
-+ 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
-+ 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
-+ 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
-+ 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
-+ };
-+
-+ lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
-+
-+ return 0;
-+}
-+
-+static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl)
-+{
-+ int i;
-+ void __iomem *lvts_edata[] = {
-+ LVTS_EDATA00(lvts_ctrl->base),
-+ LVTS_EDATA01(lvts_ctrl->base),
-+ LVTS_EDATA02(lvts_ctrl->base),
-+ LVTS_EDATA03(lvts_ctrl->base)
-+ };
-+
-+ /*
-+ * LVTS_EDATA0X : Efuse calibration reference value for sensor X
-+ *
-+ * Bits:
-+ *
-+ * 20-0 : Efuse value for normalization data
-+ */
-+ for (i = 0; i < LVTS_SENSOR_MAX; i++)
-+ writel(lvts_ctrl->calibration[i], lvts_edata[i]);
-+
-+ return 0;
-+}
-+
-+static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl)
-+{
-+ u32 value;
-+
-+ /*
-+ * LVTS_TSSEL : Sensing point index numbering
-+ *
-+ * Bits:
-+ *
-+ * 31-24: ADC Sense 3
-+ * 23-16: ADC Sense 2
-+ * 15-8 : ADC Sense 1
-+ * 7-0 : ADC Sense 0
-+ */
-+ value = LVTS_TSSEL_CONF;
-+ writel(value, LVTS_TSSEL(lvts_ctrl->base));
-+
-+ /*
-+ * LVTS_CALSCALE : ADC voltage round
-+ */
-+ value = 0x300;
-+ value = LVTS_CALSCALE_CONF;
-+
-+ /*
-+ * LVTS_MSRCTL0 : Sensor filtering strategy
-+ *
-+ * Filters:
-+ *
-+ * 000 : One sample
-+ * 001 : Avg 2 samples
-+ * 010 : 4 samples, drop min and max, avg 2 samples
-+ * 011 : 6 samples, drop min and max, avg 4 samples
-+ * 100 : 10 samples, drop min and max, avg 8 samples
-+ * 101 : 18 samples, drop min and max, avg 16 samples
-+ *
-+ * Bits:
-+ *
-+ * 0-2 : Sensor0 filter
-+ * 3-5 : Sensor1 filter
-+ * 6-8 : Sensor2 filter
-+ * 9-11 : Sensor3 filter
-+ */
-+ value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 |
-+ LVTS_HW_FILTER << 3 | LVTS_HW_FILTER;
-+ writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
-+
-+ /*
-+ * LVTS_MSRCTL1 : Measurement control
-+ *
-+ * Bits:
-+ *
-+ * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
-+ * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
-+ * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
-+ * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
-+ *
-+ * That configuration will ignore the filtering and the delays
-+ * introduced below in MONCTL1 and MONCTL2
-+ */
-+ if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
-+ value = BIT(9) | BIT(6) | BIT(5) | BIT(4);
-+ writel(value, LVTS_MSRCTL1(lvts_ctrl->base));
-+ }
-+
-+ /*
-+ * LVTS_MONCTL1 : Period unit and group interval configuration
-+ *
-+ * The clock source of LVTS thermal controller is 26MHz.
-+ *
-+ * The period unit is a time base for all the interval delays
-+ * specified in the registers. By default we use 12. The time
-+ * conversion is done by multiplying by 256 and 1/26.10^6
-+ *
-+ * An interval delay multiplied by the period unit gives the
-+ * duration in seconds.
-+ *
-+ * - Filter interval delay is a delay between two samples of
-+ * the same sensor.
-+ *
-+ * - Sensor interval delay is a delay between two samples of
-+ * different sensors.
-+ *
-+ * - Group interval delay is a delay between different rounds.
-+ *
-+ * For example:
-+ * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1,
-+ * and two sensors, TS1 and TS2, are in a LVTS thermal controller
-+ * and then
-+ * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us
-+ * Filter interval delay = 1 * Period unit = 118.149us
-+ * Sensor interval delay = 2 * Period unit = 236.298us
-+ * Group interval delay = 1 * Period unit = 118.149us
-+ *
-+ * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1...
-+ * <--> Filter interval delay
-+ * <--> Sensor interval delay
-+ * <--> Group interval delay
-+ * Bits:
-+ * 29 - 20 : Group interval
-+ * 16 - 13 : Send a single interrupt when crossing the hot threshold (1)
-+ * or an interrupt everytime the hot threshold is crossed (0)
-+ * 9 - 0 : Period unit
-+ *
-+ */
-+ value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT;
-+ writel(value, LVTS_MONCTL1(lvts_ctrl->base));
-+
-+ /*
-+ * LVTS_MONCTL2 : Filtering and sensor interval
-+ *
-+ * Bits:
-+ *
-+ * 25-16 : Interval unit in PERIOD_UNIT between sample on
-+ * the same sensor, filter interval
-+ * 9-0 : Interval unit in PERIOD_UNIT between each sensor
-+ *
-+ */
-+ value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL;
-+ writel(value, LVTS_MONCTL2(lvts_ctrl->base));
-+
-+ return lvts_irq_init(lvts_ctrl);
-+}
-+
-+static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
-+{
-+ struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors;
-+ struct thermal_zone_device *tz;
-+ u32 sensor_map = 0;
-+ int i;
-+
-+ for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) {
-+
-+ int dt_id = lvts_sensors[i].dt_id;
-+
-+ tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i],
-+ &lvts_ops);
-+ if (IS_ERR(tz)) {
-+ /*
-+ * This thermal zone is not described in the
-+ * device tree. It is not an error from the
-+ * thermal OF code POV, we just continue.
-+ */
-+ if (PTR_ERR(tz) == -ENODEV)
-+ continue;
-+
-+ return PTR_ERR(tz);
-+ }
-+
-+ /*
-+ * The thermal zone pointer will be needed in the
-+ * interrupt handler, we store it in the sensor
-+ * structure. The thermal domain structure will be
-+ * passed to the interrupt handler private data as the
-+ * interrupt is shared for all the controller
-+ * belonging to the thermal domain.
-+ */
-+ lvts_sensors[i].tz = tz;
-+
-+ /*
-+ * This sensor was correctly associated with a thermal
-+ * zone, let's set the corresponding bit in the sensor
-+ * map, so we can enable the temperature monitoring in
-+ * the hardware thermal controller.
-+ */
-+ sensor_map |= BIT(i);
-+ }
-+
-+ /*
-+ * Bits:
-+ * 9: Single point access flow
-+ * 0-3: Enable sensing point 0-3
-+ *
-+ * The initialization of the thermal zones give us
-+ * which sensor point to enable. If any thermal zone
-+ * was not described in the device tree, it won't be
-+ * enabled here in the sensor map.
-+ */
-+ writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
-+
-+ return 0;
-+}
-+
-+static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td,
-+ const struct lvts_data *lvts_data)
-+{
-+ struct lvts_ctrl *lvts_ctrl;
-+ int i, ret;
-+
-+ ret = lvts_ctrl_init(dev, lvts_td, lvts_data);
-+ if (ret)
-+ return ret;
-+
-+ ret = lvts_domain_reset(dev, lvts_td->reset);
-+ if (ret) {
-+ dev_dbg(dev, "Failed to reset domain");
-+ return ret;
-+ }
-+
-+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
-+
-+ lvts_ctrl = &lvts_td->lvts_ctrl[i];
-+
-+ /*
-+ * Initialization steps:
-+ *
-+ * - Enable the clock
-+ * - Connect to the LVTS
-+ * - Initialize the LVTS
-+ * - Prepare the calibration data
-+ * - Select monitored sensors
-+ * [ Configure sampling ]
-+ * [ Configure the interrupt ]
-+ * - Start measurement
-+ */
-+ ret = lvts_ctrl_set_enable(lvts_ctrl, true);
-+ if (ret) {
-+ dev_dbg(dev, "Failed to enable LVTS clock");
-+ return ret;
-+ }
-+
-+ ret = lvts_ctrl_connect(dev, lvts_ctrl);
-+ if (ret) {
-+ dev_dbg(dev, "Failed to connect to LVTS controller");
-+ return ret;
-+ }
-+
-+ ret = lvts_ctrl_initialize(dev, lvts_ctrl);
-+ if (ret) {
-+ dev_dbg(dev, "Failed to initialize controller");
-+ return ret;
-+ }
-+
-+ ret = lvts_ctrl_calibrate(dev, lvts_ctrl);
-+ if (ret) {
-+ dev_dbg(dev, "Failed to calibrate controller");
-+ return ret;
-+ }
-+
-+ ret = lvts_ctrl_configure(dev, lvts_ctrl);
-+ if (ret) {
-+ dev_dbg(dev, "Failed to configure controller");
-+ return ret;
-+ }
-+
-+ ret = lvts_ctrl_start(dev, lvts_ctrl);
-+ if (ret) {
-+ dev_dbg(dev, "Failed to start controller");
-+ return ret;
-+ }
-+ }
-+
-+ return lvts_debugfs_init(dev, lvts_td);
-+}
-+
-+static int lvts_probe(struct platform_device *pdev)
-+{
-+ const struct lvts_data *lvts_data;
-+ struct lvts_domain *lvts_td;
-+ struct device *dev = &pdev->dev;
-+ struct resource *res;
-+ int irq, ret;
-+
-+ lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL);
-+ if (!lvts_td)
-+ return -ENOMEM;
-+
-+ lvts_data = of_device_get_match_data(dev);
-+
-+ lvts_td->clk = devm_clk_get_enabled(dev, NULL);
-+ if (IS_ERR(lvts_td->clk))
-+ return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n");
-+
-+ res = platform_get_mem_or_io(pdev, 0);
-+ if (!res)
-+ return dev_err_probe(dev, (-ENXIO), "No IO resource\n");
-+
-+ lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
-+ if (IS_ERR(lvts_td->base))
-+ return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n");
-+
-+ lvts_td->reset = devm_reset_control_get_by_index(dev, 0);
-+ if (IS_ERR(lvts_td->reset))
-+ return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n");
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0)
-+ return dev_err_probe(dev, irq, "No irq resource\n");
-+
-+ ret = lvts_domain_init(dev, lvts_td, lvts_data);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
-+
-+ /*
-+ * At this point the LVTS is initialized and enabled. We can
-+ * safely enable the interrupt.
-+ */
-+ ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler,
-+ IRQF_ONESHOT, dev_name(dev), lvts_td);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Failed to request interrupt\n");
-+
-+ platform_set_drvdata(pdev, lvts_td);
-+
-+ return 0;
-+}
-+
-+static int lvts_remove(struct platform_device *pdev)
-+{
-+ struct lvts_domain *lvts_td;
-+ int i;
-+
-+ lvts_td = platform_get_drvdata(pdev);
-+
-+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
-+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
-+
-+ lvts_debugfs_exit(lvts_td);
-+
-+ return 0;
-+}
-+
-+static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = {
-+ {
-+ .cal_offset = { 0x04, 0x07 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8195_MCU_BIG_CPU0 },
-+ { .dt_id = MT8195_MCU_BIG_CPU1 }
-+ },
-+ .num_lvts_sensor = 2,
-+ .offset = 0x0,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+ },
-+ {
-+ .cal_offset = { 0x0d, 0x10 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8195_MCU_BIG_CPU2 },
-+ { .dt_id = MT8195_MCU_BIG_CPU3 }
-+ },
-+ .num_lvts_sensor = 2,
-+ .offset = 0x100,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+ },
-+ {
-+ .cal_offset = { 0x16, 0x19, 0x1c, 0x1f },
-+ .lvts_sensor = {
-+ { .dt_id = MT8195_MCU_LITTLE_CPU0 },
-+ { .dt_id = MT8195_MCU_LITTLE_CPU1 },
-+ { .dt_id = MT8195_MCU_LITTLE_CPU2 },
-+ { .dt_id = MT8195_MCU_LITTLE_CPU3 }
-+ },
-+ .num_lvts_sensor = 4,
-+ .offset = 0x200,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+ }
-+};
-+
-+static const struct lvts_data mt8195_lvts_mcu_data = {
-+ .lvts_ctrl = mt8195_lvts_data_ctrl,
-+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_data_ctrl),
-+};
-+
-+static const struct of_device_id lvts_of_match[] = {
-+ { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, lvts_of_match);
-+
-+static struct platform_driver lvts_driver = {
-+ .probe = lvts_probe,
-+ .remove = lvts_remove,
-+ .driver = {
-+ .name = "mtk-lvts-thermal",
-+ .of_match_table = lvts_of_match,
-+ },
-+};
-+module_platform_driver(lvts_driver);
-+
-+MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>");
-+MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 498e2f7a6e69dcbca24715de2b4b97569fdfeff4 Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Thu, 9 Feb 2023 11:56:24 +0100
-Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controllers
-
-Add LVTS thermal controllers dt-binding definition for mt8192 and mt8195.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20230209105628.50294-3-bchihi@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- .../thermal/mediatek,lvts-thermal.yaml | 142 ++++++++++++++++++
- .../thermal/mediatek,lvts-thermal.h | 19 +++
- 2 files changed, 161 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
- create mode 100644 include/dt-bindings/thermal/mediatek,lvts-thermal.h
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
-@@ -0,0 +1,142 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek SoC Low Voltage Thermal Sensor (LVTS)
-+
-+maintainers:
-+ - Balsam CHIHI <bchihi@baylibre.com>
-+
-+description: |
-+ LVTS is a thermal management architecture composed of three subsystems,
-+ a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU),
-+ a Converter - Low Voltage Thermal Sensor converter (LVTS), and
-+ a Digital controller (LVTS_CTRL).
-+
-+properties:
-+ compatible:
-+ enum:
-+ - mediatek,mt8192-lvts-ap
-+ - mediatek,mt8192-lvts-mcu
-+ - mediatek,mt8195-lvts-ap
-+ - mediatek,mt8195-lvts-mcu
-+
-+ reg:
-+ maxItems: 1
-+
-+ interrupts:
-+ maxItems: 1
-+
-+ clocks:
-+ maxItems: 1
-+
-+ resets:
-+ maxItems: 1
-+ description: LVTS reset for clearing temporary data on AP/MCU.
-+
-+ nvmem-cells:
-+ minItems: 1
-+ items:
-+ - description: Calibration eFuse data 1 for LVTS
-+ - description: Calibration eFuse data 2 for LVTS
-+
-+ nvmem-cell-names:
-+ minItems: 1
-+ items:
-+ - const: lvts-calib-data-1
-+ - const: lvts-calib-data-2
-+
-+ "#thermal-sensor-cells":
-+ const: 1
-+
-+allOf:
-+ - $ref: thermal-sensor.yaml#
-+
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ enum:
-+ - mediatek,mt8192-lvts-ap
-+ - mediatek,mt8192-lvts-mcu
-+ then:
-+ properties:
-+ nvmem-cells:
-+ maxItems: 1
-+
-+ nvmem-cell-names:
-+ maxItems: 1
-+
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ enum:
-+ - mediatek,mt8195-lvts-ap
-+ - mediatek,mt8195-lvts-mcu
-+ then:
-+ properties:
-+ nvmem-cells:
-+ minItems: 2
-+
-+ nvmem-cell-names:
-+ minItems: 2
-+
-+required:
-+ - compatible
-+ - reg
-+ - interrupts
-+ - clocks
-+ - resets
-+ - nvmem-cells
-+ - nvmem-cell-names
-+ - "#thermal-sensor-cells"
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ #include <dt-bindings/interrupt-controller/arm-gic.h>
-+ #include <dt-bindings/clock/mt8195-clk.h>
-+ #include <dt-bindings/reset/mt8195-resets.h>
-+ #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
-+
-+ soc {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
-+ lvts_mcu: thermal-sensor@11278000 {
-+ compatible = "mediatek,mt8195-lvts-mcu";
-+ reg = <0 0x11278000 0 0x1000>;
-+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
-+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
-+ resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
-+ nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
-+ nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
-+ #thermal-sensor-cells = <1>;
-+ };
-+ };
-+
-+ thermal_zones: thermal-zones {
-+ cpu0-thermal {
-+ polling-delay = <1000>;
-+ polling-delay-passive = <250>;
-+ thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
-+
-+ trips {
-+ cpu0_alert: trip-alert {
-+ temperature = <85000>;
-+ hysteresis = <2000>;
-+ type = "passive";
-+ };
-+
-+ cpu0_crit: trip-crit {
-+ temperature = <100000>;
-+ hysteresis = <2000>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+ };
---- /dev/null
-+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-@@ -0,0 +1,19 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Balsam CHIHI <bchihi@baylibre.com>
-+ */
-+
-+#ifndef __MEDIATEK_LVTS_DT_H
-+#define __MEDIATEK_LVTS_DT_H
-+
-+#define MT8195_MCU_BIG_CPU0 0
-+#define MT8195_MCU_BIG_CPU1 1
-+#define MT8195_MCU_BIG_CPU2 2
-+#define MT8195_MCU_BIG_CPU3 3
-+#define MT8195_MCU_LITTLE_CPU0 4
-+#define MT8195_MCU_LITTLE_CPU1 5
-+#define MT8195_MCU_LITTLE_CPU2 6
-+#define MT8195_MCU_LITTLE_CPU3 7
-+
-+#endif /* __MEDIATEK_LVTS_DT_H */
+++ /dev/null
-From 05aaa7fdb0736262e224369b9b9f1410320fc71b Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 7 Mar 2023 16:45:21 +0100
-Subject: [PATCH] dt-bindings: thermal: mediatek: Add AP domain to LVTS thermal
- controllers for mt8195
-
-Add AP Domain to LVTS thermal controllers dt-binding definition for mt8195.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230307154524.118541-2-bchihi@baylibre.com
----
- include/dt-bindings/thermal/mediatek,lvts-thermal.h | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-@@ -16,4 +16,14 @@
- #define MT8195_MCU_LITTLE_CPU2 6
- #define MT8195_MCU_LITTLE_CPU3 7
-
-+#define MT8195_AP_VPU0 8
-+#define MT8195_AP_VPU1 9
-+#define MT8195_AP_GPU0 10
-+#define MT8195_AP_GPU1 11
-+#define MT8195_AP_VDEC 12
-+#define MT8195_AP_IMG 13
-+#define MT8195_AP_INFRA 14
-+#define MT8195_AP_CAM0 15
-+#define MT8195_AP_CAM1 16
-+
- #endif /* __MEDIATEK_LVTS_DT_H */
+++ /dev/null
-From a6ff3c0021468721b96e84892a8cae24bde8d65f Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:29 +0100
-Subject: [PATCH] thermal/core: Add a thermal zone 'devdata' accessor
-
-The thermal zone device structure is exposed to the different drivers
-and obviously they access the internals while that should be
-restricted to the core thermal code.
-
-In order to self-encapsulate the thermal core code, we need to prevent
-the drivers accessing directly the thermal zone structure and provide
-accessor functions to deal with.
-
-Provide an accessor to the 'devdata' structure and make use of it in
-the different drivers.
-
-No functional changes intended.
-
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
-Acked-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/thermal_core.c | 6 ++++++
- include/linux/thermal.h | 7 +++++++
- 2 files changed, 13 insertions(+)
-
---- a/drivers/thermal/thermal_core.c
-+++ b/drivers/thermal/thermal_core.c
-@@ -1346,6 +1346,12 @@ struct thermal_zone_device *thermal_zone
- }
- EXPORT_SYMBOL_GPL(thermal_zone_device_register);
-
-+void *thermal_zone_device_priv(struct thermal_zone_device *tzd)
-+{
-+ return tzd->devdata;
-+}
-+EXPORT_SYMBOL_GPL(thermal_zone_device_priv);
-+
- /**
- * thermal_zone_device_unregister - removes the registered thermal zone device
- * @tz: the thermal zone device to remove
---- a/include/linux/thermal.h
-+++ b/include/linux/thermal.h
-@@ -346,6 +346,8 @@ thermal_zone_device_register_with_trips(
- void *, struct thermal_zone_device_ops *,
- struct thermal_zone_params *, int, int);
-
-+void *thermal_zone_device_priv(struct thermal_zone_device *tzd);
-+
- int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int,
- struct thermal_cooling_device *,
- unsigned long, unsigned long,
-@@ -417,6 +419,11 @@ static inline int thermal_zone_get_offse
- struct thermal_zone_device *tz)
- { return -ENODEV; }
-
-+static inline void *thermal_zone_device_priv(struct thermal_zone_device *tz)
-+{
-+ return NULL;
-+}
-+
- static inline int thermal_zone_device_enable(struct thermal_zone_device *tz)
- { return -ENODEV; }
-
+++ /dev/null
-From 072e35c98806100182c0a7263cf4cba09ce43463 Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:38 +0100
-Subject: [PATCH] thermal/core: Add thermal_zone_device structure 'type'
- accessor
-
-The thermal zone device structure is exposed via the exported
-thermal.h header. This structure should stay private the thermal core
-code. In order to encapsulate the structure, let's add an accessor to
-get the 'type' of the thermal zone.
-
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/thermal_core.c | 6 ++++++
- include/linux/thermal.h | 6 ++++++
- 2 files changed, 12 insertions(+)
-
---- a/drivers/thermal/thermal_core.c
-+++ b/drivers/thermal/thermal_core.c
-@@ -1352,6 +1352,12 @@ void *thermal_zone_device_priv(struct th
- }
- EXPORT_SYMBOL_GPL(thermal_zone_device_priv);
-
-+const char *thermal_zone_device_type(struct thermal_zone_device *tzd)
-+{
-+ return tzd->type;
-+}
-+EXPORT_SYMBOL_GPL(thermal_zone_device_type);
-+
- /**
- * thermal_zone_device_unregister - removes the registered thermal zone device
- * @tz: the thermal zone device to remove
---- a/include/linux/thermal.h
-+++ b/include/linux/thermal.h
-@@ -347,6 +347,7 @@ thermal_zone_device_register_with_trips(
- struct thermal_zone_params *, int, int);
-
- void *thermal_zone_device_priv(struct thermal_zone_device *tzd);
-+const char *thermal_zone_device_type(struct thermal_zone_device *tzd);
-
- int thermal_zone_bind_cooling_device(struct thermal_zone_device *, int,
- struct thermal_cooling_device *,
-@@ -423,6 +424,11 @@ static inline void *thermal_zone_device_
- {
- return NULL;
- }
-+
-+static inline const char *thermal_zone_device_type(struct thermal_zone_device *tzd)
-+{
-+ return NULL;
-+}
-
- static inline int thermal_zone_device_enable(struct thermal_zone_device *tz)
- { return -ENODEV; }
+++ /dev/null
-From 7d78bab533eb9aa0e5240e25a204e8f416723ed6 Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:30 +0100
-Subject: [PATCH 07/42] thermal/core: Use the thermal zone 'devdata' accessor
- in thermal located drivers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The thermal zone device structure is exposed to the different drivers
-and obviously they access the internals while that should be
-restricted to the core thermal code.
-
-In order to self-encapsulate the thermal core code, we need to prevent
-the drivers accessing directly the thermal zone structure and provide
-accessor functions to deal with.
-
-Use the devdata accessor introduced in the previous patch.
-
-No functional changes intended.
-
-[skipped drivers not relevant for mediatek target]
-
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> #R-Car
-Acked-by: Mark Brown <broonie@kernel.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek auxadc and lvts
-Reviewed-by: Balsam CHIHI <bchihi@baylibre.com> #Mediatek lvts
-Reviewed-by: Adam Ward <DLG-Adam.Ward.opensource@dm.renesas.com> #da9062
-Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com> #spread
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> #sun8i_thermal
-Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com> #Broadcom
-Reviewed-by: Dhruva Gole <d-gole@ti.com> # K3 bandgap
-Acked-by: Linus Walleij <linus.walleij@linaro.org>
-Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip
-Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> #uniphier
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/mediatek/auxadc_thermal.c | 2 +-
- drivers/thermal/mediatek/lvts_thermal.c | 4 ++--
- 43 files changed, 71 insertions(+), 73 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -763,7 +763,7 @@ static int mtk_thermal_bank_temperature(
-
- static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
- {
-- struct mtk_thermal *mt = tz->devdata;
-+ struct mtk_thermal *mt = thermal_zone_device_priv(tz);
- int i;
- int tempmax = INT_MIN;
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -252,7 +252,7 @@ static u32 lvts_temp_to_raw(int temperat
-
- static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
- {
-- struct lvts_sensor *lvts_sensor = tz->devdata;
-+ struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
- void __iomem *msr = lvts_sensor->msr;
- u32 value;
-
-@@ -290,7 +290,7 @@ static int lvts_get_temp(struct thermal_
-
- static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
- {
-- struct lvts_sensor *lvts_sensor = tz->devdata;
-+ struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
- void __iomem *base = lvts_sensor->base;
- u32 raw_low = lvts_temp_to_raw(low);
- u32 raw_high = lvts_temp_to_raw(high);
+++ /dev/null
-From cc9c60e9cfeeac45d63361fa8c085c43c4bdfe3a Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:36 +0100
-Subject: [PATCH 08/42] thermal/hwmon: Use the right device for
- devm_thermal_add_hwmon_sysfs()
-
-The devres variant of thermal_add_hwmon_sysfs() only takes the thermal
-zone structure pointer as parameter.
-
-Actually, it uses the tz->device to add it in the devres list.
-
-It is preferable to use the device registering the thermal zone
-instead of the thermal zone device itself. That prevents the driver
-accessing the thermal zone structure internals and it is from my POV
-more correct regarding how devm_ is used.
-
-[skipped imx thermal which did not apply cleanly and irrelevant on
-mediatek target]
-
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> #amlogic_thermal
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> #sun8i_thermal
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek auxadc
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/amlogic_thermal.c | 2 +-
- drivers/thermal/imx_sc_thermal.c | 2 +-
- drivers/thermal/k3_bandgap.c | 2 +-
- drivers/thermal/mediatek/auxadc_thermal.c | 2 +-
- drivers/thermal/qcom/qcom-spmi-adc-tm5.c | 2 +-
- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 2 +-
- drivers/thermal/qcom/tsens.c | 2 +-
- drivers/thermal/qoriq_thermal.c | 2 +-
- drivers/thermal/sun8i_thermal.c | 2 +-
- drivers/thermal/tegra/tegra30-tsensor.c | 2 +-
- drivers/thermal/thermal_hwmon.c | 4 ++--
- drivers/thermal/thermal_hwmon.h | 4 ++--
- drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
- 13 files changed, 15 insertions(+), 15 deletions(-)
-
---- a/drivers/thermal/amlogic_thermal.c
-+++ b/drivers/thermal/amlogic_thermal.c
-@@ -286,7 +286,7 @@ static int amlogic_thermal_probe(struct
- return ret;
- }
-
-- if (devm_thermal_add_hwmon_sysfs(pdata->tzd))
-+ if (devm_thermal_add_hwmon_sysfs(&pdev->dev, pdata->tzd))
- dev_warn(&pdev->dev, "Failed to add hwmon sysfs attributes\n");
-
- ret = amlogic_thermal_initialize(pdata);
---- a/drivers/thermal/imx_sc_thermal.c
-+++ b/drivers/thermal/imx_sc_thermal.c
-@@ -120,7 +120,7 @@ static int imx_sc_thermal_probe(struct p
- return ret;
- }
-
-- if (devm_thermal_add_hwmon_sysfs(sensor->tzd))
-+ if (devm_thermal_add_hwmon_sysfs(&pdev->dev, sensor->tzd))
- dev_warn(&pdev->dev, "failed to add hwmon sysfs attributes\n");
- }
-
---- a/drivers/thermal/k3_bandgap.c
-+++ b/drivers/thermal/k3_bandgap.c
-@@ -222,7 +222,7 @@ static int k3_bandgap_probe(struct platf
- goto err_alloc;
- }
-
-- if (devm_thermal_add_hwmon_sysfs(data[id].tzd))
-+ if (devm_thermal_add_hwmon_sysfs(dev, data[id].tzd))
- dev_warn(dev, "Failed to add hwmon sysfs attributes\n");
- }
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1210,7 +1210,7 @@ static int mtk_thermal_probe(struct plat
- goto err_disable_clk_peri_therm;
- }
-
-- ret = devm_thermal_add_hwmon_sysfs(tzdev);
-+ ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
- if (ret)
- dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
-
---- a/drivers/thermal/qcom/qcom-spmi-adc-tm5.c
-+++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5.c
-@@ -688,7 +688,7 @@ static int adc_tm5_register_tzd(struct a
- return PTR_ERR(tzd);
- }
- adc_tm->channels[i].tzd = tzd;
-- if (devm_thermal_add_hwmon_sysfs(tzd))
-+ if (devm_thermal_add_hwmon_sysfs(adc_tm->dev, tzd))
- dev_warn(adc_tm->dev,
- "Failed to add hwmon sysfs attributes\n");
- }
---- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
-+++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
-@@ -460,7 +460,7 @@ static int qpnp_tm_probe(struct platform
- return ret;
- }
-
-- if (devm_thermal_add_hwmon_sysfs(chip->tz_dev))
-+ if (devm_thermal_add_hwmon_sysfs(&pdev->dev, chip->tz_dev))
- dev_warn(&pdev->dev,
- "Failed to add hwmon sysfs attributes\n");
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -1056,7 +1056,7 @@ static int tsens_register(struct tsens_p
- if (priv->ops->enable)
- priv->ops->enable(priv, i);
-
-- if (devm_thermal_add_hwmon_sysfs(tzd))
-+ if (devm_thermal_add_hwmon_sysfs(priv->dev, tzd))
- dev_warn(priv->dev,
- "Failed to add hwmon sysfs attributes\n");
- }
---- a/drivers/thermal/qoriq_thermal.c
-+++ b/drivers/thermal/qoriq_thermal.c
-@@ -158,7 +158,7 @@ static int qoriq_tmu_register_tmu_zone(s
- return ret;
- }
-
-- if (devm_thermal_add_hwmon_sysfs(tzd))
-+ if (devm_thermal_add_hwmon_sysfs(dev, tzd))
- dev_warn(dev,
- "Failed to add hwmon sysfs attributes\n");
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -468,7 +468,7 @@ static int sun8i_ths_register(struct ths
- if (IS_ERR(tmdev->sensor[i].tzd))
- return PTR_ERR(tmdev->sensor[i].tzd);
-
-- if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd))
-+ if (devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd))
- dev_warn(tmdev->dev,
- "Failed to add hwmon sysfs attributes\n");
- }
---- a/drivers/thermal/tegra/tegra30-tsensor.c
-+++ b/drivers/thermal/tegra/tegra30-tsensor.c
-@@ -530,7 +530,7 @@ static int tegra_tsensor_register_channe
- return 0;
- }
-
-- if (devm_thermal_add_hwmon_sysfs(tsc->tzd))
-+ if (devm_thermal_add_hwmon_sysfs(ts->dev, tsc->tzd))
- dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n");
-
- return 0;
---- a/drivers/thermal/thermal_hwmon.c
-+++ b/drivers/thermal/thermal_hwmon.c
-@@ -255,7 +255,7 @@ static void devm_thermal_hwmon_release(s
- thermal_remove_hwmon_sysfs(*(struct thermal_zone_device **)res);
- }
-
--int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
-+int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz)
- {
- struct thermal_zone_device **ptr;
- int ret;
-@@ -272,7 +272,7 @@ int devm_thermal_add_hwmon_sysfs(struct
- }
-
- *ptr = tz;
-- devres_add(&tz->device, ptr);
-+ devres_add(dev, ptr);
-
- return ret;
- }
---- a/drivers/thermal/thermal_hwmon.h
-+++ b/drivers/thermal/thermal_hwmon.h
-@@ -17,7 +17,7 @@
-
- #ifdef CONFIG_THERMAL_HWMON
- int thermal_add_hwmon_sysfs(struct thermal_zone_device *tz);
--int devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz);
-+int devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz);
- void thermal_remove_hwmon_sysfs(struct thermal_zone_device *tz);
- #else
- static inline int
-@@ -27,7 +27,7 @@ thermal_add_hwmon_sysfs(struct thermal_z
- }
-
- static inline int
--devm_thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
-+devm_thermal_add_hwmon_sysfs(struct device *dev, struct thermal_zone_device *tz)
- {
- return 0;
- }
---- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-@@ -182,7 +182,7 @@ int ti_thermal_expose_sensor(struct ti_b
- ti_bandgap_set_sensor_data(bgp, id, data);
- ti_bandgap_write_update_interval(bgp, data->sensor_id, interval);
-
-- if (devm_thermal_add_hwmon_sysfs(data->ti_thermal))
-+ if (devm_thermal_add_hwmon_sysfs(bgp->dev, data->ti_thermal))
- dev_warn(bgp->dev, "failed to add hwmon sysfs attributes\n");
-
- return 0;
+++ /dev/null
-From 5a72b8e4bac753e4dc74dc0a1335d120f63df97a Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:37 +0100
-Subject: [PATCH 09/42] thermal: Don't use 'device' internal thermal zone
- structure field
-
-Some drivers are directly using the thermal zone's 'device' structure
-field.
-
-Use the driver device pointer instead of the thermal zone device when
-it is available.
-
-Remove the traces when they are duplicate with the traces in the core
-code.
-
-[again skipped imx_thermal.c]
-
-Cc: Jean Delvare <jdelvare@suse.com>
-Cc: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Reviewed-by: Balsam CHIHI <bchihi@baylibre.com> #Mediatek LVTS
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek LVTS
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/mediatek/lvts_thermal.c | 4 ++--
- drivers/thermal/thermal_hwmon.c | 4 ++--
- drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
- 3 files changed, 5 insertions(+), 5 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -305,7 +305,7 @@ static int lvts_set_trips(struct thermal
- * 14-0 : Raw temperature for threshold
- */
- if (low != -INT_MAX) {
-- dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low);
-+ pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low);
- writel(raw_low, LVTS_H2NTHRE(base));
- }
-
-@@ -318,7 +318,7 @@ static int lvts_set_trips(struct thermal
- *
- * 14-0 : Raw temperature for threshold
- */
-- dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high);
-+ pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high);
- writel(raw_high, LVTS_HTHRE(base));
-
- return 0;
---- a/drivers/thermal/thermal_hwmon.c
-+++ b/drivers/thermal/thermal_hwmon.c
-@@ -220,14 +220,14 @@ void thermal_remove_hwmon_sysfs(struct t
- hwmon = thermal_hwmon_lookup_by_type(tz);
- if (unlikely(!hwmon)) {
- /* Should never happen... */
-- dev_dbg(&tz->device, "hwmon device lookup failed!\n");
-+ dev_dbg(hwmon->device, "hwmon device lookup failed!\n");
- return;
- }
-
- temp = thermal_hwmon_lookup_temp(hwmon, tz);
- if (unlikely(!temp)) {
- /* Should never happen... */
-- dev_dbg(&tz->device, "temperature input lookup failed!\n");
-+ dev_dbg(hwmon->device, "temperature input lookup failed!\n");
- return;
- }
-
---- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-@@ -43,7 +43,7 @@ static void ti_thermal_work(struct work_
-
- thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED);
-
-- dev_dbg(&data->ti_thermal->device, "updated thermal zone %s\n",
-+ dev_dbg(data->bgp->dev, "updated thermal zone %s\n",
- data->ti_thermal->type);
- }
-
+++ /dev/null
-From 66b3a292d3fc749e8ec7ac5278a17e8a5757ecbc Mon Sep 17 00:00:00 2001
-From: Daniel Lezcano <daniel.lezcano@linaro.org>
-Date: Wed, 1 Mar 2023 21:14:41 +0100
-Subject: [PATCH 10/42] thermal: Use thermal_zone_device_type() accessor
-
-Replace the accesses to 'tz->type' by its accessor version in order to
-self-encapsulate the thermal_zone_device structure.
-
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Reviewed-by: Ido Schimmel <idosch@nvidia.com> #mlxsw
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #MediaTek LVTS
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/net/ethernet/mellanox/mlxsw/core_thermal.c | 2 +-
- drivers/thermal/mediatek/lvts_thermal.c | 6 ++++--
- drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +-
- 3 files changed, 6 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c
-+++ b/drivers/net/ethernet/mellanox/mlxsw/core_thermal.c
-@@ -168,7 +168,7 @@ mlxsw_thermal_module_trips_update(struct
-
- if (crit_temp > emerg_temp) {
- dev_warn(dev, "%s : Critical threshold %d is above emergency threshold %d\n",
-- tz->tzdev->type, crit_temp, emerg_temp);
-+ thermal_zone_device_type(tz->tzdev), crit_temp, emerg_temp);
- return 0;
- }
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -305,7 +305,8 @@ static int lvts_set_trips(struct thermal
- * 14-0 : Raw temperature for threshold
- */
- if (low != -INT_MAX) {
-- pr_debug("%s: Setting low limit temperature interrupt: %d\n", tz->type, low);
-+ pr_debug("%s: Setting low limit temperature interrupt: %d\n",
-+ thermal_zone_device_type(tz), low);
- writel(raw_low, LVTS_H2NTHRE(base));
- }
-
-@@ -318,7 +319,8 @@ static int lvts_set_trips(struct thermal
- *
- * 14-0 : Raw temperature for threshold
- */
-- pr_debug("%s: Setting high limit temperature interrupt: %d\n", tz->type, high);
-+ pr_debug("%s: Setting high limit temperature interrupt: %d\n",
-+ thermal_zone_device_type(tz), high);
- writel(raw_high, LVTS_HTHRE(base));
-
- return 0;
---- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
-@@ -44,7 +44,7 @@ static void ti_thermal_work(struct work_
- thermal_zone_device_update(data->ti_thermal, THERMAL_EVENT_UNSPECIFIED);
-
- dev_dbg(data->bgp->dev, "updated thermal zone %s\n",
-- data->ti_thermal->type);
-+ thermal_zone_device_type(data->ti_thermal));
- }
-
- /**
+++ /dev/null
-From f6658c1c4ae98477d6be00495226c0617354fe76 Mon Sep 17 00:00:00 2001
-From: Markus Schneider-Pargmann <msp@baylibre.com>
-Date: Fri, 27 Jan 2023 16:44:43 +0100
-Subject: [PATCH 11/42] thermal/drivers/mediatek: Control buffer enablement
- tweaks
-
-Add logic in order to be able to turn on the control buffer on MT8365.
-This change now allows to have control buffer support for MTK_THERMAL_V1,
-and it allows to define the register offset, and mask used to enable it.
-
-Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
-Signed-off-by: Fabien Parent <fparent@baylibre.com>
-Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-2-55a1ae14af74@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mediatek/auxadc_thermal.c | 28 +++++++++++++++--------
- 1 file changed, 19 insertions(+), 9 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -307,6 +307,9 @@ struct mtk_thermal_data {
- bool need_switch_bank;
- struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
- enum mtk_thermal_version version;
-+ u32 apmixed_buffer_ctl_reg;
-+ u32 apmixed_buffer_ctl_mask;
-+ u32 apmixed_buffer_ctl_set;
- };
-
- struct mtk_thermal {
-@@ -560,6 +563,9 @@ static const struct mtk_thermal_data mt7
- .adcpnp = mt7622_adcpnp,
- .sensor_mux_values = mt7622_mux_values,
- .version = MTK_THERMAL_V2,
-+ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
-+ .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
-+ .apmixed_buffer_ctl_set = BIT(0),
- };
-
- /*
-@@ -1079,14 +1085,18 @@ static const struct of_device_id mtk_the
- };
- MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
-
--static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
-+static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt,
-+ void __iomem *apmixed_base)
- {
-- int tmp;
-+ u32 tmp;
-+
-+ if (!mt->conf->apmixed_buffer_ctl_reg)
-+ return;
-
-- tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
-- tmp &= ~(0x37);
-- tmp |= 0x1;
-- writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
-+ tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
-+ tmp &= mt->conf->apmixed_buffer_ctl_mask;
-+ tmp |= mt->conf->apmixed_buffer_ctl_set;
-+ writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
- udelay(200);
- }
-
-@@ -1184,10 +1194,10 @@ static int mtk_thermal_probe(struct plat
- goto err_disable_clk_auxadc;
- }
-
-- if (mt->conf->version != MTK_THERMAL_V1) {
-- mtk_thermal_turn_on_buffer(apmixed_base);
-+ mtk_thermal_turn_on_buffer(mt, apmixed_base);
-+
-+ if (mt->conf->version != MTK_THERMAL_V2)
- mtk_thermal_release_periodic_ts(mt, auxadc_base);
-- }
-
- if (mt->conf->version == MTK_THERMAL_V1)
- mt->raw_to_mcelsius = raw_to_mcelsius_v1;
+++ /dev/null
-From c4eff784465f88218dc5eb51320320464db83d3f Mon Sep 17 00:00:00 2001
-From: Fabien Parent <fparent@baylibre.com>
-Date: Fri, 27 Jan 2023 16:44:44 +0100
-Subject: [PATCH 12/42] thermal/drivers/mediatek: Add support for MT8365 SoC
-
-MT8365 is similar to the other SoCs supported by the driver. It has only
-one bank and 3 actual sensors that can be multiplexed. There is another
-one sensor that does not have usable data.
-
-Signed-off-by: Fabien Parent <fparent@baylibre.com>
-Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-3-55a1ae14af74@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mediatek/auxadc_thermal.c | 68 +++++++++++++++++++++++
- 1 file changed, 68 insertions(+)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -31,6 +31,7 @@
- #define AUXADC_CON2_V 0x010
- #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
-
-+#define APMIXED_SYS_TS_CON0 0x600
- #define APMIXED_SYS_TS_CON1 0x604
-
- /* Thermal Controller Registers */
-@@ -281,6 +282,17 @@ enum mtk_thermal_version {
- /* The calibration coefficient of sensor */
- #define MT7986_CALIBRATION 165
-
-+/* MT8365 */
-+#define MT8365_TEMP_AUXADC_CHANNEL 11
-+#define MT8365_CALIBRATION 164
-+#define MT8365_NUM_CONTROLLER 1
-+#define MT8365_NUM_BANKS 1
-+#define MT8365_NUM_SENSORS 3
-+#define MT8365_NUM_SENSORS_PER_ZONE 3
-+#define MT8365_TS1 0
-+#define MT8365_TS2 1
-+#define MT8365_TS3 2
-+
- struct mtk_thermal;
-
- struct thermal_bank_cfg {
-@@ -435,6 +447,24 @@ static const int mt7986_mux_values[MT798
- static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
- static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
-
-+/* MT8365 thermal sensor data */
-+static const int mt8365_bank_data[MT8365_NUM_SENSORS] = {
-+ MT8365_TS1, MT8365_TS2, MT8365_TS3
-+};
-+
-+static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = {
-+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
-+};
-+
-+static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = {
-+ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
-+};
-+
-+static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 };
-+static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 };
-+
-+static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 };
-+
- /*
- * The MT8173 thermal controller has four banks. Each bank can read up to
- * four temperature sensors simultaneously. The MT8173 has a total of 5
-@@ -510,6 +540,40 @@ static const struct mtk_thermal_data mt2
- };
-
- /*
-+ * The MT8365 thermal controller has one bank, which can read up to
-+ * four temperature sensors simultaneously. The MT8365 has a total of 3
-+ * temperature sensors.
-+ *
-+ * The thermal core only gets the maximum temperature of this one bank,
-+ * so the bank concept wouldn't be necessary here. However, the SVS (Smart
-+ * Voltage Scaling) unit makes its decisions based on the same bank
-+ * data.
-+ */
-+static const struct mtk_thermal_data mt8365_thermal_data = {
-+ .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL,
-+ .num_banks = MT8365_NUM_BANKS,
-+ .num_sensors = MT8365_NUM_SENSORS,
-+ .vts_index = mt8365_vts_index,
-+ .cali_val = MT8365_CALIBRATION,
-+ .num_controller = MT8365_NUM_CONTROLLER,
-+ .controller_offset = mt8365_tc_offset,
-+ .need_switch_bank = false,
-+ .bank_data = {
-+ {
-+ .num_sensors = MT8365_NUM_SENSORS,
-+ .sensors = mt8365_bank_data
-+ },
-+ },
-+ .msr = mt8365_msr,
-+ .adcpnp = mt8365_adcpnp,
-+ .sensor_mux_values = mt8365_mux_values,
-+ .version = MTK_THERMAL_V1,
-+ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0,
-+ .apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28),
-+ .apmixed_buffer_ctl_set = 0,
-+};
-+
-+/*
- * The MT2712 thermal controller has one bank, which can read up to
- * four temperature sensors simultaneously. The MT2712 has a total of 4
- * temperature sensors.
-@@ -1080,6 +1144,10 @@ static const struct of_device_id mtk_the
- {
- .compatible = "mediatek,mt8183-thermal",
- .data = (void *)&mt8183_thermal_data,
-+ },
-+ {
-+ .compatible = "mediatek,mt8365-thermal",
-+ .data = (void *)&mt8365_thermal_data,
- }, {
- },
- };
+++ /dev/null
-From 4eead70db74922bc61e9d0b4591524369a335751 Mon Sep 17 00:00:00 2001
-From: Amjad Ouled-Ameur <aouledameur@baylibre.com>
-Date: Fri, 27 Jan 2023 16:44:46 +0100
-Subject: [PATCH 13/42] thermal/drivers/mediatek: Add delay after thermal banks
- initialization
-
-Thermal sensor reads performed immediately after thermal bank
-initialization returns bogus values. This is currently tackled by returning
-0 if the temperature is bogus (exceeding 200000).
-
-Instead, add a delay between the bank init and the thermal zone device
-register to properly fix this.
-
-Signed-off-by: Michael Kao <michael.kao@mediatek.com>
-Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
-Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20221018-up-i350-thermal-bringup-v9-5-55a1ae14af74@baylibre.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/mediatek/auxadc_thermal.c | 11 +++--------
- 1 file changed, 3 insertions(+), 8 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -816,14 +816,6 @@ static int mtk_thermal_bank_temperature(
- mt, conf->bank_data[bank->id].sensors[i], raw);
-
-
-- /*
-- * The first read of a sensor often contains very high bogus
-- * temperature value. Filter these out so that the system does
-- * not immediately shut down.
-- */
-- if (temp > 200000)
-- temp = 0;
--
- if (temp > max)
- max = temp;
- }
-@@ -1281,6 +1273,9 @@ static int mtk_thermal_probe(struct plat
-
- platform_set_drvdata(pdev, mt);
-
-+ /* Delay for thermal banks to be ready */
-+ msleep(30);
-+
- tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
- &mtk_thermal_ops);
- if (IS_ERR(tzdev)) {
+++ /dev/null
-From ad9dc9e92367803a4f9576aea0dab110d03fc510 Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wenst@chromium.org>
-Date: Tue, 28 Mar 2023 11:10:17 +0800
-Subject: [PATCH 14/42] thermal/drivers/mediatek/lvts_thermal: Fix sensor 1
- interrupt status bitmask
-
-The binary representation for sensor 1 interrupt status was incorrectly
-assembled, when compared to the full table given in the same comment
-section. The conversion into hex was also incorrect, leading to
-incorrect interrupt status bitmask for sensor 1. This would cause the
-driver to incorrectly identify changes for sensor 1, when in fact it
-was sensor 0, or a sensor access time out.
-
-Fix the binary and hex representations in the comments, and the actual
-bitmask macro.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230328031017.1360976-1-wenst@chromium.org
----
- drivers/thermal/mediatek/lvts_thermal.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -66,7 +66,7 @@
- #define LVTS_MONINT_CONF 0x9FBF7BDE
-
- #define LVTS_INT_SENSOR0 0x0009001F
--#define LVTS_INT_SENSOR1 0X000881F0
-+#define LVTS_INT_SENSOR1 0x001203E0
- #define LVTS_INT_SENSOR2 0x00247C00
- #define LVTS_INT_SENSOR3 0x1FC00000
-
-@@ -395,8 +395,8 @@ static irqreturn_t lvts_ctrl_irq_handler
- * => 0x1FC00000
- * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
- * => 0x00247C00
-- * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000
-- * => 0X000881F0
-+ * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000
-+ * => 0X001203E0
- * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
- * => 0x0009001F
- */
+++ /dev/null
-From 9aad43ad3285fc21158fb416830a6156a9a31fa5 Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 7 Mar 2023 16:45:22 +0100
-Subject: [PATCH 15/42] thermal/drivers/mediatek/lvts_thermal: Add AP domain
- for mt8195
-
-Add MT8195 AP Domain support to LVTS Driver.
-
-Take the opportunity to update the comments to show calibration data
-information related to the new domain.
-
-[dlezcano]: Massaged a bit the changelog
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230307154524.118541-3-bchihi@baylibre.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 94 +++++++++++++++++++------
- 1 file changed, 74 insertions(+), 20 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -530,29 +530,33 @@ static int lvts_sensor_init(struct devic
- * The efuse blob values follows the sensor enumeration per thermal
- * controller. The decoding of the stream is as follow:
- *
-- * <--?-> <----big0 ???---> <-sensor0-> <-0->
-- * ------------------------------------------
-- * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 |
-- * ------------------------------------------
-+ * stream index map for MCU Domain :
- *
-- * <--sensor1--><-0-> <----big1 ???---> <-sen
-- * ------------------------------------------
-- * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
-- * ------------------------------------------
-+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
-+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
- *
-- * sor0-> <-0-> <-sensor1-> <-0-> ..........
-- * ------------------------------------------
-- * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
-- * ------------------------------------------
-+ * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3----->
-+ * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12
- *
-- * And so on ...
-+ * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
-+ * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
-+ *
-+ * stream index map for AP Domain :
-+ *
-+ * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
-+ * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
-+ *
-+ * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
-+ * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
-+ *
-+ * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
-+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
-+ *
-+ * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
-+ * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
- *
- * The data description gives the offset of the calibration data in
- * this bytes stream for each sensor.
-- *
-- * Each thermal controller can handle up to 4 sensors max, we don't
-- * care if there are less as the array of calibration is sized to 4
-- * anyway. The unused sensor slot will be zeroed.
- */
- static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
- const struct lvts_ctrl_data *lvts_ctrl_data,
-@@ -1165,7 +1169,7 @@ static int lvts_remove(struct platform_d
- return 0;
- }
-
--static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = {
-+static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
- {
- .cal_offset = { 0x04, 0x07 },
- .lvts_sensor = {
-@@ -1200,13 +1204,63 @@ static const struct lvts_ctrl_data mt819
- }
- };
-
-+static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
-+ {
-+ .cal_offset = { 0x25, 0x28 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8195_AP_VPU0 },
-+ { .dt_id = MT8195_AP_VPU1 }
-+ },
-+ .num_lvts_sensor = 2,
-+ .offset = 0x0,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+ },
-+ {
-+ .cal_offset = { 0x2e, 0x31 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8195_AP_GPU0 },
-+ { .dt_id = MT8195_AP_GPU1 }
-+ },
-+ .num_lvts_sensor = 2,
-+ .offset = 0x100,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+ },
-+ {
-+ .cal_offset = { 0x37, 0x3a, 0x3d },
-+ .lvts_sensor = {
-+ { .dt_id = MT8195_AP_VDEC },
-+ { .dt_id = MT8195_AP_IMG },
-+ { .dt_id = MT8195_AP_INFRA },
-+ },
-+ .num_lvts_sensor = 3,
-+ .offset = 0x200,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+ },
-+ {
-+ .cal_offset = { 0x43, 0x46 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8195_AP_CAM0 },
-+ { .dt_id = MT8195_AP_CAM1 }
-+ },
-+ .num_lvts_sensor = 2,
-+ .offset = 0x300,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
-+ }
-+};
-+
- static const struct lvts_data mt8195_lvts_mcu_data = {
-- .lvts_ctrl = mt8195_lvts_data_ctrl,
-- .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_data_ctrl),
-+ .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
-+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
-+};
-+
-+static const struct lvts_data mt8195_lvts_ap_data = {
-+ .lvts_ctrl = mt8195_lvts_ap_data_ctrl,
-+ .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
- };
-
- static const struct of_device_id lvts_of_match[] = {
- { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
-+ { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
- {},
- };
- MODULE_DEVICE_TABLE(of, lvts_of_match);
+++ /dev/null
-From 7105a86760bd9e4d107075cefc75016b693a5542 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Wed, 19 Apr 2023 08:11:45 +0200
-Subject: [PATCH 16/42] Revert "thermal/drivers/mediatek: Add delay after
- thermal banks initialization"
-
-Some more testing revealed that this commit introduces a regression on some
-MT8173 Chromebooks and at least on one MT6795 Sony Xperia M5 smartphone due
-to the delay being apparently variable and machine specific.
-
-Another solution would be to delay for a bit more (~70ms) but this is not
-feasible for two reasons: first of all, we're adding an even bigger delay
-in a probe function; second, some machines need less, some may need even
-more, making the msleep at probe solution highly suboptimal.
-
-This reverts commit 10debf8c2da8011c8009dd4b3f6d0ab85891c81b.
-
-Fixes: 10debf8c2da8 ("thermal/drivers/mediatek: Add delay after thermal banks initialization")
-Reported-by: "kernelci.org bot" <bot@kernelci.org>
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230419061146.22246-2-angelogioacchino.delregno@collabora.com
----
- drivers/thermal/mediatek/auxadc_thermal.c | 11 ++++++++---
- 1 file changed, 8 insertions(+), 3 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -816,6 +816,14 @@ static int mtk_thermal_bank_temperature(
- mt, conf->bank_data[bank->id].sensors[i], raw);
-
-
-+ /*
-+ * The first read of a sensor often contains very high bogus
-+ * temperature value. Filter these out so that the system does
-+ * not immediately shut down.
-+ */
-+ if (temp > 200000)
-+ temp = 0;
-+
- if (temp > max)
- max = temp;
- }
-@@ -1273,9 +1281,6 @@ static int mtk_thermal_probe(struct plat
-
- platform_set_drvdata(pdev, mt);
-
-- /* Delay for thermal banks to be ready */
-- msleep(30);
--
- tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
- &mtk_thermal_ops);
- if (IS_ERR(tzdev)) {
+++ /dev/null
-From 681b652c9dfc4037d4a55b2733e091a4e1a5de18 Mon Sep 17 00:00:00 2001
-From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Date: Wed, 19 Apr 2023 08:11:46 +0200
-Subject: [PATCH 17/42] thermal/drivers/mediatek: Add temperature constraints
- to validate read
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The AUXADC thermal v1 allows reading temperature range between -20°C to
-150°C and any value out of this range is invalid.
-
-Add new definitions for MT8173_TEMP_{MIN_MAX} and a new small helper
-mtk_thermal_temp_is_valid() to check if new readings are in range: if
-not, we tell to the API that the reading is invalid by returning
-THERMAL_TEMP_INVALID.
-
-It was chosen to introduce the helper function because, even though this
-temperature range is realistically ok for all, it comes from a downstream
-kernel driver for version 1, but here we also support v2 and v3 which may
-may have wider constraints.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230419061146.22246-3-angelogioacchino.delregno@collabora.com
----
- drivers/thermal/mediatek/auxadc_thermal.c | 24 +++++++++++++++++------
- 1 file changed, 18 insertions(+), 6 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -116,6 +116,10 @@
- /* The calibration coefficient of sensor */
- #define MT8173_CALIBRATION 165
-
-+/* Valid temperatures range */
-+#define MT8173_TEMP_MIN -20000
-+#define MT8173_TEMP_MAX 150000
-+
- /*
- * Layout of the fuses providing the calibration data
- * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
-@@ -689,6 +693,11 @@ static const struct mtk_thermal_data mt7
- .version = MTK_THERMAL_V3,
- };
-
-+static bool mtk_thermal_temp_is_valid(int temp)
-+{
-+ return (temp >= MT8173_TEMP_MIN) && (temp <= MT8173_TEMP_MAX);
-+}
-+
- /**
- * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
- * @mt: The thermal controller
-@@ -815,14 +824,17 @@ static int mtk_thermal_bank_temperature(
- temp = mt->raw_to_mcelsius(
- mt, conf->bank_data[bank->id].sensors[i], raw);
-
--
- /*
-- * The first read of a sensor often contains very high bogus
-- * temperature value. Filter these out so that the system does
-- * not immediately shut down.
-+ * Depending on the filt/sen intervals and ADC polling time,
-+ * we may need up to 60 milliseconds after initialization: this
-+ * will result in the first reading containing an out of range
-+ * temperature value.
-+ * Validate the reading to both address the aforementioned issue
-+ * and to eventually avoid bogus readings during runtime in the
-+ * event that the AUXADC gets unstable due to high EMI, etc.
- */
-- if (temp > 200000)
-- temp = 0;
-+ if (!mtk_thermal_temp_is_valid(temp))
-+ temp = THERMAL_TEMP_INVALID;
-
- if (temp > max)
- max = temp;
+++ /dev/null
-From 458fa1d508de3f17e49d974a0158d9aeff273a58 Mon Sep 17 00:00:00 2001
-From: Kang Chen <void0red@hust.edu.cn>
-Date: Wed, 19 Apr 2023 10:07:48 +0800
-Subject: [PATCH 18/42] thermal/drivers/mediatek: Use devm_of_iomap to avoid
- resource leak in mtk_thermal_probe
-
-Smatch reports:
-1. mtk_thermal_probe() warn: 'apmixed_base' from of_iomap() not released.
-2. mtk_thermal_probe() warn: 'auxadc_base' from of_iomap() not released.
-
-The original code forgets to release iomap resource when handling errors,
-fix it by switch to devm_of_iomap.
-
-Fixes: 89945047b166 ("thermal: mediatek: Add tsensor support for V2 thermal system")
-Signed-off-by: Kang Chen <void0red@hust.edu.cn>
-Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230419020749.621257-1-void0red@hust.edu.cn
----
- drivers/thermal/mediatek/auxadc_thermal.c | 14 ++++++++++++--
- 1 file changed, 12 insertions(+), 2 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1232,7 +1232,12 @@ static int mtk_thermal_probe(struct plat
- return -ENODEV;
- }
-
-- auxadc_base = of_iomap(auxadc, 0);
-+ auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL);
-+ if (IS_ERR(auxadc_base)) {
-+ of_node_put(auxadc);
-+ return PTR_ERR(auxadc_base);
-+ }
-+
- auxadc_phys_base = of_get_phys_base(auxadc);
-
- of_node_put(auxadc);
-@@ -1248,7 +1253,12 @@ static int mtk_thermal_probe(struct plat
- return -ENODEV;
- }
-
-- apmixed_base = of_iomap(apmixedsys, 0);
-+ apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL);
-+ if (IS_ERR(apmixed_base)) {
-+ of_node_put(apmixedsys);
-+ return PTR_ERR(apmixed_base);
-+ }
-+
- apmixed_phys_base = of_get_phys_base(apmixedsys);
-
- of_node_put(apmixedsys);
+++ /dev/null
-From 227d1856924ec00a4f5bdf5afcf77bc7f3f04e86 Mon Sep 17 00:00:00 2001
-From: Kang Chen <void0red@hust.edu.cn>
-Date: Wed, 19 Apr 2023 10:07:49 +0800
-Subject: [PATCH 19/42] thermal/drivers/mediatek: Change clk_prepare_enable to
- devm_clk_get_enabled in mtk_thermal_probe
-
-Use devm_clk_get_enabled to do automatic resource management.
-Meanwhile, remove error handling labels in the probe function and
-the whole remove function.
-
-Signed-off-by: Kang Chen <void0red@hust.edu.cn>
-Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230419020749.621257-2-void0red@hust.edu.cn
----
- drivers/thermal/mediatek/auxadc_thermal.c | 44 +++++------------------
- 1 file changed, 9 insertions(+), 35 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1206,14 +1206,6 @@ static int mtk_thermal_probe(struct plat
-
- mt->conf = of_device_get_match_data(&pdev->dev);
-
-- mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
-- if (IS_ERR(mt->clk_peri_therm))
-- return PTR_ERR(mt->clk_peri_therm);
--
-- mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
-- if (IS_ERR(mt->clk_auxadc))
-- return PTR_ERR(mt->clk_auxadc);
--
- mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
- if (IS_ERR(mt->thermal_base))
- return PTR_ERR(mt->thermal_base);
-@@ -1272,16 +1264,18 @@ static int mtk_thermal_probe(struct plat
- if (ret)
- return ret;
-
-- ret = clk_prepare_enable(mt->clk_auxadc);
-- if (ret) {
-+ mt->clk_auxadc = devm_clk_get_enabled(&pdev->dev, "auxadc");
-+ if (IS_ERR(mt->clk_auxadc)) {
-+ ret = PTR_ERR(mt->clk_auxadc);
- dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
- return ret;
- }
-
-- ret = clk_prepare_enable(mt->clk_peri_therm);
-- if (ret) {
-+ mt->clk_peri_therm = devm_clk_get_enabled(&pdev->dev, "therm");
-+ if (IS_ERR(mt->clk_peri_therm)) {
-+ ret = PTR_ERR(mt->clk_peri_therm);
- dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
-- goto err_disable_clk_auxadc;
-+ return ret;
- }
-
- mtk_thermal_turn_on_buffer(mt, apmixed_base);
-@@ -1305,38 +1299,18 @@ static int mtk_thermal_probe(struct plat
-
- tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
- &mtk_thermal_ops);
-- if (IS_ERR(tzdev)) {
-- ret = PTR_ERR(tzdev);
-- goto err_disable_clk_peri_therm;
-- }
-+ if (IS_ERR(tzdev))
-+ return PTR_ERR(tzdev);
-
- ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
- if (ret)
- dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
-
- return 0;
--
--err_disable_clk_peri_therm:
-- clk_disable_unprepare(mt->clk_peri_therm);
--err_disable_clk_auxadc:
-- clk_disable_unprepare(mt->clk_auxadc);
--
-- return ret;
--}
--
--static int mtk_thermal_remove(struct platform_device *pdev)
--{
-- struct mtk_thermal *mt = platform_get_drvdata(pdev);
--
-- clk_disable_unprepare(mt->clk_peri_therm);
-- clk_disable_unprepare(mt->clk_auxadc);
--
-- return 0;
- }
-
- static struct platform_driver mtk_thermal_driver = {
- .probe = mtk_thermal_probe,
-- .remove = mtk_thermal_remove,
- .driver = {
- .name = "mtk-thermal",
- .of_match_table = mtk_thermal_of_match,
+++ /dev/null
-From 655fe2533ac05323a07c19ba079bf2064e7741af Mon Sep 17 00:00:00 2001
-From: Rob Herring <robh@kernel.org>
-Date: Sun, 19 Mar 2023 11:32:31 -0500
-Subject: [PATCH 20/42] thermal/drivers/mediatek: Use of_address_to_resource()
-
-Replace of_get_address() and of_translate_address() calls with single
-call to of_address_to_resource().
-
-Signed-off-by: Rob Herring <robh@kernel.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230319163231.226738-1-robh@kernel.org
----
- drivers/thermal/mediatek/auxadc_thermal.c | 8 +++-----
- 1 file changed, 3 insertions(+), 5 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -979,14 +979,12 @@ static void mtk_thermal_init_bank(struct
-
- static u64 of_get_phys_base(struct device_node *np)
- {
-- u64 size64;
-- const __be32 *regaddr_p;
-+ struct resource res;
-
-- regaddr_p = of_get_address(np, 0, &size64, NULL);
-- if (!regaddr_p)
-+ if (of_address_to_resource(np, 0, &res))
- return OF_BAD_ADDR;
-
-- return of_translate_address(np, regaddr_p);
-+ return res.start;
- }
-
- static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
+++ /dev/null
-From 2c380d07215e6fce3ac66cc5af059bc2c2a69f7a Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ricardo=20Ca=C3=B1uelo?= <ricardo.canuelo@collabora.com>
-Date: Thu, 25 May 2023 14:18:11 +0200
-Subject: [PATCH 21/42] Revert "thermal/drivers/mediatek: Use devm_of_iomap to
- avoid resource leak in mtk_thermal_probe"
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This reverts commit f05c7b7d9ea9477fcc388476c6f4ade8c66d2d26.
-
-That change was causing a regression in the generic-adc-thermal-probed
-bootrr test as reported in the kernelci-results list [1].
-A proper rework will take longer, so revert it for now.
-
-[1] https://groups.io/g/kernelci-results/message/42660
-
-Fixes: f05c7b7d9ea9 ("thermal/drivers/mediatek: Use devm_of_iomap to avoid resource leak in mtk_thermal_probe")
-Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
-Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230525121811.3360268-1-ricardo.canuelo@collabora.com
----
- drivers/thermal/mediatek/auxadc_thermal.c | 14 ++------------
- 1 file changed, 2 insertions(+), 12 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1222,12 +1222,7 @@ static int mtk_thermal_probe(struct plat
- return -ENODEV;
- }
-
-- auxadc_base = devm_of_iomap(&pdev->dev, auxadc, 0, NULL);
-- if (IS_ERR(auxadc_base)) {
-- of_node_put(auxadc);
-- return PTR_ERR(auxadc_base);
-- }
--
-+ auxadc_base = of_iomap(auxadc, 0);
- auxadc_phys_base = of_get_phys_base(auxadc);
-
- of_node_put(auxadc);
-@@ -1243,12 +1238,7 @@ static int mtk_thermal_probe(struct plat
- return -ENODEV;
- }
-
-- apmixed_base = devm_of_iomap(&pdev->dev, apmixedsys, 0, NULL);
-- if (IS_ERR(apmixed_base)) {
-- of_node_put(apmixedsys);
-- return PTR_ERR(apmixed_base);
-- }
--
-+ apmixed_base = of_iomap(apmixedsys, 0);
- apmixed_phys_base = of_get_phys_base(apmixedsys);
-
- of_node_put(apmixedsys);
+++ /dev/null
-From 496f4b08981d8a788ad5a2073fa1c65a2af1862b Mon Sep 17 00:00:00 2001
-From: Chen-Yu Tsai <wenst@chromium.org>
-Date: Tue, 13 Jun 2023 17:13:16 +0800
-Subject: [PATCH 22/42] thermal/drivers/mediatek/lvts_thermal: Register thermal
- zones as hwmon sensors
-
-Register thermal zones as hwmon sensors to let userspace read
-temperatures using standard hwmon interface.
-
-Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230613091317.1691247-1-wenst@chromium.org
----
- drivers/thermal/mediatek/lvts_thermal.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -19,6 +19,8 @@
- #include <linux/thermal.h>
- #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
-
-+#include "../thermal_hwmon.h"
-+
- #define LVTS_MONCTL0(__base) (__base + 0x0000)
- #define LVTS_MONCTL1(__base) (__base + 0x0004)
- #define LVTS_MONCTL2(__base) (__base + 0x0008)
-@@ -996,6 +998,9 @@ static int lvts_ctrl_start(struct device
- return PTR_ERR(tz);
- }
-
-+ if (devm_thermal_add_hwmon_sysfs(dev, tz))
-+ dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id);
-+
- /*
- * The thermal zone pointer will be needed in the
- * interrupt handler, we store it in the sensor
+++ /dev/null
-From 885b9768ce2a66ed5d250822aed53d5114c895da Mon Sep 17 00:00:00 2001
-From: Yangtao Li <frank.li@vivo.com>
-Date: Tue, 20 Jun 2023 17:07:31 +0800
-Subject: [PATCH 23/42] thermal/drivers/mediatek/lvts_thermal: Remove redundant
- msg in lvts_ctrl_start()
-
-The upper-layer devm_thermal_add_hwmon_sysfs() function can directly
-print error information.
-
-Signed-off-by: Yangtao Li <frank.li@vivo.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230620090732.50025-10-frank.li@vivo.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -998,8 +998,7 @@ static int lvts_ctrl_start(struct device
- return PTR_ERR(tz);
- }
-
-- if (devm_thermal_add_hwmon_sysfs(dev, tz))
-- dev_warn(dev, "zone %d: Failed to add hwmon sysfs attributes\n", dt_id);
-+ devm_thermal_add_hwmon_sysfs(dev, tz);
-
- /*
- * The thermal zone pointer will be needed in the
+++ /dev/null
-From 27b389d9f62c2174f95fe4002b11e77d4cb3ce80 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:32 -0400
-Subject: [PATCH 25/42] thermal/drivers/mediatek/lvts_thermal: Handle IRQ on
- all controllers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There is a single IRQ handler for each LVTS thermal domain, and it is
-supposed to check each of its underlying controllers for the origin of
-the interrupt and clear its status. However due to a typo, only the
-first controller was ever being handled, which resulted in the interrupt
-never being cleared when it happened on the other controllers. Add the
-missing index so interrupts are handled for all controllers.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-2-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -451,7 +451,7 @@ static irqreturn_t lvts_irq_handler(int
-
- for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
-
-- aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl);
-+ aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]);
- if (aux != IRQ_HANDLED)
- continue;
-
+++ /dev/null
-From 6d827142643ee10c13ff9a1d90f38fb399aa9fff Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:33 -0400
-Subject: [PATCH 26/42] thermal/drivers/mediatek/lvts_thermal: Honor sensors in
- immediate mode
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Each controller can be configured to operate on immediate or filtered
-mode. On filtered mode, the sensors are enabled by setting the
-corresponding bits in MONCTL0, while on immediate mode, by setting
-MSRCTL1.
-
-Previously, the code would set MSRCTL1 for all four sensors when
-configured to immediate mode, but given that the controller might not
-have all four sensors connected, this would cause interrupts to trigger
-for non-existent sensors. Fix this by handling the MSRCTL1 register
-analogously to the MONCTL0: only enable the sensors that were declared.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-3-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 57 ++++++++++++++-----------
- 1 file changed, 33 insertions(+), 24 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -897,24 +897,6 @@ static int lvts_ctrl_configure(struct de
- writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
-
- /*
-- * LVTS_MSRCTL1 : Measurement control
-- *
-- * Bits:
-- *
-- * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
-- * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
-- * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
-- * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
-- *
-- * That configuration will ignore the filtering and the delays
-- * introduced below in MONCTL1 and MONCTL2
-- */
-- if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
-- value = BIT(9) | BIT(6) | BIT(5) | BIT(4);
-- writel(value, LVTS_MSRCTL1(lvts_ctrl->base));
-- }
--
-- /*
- * LVTS_MONCTL1 : Period unit and group interval configuration
- *
- * The clock source of LVTS thermal controller is 26MHz.
-@@ -979,6 +961,15 @@ static int lvts_ctrl_start(struct device
- struct thermal_zone_device *tz;
- u32 sensor_map = 0;
- int i;
-+ /*
-+ * Bitmaps to enable each sensor on immediate and filtered modes, as
-+ * described in MSRCTL1 and MONCTL0 registers below, respectively.
-+ */
-+ u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) };
-+ u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
-+
-+ u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ?
-+ sensor_imm_bitmap : sensor_filt_bitmap;
-
- for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) {
-
-@@ -1016,20 +1007,38 @@ static int lvts_ctrl_start(struct device
- * map, so we can enable the temperature monitoring in
- * the hardware thermal controller.
- */
-- sensor_map |= BIT(i);
-+ sensor_map |= sensor_bitmap[i];
- }
-
- /*
-- * Bits:
-- * 9: Single point access flow
-- * 0-3: Enable sensing point 0-3
-- *
- * The initialization of the thermal zones give us
- * which sensor point to enable. If any thermal zone
- * was not described in the device tree, it won't be
- * enabled here in the sensor map.
- */
-- writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
-+ if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
-+ /*
-+ * LVTS_MSRCTL1 : Measurement control
-+ *
-+ * Bits:
-+ *
-+ * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
-+ * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
-+ * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
-+ * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
-+ *
-+ * That configuration will ignore the filtering and the delays
-+ * introduced in MONCTL1 and MONCTL2
-+ */
-+ writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base));
-+ } else {
-+ /*
-+ * Bits:
-+ * 9: Single point access flow
-+ * 0-3: Enable sensing point 0-3
-+ */
-+ writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
-+ }
-
- return 0;
- }
+++ /dev/null
-From 93bb11dd19bdcc1fc97c7ceababd0db9fde128ad Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:34 -0400
-Subject: [PATCH 27/42] thermal/drivers/mediatek/lvts_thermal: Use offset
- threshold for IRQ
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There are two kinds of temperature monitoring interrupts available:
-* High Offset, Low Offset
-* Hot, Hot to normal, Cold
-
-The code currently uses the hot/h2n/cold interrupts, however in a way
-that doesn't work: the cold threshold is left uninitialized, which
-prevents the other thresholds from ever triggering, and the h2n
-interrupt is used as the lower threshold, which prevents the hot
-interrupt from triggering again after the thresholds are updated by the
-thermal framework, since a hot interrupt can only trigger again after
-the hot to normal interrupt has been triggered.
-
-But better yet than addressing those issues, is to use the high/low
-offset interrupts instead. This way only two thresholds need to be
-managed, which have a simpler state machine, making them a better match
-to the thermal framework's high and low thresholds.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-4-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -298,9 +298,9 @@ static int lvts_set_trips(struct thermal
- u32 raw_high = lvts_temp_to_raw(high);
-
- /*
-- * Hot to normal temperature threshold
-+ * Low offset temperature threshold
- *
-- * LVTS_H2NTHRE
-+ * LVTS_OFFSETL
- *
- * Bits:
- *
-@@ -309,13 +309,13 @@ static int lvts_set_trips(struct thermal
- if (low != -INT_MAX) {
- pr_debug("%s: Setting low limit temperature interrupt: %d\n",
- thermal_zone_device_type(tz), low);
-- writel(raw_low, LVTS_H2NTHRE(base));
-+ writel(raw_low, LVTS_OFFSETL(base));
- }
-
- /*
-- * Hot temperature threshold
-+ * High offset temperature threshold
- *
-- * LVTS_HTHRE
-+ * LVTS_OFFSETH
- *
- * Bits:
- *
-@@ -323,7 +323,7 @@ static int lvts_set_trips(struct thermal
- */
- pr_debug("%s: Setting high limit temperature interrupt: %d\n",
- thermal_zone_device_type(tz), high);
-- writel(raw_high, LVTS_HTHRE(base));
-+ writel(raw_high, LVTS_OFFSETH(base));
-
- return 0;
- }
+++ /dev/null
-From 8f8cab9d3e90acf1db278ef44ad05f10aefb973f Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:35 -0400
-Subject: [PATCH 28/42] thermal/drivers/mediatek/lvts_thermal: Disable
- undesired interrupts
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Out of the many interrupts supported by the hardware, the only ones of
-interest to the driver currently are:
-* The temperature went over the high offset threshold, for any of the
- sensors
-* The temperature went below the low offset threshold, for any of the
- sensors
-* The temperature went over the stage3 threshold
-
-These are the only thresholds configured by the driver through the
-OFFSETH, OFFSETL, and PROTTC registers, respectively.
-
-The current interrupt mask in LVTS_MONINT_CONF, enables many more
-interrupts, including data ready on sensors for both filtered and
-immediate mode. These are not only not handled by the driver, but they
-are also triggered too often, causing unneeded overhead. Disable these
-unnecessary interrupts.
-
-The meaning of each bit can be seen in the comment describing
-LVTS_MONINTST in the IRQ handler.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-5-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -65,7 +65,7 @@
- #define LVTS_HW_FILTER 0x2
- #define LVTS_TSSEL_CONF 0x13121110
- #define LVTS_CALSCALE_CONF 0x300
--#define LVTS_MONINT_CONF 0x9FBF7BDE
-+#define LVTS_MONINT_CONF 0x8300318C
-
- #define LVTS_INT_SENSOR0 0x0009001F
- #define LVTS_INT_SENSOR1 0x001203E0
+++ /dev/null
-From bd1ccf9408e6155564530af5e09b53ae497fe332 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:36 -0400
-Subject: [PATCH 29/42] thermal/drivers/mediatek/lvts_thermal: Don't leave
- threshold zeroed
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The thermal framework might leave the low threshold unset if there
-aren't any lower trip points. This leaves the register zeroed, which
-translates to a very high temperature for the low threshold. The
-interrupt for this threshold is then immediately triggered, and the
-state machine gets stuck, preventing any other temperature monitoring
-interrupts to ever trigger.
-
-(The same happens by not setting the Cold or Hot to Normal thresholds
-when using those)
-
-Set the unused threshold to a valid low value. This value was chosen so
-that for any valid golden temperature read from the efuse, when the
-value is converted to raw and back again to milliCelsius, the result
-doesn't underflow.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-6-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -83,6 +83,8 @@
-
- #define LVTS_HW_SHUTDOWN_MT8195 105000
-
-+#define LVTS_MINIMUM_THRESHOLD 20000
-+
- static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
- static int coeff_b = LVTS_COEFF_B;
-
-@@ -294,7 +296,7 @@ static int lvts_set_trips(struct thermal
- {
- struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
- void __iomem *base = lvts_sensor->base;
-- u32 raw_low = lvts_temp_to_raw(low);
-+ u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
- u32 raw_high = lvts_temp_to_raw(high);
-
- /*
-@@ -306,11 +308,9 @@ static int lvts_set_trips(struct thermal
- *
- * 14-0 : Raw temperature for threshold
- */
-- if (low != -INT_MAX) {
-- pr_debug("%s: Setting low limit temperature interrupt: %d\n",
-- thermal_zone_device_type(tz), low);
-- writel(raw_low, LVTS_OFFSETL(base));
-- }
-+ pr_debug("%s: Setting low limit temperature interrupt: %d\n",
-+ thermal_zone_device_type(tz), low);
-+ writel(raw_low, LVTS_OFFSETL(base));
-
- /*
- * High offset temperature threshold
+++ /dev/null
-From d4dd09968cab3249e6148e1c3fccb51824edb411 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 6 Jul 2023 11:37:37 -0400
-Subject: [PATCH 30/42] thermal/drivers/mediatek/lvts_thermal: Manage threshold
- between sensors
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Each LVTS thermal controller can have up to four sensors, each capable
-of triggering its own interrupt when its measured temperature crosses
-the configured threshold. The threshold for each sensor is handled
-separately by the thermal framework, since each one is registered with
-its own thermal zone and trips. However, the temperature thresholds are
-configured on the controller, and therefore are shared between all
-sensors on that controller.
-
-When the temperature measured by the sensors is different enough to
-cause the thermal framework to configure different thresholds for each
-one, interrupts start triggering on sensors outside the last threshold
-configured.
-
-To address the issue, track the thresholds required by each sensor and
-only actually set the highest one in the hardware, and disable
-interrupts for all sensors outside the current configured range.
-
-Fixes: f5f633b18234 ("thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver")
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230706153823.201943-7-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 69 +++++++++++++++++++++++++
- 1 file changed, 69 insertions(+)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -67,6 +67,11 @@
- #define LVTS_CALSCALE_CONF 0x300
- #define LVTS_MONINT_CONF 0x8300318C
-
-+#define LVTS_MONINT_OFFSET_SENSOR0 0xC
-+#define LVTS_MONINT_OFFSET_SENSOR1 0x180
-+#define LVTS_MONINT_OFFSET_SENSOR2 0x3000
-+#define LVTS_MONINT_OFFSET_SENSOR3 0x3000000
-+
- #define LVTS_INT_SENSOR0 0x0009001F
- #define LVTS_INT_SENSOR1 0x001203E0
- #define LVTS_INT_SENSOR2 0x00247C00
-@@ -112,6 +117,8 @@ struct lvts_sensor {
- void __iomem *base;
- int id;
- int dt_id;
-+ int low_thresh;
-+ int high_thresh;
- };
-
- struct lvts_ctrl {
-@@ -121,6 +128,8 @@ struct lvts_ctrl {
- int num_lvts_sensor;
- int mode;
- void __iomem *base;
-+ int low_thresh;
-+ int high_thresh;
- };
-
- struct lvts_domain {
-@@ -292,12 +301,66 @@ static int lvts_get_temp(struct thermal_
- return 0;
- }
-
-+static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl)
-+{
-+ u32 masks[] = {
-+ LVTS_MONINT_OFFSET_SENSOR0,
-+ LVTS_MONINT_OFFSET_SENSOR1,
-+ LVTS_MONINT_OFFSET_SENSOR2,
-+ LVTS_MONINT_OFFSET_SENSOR3,
-+ };
-+ u32 value = 0;
-+ int i;
-+
-+ value = readl(LVTS_MONINT(lvts_ctrl->base));
-+
-+ for (i = 0; i < ARRAY_SIZE(masks); i++) {
-+ if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
-+ && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
-+ value |= masks[i];
-+ else
-+ value &= ~masks[i];
-+ }
-+
-+ writel(value, LVTS_MONINT(lvts_ctrl->base));
-+}
-+
-+static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
-+{
-+ int i;
-+
-+ if (high > lvts_ctrl->high_thresh)
-+ return true;
-+
-+ for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++)
-+ if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
-+ && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
-+ return false;
-+
-+ return true;
-+}
-+
- static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
- {
- struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
-+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
- void __iomem *base = lvts_sensor->base;
- u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
- u32 raw_high = lvts_temp_to_raw(high);
-+ bool should_update_thresh;
-+
-+ lvts_sensor->low_thresh = low;
-+ lvts_sensor->high_thresh = high;
-+
-+ should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high);
-+ if (should_update_thresh) {
-+ lvts_ctrl->high_thresh = high;
-+ lvts_ctrl->low_thresh = low;
-+ }
-+ lvts_update_irq_mask(lvts_ctrl);
-+
-+ if (!should_update_thresh)
-+ return 0;
-
- /*
- * Low offset temperature threshold
-@@ -521,6 +584,9 @@ static int lvts_sensor_init(struct devic
- */
- lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
- imm_regs[i] : msr_regs[i];
-+
-+ lvts_sensor[i].low_thresh = INT_MIN;
-+ lvts_sensor[i].high_thresh = INT_MIN;
- };
-
- lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor;
-@@ -688,6 +754,9 @@ static int lvts_ctrl_init(struct device
- */
- lvts_ctrl[i].hw_tshut_raw_temp =
- lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
-+
-+ lvts_ctrl[i].low_thresh = INT_MIN;
-+ lvts_ctrl[i].high_thresh = INT_MIN;
- }
-
- /*
+++ /dev/null
-From 5af4904adc8b840987000724977c13c706d3b7d8 Mon Sep 17 00:00:00 2001
-From: Minjie Du <duminjie@vivo.com>
-Date: Thu, 13 Jul 2023 12:24:12 +0800
-Subject: [PATCH 31/42] thermal/drivers/mediatek/lvts: Fix parameter check in
- lvts_debugfs_init()
-
-The documentation says "If an error occurs, ERR_PTR(-ERROR) will be
-returned" but the current code checks against a NULL pointer returned.
-
-Fix this by checking if IS_ERR().
-
-Signed-off-by: Minjie Du <duminjie@vivo.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230713042413.2519-1-duminjie@vivo.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -201,7 +201,7 @@ static int lvts_debugfs_init(struct devi
- int i;
-
- lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
-- if (!lvts_td->dom_dentry)
-+ if (IS_ERR(lvts_td->dom_dentry))
- return 0;
-
- for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
+++ /dev/null
-From 6186be80317d1dbda34d35c06c084a083938f2d3 Mon Sep 17 00:00:00 2001
-From: Chen Jiahao <chenjiahao16@huawei.com>
-Date: Wed, 2 Aug 2023 17:45:27 +0800
-Subject: [PATCH 32/42] thermal/drivers/mediatek: Clean up redundant
- dev_err_probe()
-
-Referring to platform_get_irq()'s definition, the return value has
-already been checked if ret < 0, and printed via dev_err_probe().
-Calling dev_err_probe() one more time outside platform_get_irq()
-is obviously redundant.
-
-Removing dev_err_probe() outside platform_get_irq() to clean up
-above problem.
-
-Signed-off-by: Chen Jiahao <chenjiahao16@huawei.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230802094527.988842-1-chenjiahao16@huawei.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -1216,7 +1216,7 @@ static int lvts_probe(struct platform_de
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
-- return dev_err_probe(dev, irq, "No irq resource\n");
-+ return irq;
-
- ret = lvts_domain_init(dev, lvts_td, lvts_data);
- if (ret)
+++ /dev/null
-From c2ab54ab0425388e65901a7af2fbf69ead968708 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?=
- <nfraprado@collabora.com>
-Date: Thu, 13 Jul 2023 11:42:37 -0400
-Subject: [PATCH 33/42] thermal/drivers/mediatek/lvts_thermal: Make readings
- valid in filtered mode
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Currently, when a controller is configured to use filtered mode, thermal
-readings are valid only about 30% of the time.
-
-Upon testing, it was noticed that lowering any of the interval settings
-resulted in an improved rate of valid data. The same was observed when
-decreasing the number of samples for each sensor (which also results in
-quicker measurements).
-
-Retrying the read with a timeout longer than the time it takes to
-resample (about 344us with these settings and 4 sensors) also improves
-the rate.
-
-Lower all timing settings to the minimum, configure the filtering to
-single sample, and poll the measurement register for at least one period
-to improve the data validity on filtered mode. With these changes in
-place, out of 100000 reads, a single one failed, ie 99.999% of the data
-was valid.
-
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Tested-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230713154743.611870-1-nfraprado@collabora.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 19 ++++++++++++-------
- 1 file changed, 12 insertions(+), 7 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -58,11 +58,11 @@
- #define LVTS_PROTTC(__base) (__base + 0x00CC)
- #define LVTS_CLKEN(__base) (__base + 0x00E4)
-
--#define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38))
--#define LVTS_GROUP_INTERVAL 1
--#define LVTS_FILTER_INTERVAL 1
--#define LVTS_SENSOR_INTERVAL 1
--#define LVTS_HW_FILTER 0x2
-+#define LVTS_PERIOD_UNIT 0
-+#define LVTS_GROUP_INTERVAL 0
-+#define LVTS_FILTER_INTERVAL 0
-+#define LVTS_SENSOR_INTERVAL 0
-+#define LVTS_HW_FILTER 0x0
- #define LVTS_TSSEL_CONF 0x13121110
- #define LVTS_CALSCALE_CONF 0x300
- #define LVTS_MONINT_CONF 0x8300318C
-@@ -86,6 +86,9 @@
- #define LVTS_MSR_IMMEDIATE_MODE 0
- #define LVTS_MSR_FILTERED_MODE 1
-
-+#define LVTS_MSR_READ_TIMEOUT_US 400
-+#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
-+
- #define LVTS_HW_SHUTDOWN_MT8195 105000
-
- #define LVTS_MINIMUM_THRESHOLD 20000
-@@ -268,6 +271,7 @@ static int lvts_get_temp(struct thermal_
- struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
- void __iomem *msr = lvts_sensor->msr;
- u32 value;
-+ int rc;
-
- /*
- * Measurement registers:
-@@ -280,7 +284,8 @@ static int lvts_get_temp(struct thermal_
- * 16 : Valid temperature
- * 15-0 : Raw temperature
- */
-- value = readl(msr);
-+ rc = readl_poll_timeout(msr, value, value & BIT(16),
-+ LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US);
-
- /*
- * As the thermal zone temperature will read before the
-@@ -293,7 +298,7 @@ static int lvts_get_temp(struct thermal_
- * functionning temperature and directly jump to a system
- * shutdown.
- */
-- if (!(value & BIT(16)))
-+ if (rc)
- return -EAGAIN;
-
- *temp = lvts_raw_to_temp(value & 0xFFFF);
+++ /dev/null
-From c864ff9de3b225b43bb8e08dedb223632323e059 Mon Sep 17 00:00:00 2001
-From: Andrei Coardos <aboutphysycs@gmail.com>
-Date: Fri, 11 Aug 2023 22:28:47 +0300
-Subject: [PATCH 34/42] thermal/drivers/mediatek/auxadc_thermal: Removed call
- to platform_set_drvdata()
-
-This function call was found to be unnecessary as there is no equivalent
-platform_get_drvdata() call to access the private data of the driver. Also,
-the private data is defined in this driver, so there is no risk of it being
-accessed outside of this driver file.
-
-Signed-off-by: Andrei Coardos <aboutphysycs@gmail.com>
-Reviewed-by: Alexandru Ardelean <alex@shruggie.ro>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230811192847.3838-1-aboutphysycs@gmail.com
----
- drivers/thermal/mediatek/auxadc_thermal.c | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1283,8 +1283,6 @@ static int mtk_thermal_probe(struct plat
- mtk_thermal_init_bank(mt, i, apmixed_phys_base,
- auxadc_phys_base, ctrl_id);
-
-- platform_set_drvdata(pdev, mt);
--
- tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
- &mtk_thermal_ops);
- if (IS_ERR(tzdev))
+++ /dev/null
-From 6cf96078969ec00b873db99bae4e47001290685e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
-Date: Wed, 27 Sep 2023 21:37:23 +0200
-Subject: [PATCH 35/42] thermal: lvts: Convert to platform remove callback
- returning void
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The .remove() callback for a platform driver returns an int which makes
-many driver authors wrongly assume it's possible to do error handling by
-returning an error code. However the value returned is ignored (apart
-from emitting a warning) and this typically results in resource leaks.
-
-To improve here there is a quest to make the remove callback return
-void. In the first step of this quest all drivers are converted to
-.remove_new(), which already returns void. Eventually after all drivers
-are converted, .remove_new() will be renamed to .remove().
-
-Trivially convert this driver from always returning zero in the remove
-callback to the void returning variant.
-
-Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
-Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
----
- drivers/thermal/mediatek/lvts_thermal.c | 6 ++----
- 1 file changed, 2 insertions(+), 4 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -1241,7 +1241,7 @@ static int lvts_probe(struct platform_de
- return 0;
- }
-
--static int lvts_remove(struct platform_device *pdev)
-+static void lvts_remove(struct platform_device *pdev)
- {
- struct lvts_domain *lvts_td;
- int i;
-@@ -1252,8 +1252,6 @@ static int lvts_remove(struct platform_d
- lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
-
- lvts_debugfs_exit(lvts_td);
--
-- return 0;
- }
-
- static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
-@@ -1354,7 +1352,7 @@ MODULE_DEVICE_TABLE(of, lvts_of_match);
-
- static struct platform_driver lvts_driver = {
- .probe = lvts_probe,
-- .remove = lvts_remove,
-+ .remove_new = lvts_remove,
- .driver = {
- .name = "mtk-lvts-thermal",
- .of_match_table = lvts_of_match,
+++ /dev/null
-From 26cc18a3d6d9eac21c4f4b4bb96147b2c6617c86 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Fri, 22 Sep 2023 07:50:19 +0200
-Subject: [PATCH 36/42] thermal/drivers/mediatek/lvts_thermal: Make coeff
- configurable
-
-The upcoming mt7988 has different temperature coefficients so we
-cannot use constants in the functions lvts_golden_temp_init,
-lvts_golden_temp_init and lvts_raw_to_temp anymore.
-
-Add a field in the lvts_ctrl pointing to the lvts_data which now
-contains the soc-specific temperature coefficents.
-
-To make the code better readable, rename static int coeff_b to
-golden_temp_offset, COEFF_A to temp_factor and COEFF_B to temp_offset.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Tested-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230922055020.6436-4-linux@fw-web.de
----
- drivers/thermal/mediatek/lvts_thermal.c | 51 ++++++++++++++++---------
- 1 file changed, 34 insertions(+), 17 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -80,8 +80,8 @@
- #define LVTS_SENSOR_MAX 4
- #define LVTS_GOLDEN_TEMP_MAX 62
- #define LVTS_GOLDEN_TEMP_DEFAULT 50
--#define LVTS_COEFF_A -250460
--#define LVTS_COEFF_B 250460
-+#define LVTS_COEFF_A_MT8195 -250460
-+#define LVTS_COEFF_B_MT8195 250460
-
- #define LVTS_MSR_IMMEDIATE_MODE 0
- #define LVTS_MSR_FILTERED_MODE 1
-@@ -94,7 +94,7 @@
- #define LVTS_MINIMUM_THRESHOLD 20000
-
- static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
--static int coeff_b = LVTS_COEFF_B;
-+static int golden_temp_offset;
-
- struct lvts_sensor_data {
- int dt_id;
-@@ -112,6 +112,8 @@ struct lvts_ctrl_data {
- struct lvts_data {
- const struct lvts_ctrl_data *lvts_ctrl;
- int num_lvts_ctrl;
-+ int temp_factor;
-+ int temp_offset;
- };
-
- struct lvts_sensor {
-@@ -126,6 +128,7 @@ struct lvts_sensor {
-
- struct lvts_ctrl {
- struct lvts_sensor sensors[LVTS_SENSOR_MAX];
-+ const struct lvts_data *lvts_data;
- u32 calibration[LVTS_SENSOR_MAX];
- u32 hw_tshut_raw_temp;
- int num_lvts_sensor;
-@@ -247,21 +250,21 @@ static void lvts_debugfs_exit(struct lvt
-
- #endif
-
--static int lvts_raw_to_temp(u32 raw_temp)
-+static int lvts_raw_to_temp(u32 raw_temp, int temp_factor)
- {
- int temperature;
-
-- temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
-- temperature += coeff_b;
-+ temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14;
-+ temperature += golden_temp_offset;
-
- return temperature;
- }
-
--static u32 lvts_temp_to_raw(int temperature)
-+static u32 lvts_temp_to_raw(int temperature, int temp_factor)
- {
-- u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
-+ u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14;
-
-- raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
-+ raw_temp = div_s64(raw_temp, -temp_factor);
-
- return raw_temp;
- }
-@@ -269,6 +272,9 @@ static u32 lvts_temp_to_raw(int temperat
- static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
- {
- struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
-+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
-+ sensors[lvts_sensor->id]);
-+ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
- void __iomem *msr = lvts_sensor->msr;
- u32 value;
- int rc;
-@@ -301,7 +307,7 @@ static int lvts_get_temp(struct thermal_
- if (rc)
- return -EAGAIN;
-
-- *temp = lvts_raw_to_temp(value & 0xFFFF);
-+ *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor);
-
- return 0;
- }
-@@ -348,10 +354,13 @@ static bool lvts_should_update_thresh(st
- static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
- {
- struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
-- struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
-+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
-+ sensors[lvts_sensor->id]);
-+ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
- void __iomem *base = lvts_sensor->base;
-- u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
-- u32 raw_high = lvts_temp_to_raw(high);
-+ u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD,
-+ lvts_data->temp_factor);
-+ u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor);
- bool should_update_thresh;
-
- lvts_sensor->low_thresh = low;
-@@ -692,7 +701,7 @@ static int lvts_calibration_read(struct
- return 0;
- }
-
--static int lvts_golden_temp_init(struct device *dev, u32 *value)
-+static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset)
- {
- u32 gt;
-
-@@ -701,7 +710,7 @@ static int lvts_golden_temp_init(struct
- if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
- golden_temp = gt;
-
-- coeff_b = golden_temp * 500 + LVTS_COEFF_B;
-+ golden_temp_offset = golden_temp * 500 + temp_offset;
-
- return 0;
- }
-@@ -724,7 +733,7 @@ static int lvts_ctrl_init(struct device
- * The golden temp information is contained in the first chunk
- * of efuse data.
- */
-- ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
-+ ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset);
- if (ret)
- return ret;
-
-@@ -735,6 +744,7 @@ static int lvts_ctrl_init(struct device
- for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
-
- lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
-+ lvts_ctrl[i].lvts_data = lvts_data;
-
- ret = lvts_sensor_init(dev, &lvts_ctrl[i],
- &lvts_data->lvts_ctrl[i]);
-@@ -758,7 +768,8 @@ static int lvts_ctrl_init(struct device
- * after initializing the calibration.
- */
- lvts_ctrl[i].hw_tshut_raw_temp =
-- lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
-+ lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp,
-+ lvts_data->temp_factor);
-
- lvts_ctrl[i].low_thresh = INT_MIN;
- lvts_ctrl[i].high_thresh = INT_MIN;
-@@ -1223,6 +1234,8 @@ static int lvts_probe(struct platform_de
- if (irq < 0)
- return irq;
-
-+ golden_temp_offset = lvts_data->temp_offset;
-+
- ret = lvts_domain_init(dev, lvts_td, lvts_data);
- if (ret)
- return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
-@@ -1336,11 +1349,15 @@ static const struct lvts_ctrl_data mt819
- static const struct lvts_data mt8195_lvts_mcu_data = {
- .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
- .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
-+ .temp_factor = LVTS_COEFF_A_MT8195,
-+ .temp_offset = LVTS_COEFF_B_MT8195,
- };
-
- static const struct lvts_data mt8195_lvts_ap_data = {
- .lvts_ctrl = mt8195_lvts_ap_data_ctrl,
- .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
-+ .temp_factor = LVTS_COEFF_A_MT8195,
-+ .temp_offset = LVTS_COEFF_B_MT8195,
- };
-
- static const struct of_device_id lvts_of_match[] = {
+++ /dev/null
-From be2cc09bd5b46f13629d4fcdeac7ad1b18bb1a0b Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Fri, 22 Sep 2023 07:50:18 +0200
-Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal sensors for
- mt7988
-
-Add sensor constants for MT7988.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Acked-by: Conor Dooley <conor.dooley@microchip.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230922055020.6436-3-linux@fw-web.de
----
- include/dt-bindings/thermal/mediatek,lvts-thermal.h | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-@@ -7,6 +7,15 @@
- #ifndef __MEDIATEK_LVTS_DT_H
- #define __MEDIATEK_LVTS_DT_H
-
-+#define MT7988_CPU_0 0
-+#define MT7988_CPU_1 1
-+#define MT7988_ETH2P5G_0 2
-+#define MT7988_ETH2P5G_1 3
-+#define MT7988_TOPS_0 4
-+#define MT7988_TOPS_1 5
-+#define MT7988_ETHWARP_0 6
-+#define MT7988_ETHWARP_1 7
-+
- #define MT8195_MCU_BIG_CPU0 0
- #define MT8195_MCU_BIG_CPU1 1
- #define MT8195_MCU_BIG_CPU2 2
+++ /dev/null
-From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Fri, 22 Sep 2023 07:50:20 +0200
-Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988
- support
-
-Add Support for Mediatek Filogic 880/MT7988 LVTS.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Tested-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de
----
- drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++
- 1 file changed, 38 insertions(+)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -82,6 +82,8 @@
- #define LVTS_GOLDEN_TEMP_DEFAULT 50
- #define LVTS_COEFF_A_MT8195 -250460
- #define LVTS_COEFF_B_MT8195 250460
-+#define LVTS_COEFF_A_MT7988 -204650
-+#define LVTS_COEFF_B_MT7988 204650
-
- #define LVTS_MSR_IMMEDIATE_MODE 0
- #define LVTS_MSR_FILTERED_MODE 1
-@@ -89,6 +91,7 @@
- #define LVTS_MSR_READ_TIMEOUT_US 400
- #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
-
-+#define LVTS_HW_SHUTDOWN_MT7988 105000
- #define LVTS_HW_SHUTDOWN_MT8195 105000
-
- #define LVTS_MINIMUM_THRESHOLD 20000
-@@ -1267,6 +1270,33 @@ static void lvts_remove(struct platform_
- lvts_debugfs_exit(lvts_td);
- }
-
-+static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
-+ {
-+ .cal_offset = { 0x00, 0x04, 0x08, 0x0c },
-+ .lvts_sensor = {
-+ { .dt_id = MT7988_CPU_0 },
-+ { .dt_id = MT7988_CPU_1 },
-+ { .dt_id = MT7988_ETH2P5G_0 },
-+ { .dt_id = MT7988_ETH2P5G_1 }
-+ },
-+ .num_lvts_sensor = 4,
-+ .offset = 0x0,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
-+ },
-+ {
-+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
-+ .lvts_sensor = {
-+ { .dt_id = MT7988_TOPS_0},
-+ { .dt_id = MT7988_TOPS_1},
-+ { .dt_id = MT7988_ETHWARP_0},
-+ { .dt_id = MT7988_ETHWARP_1}
-+ },
-+ .num_lvts_sensor = 4,
-+ .offset = 0x100,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
-+ }
-+};
-+
- static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
- {
- .cal_offset = { 0x04, 0x07 },
-@@ -1346,6 +1376,13 @@ static const struct lvts_ctrl_data mt819
- }
- };
-
-+static const struct lvts_data mt7988_lvts_ap_data = {
-+ .lvts_ctrl = mt7988_lvts_ap_data_ctrl,
-+ .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
-+ .temp_factor = LVTS_COEFF_A_MT7988,
-+ .temp_offset = LVTS_COEFF_B_MT7988,
-+};
-+
- static const struct lvts_data mt8195_lvts_mcu_data = {
- .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
- .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
-@@ -1361,6 +1398,7 @@ static const struct lvts_data mt8195_lvt
- };
-
- static const struct of_device_id lvts_of_match[] = {
-+ { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
- { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
- { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
- {},
+++ /dev/null
-From fb1bbb5b63e4e3c788a978724749ced57d208054 Mon Sep 17 00:00:00 2001
-From: Minjie Du <duminjie@vivo.com>
-Date: Thu, 21 Sep 2023 17:10:50 +0800
-Subject: [PATCH 38/42] thermal/drivers/mediatek/lvts_thermal: Fix error check
- in lvts_debugfs_init()
-
-debugfs_create_dir() function returns an error value embedded in
-the pointer (PTR_ERR). Evaluate the return value using IS_ERR
-rather than checking for NULL.
-
-Signed-off-by: Minjie Du <duminjie@vivo.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230921091057.3812-1-duminjie@vivo.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -219,7 +219,7 @@ static int lvts_debugfs_init(struct devi
-
- sprintf(name, "controller%d", i);
- dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
-- if (!dentry)
-+ if (IS_ERR(dentry))
- continue;
-
- regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
+++ /dev/null
-From e6f43063f2fe9f08b34797bc6d223f7d63b01910 Mon Sep 17 00:00:00 2001
-From: Markus Schneider-Pargmann <msp@baylibre.com>
-Date: Mon, 18 Sep 2023 12:07:06 +0200
-Subject: [PATCH 39/42] thermal/drivers/mediatek: Fix probe for THERMAL_V2
-
-Fix the probe function to call mtk_thermal_release_periodic_ts for
-everything != MTK_THERMAL_V1. This was accidentally changed from V1
-to V2 in the original patch.
-
-Reported-by: Frank Wunderlich <frank-w@public-files.de>
-Closes: https://lore.kernel.org/lkml/B0B3775B-B8D1-4284-814F-4F41EC22F532@public-files.de/
-Reported-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Closes: https://lore.kernel.org/lkml/07a569b9-e691-64ea-dd65-3b49842af33d@linaro.org/
-Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks")
-Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230918100706.1229239-1-msp@baylibre.com
----
- drivers/thermal/mediatek/auxadc_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1268,7 +1268,7 @@ static int mtk_thermal_probe(struct plat
-
- mtk_thermal_turn_on_buffer(mt, apmixed_base);
-
-- if (mt->conf->version != MTK_THERMAL_V2)
-+ if (mt->conf->version != MTK_THERMAL_V1)
- mtk_thermal_release_periodic_ts(mt, auxadc_base);
-
- if (mt->conf->version == MTK_THERMAL_V1)
+++ /dev/null
-From a1d874ef3376295ee8ed89b3b5315f4c840ff00b Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 17 Oct 2023 21:05:42 +0200
-Subject: [PATCH 40/42] thermal/drivers/mediatek/lvts_thermal: Add suspend and
- resume
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add suspend and resume support to LVTS driver.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-[bero@baylibre.com: suspend/resume in noirq phase]
-Co-developed-by: Bernhard Rosenkränzer <bero@baylibre.com>
-Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20231017190545.157282-3-bero@baylibre.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 37 +++++++++++++++++++++++++
- 1 file changed, 37 insertions(+)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -1297,6 +1297,38 @@ static const struct lvts_ctrl_data mt798
- }
- };
-
-+static int lvts_suspend(struct device *dev)
-+{
-+ struct lvts_domain *lvts_td;
-+ int i;
-+
-+ lvts_td = dev_get_drvdata(dev);
-+
-+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
-+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
-+
-+ clk_disable_unprepare(lvts_td->clk);
-+
-+ return 0;
-+}
-+
-+static int lvts_resume(struct device *dev)
-+{
-+ struct lvts_domain *lvts_td;
-+ int i, ret;
-+
-+ lvts_td = dev_get_drvdata(dev);
-+
-+ ret = clk_prepare_enable(lvts_td->clk);
-+ if (ret)
-+ return ret;
-+
-+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
-+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
-+
-+ return 0;
-+}
-+
- static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
- {
- .cal_offset = { 0x04, 0x07 },
-@@ -1405,12 +1437,17 @@ static const struct of_device_id lvts_of
- };
- MODULE_DEVICE_TABLE(of, lvts_of_match);
-
-+static const struct dev_pm_ops lvts_pm_ops = {
-+ NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume)
-+};
-+
- static struct platform_driver lvts_driver = {
- .probe = lvts_probe,
- .remove_new = lvts_remove,
- .driver = {
- .name = "mtk-lvts-thermal",
- .of_match_table = lvts_of_match,
-+ .pm = &lvts_pm_ops,
- },
- };
- module_platform_driver(lvts_driver);
+++ /dev/null
-From 0bb4937b58ab712f158588376dbac97f8e9df68e Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 17 Oct 2023 21:05:41 +0200
-Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controller
- definition for mt8192
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add LVTS thermal controller definition for MT8192.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20231017190545.157282-2-bero@baylibre.com
----
- .../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
-@@ -35,4 +35,23 @@
- #define MT8195_AP_CAM0 15
- #define MT8195_AP_CAM1 16
-
-+#define MT8192_MCU_BIG_CPU0 0
-+#define MT8192_MCU_BIG_CPU1 1
-+#define MT8192_MCU_BIG_CPU2 2
-+#define MT8192_MCU_BIG_CPU3 3
-+#define MT8192_MCU_LITTLE_CPU0 4
-+#define MT8192_MCU_LITTLE_CPU1 5
-+#define MT8192_MCU_LITTLE_CPU2 6
-+#define MT8192_MCU_LITTLE_CPU3 7
-+
-+#define MT8192_AP_VPU0 8
-+#define MT8192_AP_VPU1 9
-+#define MT8192_AP_GPU0 10
-+#define MT8192_AP_GPU1 11
-+#define MT8192_AP_INFRA 12
-+#define MT8192_AP_CAM 13
-+#define MT8192_AP_MD0 14
-+#define MT8192_AP_MD1 15
-+#define MT8192_AP_MD2 16
-+
- #endif /* __MEDIATEK_LVTS_DT_H */
+++ /dev/null
-From 7d8b3864b38d881cf105328ff8569f47446811ad Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 17 Oct 2023 21:05:43 +0200
-Subject: [PATCH 41/42] thermal/drivers/mediatek/lvts_thermal: Add mt8192
- support
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add LVTS Driver support for MT8192.
-
-Co-developed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-[bero@baylibre.com: cosmetic changes, rebase]
-Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
-Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20231017190545.157282-4-bero@baylibre.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
- 1 file changed, 95 insertions(+)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -92,6 +92,7 @@
- #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
-
- #define LVTS_HW_SHUTDOWN_MT7988 105000
-+#define LVTS_HW_SHUTDOWN_MT8192 105000
- #define LVTS_HW_SHUTDOWN_MT8195 105000
-
- #define LVTS_MINIMUM_THRESHOLD 20000
-@@ -1329,6 +1330,88 @@ static int lvts_resume(struct device *de
- return 0;
- }
-
-+static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
-+ {
-+ .cal_offset = { 0x04, 0x08 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8192_MCU_BIG_CPU0 },
-+ { .dt_id = MT8192_MCU_BIG_CPU1 }
-+ },
-+ .num_lvts_sensor = 2,
-+ .offset = 0x0,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+ .mode = LVTS_MSR_FILTERED_MODE,
-+ },
-+ {
-+ .cal_offset = { 0x0c, 0x10 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8192_MCU_BIG_CPU2 },
-+ { .dt_id = MT8192_MCU_BIG_CPU3 }
-+ },
-+ .num_lvts_sensor = 2,
-+ .offset = 0x100,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+ .mode = LVTS_MSR_FILTERED_MODE,
-+ },
-+ {
-+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8192_MCU_LITTLE_CPU0 },
-+ { .dt_id = MT8192_MCU_LITTLE_CPU1 },
-+ { .dt_id = MT8192_MCU_LITTLE_CPU2 },
-+ { .dt_id = MT8192_MCU_LITTLE_CPU3 }
-+ },
-+ .num_lvts_sensor = 4,
-+ .offset = 0x200,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+ .mode = LVTS_MSR_FILTERED_MODE,
-+ }
-+};
-+
-+static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
-+ {
-+ .cal_offset = { 0x24, 0x28 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8192_AP_VPU0 },
-+ { .dt_id = MT8192_AP_VPU1 }
-+ },
-+ .num_lvts_sensor = 2,
-+ .offset = 0x0,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+ },
-+ {
-+ .cal_offset = { 0x2c, 0x30 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8192_AP_GPU0 },
-+ { .dt_id = MT8192_AP_GPU1 }
-+ },
-+ .num_lvts_sensor = 2,
-+ .offset = 0x100,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+ },
-+ {
-+ .cal_offset = { 0x34, 0x38 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8192_AP_INFRA },
-+ { .dt_id = MT8192_AP_CAM },
-+ },
-+ .num_lvts_sensor = 2,
-+ .offset = 0x200,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+ },
-+ {
-+ .cal_offset = { 0x3c, 0x40, 0x44 },
-+ .lvts_sensor = {
-+ { .dt_id = MT8192_AP_MD0 },
-+ { .dt_id = MT8192_AP_MD1 },
-+ { .dt_id = MT8192_AP_MD2 }
-+ },
-+ .num_lvts_sensor = 3,
-+ .offset = 0x300,
-+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
-+ }
-+};
-+
- static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
- {
- .cal_offset = { 0x04, 0x07 },
-@@ -1415,6 +1498,16 @@ static const struct lvts_data mt7988_lvt
- .temp_offset = LVTS_COEFF_B_MT7988,
- };
-
-+static const struct lvts_data mt8192_lvts_mcu_data = {
-+ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
-+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
-+};
-+
-+static const struct lvts_data mt8192_lvts_ap_data = {
-+ .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
-+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
-+};
-+
- static const struct lvts_data mt8195_lvts_mcu_data = {
- .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
- .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
-@@ -1431,6 +1524,8 @@ static const struct lvts_data mt8195_lvt
-
- static const struct of_device_id lvts_of_match[] = {
- { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
-+ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
-+ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
- { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
- { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
- {},
+++ /dev/null
-From 5d126a3c87cf7964b28bacf3826eea4266265bce Mon Sep 17 00:00:00 2001
-From: Balsam CHIHI <bchihi@baylibre.com>
-Date: Tue, 17 Oct 2023 21:05:45 +0200
-Subject: [PATCH 42/42] thermal/drivers/mediatek/lvts_thermal: Update
- calibration data documentation
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Update LVTS calibration data documentation for mt8192 and mt8195.
-
-Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
-Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
-[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>]
-Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20231017190545.157282-6-bero@baylibre.com
----
- drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++--
- 1 file changed, 29 insertions(+), 2 deletions(-)
-
---- a/drivers/thermal/mediatek/lvts_thermal.c
-+++ b/drivers/thermal/mediatek/lvts_thermal.c
-@@ -616,7 +616,34 @@ static int lvts_sensor_init(struct devic
- * The efuse blob values follows the sensor enumeration per thermal
- * controller. The decoding of the stream is as follow:
- *
-- * stream index map for MCU Domain :
-+ * MT8192 :
-+ * Stream index map for MCU Domain mt8192 :
-+ *
-+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
-+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
-+ *
-+ * <-----sensor#2-----> <-----sensor#3----->
-+ * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
-+ *
-+ * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
-+ * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
-+ *
-+ * Stream index map for AP Domain mt8192 :
-+ *
-+ * <-----sensor#0-----> <-----sensor#1----->
-+ * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
-+ *
-+ * <-----sensor#2-----> <-----sensor#3----->
-+ * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
-+ *
-+ * <-----sensor#4-----> <-----sensor#5----->
-+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
-+ *
-+ * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
-+ * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
-+ *
-+ * MT8195 :
-+ * Stream index map for MCU Domain mt8195 :
- *
- * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
- * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
-@@ -627,7 +654,7 @@ static int lvts_sensor_init(struct devic
- * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
- * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
- *
-- * stream index map for AP Domain :
-+ * Stream index map for AP Domain mt8195 :
- *
- * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
- * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
+++ /dev/null
-From patchwork Thu Sep 7 11:20:18 2023
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Frank Wunderlich <linux@fw-web.de>
-X-Patchwork-Id: 13376356
-From: Frank Wunderlich <linux@fw-web.de>
-To: linux-mediatek@lists.infradead.org
-Subject: [PATCH] thermal/drivers/mediatek: Fix control buffer enablement on
- MT7896
-Date: Thu, 7 Sep 2023 13:20:18 +0200
-Message-Id: <20230907112018.52811-1-linux@fw-web.de>
-X-Mailer: git-send-email 2.34.1
-MIME-Version: 1.0
-X-Mail-ID: e7eeb8e1-00de-41f6-a5df-ce2e9164136e
-X-BeenThere: linux-mediatek@lists.infradead.org
-X-Mailman-Version: 2.1.34
-Precedence: list
-List-Id: <linux-mediatek.lists.infradead.org>
-Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
- "Rafael J. Wysocki" <rafael@kernel.org>, linux-pm@vger.kernel.org,
- Amit Kucheria <amitk@kernel.org>, Daniel Golle <daniel@makrotopia.org>,
- stable@vger.kernel.org, linux-kernel@vger.kernel.org,
- Matthias Brugger <matthias.bgg@gmail.com>, Zhang Rui <rui.zhang@intel.com>,
- linux-arm-kernel@lists.infradead.org,
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
-
-From: Frank Wunderlich <frank-w@public-files.de>
-
-Reading thermal sensor on mt7986 devices returns invalid temperature:
-
-bpi-r3 ~ # cat /sys/class/thermal/thermal_zone0/temp
- -274000
-
-Fix this by adding missing members in mtk_thermal_data struct which were
-used in mtk_thermal_turn_on_buffer after commit 33140e668b10.
-
-Cc: stable@vger.kernel.org
-Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks")
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
----
- drivers/thermal/mediatek/auxadc_thermal.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -691,6 +691,9 @@ static const struct mtk_thermal_data mt7
- .adcpnp = mt7986_adcpnp,
- .sensor_mux_values = mt7986_mux_values,
- .version = MTK_THERMAL_V3,
-+ .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
-+ .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
-+ .apmixed_buffer_ctl_set = BIT(0),
- };
-
- static bool mtk_thermal_temp_is_valid(int temp)
+++ /dev/null
-From 11f9a0f4e51887ad7b4a2898a368fcd0c2984e89 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 9 Oct 2022 12:16:31 +0200
-Subject: [PATCH 12/16] i2c: mediatek: add mt7986 support
-
-Add i2c support for MT7986 SoC.
-
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -431,6 +431,19 @@ static const struct mtk_i2c_compatible m
- .max_dma_support = 33,
- };
-
-+static const struct mtk_i2c_compatible mt7986_compat = {
-+ .quirks = &mt7622_i2c_quirks,
-+ .regs = mt_i2c_regs_v1,
-+ .pmic_i2c = 0,
-+ .dcm = 1,
-+ .auto_restart = 1,
-+ .aux_len_reg = 1,
-+ .timing_adjust = 0,
-+ .dma_sync = 1,
-+ .ltiming_adjust = 0,
-+ .max_dma_support = 32,
-+};
-+
- static const struct mtk_i2c_compatible mt8173_compat = {
- .regs = mt_i2c_regs_v1,
- .pmic_i2c = 0,
-@@ -503,6 +516,7 @@ static const struct of_device_id mtk_i2c
- { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
- { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
- { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
-+ { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
- { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
- { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
- { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
+++ /dev/null
-From 98204ccafd45a8a6109ff2d60e2c179b95d92578 Mon Sep 17 00:00:00 2001
-From: ye xingchen <ye.xingchen@zte.com.cn>
-Date: Thu, 19 Jan 2023 17:19:58 +0800
-Subject: [PATCH 13/16] i2c: mt65xx: Use
- devm_platform_get_and_ioremap_resource()
-
-Convert platform_get_resource(), devm_ioremap_resource() to a single
-call to devm_platform_get_and_ioremap_resource(), as this is exactly
-what this function does.
-
-Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1366,20 +1366,17 @@ static int mtk_i2c_probe(struct platform
- {
- int ret = 0;
- struct mtk_i2c *i2c;
-- struct resource *res;
- int i, irq, speed_clk;
-
- i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
- if (!i2c)
- return -ENOMEM;
-
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- i2c->base = devm_ioremap_resource(&pdev->dev, res);
-+ i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
- if (IS_ERR(i2c->base))
- return PTR_ERR(i2c->base);
-
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-- i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
-+ i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
- if (IS_ERR(i2c->pdmabase))
- return PTR_ERR(i2c->pdmabase);
-
+++ /dev/null
-From 8106fa2e0ae6082833fe1df97829c46c0183eaea Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Sat, 11 Mar 2023 12:16:54 +0100
-Subject: [PATCH 14/16] i2c: mt65xx: drop of_match_ptr for ID table
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The driver can match only via the DT table so the table should be always
-used and the of_match_ptr does not have any sense (this also allows ACPI
-matching via PRP0001, even though it might not be relevant here).
-
- drivers/i2c/busses/i2c-mt65xx.c:514:34: error: ‘mtk_i2c_of_match’ defined but not used [-Werror=unused-const-variable=]
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Guenter Roeck <groeck@chromium.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1546,7 +1546,7 @@ static struct platform_driver mtk_i2c_dr
- .driver = {
- .name = I2C_DRV_NAME,
- .pm = &mtk_i2c_pm,
-- .of_match_table = of_match_ptr(mtk_i2c_of_match),
-+ .of_match_table = mtk_i2c_of_match,
- },
- };
-
+++ /dev/null
-From f69f3d662ba3bf999c36d9ac1e684540c4487bc3 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 10 Apr 2023 17:19:38 +0100
-Subject: [PATCH 15/16] i2c: mediatek: add support for MT7981 SoC
-
-Add support for the I2C units found in the MediaTek MT7981 and MT7988
-SoCs. Just like other recent MediaTek I2C units that also uses v3
-register offsets (which differ from v2 only by OFFSET_SLAVE_ADDR being
-0x94 instead of 0x4).
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -431,6 +431,18 @@ static const struct mtk_i2c_compatible m
- .max_dma_support = 33,
- };
-
-+static const struct mtk_i2c_compatible mt7981_compat = {
-+ .regs = mt_i2c_regs_v3,
-+ .pmic_i2c = 0,
-+ .dcm = 0,
-+ .auto_restart = 1,
-+ .aux_len_reg = 1,
-+ .timing_adjust = 1,
-+ .dma_sync = 1,
-+ .ltiming_adjust = 1,
-+ .max_dma_support = 33
-+};
-+
- static const struct mtk_i2c_compatible mt7986_compat = {
- .quirks = &mt7622_i2c_quirks,
- .regs = mt_i2c_regs_v1,
-@@ -516,6 +528,7 @@ static const struct of_device_id mtk_i2c
- { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
- { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
- { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
-+ { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat },
- { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
- { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
- { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
+++ /dev/null
-From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sat, 26 Aug 2023 21:56:51 +0100
-Subject: [PATCH] i2c: mt65xx: allow optional pmic clock
-
-Using the I2C host controller on the MT7981 SoC requires 4 clocks to
-be enabled. One of them, the pmic clk, is only enabled in case
-'mediatek,have-pmic' is also set which has other consequences which
-are not desired in this case.
-
-Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty
-is not present and the bus is not used to connect to a pmic, but may
-still require to enable the pmic clock.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++----
- 1 file changed, 8 insertions(+), 4 deletions(-)
-
---- a/drivers/i2c/busses/i2c-mt65xx.c
-+++ b/drivers/i2c/busses/i2c-mt65xx.c
-@@ -1444,15 +1444,19 @@ static int mtk_i2c_probe(struct platform
- if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
- return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
-
-+ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic");
-+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
-+ dev_err(&pdev->dev, "cannot get pmic clock\n");
-+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
-+ }
-+
- if (i2c->have_pmic) {
-- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
-- if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
-+ if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) {
- dev_err(&pdev->dev, "cannot get pmic clock\n");
-- return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
-+ return -ENODEV;
- }
- speed_clk = I2C_MT65XX_CLK_PMIC;
- } else {
-- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
- speed_clk = I2C_MT65XX_CLK_MAIN;
- }
-
+++ /dev/null
-From d35469096915f2551ed1d26da1ab12ff500fc963 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:33 +0800
-Subject: [PATCH 1/9] ASoC: mediatek: mt7986: add common header
-
-Add header files for register definition and structure.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-2-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-afe-common.h | 49 +++++
- sound/soc/mediatek/mt7986/mt7986-reg.h | 196 ++++++++++++++++++
- 2 files changed, 245 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-common.h
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-reg.h
-
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-afe-common.h
-@@ -0,0 +1,49 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * mt7986-afe-common.h -- MediaTek 7986 audio driver definitions
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ * Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#ifndef _MT_7986_AFE_COMMON_H_
-+#define _MT_7986_AFE_COMMON_H_
-+
-+#include <sound/soc.h>
-+#include <linux/clk.h>
-+#include <linux/list.h>
-+#include <linux/regmap.h>
-+#include "../common/mtk-base-afe.h"
-+
-+enum {
-+ MT7986_MEMIF_DL1,
-+ MT7986_MEMIF_VUL12,
-+ MT7986_MEMIF_NUM,
-+ MT7986_DAI_ETDM = MT7986_MEMIF_NUM,
-+ MT7986_DAI_NUM,
-+};
-+
-+enum {
-+ MT7986_IRQ_0,
-+ MT7986_IRQ_1,
-+ MT7986_IRQ_2,
-+ MT7986_IRQ_NUM,
-+};
-+
-+struct mt7986_afe_private {
-+ struct clk_bulk_data *clks;
-+ int num_clks;
-+
-+ int pm_runtime_bypass_reg_ctl;
-+
-+ /* dai */
-+ void *dai_priv[MT7986_DAI_NUM];
-+};
-+
-+unsigned int mt7986_afe_rate_transform(struct device *dev,
-+ unsigned int rate);
-+
-+/* dai register */
-+int mt7986_dai_etdm_register(struct mtk_base_afe *afe);
-+#endif
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-reg.h
-@@ -0,0 +1,196 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * mt7986-reg.h -- MediaTek 7986 audio driver reg definition
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ * Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#ifndef _MT7986_REG_H_
-+#define _MT7986_REG_H_
-+
-+#define AUDIO_TOP_CON2 0x0008
-+#define AUDIO_TOP_CON4 0x0010
-+#define AUDIO_ENGEN_CON0 0x0014
-+#define AFE_IRQ_MCU_EN 0x0100
-+#define AFE_IRQ_MCU_STATUS 0x0120
-+#define AFE_IRQ_MCU_CLR 0x0128
-+#define AFE_IRQ0_MCU_CFG0 0x0140
-+#define AFE_IRQ0_MCU_CFG1 0x0144
-+#define AFE_IRQ1_MCU_CFG0 0x0148
-+#define AFE_IRQ1_MCU_CFG1 0x014c
-+#define AFE_IRQ2_MCU_CFG0 0x0150
-+#define AFE_IRQ2_MCU_CFG1 0x0154
-+#define ETDM_IN5_CON0 0x13f0
-+#define ETDM_IN5_CON1 0x13f4
-+#define ETDM_IN5_CON2 0x13f8
-+#define ETDM_IN5_CON3 0x13fc
-+#define ETDM_IN5_CON4 0x1400
-+#define ETDM_OUT5_CON0 0x1570
-+#define ETDM_OUT5_CON4 0x1580
-+#define ETDM_OUT5_CON5 0x1584
-+#define ETDM_4_7_COWORK_CON0 0x15e0
-+#define ETDM_4_7_COWORK_CON1 0x15e4
-+#define AFE_CONN018_1 0x1b44
-+#define AFE_CONN018_4 0x1b50
-+#define AFE_CONN019_1 0x1b64
-+#define AFE_CONN019_4 0x1b70
-+#define AFE_CONN124_1 0x2884
-+#define AFE_CONN124_4 0x2890
-+#define AFE_CONN125_1 0x28a4
-+#define AFE_CONN125_4 0x28b0
-+#define AFE_CONN_RS_0 0x3920
-+#define AFE_CONN_RS_3 0x392c
-+#define AFE_CONN_16BIT_0 0x3960
-+#define AFE_CONN_16BIT_3 0x396c
-+#define AFE_CONN_24BIT_0 0x3980
-+#define AFE_CONN_24BIT_3 0x398c
-+#define AFE_MEMIF_CON0 0x3d98
-+#define AFE_MEMIF_RD_MON 0x3da0
-+#define AFE_MEMIF_WR_MON 0x3da4
-+#define AFE_DL0_BASE_MSB 0x3e40
-+#define AFE_DL0_BASE 0x3e44
-+#define AFE_DL0_CUR_MSB 0x3e48
-+#define AFE_DL0_CUR 0x3e4c
-+#define AFE_DL0_END_MSB 0x3e50
-+#define AFE_DL0_END 0x3e54
-+#define AFE_DL0_RCH_MON 0x3e58
-+#define AFE_DL0_LCH_MON 0x3e5c
-+#define AFE_DL0_CON0 0x3e60
-+#define AFE_VUL0_BASE_MSB 0x4220
-+#define AFE_VUL0_BASE 0x4224
-+#define AFE_VUL0_CUR_MSB 0x4228
-+#define AFE_VUL0_CUR 0x422c
-+#define AFE_VUL0_END_MSB 0x4230
-+#define AFE_VUL0_END 0x4234
-+#define AFE_VUL0_CON0 0x4238
-+
-+#define AFE_MAX_REGISTER AFE_VUL0_CON0
-+#define AFE_IRQ_STATUS_BITS 0x7
-+#define AFE_IRQ_CNT_SHIFT 0
-+#define AFE_IRQ_CNT_MASK 0xffffff
-+
-+/* AUDIO_TOP_CON2 */
-+#define CLK_OUT5_PDN BIT(14)
-+#define CLK_OUT5_PDN_MASK BIT(14)
-+#define CLK_IN5_PDN BIT(7)
-+#define CLK_IN5_PDN_MASK BIT(7)
-+
-+/* AUDIO_TOP_CON4 */
-+#define PDN_APLL_TUNER2 BIT(12)
-+#define PDN_APLL_TUNER2_MASK BIT(12)
-+
-+/* AUDIO_ENGEN_CON0 */
-+#define AUD_APLL2_EN BIT(3)
-+#define AUD_APLL2_EN_MASK BIT(3)
-+#define AUD_26M_EN BIT(0)
-+#define AUD_26M_EN_MASK BIT(0)
-+
-+/* AFE_DL0_CON0 */
-+#define DL0_ON_SFT 28
-+#define DL0_ON_MASK 0x1
-+#define DL0_ON_MASK_SFT BIT(28)
-+#define DL0_MINLEN_SFT 20
-+#define DL0_MINLEN_MASK 0xf
-+#define DL0_MINLEN_MASK_SFT (0xf << 20)
-+#define DL0_MODE_SFT 8
-+#define DL0_MODE_MASK 0x1f
-+#define DL0_MODE_MASK_SFT (0x1f << 8)
-+#define DL0_PBUF_SIZE_SFT 5
-+#define DL0_PBUF_SIZE_MASK 0x3
-+#define DL0_PBUF_SIZE_MASK_SFT (0x3 << 5)
-+#define DL0_MONO_SFT 4
-+#define DL0_MONO_MASK 0x1
-+#define DL0_MONO_MASK_SFT BIT(4)
-+#define DL0_HALIGN_SFT 2
-+#define DL0_HALIGN_MASK 0x1
-+#define DL0_HALIGN_MASK_SFT BIT(2)
-+#define DL0_HD_MODE_SFT 0
-+#define DL0_HD_MODE_MASK 0x3
-+#define DL0_HD_MODE_MASK_SFT (0x3 << 0)
-+
-+/* AFE_VUL0_CON0 */
-+#define VUL0_ON_SFT 28
-+#define VUL0_ON_MASK 0x1
-+#define VUL0_ON_MASK_SFT BIT(28)
-+#define VUL0_MODE_SFT 8
-+#define VUL0_MODE_MASK 0x1f
-+#define VUL0_MODE_MASK_SFT (0x1f << 8)
-+#define VUL0_MONO_SFT 4
-+#define VUL0_MONO_MASK 0x1
-+#define VUL0_MONO_MASK_SFT BIT(4)
-+#define VUL0_HALIGN_SFT 2
-+#define VUL0_HALIGN_MASK 0x1
-+#define VUL0_HALIGN_MASK_SFT BIT(2)
-+#define VUL0_HD_MODE_SFT 0
-+#define VUL0_HD_MODE_MASK 0x3
-+#define VUL0_HD_MODE_MASK_SFT (0x3 << 0)
-+
-+/* AFE_IRQ_MCU_CON */
-+#define IRQ_MCU_MODE_SFT 4
-+#define IRQ_MCU_MODE_MASK 0x1f
-+#define IRQ_MCU_MODE_MASK_SFT (0x1f << 4)
-+#define IRQ_MCU_ON_SFT 0
-+#define IRQ_MCU_ON_MASK 0x1
-+#define IRQ_MCU_ON_MASK_SFT BIT(0)
-+#define IRQ0_MCU_CLR_SFT 0
-+#define IRQ0_MCU_CLR_MASK 0x1
-+#define IRQ0_MCU_CLR_MASK_SFT BIT(0)
-+#define IRQ1_MCU_CLR_SFT 1
-+#define IRQ1_MCU_CLR_MASK 0x1
-+#define IRQ1_MCU_CLR_MASK_SFT BIT(1)
-+#define IRQ2_MCU_CLR_SFT 2
-+#define IRQ2_MCU_CLR_MASK 0x1
-+#define IRQ2_MCU_CLR_MASK_SFT BIT(2)
-+
-+/* ETDM_IN5_CON2 */
-+#define IN_CLK_SRC(x) ((x) << 10)
-+#define IN_CLK_SRC_SFT 10
-+#define IN_CLK_SRC_MASK GENMASK(12, 10)
-+
-+/* ETDM_IN5_CON3 */
-+#define IN_SEL_FS(x) ((x) << 26)
-+#define IN_SEL_FS_SFT 26
-+#define IN_SEL_FS_MASK GENMASK(30, 26)
-+
-+/* ETDM_IN5_CON4 */
-+#define IN_RELATCH(x) ((x) << 20)
-+#define IN_RELATCH_SFT 20
-+#define IN_RELATCH_MASK GENMASK(24, 20)
-+#define IN_CLK_INV BIT(18)
-+#define IN_CLK_INV_MASK BIT(18)
-+
-+/* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */
-+#define RELATCH_SRC_MASK GENMASK(30, 28)
-+#define ETDM_CH_NUM_MASK GENMASK(27, 23)
-+#define ETDM_WRD_LEN_MASK GENMASK(20, 16)
-+#define ETDM_BIT_LEN_MASK GENMASK(15, 11)
-+#define ETDM_FMT_MASK GENMASK(8, 6)
-+#define ETDM_SYNC BIT(1)
-+#define ETDM_SYNC_MASK BIT(1)
-+#define ETDM_EN BIT(0)
-+#define ETDM_EN_MASK BIT(0)
-+
-+/* ETDM_OUT5_CON4 */
-+#define OUT_RELATCH(x) ((x) << 24)
-+#define OUT_RELATCH_SFT 24
-+#define OUT_RELATCH_MASK GENMASK(28, 24)
-+#define OUT_CLK_SRC(x) ((x) << 6)
-+#define OUT_CLK_SRC_SFT 6
-+#define OUT_CLK_SRC_MASK GENMASK(8, 6)
-+#define OUT_SEL_FS(x) (x)
-+#define OUT_SEL_FS_SFT 0
-+#define OUT_SEL_FS_MASK GENMASK(4, 0)
-+
-+/* ETDM_OUT5_CON5 */
-+#define ETDM_CLK_DIV BIT(12)
-+#define ETDM_CLK_DIV_MASK BIT(12)
-+#define OUT_CLK_INV BIT(9)
-+#define OUT_CLK_INV_MASK BIT(9)
-+
-+/* ETDM_4_7_COWORK_CON0 */
-+#define OUT_SEL(x) ((x) << 12)
-+#define OUT_SEL_SFT 12
-+#define OUT_SEL_MASK GENMASK(15, 12)
-+#endif
+++ /dev/null
-From 948a288897015fb3ee63b3f720b396b590c17fd7 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:34 +0800
-Subject: [PATCH 2/9] ASoC: mediatek: mt7986: support etdm in platform driver
-
-Add mt7986 etdm dai driver support.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-3-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 411 ++++++++++++++++++++
- 1 file changed, 411 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-@@ -0,0 +1,411 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MediaTek ALSA SoC Audio DAI eTDM Control
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ * Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/bitfield.h>
-+#include <linux/bitops.h>
-+#include <linux/regmap.h>
-+#include <sound/pcm_params.h>
-+#include "mt7986-afe-common.h"
-+#include "mt7986-reg.h"
-+
-+#define HOPPING_CLK 0
-+#define APLL_CLK 1
-+#define MTK_DAI_ETDM_FORMAT_I2S 0
-+#define MTK_DAI_ETDM_FORMAT_DSPA 4
-+#define MTK_DAI_ETDM_FORMAT_DSPB 5
-+
-+enum {
-+ MTK_ETDM_RATE_8K = 0,
-+ MTK_ETDM_RATE_12K = 1,
-+ MTK_ETDM_RATE_16K = 2,
-+ MTK_ETDM_RATE_24K = 3,
-+ MTK_ETDM_RATE_32K = 4,
-+ MTK_ETDM_RATE_48K = 5,
-+ MTK_ETDM_RATE_96K = 7,
-+ MTK_ETDM_RATE_192K = 9,
-+ MTK_ETDM_RATE_11K = 16,
-+ MTK_ETDM_RATE_22K = 17,
-+ MTK_ETDM_RATE_44K = 18,
-+ MTK_ETDM_RATE_88K = 19,
-+ MTK_ETDM_RATE_176K = 20,
-+};
-+
-+struct mtk_dai_etdm_priv {
-+ bool bck_inv;
-+ bool lrck_inv;
-+ bool slave_mode;
-+ unsigned int format;
-+};
-+
-+static unsigned int mt7986_etdm_rate_transform(struct device *dev, unsigned int rate)
-+{
-+ switch (rate) {
-+ case 8000:
-+ return MTK_ETDM_RATE_8K;
-+ case 11025:
-+ return MTK_ETDM_RATE_11K;
-+ case 12000:
-+ return MTK_ETDM_RATE_12K;
-+ case 16000:
-+ return MTK_ETDM_RATE_16K;
-+ case 22050:
-+ return MTK_ETDM_RATE_22K;
-+ case 24000:
-+ return MTK_ETDM_RATE_24K;
-+ case 32000:
-+ return MTK_ETDM_RATE_32K;
-+ case 44100:
-+ return MTK_ETDM_RATE_44K;
-+ case 48000:
-+ return MTK_ETDM_RATE_48K;
-+ case 88200:
-+ return MTK_ETDM_RATE_88K;
-+ case 96000:
-+ return MTK_ETDM_RATE_96K;
-+ case 176400:
-+ return MTK_ETDM_RATE_176K;
-+ case 192000:
-+ return MTK_ETDM_RATE_192K;
-+ default:
-+ dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
-+ __func__, rate, MTK_ETDM_RATE_48K);
-+ return MTK_ETDM_RATE_48K;
-+ }
-+}
-+
-+static int get_etdm_wlen(unsigned int bitwidth)
-+{
-+ return bitwidth <= 16 ? 16 : 32;
-+}
-+
-+/* dai component */
-+/* interconnection */
-+
-+static const struct snd_kcontrol_new o124_mix[] = {
-+ SOC_DAPM_SINGLE_AUTODISABLE("I032_Switch", AFE_CONN124_1, 0, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new o125_mix[] = {
-+ SOC_DAPM_SINGLE_AUTODISABLE("I033_Switch", AFE_CONN125_1, 1, 1, 0),
-+};
-+
-+static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
-+
-+ /* DL */
-+ SND_SOC_DAPM_MIXER("I150", SND_SOC_NOPM, 0, 0, NULL, 0),
-+ SND_SOC_DAPM_MIXER("I151", SND_SOC_NOPM, 0, 0, NULL, 0),
-+ /* UL */
-+ SND_SOC_DAPM_MIXER("O124", SND_SOC_NOPM, 0, 0, o124_mix, ARRAY_SIZE(o124_mix)),
-+ SND_SOC_DAPM_MIXER("O125", SND_SOC_NOPM, 0, 0, o125_mix, ARRAY_SIZE(o125_mix)),
-+};
-+
-+static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
-+ {"I150", NULL, "ETDM Capture"},
-+ {"I151", NULL, "ETDM Capture"},
-+ {"ETDM Playback", NULL, "O124"},
-+ {"ETDM Playback", NULL, "O125"},
-+ {"O124", "I032_Switch", "I032"},
-+ {"O125", "I033_Switch", "I033"},
-+};
-+
-+/* dai ops */
-+static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+ struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+ int ret;
-+
-+ ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
-+ if (ret)
-+ return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
-+
-+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK, 0);
-+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK, 0);
-+
-+ return 0;
-+}
-+
-+static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+ struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+
-+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_OUT5_PDN_MASK,
-+ CLK_OUT5_PDN);
-+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON2, CLK_IN5_PDN_MASK,
-+ CLK_IN5_PDN);
-+
-+ clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
-+}
-+
-+static unsigned int get_etdm_ch_fixup(unsigned int channels)
-+{
-+ if (channels > 16)
-+ return 24;
-+ else if (channels > 8)
-+ return 16;
-+ else if (channels > 4)
-+ return 8;
-+ else if (channels > 2)
-+ return 4;
-+ else
-+ return 2;
-+}
-+
-+static int mtk_dai_etdm_config(struct mtk_base_afe *afe,
-+ struct snd_pcm_hw_params *params,
-+ struct snd_soc_dai *dai,
-+ int stream)
-+{
-+ struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+ struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id];
-+ unsigned int rate = params_rate(params);
-+ unsigned int etdm_rate = mt7986_etdm_rate_transform(afe->dev, rate);
-+ unsigned int afe_rate = mt7986_afe_rate_transform(afe->dev, rate);
-+ unsigned int channels = params_channels(params);
-+ unsigned int bit_width = params_width(params);
-+ unsigned int wlen = get_etdm_wlen(bit_width);
-+ unsigned int val = 0;
-+ unsigned int mask = 0;
-+
-+ dev_dbg(afe->dev, "%s(), stream %d, rate %u, bitwidth %u\n",
-+ __func__, stream, rate, bit_width);
-+
-+ /* CON0 */
-+ mask |= ETDM_BIT_LEN_MASK;
-+ val |= FIELD_PREP(ETDM_BIT_LEN_MASK, bit_width - 1);
-+ mask |= ETDM_WRD_LEN_MASK;
-+ val |= FIELD_PREP(ETDM_WRD_LEN_MASK, wlen - 1);
-+ mask |= ETDM_FMT_MASK;
-+ val |= FIELD_PREP(ETDM_FMT_MASK, etdm_data->format);
-+ mask |= ETDM_CH_NUM_MASK;
-+ val |= FIELD_PREP(ETDM_CH_NUM_MASK, get_etdm_ch_fixup(channels) - 1);
-+ mask |= RELATCH_SRC_MASK;
-+ val |= FIELD_PREP(RELATCH_SRC_MASK, APLL_CLK);
-+
-+ switch (stream) {
-+ case SNDRV_PCM_STREAM_PLAYBACK:
-+ /* set ETDM_OUT5_CON0 */
-+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, mask, val);
-+
-+ /* set ETDM_OUT5_CON4 */
-+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+ OUT_RELATCH_MASK, OUT_RELATCH(afe_rate));
-+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+ OUT_CLK_SRC_MASK, OUT_CLK_SRC(APLL_CLK));
-+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON4,
-+ OUT_SEL_FS_MASK, OUT_SEL_FS(etdm_rate));
-+
-+ /* set ETDM_OUT5_CON5 */
-+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON5,
-+ ETDM_CLK_DIV_MASK, ETDM_CLK_DIV);
-+ break;
-+ case SNDRV_PCM_STREAM_CAPTURE:
-+ /* set ETDM_IN5_CON0 */
-+ regmap_update_bits(afe->regmap, ETDM_IN5_CON0, mask, val);
-+ regmap_update_bits(afe->regmap, ETDM_IN5_CON0,
-+ ETDM_SYNC_MASK, ETDM_SYNC);
-+
-+ /* set ETDM_IN5_CON2 */
-+ regmap_update_bits(afe->regmap, ETDM_IN5_CON2,
-+ IN_CLK_SRC_MASK, IN_CLK_SRC(APLL_CLK));
-+
-+ /* set ETDM_IN5_CON3 */
-+ regmap_update_bits(afe->regmap, ETDM_IN5_CON3,
-+ IN_SEL_FS_MASK, IN_SEL_FS(etdm_rate));
-+
-+ /* set ETDM_IN5_CON4 */
-+ regmap_update_bits(afe->regmap, ETDM_IN5_CON4,
-+ IN_RELATCH_MASK, IN_RELATCH(afe_rate));
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params,
-+ struct snd_soc_dai *dai)
-+{
-+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+
-+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
-+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
-+
-+ return 0;
-+}
-+
-+static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
-+ struct snd_soc_dai *dai)
-+{
-+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+
-+ dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
-+ switch (cmd) {
-+ case SNDRV_PCM_TRIGGER_START:
-+ case SNDRV_PCM_TRIGGER_RESUME:
-+ regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
-+ ETDM_EN);
-+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
-+ ETDM_EN);
-+ break;
-+ case SNDRV_PCM_TRIGGER_STOP:
-+ case SNDRV_PCM_TRIGGER_SUSPEND:
-+ regmap_update_bits(afe->regmap, ETDM_IN5_CON0, ETDM_EN_MASK,
-+ 0);
-+ regmap_update_bits(afe->regmap, ETDM_OUT5_CON0, ETDM_EN_MASK,
-+ 0);
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
-+static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
-+{
-+ struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-+ struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+ struct mtk_dai_etdm_priv *etdm_data;
-+ void *priv_data;
-+
-+ switch (dai->id) {
-+ case MT7986_DAI_ETDM:
-+ break;
-+ default:
-+ dev_warn(afe->dev, "%s(), id %d not support\n",
-+ __func__, dai->id);
-+ return -EINVAL;
-+ }
-+
-+ priv_data = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_etdm_priv),
-+ GFP_KERNEL);
-+ if (!priv_data)
-+ return -ENOMEM;
-+
-+ afe_priv->dai_priv[dai->id] = priv_data;
-+ etdm_data = afe_priv->dai_priv[dai->id];
-+
-+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
-+ case SND_SOC_DAIFMT_I2S:
-+ etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
-+ break;
-+ case SND_SOC_DAIFMT_DSP_A:
-+ etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
-+ break;
-+ case SND_SOC_DAIFMT_DSP_B:
-+ etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
-+ case SND_SOC_DAIFMT_NB_NF:
-+ etdm_data->bck_inv = false;
-+ etdm_data->lrck_inv = false;
-+ break;
-+ case SND_SOC_DAIFMT_NB_IF:
-+ etdm_data->bck_inv = false;
-+ etdm_data->lrck_inv = true;
-+ break;
-+ case SND_SOC_DAIFMT_IB_NF:
-+ etdm_data->bck_inv = true;
-+ etdm_data->lrck_inv = false;
-+ break;
-+ case SND_SOC_DAIFMT_IB_IF:
-+ etdm_data->bck_inv = true;
-+ etdm_data->lrck_inv = true;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+ case SND_SOC_DAIFMT_CBM_CFM:
-+ etdm_data->slave_mode = true;
-+ break;
-+ case SND_SOC_DAIFMT_CBS_CFS:
-+ etdm_data->slave_mode = false;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
-+ .startup = mtk_dai_etdm_startup,
-+ .shutdown = mtk_dai_etdm_shutdown,
-+ .hw_params = mtk_dai_etdm_hw_params,
-+ .trigger = mtk_dai_etdm_trigger,
-+ .set_fmt = mtk_dai_etdm_set_fmt,
-+};
-+
-+/* dai driver */
-+#define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
-+ SNDRV_PCM_RATE_88200 |\
-+ SNDRV_PCM_RATE_96000 |\
-+ SNDRV_PCM_RATE_176400 |\
-+ SNDRV_PCM_RATE_192000)
-+
-+#define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
-+ SNDRV_PCM_FMTBIT_S24_LE |\
-+ SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
-+ {
-+ .name = "ETDM",
-+ .id = MT7986_DAI_ETDM,
-+ .capture = {
-+ .stream_name = "ETDM Capture",
-+ .channels_min = 1,
-+ .channels_max = 2,
-+ .rates = MTK_ETDM_RATES,
-+ .formats = MTK_ETDM_FORMATS,
-+ },
-+ .playback = {
-+ .stream_name = "ETDM Playback",
-+ .channels_min = 1,
-+ .channels_max = 2,
-+ .rates = MTK_ETDM_RATES,
-+ .formats = MTK_ETDM_FORMATS,
-+ },
-+ .ops = &mtk_dai_etdm_ops,
-+ .symmetric_rate = 1,
-+ .symmetric_sample_bits = 1,
-+ },
-+};
-+
-+int mt7986_dai_etdm_register(struct mtk_base_afe *afe)
-+{
-+ struct mtk_base_afe_dai *dai;
-+
-+ dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
-+ if (!dai)
-+ return -ENOMEM;
-+
-+ list_add(&dai->list, &afe->sub_dais);
-+
-+ dai->dai_drivers = mtk_dai_etdm_driver;
-+ dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
-+
-+ dai->dapm_widgets = mtk_dai_etdm_widgets;
-+ dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
-+ dai->dapm_routes = mtk_dai_etdm_routes;
-+ dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
-+
-+ return 0;
-+}
+++ /dev/null
-From fc7776dee86bc07d22820a904760a95f49a2f12e Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:35 +0800
-Subject: [PATCH 3/9] ASoC: mediatek: mt7986: add platform driver
-
-Add mt7986 platform driver.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-4-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/Kconfig | 10 +
- sound/soc/mediatek/Makefile | 1 +
- sound/soc/mediatek/mt7986/Makefile | 8 +
- sound/soc/mediatek/mt7986/mt7986-afe-pcm.c | 622 +++++++++++++++++++++
- 4 files changed, 641 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/Makefile
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-pcm.c
-
---- a/sound/soc/mediatek/Kconfig
-+++ b/sound/soc/mediatek/Kconfig
-@@ -54,6 +54,16 @@ config SND_SOC_MT6797_MT6351
- Select Y if you have such device.
- If unsure select "N".
-
-+config SND_SOC_MT7986
-+ tristate "ASoC support for Mediatek MT7986 chip"
-+ depends on ARCH_MEDIATEK
-+ select SND_SOC_MEDIATEK
-+ help
-+ This adds ASoC platform driver support for MediaTek MT7986 chip
-+ that can be used with other codecs.
-+ Select Y if you have such device.
-+ If unsure select "N".
-+
- config SND_SOC_MT8173
- tristate "ASoC support for Mediatek MT8173 chip"
- depends on ARCH_MEDIATEK
---- a/sound/soc/mediatek/Makefile
-+++ b/sound/soc/mediatek/Makefile
-@@ -2,6 +2,7 @@
- obj-$(CONFIG_SND_SOC_MEDIATEK) += common/
- obj-$(CONFIG_SND_SOC_MT2701) += mt2701/
- obj-$(CONFIG_SND_SOC_MT6797) += mt6797/
-+obj-$(CONFIG_SND_SOC_MT7986) += mt7986/
- obj-$(CONFIG_SND_SOC_MT8173) += mt8173/
- obj-$(CONFIG_SND_SOC_MT8183) += mt8183/
- obj-$(CONFIG_SND_SOC_MT8186) += mt8186/
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/Makefile
-@@ -0,0 +1,8 @@
-+# SPDX-License-Identifier: GPL-2.0
-+
-+# platform driver
-+snd-soc-mt7986-afe-objs := \
-+ mt7986-afe-pcm.o \
-+ mt7986-dai-etdm.o
-+
-+obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-afe-pcm.c
-@@ -0,0 +1,622 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MediaTek ALSA SoC AFE platform driver for MT7986
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ * Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/pm_runtime.h>
-+
-+#include "mt7986-afe-common.h"
-+#include "mt7986-reg.h"
-+#include "../common/mtk-afe-platform-driver.h"
-+#include "../common/mtk-afe-fe-dai.h"
-+
-+enum {
-+ MTK_AFE_RATE_8K = 0,
-+ MTK_AFE_RATE_11K = 1,
-+ MTK_AFE_RATE_12K = 2,
-+ MTK_AFE_RATE_16K = 4,
-+ MTK_AFE_RATE_22K = 5,
-+ MTK_AFE_RATE_24K = 6,
-+ MTK_AFE_RATE_32K = 8,
-+ MTK_AFE_RATE_44K = 9,
-+ MTK_AFE_RATE_48K = 10,
-+ MTK_AFE_RATE_88K = 13,
-+ MTK_AFE_RATE_96K = 14,
-+ MTK_AFE_RATE_176K = 17,
-+ MTK_AFE_RATE_192K = 18,
-+};
-+
-+enum {
-+ CLK_INFRA_AUD_BUS_CK = 0,
-+ CLK_INFRA_AUD_26M_CK,
-+ CLK_INFRA_AUD_L_CK,
-+ CLK_INFRA_AUD_AUD_CK,
-+ CLK_INFRA_AUD_EG2_CK,
-+ CLK_NUM
-+};
-+
-+static const char *aud_clks[CLK_NUM] = {
-+ [CLK_INFRA_AUD_BUS_CK] = "aud_bus_ck",
-+ [CLK_INFRA_AUD_26M_CK] = "aud_26m_ck",
-+ [CLK_INFRA_AUD_L_CK] = "aud_l_ck",
-+ [CLK_INFRA_AUD_AUD_CK] = "aud_aud_ck",
-+ [CLK_INFRA_AUD_EG2_CK] = "aud_eg2_ck",
-+};
-+
-+unsigned int mt7986_afe_rate_transform(struct device *dev, unsigned int rate)
-+{
-+ switch (rate) {
-+ case 8000:
-+ return MTK_AFE_RATE_8K;
-+ case 11025:
-+ return MTK_AFE_RATE_11K;
-+ case 12000:
-+ return MTK_AFE_RATE_12K;
-+ case 16000:
-+ return MTK_AFE_RATE_16K;
-+ case 22050:
-+ return MTK_AFE_RATE_22K;
-+ case 24000:
-+ return MTK_AFE_RATE_24K;
-+ case 32000:
-+ return MTK_AFE_RATE_32K;
-+ case 44100:
-+ return MTK_AFE_RATE_44K;
-+ case 48000:
-+ return MTK_AFE_RATE_48K;
-+ case 88200:
-+ return MTK_AFE_RATE_88K;
-+ case 96000:
-+ return MTK_AFE_RATE_96K;
-+ case 176400:
-+ return MTK_AFE_RATE_176K;
-+ case 192000:
-+ return MTK_AFE_RATE_192K;
-+ default:
-+ dev_warn(dev, "%s(), rate %u invalid, using %d!!!\n",
-+ __func__, rate, MTK_AFE_RATE_48K);
-+ return MTK_AFE_RATE_48K;
-+ }
-+}
-+
-+static const struct snd_pcm_hardware mt7986_afe_hardware = {
-+ .info = SNDRV_PCM_INFO_MMAP |
-+ SNDRV_PCM_INFO_INTERLEAVED |
-+ SNDRV_PCM_INFO_MMAP_VALID,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
-+ SNDRV_PCM_FMTBIT_S24_LE |
-+ SNDRV_PCM_FMTBIT_S32_LE,
-+ .period_bytes_min = 256,
-+ .period_bytes_max = 4 * 48 * 1024,
-+ .periods_min = 2,
-+ .periods_max = 256,
-+ .buffer_bytes_max = 8 * 48 * 1024,
-+ .fifo_size = 0,
-+};
-+
-+static int mt7986_memif_fs(struct snd_pcm_substream *substream,
-+ unsigned int rate)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
-+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
-+
-+ return mt7986_afe_rate_transform(afe->dev, rate);
-+}
-+
-+static int mt7986_irq_fs(struct snd_pcm_substream *substream,
-+ unsigned int rate)
-+{
-+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
-+ struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
-+ struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
-+
-+ return mt7986_afe_rate_transform(afe->dev, rate);
-+}
-+
-+#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
-+ SNDRV_PCM_RATE_88200 |\
-+ SNDRV_PCM_RATE_96000 |\
-+ SNDRV_PCM_RATE_176400 |\
-+ SNDRV_PCM_RATE_192000)
-+
-+#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
-+ SNDRV_PCM_FMTBIT_S24_LE |\
-+ SNDRV_PCM_FMTBIT_S32_LE)
-+
-+static struct snd_soc_dai_driver mt7986_memif_dai_driver[] = {
-+ /* FE DAIs: memory intefaces to CPU */
-+ {
-+ .name = "DL1",
-+ .id = MT7986_MEMIF_DL1,
-+ .playback = {
-+ .stream_name = "DL1",
-+ .channels_min = 1,
-+ .channels_max = 2,
-+ .rates = MTK_PCM_RATES,
-+ .formats = MTK_PCM_FORMATS,
-+ },
-+ .ops = &mtk_afe_fe_ops,
-+ },
-+ {
-+ .name = "UL1",
-+ .id = MT7986_MEMIF_VUL12,
-+ .capture = {
-+ .stream_name = "UL1",
-+ .channels_min = 1,
-+ .channels_max = 2,
-+ .rates = MTK_PCM_RATES,
-+ .formats = MTK_PCM_FORMATS,
-+ },
-+ .ops = &mtk_afe_fe_ops,
-+ },
-+};
-+
-+static const struct snd_kcontrol_new o018_mix[] = {
-+ SOC_DAPM_SINGLE_AUTODISABLE("I150_Switch", AFE_CONN018_4, 22, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new o019_mix[] = {
-+ SOC_DAPM_SINGLE_AUTODISABLE("I151_Switch", AFE_CONN019_4, 23, 1, 0),
-+};
-+
-+static const struct snd_soc_dapm_widget mt7986_memif_widgets[] = {
-+ /* DL */
-+ SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),
-+ SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),
-+
-+ /* UL */
-+ SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,
-+ o018_mix, ARRAY_SIZE(o018_mix)),
-+ SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,
-+ o019_mix, ARRAY_SIZE(o019_mix)),
-+};
-+
-+static const struct snd_soc_dapm_route mt7986_memif_routes[] = {
-+ {"I032", NULL, "DL1"},
-+ {"I033", NULL, "DL1"},
-+ {"UL1", NULL, "O018"},
-+ {"UL1", NULL, "O019"},
-+ {"O018", "I150_Switch", "I150"},
-+ {"O019", "I151_Switch", "I151"},
-+};
-+
-+static const struct snd_soc_component_driver mt7986_afe_pcm_dai_component = {
-+ .name = "mt7986-afe-pcm-dai",
-+};
-+
-+static const struct mtk_base_memif_data memif_data[MT7986_MEMIF_NUM] = {
-+ [MT7986_MEMIF_DL1] = {
-+ .name = "DL1",
-+ .id = MT7986_MEMIF_DL1,
-+ .reg_ofs_base = AFE_DL0_BASE,
-+ .reg_ofs_cur = AFE_DL0_CUR,
-+ .reg_ofs_end = AFE_DL0_END,
-+ .reg_ofs_base_msb = AFE_DL0_BASE_MSB,
-+ .reg_ofs_cur_msb = AFE_DL0_CUR_MSB,
-+ .reg_ofs_end_msb = AFE_DL0_END_MSB,
-+ .fs_reg = AFE_DL0_CON0,
-+ .fs_shift = DL0_MODE_SFT,
-+ .fs_maskbit = DL0_MODE_MASK,
-+ .mono_reg = AFE_DL0_CON0,
-+ .mono_shift = DL0_MONO_SFT,
-+ .enable_reg = AFE_DL0_CON0,
-+ .enable_shift = DL0_ON_SFT,
-+ .hd_reg = AFE_DL0_CON0,
-+ .hd_shift = DL0_HD_MODE_SFT,
-+ .hd_align_reg = AFE_DL0_CON0,
-+ .hd_align_mshift = DL0_HALIGN_SFT,
-+ .pbuf_reg = AFE_DL0_CON0,
-+ .pbuf_shift = DL0_PBUF_SIZE_SFT,
-+ .minlen_reg = AFE_DL0_CON0,
-+ .minlen_shift = DL0_MINLEN_SFT,
-+ },
-+ [MT7986_MEMIF_VUL12] = {
-+ .name = "VUL12",
-+ .id = MT7986_MEMIF_VUL12,
-+ .reg_ofs_base = AFE_VUL0_BASE,
-+ .reg_ofs_cur = AFE_VUL0_CUR,
-+ .reg_ofs_end = AFE_VUL0_END,
-+ .reg_ofs_base_msb = AFE_VUL0_BASE_MSB,
-+ .reg_ofs_cur_msb = AFE_VUL0_CUR_MSB,
-+ .reg_ofs_end_msb = AFE_VUL0_END_MSB,
-+ .fs_reg = AFE_VUL0_CON0,
-+ .fs_shift = VUL0_MODE_SFT,
-+ .fs_maskbit = VUL0_MODE_MASK,
-+ .mono_reg = AFE_VUL0_CON0,
-+ .mono_shift = VUL0_MONO_SFT,
-+ .enable_reg = AFE_VUL0_CON0,
-+ .enable_shift = VUL0_ON_SFT,
-+ .hd_reg = AFE_VUL0_CON0,
-+ .hd_shift = VUL0_HD_MODE_SFT,
-+ .hd_align_reg = AFE_VUL0_CON0,
-+ .hd_align_mshift = VUL0_HALIGN_SFT,
-+ },
-+};
-+
-+static const struct mtk_base_irq_data irq_data[MT7986_IRQ_NUM] = {
-+ [MT7986_IRQ_0] = {
-+ .id = MT7986_IRQ_0,
-+ .irq_cnt_reg = AFE_IRQ0_MCU_CFG1,
-+ .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+ .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+ .irq_fs_reg = AFE_IRQ0_MCU_CFG0,
-+ .irq_fs_shift = IRQ_MCU_MODE_SFT,
-+ .irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+ .irq_en_reg = AFE_IRQ0_MCU_CFG0,
-+ .irq_en_shift = IRQ_MCU_ON_SFT,
-+ .irq_clr_reg = AFE_IRQ_MCU_CLR,
-+ .irq_clr_shift = IRQ0_MCU_CLR_SFT,
-+ },
-+ [MT7986_IRQ_1] = {
-+ .id = MT7986_IRQ_1,
-+ .irq_cnt_reg = AFE_IRQ1_MCU_CFG1,
-+ .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+ .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+ .irq_fs_reg = AFE_IRQ1_MCU_CFG0,
-+ .irq_fs_shift = IRQ_MCU_MODE_SFT,
-+ .irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+ .irq_en_reg = AFE_IRQ1_MCU_CFG0,
-+ .irq_en_shift = IRQ_MCU_ON_SFT,
-+ .irq_clr_reg = AFE_IRQ_MCU_CLR,
-+ .irq_clr_shift = IRQ1_MCU_CLR_SFT,
-+ },
-+ [MT7986_IRQ_2] = {
-+ .id = MT7986_IRQ_2,
-+ .irq_cnt_reg = AFE_IRQ2_MCU_CFG1,
-+ .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,
-+ .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,
-+ .irq_fs_reg = AFE_IRQ2_MCU_CFG0,
-+ .irq_fs_shift = IRQ_MCU_MODE_SFT,
-+ .irq_fs_maskbit = IRQ_MCU_MODE_MASK,
-+ .irq_en_reg = AFE_IRQ2_MCU_CFG0,
-+ .irq_en_shift = IRQ_MCU_ON_SFT,
-+ .irq_clr_reg = AFE_IRQ_MCU_CLR,
-+ .irq_clr_shift = IRQ2_MCU_CLR_SFT,
-+ },
-+};
-+
-+static bool mt7986_is_volatile_reg(struct device *dev, unsigned int reg)
-+{
-+ /*
-+ * Those auto-gen regs are read-only, so put it as volatile because
-+ * volatile registers cannot be cached, which means that they cannot
-+ * be set when power is off
-+ */
-+
-+ switch (reg) {
-+ case AFE_DL0_CUR_MSB:
-+ case AFE_DL0_CUR:
-+ case AFE_DL0_RCH_MON:
-+ case AFE_DL0_LCH_MON:
-+ case AFE_VUL0_CUR_MSB:
-+ case AFE_VUL0_CUR:
-+ case AFE_IRQ_MCU_STATUS:
-+ case AFE_MEMIF_RD_MON:
-+ case AFE_MEMIF_WR_MON:
-+ return true;
-+ default:
-+ return false;
-+ };
-+}
-+
-+static const struct regmap_config mt7986_afe_regmap_config = {
-+ .reg_bits = 32,
-+ .reg_stride = 4,
-+ .val_bits = 32,
-+ .volatile_reg = mt7986_is_volatile_reg,
-+ .max_register = AFE_MAX_REGISTER,
-+ .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),
-+};
-+
-+static int mt7986_init_clock(struct mtk_base_afe *afe)
-+{
-+ struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+ int ret, i;
-+
-+ afe_priv->clks = devm_kcalloc(afe->dev, CLK_NUM,
-+ sizeof(*afe_priv->clks), GFP_KERNEL);
-+ if (!afe_priv->clks)
-+ return -ENOMEM;
-+ afe_priv->num_clks = CLK_NUM;
-+
-+ for (i = 0; i < afe_priv->num_clks; i++)
-+ afe_priv->clks[i].id = aud_clks[i];
-+
-+ ret = devm_clk_bulk_get(afe->dev, afe_priv->num_clks, afe_priv->clks);
-+ if (ret)
-+ return dev_err_probe(afe->dev, ret, "Failed to get clocks\n");
-+
-+ return 0;
-+}
-+
-+static irqreturn_t mt7986_afe_irq_handler(int irq_id, void *dev)
-+{
-+ struct mtk_base_afe *afe = dev;
-+ struct mtk_base_afe_irq *irq;
-+ u32 mcu_en, status, status_mcu;
-+ int i, ret;
-+ irqreturn_t irq_ret = IRQ_HANDLED;
-+
-+ /* get irq that is sent to MCU */
-+ regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
-+
-+ ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
-+ /* only care IRQ which is sent to MCU */
-+ status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
-+
-+ if (ret || status_mcu == 0) {
-+ dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
-+ __func__, ret, status, mcu_en);
-+
-+ irq_ret = IRQ_NONE;
-+ goto err_irq;
-+ }
-+
-+ for (i = 0; i < MT7986_MEMIF_NUM; i++) {
-+ struct mtk_base_afe_memif *memif = &afe->memif[i];
-+
-+ if (!memif->substream)
-+ continue;
-+
-+ if (memif->irq_usage < 0)
-+ continue;
-+
-+ irq = &afe->irqs[memif->irq_usage];
-+
-+ if (status_mcu & (1 << irq->irq_data->irq_en_shift))
-+ snd_pcm_period_elapsed(memif->substream);
-+ }
-+
-+err_irq:
-+ /* clear irq */
-+ regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu);
-+
-+ return irq_ret;
-+}
-+
-+static int mt7986_afe_runtime_suspend(struct device *dev)
-+{
-+ struct mtk_base_afe *afe = dev_get_drvdata(dev);
-+ struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+
-+ if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
-+ goto skip_regmap;
-+
-+ /* disable clk*/
-+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0x3fff);
-+ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK, 0);
-+ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK, 0);
-+
-+ /* make sure all irq status are cleared, twice intended */
-+ regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
-+
-+skip_regmap:
-+ clk_bulk_disable_unprepare(afe_priv->num_clks, afe_priv->clks);
-+
-+ return 0;
-+}
-+
-+static int mt7986_afe_runtime_resume(struct device *dev)
-+{
-+ struct mtk_base_afe *afe = dev_get_drvdata(dev);
-+ struct mt7986_afe_private *afe_priv = afe->platform_priv;
-+ int ret;
-+
-+ ret = clk_bulk_prepare_enable(afe_priv->num_clks, afe_priv->clks);
-+ if (ret)
-+ return dev_err_probe(afe->dev, ret, "Failed to enable clocks\n");
-+
-+ if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
-+ return 0;
-+
-+ /* enable clk*/
-+ regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 0x3fff, 0);
-+ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_APLL2_EN_MASK,
-+ AUD_APLL2_EN);
-+ regmap_update_bits(afe->regmap, AUDIO_ENGEN_CON0, AUD_26M_EN_MASK,
-+ AUD_26M_EN);
-+
-+ return 0;
-+}
-+
-+static int mt7986_afe_component_probe(struct snd_soc_component *component)
-+{
-+ return mtk_afe_add_sub_dai_control(component);
-+}
-+
-+static const struct snd_soc_component_driver mt7986_afe_component = {
-+ .name = AFE_PCM_NAME,
-+ .probe = mt7986_afe_component_probe,
-+ .pointer = mtk_afe_pcm_pointer,
-+ .pcm_construct = mtk_afe_pcm_new,
-+};
-+
-+static int mt7986_dai_memif_register(struct mtk_base_afe *afe)
-+{
-+ struct mtk_base_afe_dai *dai;
-+
-+ dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
-+ if (!dai)
-+ return -ENOMEM;
-+
-+ list_add(&dai->list, &afe->sub_dais);
-+
-+ dai->dai_drivers = mt7986_memif_dai_driver;
-+ dai->num_dai_drivers = ARRAY_SIZE(mt7986_memif_dai_driver);
-+
-+ dai->dapm_widgets = mt7986_memif_widgets;
-+ dai->num_dapm_widgets = ARRAY_SIZE(mt7986_memif_widgets);
-+ dai->dapm_routes = mt7986_memif_routes;
-+ dai->num_dapm_routes = ARRAY_SIZE(mt7986_memif_routes);
-+
-+ return 0;
-+}
-+
-+typedef int (*dai_register_cb)(struct mtk_base_afe *);
-+static const dai_register_cb dai_register_cbs[] = {
-+ mt7986_dai_etdm_register,
-+ mt7986_dai_memif_register,
-+};
-+
-+static int mt7986_afe_pcm_dev_probe(struct platform_device *pdev)
-+{
-+ struct mtk_base_afe *afe;
-+ struct mt7986_afe_private *afe_priv;
-+ struct device *dev;
-+ int i, irq_id, ret;
-+
-+ afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
-+ if (!afe)
-+ return -ENOMEM;
-+ platform_set_drvdata(pdev, afe);
-+
-+ afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
-+ GFP_KERNEL);
-+ if (!afe->platform_priv)
-+ return -ENOMEM;
-+
-+ afe_priv = afe->platform_priv;
-+ afe->dev = &pdev->dev;
-+ dev = afe->dev;
-+
-+ afe->base_addr = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(afe->base_addr))
-+ return PTR_ERR(afe->base_addr);
-+
-+ /* initial audio related clock */
-+ ret = mt7986_init_clock(afe);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Cannot initialize clocks\n");
-+
-+ ret = devm_pm_runtime_enable(dev);
-+ if (ret)
-+ return ret;
-+
-+ /* enable clock for regcache get default value from hw */
-+ afe_priv->pm_runtime_bypass_reg_ctl = true;
-+ pm_runtime_get_sync(&pdev->dev);
-+
-+ afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
-+ &mt7986_afe_regmap_config);
-+
-+ pm_runtime_put_sync(&pdev->dev);
-+ if (IS_ERR(afe->regmap))
-+ return PTR_ERR(afe->regmap);
-+
-+ afe_priv->pm_runtime_bypass_reg_ctl = false;
-+
-+ /* init memif */
-+ afe->memif_size = MT7986_MEMIF_NUM;
-+ afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
-+ GFP_KERNEL);
-+ if (!afe->memif)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < afe->memif_size; i++) {
-+ afe->memif[i].data = &memif_data[i];
-+ afe->memif[i].irq_usage = -1;
-+ }
-+
-+ mutex_init(&afe->irq_alloc_lock);
-+
-+ /* irq initialize */
-+ afe->irqs_size = MT7986_IRQ_NUM;
-+ afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
-+ GFP_KERNEL);
-+ if (!afe->irqs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < afe->irqs_size; i++)
-+ afe->irqs[i].irq_data = &irq_data[i];
-+
-+ /* request irq */
-+ irq_id = platform_get_irq(pdev, 0);
-+ if (irq_id < 0) {
-+ ret = irq_id;
-+ return dev_err_probe(dev, ret, "No irq found\n");
-+ }
-+ ret = devm_request_irq(dev, irq_id, mt7986_afe_irq_handler,
-+ IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Failed to request irq for asys-isr\n");
-+
-+ /* init sub_dais */
-+ INIT_LIST_HEAD(&afe->sub_dais);
-+
-+ for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
-+ ret = dai_register_cbs[i](afe);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "DAI register failed, i: %d\n", i);
-+ }
-+
-+ /* init dai_driver and component_driver */
-+ ret = mtk_afe_combine_sub_dai(afe);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");
-+
-+ afe->mtk_afe_hardware = &mt7986_afe_hardware;
-+ afe->memif_fs = mt7986_memif_fs;
-+ afe->irq_fs = mt7986_irq_fs;
-+
-+ afe->runtime_resume = mt7986_afe_runtime_resume;
-+ afe->runtime_suspend = mt7986_afe_runtime_suspend;
-+
-+ /* register component */
-+ ret = devm_snd_soc_register_component(&pdev->dev,
-+ &mt7986_afe_component,
-+ NULL, 0);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Cannot register AFE component\n");
-+
-+ ret = devm_snd_soc_register_component(afe->dev,
-+ &mt7986_afe_pcm_dai_component,
-+ afe->dai_drivers,
-+ afe->num_dai_drivers);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Cannot register PCM DAI component\n");
-+
-+ return 0;
-+}
-+
-+static void mt7986_afe_pcm_dev_remove(struct platform_device *pdev)
-+{
-+ pm_runtime_disable(&pdev->dev);
-+ if (!pm_runtime_status_suspended(&pdev->dev))
-+ mt7986_afe_runtime_suspend(&pdev->dev);
-+}
-+
-+static const struct of_device_id mt7986_afe_pcm_dt_match[] = {
-+ { .compatible = "mediatek,mt7986-afe" },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mt7986_afe_pcm_dt_match);
-+
-+static const struct dev_pm_ops mt7986_afe_pm_ops = {
-+ SET_RUNTIME_PM_OPS(mt7986_afe_runtime_suspend,
-+ mt7986_afe_runtime_resume, NULL)
-+};
-+
-+static struct platform_driver mt7986_afe_pcm_driver = {
-+ .driver = {
-+ .name = "mt7986-audio",
-+ .of_match_table = mt7986_afe_pcm_dt_match,
-+ .pm = &mt7986_afe_pm_ops,
-+ },
-+ .probe = mt7986_afe_pcm_dev_probe,
-+ .remove_new = mt7986_afe_pcm_dev_remove,
-+};
-+module_platform_driver(mt7986_afe_pcm_driver);
-+
-+MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA MT7986");
-+MODULE_AUTHOR("Vic Wu <vic.wu@mediatek.com>");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From ddf6abc1c78072f8ccad59166be95f0ca5af8ca4 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:36 +0800
-Subject: [PATCH 4/9] ASoC: mediatek: mt7986: add machine driver with wm8960
-
-Add support for mt7986 board with wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-5-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/Kconfig | 10 ++
- sound/soc/mediatek/mt7986/Makefile | 1 +
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 196 ++++++++++++++++++++++
- 3 files changed, 207 insertions(+)
- create mode 100644 sound/soc/mediatek/mt7986/mt7986-wm8960.c
-
---- a/sound/soc/mediatek/Kconfig
-+++ b/sound/soc/mediatek/Kconfig
-@@ -64,6 +64,16 @@ config SND_SOC_MT7986
- Select Y if you have such device.
- If unsure select "N".
-
-+config SND_SOC_MT7986_WM8960
-+ tristate "ASoc Audio driver for MT7986 with WM8960 codec"
-+ depends on SND_SOC_MT7986 && I2C
-+ select SND_SOC_WM8960
-+ help
-+ This adds support for ASoC machine driver for MediaTek MT7986
-+ boards with the WM8960 codecs.
-+ Select Y if you have such device.
-+ If unsure select "N".
-+
- config SND_SOC_MT8173
- tristate "ASoC support for Mediatek MT8173 chip"
- depends on ARCH_MEDIATEK
---- a/sound/soc/mediatek/mt7986/Makefile
-+++ b/sound/soc/mediatek/mt7986/Makefile
-@@ -6,3 +6,4 @@ snd-soc-mt7986-afe-objs := \
- mt7986-dai-etdm.o
-
- obj-$(CONFIG_SND_SOC_MT7986) += snd-soc-mt7986-afe.o
-+obj-$(CONFIG_SND_SOC_MT7986_WM8960) += mt7986-wm8960.o
---- /dev/null
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -0,0 +1,196 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * mt7986-wm8960.c -- MT7986-WM8960 ALSA SoC machine driver
-+ *
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Authors: Vic Wu <vic.wu@mediatek.com>
-+ * Maso Huang <maso.huang@mediatek.com>
-+ */
-+
-+#include <linux/module.h>
-+#include <sound/soc.h>
-+
-+#include "mt7986-afe-common.h"
-+
-+struct mt7986_wm8960_priv {
-+ struct device_node *platform_node;
-+ struct device_node *codec_node;
-+};
-+
-+static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = {
-+ SND_SOC_DAPM_HP("Headphone", NULL),
-+ SND_SOC_DAPM_MIC("AMIC", NULL),
-+};
-+
-+static const struct snd_kcontrol_new mt7986_wm8960_controls[] = {
-+ SOC_DAPM_PIN_SWITCH("Headphone"),
-+ SOC_DAPM_PIN_SWITCH("AMIC"),
-+};
-+
-+SND_SOC_DAILINK_DEFS(playback,
-+ DAILINK_COMP_ARRAY(COMP_CPU("DL1")),
-+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
-+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+SND_SOC_DAILINK_DEFS(capture,
-+ DAILINK_COMP_ARRAY(COMP_CPU("UL1")),
-+ DAILINK_COMP_ARRAY(COMP_DUMMY()),
-+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+SND_SOC_DAILINK_DEFS(codec,
-+ DAILINK_COMP_ARRAY(COMP_CPU("ETDM")),
-+ DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "wm8960-hifi")),
-+ DAILINK_COMP_ARRAY(COMP_EMPTY()));
-+
-+static struct snd_soc_dai_link mt7986_wm8960_dai_links[] = {
-+ /* FE */
-+ {
-+ .name = "wm8960-playback",
-+ .stream_name = "wm8960-playback",
-+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
-+ SND_SOC_DPCM_TRIGGER_POST},
-+ .dynamic = 1,
-+ .dpcm_playback = 1,
-+ SND_SOC_DAILINK_REG(playback),
-+ },
-+ {
-+ .name = "wm8960-capture",
-+ .stream_name = "wm8960-capture",
-+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
-+ SND_SOC_DPCM_TRIGGER_POST},
-+ .dynamic = 1,
-+ .dpcm_capture = 1,
-+ SND_SOC_DAILINK_REG(capture),
-+ },
-+ /* BE */
-+ {
-+ .name = "wm8960-codec",
-+ .no_pcm = 1,
-+ .dai_fmt = SND_SOC_DAIFMT_I2S |
-+ SND_SOC_DAIFMT_NB_NF |
-+ SND_SOC_DAIFMT_CBS_CFS |
-+ SND_SOC_DAIFMT_GATED,
-+ .dpcm_playback = 1,
-+ .dpcm_capture = 1,
-+ SND_SOC_DAILINK_REG(codec),
-+ },
-+};
-+
-+static struct snd_soc_card mt7986_wm8960_card = {
-+ .name = "mt7986-wm8960",
-+ .owner = THIS_MODULE,
-+ .dai_link = mt7986_wm8960_dai_links,
-+ .num_links = ARRAY_SIZE(mt7986_wm8960_dai_links),
-+ .controls = mt7986_wm8960_controls,
-+ .num_controls = ARRAY_SIZE(mt7986_wm8960_controls),
-+ .dapm_widgets = mt7986_wm8960_widgets,
-+ .num_dapm_widgets = ARRAY_SIZE(mt7986_wm8960_widgets),
-+};
-+
-+static int mt7986_wm8960_machine_probe(struct platform_device *pdev)
-+{
-+ struct snd_soc_card *card = &mt7986_wm8960_card;
-+ struct snd_soc_dai_link *dai_link;
-+ struct device_node *platform, *codec;
-+ struct mt7986_wm8960_priv *priv;
-+ int ret, i;
-+
-+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ platform = of_get_child_by_name(pdev->dev.of_node, "platform");
-+
-+ if (platform) {
-+ priv->platform_node = of_parse_phandle(platform, "sound-dai", 0);
-+ of_node_put(platform);
-+
-+ if (!priv->platform_node) {
-+ dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n");
-+ return -EINVAL;
-+ }
-+ } else {
-+ dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
-+ return -EINVAL;
-+ }
-+
-+ for_each_card_prelinks(card, i, dai_link) {
-+ if (dai_link->platforms->name)
-+ continue;
-+ dai_link->platforms->of_node = priv->platform_node;
-+ }
-+
-+ card->dev = &pdev->dev;
-+
-+ codec = of_get_child_by_name(pdev->dev.of_node, "codec");
-+
-+ if (codec) {
-+ priv->codec_node = of_parse_phandle(codec, "sound-dai", 0);
-+ of_node_put(codec);
-+
-+ if (!priv->codec_node) {
-+ of_node_put(priv->platform_node);
-+ dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n");
-+ return -EINVAL;
-+ }
-+ } else {
-+ of_node_put(priv->platform_node);
-+ dev_err(&pdev->dev, "Property 'codec' missing or invalid\n");
-+ return -EINVAL;
-+ }
-+
-+ for_each_card_prelinks(card, i, dai_link) {
-+ if (dai_link->codecs->name)
-+ continue;
-+ dai_link->codecs->of_node = priv->codec_node;
-+ }
-+
-+ ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
-+ if (ret) {
-+ dev_err(&pdev->dev, "Failed to parse audio-routing: %d\n", ret);
-+ goto err_of_node_put;
-+ }
-+
-+ ret = devm_snd_soc_register_card(&pdev->dev, card);
-+ if (ret) {
-+ dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+ goto err_of_node_put;
-+ }
-+
-+err_of_node_put:
-+ of_node_put(priv->codec_node);
-+ of_node_put(priv->platform_node);
-+ return ret;
-+}
-+
-+static void mt7986_wm8960_machine_remove(struct platform_device *pdev)
-+{
-+ struct snd_soc_card *card = platform_get_drvdata(pdev);
-+ struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card);
-+
-+ of_node_put(priv->codec_node);
-+ of_node_put(priv->platform_node);
-+}
-+
-+static const struct of_device_id mt7986_wm8960_machine_dt_match[] = {
-+ {.compatible = "mediatek,mt7986-wm8960-sound"},
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, mt7986_wm8960_machine_dt_match);
-+
-+static struct platform_driver mt7986_wm8960_machine = {
-+ .driver = {
-+ .name = "mt7986-wm8960",
-+ .of_match_table = mt7986_wm8960_machine_dt_match,
-+ },
-+ .probe = mt7986_wm8960_machine_probe,
-+ .remove_new = mt7986_wm8960_machine_remove,
-+};
-+
-+module_platform_driver(mt7986_wm8960_machine);
-+
-+/* Module information */
-+MODULE_DESCRIPTION("MT7986 WM8960 ALSA SoC machine driver");
-+MODULE_AUTHOR("Vic Wu <vic.wu@mediatek.com>");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("mt7986 wm8960 soc card");
+++ /dev/null
-From 72469f950b629e57e60fbcbefed45e083619b986 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:37 +0800
-Subject: [PATCH 5/9] ASoC: dt-bindings: mediatek,mt7986-wm8960: add
- mt7986-wm8960 document
-
-Add document for mt7986 board with wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-6-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../sound/mediatek,mt7986-wm8960.yaml | 67 +++++++++++++++++++
- 1 file changed, 67 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-wm8960.yaml
-@@ -0,0 +1,67 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/sound/mediatek,mt7986-wm8960.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek MT7986 sound card with WM8960 codec
-+
-+maintainers:
-+ - Maso Huang <maso.huang@mediatek.com>
-+
-+allOf:
-+ - $ref: sound-card-common.yaml#
-+
-+properties:
-+ compatible:
-+ const: mediatek,mt7986-wm8960-sound
-+
-+ platform:
-+ type: object
-+ additionalProperties: false
-+ properties:
-+ sound-dai:
-+ description: The phandle of MT7986 platform.
-+ maxItems: 1
-+ required:
-+ - sound-dai
-+
-+ codec:
-+ type: object
-+ additionalProperties: false
-+ properties:
-+ sound-dai:
-+ description: The phandle of wm8960 codec.
-+ maxItems: 1
-+ required:
-+ - sound-dai
-+
-+unevaluatedProperties: false
-+
-+required:
-+ - compatible
-+ - audio-routing
-+ - platform
-+ - codec
-+
-+examples:
-+ - |
-+ sound {
-+ compatible = "mediatek,mt7986-wm8960-sound";
-+ model = "mt7986-wm8960";
-+ audio-routing =
-+ "Headphone", "HP_L",
-+ "Headphone", "HP_R",
-+ "LINPUT1", "AMIC",
-+ "RINPUT1", "AMIC";
-+
-+ platform {
-+ sound-dai = <&afe>;
-+ };
-+
-+ codec {
-+ sound-dai = <&wm8960>;
-+ };
-+ };
-+
-+...
+++ /dev/null
-From d16202eb38585adbc16e32d11188dbc2127015de Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 17 Aug 2023 18:13:38 +0800
-Subject: [PATCH 6/9] ASoC: dt-bindings: mediatek,mt7986-afe: add audio afe
- document
-
-Add mt7986 audio afe document.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20230817101338.18782-7-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- .../bindings/sound/mediatek,mt7986-afe.yaml | 160 ++++++++++++++++++
- 1 file changed, 160 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml
-@@ -0,0 +1,160 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/sound/mediatek,mt7986-afe.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek AFE PCM controller for MT7986
-+
-+maintainers:
-+ - Maso Huang <maso.huang@mediatek.com>
-+
-+properties:
-+ compatible:
-+ oneOf:
-+ - const: mediatek,mt7986-afe
-+ - items:
-+ - enum:
-+ - mediatek,mt7981-afe
-+ - mediatek,mt7988-afe
-+ - const: mediatek,mt7986-afe
-+
-+ reg:
-+ maxItems: 1
-+
-+ interrupts:
-+ maxItems: 1
-+
-+ clocks:
-+ minItems: 5
-+ items:
-+ - description: audio bus clock
-+ - description: audio 26M clock
-+ - description: audio intbus clock
-+ - description: audio hopping clock
-+ - description: audio pll clock
-+ - description: mux for pcm_mck
-+ - description: audio i2s/pcm mck
-+
-+ clock-names:
-+ minItems: 5
-+ items:
-+ - const: bus_ck
-+ - const: 26m_ck
-+ - const: l_ck
-+ - const: aud_ck
-+ - const: eg2_ck
-+ - const: sel
-+ - const: i2s_m
-+
-+required:
-+ - compatible
-+ - reg
-+ - interrupts
-+ - clocks
-+ - clock-names
-+
-+allOf:
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ const: mediatek,mt7986-afe
-+ then:
-+ properties:
-+ clocks:
-+ items:
-+ - description: audio bus clock
-+ - description: audio 26M clock
-+ - description: audio intbus clock
-+ - description: audio hopping clock
-+ - description: audio pll clock
-+ clock-names:
-+ items:
-+ - const: bus_ck
-+ - const: 26m_ck
-+ - const: l_ck
-+ - const: aud_ck
-+ - const: eg2_ck
-+
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ const: mediatek,mt7981-afe
-+ then:
-+ properties:
-+ clocks:
-+ items:
-+ - description: audio bus clock
-+ - description: audio 26M clock
-+ - description: audio intbus clock
-+ - description: audio hopping clock
-+ - description: audio pll clock
-+ - description: mux for pcm_mck
-+ clock-names:
-+ items:
-+ - const: bus_ck
-+ - const: 26m_ck
-+ - const: l_ck
-+ - const: aud_ck
-+ - const: eg2_ck
-+ - const: sel
-+
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ const: mediatek,mt7988-afe
-+ then:
-+ properties:
-+ clocks:
-+ items:
-+ - description: audio bus clock
-+ - description: audio 26M clock
-+ - description: audio intbus clock
-+ - description: audio hopping clock
-+ - description: audio pll clock
-+ - description: mux for pcm_mck
-+ - description: audio i2s/pcm mck
-+ clock-names:
-+ items:
-+ - const: bus_ck
-+ - const: 26m_ck
-+ - const: l_ck
-+ - const: aud_ck
-+ - const: eg2_ck
-+ - const: sel
-+ - const: i2s_m
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ #include <dt-bindings/interrupt-controller/arm-gic.h>
-+ #include <dt-bindings/interrupt-controller/irq.h>
-+ #include <dt-bindings/clock/mt7986-clk.h>
-+
-+ afe@11210000 {
-+ compatible = "mediatek,mt7986-afe";
-+ reg = <0x11210000 0x9000>;
-+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>,
-+ <&infracfg_ao CLK_INFRA_AUD_26M_CK>,
-+ <&infracfg_ao CLK_INFRA_AUD_L_CK>,
-+ <&infracfg_ao CLK_INFRA_AUD_AUD_CK>,
-+ <&infracfg_ao CLK_INFRA_AUD_EG2_CK>;
-+ clock-names = "bus_ck",
-+ "26m_ck",
-+ "l_ck",
-+ "aud_ck",
-+ "eg2_ck";
-+ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
-+ <&topckgen CLK_TOP_AUD_L_SEL>,
-+ <&topckgen CLK_TOP_A_TUNER_SEL>;
-+ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
-+ <&apmixedsys CLK_APMIXED_APLL2>,
-+ <&topckgen CLK_TOP_APLL2_D4>;
-+ };
-+
-+...
+++ /dev/null
-From f3f0934e5c7b9c16e0cb2435be3555382e6293ad Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:17 +0800
-Subject: [PATCH 7/9] ASoC: mediatek: mt7986: drop the remove callback of
- mt7986_wm8960
-
-Drop the remove callback of mt7986_wm8960.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-2-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 10 ----------
- 1 file changed, 10 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -163,15 +163,6 @@ err_of_node_put:
- return ret;
- }
-
--static void mt7986_wm8960_machine_remove(struct platform_device *pdev)
--{
-- struct snd_soc_card *card = platform_get_drvdata(pdev);
-- struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card);
--
-- of_node_put(priv->codec_node);
-- of_node_put(priv->platform_node);
--}
--
- static const struct of_device_id mt7986_wm8960_machine_dt_match[] = {
- {.compatible = "mediatek,mt7986-wm8960-sound"},
- { /* sentinel */ }
-@@ -184,7 +175,6 @@ static struct platform_driver mt7986_wm8
- .of_match_table = mt7986_wm8960_machine_dt_match,
- },
- .probe = mt7986_wm8960_machine_probe,
-- .remove_new = mt7986_wm8960_machine_remove,
- };
-
- module_platform_driver(mt7986_wm8960_machine);
+++ /dev/null
-From 98b8fb2cb4fcab1903d0baf611bf0c3f822a08dc Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:18 +0800
-Subject: [PATCH 8/9] ASoC: mediatek: mt7986: remove the mt7986_wm8960_priv
- structure
-
-Remove the mt7986_wm8960_priv structure.
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-3-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 33 +++++++++--------------
- 1 file changed, 12 insertions(+), 21 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -12,11 +12,6 @@
-
- #include "mt7986-afe-common.h"
-
--struct mt7986_wm8960_priv {
-- struct device_node *platform_node;
-- struct device_node *codec_node;
--};
--
- static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = {
- SND_SOC_DAPM_HP("Headphone", NULL),
- SND_SOC_DAPM_MIC("AMIC", NULL),
-@@ -92,20 +87,18 @@ static int mt7986_wm8960_machine_probe(s
- struct snd_soc_card *card = &mt7986_wm8960_card;
- struct snd_soc_dai_link *dai_link;
- struct device_node *platform, *codec;
-- struct mt7986_wm8960_priv *priv;
-+ struct device_node *platform_dai_node, *codec_dai_node;
- int ret, i;
-
-- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
-- if (!priv)
-- return -ENOMEM;
-+ card->dev = &pdev->dev;
-
- platform = of_get_child_by_name(pdev->dev.of_node, "platform");
-
- if (platform) {
-- priv->platform_node = of_parse_phandle(platform, "sound-dai", 0);
-+ platform_dai_node = of_parse_phandle(platform, "sound-dai", 0);
- of_node_put(platform);
-
-- if (!priv->platform_node) {
-+ if (!platform_dai_node) {
- dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n");
- return -EINVAL;
- }
-@@ -117,24 +110,22 @@ static int mt7986_wm8960_machine_probe(s
- for_each_card_prelinks(card, i, dai_link) {
- if (dai_link->platforms->name)
- continue;
-- dai_link->platforms->of_node = priv->platform_node;
-+ dai_link->platforms->of_node = platform_dai_node;
- }
-
-- card->dev = &pdev->dev;
--
- codec = of_get_child_by_name(pdev->dev.of_node, "codec");
-
- if (codec) {
-- priv->codec_node = of_parse_phandle(codec, "sound-dai", 0);
-+ codec_dai_node = of_parse_phandle(codec, "sound-dai", 0);
- of_node_put(codec);
-
-- if (!priv->codec_node) {
-- of_node_put(priv->platform_node);
-+ if (!codec_dai_node) {
-+ of_node_put(platform_dai_node);
- dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n");
- return -EINVAL;
- }
- } else {
-- of_node_put(priv->platform_node);
-+ of_node_put(platform_dai_node);
- dev_err(&pdev->dev, "Property 'codec' missing or invalid\n");
- return -EINVAL;
- }
-@@ -142,7 +133,7 @@ static int mt7986_wm8960_machine_probe(s
- for_each_card_prelinks(card, i, dai_link) {
- if (dai_link->codecs->name)
- continue;
-- dai_link->codecs->of_node = priv->codec_node;
-+ dai_link->codecs->of_node = codec_dai_node;
- }
-
- ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
-@@ -158,8 +149,8 @@ static int mt7986_wm8960_machine_probe(s
- }
-
- err_of_node_put:
-- of_node_put(priv->codec_node);
-- of_node_put(priv->platform_node);
-+ of_node_put(platform_dai_node);
-+ of_node_put(codec_dai_node);
- return ret;
- }
-
+++ /dev/null
-From 4e229f4264f4be7a6a554487714c0913ef59cf7f Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Tue, 24 Oct 2023 11:50:19 +0800
-Subject: [PATCH 9/9] ASoC: mediatek: mt7986: add sample rate checker
-
-mt7986 only supports 8/12/16/24/32/48/96/192 kHz
-
-Signed-off-by: Maso Huang <maso.huang@mediatek.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://lore.kernel.org/r/20231024035019.11732-4-maso.huang@mediatek.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 23 +++++++++++++++++----
- 1 file changed, 19 insertions(+), 4 deletions(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
-@@ -237,12 +237,27 @@ static int mtk_dai_etdm_hw_params(struct
- struct snd_pcm_hw_params *params,
- struct snd_soc_dai *dai)
- {
-+ unsigned int rate = params_rate(params);
- struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
-
-- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
-- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
--
-- return 0;
-+ switch (rate) {
-+ case 8000:
-+ case 12000:
-+ case 16000:
-+ case 24000:
-+ case 32000:
-+ case 48000:
-+ case 96000:
-+ case 192000:
-+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
-+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
-+ return 0;
-+ default:
-+ dev_err(afe->dev,
-+ "Sample rate %d invalid. Supported rates: 8/12/16/24/32/48/96/192 kHz\n",
-+ rate);
-+ return -EINVAL;
-+ }
- }
-
- static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
+++ /dev/null
-From e4cde335d1771863a60b6931e51357b8470e85c4 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sun, 10 Dec 2023 22:41:39 +0000
-Subject: [PATCH] ASoC: mediatek: mt7986: silence error in case of
- -EPROBE_DEFER
-
-If probe is defered no error should be printed. Mute it.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- sound/soc/mediatek/mt7986/mt7986-wm8960.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
-@@ -144,7 +144,9 @@ static int mt7986_wm8960_machine_probe(s
-
- ret = devm_snd_soc_register_card(&pdev->dev, card);
- if (ret) {
-- dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
-+
- goto err_of_node_put;
- }
-
+++ /dev/null
-From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 7 Sep 2023 10:54:37 +0800
-Subject: [PATCH] arm64: dts: mt7986: add afe
-
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 23 +++++++++++
- 1 files changed, 23 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -248,6 +248,28 @@
- status = "disabled";
- };
-
-+ afe: audio-controller@11210000 {
-+ compatible = "mediatek,mt7986-afe";
-+ reg = <0 0x11210000 0 0x9000>;
-+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
-+ <&infracfg CLK_INFRA_AUD_26M_CK>,
-+ <&infracfg CLK_INFRA_AUD_L_CK>,
-+ <&infracfg CLK_INFRA_AUD_AUD_CK>,
-+ <&infracfg CLK_INFRA_AUD_EG2_CK>;
-+ clock-names = "aud_bus_ck",
-+ "aud_26m_ck",
-+ "aud_l_ck",
-+ "aud_aud_ck",
-+ "aud_eg2_ck";
-+ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
-+ <&topckgen CLK_TOP_AUD_L_SEL>,
-+ <&topckgen CLK_TOP_A_TUNER_SEL>;
-+ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
-+ <&apmixedsys CLK_APMIXED_APLL2>,
-+ <&topckgen CLK_TOP_APLL2_D4>;
-+ };
-+
- pwm: pwm@10048000 {
- compatible = "mediatek,mt7986-pwm";
- reg = <0 0x10048000 0 0x1000>;
+++ /dev/null
-From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
-From: Maso Huang <maso.huang@mediatek.com>
-Date: Thu, 7 Sep 2023 10:54:37 +0800
-Subject: [PATCH] arm64: dts: mt7986: add sound wm8960
-
----
- .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 39 +++++++++++++++++++
- 1 files changed, 39 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts
-@@ -4,6 +4,35 @@
-
- / {
- compatible = "mediatek,mt7986a-rfb-snand";
-+
-+ sound_wm8960 {
-+ compatible = "mediatek,mt7986-wm8960-sound";
-+ audio-routing = "Headphone", "HP_L",
-+ "Headphone", "HP_R",
-+ "LINPUT1", "AMIC",
-+ "RINPUT1", "AMIC";
-+
-+ status = "okay";
-+
-+ platform {
-+ sound-dai = <&afe>;
-+ };
-+
-+ codec {
-+ sound-dai = <&wm8960>;
-+ };
-+ };
-+};
-+
-+&i2c0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c_pins>;
-+ status = "okay";
-+
-+ wm8960: wm8960@1a {
-+ compatible = "wlf,wm8960";
-+ reg = <0x1a>;
-+ };
- };
-
- &spi0 {
-@@ -50,3 +79,13 @@
- &wifi {
- mediatek,mtd-eeprom = <&factory 0>;
- };
-+
-+&pio {
-+ i2c_pins: i2c-pins-3-4 {
-+ mux {
-+ function = "i2c";
-+ groups = "i2c";
-+ };
-+ };
-+};
-+
+++ /dev/null
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-respeaker-2mics.dtso
-@@ -0,0 +1,62 @@
-+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-+/*
-+ * Copyright (C) 2023 MediaTek Inc.
-+ * Author: Maso Huang <Maso.Huang@mediatek.com>
-+ */
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
-+
-+ fragment@0 {
-+ target-path = "/";
-+ __overlay__ {
-+ sound_wm8960 {
-+ compatible = "mediatek,mt7986-wm8960-sound";
-+ audio-routing = "Headphone", "HP_L",
-+ "Headphone", "HP_R",
-+ "LINPUT1", "AMIC",
-+ "RINPUT1", "AMIC";
-+
-+ status = "okay";
-+
-+ platform {
-+ sound-dai = <&afe>;
-+ };
-+
-+ codec {
-+ sound-dai = <&wm8960>;
-+ };
-+ };
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&i2c0>;
-+ __overlay__ {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&i2c_pins>;
-+ clock-frequency = <400000>;
-+ status = "okay";
-+
-+ wm8960: wm8960@1a {
-+ compatible = "wlf,wm8960";
-+ reg = <0x1a>;
-+ };
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&pio>;
-+ __overlay__ {
-+ i2c_pins: i2c-pins-3-4 {
-+ mux {
-+ function = "i2c";
-+ groups = "i2c";
-+ };
-+ };
-+ };
-+ };
-+};
---- a/arch/arm64/boot/dts/mediatek/Makefile
-+++ b/arch/arm64/boot/dts/mediatek/Makefile
-@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-b
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
-+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-respeaker-2mics.dtbo
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
- dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -312,7 +312,7 @@
- /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
- * SATA functions. i.e. output-high: PCIe, output-low: SATA
- */
-- asm_sel {
-+ asmsel: asm_sel {
- gpio-hog;
- gpios = <90 GPIO_ACTIVE_HIGH>;
- output-high;
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "bananapi,bpi-r64", "mediatek,mt7622";
-+
-+ fragment@0 {
-+ target = <&asmsel>;
-+ __overlay__ {
-+ gpios = <90 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+
-+ fragment@1 {
-+ target = <&sata>;
-+ __overlay__ {
-+ status = "okay";
-+ };
-+ };
-+
-+ fragment@2 {
-+ target = <&sata_phy>;
-+ __overlay__ {
-+ status = "okay";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso
-@@ -0,0 +1,17 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+/dts-v1/;
-+/plugin/;
-+
-+/ {
-+ compatible = "bananapi,bpi-r64", "mediatek,mt7622";
-+
-+ fragment@0 {
-+ target = <&asmsel>;
-+ __overlay__ {
-+ gpios = <90 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+};
+++ /dev/null
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
-
- endchoice
-
-+config CMDLINE_OVERRIDE
-+ bool "Use alternative cmdline from device tree"
-+ help
-+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+ be used, this is not a good option for kernels that are shared across
-+ devices. This setting enables using "chosen/cmdline-override" as the
-+ cmdline if it exists in the device tree.
-+
- config CMDLINE
- string "Default kernel command string"
- default ""
---- a/drivers/of/fdt.c
-+++ b/drivers/of/fdt.c
-@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha
- if (p != NULL && l > 0)
- strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
-
-+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
-+ * device tree option of chosen/bootargs-override. This is
-+ * helpful on boards where u-boot sets bootargs, and is unable
-+ * to be modified.
-+ */
-+#ifdef CONFIG_CMDLINE_OVERRIDE
-+ p = of_get_flat_dt_prop(node, "bootargs-override", &l);
-+ if (p != NULL && l > 0)
-+ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
-+#endif
-+
- handle_cmdline:
- /*
- * CONFIG_CMDLINE is meant to be a default in case nothing else
---- a/arch/arm64/Kconfig
-+++ b/arch/arm64/Kconfig
-@@ -2240,6 +2240,14 @@ config CMDLINE_FORCE
-
- endchoice
-
-+config CMDLINE_OVERRIDE
-+ bool "Use alternative cmdline from device tree"
-+ help
-+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+ be used, this is not a good option for kernels that are shared across
-+ devices. This setting enables using "chosen/cmdline-override" as the
-+ cmdline if it exists in the device tree.
-+
- config EFI_STUB
- bool
-
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -639,5 +639,28 @@
- };
-
- &wmac {
-+ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0
-+ 0x0 0x0 0x0 0x0
-+ 0x0 0x0 0x0 0x0
-+ 0x0 0x44000020 0x0 0x10002000
-+ 0x4400 0x4000000 0x0 0x0
-+ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600
-+ 0x41c4 0x26000000 0xc0c52600 0x0
-+ 0x0 0x0 0x0 0x0
-+ 0x0 0x0 0x0 0x0
-+ 0x0 0x0 0x0 0x0
-+ 0x0 0x0 0x0 0x0
-+ 0x0 0x0 0x0 0xc6c6
-+ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182
-+ 0x83838382 0x0 0x0 0x0
-+ 0x0 0x0 0x0 0x0
-+ 0x84002e00 0x90000087 0x8a000000 0x0
-+ 0x0 0x0 0x0 0x0
-+ 0x0 0x0 0x0 0x0
-+ 0xb000009 0x0 0x0 0x0
-+ 0x0 0x0 0x0 0x0
-+ 0x0 0x0 0x0 0x0
-+ 0x0 0x0 0x0 0x7707>;
-+
- status = "okay";
- };
+++ /dev/null
---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
-@@ -32,6 +32,9 @@
- chosen {
- stdout-path = "serial0:115200n8";
- bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
-+ rootdisk-emmc = <&emmc_rootfs>;
-+ rootdisk-sd = <&sd_rootfs>;
-+ rootdisk-snfi = <&ubi_rootfs>;
- };
-
- cpus {
-@@ -233,6 +236,26 @@
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
- non-removable;
-+
-+ card@0 {
-+ compatible = "mmc-card";
-+ reg = <0>;
-+
-+ block {
-+ compatible = "block-device";
-+ partitions {
-+ block-partition-env {
-+ partname = "ubootenv";
-+ nvmem-layout {
-+ compatible = "u-boot,env-layout";
-+ };
-+ };
-+ emmc_rootfs: block-partition-production {
-+ partname = "production";
-+ };
-+ };
-+ };
-+ };
- };
-
- &mmc1 {
-@@ -249,6 +272,26 @@
- vqmmc-supply = <®_3p3v>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-+
-+ card@0 {
-+ compatible = "mmc-card";
-+ reg = <0>;
-+
-+ block {
-+ compatible = "block-device";
-+ partitions {
-+ block-partition-env {
-+ partname = "ubootenv";
-+ nvmem-layout {
-+ compatible = "u-boot,env-layout";
-+ };
-+ };
-+ sd_rootfs: block-partition-production {
-+ partname = "production";
-+ };
-+ };
-+ };
-+ };
- };
-
- &nandc {
-@@ -283,14 +326,29 @@
- };
-
- partition@80000 {
-- label = "fip";
-- reg = <0x80000 0x200000>;
-- read-only;
-- };
--
-- ubi: partition@280000 {
- label = "ubi";
-- reg = <0x280000 0x7d80000>;
-+ reg = <0x80000 0x7f80000>;
-+ compatible = "linux,ubi";
-+
-+ volumes {
-+ ubi-volume-ubootenv {
-+ volname = "ubootenv";
-+ nvmem-layout {
-+ compatible = "u-boot,env-redundant-bool-layout";
-+ };
-+ };
-+
-+ ubi-volume-ubootenv2 {
-+ volname = "ubootenv2";
-+ nvmem-layout {
-+ compatible = "u-boot,env-redundant-bool-layout";
-+ };
-+ };
-+
-+ ubi_rootfs: ubi-volume-fit {
-+ volname = "fit";
-+ };
-+ };
- };
- };
- };
+++ /dev/null
---- a/drivers/spi/spi-mt65xx.c
-+++ b/drivers/spi/spi-mt65xx.c
-@@ -1225,8 +1225,15 @@ static int mtk_spi_probe(struct platform
- if (ret < 0)
- return dev_err_probe(dev, ret, "failed to enable hclk\n");
-
-+ ret = clk_prepare_enable(mdata->sel_clk);
-+ if (ret < 0) {
-+ clk_disable_unprepare(mdata->spi_hclk);
-+ return dev_err_probe(dev, ret, "failed to enable sel_clk\n");
-+ }
-+
- ret = clk_prepare_enable(mdata->spi_clk);
- if (ret < 0) {
-+ clk_disable_unprepare(mdata->sel_clk);
- clk_disable_unprepare(mdata->spi_hclk);
- return dev_err_probe(dev, ret, "failed to enable spi_clk\n");
- }
+++ /dev/null
-From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001
-Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sun, 12 Mar 2023 16:40:31 +0100
-Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename
- mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region
-
-This is a preliminary patch to move wed ilm/dlm and cpuboot properties in
-dedicated dts nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -234,8 +234,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we
- }
-
- static int
--mtk_wed_get_memory_region(struct mtk_wed_hw *hw, int index,
-- struct mtk_wed_wo_memory_region *region)
-+mtk_wed_get_reserved_memory_region(struct mtk_wed_hw *hw, int index,
-+ struct mtk_wed_wo_memory_region *region)
- {
- struct reserved_mem *rmem;
- struct device_node *np;
-@@ -321,7 +321,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- if (index < 0)
- continue;
-
-- ret = mtk_wed_get_memory_region(wo->hw, index, &mem_region[i]);
-+ ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
- if (ret)
- return ret;
- }
+++ /dev/null
-From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001
-Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sat, 11 Mar 2023 16:32:41 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++----------
- 1 file changed, 11 insertions(+), 10 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -121,12 +121,6 @@
- reg = <0 0x151f8000 0 0x2000>;
- no-map;
- };
--
-- wo_boot: wo-boot@15194000 {
-- reg = <0 0x15194000 0 0x1000>;
-- no-map;
-- };
--
- };
-
- timer {
-@@ -540,10 +534,11 @@
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
-- <&wo_data>, <&wo_boot>;
-+ <&wo_data>;
- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-- "wo-data", "wo-boot";
-+ "wo-data";
- mediatek,wo-ccif = <&wo_ccif0>;
-+ mediatek,wo-cpuboot = <&wo_cpuboot>;
- };
-
- wed1: wed@15011000 {
-@@ -553,10 +548,11 @@
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
-- <&wo_data>, <&wo_boot>;
-+ <&wo_data>;
- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-- "wo-data", "wo-boot";
-+ "wo-data";
- mediatek,wo-ccif = <&wo_ccif1>;
-+ mediatek,wo-cpuboot = <&wo_cpuboot>;
- };
-
- wo_ccif0: syscon@151a5000 {
-@@ -573,6 +569,11 @@
- interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- };
-
-+ wo_cpuboot: syscon@15194000 {
-+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
-+ reg = <0 0x15194000 0 0x1000>;
-+ };
-+
- eth: ethernet@15100000 {
- compatible = "mediatek,mt7986-eth";
- reg = <0 0x15100000 0 0x80000>;
+++ /dev/null
-From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001
-Message-Id: <f292d1bf83ec160bef2532b58aa08f5b71041923.1678716918.git.lorenzo@kernel.org>
-In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sat, 11 Mar 2023 18:13:04 +0100
-Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a
- dedicated dts node
-
-Since the cpuboot memory region is not part of the RAM SoC, move cpuboot
-in a deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where cpuboot was
-defined as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++----
- drivers/net/ethernet/mediatek/mtk_wed_wo.h | 3 +-
- 2 files changed, 30 insertions(+), 7 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -34,12 +34,23 @@ static struct mtk_wed_wo_memory_region m
-
- static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
- {
-- return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+ u32 val;
-+
-+ if (!wo->boot_regmap)
-+ return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+
-+ if (regmap_read(wo->boot_regmap, reg, &val))
-+ val = ~0;
-+
-+ return val;
- }
-
- static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
- {
-- writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
-+ if (wo->boot_regmap)
-+ regmap_write(wo->boot_regmap, reg, val);
-+ else
-+ writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
- }
-
- static struct sk_buff *
-@@ -313,6 +324,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- u32 val, boot_cr;
- int ret, i;
-
-+ wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
-+ "mediatek,wo-cpuboot");
-+
- /* load firmware region metadata */
- for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
- int index = of_property_match_string(wo->hw->node,
-@@ -321,6 +335,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- if (index < 0)
- continue;
-
-+ if (index == MTK_WED_WO_REGION_BOOT && !IS_ERR(wo->boot_regmap))
-+ continue;
-+
- ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
- if (ret)
- return ret;
---- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
-@@ -231,6 +231,7 @@ struct mtk_wed_wo_queue {
- struct mtk_wed_wo {
- struct mtk_wed_hw *hw;
-
-+ struct regmap *boot_regmap;
- struct mtk_wed_wo_queue q_tx;
- struct mtk_wed_wo_queue q_rx;
-
+++ /dev/null
-From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001
-Message-Id: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Sun, 12 Mar 2023 18:51:47 +0100
-Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts
- node
-
-Since the ilm memory region is not part of the RAM SoC, move ilm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where ilm was defined
-as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++---
- 1 file changed, 49 insertions(+), 6 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -316,6 +316,39 @@ next:
- }
-
- static int
-+mtk_wed_mcu_load_ilm(struct mtk_wed_wo *wo)
-+{
-+ struct mtk_wed_wo_memory_region *ilm_region;
-+ struct resource res;
-+ struct device_node *np;
-+ int ret;
-+
-+ np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0);
-+ if (!np)
-+ return 0;
-+
-+ ret = of_address_to_resource(np, 0, &res);
-+ of_node_put(np);
-+
-+ if (ret < 0)
-+ return ret;
-+
-+ ilm_region = &mem_region[MTK_WED_WO_REGION_ILM];
-+ ilm_region->phy_addr = res.start;
-+ ilm_region->size = resource_size(&res);
-+ ilm_region->addr = devm_ioremap(wo->hw->dev, res.start,
-+ resource_size(&res));
-+
-+ if (!IS_ERR(ilm_region->addr))
-+ return 0;
-+
-+ ret = PTR_ERR(ilm_region->addr);
-+ ilm_region->addr = NULL;
-+
-+ return ret;
-+}
-+
-+static int
- mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
- {
- const struct mtk_wed_fw_trailer *trailer;
-@@ -324,14 +357,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
- u32 val, boot_cr;
- int ret, i;
-
-+ mtk_wed_mcu_load_ilm(wo);
- wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
- "mediatek,wo-cpuboot");
-
- /* load firmware region metadata */
- for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
-- int index = of_property_match_string(wo->hw->node,
-- "memory-region-names",
-- mem_region[i].name);
-+ int index;
-+
-+ if (mem_region[i].addr)
-+ continue;
-+
-+ index = of_property_match_string(wo->hw->node,
-+ "memory-region-names",
-+ mem_region[i].name);
- if (index < 0)
- continue;
-
+++ /dev/null
-From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001
-Message-Id: <b74ba226be2c45091b93bd49192bdd6d2178729e.1678718888.git.lorenzo@kernel.org>
-In-Reply-To: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-References: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:45:16 +0100
-Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts
- node
-
-Since the dlm memory region is not part of the RAM SoC, move dlm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-Keep backward-compatibility with older dts version where dlm was defined
-as reserved-memory child node.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1320,6 +1320,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
- struct device_node *np;
- int index;
-
-+ np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0);
-+ if (np) {
-+ struct resource res;
-+ int ret;
-+
-+ ret = of_address_to_resource(np, 0, &res);
-+ of_node_put(np);
-+
-+ if (ret < 0)
-+ return ret;
-+
-+ dev->rro.miod_phys = res.start;
-+ goto out;
-+ }
-+
-+ /* For backward compatibility, we need to check if DLM
-+ * node is defined through reserved memory property.
-+ */
- index = of_property_match_string(dev->hw->node, "memory-region-names",
- "wo-dlm");
- if (index < 0)
-@@ -1336,6 +1354,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
- return -ENODEV;
-
- dev->rro.miod_phys = rmem->base;
-+out:
- dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys;
-
- return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring,
+++ /dev/null
-From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001
-Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:10:56 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node
-
-Since the ilm memory region is not part of the RAM SoC, move ilm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------
- 1 file changed, 16 insertions(+), 18 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -97,16 +97,6 @@
- no-map;
- };
-
-- wo_ilm0: wo-ilm@151e0000 {
-- reg = <0 0x151e0000 0 0x8000>;
-- no-map;
-- };
--
-- wo_ilm1: wo-ilm@151f0000 {
-- reg = <0 0x151f0000 0 0x8000>;
-- no-map;
-- };
--
- wo_data: wo-data@4fd80000 {
- reg = <0 0x4fd80000 0 0x240000>;
- no-map;
-@@ -533,11 +523,10 @@
- reg = <0 0x15010000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
-- <&wo_data>;
-- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-- "wo-data";
-+ memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
-+ memory-region-names = "wo-emi", "wo-dlm", "wo-data";
- mediatek,wo-ccif = <&wo_ccif0>;
-+ mediatek,wo-ilm = <&wo_ilm0>;
- mediatek,wo-cpuboot = <&wo_cpuboot>;
- };
-
-@@ -547,11 +536,10 @@
- reg = <0 0x15011000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
-- <&wo_data>;
-- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
-- "wo-data";
-+ memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
-+ memory-region-names = "wo-emi", "wo-dlm", "wo-data";
- mediatek,wo-ccif = <&wo_ccif1>;
-+ mediatek,wo-ilm = <&wo_ilm1>;
- mediatek,wo-cpuboot = <&wo_cpuboot>;
- };
-
-@@ -569,6 +557,16 @@
- interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
- };
-
-+ wo_ilm0: syscon@151e0000 {
-+ compatible = "mediatek,mt7986-wo-ilm", "syscon";
-+ reg = <0 0x151e0000 0 0x8000>;
-+ };
-+
-+ wo_ilm1: syscon@151f0000 {
-+ compatible = "mediatek,mt7986-wo-ilm", "syscon";
-+ reg = <0 0x151f0000 0 0x8000>;
-+ };
-+
- wo_cpuboot: syscon@15194000 {
- compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
- reg = <0 0x15194000 0 0x1000>;
+++ /dev/null
-From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001
-Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org>
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Mon, 13 Mar 2023 15:53:30 +0100
-Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node
-
-Since the dlm memory region is not part of the RAM SoC, move dlm in a
-deidicated syscon node.
-This patch helps to keep backward-compatibility with older version of
-uboot codebase where we have a limit of 8 reserved-memory dts child
-nodes.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++-----------
- 1 file changed, 16 insertions(+), 14 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -101,16 +101,6 @@
- reg = <0 0x4fd80000 0 0x240000>;
- no-map;
- };
--
-- wo_dlm0: wo-dlm@151e8000 {
-- reg = <0 0x151e8000 0 0x2000>;
-- no-map;
-- };
--
-- wo_dlm1: wo-dlm@151f8000 {
-- reg = <0 0x151f8000 0 0x2000>;
-- no-map;
-- };
- };
-
- timer {
-@@ -523,10 +513,11 @@
- reg = <0 0x15010000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-- memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
-- memory-region-names = "wo-emi", "wo-dlm", "wo-data";
-+ memory-region = <&wo_emi0>, <&wo_data>;
-+ memory-region-names = "wo-emi", "wo-data";
- mediatek,wo-ccif = <&wo_ccif0>;
- mediatek,wo-ilm = <&wo_ilm0>;
-+ mediatek,wo-dlm = <&wo_dlm0>;
- mediatek,wo-cpuboot = <&wo_cpuboot>;
- };
-
-@@ -536,10 +527,11 @@
- reg = <0 0x15011000 0 0x1000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-- memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
-- memory-region-names = "wo-emi", "wo-dlm", "wo-data";
-+ memory-region = <&wo_emi1>, <&wo_data>;
-+ memory-region-names = "wo-emi", "wo-data";
- mediatek,wo-ccif = <&wo_ccif1>;
- mediatek,wo-ilm = <&wo_ilm1>;
-+ mediatek,wo-dlm = <&wo_dlm1>;
- mediatek,wo-cpuboot = <&wo_cpuboot>;
- };
-
-@@ -567,6 +559,16 @@
- reg = <0 0x151f0000 0 0x8000>;
- };
-
-+ wo_dlm0: syscon@151e8000 {
-+ compatible = "mediatek,mt7986-wo-dlm", "syscon";
-+ reg = <0 0x151e8000 0 0x2000>;
-+ };
-+
-+ wo_dlm1: syscon@151f8000 {
-+ compatible = "mediatek,mt7986-wo-dlm", "syscon";
-+ reg = <0 0x151f8000 0 0x2000>;
-+ };
-+
- wo_cpuboot: syscon@15194000 {
- compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
- reg = <0 0x15194000 0 0x1000>;
+++ /dev/null
----
- drivers/leds/Kconfig | 10 ++++++++++
- drivers/leds/Makefile | 1 +
- 2 files changed, 11 insertions(+)
-
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -874,6 +874,16 @@ source "drivers/leds/flash/Kconfig"
- comment "RGB LED drivers"
- source "drivers/leds/rgb/Kconfig"
-
-+config LEDS_SMARTRG_LED
-+ tristate "LED support for Adtran SmartRG"
-+ depends on LEDS_CLASS && I2C && OF
-+ help
-+ This option enables support for the Adtran SmartRG platform
-+ system LED driver.
-+
-+ To compile this driver as a module, choose M here: the module
-+ will be called leds-smartrg-system.
-+
- comment "LED Triggers"
- source "drivers/leds/trigger/Kconfig"
-
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -76,6 +76,7 @@ obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
- obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
- obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o
- obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o
-+obj-$(CONFIG_LEDS_SMARTRG_LED) += leds-smartrg-system.o
- obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o
- obj-$(CONFIG_LEDS_SYSCON) += leds-syscon.o
- obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o
+++ /dev/null
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Thu, 2 Nov 2023 16:47:07 +0100
-Subject: [PATCH net-next 1/2] net: ethernet: mediatek: split tx and rx fields
- in mtk_soc_data struct
-
-Split tx and rx fields in mtk_soc_data struct. This is a preliminary
-patch to roll back to QDMA for MT7986 SoC in order to fix a hw hang
-if the device receives a corrupted packet.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 210 ++++++++++++--------
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 29 +--
- 2 files changed, 139 insertions(+), 100 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1264,7 +1264,7 @@ static int mtk_init_fq_dma(struct mtk_et
- eth->scratch_ring = eth->sram_base;
- else
- eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
-- cnt * soc->txrx.txd_size,
-+ cnt * soc->tx.desc_size,
- ð->phy_scratch_ring,
- GFP_KERNEL);
- if (unlikely(!eth->scratch_ring))
-@@ -1280,16 +1280,16 @@ static int mtk_init_fq_dma(struct mtk_et
- if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
- return -ENOMEM;
-
-- phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
-+ phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
-
- for (i = 0; i < cnt; i++) {
- struct mtk_tx_dma_v2 *txd;
-
-- txd = eth->scratch_ring + i * soc->txrx.txd_size;
-+ txd = eth->scratch_ring + i * soc->tx.desc_size;
- txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
- if (i < cnt - 1)
- txd->txd2 = eth->phy_scratch_ring +
-- (i + 1) * soc->txrx.txd_size;
-+ (i + 1) * soc->tx.desc_size;
-
- txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
- txd->txd4 = 0;
-@@ -1538,7 +1538,7 @@ static int mtk_tx_map(struct sk_buff *sk
- if (itxd == ring->last_free)
- return -ENOMEM;
-
-- itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+ itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
- memset(itx_buf, 0, sizeof(*itx_buf));
-
- txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
-@@ -1579,7 +1579,7 @@ static int mtk_tx_map(struct sk_buff *sk
-
- memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
- txd_info.size = min_t(unsigned int, frag_size,
-- soc->txrx.dma_max_len);
-+ soc->tx.dma_max_len);
- txd_info.qid = queue;
- txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
- !(frag_size - txd_info.size);
-@@ -1592,7 +1592,7 @@ static int mtk_tx_map(struct sk_buff *sk
- mtk_tx_set_dma_desc(dev, txd, &txd_info);
-
- tx_buf = mtk_desc_to_tx_buf(ring, txd,
-- soc->txrx.txd_size);
-+ soc->tx.desc_size);
- if (new_desc)
- memset(tx_buf, 0, sizeof(*tx_buf));
- tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
-@@ -1635,7 +1635,7 @@ static int mtk_tx_map(struct sk_buff *sk
- } else {
- int next_idx;
-
-- next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
-+ next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
- ring->dma_size);
- mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
- }
-@@ -1644,7 +1644,7 @@ static int mtk_tx_map(struct sk_buff *sk
-
- err_dma:
- do {
-- tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+ tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
-
- /* unmap dma */
- mtk_tx_unmap(eth, tx_buf, NULL, false);
-@@ -1669,7 +1669,7 @@ static int mtk_cal_txd_req(struct mtk_et
- for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
- frag = &skb_shinfo(skb)->frags[i];
- nfrags += DIV_ROUND_UP(skb_frag_size(frag),
-- eth->soc->txrx.dma_max_len);
-+ eth->soc->tx.dma_max_len);
- }
- } else {
- nfrags += skb_shinfo(skb)->nr_frags;
-@@ -1810,7 +1810,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
-
- ring = ð->rx_ring[i];
- idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
-- rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+ rxd = ring->dma + idx * eth->soc->rx.desc_size;
- if (rxd->rxd2 & RX_DMA_DONE) {
- ring->calc_idx_update = true;
- return ring;
-@@ -1978,7 +1978,7 @@ static int mtk_xdp_submit_frame(struct m
- }
- htxd = txd;
-
-- tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
-+ tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
- memset(tx_buf, 0, sizeof(*tx_buf));
- htx_buf = tx_buf;
-
-@@ -1997,7 +1997,7 @@ static int mtk_xdp_submit_frame(struct m
- goto unmap;
-
- tx_buf = mtk_desc_to_tx_buf(ring, txd,
-- soc->txrx.txd_size);
-+ soc->tx.desc_size);
- memset(tx_buf, 0, sizeof(*tx_buf));
- n_desc++;
- }
-@@ -2035,7 +2035,7 @@ static int mtk_xdp_submit_frame(struct m
- } else {
- int idx;
-
-- idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
-+ idx = txd_to_idx(ring, txd, soc->tx.desc_size);
- mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
- MT7628_TX_CTX_IDX0);
- }
-@@ -2046,7 +2046,7 @@ static int mtk_xdp_submit_frame(struct m
-
- unmap:
- while (htxd != txd) {
-- tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
-+ tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
- mtk_tx_unmap(eth, tx_buf, NULL, false);
-
- htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
-@@ -2177,7 +2177,7 @@ static int mtk_poll_rx(struct napi_struc
- goto rx_done;
-
- idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
-- rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+ rxd = ring->dma + idx * eth->soc->rx.desc_size;
- data = ring->data[idx];
-
- if (!mtk_rx_get_desc(eth, &trxd, rxd))
-@@ -2312,7 +2312,7 @@ static int mtk_poll_rx(struct napi_struc
- rxdcsum = &trxd.rxd4;
- }
-
-- if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
-+ if (*rxdcsum & eth->soc->rx.dma_l4_valid)
- skb->ip_summed = CHECKSUM_UNNECESSARY;
- else
- skb_checksum_none_assert(skb);
-@@ -2436,7 +2436,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
- break;
-
- tx_buf = mtk_desc_to_tx_buf(ring, desc,
-- eth->soc->txrx.txd_size);
-+ eth->soc->tx.desc_size);
- if (!tx_buf->data)
- break;
-
-@@ -2487,7 +2487,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
- }
- mtk_tx_unmap(eth, tx_buf, &bq, true);
-
-- desc = ring->dma + cpu * eth->soc->txrx.txd_size;
-+ desc = ring->dma + cpu * eth->soc->tx.desc_size;
- ring->last_free = desc;
- atomic_inc(&ring->free_count);
-
-@@ -2577,7 +2577,7 @@ static int mtk_napi_rx(struct napi_struc
- do {
- int rx_done;
-
-- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
-+ mtk_w32(eth, eth->soc->rx.irq_done_mask,
- reg_map->pdma.irq_status);
- rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
- rx_done_total += rx_done;
-@@ -2593,10 +2593,10 @@ static int mtk_napi_rx(struct napi_struc
- return budget;
-
- } while (mtk_r32(eth, reg_map->pdma.irq_status) &
-- eth->soc->txrx.rx_irq_done_mask);
-+ eth->soc->rx.irq_done_mask);
-
- if (napi_complete_done(napi, rx_done_total))
-- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
-
- return rx_done_total;
- }
-@@ -2605,7 +2605,7 @@ static int mtk_tx_alloc(struct mtk_eth *
- {
- const struct mtk_soc_data *soc = eth->soc;
- struct mtk_tx_ring *ring = ð->tx_ring;
-- int i, sz = soc->txrx.txd_size;
-+ int i, sz = soc->tx.desc_size;
- struct mtk_tx_dma_v2 *txd;
- int ring_size;
- u32 ofs, val;
-@@ -2728,14 +2728,14 @@ static void mtk_tx_clean(struct mtk_eth
- }
- if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
- dma_free_coherent(eth->dma_dev,
-- ring->dma_size * soc->txrx.txd_size,
-+ ring->dma_size * soc->tx.desc_size,
- ring->dma, ring->phys);
- ring->dma = NULL;
- }
-
- if (ring->dma_pdma) {
- dma_free_coherent(eth->dma_dev,
-- ring->dma_size * soc->txrx.txd_size,
-+ ring->dma_size * soc->tx.desc_size,
- ring->dma_pdma, ring->phys_pdma);
- ring->dma_pdma = NULL;
- }
-@@ -2790,15 +2790,15 @@ static int mtk_rx_alloc(struct mtk_eth *
- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
- rx_flag != MTK_RX_FLAGS_NORMAL) {
- ring->dma = dma_alloc_coherent(eth->dma_dev,
-- rx_dma_size * eth->soc->txrx.rxd_size,
-- &ring->phys, GFP_KERNEL);
-+ rx_dma_size * eth->soc->rx.desc_size,
-+ &ring->phys, GFP_KERNEL);
- } else {
- struct mtk_tx_ring *tx_ring = ð->tx_ring;
-
- ring->dma = tx_ring->dma + tx_ring_size *
-- eth->soc->txrx.txd_size * (ring_no + 1);
-+ eth->soc->tx.desc_size * (ring_no + 1);
- ring->phys = tx_ring->phys + tx_ring_size *
-- eth->soc->txrx.txd_size * (ring_no + 1);
-+ eth->soc->tx.desc_size * (ring_no + 1);
- }
-
- if (!ring->dma)
-@@ -2809,7 +2809,7 @@ static int mtk_rx_alloc(struct mtk_eth *
- dma_addr_t dma_addr;
- void *data;
-
-- rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+ rxd = ring->dma + i * eth->soc->rx.desc_size;
- if (ring->page_pool) {
- data = mtk_page_pool_get_buff(ring->page_pool,
- &dma_addr, GFP_KERNEL);
-@@ -2900,7 +2900,7 @@ static void mtk_rx_clean(struct mtk_eth
- if (!ring->data[i])
- continue;
-
-- rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+ rxd = ring->dma + i * eth->soc->rx.desc_size;
- if (!rxd->rxd1)
- continue;
-
-@@ -2917,7 +2917,7 @@ static void mtk_rx_clean(struct mtk_eth
-
- if (!in_sram && ring->dma) {
- dma_free_coherent(eth->dma_dev,
-- ring->dma_size * eth->soc->txrx.rxd_size,
-+ ring->dma_size * eth->soc->rx.desc_size,
- ring->dma, ring->phys);
- ring->dma = NULL;
- }
-@@ -3280,7 +3280,7 @@ static void mtk_dma_free(struct mtk_eth
- netdev_reset_queue(eth->netdev[i]);
- if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
- dma_free_coherent(eth->dma_dev,
-- MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
-+ MTK_QDMA_RING_SIZE * soc->tx.desc_size,
- eth->scratch_ring, eth->phy_scratch_ring);
- eth->scratch_ring = NULL;
- eth->phy_scratch_ring = 0;
-@@ -3330,7 +3330,7 @@ static irqreturn_t mtk_handle_irq_rx(int
-
- eth->rx_events++;
- if (likely(napi_schedule_prep(ð->rx_napi))) {
-- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- __napi_schedule(ð->rx_napi);
- }
-
-@@ -3356,9 +3356,9 @@ static irqreturn_t mtk_handle_irq(int ir
- const struct mtk_reg_map *reg_map = eth->soc->reg_map;
-
- if (mtk_r32(eth, reg_map->pdma.irq_mask) &
-- eth->soc->txrx.rx_irq_done_mask) {
-+ eth->soc->rx.irq_done_mask) {
- if (mtk_r32(eth, reg_map->pdma.irq_status) &
-- eth->soc->txrx.rx_irq_done_mask)
-+ eth->soc->rx.irq_done_mask)
- mtk_handle_irq_rx(irq, _eth);
- }
- if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
-@@ -3376,10 +3376,10 @@ static void mtk_poll_controller(struct n
- struct mtk_eth *eth = mac->hw;
-
- mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
-- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- mtk_handle_irq_rx(eth->irq[2], dev);
- mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
-- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
- }
- #endif
-
-@@ -3545,7 +3545,7 @@ static int mtk_open(struct net_device *d
- napi_enable(ð->tx_napi);
- napi_enable(ð->rx_napi);
- mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
-- mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
- refcount_set(ð->dma_refcnt, 1);
- }
- else
-@@ -3628,7 +3628,7 @@ static int mtk_stop(struct net_device *d
- mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
-
- mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
-- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- napi_disable(ð->tx_napi);
- napi_disable(ð->rx_napi);
-
-@@ -4107,9 +4107,9 @@ static int mtk_hw_init(struct mtk_eth *e
-
- /* FE int grouping */
- mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
-- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
-+ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
- mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
-- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
-+ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
- mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
-
- if (mtk_is_netsys_v3_or_greater(eth)) {
-@@ -5270,11 +5270,15 @@ static const struct mtk_soc_data mt2701_
- .required_clks = MT7623_CLKS_BITMAP,
- .required_pctl = true,
- .version = 1,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
-@@ -5290,11 +5294,15 @@ static const struct mtk_soc_data mt7621_
- .offload_version = 1,
- .hash_offset = 2,
- .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
-@@ -5312,11 +5320,15 @@ static const struct mtk_soc_data mt7622_
- .hash_offset = 2,
- .has_accounting = true,
- .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
-@@ -5333,11 +5345,15 @@ static const struct mtk_soc_data mt7623_
- .hash_offset = 2,
- .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
- .disable_pll_modes = true,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
-@@ -5352,11 +5368,15 @@ static const struct mtk_soc_data mt7629_
- .required_pctl = false,
- .has_accounting = true,
- .version = 1,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
-@@ -5374,11 +5394,15 @@ static const struct mtk_soc_data mt7981_
- .hash_offset = 4,
- .has_accounting = true,
- .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma_v2),
-- .rxd_size = sizeof(struct mtk_rx_dma_v2),
-- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma_v2),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+ .dma_len_offset = 8,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma_v2),
-+ .irq_done_mask = MTK_RX_DONE_INT_V2,
-+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- .dma_len_offset = 8,
- },
-@@ -5396,11 +5420,15 @@ static const struct mtk_soc_data mt7986_
- .hash_offset = 4,
- .has_accounting = true,
- .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma_v2),
-- .rxd_size = sizeof(struct mtk_rx_dma_v2),
-- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma_v2),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+ .dma_len_offset = 8,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma_v2),
-+ .irq_done_mask = MTK_RX_DONE_INT_V2,
-+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- .dma_len_offset = 8,
- },
-@@ -5418,11 +5446,15 @@ static const struct mtk_soc_data mt7988_
- .hash_offset = 4,
- .has_accounting = true,
- .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma_v2),
-- .rxd_size = sizeof(struct mtk_rx_dma_v2),
-- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma_v2),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+ .dma_len_offset = 8,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma_v2),
-+ .irq_done_mask = MTK_RX_DONE_INT_V2,
-+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- .dma_len_offset = 8,
- },
-@@ -5435,11 +5467,15 @@ static const struct mtk_soc_data rt5350_
- .required_clks = MT7628_CLKS_BITMAP,
- .required_pctl = false,
- .version = 1,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID_PDMA,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -327,8 +327,8 @@
- /* QDMA descriptor txd3 */
- #define TX_DMA_OWNER_CPU BIT(31)
- #define TX_DMA_LS0 BIT(30)
--#define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len)
-+#define TX_DMA_PLEN0(x) (((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
-+#define TX_DMA_PLEN1(x) ((x) & eth->soc->tx.dma_max_len)
- #define TX_DMA_SWC BIT(14)
- #define TX_DMA_PQID GENMASK(3, 0)
- #define TX_DMA_ADDR64_MASK GENMASK(3, 0)
-@@ -348,8 +348,8 @@
- /* QDMA descriptor rxd2 */
- #define RX_DMA_DONE BIT(31)
- #define RX_DMA_LSO BIT(30)
--#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
-+#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
-+#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
- #define RX_DMA_VTAG BIT(15)
- #define RX_DMA_ADDR64_MASK GENMASK(3, 0)
- #if IS_ENABLED(CONFIG_64BIT)
-@@ -1209,10 +1209,9 @@ struct mtk_reg_map {
- * @foe_entry_size Foe table entry size.
- * @has_accounting Bool indicating support for accounting of
- * offloaded flows.
-- * @txd_size Tx DMA descriptor size.
-- * @rxd_size Rx DMA descriptor size.
-- * @rx_irq_done_mask Rx irq done register mask.
-- * @rx_dma_l4_valid Rx DMA valid register mask.
-+ * @desc_size Tx/Rx DMA descriptor size.
-+ * @irq_done_mask Rx irq done register mask.
-+ * @dma_l4_valid Rx DMA valid register mask.
- * @dma_max_len Max DMA tx/rx buffer length.
- * @dma_len_offset Tx/Rx DMA length field offset.
- */
-@@ -1230,13 +1229,17 @@ struct mtk_soc_data {
- bool has_accounting;
- bool disable_pll_modes;
- struct {
-- u32 txd_size;
-- u32 rxd_size;
-- u32 rx_irq_done_mask;
-- u32 rx_dma_l4_valid;
-+ u32 desc_size;
- u32 dma_max_len;
- u32 dma_len_offset;
-- } txrx;
-+ } tx;
-+ struct {
-+ u32 desc_size;
-+ u32 irq_done_mask;
-+ u32 dma_l4_valid;
-+ u32 dma_max_len;
-+ u32 dma_len_offset;
-+ } rx;
- };
-
- #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000)
+++ /dev/null
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 10 Oct 2023 21:06:43 +0200
-Subject: [PATCH net-next 2/2] net: ethernet: mediatek: use QDMA instead of
- ADMAv2 on MT7981 and MT7986
-
-ADMA is plagued by RX hangs which can't easily detected and happen upon
-receival of a corrupted package.
-Use QDMA just like on netsys v1 which is also still present and usable, and
-doesn't suffer from that problem.
-
-Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++-----------
- 1 file changed, 23 insertions(+), 23 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -110,16 +110,16 @@ static const struct mtk_reg_map mt7986_r
- .tx_irq_mask = 0x461c,
- .tx_irq_status = 0x4618,
- .pdma = {
-- .rx_ptr = 0x6100,
-- .rx_cnt_cfg = 0x6104,
-- .pcrx_ptr = 0x6108,
-- .glo_cfg = 0x6204,
-- .rst_idx = 0x6208,
-- .delay_irq = 0x620c,
-- .irq_status = 0x6220,
-- .irq_mask = 0x6228,
-- .adma_rx_dbg0 = 0x6238,
-- .int_grp = 0x6250,
-+ .rx_ptr = 0x4100,
-+ .rx_cnt_cfg = 0x4104,
-+ .pcrx_ptr = 0x4108,
-+ .glo_cfg = 0x4204,
-+ .rst_idx = 0x4208,
-+ .delay_irq = 0x420c,
-+ .irq_status = 0x4220,
-+ .irq_mask = 0x4228,
-+ .adma_rx_dbg0 = 0x4238,
-+ .int_grp = 0x4250,
- },
- .qdma = {
- .qtx_cfg = 0x4400,
-@@ -1232,7 +1232,7 @@ static bool mtk_rx_get_desc(struct mtk_e
- rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
- rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
- rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
-- if (mtk_is_netsys_v2_or_greater(eth)) {
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
- rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
- rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
- }
-@@ -2184,7 +2184,7 @@ static int mtk_poll_rx(struct napi_struc
- break;
-
- /* find out which mac the packet come from. values start at 1 */
-- if (mtk_is_netsys_v2_or_greater(eth)) {
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
- u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
-
- switch (val) {
-@@ -2296,7 +2296,7 @@ static int mtk_poll_rx(struct napi_struc
- skb->dev = netdev;
- bytes += skb->len;
-
-- if (mtk_is_netsys_v2_or_greater(eth)) {
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
- reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
- hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
- if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -2846,7 +2846,7 @@ static int mtk_rx_alloc(struct mtk_eth *
-
- rxd->rxd3 = 0;
- rxd->rxd4 = 0;
-- if (mtk_is_netsys_v2_or_greater(eth)) {
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
- rxd->rxd5 = 0;
- rxd->rxd6 = 0;
- rxd->rxd7 = 0;
-@@ -4053,7 +4053,7 @@ static int mtk_hw_init(struct mtk_eth *e
- else
- mtk_hw_reset(eth);
-
-- if (mtk_is_netsys_v2_or_greater(eth)) {
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
- /* Set FE to PDMAv2 if necessary */
- val = mtk_r32(eth, MTK_FE_GLO_MISC);
- mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
-@@ -5400,11 +5400,11 @@ static const struct mtk_soc_data mt7981_
- .dma_len_offset = 8,
- },
- .rx = {
-- .desc_size = sizeof(struct mtk_rx_dma_v2),
-- .irq_done_mask = MTK_RX_DONE_INT_V2,
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
- .dma_l4_valid = RX_DMA_L4_VALID_V2,
-- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-- .dma_len_offset = 8,
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
- },
- };
-
-@@ -5426,11 +5426,11 @@ static const struct mtk_soc_data mt7986_
- .dma_len_offset = 8,
- },
- .rx = {
-- .desc_size = sizeof(struct mtk_rx_dma_v2),
-- .irq_done_mask = MTK_RX_DONE_INT_V2,
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
- .dma_l4_valid = RX_DMA_L4_VALID_V2,
-- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-- .dma_len_offset = 8,
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
- },
- };
-
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 18 Jan 2024 12:51:32 +0100
-Subject: [PATCH] net: ethernet: mtk_eth_soc: fix WED + wifi reset
-
-The WLAN + WED reset sequence relies on being able to receive interrupts from
-the card, in order to synchronize individual steps with the firmware.
-When WED is stopped, leave interrupts running and rely on the driver turning
-off unwanted ones.
-WED DMA also needs to be disabled before resetting.
-
-Fixes: f78cd9c783e0 ("net: ethernet: mtk_wed: update mtk_wed_stop")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1071,13 +1071,13 @@ mtk_wed_dma_disable(struct mtk_wed_devic
- static void
- mtk_wed_stop(struct mtk_wed_device *dev)
- {
-+ mtk_wed_dma_disable(dev);
- mtk_wed_set_ext_int(dev, false);
-
- wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
- wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
- wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
- wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
-- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
-
- if (!mtk_wed_get_rx_capa(dev))
- return;
-@@ -1090,7 +1090,6 @@ static void
- mtk_wed_deinit(struct mtk_wed_device *dev)
- {
- mtk_wed_stop(dev);
-- mtk_wed_dma_disable(dev);
-
- wed_clr(dev, MTK_WED_CTRL,
- MTK_WED_CTRL_WDMA_INT_AGENT_EN |
-@@ -2621,9 +2620,6 @@ mtk_wed_irq_get(struct mtk_wed_device *d
- static void
- mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
- {
-- if (!dev->running)
-- return;
--
- mtk_wed_set_ext_int(dev, !!mask);
- wed_w32(dev, MTK_WED_INT_MASK, mask);
- }
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -578,6 +578,7 @@
+@@ -575,6 +575,7 @@
compatible = "mediatek,mt7622-nor",
"mediatek,mt8173-nor";
reg = <0 0x11014000 0 0xe0>;
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -145,9 +145,9 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- switch@0 {
++ switch@1f {
+ compatible = "mediatek,mt7531";
+- reg = <0>;
++ reg = <31>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&pio>;
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -117,9 +117,9 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- switch@0 {
++ switch@1f {
+ compatible = "mediatek,mt7531";
+- reg = <0>;
++ reg = <31>;
+ reset-gpios = <&pio 54 0>;
+
+ ports {
chosen {
stdout-path = "serial2:115200n8";
- bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
-+ bootargs = "root=/dev/fit0 earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
++ bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
+ rootdisk-emmc = <&emmc_rootdisk>;
+ rootdisk-sd = <&sd_rootdisk>;
};
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -347,7 +347,7 @@
+@@ -345,7 +345,7 @@
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10310000 0 0x1000>,
-From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001
+From patchwork Fri Apr 19 16:59:07 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13636668
+Return-Path:
+ <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
+Date: Fri, 19 Apr 2024 17:59:07 +0100
+From: Daniel Golle <daniel@makrotopia.org>
+To: "Rafael J. Wysocki" <rafael@kernel.org>,
+ Viresh Kumar <viresh.kumar@linaro.org>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+ linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org,
+ linux-mediatek@lists.infradead.org
+Subject: [PATCH] cpufreq: mediatek: Add support for MT7988A
+Message-ID:
+ <acf4fb446aacfbf6ce7b6e94bf3aad303e0ad4d1.1713545923.git.daniel@makrotopia.org>
+Content-Disposition: inline
+List-Id: <linux-mediatek.lists.infradead.org>
+
From: Sam Shih <sam.shih@mediatek.com>
-Date: Tue, 28 Feb 2023 19:59:22 +0800
-Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988
-This add cpufreq support for mediatek MT7988 SoC.
+This add cpufreq support for mediatek MT7988A SoC.
-The platform data of MT7988 is different from previous MediaTek SoCs,
+The platform data of MT7988A is different from previous MediaTek SoCs,
so we add a new compatible and platform data for it.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
-+ { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
++ { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data },
{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -849,6 +849,12 @@
+@@ -844,6 +844,12 @@
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1: pcie@1a145000 {
-@@ -887,6 +893,12 @@
+@@ -882,6 +888,12 @@
#address-cells = <0>;
#interrupt-cells = <1>;
};
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -837,6 +837,9 @@
+@@ -832,6 +832,9 @@
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
-@@ -881,6 +884,9 @@
+@@ -876,6 +879,9 @@
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
+@@ -937,7 +943,7 @@
+ };
+
+ hifsys: clock-controller@1af00000 {
+- compatible = "mediatek,mt7622-hifsys";
++ compatible = "mediatek,mt7622-hifsys", "syscon";
+ reg = <0 0x1af00000 0 0x70>;
+ #clock-cells = <1>;
+ };
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -20,6 +20,7 @@
--- /dev/null
+From 5314e73cb941b47e6866b49b3b78c25e32d62df8 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Sat, 23 Mar 2024 20:21:14 +0100
+Subject: [PATCH] net: phy: add Airoha EN8801SC PHY
+
+Airoha EN8801SC Gigabit PHY is used on Edgecore EAP111, so include a
+modified version of MTK SDK driver.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ drivers/net/phy/Kconfig | 5 +++++
+ drivers/net/phy/Makefile | 1 +
+ 2 files changed, 6 insertions(+)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -142,6 +142,11 @@ endif # RTL8366_SMI
+
+ comment "MII PHY device drivers"
+
++config AIROHA_EN8801SC_PHY
++ tristate "Airoha EN8801SC Gigabit PHY"
++ help
++ Currently supports the Airoha EN8801SC PHY.
++
+ config AIR_EN8811H_PHY
+ tristate "Airoha EN8811H 2.5 Gigabit PHY"
+ help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -49,6 +49,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
+
+ obj-$(CONFIG_ADIN_PHY) += adin.o
+ obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
++obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o
+ obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
+ obj-$(CONFIG_AMD_PHY) += amd.o
+ obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
--- /dev/null
+From eb58bf4afd708eb3c64c7b9b2c5fbfacdcdee3e5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 14 Feb 2024 15:04:54 +0100
+Subject: [PATCH] pwm: mediatek: add support for MT7988
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+MT7988 uses new registers layout just like MT7981 but it supports 8 PWM
+interfaces.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20240214140454.6438-2-zajec5@gmail.com
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/pwm/pwm-mediatek.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/pwm/pwm-mediatek.c
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -341,6 +341,13 @@ static const struct pwm_mediatek_of_data
+ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
++static const struct pwm_mediatek_of_data mt7988_pwm_data = {
++ .num_pwms = 8,
++ .pwm45_fixup = false,
++ .has_ck_26m_sel = false,
++ .reg_offset = mtk_pwm_reg_offset_v2,
++};
++
+ static const struct pwm_mediatek_of_data mt8183_pwm_data = {
+ .num_pwms = 4,
+ .pwm45_fixup = false,
+@@ -371,6 +378,7 @@ static const struct of_device_id pwm_med
+ { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
+ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
++ { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
+ { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
+ { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
+ { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -248,6 +248,28 @@
- status = "disabled";
+@@ -202,6 +202,28 @@
+ #interrupt-cells = <2>;
};
+ afe: audio-controller@11210000 {
-
};
- timer {
-@@ -543,10 +537,11 @@
+ soc {
+@@ -532,10 +526,11 @@
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
};
wed1: wed@15011000 {
-@@ -556,10 +551,11 @@
+@@ -545,10 +540,11 @@
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
+ mediatek,wo-cpuboot = <&wo_cpuboot>;
};
- wo_ccif0: syscon@151a5000 {
-@@ -576,6 +572,11 @@
+ eth: ethernet@15100000 {
+@@ -606,6 +602,11 @@
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
};
+ reg = <0 0x15194000 0 0x1000>;
+ };
+
- eth: ethernet@15100000 {
- compatible = "mediatek,mt7986-eth";
- reg = <0 0x15100000 0 0x80000>;
+ wifi: wifi@18000000 {
+ compatible = "mediatek,mt7986-wmac";
+ reg = <0 0x18000000 0 0x1000000>,
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1321,6 +1321,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1320,6 +1320,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
struct device_node *np;
int index;
index = of_property_match_string(dev->hw->node, "memory-region-names",
"wo-dlm");
if (index < 0)
-@@ -1337,6 +1355,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1336,6 +1354,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
return -ENODEV;
dev->rro.miod_phys = rmem->base;
wo_data: wo-data@4fd80000 {
reg = <0 0x4fd80000 0 0x240000>;
no-map;
-@@ -536,11 +526,10 @@
+@@ -525,11 +515,10 @@
reg = <0 0x15010000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
mediatek,wo-cpuboot = <&wo_cpuboot>;
};
-@@ -550,11 +539,10 @@
+@@ -539,11 +528,10 @@
reg = <0 0x15011000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
mediatek,wo-cpuboot = <&wo_cpuboot>;
};
-@@ -572,6 +560,16 @@
+@@ -602,6 +590,16 @@
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
};
- };
};
- timer {
-@@ -526,10 +516,11 @@
+ soc {
+@@ -515,10 +505,11 @@
reg = <0 0x15010000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
mediatek,wo-cpuboot = <&wo_cpuboot>;
};
-@@ -539,10 +530,11 @@
+@@ -528,10 +519,11 @@
reg = <0 0x15011000 0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
mediatek,wo-cpuboot = <&wo_cpuboot>;
};
-@@ -570,6 +562,16 @@
+@@ -600,6 +592,16 @@
reg = <0 0x151f0000 0 0x8000>;
};
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 18 Jan 2024 12:51:32 +0100
-Subject: [PATCH] net: ethernet: mtk_eth_soc: fix WED + wifi reset
-
-The WLAN + WED reset sequence relies on being able to receive interrupts from
-the card, in order to synchronize individual steps with the firmware.
-When WED is stopped, leave interrupts running and rely on the driver turning
-off unwanted ones.
-WED DMA also needs to be disabled before resetting.
-
-Fixes: f78cd9c783e0 ("net: ethernet: mtk_wed: update mtk_wed_stop")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1072,13 +1072,13 @@ mtk_wed_dma_disable(struct mtk_wed_devic
- static void
- mtk_wed_stop(struct mtk_wed_device *dev)
- {
-+ mtk_wed_dma_disable(dev);
- mtk_wed_set_ext_int(dev, false);
-
- wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
- wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
- wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
- wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
-- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
-
- if (!mtk_wed_get_rx_capa(dev))
- return;
-@@ -1091,7 +1091,6 @@ static void
- mtk_wed_deinit(struct mtk_wed_device *dev)
- {
- mtk_wed_stop(dev);
-- mtk_wed_dma_disable(dev);
-
- wed_clr(dev, MTK_WED_CTRL,
- MTK_WED_CTRL_WDMA_INT_AGENT_EN |
-@@ -2622,9 +2621,6 @@ mtk_wed_irq_get(struct mtk_wed_device *d
- static void
- mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
- {
-- if (!dev->running)
-- return;
--
- mtk_wed_set_ext_int(dev, !!mask);
- wed_w32(dev, MTK_WED_INT_MASK, mask);
- }
compatible = "enterasys,ws-ap3710i";
aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet2;
led-boot = &led_power_green;
led-failsafe = &led_power_red;
led-running = &led_power_green;
label-mac-device = &enet0;
};
+ chosen {
+ bootargs-override = "console=ttyS0,115200";
+ stdout-path = &serial0;
+ };
+
memory {
device_type = "memory";
};
#size-cells = <1>;
partition@0 {
- compatible = "denx,fit";
+ compatible = "denx,uimage";
reg = <0x0 0x1d80000>;
label = "firmware";
};
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
reg = <0 0xffe09000 0 0x1000>;
+
+ /* Filled by U-Boot */
+ bus-range = <0x00 0x01>;
+ dma-ranges = <0x2000000 0x00 0xfff00000 0x00 0xffe00000
+ 0x00 0x100000 0x42000000 0x00 0x00 0x00
+ 0x00 0x00 0x10000000>;
+
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
reg = <0 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+
+ /* Filled by U-Boot */
+ bus-range = <0x00 0x01>;
+ dma-ranges = <0x2000000 0x00 0xfff00000 0x00
+ 0xffe00000 0x00 0x100000 0x42000000
+ 0x00 0x00 0x00 0x00 0x00 0x10000000>;
+
pcie@0 {
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
};
/include/ "fsl/p1020si-post.dtsi"
+/ {
+ cpus {
+ PowerPC,P1020@0 {
+ bus-frequency = <399999996>;
+ timebase-frequency = <50000000>;
+ clock-frequency = <799999992>;
+ d-cache-block-size = <0x20>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <0x80>;
+ i-cache-block-size = <0x20>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <0x80>;
+ cpu-release-addr = <0x0 0x0ffff280>;
+ status = "okay";
+ enable-method = "spin-table";
+ };
+
+ PowerPC,P1020@1 {
+ bus-frequency = <399999996>;
+ timebase-frequency = <50000000>;
+ clock-frequency = <799999992>;
+ d-cache-block-size = <0x20>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <0x80>;
+ i-cache-block-size = <0x20>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <0x80>;
+ cpu-release-addr = <0x0 0x0ffff2a0>;
+ status = "disabled";
+ enable-method = "spin-table";
+ };
+ };
+
+ memory {
+ reg = <0x0 0x0 0x0 0x10000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cpu1-bootpage@ff00000 {
+ /* Reserve upper 1 MB for second-core-bootpage */
+ reg = <0x0 0xff00000 0x0 0x100000>;
+ };
+ };
+
+ soc@ffe00000 {
+ bus-frequency = <399999996>;
+
+ serial@4600 {
+ clock-frequency = <399999996>;
+ };
+
+ serial@4500 {
+ clock-frequency = <399999996>;
+ };
+
+ pic@40000 {
+ clock-frequency = <399999996>;
+ };
+ };
+
+ localbus@ffe05000 {
+ bus-frequency = <24999999>;
+ };
+};
+
+&enet0 {
+ rx-stash-idx = <0x00>;
+ rx-stash-len = <0x60>;
+ bd-stash;
+};
+
+&enet2 {
+ rx-stash-idx = <0x00>;
+ rx-stash-len = <0x60>;
+ bd-stash;
+};
+
/*
* For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
* aliases to determine PCI domain numbers, drop aliases so as not to
DEVICE_VENDOR := Enterasys
DEVICE_MODEL := WS-AP3710i
BLOCKSIZE := 128k
- KERNEL = kernel-bin | lzma | fit lzma $(KDIR)/image-$$(DEVICE_DTS).dtb
+ KERNEL_NAME := simpleImage.ws-ap3710i
+ KERNEL_ENTRY := 0x1500000
+ KERNEL_LOADADDR := 0x1500000
+ KERNEL = kernel-bin | uImage none
+ KERNEL_INITRAMFS := kernel-bin | uImage none
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
endef
DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct
BLOCKSIZE := 128k
KERNEL_NAME := simpleImage.ws-ap3825i
- KERNEL_ENTRY := 0x1000000
- KERNEL_LOADADDR := 0x1000000
+ KERNEL_ENTRY := 0x1500000
+ KERNEL_LOADADDR := 0x1500000
KERNEL = kernel-bin | fit none $(KDIR)/image-$$(DEVICE_DTS).dtb
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
BOARDNAME:=P1020
-KERNEL_IMAGES:=simpleImage.ws-ap3825i simpleImage.hiveap-330
+KERNEL_IMAGES:=simpleImage.ws-ap3710i simpleImage.ws-ap3825i simpleImage.hiveap-330
define Target/Description
Build firmware images for Freescale P1020 based boards.
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o
obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -181,6 +181,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+
+@@ -363,6 +364,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
+ image-$(CONFIG_KSI8560) += cuImage.ksi8560
+ image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
++image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100) += dtbImage.mvme7100
+
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -342,7 +342,8 @@ adder875-redboot)
+ binary=y
+ ;;
+ simpleboot-hiveap-330|\
+-simpleboot-tl-wdr4900-v1)
++simpleboot-tl-wdr4900-v1|\
++simpleboot-ws-ap3710i)
+ platformo="$object/fixed-head.o $object/simpleboot.o"
+ link_address='0x1500000'
+ binary=y
obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -181,6 +181,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
- src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -363,6 +364,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
- image-$(CONFIG_KSI8560) += cuImage.ksi8560
+@@ -365,6 +366,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+image-$(CONFIG_WS_AP3825I) += simpleImage.ws-ap3825i
# Board ports in arch/powerpc/platform/86xx/Kconfig
image-$(CONFIG_MVME7100) += dtbImage.mvme7100
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -342,6 +342,7 @@ adder875-redboot)
- binary=y
+@@ -343,7 +343,8 @@ adder875-redboot)
;;
simpleboot-hiveap-330|\
-+simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
+ simpleboot-tl-wdr4900-v1|\
+-simpleboot-ws-ap3710i)
++simpleboot-ws-ap3710i|\
++simpleboot-ws-ap3825i)
platformo="$object/fixed-head.o $object/simpleboot.o"
link_address='0x1500000'
+ binary=y
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -364,6 +364,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
- image-$(CONFIG_KSI8560) += cuImage.ksi8560
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3715I) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
+
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+@@ -366,6 +367,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+image-$(CONFIG_WS_AP3715I) += simpleImage.ws-ap3715i
image-$(CONFIG_WS_AP3825I) += simpleImage.ws-ap3825i
# Board ports in arch/powerpc/platform/86xx/Kconfig
image-$(CONFIG_MVME7100) += dtbImage.mvme7100
---- a/arch/powerpc/boot/wrapper
-+++ b/arch/powerpc/boot/wrapper
-@@ -342,6 +342,7 @@ adder875-redboot)
- binary=y
- ;;
- simpleboot-hiveap-330|\
-+simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
- platformo="$object/fixed-head.o $object/simpleboot.o"
+src-plat-$(CONFIG_BR200_WP) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
- src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
-@@ -362,6 +363,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+@@ -364,6 +365,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
image-$(CONFIG_TQM8555) += cuImage.tqm8555
image-$(CONFIG_TQM8560) += cuImage.tqm8560
image-$(CONFIG_KSI8560) += cuImage.ksi8560
+image-$(CONFIG_BR200_WP) += simpleImage.br200-wp
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
- image-$(CONFIG_WS_AP3715I) += simpleImage.ws-ap3715i
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -341,6 +341,7 @@ adder875-redboot)
;;
+simpleboot-br200-wp|\
simpleboot-hiveap-330|\
- simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
+ simpleboot-tl-wdr4900-v1|\
+ simpleboot-ws-ap3710i|\
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -291,7 +291,6 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
+@@ -293,7 +293,6 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
image-$(CONFIG_PPC_HOLLY) += dtbImage.holly
image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
#
-@@ -427,15 +426,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
+@@ -430,15 +429,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
$(obj)/vmlinux.strip: vmlinux
$(STRIP) -s -R .comment $< -o $@
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o
obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -183,6 +183,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+
+@@ -355,6 +356,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
+ image-$(CONFIG_KSI8560) += cuImage.ksi8560
+ image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
++image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100) += dtbImage.mvme7100
+
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -346,7 +346,8 @@ adder875-redboot)
+ binary=y
+ ;;
+ simpleboot-hiveap-330|\
+-simpleboot-tl-wdr4900-v1)
++simpleboot-tl-wdr4900-v1|\
++simpleboot-ws-ap3710i)
+ platformo="$object/fixed-head.o $object/simpleboot.o"
+ link_address='0x1500000'
+ binary=y
obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -183,6 +183,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
- src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+@@ -184,6 +184,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -355,6 +356,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
- image-$(CONFIG_KSI8560) += cuImage.ksi8560
+@@ -357,6 +358,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+image-$(CONFIG_WS_AP3825I) += simpleImage.ws-ap3825i
# Board ports in arch/powerpc/platform/86xx/Kconfig
image-$(CONFIG_MVME7100) += dtbImage.mvme7100
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -346,6 +346,7 @@ adder875-redboot)
- binary=y
+@@ -347,7 +347,8 @@ adder875-redboot)
;;
simpleboot-hiveap-330|\
-+simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
+ simpleboot-tl-wdr4900-v1|\
+-simpleboot-ws-ap3710i)
++simpleboot-ws-ap3710i|\
++simpleboot-ws-ap3825i)
platformo="$object/fixed-head.o $object/simpleboot.o"
link_address='0x1500000'
+ binary=y
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -356,6 +356,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
- image-$(CONFIG_KSI8560) += cuImage.ksi8560
+@@ -184,6 +184,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3715I) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
+
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+@@ -358,6 +359,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+image-$(CONFIG_WS_AP3715I) += simpleImage.ws-ap3715i
image-$(CONFIG_WS_AP3825I) += simpleImage.ws-ap3825i
# Board ports in arch/powerpc/platform/86xx/Kconfig
image-$(CONFIG_MVME7100) += dtbImage.mvme7100
---- a/arch/powerpc/boot/wrapper
-+++ b/arch/powerpc/boot/wrapper
-@@ -346,6 +346,7 @@ adder875-redboot)
- binary=y
- ;;
- simpleboot-hiveap-330|\
-+simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
- platformo="$object/fixed-head.o $object/simpleboot.o"
+src-plat-$(CONFIG_BR200_WP) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
- src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
-@@ -354,6 +355,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+@@ -356,6 +357,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
image-$(CONFIG_TQM8555) += cuImage.tqm8555
image-$(CONFIG_TQM8560) += cuImage.tqm8560
image-$(CONFIG_KSI8560) += cuImage.ksi8560
+image-$(CONFIG_BR200_WP) += simpleImage.br200-wp
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
- image-$(CONFIG_WS_AP3715I) += simpleImage.ws-ap3715i
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -345,6 +345,7 @@ adder875-redboot)
;;
+simpleboot-br200-wp|\
simpleboot-hiveap-330|\
- simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
+ simpleboot-tl-wdr4900-v1|\
+ simpleboot-ws-ap3710i|\
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -293,7 +293,6 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
+@@ -295,7 +295,6 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
image-$(CONFIG_PPC_HOLLY) += dtbImage.holly
image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
#
-@@ -418,15 +417,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
+@@ -421,15 +420,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
$(obj)/vmlinux.strip: vmlinux
$(STRIP) -s -R .comment $< -o $@
FEATURES:=fpu usb pci pcie gpio nand squashfs ramdisk boot-part rootfs-part legacy-sdcard targz
SUBTARGETS:=cortexa9 cortexa53 cortexa72
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
+++ /dev/null
-CONFIG_AHCI_MVEBU=y
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MVEBU=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARMADA_370_CLK=y
-CONFIG_ARMADA_370_XP_IRQ=y
-CONFIG_ARMADA_370_XP_TIMER=y
-# CONFIG_ARMADA_37XX_WATCHDOG is not set
-CONFIG_ARMADA_38X_CLK=y
-CONFIG_ARMADA_THERMAL=y
-CONFIG_ARMADA_XP_CLK=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
-# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GLOBAL_TIMER=y
-CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_MVEBU_V7_CPUIDLE=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_ATA_LEDS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_FEROCEON_L2 is not set
-CONFIG_CACHE_L2X0=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PJ4B=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_MARVELL=y
-CONFIG_CRYPTO_DEV_MARVELL_CESA=y
-CONFIG_CRYPTO_ESSIV=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM=y
-CONFIG_CRYPTO_SHA1_ARM_NEON=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SHA512_ARM=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_MVEBU_UART0=y
-# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
-# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0xd0012000
-CONFIG_DEBUG_UART_VIRT=0xfec12000
-CONFIG_DEBUG_USER=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MVEBU=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWBM=y
-CONFIG_HWMON=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MV64XXX=y
-# CONFIG_I2C_PXA is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_IWMMXT is not set
-CONFIG_JBD2=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PCA963X=y
-CONFIG_LEDS_TLC591XX=y
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACH_ARMADA_370=y
-# CONFIG_MACH_ARMADA_375 is not set
-CONFIG_MACH_ARMADA_38X=y
-# CONFIG_MACH_ARMADA_39X is not set
-CONFIG_MACH_ARMADA_XP=y
-# CONFIG_MACH_DOVE is not set
-CONFIG_MACH_MVEBU_ANY=y
-CONFIG_MACH_MVEBU_V7=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MANGLE_BOOTARGS=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_I2C=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MVSDIO=y
-CONFIG_MMC_SDHCI=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_PXAV3=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MARVELL=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_MVEBU_CLK_COMMON=y
-CONFIG_MVEBU_CLK_COREDIV=y
-CONFIG_MVEBU_CLK_CPU=y
-CONFIG_MVEBU_DEVBUS=y
-CONFIG_MVEBU_MBUS=y
-CONFIG_MVMDIO=y
-CONFIG_MVNETA=y
-CONFIG_MVNETA_BM=y
-CONFIG_MVNETA_BM_ENABLE=y
-# CONFIG_MVPP2 is not set
-CONFIG_MV_XOR=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6XXX=y
-CONFIG_NET_DSA_TAG_DSA=y
-CONFIG_NET_DSA_TAG_DSA_COMMON=y
-CONFIG_NET_DSA_TAG_EDSA=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVME_CORE=y
-# CONFIG_NVME_HWMON is not set
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_ORION_WATCHDOG=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCI_BRIDGE_EMUL=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_MVEBU=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_MVEBU_A3700_COMPHY is not set
-# CONFIG_PHY_MVEBU_A3700_UTMI is not set
-# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
-# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ARMADA_370=y
-CONFIG_PINCTRL_ARMADA_38X=y
-CONFIG_PINCTRL_ARMADA_XP=y
-CONFIG_PINCTRL_MVEBU=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PJ4B_ERRATA_4742=y
-CONFIG_PL310_ERRATA_753970=y
-CONFIG_PLAT_ORION=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_ARMADA38X=y
-# CONFIG_RTC_DRV_MV is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SATA_HOST=y
-CONFIG_SATA_MV=y
-CONFIG_SATA_PMP=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SENSORS_PWM_FAN=y
-CONFIG_SENSORS_TMP421=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MVEBU_CONSOLE=y
-CONFIG_SERIAL_MVEBU_UART=y
-CONFIG_SFP=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_ARMADA_3700 is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_ORION=y
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_ORION=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_LEDS_TRIGGER_USBPORT=y
-CONFIG_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_MVEBU=y
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARMADA_37XX_CLK=y
-CONFIG_ARMADA_37XX_RWTM_MBOX=y
-CONFIG_ARMADA_37XX_WATCHDOG=y
-CONFIG_ARMADA_AP806_SYSCON=y
-CONFIG_ARMADA_AP_CP_HELPER=y
-CONFIG_ARMADA_CP110_SYSCON=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
-CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-# CONFIG_ARM_MHU_V2 is not set
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_ARM_PSCI_FW=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MFD_SYSCON=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MMC_SDHCI_XENON=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MVEBU_GICP=y
-CONFIG_MVEBU_ICU=y
-CONFIG_MVEBU_ODMI=y
-CONFIG_MVEBU_PIC=y
-CONFIG_MVEBU_SEI=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI_AARDVARK=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MVEBU_A3700_COMPHY=y
-CONFIG_PHY_MVEBU_A3700_UTMI=y
-CONFIG_PINCTRL_AC5=y
-CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_PINCTRL_ARMADA_AP806=y
-CONFIG_PINCTRL_ARMADA_CP110=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPI_ARMADA_3700=y
-CONFIG_SWIOTLB=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TURRIS_MOX_RWTM=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_VMAP_STACK=y
-CONFIG_ZONE_DMA32=y
v "Writing new UUID to /dev/$diskdev..."
get_image_dd "$1" of="/dev/$diskdev" bs=1 skip=440 count=4 seek=440 conv=fsync
+ dd if=/dev/zero of=$(find_mmc_part rootfs_data) bs=512 count=8
+
sleep 1
}
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_AQUANTIA_PHY=y
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_SVE=y
-# CONFIG_ARM64_TAGGED_ADDR_ABI is not set
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARMADA_37XX_CLK=y
-CONFIG_ARMADA_AP806_SYSCON=y
-CONFIG_ARMADA_AP_CPU_CLK=y
-CONFIG_ARMADA_AP_CP_HELPER=y
-CONFIG_ARMADA_CP110_SYSCON=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
-CONFIG_ARM_ARMADA_8K_CPUFREQ=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-# CONFIG_ARM_PL172_MPMC is not set
-CONFIG_ARM_PSCI_FW=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CRC_CCITT=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_EEPROM_AT24=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_HW_RANDOM_OMAP=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_LEDS_IEI_WT61P803_PUZZLE=y
-CONFIG_LEDS_IS31FL319X=y
-CONFIG_MARVELL_10G_PHY=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_IEI_WT61P803_PUZZLE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MMC_SDHCI_XENON=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MVEBU_GICP=y
-CONFIG_MVEBU_ICU=y
-CONFIG_MVEBU_ODMI=y
-CONFIG_MVEBU_PIC=y
-CONFIG_MVEBU_SEI=y
-CONFIG_MVPP2=y
-CONFIG_MV_XOR_V2=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_LAYOUT_ONIE_TLV=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_ARMADA_8K=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-# CONFIG_PCI_AARDVARK is not set
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_MVEBU_CP110_COMPHY=y
-CONFIG_PHY_MVEBU_CP110_UTMI=y
-CONFIG_PINCTRL_AC5=y
-CONFIG_PINCTRL_ARMADA_37XX=y
-CONFIG_PINCTRL_ARMADA_AP806=y
-CONFIG_PINCTRL_ARMADA_CP110=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_REGULATOR_GPIO=y
-# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
-CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SWIOTLB=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_VMAP_STACK=y
-CONFIG_ZONE_DMA32=y
+++ /dev/null
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_IRQSTACKS=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_MTD_SPLIT_SEIL_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_VIRT_CONCAT=y
-CONFIG_PHY_MVEBU_A38X_COMPHY=y
-CONFIG_POWER_RESET_QNAP=y
-CONFIG_RTC_DRV_MV=y
-CONFIG_THREAD_INFO_IN_TASK=y
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Device Tree file for Buffalo LinkStation LS220DE
- *
- * Copyright (C) 2023 Daniel González Cabanelas <dgcbueu@gmail.com>
- */
-
-/dts-v1/;
-
-#include "armada-370.dtsi"
-#include "mvebu-linkstation-fan.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- model = "Buffalo LinkStation LS220DE";
- compatible = "buffalo,ls220de", "marvell,armada370", "marvell,armada-370-xp";
-
- aliases {
- led-boot = &led_boot;
- led-failsafe = &led_failsafe;
- led-running = &led_power;
- led-upgrade = &led_upgrade;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:115200n8";
- append-rootblock = "nullparameter="; /* override the bootloader args */
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>; /* 256 MB */
- };
-
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
- MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- };
-
- system_fan: gpio_fan {
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH
- &gpio0 14 GPIO_ACTIVE_HIGH>;
- alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
-
- #cooling-cells = <2>;
- };
-
- thermal-zones {
- hdd-thermal {
- polling-delay = <20000>;
- polling-delay-passive = <2000>;
-
- thermal-sensors = <&hdd0_temp>; /* only one drivetemp sensor is supported */
-
- trips {
- hdd_alert1: trip1 {
- temperature = <34000>;
- hysteresis = <2000>;
- type = "active";
- };
- hdd_alert2: trip2 {
- temperature = <40000>;
- hysteresis = <2000>;
- type = "active";
- };
- hdd_alert3: trip3 {
- temperature = <45000>;
- hysteresis = <2000>;
- type = "passive";
- };
- hdd_hot {
- temperature = <50000>;
- hysteresis = <2000>;
- type = "hot";
- };
- hdd_crit {
- temperature = <60000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map1 {
- trip = <&hdd_alert1>;
- cooling-device = <&system_fan THERMAL_NO_LIMIT 1>;
- };
- map2 {
- trip = <&hdd_alert2>;
- cooling-device = <&system_fan 2 2>;
- };
- map3 {
- trip = <&hdd_alert3>;
- cooling-device = <&system_fan 3 THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&pmx_buttons>;
- pinctrl-names = "default";
-
- power {
- label = "Power Switch";
- linux,code = <KEY_POWER>;
- linux,input-type = <EV_SW>;
- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
- };
-
- function {
- label = "Function Button";
- linux,code = <KEY_CONFIG>;
- gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio_leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
-
- indicator_red {
- function = LED_FUNCTION_INDICATOR;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_power: power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- led_failsafe: power_red {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- };
-
- led_upgrade: power_orange {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
- };
-
- led_boot: indicator_white {
- function = LED_FUNCTION_INDICATOR;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
- };
-
- hdd1_red {
- function = LED_FUNCTION_DISK;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ata1";
- function-enumerator = <1>;
- };
-
- hdd2_red {
- function = LED_FUNCTION_DISK;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ata2";
- function-enumerator = <2>;
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_power_hdd1 &pmx_power_hdd2>;
- pinctrl-names = "default";
-
- sata1_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "HDD1";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- startup-delay-us = <2000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
- };
-
- sata2_power: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "HDD2";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- startup-delay-us = <4000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&coherencyfab {
- broken-idle;
-};
-
-ð1 {
- pinctrl-0 = <&ge1_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-handle = <ðphy0>;
- phy-connection-type = "rgmii-id";
-};
-
-&mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */
- reg = <0>;
- marvell,reg-init = <0x3 0x10 0xf000 0x091A>, /* LED function */
- <0x3 0x11 0x0000 0x4401>, /* LED polarity */
- <0x3 0x12 0x0000 0x4905>; /* LED timer */
- #thermal-sensor-cells = <0>;
- };
-};
-
-&nand_controller {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- label = "pxa3xx_nand-0";
- nand-rb = <0>;
- marvell,nand-keep-config;
- nand-on-flash-bbt;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi_kernel";
- reg = <0x00000000 0x02000000>; /* 32 MiB */
- };
-
- partition@2000000 {
- label = "ubi";
- reg = <0x02000000 0x1df00000>; /* 479 MiB */
- };
- };
- };
-};
-
-&sata {
- nr-ports = <2>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- hdd0_temp: sata-port@0 {
- reg = <0>;
- #thermal-sensor-cells = <0>;
- };
-
- hdd1_temp: sata-port@1 {
- reg = <1>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&spi0 {
- status = "okay";
- pinctrl-0 = <&spi0_pins2>;
- pinctrl-names = "default";
-
- spi-flash@0 {
- compatible = "mxicy,mx25l8005", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- reg = <0x00000 0xf0000>; /* 960 KiB*/
- label = "u-boot";
- read-only;
- };
- partition@f0000 {
- reg = <0xf0000 0x10000>; /* 64 KiB */
- label = "u-boot-env";
- };
- };
- };
-};
-
-&pmsu {
- pinctrl-0 = <&pmx_power_cpu>;
- pinctrl-names = "default";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&pinctrl {
- pmx_power_hdd2: pmx-power-hdd2 {
- marvell,pins = "mpp2";
- marvell,function = "gpio";
- };
-
- pmx_power_cpu: pmx-power-cpu {
- marvell,pins = "mpp4";
- marvell,function = "vdd";
- };
-
- pmx_power_hdd1: pmx-power-hdd1 {
- marvell,pins = "mpp8";
- marvell,function = "gpio";
- };
-
- pmx_fan_lock: pmx-fan-lock {
- marvell,pins = "mpp10";
- marvell,function = "gpio";
- };
-
- pmx_hdd_present: pmx-hdd-present {
- marvell,pins = "mpp11", "mpp12";
- marvell,function = "gpio";
- };
-
- pmx_fan_high: pmx-fan-high {
- marvell,pins = "mpp13";
- marvell,function = "gpio";
- };
-
- pmx_fan_low: pmx-fan-low {
- marvell,pins = "mpp14";
- marvell,function = "gpio";
- };
-
- pmx_buttons: pmx-buttons {
- marvell,pins = "mpp15", "mpp16";
- marvell,function = "gpio";
- };
-
- pmx_leds1: pmx-leds {
- marvell,pins = "mpp7", "mpp54", "mpp59", "mpp61";
- marvell,function = "gpo";
- };
-
- pmx_leds2: pmx-leds {
- marvell,pins = "mpp55", "mpp57", "mpp62";
- marvell,function = "gpio";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Device Tree file for Buffalo LinkStation LS421DE
- *
- * Copyright (C) 2020 Daniel González Cabanelas <dgcbueu@gmail.com>
- */
-
-/dts-v1/;
-
-#include "armada-370.dtsi"
-#include "mvebu-linkstation-fan.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- model = "Buffalo LinkStation LS421DE";
- compatible = "buffalo,ls421de", "marvell,armada370", "marvell,armada-370-xp";
-
- aliases {
- led-boot = &led_boot;
- led-failsafe = &led_failsafe;
- led-running = &led_power;
- led-upgrade = &led_upgrade;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:115200n8";
- append-rootblock = "nullparameter="; /* override the bootloader args */
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>; /* 512 MB */
- };
-
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
- MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- };
-
- system_fan: gpio_fan {
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH
- &gpio0 14 GPIO_ACTIVE_HIGH>;
- alarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
-
- #cooling-cells = <2>;
- };
-
- thermal-zones {
- hdd-thermal {
- polling-delay = <20000>;
- polling-delay-passive = <2000>;
-
- thermal-sensors = <&hdd0_temp>; /* only one drivetemp sensor is supported */
-
- trips {
- hdd_alert1: trip1 {
- temperature = <36000>;
- hysteresis = <2000>;
- type = "active";
- };
- hdd_alert2: trip2 {
- temperature = <44000>;
- hysteresis = <2000>;
- type = "active";
- };
- hdd_alert3: trip3 {
- temperature = <52000>;
- hysteresis = <2000>;
- type = "passive";
- };
- hdd_crit: trip4 {
- temperature = <60000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map1 {
- trip = <&hdd_alert1>;
- cooling-device = <&system_fan THERMAL_NO_LIMIT 1>;
- };
- map2 {
- trip = <&hdd_alert2>;
- cooling-device = <&system_fan 2 2>;
- };
- map3 {
- trip = <&hdd_alert3>;
- cooling-device = <&system_fan 3 THERMAL_NO_LIMIT>;
- };
- };
- };
-
- ethphy-thermal {
- polling-delay = <20000>;
- polling-delay-passive = <2000>;
-
- thermal-sensors = <ðphy0>;
-
- trips {
- ethphy_alert1: trip1 {
- temperature = <65000>;
- hysteresis = <4000>;
- type = "passive";
- };
-
- ethphy_crit: trip2 {
- temperature = <100000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map1 {
- trip = <ðphy_alert1>;
- cooling-device = <&system_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-
- };
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&pmx_buttons>;
- pinctrl-names = "default";
-
- power {
- label = "Power Switch";
- linux,code = <KEY_POWER>;
- linux,input-type = <EV_SW>;
- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
- };
-
- function {
- label = "Function Button";
- linux,code = <KEY_CONFIG>;
- gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio_leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
-
- system_red {
- label = "ls421de:red:system";
- gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
- };
-
- led_power: power_white {
- label = "ls421de:white:power";
- gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- led_failsafe: power_red {
- label = "ls421de:red:power";
- gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- };
-
- led_upgrade: power_orange {
- label = "ls421de:orange:power";
- gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
- };
-
- led_boot: system_white {
- label = "ls421de:white:system";
- gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
- };
-
- hdd1_red {
- label = "ls421de:red:hdd1";
- gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ata1";
- };
-
- hdd2_red {
- label = "ls421de:red:hdd2";
- gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ata2";
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_power_usb &pmx_power_hdd1 &pmx_power_hdd2>;
- pinctrl-names = "default";
-
- usb_power: regulator@0 {
- compatible = "regulator-fixed";
- reg = <0>;
- regulator-name = "USB";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
- };
-
- sata1_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "HDD1";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- startup-delay-us = <2000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
- };
-
- sata2_power: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "HDD2";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- startup-delay-us = <4000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&coherencyfab {
- broken-idle;
-};
-
-ð1 {
- pinctrl-0 = <&ge1_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-handle = <ðphy0>;
- phy-connection-type = "rgmii-id";
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- clock-frequency = <100000>;
- status = "okay";
-
- rs5c372a: rs5c372a@32 {
- compatible = "ricoh,rs5c372a";
- reg = <0x32>;
- wakeup-source;
- };
-};
-
-&mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- ethphy0: ethernet-phy@0 { /* Marvell 88E1518 */
- reg = <0>;
- marvell,reg-init = <0x2 0x10 0xffff 0x0006>, /* disable CLK125 */
- <0x3 0x10 0x0000 0x1991>, /* LED function */
- <0x3 0x11 0x0000 0x4401>, /* LED polarity */
- <0x3 0x12 0x0000 0x4905>; /* LED timer */
- #thermal-sensor-cells = <0>;
- };
-};
-
-&pciec {
- status = "okay";
- pinctrl-0 = <&pmx_pcie>;
- pinctrl-names = "default";
-
- /* Connected to uPD720202 USB 3.0 Host */
- pcie@1,0 {
- status = "okay";
- };
-};
-
-&pmsu {
- pinctrl-0 = <&pmx_power_cpu>;
- pinctrl-names = "default";
-};
-
-&rtc {
- status = "disabled";
-};
-
-&sata {
- nr-ports = <2>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- hdd0_temp: sata-port@0 {
- reg = <0>;
- #thermal-sensor-cells = <0>;
- };
-
- hdd1_temp: sata-port@1 {
- reg = <1>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&sdio {
- pinctrl-0 = <&sdio_pins2>;
- pinctrl-names = "default";
- status = "okay";
- /* No CD or WP GPIOs */
- broken-cd;
-};
-
-&uart0 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
-};
-
-&nand_controller {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- label = "pxa3xx_nand-0";
- nand-rb = <0>;
- marvell,nand-keep-config;
- nand-on-flash-bbt;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "kernel";
- reg = <0x00000000 0x02000000>; /* 32 MiB */
- };
-
- partition@2000000 {
- label = "ubi";
- reg = <0x02000000 0x1e000000>; /* 480 MiB */
- };
- };
- };
-};
-
-&spi0 {
- status = "okay";
- pinctrl-0 = <&spi0_pins2>;
- pinctrl-names = "default";
-
- spi-flash@0 {
- compatible = "mxicy,mx25l8005", "jedec,spi-nor";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <50000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- reg = <0x00000 0xf0000>; /* 960 KiB*/
- label = "u-boot";
- read-only;
- };
- partition@f0000 {
- reg = <0xf0000 0x10000>; /* 64 KiB */
- label = "u-boot-env";
- };
- };
- };
-};
-
-&pinctrl {
- pmx_power_cpu: pmx-power-cpu {
- marvell,pins = "mpp4";
- marvell,function = "vdd";
- };
-
- pmx_power_usb: pmx-power-usb {
- marvell,pins = "mpp5";
- marvell,function = "gpo";
- };
-
- pmx_power_hdd1: pmx-power-hdd1 {
- marvell,pins = "mpp8";
- marvell,function = "gpio";
- };
-
- pmx_power_hdd2: pmx-power-hdd2 {
- marvell,pins = "mpp9";
- marvell,function = "gpo";
- };
-
- pmx_fan_lock: pmx-fan-lock {
- marvell,pins = "mpp10";
- marvell,function = "gpio";
- };
-
- pmx_hdd_present: pmx-hdd-present {
- marvell,pins = "mpp11", "mpp12";
- marvell,function = "gpio";
- };
-
- pmx_fan_high: pmx-fan-high {
- marvell,pins = "mpp13";
- marvell,function = "gpio";
- };
-
- pmx_fan_low: pmx-fan-low {
- marvell,pins = "mpp14";
- marvell,function = "gpio";
- };
-
- pmx_buttons: pmx-buttons {
- marvell,pins = "mpp15", "mpp16";
- marvell,function = "gpio";
- };
-
- pmx_leds1: pmx-leds {
- marvell,pins = "mpp7", "mpp54", "mpp59", "mpp61";
- marvell,function = "gpo";
- };
-
- pmx_leds2: pmx-leds {
- marvell,pins = "mpp55", "mpp57", "mpp62";
- marvell,function = "gpio";
- };
-
- pmx_pcie: pmx-pcie {
- marvell,pins = "mpp56", "mpp60";
- marvell,function = "pcie";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Device Tree file for Ctera C200-V2
- *
- * Copyright (C) 2021 Pawel Dembicki <paweldembicki@gmail.com>
- */
-
-/dts-v1/;
-
-#include "armada-370.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Ctera C200 V2";
- compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp";
-
- aliases {
- led-boot = &led_status_green;
- led-failsafe = &led_status_red;
- led-running = &led_status_green;
- led-upgrade = &led_status_red;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x40000000>; /* 1024 MB */
- };
-
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
- MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
- };
-
- thermal-zones {
- ethphy-thermal {
- polling-delay = <20000>;
- polling-delay-passive = <2000>;
-
- thermal-sensors = <ðphy0>;
-
- trips {
- ethphy_alert1: trip1 {
- temperature = <65000>;
- hysteresis = <4000>;
- type = "passive";
- };
-
- ethphy_crit: trip2 {
- temperature = <100000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&pmx_buttons>;
- pinctrl-names = "default";
-
- power {
- label = "Power Button";
- linux,code = <KEY_POWER>;
- gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
- };
-
- reset {
- label = "Reset Button";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
- };
-
- usb1 {
- label = "USB1 Button";
- linux,code = <BTN_0>;
- gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
- };
-
- usb2 {
- label = "USB2 Button";
- linux,code = <BTN_1>;
- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-poweroff {
- compatible = "gpio-poweroff";
- pinctrl-0 = <&pmx_poweroff>;
- pinctrl-names = "default";
- gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
- pinctrl-names = "default";
-
- led-0 {
- function = LED_FUNCTION_USB;
- function-enumerator = <2>;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
- };
-
- led-1 {
- function = LED_FUNCTION_USB;
- function-enumerator = <2>;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "usbport";
- trigger-sources = <&usb1_port 1>, <&usb2_port 1>;
- };
-
- led-2 {
- function = LED_FUNCTION_USB;
- function-enumerator = <1>;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
- };
-
- led-3 {
- function = LED_FUNCTION_USB;
- function-enumerator = <1>;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "usbport";
- trigger-sources = <&usb1_port 2>, <&usb2_port 2>;
- };
-
- led-4 {
- function = LED_FUNCTION_DISK;
- function-enumerator = <2>;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "ata2";
- };
-
- led-5 {
- function = LED_FUNCTION_DISK;
- function-enumerator = <1>;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
- };
-
- led-6 {
- function = LED_FUNCTION_DISK;
- function-enumerator = <2>;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
- };
-
- led-7 {
- function = LED_FUNCTION_INDICATOR;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
- };
-
- led-8 {
- function = LED_FUNCTION_DISK_ERR;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
- };
-
- led-9 {
- function = LED_FUNCTION_DISK_ERR;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
- };
-
- led_status_red: led-10 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
- };
-
- led-11 {
- function = LED_FUNCTION_DISK;
- function-enumerator = <1>;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "ata1";
- };
-
- led_status_green: led-12 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&coherencyfab {
- broken-idle;
-};
-
-ð1 {
- pinctrl-0 = <&ge1_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-handle = <ðphy0>;
- phy-connection-type = "rgmii-id";
-};
-
-&i2c0 {
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- clock-frequency = <100000>;
- status = "okay";
-
- hwmon@2a {
- compatible = "nuvoton,nct7802";
- reg = <0x2a>;
- };
-
- rtc@30 {
- compatible = "sii,s35390a";
- reg = <0x30>;
- };
-};
-
-&mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */
- reg = <0>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&nand_controller {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- label = "pxa3xx_nand-0";
- nand-rb = <0>;
- marvell,nand-keep-config;
- nand-on-flash-bbt;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "uboot";
- reg = <0x0000000 0x200000>;
- read-only;
- };
-
- partition@200000 {
- label = "certificate";
- reg = <0x0200000 0x100000>;
- read-only;
- };
-
- partition@300000 {
- label = "preset_cfg";
- reg = <0x0300000 0x100000>;
- read-only;
- };
-
- partition@400000 {
- label = "dev_params";
- reg = <0x0400000 0x100000>;
- read-only;
- };
- partition@500000 {
- label = "active_bank";
- reg = <0x0500000 0x0100000>;
- };
-
- partition@600000 {
- label = "magic";
- reg = <0x0600000 0x0100000>;
- read-only;
- };
-
- partition@700000 {
- label = "bank1";
- reg = <0x0700000 0x2800000>;
- };
-
- partition@2f00000 {
- label = "bank2";
- reg = <0x2f00000 0x2800000>;
- };
-
- /* 0x5700000-0x5a00000 undefined in vendor firmware */
-
- partition@5a00000 {
- label = "reserved";
- reg = <0x5a00000 0x2000000>;
- };
-
- partition@7a00000 {
- label = "ubi";
- reg = <0x7a00000 0x8600000>;
- };
- };
- };
-};
-
-&pciec {
- status = "okay";
-
- pcie@1,0 {
- pinctrl-0 = <&pmx_pcie>;
- pinctrl-names = "default";
- status = "okay";
- reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
-
- /* -[0000:00]---01.0-[01]----00.0 */
- /* usbport trigger won't work */
- bridge@0,1 {
- compatible = "pci11ab,6710";
- reg = <0x3800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- usb@1,0 {
- /* Renesas uPD720202 */
- compatible = "pci1912,0015";
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
-
- usb1_port: port@1 {
- reg = <1>;
- #trigger-source-cells = <1>;
- };
-
- usb2_port: port@2 {
- reg = <2>;
- #trigger-source-cells = <1>;
- };
- };
- };
- };
-};
-
-&pinctrl {
- pmx_poweroff: pmx-poweroff {
- marvell,pins = "mpp7";
- marvell,function = "gpo";
- };
-
- pmx_power_cpu: pmx-power-cpu {
- marvell,pins = "mpp4";
- marvell,function = "vdd";
- };
-
- pmx_buttons: pmx-buttons {
- marvell,pins = "mpp6", "mpp10", "mpp14", "mpp32";
- marvell,function = "gpio";
- };
-
- pmx_leds1: pmx-leds1 {
- marvell,pins = "mpp47";
- marvell,function = "gpo";
- };
-
- pmx_leds2: pmx-leds2 {
- marvell,pins = "mpp12", "mpp13", "mpp15", "mpp16", "mpp50", "mpp51",
- "mpp52", "mpp53", "mpp55", "mpp56", "mpp57", "mpp58";
- marvell,function = "gpio";
- };
-
- pmx_pcie: pmx-pcie {
- marvell,pins = "mpp59";
- marvell,function = "gpio";
- };
-
- /* this gpio is connected to the pin of buzzer
- * leave it as is due lack of proper driver
- */
- pmx_buzzer: pmx-buzzer {
- marvell,pins = "mpp63";
- marvell,function = "gpio";
- };
-};
-
-&pmsu {
- pinctrl-0 = <&pmx_power_cpu>;
- pinctrl-names = "default";
-};
-
-&rtc {
- status = "disabled";
-};
-
-&sata {
- nr-ports = <2>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- hdd0_temp: sata-port@0 {
- reg = <0>;
- #thermal-sensor-cells = <0>;
- };
-
- hdd1_temp: sata-port@1 {
- reg = <1>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&uart0 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include "armada-380.dtsi"
-
-/ {
- model = "IIJ SA-W2";
- compatible = "iij,sa-w2", "marvell,armada380";
-
- aliases {
- led-boot = &led_power_green;
- led-failsafe = &led_power_red;
- led-running = &led_power_green;
- led-upgrade = &led_power_green;
- label-mac-device = &ge0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x10000000>; /* 256MB */
- };
-
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
- MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
- MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
-
- pcie {
- status = "okay";
-
- pcie@1,0 {
- status = "okay";
- };
-
- pcie@3,0 {
- status = "okay";
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_keys_pins>;
-
- button-init {
- label = "init";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_leds_pins>;
-
- led-0 {
- gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "phy0tpt";
- };
-
- led-1 {
- gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- };
-
- led-2 {
- gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- };
-
- led-3 {
- gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_STATUS;
- };
-
- led-4 {
- gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- };
-
- led-5 {
- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- };
-
- led-6 {
- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "phy1tpt";
- };
-
- led-7 {
- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- };
-
- led_power_green: led-8 {
- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- };
-
- led_power_red: led-9 {
- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- };
-
- led-10 {
- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "usbport";
- trigger-sources = <&hub_port2>;
- };
-
- led-11 {
- gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "usbport";
- trigger-sources = <&hub_port1>;
- };
- };
-
- regulator-vbus-usb0 {
- compatible = "regulator-fixed";
- regulator-name = "vbus-usb0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- regulator-vbus-usb1 {
- compatible = "regulator-fixed";
- regulator-name = "vbus-usb1";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 21 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
-};
-
-&pinctrl {
- pmx_usb_pins: usb-pins {
- marvell,pins = "mpp2", /* smsc usb2514b reset */
- "mpp48", "mpp49", /* port over current */
- "mpp52", "mpp53"; /* port vbus */
- marvell,function = "gpio";
- };
-
- pmx_keys_pins: keys-pins {
- marvell,pins = "mpp18";
- marvell,function = "gpio";
- };
-
- pmx_leds_pins: leds-pins {
- marvell,pins = "mpp19", "mpp20", "mpp33", "mpp34", "mpp35",
- "mpp36", "mpp44", "mpp45", "mpp46", "mpp47",
- "mpp54", "mpp55";
- marvell,function = "gpio";
- };
-};
-
-&gpio0 {
- usb-hub-reset {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-high;
- };
-};
-
-&usb0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_usb_pins>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* SMSC USB2514B on PCB */
- hub@1 {
- compatible = "usb424,2514";
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- hub_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- hub_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
-};
-
-&bm {
- status = "okay";
-};
-
-&bm_bppi {
- status = "okay";
-};
-
-ð1 {
- pinctrl-names = "default";
- pinctrl-0 = <&ge1_rgmii_pins>;
- status = "okay";
-
- phy-connection-type = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
- bm,pool-short = <3>;
-
- nvmem-cells = <&macaddr_bdinfo_6 1>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&mdio {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>;
- status = "okay";
-
- /* Marvell 88E6172 */
- switch@0 {
- compatible = "marvell,mv88e6085";
- reg = <0x0>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gpio1>;
- interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "ge1_0";
- };
-
- port@1 {
- reg = <1>;
- label = "ge1_1";
- };
-
- port@2 {
- reg = <2>;
- label = "ge1_2";
- };
-
- port@3 {
- reg = <3>;
- label = "ge1_3";
- };
-
- ge0: port@4 {
- reg = <4>;
- label = "ge0";
- nvmem-cells = <&macaddr_bdinfo_6 0>;
- nvmem-cell-names = "mac-address";
- };
-
- /*
- * eth0 is connected to port5 for WAN connection
- * on port4 ("GE0")
- */
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <ð1>;
- phy-connection-type = "rgmii-id";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-};
-
-&rtc {
- status = "disabled";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- reg = <0x0 0x100000>;
- label = "bootloader";
- read-only;
- };
-
- partition@100000 {
- reg = <0x100000 0x10000>;
- label = "bootloader-env";
- read-only;
- };
-
- partition@110000 {
- reg = <0x110000 0xf0000>;
- label = "board_info";
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_bdinfo_6: macaddr@6 {
- compatible = "mac-base";
- reg = <0x6 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@200000 {
- compatible = "iij,seil-firmware";
- reg = <0x200000 0xf00000>;
- label = "firmware";
- iij,bootdev-name = "flash";
- iij,seil-id = <0x5345494c 0x32303135>;
- };
-
- partition@1100000 {
- compatible = "iij,seil-firmware";
- reg = <0x1100000 0xf00000>;
- label = "rescue";
- iij,bootdev-name = "rescue";
- iij,seil-id = <0x5345494c 0x32303135>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "armada-385-fortinet-fg-x0e.dtsi"
-
-/ {
- model = "Fortinet FortiGate 30E";
- compatible = "fortinet,fg-30e", "marvell,armada385", "marvell,armada380";
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x40000000>; /* 1GB */
- };
-};
-
-&gpio_leds {
- led-14 {
- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
- };
-
- led-15 {
- gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
- };
-};
-
-&pinctrl {
- pmx_switch_pins: switch-pins {
- marvell,pins = "mpp19";
- marvell,function = "gpio";
- };
-};
-
-&mdio {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>, <&pmx_switch_pins>;
-
- /* Marvell 88E6176 */
- switch@2 {
- compatible = "marvell,mv88e6085";
- reg = <0x2>;
- reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "wan";
- nvmem-cells = <&macaddr_bdinfo_d880 1>;
- nvmem-cell-names = "mac-address";
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- nvmem-cells = <&macaddr_bdinfo_d880 5>;
- nvmem-cell-names = "mac-address";
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- nvmem-cells = <&macaddr_bdinfo_d880 4>;
- nvmem-cell-names = "mac-address";
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- nvmem-cells = <&macaddr_bdinfo_d880 3>;
- nvmem-cell-names = "mac-address";
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- nvmem-cells = <&macaddr_bdinfo_d880 2>;
- nvmem-cell-names = "mac-address";
- };
-
- port@6 {
- reg = <6>;
- ethernet = <ð0>;
- phy-connection-type = "rgmii-id";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "armada-385-fortinet-fg-x0e.dtsi"
-
-/ {
- model = "Fortinet FortiGate 50E";
- compatible = "fortinet,fg-50e", "marvell,armada385", "marvell,armada380";
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x80000000>; /* 2GB */
- };
-};
-
-&gpio_leds {
- led-14 {
- gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "f1072004.mdio-mii:00:1Gbps";
- };
-
- led-15 {
- gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "f1072004.mdio-mii:01:1Gbps";
- };
-
- led-16 {
- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
- };
-
- led-17 {
- gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
- };
-};
-
-&pinctrl {
- pmx_phy_switch_pins: phy-switch-pins {
- marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41";
- marvell,function = "gpio";
- };
-};
-
-ð1 {
- status = "okay";
-
- phy-handle = <ðphy0>;
- phy-connection-type = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
- nvmem-cells = <&macaddr_bdinfo_d880 1>;
- nvmem-cell-names = "mac-address";
-};
-
-ð2 {
- status = "okay";
-
- phy-handle = <ðphy1>;
- phy-connection-type = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <3>;
- nvmem-cells = <&macaddr_bdinfo_d880 2>;
- nvmem-cell-names = "mac-address";
-};
-
-&mdio {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>;
-
- /* Marvell 88E1512 */
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0141,0dd1",
- "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- interrupt-parent = <&gpio0>;
- interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <10000>;
- /*
- * LINK/ACT (Green): LED[0], Active Low
- * SPEED 100M (Amber): LED[1], Active High
- */
- marvell,reg-init = <3 16 0 0x71>,
- <3 17 0 0x4>;
- };
-
- /* Marvell 88E1512 */
- ethphy1: ethernet-phy@1 {
- compatible = "ethernet-phy-id0141,0dd1",
- "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&gpio1>;
- interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <10000>;
- /*
- * LINK/ACT (Green): LED[0], Active Low
- * SPEED 100M (Amber): LED[1], Active High
- */
- marvell,reg-init = <3 16 0 0x71>,
- <3 17 0 0x4>;
- };
-
- /* Marvell 88E6176 */
- switch@2 {
- compatible = "marvell,mv88e6085";
- reg = <0x2>;
- reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan5";
- nvmem-cells = <&macaddr_bdinfo_d880 7>;
- nvmem-cell-names = "mac-address";
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- nvmem-cells = <&macaddr_bdinfo_d880 6>;
- nvmem-cell-names = "mac-address";
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- nvmem-cells = <&macaddr_bdinfo_d880 5>;
- nvmem-cell-names = "mac-address";
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- nvmem-cells = <&macaddr_bdinfo_d880 4>;
- nvmem-cell-names = "mac-address";
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- nvmem-cells = <&macaddr_bdinfo_d880 3>;
- nvmem-cell-names = "mac-address";
- };
-
- port@6 {
- reg = <6>;
- ethernet = <ð0>;
- phy-connection-type = "rgmii-id";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include "armada-385.dtsi"
-
-/ {
- aliases {
- led-boot = &led_status_green;
- led-failsafe = &led_status_red;
- led-running = &led_status_green;
- led-upgrade = &led_status_green;
- label-mac-device = ð0;
- };
-
- chosen {
- stdout-path = "serial0:9600n8";
- };
-
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
- MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
- MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_gpio_keys_pins>;
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio_leds: gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_gpio_leds_pins>;
-
- led-0 {
- gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_ALARM;
- };
-
- led-1 {
- gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_RED>;
- };
-
- led_status_green: led-2 {
- gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- };
-
- led-3 {
- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- };
-
- led-4 {
- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_ALARM;
- };
-
- led_status_red: led-5 {
- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_STATUS;
- };
-
- led-6 {
- gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "mv88e6xxx-1:01:1Gbps";
- };
-
- led-7 {
- gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- linux,default-trigger = "mv88e6xxx-1:01:100Mbps";
- };
-
- led-8 {
- gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- linux,default-trigger = "mv88e6xxx-1:02:100Mbps";
- };
-
- led-9 {
- gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "mv88e6xxx-1:02:1Gbps";
- };
-
- led-10 {
- gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "mv88e6xxx-1:04:1Gbps";
- };
-
- led-11 {
- gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- linux,default-trigger = "mv88e6xxx-1:04:100Mbps";
- };
-
- led-12 {
- gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "mv88e6xxx-1:03:1Gbps";
- };
-
- led-13 {
- gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- linux,default-trigger = "mv88e6xxx-1:03:100Mbps";
- };
- };
-
- reg_usb_vbus: regulator-usb-vbus {
- compatible = "fixed-regulator";
- regulator-name = "usb-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
- regulator-always-on;
- };
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
-
- gpio2: gpio@24 {
- compatible = "nxp,pca9555";
- reg = <0x24>;
- gpio-controller;
- #gpio-cells = <0x2>;
- };
-
- hwmon@28 {
- compatible = "nuvoton,nct7802";
- reg = <0x28>;
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
-};
-
-&pinctrl {
- pmx_gpio_leds_pins: gpio-leds-pins {
- marvell,pins = "mpp30", "mpp32", "mpp33", "mpp35",
- "mpp45", "mpp47";
- marvell,function = "gpio";
- };
-
- pmx_usb_pins: usb-pins {
- marvell,pins = "mpp53";
- marvell,function = "gpio";
- };
-
- pmx_gpio_keys_pins: gpio-keys-pins {
- marvell,pins = "mpp54";
- marvell,function = "gpio";
- };
-};
-
-&bm {
- status = "okay";
-};
-
-&bm_bppi {
- status = "okay";
-};
-
-ð0 {
- pinctrl-names = "default";
- pinctrl-0 = <&ge0_rgmii_pins>;
- status = "okay";
-
- phy-connection-type = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <0>;
- bm,pool-short = <1>;
- nvmem-cells = <&macaddr_bdinfo_d880 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&usb3_0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_usb_pins>;
- status = "okay";
-
- vbus-supply = <®_usb_vbus>;
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- reg = <0x0 0x1c0000>;
- label = "u-boot";
- read-only;
- };
-
- partition@1c0000 {
- reg = <0x1c0000 0x10000>;
- label = "firmware-info";
-
- /*
- * 0x10 - 0x2f : image name (image1)
- * 0x30 - 0x4f : image name (image2)
- * 0x170 (1byte): active image (0x0/0x1)
- * 0x184 - 0x185: kernel block count (image1)
- * 0x18c - 0x18d: rootfs block count (image1)
- * 0x194 - 0x195: kernel block count (image2)
- * 0x19c - 0x19d: rootfs block count (image2)
- * 0x1be (1byte): bit7 -> active flag (image1)?
- * 0x1ce (1byte): bit7 -> active flag (image2)?
- *
- * Note: block size --> 0x200 (512 bytes)
- */
- };
-
- partition@1d0000 {
- reg = <0x1d0000 0x10000>;
- label = "dtb";
- read-only;
- };
-
- partition@1e0000 {
- reg = <0x1e0000 0x10000>;
- label = "u-boot-env";
- read-only;
- };
-
- partition@1f0000 {
- reg = <0x1f0000 0x10000>;
- label = "board-info";
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_bdinfo_d880: macaddr@d880 {
- compatible = "mac-base";
- reg = <0xd880 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@200000 {
- reg = <0x200000 0x600000>;
- label = "kernel";
- };
-
- partition@800000 {
- reg = <0x800000 0x1800000>;
- label = "rootfs";
- };
-
- partition@2000000 {
- reg = <0x2000000 0x600000>;
- label = "kn2";
- read-only;
- };
-
- partition@2600000 {
- reg = <0x2600000 0x1800000>;
- label = "rfs2";
- read-only;
- };
-
- partition@3e00000 {
- reg = <0x3e00000 0x1200000>;
- label = "part1";
- read-only;
- };
-
- partition@5000000 {
- reg = <0x5000000 0x1200000>;
- label = "part2";
- read-only;
- };
-
- partition@6200000 {
- reg = <0x6200000 0x1e00000>;
- label = "config";
- read-only;
- };
- };
- };
-};
+++ /dev/null
-/*
- * Device Tree file for the Linksys WRT32X (Venom)
- *
- * Copyright (C) 2017 Imre Kaloz <kaloz@openwrt.org>
- *
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "armada-385-linksys.dtsi"
-
-/ {
- model = "Linksys WRT32X";
- compatible = "linksys,wrt32x", "linksys,venom", "linksys,armada385",
- "marvell,armada385", "marvell,armada380";
-
- chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- append-rootblock = "root=/dev/mtdblock";
- };
-};
-
-&expander0 {
- wan_amber@0 {
- label = "venom:amber:wan";
- reg = <0x0>;
- };
-
- wan_blue@1 {
- label = "venom:blue:wan";
- reg = <0x1>;
- };
-
- usb2@5 {
- label = "venom:blue:usb2";
- reg = <0x5>;
- };
-
- usb3_1@6 {
- label = "venom:blue:usb3_1";
- reg = <0x6>;
- };
-
- usb3_2@7 {
- label = "venom:blue:usb3_2";
- reg = <0x7>;
- };
-
- wps_blue@8 {
- label = "venom:blue:wps";
- reg = <0x8>;
- };
-
- wps_amber@9 {
- label = "venom:amber:wps";
- reg = <0x9>;
- };
-};
-
-&gpio_leds {
- power {
- gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
- label = "venom:blue:power";
- };
-
- sata {
- gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
- label = "venom:blue:sata";
- };
-
- wlan_2g {
- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
- label = "venom:blue:wlan_2g";
- };
-
- wlan_5g {
- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
- label = "venom:blue:wlan_5g";
- };
-};
-
-&gpio_leds_pins {
- marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56";
-};
-
-&nand {
- /* Spansion S34ML02G2 256MiB, OEM Layout */
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x200000>; /* 2MB */
- read-only;
- };
-
- partition@200000 {
- label = "u_env";
- reg = <0x200000 0x20000>; /* 128KB */
- };
-
- partition@220000 {
- label = "s_env";
- reg = <0x220000 0x40000>; /* 256KB */
- };
-
- partition@180000 {
- label = "unused_area";
- reg = <0x260000 0x5c0000>; /* 5.75MB */
- };
-
- partition@7e0000 {
- label = "devinfo";
- reg = <0x7e0000 0x40000>; /* 256KB */
- read-only;
- };
-
- /* kernel1 overlaps with rootfs1 by design */
- partition@900000 {
- label = "kernel1";
- reg = <0x900000 0x7b00000>; /* 123MB */
- };
-
- partition@f00000 {
- label = "rootfs1";
- reg = <0xf00000 0x7500000>; /* 117MB */
- };
-
- /* kernel2 overlaps with rootfs2 by design */
- partition@8400000 {
- label = "kernel2";
- reg = <0x8400000 0x7b00000>; /* 123MB */
- };
-
- partition@8a00000 {
- label = "rootfs2";
- reg = <0x8a00000 0x7500000>; /* 117MB */
- };
-
- /* last MB is for the BBT, not writable */
- partition@ff00000 {
- label = "BBT";
- reg = <0xff00000 0x100000>;
- };
- };
-};
-
-
-&pcie1 {
- mwlwifi {
- marvell,chainmask = <4 4>;
- };
-};
-
-&pcie2 {
- mwlwifi {
- marvell,chainmask = <4 4>;
- };
-};
-
-&sdhci {
- pinctrl-names = "default";
- pinctrl-0 = <&sdhci_pins>;
- no-1-8-v;
- non-removable;
- wp-inverted;
- bus-width = <8>;
- status = "okay";
-};
-
-&usb3_1_vbus {
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-};
-
-&usb3_1_vbus_pins {
- marvell,pins = "mpp44";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
-/*
- * Device Tree file for ipTIME NAS1dual
- *
- * Copyright (C) 2020 Sungbo Eo <mans0n@gorani.run>
- *
- * Based on armada-385-linksys.dtsi
- * Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include "armada-385.dtsi"
-
-/ {
- model = "ipTIME NAS1dual";
- compatible = "iptime,nas1dual", "marvell,armada385", "marvell,armada380";
-
- aliases {
- led-boot = &led_ready;
- led-failsafe = &led_ready;
- led-running = &led_ready;
- led-upgrade = &led_ready;
- label-mac-device = ð0;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8";
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x80000000>; /* 2GB */
- };
-
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
- MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
- MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pins>;
-
- power {
- label = "Power Button";
- linux,input-type = <EV_SW>;
- linux,code = <KEY_POWER>;
- gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
- };
-
- reset {
- label = "Reset Button";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
- };
-
- copy {
- label = "USB Copy Button";
- linux,code = <KEY_COPY>;
- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_leds_pins>;
-
- led_ready: ready {
- label = "blue:ready";
- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
- };
-
- hdd {
- label = "blue:hdd";
- gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "disk-activity";
- };
-
- usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
- trigger-sources = <&usb3_0_port1 &usb3_0_port2>;
- linux,default-trigger = "usbport";
- };
- };
-
- gpio-fan {
- compatible = "gpio-fan";
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_fan_pins>;
- gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>,
- <&gpio1 18 GPIO_ACTIVE_HIGH>;
- /* We don't know the exact rpm, just use dummy values here. */
- gpio-fan,speed-map = <0 0>, <1 1>, <2 2>;
- #cooling-cells = <2>;
- };
-
- gpio-poweroff {
- compatible = "gpio-poweroff";
- gpios = <&pca9536 1 GPIO_ACTIVE_LOW>;
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&sata_power_pins>;
-
- reg_sata_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "sata-power";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- gpio = <&gpio1 20 GPIO_ACTIVE_LOW>;
- regulator-always-on;
- };
- };
-};
-
-&ahci0 {
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sata-port@0 {
- reg = <0>;
- target-supply = <®_sata_power>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&bm {
- status = "okay";
-};
-
-&bm_bppi {
- status = "okay";
-};
-
-ð0 {
- pinctrl-names = "default";
- pinctrl-0 = <&ge0_rgmii_pins>;
- status = "okay";
- phy-handle = <ðphy1>;
- phy-connection-type = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <0>;
- bm,pool-short = <1>;
- nvmem-cells = <&macaddr_uboot_fffa8>;
- nvmem-cell-names = "mac-address";
-};
-
-ð1 {
- pinctrl-names = "default";
- pinctrl-0 = <&ge1_rgmii_pins>;
- status = "okay";
- phy-handle = <ðphy0>;
- phy-connection-type = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
- bm,pool-short = <3>;
- nvmem-cells = <&macaddr_uboot_fffa8>;
- nvmem-cell-names = "mac-address";
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
-
- pca9536: gpio@41 {
- compatible = "nxp,pca9536";
- reg = <0x41>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "power-led", "power-board";
- };
-};
-
-&mdio {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>;
-
- /* LED1: On - Link, Blink - Activity, Off - No Link */
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- marvell,reg-init = <3 16 0 0x1017>;
- };
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- marvell,reg-init = <3 16 0 0x1017>;
- };
-};
-
-&pinctrl {
- gpio_keys_pins: gpio-keys-pins {
- marvell,pins = "mpp24", "mpp26", "mpp48";
- marvell,function = "gpio";
- };
-
- gpio_leds_pins: gpio-leds-pins {
- marvell,pins = "mpp18", "mpp20", "mpp51";
- marvell,function = "gpio";
- };
-
- gpio_fan_pins: gpio-fan-pins {
- marvell,pins = "mpp25", "mpp50";
- marvell,function = "gpio";
- };
-
- sata_power_pins: sata-power-pins {
- marvell,pins = "mpp52";
- marvell,function = "gpio";
- };
-
- uart1_pins_alt: uart-pins-1-alt {
- marvell,pins = "mpp45", "mpp46";
- marvell,function = "ua1";
- };
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- reg = <0x00000000 0x00100000>;
- label = "u-boot";
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_uboot_fffa8: macaddr@fffa8 {
- reg = <0xfffa8 0x6>;
- };
- };
- };
-
- partition@100000 {
- reg = <0x00100000 0x03ec0000>;
- label = "firmware";
-
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- reg = <0x00000000 0x00600000>;
- label = "kernel";
- };
-
- partition@600000 {
- reg = <0x00600000 0x038c0000>;
- label = "rootfs";
- };
- };
-
- partition@3fc0000 {
- reg = <0x03fc0000 0x00040000>;
- label = "config";
- read-only;
- };
- };
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_alt>;
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_0_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_0_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include "armada-3720-uDPU.dtsi"
-
-/ {
- model = "Methode eDPU Board";
- compatible = "methode,edpu", "marvell,armada3720", "marvell,armada3710";
-};
-
-/* PHY mode is set to 1000Base-X despite Maxlinear IC being capable of
- * 2500Base-X since until 5.15 support for mvebu is available trying to
- * use 2500Base-X will cause buffer overruns for which the fix is not
- * easily backportable.
- */
-ð0 {
- phy-mode = "1000base-x";
-};
-
-/*
- * External MV88E6361 switch is only available on v2 of the board.
- * U-Boot will enable the MDIO bus and switch nodes.
- */
-&mdio {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&smi_pins>;
-
- /* Actual device is MV88E6361 */
- switch: switch@0 {
- compatible = "marvell,mv88e6190";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- phy-mode = "2500base-x";
- managed = "in-band-status";
- ethernet = <ð0>;
- };
-
- port@9 {
- reg = <9>;
- label = "downlink";
- phy-mode = "2500base-x";
- managed = "in-band-status";
- };
-
- port@a {
- reg = <10>;
- label = "uplink";
- phy-mode = "2500base-x";
- managed = "in-band-status";
- sfp = <&sfp_eth1>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree file for ESPRESSObin-Ultra
- * Copyright (C) 2019 Globalscale technologies, Inc.
- *
- * Jason Hung <jhung@globalscaletechnologies.com>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include "armada-372x.dtsi"
-
-/ {
- model = "Globalscale Marvell ESPRESSOBin Ultra Board";
- compatible = "globalscale,espressobin-ultra", "marvell,armada3720",
- "marvell,armada3710";
-
- aliases {
- /* for dsa slave device */
- ethernet1 = &switch0port1;
- ethernet2 = &switch0port2;
- ethernet3 = &switch0port3;
- ethernet4 = &switch0port4;
- ethernet5 = &switch0port5;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
- };
-
- reg_usb3_vbus: usb3-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb3-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>;
- };
-
- usb3_phy: usb3-phy {
- compatible = "usb-nop-xceiv";
- vcc-supply = <®_usb3_vbus>;
- };
-
- leds {
- pinctrl-names = "default";
- compatible = "gpio-leds";
- /* No assigned functions to the LEDs by default */
- led1 {
- label = "ebin-ultra:blue:led1";
- gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
- };
- led2 {
- label = "ebin-ultra:green:led2";
- gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
- };
- led3 {
- label = "ebin-ultra:red:led3";
- gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
- };
- led4 {
- label = "ebin-ultra:yellow:led4";
- gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
-&sdhci0 {
- status = "okay";
- non-removable;
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs400-1_8v;
- marvell,pad-type = "fixed-1-8v";
-};
-
-&spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spi_quad_pins>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <108000000>;
- spi-rx-bus-width = <4>;
- spi-tx-bus-width = <4>;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "firmware";
- reg = <0x0 0x3e0000>;
- };
- partition@3e0000 {
- label = "hw-info";
- reg = <0x3e0000 0x10000>;
- read-only;
- };
- partition@3f0000 {
- label = "u-boot-env";
- reg = <0x3f0000 0x10000>;
- };
- };
- };
-};
-
-&uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
-
- clock-frequency = <100000>;
-
- rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
-};
-
-&usb3 {
- status = "okay";
- usb-phy = <&usb3_phy>;
-};
-
-&usb2 {
- status = "okay";
-};
-
-ð0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii-id";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&mdio {
- status = "okay";
-
- extphy: ethernet-phy@0 {
- reg = <1>;
- };
-
- switch0: switch0@1 {
- compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
-
- dsa,member = <0 0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- switch0port0: port@0 {
- reg = <0>;
- ethernet = <ð0>;
- };
-
- switch0port1: port@1 {
- reg = <1>;
- label = "lan0";
- phy-handle = <&switch0phy1>;
- };
-
- switch0port2: port@2 {
- reg = <2>;
- label = "lan1";
- phy-handle = <&switch0phy2>;
- };
-
- switch0port3: port@3 {
- reg = <3>;
- label = "lan2";
- phy-handle = <&switch0phy3>;
- };
-
- switch0port4: port@4 {
- reg = <4>;
- label = "lan3";
- phy-handle = <&switch0phy4>;
- };
-
- switch0port5: port@5 {
- reg = <5>;
- label = "wan";
- phy-handle = <&extphy>;
- phy-mode = "sgmii";
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- switch0phy1: switch0phy1@11 {
- reg = <0x11>;
- };
- switch0phy2: switch0phy2@12 {
- reg = <0x12>;
- };
- switch0phy3: switch0phy3@13 {
- reg = <0x13>;
- };
- switch0phy4: switch0phy4@14 {
- reg = <0x14>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-
-/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include "armada-372x.dtsi"
-
-/ {
- model = "GL.iNet GL-MV1000";
- compatible = "glinet,gl-mv1000", "marvell,armada3720";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
- };
-
- vcc_sd_reg1: regulator {
- compatible = "regulator-gpio";
- regulator-name = "vcc_sd1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
-
- gpios-states = <0>;
- states = <1800000 0x1
- 3300000 0x0>;
- enable-active-high;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
- };
-
- switch {
- label = "switch";
- linux,code = <BTN_0>;
- gpios = <&gpiosb 22 GPIO_ACTIVE_LOW>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- vpn {
- label = "green:vpn";
- gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
- };
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
- default-state = "on";
- };
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <104000000>;
- m25p,fast-read;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0 0xf0000>;
- read-only;
- };
-
- partition@f0000 {
- label = "u-boot-env";
- reg = <0xf0000 0x8000>;
- read-only;
- };
-
- factory: partition@f8000 {
- label = "factory";
- reg = <0xf8000 0x8000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_factory_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_factory_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
- };
- };
-
- partition@100000 {
- label = "gl-firmware-dtb";
- reg = <0x100000 0x10000>;
- read-only;
- };
-
- partition@110000 {
- label = "gl-firmware";
- reg = <0x110000 0xef0000>;
- read-only;
- };
-
- partition@ef0000 {
- label = "gl-firmware-jffs2";
- reg = <0xef0000 0x110000>;
- read-only;
- };
- };
- };
-};
-
-&sdhci1 {
- wp-inverted;
- bus-width = <4>;
- cd-gpios = <&gpionb 17 GPIO_ACTIVE_LOW>;
- marvell,pad-type = "sd";
- no-1-8-v;
- vqmmc-supply = <&vcc_sd_reg1>;
- status = "okay";
-};
-
-&sdhci0 {
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs400-1_8v;
- non-removable;
- no-sd;
- no-sdio;
- marvell,pad-type = "fixed-1-8v";
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&uart0 {
- status = "okay";
-};
-
-&mdio {
- switch0: switch0@1 {
- compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- dsa,member = <0 0>;
-
- ports: ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- ethernet = <ð0>;
- };
-
- port@1 {
- reg = <1>;
- label = "wan";
- phy-handle = <&switch0phy0>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan0";
- phy-handle = <&switch0phy1>;
-
- nvmem-cells = <&macaddr_factory_6>;
- nvmem-cell-names = "mac-address";
- };
-
- port@3 {
- reg = <3>;
- label = "lan1";
- phy-handle = <&switch0phy2>;
-
- nvmem-cells = <&macaddr_factory_6>;
- nvmem-cell-names = "mac-address";
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- switch0phy0: switch0phy0@11 {
- reg = <0x11>;
- };
- switch0phy1: switch0phy1@12 {
- reg = <0x12>;
- };
- switch0phy2: switch0phy2@13 {
- reg = <0x13>;
- };
- };
- };
-};
-
-ð0 {
- nvmem-cells = <&macaddr_factory_0>;
- nvmem-cell-names = "mac-address";
- phy-mode = "rgmii-id";
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-
-#include "armada-3720-uDPU.dtsi"
-
-/ {
- model = "Methode uDPU Board";
- compatible = "methode,udpu", "marvell,armada3720", "marvell,armada3710";
-
- sfp_eth0: sfp-eth0 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
- maximum-power-milliwatt = <3000>;
- };
-};
-
-&pinctrl_nb {
- i2c1_recovery_pins: i2c1-recovery-pins {
- groups = "i2c1";
- function = "gpio";
- };
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default", "recovery";
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-1 = <&i2c1_recovery_pins>;
- /delete-property/mrvl,i2c-fast-mode;
- scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-ð0 {
- phy-mode = "2500base-x";
- sfp = <&sfp_eth0>;
-};
-
-ð1 {
- phy-mode = "2500base-x";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device tree for the uDPU board.
- * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
- * Copyright (C) 2016 Marvell
- * Copyright (C) 2019 Methode Electronics
- * Copyright (C) 2019 Telus
- *
- * Vladimir Vid <vladimir.vid@sartura.hr>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include "armada-372x.dtsi"
-
-/ {
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
- };
-
- aliases {
- ethernet0 = ð0;
- ethernet1 = ð1;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-power1 {
- label = "udpu:green:power";
- gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
- };
-
- led-power2 {
- label = "udpu:red:power";
- gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
- };
-
- led-network1 {
- label = "udpu:green:network";
- gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
- };
-
- led-network2 {
- label = "udpu:red:network";
- gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
- };
-
- led-alarm1 {
- label = "udpu:green:alarm";
- gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
- };
-
- led-alarm2 {
- label = "udpu:red:alarm";
- gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
- };
- };
-
- sfp_eth1: sfp-eth1 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
- maximum-power-milliwatt = <3000>;
- };
-};
-
-&sdhci0 {
- status = "okay";
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs400-1_8v;
- marvell,pad-type = "fixed-1-8v";
- non-removable;
- no-sd;
- no-sdio;
-};
-
-&spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spi_quad_pins>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <54000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "firmware";
- reg = <0x0 0x180000>;
- };
-
- partition@180000 {
- label = "u-boot-env";
- reg = <0x180000 0x10000>;
- };
- };
- };
-};
-
-&pinctrl_nb {
- i2c2_recovery_pins: i2c2-recovery-pins {
- groups = "i2c2";
- function = "gpio";
- };
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default", "recovery";
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-1 = <&i2c2_recovery_pins>;
- /delete-property/mrvl,i2c-fast-mode;
- scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
- temp-sensor@48 {
- compatible = "ti,tmp75c";
- reg = <0x48>;
- };
-
- temp-sensor@49 {
- compatible = "ti,tmp75c";
- reg = <0x49>;
- };
-};
-
-ð0 {
- status = "okay";
- managed = "in-band-status";
- phys = <&comphy1 0>;
-};
-
-ð1 {
- phy-mode = "sgmii";
- status = "okay";
- managed = "in-band-status";
- phys = <&comphy0 1>;
- sfp = <&sfp_eth1>;
-};
-
-&usb3 {
- status = "okay";
- phys = <&usb2_utmi_otg_phy>;
- phy-names = "usb2-utmi-otg-phy";
-};
-
-&uart0 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Device Tree file for Globalscale MOCHAbin
- * Copyright (C) 2019 Globalscale technologies, Inc.
- * Copyright (C) 2021 Sartura Ltd.
- *
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include "armada-7040.dtsi"
-
-/ {
- model = "Globalscale MOCHAbin";
- compatible = "globalscale,mochabin", "marvell,armada7040",
- "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- ethernet0 = &cp0_eth0;
- ethernet1 = &cp0_eth1;
- ethernet2 = &cp0_eth2;
- ethernet3 = &swport1;
- ethernet4 = &swport2;
- ethernet5 = &swport3;
- ethernet6 = &swport4;
- };
-
- /* SFP+ 10G */
- sfp_eth0: sfp-eth0 {
- compatible = "sff,sfp";
- i2c-bus = <&cp0_i2c1>;
- los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
- };
-
- /* SFP 1G */
- sfp_eth2: sfp-eth2 {
- compatible = "sff,sfp";
- i2c-bus = <&cp0_i2c0>;
- los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
- };
-};
-
-/* microUSB UART console */
-&uart0 {
- status = "okay";
-
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-};
-
-/* eMMC */
-&ap_sdhci0 {
- status = "okay";
-
- bus-width = <4>;
- non-removable;
- /delete-property/ marvell,xenon-phy-slow-mode;
- no-1-8-v;
-};
-
-&cp0_pinctrl {
- cp0_uart0_pins: cp0-uart0-pins {
- marvell,pins = "mpp6", "mpp7";
- marvell,function = "uart0";
- };
-
- cp0_spi0_pins: cp0-spi0-pins {
- marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
- marvell,function = "spi0";
- };
-
- cp0_spi1_pins: cp0-spi1-pins {
- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
- marvell,function = "spi1";
- };
-
- cp0_i2c0_pins: cp0-i2c0-pins {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
-
- cp0_i2c1_pins: cp0-i2c1-pins {
- marvell,pins = "mpp2", "mpp3";
- marvell,function = "i2c1";
- };
-
- pca9554_int_pins: pca9554-int-pins {
- marvell,pins = "mpp27";
- marvell,function = "gpio";
- };
-
- cp0_rgmii1_pins: cp0-rgmii1-pins {
- marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
- "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
- marvell,function = "ge1";
- };
-
- is31_sdb_pins: is31-sdb-pins {
- marvell,pins = "mpp30";
- marvell,function = "gpio";
- };
-
- cp0_pcie_reset_pins: cp0-pcie-reset-pins {
- marvell,pins = "mpp9";
- marvell,function = "gpio";
- };
-
- cp0_switch_pins: cp0-switch-pins {
- marvell,pins = "mpp0", "mpp1";
- marvell,function = "gpio";
- };
-
- cp0_phy_pins: cp0-phy-pins {
- marvell,pins = "mpp12";
- marvell,function = "gpio";
- };
-};
-
-/* mikroBUS UART */
-&cp0_uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_uart0_pins>;
-};
-
-/* mikroBUS SPI */
-&cp0_spi0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_spi0_pins>;
-};
-
-/* SPI-NOR */
-&cp0_spi1{
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_spi1_pins>;
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <20000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x3e0000>;
- read-only;
- };
-
- partition@3e0000 {
- label = "hw-info";
- reg = <0x3e0000 0x10000>;
- read-only;
- };
-
- partition@3f0000 {
- label = "u-boot-env";
- reg = <0x3f0000 0x10000>;
- };
- };
- };
-};
-
-/* mikroBUS, 1G SFP and GPIO expander */
-&cp0_i2c0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_i2c0_pins>;
- clock-frequency = <100000>;
-
- sfp_gpio: pca9554@39 {
- compatible = "nxp,pca9554";
- pinctrl-names = "default";
- pinctrl-0 = <&pca9554_int_pins>;
- reg = <0x39>;
-
- interrupt-parent = <&cp0_gpio1>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- /*
- * IO0_0: SFP+_TX_FAULT
- * IO0_1: SFP+_TX_DISABLE
- * IO0_2: SFP+_PRSNT
- * IO0_3: SFP+_LOSS
- * IO0_4: SFP_TX_FAULT
- * IO0_5: SFP_TX_DISABLE
- * IO0_6: SFP_PRSNT
- * IO0_7: SFP_LOSS
- */
- };
-};
-
-/* IS31FL3199, mini-PCIe and 10G SFP+ */
-&cp0_i2c1 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_i2c1_pins>;
- clock-frequency = <100000>;
-
- leds@64 {
- compatible = "issi,is31fl3199";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&is31_sdb_pins>;
- shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
- reg = <0x64>;
-
- led1_red: led@1 {
- label = "red:led1";
- reg = <1>;
- led-max-microamp = <20000>;
- };
-
- led1_green: led@2 {
- label = "green:led1";
- reg = <2>;
- };
-
- led1_blue: led@3 {
- label = "blue:led1";
- reg = <3>;
- };
-
- led2_red: led@4 {
- label = "red:led2";
- reg = <4>;
- };
-
- led2_green: led@5 {
- label = "green:led2";
- reg = <5>;
- };
-
- led2_blue: led@6 {
- label = "blue:led2";
- reg = <6>;
- };
-
- led3_red: led@7 {
- label = "red:led3";
- reg = <7>;
- };
-
- led3_green: led@8 {
- label = "green:led3";
- reg = <8>;
- };
-
- led3_blue: led@9 {
- label = "blue:led3";
- reg = <9>;
- };
- };
-};
-
-&cp0_mdio {
- status = "okay";
-
- /* 88E1512 PHY */
- eth2phy: ethernet-phy@1 {
- reg = <1>;
- sfp = <&sfp_eth2>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_phy_pins>;
- reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
- };
-
- /* 88E6141 Topaz switch */
- switch: switch@3 {
- compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_switch_pins>;
- reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
-
- interrupt-parent = <&cp0_gpio1>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- swport1: port@1 {
- reg = <1>;
- label = "lan0";
- phy-handle = <&swphy1>;
- };
-
- swport2: port@2 {
- reg = <2>;
- label = "lan1";
- phy-handle = <&swphy2>;
- };
-
- swport3: port@3 {
- reg = <3>;
- label = "lan2";
- phy-handle = <&swphy3>;
- };
-
- swport4: port@4 {
- reg = <4>;
- label = "lan3";
- phy-handle = <&swphy4>;
- };
-
- port@5 {
- reg = <5>;
- ethernet = <&cp0_eth1>;
- phy-mode = "2500base-x";
- managed = "in-band-status";
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- swphy1: swphy1@17 {
- reg = <17>;
- };
-
- swphy2: swphy2@18 {
- reg = <18>;
- };
-
- swphy3: swphy3@19 {
- reg = <19>;
- };
-
- swphy4: swphy4@20 {
- reg = <20>;
- };
- };
- };
-};
-
-&cp0_ethernet {
- status = "okay";
-};
-
-/* 10G SFP+ */
-&cp0_eth0 {
- status = "okay";
-
- phy-mode = "10gbase-r";
- phys = <&cp0_comphy4 0>;
- managed = "in-band-status";
- sfp = <&sfp_eth0>;
-};
-
-/* Topaz switch uplink */
-&cp0_eth1 {
- status = "okay";
-
- phy-mode = "2500base-x";
- phys = <&cp0_comphy0 1>;
-
- fixed-link {
- speed = <2500>;
- full-duplex;
- };
-};
-
-/* 1G SFP or 1G RJ45 */
-&cp0_eth2 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_rgmii1_pins>;
-
- phy = <ð2phy>;
- phy-mode = "rgmii-id";
-};
-
-/* SMSC USB5434B hub */
-&cp0_usb3_0 {
- status = "okay";
-
- phys = <&cp0_comphy1 0>;
- phy-names = "cp0-usb3h0-comphy";
-};
-
-/* miniPCI-E USB */
-&cp0_usb3_1 {
- status = "okay";
-};
-
-&cp0_sata0 {
- status = "okay";
-
- /* 7 + 12 SATA connector (J24) */
- sata-port@0 {
- phys = <&cp0_comphy2 0>;
- phy-names = "cp0-sata0-0-phy";
- };
-
- /* M.2-2250 B-key (J39) */
- sata-port@1 {
- phys = <&cp0_comphy3 1>;
- phy-names = "cp0-sata0-1-phy";
- };
-};
-
-/* miniPCI-E (J5) */
-&cp0_pcie2 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_pcie_reset_pins>;
- phys = <&cp0_comphy5 2>;
- phy-names = "cp0-pcie2-x1-phy";
- reset-gpio = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
- ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright SolidRun Ltd.
- * Copyright (C) 2024 Tobias Schramm <tobias@t-sys.eu>
- *
- * Device tree for the CN9130-based ClearFog Pro
- */
-
-#include "cn9130.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "SolidRun ClearFog Pro";
- compatible = "solidrun,clearfog-pro", "marvell,armada-ap807-quad",
- "marvell,armada-ap807";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- gpio1 = &cp0_gpio1;
- gpio2 = &cp0_gpio2;
- i2c0 = &cp0_i2c0;
- ethernet0 = &cp0_eth0;
- ethernet1 = &cp0_eth1;
- ethernet2 = &cp0_eth2;
- spi1 = &cp0_spi1;
- };
-
- memory@00000000 {
- reg = <0x0 0x0 0x1 0x0>;
- device_type = "memory";
- };
-
- /* Virtual regulator, root of power tree */
- vin: regulator-vin {
- compatible = "regulator-fixed";
- regulator-name = "vin";
- regulator-always-on;
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- /* Regulators supplied by vin */
- v_5v0: regulator-v_5v0 {
- compatible = "regulator-fixed";
- regulator-name = "v_5v0";
- regulator-always-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vin>;
- };
-
- v_3v3: regulator-v_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "v_3v3";
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vin>;
- };
-
- /* Regulators supplied by v_5v0 */
- v_1v8: regulator-v_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "v_1v8";
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&v_5v0>;
- };
-
- v_5v0_usb3_hst_vbus: regulator-v_5v0_usb3_hst_vbus {
- compatible = "regulator-fixed";
- regulator-name = "v_5v0_usb3_hst_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&expander0 6 GPIO_ACTIVE_LOW>;
- vin-supply = <&v_5v0>;
- };
-
- /* Regulators internal to SOM */
- vqmmc: regulator-vqmmc {
- compatible = "regulator-fixed";
- regulator-name = "vqmmc";
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&v_5v0>;
- };
-
- cp0_usb3_0_phy1: cp0_usb3_phy@1 {
- compatible = "usb-nop-xceiv";
- vbus-supply = <&v_5v0_usb3_hst_vbus>;
- };
-
- cp0_sfp_eth0: sfp-eth@0 {
- compatible = "sff,sfp";
- i2c-bus = <&cp0_i2c1>;
- los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
- maximum-power-milliwatt = <2000>;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_button_pin>;
-
- reset {
- label = "Reset";
- linux,code = <KEY_RESTART>;
- gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-/* on-board eMMC */
-&ap_sdhci0 {
- bus-width = <8>;
- pinctrl-names = "default";
- vqmmc-supply = <&vqmmc>;
- status = "okay";
-};
-
-&cp0_crypto {
- status = "okay";
-};
-
-&cp0_ethernet {
- status = "okay";
-};
-
-&cp0_gpio1 {
- status = "okay";
-};
-
-&cp0_gpio2 {
- status = "okay";
-};
-
-&cp0_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_i2c0_pins>;
- clock-frequency = <100000>;
-
- /*
- * PCA9655 GPIO expander, up to 1MHz clock.
- * 0-CON3 CLKREQ#
- * 1-CON3 PERST#
- * 2-CON2 PERST#
- * 3-CON3 W_DISABLE
- * 4-CON2 CLKREQ#
- * 5-USB3 overcurrent
- * 6-USB3 power
- * 7-CON2 W_DISABLE
- * 8-JP4 P1
- * 9-JP4 P4
- * 10-JP4 P5
- * 11-m.2 DEVSLP
- * 12-SFP_LOS
- * 13-SFP_TX_FAULT
- * 14-SFP_TX_DISABLE
- * 15-SFP_MOD_DEF0
- */
- expander0: gpio-expander@20 {
- compatible = "nxp,pca9555";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&cp0_gpio1>;
- interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_expander0_pins>;
- vcc-supply = <&v_3v3>;
-
- pcie1_0_clkreq {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie1.0-clkreq";
- };
-
- pcie1_0_w_disable {
- gpio-hog;
- gpios = <3 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie1.0-w-disable";
- };
-
- pcie2_0_clkreq {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie2.0-clkreq";
- };
-
- pcie2_0_w_disable {
- gpio-hog;
- gpios = <7 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie2.0-w-disable";
- };
-
- usb3_ilimit {
- gpio-hog;
- gpios = <5 GPIO_ACTIVE_LOW>;
- input;
- line-name = "usb3-current-limit";
- };
-
- m2_devslp {
- gpio-hog;
- gpios = <11 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "m.2 devslp";
- };
- };
-
- /* ADC only for mikroBUS connector */
- mcp3021@4c {
- compatible = "microchip,mcp3021";
- reg = <0x4c>;
- };
-
- /* EEPROM on the SOM */
- eeprom@53 {
- compatible = "atmel,24c02";
- reg = <0x53>;
- pagesize = <16>;
- read-only;
-
- nvmem-layout {
- compatible = "onie,tlv-layout";
-
- onie_tlv_macaddr: mac-address {
- #nvmem-cell-cells = <1>;
- };
- };
- };
-};
-
-/* SMBUS on mini PCIe sockets */
-&cp0_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_i2c1_pins>;
- clock-frequency = <100000>;
-};
-
-&cp0_mdio {
- status = "okay";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- /* Green led blinks on activity, orange LED on link */
- marvell,reg-init = <3 16 0 0x0064>;
- };
-
- switch@4 {
- compatible = "marvell,mv88e6085";
- reg = <4>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&cp0_gpio1>;
- interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_dsa0_pins>;
- reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>;
-
- mdio-external {
- compatible = "marvell,mv88e6xxx-mdio-external";
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* 88E1512 PHY */
- port6_phy: ethernet-phy@1 {
- reg = <1>;
- };
- };
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan5";
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- };
-
- port@5 {
- reg = <5>;
- ethernet = <&cp0_eth1>;
- label = "cpu";
- phy-mode = "rgmii-id";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@6 {
- /* 88E1512 external phy */
- reg = <6>;
- label = "lan6";
- phy-handle = <&port6_phy>;
- phy-mode = "rgmii-id";
- };
- };
- };
-};
-
-/* SRDS #0 - SATA on bottom M.2 B-Key connector */
-&cp0_sata0 {
- status = "okay";
-
- sata-port@0 {
- status = "disabled";
- };
-
- sata-port@1 {
- phys = <&cp0_comphy0 1>;
- target-supply = <&v_3v3>;
- };
-};
-
-&cp0_utmi {
- status = "okay";
-};
-
-/* mini PCIe slot far from SOM, USB 2.0 only, SS lanes unused */
-&cp0_usb3_0 {
- status = "okay";
- phys = <&cp0_utmi0>;
- phy-names = "utmi";
- dr_mode = "host";
-};
-
-/* SRDS #1 - USB-A 3.0 host port */
-&cp0_usb3_1 {
- status = "okay";
- phys = <&cp0_utmi1>, <&cp0_comphy1 0>;
- phy-names = "utmi", "usb";
- usb-phy = <&cp0_usb3_0_phy1>;
- dr_mode = "host";
-};
-
-/* SRDS #2 - SFP+ 10GE */
-&cp0_eth0 {
- status = "okay";
- phy-mode = "10gbase-r";
- phys = <&cp0_comphy2 0>;
- managed = "in-band-status";
- nvmem-cells = <&onie_tlv_macaddr 0>;
- nvmem-cell-names = "mac-address";
- sfp = <&cp0_sfp_eth0>;
-};
-
-/* SRDS #3 - SGMII 1GE to L2 switch */
-&cp0_eth1 {
- status = "okay";
- phys = <&cp0_comphy3 1>;
- phy-mode = "sgmii";
- nvmem-cells = <&onie_tlv_macaddr 1>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-/* SRDS #4 - mini PCIe slot near SOM */
-&cp0_pcie1 {
- status = "okay";
- phys = <&cp0_comphy4 1>;
- num-lanes = <1>;
- reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
-};
-
-/* SRDS #5 - mini PCIe slot far from SOM */
-&cp0_pcie2 {
- status = "okay";
- phys = <&cp0_comphy5 2>;
- num-lanes = <1>;
- reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
-};
-
-/* GE PHY RGMII */
-&cp0_eth2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_ge2_rgmii_pins>;
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- nvmem-cells = <&onie_tlv_macaddr 2>;
- nvmem-cell-names = "mac-address";
-};
-
-/* micro SD card slot */
-&cp0_sdhci0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_sdhci_pins &cp0_sdhci_cd_pins>;
- bus-width = <4>;
- cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
- no-1-8-v;
- vqmmc-supply = <&v_3v3>;
- vmmc-supply = <&v_3v3>;
-};
-
-&cp0_spi1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_spi1_pins>;
-
- spi-flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- spi-max-frequency = <10000000>;
- };
-};
-
-&cp0_syscon0 {
- cp0_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
-
- cp0_i2c0_pins: cp0-i2c0-pins {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
-
- cp0_i2c1_pins: cp0-i2c1-pins {
- marvell,pins = "mpp35", "mpp36";
- marvell,function = "i2c1";
- };
-
- cp0_ge2_rgmii_pins: cp0-ge2-rgmii-pins {
- marvell,pins = "mpp44", "mpp45", "mpp46",
- "mpp47", "mpp48", "mpp49",
- "mpp50", "mpp51", "mpp52",
- "mpp53", "mpp54", "mpp55";
- marvell,function = "ge1";
- };
-
- cp0_sdhci_cd_pins: cp0-sdhci-cd-pins {
- marvell,pins = "mpp43";
- marvell,function = "sdio";
- };
-
- cp0_sdhci_pins: cp0-sdhci-pins {
- marvell,pins = "mpp56", "mpp57", "mpp58",
- "mpp59", "mpp60", "mpp61";
- marvell,function = "sdio";
- };
-
- cp0_spi1_pins: cp0-spi1-pins {
- marvell,pins = "mpp12", "mpp13", "mpp14",
- "mpp15", "mpp16";
- marvell,function = "spi1";
- };
-
- cp0_dsa0_pins: cp0-dsa0-pins {
- marvell,pins = "mpp27", "mpp29";
- marvell,function = "gpio";
- };
-
- cp0_button_pin: cp0-button-pin {
- marvell,pins = "mpp32";
- marvell,function = "gpio";
- };
-
- cp0_expander0_pins: cp0-expander0-pins {
- marvell,pins = "mpp4";
- marvell,function = "gpio";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Copyright (C) 2019 Marvell International Ltd.
- *
- * Device tree for the CN9131-DB board.
- */
-
-#include "cn9130.dtsi"
-#include "puzzle-thermal.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "iEi Puzzle-M901";
- compatible = "iei,puzzle-m901",
- "marvell,armada-ap807-quad", "marvell,armada-ap807";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- i2c0 = &cp1_i2c0;
- i2c1 = &cp0_i2c0;
- ethernet0 = &cp0_eth0;
- ethernet1 = &cp0_eth1;
- ethernet2 = &cp0_eth2;
- ethernet3 = &cp1_eth0;
- ethernet4 = &cp1_eth1;
- ethernet5 = &cp1_eth2;
- gpio1 = &cp0_gpio1;
- gpio2 = &cp0_gpio2;
- gpio3 = &cp1_gpio1;
- gpio4 = &cp1_gpio2;
- led-boot = &led_power;
- led-failsafe = &led_info;
- led-running = &led_power;
- led-upgrade = &led_info;
- };
-
- memory@00000000 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- gpio_keys {
- compatible = "gpio-keys";
-
- reset {
- label = "Reset";
- linux,code = <KEY_RESTART>;
- gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&cp0_uart0 {
- status = "okay";
-
- puzzle-mcu {
- compatible = "iei,wt61p803-puzzle";
- #address-cells = <1>;
- #size-cells = <1>;
- current-speed = <115200>;
- enable-beep;
- status = "okay";
-
- leds {
- compatible = "iei,wt61p803-puzzle-leds";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- led@0 {
- reg = <0>;
- label = "white:network";
- active-low;
- };
-
- led@1 {
- reg = <1>;
- label = "green:cloud";
- active-low;
- };
-
- led_info: led@2 {
- reg = <2>;
- label = "orange:info";
- active-low;
- };
-
- led_power: led@3 {
- reg = <3>;
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_YELLOW>;
- active-low;
- default-state = "on";
- };
- };
-
- hwmon {
- compatible = "iei,wt61p803-puzzle-hwmon";
- #address-cells = <1>;
- #size-cells = <0>;
-
- chassis_fan_group0: fan-group@0 {
- #cooling-cells = <2>;
- reg = <0x00>;
- cooling-levels = <0 159 195 211 223 241 255>;
- };
- };
- };
-};
-
-&ap_thermal_ic {
- PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
-};
-
-&cp0_thermal_ic {
- PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
-};
-
-/* on-board eMMC - U9 */
-&ap_sdhci0 {
- pinctrl-names = "default";
- bus-width = <8>;
- status = "okay";
- mmc-ddr-1_8v;
- mmc-hs400-1_8v;
-};
-
-&cp0_crypto {
- status = "okay";
-};
-
-&cp0_xmdio {
- status = "okay";
- cp0_nbaset_phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <2>;
- };
- cp0_nbaset_phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0>;
- };
- cp0_nbaset_phy2: ethernet-phy@2 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <8>;
- };
-};
-
-&cp0_ethernet {
- status = "okay";
-};
-
-/* SLM-1521-V2, CON9 */
-&cp0_eth0 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp0_comphy2 0>;
- phy = <&cp0_nbaset_phy0>;
-};
-
-&cp0_eth1 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp0_comphy4 1>;
- phy = <&cp0_nbaset_phy1>;
-};
-
-&cp0_eth2 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp0_comphy5 2>;
- phy = <&cp0_nbaset_phy2>;
-};
-
-&cp0_gpio1 {
- status = "okay";
-};
-
-&cp0_gpio2 {
- status = "okay";
-};
-
-&cp0_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_i2c0_pins>;
- status = "okay";
- clock-frequency = <100000>;
- rtc@32 {
- compatible = "epson,rx8130";
- reg = <0x32>;
- wakeup-source;
- };
-};
-
-/* SLM-1521-V2, CON6 */
-&cp0_pcie0 {
- status = "okay";
- num-lanes = <2>;
- num-viewport = <8>;
- phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
-};
-
-/* U55 */
-&cp0_spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_spi0_pins>;
- reg = <0x700680 0x50>, /* control */
- <0x2000000 0x1000000>; /* CS0 */
- status = "okay";
- spi-flash@0 {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-max-frequency = <40000000>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "U-Boot";
- reg = <0x0 0x1f0000>;
- };
- partition@1f0000 {
- label = "U-Boot ENV Factory";
- reg = <0x1f0000 0x10000>;
- };
- partition@200000 {
- label = "Reserved";
- reg = <0x200000 0x1f0000>;
- };
- partition@3f0000 {
- label = "U-Boot ENV";
- reg = <0x3f0000 0x10000>;
- };
- };
- };
-};
-
-&cp0_rtc {
- status = "disabled";
-};
-
-&cp0_syscon0 {
- cp0_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
- cp0_i2c0_pins: cp0-i2c-pins-0 {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
- cp0_i2c1_pins: cp0-i2c-pins-1 {
- marvell,pins = "mpp35", "mpp36";
- marvell,function = "i2c1";
- };
- cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
- marvell,pins = "mpp0", "mpp1", "mpp2",
- "mpp3", "mpp4", "mpp5",
- "mpp6", "mpp7", "mpp8",
- "mpp9", "mpp10", "mpp11";
- marvell,function = "ge0";
- };
- cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
- marvell,pins = "mpp44", "mpp45", "mpp46",
- "mpp47", "mpp48", "mpp49",
- "mpp50", "mpp51", "mpp52",
- "mpp53", "mpp54", "mpp55";
- marvell,function = "ge1";
- };
- cp0_spi0_pins: cp0-spi-pins-0 {
- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
- marvell,function = "spi1";
- };
- };
-};
-
-/*
- * Instantiate the first connected CP115
- */
-
-#define CP11X_NAME cp1
-#define CP11X_BASE f6000000
-#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
-#define CP11X_PCIE0_BASE f6600000
-#define CP11X_PCIE1_BASE f6620000
-#define CP11X_PCIE2_BASE f6640000
-
-#include "armada-cp115.dtsi"
-
-#undef CP11X_NAME
-#undef CP11X_BASE
-#undef CP11X_PCIEx_MEM_BASE
-#undef CP11X_PCIEx_MEM_SIZE
-#undef CP11X_PCIE0_BASE
-#undef CP11X_PCIE1_BASE
-#undef CP11X_PCIE2_BASE
-
-&cp1_crypto {
- status = "okay";
-};
-
-&cp1_xmdio {
- status = "okay";
- cp1_nbaset_phy0: ethernet-phy@3 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <2>;
- };
- cp1_nbaset_phy1: ethernet-phy@4 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0>;
- };
- cp1_nbaset_phy2: ethernet-phy@5 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <8>;
- };
-};
-
-&cp1_ethernet {
- status = "okay";
-};
-
-/* CON50 */
-&cp1_eth0 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp1_comphy2 0>;
- phy = <&cp1_nbaset_phy0>;
-};
-
-&cp1_eth1 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp1_comphy4 1>;
- phy = <&cp1_nbaset_phy1>;
-};
-
-&cp1_eth2 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp1_comphy5 2>;
- phy = <&cp1_nbaset_phy2>;
-};
-
-&cp1_sata0 {
- status = "okay";
- sata-port@1 {
- status = "okay";
- phys = <&cp1_comphy0 1>;
- };
-};
-
-&cp1_gpio1 {
- status = "okay";
-};
-
-&cp1_gpio2 {
- status = "okay";
-};
-
-&cp1_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp1_i2c0_pins>;
- clock-frequency = <100000>;
-};
-
-&cp1_rtc {
- status = "disabled";
-};
-
-&cp1_syscon0 {
- cp1_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
- cp1_i2c0_pins: cp1-i2c-pins-0 {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
- cp1_spi0_pins: cp1-spi-pins-0 {
- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
- marvell,function = "spi1";
- };
- cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
- marvell,pins = "mpp3";
- marvell,function = "gpio";
- };
- cp1_sfp_pins: sfp-pins {
- marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
- marvell,function = "gpio";
- };
- };
-};
-
-&cp1_thermal_ic {
- PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
-};
-
-&cp1_usb3_1 {
- status = "okay";
- phys = <&cp1_comphy3 1>;
- phy-names = "usb";
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Copyright (C) 2019 Marvell International Ltd.
- *
- * Device tree for the CN9132-DB board.
- */
-
-#include "cn9130.dtsi"
-#include "puzzle-thermal.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "iEi Puzzle-M902";
- compatible = "iei,puzzle-m902",
- "marvell,armada-ap807-quad", "marvell,armada-ap807";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- i2c0 = &cp1_i2c0;
- i2c1 = &cp0_i2c0;
- gpio1 = &cp0_gpio1;
- gpio2 = &cp0_gpio2;
- gpio3 = &cp1_gpio1;
- gpio4 = &cp1_gpio2;
- gpio5 = &cp2_gpio1;
- gpio6 = &cp2_gpio2;
- ethernet0 = &cp0_eth0;
- ethernet1 = &cp0_eth1;
- ethernet2 = &cp0_eth2;
- ethernet3 = &cp1_eth0;
- ethernet4 = &cp1_eth1;
- ethernet5 = &cp1_eth2;
- ethernet6 = &cp2_eth0;
- ethernet7 = &cp2_eth1;
- ethernet8 = &cp2_eth2;
- spi1 = &cp0_spi0;
- spi2 = &cp0_spi1;
- led-boot = &led_power;
- led-failsafe = &led_info;
- led-running = &led_power;
- led-upgrade = &led_info;
- };
-
- memory@00000000 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- gpio_keys {
- compatible = "gpio-keys";
-
- reset {
- label = "Reset";
- linux,code = <KEY_RESTART>;
- gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
- };
- };
-
- cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
- compatible = "regulator-fixed";
- regulator-name = "cp2-xhci0-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
- };
-
- cp2_usb3_0_phy0: cp2_usb3_phy0 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp2_reg_usb3_vbus0>;
- };
-
- cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
- compatible = "regulator-fixed";
- regulator-name = "cp2-xhci1-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
- };
-
- cp2_usb3_0_phy1: cp2_usb3_phy1 {
- compatible = "usb-nop-xceiv";
- vcc-supply = <&cp2_reg_usb3_vbus1>;
- };
-
- cp2_sfp_eth0: sfp-eth0 {
- compatible = "sff,sfp";
- i2c-bus = <&cp2_sfpp0_i2c>;
- los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
- status = "disabled";
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&cp0_uart0 {
- status = "okay";
-
- puzzle-mcu {
- compatible = "iei,wt61p803-puzzle";
- #address-cells = <1>;
- #size-cells = <1>;
- current-speed = <115200>;
- enable-beep;
- status = "okay";
-
- leds {
- compatible = "iei,wt61p803-puzzle-leds";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- led@0 {
- reg = <0>;
- label = "white:network";
- active-low;
- };
-
- led@1 {
- reg = <1>;
- label = "green:cloud";
- active-low;
- };
-
- led_info: led@2 {
- reg = <2>;
- label = "orange:info";
- active-low;
- };
-
- led_power: led@3 {
- reg = <3>;
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_YELLOW>;
- active-low;
- default-state = "on";
- };
- };
-
- hwmon {
- compatible = "iei,wt61p803-puzzle-hwmon";
- #address-cells = <1>;
- #size-cells = <0>;
-
- chassis_fan_group0: fan-group@0 {
- #cooling-cells = <2>;
- reg = <0x00>;
- cooling-levels = <0 159 195 211 223 241 255>;
- };
- };
- };
-};
-
-&ap_thermal_ic {
- PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
-};
-
-&cp0_thermal_ic {
- PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
-};
-
-
-/* on-board eMMC - U9 */
-&ap_sdhci0 {
- pinctrl-names = "default";
- bus-width = <8>;
- status = "okay";
- mmc-ddr-1_8v;
- mmc-hs400-1_8v;
-};
-
-&cp0_crypto {
- status = "okay";
-};
-
-&cp0_xmdio {
- status = "okay";
- cp0_nbaset_phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <2>;
- };
- cp0_nbaset_phy1: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0>;
- };
- cp0_nbaset_phy2: ethernet-phy@2 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <8>;
- };
-};
-
-&cp0_ethernet {
- status = "okay";
-};
-
-/* SLM-1521-V2, CON9 */
-&cp0_eth0 {
- status = "okay";
- phy-mode = "10gbase-kr";
- phys = <&cp0_comphy2 0>;
- phy = <&cp0_nbaset_phy0>;
-};
-
-&cp0_eth1 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp0_comphy4 1>;
- phy = <&cp0_nbaset_phy1>;
-};
-
-&cp0_eth2 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp0_comphy1 2>;
- phy = <&cp0_nbaset_phy2>;
-};
-
-&cp0_gpio1 {
- status = "okay";
-};
-
-&cp0_gpio2 {
- status = "okay";
-};
-
-&cp0_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_i2c0_pins>;
- status = "okay";
- clock-frequency = <100000>;
- rtc@32 {
- compatible = "epson,rx8130";
- reg = <0x32>;
- wakeup-source;
- };
-};
-
-&cp0_i2c1 {
- clock-frequency = <100000>;
-};
-
-/* SLM-1521-V2, CON6 */
-&cp0_sata0 {
- status = "okay";
- sata-port@1 {
- status = "okay";
- phys = <&cp0_comphy0 1>;
- };
-};
-
-&cp0_pcie2 {
- status = "okay";
- num-lanes = <1>;
- num-viewport = <8>;
- phys = <&cp0_comphy5 2>;
-};
-
-/* U55 */
-&cp0_spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&cp0_spi0_pins>;
- reg = <0x700680 0x50>, /* control */
- <0x2000000 0x1000000>; /* CS0 */
- status = "okay";
- spi-flash@0 {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-max-frequency = <40000000>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "U-Boot";
- reg = <0x0 0x1f0000>;
- };
- partition@1f0000 {
- label = "U-Boot ENV Factory";
- reg = <0x1f0000 0x10000>;
- };
- partition@200000 {
- label = "Reserved";
- reg = <0x200000 0x1f0000>;
- };
- partition@3f0000 {
- label = "U-Boot ENV";
- reg = <0x3f0000 0x10000>;
- };
- };
- };
-};
-
-&cp0_rtc {
- status = "disabled";
-};
-
-&cp0_syscon0 {
- cp0_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
- cp0_i2c0_pins: cp0-i2c-pins-0 {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
- cp0_i2c1_pins: cp0-i2c-pins-1 {
- marvell,pins = "mpp35", "mpp36";
- marvell,function = "i2c1";
- };
- cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
- marvell,pins = "mpp0", "mpp1", "mpp2",
- "mpp3", "mpp4", "mpp5",
- "mpp6", "mpp7", "mpp8",
- "mpp9", "mpp10", "mpp11";
- marvell,function = "ge0";
- };
- cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
- marvell,pins = "mpp44", "mpp45", "mpp46",
- "mpp47", "mpp48", "mpp49",
- "mpp50", "mpp51", "mpp52",
- "mpp53", "mpp54", "mpp55";
- marvell,function = "ge1";
- };
- cp0_spi0_pins: cp0-spi-pins-0 {
- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
- marvell,function = "spi1";
- };
- };
-};
-
-&cp0_usb3_1 {
- status = "okay";
- phys = <&cp0_comphy3 1>;
- phy-names = "usb";
-};
-
-/*
- * Instantiate the first connected CP115
- */
-
-#define CP11X_NAME cp1
-#define CP11X_BASE f4000000
-#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
-#define CP11X_PCIE0_BASE f4600000
-#define CP11X_PCIE1_BASE f4620000
-#define CP11X_PCIE2_BASE f4640000
-
-#include "armada-cp115.dtsi"
-
-#undef CP11X_NAME
-#undef CP11X_BASE
-#undef CP11X_PCIEx_MEM_BASE
-#undef CP11X_PCIEx_MEM_SIZE
-#undef CP11X_PCIE0_BASE
-#undef CP11X_PCIE1_BASE
-#undef CP11X_PCIE2_BASE
-
-&cp1_crypto {
- status = "okay";
-};
-
-&cp1_xmdio {
- status = "okay";
- cp1_nbaset_phy0: ethernet-phy@3 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <2>;
- };
- cp1_nbaset_phy1: ethernet-phy@4 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0>;
- };
- cp1_nbaset_phy2: ethernet-phy@5 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <8>;
- };
-};
-
-&cp1_ethernet {
- status = "okay";
-};
-
-/* CON50 */
-&cp1_eth0 {
- status = "okay";
- phy-mode = "10gbase-kr";
- phys = <&cp1_comphy2 0>;
- phy = <&cp1_nbaset_phy0>;
-};
-
-&cp1_eth1 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp1_comphy4 1>;
- phy = <&cp1_nbaset_phy1>;
-};
-
-&cp1_eth2 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp1_comphy1 2>;
- phy = <&cp1_nbaset_phy2>;
-};
-
-&cp1_gpio1 {
- status = "okay";
-};
-
-&cp1_gpio2 {
- status = "okay";
-};
-
-&cp1_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&cp1_i2c0_pins>;
- clock-frequency = <100000>;
-};
-
-&cp1_rtc {
- status = "disabled";
-};
-
-&cp1_syscon0 {
- cp1_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
- cp1_i2c0_pins: cp1-i2c-pins-0 {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
- cp1_spi0_pins: cp1-spi-pins-0 {
- marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
- marvell,function = "spi1";
- };
- cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
- marvell,pins = "mpp3";
- marvell,function = "gpio";
- };
- };
-};
-
-&cp1_thermal_ic {
- PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
-};
-
-/*
- * Instantiate the second connected CP115
- */
-
-#define CP11X_NAME cp2
-#define CP11X_BASE f6000000
-#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
-#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
-#define CP11X_PCIE0_BASE f6600000
-#define CP11X_PCIE1_BASE f6620000
-#define CP11X_PCIE2_BASE f6640000
-
-#include "armada-cp115.dtsi"
-
-#undef CP11X_NAME
-#undef CP11X_BASE
-#undef CP11X_PCIEx_MEM_BASE
-#undef CP11X_PCIEx_MEM_SIZE
-#undef CP11X_PCIE0_BASE
-#undef CP11X_PCIE1_BASE
-#undef CP11X_PCIE2_BASE
-
-&cp2_crypto {
- status = "okay";
-};
-
-&cp2_ethernet {
- status = "okay";
-};
-
-&cp2_xmdio {
- status = "okay";
- cp2_nbaset_phy0: ethernet-phy@6 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <2>;
- };
- cp2_nbaset_phy1: ethernet-phy@7 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0>;
- };
- cp2_nbaset_phy2: ethernet-phy@8 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <8>;
- };
-};
-
-/* SLM-1521-V2, CON9 */
-&cp2_eth0 {
- status = "okay";
- phy-mode = "10gbase-kr";
- phys = <&cp2_comphy2 0>;
- phy = <&cp2_nbaset_phy0>;
-};
-
-&cp2_eth1 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp2_comphy4 1>;
- phy = <&cp2_nbaset_phy1>;
-};
-
-&cp2_eth2 {
- status = "okay";
- phy-mode = "2500base-x";
- phys = <&cp2_comphy1 2>;
- phy = <&cp2_nbaset_phy2>;
-};
-
-&cp2_gpio1 {
- status = "okay";
-};
-
-&cp2_gpio2 {
- status = "okay";
-};
-
-&cp2_i2c0 {
- clock-frequency = <100000>;
- /* SLM-1521-V2 - U3 */
- i2c-mux@72 {
- compatible = "nxp,pca9544";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x72>;
- cp2_sfpp0_i2c: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- /* U12 */
- cp2_module_expander1: pca9555@21 {
- compatible = "nxp,pca9555";
- pinctrl-names = "default";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x21>;
- };
- };
- };
-};
-
-&cp2_rtc {
- status = "disabled";
-};
-
-&cp2_syscon0 {
- cp2_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
- cp2_i2c0_pins: cp2-i2c-pins-0 {
- marvell,pins = "mpp37", "mpp38";
- marvell,function = "i2c0";
- };
- };
-};
-
-&cp2_thermal_ic {
- PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0);
-};
+++ /dev/null
-#define PUZZLE_FAN_THERMAL(_cname, _fan) \
- polling-delay-passive = <500>; \
- polling-delay = <1000>; \
- \
- trips { \
- cpu-hot { \
- temperature = <75000>; \
- hysteresis = <5000>; \
- type = "hot"; \
- }; \
- _cname##_active_full: cpu-active-full { \
- temperature = <70000>; \
- hysteresis = <5000>; \
- type = "active"; \
- }; \
- _cname##_active_high: cpu-active-high { \
- temperature = <65000>; \
- hysteresis = <5000>; \
- type = "active"; \
- }; \
- _cname##_active_med: cpu-active-med { \
- temperature = <62500>; \
- hysteresis = <3000>; \
- type = "active"; \
- }; \
- _cname##_active_low: cpu-active-low { \
- temperature = <60000>; \
- hysteresis = <3000>; \
- type = "active"; \
- }; \
- _cname##_active_min: cpu-active-min { \
- temperature = <55000>; \
- hysteresis = <5000>; \
- type = "active"; \
- }; \
- _cname##_active_idle: cpu-active-idle { \
- temperature = <50000>; \
- hysteresis = <5000>; \
- type = "active"; \
- }; \
- }; \
- cooling-maps { \
- cpu-active-full { \
- trip = <&_cname##_active_full>; \
- cooling-device = <_fan THERMAL_NO_LIMIT \
- THERMAL_NO_LIMIT>; \
- }; \
- cpu-active-high { \
- trip = <&_cname##_active_high>; \
- cooling-device = <_fan 4 5>; \
- }; \
- cpu-active-med { \
- trip = <&_cname##_active_med>; \
- cooling-device = <_fan 3 4>; \
- }; \
- cpu-active-low { \
- trip = <&_cname##_active_low>; \
- cooling-device = <_fan 2 3>; \
- }; \
- cpu-active-min { \
- trip = <&_cname##_active_min>; \
- cooling-device = <_fan 1 2>; \
- }; \
- cpu-active-idle { \
- trip = <&_cname##_active_idle>; \
- cooling-device = <_fan 0 0>; \
- }; \
- }
led-0 {
gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_5GHZ;
linux,default-trigger = "phy0tpt";
};
led-1 {
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_WLAN_5GHZ;
};
led-2 {
led-4 {
gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_MOBILE;
};
led-5 {
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_MOBILE;
};
led-6 {
gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_2GHZ;
linux,default-trigger = "phy1tpt";
};
led-7 {
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_WLAN_2GHZ;
};
led_power_green: led-8 {
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
};
led_power_red: led-9 {
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
};
led-10 {
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_USB;
+ function-enumerator = <1>;
linux,default-trigger = "usbport";
trigger-sources = <&hub_port2>;
};
led-11 {
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_USB;
+ function-enumerator = <0>;
linux,default-trigger = "usbport";
trigger-sources = <&hub_port1>;
};
led-14 {
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_WAN;
linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
};
led-15 {
gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_WAN;
linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
};
};
led-14 {
gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_WAN;
+ function-enumerator = <1>;
linux,default-trigger = "f1072004.mdio-mii:00:1Gbps";
};
led-15 {
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_WAN;
+ function-enumerator = <2>;
linux,default-trigger = "f1072004.mdio-mii:01:1Gbps";
};
led-16 {
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <5>;
linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
};
led-17 {
gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <5>;
linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
};
};
led-1 {
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_RED>;
+ function = "ha";
};
led_status_green: led-2 {
led-3 {
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
+ function = "ha";
};
led-4 {
led-6 {
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <4>;
linux,default-trigger = "mv88e6xxx-1:01:1Gbps";
};
led-7 {
gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <4>;
linux,default-trigger = "mv88e6xxx-1:01:100Mbps";
};
led-8 {
gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <3>;
linux,default-trigger = "mv88e6xxx-1:02:100Mbps";
};
led-9 {
gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <3>;
linux,default-trigger = "mv88e6xxx-1:02:1Gbps";
};
led-10 {
gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <1>;
linux,default-trigger = "mv88e6xxx-1:04:1Gbps";
};
led-11 {
gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <1>;
linux,default-trigger = "mv88e6xxx-1:04:100Mbps";
};
led-12 {
gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <2>;
linux,default-trigger = "mv88e6xxx-1:03:1Gbps";
};
led-13 {
gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <2>;
linux,default-trigger = "mv88e6xxx-1:03:100Mbps";
};
};
# Copyright (C) 2012-2016 OpenWrt.org
# Copyright (C) 2016 LEDE-project.org
-ifneq ($(KERNEL),6.1)
DTS_DIR := $(DTS_DIR)/marvell
-endif
define Build/fortigate-header
( \
+++ /dev/null
-From 8eec6e740b564ec5e1da59ab7070b89aa23c9973 Mon Sep 17 00:00:00 2001
-From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
-Date: Fri, 16 Jun 2023 12:41:30 +0100
-Subject: [PATCH] cpufreq: armada-8k: add ap807 support
-
-Add support for the Armada AP807 die to armada-8k. This uses a
-different compatible for the CPU clock which needs to be added to
-the cpufreq driver.
-
-This commit takes a different approach to the WindRiver patch
-"cpufreq: armada: enable ap807-cpu-clk" in that rather than calling
-of_find_compatible_node() for each compatible, we use a table of
-IDs instead.
-
-Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/armada-8k-cpufreq.c | 16 +++++++++-------
- 1 file changed, 9 insertions(+), 7 deletions(-)
-
---- a/drivers/cpufreq/armada-8k-cpufreq.c
-+++ b/drivers/cpufreq/armada-8k-cpufreq.c
-@@ -21,6 +21,13 @@
- #include <linux/pm_opp.h>
- #include <linux/slab.h>
-
-+static const struct of_device_id __maybe_unused armada_8k_cpufreq_of_match[] = {
-+ { .compatible = "marvell,ap806-cpu-clock" },
-+ { .compatible = "marvell,ap807-cpu-clock" },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, armada_8k_cpufreq_of_match);
-+
- /*
- * Setup the opps list with the divider for the max frequency, that
- * will be filled at runtime.
-@@ -127,7 +134,8 @@ static int __init armada_8k_cpufreq_init
- struct device_node *node;
- struct cpumask cpus;
-
-- node = of_find_compatible_node(NULL, NULL, "marvell,ap806-cpu-clock");
-+ node = of_find_matching_node_and_match(NULL, armada_8k_cpufreq_of_match,
-+ NULL);
- if (!node || !of_device_is_available(node)) {
- of_node_put(node);
- return -ENODEV;
-@@ -204,12 +212,6 @@ static void __exit armada_8k_cpufreq_exi
- }
- module_exit(armada_8k_cpufreq_exit);
-
--static const struct of_device_id __maybe_unused armada_8k_cpufreq_of_match[] = {
-- { .compatible = "marvell,ap806-cpu-clock" },
-- { },
--};
--MODULE_DEVICE_TABLE(of, armada_8k_cpufreq_of_match);
--
- MODULE_AUTHOR("Gregory Clement <gregory.clement@bootlin.com>");
- MODULE_DESCRIPTION("Armada 8K cpufreq driver");
- MODULE_LICENSE("GPL");
+++ /dev/null
-Subject: [PATCH v2] PCI: aardvark: Implement workaround for PCIe Completion Timeout
-Date: Tue, 2 Aug 2022 14:38:16 +0200
-Message-Id: <20220802123816.21817-1-pali@kernel.org>
-X-Mailer: git-send-email 2.20.1
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-Precedence: bulk
-List-ID: <linux-pci.vger.kernel.org>
-X-Mailing-List: linux-pci@vger.kernel.org
-
-Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions
-document describes in erratum 3.12 PCIe Completion Timeout (Ref #: 251),
-that PCIe IP does not support a strong-ordered model for inbound posted vs.
-outbound completion.
-
-As a workaround for this erratum, DIS_ORD_CHK flag in Debug Mux Control
-register must be set. It disables the ordering check in the core between
-Completions and Posted requests received from the link.
-
-Marvell also suggests to do full memory barrier at the beginning of
-aardvark summary interrupt handler before calling interrupt handlers of
-endpoint drivers in order to minimize the risk for the race condition
-documented in the Erratum between the DMA done status reading and the
-completion of writing to the host memory.
-
-More details about this issue and suggested workarounds are in discussion:
-https://lore.kernel.org/linux-pci/BN9PR18MB425154FE5019DCAF2028A1D5DB8D9@BN9PR18MB4251.namprd18.prod.outlook.com/t/#u
-
-It was reported that enabling this workaround fixes instability issues and
-"Unhandled fault" errors when using 60 GHz WiFi 802.11ad card with Qualcomm
-QCA6335 chip under significant load which were caused by interrupt status
-stuck in the outbound CMPLT queue traced back to this erratum.
-
-This workaround fixes also kernel panic triggered after some minutes of
-usage 5 GHz WiFi 802.11ax card with Mediatek MT7915 chip:
-
- Internal error: synchronous external abort: 96000210 [#1] SMP
- Kernel panic - not syncing: Fatal exception in interrupt
-
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
-Signed-off-by: Pali Rohár <pali@kernel.org>
-Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
-Cc: stable@vger.kernel.org
----
- drivers/pci/controller/pci-aardvark.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/drivers/pci/controller/pci-aardvark.c
-+++ b/drivers/pci/controller/pci-aardvark.c
-@@ -212,6 +212,8 @@ enum {
- };
-
- #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
-+#define DEBUG_MUX_CTRL_REG (LMI_BASE_ADDR + 0x208)
-+#define DIS_ORD_CHK BIT(30)
-
- /* PCIe core controller registers */
- #define CTRL_CORE_BASE_ADDR 0x18000
-@@ -560,6 +562,11 @@ static void advk_pcie_setup_hw(struct ad
- PCIE_CORE_CTRL2_TD_ENABLE;
- advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
-
-+ /* Disable ordering checks, workaround for erratum 3.12 "PCIe completion timeout" */
-+ reg = advk_readl(pcie, DEBUG_MUX_CTRL_REG);
-+ reg |= DIS_ORD_CHK;
-+ advk_writel(pcie, reg, DEBUG_MUX_CTRL_REG);
-+
- /* Set lane X1 */
- reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
- reg &= ~LANE_CNT_MSK;
-@@ -1661,6 +1668,9 @@ static irqreturn_t advk_pcie_irq_handler
- struct advk_pcie *pcie = arg;
- u32 status;
-
-+ /* Full memory barrier (ARM dsb sy), workaround for erratum 3.12 "PCIe completion timeout" */
-+ mb();
-+
- status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
- if (!(status & PCIE_IRQ_CORE_INT))
- return IRQ_NONE;
+++ /dev/null
---- a/drivers/power/reset/linkstation-poweroff.c
-+++ b/drivers/power/reset/linkstation-poweroff.c
-@@ -142,6 +142,12 @@ static void linkstation_poweroff(void)
- }
-
- static const struct of_device_id ls_poweroff_of_match[] = {
-+ { .compatible = "buffalo,ls220d",
-+ .data = &linkstation_power_off_cfg,
-+ },
-+ { .compatible = "buffalo,ls220de",
-+ .data = &linkstation_power_off_cfg,
-+ },
- { .compatible = "buffalo,ls421d",
- .data = &linkstation_power_off_cfg,
- },
+++ /dev/null
-From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
-From: Adrian Panella <ianchi74@outlook.com>
-Date: Thu, 9 Mar 2017 09:37:17 +0100
-Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-Only command line ATAG will be processed, the rest of the ATAGs
-sent by bootloader will be ignored.
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
-
-This patch has been modified to be mvebu specific. The original patch
-did not pass the bootloader cmdline on if no append-rootblock stanza
-was found, resulting in blank cmdline and failure to boot.
-
-Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
----
- arch/arm/Kconfig | 11 ++++
- arch/arm/boot/compressed/atags_to_fdt.c | 85 ++++++++++++++++++++++++-
- init/main.c | 16 +++++
- 3 files changed, 111 insertions(+), 1 deletion(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1587,6 +1587,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- The command-line arguments provided by the boot loader will be
- appended to the the device tree bootargs property.
-
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+ bool "Append rootblock parsing bootloader's kernel arguments"
-+ help
-+ The command-line arguments provided by the boot loader will be
-+ appended to a new device tree property: bootloader-args.
-+ If there is a property "append-rootblock" in DT under /chosen
-+ and a root= option in bootloaders command line it will be parsed
-+ and added to DT bootargs with the form: <append-rootblock>XX.
-+ Only command line ATAG will be processed, the rest of the ATAGs
-+ sent by bootloader will be ignored.
-+
- endchoice
-
- config CMDLINE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -5,6 +5,8 @@
-
- #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
- #define do_extend_cmdline 1
-+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
- #endif
-@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const
- return offset;
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop(void *fdt, const char *node_path, const char *property,
- void *val_array, int size)
- {
-@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char
- return offset;
- return fdt_setprop(fdt, offset, property, val_array, size);
- }
-+#endif
-
- static int setprop_string(void *fdt, const char *node_path,
- const char *property, const char *string)
-@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con
- return fdt_setprop_string(fdt, offset, property, string);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop_cell(void *fdt, const char *node_path,
- const char *property, uint32_t val)
- {
-@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const
- return offset;
- return fdt_setprop_cell(fdt, offset, property, val);
- }
-+#endif
-
- static const void *getprop(const void *fdt, const char *node_path,
- const char *property, int *len)
-@@ -58,6 +64,7 @@ static const void *getprop(const void *f
- return fdt_getprop(fdt, offset, property, len);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static uint32_t get_cell_size(const void *fdt)
- {
- int len;
-@@ -69,6 +76,74 @@ static uint32_t get_cell_size(const void
- return cell_size;
- }
-
-+#endif
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+ const char *ptr, *end;
-+ const char *root="root=";
-+ int i, l;
-+ const char *rootblock;
-+
-+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
-+ ptr = str - 1;
-+
-+ do {
-+ //first find an 'r' at the begining or after a space
-+ do {
-+ ptr++;
-+ ptr = strchr(ptr, 'r');
-+ if (!ptr)
-+ goto no_append;
-+
-+ } while (ptr != str && *(ptr-1) != ' ');
-+
-+ //then check for the rest
-+ for(i = 1; i <= 4; i++)
-+ if(*(ptr+i) != *(root+i)) break;
-+
-+ } while (i != 5);
-+
-+ end = strchr(ptr, ' ');
-+ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
-+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+ ptr = end + 1;
-+
-+ /* if append-rootblock property is set use it to append to command line */
-+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+ if (rootblock == NULL)
-+ goto no_append;
-+
-+ if (*dest != ' ') {
-+ *dest = ' ';
-+ dest++;
-+ len++;
-+ }
-+
-+ if (len + l + i <= COMMAND_LINE_SIZE) {
-+ memcpy(dest, rootblock, l);
-+ dest += l - 1;
-+ memcpy(dest, ptr, i);
-+ dest += i;
-+ }
-+
-+ return dest;
-+
-+no_append:
-+ len = strlen(str);
-+ if (len + 1 < COMMAND_LINE_SIZE) {
-+ memcpy(dest, str, len);
-+ dest += len;
-+ }
-+
-+ return dest;
-+}
-+#endif
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
- char cmdline[COMMAND_LINE_SIZE];
-@@ -88,18 +163,28 @@ static void merge_fdt_bootargs(void *fdt
-
- /* and append the ATAG_CMDLINE */
- if (fdt_cmdline) {
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+ //save original bootloader args
-+ //and append ubi.mtd with root partition number to current cmdline
-+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+
-+#else
- len = strlen(fdt_cmdline);
- if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
- *ptr++ = ' ';
- memcpy(ptr, fdt_cmdline, len);
- ptr += len;
- }
-+#endif
- }
- *ptr = '\0';
-
- setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static void hex_str(char *out, uint32_t value)
- {
- uint32_t digit;
-@@ -117,6 +202,7 @@ static void hex_str(char *out, uint32_t
- }
- *out = '\0';
- }
-+#endif
-
- /*
- * Convert and fold provided ATAGs into the provided FDT.
-@@ -131,9 +217,11 @@ int atags_to_fdt(void *atag_list, void *
- struct tag *atag = atag_list;
- /* In the case of 64 bits memory size, need to reserve 2 cells for
- * address and size for each bank */
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- __be32 mem_reg_property[2 * 2 * NR_BANKS];
-- int memcount = 0;
-- int ret, memsize;
-+ int memsize, memcount = 0;
-+#endif
-+ int ret;
-
- /* make sure we've got an aligned pointer */
- if ((u32)atag_list & 0x3)
-@@ -168,7 +256,9 @@ int atags_to_fdt(void *atag_list, void *
- else
- setprop_string(fdt, "/chosen", "bootargs",
- atag->u.cmdline.cmdline);
-- } else if (atag->hdr.tag == ATAG_MEM) {
-+ }
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+ else if (atag->hdr.tag == ATAG_MEM) {
- if (memcount >= sizeof(mem_reg_property)/4)
- continue;
- if (!atag->u.mem.size)
-@@ -212,6 +302,10 @@ int atags_to_fdt(void *atag_list, void *
- setprop(fdt, "/memory", "reg", mem_reg_property,
- 4 * memcount * memsize);
- }
-+#else
-+
-+ }
-+#endif
-
- return fdt_pack(fdt);
- }
---- a/init/main.c
-+++ b/init/main.c
-@@ -112,6 +112,10 @@
-
- #include <kunit/test.h>
-
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#include <linux/of.h>
-+#endif
-+
- static int kernel_init(void *);
-
- extern void init_IRQ(void);
-@@ -993,6 +997,18 @@ asmlinkage __visible void __init __no_sa
- page_alloc_init();
-
- pr_notice("Kernel command line: %s\n", saved_command_line);
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+ //Show bootloader's original command line for reference
-+ if(of_chosen) {
-+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+ if(prop)
-+ pr_notice("Bootloader command line (ignored): %s\n", prop);
-+ else
-+ pr_notice("Bootloader command line not present\n");
-+ }
-+#endif
-+
- /* parameters may set static keys */
- jump_label_init();
- parse_early_param();
+++ /dev/null
---- a/arch/arm/mach-mvebu/Kconfig
-+++ b/arch/arm/mach-mvebu/Kconfig
-@@ -66,6 +66,7 @@ config MACH_ARMADA_38X
- select HAVE_ARM_TWD if SMP
- select MACH_MVEBU_V7
- select PINCTRL_ARMADA_38X
-+ select ARCH_WANT_LIBATA_LEDS
- help
- Say 'Y' here if you want your kernel to support boards based
- on the Marvell Armada 380/385 SoC with device tree.
+++ /dev/null
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -214,11 +214,19 @@
- &pcie1 {
- /* Marvell 88W8864, 5GHz-only */
- status = "okay";
-+
-+ mwlwifi {
-+ marvell,2ghz = <0>;
-+ };
- };
-
- &pcie2 {
- /* Marvell 88W8864, 2GHz-only */
- status = "okay";
-+
-+ mwlwifi {
-+ marvell,5ghz = <0>;
-+ };
- };
-
- &pinctrl {
---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-@@ -142,3 +142,205 @@
- };
- };
- };
-+
-+&pcie1 {
-+ mwlwifi {
-+ marvell,chainmask = <2 2>;
-+ marvell,powertable {
-+ AU =
-+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+ <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+ <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+ <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+ <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+ <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+ <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+ <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+ <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+ <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+ <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
-+ <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
-+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;
-+ CA =
-+ <36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+ <40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+ <44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+ <48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
-+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
-+ CN =
-+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
-+ <165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;
-+ ETSI =
-+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
-+ <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>;
-+ FCC =
-+ <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+ <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+ <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
-+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
-+ };
-+ };
-+};
-+
-+&pcie2 {
-+ mwlwifi {
-+ marvell,chainmask = <2 2>;
-+ marvell,powertable {
-+ AU =
-+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+ CA =
-+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,
-+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
-+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;
-+ CN =
-+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+ ETSI =
-+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
-+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
-+ FCC =
-+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;
-+ };
-+ };
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-@@ -142,3 +142,205 @@
- };
- };
- };
-+
-+&pcie1 {
-+ mwlwifi {
-+ marvell,chainmask = <4 4>;
-+ marvell,powertable {
-+ AU =
-+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
-+ CA =
-+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+ CN =
-+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
-+ ETSI =
-+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
-+ FCC =
-+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
-+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+ };
-+ };
-+};
-+
-+&pcie2 {
-+ mwlwifi {
-+ marvell,chainmask = <4 4>;
-+ marvell,powertable {
-+ AU =
-+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+ CA =
-+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+ CN =
-+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+ ETSI =
-+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+ FCC =
-+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+ };
-+ };
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-@@ -142,3 +142,205 @@
- };
- };
- };
-+
-+&pcie1 {
-+ mwlwifi {
-+ marvell,chainmask = <4 4>;
-+ marvell,powertable {
-+ AU =
-+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
-+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
-+ CA =
-+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+ CN =
-+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
-+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
-+ ETSI =
-+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
-+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
-+ FCC =
-+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
-+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
-+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
-+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
-+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
-+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
-+ };
-+ };
-+};
-+
-+&pcie2 {
-+ mwlwifi {
-+ marvell,chainmask = <4 4>;
-+ marvell,powertable {
-+ AU =
-+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+ CA =
-+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+ CN =
-+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+ ETSI =
-+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
-+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
-+ FCC =
-+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
-+ };
-+ };
-+};
---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
-@@ -157,6 +157,18 @@
- };
- };
-
-+&pcie1 {
-+ mwlwifi {
-+ marvell,chainmask = <4 4>;
-+ };
-+};
-+
-+&pcie2 {
-+ mwlwifi {
-+ marvell,chainmask = <4 4>;
-+ };
-+};
-+
- &sdhci {
- pinctrl-names = "default";
- pinctrl-0 = <&sdhci_pins>;
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -223,12 +223,100 @@
- pcie@2,0 {
- /* Port 0, Lane 1 */
- status = "okay";
-+
-+ mwlwifi {
-+ marvell,5ghz = <0>;
-+ marvell,chainmask = <4 4>;
-+ marvell,powertable {
-+ FCC =
-+ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;
-+
-+ ETSI =
-+ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
-+ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;
-+ };
-+ };
- };
-
- /* Second mini-PCIe port */
- pcie@3,0 {
- /* Port 0, Lane 3 */
- status = "okay";
-+
-+ mwlwifi {
-+ marvell,2ghz = <0>;
-+ marvell,chainmask = <4 4>;
-+ marvell,powertable {
-+ FCC =
-+ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
-+ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
-+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
-+ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
-+ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;
-+
-+ ETSI =
-+ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
-+ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;
-+ };
-+ };
- };
- };
-
+++ /dev/null
---- a/arch/arm/boot/dts/armada-xp.dtsi
-+++ b/arch/arm/boot/dts/armada-xp.dtsi
-@@ -237,12 +237,10 @@
- };
-
- &i2c0 {
-- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- reg = <0x11000 0x100>;
- };
-
- &i2c1 {
-- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
- reg = <0x11100 0x100>;
- };
-
+++ /dev/null
---- a/arch/arm/boot/dts/armada-388-rd.dts
-+++ b/arch/arm/boot/dts/armada-388-rd.dts
-@@ -103,6 +103,16 @@
- compatible = "st,m25p128", "jedec,spi-nor";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <108000000>;
-+
-+ partition@0 {
-+ label = "uboot";
-+ reg = <0 0x400000>;
-+ };
-+
-+ partition@1 {
-+ label = "firmware";
-+ reg = <0x400000 0xc00000>;
-+ };
- };
- };
-
+++ /dev/null
-From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Tue, 13 Jan 2015 11:14:09 +0100
-Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/armada-385-db-ap.dts | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/arm/boot/dts/armada-385-db-ap.dts
-+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
-@@ -218,19 +218,19 @@
- #size-cells = <1>;
-
- partition@0 {
-- label = "U-Boot";
-+ label = "u-boot";
- reg = <0x00000000 0x00800000>;
- read-only;
- };
-
- partition@800000 {
-- label = "uImage";
-+ label = "kernel";
- reg = <0x00800000 0x00400000>;
- read-only;
- };
-
- partition@c00000 {
-- label = "Root";
-+ label = "ubi";
- reg = <0x00c00000 0x3f400000>;
- };
- };
+++ /dev/null
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -483,3 +483,7 @@
- };
- };
- };
-+
-+&coherencyfab {
-+ broken-idle;
-+};
+++ /dev/null
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -385,7 +385,7 @@
-
- port@4 {
- reg = <4>;
-- label = "internet";
-+ label = "wan";
- };
-
- port@5 {
+++ /dev/null
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -14,6 +14,13 @@
- compatible = "linksys,armada385", "marvell,armada385",
- "marvell,armada380";
-
-+ aliases {
-+ led-boot = &led_power;
-+ led-failsafe = &led_power;
-+ led-running = &led_power;
-+ led-upgrade = &led_power;
-+ };
-+
- chosen {
- stdout-path = "serial0:115200n8";
- };
-@@ -71,7 +78,7 @@
- pinctrl-0 = <&gpio_leds_pins>;
- pinctrl-names = "default";
-
-- power {
-+ led_power: power {
- gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -26,6 +26,13 @@
- compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
- "marvell,armadaxp", "marvell,armada-370-xp";
-
-+ aliases {
-+ led-boot = &led_power;
-+ led-failsafe = &led_power;
-+ led-running = &led_power;
-+ led-upgrade = &led_power;
-+ };
-+
- chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &uart0;
-@@ -195,7 +202,7 @@
- pinctrl-0 = <&power_led_pin>;
- pinctrl-names = "default";
-
-- power {
-+ led_power: power {
- label = "mamba:white:power";
- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- default-state = "on";
+++ /dev/null
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -116,7 +116,7 @@
- };
-
- ð2 {
-- status = "okay";
-+ status = "disabled";
- phy-mode = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
-@@ -200,10 +200,10 @@
- label = "wan";
- };
-
-- port@5 {
-- reg = <5>;
-+ port@6 {
-+ reg = <6>;
- label = "cpu";
-- ethernet = <ð2>;
-+ ethernet = <ð0>;
-
- fixed-link {
- speed = <1000>;
+++ /dev/null
---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
-@@ -12,8 +12,8 @@
-
- / {
- model = "Linksys WRT3200ACM";
-- compatible = "linksys,rango", "linksys,armada385", "marvell,armada385",
-- "marvell,armada380";
-+ compatible = "linksys,wrt3200acm", "linksys,rango", "linksys,armada385",
-+ "marvell,armada385", "marvell,armada380";
- };
-
- &expander0 {
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -22,9 +22,10 @@
- #include "armada-xp-mv78230.dtsi"
-
- / {
-- model = "Linksys WRT1900AC";
-- compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
-- "marvell,armadaxp", "marvell,armada-370-xp";
-+ model = "Linksys WRT1900AC v1";
-+ compatible = "linksys,wrt1900ac-v1", "linksys,mamba",
-+ "marvell,armadaxp-mv78230", "marvell,armadaxp",
-+ "marvell,armada-370-xp";
-
- aliases {
- led-boot = &led_power;
---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
-@@ -9,8 +9,9 @@
- #include "armada-385-linksys.dtsi"
-
- / {
-- model = "Linksys WRT1900ACv2";
-- compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
-+ model = "Linksys WRT1900AC v2";
-+ compatible = "linksys,wrt1900ac-v2", "linksys,cobra",
-+ "linksys,armada385", "marvell,armada385",
- "marvell,armada380";
- };
-
---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
-@@ -10,8 +10,8 @@
-
- / {
- model = "Linksys WRT1200AC";
-- compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
-- "marvell,armada380";
-+ compatible = "linksys,wrt1200ac", "linksys,caiman", "linksys,armada385",
-+ "marvell,armada385", "marvell,armada380";
- };
-
- &expander0 {
---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
-@@ -10,7 +10,8 @@
-
- / {
- model = "Linksys WRT1900ACS";
-- compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
-+ compatible = "linksys,wrt1900acs", "linksys,shelby",
-+ "linksys,armada385", "marvell,armada385",
- "marvell,armada380";
- };
-
+++ /dev/null
-From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Tue, 29 Nov 2016 10:15:45 +0000
-Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
----
- .../arm/boot/dts/armada-388-clearfog-base.dts | 1 +
- .../armada-38x-solidrun-microsom-emmc.dtsi | 62 +++++++++++++++++++
- 2 files changed, 63 insertions(+)
- create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
-
---- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
-+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
-@@ -7,6 +7,7 @@
-
- /dts-v1/;
- #include "armada-388-clearfog.dtsi"
-+#include "armada-38x-solidrun-microsom-emmc.dtsi"
-
- / {
- model = "SolidRun Clearfog Base A1";
---- /dev/null
-+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
-@@ -0,0 +1,62 @@
-+/*
-+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
-+ *
-+ * Copyright (C) 2015 Russell King
-+ *
-+ * This board is in development; the contents of this file work with
-+ * the A1 rev 2.0 of the board, which does not represent final
-+ * production board. Things will change, don't expect this file to
-+ * remain compatible info the future.
-+ *
-+ * This file is dual-licensed: you can use it either under the terms
-+ * of the GPL or the X11 license, at your option. Note that this dual
-+ * licensing only applies to this file, and not this project as a
-+ * whole.
-+ *
-+ * a) This file is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This file is distributed in the hope that it will be useful
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * Or, alternatively
-+ *
-+ * b) Permission is hereby granted, free of charge, to any person
-+ * obtaining a copy of this software and associated documentation
-+ * files (the "Software"), to deal in the Software without
-+ * restriction, including without limitation the rights to use
-+ * copy, modify, merge, publish, distribute, sublicense, and/or
-+ * sell copies of the Software, and to permit persons to whom the
-+ * Software is furnished to do so, subject to the following
-+ * conditions:
-+ *
-+ * The above copyright notice and this permission notice shall be
-+ * included in all copies or substantial portions of the Software.
-+ *
-+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
-+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
-+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-+ * OTHER DEALINGS IN THE SOFTWARE.
-+ */
-+/ {
-+ soc {
-+ internal-regs {
-+ sdhci@d8000 {
-+ bus-width = <4>;
-+ no-1-8-v;
-+ non-removable;
-+ pinctrl-0 = <µsom_sdhci_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+ wp-inverted;
-+ };
-+ };
-+ };
-+};
+++ /dev/null
---- a/arch/arm/boot/dts/armada-388-helios4.dts
-+++ b/arch/arm/boot/dts/armada-388-helios4.dts
-@@ -15,6 +15,13 @@
- model = "Helios4";
- compatible = "kobol,helios4", "marvell,armada388",
- "marvell,armada385", "marvell,armada380";
-+
-+ aliases {
-+ led-boot = &led_status;
-+ led-failsafe = &led_status;
-+ led-running = &led_status;
-+ led-upgrade = &led_status;
-+ };
-
- memory {
- device_type = "memory";
-@@ -73,10 +80,9 @@
- pinctrl-names = "default";
- pinctrl-0 = <&helios_system_led_pins>;
-
-- status-led {
-+ led_status: status-led {
- label = "helios4:green:status";
- gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
-- linux,default-trigger = "heartbeat";
- default-state = "on";
- };
-
+++ /dev/null
-From: Tomasz Maciej Nowak <tmn505@gmail.com>
-Date: Fri, 7 Jul 2023 19:06:05 +0200
-Subject: [PATCH] arm64: dts: marvell: enable heartbeat LED by default
-
-Some boards could be placed in an enclosure, so enable LED18 by default,
-since that'll be the only visible indicator that the board is operating.
-
-Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
----
- arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
-+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
-@@ -25,6 +25,7 @@
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- linux,default-trigger = "heartbeat";
-+ default-state = "on";
- };
- };
- };
+++ /dev/null
-From 258233f00bcd013050efee00c5d9128ef8cd62dd Mon Sep 17 00:00:00 2001
-From: Tad <tad@spotco.us>
-Date: Fri, 5 Feb 2021 22:32:11 -0500
-Subject: [PATCH] ARM: dts: armada-xp-linksys-mamba: Increase kernel
- partition to 4MB
-
-Signed-off-by: Tad Davanzo <tad@spotco.us>
----
- arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
-@@ -454,9 +454,9 @@
- reg = <0xa00000 0x2800000>; /* 40MB */
- };
-
-- partition@d00000 {
-+ partition@e00000 {
- label = "rootfs1";
-- reg = <0xd00000 0x2500000>; /* 37MB */
-+ reg = <0xe00000 0x2400000>; /* 36MB */
- };
-
- /* kernel2 overlaps with rootfs2 by design */
-@@ -465,9 +465,9 @@
- reg = <0x3200000 0x2800000>; /* 40MB */
- };
-
-- partition@3500000 {
-+ partition@3600000 {
- label = "rootfs2";
-- reg = <0x3500000 0x2500000>; /* 37MB */
-+ reg = <0x3600000 0x2400000>; /* 36MB */
- };
-
- /*
+++ /dev/null
---- a/arch/arm/boot/dts/armada-370.dtsi
-+++ b/arch/arm/boot/dts/armada-370.dtsi
-@@ -254,7 +254,7 @@
- clocks = <&gateclk 23>;
- clock-names = "cesa0";
- marvell,crypto-srams = <&crypto_sram>;
-- marvell,crypto-sram-size = <0x7e0>;
-+ marvell,crypto-sram-size = <0x800>;
- };
- };
-
-@@ -275,12 +275,17 @@
- * cpuidle workaround.
- */
- idle-sram@0 {
-+ status = "disabled";
- reg = <0x0 0x20>;
- };
- };
- };
- };
-
-+&coherencyfab {
-+ broken-idle;
-+};
-+
- /*
- * Default UART pinctrl setting without RTS/CTS, can be overwritten on
- * board level if a different configuration is used.
+++ /dev/null
---- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts
-+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
-@@ -31,6 +31,7 @@
-
- chosen {
- stdout-path = "serial0:115200n8";
-+ append-rootblock = "nullparameter="; /* override the bootloader args */
- };
-
- memory@0 {
-@@ -94,6 +95,8 @@
- status = "okay";
- phy = <&phy1>;
- phy-mode = "sgmii";
-+ nvmem-cells = <&macaddr_vendor_0>;
-+ nvmem-cell-names = "mac-address";
- };
-
- sata@a0000 {
-@@ -175,6 +178,24 @@
- gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- };
- };
-+
-+ virtual_flash {
-+ compatible = "mtd-concat";
-+
-+ devices = <&mtd_kernel &mtd_gap &mtd_gap2>;
-+
-+ partitions {
-+ compatible = "fixed-partitions";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ compatible = "openwrt,uimage", "denx,uimage";
-+ label = "firmware";
-+ reg = <0x0 0x0>;
-+ };
-+ };
-+ };
- };
-
- &mdio {
-@@ -265,48 +286,52 @@
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <20000000>;
-
-- /*
-- * Warning!
-- *
-- * Synology u-boot uses its compiled-in environment
-- * and it seems Synology did not care to change u-boot
-- * default configuration in order to allow saving a
-- * modified environment at a sensible location. So,
-- * if you do a 'saveenv' under u-boot, your modified
-- * environment will be saved at 1MB after the start
-- * of the flash, i.e. in the middle of the uImage.
-- * For that reason, it is strongly advised not to
-- * change the default environment, unless you know
-- * what you are doing.
-- */
-- partition@0 { /* u-boot */
-- label = "RedBoot";
-- reg = <0x00000000 0x000c0000>; /* 768KB */
-- };
-+ partitions {
-+ compatible = "fixed-partitions";
-
-- partition@c0000 { /* uImage */
-- label = "zImage";
-- reg = <0x000c0000 0x002d0000>; /* 2880KB */
-- };
-+ partition@0 { /* u-boot */
-+ label = "u-boot";
-+ reg = <0x00000000 0x000c0000>; /* 768KB */
-+ read-only;
-+ };
-
-- partition@390000 { /* uInitramfs */
-- label = "rd.gz";
-- reg = <0x00390000 0x00440000>; /* 4250KB */
-- };
-+ mtd_gap: partition@c0000 { /* gap */
-+ label = "gap";
-+ reg = <0x000c0000 0x00040000>; /* 256KB */
-+ };
-
-- partition@7d0000 { /* MAC address and serial number */
-- label = "vendor";
-- reg = <0x007d0000 0x00010000>; /* 64KB */
-- };
-+ partition@100000 { /* u-boot-env */
-+ label = "u-boot-env";
-+ reg = <0x00100000 0x00010000>; /* 64KB */
-+ };
-
-- partition@7e0000 {
-- label = "RedBoot config";
-- reg = <0x007e0000 0x00010000>; /* 64KB */
-- };
-+ mtd_kernel: partition@110000 {
-+ label = "kernel";
-+ reg = <0x00110000 0x006c0000>; /* 6912KB */
-+ };
-
-- partition@7f0000 {
-- label = "FIS directory";
-- reg = <0x007f0000 0x00010000>; /* 64KB */
-+ partition@7d0000 { /* MAC address and serial number */
-+ reg = <0x007d0000 0x00010000>; /* 64KB */
-+ label = "vendor";
-+ read-only;
-+
-+ compatible = "nvmem-cells";
-+
-+ nvmem-layout {
-+ compatible = "fixed-layout";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ macaddr_vendor_0: macaddr@0 {
-+ reg = <0x0 0x6>;
-+ };
-+ };
-+ };
-+
-+ mtd_gap2: partition@7e0000 {
-+ label = "gap2";
-+ reg = <0x007e0000 0x00020000>; /* 128KB */
-+ };
- };
- };
- };
+++ /dev/null
-The WRT1900AC among other Linksys routers uses a dual-firmware layout.
-Dynamically rename the active partition to "ubi".
-
-Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
-
---- a/drivers/mtd/parsers/ofpart_core.c
-+++ b/drivers/mtd/parsers/ofpart_core.c
-@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d
- return of_get_property(pp, "compatible", NULL);
- }
-
-+static int mangled_rootblock;
-+
- static int parse_fixed_partitions(struct mtd_info *master,
- const struct mtd_partition **pparts,
- struct mtd_part_parser_data *data)
-@@ -48,6 +50,7 @@ static int parse_fixed_partitions(struct
- struct device_node *mtd_node;
- struct device_node *ofpart_node;
- const char *partname;
-+ const char *owrtpart = "ubi";
- struct device_node *pp;
- int nr_parts, i, ret = 0;
- bool dedicated = true;
-@@ -152,9 +155,13 @@ static int parse_fixed_partitions(struct
- parts[i].size = of_read_number(reg + a_cells, s_cells);
- parts[i].of_node = pp;
-
-- partname = of_get_property(pp, "label", &len);
-- if (!partname)
-- partname = of_get_property(pp, "name", &len);
-+ if (mangled_rootblock && (i == mangled_rootblock)) {
-+ partname = owrtpart;
-+ } else {
-+ partname = of_get_property(pp, "label", &len);
-+ if (!partname)
-+ partname = of_get_property(pp, "name", &len);
-+ }
- parts[i].name = partname;
-
- if (of_get_property(pp, "read-only", &len))
-@@ -271,6 +278,18 @@ static int __init ofpart_parser_init(voi
- return 0;
- }
-
-+static int __init active_root(char *str)
-+{
-+ get_option(&str, &mangled_rootblock);
-+
-+ if (!mangled_rootblock)
-+ return 1;
-+
-+ return 1;
-+}
-+
-+__setup("mangled_rootblock=", active_root);
-+
- static void __exit ofpart_parser_exit(void)
- {
- deregister_mtd_parser(&ofpart_parser);
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Subject: mvneta: tx queue workaround
-
-The hardware queue scheduling is apparently configured with fixed
-priorities, which creates a nasty fairness issue where traffic from one
-CPU can starve traffic from all other CPUs.
-
-Work around this issue by forcing all tx packets to go through one CPU,
-until this issue is fixed properly.
-
-Ref: https://github.com/openwrt/openwrt/issues/5411
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
---- a/drivers/net/ethernet/marvell/mvneta.c
-+++ b/drivers/net/ethernet/marvell/mvneta.c
-@@ -5233,6 +5233,16 @@ static int mvneta_setup_tc(struct net_de
- }
- }
-
-+#ifndef CONFIG_ARM64
-+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
-+ struct net_device *sb_dev)
-+{
-+ /* XXX: hardware queue scheduling is broken,
-+ * use only one queue until it is fixed */
-+ return 0;
-+}
-+#endif
-+
- static const struct net_device_ops mvneta_netdev_ops = {
- .ndo_open = mvneta_open,
- .ndo_stop = mvneta_stop,
-@@ -5243,6 +5253,9 @@ static const struct net_device_ops mvnet
- .ndo_fix_features = mvneta_fix_features,
- .ndo_get_stats64 = mvneta_get_stats64,
- .ndo_eth_ioctl = mvneta_ioctl,
-+#ifndef CONFIG_ARM64
-+ .ndo_select_queue = mvneta_select_queue,
-+#endif
- .ndo_bpf = mvneta_xdp,
- .ndo_xdp_xmit = mvneta_xdp_xmit,
- .ndo_setup_tc = mvneta_setup_tc,
+++ /dev/null
-From: Tobias Schramm <tobias@t-sys.eu>
-Subject: mvpp2: support fetching mac address from nvmem
-
-The mvpp2 driver did not query nvmem for hardware mac addresses. This
-patch adds querying of mac addresses stored in nvmem cells as a further
-fallback option before assigning a random address.
-Purposely added separately to fwnode_get_mac_address() above to maintain
-existing behaviour with builtin adapter mac address still taking
-precedence.
-
-Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
----
---- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-@@ -6134,6 +6134,12 @@ static void mvpp2_port_copy_mac_addr(str
- }
- }
-
-+ if (!of_get_mac_address(to_of_node(fwnode), hw_mac_addr)) {
-+ *mac_from = "nvmem cell";
-+ eth_hw_addr_set(dev, hw_mac_addr);
-+ return;
-+ }
-+
- *mac_from = "random";
- eth_hw_addr_random(dev);
- }
+++ /dev/null
-From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@arm.linux.org.uk>
-Date: Sat, 3 Oct 2015 09:13:05 +0100
-Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states
-
-The cpuidle ->enter method expects the return value to be the sleep
-state we entered. Returning negative numbers or other codes is not
-permissible since coupled CPU idle was merged.
-
-At least some of the mvebu_v7_cpu_suspend() implementations return the
-value from cpu_suspend(), which returns zero if the CPU vectors back
-into the kernel via cpu_resume() (the success case), or the non-zero
-return value of the suspend actor, or one (failure cases).
-
-We do not want to be returning the failure case value back to CPU idle
-as that indicates that we successfully entered one of the deeper idle
-states. Always return zero instead, indicating that we slept for the
-shortest amount of time.
-
-Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
----
- drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/drivers/cpuidle/cpuidle-mvebu-v7.c
-+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
-@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp
- ret = mvebu_v7_cpu_suspend(deepidle);
- cpu_pm_exit();
-
-+ /*
-+ * If we failed to enter the desired state, indicate that we
-+ * slept lightly.
-+ */
- if (ret)
-- return ret;
-+ return 0;
-
- return index;
- }
+++ /dev/null
-From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
-From: Russell King <rmk+kernel@armlinux.org.uk>
-Date: Sat, 9 Jul 2016 10:58:16 +0100
-Subject: pci: mvebu: time out reset on link up
-
-If the port reports that the link is up while we are resetting, there's
-little point in waiting for the full duration.
-
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
----
- drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------
- 1 file changed, 14 insertions(+), 6 deletions(-)
-
---- a/drivers/pci/controller/pci-mvebu.c
-+++ b/drivers/pci/controller/pci-mvebu.c
-@@ -1414,6 +1414,7 @@ static int mvebu_pcie_powerup(struct mve
-
- if (port->reset_gpio) {
- u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
-+ unsigned int i;
-
- of_property_read_u32(port->dn, "reset-delay-us",
- &reset_udelay);
-@@ -1421,7 +1422,13 @@ static int mvebu_pcie_powerup(struct mve
- udelay(100);
-
- gpiod_set_value_cansleep(port->reset_gpio, 0);
-- msleep(reset_udelay / 1000);
-+ for (i = 0; i < reset_udelay; i += 1000) {
-+ if (mvebu_pcie_link_up(port))
-+ break;
-+ msleep(1);
-+ }
-+
-+ printk("%s: reset completed in %dus\n", port->name, i);
- }
-
- return 0;
-@@ -1538,15 +1545,16 @@ static int mvebu_pcie_probe(struct platf
- if (!child)
- continue;
-
-- ret = mvebu_pcie_powerup(port);
-- if (ret < 0)
-- continue;
--
- port->base = mvebu_pcie_map_registers(pdev, child, port);
- if (IS_ERR(port->base)) {
- dev_err(dev, "%s: cannot map registers\n", port->name);
- port->base = NULL;
-- mvebu_pcie_powerdown(port);
-+ continue;
-+ }
-+
-+ ret = mvebu_pcie_powerup(port);
-+ if (ret < 0) {
-+ port->base = NULL;
- continue;
- }
-
+++ /dev/null
-From aa4a0ccc41997f2da172165c92803abace43bd1c Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:32 +0000
-Subject: [PATCH 1/7] dt-bindings: Add IEI vendor prefix and IEI WT61P803
- PUZZLE driver bindings
-
-Add the IEI WT61P803 PUZZLE Device Tree bindings for MFD, HWMON and LED
-drivers. A new vendor prefix is also added accordingly for
-IEI Integration Corp.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../hwmon/iei,wt61p803-puzzle-hwmon.yaml | 53 ++++++++++++
- .../leds/iei,wt61p803-puzzle-leds.yaml | 39 +++++++++
- .../bindings/mfd/iei,wt61p803-puzzle.yaml | 82 +++++++++++++++++++
- .../devicetree/bindings/vendor-prefixes.yaml | 2 +
- 4 files changed, 176 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
- create mode 100644 Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
- create mode 100644 Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-@@ -0,0 +1,53 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU HWMON module from IEI Integration Corp.
-+
-+maintainers:
-+ - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+ This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
-+ see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
-+
-+ The HWMON module is a sub-node of the MCU node in the Device Tree.
-+
-+properties:
-+ compatible:
-+ const: iei,wt61p803-puzzle-hwmon
-+
-+ "#address-cells":
-+ const: 1
-+
-+ "#size-cells":
-+ const: 0
-+
-+patternProperties:
-+ "^fan-group@[0-1]$":
-+ type: object
-+ properties:
-+ reg:
-+ minimum: 0
-+ maximum: 1
-+ description:
-+ Fan group ID
-+
-+ cooling-levels:
-+ minItems: 1
-+ maxItems: 255
-+ description:
-+ Cooling levels for the fans (PWM value mapping)
-+ description: |
-+ Properties for each fan group.
-+ required:
-+ - reg
-+
-+required:
-+ - compatible
-+ - "#address-cells"
-+ - "#size-cells"
-+
-+additionalProperties: false
---- /dev/null
-+++ b/Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
-@@ -0,0 +1,39 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/leds/iei,wt61p803-puzzle-leds.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU LED module from IEI Integration Corp.
-+
-+maintainers:
-+ - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+ This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details
-+ see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.
-+
-+ The LED module is a sub-node of the MCU node in the Device Tree.
-+
-+properties:
-+ compatible:
-+ const: iei,wt61p803-puzzle-leds
-+
-+ "#address-cells":
-+ const: 1
-+
-+ "#size-cells":
-+ const: 0
-+
-+ led@0:
-+ type: object
-+ $ref: common.yaml
-+ description: |
-+ Properties for a single LED.
-+
-+required:
-+ - compatible
-+ - "#address-cells"
-+ - "#size-cells"
-+
-+additionalProperties: false
---- /dev/null
-+++ b/Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-@@ -0,0 +1,82 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/mfd/iei,wt61p803-puzzle.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: IEI WT61P803 PUZZLE MCU from IEI Integration Corp.
-+
-+maintainers:
-+ - Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+description: |
-+ IEI WT61P803 PUZZLE MCU is embedded in some IEI Puzzle series boards.
-+ It's used for controlling system power states, fans, LEDs and temperature
-+ sensors.
-+
-+ For Device Tree bindings of other sub-modules (HWMON, LEDs) refer to the
-+ binding documents under the respective subsystem directories.
-+
-+properties:
-+ compatible:
-+ const: iei,wt61p803-puzzle
-+
-+ current-speed:
-+ description:
-+ Serial bus speed in bps
-+ maxItems: 1
-+
-+ enable-beep: true
-+
-+ hwmon:
-+ $ref: /schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-+
-+ leds:
-+ $ref: /schemas/leds/iei,wt61p803-puzzle-leds.yaml
-+
-+required:
-+ - compatible
-+ - current-speed
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ #include <dt-bindings/leds/common.h>
-+ serial {
-+ mcu {
-+ compatible = "iei,wt61p803-puzzle";
-+ current-speed = <115200>;
-+ enable-beep;
-+
-+ leds {
-+ compatible = "iei,wt61p803-puzzle-leds";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ led@0 {
-+ reg = <0>;
-+ function = LED_FUNCTION_POWER;
-+ color = <LED_COLOR_ID_BLUE>;
-+ };
-+ };
-+
-+ hwmon {
-+ compatible = "iei,wt61p803-puzzle-hwmon";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ fan-group@0 {
-+ #cooling-cells = <2>;
-+ reg = <0x00>;
-+ cooling-levels = <64 102 170 230 250>;
-+ };
-+
-+ fan-group@1 {
-+ #cooling-cells = <2>;
-+ reg = <0x01>;
-+ cooling-levels = <64 102 170 230 250>;
-+ };
-+ };
-+ };
-+ };
---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
-+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
-@@ -579,6 +579,8 @@ patternProperties:
- description: IC Plus Corp.
- "^idt,.*":
- description: Integrated Device Technologies, Inc.
-+ "^iei,.*":
-+ description: IEI Integration Corp.
- "^ifi,.*":
- description: Ingenieurburo Fur Ic-Technologie (I/F/I)
- "^ilitek,.*":
+++ /dev/null
-From 692cfa85272dd12995b427c0a7a585ced5d54f32 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:33 +0000
-Subject: [PATCH 2/7] drivers: mfd: Add a driver for IEI WT61P803 PUZZLE MCU
-
-Add a driver for the IEI WT61P803 PUZZLE microcontroller, used in some
-IEI Puzzle series devices. The microcontroller controls system power,
-temperature sensors, fans and LEDs.
-
-This driver implements the core functionality for device communication
-over the system serial (serdev bus). It handles MCU messages and the
-internal MCU properties. Some properties can be managed over sysfs.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/mfd/Kconfig | 9 +
- drivers/mfd/Makefile | 1 +
- drivers/mfd/iei-wt61p803-puzzle.c | 908 ++++++++++++++++++++++++
- include/linux/mfd/iei-wt61p803-puzzle.h | 66 ++
- 4 files changed, 984 insertions(+)
- create mode 100644 drivers/mfd/iei-wt61p803-puzzle.c
- create mode 100644 include/linux/mfd/iei-wt61p803-puzzle.h
-
---- a/drivers/mfd/Kconfig
-+++ b/drivers/mfd/Kconfig
-@@ -2222,6 +2222,15 @@ config SGI_MFD_IOC3
- If you have an SGI Origin, Octane, or a PCI IOC3 card,
- then say Y. Otherwise say N.
-
-+config MFD_IEI_WT61P803_PUZZLE
-+ tristate "IEI WT61P803 PUZZLE MCU driver"
-+ depends on SERIAL_DEV_BUS
-+ select MFD_CORE
-+ help
-+ IEI WT61P803 PUZZLE is a system power management microcontroller
-+ used for fan control, temperature sensor reading, LED control
-+ and system identification.
-+
- config MFD_INTEL_M10_BMC
- tristate "Intel MAX 10 Board Management Controller"
- depends on SPI_MASTER
---- a/drivers/mfd/Makefile
-+++ b/drivers/mfd/Makefile
-@@ -244,6 +244,7 @@ obj-$(CONFIG_MFD_RT4831) += rt4831.o
- obj-$(CONFIG_MFD_RT5033) += rt5033.o
- obj-$(CONFIG_MFD_RT5120) += rt5120.o
- obj-$(CONFIG_MFD_SKY81452) += sky81452.o
-+obj-$(CONFIG_MFD_IEI_WT61P803_PUZZLE) += iei-wt61p803-puzzle.o
-
- obj-$(CONFIG_INTEL_SOC_PMIC) += intel_soc_pmic_crc.o
- obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
---- /dev/null
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -0,0 +1,908 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU Driver
-+ * System management microcontroller for fan control, temperature sensor reading,
-+ * LED control and system identification on IEI Puzzle series ARM-based appliances.
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/atomic.h>
-+#include <linux/delay.h>
-+#include <linux/export.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/mfd/core.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/property.h>
-+#include <linux/sched.h>
-+#include <linux/serdev.h>
-+#include <linux/slab.h>
-+#include <linux/sysfs.h>
-+#include <asm/unaligned.h>
-+
-+/* start, payload and XOR checksum at end */
-+#define IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH (1 + 20 + 1)
-+#define IEI_WT61P803_PUZZLE_RESP_BUF_SIZE 512
-+
-+#define IEI_WT61P803_PUZZLE_MAC_LENGTH 17
-+#define IEI_WT61P803_PUZZLE_SN_LENGTH 36
-+#define IEI_WT61P803_PUZZLE_VERSION_LENGTH 6
-+#define IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH 16
-+#define IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH 8
-+#define IEI_WT61P803_PUZZLE_NB_MAC 8
-+
-+/* Use HZ as a timeout value throughout the driver */
-+#define IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT HZ
-+
-+enum iei_wt61p803_puzzle_attribute_type {
-+ IEI_WT61P803_PUZZLE_VERSION,
-+ IEI_WT61P803_PUZZLE_BUILD_INFO,
-+ IEI_WT61P803_PUZZLE_BOOTLOADER_MODE,
-+ IEI_WT61P803_PUZZLE_PROTOCOL_VERSION,
-+ IEI_WT61P803_PUZZLE_SERIAL_NUMBER,
-+ IEI_WT61P803_PUZZLE_MAC_ADDRESS,
-+ IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS,
-+ IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY,
-+ IEI_WT61P803_PUZZLE_POWER_STATUS,
-+};
-+
-+struct iei_wt61p803_puzzle_device_attribute {
-+ struct device_attribute dev_attr;
-+ enum iei_wt61p803_puzzle_attribute_type type;
-+ u8 index;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_mcu_status - MCU flags state
-+ * @ac_recovery_status_flag: AC Recovery Status Flag
-+ * @power_loss_recovery: System recovery after power loss
-+ * @power_status: System Power-on Method
-+ */
-+struct iei_wt61p803_puzzle_mcu_status {
-+ u8 ac_recovery_status_flag;
-+ u8 power_loss_recovery;
-+ u8 power_status;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_reply - MCU reply
-+ * @size: Size of the MCU reply
-+ * @data: Full MCU reply buffer
-+ * @state: Current state of the packet
-+ * @received: Was the response fullfilled
-+ */
-+struct iei_wt61p803_puzzle_reply {
-+ size_t size;
-+ unsigned char data[IEI_WT61P803_PUZZLE_RESP_BUF_SIZE];
-+ struct completion received;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_mcu_version - MCU version status
-+ * @version: Primary firmware version
-+ * @build_info: Build date and time
-+ * @bootloader_mode: Status of the MCU operation
-+ * @protocol_version: MCU communication protocol version
-+ * @serial_number: Device factory serial number
-+ * @mac_address: Device factory MAC addresses
-+ *
-+ * Last element of arrays is reserved for '\0'.
-+ */
-+struct iei_wt61p803_puzzle_mcu_version {
-+ char version[IEI_WT61P803_PUZZLE_VERSION_LENGTH + 1];
-+ char build_info[IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH + 1];
-+ bool bootloader_mode;
-+ char protocol_version[IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH + 1];
-+ char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH + 1];
-+ char mac_address[IEI_WT61P803_PUZZLE_NB_MAC][IEI_WT61P803_PUZZLE_MAC_LENGTH + 1];
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle - IEI WT61P803 PUZZLE MCU Driver
-+ * @serdev: Pointer to underlying serdev device
-+ * @dev: Pointer to underlying dev device
-+ * @reply_lock: Reply mutex lock
-+ * @reply: Pointer to the iei_wt61p803_puzzle_reply struct
-+ * @version: MCU version related data
-+ * @status: MCU status related data
-+ * @response_buffer Command response buffer allocation
-+ * @lock General member mutex lock
-+ */
-+struct iei_wt61p803_puzzle {
-+ struct serdev_device *serdev;
-+ struct device *dev;
-+ struct mutex reply_lock; /* lock to prevent multiple firmware calls */
-+ struct iei_wt61p803_puzzle_reply *reply;
-+ struct iei_wt61p803_puzzle_mcu_version version;
-+ struct iei_wt61p803_puzzle_mcu_status status;
-+ unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+ struct mutex lock; /* lock to protect response buffer */
-+};
-+
-+static unsigned char iei_wt61p803_puzzle_checksum(unsigned char *buf, size_t len)
-+{
-+ unsigned char checksum = 0;
-+ size_t i;
-+
-+ for (i = 0; i < len; i++)
-+ checksum ^= buf[i];
-+ return checksum;
-+}
-+
-+static int iei_wt61p803_puzzle_process_resp(struct iei_wt61p803_puzzle *mcu,
-+ const unsigned char *raw_resp_data, size_t size)
-+{
-+ unsigned char checksum;
-+
-+ /* Check the incoming frame header */
-+ if (!(raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START ||
-+ raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER ||
-+ (raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM &&
-+ raw_resp_data[1] == IEI_WT61P803_PUZZLE_CMD_EEPROM_READ))) {
-+ if (mcu->reply->size + size >= sizeof(mcu->reply->data))
-+ return -EIO;
-+
-+ /* Append the frame to existing data */
-+ memcpy(mcu->reply->data + mcu->reply->size, raw_resp_data, size);
-+ mcu->reply->size += size;
-+ } else {
-+ if (size >= sizeof(mcu->reply->data))
-+ return -EIO;
-+
-+ /* Start processing a new frame */
-+ memcpy(mcu->reply->data, raw_resp_data, size);
-+ mcu->reply->size = size;
-+ }
-+
-+ checksum = iei_wt61p803_puzzle_checksum(mcu->reply->data, mcu->reply->size - 1);
-+ if (checksum != mcu->reply->data[mcu->reply->size - 1]) {
-+ /* The checksum isn't matched yet, wait for new frames */
-+ return size;
-+ }
-+
-+ /* Received all the data */
-+ complete(&mcu->reply->received);
-+
-+ return size;
-+}
-+
-+static int iei_wt61p803_puzzle_recv_buf(struct serdev_device *serdev,
-+ const unsigned char *data, size_t size)
-+{
-+ struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev);
-+ int ret;
-+
-+ ret = iei_wt61p803_puzzle_process_resp(mcu, data, size);
-+ /* Return the number of processed bytes if function returns error,
-+ * discard the remaining incoming data, since the frame this data
-+ * belongs to is broken anyway
-+ */
-+ if (ret < 0)
-+ return size;
-+
-+ return ret;
-+}
-+
-+static const struct serdev_device_ops iei_wt61p803_puzzle_serdev_device_ops = {
-+ .receive_buf = iei_wt61p803_puzzle_recv_buf,
-+ .write_wakeup = serdev_device_write_wakeup,
-+};
-+
-+/**
-+ * iei_wt61p803_puzzle_write_command_watchdog() - Watchdog of the normal cmd
-+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct
-+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor))
-+ * @size: Size of the cmd char array
-+ * @reply_data: Pointer to the reply/response data array (should be allocated)
-+ * @reply_size: Pointer to size_t (size of reply_data)
-+ * @retry_count: Number of times to retry sending the command to the MCU
-+ */
-+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu,
-+ unsigned char *cmd, size_t size,
-+ unsigned char *reply_data,
-+ size_t *reply_size, int retry_count)
-+{
-+ struct device *dev = &mcu->serdev->dev;
-+ int ret, i;
-+
-+ for (i = 0; i < retry_count; i++) {
-+ ret = iei_wt61p803_puzzle_write_command(mcu, cmd, size,
-+ reply_data, reply_size);
-+ if (ret != -ETIMEDOUT)
-+ return ret;
-+ }
-+
-+ dev_err(dev, "Command response timed out. Retries: %d\n", retry_count);
-+
-+ return -ETIMEDOUT;
-+}
-+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command_watchdog);
-+
-+/**
-+ * iei_wt61p803_puzzle_write_command() - Send a structured command to the MCU
-+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct
-+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor))
-+ * @size: Size of the cmd char array
-+ * @reply_data: Pointer to the reply/response data array (should be allocated)
-+ *
-+ * Sends a structured command to the MCU.
-+ */
-+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu,
-+ unsigned char *cmd, size_t size,
-+ unsigned char *reply_data,
-+ size_t *reply_size)
-+{
-+ struct device *dev = &mcu->serdev->dev;
-+ int ret;
-+
-+ if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH)
-+ return -EINVAL;
-+
-+ mutex_lock(&mcu->reply_lock);
-+
-+ cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1);
-+
-+ /* Initialize reply struct */
-+ reinit_completion(&mcu->reply->received);
-+ mcu->reply->size = 0;
-+ usleep_range(2000, 10000);
-+ serdev_device_write_flush(mcu->serdev);
-+ ret = serdev_device_write_buf(mcu->serdev, cmd, size);
-+ if (ret < 0)
-+ goto exit;
-+
-+ serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+ ret = wait_for_completion_timeout(&mcu->reply->received,
-+ IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+ if (ret == 0) {
-+ dev_err(dev, "Command reply receive timeout\n");
-+ ret = -ETIMEDOUT;
-+ goto exit;
-+ }
-+
-+ *reply_size = mcu->reply->size;
-+ /* Copy the received data, as it will not be available after a new frame is received */
-+ memcpy(reply_data, mcu->reply->data, mcu->reply->size);
-+ ret = 0;
-+exit:
-+ mutex_unlock(&mcu->reply_lock);
-+ return ret;
-+}
-+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command);
-+
-+static int iei_wt61p803_puzzle_buzzer(struct iei_wt61p803_puzzle *mcu, bool long_beep)
-+{
-+ unsigned char *resp_buf = mcu->response_buffer;
-+ unsigned char buzzer_cmd[4] = {};
-+ size_t reply_size;
-+ int ret;
-+
-+ buzzer_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+ buzzer_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE;
-+ buzzer_cmd[2] = long_beep ? '3' : '2'; /* Buzzer 1.5 / 0.5 second beep */
-+
-+ mutex_lock(&mcu->lock);
-+ ret = iei_wt61p803_puzzle_write_command(mcu, buzzer_cmd, sizeof(buzzer_cmd),
-+ resp_buf, &reply_size);
-+ if (ret)
-+ goto exit;
-+
-+ if (reply_size != 3) {
-+ ret = -EIO;
-+ goto exit;
-+ }
-+
-+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+ ret = -EPROTO;
-+ goto exit;
-+ }
-+exit:
-+ mutex_unlock(&mcu->lock);
-+ return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_version(struct iei_wt61p803_puzzle *mcu)
-+{
-+ unsigned char version_cmd[3] = {
-+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+ IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION,
-+ };
-+ unsigned char build_info_cmd[3] = {
-+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+ IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD,
-+ };
-+ unsigned char bootloader_mode_cmd[3] = {
-+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+ IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE,
-+ };
-+ unsigned char protocol_version_cmd[3] = {
-+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,
-+ IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION,
-+ };
-+ unsigned char *rb = mcu->response_buffer;
-+ size_t reply_size;
-+ int ret;
-+
-+ mutex_lock(&mcu->lock);
-+
-+ ret = iei_wt61p803_puzzle_write_command(mcu, version_cmd, sizeof(version_cmd),
-+ rb, &reply_size);
-+ if (ret)
-+ goto err;
-+ if (reply_size < 7) {
-+ ret = -EIO;
-+ goto err;
-+ }
-+ sprintf(mcu->version.version, "v%c.%.3s", rb[2], &rb[3]);
-+
-+ ret = iei_wt61p803_puzzle_write_command(mcu, build_info_cmd,
-+ sizeof(build_info_cmd), rb,
-+ &reply_size);
-+ if (ret)
-+ goto err;
-+ if (reply_size < 15) {
-+ ret = -EIO;
-+ goto err;
-+ }
-+ sprintf(mcu->version.build_info, "%c%c/%c%c/%.4s %c%c:%c%c",
-+ rb[8], rb[9], rb[6], rb[7], &rb[2], rb[10], rb[11],
-+ rb[12], rb[13]);
-+
-+ ret = iei_wt61p803_puzzle_write_command(mcu, bootloader_mode_cmd,
-+ sizeof(bootloader_mode_cmd), rb,
-+ &reply_size);
-+ if (ret)
-+ goto err;
-+ if (reply_size < 4) {
-+ ret = -EIO;
-+ goto err;
-+ }
-+ if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS)
-+ mcu->version.bootloader_mode = false;
-+ else if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER)
-+ mcu->version.bootloader_mode = true;
-+
-+ ret = iei_wt61p803_puzzle_write_command(mcu, protocol_version_cmd,
-+ sizeof(protocol_version_cmd), rb,
-+ &reply_size);
-+ if (ret)
-+ goto err;
-+ if (reply_size < 9) {
-+ ret = -EIO;
-+ goto err;
-+ }
-+ sprintf(mcu->version.protocol_version, "v%c.%c%c%c%c%c",
-+ rb[7], rb[6], rb[5], rb[4], rb[3], rb[2]);
-+err:
-+ mutex_unlock(&mcu->lock);
-+ return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_mcu_status(struct iei_wt61p803_puzzle *mcu)
-+{
-+ unsigned char mcu_status_cmd[5] = {
-+ IEI_WT61P803_PUZZLE_CMD_HEADER_START,
-+ IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER,
-+ IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS,
-+ IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS,
-+ };
-+ unsigned char *resp_buf = mcu->response_buffer;
-+ size_t reply_size;
-+ int ret;
-+
-+ mutex_lock(&mcu->lock);
-+ ret = iei_wt61p803_puzzle_write_command(mcu, mcu_status_cmd, sizeof(mcu_status_cmd),
-+ resp_buf, &reply_size);
-+ if (ret)
-+ goto exit;
-+ if (reply_size < 20) {
-+ ret = -EIO;
-+ goto exit;
-+ }
-+
-+ /* Response format:
-+ * (IDX RESPONSE)
-+ * 0 @
-+ * 1 O
-+ * 2 S
-+ * 3 S
-+ * ...
-+ * 5 AC Recovery Status Flag
-+ * ...
-+ * 10 Power Loss Recovery
-+ * ...
-+ * 19 Power Status (system power on method)
-+ * 20 XOR checksum
-+ */
-+ if (resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER &&
-+ resp_buf[2] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS &&
-+ resp_buf[3] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS) {
-+ mcu->status.ac_recovery_status_flag = resp_buf[5];
-+ mcu->status.power_loss_recovery = resp_buf[10];
-+ mcu->status.power_status = resp_buf[19];
-+ }
-+exit:
-+ mutex_unlock(&mcu->lock);
-+ return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_serial_number(struct iei_wt61p803_puzzle *mcu)
-+{
-+ unsigned char *resp_buf = mcu->response_buffer;
-+ unsigned char serial_number_cmd[5] = {
-+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+ IEI_WT61P803_PUZZLE_CMD_EEPROM_READ,
-+ 0x00, /* EEPROM read address */
-+ 0x24, /* Data length */
-+ };
-+ size_t reply_size;
-+ int ret;
-+
-+ mutex_lock(&mcu->lock);
-+ ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd,
-+ sizeof(serial_number_cmd),
-+ resp_buf, &reply_size);
-+ if (ret)
-+ goto err;
-+
-+ if (reply_size < IEI_WT61P803_PUZZLE_SN_LENGTH + 4) {
-+ ret = -EIO;
-+ goto err;
-+ }
-+
-+ sprintf(mcu->version.serial_number, "%.*s",
-+ IEI_WT61P803_PUZZLE_SN_LENGTH, resp_buf + 4);
-+err:
-+ mutex_unlock(&mcu->lock);
-+ return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_serial_number(struct iei_wt61p803_puzzle *mcu,
-+ unsigned char serial_number[36])
-+{
-+ unsigned char *resp_buf = mcu->response_buffer;
-+ unsigned char serial_number_header[4] = {
-+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+ IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE,
-+ 0x00, /* EEPROM write address */
-+ 0xC, /* Data length */
-+ };
-+ unsigned char serial_number_cmd[4 + 12 + 1]; /* header, serial number, XOR checksum */
-+ int ret, sn_counter;
-+ size_t reply_size;
-+
-+ /* The MCU can only handle 22 byte messages, send the S/N in 12 byte chunks */
-+ mutex_lock(&mcu->lock);
-+ for (sn_counter = 0; sn_counter < 3; sn_counter++) {
-+ serial_number_header[2] = 0x0 + 0xC * sn_counter;
-+
-+ memcpy(serial_number_cmd, serial_number_header, sizeof(serial_number_header));
-+ memcpy(serial_number_cmd + sizeof(serial_number_header),
-+ serial_number + 0xC * sn_counter, 0xC);
-+
-+ ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd,
-+ sizeof(serial_number_cmd),
-+ resp_buf, &reply_size);
-+ if (ret)
-+ goto err;
-+ if (reply_size != 3) {
-+ ret = -EIO;
-+ goto err;
-+ }
-+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+ ret = -EPROTO;
-+ goto err;
-+ }
-+ }
-+
-+ sprintf(mcu->version.serial_number, "%.*s",
-+ IEI_WT61P803_PUZZLE_SN_LENGTH, serial_number);
-+err:
-+ mutex_unlock(&mcu->lock);
-+ return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_get_mac_address(struct iei_wt61p803_puzzle *mcu, int index)
-+{
-+ unsigned char *resp_buf = mcu->response_buffer;
-+ unsigned char mac_address_cmd[5] = {
-+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+ IEI_WT61P803_PUZZLE_CMD_EEPROM_READ,
-+ 0x00, /* EEPROM read address */
-+ 0x11, /* Data length */
-+ };
-+ size_t reply_size;
-+ int ret;
-+
-+ mutex_lock(&mcu->lock);
-+ mac_address_cmd[2] = 0x24 + 0x11 * index;
-+
-+ ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd,
-+ sizeof(mac_address_cmd),
-+ resp_buf, &reply_size);
-+ if (ret)
-+ goto err;
-+
-+ if (reply_size < 22) {
-+ ret = -EIO;
-+ goto err;
-+ }
-+
-+ sprintf(mcu->version.mac_address[index], "%.*s",
-+ IEI_WT61P803_PUZZLE_MAC_LENGTH, resp_buf + 4);
-+err:
-+ mutex_unlock(&mcu->lock);
-+ return ret;
-+}
-+
-+static int
-+iei_wt61p803_puzzle_write_mac_address(struct iei_wt61p803_puzzle *mcu,
-+ unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH],
-+ int mac_address_idx)
-+{
-+ unsigned char mac_address_cmd[4 + IEI_WT61P803_PUZZLE_MAC_LENGTH + 1];
-+ unsigned char *resp_buf = mcu->response_buffer;
-+ unsigned char mac_address_header[4] = {
-+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,
-+ IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE,
-+ 0x00, /* EEPROM write address */
-+ 0x11, /* Data length */
-+ };
-+ size_t reply_size;
-+ int ret;
-+
-+ if (mac_address_idx < 0 || mac_address_idx >= IEI_WT61P803_PUZZLE_NB_MAC)
-+ return -EINVAL;
-+
-+ mac_address_header[2] = 0x24 + 0x11 * mac_address_idx;
-+
-+ /* Concat mac_address_header, mac_address to mac_address_cmd */
-+ memcpy(mac_address_cmd, mac_address_header, sizeof(mac_address_header));
-+ memcpy(mac_address_cmd + sizeof(mac_address_header), mac_address,
-+ IEI_WT61P803_PUZZLE_MAC_LENGTH);
-+
-+ mutex_lock(&mcu->lock);
-+ ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd,
-+ sizeof(mac_address_cmd),
-+ resp_buf, &reply_size);
-+ if (ret)
-+ goto err;
-+ if (reply_size != 3) {
-+ ret = -EIO;
-+ goto err;
-+ }
-+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+ ret = -EPROTO;
-+ goto err;
-+ }
-+
-+ sprintf(mcu->version.mac_address[mac_address_idx], "%.*s",
-+ IEI_WT61P803_PUZZLE_MAC_LENGTH, mac_address);
-+err:
-+ mutex_unlock(&mcu->lock);
-+ return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_power_loss_recovery(struct iei_wt61p803_puzzle *mcu,
-+ int power_loss_recovery_action)
-+{
-+ unsigned char *resp_buf = mcu->response_buffer;
-+ unsigned char power_loss_recovery_cmd[5] = {};
-+ size_t reply_size;
-+ int ret;
-+
-+ if (power_loss_recovery_action < 0 || power_loss_recovery_action > 4)
-+ return -EINVAL;
-+
-+ power_loss_recovery_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+ power_loss_recovery_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER;
-+ power_loss_recovery_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS;
-+ power_loss_recovery_cmd[3] = hex_asc[power_loss_recovery_action];
-+
-+ mutex_lock(&mcu->lock);
-+ ret = iei_wt61p803_puzzle_write_command(mcu, power_loss_recovery_cmd,
-+ sizeof(power_loss_recovery_cmd),
-+ resp_buf, &reply_size);
-+ if (ret)
-+ goto exit;
-+ mcu->status.power_loss_recovery = power_loss_recovery_action;
-+exit:
-+ mutex_unlock(&mcu->lock);
-+ return ret;
-+}
-+
-+#define to_puzzle_dev_attr(_attr) \
-+ container_of(_attr, struct iei_wt61p803_puzzle_device_attribute, dev_attr)
-+
-+static ssize_t show_output(struct device *dev,
-+ struct device_attribute *attr, char *buf)
-+{
-+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+ struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr);
-+ int ret;
-+
-+ switch (pattr->type) {
-+ case IEI_WT61P803_PUZZLE_VERSION:
-+ return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.version);
-+ case IEI_WT61P803_PUZZLE_BUILD_INFO:
-+ return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.build_info);
-+ case IEI_WT61P803_PUZZLE_BOOTLOADER_MODE:
-+ return scnprintf(buf, PAGE_SIZE, "%d\n", mcu->version.bootloader_mode);
-+ case IEI_WT61P803_PUZZLE_PROTOCOL_VERSION:
-+ return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.protocol_version);
-+ case IEI_WT61P803_PUZZLE_SERIAL_NUMBER:
-+ ret = iei_wt61p803_puzzle_get_serial_number(mcu);
-+ if (!ret)
-+ ret = scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.serial_number);
-+ else
-+ ret = 0;
-+ return ret;
-+ case IEI_WT61P803_PUZZLE_MAC_ADDRESS:
-+ ret = iei_wt61p803_puzzle_get_mac_address(mcu, pattr->index);
-+ if (!ret)
-+ ret = scnprintf(buf, PAGE_SIZE, "%s\n",
-+ mcu->version.mac_address[pattr->index]);
-+ else
-+ ret = 0;
-+ return ret;
-+ case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS:
-+ case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+ case IEI_WT61P803_PUZZLE_POWER_STATUS:
-+ ret = iei_wt61p803_puzzle_get_mcu_status(mcu);
-+ if (ret)
-+ return ret;
-+
-+ mutex_lock(&mcu->lock);
-+ switch (pattr->type) {
-+ case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS:
-+ ret = scnprintf(buf, PAGE_SIZE, "%x\n",
-+ mcu->status.ac_recovery_status_flag);
-+ break;
-+ case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+ ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_loss_recovery);
-+ break;
-+ case IEI_WT61P803_PUZZLE_POWER_STATUS:
-+ ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_status);
-+ break;
-+ default:
-+ ret = 0;
-+ break;
-+ }
-+ mutex_unlock(&mcu->lock);
-+ return ret;
-+ default:
-+ return 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static ssize_t store_output(struct device *dev,
-+ struct device_attribute *attr,
-+ const char *buf, size_t len)
-+{
-+ unsigned char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH];
-+ unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH];
-+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+ struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr);
-+ int power_loss_recovery_action = 0;
-+ int ret;
-+
-+ switch (pattr->type) {
-+ case IEI_WT61P803_PUZZLE_SERIAL_NUMBER:
-+ if (len != (size_t)(IEI_WT61P803_PUZZLE_SN_LENGTH + 1))
-+ return -EINVAL;
-+ memcpy(serial_number, buf, sizeof(serial_number));
-+ ret = iei_wt61p803_puzzle_write_serial_number(mcu, serial_number);
-+ if (ret)
-+ return ret;
-+ return len;
-+ case IEI_WT61P803_PUZZLE_MAC_ADDRESS:
-+ if (len != (size_t)(IEI_WT61P803_PUZZLE_MAC_LENGTH + 1))
-+ return -EINVAL;
-+
-+ memcpy(mac_address, buf, sizeof(mac_address));
-+
-+ if (strlen(attr->attr.name) != 13)
-+ return -EIO;
-+
-+ ret = iei_wt61p803_puzzle_write_mac_address(mcu, mac_address, pattr->index);
-+ if (ret)
-+ return ret;
-+ return len;
-+ case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:
-+ ret = kstrtoint(buf, 10, &power_loss_recovery_action);
-+ if (ret)
-+ return ret;
-+ ret = iei_wt61p803_puzzle_write_power_loss_recovery(mcu,
-+ power_loss_recovery_action);
-+ if (ret)
-+ return ret;
-+ return len;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+#define IEI_WT61P803_PUZZLE_ATTR(_name, _mode, _show, _store, _type, _index) \
-+ struct iei_wt61p803_puzzle_device_attribute dev_attr_##_name = \
-+ { .dev_attr = __ATTR(_name, _mode, _show, _store), \
-+ .type = _type, \
-+ .index = _index }
-+
-+#define IEI_WT61P803_PUZZLE_ATTR_RO(_name, _type, _id) \
-+ IEI_WT61P803_PUZZLE_ATTR(_name, 0444, show_output, NULL, _type, _id)
-+
-+#define IEI_WT61P803_PUZZLE_ATTR_RW(_name, _type, _id) \
-+ IEI_WT61P803_PUZZLE_ATTR(_name, 0644, show_output, store_output, _type, _id)
-+
-+static IEI_WT61P803_PUZZLE_ATTR_RO(version, IEI_WT61P803_PUZZLE_VERSION, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(build_info, IEI_WT61P803_PUZZLE_BUILD_INFO, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(bootloader_mode, IEI_WT61P803_PUZZLE_BOOTLOADER_MODE, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(protocol_version, IEI_WT61P803_PUZZLE_PROTOCOL_VERSION, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(serial_number, IEI_WT61P803_PUZZLE_SERIAL_NUMBER, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_0, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_1, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 1);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_2, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 2);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_3, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 3);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_4, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 4);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_5, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 5);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_6, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 6);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_7, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 7);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(ac_recovery_status, IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RW(power_loss_recovery, IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY, 0);
-+static IEI_WT61P803_PUZZLE_ATTR_RO(power_status, IEI_WT61P803_PUZZLE_POWER_STATUS, 0);
-+
-+static struct attribute *iei_wt61p803_puzzle_attrs[] = {
-+ &dev_attr_version.dev_attr.attr,
-+ &dev_attr_build_info.dev_attr.attr,
-+ &dev_attr_bootloader_mode.dev_attr.attr,
-+ &dev_attr_protocol_version.dev_attr.attr,
-+ &dev_attr_serial_number.dev_attr.attr,
-+ &dev_attr_mac_address_0.dev_attr.attr,
-+ &dev_attr_mac_address_1.dev_attr.attr,
-+ &dev_attr_mac_address_2.dev_attr.attr,
-+ &dev_attr_mac_address_3.dev_attr.attr,
-+ &dev_attr_mac_address_4.dev_attr.attr,
-+ &dev_attr_mac_address_5.dev_attr.attr,
-+ &dev_attr_mac_address_6.dev_attr.attr,
-+ &dev_attr_mac_address_7.dev_attr.attr,
-+ &dev_attr_ac_recovery_status.dev_attr.attr,
-+ &dev_attr_power_loss_recovery.dev_attr.attr,
-+ &dev_attr_power_status.dev_attr.attr,
-+ NULL
-+};
-+ATTRIBUTE_GROUPS(iei_wt61p803_puzzle);
-+
-+static int iei_wt61p803_puzzle_sysfs_create(struct device *dev,
-+ struct iei_wt61p803_puzzle *mcu)
-+{
-+ int ret;
-+
-+ ret = sysfs_create_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups);
-+ if (ret)
-+ mfd_remove_devices(mcu->dev);
-+
-+ return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_sysfs_remove(struct device *dev,
-+ struct iei_wt61p803_puzzle *mcu)
-+{
-+ /* Remove sysfs groups */
-+ sysfs_remove_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups);
-+ mfd_remove_devices(mcu->dev);
-+
-+ return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_probe(struct serdev_device *serdev)
-+{
-+ struct device *dev = &serdev->dev;
-+ struct iei_wt61p803_puzzle *mcu;
-+ u32 baud;
-+ int ret;
-+
-+ /* Read the baud rate from 'current-speed', because the MCU supports different rates */
-+ if (device_property_read_u32(dev, "current-speed", &baud)) {
-+ dev_err(dev,
-+ "'current-speed' is not specified in device node\n");
-+ return -EINVAL;
-+ }
-+ dev_dbg(dev, "Driver baud rate: %d\n", baud);
-+
-+ /* Allocate the memory */
-+ mcu = devm_kzalloc(dev, sizeof(*mcu), GFP_KERNEL);
-+ if (!mcu)
-+ return -ENOMEM;
-+
-+ mcu->reply = devm_kzalloc(dev, sizeof(*mcu->reply), GFP_KERNEL);
-+ if (!mcu->reply)
-+ return -ENOMEM;
-+
-+ /* Initialize device struct data */
-+ mcu->serdev = serdev;
-+ mcu->dev = dev;
-+ init_completion(&mcu->reply->received);
-+ mutex_init(&mcu->reply_lock);
-+ mutex_init(&mcu->lock);
-+
-+ /* Setup UART interface */
-+ serdev_device_set_drvdata(serdev, mcu);
-+ serdev_device_set_client_ops(serdev, &iei_wt61p803_puzzle_serdev_device_ops);
-+ ret = devm_serdev_device_open(dev, serdev);
-+ if (ret)
-+ return ret;
-+ serdev_device_set_baudrate(serdev, baud);
-+ serdev_device_set_flow_control(serdev, false);
-+ ret = serdev_device_set_parity(serdev, SERDEV_PARITY_NONE);
-+ if (ret) {
-+ dev_err(dev, "Failed to set parity\n");
-+ return ret;
-+ }
-+
-+ ret = iei_wt61p803_puzzle_get_version(mcu);
-+ if (ret)
-+ return ret;
-+
-+ dev_dbg(dev, "MCU version: %s\n", mcu->version.version);
-+ dev_dbg(dev, "MCU firmware build info: %s\n", mcu->version.build_info);
-+ dev_dbg(dev, "MCU in bootloader mode: %s\n",
-+ mcu->version.bootloader_mode ? "true" : "false");
-+ dev_dbg(dev, "MCU protocol version: %s\n", mcu->version.protocol_version);
-+
-+ if (device_property_read_bool(dev, "enable-beep")) {
-+ ret = iei_wt61p803_puzzle_buzzer(mcu, false);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ ret = iei_wt61p803_puzzle_sysfs_create(dev, mcu);
-+ if (ret)
-+ return ret;
-+
-+ return devm_of_platform_populate(dev);
-+}
-+
-+static void iei_wt61p803_puzzle_remove(struct serdev_device *serdev)
-+{
-+ struct device *dev = &serdev->dev;
-+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);
-+
-+ iei_wt61p803_puzzle_sysfs_remove(dev, mcu);
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_dt_ids[] = {
-+ { .compatible = "iei,wt61p803-puzzle" },
-+ { }
-+};
-+
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_dt_ids);
-+
-+static struct serdev_device_driver iei_wt61p803_puzzle_drv = {
-+ .probe = iei_wt61p803_puzzle_probe,
-+ .remove = iei_wt61p803_puzzle_remove,
-+ .driver = {
-+ .name = "iei-wt61p803-puzzle",
-+ .of_match_table = iei_wt61p803_puzzle_dt_ids,
-+ },
-+};
-+
-+module_serdev_device_driver(iei_wt61p803_puzzle_drv);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU Driver");
---- /dev/null
-+++ b/include/linux/mfd/iei-wt61p803-puzzle.h
-@@ -0,0 +1,66 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+/* IEI WT61P803 PUZZLE MCU Driver
-+ * System management microcontroller for fan control, temperature sensor reading,
-+ * LED control and system identification on IEI Puzzle series ARM-based appliances.
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#ifndef _MFD_IEI_WT61P803_PUZZLE_H_
-+#define _MFD_IEI_WT61P803_PUZZLE_H_
-+
-+#define IEI_WT61P803_PUZZLE_BUF_SIZE 512
-+
-+/* Command magic numbers */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START 0x40 /* @ */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER 0x25 /* % */
-+#define IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM 0xF7
-+
-+#define IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK 0x30 /* 0 */
-+#define IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK 0x70
-+
-+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_READ 0xA1
-+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE 0xA0
-+
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION 0x56 /* V */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD 0x42 /* B */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE 0x4D /* M */
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER 0x30
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS 0x31
-+#define IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION 0x50 /* P */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE 0x43 /* C */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER 0x4F /* O */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS 0x53 /* S */
-+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_LED 0x52 /* R */
-+#define IEI_WT61P803_PUZZLE_CMD_LED_POWER 0x31 /* 1 */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_TEMP 0x54 /* T */
-+#define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL 0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FAN 0x46 /* F */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ 0x5A /* Z */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE 0x57 /* W */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE 0x30
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE 0x41 /* A */
-+
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE + (x)) /* 0 - 1 */
-+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE + (x)) /* 0 - 5 */
-+
-+struct iei_wt61p803_puzzle_mcu_version;
-+struct iei_wt61p803_puzzle_reply;
-+struct iei_wt61p803_puzzle;
-+
-+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu,
-+ unsigned char *cmd, size_t size,
-+ unsigned char *reply_data, size_t *reply_size,
-+ int retry_count);
-+
-+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu,
-+ unsigned char *cmd, size_t size,
-+ unsigned char *reply_data, size_t *reply_size);
-+
-+#endif /* _MFD_IEI_WT61P803_PUZZLE_H_ */
+++ /dev/null
-From e3310a638cd310bfd93dbbc6d2732ab6aea18dd2 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:34 +0000
-Subject: [PATCH 3/7] drivers: hwmon: Add the IEI WT61P803 PUZZLE HWMON driver
-
-Add the IEI WT61P803 PUZZLE HWMON driver, that handles the fan speed
-control via PWM, reading fan speed and reading on-board temperature
-sensors.
-
-The driver registers a HWMON device and a simple thermal cooling device to
-enable in-kernel fan management.
-
-This driver depends on the IEI WT61P803 PUZZLE MFD driver.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Acked-by: Guenter Roeck <linux@roeck-us.net>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/hwmon/Kconfig | 8 +
- drivers/hwmon/Makefile | 1 +
- drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 445 ++++++++++++++++++++++
- 3 files changed, 454 insertions(+)
- create mode 100644 drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-
---- a/drivers/hwmon/Kconfig
-+++ b/drivers/hwmon/Kconfig
-@@ -755,6 +755,14 @@ config SENSORS_IBMPOWERNV
- This driver can also be built as a module. If so, the module
- will be called ibmpowernv.
-
-+config SENSORS_IEI_WT61P803_PUZZLE_HWMON
-+ tristate "IEI WT61P803 PUZZLE MFD HWMON Driver"
-+ depends on MFD_IEI_WT61P803_PUZZLE
-+ help
-+ The IEI WT61P803 PUZZLE MFD HWMON Driver handles reading fan speed
-+ and writing fan PWM values. It also supports reading on-board
-+ temperature sensors.
-+
- config SENSORS_IIO_HWMON
- tristate "Hwmon driver that uses channels specified via iio maps"
- depends on IIO
---- a/drivers/hwmon/Makefile
-+++ b/drivers/hwmon/Makefile
-@@ -87,6 +87,7 @@ obj-$(CONFIG_SENSORS_HIH6130) += hih6130
- obj-$(CONFIG_SENSORS_ULTRA45) += ultra45_env.o
- obj-$(CONFIG_SENSORS_I5500) += i5500_temp.o
- obj-$(CONFIG_SENSORS_I5K_AMB) += i5k_amb.o
-+obj-$(CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON) += iei-wt61p803-puzzle-hwmon.o
- obj-$(CONFIG_SENSORS_IBMAEM) += ibmaem.o
- obj-$(CONFIG_SENSORS_IBMPEX) += ibmpex.o
- obj-$(CONFIG_SENSORS_IBMPOWERNV)+= ibmpowernv.o
---- /dev/null
-+++ b/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-@@ -0,0 +1,445 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU HWMON Driver
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/hwmon.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/math64.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/property.h>
-+#include <linux/slab.h>
-+#include <linux/thermal.h>
-+
-+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM 2
-+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL 255
-+
-+/**
-+ * struct iei_wt61p803_puzzle_thermal_cooling_device - Thermal cooling device instance
-+ * @mcu_hwmon: Parent driver struct pointer
-+ * @tcdev: Thermal cooling device pointer
-+ * @name: Thermal cooling device name
-+ * @pwm_channel: Controlled PWM channel (0 or 1)
-+ * @cooling_levels: Thermal cooling device cooling levels (DT)
-+ * @cur_level: Current cooling level
-+ * @num_levels: Number of cooling levels
-+ */
-+struct iei_wt61p803_puzzle_thermal_cooling_device {
-+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon;
-+ struct thermal_cooling_device *tcdev;
-+ char name[THERMAL_NAME_LENGTH];
-+ int pwm_channel;
-+ u32 *cooling_levels;
-+ int cur_level;
-+ u8 num_levels;
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_hwmon - MCU HWMON Driver
-+ * @mcu: MCU struct pointer
-+ * @response_buffer Global MCU response buffer
-+ * @thermal_cooling_dev_present: Per-channel thermal cooling device control indicator
-+ * @cdev: Per-channel thermal cooling device private structure
-+ */
-+struct iei_wt61p803_puzzle_hwmon {
-+ struct iei_wt61p803_puzzle *mcu;
-+ unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+ bool thermal_cooling_dev_present[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];
-+ struct iei_wt61p803_puzzle_thermal_cooling_device
-+ *cdev[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];
-+ struct mutex lock; /* mutex to protect response_buffer array */
-+};
-+
-+#define raw_temp_to_milidegree_celsius(x) (((x) - 0x80) * 1000)
-+static int iei_wt61p803_puzzle_read_temp_sensor(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+ int channel, long *value)
-+{
-+ unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+ unsigned char temp_sensor_ntc_cmd[4] = {
-+ IEI_WT61P803_PUZZLE_CMD_HEADER_START,
-+ IEI_WT61P803_PUZZLE_CMD_TEMP,
-+ IEI_WT61P803_PUZZLE_CMD_TEMP_ALL,
-+ };
-+ size_t reply_size;
-+ int ret;
-+
-+ mutex_lock(&mcu_hwmon->lock);
-+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, temp_sensor_ntc_cmd,
-+ sizeof(temp_sensor_ntc_cmd), resp_buf,
-+ &reply_size);
-+ if (ret)
-+ goto exit;
-+
-+ if (reply_size != 7) {
-+ ret = -EIO;
-+ goto exit;
-+ }
-+
-+ /* Check the number of NTC values */
-+ if (resp_buf[3] != '2') {
-+ ret = -EIO;
-+ goto exit;
-+ }
-+
-+ *value = raw_temp_to_milidegree_celsius(resp_buf[4 + channel]);
-+exit:
-+ mutex_unlock(&mcu_hwmon->lock);
-+ return ret;
-+}
-+
-+#define raw_fan_val_to_rpm(x, y) ((((x) << 8 | (y)) / 2) * 60)
-+static int iei_wt61p803_puzzle_read_fan_speed(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+ int channel, long *value)
-+{
-+ unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+ unsigned char fan_speed_cmd[4] = {};
-+ size_t reply_size;
-+ int ret;
-+
-+ fan_speed_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+ fan_speed_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+ fan_speed_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_RPM(channel);
-+
-+ mutex_lock(&mcu_hwmon->lock);
-+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, fan_speed_cmd,
-+ sizeof(fan_speed_cmd), resp_buf,
-+ &reply_size);
-+ if (ret)
-+ goto exit;
-+
-+ if (reply_size != 7) {
-+ ret = -EIO;
-+ goto exit;
-+ }
-+
-+ *value = raw_fan_val_to_rpm(resp_buf[3], resp_buf[4]);
-+exit:
-+ mutex_unlock(&mcu_hwmon->lock);
-+ return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_write_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+ int channel, long pwm_set_val)
-+{
-+ unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+ unsigned char pwm_set_cmd[6] = {};
-+ size_t reply_size;
-+ int ret;
-+
-+ pwm_set_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+ pwm_set_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+ pwm_set_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE;
-+ pwm_set_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);
-+ pwm_set_cmd[4] = pwm_set_val;
-+
-+ mutex_lock(&mcu_hwmon->lock);
-+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_set_cmd,
-+ sizeof(pwm_set_cmd), resp_buf,
-+ &reply_size);
-+ if (ret)
-+ goto exit;
-+
-+ if (reply_size != 3) {
-+ ret = -EIO;
-+ goto exit;
-+ }
-+
-+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {
-+ ret = -EIO;
-+ goto exit;
-+ }
-+exit:
-+ mutex_unlock(&mcu_hwmon->lock);
-+ return ret;
-+}
-+
-+static int iei_wt61p803_puzzle_read_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,
-+ int channel, long *value)
-+{
-+ unsigned char *resp_buf = mcu_hwmon->response_buffer;
-+ unsigned char pwm_get_cmd[5] = {};
-+ size_t reply_size;
-+ int ret;
-+
-+ pwm_get_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+ pwm_get_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;
-+ pwm_get_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ;
-+ pwm_get_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);
-+
-+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_get_cmd,
-+ sizeof(pwm_get_cmd), resp_buf,
-+ &reply_size);
-+ if (ret)
-+ return ret;
-+
-+ if (reply_size != 5)
-+ return -EIO;
-+
-+ if (resp_buf[2] != IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ)
-+ return -EIO;
-+
-+ *value = resp_buf[3];
-+
-+ return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_read(struct device *dev, enum hwmon_sensor_types type,
-+ u32 attr, int channel, long *val)
-+{
-+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);
-+
-+ switch (type) {
-+ case hwmon_pwm:
-+ return iei_wt61p803_puzzle_read_pwm_channel(mcu_hwmon, channel, val);
-+ case hwmon_fan:
-+ return iei_wt61p803_puzzle_read_fan_speed(mcu_hwmon, channel, val);
-+ case hwmon_temp:
-+ return iei_wt61p803_puzzle_read_temp_sensor(mcu_hwmon, channel, val);
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static int iei_wt61p803_puzzle_write(struct device *dev, enum hwmon_sensor_types type,
-+ u32 attr, int channel, long val)
-+{
-+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);
-+
-+ return iei_wt61p803_puzzle_write_pwm_channel(mcu_hwmon, channel, val);
-+}
-+
-+static umode_t iei_wt61p803_puzzle_is_visible(const void *data, enum hwmon_sensor_types type,
-+ u32 attr, int channel)
-+{
-+ const struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = data;
-+
-+ switch (type) {
-+ case hwmon_pwm:
-+ if (mcu_hwmon->thermal_cooling_dev_present[channel])
-+ return 0444;
-+ if (attr == hwmon_pwm_input)
-+ return 0644;
-+ break;
-+ case hwmon_fan:
-+ if (attr == hwmon_fan_input)
-+ return 0444;
-+ break;
-+ case hwmon_temp:
-+ if (attr == hwmon_temp_input)
-+ return 0444;
-+ break;
-+ default:
-+ return 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct hwmon_ops iei_wt61p803_puzzle_hwmon_ops = {
-+ .is_visible = iei_wt61p803_puzzle_is_visible,
-+ .read = iei_wt61p803_puzzle_read,
-+ .write = iei_wt61p803_puzzle_write,
-+};
-+
-+static const struct hwmon_channel_info *iei_wt61p803_puzzle_info[] = {
-+ HWMON_CHANNEL_INFO(pwm,
-+ HWMON_PWM_INPUT,
-+ HWMON_PWM_INPUT),
-+ HWMON_CHANNEL_INFO(fan,
-+ HWMON_F_INPUT,
-+ HWMON_F_INPUT,
-+ HWMON_F_INPUT,
-+ HWMON_F_INPUT,
-+ HWMON_F_INPUT),
-+ HWMON_CHANNEL_INFO(temp,
-+ HWMON_T_INPUT,
-+ HWMON_T_INPUT),
-+ NULL
-+};
-+
-+static const struct hwmon_chip_info iei_wt61p803_puzzle_chip_info = {
-+ .ops = &iei_wt61p803_puzzle_hwmon_ops,
-+ .info = iei_wt61p803_puzzle_info,
-+};
-+
-+static int iei_wt61p803_puzzle_get_max_state(struct thermal_cooling_device *tcdev,
-+ unsigned long *state)
-+{
-+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+
-+ if (!cdev)
-+ return -EINVAL;
-+
-+ *state = cdev->num_levels - 1;
-+ return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_get_cur_state(struct thermal_cooling_device *tcdev,
-+ unsigned long *state)
-+{
-+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+
-+ if (!cdev)
-+ return -EINVAL;
-+
-+ if (cdev->cur_level < 0)
-+ return -EAGAIN;
-+
-+ *state = cdev->cur_level;
-+ return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_set_cur_state(struct thermal_cooling_device *tcdev,
-+ unsigned long state)
-+{
-+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;
-+ u8 pwm_level;
-+
-+ if (!cdev)
-+ return -EINVAL;
-+
-+ if (state >= cdev->num_levels)
-+ return -EINVAL;
-+
-+ if (state == cdev->cur_level)
-+ return 0;
-+
-+ cdev->cur_level = state;
-+ pwm_level = cdev->cooling_levels[state];
-+
-+ return iei_wt61p803_puzzle_write_pwm_channel(cdev->mcu_hwmon, cdev->pwm_channel, pwm_level);
-+}
-+
-+static const struct thermal_cooling_device_ops iei_wt61p803_puzzle_cooling_ops = {
-+ .get_max_state = iei_wt61p803_puzzle_get_max_state,
-+ .get_cur_state = iei_wt61p803_puzzle_get_cur_state,
-+ .set_cur_state = iei_wt61p803_puzzle_set_cur_state,
-+};
-+
-+static int
-+iei_wt61p803_puzzle_enable_thermal_cooling_dev(struct device *dev,
-+ struct fwnode_handle *child,
-+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon)
-+{
-+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev;
-+ u32 pwm_channel;
-+ u8 num_levels;
-+ int i, ret;
-+
-+ ret = fwnode_property_read_u32(child, "reg", &pwm_channel);
-+ if (ret)
-+ return ret;
-+
-+ mcu_hwmon->thermal_cooling_dev_present[pwm_channel] = true;
-+
-+ num_levels = fwnode_property_count_u32(child, "cooling-levels");
-+ if (!num_levels)
-+ return -EINVAL;
-+
-+ cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);
-+ if (!cdev)
-+ return -ENOMEM;
-+
-+ cdev->cooling_levels = devm_kmalloc_array(dev, num_levels, sizeof(u32), GFP_KERNEL);
-+ if (!cdev->cooling_levels)
-+ return -ENOMEM;
-+
-+ ret = fwnode_property_read_u32_array(child, "cooling-levels",
-+ cdev->cooling_levels,
-+ num_levels);
-+ if (ret) {
-+ dev_err(dev, "Couldn't read property 'cooling-levels'\n");
-+ return ret;
-+ }
-+
-+ for (i = 0; i < num_levels; i++) {
-+ if (cdev->cooling_levels[i] >
-+ IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL) {
-+ dev_err(dev, "iei_wt61p803_fan state[%d]:%d > %d\n", i,
-+ cdev->cooling_levels[i],
-+ IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ cdev->mcu_hwmon = mcu_hwmon;
-+ cdev->pwm_channel = pwm_channel;
-+ cdev->num_levels = num_levels;
-+ cdev->cur_level = -1;
-+ mcu_hwmon->cdev[pwm_channel] = cdev;
-+
-+ snprintf(cdev->name, THERMAL_NAME_LENGTH, "wt61p803_puzzle_%d", pwm_channel);
-+ cdev->tcdev = devm_thermal_of_cooling_device_register(dev, to_of_node(child), cdev->name,
-+ cdev, &iei_wt61p803_puzzle_cooling_ops);
-+ if (IS_ERR(cdev->tcdev))
-+ return PTR_ERR(cdev->tcdev);
-+
-+ return 0;
-+}
-+
-+static int iei_wt61p803_puzzle_hwmon_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
-+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon;
-+ struct fwnode_handle *child;
-+ struct device *hwmon_dev;
-+ int ret;
-+
-+ mcu_hwmon = devm_kzalloc(dev, sizeof(*mcu_hwmon), GFP_KERNEL);
-+ if (!mcu_hwmon)
-+ return -ENOMEM;
-+
-+ mcu_hwmon->mcu = mcu;
-+ platform_set_drvdata(pdev, mcu_hwmon);
-+ mutex_init(&mcu_hwmon->lock);
-+
-+ hwmon_dev = devm_hwmon_device_register_with_info(dev, "iei_wt61p803_puzzle",
-+ mcu_hwmon,
-+ &iei_wt61p803_puzzle_chip_info,
-+ NULL);
-+ if (IS_ERR(hwmon_dev))
-+ return PTR_ERR(hwmon_dev);
-+
-+ /* Control fans via PWM lines via Linux Kernel */
-+ if (IS_ENABLED(CONFIG_THERMAL)) {
-+ device_for_each_child_node(dev, child) {
-+ ret = iei_wt61p803_puzzle_enable_thermal_cooling_dev(dev, child, mcu_hwmon);
-+ if (ret) {
-+ dev_err(dev, "Enabling the PWM fan failed\n");
-+ fwnode_handle_put(child);
-+ return ret;
-+ }
-+ }
-+ }
-+ return 0;
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_hwmon_id_table[] = {
-+ { .compatible = "iei,wt61p803-puzzle-hwmon" },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_hwmon_id_table);
-+
-+static struct platform_driver iei_wt61p803_puzzle_hwmon_driver = {
-+ .driver = {
-+ .name = "iei-wt61p803-puzzle-hwmon",
-+ .of_match_table = iei_wt61p803_puzzle_hwmon_id_table,
-+ },
-+ .probe = iei_wt61p803_puzzle_hwmon_probe,
-+};
-+
-+module_platform_driver(iei_wt61p803_puzzle_hwmon_driver);
-+
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU HWMON Driver");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From f3b44eb69cc561cf05d00506dcec0dd9be003ed8 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:35 +0000
-Subject: [PATCH 4/7] drivers: leds: Add the IEI WT61P803 PUZZLE LED driver
-
-Add support for the IEI WT61P803 PUZZLE LED driver.
-Currently only the front panel power LED is supported,
-since it is the only LED on this board wired through the
-MCU.
-
-The LED is wired directly to the on-board MCU controller
-and is toggled using an MCU command.
-
-Support for more LEDs is going to be added in case more
-boards implement this microcontroller, as LEDs use many
-different GPIOs.
-
-This driver depends on the IEI WT61P803 PUZZLE MFD driver.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- drivers/leds/Kconfig | 8 ++
- drivers/leds/Makefile | 1 +
- drivers/leds/leds-iei-wt61p803-puzzle.c | 147 ++++++++++++++++++++++++
- 3 files changed, 156 insertions(+)
- create mode 100644 drivers/leds/leds-iei-wt61p803-puzzle.c
-
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -300,6 +300,14 @@ config LEDS_IPAQ_MICRO
- Choose this option if you want to use the notification LED on
- Compaq/HP iPAQ h3100 and h3600.
-
-+config LEDS_IEI_WT61P803_PUZZLE
-+ tristate "LED Support for the IEI WT61P803 PUZZLE MCU"
-+ depends on LEDS_CLASS
-+ depends on MFD_IEI_WT61P803_PUZZLE
-+ help
-+ This option enables support for LEDs controlled by the IEI WT61P803
-+ M801 MCU.
-+
- config LEDS_HP6XX
- tristate "LED Support for the HP Jornada 6xx"
- depends on LEDS_CLASS
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -32,6 +32,7 @@ obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.
- obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
- obj-$(CONFIG_LEDS_IP30) += leds-ip30.o
- obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o
-+obj-$(CONFIG_LEDS_IEI_WT61P803_PUZZLE) += leds-iei-wt61p803-puzzle.o
- obj-$(CONFIG_LEDS_IS31FL319X) += leds-is31fl319x.o
- obj-$(CONFIG_LEDS_IS31FL32XX) += leds-is31fl32xx.o
- obj-$(CONFIG_LEDS_LM3530) += leds-lm3530.o
---- /dev/null
-+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c
-@@ -0,0 +1,147 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* IEI WT61P803 PUZZLE MCU LED Driver
-+ *
-+ * Copyright (C) 2020 Sartura Ltd.
-+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+ */
-+
-+#include <linux/leds.h>
-+#include <linux/mfd/iei-wt61p803-puzzle.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/property.h>
-+#include <linux/slab.h>
-+
-+enum iei_wt61p803_puzzle_led_state {
-+ IEI_LED_OFF = 0x30,
-+ IEI_LED_ON = 0x31,
-+ IEI_LED_BLINK_5HZ = 0x32,
-+ IEI_LED_BLINK_1HZ = 0x33,
-+};
-+
-+/**
-+ * struct iei_wt61p803_puzzle_led - MCU LED Driver
-+ * @cdev: LED classdev
-+ * @mcu: MCU struct pointer
-+ * @response_buffer Global MCU response buffer
-+ * @lock: General mutex lock to protect simultaneous R/W access to led_power_state
-+ * @led_power_state: State of the front panel power LED
-+ */
-+struct iei_wt61p803_puzzle_led {
-+ struct led_classdev cdev;
-+ struct iei_wt61p803_puzzle *mcu;
-+ unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+ struct mutex lock; /* mutex to protect led_power_state */
-+ int led_power_state;
-+};
-+
-+static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led
-+ (struct led_classdev *led_cdev)
-+{
-+ return container_of(led_cdev, struct iei_wt61p803_puzzle_led, cdev);
-+}
-+
-+static int iei_wt61p803_puzzle_led_brightness_set_blocking(struct led_classdev *cdev,
-+ enum led_brightness brightness)
-+{
-+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+ unsigned char *resp_buf = priv->response_buffer;
-+ unsigned char led_power_cmd[5] = {};
-+ size_t reply_size;
-+ int ret;
-+
-+ led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+ led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
-+ led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;
-+ led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;
-+
-+ ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,
-+ sizeof(led_power_cmd),
-+ resp_buf,
-+ &reply_size);
-+ if (ret)
-+ return ret;
-+
-+ if (reply_size != 3)
-+ return -EIO;
-+
-+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK))
-+ return -EIO;
-+
-+ mutex_lock(&priv->lock);
-+ priv->led_power_state = brightness;
-+ mutex_unlock(&priv->lock);
-+
-+ return 0;
-+}
-+
-+static enum led_brightness iei_wt61p803_puzzle_led_brightness_get(struct led_classdev *cdev)
-+{
-+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+ int led_state;
-+
-+ mutex_lock(&priv->lock);
-+ led_state = priv->led_power_state;
-+ mutex_unlock(&priv->lock);
-+
-+ return led_state;
-+}
-+
-+static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
-+ struct iei_wt61p803_puzzle_led *priv;
-+ struct led_init_data init_data = {};
-+ struct fwnode_handle *child;
-+ int ret;
-+
-+ if (device_get_child_node_count(dev) != 1)
-+ return -EINVAL;
-+
-+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->mcu = mcu;
-+ priv->led_power_state = 1;
-+ mutex_init(&priv->lock);
-+ dev_set_drvdata(dev, priv);
-+
-+ child = device_get_next_child_node(dev, NULL);
-+ init_data.fwnode = child;
-+
-+ priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
-+ priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
-+ priv->cdev.max_brightness = 1;
-+
-+ ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
-+ if (ret)
-+ dev_err(dev, "Could not register LED\n");
-+
-+ fwnode_handle_put(child);
-+ return ret;
-+}
-+
-+static const struct of_device_id iei_wt61p803_puzzle_led_of_match[] = {
-+ { .compatible = "iei,wt61p803-puzzle-leds" },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_led_of_match);
-+
-+static struct platform_driver iei_wt61p803_puzzle_led_driver = {
-+ .driver = {
-+ .name = "iei-wt61p803-puzzle-led",
-+ .of_match_table = iei_wt61p803_puzzle_led_of_match,
-+ },
-+ .probe = iei_wt61p803_puzzle_led_probe,
-+};
-+module_platform_driver(iei_wt61p803_puzzle_led_driver);
-+
-+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE front panel LED driver");
-+MODULE_AUTHOR("Luka Kovacic <luka.kovacic@sartura.hr>");
-+MODULE_LICENSE("GPL v2");
-+MODULE_ALIAS("platform:leds-iei-wt61p803-puzzle");
+++ /dev/null
-From 2fab3b4956c5b2f83c1e1abffc1df39de2933d83 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:36 +0000
-Subject: [PATCH 5/7] Documentation/ABI: Add iei-wt61p803-puzzle driver sysfs
- interface documentation
-
-Add the iei-wt61p803-puzzle driver sysfs interface documentation to allow
-monitoring and control of the microcontroller from user space.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../testing/sysfs-driver-iei-wt61p803-puzzle | 61 +++++++++++++++++++
- 1 file changed, 61 insertions(+)
- create mode 100644 Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle
-
---- /dev/null
-+++ b/Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle
-@@ -0,0 +1,61 @@
-+What: /sys/bus/serial/devices/.../mac_address_*
-+Date: September 2020
-+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
-+Description: (RW) Internal factory assigned MAC address values
-+
-+What: /sys/bus/serial/devices/.../serial_number
-+Date: September 2020
-+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
-+Description: (RW) Internal factory assigned serial number
-+
-+What: /sys/bus/serial/devices/.../version
-+Date: September 2020
-+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
-+Description: (RO) Internal MCU firmware version
-+
-+What: /sys/bus/serial/devices/.../protocol_version
-+Date: September 2020
-+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
-+Description: (RO) Internal MCU communication protocol version
-+
-+What: /sys/bus/serial/devices/.../power_loss_recovery
-+Date: September 2020
-+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
-+Description: (RW) Host platform power loss recovery settings
-+ Value mapping: 0 - Always-On, 1 - Always-Off, 2 - Always-AC, 3 - Always-WA
-+
-+What: /sys/bus/serial/devices/.../bootloader_mode
-+Date: September 2020
-+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
-+Description: (RO) Internal MCU bootloader mode status
-+ Value mapping:
-+ 0 - normal mode
-+ 1 - bootloader mode
-+
-+What: /sys/bus/serial/devices/.../power_status
-+Date: September 2020
-+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
-+Description: (RO) Power status indicates the host platform power on method.
-+ Value mapping (bitwise list):
-+ 0x80 - Null
-+ 0x40 - Firmware flag
-+ 0x20 - Power loss detection flag (powered off)
-+ 0x10 - Power loss detection flag (AC mode)
-+ 0x08 - Button power on
-+ 0x04 - Wake-on-LAN power on
-+ 0x02 - RTC alarm power on
-+ 0x01 - AC recover power on
-+
-+What: /sys/bus/serial/devices/.../build_info
-+Date: September 2020
-+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
-+Description: (RO) Internal MCU firmware build date
-+ Format: yyyy/mm/dd hh:mm
-+
-+What: /sys/bus/serial/devices/.../ac_recovery_status
-+Date: September 2020
-+Contact: Luka Kovacic <luka.kovacic@sartura.hr>
-+Description: (RO) Host platform AC recovery status value
-+ Value mapping:
-+ 0 - board has not been recovered from power down
-+ 1 - board has been recovered from power down
+++ /dev/null
-From 0aff3e5923fecc6842473ad07a688d6e2f2c2d55 Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:37 +0000
-Subject: [PATCH 6/7] Documentation/hwmon: Add iei-wt61p803-puzzle hwmon driver
- documentation
-
-Add the iei-wt61p803-puzzle driver hwmon driver interface documentation.
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- .../hwmon/iei-wt61p803-puzzle-hwmon.rst | 43 +++++++++++++++++++
- Documentation/hwmon/index.rst | 1 +
- 2 files changed, 44 insertions(+)
- create mode 100644 Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-
---- /dev/null
-+++ b/Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-@@ -0,0 +1,43 @@
-+.. SPDX-License-Identifier: GPL-2.0-only
-+
-+Kernel driver iei-wt61p803-puzzle-hwmon
-+=======================================
-+
-+Supported chips:
-+ * IEI WT61P803 PUZZLE for IEI Puzzle M801
-+
-+ Prefix: 'iei-wt61p803-puzzle-hwmon'
-+
-+Author: Luka Kovacic <luka.kovacic@sartura.hr>
-+
-+
-+Description
-+-----------
-+
-+This driver adds fan and temperature sensor reading for some IEI Puzzle
-+series boards.
-+
-+Sysfs attributes
-+----------------
-+
-+The following attributes are supported:
-+
-+- IEI WT61P803 PUZZLE for IEI Puzzle M801
-+
-+/sys files in hwmon subsystem
-+-----------------------------
-+
-+================= == =====================================================
-+fan[1-5]_input RO files for fan speed (in RPM)
-+pwm[1-2] RW files for fan[1-2] target duty cycle (0..255)
-+temp[1-2]_input RO files for temperature sensors, in millidegree Celsius
-+================= == =====================================================
-+
-+/sys files in thermal subsystem
-+-------------------------------
-+
-+================= == =====================================================
-+cur_state RW file for current cooling state of the cooling device
-+ (0..max_state)
-+max_state RO file for maximum cooling state of the cooling device
-+================= == =====================================================
---- a/Documentation/hwmon/index.rst
-+++ b/Documentation/hwmon/index.rst
-@@ -77,6 +77,7 @@ Hardware Monitoring Kernel Drivers
- ibmaem
- ibm-cffps
- ibmpowernv
-+ iei-wt61p803-puzzle-hwmon
- ina209
- ina2xx
- ina238
+++ /dev/null
-From 12479baad28d2a08c6cb9e83471057635fa1635c Mon Sep 17 00:00:00 2001
-From: Luka Kovacic <luka.kovacic () sartura ! hr>
-Date: Tue, 24 Aug 2021 12:44:38 +0000
-Subject: [PATCH 7/7] MAINTAINERS: Add an entry for the IEI WT61P803 PUZZLE
- driver
-
-Add an entry for the IEI WT61P803 PUZZLE driver (MFD, HWMON, LED drivers).
-
-Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
-Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
-Cc: Luka Perkov <luka.perkov@sartura.hr>
-Cc: Robert Marko <robert.marko@sartura.hr>
----
- MAINTAINERS | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -9900,6 +9900,22 @@ F: include/net/nl802154.h
- F: net/ieee802154/
- F: net/mac802154/
-
-+IEI WT61P803 M801 MFD DRIVER
-+M: Luka Kovacic <luka.kovacic@sartura.hr>
-+M: Luka Perkov <luka.perkov@sartura.hr>
-+M: Goran Medic <goran.medic@sartura.hr>
-+L: linux-kernel@vger.kernel.org
-+S: Maintained
-+F: Documentation/ABI/stable/sysfs-driver-iei-wt61p803-puzzle
-+F: Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml
-+F: Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml
-+F: Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml
-+F: Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst
-+F: drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
-+F: drivers/leds/leds-iei-wt61p803-puzzle.c
-+F: drivers/mfd/iei-wt61p803-puzzle.c
-+F: include/linux/mfd/iei-wt61p803-puzzle.h
-+
- IFE PROTOCOL
- M: Yotam Gigi <yotam.gi@gmail.com>
- M: Jamal Hadi Salim <jhs@mojatatu.com>
+++ /dev/null
---- a/drivers/leds/leds-iei-wt61p803-puzzle.c
-+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c
-@@ -9,9 +9,13 @@
- #include <linux/mfd/iei-wt61p803-puzzle.h>
- #include <linux/mod_devicetable.h>
- #include <linux/module.h>
-+#include <linux/of.h>
- #include <linux/platform_device.h>
- #include <linux/property.h>
- #include <linux/slab.h>
-+#include <linux/workqueue.h>
-+
-+#define IEI_LEDS_MAX 4
-
- enum iei_wt61p803_puzzle_led_state {
- IEI_LED_OFF = 0x30,
-@@ -33,7 +37,11 @@ struct iei_wt61p803_puzzle_led {
- struct iei_wt61p803_puzzle *mcu;
- unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];
- struct mutex lock; /* mutex to protect led_power_state */
-+ struct work_struct work;
- int led_power_state;
-+ int id;
-+ u8 blinking;
-+ bool active_low;
- };
-
- static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led
-@@ -51,10 +59,18 @@ static int iei_wt61p803_puzzle_led_brigh
- size_t reply_size;
- int ret;
-
-+ if (priv->blinking) {
-+ if (brightness == LED_OFF)
-+ priv->blinking = 0;
-+ else
-+ return 0;
-+ }
-+
- led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
- led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
-- led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;
-- led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;
-+ led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);
-+ led_power_cmd[3] = ((brightness == LED_OFF) ^ priv->active_low) ?
-+ IEI_LED_OFF : priv->blinking?priv->blinking:IEI_LED_ON;
-
- ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,
- sizeof(led_power_cmd),
-@@ -90,39 +106,166 @@ static enum led_brightness iei_wt61p803_
- return led_state;
- }
-
-+static void iei_wt61p803_puzzle_led_apply_blink(struct work_struct *work)
-+{
-+ struct iei_wt61p803_puzzle_led *priv = container_of(work, struct iei_wt61p803_puzzle_led, work);
-+ unsigned char led_blink_cmd[5] = {};
-+ unsigned char resp_buf[IEI_WT61P803_PUZZLE_BUF_SIZE];
-+ size_t reply_size;
-+
-+ led_blink_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;
-+ led_blink_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;
-+ led_blink_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);
-+ led_blink_cmd[3] = priv->blinking;
-+
-+ iei_wt61p803_puzzle_write_command(priv->mcu, led_blink_cmd,
-+ sizeof(led_blink_cmd),
-+ resp_buf,
-+ &reply_size);
-+
-+ return;
-+}
-+
-+static int iei_wt61p803_puzzle_led_set_blink(struct led_classdev *cdev,
-+ unsigned long *delay_on,
-+ unsigned long *delay_off)
-+{
-+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);
-+ u8 blink_mode = 0;
-+ int ret = 0;
-+
-+ /* set defaults */
-+ if (!*delay_on && !*delay_off) {
-+ *delay_on = 500;
-+ *delay_off = 500;
-+ }
-+
-+ /* minimum delay for soft-driven blinking is 100ms to keep load low */
-+ if (*delay_on < 100)
-+ *delay_on = 100;
-+
-+ if (*delay_off < 100)
-+ *delay_off = 100;
-+
-+ /* offload blinking to hardware, if possible */
-+ if (*delay_on != *delay_off) {
-+ ret = -EINVAL;
-+ } else if (*delay_on == 100) {
-+ blink_mode = IEI_LED_BLINK_5HZ;
-+ *delay_on = 100;
-+ *delay_off = 100;
-+ } else if (*delay_on <= 500) {
-+ blink_mode = IEI_LED_BLINK_1HZ;
-+ *delay_on = 500;
-+ *delay_off = 500;
-+ } else {
-+ ret = -EINVAL;
-+ }
-+
-+ mutex_lock(&priv->lock);
-+ priv->blinking = blink_mode;
-+ mutex_unlock(&priv->lock);
-+
-+ if (blink_mode)
-+ schedule_work(&priv->work);
-+
-+ return ret;
-+}
-+
-+
-+static int iei_wt61p803_puzzle_led_set_dt_default(struct led_classdev *cdev,
-+ struct device_node *np)
-+{
-+ const char *state;
-+ int ret = 0;
-+
-+ state = of_get_property(np, "default-state", NULL);
-+ if (state) {
-+ if (!strcmp(state, "on")) {
-+ ret =
-+ iei_wt61p803_puzzle_led_brightness_set_blocking(
-+ cdev, cdev->max_brightness);
-+ } else {
-+ ret = iei_wt61p803_puzzle_led_brightness_set_blocking(
-+ cdev, LED_OFF);
-+ }
-+ }
-+
-+ return ret;
-+}
-+
- static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
-+ struct device_node *np = dev_of_node(dev);
-+ struct device_node *child;
- struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);
- struct iei_wt61p803_puzzle_led *priv;
-- struct led_init_data init_data = {};
-- struct fwnode_handle *child;
- int ret;
-+ u32 reg;
-
-- if (device_get_child_node_count(dev) != 1)
-+ if (device_get_child_node_count(dev) > IEI_LEDS_MAX)
- return -EINVAL;
-
-- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-- if (!priv)
-- return -ENOMEM;
--
-- priv->mcu = mcu;
-- priv->led_power_state = 1;
-- mutex_init(&priv->lock);
-- dev_set_drvdata(dev, priv);
--
-- child = device_get_next_child_node(dev, NULL);
-- init_data.fwnode = child;
--
-- priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
-- priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
-- priv->cdev.max_brightness = 1;
-+ for_each_available_child_of_node(np, child) {
-+ struct led_init_data init_data = {};
-
-- ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
-- if (ret)
-- dev_err(dev, "Could not register LED\n");
-+ ret = of_property_read_u32(child, "reg", ®);
-+ if (ret) {
-+ dev_err(dev, "Failed to read led 'reg' property\n");
-+ goto put_child_node;
-+ }
-+
-+ if (reg > IEI_LEDS_MAX) {
-+ dev_err(dev, "Invalid led reg %u\n", reg);
-+ ret = -EINVAL;
-+ goto put_child_node;
-+ }
-+
-+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv) {
-+ ret = -ENOMEM;
-+ goto put_child_node;
-+ }
-+
-+ mutex_init(&priv->lock);
-+
-+ dev_set_drvdata(dev, priv);
-+
-+ if (of_property_read_bool(child, "active-low"))
-+ priv->active_low = true;
-+
-+ priv->mcu = mcu;
-+ priv->id = reg;
-+ priv->led_power_state = 1;
-+ priv->blinking = 0;
-+ init_data.fwnode = of_fwnode_handle(child);
-+
-+ priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;
-+ priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;
-+ priv->cdev.blink_set = iei_wt61p803_puzzle_led_set_blink;
-+
-+ priv->cdev.max_brightness = 1;
-+
-+ INIT_WORK(&priv->work, iei_wt61p803_puzzle_led_apply_blink);
-+
-+ ret = iei_wt61p803_puzzle_led_set_dt_default(&priv->cdev, child);
-+ if (ret) {
-+ dev_err(dev, "Could apply default from DT\n");
-+ goto put_child_node;
-+ }
-+
-+ ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);
-+ if (ret) {
-+ dev_err(dev, "Could not register LED\n");
-+ goto put_child_node;
-+ }
-+ }
-+
-+ return ret;
-
-- fwnode_handle_put(child);
-+put_child_node:
-+ of_node_put(child);
- return ret;
- }
-
---- a/include/linux/mfd/iei-wt61p803-puzzle.h
-+++ b/include/linux/mfd/iei-wt61p803-puzzle.h
-@@ -36,7 +36,7 @@
- #define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */
-
- #define IEI_WT61P803_PUZZLE_CMD_LED 0x52 /* R */
--#define IEI_WT61P803_PUZZLE_CMD_LED_POWER 0x31 /* 1 */
-+#define IEI_WT61P803_PUZZLE_CMD_LED_SET(n) (0x30 | (n))
-
- #define IEI_WT61P803_PUZZLE_CMD_TEMP 0x54 /* T */
- #define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL 0x41 /* A */
---- a/drivers/mfd/iei-wt61p803-puzzle.c
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -176,6 +176,9 @@ static int iei_wt61p803_puzzle_recv_buf(
- struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev);
- int ret;
-
-+ print_hex_dump_debug("puzzle-mcu rx: ", DUMP_PREFIX_NONE,
-+ 16, 1, data, size, false);
-+
- ret = iei_wt61p803_puzzle_process_resp(mcu, data, size);
- /* Return the number of processed bytes if function returns error,
- * discard the remaining incoming data, since the frame this data
-@@ -246,6 +249,9 @@ int iei_wt61p803_puzzle_write_command(st
-
- cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1);
-
-+ print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE,
-+ 16, 1, cmd, size, false);
-+
- /* Initialize reply struct */
- reinit_completion(&mcu->reply->received);
- mcu->reply->size = 0;
+++ /dev/null
---- a/drivers/mfd/iei-wt61p803-puzzle.c
-+++ b/drivers/mfd/iei-wt61p803-puzzle.c
-@@ -241,6 +241,7 @@ int iei_wt61p803_puzzle_write_command(st
- {
- struct device *dev = &mcu->serdev->dev;
- int ret;
-+ int retries;
-
- if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH)
- return -EINVAL;
-@@ -252,24 +253,36 @@ int iei_wt61p803_puzzle_write_command(st
- print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE,
- 16, 1, cmd, size, false);
-
-+ retries = 3;
- /* Initialize reply struct */
-- reinit_completion(&mcu->reply->received);
-- mcu->reply->size = 0;
-- usleep_range(2000, 10000);
-- serdev_device_write_flush(mcu->serdev);
-- ret = serdev_device_write_buf(mcu->serdev, cmd, size);
-- if (ret < 0)
-- goto exit;
--
-- serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-- ret = wait_for_completion_timeout(&mcu->reply->received,
-- IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-- if (ret == 0) {
-- dev_err(dev, "Command reply receive timeout\n");
-- ret = -ETIMEDOUT;
-- goto exit;
-+ while (retries) {
-+ reinit_completion(&mcu->reply->received);
-+ mcu->reply->size = 0;
-+ usleep_range(2000, 10000);
-+ serdev_device_write_flush(mcu->serdev);
-+ ret = serdev_device_write_buf(mcu->serdev, cmd, size);
-+ if (ret < 0)
-+ goto exit;
-+
-+ serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+ ret = wait_for_completion_timeout(&mcu->reply->received,
-+ IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);
-+ retries--;
-+ if (ret == 0) {
-+ if (retries == 0) {
-+ dev_err(dev, "Command reply receive timeout\n");
-+ ret = -ETIMEDOUT;
-+ goto exit;
-+ }
-+ }
-+ else {
-+ if (mcu->reply->data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&
-+ mcu->reply->data[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&
-+ mcu->reply->data[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK) {
-+ break;
-+ }
-+ }
- }
--
- *reply_size = mcu->reply->size;
- /* Copy the received data, as it will not be available after a new frame is received */
- memcpy(reply_data, mcu->reply->data, mcu->reply->size);
static int kernel_init(void *);
/*
-@@ -928,6 +932,18 @@ void start_kernel(void)
+@@ -930,6 +934,18 @@ void start_kernel(void)
boot_cpu_hotplug_init();
pr_notice("Kernel command line: %s\n", saved_command_line);
CPU_TYPE:=arm926ej-s
SUBTARGETS:=generic
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
KERNELNAME:=zImage dtbs
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_FORCE_MAX_ORDER=11
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_CPU_AUTO=y
-# CONFIG_ARCH_MULTI_V4 is not set
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_MXS=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_PM=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_COREDUMP=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRC16=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEV_MXS_DCP=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_FEC=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-# CONFIG_GIANFAR is not set
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MXS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCA=y
-CONFIG_I2C_ALGOPCF=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PINCTRL=y
-CONFIG_I2C_MXS=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_SYSFS_TRIGGER=y
-CONFIG_IIO_TRIGGER=y
-# CONFIG_IIO_TRIGGERED_BUFFER is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MXS=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-CONFIG_JBD2=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_MXS_LRADC=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MXS=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MXS_DMA=y
-# CONFIG_MXS_LRADC_ADC is not set
-CONFIG_MXS_TIMER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_MXS_OCOTP=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX23=y
-CONFIG_PINCTRL_IMX28=y
-CONFIG_PINCTRL_MXS=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RATIONAL=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_STMP=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MXS_AUART=y
-CONFIG_SERIAL_MXS_AUART_CONSOLE=y
-CONFIG_SMSC_PHY=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_IMX23=y
-CONFIG_SOC_IMX28=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MXS=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_STMP3XXX_RTC_WATCHDOG=y
-CONFIG_STMP_DEVICE=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-# CONFIG_UNUSED_BOARD_FILES is not set
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_IMX=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_MXS_PHY=y
-CONFIG_USB_OTG=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_CPU_AUTO=y
+# CONFIG_ARCH_MULTI_V4 is not set
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V4_V5=y
+CONFIG_ARCH_MULTI_V5=y
+CONFIG_ARCH_MXS=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_PM=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COREDUMP=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_ARM926T=y
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CRC16=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEV_MXS_DCP=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_FEC=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+# CONFIG_GIANFAR is not set
+CONFIG_GLOB=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MXS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_ALGOPCA=y
+CONFIG_I2C_ALGOPCF=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PINCTRL=y
+CONFIG_I2C_MXS=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_SYSFS_TRIGGER=y
+CONFIG_IIO_TRIGGER=y
+# CONFIG_IIO_TRIGGERED_BUFFER is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MXS=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_MXS_LRADC=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_MXS=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MXS_DMA=y
+# CONFIG_MXS_LRADC_ADC is not set
+CONFIG_MXS_TIMER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_MXS_OCOTP=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX23=y
+CONFIG_PINCTRL_IMX28=y
+CONFIG_PINCTRL_MXS=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RATIONAL=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_STMP=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_MXS_AUART=y
+CONFIG_SERIAL_MXS_AUART_CONSOLE=y
+CONFIG_SMSC_PHY=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_IMX23=y
+CONFIG_SOC_IMX28=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MXS=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_STMP3XXX_RTC_WATCHDOG=y
+CONFIG_STMP_DEVICE=y
+CONFIG_SWPHY=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_IMX=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_OTG=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USE_OF=y
+# CONFIG_VFP is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
KERNEL_NAME := zImage
KERNEL := kernel-bin | uImage none
IMAGES := sdcard.img.gz
+ DTS_DIR := $(DTS_DIR)/nxp/mxs
DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
endef
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
-@@ -25,6 +25,7 @@
+@@ -26,6 +26,7 @@
#include <linux/ktime.h>
#include <linux/mm.h>
#include <linux/nvme.h>
#include <linux/platform_data/x86/apple.h>
#include <linux/pm_runtime.h>
#include <linux/suspend.h>
-@@ -5900,3 +5901,34 @@ static void nvidia_ion_ahci_fixup(struct
- pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
- }
- DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
+@@ -6000,3 +6001,34 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size);
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size);
+ #endif
+
+#ifdef CONFIG_PCI_HOST_THUNDER_PEM
+/*
+++ /dev/null
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=oxnas
-BOARDNAME:=PLXTECH/Oxford NAS782x/OX8xx
-SUBTARGETS:=ox810se ox820
-FEATURES:=gpio ramdisk rtc squashfs
-DEVICE_TYPE:=nas
-
-KERNEL_PATCHVER:=5.15
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES += \
- kmod-button-hotplug kmod-input-gpio-keys-polled \
- kmod-leds-gpio uboot-envtools
-
-KERNELNAME:=zImage dtbs
-
-$(eval $(call BuildTarget))
+++ /dev/null
-
-. /lib/functions/uci-defaults.sh
-. /lib/functions/system.sh
-
-bootloader_cmdline_var() {
- local param
- local pval
- for arg in $(cat /proc/device-tree/chosen/bootloader-args); do
- param="$(echo $arg | cut -d'=' -f 1)"
- pval="$(echo $arg | cut -d'=' -f 2-)"
-
- if [ "$param" = "$1" ]; then
- echo "$pval"
- fi
- done
-}
-
-legacy_boot_mac_adr() {
- local macstr
- local oIFS
- macstr="$(bootloader_cmdline_var mac_adr)"
- oIFS="$IFS"
- IFS=","
- set -- $macstr
- printf "%02x:%02x:%02x:%02x:%02x:%02x" $1 $2 $3 $4 $5 $6
- IFS="$oIFS"
-}
-
-oxnas_setup_interfaces()
-{
- local board="$1"
-
- case $board in
- *)
- ucidef_set_interface_lan "eth0" "dhcp"
- ;;
- esac
-}
-
-oxnas_setup_macs()
-{
- local board="$1"
- local lan_mac=""
-
- case $board in
- shuttle,kd20)
- lan_mac="$(legacy_boot_mac_adr)"
- ;;
- esac
-
- [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
-}
-
-board_config_update
-board=$(board_name)
-oxnas_setup_interfaces $board
-oxnas_setup_macs $board
-board_config_flush
-
-exit 0
+++ /dev/null
-#!/bin/sh /etc/rc.common
-
-START=99
-
-get_irq() {
- local name="$1"
- grep -m 1 "$name" /proc/interrupts | cut -d: -f1 | sed 's, *,,'
-}
-
-set_irq_affinity() {
- local name="$1"
- local val="$2"
- local irq="$(get_irq "$name")"
- [ -n "$irq" ] || return
- echo "$val" > "/proc/irq/$irq/smp_affinity"
-}
-
-start() {
- set_irq_affinity ehci_hcd 2
- set_irq_affinity xhci_hcd 2
- set_irq_affinity sata 2
-}
+++ /dev/null
-REQUIRE_IMAGE_METADATA=1
-
-platform_check_image() {
- return 0
-}
-
-platform_do_upgrade() {
- nand_do_upgrade $1
-}
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_CPU_AUTO=y
-# CONFIG_ARCH_MULTI_V4 is not set
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OXNAS=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEBUG_FS=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_BLK_PM=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=64
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_OXNAS=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZ4=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_DWMAC_OXNAS=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ELF_CORE=y
-CONFIG_FAT_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FREEZER=y
-CONFIG_FWNODE_MDIO=y
-# CONFIG_FW_CACHE is not set
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HWMON=y
-CONFIG_HZ_FIXED=0
-CONFIG_ICPLUS_PHY=y
-CONFIG_INET_DIAG=y
-# CONFIG_INET_DIAG_DESTROY is not set
-# CONFIG_INET_RAW_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_KALLSYMS=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LZ4_COMPRESS=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_OX810SE is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OXNAS_RPS_TIMER=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-CONFIG_PCS_XPCS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_OXNAS=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_OXNAS=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_OXNAS=y
-CONFIG_PPS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_TRACE=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_OXNAS=y
-CONFIG_SCHED_DEBUG=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SOCK_DIAG=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VERSATILE_FPGA_IRQ=y
-CONFIG_VERSATILE_FPGA_IRQ_NR=4
-CONFIG_VFAT_FS=y
-# CONFIG_VFP is not set
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_WATCHDOG is not set
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_INFLATE=y
+++ /dev/null
-/dts-v1/;
-
-#include "ox820.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Akitio MyCloud";
-
- compatible = "akitio,mycloud", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 128Mbytes DDR */
- reg = <0x60000000 0x8000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- };
-
- i2c-gpio {
- compatible = "i2c-gpio";
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
- &gpio1 10 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c>;
- i2c-gpio,delay-us = <10>;
- #address-cells = <1>;
- #size-cells = <0>;
- ds1307: rtc@68 {
- compatible = "dallas,ds1307";
- reg = <0x68>;
- };
- };
-
- keys {
- compatible = "gpio-keys-polled";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_buttons>;
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
- power {
- label = "power";
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- };
- reset {
- label = "reset";
- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds>;
- led_status: status {
- label = "akitio:red:status";
- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio-poweroff {
- compatible = "gpio-poweroff";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_poweroff>;
- gpios = <&gpio1 13 GPIO_SINGLE_ENDED>;
- };
-};
-
-&pinctrl {
- pinctrl_i2c: i2c-0 {
- i2c {
- pins = "gpio41", "gpio42"; /* MF_B9, MF_B10 */
- function = "gpio";
- /* ToDo: find a way to set debounce for those pins */
- };
- };
- pinctrl_buttons: buttons-0 {
- buttons {
- pins = "gpio11", "gpio38"; /* MF_A11, MF_B6 GPIO */
- function = "gpio";
- };
- };
- pinctrl_leds: leds-0 {
- leds {
- pins = "gpio29"; /* MF_A29 GPIO */
- function = "gpio";
- };
- };
- pinctrl_poweroff: poweroff-0 {
- poweroff {
- pins = "gpio45"; /* MF_B13 GPIO */
- function = "gpio";
- };
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "boot";
- reg = <0x0 0x26c0000>;
- };
-
- partition@26c0000 {
- label = "ubi";
- reg = <0x26c0000 0xd940000>;
- };
- };
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&ehci {
- status = "okay";
-};
-
-&sata {
- status = "okay";
- nr-ports = <2>;
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
+++ /dev/null
-/*
- * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
- *
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- *
- * Licensed under GPLv2 or later
- */
-
-/dts-v1/;
-#include "ox820.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Cloud Engines PogoPlug Pro";
-
- compatible = "cloudengines,pogoplugpro", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 128Mbytes DDR */
- reg = <0x60000000 0x8000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_warn;
- led-running = &led_act;
- led-upgrade = &led_warn;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status: blue {
- label = "pogoplug:blue";
- gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- led_warn: orange {
- label = "pogoplug:orange";
- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- led_act: green {
- label = "pogoplug:green";
- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "stage1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "u-boot";
- reg = <0x00040000 0x00380000>;
- read-only;
- };
-
- partition@3c0000 {
- label = "u-boot-env";
- reg = <0x003c0000 0x00080000>;
- };
-
- partition@440000 {
- label = "kernel";
- reg = <0x00440000 0x009c0000>;
- };
-
- partition@e00000 {
- label = "ubi";
- reg = <0x00e00000 0x07200000>;
- };
- };
-};
-
-&ehci {
- status = "okay";
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&sata {
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
+++ /dev/null
-/dts-v1/;
-
-#include "ox820.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "MitraStar Technology Corp. STG-212";
-
- compatible = "mitrastar,stg-212", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 128Mbytes DDR */
- reg = <0x60000000 0x8000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_warn;
- led-running = &led_status;
- led-upgrade = &led_warn;
- };
-
- keys {
- compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
-
- reset {
- label = "reset";
- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- copy {
- label = "copy";
- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_COPY>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led_status: status {
- label = "zyxel:blue:status";
- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- };
- led_warn: status2 {
- label = "zyxel:red:status";
- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
- };
- copy {
- label = "zyxel:orange:copy";
- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
- trigger-sources = <&ehci_port1>, <&ehci_port2>;
- linux,default-trigger = "usbport";
- };
- };
-
- i2c-gpio {
- compatible = "i2c-gpio";
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
- &gpio1 10 GPIO_ACTIVE_HIGH>;
- i2c-gpio,delay-us = <10>;
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "stage1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "u-boot";
- reg = <0x00040000 0x00380000>;
- read-only;
- };
-
- partition@3c0000 {
- label = "u-boot-env";
- reg = <0x003c0000 0x00080000>;
- };
-
- partition@440000 {
- label = "kernel";
- reg = <0x00440000 0x009c0000>;
- };
-
- partition@e00000 {
- label = "ubi";
- reg = <0x00e00000 0x07200000>;
- };
- };
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&ehci {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
+++ /dev/null
-/dts-v1/;
-
-#include "ox820.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- model = "Shuttle KD20";
-
- compatible = "shuttle,kd20", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 256Mbytes DDR */
- reg = <0x60000000 0x10000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_warn;
- led-running = &led_status;
- led-upgrade = &led_warn;
- };
-
- thermal-zones {
- chassis-thermal {
- /* Poll every 20 seconds */
- polling-delay = <20000>;
- /* Poll every 2nd second when cooling */
- polling-delay-passive = <2000>;
-
- thermal-sensors = <&hdd0_temp>, <&hdd1_temp>;
-
- trips {
- chassis_alert0: chassis-alert0 {
- /* At 43 degrees turn on fan */
- temperature = <43000>;
- hysteresis = <3000>;
- type = "active";
- };
-
- chassis_alert1: chassis-alert1 {
- /* At 60 degrees emergency shutdown */
- temperature = <60000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&chassis_alert0>;
- cooling-device = <&system_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
- i2c-gpio {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 9 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- sck-gpios = <&gpio1 10 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <10>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc0: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
-
- keys {
- compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
-
- power {
- label = "power";
- gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- };
- reset {
- label = "reset";
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- eject1 {
- label = "eject1";
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_EJECTCD>;
- };
- eject2 {
- label = "eject2";
- gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
- linux,code = <162>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led_status: status {
- label = "kd20:blue:status";
- gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
- };
- led_warn: status2 {
- label = "kd20:red:status";
- gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
- };
- hdd1blue {
- label = "kd20:blue:hdd1";
- gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ata1";
- };
- hdd1red {
- label = "kd20:red:hdd1";
- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- };
- hdd2blue {
- label = "kd20:blue:hdd2";
- gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ata2";
- };
- hdd2red {
- label = "kd20:red:hdd2";
- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- };
- usb {
- label = "kd20:blue:usb";
- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- trigger-sources = <&ehci_port1>, <&ehci_port2>;
- linux,default-trigger = "usbport";
- };
- };
-
- beeper: beeper {
- compatible = "gpio-beeper";
- gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- };
-
- system_fan: gpio-fan {
- compatible = "gpio-fan";
- gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = <0 0
- 3000 1>;
- #cooling-cells = <2>;
- };
-
- gpio-poweroff {
- compatible = "gpio-poweroff";
- gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "stage1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "u-boot";
- reg = <0x00040000 0x001e0000>;
- read-only;
- };
-
- partition@220000 {
- label = "u-boot-env";
- reg = <0x00220000 0x00020000>;
- };
-
- partition@240000 {
- label = "initrd";
- reg = <0x00240000 0x00600000>;
- };
-
- partition@840000 {
- label = "kernel";
- reg = <0x00840000 0x007C0000>;
- };
-
- partition@e00000 {
- label = "ubi";
- reg = <0x01000000 0x07000000>;
- };
- };
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&ehci {
- status = "okay";
-};
-
-&sata {
- status = "okay";
- nr-ports = <2>;
-
- hdd0_temp: sata-port@0 {
- reg = <0>;
- #thermal-sensor-cells = <0>;
- };
-
- hdd1_temp: sata-port@1 {
- reg = <1>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
+++ /dev/null
-/* linux/include/asm-arm/arch-oxnas/uncompress.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#define OXNAS_UART1_BASE 0x44200000
-
-static inline void putc(int c)
-{
- static volatile unsigned char *uart =
- (volatile unsigned char *)OXNAS_UART1_BASE;
-
- while (!(uart[5] & 0x20)) { /* LSR reg THR empty bit */
- barrier();
- }
- uart[0] = c; /* THR register */
-}
-
-static inline void flush(void)
-{
-}
-
-#define arch_decomp_setup()
-
-#define arch_decomp_wdog()
-
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
+++ /dev/null
-/*
- * sata_oxnas
- * A driver to interface the 934 based sata core present in the ox820
- * with libata and scsi
- * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>
- * based on ox820 sata code by:
- * Copyright (c) 2007 Oxford Semiconductor Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/ata.h>
-#include <linux/libata.h>
-#include <linux/of_platform.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/clk.h>
-#include <linux/reset.h>
-
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <linux/version.h>
-
-static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val |= mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_value_mask(void __iomem *p,
- unsigned mask, unsigned new_value)
-{
- /* TODO sanity check mask & new_value = new_value */
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- val |= new_value;
- writel_relaxed(val, p);
-}
-
-/* sgdma request structure */
-struct sgdma_request {
- volatile u32 qualifier;
- volatile u32 control;
- dma_addr_t src_pa;
- dma_addr_t dst_pa;
-} __packed __aligned(4);
-
-
-/* Controller information */
-enum {
- SATA_OXNAS_MAX_PRD = 63,
- SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *
- sizeof(struct ata_bmdma_prd) +
- sizeof(struct sgdma_request),
- SATA_OXNAS_MAX_PORTS = 2,
- /** The different Oxsemi SATA core version numbers */
- SATA_OXNAS_CORE_VERSION = 0x1f3,
- SATA_OXNAS_IRQ_FLAG = IRQF_SHARED,
- SATA_OXNAS_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
- ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),
- SATA_OXNAS_QUEUE_DEPTH = 32,
-
- SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,
-};
-
-
-/*
- * SATA Port Registers
- */
-enum {
- /** sata host port register offsets */
- ORB1 = 0x00,
- ORB2 = 0x04,
- ORB3 = 0x08,
- ORB4 = 0x0C,
- ORB5 = 0x10,
- MASTER_STATUS = 0x10,
- FIS_CTRL = 0x18,
- FIS_DATA = 0x1C,
- INT_STATUS = 0x30,
- INT_CLEAR = 0x30,
- INT_ENABLE = 0x34,
- INT_DISABLE = 0x38,
- VERSION = 0x3C,
- SATA_CONTROL = 0x5C,
- SATA_COMMAND = 0x60,
- HID_FEATURES = 0x64,
- PORT_CONTROL = 0x68,
- DRIVE_CONTROL = 0x6C,
- /** These registers allow access to the link layer registers
- that reside in a different clock domain to the processor bus */
- LINK_DATA = 0x70,
- LINK_RD_ADDR = 0x74,
- LINK_WR_ADDR = 0x78,
- LINK_CONTROL = 0x7C,
- /* window control */
- WIN1LO = 0x80,
- WIN1HI = 0x84,
- WIN2LO = 0x88,
- WIN2HI = 0x8C,
- WIN0_CONTROL = 0x90,
-};
-
-/** sata port register bits */
-enum{
- /**
- * commands to issue in the master status to tell it to move shadow ,
- * registers to the actual device ,
- */
- SATA_OPCODE_MASK = 0x00000007,
- CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,
- CMD_WRITE_TO_ORB_REGS = 0x2,
- CMD_SYNC_ESCAPE = 0x7,
- CMD_CORE_BUSY = (1 << 7),
- CMD_DRIVE_SELECT_SHIFT = 12,
- CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),
-
- /** interrupt bits */
- INT_END_OF_CMD = 1 << 0,
- INT_LINK_SERROR = 1 << 1,
- INT_ERROR = 1 << 2,
- INT_LINK_IRQ = 1 << 3,
- INT_REG_ACCESS_ERR = 1 << 7,
- INT_BIST_FIS = 1 << 11,
- INT_MASKABLE = INT_END_OF_CMD |
- INT_LINK_SERROR |
- INT_ERROR |
- INT_LINK_IRQ |
- INT_REG_ACCESS_ERR |
- INT_BIST_FIS,
- INT_WANT = INT_END_OF_CMD |
- INT_LINK_SERROR |
- INT_REG_ACCESS_ERR |
- INT_ERROR,
- INT_ERRORS = INT_LINK_SERROR |
- INT_REG_ACCESS_ERR |
- INT_ERROR,
-
- /** raw interrupt bits, unmaskable, but do not generate interrupts */
- RAW_END_OF_CMD = INT_END_OF_CMD << 16,
- RAW_LINK_SERROR = INT_LINK_SERROR << 16,
- RAW_ERROR = INT_ERROR << 16,
- RAW_LINK_IRQ = INT_LINK_IRQ << 16,
- RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,
- RAW_BIST_FIS = INT_BIST_FIS << 16,
- RAW_WANT = INT_WANT << 16,
- RAW_ERRORS = INT_ERRORS << 16,
-
- /**
- * variables to write to the device control register to set the current
- * device, ie. master or slave.
- */
- DR_CON_48 = 2,
- DR_CON_28 = 0,
-
- SATA_CTL_ERR_MASK = 0x00000016,
-
-};
-
-/* ATA SGDMA register offsets */
-enum {
- SGDMA_CONTROL = 0x0,
- SGDMA_STATUS = 0x4,
- SGDMA_REQUESTPTR = 0x8,
- SGDMA_RESETS = 0xC,
- SGDMA_CORESIZE = 0x10,
-};
-
-/* DMA controller register offsets */
-enum {
- DMA_CONTROL = 0x0,
- DMA_CORESIZE = 0x20,
-
- DMA_CONTROL_RESET = (1 << 12),
-};
-
-enum {
- /* see DMA core docs for the values. Out means from memory (bus A) out
- * to disk (bus B) */
- SGDMA_REQCTL0OUT = 0x0497c03d,
- /* burst mode disabled when no micro code used */
- SGDMA_REQCTL0IN = 0x0493a3c1,
- SGDMA_REQCTL1OUT = 0x0497c07d,
- SGDMA_REQCTL1IN = 0x0497a3c5,
- SGDMA_CONTROL_NOGO = 0x3e,
- SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,
- SGDMA_ERRORMASK = 0x3f,
- SGDMA_BUSY = 0x80,
-
- SGDMA_RESETS_CTRL = 1 << 0,
- SGDMA_RESETS_ARBT = 1 << 1,
- SGDMA_RESETS_AHB = 1 << 2,
- SGDMA_RESETS_ALL = SGDMA_RESETS_CTRL |
- SGDMA_RESETS_ARBT |
- SGDMA_RESETS_AHB,
-
- /* Final EOTs */
- SGDMA_REQQUAL = 0x00220001,
-
-};
-
-/** SATA core register offsets */
-enum {
- DM_DBG1 = 0x000,
- RAID_SET = 0x004,
- DM_DBG2 = 0x008,
- DATACOUNT_PORT0 = 0x010,
- DATACOUNT_PORT1 = 0x014,
- CORE_INT_STATUS = 0x030,
- CORE_INT_CLEAR = 0x030,
- CORE_INT_ENABLE = 0x034,
- CORE_INT_DISABLE = 0x038,
- CORE_REBUILD_ENABLE = 0x050,
- CORE_FAILED_PORT_R = 0x054,
- DEVICE_CONTROL = 0x068,
- EXCESS = 0x06C,
- RAID_SIZE_LOW = 0x070,
- RAID_SIZE_HIGH = 0x074,
- PORT_ERROR_MASK = 0x078,
- IDLE_STATUS = 0x07C,
- RAID_CONTROL = 0x090,
- DATA_PLANE_CTRL = 0x0AC,
- CORE_DATAPLANE_STAT = 0x0b8,
- PROC_PC = 0x100,
- CONFIG_IN = 0x3d8,
- PROC_START = 0x3f0,
- PROC_RESET = 0x3f4,
- UCODE_STORE = 0x1000,
- RAID_WP_BOT_LOW = 0x1FF0,
- RAID_WP_BOT_HIGH = 0x1FF4,
- RAID_WP_TOP_LOW = 0x1FF8,
- RAID_WP_TOP_HIGH = 0x1FFC,
- DATA_MUX_RAM0 = 0x8000,
- DATA_MUX_RAM1 = 0xA000,
- PORT_SIZE = 0x10000,
-};
-
-enum {
- /* Sata core debug1 register bits */
- CORE_PORT0_DATA_DIR_BIT = 20,
- CORE_PORT1_DATA_DIR_BIT = 21,
- CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,
- CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,
-
- /** sata core control register bits */
- SCTL_CLR_ERR = 0x00003016,
- RAID_CLR_ERR = 0x0000011e,
-
- /* Interrupts direct from the ports */
- NORMAL_INTS_WANTED = 0x00000303,
-
- /* shift these left by port number */
- COREINT_HOST = 0x00000001,
- COREINT_END = 0x00000100,
- CORERAW_HOST = COREINT_HOST << 16,
- CORERAW_END = COREINT_END << 16,
-
- /* Interrupts from the RAID controller only */
- RAID_INTS_WANTED = 0x00008300,
-
- /* The bits in the IDLE_STATUS that, when set indicate an idle core */
- IDLE_CORES = (1 << 18) | (1 << 19),
-
- /* Data plane control error-mask mask and bit, these bit in the data
- * plane control mask out errors from the ports that prevent the SGDMA
- * care from sending an interrupt */
- DPC_ERROR_MASK = 0x00000300,
- DPC_ERROR_MASK_BIT = 0x00000100,
- /* enable jbod micro-code */
- DPC_JBOD_UCODE = 1 << 0,
- DPC_FIS_SWCH = 1 << 1,
-
- /** Device Control register bits */
- DEVICE_CONTROL_DMABT = 1 << 4,
- DEVICE_CONTROL_ABORT = 1 << 2,
- DEVICE_CONTROL_PAD = 1 << 3,
- DEVICE_CONTROL_PADPAT = 1 << 16,
- DEVICE_CONTROL_PRTRST = 1 << 8,
- DEVICE_CONTROL_RAMRST = 1 << 12,
- DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,
-
- /** oxsemi HW raid modes */
- OXNASSATA_NOTRAID = 0,
- OXNASSATA_RAID0 = 1,
- OXNASSATA_RAID1 = 2,
- /** OX820 specific HW-RAID register values */
- RAID_TWODISKS = 3,
- UNKNOWN_MODE = ~0,
-
- CONFIG_IN_RESUME = 2,
-};
-
-/* SATA PHY Registers */
-enum {
- PHY_STAT = 0x00,
- PHY_DATA = 0x04,
-};
-
-enum {
- STAT_READ_VALID = (1 << 21),
- STAT_CR_ACK = (1 << 20),
- STAT_CR_READ = (1 << 19),
- STAT_CR_WRITE = (1 << 18),
- STAT_CAP_DATA = (1 << 17),
- STAT_CAP_ADDR = (1 << 16),
-
- STAT_ACK_ANY = STAT_CR_ACK |
- STAT_CR_READ |
- STAT_CR_WRITE |
- STAT_CAP_DATA |
- STAT_CAP_ADDR,
-
- CR_READ_ENABLE = (1 << 16),
- CR_WRITE_ENABLE = (1 << 17),
- CR_CAP_DATA = (1 << 18),
-};
-
-enum {
- /* Link layer registers */
- SERROR_IRQ_MASK = 5,
-};
-
-enum {
- OXNAS_SATA_SOFTRESET = 1,
- OXNAS_SATA_REINIT = 2,
-};
-
-enum {
- OXNAS_SATA_UCODE_RAID0,
- OXNAS_SATA_UCODE_RAID1,
- OXNAS_SATA_UCODE_JBOD,
- OXNAS_SATA_UCODE_NONE,
-};
-
-enum {
- SATA_UNLOCKED,
- SATA_WRITER,
- SATA_READER,
- SATA_REBUILD,
- SATA_HWRAID,
- SATA_SCSI_STACK
-};
-
-typedef irqreturn_t (*oxnas_sata_isr_callback_t)(int, unsigned long, int);
-
-struct sata_oxnas_host_priv {
- void __iomem *port_base;
- void __iomem *dmactl_base;
- void __iomem *sgdma_base;
- void __iomem *core_base;
- void __iomem *phy_base;
- dma_addr_t dma_base;
- void __iomem *dma_base_va;
- size_t dma_size;
- int irq;
- int n_ports;
- int current_ucode;
- u32 port_frozen;
- u32 port_in_eh;
- struct clk *clk;
- struct reset_control *rst_sata;
- struct reset_control *rst_link;
- struct reset_control *rst_phy;
- spinlock_t phy_lock;
- spinlock_t core_lock;
- int core_locked;
- int reentrant_port_no;
- int hw_lock_count;
- int direct_lock_count;
- void *locker_uid;
- int current_locker_type;
- int scsi_nonblocking_attempts;
- oxnas_sata_isr_callback_t isr_callback;
- void *isr_arg;
- wait_queue_head_t fast_wait_queue;
- wait_queue_head_t scsi_wait_queue;
-};
-
-
-struct sata_oxnas_port_priv {
- void __iomem *port_base;
- void __iomem *dmactl_base;
- void __iomem *sgdma_base;
- void __iomem *core_base;
- struct sgdma_request *sgdma_request;
- dma_addr_t sgdma_request_pa;
-};
-
-static u8 sata_oxnas_check_status(struct ata_port *ap);
-static int sata_oxnas_cleanup(struct ata_host *ah);
-static void sata_oxnas_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static void sata_oxnas_irq_on(struct ata_port *ap);
-static void sata_oxnas_post_reset_init(struct ata_port *ap);
-
-static int sata_oxnas_acquire_hw(struct ata_port *ap, int may_sleep,
- int timeout_jiffies);
-static void sata_oxnas_release_hw(struct ata_port *ap);
-
-static const void *HW_LOCKER_UID = (void *)0xdeadbeef;
-
-/***************************************************************************
-* ASIC access
-***************************************************************************/
-static void wait_cr_ack(void __iomem *phy_base)
-{
- while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)
- ; /* wait for an ack bit to be set */
-}
-
-static u16 read_cr(void __iomem *phy_base, u16 address)
-{
- iowrite32((u32)address, phy_base + PHY_STAT);
- wait_cr_ack(phy_base);
- iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);
- wait_cr_ack(phy_base);
- return (u16)ioread32(phy_base + PHY_STAT);
-}
-
-static void write_cr(void __iomem *phy_base, u16 data, u16 address)
-{
- iowrite32((u32)address, phy_base + PHY_STAT);
- wait_cr_ack(phy_base);
- iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);
- wait_cr_ack(phy_base);
- iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);
- wait_cr_ack(phy_base);
-}
-
-#define PH_GAIN 2
-#define FR_GAIN 3
-#define PH_GAIN_OFFSET 6
-#define FR_GAIN_OFFSET 8
-#define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
-#define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
-#define USE_INT_SETTING (1<<5)
-
-void workaround5458(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
- void __iomem *phy_base = hd->phy_base;
- u16 rx_control;
- unsigned i;
-
- for (i = 0; i < 2; i++) {
- rx_control = read_cr(phy_base, 0x201d + (i << 8));
- rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
- rx_control |= PH_GAIN << PH_GAIN_OFFSET;
- rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;
- write_cr(phy_base, rx_control, 0x201d+(i<<8));
- }
-}
-
-/**
- * allows access to the link layer registers
- * @param link_reg the link layer register to access (oxsemi indexing ie
- * 00 = static config, 04 = phy ctrl)
- */
-void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
- void __iomem *port_base = pd->port_base;
- u32 patience;
- unsigned long flags;
-
- DPRINTK("P%d [0x%02x]->0x%08x\n", ap->port_no, link_reg, val);
-
- spin_lock_irqsave(&hd->phy_lock, flags);
- iowrite32(val, port_base + LINK_DATA);
-
- /* accessed twice as a work around for a bug in the SATA abp bridge
- * hardware (bug 6828) */
- iowrite32(link_reg , port_base + LINK_WR_ADDR);
- ioread32(port_base + LINK_WR_ADDR);
-
- for (patience = 0x100000; patience > 0; --patience) {
- if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
- break;
- }
- spin_unlock_irqrestore(&hd->phy_lock, flags);
-}
-
-static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,
- u32 val)
-{
- sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);
- return 0;
-}
-
-static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,
- u32 val)
-{
- return sata_oxnas_scr_write_port(link->ap, sc_reg, val);
-}
-
-u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
- void __iomem *port_base = pd->port_base;
- u32 result;
- u32 patience;
- unsigned long flags;
-
- spin_lock_irqsave(&hd->phy_lock, flags);
- /* accessed twice as a work around for a bug in the SATA abp bridge
- * hardware (bug 6828) */
- iowrite32(link_reg, port_base + LINK_RD_ADDR);
- ioread32(port_base + LINK_RD_ADDR);
-
- for (patience = 0x100000; patience > 0; --patience) {
- if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
- break;
- }
- if (patience == 0)
- DPRINTK("link read timed out for port %d\n", ap->port_no);
-
- result = ioread32(port_base + LINK_DATA);
- spin_unlock_irqrestore(&hd->phy_lock, flags);
-
- return result;
-}
-
-static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,
- u32 *val)
-{
- *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));
- return 0;
-}
-
-static int sata_oxnas_scr_read(struct ata_link *link,
- unsigned int sc_reg, u32 *val)
-{
- return sata_oxnas_scr_read_port(link->ap, sc_reg, val);
-}
-
-/**
- * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
- * registered, to be sure hardware is quiet. It clears and masks interrupt bits
- * in the SATA core.
- *
- * @param ap hardware with the registers in
- */
-static void sata_oxnas_irq_clear(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
-
- /* clear pending interrupts */
- iowrite32(~0, port_priv->port_base + INT_CLEAR);
- iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);
-}
-
-/**
- * qc_issue is used to make a command active, once the hardware and S/G tables
- * have been prepared. IDE BMDMA drivers use the helper function
- * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
- * drivers roll their own ->qc_issue implementation, using this as the
- * "issue new ATA command to hardware" hook.
- * @param qc the queued command to issue
- */
-static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)
-{
- struct sata_oxnas_port_priv *pd = qc->ap->private_data;
- struct sata_oxnas_host_priv *hd = qc->ap->host->private_data;
-
- void __iomem *port_base = pd->port_base;
- void __iomem *core_base = pd->core_base;
- int port_no = qc->ap->port_no;
- int no_microcode = (hd->current_ucode == UNKNOWN_MODE);
- u32 reg;
-
- /* check the core is idle */
- if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {
- int count = 0;
-
- DPRINTK("core busy for a command on port %d\n",
- qc->ap->port_no);
- do {
- mdelay(1);
- if (++count > 100) {
- DPRINTK("core busy for a command on port %d\n",
- qc->ap->port_no);
- /* CrazyDumpDebug(); */
- sata_oxnas_cleanup(qc->ap->host);
- }
- } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);
- }
-
- /* enable passing of error signals to DMA sub-core by clearing the
- * appropriate bit */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- if (no_microcode)
- reg |= (DPC_ERROR_MASK_BIT | (DPC_ERROR_MASK_BIT << 1));
- reg &= ~(DPC_ERROR_MASK_BIT << port_no);
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
-
- /* Disable all interrupts for ports and RAID controller */
- iowrite32(~0, port_base + INT_DISABLE);
-
- /* Disable all interrupts for core */
- iowrite32(~0, core_base + CORE_INT_DISABLE);
- wmb();
-
- /* Load the command settings into the orb registers */
- sata_oxnas_tf_load(qc->ap, &qc->tf);
-
- /* both pio and dma commands use dma */
- if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
- /* Start the DMA */
- iowrite32(SGDMA_CONTROL_GO, pd->sgdma_base + SGDMA_CONTROL);
- wmb();
- }
-
- /* enable End of command interrupt */
- iowrite32(INT_WANT, port_base + INT_ENABLE);
- iowrite32(COREINT_END, core_base + CORE_INT_ENABLE);
- wmb();
-
- /* Start the command */
- reg = ioread32(port_base + SATA_COMMAND);
- reg &= ~SATA_OPCODE_MASK;
- reg |= CMD_WRITE_TO_ORB_REGS;
- iowrite32(reg , port_base + SATA_COMMAND);
- wmb();
-
- return 0;
-}
-
-/**
- * Will schedule the libATA error handler on the premise that there has
- * been a hotplug event on the port specified
- */
-void sata_oxnas_checkforhotplug(struct ata_port *ap)
-{
- DPRINTK("ENTER\n");
-
- ata_ehi_hotplugged(&ap->link.eh_info);
- ata_port_freeze(ap);
-}
-
-
-/**************************************************************************/
-/* Locking */
-/**************************************************************************/
-/**
- * The underlying function that controls access to the sata core
- *
- * @return non-zero indicates that you have acquired exclusive access to the
- * sata core.
- */
-static int __acquire_sata_core(
- struct ata_host *ah,
- int port_no,
- oxnas_sata_isr_callback_t callback,
- void *arg,
- int may_sleep,
- int timeout_jiffies,
- int hw_access,
- void *uid,
- int locker_type)
-{
- unsigned long end = jiffies + timeout_jiffies;
- int acquired = 0;
- unsigned long flags;
- int timed_out = 0;
- struct sata_oxnas_host_priv *hd;
-
- DEFINE_WAIT(wait);
-
- if (!ah)
- return acquired;
-
- hd = ah->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
-
- DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, "
- "callback %p, hw_access %d, core_locked %d, "
- "reentrant_port_no %d, isr_callback %p\n",
- uid, port_no, hd->hw_lock_count, hd->direct_lock_count,
- callback, hw_access, hd->core_locked, hd->reentrant_port_no,
- hd->isr_callback);
-
- while (!timed_out) {
- if (hd->core_locked ||
- (!hw_access && hd->scsi_nonblocking_attempts)) {
- /* Can only allow access if from SCSI/SATA stack and if
- * reentrant access is allowed and this access is to the
- * same port for which the lock is current held
- */
- if (hw_access && (port_no == hd->reentrant_port_no)) {
- BUG_ON(!hd->hw_lock_count);
- ++(hd->hw_lock_count);
-
- DPRINTK("Allow SCSI/SATA re-entrant access to "
- "uid %p port %d\n", uid, port_no);
- acquired = 1;
- break;
- } else if (!hw_access) {
- if ((locker_type == SATA_READER) &&
- (hd->current_locker_type == SATA_READER)) {
- WARN(1,
- "Already locked by reader, "
- "uid %p, locker_uid %p, "
- "port %d, h/w count %d, "
- "d count %d, hw_access %d\n",
- uid, hd->locker_uid, port_no,
- hd->hw_lock_count,
- hd->direct_lock_count,
- hw_access);
- goto check_uid;
- }
-
- if ((locker_type != SATA_READER) &&
- (locker_type != SATA_WRITER)) {
- goto wait_for_lock;
- }
-
-check_uid:
- WARN(uid == hd->locker_uid, "Attempt to lock "
- "by locker type %d uid %p, already "
- "locked by locker type %d with "
- "locker_uid %p, port %d, "
- "h/w count %d, d count %d, "
- "hw_access %d\n", locker_type, uid,
- hd->current_locker_type,
- hd->locker_uid, port_no,
- hd->hw_lock_count,
- hd->direct_lock_count, hw_access);
- }
- } else {
- WARN(hd->hw_lock_count || hd->direct_lock_count,
- "Core unlocked but counts non-zero: uid %p, "
- "locker_uid %p, port %d, h/w count %d, "
- "d count %d, hw_access %d\n", uid,
- hd->locker_uid, port_no, hd->hw_lock_count,
- hd->direct_lock_count, hw_access);
-
- BUG_ON(hd->current_locker_type != SATA_UNLOCKED);
-
- WARN(hd->locker_uid, "Attempt to lock uid %p when "
- "locker_uid %p is non-zero, port %d, "
- "h/w count %d, d count %d, hw_access %d\n",
- uid, hd->locker_uid, port_no, hd->hw_lock_count,
- hd->direct_lock_count, hw_access);
-
- if (!hw_access) {
- /* Direct access attempting to acquire
- * non-contented lock
- */
- /* Must have callback for direct access */
- BUG_ON(!callback);
- /* Sanity check lock state */
- BUG_ON(hd->reentrant_port_no != -1);
-
- hd->isr_callback = callback;
- hd->isr_arg = arg;
- ++(hd->direct_lock_count);
-
- hd->current_locker_type = locker_type;
- } else {
- /* SCSI/SATA attempting to acquire
- * non-contented lock
- */
- /* No callbacks for SCSI/SATA access */
- BUG_ON(callback);
- /* No callback args for SCSI/SATA access */
- BUG_ON(arg);
-
- /* Sanity check lock state */
- BUG_ON(hd->isr_callback);
- BUG_ON(hd->isr_arg);
-
- ++(hd->hw_lock_count);
- hd->reentrant_port_no = port_no;
-
- hd->current_locker_type = SATA_SCSI_STACK;
- }
-
- hd->core_locked = 1;
- hd->locker_uid = uid;
- acquired = 1;
- break;
- }
-
-wait_for_lock:
- if (!may_sleep) {
- DPRINTK("Denying for uid %p locker_type %d, "
- "hw_access %d, port %d, current_locker_type %d as "
- "cannot sleep\n", uid, locker_type, hw_access, port_no,
- hd->current_locker_type);
-
- if (hw_access)
- ++(hd->scsi_nonblocking_attempts);
-
- break;
- }
-
- /* Core is locked and we're allowed to sleep, so wait to be
- * awoken when the core is unlocked
- */
- for (;;) {
- prepare_to_wait(hw_access ? &hd->scsi_wait_queue :
- &hd->fast_wait_queue,
- &wait, TASK_UNINTERRUPTIBLE);
- if (!hd->core_locked &&
- !(!hw_access && hd->scsi_nonblocking_attempts)) {
- /* We're going to use variables that will have
- * been changed by the waker prior to clearing
- * core_locked so we need to ensure we see
- * changes to all those variables
- */
- smp_rmb();
- break;
- }
- if (time_after(jiffies, end)) {
- printk(KERN_WARNING "__acquire_sata_core() "
- "uid %p failing for port %d timed out, "
- "locker_uid %p, h/w count %d, "
- "d count %d, callback %p, hw_access %d, "
- "core_locked %d, reentrant_port_no %d, "
- "isr_callback %p, isr_arg %p\n", uid,
- port_no, hd->locker_uid,
- hd->hw_lock_count,
- hd->direct_lock_count, callback,
- hw_access, hd->core_locked,
- hd->reentrant_port_no, hd->isr_callback,
- hd->isr_arg);
- timed_out = 1;
- break;
- }
- spin_unlock_irqrestore(&hd->core_lock, flags);
- if (!schedule_timeout(4*HZ)) {
- printk(KERN_INFO "__acquire_sata_core() uid %p, "
- "locker_uid %p, timed-out of "
- "schedule(), checking overall timeout\n",
- uid, hd->locker_uid);
- }
- spin_lock_irqsave(&hd->core_lock, flags);
- }
- finish_wait(hw_access ? &hd->scsi_wait_queue :
- &hd->fast_wait_queue, &wait);
- }
-
- if (hw_access && acquired) {
- if (hd->scsi_nonblocking_attempts)
- hd->scsi_nonblocking_attempts = 0;
-
- /* Wake any other SCSI/SATA waiters so they can get reentrant
- * access to the same port if appropriate. This is because if
- * the SATA core is locked by fast access, or SCSI/SATA access
- * to other port, then can have >1 SCSI/SATA waiters on the wait
- * list so want to give reentrant accessors a chance to get
- * access ASAP
- */
- if (!list_empty(&hd->scsi_wait_queue.head))
- wake_up(&hd->scsi_wait_queue);
- }
-
- DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n",
- uid, acquired, port_no, callback);
-
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- return acquired;
-}
-
-int sata_core_has_fast_waiters(struct ata_host *ah)
-{
- int has_waiters;
- unsigned long flags;
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
- has_waiters = !list_empty(&hd->fast_wait_queue.head);
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- return has_waiters;
-}
-EXPORT_SYMBOL(sata_core_has_fast_waiters);
-
-int sata_core_has_scsi_waiters(struct ata_host *ah)
-{
- int has_waiters;
- unsigned long flags;
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
- has_waiters = hd->scsi_nonblocking_attempts ||
- !list_empty(&hd->scsi_wait_queue.head);
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- return has_waiters;
-}
-EXPORT_SYMBOL(sata_core_has_scsi_waiters);
-
-/*
- * ata_port operation to gain ownership of the SATA hardware prior to issuing
- * a command against a SATA host. Allows any number of users of the port against
- * which the lock was first acquired, thus enforcing that only one SATA core
- * port may be operated on at once.
- */
-static int sata_oxnas_acquire_hw(
- struct ata_port *ap,
- int may_sleep,
- int timeout_jiffies)
-{
- return __acquire_sata_core(ap->host, ap->port_no, NULL, 0, may_sleep,
- timeout_jiffies, 1, (void *)HW_LOCKER_UID,
- SATA_SCSI_STACK);
-}
-
-/*
- * operation to release ownership of the SATA hardware
- */
-static void sata_oxnas_release_hw(struct ata_port *ap)
-{
- unsigned long flags;
- int released = 0;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
-
- DPRINTK("Entered port_no = %d, h/w count %d, d count %d, "
- "core locked = %d, reentrant_port_no = %d, isr_callback %p\n",
- ap->port_no, hd->hw_lock_count, hd->direct_lock_count,
- hd->core_locked, hd->reentrant_port_no, hd->isr_callback);
-
- if (!hd->core_locked) {
- /* Nobody holds the SATA lock */
- printk(KERN_WARNING "Nobody holds SATA lock, port_no %d\n",
- ap->port_no);
- released = 1;
- } else if (!hd->hw_lock_count) {
- /* SCSI/SATA has released without holding the lock */
- printk(KERN_WARNING "SCSI/SATA does not hold SATA lock, "
- "port_no %d\n", ap->port_no);
- } else {
- /* Trap incorrect usage */
- BUG_ON(hd->reentrant_port_no == -1);
- BUG_ON(ap->port_no != hd->reentrant_port_no);
- BUG_ON(hd->direct_lock_count);
- BUG_ON(hd->current_locker_type != SATA_SCSI_STACK);
-
- WARN(!hd->locker_uid || (hd->locker_uid != HW_LOCKER_UID),
- "Invalid locker uid %p, h/w count %d, d count %d, "
- "reentrant_port_no %d, core_locked %d, "
- "isr_callback %p\n", hd->locker_uid, hd->hw_lock_count,
- hd->direct_lock_count, hd->reentrant_port_no,
- hd->core_locked, hd->isr_callback);
-
- if (--(hd->hw_lock_count)) {
- DPRINTK("Still nested port_no %d\n", ap->port_no);
- } else {
- DPRINTK("Release port_no %d\n", ap->port_no);
- hd->reentrant_port_no = -1;
- hd->isr_callback = NULL;
- hd->current_locker_type = SATA_UNLOCKED;
- hd->locker_uid = 0;
- hd->core_locked = 0;
- released = 1;
- wake_up(!list_empty(&hd->scsi_wait_queue.head) ?
- &hd->scsi_wait_queue :
- &hd->fast_wait_queue);
- }
- }
-
- DPRINTK("Leaving, port_no %d, count %d\n", ap->port_no,
- hd->hw_lock_count);
-
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- /* CONFIG_SATA_OX820_DIRECT_HWRAID */
- /* if (released)
- ox820hwraid_restart_queue();
- } */
-}
-
-static inline int sata_oxnas_is_host_frozen(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- smp_rmb();
- return hd->port_in_eh || hd->port_frozen;
-}
-
-
-static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- return (ioread32(hd->port_base + SATA_COMMAND) & CMD_CORE_BUSY) ||
- (hd->n_ports > 1 &&
- (ioread32(hd->port_base + PORT_SIZE + SATA_COMMAND) &
- CMD_CORE_BUSY));
-}
-
-static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
-
- return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;
-}
-
-
-/**
- * Turns on the cores clock and resets it
- */
-static void sata_oxnas_reset_core(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *host_priv = ah->private_data;
- int n;
-
- DPRINTK("ENTER\n");
- clk_prepare_enable(host_priv->clk);
-
- reset_control_assert(host_priv->rst_sata);
- reset_control_assert(host_priv->rst_link);
- reset_control_assert(host_priv->rst_phy);
-
- udelay(50);
-
- /* un-reset the PHY, then Link and Controller */
- reset_control_deassert(host_priv->rst_phy);
- udelay(50);
-
- reset_control_deassert(host_priv->rst_sata);
- reset_control_deassert(host_priv->rst_link);
- udelay(50);
-
- workaround5458(ah);
- /* tune for sata compatibility */
- sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);
-
- for (n = 0; n < host_priv->n_ports; n++) {
- /* each port in turn */
- sata_oxnas_link_write(ah->ports[n], 0x70, 0x55629);
- }
- udelay(50);
-}
-
-
-/**
- * Called after an identify device command has worked out what kind of device
- * is on the port
- *
- * @param port The port to configure
- * @param pdev The hardware associated with controlling the port
- */
-static void sata_oxnas_dev_config(struct ata_device *pdev)
-{
- struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;
- void __iomem *port_base = pd->port_base;
- u32 reg;
-
- DPRINTK("ENTER\n");
- /* Set the bits to put the port into 28 or 48-bit node */
- reg = ioread32(port_base + DRIVE_CONTROL);
- reg &= ~3;
- reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;
- iowrite32(reg, port_base + DRIVE_CONTROL);
-
- /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
- if (pdev->flags & ATA_DFLAG_LBA48) {
- reg = ioread32(port_base + PORT_CONTROL);
- reg |= 2;
- iowrite32(reg, port_base + PORT_CONTROL);
- }
-}
-/**
- * called to write a taskfile into the ORB registers
- * @param ap hardware with the registers in
- * @param tf taskfile to write to the registers
- */
-static void sata_oxnas_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- u32 count = 0;
- u32 Orb1 = 0;
- u32 Orb2 = 0;
- u32 Orb3 = 0;
- u32 Orb4 = 0;
- u32 Command_Reg;
-
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
- void __iomem *port_base = port_priv->port_base;
- unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
-
- /* wait a maximum of 10ms for the core to be idle */
- do {
- Command_Reg = ioread32(port_base + SATA_COMMAND);
- if (!(Command_Reg & CMD_CORE_BUSY))
- break;
- count++;
- udelay(50);
- } while (count < 200);
-
- /* check if the ctl register has interrupts disabled or enabled and
- * modify the interrupt enable registers on the ata core as required */
- if (tf->ctl & ATA_NIEN) {
- /* interrupts disabled */
- u32 mask = (COREINT_END << ap->port_no);
-
- iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);
- sata_oxnas_irq_clear(ap);
- } else {
- sata_oxnas_irq_on(ap);
- }
-
- Orb2 |= (tf->command) << 24;
-
- /* write 48 or 28 bit tf parameters */
- if (is_addr) {
- /* set LBA bit as it's an address */
- Orb1 |= (tf->device & ATA_LBA) << 24;
-
- if (tf->flags & ATA_TFLAG_LBA48) {
- Orb1 |= ATA_LBA << 24;
- Orb2 |= (tf->hob_nsect) << 8;
- Orb3 |= (tf->hob_lbal) << 24;
- Orb4 |= (tf->hob_lbam) << 0;
- Orb4 |= (tf->hob_lbah) << 8;
- Orb4 |= (tf->hob_feature) << 16;
- } else {
- Orb3 |= (tf->device & 0xf) << 24;
- }
-
- /* write 28-bit lba */
- Orb2 |= (tf->nsect) << 0;
- Orb2 |= (tf->feature) << 16;
- Orb3 |= (tf->lbal) << 0;
- Orb3 |= (tf->lbam) << 8;
- Orb3 |= (tf->lbah) << 16;
- Orb4 |= (tf->ctl) << 24;
- }
-
- if (tf->flags & ATA_TFLAG_DEVICE)
- Orb1 |= (tf->device) << 24;
-
- ap->last_ctl = tf->ctl;
-
- /* write values to registers */
- iowrite32(Orb1, port_base + ORB1);
- iowrite32(Orb2, port_base + ORB2);
- iowrite32(Orb3, port_base + ORB3);
- iowrite32(Orb4, port_base + ORB4);
-}
-
-
-void sata_oxnas_set_mode(struct ata_host *ah, u32 mode, u32 force)
-{
- struct sata_oxnas_host_priv *host_priv = ah->private_data;
- void __iomem *core_base = host_priv->core_base;
-
- unsigned int *src;
- void __iomem *dst;
- unsigned int progmicrocode = 0;
- unsigned int changeparameters = 0;
-
- u32 previous_mode;
-
- /* these micro-code programs _should_ include the version word */
-
- /* JBOD */
- static const unsigned int jbod[] = {
- 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
- 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
- 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
- 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
- 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
- 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
- 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
- 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
- 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
- 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
- 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
- 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
- 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
- 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
- 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
- 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
- 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
- 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
- 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
- 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
- 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
- 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
- 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
- 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
- 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
- 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
- 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
- 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
- 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
- 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
- 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
- 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
- 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
- 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
- 0x00718908, 0x0208A206, 0x00EE0005, ~0
- };
-
- /* Bi-Modal RAID-0/1 */
- static const unsigned int raid[] = {
- 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
- 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
- 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
- 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
- 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
- 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
- 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
- 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
- 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
- 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
- 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
- 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
- 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
- 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
- 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
- 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
- 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
- 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
- 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
- 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
- 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
- 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
- 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
- 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
- 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
- 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
- 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
- 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
- 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
- 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
- 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
- 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
- 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
- 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
- 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
- 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
- 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
- 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
- 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
- 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
- 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
- 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
- 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
- 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
- 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
- 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
- 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
- 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
- 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
- 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
- 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
- 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
- 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
- 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
- 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
- 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
- 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
- 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
- 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
- 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
- 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
- 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
- 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
- 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
- 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
- 0x02400000, ~0
- };
-
- DPRINTK("ENTER: mode:%d, force:%d\n", mode, force);
-
- if (force)
- previous_mode = UNKNOWN_MODE;
- else
- previous_mode = host_priv->current_ucode;
-
- if (mode == previous_mode)
- return;
-
- host_priv->current_ucode = mode;
-
- /* decide what needs to be done using the STD in my logbook */
- switch (previous_mode) {
- case OXNASSATA_RAID1:
- switch (mode) {
- case OXNASSATA_RAID0:
- changeparameters = 1;
- break;
- case OXNASSATA_NOTRAID:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
- break;
- case OXNASSATA_RAID0:
- switch (mode) {
- case OXNASSATA_RAID1:
- changeparameters = 1;
- break;
- case OXNASSATA_NOTRAID:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
- break;
- case OXNASSATA_NOTRAID:
- switch (mode) {
- case OXNASSATA_RAID0:
- case OXNASSATA_RAID1:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
- break;
- case UNKNOWN_MODE:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
-
- /* no need to reprogram everything if already in the right mode */
- if (progmicrocode) {
- /* reset micro-code processor */
- iowrite32(1, core_base + PROC_RESET);
- wmb();
-
- /* select micro-code */
- switch (mode) {
- case OXNASSATA_RAID1:
- case OXNASSATA_RAID0:
- VPRINTK("Loading RAID micro-code\n");
- src = (unsigned int *)&raid[1];
- break;
- case OXNASSATA_NOTRAID:
- VPRINTK("Loading JBOD micro-code\n");
- src = (unsigned int *)&jbod[1];
- break;
- default:
- BUG();
- break;
- }
-
- /* load micro code */
- dst = core_base + UCODE_STORE;
- while (*src != ~0) {
- iowrite32(*src, dst);
- src++;
- dst += sizeof(*src);
- }
- wmb();
- }
-
- if (changeparameters) {
- u32 reg;
- /* set other mode dependent flags */
- switch (mode) {
- case OXNASSATA_RAID1:
- /* clear JBOD mode */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg |= DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
-
- /* set the hardware up for RAID-1 */
- iowrite32(0, core_base + RAID_WP_BOT_LOW);
- iowrite32(0, core_base + RAID_WP_BOT_HIGH);
- iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
- iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
- iowrite32(0, core_base + RAID_SIZE_LOW);
- iowrite32(0, core_base + RAID_SIZE_HIGH);
- wmb();
- break;
- case OXNASSATA_RAID0:
- /* clear JBOD mode */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg |= DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
-
- /* set the hardware up for RAID-1 */
- iowrite32(0, core_base + RAID_WP_BOT_LOW);
- iowrite32(0, core_base + RAID_WP_BOT_HIGH);
- iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
- iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
- iowrite32(0xffffffff, core_base + RAID_SIZE_LOW);
- iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);
- wmb();
- break;
- case OXNASSATA_NOTRAID:
- /* enable jbod mode */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg &= ~DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
-
- /* start micro-code processor*/
- iowrite32(1, core_base + PROC_START);
- break;
- default:
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg |= DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
- break;
- }
- }
-}
-
-/**
- * sends a sync-escape if there is a link present
- */
-static inline void sata_oxnas_send_sync_escape(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 reg;
-
- /* read the SSTATUS register and only send a sync escape if there is a
- * link active */
- if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {
- reg = ioread32(pd->port_base + SATA_COMMAND);
- reg &= ~SATA_OPCODE_MASK;
- reg |= CMD_SYNC_ESCAPE;
- iowrite32(reg, pd->port_base + SATA_COMMAND);
- }
-}
-
-/* clears errors */
-static inline void sata_oxnas_clear_CS_error(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 *base = pd->port_base;
- u32 reg;
-
- reg = ioread32(base + SATA_CONTROL);
- reg &= SATA_CTL_ERR_MASK;
- iowrite32(reg, base + SATA_CONTROL);
-}
-
-static inline void sata_oxnas_reset_sgdma(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
-
- iowrite32(SGDMA_RESETS_CTRL, pd->sgdma_base + SGDMA_RESETS);
-}
-
-static inline void sata_oxnas_reset_dma(struct ata_port *ap, int assert)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 reg;
-
- reg = ioread32(pd->dmactl_base + DMA_CONTROL);
- if (assert)
- reg |= DMA_CONTROL_RESET;
- else
- reg &= ~DMA_CONTROL_RESET;
-
- iowrite32(reg, pd->dmactl_base + DMA_CONTROL);
-};
-
-/**
- * Clears the error caused by the core's registers being accessed when the
- * core is busy.
- */
-static inline void sata_oxnas_clear_reg_access_error(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 *base = pd->port_base;
- u32 reg;
-
- reg = ioread32(base + INT_STATUS);
-
- DPRINTK("ENTER\n");
- if (reg & INT_REG_ACCESS_ERR) {
- DPRINTK("clearing register access error on port %d\n",
- ap->port_no);
- iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);
- }
- reg = ioread32(base + INT_STATUS);
- if (reg & INT_REG_ACCESS_ERR)
- DPRINTK("register access error didn't clear\n");
-}
-
-static inline void sata_oxnas_clear_sctl_error(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 *base = pd->port_base;
- u32 reg;
-
- reg = ioread32(base + SATA_CONTROL);
- reg |= SCTL_CLR_ERR;
- iowrite32(reg, base + SATA_CONTROL);
-}
-
-static inline void sata_oxnas_clear_raid_error(struct ata_host *ah)
-{
- return;
-};
-
-/**
- * Clean up all the state machines in the sata core.
- * @return post cleanup action required
- */
-static int sata_oxnas_cleanup(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
- int actions_required = 0;
- int n;
-
- printk(KERN_INFO "sata_oxnas: resetting SATA core\n");
- /* core not recovering, reset it */
- mdelay(5);
- sata_oxnas_reset_core(ah);
- mdelay(5);
- actions_required |= OXNAS_SATA_REINIT;
- /* Perform any SATA core re-initialisation after reset post reset init
- * needs to be called for both ports as there's one reset for both
- * ports */
- for (n = 0; n < hd->n_ports; n++)
- sata_oxnas_post_reset_init(ah->ports[n]);
-
-
- return actions_required;
-}
-
-/**
- * ata_qc_new - Request an available ATA command, for queueing
- * @ap: Port associated with device @dev
- * @return non zero will refuse a new command, zero will may grant on subject
- * to conditions elsewhere.
- *
- */
-static int sata_oxnas_qc_new(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("port %d\n", ap->port_no);
- smp_rmb();
- if (hd->port_frozen || hd->port_in_eh)
- return 1;
- else
- return !sata_oxnas_acquire_hw(ap, 0, 0);
-}
-
-/**
- * releases the lock on the port the command used
- */
-static void sata_oxnas_qc_free(struct ata_queued_cmd *qc)
-{
- DPRINTK("\n");
- sata_oxnas_release_hw(qc->ap);
-}
-
-static void sata_oxnas_freeze(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("\n");
- hd->port_frozen |= BIT(ap->port_no);
- smp_wmb();
-}
-
-static void sata_oxnas_thaw(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("\n");
- hd->port_frozen &= ~BIT(ap->port_no);
- smp_wmb();
-}
-
-void sata_oxnas_freeze_host(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("ENTER\n");
- hd->port_in_eh |= BIT(ap->port_no);
- smp_wmb();
-}
-
-void sata_oxnas_thaw_host(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("ENTER\n");
- hd->port_in_eh &= ~BIT(ap->port_no);
- smp_wmb();
-}
-
-static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)
-{
- DPRINTK("ENTER\n");
- /* If the core is busy here, make it idle */
- if (qc->flags & ATA_QCFLAG_FAILED)
- sata_oxnas_cleanup(qc->ap->host);
-}
-
-
-/**
- * turn on the interrupts
- *
- * @param ap Hardware with the registers in
- */
-static void sata_oxnas_irq_on(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 mask = (COREINT_END << ap->port_no);
-
- /* Clear pending interrupts */
- iowrite32(~0, pd->port_base + INT_CLEAR);
- iowrite32(mask, pd->core_base + CORE_INT_STATUS);
- wmb();
-
- /* enable End of command interrupt */
- iowrite32(INT_WANT, pd->port_base + INT_ENABLE);
- iowrite32(mask, pd->core_base + CORE_INT_ENABLE);
-}
-
-
-/** @return true if the port has a cable connected */
-int sata_oxnas_check_link(struct ata_port *ap)
-{
- int reg;
-
- sata_oxnas_scr_read_port(ap, SCR_STATUS, ®);
- /* Check for the cable present indicated by SCR status bit-0 set */
- return reg & 0x1;
-}
-
-/**
- * ata_std_postreset - standard postreset callback
- * @link: the target ata_link
- * @classes: classes of attached devices
- *
- * This function is invoked after a successful reset. Note that
- * the device might have been reset more than once using
- * different reset methods before postreset is invoked.
- *
- * LOCKING:
- * Kernel thread context (may sleep)
- */
-static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)
-{
- struct ata_port *ap = link->ap;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- unsigned int dev;
-
- DPRINTK("ENTER\n");
- ata_std_postreset(link, classes);
-
- /* turn on phy error detection by removing the masks */
- sata_oxnas_link_write(ap->host->ports[0], 0x0c, 0x30003);
- if (hd->n_ports > 1)
- sata_oxnas_link_write(ap->host->ports[1], 0x0c, 0x30003);
-
- /* bail out if no device is present */
- if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
- DPRINTK("EXIT, no device\n");
- return;
- }
-
- /* go through all the devices and configure them */
- for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
- if (ap->link.device[dev].class == ATA_DEV_ATA)
- sata_oxnas_dev_config(&(ap->link.device[dev]));
- }
-
- DPRINTK("EXIT\n");
-}
-
-/**
- * Called to read the hardware registers / DMA buffers, to
- * obtain the current set of taskfile register values.
- * @param ap hardware with the registers in
- * @param tf taskfile to read the registers into
- */
-static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
-{
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
- void __iomem *port_base = port_priv->port_base;
- /* read the orb registers */
- u32 Orb1 = ioread32(port_base + ORB1);
- u32 Orb2 = ioread32(port_base + ORB2);
- u32 Orb3 = ioread32(port_base + ORB3);
- u32 Orb4 = ioread32(port_base + ORB4);
-
- /* read common 28/48 bit tf parameters */
- tf->device = (Orb1 >> 24);
- tf->nsect = (Orb2 >> 0);
- tf->feature = (Orb2 >> 16);
- tf->command = sata_oxnas_check_status(ap);
-
- /* read 48 or 28 bit tf parameters */
- if (tf->flags & ATA_TFLAG_LBA48) {
- tf->hob_nsect = (Orb2 >> 8);
- tf->lbal = (Orb3 >> 0);
- tf->lbam = (Orb3 >> 8);
- tf->lbah = (Orb3 >> 16);
- tf->hob_lbal = (Orb3 >> 24);
- tf->hob_lbam = (Orb4 >> 0);
- tf->hob_lbah = (Orb4 >> 8);
- /* feature ext and control are write only */
- } else {
- /* read 28-bit lba */
- tf->lbal = (Orb3 >> 0);
- tf->lbam = (Orb3 >> 8);
- tf->lbah = (Orb3 >> 16);
- }
-}
-
-/**
- * Read a result task-file from the sata core registers.
- */
-static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)
-{
- /* Read the most recently received FIS from the SATA core ORB registers
- and convert to an ATA taskfile */
- sata_oxnas_tf_read(qc->ap, &qc->result_tf);
- return true;
-}
-
-/**
- * Reads the Status ATA shadow register from hardware.
- *
- * @return The status register
- */
-static u8 sata_oxnas_check_status(struct ata_port *ap)
-{
- u32 Reg;
- u8 status;
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
- void __iomem *port_base = port_priv->port_base;
-
- /* read byte 3 of Orb2 register */
- status = ioread32(port_base + ORB2) >> 24;
-
- /* check for the drive going missing indicated by SCR status bits
- * 0-3 = 0 */
- sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);
-
- if (!(Reg & 0x1)) {
- status |= ATA_DF;
- status |= ATA_ERR;
- }
-
- return status;
-}
-
-static inline void sata_oxnas_reset_ucode(struct ata_host *ah, int force,
- int no_microcode)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- DPRINTK("ENTER\n");
- if (no_microcode) {
- u32 reg;
-
- sata_oxnas_set_mode(ah, UNKNOWN_MODE, force);
- reg = ioread32(hd->core_base + DEVICE_CONTROL);
- reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;
- iowrite32(reg, hd->core_base + DEVICE_CONTROL);
- } else {
- /* JBOD uCode */
- sata_oxnas_set_mode(ah, OXNASSATA_NOTRAID, force);
- /* Turn the work around off as it may have been left on by any
- * HW-RAID code that we've been working with */
- iowrite32(0x0, hd->core_base + PORT_ERROR_MASK);
- }
-}
-
-/**
- * Prepare as much as possible for a command without involving anything that is
- * shared between ports.
- */
-static enum ata_completion_errors sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
-{
- struct sata_oxnas_port_priv *pd;
- int port_no = qc->ap->port_no;
-
- /* if the port's not connected, complete now with an error */
- if (!sata_oxnas_check_link(qc->ap)) {
- ata_port_err(qc->ap,
- "port %d not connected completing with error\n",
- port_no);
- qc->err_mask |= AC_ERR_ATA_BUS;
- ata_qc_complete(qc);
- }
-
- sata_oxnas_reset_ucode(qc->ap->host, 0, 0);
-
- /* both pio and dma commands use dma */
- if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
-
- /* program the scatterlist into the prd table */
- ata_bmdma_qc_prep(qc);
-
- /* point the sgdma controller at the dma request structure */
- pd = qc->ap->private_data;
-
- iowrite32(pd->sgdma_request_pa,
- pd->sgdma_base + SGDMA_REQUESTPTR);
-
- /* setup the request table */
- if (port_no == 0) {
- pd->sgdma_request->control =
- (qc->dma_dir == DMA_FROM_DEVICE) ?
- SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;
- } else {
- pd->sgdma_request->control =
- (qc->dma_dir == DMA_FROM_DEVICE) ?
- SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;
- }
- pd->sgdma_request->qualifier = SGDMA_REQQUAL;
- pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;
- pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;
- smp_wmb();
-
- /* tell it to wait */
- iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
- }
-
- return AC_ERR_OK;
-}
-
-static int sata_oxnas_port_start(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
- struct device *dev = ap->host->dev;
- struct sata_oxnas_port_priv *pp;
- void *mem;
- dma_addr_t mem_dma;
-
- DPRINTK("ENTER\n");
-
- pp = kzalloc(sizeof(*pp), GFP_KERNEL);
- if (!pp)
- return -ENOMEM;
-
- pp->port_base = host_priv->port_base +
- (ap->port_no ? PORT_SIZE : 0);
- pp->dmactl_base = host_priv->dmactl_base +
- (ap->port_no ? DMA_CORESIZE : 0);
- pp->sgdma_base = host_priv->sgdma_base +
- (ap->port_no ? SGDMA_CORESIZE : 0);
- pp->core_base = host_priv->core_base;
-
- /* preallocated */
- if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * host_priv->n_ports) {
- DPRINTK("using preallocated DMA\n");
- mem_dma = host_priv->dma_base +
- (ap->port_no ? SATA_OXNAS_DMA_SIZE : 0);
- mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);
- } else {
- mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,
- GFP_KERNEL);
- }
- if (!mem)
- goto err_ret;
-
- pp->sgdma_request_pa = mem_dma;
- pp->sgdma_request = mem;
-
- ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);
- ap->bmdma_prd = mem + sizeof(struct sgdma_request);
-
- ap->private_data = pp;
-
- sata_oxnas_post_reset_init(ap);
-
- return 0;
-
-err_ret:
- kfree(pp);
- return -ENOMEM;
-
-}
-
-static void sata_oxnas_port_stop(struct ata_port *ap)
-{
- struct device *dev = ap->host->dev;
- struct sata_oxnas_port_priv *pp = ap->private_data;
- struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
-
- DPRINTK("ENTER\n");
- ap->private_data = NULL;
- if (host_priv->dma_size) {
- iounmap(pp->sgdma_request);
- } else {
- dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,
- pp->sgdma_request, pp->sgdma_request_pa);
- }
-
- kfree(pp);
-}
-
-
-static void sata_oxnas_post_reset_init(struct ata_port *ap)
-{
- uint dev;
-
- /* force to load u-code only once after reset */
- sata_oxnas_reset_ucode(ap->host, !ap->port_no, 0);
-
- /* turn on phy error detection by removing the masks */
- sata_oxnas_link_write(ap, 0x0C, 0x30003);
-
- /* enable hotplug event detection */
- sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
- sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);
- sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));
-
- /* enable interrupts for ports */
- sata_oxnas_irq_on(ap);
-
- /* go through all the devices and configure them */
- for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
- if (ap->link.device[dev].class == ATA_DEV_ATA) {
- sata_std_hardreset(&ap->link, NULL, jiffies + HZ);
- sata_oxnas_dev_config(&(ap->link.device[dev]));
- }
- }
-
- /* clean up any remaining errors */
- sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
- VPRINTK("done\n");
-}
-
-/**
- * host_stop() is called when the rmmod or hot unplug process begins. The
- * hook must stop all hardware interrupts, DMA engines, etc.
- *
- * @param ap hardware with the registers in
- */
-static void sata_oxnas_host_stop(struct ata_host *host_set)
-{
- DPRINTK("\n");
-}
-
-
-#define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
-static void sata_oxnas_error_handler(struct ata_port *ap)
-{
- DPRINTK("Enter port_no %d\n", ap->port_no);
- sata_oxnas_freeze_host(ap);
-
- /* If the core is busy here, make it idle */
- sata_oxnas_cleanup(ap->host);
-
- ata_std_error_handler(ap);
-
- sata_oxnas_thaw_host(ap);
-}
-
-static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
- unsigned long deadline)
-{
- struct ata_port *ap = link->ap;
- struct sata_oxnas_port_priv *pd = ap->private_data;
- void __iomem *port_base = pd->port_base;
- int rc;
-
- struct ata_taskfile tf;
- u32 Command_Reg;
-
- DPRINTK("ENTER\n");
-
- port_base = pd->port_base;
-
- if (ata_link_offline(link)) {
- DPRINTK("PHY reports no device\n");
- *class = ATA_DEV_NONE;
- goto out;
- }
-
- /* write value to register */
- iowrite32(0, port_base + ORB1);
- iowrite32(0, port_base + ORB2);
- iowrite32(0, port_base + ORB3);
- iowrite32((ap->ctl) << 24, port_base + ORB4);
-
- /* command the core to send a control FIS */
- Command_Reg = ioread32(port_base + SATA_COMMAND);
- Command_Reg &= ~SATA_OPCODE_MASK;
- Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- iowrite32(Command_Reg, port_base + SATA_COMMAND);
- udelay(20); /* FIXME: flush */
-
- /* write value to register */
- iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);
-
- /* command the core to send a control FIS */
- Command_Reg &= ~SATA_OPCODE_MASK;
- Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- iowrite32(Command_Reg, port_base + SATA_COMMAND);
- udelay(20); /* FIXME: flush */
-
- /* write value to register */
- iowrite32((ap->ctl) << 24, port_base + ORB4);
-
- /* command the core to send a control FIS */
- Command_Reg &= ~SATA_OPCODE_MASK;
- Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- iowrite32(Command_Reg, port_base + SATA_COMMAND);
-
- msleep(150);
-
- rc = ata_sff_wait_ready(link, deadline);
-
- /* if link is occupied, -ENODEV too is an error */
- if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
- ata_link_err(link, "SRST failed (errno=%d)\n", rc);
- return rc;
- }
-
- /* determine by signature whether we have ATA or ATAPI devices */
- sata_oxnas_tf_read(ap, &tf);
- *class = ata_dev_classify(&tf);
-
- if (*class == ATA_DEV_UNKNOWN)
- *class = ATA_DEV_NONE;
-
-out:
- DPRINTK("EXIT, class=%u\n", *class);
- return 0;
-}
-
-
-int sata_oxnas_init_controller(struct ata_host *host)
-{
- return 0;
-}
-
-/**
- * Ref bug-6320
- *
- * This code is a work around for a DMA hardware bug that will repeat the
- * penultimate 8-bytes on some reads. This code will check that the amount
- * of data transferred is a multiple of 512 bytes, if not the in it will
- * fetch the correct data from a buffer in the SATA core and copy it into
- * memory.
- *
- * @param port SATA port to check and if necessary, correct.
- */
-static int sata_oxnas_bug_6320_detect(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- void __iomem *core_base = pd->core_base;
- int is_read;
- int quads_transferred;
- int remainder;
- int sector_quads_remaining;
- int bug_present = 0;
-
- /* Only want to apply fix to reads */
- is_read = !(ioread32(core_base + DM_DBG1) & (ap->port_no ?
- BIT(CORE_PORT1_DATA_DIR_BIT) :
- BIT(CORE_PORT0_DATA_DIR_BIT)));
-
- /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
- transferred (datacount_port register counts quads transferred) */
- quads_transferred =
- ioread32(core_base + (ap->port_no ?
- DATACOUNT_PORT1 : DATACOUNT_PORT0));
-
- remainder = quads_transferred & 0x7f;
- sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
-
- if (is_read && (sector_quads_remaining == 2)) {
- bug_present = 1;
- } else if (sector_quads_remaining) {
- if (is_read) {
- ata_port_warn(ap, "SATA read fixup cannot deal with "
- "%d quads remaining\n",
- sector_quads_remaining);
- } else {
- ata_port_warn(ap, "SATA write fixup of %d quads "
- "remaining not supported\n",
- sector_quads_remaining);
- }
- }
-
- return bug_present;
-}
-
-/* This port done an interrupt */
-static void sata_oxnas_port_irq(struct ata_port *ap, int force_error)
-{
- struct ata_queued_cmd *qc;
- struct sata_oxnas_port_priv *pd = ap->private_data;
- void __iomem *port_base = pd->port_base;
-
- u32 int_status;
- unsigned long flags = 0;
-
- DPRINTK("ENTER port %d irqstatus %x\n", ap->port_no,
- ioread32(port_base + INT_STATUS));
-
- if (ap->qc_active & (1ULL << ATA_TAG_INTERNAL)) {
- qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
- DPRINTK("completing non-ncq cmd\n");
-
- if (qc)
- ata_qc_complete(qc);
-
- return;
- }
-
- qc = ata_qc_from_tag(ap, ap->link.active_tag);
-
-
- /* record the port's interrupt */
- int_status = ioread32(port_base + INT_STATUS);
-
- /* If there's no command associated with this IRQ, ignore it. We may get
- * spurious interrupts when cleaning-up after a failed command, ignore
- * these too. */
- if (likely(qc)) {
- /* get the status before any error cleanup */
- qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));
- if (force_error) {
- /* Pretend there has been a link error */
- qc->err_mask |= AC_ERR_ATA_BUS;
- DPRINTK(" ####force error####\n");
- }
- /* tell libata we're done */
- local_irq_save(flags);
- sata_oxnas_irq_clear(ap);
- local_irq_restore(flags);
- ata_qc_complete(qc);
- } else {
- VPRINTK("Ignoring interrupt, can't find the command tag="
- "%d %08x\n", ap->link.active_tag, ap->qc_active);
- }
-
- /* maybe a hotplug event */
- if (unlikely(int_status & INT_LINK_SERROR)) {
- u32 serror;
-
- sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);
- if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
- ata_ehi_hotplugged(&ap->link.eh_info);
- ata_port_freeze(ap);
- }
- }
-}
-
-/**
- * irq_handler is the interrupt handling routine registered with the system,
- * by libata.
- */
-static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)
-{
- struct ata_host *ah = dev_instance;
- struct sata_oxnas_host_priv *hd = ah->private_data;
- void __iomem *core_base = hd->core_base;
-
- u32 int_status;
- irqreturn_t ret = IRQ_NONE;
- u32 port_no;
- u32 mask;
- int bug_present;
-
- /* loop until there are no more interrupts */
- while ((int_status = (ioread32(core_base + CORE_INT_STATUS)) &
- (COREINT_END | (COREINT_END << 1)))) {
-
- /* clear any interrupt */
- iowrite32(int_status, core_base + CORE_INT_CLEAR);
-
- /* Only need workaround_bug_6320 for single disk systems as dual
- * disk will use uCode which prevents this read underrun problem
- * from occurring.
- * All single disk systems will use port 0 */
- for (port_no = 0; port_no < hd->n_ports; ++port_no) {
- /* check the raw end of command interrupt to see if the
- * port is done */
- mask = (COREINT_END << port_no);
- if (!(int_status & mask))
- continue;
-
- /* this port had an interrupt, clear it */
- iowrite32(mask, core_base + CORE_INT_CLEAR);
- /* check for bug 6320 only if no microcode was loaded */
- bug_present = (hd->current_ucode == UNKNOWN_MODE) &&
- sata_oxnas_bug_6320_detect(ah->ports[port_no]);
-
- sata_oxnas_port_irq(ah->ports[port_no],
- bug_present);
- ret = IRQ_HANDLED;
- }
- }
-
- return ret;
-}
-
-/*
- * scsi mid-layer and libata interface structures
- */
-static struct scsi_host_template sata_oxnas_sht = {
- ATA_NCQ_SHT("sata_oxnas"),
- .can_queue = SATA_OXNAS_QUEUE_DEPTH,
- .sg_tablesize = SATA_OXNAS_MAX_PRD,
- .dma_boundary = ATA_DMA_BOUNDARY,
-};
-
-
-static struct ata_port_operations sata_oxnas_ops = {
- .inherits = &sata_port_ops,
- .qc_prep = sata_oxnas_qc_prep,
- .qc_issue = sata_oxnas_qc_issue,
- .qc_fill_rtf = sata_oxnas_qc_fill_rtf,
- .qc_new = sata_oxnas_qc_new,
- .qc_free = sata_oxnas_qc_free,
-
- .scr_read = sata_oxnas_scr_read,
- .scr_write = sata_oxnas_scr_write,
-
- .freeze = sata_oxnas_freeze,
- .thaw = sata_oxnas_thaw,
- .softreset = sata_oxnas_softreset,
- /* .hardreset = sata_oxnas_hardreset, */
- .postreset = sata_oxnas_postreset,
- .error_handler = sata_oxnas_error_handler,
- .post_internal_cmd = sata_oxnas_post_internal_cmd,
-
- .port_start = sata_oxnas_port_start,
- .port_stop = sata_oxnas_port_stop,
-
- .host_stop = sata_oxnas_host_stop,
- /* .pmp_attach = sata_oxnas_pmp_attach, */
- /* .pmp_detach = sata_oxnas_pmp_detach, */
- .sff_check_status = sata_oxnas_check_status,
- .acquire_hw = sata_oxnas_acquire_hw,
-};
-
-static const struct ata_port_info sata_oxnas_port_info = {
- .flags = SATA_OXNAS_HOST_FLAGS,
- .pio_mask = ATA_PIO4,
- .udma_mask = ATA_UDMA6,
- .port_ops = &sata_oxnas_ops,
-};
-
-static int sata_oxnas_probe(struct platform_device *ofdev)
-{
- int retval = -ENXIO;
- int n_ports = 0;
- void __iomem *port_base = NULL;
- void __iomem *dmactl_base = NULL;
- void __iomem *sgdma_base = NULL;
- void __iomem *core_base = NULL;
- void __iomem *phy_base = NULL;
- struct reset_control *rstc;
-
- struct resource res = {};
- struct sata_oxnas_host_priv *host_priv = NULL;
- int irq = 0;
- struct ata_host *host = NULL;
- struct clk *clk = NULL;
-
- const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };
-
- of_property_read_u32(ofdev->dev.of_node, "nr-ports", &n_ports);
- if (n_ports < 1 || n_ports > SATA_OXNAS_MAX_PORTS)
- goto error_exit_with_cleanup;
-
- port_base = of_iomap(ofdev->dev.of_node, 0);
- if (!port_base)
- goto error_exit_with_cleanup;
-
- dmactl_base = of_iomap(ofdev->dev.of_node, 1);
- if (!dmactl_base)
- goto error_exit_with_cleanup;
-
- sgdma_base = of_iomap(ofdev->dev.of_node, 2);
- if (!sgdma_base)
- goto error_exit_with_cleanup;
-
- core_base = of_iomap(ofdev->dev.of_node, 3);
- if (!core_base)
- goto error_exit_with_cleanup;
-
- phy_base = of_iomap(ofdev->dev.of_node, 4);
- if (!phy_base)
- goto error_exit_with_cleanup;
-
- host_priv = devm_kzalloc(&ofdev->dev,
- sizeof(struct sata_oxnas_host_priv),
- GFP_KERNEL);
- if (!host_priv)
- goto error_exit_with_cleanup;
-
- host_priv->port_base = port_base;
- host_priv->dmactl_base = dmactl_base;
- host_priv->sgdma_base = sgdma_base;
- host_priv->core_base = core_base;
- host_priv->phy_base = phy_base;
- host_priv->n_ports = n_ports;
- host_priv->current_ucode = UNKNOWN_MODE;
-
- if (!of_address_to_resource(ofdev->dev.of_node, 5, &res)) {
- host_priv->dma_base = res.start;
- host_priv->dma_size = resource_size(&res);
- }
-
- irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
- if (!irq) {
- dev_err(&ofdev->dev, "invalid irq from platform\n");
- goto error_exit_with_cleanup;
- }
- host_priv->irq = irq;
-
- clk = of_clk_get(ofdev->dev.of_node, 0);
- if (IS_ERR(clk)) {
- retval = PTR_ERR(clk);
- clk = NULL;
- goto error_exit_with_cleanup;
- }
- host_priv->clk = clk;
-
- rstc = devm_reset_control_get(&ofdev->dev, "sata");
- if (IS_ERR(rstc)) {
- retval = PTR_ERR(rstc);
- goto error_exit_with_cleanup;
- }
- host_priv->rst_sata = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "link");
- if (IS_ERR(rstc)) {
- retval = PTR_ERR(rstc);
- goto error_exit_with_cleanup;
- }
- host_priv->rst_link = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "phy");
- if (IS_ERR(rstc)) {
- retval = PTR_ERR(rstc);
- goto error_exit_with_cleanup;
- }
- host_priv->rst_phy = rstc;
-
- /* allocate host structure */
- host = ata_host_alloc_pinfo(&ofdev->dev, ppi, n_ports);
-
- if (!host) {
- retval = -ENOMEM;
- goto error_exit_with_cleanup;
- }
- host->private_data = host_priv;
- host->iomap = port_base;
-
- /* initialize core locking and queues */
- init_waitqueue_head(&host_priv->fast_wait_queue);
- init_waitqueue_head(&host_priv->scsi_wait_queue);
- spin_lock_init(&host_priv->phy_lock);
- spin_lock_init(&host_priv->core_lock);
- host_priv->core_locked = 0;
- host_priv->reentrant_port_no = -1;
- host_priv->hw_lock_count = 0;
- host_priv->direct_lock_count = 0;
- host_priv->locker_uid = 0;
- host_priv->current_locker_type = SATA_UNLOCKED;
- host_priv->isr_arg = NULL;
- host_priv->isr_callback = NULL;
-
- /* initialize host controller */
- retval = sata_oxnas_init_controller(host);
- if (retval)
- goto error_exit_with_cleanup;
-
- /*
- * Now, register with libATA core, this will also initiate the
- * device discovery process, invoking our port_start() handler &
- * error_handler() to execute a dummy softreset EH session
- */
- ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,
- &sata_oxnas_sht);
-
- return 0;
-
-error_exit_with_cleanup:
- if (irq)
- irq_dispose_mapping(host_priv->irq);
- if (clk)
- clk_put(clk);
- if (host)
- ata_host_detach(host);
- if (port_base)
- iounmap(port_base);
- if (sgdma_base)
- iounmap(sgdma_base);
- if (core_base)
- iounmap(core_base);
- if (phy_base)
- iounmap(phy_base);
- return retval;
-}
-
-
-static int sata_oxnas_remove(struct platform_device *ofdev)
-{
- struct ata_host *host = dev_get_drvdata(&ofdev->dev);
- struct sata_oxnas_host_priv *host_priv = host->private_data;
-
- ata_host_detach(host);
-
- irq_dispose_mapping(host_priv->irq);
- iounmap(host_priv->port_base);
- iounmap(host_priv->sgdma_base);
- iounmap(host_priv->core_base);
-
- /* reset Controller, Link and PHY */
- reset_control_assert(host_priv->rst_sata);
- reset_control_assert(host_priv->rst_link);
- reset_control_assert(host_priv->rst_phy);
-
- /* Disable the clock to the SATA block */
- clk_disable_unprepare(host_priv->clk);
- clk_put(host_priv->clk);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)
-{
- struct ata_host *host = dev_get_drvdata(&op->dev);
-
- return ata_host_suspend(host, state);
-}
-
-static int sata_oxnas_resume(struct platform_device *op)
-{
- struct ata_host *host = dev_get_drvdata(&op->dev);
- int ret;
-
- ret = sata_oxnas_init_controller(host);
- if (ret) {
- dev_err(&op->dev, "Error initializing hardware\n");
- return ret;
- }
- ata_host_resume(host);
- return 0;
-}
-#endif
-
-
-
-static struct of_device_id oxnas_sata_match[] = {
- {
- .compatible = "plxtech,nas782x-sata",
- },
- {},
-};
-
-MODULE_DEVICE_TABLE(of, oxnas_sata_match);
-
-static struct platform_driver oxnas_sata_driver = {
- .driver = {
- .name = "oxnas-sata",
- .owner = THIS_MODULE,
- .of_match_table = oxnas_sata_match,
- },
- .probe = sata_oxnas_probe,
- .remove = sata_oxnas_remove,
-#ifdef CONFIG_PM
- .suspend = sata_oxnas_suspend,
- .resume = sata_oxnas_resume,
-#endif
-};
-
-module_platform_driver(oxnas_sata_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_VERSION("1.0");
-MODULE_AUTHOR("Oxford Semiconductor Ltd.");
-MODULE_DESCRIPTION("low-level driver for Oxford 934 SATA core");
+++ /dev/null
-/*
- * PCIe driver for PLX NAS782X SoCs
- *
- * Author: Ma Haijun <mahaijuns@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/mbus.h>
-#include <linux/mfd/syscon.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_gpio.h>
-#include <linux/of_irq.h>
-#include <linux/of_pci.h>
-#include <linux/of_platform.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/phy.h>
-#include <linux/phy/phy.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../pci.h"
-
-#define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114
-
-static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val |= mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_value_mask(void __iomem *p,
- unsigned mask, unsigned new_value)
-{
- /* TODO sanity check mask & new_value = new_value */
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- val |= new_value;
- writel_relaxed(val, p);
-}
-
-#define VERSION_ID_MAGIC 0x082510b5
-#define LINK_UP_TIMEOUT_SECONDS 1
-#define NUM_CONTROLLERS 1
-
-enum {
- PCIE_DEVICE_TYPE_MASK = 0x0F,
- PCIE_DEVICE_TYPE_ENDPOINT = 0,
- PCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1,
- PCIE_DEVICE_TYPE_ROOT = 4,
-
- PCIE_LTSSM = BIT(4),
- PCIE_READY_ENTR_L23 = BIT(9),
- PCIE_LINK_UP = BIT(11),
- PCIE_OBTRANS = BIT(12),
-};
-
-/* core config registers */
-enum {
- PCI_CONFIG_VERSION_DEVICEID = 0,
- PCI_CONFIG_COMMAND_STATUS = 4,
-};
-
-/* inbound config registers */
-enum {
- IB_ADDR_XLATE_ENABLE = 0xFC,
-
- /* bits */
- ENABLE_IN_ADDR_TRANS = BIT(0),
-};
-
-/* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */
-enum {
- PCIE_POM0_MEM_ADDR = 0,
- PCIE_POM1_MEM_ADDR = 4,
- PCIE_IN0_MEM_ADDR = 8,
- PCIE_IN1_MEM_ADDR = 12,
- PCIE_IN_IO_ADDR = 16,
- PCIE_IN_CFG0_ADDR = 20,
- PCIE_IN_CFG1_ADDR = 24,
- PCIE_IN_MSG_ADDR = 28,
- PCIE_IN0_MEM_LIMIT = 32,
- PCIE_IN1_MEM_LIMIT = 36,
- PCIE_IN_IO_LIMIT = 40,
- PCIE_IN_CFG0_LIMIT = 44,
- PCIE_IN_CFG1_LIMIT = 48,
- PCIE_IN_MSG_LIMIT = 52,
- PCIE_AHB_SLAVE_CTRL = 56,
-
- PCIE_SLAVE_BE_SHIFT = 22,
-};
-
-#define PCIE_SLAVE_BE(val) ((val) << PCIE_SLAVE_BE_SHIFT)
-#define PCIE_SLAVE_BE_MASK PCIE_SLAVE_BE(0xF)
-
-struct oxnas_pcie_shared {
- /* seems all access are serialized, no lock required */
- int refcount;
-};
-
-/* Structure representing one PCIe interfaces */
-struct oxnas_pcie {
- void __iomem *cfgbase;
- void __iomem *base;
- void __iomem *inbound;
- struct regmap *sys_ctrl;
- unsigned int outbound_offset;
- unsigned int pcie_ctrl_offset;
- struct phy *phy;
- int haslink;
- struct platform_device *pdev;
- struct resource io;
- struct resource cfg;
- struct resource pre_mem; /* prefetchable */
- struct resource non_mem; /* non-prefetchable */
- struct resource busn; /* max available bus numbers */
- int card_reset; /* gpio pin, optional */
- unsigned hcsl_en; /* hcsl pci enable bit */
- struct clk *clk;
- struct clk *busclk; /* for pcie bus, actually the PLLB */
- void *private_data[1];
- spinlock_t lock;
-};
-
-static struct oxnas_pcie_shared pcie_shared = {
- .refcount = 0,
-};
-
-static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys)
-{
- return sys->private_data;
-}
-
-
-static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
-{
- regmap_update_bits(pcie->sys_ctrl, pcie->outbound_offset + PCIE_AHB_SLAVE_CTRL,
- PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));
- wmb();
-}
-
-static int oxnas_pcie_link_up(struct oxnas_pcie *pcie)
-{
- unsigned long end;
- unsigned int val;
-
- /* Poll for PCIE link up */
- end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);
- while (!time_after(jiffies, end)) {
- regmap_read(pcie->sys_ctrl, pcie->pcie_ctrl_offset, &val);
- if (val & PCIE_LINK_UP)
- return 1;
- }
- return 0;
-}
-
-static void oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
-{
- /* We won't have any inbound address translation. This allows PCI
- * devices to access anywhere in the AHB address map. Might be regarded
- * as a bit dangerous, but let's get things working before we worry
- * about that
- */
- oxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE,
- ENABLE_IN_ADDR_TRANS);
- wmb();
-
- /*
- * Program outbound translation windows
- *
- * Outbound window is what is referred to as "PCI client" region in HRM
- *
- * Could use the larger alternative address space to get >>64M regions
- * for graphics cards etc., but will not bother at this point.
- *
- * IP bug means that AMBA window size must be a power of 2
- *
- * Set mem0 window for first 16MB of outbound window non-prefetchable
- * Set mem1 window for second 16MB of outbound window prefetchable
- * Set io window for next 16MB of outbound window
- * Set cfg0 for final 1MB of outbound window
- *
- * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for
- * 820 that would need them
- *
- * Probably ideally want no offset between mem0 window start as seen by
- * ARM and as seen on PCI bus and get Linux to assign memory regions to
- * PCI devices using the same "PCI client" region start address as seen
- * by ARM
- */
-
- /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_ADDR, pcie->non_mem.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_LIMIT, pcie->non_mem.end);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM0_MEM_ADDR, pcie->non_mem.start);
-
- /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_ADDR, pcie->pre_mem.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_LIMIT, pcie->pre_mem.end);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM1_MEM_ADDR, pcie->pre_mem.start);
-
- /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_ADDR, pcie->io.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_LIMIT, pcie->io.end);
-
-
- /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_ADDR, pcie->cfg.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_LIMIT, pcie->cfg.end);
- wmb();
-
- /* Enable outbound address translation */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, PCIE_OBTRANS, PCIE_OBTRANS);
- wmb();
-
- /*
- * Program PCIe command register for core to:
- * enable memory space
- * enable bus master
- * enable io
- */
- writel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS);
- /* which is which */
- wmb();
-}
-
-static unsigned oxnas_pcie_cfg_to_offset(
- struct pci_sys_data *sys,
- unsigned char bus_number,
- unsigned int devfn,
- int where)
-{
- unsigned int function = PCI_FUNC(devfn);
- unsigned int slot = PCI_SLOT(devfn);
- unsigned char bus_number_offset;
-
- bus_number_offset = bus_number - sys->busnr;
-
- /*
- * We'll assume for now that the offset, function, slot, bus encoding
- * should map onto linear, contiguous addresses in PCIe config space,
- * albeit that the majority will be unused as only slot 0 is valid for
- * any PCIe bus and most devices have only function 0
- *
- * Could be that PCIe in fact works by not encoding the slot number into
- * the config space address as it's known that only slot 0 is valid.
- * We'll have to experiment if/when we get a PCIe switch connected to
- * the PCIe host
- */
- return (bus_number_offset << 20) | (slot << 15) | (function << 12) |
- (where & ~3);
-}
-
-/* PCI configuration space write function */
-static int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
- int where, int size, u32 val)
-{
- unsigned long flags;
- struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
- unsigned offset;
- u32 value;
- u32 lanes;
-
- /* Only a single device per bus for PCIe point-to-point links */
- if (PCI_SLOT(devfn) > 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- if (!pcie->haslink)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
- where);
-
- value = val << (8 * (where & 3));
- lanes = (0xf >> (4-size)) << (where & 3);
- /* it race with mem and io write, but the possibility is low, normally
- * all config writes happens at driver initialize stage, wont interleave
- * with others.
- * and many pcie cards use dword (4bytes) access mem/io access only,
- * so not bother to copy that ugly work-around now. */
- spin_lock_irqsave(&pcie->lock, flags);
- set_out_lanes(pcie, lanes);
- writel_relaxed(value, pcie->cfgbase + offset);
- set_out_lanes(pcie, 0xf);
- spin_unlock_irqrestore(&pcie->lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-/* PCI configuration space read function */
-static int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
- int size, u32 *val)
-{
- struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
- unsigned offset;
- u32 value;
- u32 left_bytes, right_bytes;
-
- /* Only a single device per bus for PCIe point-to-point links */
- if (PCI_SLOT(devfn) > 0) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- if (!pcie->haslink) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
- where);
- value = readl_relaxed(pcie->cfgbase + offset);
- left_bytes = where & 3;
- right_bytes = 4 - left_bytes - size;
- value <<= right_bytes * 8;
- value >>= (left_bytes + right_bytes) * 8;
- *val = value;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops oxnas_pcie_ops = {
- .read = oxnas_pcie_rd_conf,
- .write = oxnas_pcie_wr_conf,
-};
-
-static int oxnas_pcie_setup(int nr, struct pci_sys_data *sys)
-{
- struct oxnas_pcie *pcie = sys_to_pcie(sys);
-
- pci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset);
- pci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset);
- pci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset);
- pci_add_resource(&sys->resources, &pcie->busn);
- if (sys->busnr == 0) { /* default one */
- sys->busnr = pcie->busn.start;
- }
- /* do not use devm_ioremap_resource, it does not like cfg resource */
- pcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start,
- resource_size(&pcie->cfg));
- if (!pcie->cfgbase)
- return -ENOMEM;
-
- oxnas_pcie_setup_hw(pcie);
-
- return 1;
-}
-
-static void oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)
-{
- struct hw_pci hw;
- int i;
-
- memset(&hw, 0, sizeof(hw));
- for (i = 0; i < NUM_CONTROLLERS; i++)
- pcie->private_data[i] = pcie;
-
- hw.nr_controllers = NUM_CONTROLLERS;
-/* I think use stack pointer is a bad idea though it is valid in this case */
- hw.private_data = pcie->private_data;
- hw.setup = oxnas_pcie_setup;
- hw.map_irq = of_irq_parse_and_map_pci;
- hw.ops = &oxnas_pcie_ops;
-
- /* pass dev to maintain of tree, interrupt mapping rely on this */
- pci_common_init_dev(dev, &hw);
-}
-
-static int oxnas_pcie_shared_init(struct platform_device *pdev, struct oxnas_pcie *pcie)
-{
- if (++pcie_shared.refcount == 1) {
- phy_init(pcie->phy);
- phy_power_on(pcie->phy);
- return 0;
- } else {
- return 0;
- }
-}
-
-#if 0
-/* maybe we will call it when enter low power state */
-static void oxnas_pcie_shared_deinit(struct platform_device *pdev)
-{
- if (--pcie_shared.refcount == 0) {
- /* no cleanup needed */;
- }
-}
-#endif
-
-static int
-oxnas_pcie_map_registers(struct platform_device *pdev,
- struct device_node *np,
- struct oxnas_pcie *pcie)
-{
- struct resource regs;
- int ret = 0;
- u32 outbound_ctrl_offset;
- u32 pcie_ctrl_offset;
-
- ret = of_address_to_resource(np, 0, ®s);
- if (ret) {
- dev_err(&pdev->dev, "failed to parse base register space\n");
- return -EINVAL;
- }
-
- pcie->base = devm_ioremap_resource(&pdev->dev, ®s);
- if (!pcie->base) {
- dev_err(&pdev->dev, "failed to map base register space\n");
- return -ENOMEM;
- }
-
- ret = of_address_to_resource(np, 1, ®s);
- if (ret) {
- dev_err(&pdev->dev, "failed to parse inbound register space\n");
- return -EINVAL;
- }
-
- pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s);
- if (!pcie->inbound) {
- dev_err(&pdev->dev, "failed to map inbound register space\n");
- return -ENOMEM;
- }
-
- pcie->phy = devm_of_phy_get(&pdev->dev, np, NULL);
- if (IS_ERR(pcie->phy)) {
- if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) {
- dev_err(&pdev->dev, "failed to probe phy\n");
- return PTR_ERR(pcie->phy);
- }
- dev_warn(&pdev->dev, "phy not attached\n");
- pcie->phy = NULL;
- }
-
- if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
- &outbound_ctrl_offset)) {
- dev_err(&pdev->dev, "failed to parse outbound register offset\n");
- return -EINVAL;
- }
- pcie->outbound_offset = outbound_ctrl_offset;
-
- if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
- &pcie_ctrl_offset)) {
- dev_err(&pdev->dev, "failed to parse pcie-ctrl register offset\n");
- return -EINVAL;
- }
- pcie->pcie_ctrl_offset = pcie_ctrl_offset;
-
- return 0;
-}
-
-static int oxnas_pcie_init_res(struct platform_device *pdev,
- struct oxnas_pcie *pcie,
- struct device_node *np)
-{
- struct of_pci_range range;
- struct of_pci_range_parser parser;
- int ret;
-
- if (of_pci_range_parser_init(&parser, np))
- return -EINVAL;
-
- /* Get the I/O and memory ranges from DT */
- for_each_of_pci_range(&parser, &range) {
-
- unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
- if (restype == IORESOURCE_IO) {
- of_pci_range_to_resource(&range, np, &pcie->io);
- pcie->io.name = "I/O";
- }
- if (restype == IORESOURCE_MEM) {
- if (range.flags & IORESOURCE_PREFETCH) {
- of_pci_range_to_resource(&range, np, &pcie->pre_mem);
- pcie->pre_mem.name = "PRE MEM";
- } else {
- of_pci_range_to_resource(&range, np, &pcie->non_mem);
- pcie->non_mem.name = "NON MEM";
- }
-
- }
- if (restype == 0)
- of_pci_range_to_resource(&range, np, &pcie->cfg);
- }
-
- /* Get the bus range */
- ret = of_pci_parse_bus_range(np, &pcie->busn);
-
- if (ret) {
- dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
- ret);
- return ret;
- }
-
- pcie->card_reset = of_get_gpio(np, 0);
- if (pcie->card_reset < 0)
- dev_info(&pdev->dev, "card reset gpio pin not exists\n");
-
- if (of_property_read_u32(np, "plxtech,pcie-hcsl-bit", &pcie->hcsl_en))
- return -EINVAL;
-
- pcie->clk = of_clk_get_by_name(np, "pcie");
- if (IS_ERR(pcie->clk)) {
- return PTR_ERR(pcie->clk);
- }
-
- pcie->busclk = of_clk_get_by_name(np, "busclk");
- if (IS_ERR(pcie->busclk)) {
- clk_put(pcie->clk);
- return PTR_ERR(pcie->busclk);
- }
-
- return 0;
-}
-
-static void oxnas_pcie_init_hw(struct platform_device *pdev,
- struct oxnas_pcie *pcie)
-{
- u32 version_id;
- int ret;
-
- clk_prepare_enable(pcie->busclk);
-
- /* reset PCIe cards use hard-wired gpio pin */
- if (pcie->card_reset >= 0 &&
- !gpio_direction_output(pcie->card_reset, 0)) {
- wmb();
- mdelay(10);
- /* must tri-state the pin to pull it up */
- gpio_direction_input(pcie->card_reset);
- wmb();
- mdelay(100);
- }
-
- /* ToDo: use phy power-on port... */
- regmap_update_bits(pcie->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET,
- BIT(pcie->hcsl_en), BIT(pcie->hcsl_en));
-
- /* core */
- ret = device_reset(&pdev->dev);
- if (ret) {
- dev_err(&pdev->dev, "core reset failed %d\n", ret);
- return;
- }
-
- /* Start PCIe core clocks */
- clk_prepare_enable(pcie->clk);
-
- version_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID);
- dev_info(&pdev->dev, "PCIe version/deviceID 0x%x\n", version_id);
-
- if (version_id != VERSION_ID_MAGIC) {
- dev_info(&pdev->dev, "PCIe controller not found\n");
- pcie->haslink = 0;
- return;
- }
-
- /* allow entry to L23 state */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
- PCIE_READY_ENTR_L23, PCIE_READY_ENTR_L23);
-
- /* Set PCIe core into RootCore mode */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
- PCIE_DEVICE_TYPE_MASK, PCIE_DEVICE_TYPE_ROOT);
- wmb();
-
- /* Bring up the PCI core */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
- PCIE_LTSSM, PCIE_LTSSM);
- wmb();
-}
-
-static int oxnas_pcie_probe(struct platform_device *pdev)
-{
- struct oxnas_pcie *pcie;
- struct device_node *np = pdev->dev.of_node;
- int ret;
-
- pcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie),
- GFP_KERNEL);
- if (!pcie)
- return -ENOMEM;
-
- pcie->pdev = pdev;
- pcie->haslink = 1;
- spin_lock_init(&pcie->lock);
-
- pcie->sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
- if (IS_ERR(pcie->sys_ctrl))
- return PTR_ERR(pcie->sys_ctrl);
-
- ret = oxnas_pcie_init_res(pdev, pcie, np);
- if (ret)
- return ret;
- if (pcie->card_reset >= 0) {
- ret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN,
- dev_name(&pdev->dev));
- if (ret) {
- dev_err(&pdev->dev, "cannot request gpio pin %d\n",
- pcie->card_reset);
- return ret;
- }
- }
-
- ret = oxnas_pcie_map_registers(pdev, np, pcie);
- if (ret) {
- dev_err(&pdev->dev, "cannot map registers\n");
- goto err_free_gpio;
- }
-
- ret = oxnas_pcie_shared_init(pdev, pcie);
- if (ret)
- goto err_free_gpio;
-
- /* if hw not found, haslink cleared */
- oxnas_pcie_init_hw(pdev, pcie);
-
- if (pcie->haslink && oxnas_pcie_link_up(pcie)) {
- pcie->haslink = 1;
- dev_info(&pdev->dev, "link up\n");
- } else {
- pcie->haslink = 0;
- dev_info(&pdev->dev, "link down\n");
- }
- /* should we register our controller even when pcie->haslink is 0 ? */
- /* register the controller with framework */
- oxnas_pcie_enable(&pdev->dev, pcie);
-
- return 0;
-
-err_free_gpio:
- if (pcie->card_reset)
- gpio_free(pcie->card_reset);
-
- return ret;
-}
-
-static const struct of_device_id oxnas_pcie_of_match_table[] = {
- { .compatible = "plxtech,nas782x-pcie", },
- {},
-};
-
-static struct platform_driver oxnas_pcie_driver = {
- .driver = {
- .name = "oxnas-pcie",
- .suppress_bind_attrs = true,
- .of_match_table = oxnas_pcie_of_match_table,
- },
- .probe = oxnas_pcie_probe,
-};
-
-builtin_platform_driver(oxnas_pcie_driver);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>
- *
- */
-
-#include <dt-bindings/phy/phy.h>
-#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/mfd/syscon.h>
-#include <linux/phy/phy.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-
-#define ADDR_VAL(val) ((val) & 0xFFFF)
-#define DATA_VAL(val) ((val) & 0xFFFF)
-
-#define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114
-
-enum {
- HCSL_BIAS_ON = BIT(0),
- HCSL_PCIE_EN = BIT(1),
- HCSL_PCIEA_EN = BIT(2),
- HCSL_PCIEB_EN = BIT(3),
-};
-
-enum {
- /* pcie phy reg offset */
- PHY_ADDR = 0,
- PHY_DATA = 4,
- /* phy data reg bits */
- READ_EN = BIT(16),
- WRITE_EN = BIT(17),
- CAP_DATA = BIT(18),
-};
-
-struct oxnas_pcie_phy {
- struct device *dev;
- void __iomem *membase;
- const struct phy_ops *ops;
- struct regmap *sys_ctrl;
- struct reset_control *rstc;
-};
-
-static int oxnas_pcie_phy_init(struct phy *phy)
-{
- struct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy);
- int ret;
-
- /* generate clocks from HCSL buffers, shared parts */
- regmap_write(pciephy->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET, HCSL_BIAS_ON|HCSL_PCIE_EN);
-
- /* Ensure PCIe PHY is properly reset */
- ret = reset_control_reset(pciephy->rstc);
-
- if (ret) {
- dev_err(pciephy->dev, "phy reset failed %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-static int oxnas_pcie_phy_power_on(struct phy *phy)
-{
- struct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy);
-
- /* Enable PCIe Pre-Emphasis: What these value means? */
- writel(ADDR_VAL(0x0014), pciephy->membase + PHY_ADDR);
- writel(DATA_VAL(0xce10) | CAP_DATA, pciephy->membase + PHY_DATA);
- writel(DATA_VAL(0xce10) | WRITE_EN, pciephy->membase + PHY_DATA);
-
- writel(ADDR_VAL(0x2004), pciephy->membase + PHY_ADDR);
- writel(DATA_VAL(0x82c7) | CAP_DATA, pciephy->membase + PHY_DATA);
- writel(DATA_VAL(0x82c7) | WRITE_EN, pciephy->membase + PHY_DATA);
-
- return 0;
-}
-
-static const struct phy_ops ops = {
- .init = oxnas_pcie_phy_init,
- .power_on = oxnas_pcie_phy_power_on,
- .owner = THIS_MODULE,
-};
-
-static int oxnas_pcie_phy_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = pdev->dev.of_node;
- struct phy *generic_phy;
- struct phy_provider *phy_provider;
- struct oxnas_pcie_phy *pciephy;
- struct regmap *sys_ctrl;
- struct reset_control *rstc;
- void __iomem *membase;
-
- membase = of_iomap(np, 0);
- if (IS_ERR(membase))
- return PTR_ERR(membase);
-
- sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
- if (IS_ERR(sys_ctrl))
- return PTR_ERR(sys_ctrl);
-
- rstc = devm_reset_control_get_shared(dev, "phy");
- if (IS_ERR(rstc))
- return PTR_ERR(rstc);
-
- pciephy = devm_kzalloc(dev, sizeof(*pciephy), GFP_KERNEL);
- if (!pciephy)
- return -ENOMEM;
-
- pciephy->sys_ctrl = sys_ctrl;
- pciephy->rstc = rstc;
- pciephy->membase = membase;
- pciephy->dev = dev;
- pciephy->ops = &ops;
-
- generic_phy = devm_phy_create(dev, dev->of_node, pciephy->ops);
- if (IS_ERR(generic_phy)) {
- dev_err(dev, "failed to create PHY\n");
- return PTR_ERR(generic_phy);
- }
-
- phy_set_drvdata(generic_phy, pciephy);
- phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-
- return PTR_ERR_OR_ZERO(phy_provider);
-}
-
-static const struct of_device_id oxnas_pcie_phy_id_table[] = {
- { .compatible = "oxsemi,ox820-pcie-phy" },
- { },
-};
-
-static struct platform_driver oxnas_pcie_phy_driver = {
- .probe = oxnas_pcie_phy_probe,
- .driver = {
- .name = "ox820-pcie-phy",
- .of_match_table = oxnas_pcie_phy_id_table,
- },
-};
-
-builtin_platform_driver(oxnas_pcie_phy_driver);
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * oxnas SoC reset driver
- * based on:
- * Microsemi MIPS SoC reset driver
- * and ox820_assert_system_reset() written by Ma Hajun <mahaijuns@gmail.com>
- *
- * License: GPL
- * Copyright (c) 2013 Ma Hajun <mahaijuns@gmail.com>
- * Copyright (c) 2017 Microsemi Corporation
- * Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>
- */
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/notifier.h>
-#include <linux/mfd/syscon.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/reboot.h>
-#include <linux/regmap.h>
-
-/* bit numbers of reset control register */
-#define OX820_SYS_CTRL_RST_SCU 0
-#define OX820_SYS_CTRL_RST_COPRO 1
-#define OX820_SYS_CTRL_RST_ARM0 2
-#define OX820_SYS_CTRL_RST_ARM1 3
-#define OX820_SYS_CTRL_RST_USBHS 4
-#define OX820_SYS_CTRL_RST_USBHSPHYA 5
-#define OX820_SYS_CTRL_RST_MACA 6
-#define OX820_SYS_CTRL_RST_MAC OX820_SYS_CTRL_RST_MACA
-#define OX820_SYS_CTRL_RST_PCIEA 7
-#define OX820_SYS_CTRL_RST_SGDMA 8
-#define OX820_SYS_CTRL_RST_CIPHER 9
-#define OX820_SYS_CTRL_RST_DDR 10
-#define OX820_SYS_CTRL_RST_SATA 11
-#define OX820_SYS_CTRL_RST_SATA_LINK 12
-#define OX820_SYS_CTRL_RST_SATA_PHY 13
-#define OX820_SYS_CTRL_RST_PCIEPHY 14
-#define OX820_SYS_CTRL_RST_STATIC 15
-#define OX820_SYS_CTRL_RST_GPIO 16
-#define OX820_SYS_CTRL_RST_UART1 17
-#define OX820_SYS_CTRL_RST_UART2 18
-#define OX820_SYS_CTRL_RST_MISC 19
-#define OX820_SYS_CTRL_RST_I2S 20
-#define OX820_SYS_CTRL_RST_SD 21
-#define OX820_SYS_CTRL_RST_MACB 22
-#define OX820_SYS_CTRL_RST_PCIEB 23
-#define OX820_SYS_CTRL_RST_VIDEO 24
-#define OX820_SYS_CTRL_RST_DDR_PHY 25
-#define OX820_SYS_CTRL_RST_USBHSPHYB 26
-#define OX820_SYS_CTRL_RST_USBDEV 27
-#define OX820_SYS_CTRL_RST_ARMDBG 29
-#define OX820_SYS_CTRL_RST_PLLA 30
-#define OX820_SYS_CTRL_RST_PLLB 31
-
-/* bit numbers of clock control register */
-#define OX820_SYS_CTRL_CLK_COPRO 0
-#define OX820_SYS_CTRL_CLK_DMA 1
-#define OX820_SYS_CTRL_CLK_CIPHER 2
-#define OX820_SYS_CTRL_CLK_SD 3
-#define OX820_SYS_CTRL_CLK_SATA 4
-#define OX820_SYS_CTRL_CLK_I2S 5
-#define OX820_SYS_CTRL_CLK_USBHS 6
-#define OX820_SYS_CTRL_CLK_MACA 7
-#define OX820_SYS_CTRL_CLK_MAC OX820_SYS_CTRL_CLK_MACA
-#define OX820_SYS_CTRL_CLK_PCIEA 8
-#define OX820_SYS_CTRL_CLK_STATIC 9
-#define OX820_SYS_CTRL_CLK_MACB 10
-#define OX820_SYS_CTRL_CLK_PCIEB 11
-#define OX820_SYS_CTRL_CLK_REF600 12
-#define OX820_SYS_CTRL_CLK_USBDEV 13
-#define OX820_SYS_CTRL_CLK_DDR 14
-#define OX820_SYS_CTRL_CLK_DDRPHY 15
-#define OX820_SYS_CTRL_CLK_DDRCK 16
-
-/* Regmap offsets */
-#define OX820_CLK_SET_REGOFFSET 0x2c
-#define OX820_CLK_CLR_REGOFFSET 0x30
-#define OX820_RST_SET_REGOFFSET 0x34
-#define OX820_RST_CLR_REGOFFSET 0x38
-#define OX820_SECONDARY_SEL_REGOFFSET 0x14
-#define OX820_TERTIARY_SEL_REGOFFSET 0x8c
-#define OX820_QUATERNARY_SEL_REGOFFSET 0x94
-#define OX820_DEBUG_SEL_REGOFFSET 0x9c
-#define OX820_ALTERNATIVE_SEL_REGOFFSET 0xa4
-#define OX820_PULLUP_SEL_REGOFFSET 0xac
-#define OX820_SEC_SECONDARY_SEL_REGOFFSET 0x100014
-#define OX820_SEC_TERTIARY_SEL_REGOFFSET 0x10008c
-#define OX820_SEC_QUATERNARY_SEL_REGOFFSET 0x100094
-#define OX820_SEC_DEBUG_SEL_REGOFFSET 0x10009c
-#define OX820_SEC_ALTERNATIVE_SEL_REGOFFSET 0x1000a4
-#define OX820_SEC_PULLUP_SEL_REGOFFSET 0x1000ac
-
-
-struct oxnas_restart_context {
- struct regmap *sys_ctrl;
- struct notifier_block restart_handler;
-};
-
-static int ox820_restart_handle(struct notifier_block *this,
- unsigned long mode, void *cmd)
-{
- struct oxnas_restart_context *ctx = container_of(this, struct
- oxnas_restart_context,
- restart_handler);
- u32 value;
-
- /* Assert reset to cores as per power on defaults
- * Don't touch the DDR interface as things will come to an impromptu stop
- * NB Possibly should be asserting reset for PLLB, but there are timing
- * concerns here according to the docs */
- value = BIT(OX820_SYS_CTRL_RST_COPRO) |
- BIT(OX820_SYS_CTRL_RST_USBHS) |
- BIT(OX820_SYS_CTRL_RST_USBHSPHYA) |
- BIT(OX820_SYS_CTRL_RST_MACA) |
- BIT(OX820_SYS_CTRL_RST_PCIEA) |
- BIT(OX820_SYS_CTRL_RST_SGDMA) |
- BIT(OX820_SYS_CTRL_RST_CIPHER) |
- BIT(OX820_SYS_CTRL_RST_SATA) |
- BIT(OX820_SYS_CTRL_RST_SATA_LINK) |
- BIT(OX820_SYS_CTRL_RST_SATA_PHY) |
- BIT(OX820_SYS_CTRL_RST_PCIEPHY) |
- BIT(OX820_SYS_CTRL_RST_STATIC) |
- BIT(OX820_SYS_CTRL_RST_UART1) |
- BIT(OX820_SYS_CTRL_RST_UART2) |
- BIT(OX820_SYS_CTRL_RST_MISC) |
- BIT(OX820_SYS_CTRL_RST_I2S) |
- BIT(OX820_SYS_CTRL_RST_SD) |
- BIT(OX820_SYS_CTRL_RST_MACB) |
- BIT(OX820_SYS_CTRL_RST_PCIEB) |
- BIT(OX820_SYS_CTRL_RST_VIDEO) |
- BIT(OX820_SYS_CTRL_RST_USBHSPHYB) |
- BIT(OX820_SYS_CTRL_RST_USBDEV);
-
- regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
-
- /* Release reset to cores as per power on defaults */
- regmap_write(ctx->sys_ctrl, OX820_RST_CLR_REGOFFSET, BIT(OX820_SYS_CTRL_RST_GPIO));
-
- /* Disable clocks to cores as per power-on defaults - must leave DDR
- * related clocks enabled otherwise we'll stop rather abruptly. */
- value =
- BIT(OX820_SYS_CTRL_CLK_COPRO) |
- BIT(OX820_SYS_CTRL_CLK_DMA) |
- BIT(OX820_SYS_CTRL_CLK_CIPHER) |
- BIT(OX820_SYS_CTRL_CLK_SD) |
- BIT(OX820_SYS_CTRL_CLK_SATA) |
- BIT(OX820_SYS_CTRL_CLK_I2S) |
- BIT(OX820_SYS_CTRL_CLK_USBHS) |
- BIT(OX820_SYS_CTRL_CLK_MAC) |
- BIT(OX820_SYS_CTRL_CLK_PCIEA) |
- BIT(OX820_SYS_CTRL_CLK_STATIC) |
- BIT(OX820_SYS_CTRL_CLK_MACB) |
- BIT(OX820_SYS_CTRL_CLK_PCIEB) |
- BIT(OX820_SYS_CTRL_CLK_REF600) |
- BIT(OX820_SYS_CTRL_CLK_USBDEV);
-
- regmap_write(ctx->sys_ctrl, OX820_CLK_CLR_REGOFFSET, value);
-
- /* Enable clocks to cores as per power-on defaults */
-
- /* Set sys-control pin mux'ing as per power-on defaults */
- regmap_write(ctx->sys_ctrl, OX820_SECONDARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_TERTIARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_QUATERNARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_DEBUG_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_ALTERNATIVE_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_PULLUP_SEL_REGOFFSET, 0);
-
- regmap_write(ctx->sys_ctrl, OX820_SEC_SECONDARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_TERTIARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_QUATERNARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_DEBUG_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_ALTERNATIVE_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_PULLUP_SEL_REGOFFSET, 0);
-
- /* No need to save any state, as the ROM loader can determine whether
- * reset is due to power cycling or programatic action, just hit the
- * (self-clearing) CPU reset bit of the block reset register */
- value =
- BIT(OX820_SYS_CTRL_RST_SCU) |
- BIT(OX820_SYS_CTRL_RST_ARM0) |
- BIT(OX820_SYS_CTRL_RST_ARM1);
-
- regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
-
- pr_emerg("Unable to restart system\n");
- return NOTIFY_DONE;
-}
-
-static int ox820_restart_probe(struct platform_device *pdev)
-{
- struct oxnas_restart_context *ctx;
- struct regmap *sys_ctrl;
- struct device *dev = &pdev->dev;
- int err = 0;
-
- sys_ctrl = syscon_node_to_regmap(pdev->dev.of_node);
- if (IS_ERR(sys_ctrl))
- return PTR_ERR(sys_ctrl);
-
- ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
- if (!ctx)
- return -ENOMEM;
-
- ctx->sys_ctrl = sys_ctrl;
- ctx->restart_handler.notifier_call = ox820_restart_handle;
- ctx->restart_handler.priority = 192;
- err = register_restart_handler(&ctx->restart_handler);
- if (err)
- dev_err(dev, "can't register restart notifier (err=%d)\n", err);
-
- return err;
-}
-
-static const struct of_device_id ox820_restart_of_match[] = {
- { .compatible = "oxsemi,ox820-sys-ctrl" },
- {}
-};
-
-static struct platform_driver ox820_restart_driver = {
- .probe = ox820_restart_probe,
- .driver = {
- .name = "ox820-chip-reset",
- .of_match_table = ox820_restart_of_match,
- },
-};
-builtin_platform_driver(ox820_restart_driver);
+++ /dev/null
-/*
- * drivers/usb/host/ehci-oxnas.c
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/mfd/syscon.h>
-#include <linux/usb.h>
-#include <linux/usb/hcd.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-
-#define USBHSMPH_CTRL_REGOFFSET 0x40
-#define USBHSMPH_STAT_REGOFFSET 0x44
-#define REF300_DIV_REGOFFSET 0xF8
-#define USBHSPHY_CTRL_REGOFFSET 0x84
-#define USB_CTRL_REGOFFSET 0x90
-#define PLLB_DIV_CTRL_REGOFFSET 0x1000F8
-#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16
-#define USBHSPHY_SUSPENDM_MANUAL_STATE 15
-#define USBHSPHY_ATE_ESET 14
-#define USBHSPHY_TEST_DIN 6
-#define USBHSPHY_TEST_ADD 2
-#define USBHSPHY_TEST_DOUT_SEL 1
-#define USBHSPHY_TEST_CLK 0
-
-#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5
-#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-
-#define USBAMUX_DEVICE BIT(4)
-
-#define USBPHY_REFCLKDIV_SHIFT 2
-#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT)
-
-#define USB_CTRL_USB_CKO_SEL_BIT 0
-
-#define USB_INT_CLK_XTAL 0
-#define USB_INT_CLK_REF300 2
-#define USB_INT_CLK_PLLB 3
-
-#define REF300_DIV_INT_SHIFT 8
-#define REF300_DIV_FRAC_SHIFT 0
-#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
-#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
-
-#define PLLB_BYPASS 1
-#define PLLB_ENSAT 3
-#define PLLB_OUTDIV 4
-#define PLLB_REFDIV 8
-#define PLLB_DIV_INT_SHIFT 8
-#define PLLB_DIV_FRAC_SHIFT 0
-#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
-#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
-
-#include "ehci.h"
-
-struct oxnas_hcd {
- struct clk *clk;
- struct clk *refsrc;
- struct clk *phyref;
- int use_pllb;
- int use_phya;
- struct reset_control *rst_host;
- struct reset_control *rst_phya;
- struct reset_control *rst_phyb;
- struct regmap *syscon;
-};
-
-#define DRIVER_DESC "Oxnas On-Chip EHCI Host Controller"
-
-static struct hc_driver __read_mostly oxnas_hc_driver;
-
-static void start_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
-{
- if (oxnas->use_pllb) {
- /* enable pllb */
- clk_prepare_enable(oxnas->refsrc);
- /* enable ref600 */
- clk_prepare_enable(oxnas->phyref);
- /* 600MHz pllb divider for 12MHz */
- regmap_write_bits(oxnas->syscon, PLLB_DIV_CTRL_REGOFFSET, 0xffff, PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0));
- } else {
- /* ref 300 divider for 12MHz */
- regmap_write_bits(oxnas->syscon, REF300_DIV_REGOFFSET, 0xffff, REF300_DIV_INT(25) | REF300_DIV_FRAC(0));
- }
-
- /* Ensure the USB block is properly reset */
- reset_control_reset(oxnas->rst_host);
- reset_control_reset(oxnas->rst_phya);
- reset_control_reset(oxnas->rst_phyb);
-
- /* Force the high speed clock to be generated all the time, via serial
- programming of the USB HS PHY */
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN));
-
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (1UL << USBHSPHY_TEST_CLK) |
- (2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN));
-
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN));
-
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (1UL << USBHSPHY_TEST_CLK) |
- (0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN));
-
- if (oxnas->use_pllb) /* use pllb clock */
- regmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff,
- USB_CLK_INTERNAL | USB_INT_CLK_PLLB);
- else /* use ref300 derived clock */
- regmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff,
- USB_CLK_INTERNAL | USB_INT_CLK_REF300);
-
- if (oxnas->use_phya) {
- /* Configure USB PHYA as a host */
- regmap_update_bits(oxnas->syscon, USB_CTRL_REGOFFSET, USBAMUX_DEVICE, 0);
- }
-
- /* Enable the clock to the USB block */
- clk_prepare_enable(oxnas->clk);
-}
-
-static void stop_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
-{
- reset_control_assert(oxnas->rst_host);
- reset_control_assert(oxnas->rst_phya);
- reset_control_assert(oxnas->rst_phyb);
-
- if (oxnas->use_pllb) {
- clk_disable_unprepare(oxnas->phyref);
- clk_disable_unprepare(oxnas->refsrc);
- }
- clk_disable_unprepare(oxnas->clk);
-}
-
-static int ehci_oxnas_reset(struct usb_hcd *hcd)
-{
- #define txttfill_tuning reserved2[0]
-
- struct ehci_hcd *ehci;
- u32 tmp;
- int retval = ehci_setup(hcd);
- if (retval)
- return retval;
-
- ehci = hcd_to_ehci(hcd);
- tmp = ehci_readl(ehci, &ehci->regs->txfill_tuning);
- tmp &= ~0x00ff0000;
- tmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes) */
- tmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/
- ehci_writel(ehci, tmp, &ehci->regs->txfill_tuning);
-
- tmp = ehci_readl(ehci, &ehci->regs->txttfill_tuning);
- tmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */
- ehci_writel(ehci, tmp, &ehci->regs->txttfill_tuning);
-
- return retval;
-}
-
-static int ehci_oxnas_drv_probe(struct platform_device *ofdev)
-{
- struct device_node *np = ofdev->dev.of_node;
- struct usb_hcd *hcd;
- struct ehci_hcd *ehci;
- struct resource res;
- struct oxnas_hcd *oxnas;
- int irq, err;
- struct reset_control *rstc;
-
- if (usb_disabled())
- return -ENODEV;
-
- if (!ofdev->dev.dma_mask)
- ofdev->dev.dma_mask = &ofdev->dev.coherent_dma_mask;
- if (!ofdev->dev.coherent_dma_mask)
- ofdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-
- hcd = usb_create_hcd(&oxnas_hc_driver, &ofdev->dev,
- dev_name(&ofdev->dev));
- if (!hcd)
- return -ENOMEM;
-
- err = of_address_to_resource(np, 0, &res);
- if (err)
- goto err_res;
-
- hcd->rsrc_start = res.start;
- hcd->rsrc_len = resource_size(&res);
-
- hcd->regs = devm_ioremap_resource(&ofdev->dev, &res);
- if (IS_ERR(hcd->regs)) {
- dev_err(&ofdev->dev, "devm_ioremap_resource failed\n");
- err = PTR_ERR(hcd->regs);
- goto err_ioremap;
- }
-
- oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;
-
- oxnas->use_pllb = of_property_read_bool(np, "oxsemi,ehci_use_pllb");
- oxnas->use_phya = of_property_read_bool(np, "oxsemi,ehci_use_phya");
-
- oxnas->syscon = syscon_regmap_lookup_by_phandle(np, "oxsemi,sys-ctrl");
- if (IS_ERR(oxnas->syscon)) {
- err = PTR_ERR(oxnas->syscon);
- goto err_syscon;
- }
-
- oxnas->clk = of_clk_get_by_name(np, "usb");
- if (IS_ERR(oxnas->clk)) {
- err = PTR_ERR(oxnas->clk);
- goto err_clk;
- }
-
- if (oxnas->use_pllb) {
- oxnas->refsrc = of_clk_get_by_name(np, "refsrc");
- if (IS_ERR(oxnas->refsrc)) {
- err = PTR_ERR(oxnas->refsrc);
- goto err_refsrc;
- }
- oxnas->phyref = of_clk_get_by_name(np, "phyref");
- if (IS_ERR(oxnas->refsrc)) {
- err = PTR_ERR(oxnas->refsrc);
- goto err_phyref;
- }
-
- } else {
- oxnas->refsrc = NULL;
- oxnas->phyref = NULL;
- }
-
- rstc = devm_reset_control_get(&ofdev->dev, "host");
- if (IS_ERR(rstc)) {
- err = PTR_ERR(rstc);
- goto err_rst;
- }
- oxnas->rst_host = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "phya");
- if (IS_ERR(rstc)) {
- err = PTR_ERR(rstc);
- goto err_rst;
- }
- oxnas->rst_phya = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "phyb");
- if (IS_ERR(rstc)) {
- err = PTR_ERR(rstc);
- goto err_rst;
- }
- oxnas->rst_phyb = rstc;
-
- irq = irq_of_parse_and_map(np, 0);
- if (!irq) {
- dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
- err = -EBUSY;
- goto err_irq;
- }
-
- hcd->has_tt = 1;
- ehci = hcd_to_ehci(hcd);
- ehci->caps = hcd->regs;
-
- start_oxnas_usb_ehci(oxnas);
-
- err = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (err)
- goto err_hcd;
-
- return 0;
-
-err_hcd:
- stop_oxnas_usb_ehci(oxnas);
-err_irq:
-err_rst:
- if (oxnas->phyref)
- clk_put(oxnas->phyref);
-err_phyref:
- if (oxnas->refsrc)
- clk_put(oxnas->refsrc);
-err_refsrc:
- clk_put(oxnas->clk);
-err_syscon:
-err_clk:
-err_ioremap:
-err_res:
- usb_put_hcd(hcd);
-
- return err;
-}
-
-static int ehci_oxnas_drv_remove(struct platform_device *pdev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
- struct oxnas_hcd *oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;
-
- usb_remove_hcd(hcd);
- if (oxnas->use_pllb) {
- clk_disable_unprepare(oxnas->phyref);
- clk_put(oxnas->phyref);
- clk_disable_unprepare(oxnas->refsrc);
- clk_put(oxnas->refsrc);
- }
- clk_disable_unprepare(oxnas->clk);
- usb_put_hcd(hcd);
-
- return 0;
-}
-
-static const struct of_device_id oxnas_ehci_dt_ids[] = {
- { .compatible = "plxtech,nas782x-ehci" },
- { /* sentinel */ }
-};
-
-MODULE_DEVICE_TABLE(of, oxnas_ehci_dt_ids);
-
-static struct platform_driver ehci_oxnas_driver = {
- .probe = ehci_oxnas_drv_probe,
- .remove = ehci_oxnas_drv_remove,
- .shutdown = usb_hcd_platform_shutdown,
- .driver.name = "oxnas-ehci",
- .driver.of_match_table = oxnas_ehci_dt_ids,
-};
-
-static const struct ehci_driver_overrides oxnas_overrides __initconst = {
- .reset = ehci_oxnas_reset,
- .extra_priv_size = sizeof(struct oxnas_hcd),
-};
-
-static int __init ehci_oxnas_init(void)
-{
- if (usb_disabled())
- return -ENODEV;
-
- ehci_init_driver(&oxnas_hc_driver, &oxnas_overrides);
- return platform_driver_register(&ehci_oxnas_driver);
-}
-module_init(ehci_oxnas_init);
-
-static void __exit ehci_oxnas_cleanup(void)
-{
- platform_driver_unregister(&ehci_oxnas_driver);
-}
-module_exit(ehci_oxnas_cleanup);
-
-MODULE_DESCRIPTION(DRIVER_DESC);
-MODULE_ALIAS("platform:oxnas-ehci");
-MODULE_LICENSE("GPL");
+++ /dev/null
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux
-UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage
-
-include $(SUBTARGET).mk
-
-$(eval $(call BuildImage))
+++ /dev/null
-KERNEL_LOADADDR := 0x48008000
-
-define Device/Default
- KERNEL_NAME := zImage
- KERNEL_SUFFIX := -uImage
- KERNEL_INSTALL := 1
- FILESYSTEMS := squashfs ext4
- PROFILES := Default
- DEVICE_DTS := ox810se-$(subst _,-,$(1))
- IMAGES := sysupgrade.tar
- IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
-endef
-
-define Device/wd_mbwe
- DEVICE_VENDOR := Western Digital
- DEVICE_MODEL := My Book
- DEVICE_VARIANT := World Edition
- KERNEL := kernel-bin | append-dtb | uImage none
-endef
-TARGET_DEVICES += wd_mbwe
+++ /dev/null
-UBIFS_OPTS := -m 2048 -e 126KiB -c 4096
-KERNEL_LOADADDR := 0x60008000
-
-define Device/Default
- KERNEL_NAME := zImage
- KERNEL_SUFFIX := -uImage
- KERNEL_INSTALL := 1
- BLOCKSIZE := 128k
- PAGESIZE := 2048
- SUBPAGESIZE := 512
- FILESYSTEMS := squashfs ubifs
- PROFILES := Default
- DEVICE_DTS := ox820-$(subst _,-,$(1))
- KERNEL := kernel-bin | append-dtb | uImage none
- IMAGES := ubinized.bin sysupgrade.tar
- IMAGE/ubinized.bin := append-ubi
- IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
-endef
-
-define Build/omninas-factory
- rm -rf $@.tmp $@.dummy $@.dummy.gz
- mkdir -p $@.tmp
- $(CP) $@ $@.tmp/uImage
- dd if=/dev/zero bs=64k count=4 of=$@.dummy
- gzip $@.dummy
- mkimage -A arm -T ramdisk -C gzip -n "dummy" \
- -d $@.dummy.gz \
- $@.tmp/rdimg.gz
- echo 2.35.20140102 > $@.tmp/version ; echo >> $@.tmp/version
- chmod 0744 $@.tmp/*
- $(TAR) -C $@.tmp -czvf $@ \
- $(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") .
-endef
-
-define Build/encrypt-3des
- openssl enc -des3 -a -k $(1) -in $@ -out $@.new && mv $@.new $@
-endef
-
-define Device/akitio_mycloud
- DEVICE_VENDOR := Akitio
- DEVICE_MODEL := MyCloud Mini
- SUPPORTED_DEVICES += akitio
- DEVICE_PACKAGES := kmod-ata-oxnas-sata kmod-i2c-gpio kmod-rtc-ds1307 \
- kmod-usb2-oxnas kmod-usb-ledtrig-usbport
-endef
-TARGET_DEVICES += akitio_mycloud
-
-define Device/cloudengines_pogoplugpro
- DEVICE_VENDOR := Cloud Engines
- DEVICE_MODEL := PogoPlug Pro (with mPCIe)
- SUPPORTED_DEVICES += pogoplug-pro
- DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb-ledtrig-usbport \
- kmod-ata-oxnas-sata kmod-rt2800-pci wpad-basic-mbedtls
-endef
-TARGET_DEVICES += cloudengines_pogoplugpro
-
-define Device/cloudengines_pogoplug-series-3
- DEVICE_VENDOR := Cloud Engines
- DEVICE_MODEL := PogoPlug Series V3 (without mPCIe)
- SUPPORTED_DEVICES += cloudengines,pogoplugv3 pogoplug-v3
- DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb-ledtrig-usbport \
- kmod-ata-oxnas-sata
-endef
-TARGET_DEVICES += cloudengines_pogoplug-series-3
-
-define Device/shuttle_kd20
- DEVICE_VENDOR := Shuttle
- DEVICE_MODEL := KD20
- SUPPORTED_DEVICES += kd20
- DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb3 kmod-usb-ledtrig-usbport \
- kmod-i2c-gpio kmod-rtc-pcf8563 kmod-gpio-beeper kmod-hwmon-drivetemp \
- kmod-hwmon-gpiofan kmod-ata-oxnas-sata kmod-md-mod kmod-md-raid0 \
- kmod-md-raid1 kmod-fs-ext4 kmod-fs-xfs
-endef
-TARGET_DEVICES += shuttle_kd20
-
-define Device/mitrastar_stg-212
- DEVICE_VENDOR := MitraStar
- DEVICE_MODEL := STG-212
- SUPPORTED_DEVICES += stg212
- DEVICE_PACKAGES := kmod-ata-oxnas-sata kmod-fs-ext4 kmod-fs-xfs \
- kmod-usb2-oxnas kmod-usb-ledtrig-usbport
-endef
-TARGET_DEVICES += mitrastar_stg-212
+++ /dev/null
-define KernelPackage/ata-oxnas-sata
- TITLE:=oxnas Serial ATA support
- KCONFIG:=CONFIG_SATA_OXNAS
- FILES:=$(LINUX_DIR)/drivers/ata/sata_oxnas.ko
- AUTOLOAD:=$(call AutoLoad,41,sata_oxnas,1)
- $(call AddDepends/ata,@TARGET_oxnas)
-endef
-
-define KernelPackage/ata-oxnas-sata/description
- SATA support for OX934 core found in the OX8xx/PLX782x SoCs
-endef
-
-$(eval $(call KernelPackage,ata-oxnas-sata))
-
-
-define KernelPackage/usb2-oxnas
- TITLE:=OX820 EHCI driver
- KCONFIG:=CONFIG_USB_EHCI_OXNAS
- FILES:=$(LINUX_DIR)/drivers/usb/host/ehci-oxnas.ko
- AUTOLOAD:=$(call AutoLoad,55,ehci-oxnas,1)
- $(call AddDepends/usb,@TARGET_oxnas_ox820 +kmod-usb2)
-endef
-
-define KernelPackage/usb2-oxnas/description
- This driver provides USB Device Controller support for the
- EHCI USB host built-in to the OX820 SoC.
-endef
-
-$(eval $(call KernelPackage,usb2-oxnas))
+++ /dev/null
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-# CONFIG_DEBUG_UNCOMPRESS is not set
-CONFIG_EXT4_FS=y
-CONFIG_FS_MBCACHE=y
-CONFIG_MACH_OX810SE=y
+++ /dev/null
-define Profile/Default
- NAME:=Default Profile
- PRIORITY:=1
-endef
-
-define Profile/Default/Description
- Default package set compatible with most boards.
-endef
-
-$(eval $(call Profile,Default))
+++ /dev/null
-FEATURES+=source-only
-
-SUBTARGET:=ox810se
-BOARDNAME:=OX810SE
-CPU_TYPE:=arm926ej-s
-
-define Target/Description
- Oxford OX810SE
-endef
+++ /dev/null
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_WANT_LIBATA_LEDS=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ATA_LEDS=y
-CONFIG_CACHE_L2X0=y
-# CONFIG_CACHE_L2X0_PMU is not set
-CONFIG_CPU_32v6=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_ABRT_EV6=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V6=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_PABRT_V6=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V6=y
-CONFIG_CPU_V6K=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_LL_UART_8250=y
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
-CONFIG_DEBUG_UART_8250_SHIFT=0
-CONFIG_DEBUG_UART_PHYS=0x44200000
-CONFIG_DEBUG_UART_VIRT=0xf4200000
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_DMA_CACHE_RWFO=y
-CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_SMP=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MACH_OX820=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-# CONFIG_MTD_NAND_ECC_SW_BCH is not set
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
-CONFIG_MTD_NAND_OXNAS=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NR_CPUS=16
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_OXNAS=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_SECURITY=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress-ox820.h"
-CONFIG_XPS=y
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Copyright (C) 2016 OpenWrt.org
-
-define Profile/Default
- NAME:=Default Profile
- PRIORITY:=1
- PACKAGES:=\
- kmod-i2c-gpio kmod-gpio-beeper kmod-hwmon-gpiofan \
- kmod-rtc-pcf8563 kmod-rtc-ds1307 kmod-usb3
-endef
-
-define Profile/Default/Description
- Default package set compatible with most boards.
-endef
-
-$(eval $(call Profile,Default))
+++ /dev/null
-SUBTARGET:=ox820
-BOARDNAME:=OX820/NAS782x
-CPU_TYPE:=mpcore
-FEATURES+=nand pci pcie ubifs usb
-
-define Target/Description
- Oxford/PLXTECH OX820/NAS782x
-endef
\ No newline at end of file
+++ /dev/null
-- add compatible string
-- add console to bootargs
-- add led aliases
-- adjust nand partition table
----
---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-@@ -11,10 +11,10 @@
- / {
- model = "Cloud Engines PogoPlug Series 3";
-
-- compatible = "cloudengines,pogoplugv3", "oxsemi,ox820";
-+ compatible = "cloudengines,pogoplug-series-3", "cloudengines,pogoplugv3", "oxsemi,ox820";
-
- chosen {
-- bootargs = "earlyprintk";
-+ bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
-@@ -27,24 +27,28 @@
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
-+ led-boot = &led_status;
-+ led-failsafe = &led_warn;
-+ led-running = &led_act;
-+ led-upgrade = &led_warn;
- };
-
- leds {
- compatible = "gpio-leds";
-
-- blue {
-+ led_status: blue {
- label = "pogoplug:blue";
- gpios = <&gpio0 2 0>;
- default-state = "keep";
- };
-
-- orange {
-+ led_warn: orange {
- label = "pogoplug:orange";
- gpios = <&gpio1 16 1>;
- default-state = "keep";
- };
-
-- green {
-+ led_act: green {
- label = "pogoplug:green";
- gpios = <&gpio1 17 1>;
- default-state = "keep";
-@@ -73,11 +77,27 @@
- nand-ecc-algo = "hamming";
-
- partition@0 {
-- label = "boot";
-- reg = <0x00000000 0x00e00000>;
-+ label = "stage1";
-+ reg = <0x00000000 0x00040000>;
- read-only;
- };
-
-+ partition@40000 {
-+ label = "u-boot";
-+ reg = <0x00040000 0x00380000>;
-+ read-only;
-+ };
-+
-+ partition@3c0000 {
-+ label = "u-boot-env";
-+ reg = <0x003c0000 0x00080000>;
-+ };
-+
-+ partition@440000 {
-+ label = "kernel";
-+ reg = <0x00440000 0x009c0000>;
-+ };
-+
- partition@e00000 {
- label = "ubi";
- reg = <0x00e00000 0x07200000>;
+++ /dev/null
-From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 1 Jun 2018 02:41:15 +0200
-Subject: [PATCH] arm: ox820: remove left-overs
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/clk/clk-oxnas.c | 2 --
- include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++-------------
- 2 files changed, 14 insertions(+), 20 deletions(-)
-
---- a/drivers/clk/clk-oxnas.c
-+++ b/drivers/clk/clk-oxnas.c
-@@ -29,8 +29,6 @@ struct oxnas_stdclk_data {
- struct clk_hw_onecell_data *onecell_data;
- struct clk_oxnas_gate **gates;
- unsigned int ngates;
-- struct clk_oxnas_pll **plls;
-- unsigned int nplls;
- };
-
- /* Regmap offsets */
---- a/include/dt-bindings/clock/oxsemi,ox820.h
-+++ b/include/dt-bindings/clock/oxsemi,ox820.h
-@@ -6,24 +6,20 @@
- #ifndef DT_CLOCK_OXSEMI_OX820_H
- #define DT_CLOCK_OXSEMI_OX820_H
-
--/* PLLs */
--#define CLK_820_PLLA 0
--#define CLK_820_PLLB 1
--
- /* Gate Clocks */
--#define CLK_820_LEON 2
--#define CLK_820_DMA_SGDMA 3
--#define CLK_820_CIPHER 4
--#define CLK_820_SD 5
--#define CLK_820_SATA 6
--#define CLK_820_AUDIO 7
--#define CLK_820_USBMPH 8
--#define CLK_820_ETHA 9
--#define CLK_820_PCIEA 10
--#define CLK_820_NAND 11
--#define CLK_820_PCIEB 12
--#define CLK_820_ETHB 13
--#define CLK_820_REF600 14
--#define CLK_820_USBDEV 15
-+#define CLK_820_LEON 0
-+#define CLK_820_DMA_SGDMA 1
-+#define CLK_820_CIPHER 2
-+#define CLK_820_SD 3
-+#define CLK_820_SATA 4
-+#define CLK_820_AUDIO 5
-+#define CLK_820_USBMPH 6
-+#define CLK_820_ETHA 7
-+#define CLK_820_PCIEA 8
-+#define CLK_820_NAND 9
-+#define CLK_820_PCIEB 10
-+#define CLK_820_ETHB 11
-+#define CLK_820_REF600 12
-+#define CLK_820_USBDEV 13
-
- #endif /* DT_CLOCK_OXSEMI_OX820_H */
+++ /dev/null
---- a/drivers/clk/clk-oxnas.c
-+++ b/drivers/clk/clk-oxnas.c
-@@ -5,19 +5,42 @@
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-+#include <linux/clk.h>
-+#include <linux/clkdev.h>
- #include <linux/clk-provider.h>
- #include <linux/kernel.h>
- #include <linux/init.h>
-+#include <linux/delay.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
- #include <linux/platform_device.h>
- #include <linux/stringify.h>
- #include <linux/regmap.h>
- #include <linux/mfd/syscon.h>
-+#include <linux/reset.h>
-
- #include <dt-bindings/clock/oxsemi,ox810se.h>
- #include <dt-bindings/clock/oxsemi,ox820.h>
-
-+#define REF300_DIV_INT_SHIFT 8
-+#define REF300_DIV_FRAC_SHIFT 0
-+#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
-+#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
-+
-+#define PLLB_BYPASS 1
-+#define PLLB_ENSAT 3
-+#define PLLB_OUTDIV 4
-+#define PLLB_REFDIV 8
-+#define PLLB_DIV_INT_SHIFT 8
-+#define PLLB_DIV_FRAC_SHIFT 0
-+#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
-+#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
-+
-+#define PLLA_REFDIV_MASK 0x3F
-+#define PLLA_REFDIV_SHIFT 8
-+#define PLLA_OUTDIV_MASK 0x7
-+#define PLLA_OUTDIV_SHIFT 4
-+
- /* Standard regmap gate clocks */
- struct clk_oxnas_gate {
- struct clk_hw hw;
-@@ -36,6 +59,135 @@ struct oxnas_stdclk_data {
- #define CLK_SET_REGOFFSET 0x2c
- #define CLK_CLR_REGOFFSET 0x30
-
-+#define PLLA_CTRL0_REGOFFSET 0x1f0
-+#define PLLA_CTRL1_REGOFFSET 0x1f4
-+#define PLLB_CTRL0_REGOFFSET 0x1001f0
-+#define MHZ (1000 * 1000)
-+
-+struct clk_oxnas_pll {
-+ struct clk_hw hw;
-+ struct device_node *devnode;
-+ struct reset_control *rstc;
-+ struct regmap *syscon;
-+};
-+
-+#define to_clk_oxnas_pll(_hw) container_of(_hw, struct clk_oxnas_pll, hw)
-+
-+static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ struct clk_oxnas_pll *plla = to_clk_oxnas_pll(hw);
-+ unsigned long fin = parent_rate;
-+ unsigned long refdiv, outdiv;
-+ unsigned int pll0, fbdiv;
-+
-+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL0_REGOFFSET, &pll0));
-+
-+ refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
-+ refdiv += 1;
-+ outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
-+ outdiv += 1;
-+
-+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL1_REGOFFSET, &fbdiv));
-+ /* seems we will not be here when pll is bypassed, so ignore this
-+ * case */
-+
-+ return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
-+}
-+
-+static const char *pll_clk_parents[] = {
-+ "oscillator",
-+};
-+
-+static struct clk_ops plla_ops = {
-+ .recalc_rate = plla_clk_recalc_rate,
-+};
-+
-+static struct clk_init_data clk_plla_init = {
-+ .name = "plla",
-+ .ops = &plla_ops,
-+ .parent_names = pll_clk_parents,
-+ .num_parents = ARRAY_SIZE(pll_clk_parents),
-+};
-+
-+static int pllb_clk_is_prepared(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ return !!pllb->rstc;
-+}
-+
-+static int pllb_clk_prepare(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ pllb->rstc = of_reset_control_get(pllb->devnode, NULL);
-+
-+ return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0;
-+}
-+
-+static void pllb_clk_unprepare(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ BUG_ON(IS_ERR(pllb->rstc));
-+
-+ reset_control_put(pllb->rstc);
-+ pllb->rstc = NULL;
-+}
-+
-+static int pllb_clk_enable(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ BUG_ON(IS_ERR(pllb->rstc));
-+
-+ /* put PLL into bypass */
-+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
-+ wmb();
-+ udelay(10);
-+ reset_control_assert(pllb->rstc);
-+ udelay(10);
-+ /* set PLL B control information */
-+ regmap_write_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, 0xffff,
-+ (1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV));
-+ reset_control_deassert(pllb->rstc);
-+ udelay(100);
-+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), 0);
-+
-+ return 0;
-+}
-+
-+static void pllb_clk_disable(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ BUG_ON(IS_ERR(pllb->rstc));
-+
-+ /* put PLL into bypass */
-+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
-+
-+ wmb();
-+ udelay(10);
-+
-+ reset_control_assert(pllb->rstc);
-+}
-+
-+static struct clk_ops pllb_ops = {
-+ .prepare = pllb_clk_prepare,
-+ .unprepare = pllb_clk_unprepare,
-+ .is_prepared = pllb_clk_is_prepared,
-+ .enable = pllb_clk_enable,
-+ .disable = pllb_clk_disable,
-+};
-+
-+static struct clk_init_data clk_pllb_init = {
-+ .name = "pllb",
-+ .ops = &pllb_ops,
-+ .parent_names = pll_clk_parents,
-+ .num_parents = ARRAY_SIZE(pll_clk_parents),
-+};
-+
- static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
- {
- return container_of(hw, struct clk_oxnas_gate, hw);
-@@ -251,3 +403,42 @@ static struct platform_driver oxnas_stdc
- },
- };
- builtin_platform_driver(oxnas_stdclk_driver);
-+
-+void __init oxnas_init_plla(struct device_node *np)
-+{
-+ struct clk *clk;
-+ struct clk_oxnas_pll *plla;
-+
-+ plla = kmalloc(sizeof(*plla), GFP_KERNEL);
-+ BUG_ON(!plla);
-+
-+ plla->syscon = syscon_node_to_regmap(of_get_parent(np));
-+ plla->hw.init = &clk_plla_init;
-+ plla->devnode = np;
-+ plla->rstc = NULL;
-+ clk = clk_register(NULL, &plla->hw);
-+ BUG_ON(IS_ERR(clk));
-+ /* mark it as enabled */
-+ clk_prepare_enable(clk);
-+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
-+}
-+CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
-+
-+void __init oxnas_init_pllb(struct device_node *np)
-+{
-+ struct clk *clk;
-+ struct clk_oxnas_pll *pllb;
-+
-+ pllb = kmalloc(sizeof(*pllb), GFP_KERNEL);
-+ BUG_ON(!pllb);
-+
-+ pllb->syscon = syscon_node_to_regmap(of_get_parent(np));
-+ pllb->hw.init = &clk_pllb_init;
-+ pllb->devnode = np;
-+ pllb->rstc = NULL;
-+
-+ clk = clk_register(NULL, &pllb->hw);
-+ BUG_ON(IS_ERR(clk));
-+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
-+}
-+CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -61,12 +61,6 @@
- clocks = <&osc>;
- };
-
-- plla: plla {
-- compatible = "fixed-clock";
-- #clock-cells = <0>;
-- clock-frequency = <850000000>;
-- };
--
- armclk: armclk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
-@@ -266,6 +260,19 @@
- compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
- #clock-cells = <1>;
- };
-+
-+ plla: plla {
-+ compatible = "plxtech,nas782x-plla";
-+ #clock-cells = <0>;
-+ clocks = <&osc>;
-+ };
-+
-+ pllb: pllb {
-+ compatible = "plxtech,nas782x-pllb";
-+ #clock-cells = <0>;
-+ clocks = <&osc>;
-+ resets = <&reset RESET_PLLB>;
-+ };
- };
- };
-
-@@ -287,6 +294,13 @@
- clocks = <&armclk>;
- };
-
-+ watchdog@620 {
-+ compatible = "mpcore_wdt";
-+ reg = <0x620 0x20>;
-+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
-+ clocks = <&armclk>;
-+ };
-+
- gic: interrupt-controller@1000 {
- compatible = "arm,arm11mp-gic";
- interrupt-controller;
+++ /dev/null
---- a/drivers/power/reset/Kconfig
-+++ b/drivers/power/reset/Kconfig
-@@ -148,6 +148,12 @@ config POWER_RESET_OXNAS
- help
- Restart support for OXNAS/PLXTECH OX820 SoC.
-
-+config POWER_RESET_OXNAS
-+ bool "OXNAS SoC restart driver"
-+ depends on ARCH_OXNAS
-+ help
-+ Restart support for OXNAS boards.
-+
- config POWER_RESET_PIIX4_POWEROFF
- tristate "Intel PIIX4 power-off driver"
- depends on PCI
---- a/drivers/power/reset/Makefile
-+++ b/drivers/power/reset/Makefile
-@@ -19,6 +19,7 @@ obj-$(CONFIG_POWER_RESET_QCOM_PON) += qc
- obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o
- obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
- obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
-+obj-$(CONFIG_POWER_RESET_OXNAS) += oxnas-restart.o
- obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
- obj-$(CONFIG_POWER_RESET_REGULATOR) += regulator-poweroff.o
- obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
+++ /dev/null
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -247,6 +247,15 @@
- };
- };
-
-+ pcie_phy: pcie-phy@a00000 {
-+ compatible = "oxsemi,ox820-pcie-phy";
-+ reg = <0xa00000 0x10>;
-+ #phy-cells = <0>;
-+ resets = <&reset RESET_PCIEPHY>;
-+ reset-names = "phy";
-+ status = "disabled";
-+ };
-+
- sys: sys-ctrl@e00000 {
- compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
- reg = <0xe00000 0x200000>;
---- a/drivers/phy/Kconfig
-+++ b/drivers/phy/Kconfig
-@@ -35,6 +35,13 @@ config PHY_LPC18XX_USB_OTG
- This driver is need for USB0 support on LPC18xx/43xx and takes
- care of enabling and clock setup.
-
-+config PHY_OXNAS
-+ tristate "Oxford Semi. OX820 PCI-E PHY support"
-+ depends on HAS_IOMEM && OF && (ARM || COMPILE_TEST)
-+ select GENERIC_PHY
-+ help
-+ This option enables support for OXNAS OX820 SoC PCIE PHY.
-+
- config PHY_PISTACHIO_USB
- tristate "IMG Pistachio USB2.0 PHY driver"
- depends on MIPS || COMPILE_TEST
---- a/drivers/phy/Makefile
-+++ b/drivers/phy/Makefile
-@@ -7,6 +7,7 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o
- obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
- obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
- obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
-+obj-$(CONFIG_PHY_OXNAS) += phy-oxnas-pcie.o
- obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
- obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
- obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
+++ /dev/null
---- a/drivers/pci/controller/Kconfig
-+++ b/drivers/pci/controller/Kconfig
-@@ -312,6 +312,11 @@ config PCIE_HISI_ERR
- Say Y here if you want error handling support
- for the PCIe controller's errors on HiSilicon HIP SoCs
-
-+config PCIE_OXNAS
-+ bool "PLX Oxnas PCIe controller"
-+ depends on ARCH_OXNAS
-+ select PCIEPORTBUS
-+
- source "drivers/pci/controller/dwc/Kconfig"
- source "drivers/pci/controller/mobiveil/Kconfig"
- source "drivers/pci/controller/cadence/Kconfig"
---- a/drivers/pci/controller/Makefile
-+++ b/drivers/pci/controller/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie
- obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
- obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
- obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
-+obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
- obj-$(CONFIG_VMD) += vmd.o
- obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
- obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -289,7 +289,7 @@
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-- ranges = <0 0x47000000 0x1000000>;
-+ ranges = <0 0x47000000 0x2000>;
-
- scu: scu@0 {
- compatible = "arm,arm11mp-scu";
-@@ -318,5 +318,86 @@
- <0x100 0x500>;
- };
- };
-+
-+ pcie0: pcie@47c00000 {
-+ compatible = "plxtech,nas782x-pcie";
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ /* flag & space bus address host address size */
-+ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
-+ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
-+ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
-+ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
-+
-+ bus-range = <0x00 0x7f>;
-+
-+ /* cfg inbound translator */
-+ reg = <0x47c00000 0x1000>, <0x47d00000 0x100>;
-+
-+ phys = <&pcie_phy>;
-+ phy-names = "pcie-phy";
-+
-+ #interrupt-cells = <1>;
-+ /* wild card mask, match all bus address & interrupt specifier */
-+ /* format: bus address mask, interrupt specifier mask */
-+ /* each bit 1 means need match, 0 means ignored when match */
-+ interrupt-map-mask = <0 0 0 0>;
-+ /* format: a list of: bus address, interrupt specifier,
-+ * parent interrupt controller & specifier */
-+ interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
-+ gpios = <&gpio1 12 0>;
-+ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
-+ clock-names = "pcie", "busclk";
-+ resets = <&reset RESET_PCIEA>;
-+ reset-names = "pcie";
-+
-+ plxtech,pcie-hcsl-bit = <2>;
-+ plxtech,pcie-ctrl-offset = <0x120>;
-+ plxtech,pcie-outbound-offset = <0x138>;
-+ status = "disabled";
-+ };
-+
-+ pcie1: pcie@47e00000 {
-+ compatible = "plxtech,nas782x-pcie";
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ /* flag & space bus address host address size */
-+ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
-+ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
-+ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
-+ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
-+
-+ bus-range = <0x80 0xff>;
-+
-+ /* cfg inbound translator */
-+ reg = <0x47e00000 0x1000>, <0x47f00000 0x100>;
-+
-+ phys = <&pcie_phy>;
-+ phy-names = "pcie-phy";
-+
-+ #interrupt-cells = <1>;
-+ /* wild card mask, match all bus address & interrupt specifier */
-+ /* format: bus address mask, interrupt specifier mask */
-+ /* each bit 1 means need match, 0 means ignored when match */
-+ interrupt-map-mask = <0 0 0 0>;
-+ /* format: a list of: bus address, interrupt specifier,
-+ * parent interrupt controller & specifier */
-+ interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
-+
-+ /* gpios = <&gpio1 12 0>; */
-+ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
-+ clock-names = "pcie", "busclk";
-+ resets = <&reset RESET_PCIEB>;
-+ reset-names = "pcie";
-+
-+ plxtech,pcie-hcsl-bit = <3>;
-+ plxtech,pcie-ctrl-offset = <0x124>;
-+ plxtech,pcie-outbound-offset = <0x174>;
-+ status = "disabled";
-+ };
- };
- };
+++ /dev/null
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -568,6 +568,14 @@ config SATA_VITESSE
-
- If unsure, say N.
-
-+config SATA_OXNAS
-+ tristate "PLXTECH NAS782X SATA support"
-+ select SATA_HOST
-+ help
-+ This option enables support for Nas782x Serial ATA controller.
-+
-+ If unsure, say N.
-+
- comment "PATA SFF controllers with BMDMA"
-
- config PATA_ALI
---- a/drivers/ata/Makefile
-+++ b/drivers/ata/Makefile
-@@ -46,6 +46,7 @@ obj-$(CONFIG_SATA_SVW) += sata_svw.o
- obj-$(CONFIG_SATA_ULI) += sata_uli.o
- obj-$(CONFIG_SATA_VIA) += sata_via.o
- obj-$(CONFIG_SATA_VITESSE) += sata_vsc.o
-+obj-$(CONFIG_SATA_OXNAS) += sata_oxnas.o
-
- # SFF PATA w/ BMDMA
- obj-$(CONFIG_PATA_ALI) += pata_ali.o
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -399,5 +399,20 @@
- plxtech,pcie-outbound-offset = <0x174>;
- status = "disabled";
- };
-+
-+ sata: sata@45900000 {
-+ compatible = "plxtech,nas782x-sata";
-+ /* ports dmactl sgdma */
-+ reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>,
-+ /* core phy descriptors (optional) */
-+ <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>;
-+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&stdclk CLK_820_SATA>;
-+ resets = <&reset RESET_SATA>, <&reset RESET_SATA_LINK>, <&reset RESET_SATA_PHY>;
-+ reset-names = "sata", "link", "phy";
-+ nr-ports = <1>;
-+ status = "disabled";
-+ };
-+
- };
- };
---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-@@ -111,3 +111,7 @@
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
- };
-+
-+&sata {
-+ status = "okay";
-+};
+++ /dev/null
---- a/arch/arm/mach-oxnas/Kconfig
-+++ b/arch/arm/mach-oxnas/Kconfig
-@@ -2,6 +2,7 @@
- menuconfig ARCH_OXNAS
- bool "Oxford Semiconductor OXNAS Family SoCs"
- select ARCH_HAS_RESET_CONTROLLER
-+ select ARCH_WANT_LIBATA_LEDS
- select COMMON_CLK_OXNAS
- select GPIOLIB
- select MFD_SYSCON
+++ /dev/null
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -339,6 +339,13 @@ config USB_OCTEON_EHCI
- USB 2.0 device support. All CN6XXX based chips with USB are
- supported.
-
-+config USB_EHCI_OXNAS
-+ tristate "OXNAS EHCI Module"
-+ depends on USB_EHCI_HCD && ARCH_OXNAS
-+ select USB_EHCI_ROOT_HUB_TT
-+ help
-+ Enable support for the OX820 SOC's on-chip EHCI controller.
-+
- endif # USB_EHCI_HCD
-
- config USB_OXU210HP_HCD
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -46,6 +46,7 @@ obj-$(CONFIG_USB_EHCI_HCD_STI) += ehci-s
- obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
- obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o
- obj-$(CONFIG_USB_EHCI_BRCMSTB) += ehci-brcm.o
-+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o
-
- obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o
- obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -106,6 +106,31 @@
- status = "disabled";
- };
-
-+ ehci: ehci@40200100 {
-+ compatible = "plxtech,nas782x-ehci";
-+ reg = <0x40200100 0xf00>;
-+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>;
-+ clock-names = "usb", "refsrc", "phyref";
-+ resets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>;
-+ reset-names = "host", "phya", "phyb";
-+ oxsemi,sys-ctrl = <&sys>;
-+ /* Otherwise ref300 is used, which is derived from sata phy
-+ * in that case, usb depends on sata initialization */
-+ /* FIXME: how to make this dependency explicit ? */
-+ oxsemi,ehci_use_pllb;
-+ status = "disabled";
-+
-+ ehci_port1: port@1 {
-+ reg = <1>;
-+ #trigger-source-cells = <0>;
-+ };
-+ ehci_port2: port@2 {
-+ reg = <2>;
-+ #trigger-source-cells = <0>;
-+ };
-+ };
-+
- apb-bridge@44000000 {
- #address-cells = <1>;
- #size-cells = <1>;
---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-@@ -105,6 +105,10 @@
- };
- };
-
-+&ehci {
-+ status = "okay";
-+};
-+
- ða {
- status = "okay";
-
+++ /dev/null
-From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
-From: Adrian Panella <ianchi74@outlook.com>
-Date: Thu, 9 Mar 2017 09:37:17 +0100
-Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-Only command line ATAG will be processed, the rest of the ATAGs
-sent by bootloader will be ignored.
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
----
- arch/arm/Kconfig | 11 +++++
- arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-
- init/main.c | 16 ++++++++
- 3 files changed, 98 insertions(+), 1 deletion(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1728,6 +1728,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- The command-line arguments provided by the boot loader will be
- appended to the the device tree bootargs property.
-
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+ bool "Append rootblock parsing bootloader's kernel arguments"
-+ help
-+ The command-line arguments provided by the boot loader will be
-+ appended to a new device tree property: bootloader-args.
-+ If there is a property "append-rootblock" in DT under /chosen
-+ and a root= option in bootloaders command line it will be parsed
-+ and added to DT bootargs with the form: <append-rootblock>XX.
-+ Only command line ATAG will be processed, the rest of the ATAGs
-+ sent by bootloader will be ignored.
-+
- endchoice
-
- config CMDLINE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -5,6 +5,8 @@
-
- #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
- #define do_extend_cmdline 1
-+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
- #endif
-@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const
- return offset;
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop(void *fdt, const char *node_path, const char *property,
- void *val_array, int size)
- {
-@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char
- return offset;
- return fdt_setprop(fdt, offset, property, val_array, size);
- }
-+#endif
-
- static int setprop_string(void *fdt, const char *node_path,
- const char *property, const char *string)
-@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con
- return fdt_setprop_string(fdt, offset, property, string);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop_cell(void *fdt, const char *node_path,
- const char *property, uint32_t val)
- {
-@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const
- return offset;
- return fdt_setprop_cell(fdt, offset, property, val);
- }
-+#endif
-
- static const void *getprop(const void *fdt, const char *node_path,
- const char *property, int *len)
-@@ -58,6 +64,7 @@ static const void *getprop(const void *f
- return fdt_getprop(fdt, offset, property, len);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static uint32_t get_cell_size(const void *fdt)
- {
- int len;
-@@ -69,6 +76,61 @@ static uint32_t get_cell_size(const void
- return cell_size;
- }
-
-+#endif
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+ const char *ptr, *end;
-+ const char *root="root=";
-+ int i, l;
-+ const char *rootblock;
-+
-+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
-+ ptr = str - 1;
-+
-+ do {
-+ //first find an 'r' at the begining or after a space
-+ do {
-+ ptr++;
-+ ptr = strchr(ptr, 'r');
-+ if(!ptr) return dest;
-+
-+ } while (ptr != str && *(ptr-1) != ' ');
-+
-+ //then check for the rest
-+ for(i = 1; i <= 4; i++)
-+ if(*(ptr+i) != *(root+i)) break;
-+
-+ } while (i != 5);
-+
-+ end = strchr(ptr, ' ');
-+ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
-+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+ ptr = end + 1;
-+
-+ /* if append-rootblock property is set use it to append to command line */
-+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+ if(rootblock != NULL) {
-+ if(*dest != ' ') {
-+ *dest = ' ';
-+ dest++;
-+ len++;
-+ }
-+ if (len + l + i <= COMMAND_LINE_SIZE) {
-+ memcpy(dest, rootblock, l);
-+ dest += l - 1;
-+ memcpy(dest, ptr, i);
-+ dest += i;
-+ }
-+ }
-+ return dest;
-+}
-+#endif
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
- char cmdline[COMMAND_LINE_SIZE];
-@@ -88,18 +150,28 @@ static void merge_fdt_bootargs(void *fdt
-
- /* and append the ATAG_CMDLINE */
- if (fdt_cmdline) {
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+ //save original bootloader args
-+ //and append ubi.mtd with root partition number to current cmdline
-+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+
-+#else
- len = strlen(fdt_cmdline);
- if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
- *ptr++ = ' ';
- memcpy(ptr, fdt_cmdline, len);
- ptr += len;
- }
-+#endif
- }
- *ptr = '\0';
-
- setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static void hex_str(char *out, uint32_t value)
- {
- uint32_t digit;
-@@ -117,6 +189,7 @@ static void hex_str(char *out, uint32_t
- }
- *out = '\0';
- }
-+#endif
-
- /*
- * Convert and fold provided ATAGs into the provided FDT.
-@@ -131,9 +204,11 @@ int atags_to_fdt(void *atag_list, void *
- struct tag *atag = atag_list;
- /* In the case of 64 bits memory size, need to reserve 2 cells for
- * address and size for each bank */
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- __be32 mem_reg_property[2 * 2 * NR_BANKS];
-- int memcount = 0;
-- int ret, memsize;
-+ int memsize, memcount = 0;
-+#endif
-+ int ret;
-
- /* make sure we've got an aligned pointer */
- if ((u32)atag_list & 0x3)
-@@ -168,7 +243,9 @@ int atags_to_fdt(void *atag_list, void *
- else
- setprop_string(fdt, "/chosen", "bootargs",
- atag->u.cmdline.cmdline);
-- } else if (atag->hdr.tag == ATAG_MEM) {
-+ }
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+ else if (atag->hdr.tag == ATAG_MEM) {
- if (memcount >= sizeof(mem_reg_property)/4)
- continue;
- if (!atag->u.mem.size)
-@@ -212,6 +289,10 @@ int atags_to_fdt(void *atag_list, void *
- setprop(fdt, "/memory", "reg", mem_reg_property,
- 4 * memcount * memsize);
- }
-+#else
-+
-+ }
-+#endif
-
- return fdt_pack(fdt);
- }
---- a/init/main.c
-+++ b/init/main.c
-@@ -113,6 +113,10 @@
-
- #include <kunit/test.h>
-
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#include <linux/of.h>
-+#endif
-+
- static int kernel_init(void *);
-
- extern void init_IRQ(void);
-@@ -993,6 +997,18 @@ asmlinkage __visible void __init __no_sa
- page_alloc_init();
-
- pr_notice("Kernel command line: %s\n", saved_command_line);
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+ //Show bootloader's original command line for reference
-+ if(of_chosen) {
-+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+ if(prop)
-+ pr_notice("Bootloader command line (ignored): %s\n", prop);
-+ else
-+ pr_notice("Bootloader command line not present\n");
-+ }
-+#endif
-+
- /* parameters may set static keys */
- jump_label_init();
- parse_early_param();
+++ /dev/null
---- a/drivers/ata/libata-core.c
-+++ b/drivers/ata/libata-core.c
-@@ -1531,6 +1531,14 @@ unsigned ata_exec_internal_sg(struct ata
- return AC_ERR_SYSTEM;
- }
-
-+ if (ap->ops->acquire_hw && !ap->ops->acquire_hw(ap, 0, 0)) {
-+ spin_unlock_irqrestore(ap->lock, flags);
-+ if (!ap->ops->acquire_hw(ap, 1, (2*HZ))) {
-+ return AC_ERR_TIMEOUT;
-+ }
-+ spin_lock_irqsave(ap->lock, flags);
-+ }
-+
- /* initialize internal qc */
- qc = __ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
-
-@@ -4587,6 +4595,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
- if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
- return NULL;
-
-+ if (ap->ops->qc_new && ap->ops->qc_new(ap))
-+ return NULL;
-+
- /* libsas case */
- if (ap->flags & ATA_FLAG_SAS_HOST) {
- tag = ata_sas_allocate_tag(ap);
-@@ -4632,6 +4643,8 @@ void ata_qc_free(struct ata_queued_cmd *
- qc->tag = ATA_TAG_POISON;
- if (ap->flags & ATA_FLAG_SAS_HOST)
- ata_sas_free_tag(tag, ap);
-+ if (ap->ops->qc_free)
-+ ap->ops->qc_free(qc);
- }
- }
-
---- a/include/linux/libata.h
-+++ b/include/linux/libata.h
-@@ -927,6 +927,8 @@ struct ata_port_operations {
- enum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *qc);
- unsigned int (*qc_issue)(struct ata_queued_cmd *qc);
- bool (*qc_fill_rtf)(struct ata_queued_cmd *qc);
-+ int (*qc_new)(struct ata_port *ap);
-+ void (*qc_free)(struct ata_queued_cmd *qc);
-
- /*
- * Configuration and exception handling
-@@ -1017,6 +1019,9 @@ struct ata_port_operations {
- void (*phy_reset)(struct ata_port *ap);
- void (*eng_timeout)(struct ata_port *ap);
-
-+ int (*acquire_hw)(struct ata_port *ap, int may_sleep,
-+ int timeout_jiffies);
-+
- /*
- * ->inherits must be the last field and all the preceding
- * fields must be pointers.
CPU_SUBTYPE:=24kf
SUBTARGETS:=generic
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
include $(INCLUDE_DIR)/target.mk
+++ /dev/null
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BOARD_INGENIC is not set
-CONFIG_BOARD_SCACHE=y
-CONFIG_BUILTIN_DTB=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKSRC_MIPS_GIC=y
-CONFIG_CLKSRC_PISTACHIO=y
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_PISTACHIO=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONNECTOR=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-# CONFIG_CPU_HAS_SMARTMIPS is not set
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-# CONFIG_CPU_MICROMIPS is not set
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-# CONFIG_CPU_MIPS32_R6 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-# CONFIG_CPU_MIPS64_R6 is not set
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_MIPSR2_IRQ_EI=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRC16=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CSRC_R4K=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_EXT4_FS=y
-# CONFIG_FIT_IMAGE_FDT_BOSTON is not set
-# CONFIG_FIT_IMAGE_FDT_JAGUAR2 is not set
-# CONFIG_FIT_IMAGE_FDT_LUTON is not set
-CONFIG_FIT_IMAGE_FDT_MARDUK=y
-# CONFIG_FIT_IMAGE_FDT_NI169445 is not set
-# CONFIG_FIT_IMAGE_FDT_OCELOT is not set
-# CONFIG_FIT_IMAGE_FDT_SERVAL is not set
-# CONFIG_FIT_IMAGE_FDT_XILFPGA is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_IMG=y
-CONFIG_IMGPDC_WDT=y
-CONFIG_IMG_MDC_DMA=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-# CONFIG_LEGACY_BOARD_OCELOT is not set
-# CONFIG_LEGACY_BOARD_SEAD3 is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOG_BUF_SHIFT=18
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICREL_PHY=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_AUTO_PFN_OFFSET=y
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-CONFIG_MIPS_CM=y
-CONFIG_MIPS_CMDLINE_DTB_EXTEND=y
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CPC=y
-CONFIG_MIPS_CPS=y
-# CONFIG_MIPS_CPS_CPUIDLE is not set
-# CONFIG_MIPS_CPS_NS16550_BOOL is not set
-CONFIG_MIPS_CPS_PM=y
-CONFIG_MIPS_CPU_SCACHE=y
-CONFIG_MIPS_EBPF_JIT=y
-CONFIG_MIPS_GENERIC=y
-CONFIG_MIPS_GENERIC_KERNEL=y
-CONFIG_MIPS_GIC=y
-CONFIG_MIPS_L1_CACHE_SHIFT=7
-CONFIG_MIPS_L1_CACHE_SHIFT_7=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-CONFIG_MIPS_MT=y
-CONFIG_MIPS_MT_FPAFF=y
-CONFIG_MIPS_MT_SMP=y
-CONFIG_MIPS_NO_APPENDED_DTB=y
-CONFIG_MIPS_NR_CPU_NR_MAP=4
-CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_DW=y
-# CONFIG_MMC_DW_BLUEFIELD is not set
-# CONFIG_MMC_DW_EXYNOS is not set
-# CONFIG_MMC_DW_HI3798CV200 is not set
-# CONFIG_MMC_DW_K3 is not set
-CONFIG_MMC_DW_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NO_EXCEPT_FILL=y
-CONFIG_NR_CPUS=4
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PCI_DRIVERS_GENERIC=y
-CONFIG_PCS_XPCS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_PISTACHIO_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_PISTACHIO=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_IMG=y
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_PISTACHIO=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_SCHEDSTATS=y
-CONFIG_SCHED_INFO=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_SC16IS7XX=y
-CONFIG_SERIAL_SC16IS7XX_CORE=y
-# CONFIG_SERIAL_SC16IS7XX_I2C is not set
-CONFIG_SERIAL_SC16IS7XX_SPI=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPI=y
-CONFIG_SPI_IMG_SPFI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SRAM=y
-CONFIG_SRCU=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SWPHY=y
-CONFIG_SYNC_R4K=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_CPU_MIPS32_R6=y
-CONFIG_SYS_HAS_CPU_MIPS64_R1=y
-CONFIG_SYS_HAS_CPU_MIPS64_R2=y
-CONFIG_SYS_HAS_CPU_MIPS64_R6=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_HIGHMEM=y
-CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MICROMIPS=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_MIPS_CPS=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_SYS_SUPPORTS_RELOCATABLE=y
-CONFIG_SYS_SUPPORTS_SCHED_SMT=y
-CONFIG_SYS_SUPPORTS_SMARTMIPS=y
-CONFIG_SYS_SUPPORTS_SMP=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UHI_BOOT=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_DWC2_DUAL_ROLE=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-# CONFIG_VIRT_BOARD_RANCHU is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WEAK_ORDERING=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSMALLOC=y
-# CONFIG_ZSMALLOC_STAT is not set
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-From a2dd154377c9aa6ddda00d39b8c7c334e4fa16ff Mon Sep 17 00:00:00 2001
-From: Damien Horsley <damien.horsley@imgtec.com>
-Date: Tue, 22 Mar 2016 12:46:09 +0000
-Subject: dmaengine: img-mdc: Handle early status read
-
-It is possible that mdc_tx_status may be called before the first
-node has been read from memory.
-
-In this case, the residue value stored in the register is undefined.
-Return the transfer size instead.
-
-Signed-off-by: Damien Horsley <damien.horsley@imgtec.com>
----
- drivers/dma/img-mdc-dma.c | 40 ++++++++++++++++++++++++----------------
- 1 file changed, 24 insertions(+), 16 deletions(-)
-
---- a/drivers/dma/img-mdc-dma.c
-+++ b/drivers/dma/img-mdc-dma.c
-@@ -618,25 +618,33 @@ static enum dma_status mdc_tx_status(str
- (MDC_CMDS_PROCESSED_CMDS_DONE_MASK + 1);
-
- /*
-- * If the command loaded event hasn't been processed yet, then
-- * the difference above includes an extra command.
-+ * If the first node has not yet been read from memory,
-+ * the residue register value is undefined
- */
-- if (!mdesc->cmd_loaded)
-- cmds--;
-- else
-- cmds += mdesc->list_cmds_done;
--
-- bytes = mdesc->list_xfer_size;
-- ldesc = mdesc->list;
-- for (i = 0; i < cmds; i++) {
-- bytes -= ldesc->xfer_size + 1;
-- ldesc = ldesc->next_desc;
-- }
-- if (ldesc) {
-- if (residue != MDC_TRANSFER_SIZE_MASK)
-- bytes -= ldesc->xfer_size - residue;
-+ if (!mdesc->cmd_loaded && !cmds) {
-+ bytes = mdesc->list_xfer_size;
-+ } else {
-+ /*
-+ * If the command loaded event hasn't been processed yet, then
-+ * the difference above includes an extra command.
-+ */
-+ if (!mdesc->cmd_loaded)
-+ cmds--;
- else
-+ cmds += mdesc->list_cmds_done;
-+
-+ bytes = mdesc->list_xfer_size;
-+ ldesc = mdesc->list;
-+ for (i = 0; i < cmds; i++) {
- bytes -= ldesc->xfer_size + 1;
-+ ldesc = ldesc->next_desc;
-+ }
-+ if (ldesc) {
-+ if (residue != MDC_TRANSFER_SIZE_MASK)
-+ bytes -= ldesc->xfer_size - residue;
-+ else
-+ bytes -= ldesc->xfer_size + 1;
-+ }
- }
- }
- spin_unlock_irqrestore(&mchan->vc.lock, flags);
+++ /dev/null
-From cd2a6af51553d38072cd31699b58d16ca6176ef5 Mon Sep 17 00:00:00 2001
-From: Ionela Voinescu <ionela.voinescu@imgtec.com>
-Date: Thu, 2 Feb 2017 16:46:14 +0000
-Subject: spi: img-spfi: Implement dual and quad mode
-
-For dual and quad modes to work the SPFI controller needs
-to have information about command/address/dummy bytes in the
-transaction register. This information is not relevant for
-single mode, and therefore it can have any value in the
-allowed range. Therefore, for any read or write transfers of less
-than 8 bytes (cmd = 1 byte, addr up to 7 bytes), SPFI will be
-configured, but not enabled (unless it is the last transfer in
-the queue). The transfer will be enabled by the subsequent tranfer.
-A pending transfer is determined by the content of the transaction
-register: if command part is set and tsize is not.
-
-This way we ensure that for dual and quad transactions
-the command request size will apear in the command/address part
-of the transaction register, while the data size will be in
-tsize, all data being sent/received in the same transaction (as
-set up in the transaction register).
-
-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
-Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
----
- drivers/spi/spi-img-spfi.c | 96 ++++++++++++++++++++++++++++++++++++++++------
- 1 file changed, 85 insertions(+), 11 deletions(-)
-
---- a/drivers/spi/spi-img-spfi.c
-+++ b/drivers/spi/spi-img-spfi.c
-@@ -36,7 +36,8 @@
- #define SPFI_CONTROL_SOFT_RESET BIT(11)
- #define SPFI_CONTROL_SEND_DMA BIT(10)
- #define SPFI_CONTROL_GET_DMA BIT(9)
--#define SPFI_CONTROL_SE BIT(8)
-+#define SPFI_CONTROL_SE BIT(8)
-+#define SPFI_CONTROL_TX_RX BIT(1)
- #define SPFI_CONTROL_TMODE_SHIFT 5
- #define SPFI_CONTROL_TMODE_MASK 0x7
- #define SPFI_CONTROL_TMODE_SINGLE 0
-@@ -47,6 +48,10 @@
- #define SPFI_TRANSACTION 0x18
- #define SPFI_TRANSACTION_TSIZE_SHIFT 16
- #define SPFI_TRANSACTION_TSIZE_MASK 0xffff
-+#define SPFI_TRANSACTION_CMD_SHIFT 13
-+#define SPFI_TRANSACTION_CMD_MASK 0x7
-+#define SPFI_TRANSACTION_ADDR_SHIFT 10
-+#define SPFI_TRANSACTION_ADDR_MASK 0x7
-
- #define SPFI_PORT_STATE 0x1c
- #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20
-@@ -83,6 +88,7 @@
- */
- #define SPFI_32BIT_FIFO_SIZE 64
- #define SPFI_8BIT_FIFO_SIZE 16
-+#define SPFI_DATA_REQUEST_MAX_SIZE 8
-
- struct img_spfi {
- struct device *dev;
-@@ -99,6 +105,8 @@ struct img_spfi {
- struct dma_chan *tx_ch;
- bool tx_dma_busy;
- bool rx_dma_busy;
-+
-+ bool complete;
- };
-
- static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)
-@@ -115,9 +123,11 @@ static inline void spfi_start(struct img
- {
- u32 val;
-
-- val = spfi_readl(spfi, SPFI_CONTROL);
-- val |= SPFI_CONTROL_SPFI_EN;
-- spfi_writel(spfi, val, SPFI_CONTROL);
-+ if (spfi->complete) {
-+ val = spfi_readl(spfi, SPFI_CONTROL);
-+ val |= SPFI_CONTROL_SPFI_EN;
-+ spfi_writel(spfi, val, SPFI_CONTROL);
-+ }
- }
-
- static inline void spfi_reset(struct img_spfi *spfi)
-@@ -130,12 +140,21 @@ static int spfi_wait_all_done(struct img
- {
- unsigned long timeout = jiffies + msecs_to_jiffies(50);
-
-+ if (!(spfi->complete))
-+ return 0;
-+
- while (time_before(jiffies, timeout)) {
- u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
-
- if (status & SPFI_INTERRUPT_ALLDONETRIG) {
- spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG,
- SPFI_INTERRUPT_CLEAR);
-+ /*
-+ * Disable SPFI for it not to interfere with
-+ * pending transactions
-+ */
-+ spfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL)
-+ & ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL);
- return 0;
- }
- cpu_relax();
-@@ -441,9 +460,32 @@ static void img_spfi_config(struct spi_m
- struct spi_transfer *xfer)
- {
- struct img_spfi *spfi = spi_master_get_devdata(spi->master);
-- u32 val, div;
-+ u32 val, div, transact;
-+ bool is_pending;
-
- /*
-+ * For read or write transfers of less than 8 bytes (cmd = 1 byte,
-+ * addr up to 7 bytes), SPFI will be configured, but not enabled
-+ * (unless it is the last transfer in the queue).The transfer will
-+ * be enabled by the subsequent transfer.
-+ * A pending transfer is determined by the content of the
-+ * transaction register: if command part is set and tsize
-+ * is not
-+ */
-+ transact = spfi_readl(spfi, SPFI_TRANSACTION);
-+ is_pending = ((transact >> SPFI_TRANSACTION_CMD_SHIFT) &
-+ SPFI_TRANSACTION_CMD_MASK) &&
-+ (!((transact >> SPFI_TRANSACTION_TSIZE_SHIFT) &
-+ SPFI_TRANSACTION_TSIZE_MASK));
-+
-+ /* If there are no pending transactions it's OK to soft reset */
-+ if (!is_pending) {
-+ /* Start the transaction from a known (reset) state */
-+ spfi_reset(spfi);
-+ }
-+
-+ /*
-+ * Before anything else, set up parameters.
- * output = spfi_clk * (BITCLK / 512), where BITCLK must be a
- * power of 2 up to 128
- */
-@@ -456,20 +498,52 @@ static void img_spfi_config(struct spi_m
- val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
- spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
-
-- spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
-- SPFI_TRANSACTION);
-+ if (!list_is_last(&xfer->transfer_list, &master->cur_msg->transfers) &&
-+ /*
-+ * For duplex mode (both the tx and rx buffers are !NULL) the
-+ * CMD, ADDR, and DUMMY byte parts of the transaction register
-+ * should always be 0 and therefore the pending transfer
-+ * technique cannot be used.
-+ */
-+ (xfer->tx_buf) && (!xfer->rx_buf) &&
-+ (xfer->len <= SPFI_DATA_REQUEST_MAX_SIZE) && !is_pending) {
-+ transact = (1 & SPFI_TRANSACTION_CMD_MASK) <<
-+ SPFI_TRANSACTION_CMD_SHIFT;
-+ transact |= ((xfer->len - 1) & SPFI_TRANSACTION_ADDR_MASK) <<
-+ SPFI_TRANSACTION_ADDR_SHIFT;
-+ spfi->complete = false;
-+ } else {
-+ spfi->complete = true;
-+ if (is_pending) {
-+ /* Keep setup from pending transfer */
-+ transact |= ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) <<
-+ SPFI_TRANSACTION_TSIZE_SHIFT);
-+ } else {
-+ transact = ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) <<
-+ SPFI_TRANSACTION_TSIZE_SHIFT);
-+ }
-+ }
-+ spfi_writel(spfi, transact, SPFI_TRANSACTION);
-
- val = spfi_readl(spfi, SPFI_CONTROL);
- val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);
-- if (xfer->tx_buf)
-+ /*
-+ * We set up send DMA for pending transfers also, as
-+ * those are always send transfers
-+ */
-+ if ((xfer->tx_buf) || is_pending)
- val |= SPFI_CONTROL_SEND_DMA;
-- if (xfer->rx_buf)
-+ if (xfer->tx_buf)
-+ val |= SPFI_CONTROL_TX_RX;
-+ if (xfer->rx_buf) {
- val |= SPFI_CONTROL_GET_DMA;
-+ val &= ~SPFI_CONTROL_TX_RX;
-+ }
- val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT);
-- if (xfer->tx_nbits == SPI_NBITS_DUAL &&
-+ if (xfer->tx_nbits == SPI_NBITS_DUAL ||
- xfer->rx_nbits == SPI_NBITS_DUAL)
- val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT;
-- else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
-+ else if (xfer->tx_nbits == SPI_NBITS_QUAD ||
- xfer->rx_nbits == SPI_NBITS_QUAD)
- val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
- val |= SPFI_CONTROL_SE;
+++ /dev/null
-From 905ee06a9966113fe51d6bad1819759cb30fd0bd Mon Sep 17 00:00:00 2001
-From: Ionela Voinescu <ionela.voinescu@imgtec.com>
-Date: Tue, 9 Feb 2016 10:18:31 +0000
-Subject: spi: img-spfi: use device 0 configuration for all devices
-
-Given that we control the chip select line externally
-we can use only one parameter register (device 0 parameter
-register) and one set of configuration bits (port configuration
-bits for device 0) for all devices (all chip select lines).
-
-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
----
- drivers/spi/spi-img-spfi.c | 23 ++++++++++++++++-------
- 1 file changed, 16 insertions(+), 7 deletions(-)
-
---- a/drivers/spi/spi-img-spfi.c
-+++ b/drivers/spi/spi-img-spfi.c
-@@ -429,18 +429,23 @@ static int img_spfi_prepare(struct spi_m
- struct img_spfi *spfi = spi_master_get_devdata(master);
- u32 val;
-
-+ /*
-+ * The chip select line is controlled externally so
-+ * we can use the CS0 configuration for all devices
-+ */
- val = spfi_readl(spfi, SPFI_PORT_STATE);
-+
-+ /* 0 for device selection */
- val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK <<
- SPFI_PORT_STATE_DEV_SEL_SHIFT);
-- val |= msg->spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT;
- if (msg->spi->mode & SPI_CPHA)
-- val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
-+ val |= SPFI_PORT_STATE_CK_PHASE(0);
- else
-- val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
-+ val &= ~SPFI_PORT_STATE_CK_PHASE(0);
- if (msg->spi->mode & SPI_CPOL)
-- val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
-+ val |= SPFI_PORT_STATE_CK_POL(0);
- else
-- val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
-+ val &= ~SPFI_PORT_STATE_CK_POL(0);
- spfi_writel(spfi, val, SPFI_PORT_STATE);
-
- return 0;
-@@ -492,11 +497,15 @@ static void img_spfi_config(struct spi_m
- div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz);
- div = clamp(512 / (1 << get_count_order(div)), 1, 128);
-
-- val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));
-+ /*
-+ * The chip select line is controlled externally so
-+ * we can use the CS0 parameters for all devices
-+ */
-+ val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(0));
- val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK <<
- SPFI_DEVICE_PARAMETER_BITCLK_SHIFT);
- val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
-- spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
-+ spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(0));
-
- if (!list_is_last(&xfer->transfer_list, &master->cur_msg->transfers) &&
- /*
+++ /dev/null
-From 56466f505f58f44b69feb7eaed3b506842800456 Mon Sep 17 00:00:00 2001
-From: Ionela Voinescu <ionela.voinescu@imgtec.com>
-Date: Tue, 1 Mar 2016 17:49:45 +0000
-Subject: spi: img-spfi: RX maximum burst size for DMA is 8
-
-The depth of the FIFOs is 16 bytes. The DMA request line is tied
-to the half full/empty (depending on the use of the TX or RX FIFO)
-threshold. For the TX FIFO, if you set a burst size of 8 (equal to
-half the depth) the first burst goes into FIFO without any issues,
-but due the latency involved (the time the data leaves the DMA
-engine to the time it arrives at the FIFO), the DMA might trigger
-another burst of 8. But given that there is no space for 2 additonal
-bursts of 8, this would result in a failure. Therefore, we have to
-keep the burst size for TX to 4 to accomodate for an extra burst.
-
-For the read (RX) scenario, the DMA request line goes high when
-there is at least 8 entries in the FIFO (half full), and we can
-program the burst size to be 8 because the risk of accidental burst
-does not exist. The DMA engine will not trigger another read until
-the read data for all the burst it has sent out has been received.
-
-While here, move the burst size setting outside of the if/else branches
-as they have the same value for both 8 and 32 bit data widths.
-
-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
----
- drivers/spi/spi-img-spfi.c | 6 ++----
- 1 file changed, 2 insertions(+), 4 deletions(-)
-
---- a/drivers/spi/spi-img-spfi.c
-+++ b/drivers/spi/spi-img-spfi.c
-@@ -338,12 +338,11 @@ static int img_spfi_start_dma(struct spi
- if (xfer->len % 4 == 0) {
- rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;
- rxconf.src_addr_width = 4;
-- rxconf.src_maxburst = 4;
- } else {
- rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;
- rxconf.src_addr_width = 1;
-- rxconf.src_maxburst = 4;
- }
-+ rxconf.src_maxburst = 8;
- dmaengine_slave_config(spfi->rx_ch, &rxconf);
-
- rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl,
-@@ -362,12 +361,11 @@ static int img_spfi_start_dma(struct spi
- if (xfer->len % 4 == 0) {
- txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;
- txconf.dst_addr_width = 4;
-- txconf.dst_maxburst = 4;
- } else {
- txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;
- txconf.dst_addr_width = 1;
-- txconf.dst_maxburst = 4;
- }
-+ txconf.dst_maxburst = 4;
- dmaengine_slave_config(spfi->tx_ch, &txconf);
-
- txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,
+++ /dev/null
-From 5fcca3fd4b621d7b5bdeca18d36dfc6ca6cfe383 Mon Sep 17 00:00:00 2001
-From: Ionela Voinescu <ionela.voinescu@imgtec.com>
-Date: Wed, 10 Aug 2016 11:42:26 +0100
-Subject: spi: img-spfi: finish every transfer cleanly
-
-Before this change, the interrupt status bit that signaled
-the end of a tranfers was cleared in the wait_all_done
-function. That functionality triggered issues for DMA
-duplex transactions where the wait function was called
-twice, in both the TX and RX callbacks.
-
-In order to fix the issue, clear all interrupt data bits
-at the end of a PIO transfer or at the end of both TX and RX
-duplex transfers, if the transfer is not a pending tranfer
-(command waiting for data). After that, the status register
-is checked for new incoming data or new data requests to be
-signaled. If SPFI finished cleanly, no new interrupt data
-bits should be set.
-
-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
----
- drivers/spi/spi-img-spfi.c | 49 +++++++++++++++++++++++++++++++++-------------
- 1 file changed, 35 insertions(+), 14 deletions(-)
-
---- a/drivers/spi/spi-img-spfi.c
-+++ b/drivers/spi/spi-img-spfi.c
-@@ -79,6 +79,14 @@
- #define SPFI_INTERRUPT_SDE BIT(1)
- #define SPFI_INTERRUPT_SDTRIG BIT(0)
-
-+#define SPFI_INTERRUPT_DATA_BITS (SPFI_INTERRUPT_SDHF |\
-+ SPFI_INTERRUPT_SDFUL |\
-+ SPFI_INTERRUPT_GDEX32BIT |\
-+ SPFI_INTERRUPT_GDHF |\
-+ SPFI_INTERRUPT_GDFUL |\
-+ SPFI_INTERRUPT_ALLDONETRIG |\
-+ SPFI_INTERRUPT_GDEX8BIT)
-+
- /*
- * There are four parallel FIFOs of 16 bytes each. The word buffer
- * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an
-@@ -136,6 +144,23 @@ static inline void spfi_reset(struct img
- spfi_writel(spfi, 0, SPFI_CONTROL);
- }
-
-+static inline void spfi_finish(struct img_spfi *spfi)
-+{
-+ if (!(spfi->complete))
-+ return;
-+
-+ /* Clear data bits as all transfers(TX and RX) have finished */
-+ spfi_writel(spfi, SPFI_INTERRUPT_DATA_BITS, SPFI_INTERRUPT_CLEAR);
-+ if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) & SPFI_INTERRUPT_DATA_BITS) {
-+ dev_err(spfi->dev, "SPFI did not finish transfer cleanly.\n");
-+ spfi_reset(spfi);
-+ }
-+ /* Disable SPFI for it not to interfere with pending transactions */
-+ spfi_writel(spfi,
-+ spfi_readl(spfi, SPFI_CONTROL) & ~SPFI_CONTROL_SPFI_EN,
-+ SPFI_CONTROL);
-+}
-+
- static int spfi_wait_all_done(struct img_spfi *spfi)
- {
- unsigned long timeout = jiffies + msecs_to_jiffies(50);
-@@ -144,19 +169,9 @@ static int spfi_wait_all_done(struct img
- return 0;
-
- while (time_before(jiffies, timeout)) {
-- u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
--
-- if (status & SPFI_INTERRUPT_ALLDONETRIG) {
-- spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG,
-- SPFI_INTERRUPT_CLEAR);
-- /*
-- * Disable SPFI for it not to interfere with
-- * pending transactions
-- */
-- spfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL)
-- & ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL);
-+ if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) &
-+ SPFI_INTERRUPT_ALLDONETRIG)
- return 0;
-- }
- cpu_relax();
- }
-
-@@ -288,6 +303,8 @@ static int img_spfi_start_pio(struct spi
- }
-
- ret = spfi_wait_all_done(spfi);
-+ spfi_finish(spfi);
-+
- if (ret < 0)
- return ret;
-
-@@ -303,8 +320,10 @@ static void img_spfi_dma_rx_cb(void *dat
-
- spin_lock_irqsave(&spfi->lock, flags);
- spfi->rx_dma_busy = false;
-- if (!spfi->tx_dma_busy)
-+ if (!spfi->tx_dma_busy) {
-+ spfi_finish(spfi);
- spi_finalize_current_transfer(spfi->master);
-+ }
- spin_unlock_irqrestore(&spfi->lock, flags);
- }
-
-@@ -317,8 +336,10 @@ static void img_spfi_dma_tx_cb(void *dat
-
- spin_lock_irqsave(&spfi->lock, flags);
- spfi->tx_dma_busy = false;
-- if (!spfi->rx_dma_busy)
-+ if (!spfi->rx_dma_busy) {
-+ spfi_finish(spfi);
- spi_finalize_current_transfer(spfi->master);
-+ }
- spin_unlock_irqrestore(&spfi->lock, flags);
- }
-
+++ /dev/null
-From 3642843a06025ec333d7e92580cf52cb8db2a652 Mon Sep 17 00:00:00 2001
-From: Govindraj Raja <Govindraj.Raja@imgtec.com>
-Date: Fri, 8 Jan 2016 16:36:07 +0000
-Subject: clk: pistachio: Fix wrong SDHost card speed
-
-The SDHost currently clocks the card 4x slower than it
-should do, because there is fixed divide by 4 in the
-sdhost wrapper that is not present in the clock tree.
-To model this add a fixed divide by 4 clock node in
-the SDHost clock path.
-
-This will ensure the right clock frequency is selected when
-the mmc driver tries to configure frequency on card insert.
-
-Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
----
- drivers/clk/pistachio/clk-pistachio.c | 3 ++-
- include/dt-bindings/clock/pistachio-clk.h | 1 +
- 2 files changed, 3 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/pistachio/clk-pistachio.c
-+++ b/drivers/clk/pistachio/clk-pistachio.c
-@@ -41,7 +41,7 @@ static struct pistachio_gate pistachio_g
- GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
- 0x104, 22),
- GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
-- GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
-+ GATE(CLK_SD_HOST, "sd_host", "sd_host_div4", 0x104, 24),
- GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
- GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
- GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
-@@ -51,6 +51,7 @@ static struct pistachio_gate pistachio_g
- static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {
- FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),
- FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),
-+ FIXED_FACTOR(CLK_SDHOST_DIV4, "sd_host_div4", "sd_host_div", 4),
- };
-
- static struct pistachio_div pistachio_divs[] __initdata = {
---- a/include/dt-bindings/clock/pistachio-clk.h
-+++ b/include/dt-bindings/clock/pistachio-clk.h
-@@ -18,6 +18,7 @@
- /* Fixed-factor clocks */
- #define CLK_WIFI_DIV4 16
- #define CLK_WIFI_DIV8 17
-+#define CLK_SDHOST_DIV4 18
-
- /* Gate clocks */
- #define CLK_MIPS 32
+++ /dev/null
-From 981c1d416af45eff207227aec106381ac23aac99 Mon Sep 17 00:00:00 2001
-From: Ian Pozella <Ian.Pozella@imgtec.com>
-Date: Mon, 20 Feb 2017 10:00:52 +0000
-Subject: MIPS: DTS: img: marduk: switch mmc to 1 bit mode
-
-The mmc block in Pistachio allows 1 to 8 data bits to be used.
-Marduk uses 4 bits allowing the upper 4 bits to be allocated
-to the Mikrobus ports. However these bits are still connected
-internally meaning the mmc block recieves signals on all data lines
-and seems the internal HW CRC checks get corrupted by this erroneous
-data.
-
-We cannot control what data is sent on these lines because they go
-to external ports. 1 bit mode does not exhibit the issue hence the
-safe default is to use this. If a user knows that in their use case
-they will not use the upper bits then they can set to 4 bit mode in
-order to improve performance.
-
-Also make sure that the upper 4 bits don't get allocated to the mmc
-driver (the default is to assign all 8 pins) so they can be allocated
-to other drivers. Allocating all 4 despite setting 1 bit mode as this
-matches what is there in hardware.
-
-Signed-off-by: Ian Pozella <Ian.Pozella@imgtec.com>
----
- arch/mips/boot/dts/img/pistachio_marduk.dts | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/arch/mips/boot/dts/img/pistachio_marduk.dts
-+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
-@@ -118,7 +118,7 @@
-
- &sdhost {
- status = "okay";
-- bus-width = <4>;
-+ bus-width = <1>;
- disable-wp;
- };
-
-@@ -128,6 +128,7 @@
-
- &pin_sdhost_data {
- drive-strength = <2>;
-+ pins = "mfio17", "mfio18", "mfio19", "mfio20";
- };
-
- &pwm {
+++ /dev/null
-From f32bc2aa01edcba2f2ed5db151cf183eac9ef919 Mon Sep 17 00:00:00 2001
-From: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>
-Date: Sat, 25 Feb 2017 16:42:50 +0000
-Subject: mtd: nor: support mtd name from device tree
-
-Signed-off-by: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>
----
- drivers/mtd/spi-nor/spi-nor.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/spi-nor/core.c
-+++ b/drivers/mtd/spi-nor/core.c
-@@ -3108,6 +3108,7 @@ int spi_nor_scan(struct spi_nor *nor, co
- struct device *dev = nor->dev;
- struct mtd_info *mtd = &nor->mtd;
- struct device_node *np = spi_nor_get_flash_node(nor);
-+ const char __maybe_unused *of_mtd_name = NULL;
- int ret;
- int i;
-
-@@ -3162,7 +3163,12 @@ int spi_nor_scan(struct spi_nor *nor, co
- if (ret)
- return ret;
-
-- if (!mtd->name)
-+#ifdef CONFIG_MTD_OF_PARTS
-+ of_property_read_string(np, "linux,mtd-name", &of_mtd_name);
-+#endif
-+ if (of_mtd_name)
-+ mtd->name = of_mtd_name;
-+ else if (!mtd->name)
- mtd->name = dev_name(dev);
- mtd->priv = nor;
- mtd->type = MTD_NORFLASH;
---- a/drivers/mtd/mtdcore.c
-+++ b/drivers/mtd/mtdcore.c
-@@ -870,6 +870,17 @@ out_error:
- */
- static void mtd_set_dev_defaults(struct mtd_info *mtd)
- {
-+#ifdef CONFIG_MTD_OF_PARTS
-+ const char __maybe_unused *of_mtd_name = NULL;
-+ struct device_node *np;
-+
-+ np = mtd_get_of_node(mtd);
-+ if (np && !mtd->name) {
-+ of_property_read_string(np, "linux,mtd-name", &of_mtd_name);
-+ if (of_mtd_name)
-+ mtd->name = of_mtd_name;
-+ } else
-+#endif
- if (mtd->dev.parent) {
- if (!mtd->owner && mtd->dev.parent->driver)
- mtd->owner = mtd->dev.parent->driver->owner;
+++ /dev/null
-From 0023c706f7e0f0f02bd48a63a2f3c04c839532ae Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sat, 15 Aug 2020 16:04:53 +0200
-Subject: [PATCH 901/904] MIPS: DTS: img: marduk: Add SPI NAND flash
-
-Add Gigadevice GD5F4GQ4UCYIGT SPI NAND flash to the device tree.
-
-The NAND flash chip is connected with quad SPI, but reading currently
-fails in quad SPI mode.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- arch/mips/boot/dts/img/pistachio_marduk.dts | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/mips/boot/dts/img/pistachio_marduk.dts
-+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
-@@ -89,6 +89,12 @@
- reg = <0>;
- spi-max-frequency = <50000000>;
- };
-+
-+ flash@1 {
-+ compatible = "spi-nand";
-+ reg = <1>;
-+ spi-max-frequency = <50000000>;
-+ };
- };
-
- &uart0 {
+++ /dev/null
-From b7700154d75e8d7c9a2022f09c2d5430137606fa Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sat, 15 Aug 2020 16:05:25 +0200
-Subject: [PATCH 902/904] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN
-
-Add Cascoda CA8210 6LoWPAN controller to device tree.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- arch/mips/boot/dts/img/pistachio_marduk.dts | 22 +++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/mips/boot/dts/img/pistachio_marduk.dts
-+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
-@@ -76,6 +76,28 @@
- VDD-supply = <&internal_dac_supply>;
- };
-
-+&spfi0 {
-+ status = "okay";
-+ pinctrl-0 = <&spim0_pins>, <&spim0_cs0_alt_pin>, <&spim0_cs2_alt_pin>, <&spim0_cs3_alt_pin>, <&spim0_cs4_alt_pin>;
-+ pinctrl-names = "default";
-+
-+ cs-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>, <&gpio0 2 GPIO_ACTIVE_HIGH>,
-+ <&gpio1 12 GPIO_ACTIVE_HIGH>, <&gpio1 13 GPIO_ACTIVE_HIGH>;
-+
-+ ca8210: ca8210@0 {
-+ status = "okay";
-+ compatible = "cascoda,ca8210";
-+ reg = <0>;
-+ spi-max-frequency = <4000000>;
-+ spi-cpol;
-+ reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
-+ irq-gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
-+ extclock-enable;
-+ extclock-freq = <16000000>;
-+ extclock-gpio = <2>;
-+ };
-+};
-+
- &spfi1 {
- status = "okay";
-
+++ /dev/null
-From ad4eba0c36ce8af6ab9ea1bc163e4c1ac7c271c3 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sat, 15 Aug 2020 16:09:02 +0200
-Subject: [PATCH 903/904] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW
-
-Add NXP SC16IS752IPW SPI-UART controller to device tree.
-
-This controller drives 2 UARTs and 7 LEDs on the board.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- arch/mips/boot/dts/img/pistachio_marduk.dts | 51 +++++++++++++++++++++
- 1 file changed, 51 insertions(+)
-
---- a/arch/mips/boot/dts/img/pistachio_marduk.dts
-+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
-@@ -46,6 +46,46 @@
- regulator-max-microvolt = <1800000>;
- };
-
-+ /* EXT clock from ca8210 is fed to sc16is752 */
-+ ca8210_ext_clk: ca8210-ext-clk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <16000000>;
-+ clock-output-names = "ca8210_ext_clock";
-+ };
-+
-+ gpioleds {
-+ compatible = "gpio-leds";
-+ user1 {
-+ label = "marduk:red:user1";
-+ gpios = <&sc16is752 0 GPIO_ACTIVE_LOW>;
-+ };
-+ user2 {
-+ label = "marduk:red:user2";
-+ gpios = <&sc16is752 1 GPIO_ACTIVE_LOW>;
-+ };
-+ user3 {
-+ label = "marduk:red:user3";
-+ gpios = <&sc16is752 2 GPIO_ACTIVE_LOW>;
-+ };
-+ user4 {
-+ label = "marduk:red:user4";
-+ gpios = <&sc16is752 3 GPIO_ACTIVE_LOW>;
-+ };
-+ user5 {
-+ label = "marduk:red:user5";
-+ gpios = <&sc16is752 4 GPIO_ACTIVE_LOW>;
-+ };
-+ user6 {
-+ label = "marduk:red:user6";
-+ gpios = <&sc16is752 5 GPIO_ACTIVE_LOW>;
-+ };
-+ user7 {
-+ label = "marduk:red:user7";
-+ gpios = <&sc16is752 6 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+
- led-controller {
- compatible = "pwm-leds";
-
-@@ -96,6 +136,17 @@
- extclock-freq = <16000000>;
- extclock-gpio = <2>;
- };
-+
-+ sc16is752: sc16is752@1 {
-+ compatible = "nxp,sc16is752";
-+ reg = <1>;
-+ clocks = <&ca8210_ext_clk>;
-+ spi-max-frequency = <4000000>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ };
- };
-
- &spfi1 {
+++ /dev/null
-From ff0e950b605047bf50d470023e0fb2fc2003a0f0 Mon Sep 17 00:00:00 2001
-From: Ian Pozella <Ian.Pozella@imgtec.com>
-Date: Mon, 20 Feb 2017 10:38:07 +0000
-Subject: [PATCH 904/904] MIPS: DTS: img: marduk: Add partition name
-
-Signed-off-by: Ian Pozella <Ian.Pozella@imgtec.com>
----
- arch/mips/boot/dts/img/pistachio_marduk.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/mips/boot/dts/img/pistachio_marduk.dts
-+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
-@@ -161,12 +161,14 @@
- compatible = "spansion,s25fl016k", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
-+ linux,mtd-name = "spi-nor";
- };
-
- flash@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <50000000>;
-+ linux,mtd-name = "spi-nand";
- };
- };
-
+++ /dev/null
---- a/arch/mips/boot/dts/img/pistachio_marduk.dts
-+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
-@@ -19,6 +19,11 @@
- ethernet0 = &enet;
- spi0 = &spfi0;
- spi1 = &spfi1;
-+
-+ led-boot = &led_heartbeat;
-+ led-failsafe = &led_heartbeat;
-+ led-running = &led_heartbeat;
-+ led-upgrade = &led_heartbeat;
- };
-
- chosen {
-@@ -89,11 +94,10 @@
- led-controller {
- compatible = "pwm-leds";
-
-- led-1 {
-+ led_heartbeat: heartbeat {
- label = "marduk:red:heartbeat";
- pwms = <&pwm 3 300000>;
- max-brightness = <255>;
-- linux,default-trigger = "heartbeat";
- };
- };
-
+++ /dev/null
-From 58d03770ac5f78ff2d819caabea9371a041bf7be Mon Sep 17 00:00:00 2001
-From: Zoltan HERPAI <wigyori@uid0.hu>
-Date: Wed, 20 Mar 2024 09:36:02 +0100
-Subject: pwm: img: fix pwm clock lookup
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-22e8e19 has introduced a regression in the imgchip->pwm_clk lookup, whereas
-the clock name has also been renamed to "imgchip". This causes the driver
-failing to load:
-
-[ 0.546905] img-pwm 18101300.pwm: failed to get imgchip clock
-[ 0.553418] img-pwm: probe of 18101300.pwm failed with error -2
-
-Fix this lookup by reverting the clock name back to "pwm".
-
-Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
-Link: https://lore.kernel.org/r/20240320083602.81592-1-wigyori@uid0.hu
-Fixes: 22e8e19a46f7 ("pwm: img: Rename variable pointing to driver private data")
-Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
----
- drivers/pwm/pwm-img.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/pwm/pwm-img.c
-+++ b/drivers/pwm/pwm-img.c
-@@ -289,9 +289,9 @@ static int img_pwm_probe(struct platform
- return PTR_ERR(imgchip->sys_clk);
- }
-
-- imgchip->pwm_clk = devm_clk_get(&pdev->dev, "imgchip");
-+ imgchip->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
- if (IS_ERR(imgchip->pwm_clk)) {
-- dev_err(&pdev->dev, "failed to get imgchip clock\n");
-+ dev_err(&pdev->dev, "failed to get pwm clock\n");
- return PTR_ERR(imgchip->pwm_clk);
- }
-
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
-@@ -2942,12 +2942,20 @@ static void spi_nor_set_mtd_info(struct
+@@ -2964,12 +2964,20 @@ static void spi_nor_set_mtd_info(struct
{
struct mtd_info *mtd = &nor->mtd;
struct device *dev = nor->dev;
SUBTARGETS:=generic
KERNEL_PATCHVER:=5.15
+KERNEL_TESTING_PATCHVER:=6.1
KERNELNAME:=zImage
CONFIG_FSL_CORENET_RCPM=y
CONFIG_FSL_DMA=y
CONFIG_FSL_DPAA=y
-# CONFIG_FSL_DPAA2_SWITCH is not set
# CONFIG_FSL_DPAA_CHECKING is not set
CONFIG_FSL_DPAA_ETH=y
CONFIG_FSL_EMB_PERFMON=y
CONFIG_FS_MBCACHE=y
CONFIG_FS_POSIX_ACL=y
CONFIG_FTL=y
+CONFIG_FUNCTION_ALIGNMENT=0
CONFIG_FUNCTION_ERROR_INJECTION=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
--- /dev/null
+CONFIG_64BIT=y
+CONFIG_ALTIVEC=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=13
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=32
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y
+CONFIG_ASN1=y
+CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
+CONFIG_AUDIT_ARCH=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BOOKE=y
+CONFIG_BOOKE_OR_40x=y
+CONFIG_BOOKE_WDT=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLK_QORIQ=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CORENET_GENERIC=y
+# CONFIG_CPUFREQ_DT is not set
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_STAT is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_TEO=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32C_VPMSUM is not set
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
+CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
+# CONFIG_CRYPTO_DEV_NX is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ENGINE=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+# CONFIG_CRYPTO_MD5_PPC is not set
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RSA=y
+# CONFIG_CRYPTO_SHA1_PPC is not set
+CONFIG_CRYPTO_XTS=y
+CONFIG_DATA_SHIFT=12
+CONFIG_DEBUG_INFO=y
+CONFIG_DEFAULT_UIMAGE=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_OPS_BYPASS=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_E5500_CPU is not set
+CONFIG_E6500_CPU=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+# CONFIG_EDAC_CPC925 is not set
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_MPC85XX=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EPAPR_PARAVIRT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_F2FS_FS=y
+CONFIG_FIXED_PHY=y
+# CONFIG_FSL_BMAN_TEST is not set
+CONFIG_FSL_CORENET_CF=y
+CONFIG_FSL_CORENET_RCPM=y
+CONFIG_FSL_DMA=y
+CONFIG_FSL_DPAA=y
+# CONFIG_FSL_DPAA_CHECKING is not set
+CONFIG_FSL_DPAA_ETH=y
+CONFIG_FSL_EMB_PERFMON=y
+CONFIG_FSL_FMAN=y
+CONFIG_FSL_GUTS=y
+CONFIG_FSL_IFC=y
+CONFIG_FSL_LBC=y
+CONFIG_FSL_MPIC_TIMER_WAKEUP=y
+CONFIG_FSL_PAMU=y
+CONFIG_FSL_PCI=y
+# CONFIG_FSL_QMAN_TEST is not set
+CONFIG_FSL_SOC=y
+CONFIG_FSL_SOC_BOOKE=y
+CONFIG_FSL_XGMAC_MDIO=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FTL=y
+CONFIG_FUNCTION_ERROR_INJECTION=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+# CONFIG_GEN_RTC is not set
+# CONFIG_GIANFAR is not set
+CONFIG_GLOB=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_GRO_CELLS=y
+# CONFIG_HANGCHECK_TIMER is not set
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_MPC=y
+CONFIG_ILLEGAL_POINTER_VALUE=0x5deadbeef0000000
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+CONFIG_IOMMU_HELPER=y
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_ISA_DMA_API=y
+CONFIG_JBD2=y
+CONFIG_JUMP_LABEL=y
+CONFIG_JUMP_LABEL_FEATURE_CHECKS=y
+# CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG is not set
+CONFIG_KALLSYMS=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_KERNEL_START=0xc000000000000000
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MATH_EMULATION=y
+# CONFIG_MATH_EMULATION_FULL is not set
+CONFIG_MATH_EMULATION_HW_UNIMPLEMENTED=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_WBSD is not set
+CONFIG_MMIOWB=y
+CONFIG_MMU_GATHER_MERGE_VMAS=y
+CONFIG_MMU_GATHER_PAGE_SIZE=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MPIC=y
+CONFIG_MPIC_MSGR=y
+CONFIG_MPIC_TIMER=y
+CONFIG_MPILIB=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MV88E6XXX=y
+CONFIG_NET_DSA_TAG_DSA=y
+CONFIG_NET_DSA_TAG_DSA_COMMON=y
+CONFIG_NET_DSA_TAG_EDSA=y
+CONFIG_NET_DSA_TAG_OCELOT=y
+CONFIG_NET_DSA_TAG_TRAILER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NONSTATIC_KERNEL=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=24
+CONFIG_NR_IRQS=512
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DMA_DEFAULT_COHERENT=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGSUSPEND=y
+CONFIG_OPTPROBES=y
+CONFIG_PACKING=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xc000000000000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_ARCH_FALLBACKS=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCS_LYNX=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYSICAL_START=0x00000000
+CONFIG_PHYS_64BIT=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PM=y
+# CONFIG_PMU_SYSFS is not set
+CONFIG_PM_CLK=y
+CONFIG_PPC=y
+CONFIG_PPC64=y
+CONFIG_PPC64_ELF_ABI_V1=y
+CONFIG_PPC_ADV_DEBUG_DACS=2
+CONFIG_PPC_ADV_DEBUG_DVCS=0
+CONFIG_PPC_ADV_DEBUG_IACS=2
+CONFIG_PPC_ADV_DEBUG_REGS=y
+CONFIG_PPC_BARRIER_NOSPEC=y
+CONFIG_PPC_BOOK3E_64=y
+# CONFIG_PPC_BOOK3S_64 is not set
+CONFIG_PPC_DAWR=y
+CONFIG_PPC_DOORBELL=y
+CONFIG_PPC_E500=y
+CONFIG_PPC_E500MC=y
+# CONFIG_PPC_EARLY_DEBUG is not set
+CONFIG_PPC_EPAPR_HV_PIC=y
+CONFIG_PPC_FPU=y
+CONFIG_PPC_FPU_REGS=y
+CONFIG_PPC_INDIRECT_PCI=y
+# CONFIG_PPC_IRQ_SOFT_MASK_DEBUG is not set
+CONFIG_PPC_KUAP=y
+# CONFIG_PPC_KUAP_DEBUG is not set
+CONFIG_PPC_KUEP=y
+CONFIG_PPC_MMU_NOHASH=y
+CONFIG_PPC_MSI_BITMAP=y
+CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
+CONFIG_PPC_PAGE_SHIFT=12
+# CONFIG_PPC_QEMU_E500 is not set
+CONFIG_PPC_QUEUED_SPINLOCKS=y
+CONFIG_PPC_SMP_MUXED_IPI=y
+CONFIG_PPC_UDBG_16550=y
+CONFIG_PPC_WERROR=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTE_64BIT=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK_QORIQ=y
+CONFIG_QORIQ_CPUFREQ=y
+CONFIG_QORIQ_THERMAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELOCATABLE=y
+# CONFIG_RELOCATABLE_TEST is not set
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SCOM_DEBUGFS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_FSL_LINFLEXUART=y
+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_ESPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SRCU=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_TARGET_CPU="e6500"
+CONFIG_TARGET_CPU_BOOL=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_THREAD_SHIFT=14
+# CONFIG_TOOLCHAIN_DEFAULT_CPU is not set
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+# CONFIG_UACCE is not set
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_UAS=y
+CONFIG_VGA_CONSOLE=y
+CONFIG_VIRT_CPU_ACCOUNTING=y
+CONFIG_VIRT_CPU_ACCOUNTING_NATIVE=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XPS=y
+CONFIG_ZLIB_DEFLATE=y
BOARD:=qualcommax
BOARDNAME:=Qualcomm Atheros 802.11ax WiSoC-s
FEATURES:=squashfs ramdisk fpu nand rtc emmc
-KERNELNAME:=Image dtbs
+KERNELNAME:=Image
CPU_TYPE:=cortex-a53
SUBTARGETS:=ipq807x ipq60xx
+++ /dev/null
-CONFIG_64BIT=y
-# CONFIG_APQ_GCC_8084 is not set
-# CONFIG_APQ_MMCC_8084 is not set
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_ERRATUM_1165522=y
-CONFIG_ARM64_ERRATUM_1286807=y
-CONFIG_ARM64_ERRATUM_2051678=y
-CONFIG_ARM64_ERRATUM_2054223=y
-CONFIG_ARM64_ERRATUM_2067961=y
-CONFIG_ARM64_ERRATUM_2077057=y
-CONFIG_ARM64_ERRATUM_2658417=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_ARM64_SME=y
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
-CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
-CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-# CONFIG_ARM_MHU_V2 is not set
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
-CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
-CONFIG_AT803X_PHY=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_PM=y
-CONFIG_CAVIUM_TX2_ERRATUM_219=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_COREDUMP=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_FREQ_THERMAL=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRC16=y
-CONFIG_CRC8=y
-CONFIG_CRYPTO_AUTHENC=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DEV_QCE=y
-CONFIG_CRYPTO_DEV_QCE_AEAD=y
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
-CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
-CONFIG_CRYPTO_DEV_QCE_SHA=y
-CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
-CONFIG_CRYPTO_DEV_QCOM_RNG=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEV_COREDUMP=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FUJITSU_ERRATUM_010001=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_QCOM=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-# CONFIG_I2C_QCOM_CCI is not set
-CONFIG_I2C_QUP=y
-CONFIG_IIO=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IPQ_APSS_6018=y
-CONFIG_IPQ_APSS_PLL=y
-# CONFIG_IPQ_GCC_4019 is not set
-# CONFIG_IPQ_GCC_6018 is not set
-# CONFIG_IPQ_GCC_806X is not set
-# CONFIG_IPQ_GCC_8074 is not set
-# CONFIG_IPQ_LCC_806X is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_KPSS_XCC is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_IPQ4019=y
-# CONFIG_MDM_GCC_9615 is not set
-# CONFIG_MDM_LCC_9615 is not set
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_QCOM_RPM is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_MSM=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MSM_GCC_8660 is not set
-# CONFIG_MSM_GCC_8909 is not set
-# CONFIG_MSM_GCC_8916 is not set
-# CONFIG_MSM_GCC_8939 is not set
-# CONFIG_MSM_GCC_8960 is not set
-# CONFIG_MSM_GCC_8974 is not set
-# CONFIG_MSM_GCC_8976 is not set
-# CONFIG_MSM_GCC_8994 is not set
-# CONFIG_MSM_GCC_8996 is not set
-# CONFIG_MSM_GCC_8998 is not set
-# CONFIG_MSM_GPUCC_8998 is not set
-# CONFIG_MSM_LCC_8960 is not set
-# CONFIG_MSM_MMCC_8960 is not set
-# CONFIG_MSM_MMCC_8974 is not set
-# CONFIG_MSM_MMCC_8996 is not set
-# CONFIG_MSM_MMCC_8998 is not set
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_QCOM=y
-CONFIG_MTD_QCOMSMEM_PARTS=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_QCOM_QFPROM=y
-# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_U_BOOT_ENV=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_QCOM=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-# CONFIG_PHY_QCOM_EDP is not set
-# CONFIG_PHY_QCOM_IPQ4019_USB is not set
-# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
-# CONFIG_PHY_QCOM_IPQ806X_USB is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-CONFIG_PHY_QCOM_QMP=y
-CONFIG_PHY_QCOM_QUSB2=y
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_IPQ6018 is not set
-# CONFIG_PINCTRL_IPQ8074 is not set
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_MSM8916 is not set
-# CONFIG_PINCTRL_MSM8976 is not set
-# CONFIG_PINCTRL_MSM8994 is not set
-# CONFIG_PINCTRL_MSM8996 is not set
-# CONFIG_PINCTRL_MSM8998 is not set
-# CONFIG_PINCTRL_QCM2290 is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_QCS404 is not set
-# CONFIG_PINCTRL_SC7180 is not set
-# CONFIG_PINCTRL_SC8280XP is not set
-# CONFIG_PINCTRL_SDM660 is not set
-# CONFIG_PINCTRL_SDM845 is not set
-# CONFIG_PINCTRL_SM6350 is not set
-# CONFIG_PINCTRL_SM6375 is not set
-# CONFIG_PINCTRL_SM8150 is not set
-# CONFIG_PINCTRL_SM8250 is not set
-# CONFIG_PINCTRL_SM8450 is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_OPP=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_MSM is not set
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QCA807X_PHY=y
-CONFIG_QCA808X_PHY=y
-# CONFIG_QCM_DISPCC_2290 is not set
-# CONFIG_QCM_GCC_2290 is not set
-# CONFIG_QCOM_A53PLL is not set
-# CONFIG_QCOM_AOSS_QMP is not set
-CONFIG_QCOM_APCS_IPC=y
-# CONFIG_QCOM_APM is not set
-# CONFIG_QCOM_APR is not set
-CONFIG_QCOM_BAM_DMA=y
-# CONFIG_QCOM_CLK_APCC_MSM8996 is not set
-# CONFIG_QCOM_CLK_APCS_MSM8916 is not set
-# CONFIG_QCOM_CLK_APCS_SDX55 is not set
-# CONFIG_QCOM_COMMAND_DB is not set
-# CONFIG_QCOM_CPR is not set
-# CONFIG_QCOM_EBI2 is not set
-# CONFIG_QCOM_FASTRPC is not set
-# CONFIG_QCOM_GENI_SE is not set
-# CONFIG_QCOM_GSBI is not set
-# CONFIG_QCOM_HFPLL is not set
-# CONFIG_QCOM_ICC_BWMON is not set
-# CONFIG_QCOM_IPCC is not set
-# CONFIG_QCOM_LLCC is not set
-CONFIG_QCOM_MDT_LOADER=y
-# CONFIG_QCOM_MPM is not set
-CONFIG_QCOM_NET_PHYLIB=y
-# CONFIG_QCOM_OCMEM is not set
-# CONFIG_QCOM_PDC is not set
-CONFIG_QCOM_PIL_INFO=y
-# CONFIG_QCOM_Q6V5_ADSP is not set
-CONFIG_QCOM_Q6V5_COMMON=y
-# CONFIG_QCOM_Q6V5_MSS is not set
-# CONFIG_QCOM_Q6V5_PAS is not set
-CONFIG_QCOM_Q6V5_WCSS=y
-# CONFIG_QCOM_RMTFS_MEM is not set
-# CONFIG_QCOM_RPMH is not set
-CONFIG_QCOM_RPROC_COMMON=y
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-# CONFIG_QCOM_SMD_RPM is not set
-CONFIG_QCOM_SMEM=y
-CONFIG_QCOM_SMEM_STATE=y
-CONFIG_QCOM_SMP2P=y
-# CONFIG_QCOM_SMSM is not set
-CONFIG_QCOM_SOCINFO=y
-# CONFIG_QCOM_SPM is not set
-# CONFIG_QCOM_STATS is not set
-# CONFIG_QCOM_SYSMON is not set
-CONFIG_QCOM_TSENS=y
-# CONFIG_QCOM_WCNSS_CTRL is not set
-# CONFIG_QCOM_WCNSS_PIL is not set
-CONFIG_QCOM_WDT=y
-# CONFIG_QCS_GCC_404 is not set
-# CONFIG_QCS_Q6SSTOP_404 is not set
-# CONFIG_QCS_TURING_404 is not set
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_CPR3 is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
-CONFIG_RELOCATABLE=y
-CONFIG_REMOTEPROC=y
-CONFIG_REMOTEPROC_CDEV=y
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPMSG=y
-CONFIG_RPMSG_CHAR=y
-# CONFIG_RPMSG_CTRL is not set
-# CONFIG_RPMSG_NS is not set
-CONFIG_RPMSG_QCOM_GLINK=y
-CONFIG_RPMSG_QCOM_GLINK_RPM=y
-CONFIG_RPMSG_QCOM_GLINK_SMEM=y
-CONFIG_RPMSG_QCOM_SMD=y
-# CONFIG_RPMSG_TTY is not set
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_SMT=y
-CONFIG_SCHED_THERMAL_PRESSURE=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_PROC_FS is not set
-# CONFIG_SC_CAMCC_7280 is not set
-# CONFIG_SC_DISPCC_7180 is not set
-# CONFIG_SC_GCC_7180 is not set
-# CONFIG_SC_GCC_8280XP is not set
-# CONFIG_SC_GPUCC_7180 is not set
-# CONFIG_SC_LPASSCC_7280 is not set
-# CONFIG_SC_LPASS_CORECC_7180 is not set
-# CONFIG_SC_LPASS_CORECC_7280 is not set
-# CONFIG_SC_MSS_7180 is not set
-# CONFIG_SC_VIDEOCC_7180 is not set
-# CONFIG_SDM_CAMCC_845 is not set
-# CONFIG_SDM_DISPCC_845 is not set
-# CONFIG_SDM_GCC_660 is not set
-# CONFIG_SDM_GCC_845 is not set
-# CONFIG_SDM_GPUCC_845 is not set
-# CONFIG_SDM_LPASSCC_845 is not set
-# CONFIG_SDM_VIDEOCC_845 is not set
-# CONFIG_SDX_GCC_65 is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-# CONFIG_SM_CAMCC_8450 is not set
-# CONFIG_SM_GCC_8150 is not set
-# CONFIG_SM_GCC_8250 is not set
-# CONFIG_SM_GCC_8450 is not set
-# CONFIG_SM_GPUCC_6350 is not set
-# CONFIG_SM_GPUCC_8150 is not set
-# CONFIG_SM_GPUCC_8250 is not set
-# CONFIG_SM_GPUCC_8350 is not set
-# CONFIG_SM_VIDEOCC_8150 is not set
-# CONFIG_SM_VIDEOCC_8250 is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_QUP=y
-CONFIG_SRCU=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_ANCHOR=y
-# CONFIG_VIRTIO_BLK is not set
-# CONFIG_VIRTIO_NET is not set
-CONFIG_VMAP_STACK=y
-CONFIG_WANT_DEV_COREDUMP=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_SYSFS=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
};
partition@480000 {
+ compatible = "u-boot,env";
label = "0:appsblenv";
reg = <0x480000 0x10000>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Linksys MX8500";
+ compatible = "linksys,mx8500", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ serial1 = &blsp1_uart3;
+ led-boot = &led_system_blue;
+ led-running = &led_system_blue;
+ led-failsafe = &led_system_red;
+ led-upgrade = &led_system_green;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
+ };
+
+ gpio_export {
+ compatible = "gpio-export";
+ #size-cells = <0>;
+
+ bt_pwr {
+ gpio-export,name = "bt_pwr";
+ gpio-export,output = <1>;
+ gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&button_pins>;
+ pinctrl-names = "default";
+
+ reset-button {
+ label = "reset";
+ gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps-button {
+ label = "wps";
+ gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+};
+
+&tlmm {
+ button_pins: button-state {
+ pins = "gpio64", "gpio67";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio_pins: mdio-state {
+ mdc-pins {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ /*
+ * Bootloader will find the NAND DT node by the compatible and
+ * then "fixup" it by adding the partitions from the SMEM table
+ * using the legacy bindings thus making it impossible for us
+ * to change the partition table or utilize NVMEM for calibration.
+ * So add a dummy partitions node that bootloader will populate
+ * and set it as disabled so the kernel ignores it instead of
+ * printing warnings due to the broken way bootloader adds the
+ * partitions.
+ */
+ partitions {
+ status = "disabled";
+ };
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "0:mibib";
+ reg = <0x100000 0x100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "0:bootconfig";
+ reg = <0x200000 0x80000>;
+ read-only;
+ };
+
+ partition@280000 {
+ label = "0:bootconfig1";
+ reg = <0x280000 0x80000>;
+ read-only;
+ };
+
+ partition@300000 {
+ label = "0:qsee";
+ reg = <0x300000 0x300000>;
+ read-only;
+ };
+
+ partition@600000 {
+ label = "0:qsee_1";
+ reg = <0x600000 0x300000>;
+ read-only;
+ };
+
+ partition@900000 {
+ label = "0:devcfg";
+ reg = <0x900000 0x80000>;
+ read-only;
+ };
+
+ partition@980000 {
+ label = "0:devcfg_1";
+ reg = <0x980000 0x80000>;
+ read-only;
+ };
+
+ partition@a00000 {
+ label = "0:apdp";
+ reg = <0xa00000 0x80000>;
+ read-only;
+ };
+
+ partition@a80000 {
+ label = "0:apdp_1";
+ reg = <0xa80000 0x80000>;
+ read-only;
+ };
+
+ partition@b00000 {
+ label = "0:rpm";
+ reg = <0xb00000 0x80000>;
+ read-only;
+ };
+
+ partition@b80000 {
+ label = "0:rpm_1";
+ reg = <0xb80000 0x80000>;
+ read-only;
+ };
+
+ partition@c00000 {
+ label = "0:cdt";
+ reg = <0xc00000 0x80000>;
+ read-only;
+ };
+
+ partition@c80000 {
+ label = "0:cdt_1";
+ reg = <0xc80000 0x80000>;
+ read-only;
+ };
+
+ partition@d00000 {
+ label = "0:appsblenv";
+ reg = <0xd00000 0x80000>;
+ };
+
+ partition@d80000 {
+ label = "0:appsbl";
+ reg = <0xd80000 0x100000>;
+ read-only;
+ };
+
+ partition@e80000 {
+ label = "0:appsbl_1";
+ reg = <0xe80000 0x100000>;
+ read-only;
+ };
+
+ partition@f80000 {
+ label = "0:art";
+ reg = <0xf80000 0x80000>;
+ read-only;
+ };
+
+ partition@1000000 {
+ label = "u_env";
+ reg = <0x1000000 0x40000>;
+ };
+
+ partition@1040000 {
+ label = "s_env";
+ reg = <0x1040000 0x20000>;
+ };
+
+ partition@1060000 {
+ label = "devinfo";
+ reg = <0x1060000 0x20000>;
+ read-only;
+ };
+
+ partition@1080000 {
+ label = "kernel";
+ reg = <0x1080000 0x9600000>;
+ };
+
+ partition@1680000 {
+ label = "rootfs";
+ reg = <0x1680000 0x9000000>;
+ };
+
+ partition@a680000 {
+ label = "alt_kernel";
+ reg = <0xa680000 0x9600000>;
+ };
+
+ partition@ac80000 {
+ label = "alt_rootfs";
+ reg = <0xac80000 0x9000000>;
+ };
+
+ partition@13c80000 {
+ label = "sysdiag";
+ reg = <0x13c80000 0x200000>;
+ read-only;
+ };
+
+ partition@13e80000 {
+ label = "0:ethphyfw";
+ reg = <0x13e80000 0x100000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aqr_fw: firmware@0 {
+ /* Skip the QCOM MBN Header of 40 bytes */
+ reg = <0x28 0x60002>;
+ };
+ };
+ };
+
+ partition@13f80000 {
+ label = "syscfg";
+ reg = <0x13f80000 0xb180000>;
+ read-only;
+ };
+
+ partition@1f100000 {
+ label = "app_data";
+ reg = <0x1f100000 0x500000>;
+ read-only;
+ };
+
+ partition@1f600000 {
+ label = "0:wififw";
+ reg = <0x1f600000 0xa00000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ led-controller@62 {
+ compatible = "nxp,pca9633";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x62>;
+ nxp,hw-blink;
+
+ led_system_red: led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led_system_green: led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led_system_blue: led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ ethernet-phy-package@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,qca8075-package";
+ reg = <0>;
+
+ qcom,package-mode = "qsgmii";
+
+ qca8075_0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+ };
+
+ aqr114c: ethernet-phy@8 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ firmware-name = "marvell/AQR-G4_v5.6.5-AQR_WNC_SAQA-L2_GT_ID45287_VER24005.cld";
+ nvmem-cells = <&aqr_fw>;
+ nvmem-cell-names = "firmware";
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
+ switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
+ switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
+ switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
+
+ qcom,port_phyinfo {
+ port@1 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+
+ port@2 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+
+ port@3 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+
+ port@4 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+
+ port@6 {
+ port_id = <6>;
+ phy_address = <8>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ ethernet-phy-ieee802.3-c45;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp1 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_0>;
+ label = "lan1";
+};
+
+&dp2 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_1>;
+ label = "lan2";
+};
+
+&dp3 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_2>;
+ label = "lan3";
+};
+
+&dp4 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_3>;
+ label = "lan4";
+};
+
+&dp6_syn {
+ status = "okay";
+ phy-mode = "usxgmii";
+ phy-handle = <&aqr114c>;
+ label = "wan";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&pcie_qmp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi@1,0 {
+ status = "okay";
+
+ /* ath11k has no DT compatible for PCI cards */
+ compatible = "pci17cb,1104";
+ reg = <0x00010000 0 0 0 0>;
+
+ qcom,ath11k-calibration-variant = "Linksys-MX8500";
+ };
+ };
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Linksys-MX8500";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Spectrum SAX1V1K";
+ compatible = "spectrum,sax1v1k", "qcom,ipq8074";
+
+ aliases {
+ led-boot = &led_system_red;
+ led-failsafe = &led_system_red;
+ led-running = &led_system_blue;
+ led-upgrade = &led_system_red;
+ serial0 = &blsp1_uart5;
+ /* Aliases as required by u-boot to patch MAC addresses */
+ ethernet0 = &dp6_syn;
+ ethernet1 = &dp4;
+ ethernet2 = &dp3;
+ ethernet3 = &dp2;
+ label-mac-device = &dp6_syn;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_system_blue: system-blue {
+ gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led_system_red: system-red {
+ gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ ethernet-phy-package@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,qca8075-package";
+ reg = <0>;
+
+ qcom,package-mode = "qsgmii";
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+ };
+
+ qca8081: ethernet-phy@28 {
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <28>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&sdhc_1 {
+ /* Following same rule as QNAP 301W
+ * the emmc has a problem with the hs400 > hs200 speed switch.
+ * Therefore remove the mmc-hs400-1_8v property
+ */
+ /delete-property/ mmc-hs400-1_8v;
+ mmc-hs200-1_8v;
+ mmc-ddr-1_8v;
+ vqmmc-supply = <&l11>;
+ status = "okay";
+};
+
+&switch {
+ switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
+ switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
+ switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
+ switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
+ status = "okay";
+
+ qcom,port_phyinfo {
+ port@2 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+
+ port@3 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+
+ port@4 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+
+ port@6 {
+ port_id = <6>;
+ phy_address = <28>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp2 {
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_1>;
+ label = "lan3";
+ status = "okay";
+};
+
+&dp3 {
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_2>;
+ label = "lan2";
+ status = "okay";
+};
+
+&dp4 {
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_3>;
+ label = "lan1";
+ status = "okay";
+};
+
+&dp6_syn {
+ phy-handle = <&qca8081>;
+ label = "wan";
+ status = "okay";
+};
+
+&wifi {
+ qcom,ath11k-calibration-variant = "Spectrum-SAX1V1K";
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Zbtlink ZBT-Z800AX";
+ compatible = "zbtlink,zbt-z800ax", "qcom,ipq8074";
+
+ aliases {
+ led-boot = &led_net;
+ led-failsafe = &led_net;
+ led-upgrade = &led_net;
+ serial0 = &blsp1_uart5;
+ /*
+ * Aliases as required by u-boot
+ * to patch MAC addresses
+ */
+ ethernet0 = &dp1;
+ ethernet1 = &dp2;
+ ethernet2 = &dp3;
+ ethernet3 = &dp4;
+ ethernet4 = &dp5;
+ label-mac-device = &dp1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_1";
+ };
+
+ gpio-export {
+ compatible = "gpio-export";
+
+ lte-power {
+ gpio-export,name = "lte_power";
+ gpio-export,output = <1>;
+ gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&button_pins>;
+ pinctrl-names = "default";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_net: net {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN_ONLINE;
+ gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+ };
+
+ module {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_MOBILE;
+ gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
+ };
+
+ wlan2g {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_2GHZ;
+ gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy1radio";
+ };
+
+ wlan5g {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_5GHZ;
+ gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0radio";
+ };
+ };
+};
+
+&tlmm {
+ button_pins: button-pins {
+ mux {
+ pins = "gpio34", "gpio46";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_spi1 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ cs-select = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x50000>;
+ read-only;
+ };
+
+ partition@50000 {
+ label = "0:mibib";
+ reg = <0x50000 0x10000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "0:bootconfig";
+ reg = <0x60000 0x20000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "0:bootconfig1";
+ reg = <0x80000 0x20000>;
+ read-only;
+ };
+
+ partition@a0000 {
+ label = "0:qsee";
+ reg = <0xa0000 0x180000>;
+ read-only;
+ };
+
+ partition@220000 {
+ label = "0:qsee_1";
+ reg = <0x220000 0x180000>;
+ read-only;
+ };
+
+ partition@3a0000 {
+ label = "0:devcfg";
+ reg = <0x3a0000 0x10000>;
+ read-only;
+ };
+
+ partition@3b0000 {
+ label = "0:devcfg_1";
+ reg = <0x3b0000 0x10000>;
+ read-only;
+ };
+
+ partition@3c0000 {
+ label = "0:apdp";
+ reg = <0x3c0000 0x10000>;
+ read-only;
+ };
+
+ partition@3d0000 {
+ label = "0:apdp_1";
+ reg = <0x3d0000 0x10000>;
+ read-only;
+ };
+
+ partition@3e0000 {
+ label = "0:rpm";
+ reg = <0x3e0000 0x40000>;
+ read-only;
+ };
+
+ partition@420000 {
+ label = "0:rpm_1";
+ reg = <0x420000 0x40000>;
+ read-only;
+ };
+
+ partition@460000 {
+ label = "0:cdt";
+ reg = <0x460000 0x10000>;
+ read-only;
+ };
+
+ partition@470000 {
+ label = "0:cdt_1";
+ reg = <0x470000 0x10000>;
+ read-only;
+ };
+
+ partition@480000 {
+ label = "0:appsblenv";
+ reg = <0x480000 0x10000>;
+ };
+
+ partition@490000 {
+ label = "0:appsbl";
+ reg = <0x490000 0xa0000>;
+ read-only;
+ };
+
+ partition@530000 {
+ label = "0:appsbl_1";
+ reg = <0x530000 0xa0000>;
+ read-only;
+ };
+
+ partition@5d0000 {
+ label = "0:art";
+ reg = <0x5d0000 0x40000>;
+ read-only;
+ };
+
+ partition@610000 {
+ label = "0:ethphyfw";
+ reg = <0x610000 0x80000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ partitions {
+ status = "disabled";
+ };
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "rootfs";
+ reg = <0x0000000 0x3400000>;
+ };
+
+ partition@3400000 {
+ label = "0:wififw";
+ reg = <0x3400000 0x0800000>;
+ read-only;
+ };
+
+ partition@3c00000 {
+ label = "rootfs_1";
+ reg = <0x3c00000 0x3400000>;
+ };
+
+ partition@7000000 {
+ label = "0:wififw_1";
+ reg = <0x7000000 0x0800000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&qusb_phy_1 {
+ status = "okay";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&ssphy_1 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ ethernet-phy-package@0 {
+ compatible = "qcom,qca8075-package";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ qca8075_0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+
+ qca8075_4: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ };
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>;
+ switch_wan_bmp = <ESS_PORT5>;
+ switch_mac_mode = <MAC_MODE_PSGMII>;
+
+ qcom,port_phyinfo {
+ port@1 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+ port@2 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+ port@3 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+ port@4 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+ port@5 {
+ port_id = <5>;
+ phy_address = <4>;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp1 {
+ status = "okay";
+ phy-handle = <&qca8075_0>;
+ label = "lan1";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_1>;
+ label = "lan2";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan3";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan4";
+};
+
+&dp5 {
+ status = "okay";
+ phy-handle = <&qca8075_4>;
+ label = "wan";
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "ZBT-Z800AX";
+};
endef
TARGET_DEVICES += edimax_cax1800
-define Device/linksys_mx4200v1
+define Device/linksys_mx
$(call Device/FitImage)
DEVICE_VENDOR := Linksys
- DEVICE_MODEL := MX4200
- DEVICE_VARIANT := v1
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_SIZE := 6144k
IMAGE_SIZE := 147456k
NAND_SIZE := 512m
- SOC := ipq8174
+ SOC := ipq8072
IMAGES += factory.bin
- IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MX4200
- DEVICE_PACKAGES := kmod-leds-pca963x ipq-wifi-linksys_mx4200 kmod-bluetooth
+ IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=$$$$(DEVICE_MODEL)
+ DEVICE_PACKAGES := kmod-leds-pca963x
+endef
+
+define Device/linksys_mx4200v1
+ $(call Device/linksys_mx)
+ DEVICE_MODEL := MX4200
+ DEVICE_VARIANT := v1
+ SOC := ipq8174
+ DEVICE_PACKAGES += ipq-wifi-linksys_mx4200 kmod-bluetooth
endef
TARGET_DEVICES += linksys_mx4200v1
TARGET_DEVICES += linksys_mx4200v2
define Device/linksys_mx5300
- $(call Device/FitImage)
- DEVICE_VENDOR := Linksys
+ $(call Device/linksys_mx)
DEVICE_MODEL := MX5300
- BLOCKSIZE := 128k
- PAGESIZE := 2048
- KERNEL_SIZE := 6144k
- IMAGE_SIZE := 147456k
- NAND_SIZE := 512m
- SOC := ipq8072
- IMAGES += factory.bin
- IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MX5300
- DEVICE_PACKAGES := kmod-leds-pca963x kmod-rtc-ds1307 \
- ipq-wifi-linksys_mx5300 kmod-ath10k-ct ath10k-firmware-qca9984-ct
+ DEVICE_PACKAGES += kmod-rtc-ds1307 ipq-wifi-linksys_mx5300 \
+ kmod-ath10k-ct ath10k-firmware-qca9984-ct
endef
TARGET_DEVICES += linksys_mx5300
+define Device/linksys_mx8500
+ $(call Device/linksys_mx)
+ DEVICE_MODEL := MX8500
+ DEVICE_PACKAGES += ipq-wifi-linksys_mx8500 kmod-ath11k-pci \
+ ath11k-firmware-qcn9074 kmod-bluetooth
+endef
+TARGET_DEVICES += linksys_mx8500
+
define Device/netgear_rax120v2
$(call Device/FitImage)
$(call Device/UbiFit)
endef
TARGET_DEVICES += redmi_ax6
+define Device/spectrum_sax1v1k
+ $(call Device/FitImage)
+ $(call Device/EmmcImage)
+ DEVICE_VENDOR := Spectrum
+ DEVICE_MODEL := SAX1V1K
+ DEVICE_DTS_CONFIG := config@rt5010w-d187-rev6
+ SOC := ipq8072
+ IMAGES := sysupgrade.bin
+ DEVICE_PACKAGES := ipq-wifi-spectrum_sax1v1k
+endef
+TARGET_DEVICES += spectrum_sax1v1k
+
define Device/xiaomi_ax3600
$(call Device/FitImage)
$(call Device/UbiFit)
endef
TARGET_DEVICES += yuncore_ax880
+define Device/zbtlink_zbt-z800ax
+ $(call Device/FitImage)
+ $(call Device/UbiFit)
+ DEVICE_VENDOR := Zbtlink
+ DEVICE_MODEL := ZBT-Z800AX
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
+ DEVICE_DTS_CONFIG := config@hk09
+ SOC := ipq8072
+ DEVICE_PACKAGES := ipq-wifi-zbtlink_zbt-z800ax
+ IMAGES += factory.bin
+ IMAGE/factory.bin := append-ubi | qsdk-ipq-factory-nand
+endef
+TARGET_DEVICES += zbtlink_zbt-z800ax
+
define Device/zte_mf269
$(call Device/FitImage)
$(call Device/UbiFit)
START=99
-. /lib/functions.sh
-
boot() {
case $(board_name) in
- yuncore,fap650)
- fw_setenv owrt_bootcount 0
- ;;
- esac
+ yuncore,fap650)
+ fw_setenv owrt_bootcount 0
+ ;;
+ esac
}
ucidef_set_led_netdev "wan-port-link" "WAN-PORT-LINK" "90000.mdio-1:18:green:wan" "wan" "tx rx link_10 link_100 link_1000 link_2500"
ucidef_set_led_netdev "lan-port-link" "LAN-PORT-LINK" "90000.mdio-1:1c:green:lan" "lan" "tx rx link_10 link_100 link_1000 link_2500"
;;
+zbtlink,zbt-z800ax)
+ ucidef_set_led_netdev "internet" "Internet" "green:wan-online" "wan"
+ ;;
esac
board_config_flush
buffalo,wxr-5950ax12|\
dynalink,dl-wrx36|\
linksys,mx5300|\
- xiaomi,ax9000)
+ linksys,mx8500|\
+ xiaomi,ax9000|\
+ zbtlink,zbt-z800ax)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
;;
cmcc,rm2-6)
linksys,mx4200v2|\
prpl,haze|\
redmi,ax6|\
+ spectrum,sax1v1k|\
xiaomi,ax3600)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
;;
local label_mac=""
case "$board" in
- linksys,mx4200v1|\
linksys,mx4200v2)
label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
for i in $(seq 3 5); do
done
[ "$(mtd_get_mac_ascii u_env eth2addr)" != "$label_mac" ] && wan_mac=$label_mac
;;
+ linksys,mx8500)
+ label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
+ lan_mac=$(macaddr_add $label_mac 1)
+ wan_mac=$label_mac
+ ;;
esac
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
dynalink,dl-wrx36|\
edgecore,eap102|\
edimax,cax1800|\
- linksys,mx4200v1|\
- linksys,mx4200v2|\
linksys,mx5300|\
- netgear,rax120v2|\
netgear,wax218|\
netgear,wax620|\
netgear,wax630|\
xiaomi,ax3600|\
xiaomi,ax9000|\
yuncore,ax880|\
- zte,mf269|\
- zyxel,nbg7815)
+ zbtlink,zbt-z800ax|\
+ zte,mf269)
caldata_extract "0:art" 0x1000 0x20000
;;
- prpl,haze)
+ linksys,mx4200v1|\
+ linksys,mx8500)
+ caldata_extract "0:art" 0x1000 0x20000
+ ath11k_remove_regdomain
+ ;;
+ linksys,mx4200v2)
+ caldata_extract "0:art" 0x1000 0x20000
+ label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
+ ath11k_patch_mac $(macaddr_add $label_mac 2) 0
+ ath11k_patch_mac $(macaddr_add $label_mac 1) 1
+ ath11k_patch_mac $(macaddr_add $label_mac 3) 2
+ ath11k_remove_regdomain
+ ath11k_set_macflag
+ ;;
+ netgear,rax120v2)
+ caldata_extract "0:art" 0x1000 0x20000
+ ath11k_patch_mac $(mtd_get_mac_binary boarddata1 0xc) 0
+ ath11k_patch_mac $(mtd_get_mac_binary boarddata1 0x0) 1
+ ath11k_patch_mac $(mtd_get_mac_binary boarddata1 0x6) 2
+ ath11k_set_macflag
+ ;;
+ prpl,haze|\
+ spectrum,sax1v1k)
caldata_extract_mmc "0:ART" 0x1000 0x20000
;;
+ zyxel,nbg7815)
+ caldata_extract "0:art" 0x1000 0x20000
+ label_mac=$(get_mac_label)
+ ath11k_patch_mac $(macaddr_add $label_mac 3) 0
+ ath11k_patch_mac $(macaddr_add $label_mac 2) 1
+ ath11k_patch_mac $(macaddr_add $label_mac 4) 2
+ ath11k_set_macflag
+ ;;
esac
;;
"ath11k/QCN9074/hw1.0/cal-pci-0000:01:00.0.bin"|\
"ath11k/QCN9074/hw1.0/cal-pci-0001:01:00.0.bin")
case "$board" in
+ linksys,mx8500)
+ caldata_extract "0:art" 0x26800 0x20000
+ ath11k_remove_regdomain
+ ;;
prpl,haze)
caldata_extract_mmc "0:ART" 0x26800 0x20000
;;
[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress
;;
- linksys,mx4200v1|\
- linksys,mx4200v2)
- label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
- [ "$PHYNBR" = "0" ] && macaddr_add $label_mac 2 > /sys${DEVPATH}/macaddress
- [ "$PHYNBR" = "1" ] && macaddr_add $label_mac 1 > /sys${DEVPATH}/macaddress
- [ "$PHYNBR" = "2" ] && macaddr_add $label_mac 3 > /sys${DEVPATH}/macaddress
+ zbtlink,zbt-z800ax)
+ [ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) -1 > /sys${DEVPATH}/macaddress
+ [ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) -2 > /sys${DEVPATH}/macaddress
;;
esac
;;
linksys,mx4200v1|\
linksys,mx4200v2|\
- linksys,mx5300)
+ linksys,mx5300|\
+ linksys,mx8500)
mtd resetbc s_env || true
;;
esac
#!/bin/sh /etc/rc.common
+######################################################################
+# vim: set ft=bash
+# shellcheck disable=2155,3019,3043,3057,3060
+######################################################################
START=93
+PROG=smp_affinity
+
+log_msg() {
+
+ local irq_name="$1" affinity="$2" irq="$3"
+
+ msg="$(printf "Pinning IRQ($irq) %-24s to CPU ${affinity}\n" "$irq_name")"
+
+ logger -t "$PROG" "$msg"
+}
+
+######################################################################
+### Takes a comma, space separated, or range list of CPU numbers and
+## returns a bitmask of CPUs.
+## cpus_to_bitmask "0,1,2,3" -> f
+## cpus_to_bitmask "0 1 2 3" -> f
+## cpus_to_bitmask "0-3" -> f
+## cpus_to_bitmask "3" -> 8
+#######################################################################
+
+cpus_to_bitmask() {
+
+ local bitmask=0
+ # shellcheck disable=2048
+ for range in ${*//,/ }; do
+ start="${range%-*}"
+ end="${range#*-}"
+ if [ -z "$end" ]; then
+ bitmask="$((bitmask | 1 << start))"
+ else
+ bitmask="$((bitmask | (2 ** (end - start + 1) - 1) << start))"
+ fi
+ done
+ printf '%x' $bitmask
+}
+
+######################################################################
+### Takes a bitmask of CPUs and returns a space separated list of
+## CPU numbers.
+## bitmask_to_cpus f -> 0 1 2 3
+######################################################################
+
+bitmask_to_cpus() {
+
+ [ "${1:0:2}" != "0x" ] && set -- "0x$1"
+ local bitmask="$(printf '%d' "$1")"
+
+ local cpus=""
+ for i in $(seq 0 63); do
+ if [ $((bitmask & 1)) -ne 0 ]; then
+ cpus="$cpus $i"
+ fi
+ bitmask=$((bitmask >> 1))
+ done
+ echo "${cpus# }"
+}
+
+######################################################################
+### Sets the affinity of the IRQs with the given name to the given CPU.
+## 1st argument: IRQ name ("reo2host-destination-ring1") (req)
+## 2nd argument: CPU number (req)
+######################################################################
+
+set_affinity() {
+
+ local irq_name="$1" affinity="$2" bitmask irq
+ awk -v irq_name="$1" '$0 ~ irq_name { print substr($1, 1, length($1)-1); exit }' /proc/interrupts \
+ | while read -r irq; do
+ $enable_log && {
+ log_msg "$irq_name" "$affinity" "$irq"
+ }
+ bitmask=$(cpus_to_bitmask "$affinity") && echo "$bitmask" > "/proc/irq/$irq/smp_affinity"
+ done
+}
+
enable_affinity_ipq807x() {
- set_affinity() {
- irq=$(awk "/$1/{ print substr(\$1, 1, length(\$1)-1); exit }" /proc/interrupts)
- [ -n "$irq" ] && echo $2 > /proc/irq/$irq/smp_affinity
- }
-
- # assign 4 rx interrupts to each core
- set_affinity 'reo2host-destination-ring1' 1
- set_affinity 'reo2host-destination-ring2' 2
- set_affinity 'reo2host-destination-ring3' 4
- set_affinity 'reo2host-destination-ring4' 8
-
- # assign 3 tcl completions to last 3 CPUs
- set_affinity 'wbm2host-tx-completions-ring1' 2
- set_affinity 'wbm2host-tx-completions-ring2' 4
- set_affinity 'wbm2host-tx-completions-ring3' 8
-
- # assign 3 ppdu mac interrupts to last 3 cores
- set_affinity 'ppdu-end-interrupts-mac1' 2
- set_affinity 'ppdu-end-interrupts-mac2' 4
- set_affinity 'ppdu-end-interrupts-mac3' 8
-
- # assign lan/wan to core 4
- set_affinity 'edma_txcmpl' 8
- set_affinity 'edma_rxfill' 8
- set_affinity 'edma_rxdesc' 8
- set_affinity 'edma_misc' 8
+
+ # assign 4 rx interrupts to each core
+ set_affinity 'reo2host-destination-ring1' 0
+ set_affinity 'reo2host-destination-ring2' 1
+ set_affinity 'reo2host-destination-ring3' 2
+ set_affinity 'reo2host-destination-ring4' 3
+
+ # assign 3 tcl completions to last 3 CPUs
+ set_affinity 'wbm2host-tx-completions-ring1' 1
+ set_affinity 'wbm2host-tx-completions-ring2' 2
+ set_affinity 'wbm2host-tx-completions-ring3' 3
+
+ # assign 3 ppdu mac interrupts to last 3 cores
+ set_affinity 'ppdu-end-interrupts-mac1' 1
+ set_affinity 'ppdu-end-interrupts-mac2' 2
+ set_affinity 'ppdu-end-interrupts-mac3' 3
+
+ # assign 4 lan/wan to core 4
+ set_affinity 'edma_txcmpl' 3
+ set_affinity 'edma_rxfill' 3
+ set_affinity 'edma_rxdesc' 3
+ set_affinity 'edma_misc' 3
}
boot() {
- enable_affinity_ipq807x
+
+ local enable
+
+ config_load smp_affinity
+
+ config_get_bool enable "general" enable 1
+ config_get_bool enable_log "general" enable_log 1
+
+ [ "$enable" -eq 1 ] && enable=true || enable=false
+ [ "$enable_log" -eq 1 ] && enable_log=true || enable_log=false
+
+ $enable && enable_affinity_ipq807x
}
--- /dev/null
+#!/bin/sh
+
+uci -q get smp_affinity && exit 0
+touch /etc/config/smp_affinity
+
+uci -q batch << EOF
+ set smp_affinity.general=smp_affinity
+ set smp_affinity.general.enable='1'
+ set smp_affinity.general.enable_log='1'
+ commit smp_affinity
+EOF
netgear,rax120v2|\
netgear,wax218|\
netgear,wax620|\
- netgear,wax630)
+ netgear,wax630|\
+ zbtlink,zbt-z800ax)
nand_do_upgrade "$1"
;;
buffalo,wxr-5950ax12)
;;
linksys,mx4200v1|\
linksys,mx4200v2|\
- linksys,mx5300)
+ linksys,mx5300|\
+ linksys,mx8500)
boot_part="$(fw_printenv -n boot_part)"
if [ "$boot_part" -eq "1" ]; then
fw_setenv boot_part 2
nand_do_upgrade "$1"
;;
prpl,haze|\
- qnap,301w)
+ qnap,301w|\
+ spectrum,sax1v1k)
kernelname="0:HLOS"
rootfsname="rootfs"
mmc_do_upgrade "$1"
+++ /dev/null
-From 6463c10bfdbd684ec7ecfd408ea541283215a088 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:06:28 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add A53 PLL node
-
-Add the required node for A53 PLL which will be used to provide the CPU
-clock via APCS for APSS scaling.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220628.339366-9-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -677,6 +677,14 @@
- #mbox-cells = <1>;
- };
-
-+ a53pll: clock@b116000 {
-+ compatible = "qcom,ipq8074-a53pll";
-+ reg = <0x0b116000 0x40>;
-+ #clock-cells = <0>;
-+ clocks = <&xo>;
-+ clock-names = "xo";
-+ };
-+
- timer@b120000 {
- #address-cells = <1>;
- #size-cells = <1>;
+++ /dev/null
-From e593e834fe8ba9bf314d8215ac05d8787f81efda Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:02:42 +0200
-Subject: [PATCH] thermal/drivers/tsens: Add support for combined interrupt
-
-Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for
-signaling both up/low and critical trips.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220245.338396-2-robimarko@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/qcom/tsens-8960.c | 1 +
- drivers/thermal/qcom/tsens-v0_1.c | 1 +
- drivers/thermal/qcom/tsens-v1.c | 1 +
- drivers/thermal/qcom/tsens-v2.c | 1 +
- drivers/thermal/qcom/tsens.c | 38 ++++++++++++++++++++++++++-----
- drivers/thermal/qcom/tsens.h | 2 ++
- 6 files changed, 38 insertions(+), 6 deletions(-)
-
---- a/drivers/thermal/qcom/tsens-8960.c
-+++ b/drivers/thermal/qcom/tsens-8960.c
-@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 =
- static struct tsens_features tsens_8960_feat = {
- .ver_major = VER_0,
- .crit_int = 0,
-+ .combo_int = 0,
- .adc = 1,
- .srot_split = 0,
- .max_sensors = 11,
---- a/drivers/thermal/qcom/tsens-v0_1.c
-+++ b/drivers/thermal/qcom/tsens-v0_1.c
-@@ -549,6 +549,7 @@ static int __init init_8939(struct tsens
- static struct tsens_features tsens_v0_1_feat = {
- .ver_major = VER_0_1,
- .crit_int = 0,
-+ .combo_int = 0,
- .adc = 1,
- .srot_split = 1,
- .max_sensors = 11,
---- a/drivers/thermal/qcom/tsens-v1.c
-+++ b/drivers/thermal/qcom/tsens-v1.c
-@@ -273,6 +273,7 @@ static int calibrate_8976(struct tsens_p
- static struct tsens_features tsens_v1_feat = {
- .ver_major = VER_1_X,
- .crit_int = 0,
-+ .combo_int = 0,
- .adc = 1,
- .srot_split = 1,
- .max_sensors = 11,
---- a/drivers/thermal/qcom/tsens-v2.c
-+++ b/drivers/thermal/qcom/tsens-v2.c
-@@ -31,6 +31,7 @@
- static struct tsens_features tsens_v2_feat = {
- .ver_major = VER_2_X,
- .crit_int = 1,
-+ .combo_int = 0,
- .adc = 0,
- .srot_split = 1,
- .max_sensors = 16,
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -532,6 +532,27 @@ static irqreturn_t tsens_irq_thread(int
- return IRQ_HANDLED;
- }
-
-+/**
-+ * tsens_combined_irq_thread() - Threaded interrupt handler for combined interrupts
-+ * @irq: irq number
-+ * @data: tsens controller private data
-+ *
-+ * Handle the combined interrupt as if it were 2 separate interrupts, so call the
-+ * critical handler first and then the up/low one.
-+ *
-+ * Return: IRQ_HANDLED
-+ */
-+static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
-+{
-+ irqreturn_t ret;
-+
-+ ret = tsens_critical_irq_thread(irq, data);
-+ if (ret != IRQ_HANDLED)
-+ return ret;
-+
-+ return tsens_irq_thread(irq, data);
-+}
-+
- static int tsens_set_trips(struct thermal_zone_device *tz, int low, int high)
- {
- struct tsens_sensor *s = tz->devdata;
-@@ -1074,13 +1095,18 @@ static int tsens_register(struct tsens_p
- tsens_mC_to_hw(priv->sensor, 0));
- }
-
-- ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
-- if (ret < 0)
-- return ret;
-+ if (priv->feat->combo_int) {
-+ ret = tsens_register_irq(priv, "combined",
-+ tsens_combined_irq_thread);
-+ } else {
-+ ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
-+ if (ret < 0)
-+ return ret;
-
-- if (priv->feat->crit_int)
-- ret = tsens_register_irq(priv, "critical",
-- tsens_critical_irq_thread);
-+ if (priv->feat->crit_int)
-+ ret = tsens_register_irq(priv, "critical",
-+ tsens_critical_irq_thread);
-+ }
-
- return ret;
- }
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -493,6 +493,7 @@ enum regfield_ids {
- * struct tsens_features - Features supported by the IP
- * @ver_major: Major number of IP version
- * @crit_int: does the IP support critical interrupts?
-+ * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
- * @adc: do the sensors only output adc code (instead of temperature)?
- * @srot_split: does the IP neatly splits the register space into SROT and TM,
- * with SROT only being available to secure boot firmware?
-@@ -502,6 +503,7 @@ enum regfield_ids {
- struct tsens_features {
- unsigned int ver_major;
- unsigned int crit_int:1;
-+ unsigned int combo_int:1;
- unsigned int adc:1;
- unsigned int srot_split:1;
- unsigned int has_watchdog:1;
+++ /dev/null
-From 7805365fee582056b32c69cf35aafbb94b14a8ca Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:02:43 +0200
-Subject: [PATCH] thermal/drivers/tsens: Allow configuring min and max trips
-
-IPQ8074 and IPQ6018 dont support negative trip temperatures and support
-up to 204 degrees C as the max trip temperature.
-
-So, instead of always setting the -40 as min and 120 degrees C as max
-allow it to be configured as part of the features.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220818220245.338396-3-robimarko@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/qcom/tsens-8960.c | 2 ++
- drivers/thermal/qcom/tsens-v0_1.c | 2 ++
- drivers/thermal/qcom/tsens-v1.c | 2 ++
- drivers/thermal/qcom/tsens-v2.c | 2 ++
- drivers/thermal/qcom/tsens.c | 4 ++--
- drivers/thermal/qcom/tsens.h | 4 ++++
- 6 files changed, 14 insertions(+), 2 deletions(-)
-
---- a/drivers/thermal/qcom/tsens-8960.c
-+++ b/drivers/thermal/qcom/tsens-8960.c
-@@ -273,6 +273,8 @@ static struct tsens_features tsens_8960_
- .adc = 1,
- .srot_split = 0,
- .max_sensors = 11,
-+ .trip_min_temp = -40000,
-+ .trip_max_temp = 120000,
- };
-
- struct tsens_plat_data data_8960 = {
---- a/drivers/thermal/qcom/tsens-v0_1.c
-+++ b/drivers/thermal/qcom/tsens-v0_1.c
-@@ -553,6 +553,8 @@ static struct tsens_features tsens_v0_1_
- .adc = 1,
- .srot_split = 1,
- .max_sensors = 11,
-+ .trip_min_temp = -40000,
-+ .trip_max_temp = 120000,
- };
-
- static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
---- a/drivers/thermal/qcom/tsens-v1.c
-+++ b/drivers/thermal/qcom/tsens-v1.c
-@@ -277,6 +277,8 @@ static struct tsens_features tsens_v1_fe
- .adc = 1,
- .srot_split = 1,
- .max_sensors = 11,
-+ .trip_min_temp = -40000,
-+ .trip_max_temp = 120000,
- };
-
- static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
---- a/drivers/thermal/qcom/tsens-v2.c
-+++ b/drivers/thermal/qcom/tsens-v2.c
-@@ -35,6 +35,8 @@ static struct tsens_features tsens_v2_fe
- .adc = 0,
- .srot_split = 1,
- .max_sensors = 16,
-+ .trip_min_temp = -40000,
-+ .trip_max_temp = 120000,
- };
-
- static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -573,8 +573,8 @@ static int tsens_set_trips(struct therma
- dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
- hw_id, __func__, low, high);
-
-- cl_high = clamp_val(high, -40000, 120000);
-- cl_low = clamp_val(low, -40000, 120000);
-+ cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
-+ cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
-
- high_val = tsens_mC_to_hw(s, cl_high);
- low_val = tsens_mC_to_hw(s, cl_low);
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -499,6 +499,8 @@ enum regfield_ids {
- * with SROT only being available to secure boot firmware?
- * @has_watchdog: does this IP support watchdog functionality?
- * @max_sensors: maximum sensors supported by this version of the IP
-+ * @trip_min_temp: minimum trip temperature supported by this version of the IP
-+ * @trip_max_temp: maximum trip temperature supported by this version of the IP
- */
- struct tsens_features {
- unsigned int ver_major;
-@@ -508,6 +510,8 @@ struct tsens_features {
- unsigned int srot_split:1;
- unsigned int has_watchdog:1;
- unsigned int max_sensors;
-+ int trip_min_temp;
-+ int trip_max_temp;
- };
-
- /**
+++ /dev/null
-From 0164d794cbc58488a7321272e95958d10cf103a4 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:02:44 +0200
-Subject: [PATCH] thermal/drivers/tsens: Add IPQ8074 support
-
-Qualcomm IPQ8074 uses tsens v2.3 IP, however unlike other tsens v2 IP
-it only has one IRQ, that is used for up/low as well as critical.
-It also does not support negative trip temperatures.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220818220245.338396-4-robimarko@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
----
- drivers/thermal/qcom/tsens-v2.c | 17 +++++++++++++++++
- drivers/thermal/qcom/tsens.c | 3 +++
- drivers/thermal/qcom/tsens.h | 2 +-
- 3 files changed, 21 insertions(+), 1 deletion(-)
-
---- a/drivers/thermal/qcom/tsens-v2.c
-+++ b/drivers/thermal/qcom/tsens-v2.c
-@@ -39,6 +39,17 @@ static struct tsens_features tsens_v2_fe
- .trip_max_temp = 120000,
- };
-
-+static struct tsens_features ipq8074_feat = {
-+ .ver_major = VER_2_X,
-+ .crit_int = 1,
-+ .combo_int = 1,
-+ .adc = 0,
-+ .srot_split = 1,
-+ .max_sensors = 16,
-+ .trip_min_temp = 0,
-+ .trip_max_temp = 204000,
-+};
-+
- static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
- /* ----- SROT ------ */
- /* VERSION */
-@@ -104,6 +115,12 @@ struct tsens_plat_data data_tsens_v2 = {
- .fields = tsens_v2_regfields,
- };
-
-+struct tsens_plat_data data_ipq8074 = {
-+ .ops = &ops_generic_v2,
-+ .feat = &ipq8074_feat,
-+ .fields = tsens_v2_regfields,
-+};
-+
- /* Kept around for backward compatibility with old msm8996.dtsi */
- struct tsens_plat_data data_8996 = {
- .num_sensors = 13,
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -981,6 +981,9 @@ static const struct of_device_id tsens_t
- .compatible = "qcom,ipq8064-tsens",
- .data = &data_8960,
- }, {
-+ .compatible = "qcom,ipq8074-tsens",
-+ .data = &data_ipq8074,
-+ }, {
- .compatible = "qcom,mdm9607-tsens",
- .data = &data_9607,
- }, {
---- a/drivers/thermal/qcom/tsens.h
-+++ b/drivers/thermal/qcom/tsens.h
-@@ -597,6 +597,6 @@ extern struct tsens_plat_data data_8916,
- extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
-
- /* TSENS v2 targets */
--extern struct tsens_plat_data data_8996, data_tsens_v2;
-+extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
-
- #endif /* __QCOM_TSENS_H__ */
+++ /dev/null
-From c3cc0c2a17f552be2426200e47a9e2c62cf449ce Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:02:45 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add thermal nodes
-
-IPQ8074 has a tsens v2.3.0 peripheral which monitors
-temperatures around the various subsystems on the
-die.
-
-So lets add the tsens and thermal zone nodes, passive
-CPU cooling will come in later patches after CPU frequency
-scaling is supported.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
- 1 file changed, 96 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -276,6 +276,16 @@
- status = "disabled";
- };
-
-+ tsens: thermal-sensor@4a9000 {
-+ compatible = "qcom,ipq8074-tsens";
-+ reg = <0x4a9000 0x1000>, /* TM */
-+ <0x4a8000 0x1000>; /* SROT */
-+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "combined";
-+ #qcom,sensors = <16>;
-+ #thermal-sensor-cells = <1>;
-+ };
-+
- cryptobam: dma-controller@704000 {
- compatible = "qcom,bam-v1.7.0";
- reg = <0x00704000 0x20000>;
-@@ -876,4 +886,90 @@
- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-+
-+ thermal-zones {
-+ nss-top-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 4>;
-+ };
-+
-+ nss0-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 5>;
-+ };
-+
-+ nss1-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 6>;
-+ };
-+
-+ wcss-phya0-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 7>;
-+ };
-+
-+ wcss-phya1-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 8>;
-+ };
-+
-+ cpu0_thermal: cpu0-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 9>;
-+ };
-+
-+ cpu1_thermal: cpu1-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 10>;
-+ };
-+
-+ cpu2_thermal: cpu2-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 11>;
-+ };
-+
-+ cpu3_thermal: cpu3-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 12>;
-+ };
-+
-+ cluster_thermal: cluster-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 13>;
-+ };
-+
-+ wcss-phyb0-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 14>;
-+ };
-+
-+ wcss-phyb1-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+
-+ thermal-sensors = <&tsens 15>;
-+ };
-+ };
- };
+++ /dev/null
-From 0df592a0a1a3fff9133977192677aa915afc174f Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:08:49 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add clocks to APCS
-
-APCS now has support for providing the APSS clocks as the child device
-for IPQ8074.
-
-So, add the A53 PLL and XO clocks in order to use APCS as the CPU
-clocksource for APSS scaling.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -682,6 +682,8 @@
- apcs_glb: mailbox@b111000 {
- compatible = "qcom,ipq8074-apcs-apps-global";
- reg = <0x0b111000 0x1000>;
-+ clocks = <&a53pll>, <&xo>;
-+ clock-names = "pll", "xo";
-
- #clock-cells = <1>;
- #mbox-cells = <1>;
+++ /dev/null
-From e6c5115d6845f25eda7e162dcd783a2044215867 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 30 Oct 2022 18:57:01 +0100
-Subject: [PATCH] clk: qcom: ipq8074: convert to parent data
-
-Convert the IPQ8074 GCC driver to use parent data instead of global
-name matching.
-
-Utilize ARRAY_SIZE for num_parents instead of hardcoding the value.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221030175703.1103224-1-robimarko@gmail.com
----
- drivers/clk/qcom/gcc-ipq8074.c | 1781 +++++++++++++++-----------------
- 1 file changed, 813 insertions(+), 968 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -49,349 +49,6 @@ enum {
- P_UNIPHY2_TX,
- };
-
--static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const struct parent_map gcc_xo_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
--};
--
--static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll2",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL2, 2 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const char * const gcc_xo_gpll0_sleep_clk[] = {
-- "xo",
-- "gpll0",
-- "sleep_clk",
--};
--
--static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 2 },
-- { P_SLEEP_CLK, 6 },
--};
--
--static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll6",
-- "gpll0",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL6, 1 },
-- { P_GPLL0, 3 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
-- "xo",
-- "gpll0_out_main_div2",
-- "gpll0",
--};
--
--static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0_DIV2, 2 },
-- { P_GPLL0, 1 },
--};
--
--static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
-- "usb3phy_0_cc_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
-- { P_USB3PHY_0_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
-- "usb3phy_1_cc_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
-- { P_USB3PHY_1_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
-- "pcie20_phy0_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
-- { P_PCIE20_PHY0_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
-- "pcie20_phy1_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
-- { P_PCIE20_PHY1_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll6",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL6, 2 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll6",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL6, 2 },
-- { P_GPLL0_DIV2, 3 },
--};
--
--static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
-- "xo",
-- "bias_pll_nss_noc_clk",
-- "gpll0",
-- "gpll2",
--};
--
--static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
-- { P_XO, 0 },
-- { P_BIAS_PLL_NSS_NOC, 1 },
-- { P_GPLL0, 2 },
-- { P_GPLL2, 3 },
--};
--
--static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
-- "xo",
-- "nss_crypto_pll",
-- "gpll0",
--};
--
--static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_NSS_CRYPTO_PLL, 1 },
-- { P_GPLL0, 2 },
--};
--
--static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
-- "xo",
-- "ubi32_pll",
-- "gpll0",
-- "gpll2",
-- "gpll4",
-- "gpll6",
--};
--
--static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
-- { P_XO, 0 },
-- { P_UBI32_PLL, 1 },
-- { P_GPLL0, 2 },
-- { P_GPLL2, 3 },
-- { P_GPLL4, 4 },
-- { P_GPLL6, 5 },
--};
--
--static const char * const gcc_xo_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0_DIV2, 1 },
--};
--
--static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
-- "xo",
-- "bias_pll_cc_clk",
-- "gpll0",
-- "gpll4",
-- "nss_crypto_pll",
-- "ubi32_pll",
--};
--
--static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
-- { P_XO, 0 },
-- { P_BIAS_PLL, 1 },
-- { P_GPLL0, 2 },
-- { P_GPLL4, 3 },
-- { P_NSS_CRYPTO_PLL, 4 },
-- { P_UBI32_PLL, 5 },
--};
--
--static const char * const gcc_xo_gpll0_gpll4[] = {
-- "xo",
-- "gpll0",
-- "gpll4",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL4, 2 },
--};
--
--static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_rx_clk",
-- "uniphy0_gcc_tx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_RX, 1 },
-- { P_UNIPHY0_TX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_tx_clk",
-- "uniphy0_gcc_rx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_TX, 1 },
-- { P_UNIPHY0_RX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_rx_clk",
-- "uniphy0_gcc_tx_clk",
-- "uniphy1_gcc_rx_clk",
-- "uniphy1_gcc_tx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map
--gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_RX, 1 },
-- { P_UNIPHY0_TX, 2 },
-- { P_UNIPHY1_RX, 3 },
-- { P_UNIPHY1_TX, 4 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_tx_clk",
-- "uniphy0_gcc_rx_clk",
-- "uniphy1_gcc_tx_clk",
-- "uniphy1_gcc_rx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map
--gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_TX, 1 },
-- { P_UNIPHY0_RX, 2 },
-- { P_UNIPHY1_TX, 3 },
-- { P_UNIPHY1_RX, 4 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
-- "xo",
-- "uniphy2_gcc_rx_clk",
-- "uniphy2_gcc_tx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY2_RX, 1 },
-- { P_UNIPHY2_TX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
-- "xo",
-- "uniphy2_gcc_tx_clk",
-- "uniphy2_gcc_rx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY2_TX, 1 },
-- { P_UNIPHY2_RX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
-- "xo",
-- "gpll0",
-- "gpll6",
-- "gpll0_out_main_div2",
-- "sleep_clk",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL6, 2 },
-- { P_GPLL0_DIV2, 4 },
-- { P_SLEEP_CLK, 6 },
--};
--
- static struct clk_alpha_pll gpll0_main = {
- .offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
-@@ -400,8 +57,9 @@ static struct clk_alpha_pll gpll0_main =
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -414,9 +72,8 @@ static struct clk_fixed_factor gpll0_out
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_out_main_div2",
-- .parent_names = (const char *[]){
-- "gpll0_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll0_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-@@ -428,9 +85,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll0",
-- .parent_names = (const char *[]){
-- "gpll0_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll0_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- },
-@@ -444,8 +100,9 @@ static struct clk_alpha_pll gpll2_main =
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gpll2_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -460,9 +117,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll2",
-- .parent_names = (const char *[]){
-- "gpll2_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll2_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- },
-@@ -476,8 +132,9 @@ static struct clk_alpha_pll gpll4_main =
- .enable_mask = BIT(5),
- .hw.init = &(struct clk_init_data){
- .name = "gpll4_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -492,9 +149,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll4",
-- .parent_names = (const char *[]){
-- "gpll4_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll4_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- },
-@@ -509,8 +165,9 @@ static struct clk_alpha_pll gpll6_main =
- .enable_mask = BIT(7),
- .hw.init = &(struct clk_init_data){
- .name = "gpll6_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -525,9 +182,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 2,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll6",
-- .parent_names = (const char *[]){
-- "gpll6_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll6_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- },
-@@ -538,9 +194,8 @@ static struct clk_fixed_factor gpll6_out
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "gpll6_out_main_div2",
-- .parent_names = (const char *[]){
-- "gpll6_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll6_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-@@ -555,8 +210,9 @@ static struct clk_alpha_pll ubi32_pll_ma
- .enable_mask = BIT(6),
- .hw.init = &(struct clk_init_data){
- .name = "ubi32_pll_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_huayra_ops,
-@@ -570,9 +226,8 @@ static struct clk_alpha_pll_postdiv ubi3
- .width = 2,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ubi32_pll",
-- .parent_names = (const char *[]){
-- "ubi32_pll_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &ubi32_pll_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -587,8 +242,9 @@ static struct clk_alpha_pll nss_crypto_p
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "nss_crypto_pll_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -602,9 +258,8 @@ static struct clk_alpha_pll_postdiv nss_
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_crypto_pll",
-- .parent_names = (const char *[]){
-- "nss_crypto_pll_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_crypto_pll_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- },
-@@ -617,6 +272,18 @@ static const struct freq_tbl ftbl_pcnoc_
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw},
-+ { .hw = &gpll0_out_main_div2.hw},
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
- .cmd_rcgr = 0x27000,
- .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
-@@ -624,8 +291,8 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcnoc_bfdcd_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- .flags = CLK_IS_CRITICAL,
- },
-@@ -636,9 +303,8 @@ static struct clk_fixed_factor pcnoc_clk
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "pcnoc_clk_src",
-- .parent_names = (const char *[]){
-- "pcnoc_bfdcd_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_bfdcd_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -652,8 +318,9 @@ static struct clk_branch gcc_sleep_clk_s
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sleep_clk_src",
-- .parent_names = (const char *[]){
-- "sleep_clk"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "sleep_clk",
-+ .name = "sleep_clk",
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
-@@ -676,8 +343,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -702,8 +369,8 @@ static struct clk_rcg2 blsp1_qup1_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -715,8 +382,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -729,8 +396,8 @@ static struct clk_rcg2 blsp1_qup2_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -742,8 +409,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -756,8 +423,8 @@ static struct clk_rcg2 blsp1_qup3_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -769,8 +436,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -783,8 +450,8 @@ static struct clk_rcg2 blsp1_qup4_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -796,8 +463,8 @@ static struct clk_rcg2 blsp1_qup5_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -810,8 +477,8 @@ static struct clk_rcg2 blsp1_qup5_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -823,8 +490,8 @@ static struct clk_rcg2 blsp1_qup6_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -837,8 +504,8 @@ static struct clk_rcg2 blsp1_qup6_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -871,8 +538,8 @@ static struct clk_rcg2 blsp1_uart1_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -885,8 +552,8 @@ static struct clk_rcg2 blsp1_uart2_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -899,8 +566,8 @@ static struct clk_rcg2 blsp1_uart3_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -913,8 +580,8 @@ static struct clk_rcg2 blsp1_uart4_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -927,8 +594,8 @@ static struct clk_rcg2 blsp1_uart5_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart5_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -941,8 +608,8 @@ static struct clk_rcg2 blsp1_uart6_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart6_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -952,6 +619,11 @@ static const struct clk_parent_data gcc_
- { .hw = &gpll0.clkr.hw },
- };
-
-+static const struct parent_map gcc_xo_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+};
-+
- static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
-@@ -966,7 +638,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie0_axi_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -975,6 +647,18 @@ static const struct freq_tbl ftbl_pcie_a
- F(19200000, P_XO, 1, 0, 0),
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 2 },
-+ { P_SLEEP_CLK, 6 },
-+};
-+
- static struct clk_rcg2 pcie0_aux_clk_src = {
- .cmd_rcgr = 0x75024,
- .freq_tbl = ftbl_pcie_aux_clk_src,
-@@ -983,12 +667,22 @@ static struct clk_rcg2 pcie0_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie0_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
-+ { .name = "pcie20_phy0_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
-+ { P_PCIE20_PHY0_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux pcie0_pipe_clk_src = {
- .reg = 0x7501c,
- .shift = 8,
-@@ -997,8 +691,8 @@ static struct clk_regmap_mux pcie0_pipe_
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "pcie0_pipe_clk_src",
-- .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1013,7 +707,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie1_axi_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1026,12 +720,22 @@ static struct clk_rcg2 pcie1_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie1_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
-+ { .name = "pcie20_phy1_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
-+ { P_PCIE20_PHY1_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux pcie1_pipe_clk_src = {
- .reg = 0x7601c,
- .shift = 8,
-@@ -1040,8 +744,8 @@ static struct clk_regmap_mux pcie1_pipe_
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "pcie1_pipe_clk_src",
-- .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1060,6 +764,20 @@ static const struct freq_tbl ftbl_sdcc_a
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll2.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL2, 2 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 sdcc1_apps_clk_src = {
- .cmd_rcgr = 0x42004,
- .freq_tbl = ftbl_sdcc_apps_clk_src,
-@@ -1068,8 +786,8 @@ static struct clk_rcg2 sdcc1_apps_clk_sr
- .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -1080,6 +798,20 @@ static const struct freq_tbl ftbl_sdcc_i
- F(308570000, P_GPLL6, 3.5, 0, 0),
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL6, 2 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 sdcc1_ice_core_clk_src = {
- .cmd_rcgr = 0x5d000,
- .freq_tbl = ftbl_sdcc_ice_core_clk_src,
-@@ -1088,8 +820,8 @@ static struct clk_rcg2 sdcc1_ice_core_cl
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_ice_core_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1102,8 +834,8 @@ static struct clk_rcg2 sdcc2_apps_clk_sr
- .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -1115,6 +847,18 @@ static const struct freq_tbl ftbl_usb_ma
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0_out_main_div2.hw },
-+ { .hw = &gpll0.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0_DIV2, 2 },
-+ { P_GPLL0, 1 },
-+};
-+
- static struct clk_rcg2 usb0_master_clk_src = {
- .cmd_rcgr = 0x3e00c,
- .freq_tbl = ftbl_usb_master_clk_src,
-@@ -1123,8 +867,8 @@ static struct clk_rcg2 usb0_master_clk_s
- .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb0_master_clk_src",
-- .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1142,8 +886,8 @@ static struct clk_rcg2 usb0_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb0_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1155,6 +899,20 @@ static const struct freq_tbl ftbl_usb_mo
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL6, 1 },
-+ { P_GPLL0, 3 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 usb0_mock_utmi_clk_src = {
- .cmd_rcgr = 0x3e020,
- .freq_tbl = ftbl_usb_mock_utmi_clk_src,
-@@ -1163,12 +921,22 @@ static struct clk_rcg2 usb0_mock_utmi_cl
- .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb0_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
-+ { .name = "usb3phy_0_cc_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
-+ { P_USB3PHY_0_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux usb0_pipe_clk_src = {
- .reg = 0x3e048,
- .shift = 8,
-@@ -1177,8 +945,8 @@ static struct clk_regmap_mux usb0_pipe_c
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "usb0_pipe_clk_src",
-- .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1193,8 +961,8 @@ static struct clk_rcg2 usb1_master_clk_s
- .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb1_master_clk_src",
-- .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1207,8 +975,8 @@ static struct clk_rcg2 usb1_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb1_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1221,12 +989,22 @@ static struct clk_rcg2 usb1_mock_utmi_cl
- .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb1_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
-+ { .name = "usb3phy_1_cc_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
-+ { P_USB3PHY_1_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux usb1_pipe_clk_src = {
- .reg = 0x3f048,
- .shift = 8,
-@@ -1235,8 +1013,8 @@ static struct clk_regmap_mux usb1_pipe_c
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "usb1_pipe_clk_src",
-- .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_usb3phy_1_cc_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1250,8 +1028,9 @@ static struct clk_branch gcc_xo_clk_src
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_xo_clk_src",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-@@ -1265,9 +1044,8 @@ static struct clk_fixed_factor gcc_xo_di
- .div = 4,
- .hw.init = &(struct clk_init_data){
- .name = "gcc_xo_div4_clk_src",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1285,6 +1063,20 @@ static const struct freq_tbl ftbl_system
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL6, 2 },
-+ { P_GPLL0_DIV2, 3 },
-+};
-+
- static struct clk_rcg2 system_noc_bfdcd_clk_src = {
- .cmd_rcgr = 0x26004,
- .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
-@@ -1292,8 +1084,8 @@ static struct clk_rcg2 system_noc_bfdcd_
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_bfdcd_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- .flags = CLK_IS_CRITICAL,
- },
-@@ -1304,9 +1096,8 @@ static struct clk_fixed_factor system_no
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
-- .parent_names = (const char *[]){
-- "system_noc_bfdcd_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &system_noc_bfdcd_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1327,7 +1118,7 @@ static struct clk_rcg2 nss_ce_clk_src =
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ce_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1338,6 +1129,20 @@ static const struct freq_tbl ftbl_nss_no
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "bias_pll_nss_noc_clk" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll2.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
-+ { P_XO, 0 },
-+ { P_BIAS_PLL_NSS_NOC, 1 },
-+ { P_GPLL0, 2 },
-+ { P_GPLL2, 3 },
-+};
-+
- static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
- .cmd_rcgr = 0x68088,
- .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
-@@ -1345,8 +1150,8 @@ static struct clk_rcg2 nss_noc_bfdcd_clk
- .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_noc_bfdcd_clk_src",
-- .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1356,9 +1161,8 @@ static struct clk_fixed_factor nss_noc_c
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "nss_noc_clk_src",
-- .parent_names = (const char *[]){
-- "nss_noc_bfdcd_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_bfdcd_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1371,6 +1175,18 @@ static const struct freq_tbl ftbl_nss_cr
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &nss_crypto_pll.clkr.hw },
-+ { .hw = &gpll0.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_NSS_CRYPTO_PLL, 1 },
-+ { P_GPLL0, 2 },
-+};
-+
- static struct clk_rcg2 nss_crypto_clk_src = {
- .cmd_rcgr = 0x68144,
- .freq_tbl = ftbl_nss_crypto_clk_src,
-@@ -1379,8 +1195,8 @@ static struct clk_rcg2 nss_crypto_clk_sr
- .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_crypto_clk_src",
-- .parent_names = gcc_xo_nss_crypto_pll_gpll0,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_nss_crypto_pll_gpll0,
-+ .num_parents = ARRAY_SIZE(gcc_xo_nss_crypto_pll_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1394,6 +1210,24 @@ static const struct freq_tbl ftbl_nss_ub
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll2.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
-+ { P_XO, 0 },
-+ { P_UBI32_PLL, 1 },
-+ { P_GPLL0, 2 },
-+ { P_GPLL2, 3 },
-+ { P_GPLL4, 4 },
-+ { P_GPLL6, 5 },
-+};
-+
- static struct clk_rcg2 nss_ubi0_clk_src = {
- .cmd_rcgr = 0x68104,
- .freq_tbl = ftbl_nss_ubi_clk_src,
-@@ -1401,8 +1235,8 @@ static struct clk_rcg2 nss_ubi0_clk_src
- .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ubi0_clk_src",
-- .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-- .num_parents = 6,
-+ .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-+ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
- .ops = &clk_rcg2_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1415,9 +1249,8 @@ static struct clk_regmap_div nss_ubi0_di
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_ubi0_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_ubi0_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi0_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1432,8 +1265,8 @@ static struct clk_rcg2 nss_ubi1_clk_src
- .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ubi1_clk_src",
-- .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-- .num_parents = 6,
-+ .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-+ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
- .ops = &clk_rcg2_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1446,9 +1279,8 @@ static struct clk_regmap_div nss_ubi1_di
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_ubi1_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_ubi1_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi1_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1462,6 +1294,16 @@ static const struct freq_tbl ftbl_ubi_mp
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0_DIV2, 1 },
-+};
-+
- static struct clk_rcg2 ubi_mpt_clk_src = {
- .cmd_rcgr = 0x68090,
- .freq_tbl = ftbl_ubi_mpt_clk_src,
-@@ -1469,8 +1311,8 @@ static struct clk_rcg2 ubi_mpt_clk_src =
- .parent_map = gcc_xo_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ubi_mpt_clk_src",
-- .parent_names = gcc_xo_gpll0_out_main_div2,
-- .num_parents = 2,
-+ .parent_data = gcc_xo_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1481,6 +1323,18 @@ static const struct freq_tbl ftbl_nss_im
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL4, 2 },
-+};
-+
- static struct clk_rcg2 nss_imem_clk_src = {
- .cmd_rcgr = 0x68158,
- .freq_tbl = ftbl_nss_imem_clk_src,
-@@ -1488,8 +1342,8 @@ static struct clk_rcg2 nss_imem_clk_src
- .parent_map = gcc_xo_gpll0_gpll4_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_imem_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1500,6 +1354,24 @@ static const struct freq_tbl ftbl_nss_pp
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "bias_pll_cc_clk" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+ { .hw = &nss_crypto_pll.clkr.hw },
-+ { .hw = &ubi32_pll.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
-+ { P_XO, 0 },
-+ { P_BIAS_PLL, 1 },
-+ { P_GPLL0, 2 },
-+ { P_GPLL4, 3 },
-+ { P_NSS_CRYPTO_PLL, 4 },
-+ { P_UBI32_PLL, 5 },
-+};
-+
- static struct clk_rcg2 nss_ppe_clk_src = {
- .cmd_rcgr = 0x68080,
- .freq_tbl = ftbl_nss_ppe_clk_src,
-@@ -1507,8 +1379,8 @@ static struct clk_rcg2 nss_ppe_clk_src =
- .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ppe_clk_src",
-- .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
-- .num_parents = 6,
-+ .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
-+ .num_parents = ARRAY_SIZE(gcc_xo_bias_gpll0_gpll4_nss_ubi32),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1518,9 +1390,8 @@ static struct clk_fixed_factor nss_ppe_c
- .div = 4,
- .hw.init = &(struct clk_init_data){
- .name = "nss_ppe_cdiv_clk_src",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1534,6 +1405,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_RX, 1 },
-+ { P_UNIPHY0_TX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port1_rx_clk_src = {
- .cmd_rcgr = 0x68020,
- .freq_tbl = ftbl_nss_port1_rx_clk_src,
-@@ -1541,8 +1428,8 @@ static struct clk_rcg2 nss_port1_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port1_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1554,9 +1441,8 @@ static struct clk_regmap_div nss_port1_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port1_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port1_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1571,6 +1457,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_TX, 1 },
-+ { P_UNIPHY0_RX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port1_tx_clk_src = {
- .cmd_rcgr = 0x68028,
- .freq_tbl = ftbl_nss_port1_tx_clk_src,
-@@ -1578,8 +1480,8 @@ static struct clk_rcg2 nss_port1_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port1_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1591,9 +1493,8 @@ static struct clk_regmap_div nss_port1_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port1_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port1_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1608,8 +1509,8 @@ static struct clk_rcg2 nss_port2_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port2_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1621,9 +1522,8 @@ static struct clk_regmap_div nss_port2_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port2_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port2_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1638,8 +1538,8 @@ static struct clk_rcg2 nss_port2_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port2_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1651,9 +1551,8 @@ static struct clk_regmap_div nss_port2_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port2_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port2_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1668,8 +1567,8 @@ static struct clk_rcg2 nss_port3_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port3_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1681,9 +1580,8 @@ static struct clk_regmap_div nss_port3_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port3_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port3_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1698,8 +1596,8 @@ static struct clk_rcg2 nss_port3_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port3_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1711,9 +1609,8 @@ static struct clk_regmap_div nss_port3_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port3_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port3_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1728,8 +1625,8 @@ static struct clk_rcg2 nss_port4_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port4_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1741,9 +1638,8 @@ static struct clk_regmap_div nss_port4_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port4_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port4_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1758,8 +1654,8 @@ static struct clk_rcg2 nss_port4_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port4_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1771,9 +1667,8 @@ static struct clk_regmap_div nss_port4_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port4_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port4_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1793,6 +1688,27 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .name = "uniphy1_gcc_rx_clk" },
-+ { .name = "uniphy1_gcc_tx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map
-+gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_RX, 1 },
-+ { P_UNIPHY0_TX, 2 },
-+ { P_UNIPHY1_RX, 3 },
-+ { P_UNIPHY1_TX, 4 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port5_rx_clk_src = {
- .cmd_rcgr = 0x68060,
- .freq_tbl = ftbl_nss_port5_rx_clk_src,
-@@ -1800,8 +1716,8 @@ static struct clk_rcg2 nss_port5_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port5_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
-- .num_parents = 7,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1813,9 +1729,8 @@ static struct clk_regmap_div nss_port5_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port5_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1835,6 +1750,27 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .name = "uniphy1_gcc_tx_clk" },
-+ { .name = "uniphy1_gcc_rx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map
-+gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_TX, 1 },
-+ { P_UNIPHY0_RX, 2 },
-+ { P_UNIPHY1_TX, 3 },
-+ { P_UNIPHY1_RX, 4 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port5_tx_clk_src = {
- .cmd_rcgr = 0x68068,
- .freq_tbl = ftbl_nss_port5_tx_clk_src,
-@@ -1842,8 +1778,8 @@ static struct clk_rcg2 nss_port5_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port5_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
-- .num_parents = 7,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1855,9 +1791,8 @@ static struct clk_regmap_div nss_port5_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port5_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1877,6 +1812,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy2_gcc_rx_clk" },
-+ { .name = "uniphy2_gcc_tx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY2_RX, 1 },
-+ { P_UNIPHY2_TX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port6_rx_clk_src = {
- .cmd_rcgr = 0x68070,
- .freq_tbl = ftbl_nss_port6_rx_clk_src,
-@@ -1884,8 +1835,8 @@ static struct clk_rcg2 nss_port6_rx_clk_
- .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port6_rx_clk_src",
-- .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1897,9 +1848,8 @@ static struct clk_regmap_div nss_port6_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port6_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port6_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1919,6 +1869,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy2_gcc_tx_clk" },
-+ { .name = "uniphy2_gcc_rx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY2_TX, 1 },
-+ { P_UNIPHY2_RX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port6_tx_clk_src = {
- .cmd_rcgr = 0x68078,
- .freq_tbl = ftbl_nss_port6_tx_clk_src,
-@@ -1926,8 +1892,8 @@ static struct clk_rcg2 nss_port6_tx_clk_
- .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port6_tx_clk_src",
-- .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1939,9 +1905,8 @@ static struct clk_regmap_div nss_port6_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port6_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port6_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1964,8 +1929,8 @@ static struct clk_rcg2 crypto_clk_src =
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "crypto_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1975,6 +1940,22 @@ static struct freq_tbl ftbl_gp_clk_src[]
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL6, 2 },
-+ { P_GPLL0_DIV2, 4 },
-+ { P_SLEEP_CLK, 6 },
-+};
-+
- static struct clk_rcg2 gp1_clk_src = {
- .cmd_rcgr = 0x08004,
- .freq_tbl = ftbl_gp_clk_src,
-@@ -1983,8 +1964,8 @@ static struct clk_rcg2 gp1_clk_src = {
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp1_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1997,8 +1978,8 @@ static struct clk_rcg2 gp2_clk_src = {
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp2_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -2011,8 +1992,8 @@ static struct clk_rcg2 gp3_clk_src = {
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp3_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -2024,9 +2005,8 @@ static struct clk_branch gcc_blsp1_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2041,9 +2021,8 @@ static struct clk_branch gcc_blsp1_qup1_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup1_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2058,9 +2037,8 @@ static struct clk_branch gcc_blsp1_qup1_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup1_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2075,9 +2053,8 @@ static struct clk_branch gcc_blsp1_qup2_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup2_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2092,9 +2069,8 @@ static struct clk_branch gcc_blsp1_qup2_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup2_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2109,9 +2085,8 @@ static struct clk_branch gcc_blsp1_qup3_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup3_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2126,9 +2101,8 @@ static struct clk_branch gcc_blsp1_qup3_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup3_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2143,9 +2117,8 @@ static struct clk_branch gcc_blsp1_qup4_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup4_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2160,9 +2133,8 @@ static struct clk_branch gcc_blsp1_qup4_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup4_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2177,9 +2149,8 @@ static struct clk_branch gcc_blsp1_qup5_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup5_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2194,9 +2165,8 @@ static struct clk_branch gcc_blsp1_qup5_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup5_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2211,9 +2181,8 @@ static struct clk_branch gcc_blsp1_qup6_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup6_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2228,9 +2197,8 @@ static struct clk_branch gcc_blsp1_qup6_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup6_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2245,9 +2213,8 @@ static struct clk_branch gcc_blsp1_uart1
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart1_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart1_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart1_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2262,9 +2229,8 @@ static struct clk_branch gcc_blsp1_uart2
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart2_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart2_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart2_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2279,9 +2245,8 @@ static struct clk_branch gcc_blsp1_uart3
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart3_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart3_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart3_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2296,9 +2261,8 @@ static struct clk_branch gcc_blsp1_uart4
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart4_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart4_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart4_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2313,9 +2277,8 @@ static struct clk_branch gcc_blsp1_uart5
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart5_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart5_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart5_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2330,9 +2293,8 @@ static struct clk_branch gcc_blsp1_uart6
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart6_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart6_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart6_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2348,9 +2310,8 @@ static struct clk_branch gcc_prng_ahb_cl
- .enable_mask = BIT(8),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_prng_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2365,9 +2326,8 @@ static struct clk_branch gcc_qpic_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qpic_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2382,9 +2342,8 @@ static struct clk_branch gcc_qpic_clk =
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qpic_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2399,9 +2358,8 @@ static struct clk_branch gcc_pcie0_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2416,9 +2374,8 @@ static struct clk_branch gcc_pcie0_aux_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_aux_clk",
-- .parent_names = (const char *[]){
-- "pcie0_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2433,9 +2390,8 @@ static struct clk_branch gcc_pcie0_axi_m
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_axi_m_clk",
-- .parent_names = (const char *[]){
-- "pcie0_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2450,9 +2406,8 @@ static struct clk_branch gcc_pcie0_axi_s
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_axi_s_clk",
-- .parent_names = (const char *[]){
-- "pcie0_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2468,9 +2423,8 @@ static struct clk_branch gcc_pcie0_pipe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_pipe_clk",
-- .parent_names = (const char *[]){
-- "pcie0_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2485,9 +2439,8 @@ static struct clk_branch gcc_sys_noc_pci
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_pcie0_axi_clk",
-- .parent_names = (const char *[]){
-- "pcie0_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2502,9 +2455,8 @@ static struct clk_branch gcc_pcie1_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2519,9 +2471,8 @@ static struct clk_branch gcc_pcie1_aux_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_aux_clk",
-- .parent_names = (const char *[]){
-- "pcie1_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2536,9 +2487,8 @@ static struct clk_branch gcc_pcie1_axi_m
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_axi_m_clk",
-- .parent_names = (const char *[]){
-- "pcie1_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2553,9 +2503,8 @@ static struct clk_branch gcc_pcie1_axi_s
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_axi_s_clk",
-- .parent_names = (const char *[]){
-- "pcie1_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2571,9 +2520,8 @@ static struct clk_branch gcc_pcie1_pipe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_pipe_clk",
-- .parent_names = (const char *[]){
-- "pcie1_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2588,9 +2536,8 @@ static struct clk_branch gcc_sys_noc_pci
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_pcie1_axi_clk",
-- .parent_names = (const char *[]){
-- "pcie1_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2605,9 +2552,8 @@ static struct clk_branch gcc_usb0_aux_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_aux_clk",
-- .parent_names = (const char *[]){
-- "usb0_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2622,9 +2568,8 @@ static struct clk_branch gcc_sys_noc_usb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_usb0_axi_clk",
-- .parent_names = (const char *[]){
-- "usb0_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2639,9 +2584,8 @@ static struct clk_branch gcc_usb0_master
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_master_clk",
-- .parent_names = (const char *[]){
-- "usb0_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2656,9 +2600,8 @@ static struct clk_branch gcc_usb0_mock_u
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_mock_utmi_clk",
-- .parent_names = (const char *[]){
-- "usb0_mock_utmi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_mock_utmi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2673,9 +2616,8 @@ static struct clk_branch gcc_usb0_phy_cf
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_phy_cfg_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2691,9 +2633,8 @@ static struct clk_branch gcc_usb0_pipe_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_pipe_clk",
-- .parent_names = (const char *[]){
-- "usb0_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2708,9 +2649,8 @@ static struct clk_branch gcc_usb0_sleep_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_sleep_clk",
-- .parent_names = (const char *[]){
-- "gcc_sleep_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_sleep_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2725,9 +2665,8 @@ static struct clk_branch gcc_usb1_aux_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_aux_clk",
-- .parent_names = (const char *[]){
-- "usb1_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2742,9 +2681,8 @@ static struct clk_branch gcc_sys_noc_usb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_usb1_axi_clk",
-- .parent_names = (const char *[]){
-- "usb1_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2759,9 +2697,8 @@ static struct clk_branch gcc_usb1_master
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_master_clk",
-- .parent_names = (const char *[]){
-- "usb1_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2776,9 +2713,8 @@ static struct clk_branch gcc_usb1_mock_u
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_mock_utmi_clk",
-- .parent_names = (const char *[]){
-- "usb1_mock_utmi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_mock_utmi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2793,9 +2729,8 @@ static struct clk_branch gcc_usb1_phy_cf
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_phy_cfg_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2811,9 +2746,8 @@ static struct clk_branch gcc_usb1_pipe_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_pipe_clk",
-- .parent_names = (const char *[]){
-- "usb1_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2828,9 +2762,8 @@ static struct clk_branch gcc_usb1_sleep_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_sleep_clk",
-- .parent_names = (const char *[]){
-- "gcc_sleep_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_sleep_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2845,9 +2778,8 @@ static struct clk_branch gcc_sdcc1_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2862,9 +2794,8 @@ static struct clk_branch gcc_sdcc1_apps_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_apps_clk",
-- .parent_names = (const char *[]){
-- "sdcc1_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &sdcc1_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2879,9 +2810,8 @@ static struct clk_branch gcc_sdcc1_ice_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ice_core_clk",
-- .parent_names = (const char *[]){
-- "sdcc1_ice_core_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &sdcc1_ice_core_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2896,9 +2826,8 @@ static struct clk_branch gcc_sdcc2_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2913,9 +2842,8 @@ static struct clk_branch gcc_sdcc2_apps_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_apps_clk",
-- .parent_names = (const char *[]){
-- "sdcc2_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &sdcc2_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2930,9 +2858,8 @@ static struct clk_branch gcc_mem_noc_nss
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mem_noc_nss_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2947,9 +2874,8 @@ static struct clk_branch gcc_nss_ce_apb_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ce_apb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2964,9 +2890,8 @@ static struct clk_branch gcc_nss_ce_axi_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ce_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2981,9 +2906,8 @@ static struct clk_branch gcc_nss_cfg_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_cfg_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2998,9 +2922,8 @@ static struct clk_branch gcc_nss_crypto_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_crypto_clk",
-- .parent_names = (const char *[]){
-- "nss_crypto_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_crypto_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3015,9 +2938,8 @@ static struct clk_branch gcc_nss_csr_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_csr_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3032,9 +2954,8 @@ static struct clk_branch gcc_nss_edma_cf
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_edma_cfg_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3049,9 +2970,8 @@ static struct clk_branch gcc_nss_edma_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_edma_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3066,9 +2986,8 @@ static struct clk_branch gcc_nss_imem_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_imem_clk",
-- .parent_names = (const char *[]){
-- "nss_imem_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_imem_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3083,9 +3002,8 @@ static struct clk_branch gcc_nss_noc_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_noc_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3100,9 +3018,8 @@ static struct clk_branch gcc_nss_ppe_btq
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_btq_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3117,9 +3034,8 @@ static struct clk_branch gcc_nss_ppe_cfg
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_cfg_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3134,9 +3050,8 @@ static struct clk_branch gcc_nss_ppe_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3151,9 +3066,8 @@ static struct clk_branch gcc_nss_ppe_ipe
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_ipe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3168,9 +3082,8 @@ static struct clk_branch gcc_nss_ptp_ref
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ptp_ref_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_cdiv_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_cdiv_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3186,9 +3099,8 @@ static struct clk_branch gcc_crypto_ppe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_ppe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3203,9 +3115,8 @@ static struct clk_branch gcc_nssnoc_ce_a
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ce_apb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3220,9 +3131,8 @@ static struct clk_branch gcc_nssnoc_ce_a
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ce_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3237,9 +3147,8 @@ static struct clk_branch gcc_nssnoc_cryp
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_crypto_clk",
-- .parent_names = (const char *[]){
-- "nss_crypto_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_crypto_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3254,9 +3163,8 @@ static struct clk_branch gcc_nssnoc_ppe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ppe_cfg_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3271,9 +3179,8 @@ static struct clk_branch gcc_nssnoc_ppe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ppe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3288,9 +3195,8 @@ static struct clk_branch gcc_nssnoc_qosg
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_qosgen_ref_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3305,9 +3211,8 @@ static struct clk_branch gcc_nssnoc_snoc
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_snoc_clk",
-- .parent_names = (const char *[]){
-- "system_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &system_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3322,9 +3227,8 @@ static struct clk_branch gcc_nssnoc_time
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_timeout_ref_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_div4_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_div4_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3339,9 +3243,8 @@ static struct clk_branch gcc_nssnoc_ubi0
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ubi0_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3356,9 +3259,8 @@ static struct clk_branch gcc_nssnoc_ubi1
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ubi1_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3374,9 +3276,8 @@ static struct clk_branch gcc_ubi0_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3392,9 +3293,8 @@ static struct clk_branch gcc_ubi0_axi_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3410,9 +3310,8 @@ static struct clk_branch gcc_ubi0_nc_axi
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_nc_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3428,9 +3327,8 @@ static struct clk_branch gcc_ubi0_core_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_core_clk",
-- .parent_names = (const char *[]){
-- "nss_ubi0_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi0_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3446,9 +3344,8 @@ static struct clk_branch gcc_ubi0_mpt_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_mpt_clk",
-- .parent_names = (const char *[]){
-- "ubi_mpt_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &ubi_mpt_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3464,9 +3361,8 @@ static struct clk_branch gcc_ubi1_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3482,9 +3378,8 @@ static struct clk_branch gcc_ubi1_axi_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3500,9 +3395,8 @@ static struct clk_branch gcc_ubi1_nc_axi
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_nc_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3518,9 +3412,8 @@ static struct clk_branch gcc_ubi1_core_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_core_clk",
-- .parent_names = (const char *[]){
-- "nss_ubi1_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi1_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3536,9 +3429,8 @@ static struct clk_branch gcc_ubi1_mpt_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_mpt_clk",
-- .parent_names = (const char *[]){
-- "ubi_mpt_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &ubi_mpt_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3553,9 +3445,8 @@ static struct clk_branch gcc_cmn_12gpll_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_cmn_12gpll_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3570,9 +3461,8 @@ static struct clk_branch gcc_cmn_12gpll_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_cmn_12gpll_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3587,9 +3477,8 @@ static struct clk_branch gcc_mdio_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdio_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3604,9 +3493,8 @@ static struct clk_branch gcc_uniphy0_ahb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3621,9 +3509,8 @@ static struct clk_branch gcc_uniphy0_sys
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3638,9 +3525,8 @@ static struct clk_branch gcc_uniphy1_ahb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3655,9 +3541,8 @@ static struct clk_branch gcc_uniphy1_sys
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3672,9 +3557,8 @@ static struct clk_branch gcc_uniphy2_ahb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3689,9 +3573,8 @@ static struct clk_branch gcc_uniphy2_sys
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3706,9 +3589,8 @@ static struct clk_branch gcc_nss_port1_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port1_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3723,9 +3605,8 @@ static struct clk_branch gcc_nss_port1_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port1_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3740,9 +3621,8 @@ static struct clk_branch gcc_nss_port2_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port2_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3757,9 +3637,8 @@ static struct clk_branch gcc_nss_port2_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port2_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3774,9 +3653,8 @@ static struct clk_branch gcc_nss_port3_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port3_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3791,9 +3669,8 @@ static struct clk_branch gcc_nss_port3_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port3_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3808,9 +3685,8 @@ static struct clk_branch gcc_nss_port4_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port4_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3825,9 +3701,8 @@ static struct clk_branch gcc_nss_port4_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port4_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3842,9 +3717,8 @@ static struct clk_branch gcc_nss_port5_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port5_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3859,9 +3733,8 @@ static struct clk_branch gcc_nss_port5_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port5_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3876,9 +3749,8 @@ static struct clk_branch gcc_nss_port6_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port6_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3893,9 +3765,8 @@ static struct clk_branch gcc_nss_port6_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port6_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3910,9 +3781,8 @@ static struct clk_branch gcc_port1_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port1_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3927,9 +3797,8 @@ static struct clk_branch gcc_port2_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port2_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3944,9 +3813,8 @@ static struct clk_branch gcc_port3_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port3_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3961,9 +3829,8 @@ static struct clk_branch gcc_port4_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port4_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3978,9 +3845,8 @@ static struct clk_branch gcc_port5_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port5_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3995,9 +3861,8 @@ static struct clk_branch gcc_port6_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port6_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4012,9 +3877,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port1_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4029,9 +3893,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port1_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4046,9 +3909,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port2_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4063,9 +3925,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port2_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4080,9 +3941,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port3_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4097,9 +3957,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port3_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4114,9 +3973,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port4_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4131,9 +3989,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port4_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4148,9 +4005,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port5_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4165,9 +4021,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port5_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4182,9 +4037,8 @@ static struct clk_branch gcc_uniphy1_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_port5_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4199,9 +4053,8 @@ static struct clk_branch gcc_uniphy1_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_port5_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4216,9 +4069,8 @@ static struct clk_branch gcc_uniphy2_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_port6_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4233,9 +4085,8 @@ static struct clk_branch gcc_uniphy2_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_port6_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4251,9 +4102,8 @@ static struct clk_branch gcc_crypto_ahb_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4269,9 +4119,8 @@ static struct clk_branch gcc_crypto_axi_
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_axi_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4287,9 +4136,8 @@ static struct clk_branch gcc_crypto_clk
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_clk",
-- .parent_names = (const char *[]){
-- "crypto_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &crypto_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4304,9 +4152,8 @@ static struct clk_branch gcc_gp1_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp1_clk",
-- .parent_names = (const char *[]){
-- "gp1_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gp1_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4321,9 +4168,8 @@ static struct clk_branch gcc_gp2_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp2_clk",
-- .parent_names = (const char *[]){
-- "gp2_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gp2_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4338,9 +4184,8 @@ static struct clk_branch gcc_gp3_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp3_clk",
-- .parent_names = (const char *[]){
-- "gp3_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gp3_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4362,7 +4207,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie0_rchng_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
+++ /dev/null
-From 8857b0ab6a562c473c5bded0efda9390b82a84d4 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 27 Sep 2022 22:12:17 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: fix NAND node name
-
-Per schema it should be nand-controller@79b0000 instead of nand@79b0000.
-Fix it to match nand-controller.yaml requirements.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220927201218.1264506-1-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -348,7 +348,7 @@
- status = "disabled";
- };
-
-- qpic_nand: nand@79b0000 {
-+ qpic_nand: nand-controller@79b0000 {
- compatible = "qcom,ipq6018-nand";
- reg = <0x0 0x079b0000 0x0 0x10000>;
- #address-cells = <1>;
+++ /dev/null
-From e78a40eb24187a8b4f9b89e2181f674df39c2013 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 7 Nov 2022 14:29:00 +0100
-Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add missing networking
- resets
-
-Add bindings for the missing networking resets found in IPQ8074 GCC.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221107132901.489240-2-robimarko@gmail.com
----
- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-@@ -367,6 +367,20 @@
- #define GCC_PCIE1_AHB_ARES 129
- #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
- #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
-+#define GCC_PPE_FULL_RESET 132
-+#define GCC_UNIPHY0_SOFT_RESET 133
-+#define GCC_UNIPHY0_XPCS_RESET 134
-+#define GCC_UNIPHY1_SOFT_RESET 135
-+#define GCC_UNIPHY1_XPCS_RESET 136
-+#define GCC_UNIPHY2_SOFT_RESET 137
-+#define GCC_UNIPHY2_XPCS_RESET 138
-+#define GCC_EDMA_HW_RESET 139
-+#define GCC_NSSPORT1_RESET 140
-+#define GCC_NSSPORT2_RESET 141
-+#define GCC_NSSPORT3_RESET 142
-+#define GCC_NSSPORT4_RESET 143
-+#define GCC_NSSPORT5_RESET 144
-+#define GCC_NSSPORT6_RESET 145
-
- #define USB0_GDSC 0
- #define USB1_GDSC 1
+++ /dev/null
-From da76cb63d04dc22ed32123b8c1d084c006d67bfb Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 7 Nov 2022 14:29:01 +0100
-Subject: [PATCH] clk: qcom: ipq8074: add missing networking resets
-
-Downstream QCA 5.4 kernel defines networking resets which are not present
-in the mainline kernel but are required for the networking drivers.
-
-So, port the downstream resets and avoid using magic values for mask,
-construct mask for resets which require multiple bits to be set/cleared.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221107132901.489240-3-robimarko@gmail.com
----
- drivers/clk/qcom/gcc-ipq8074.c | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -4665,6 +4665,20 @@ static const struct qcom_reset_map gcc_i
- [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
- [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
- [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
-+ [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
-+ [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
-+ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
-+ [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
-+ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
-+ [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
-+ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
-+ [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
-+ [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
-+ [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
-+ [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
-+ [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
-+ [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
-+ [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
- };
-
- static struct gdsc *gcc_ipq8074_gdscs[] = {
+++ /dev/null
-From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:46:55 +0100
-Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
-
-It appears that having only .name populated in parent_data for clocks
-which are only globally searchable currently will not work as the clk core
-won't copy that name if there is no .fw_name present as well.
-
-So, populate .fw_name for all parent clocks in parent_data.
-
-Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
-
-Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
----
- drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
- 1 file changed, 26 insertions(+), 26 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -674,7 +674,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
- };
-
- static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
-- { .name = "pcie20_phy0_pipe_clk" },
-+ { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
- { .fw_name = "xo", .name = "xo" },
- };
-
-@@ -727,7 +727,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
- };
-
- static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
-- { .name = "pcie20_phy1_pipe_clk" },
-+ { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
- { .fw_name = "xo", .name = "xo" },
- };
-
-@@ -1131,7 +1131,7 @@ static const struct freq_tbl ftbl_nss_no
-
- static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "bias_pll_nss_noc_clk" },
-+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
- { .hw = &gpll0.clkr.hw },
- { .hw = &gpll2.clkr.hw },
- };
-@@ -1356,7 +1356,7 @@ static const struct freq_tbl ftbl_nss_pp
-
- static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- { .hw = &gpll0.clkr.hw },
- { .hw = &gpll4.clkr.hw },
- { .hw = &nss_crypto_pll.clkr.hw },
-@@ -1407,10 +1407,10 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy0_gcc_rx_clk" },
-- { .name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
-@@ -1459,10 +1459,10 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy0_gcc_tx_clk" },
-- { .name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
-@@ -1690,12 +1690,12 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy0_gcc_rx_clk" },
-- { .name = "uniphy0_gcc_tx_clk" },
-- { .name = "uniphy1_gcc_rx_clk" },
-- { .name = "uniphy1_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
-+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map
-@@ -1752,12 +1752,12 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy0_gcc_tx_clk" },
-- { .name = "uniphy0_gcc_rx_clk" },
-- { .name = "uniphy1_gcc_tx_clk" },
-- { .name = "uniphy1_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
-+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map
-@@ -1814,10 +1814,10 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy2_gcc_rx_clk" },
-- { .name = "uniphy2_gcc_tx_clk" },
-+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
-+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
-@@ -1871,10 +1871,10 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
- { .fw_name = "xo", .name = "xo" },
-- { .name = "uniphy2_gcc_tx_clk" },
-- { .name = "uniphy2_gcc_rx_clk" },
-+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
-+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
+++ /dev/null
-From 9033c3c86ea0dd35bd2ab957317573b755967298 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 30 Oct 2022 18:57:03 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: pass XO and sleep clocks to GCC
-
-Pass XO and sleep clocks to the GCC controller so it does not have to
-find them by matching globaly by name.
-
-If not passed directly, driver maintains backwards compatibility by then
-falling back to global lookup.
-
-Since we are here, set cell numbers in decimal instead of hex.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221030175703.1103224-3-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -363,9 +363,11 @@
- gcc: gcc@1800000 {
- compatible = "qcom,gcc-ipq8074";
- reg = <0x01800000 0x80000>;
-- #clock-cells = <0x1>;
-+ clocks = <&xo>, <&sleep_clk>;
-+ clock-names = "xo", "sleep_clk";
-+ #clock-cells = <1>;
- #power-domain-cells = <1>;
-- #reset-cells = <0x1>;
-+ #reset-cells = <1>;
- };
-
- tcsr_mutex: hwlock@1905000 {
+++ /dev/null
-From fb76b808f8628215afebaf0f8af0bde635302590 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:18:14 +0200
-Subject: [PATCH] arm64: dts: qcom: add PMP8074 DTSI
-
-PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is
-controlled via SPMI.
-
-Add DTSI for it providing GPIO, regulator, RTC and VADC support.
-
-RTC is disabled by default as there is no built-in battery so it will
-loose time unless board vendor added a battery, so make it optional.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/pmp8074.dtsi | 125 ++++++++++++++++++++++++++
- 1 file changed, 125 insertions(+)
- create mode 100644 arch/arm64/boot/dts/qcom/pmp8074.dtsi
-
---- /dev/null
-+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
-@@ -0,0 +1,125 @@
-+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
-+
-+#include <dt-bindings/spmi/spmi.h>
-+#include <dt-bindings/iio/qcom,spmi-vadc.h>
-+
-+&spmi_bus {
-+ pmic@0 {
-+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
-+ reg = <0x0 SPMI_USID>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pmp8074_adc: adc@3100 {
-+ compatible = "qcom,spmi-adc-rev2";
-+ reg = <0x3100>;
-+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ #io-channel-cells = <1>;
-+
-+ ref-gnd@0 {
-+ reg = <ADC5_REF_GND>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ vref-1p25@1 {
-+ reg = <ADC5_1P25VREF>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ vref-vadc@2 {
-+ reg = <ADC5_VREF_VADC>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ pmic_die: die-temp@6 {
-+ reg = <ADC5_DIE_TEMP>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ xo_therm: xo-temp@76 {
-+ reg = <ADC5_XO_THERM_100K_PU>;
-+ qcom,ratiometric;
-+ qcom,hw-settle-time = <200>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ pa_therm1: thermistor1@77 {
-+ reg = <ADC5_AMUX_THM1_100K_PU>;
-+ qcom,ratiometric;
-+ qcom,hw-settle-time = <200>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ pa_therm2: thermistor2@78 {
-+ reg = <ADC5_AMUX_THM2_100K_PU>;
-+ qcom,ratiometric;
-+ qcom,hw-settle-time = <200>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ pa_therm3: thermistor3@79 {
-+ reg = <ADC5_AMUX_THM3_100K_PU>;
-+ qcom,ratiometric;
-+ qcom,hw-settle-time = <200>;
-+ qcom,pre-scaling = <1 1>;
-+ };
-+
-+ vph-pwr@131 {
-+ reg = <ADC5_VPH_PWR>;
-+ qcom,pre-scaling = <1 3>;
-+ };
-+ };
-+
-+ pmp8074_rtc: rtc@6000 {
-+ compatible = "qcom,pm8941-rtc";
-+ reg = <0x6000>;
-+ reg-names = "rtc", "alarm";
-+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
-+ allow-set-time;
-+ status = "disabled";
-+ };
-+
-+ pmp8074_gpios: gpio@c000 {
-+ compatible = "qcom,pmp8074-gpio", "qcom,spmi-gpio";
-+ reg = <0xc000>;
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ gpio-ranges = <&pmp8074_gpios 0 0 12>;
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+ };
-+
-+ pmic@1 {
-+ compatible = "qcom,pmp8074", "qcom,spmi-pmic";
-+ reg = <0x1 SPMI_USID>;
-+
-+ regulators {
-+ compatible = "qcom,pmp8074-regulators";
-+
-+ s3: s3 {
-+ regulator-name = "vdd_s3";
-+ regulator-min-microvolt = <592000>;
-+ regulator-max-microvolt = <1064000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ s4: s4 {
-+ regulator-name = "vdd_s4";
-+ regulator-min-microvolt = <712000>;
-+ regulator-max-microvolt = <992000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ l11: l11 {
-+ regulator-name = "l11";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+ };
-+ };
-+};
+++ /dev/null
-From 2c394cfc1779886048feca7dc7f4075da5f6328c Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:18:15 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074-hk01: add VQMMC supply
-
-Since now we have control over the PMP8074 PMIC providing various system
-voltages including L11 which provides the SDIO/eMMC I/O voltage set it as
-the SDHCI VQMMC supply.
-
-This allows SDHCI controller to switch to 1.8V I/O mode and support high
-speed modes like HS200 and HS400.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818221815.346233-5-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-@@ -3,6 +3,7 @@
- /* Copyright (c) 2017, The Linux Foundation. All rights reserved.
- */
- #include "ipq8074.dtsi"
-+#include "pmp8074.dtsi"
-
- / {
- model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
-@@ -84,6 +85,7 @@
-
- &sdhc_1 {
- status = "okay";
-+ vqmmc-supply = <&l11>;
- };
-
- &qusb_phy_0 {
+++ /dev/null
-From 82ceb86227b1fc15c76d5fc691b2bf425f1a63b3 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 7 Nov 2022 10:29:30 +0100
-Subject: [PATCH] arm64: dts: qcom: hk01: use GPIO flags for tlmm
-
-Use respective GPIO_ACTIVE_LOW/HIGH flags for tlmm GPIOs instead of
-harcoding the cell value.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221107092930.33325-3-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-@@ -4,6 +4,7 @@
- */
- #include "ipq8074.dtsi"
- #include "pmp8074.dtsi"
-+#include <dt-bindings/gpio/gpio.h>
-
- / {
- model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
-@@ -52,12 +53,12 @@
-
- &pcie0 {
- status = "okay";
-- perst-gpios = <&tlmm 61 0x1>;
-+ perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- };
-
- &pcie1 {
- status = "okay";
-- perst-gpios = <&tlmm 58 0x1>;
-+ perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- };
-
- &pcie_qmp0 {
+++ /dev/null
-From 1b1c1423ca3e740984aa883512a72c4ea08fbe28 Mon Sep 17 00:00:00 2001
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-Date: Mon, 7 Nov 2022 15:55:17 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074-*: Fix up comments
-
-Make sure all multiline C-style commends begin with just '/*' with
-the comment text starting on a new line.
-
-Also, fix up some whitespace within comments.
-
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221107145522.6706-8-konrad.dybcio@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 3 ++-
- arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts | 3 ++-
- arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts | 3 ++-
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++------
- 4 files changed, 12 insertions(+), 9 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-@@ -1,6 +1,7 @@
- // SPDX-License-Identifier: GPL-2.0-only
- /dts-v1/;
--/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
- */
- #include "ipq8074.dtsi"
- #include "pmp8074.dtsi"
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dts
-@@ -1,5 +1,6 @@
- // SPDX-License-Identifier: GPL-2.0-only
--/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
-+/*
-+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
- */
- /dts-v1/;
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dts
-@@ -1,6 +1,7 @@
- // SPDX-License-Identifier: GPL-2.0-only
- /dts-v1/;
--/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
-+/*
-+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
- */
- #include "ipq8074-hk10.dtsi"
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -129,10 +129,10 @@
- status = "disabled";
-
- usb1_ssphy: phy@58200 {
-- reg = <0x00058200 0x130>, /* Tx */
-+ reg = <0x00058200 0x130>, /* Tx */
- <0x00058400 0x200>, /* Rx */
-- <0x00058800 0x1f8>, /* PCS */
-- <0x00058600 0x044>; /* PCS misc*/
-+ <0x00058800 0x1f8>, /* PCS */
-+ <0x00058600 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB1_PIPE_CLK>;
-@@ -172,10 +172,10 @@
- status = "disabled";
-
- usb0_ssphy: phy@78200 {
-- reg = <0x00078200 0x130>, /* Tx */
-+ reg = <0x00078200 0x130>, /* Tx */
- <0x00078400 0x200>, /* Rx */
-- <0x00078800 0x1f8>, /* PCS */
-- <0x00078600 0x044>; /* PCS misc*/
-+ <0x00078800 0x1f8>, /* PCS */
-+ <0x00078600 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
+++ /dev/null
-From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Tue, 8 Nov 2022 15:23:57 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
- DT schema
-
-DT schema expects TLMM pin configuration nodes to be named with
-'-state' suffix and their optional children with '-pins' suffix.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -320,35 +320,35 @@
- interrupt-controller;
- #interrupt-cells = <0x2>;
-
-- serial_4_pins: serial4-pinmux {
-+ serial_4_pins: serial4-state {
- pins = "gpio23", "gpio24";
- function = "blsp4_uart1";
- drive-strength = <8>;
- bias-disable;
- };
-
-- i2c_0_pins: i2c-0-pinmux {
-+ i2c_0_pins: i2c-0-state {
- pins = "gpio42", "gpio43";
- function = "blsp1_i2c";
- drive-strength = <8>;
- bias-disable;
- };
-
-- spi_0_pins: spi-0-pins {
-+ spi_0_pins: spi-0-state {
- pins = "gpio38", "gpio39", "gpio40", "gpio41";
- function = "blsp0_spi";
- drive-strength = <8>;
- bias-disable;
- };
-
-- hsuart_pins: hsuart-pins {
-+ hsuart_pins: hsuart-state {
- pins = "gpio46", "gpio47", "gpio48", "gpio49";
- function = "blsp2_uart";
- drive-strength = <8>;
- bias-disable;
- };
-
-- qpic_pins: qpic-pins {
-+ qpic_pins: qpic-state {
- pins = "gpio1", "gpio3", "gpio4",
- "gpio5", "gpio6", "gpio7",
- "gpio8", "gpio10", "gpio11",
+++ /dev/null
-From 20afb6751739264ea41993877de93923911dfdc3 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Thu, 6 Oct 2022 14:46:27 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: align TLMM pin configuration with
- DT schema
-
-DT schema expects TLMM pin configuration nodes to be named with
-'-state' suffix and their optional children with '-pins' suffix.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Bjorn Andersson <andersson@kernel.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221006124659.217540-3-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 4 ++--
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
- 2 files changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
-@@ -51,13 +51,13 @@
- };
-
- &tlmm {
-- i2c_1_pins: i2c-1-pins {
-+ i2c_1_pins: i2c-1-state {
- pins = "gpio42", "gpio43";
- function = "blsp2_i2c";
- drive-strength = <8>;
- };
-
-- spi_0_pins: spi-0-pins {
-+ spi_0_pins: spi-0-state {
- pins = "gpio38", "gpio39", "gpio40", "gpio41";
- function = "blsp0_spi";
- drive-strength = <8>;
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -218,14 +218,14 @@
- interrupt-controller;
- #interrupt-cells = <2>;
-
-- serial_3_pins: serial3-pinmux {
-+ serial_3_pins: serial3-state {
- pins = "gpio44", "gpio45";
- function = "blsp2_uart";
- drive-strength = <8>;
- bias-pull-down;
- };
-
-- qpic_pins: qpic-pins {
-+ qpic_pins: qpic-state {
- pins = "gpio1", "gpio3", "gpio4",
- "gpio5", "gpio6", "gpio7",
- "gpio8", "gpio10", "gpio11",
+++ /dev/null
-From a4748d2850783d36f77ccf2b5fcc86ccf1800ef1 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:48:36 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed
-
-Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
-generation limit.
-This allows the generic DWC code to configure the link speed correctly.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -768,6 +768,7 @@
- linux,pci-domain = <1>;
- bus-range = <0x00 0xff>;
- num-lanes = <1>;
-+ max-link-speed = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
-
+++ /dev/null
-From f356132229b18ceef5d5ef9103bbaa9bdeb84c8d Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 13 Jan 2023 17:44:47 +0100
-Subject: [PATCH] PCI: qcom: Add IPQ8074 Gen3 port support
-
-IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
-Add compatible for Gen3 port which uses the same controller as IPQ6018.
-
-Link: https://lore.kernel.org/r/20230113164449.906002-7-robimarko@gmail.com
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
----
- drivers/pci/controller/dwc/pcie-qcom.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -1762,6 +1762,7 @@ static const struct of_device_id qcom_pc
- { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
- { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
- { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
-+ { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
- { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
- { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
- { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
+++ /dev/null
-From 614d31c231c7707322b643f409eeb7e28adc7f8c Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 8 Jan 2023 13:36:28 +0100
-Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for usb3phy-s
-
-Having only .name populated in parent_data for clocks which are only
-globally searchable currently will not work as the clk core won't copy
-that name if there is no .fw_name present as well.
-
-So, populate .fw_name for usb3phy clocks in parent_data as they were
-missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents").
-
-Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/clk/qcom/gcc-ipq8074.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -928,7 +928,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
- };
-
- static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
-- { .name = "usb3phy_0_cc_pipe_clk" },
-+ { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
- { .fw_name = "xo", .name = "xo" },
- };
-
-@@ -996,7 +996,7 @@ static struct clk_rcg2 usb1_mock_utmi_cl
- };
-
- static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
-- { .name = "usb3phy_1_cc_pipe_clk" },
-+ { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
- { .fw_name = "xo", .name = "xo" },
- };
-
+++ /dev/null
-From d93bd4630ce163f3761aedc0b342b072bee6db6b Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 22 Mar 2023 18:41:40 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add compatible fallback to mailbox
-
-IPQ8074 mailbox is compatible with IPQ6018.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230322174148.810938-4-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -682,7 +682,8 @@
- };
-
- apcs_glb: mailbox@b111000 {
-- compatible = "qcom,ipq8074-apcs-apps-global";
-+ compatible = "qcom,ipq8074-apcs-apps-global",
-+ "qcom,ipq6018-apcs-apps-global";
- reg = <0x0b111000 0x1000>;
- clocks = <&a53pll>, <&xo>;
- clock-names = "pll", "xo";
+++ /dev/null
-From 56d3067cb694ba60d654e7f5ef231b6fabc4697f Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 7 Jun 2023 20:44:48 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add critical thermal trips
-
-According to bindings, thermal zones must have associated trips as well.
-Since we currently dont have CPUFreq support and thus no passive cooling
-lets start by defining critical trips to protect the devices against
-severe overheating.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230607184448.2512179-1-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
- 1 file changed, 96 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -899,6 +899,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 4>;
-+
-+ trips {
-+ nss-top-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
-
- nss0-thermal {
-@@ -906,6 +914,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 5>;
-+
-+ trips {
-+ nss-0-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
-
- nss1-thermal {
-@@ -913,6 +929,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 6>;
-+
-+ trips {
-+ nss-1-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
-
- wcss-phya0-thermal {
-@@ -920,6 +944,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 7>;
-+
-+ trips {
-+ wcss-phya0-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
-
- wcss-phya1-thermal {
-@@ -927,6 +959,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 8>;
-+
-+ trips {
-+ wcss-phya1-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
-
- cpu0_thermal: cpu0-thermal {
-@@ -934,6 +974,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 9>;
-+
-+ trips {
-+ cpu0-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
-
- cpu1_thermal: cpu1-thermal {
-@@ -941,6 +989,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 10>;
-+
-+ trips {
-+ cpu1-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
-
- cpu2_thermal: cpu2-thermal {
-@@ -948,6 +1004,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 11>;
-+
-+ trips {
-+ cpu2-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
-
- cpu3_thermal: cpu3-thermal {
-@@ -955,6 +1019,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 12>;
-+
-+ trips {
-+ cpu3-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
-
- cluster_thermal: cluster-thermal {
-@@ -962,6 +1034,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 13>;
-+
-+ trips {
-+ cluster-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
-
- wcss-phyb0-thermal {
-@@ -969,6 +1049,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 14>;
-+
-+ trips {
-+ wcss-phyb0-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
-
- wcss-phyb1-thermal {
-@@ -976,6 +1064,14 @@
- polling-delay = <1000>;
-
- thermal-sensors = <&tsens 15>;
-+
-+ trips {
-+ wcss-phyb1-crit {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
- };
- };
- };
+++ /dev/null
-From 93e161c8f4b9b051e5e746814138cb5520b4b897 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 1 Sep 2023 20:10:04 +0200
-Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ8174 family
-
-IPQ8174 (Oak) family is part of the IPQ8074 family, but the ID-s for it
-are missing so lets add them.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Kathiravan T <quic_kathirav@quicinc.com>
-Acked-by: Conor Dooley <conor.dooley@microchip.com>
-Link: https://lore.kernel.org/r/20230901181041.1538999-1-robimarko@gmail.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- include/dt-bindings/arm/qcom,ids.h | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/include/dt-bindings/arm/qcom,ids.h
-+++ b/include/dt-bindings/arm/qcom,ids.h
-@@ -121,6 +121,9 @@
- #define QCOM_ID_SM6125 394
- #define QCOM_ID_IPQ8070A 395
- #define QCOM_ID_IPQ8071A 396
-+#define QCOM_ID_IPQ8172 397
-+#define QCOM_ID_IPQ8173 398
-+#define QCOM_ID_IPQ8174 399
- #define QCOM_ID_IPQ6018 402
- #define QCOM_ID_IPQ6028 403
- #define QCOM_ID_IPQ6000 421
+++ /dev/null
-From 47e161a7873b0891f4e01a69a839f6161d816ea8 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 25 Oct 2023 14:57:57 +0530
-Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ6018
-
-IPQ6018 SoC series comes in multiple SKU-s, and not all of them support
-high frequency OPP points.
-
-SoC itself does however have a single bit in QFPROM to indicate the CPU
-speed-bin.
-That bit is used to indicate frequency limit of 1.5GHz, but that alone is
-not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to
-limit it further.
-
-IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device
-will get created by NVMEM CPUFreq driver.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-[ Viresh: Fixed rebase conflict. ]
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
- drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++
- 2 files changed, 59 insertions(+)
-
---- a/drivers/cpufreq/cpufreq-dt-platdev.c
-+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -163,6 +163,7 @@ static const struct of_device_id blockli
- { .compatible = "ti,dra7", },
- { .compatible = "ti,omap3", },
-
-+ { .compatible = "qcom,ipq6018", },
- { .compatible = "qcom,ipq8064", },
- { .compatible = "qcom,apq8064", },
- { .compatible = "qcom,msm8974", },
---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
-@@ -31,6 +31,8 @@
-
- #include <dt-bindings/arm/qcom,ids.h>
-
-+#define IPQ6000_VERSION BIT(2)
-+
- struct qcom_cpufreq_drv;
-
- struct qcom_cpufreq_match_data {
-@@ -204,6 +206,57 @@ len_error:
- return ret;
- }
-
-+static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
-+ struct nvmem_cell *speedbin_nvmem,
-+ char **pvs_name,
-+ struct qcom_cpufreq_drv *drv)
-+{
-+ u32 msm_id;
-+ int ret;
-+ u8 *speedbin;
-+ *pvs_name = NULL;
-+
-+ ret = qcom_smem_get_soc_id(&msm_id);
-+ if (ret)
-+ return ret;
-+
-+ speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
-+ if (IS_ERR(speedbin))
-+ return PTR_ERR(speedbin);
-+
-+ switch (msm_id) {
-+ case QCOM_ID_IPQ6005:
-+ case QCOM_ID_IPQ6010:
-+ case QCOM_ID_IPQ6018:
-+ case QCOM_ID_IPQ6028:
-+ /* Fuse Value Freq BIT to set
-+ * ---------------------------------
-+ * 2’b0 No Limit BIT(0)
-+ * 2’b1 1.5 GHz BIT(1)
-+ */
-+ drv->versions = 1 << (unsigned int)(*speedbin);
-+ break;
-+ case QCOM_ID_IPQ6000:
-+ /*
-+ * IPQ6018 family only has one bit to advertise the CPU
-+ * speed-bin, but that is not enough for IPQ6000 which
-+ * is only rated up to 1.2GHz.
-+ * So for IPQ6000 manually set BIT(2) based on SMEM ID.
-+ */
-+ drv->versions = IPQ6000_VERSION;
-+ break;
-+ default:
-+ dev_err(cpu_dev,
-+ "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
-+ msm_id);
-+ drv->versions = IPQ6000_VERSION;
-+ break;
-+ }
-+
-+ kfree(speedbin);
-+ return 0;
-+}
-+
- static const struct qcom_cpufreq_match_data match_data_kryo = {
- .get_version = qcom_cpufreq_kryo_name_version,
- };
-@@ -218,6 +271,10 @@ static const struct qcom_cpufreq_match_d
- .genpd_names = qcs404_genpd_names,
- };
-
-+static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
-+ .get_version = qcom_cpufreq_ipq6018_name_version,
-+};
-+
- static int qcom_cpufreq_probe(struct platform_device *pdev)
- {
- struct qcom_cpufreq_drv *drv;
-@@ -362,6 +419,7 @@ static const struct of_device_id qcom_cp
- { .compatible = "qcom,apq8096", .data = &match_data_kryo },
- { .compatible = "qcom,msm8996", .data = &match_data_kryo },
- { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
-+ { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
- { .compatible = "qcom,ipq8064", .data = &match_data_krait },
- { .compatible = "qcom,apq8064", .data = &match_data_krait },
- { .compatible = "qcom,msm8974", .data = &match_data_krait },
+++ /dev/null
-From 0b9cd949136f1b63f7aa9424b6e583a1ab261e36 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 13 Oct 2023 19:20:02 +0200
-Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
-
-IPQ8074 comes in 3 families:
-* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
-* IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz
-* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
-
-So, in order to be able to share one OPP table lets add support for IPQ8074
-family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
-
-IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
-will get created by NVMEM CPUFreq driver.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-[ Viresh: Fixed rebase conflict. ]
-Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
----
- drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
- drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++
- 2 files changed, 49 insertions(+)
-
---- a/drivers/cpufreq/cpufreq-dt-platdev.c
-+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
-@@ -165,6 +165,7 @@ static const struct of_device_id blockli
-
- { .compatible = "qcom,ipq6018", },
- { .compatible = "qcom,ipq8064", },
-+ { .compatible = "qcom,ipq8074", },
- { .compatible = "qcom,apq8064", },
- { .compatible = "qcom,msm8974", },
- { .compatible = "qcom,msm8960", },
---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
-+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
-@@ -33,6 +33,11 @@
-
- #define IPQ6000_VERSION BIT(2)
-
-+enum ipq8074_versions {
-+ IPQ8074_HAWKEYE_VERSION = 0,
-+ IPQ8074_ACORN_VERSION,
-+};
-+
- struct qcom_cpufreq_drv;
-
- struct qcom_cpufreq_match_data {
-@@ -257,6 +262,44 @@ static int qcom_cpufreq_ipq6018_name_ver
- return 0;
- }
-
-+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
-+ struct nvmem_cell *speedbin_nvmem,
-+ char **pvs_name,
-+ struct qcom_cpufreq_drv *drv)
-+{
-+ u32 msm_id;
-+ int ret;
-+ *pvs_name = NULL;
-+
-+ ret = qcom_smem_get_soc_id(&msm_id);
-+ if (ret)
-+ return ret;
-+
-+ switch (msm_id) {
-+ case QCOM_ID_IPQ8070A:
-+ case QCOM_ID_IPQ8071A:
-+ case QCOM_ID_IPQ8172:
-+ case QCOM_ID_IPQ8173:
-+ case QCOM_ID_IPQ8174:
-+ drv->versions = BIT(IPQ8074_ACORN_VERSION);
-+ break;
-+ case QCOM_ID_IPQ8072A:
-+ case QCOM_ID_IPQ8074A:
-+ case QCOM_ID_IPQ8076A:
-+ case QCOM_ID_IPQ8078A:
-+ drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
-+ break;
-+ default:
-+ dev_err(cpu_dev,
-+ "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
-+ msm_id);
-+ drv->versions = BIT(IPQ8074_ACORN_VERSION);
-+ break;
-+ }
-+
-+ return 0;
-+}
-+
- static const struct qcom_cpufreq_match_data match_data_kryo = {
- .get_version = qcom_cpufreq_kryo_name_version,
- };
-@@ -275,6 +318,10 @@ static const struct qcom_cpufreq_match_d
- .get_version = qcom_cpufreq_ipq6018_name_version,
- };
-
-+static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
-+ .get_version = qcom_cpufreq_ipq8074_name_version,
-+};
-+
- static int qcom_cpufreq_probe(struct platform_device *pdev)
- {
- struct qcom_cpufreq_drv *drv;
-@@ -421,6 +468,7 @@ static const struct of_device_id qcom_cp
- { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
- { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
- { .compatible = "qcom,ipq8064", .data = &match_data_krait },
-+ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
- { .compatible = "qcom,apq8064", .data = &match_data_krait },
- { .compatible = "qcom,msm8974", .data = &match_data_krait },
- { .compatible = "qcom,msm8960", .data = &match_data_krait },
+++ /dev/null
-From c917237a7cb17b97cc48e073881a9873f3caeaa2 Mon Sep 17 00:00:00 2001
-From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
-Date: Thu, 14 Sep 2023 12:29:57 +0530
-Subject: [PATCH] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock
- provider
-
-While the kernel is booting up, APSS PLL will be running at 800MHz with
-GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
-configured and select the rate based on the opp table and the source will
-be changed to APSS_PLL_EARLY.
-
-Without this patch, CPU Freq driver reports that CPU is running at 24MHz
-instead of the 800MHz.
-
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Tested-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
----
- drivers/clk/qcom/apss-ipq6018.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/clk/qcom/apss-ipq6018.c
-+++ b/drivers/clk/qcom/apss-ipq6018.c
-@@ -20,16 +20,19 @@
-
- enum {
- P_XO,
-+ P_GPLL0,
- P_APSS_PLL_EARLY,
- };
-
- static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
- { .fw_name = "xo" },
-+ { .fw_name = "gpll0" },
- { .fw_name = "pll" },
- };
-
- static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
- { P_XO, 0 },
-+ { P_GPLL0, 4 },
- { P_APSS_PLL_EARLY, 5 },
- };
-
+++ /dev/null
-From 3b48a7d925a757b3fa53c04baaf68bb8313c3ffb Mon Sep 17 00:00:00 2001
-From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
-Date: Thu, 14 Sep 2023 12:29:58 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq8074: include the GPLL0 as clock
- provider for mailbox
-
-While the kernel is booting up, APSS PLL will be running at 800MHz with
-GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
-configured to the rate based on the opp table and the source also will
-be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
-with this inclusion, CPU Freq correctly reports that CPU is running at
-800MHz rather than 24MHz.
-
-Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -685,8 +685,8 @@
- compatible = "qcom,ipq8074-apcs-apps-global",
- "qcom,ipq6018-apcs-apps-global";
- reg = <0x0b111000 0x1000>;
-- clocks = <&a53pll>, <&xo>;
-- clock-names = "pll", "xo";
-+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
-+ clock-names = "pll", "xo", "gpll0";
-
- #clock-cells = <1>;
- #mbox-cells = <1>;
+++ /dev/null
-From c0877a26b7ee54ef30d16ffdcdd37f2bcffe518e Mon Sep 17 00:00:00 2001
-From: Kathiravan T <quic_kathirav@quicinc.com>
-Date: Wed, 8 Feb 2023 11:27:08 +0530
-Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ5332 and its
- variant
-
-Add SOC ID for Qualcomm IPQ5332 and IPQ5322 variants.
-
-Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230208055709.13162-2-quic_kathirav@quicinc.com
----
- include/dt-bindings/arm/qcom,ids.h | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/include/dt-bindings/arm/qcom,ids.h
-+++ b/include/dt-bindings/arm/qcom,ids.h
-@@ -143,6 +143,8 @@
- #define QCOM_ID_SC7280 487
- #define QCOM_ID_SC7180P 495
- #define QCOM_ID_SM6375 507
-+#define QCOM_ID_IPQ5332 592
-+#define QCOM_ID_IPQ5322 593
-
- /*
- * The board type and revision information, used by Qualcomm bootloaders and
+++ /dev/null
-From 725352e15e1d030885611a546eb1f2884851a407 Mon Sep 17 00:00:00 2001
-From: Varadarajan Narayanan <quic_varada@quicinc.com>
-Date: Tue, 14 Mar 2023 11:43:33 +0530
-Subject: [PATCH] dt-bindings: arm: qcom,ids: Add IDs for IPQ9574 and its
- variants
-
-Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550,
-IPQ9514 and IPQ9510
-
-Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Kathiravan T <quic_kathirav@quicinc.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/1678774414-14414-2-git-send-email-quic_varada@quicinc.com
----
- include/dt-bindings/arm/qcom,ids.h | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/include/dt-bindings/arm/qcom,ids.h
-+++ b/include/dt-bindings/arm/qcom,ids.h
-@@ -143,6 +143,12 @@
- #define QCOM_ID_SC7280 487
- #define QCOM_ID_SC7180P 495
- #define QCOM_ID_SM6375 507
-+#define QCOM_ID_IPQ9514 510
-+#define QCOM_ID_IPQ9550 511
-+#define QCOM_ID_IPQ9554 512
-+#define QCOM_ID_IPQ9570 513
-+#define QCOM_ID_IPQ9574 514
-+#define QCOM_ID_IPQ9510 521
- #define QCOM_ID_IPQ5332 592
- #define QCOM_ID_IPQ5322 593
-
+++ /dev/null
-From 614c778cf0d570642c50715adfa0b70930d8cf29 Mon Sep 17 00:00:00 2001
-From: Kathiravan T <quic_kathirav@quicinc.com>
-Date: Tue, 9 May 2023 09:05:30 +0530
-Subject: [PATCH] dt-bindings: arm: qcom,ids: add SoC ID for IPQ5312 and
- IPQ5302
-
-Add the SoC ID for IPQ5312 and IPQ5302, which belong to the family of
-IPQ5332 SoC.
-
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230509033531.21468-2-quic_kathirav@quicinc.com
----
- include/dt-bindings/arm/qcom,ids.h | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/include/dt-bindings/arm/qcom,ids.h
-+++ b/include/dt-bindings/arm/qcom,ids.h
-@@ -151,6 +151,8 @@
- #define QCOM_ID_IPQ9510 521
- #define QCOM_ID_IPQ5332 592
- #define QCOM_ID_IPQ5322 593
-+#define QCOM_ID_IPQ5312 594
-+#define QCOM_ID_IPQ5302 595
-
- /*
- * The board type and revision information, used by Qualcomm bootloaders and
+++ /dev/null
-From b3c72f2795467e3d43ee429b0ebd5f523ec08f60 Mon Sep 17 00:00:00 2001
-From: Kathiravan T <quic_kathirav@quicinc.com>
-Date: Mon, 5 Jun 2023 13:35:28 +0530
-Subject: [PATCH] dt-bindings: arm: qcom,ids: add SoC ID for IPQ5300
-
-Add the SoC ID for IPQ5300, which belong to the family of IPQ5332 SoC.
-
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230605080531.3879-2-quic_kathirav@quicinc.com
----
- include/dt-bindings/arm/qcom,ids.h | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/include/dt-bindings/arm/qcom,ids.h
-+++ b/include/dt-bindings/arm/qcom,ids.h
-@@ -153,6 +153,7 @@
- #define QCOM_ID_IPQ5322 593
- #define QCOM_ID_IPQ5312 594
- #define QCOM_ID_IPQ5302 595
-+#define QCOM_ID_IPQ5300 624
-
- /*
- * The board type and revision information, used by Qualcomm bootloaders and
+++ /dev/null
-From feeef118fda562cf9081edef8ad464d89db070f4 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 27 Sep 2022 22:12:18 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node
-
-The ARM timer is usually considered not part of SoC node, just like
-other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
-
-arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
- From schema: dtschema/schemas/simple-bus.yaml
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220927201218.1264506-2-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -510,14 +510,6 @@
- clock-names = "xo";
- };
-
-- timer {
-- compatible = "arm,armv8-timer";
-- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-- };
--
- timer@b120000 {
- #address-cells = <1>;
- #size-cells = <1>;
-@@ -769,6 +761,14 @@
- };
- };
-
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-+ };
-+
- wcss: wcss-smp2p {
- compatible = "qcom,smp2p";
- qcom,smem = <435>, <428>;
+++ /dev/null
-From 2c6e322a41c5e1ca45be50b9d5fbcda62dc23a0d Mon Sep 17 00:00:00 2001
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-Date: Mon, 2 Jan 2023 10:46:28 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq6018: Sort nodes properly
-
-Order nodes by unit address if one exists and alphabetically otherwise.
-
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230102094642.74254-4-konrad.dybcio@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 562 +++++++++++++-------------
- 1 file changed, 281 insertions(+), 281 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -87,6 +87,12 @@
- };
- };
-
-+ firmware {
-+ scm {
-+ compatible = "qcom,scm-ipq6018", "qcom,scm";
-+ };
-+ };
-+
- cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
- opp-shared;
-@@ -123,12 +129,6 @@
- };
- };
-
-- firmware {
-- scm {
-- compatible = "qcom,scm-ipq6018", "qcom,scm";
-- };
-- };
--
- pmuv8: pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
-@@ -166,6 +166,28 @@
- };
- };
-
-+ rpm-glink {
-+ compatible = "qcom,glink-rpm";
-+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
-+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
-+ mboxes = <&apcs_glb 0>;
-+
-+ rpm_requests: glink-channel {
-+ compatible = "qcom,rpm-ipq6018";
-+ qcom,glink-channels = "rpm_requests";
-+
-+ regulators {
-+ compatible = "qcom,rpm-mp5496-regulators";
-+
-+ ipq6018_s2: s2 {
-+ regulator-min-microvolt = <725000>;
-+ regulator-max-microvolt = <1062500>;
-+ regulator-always-on;
-+ };
-+ };
-+ };
-+ };
-+
- smem {
- compatible = "qcom,smem";
- memory-region = <&smem_region>;
-@@ -179,6 +201,102 @@
- dma-ranges;
- compatible = "simple-bus";
-
-+ qusb_phy_1: qusb@59000 {
-+ compatible = "qcom,ipq6018-qusb2-phy";
-+ reg = <0x0 0x00059000 0x0 0x180>;
-+ #phy-cells = <0>;
-+
-+ clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
-+ <&xo>;
-+ clock-names = "cfg_ahb", "ref";
-+
-+ resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
-+ status = "disabled";
-+ };
-+
-+ ssphy_0: ssphy@78000 {
-+ compatible = "qcom,ipq6018-qmp-usb3-phy";
-+ reg = <0x0 0x00078000 0x0 0x1c4>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ clocks = <&gcc GCC_USB0_AUX_CLK>,
-+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
-+ clock-names = "aux", "cfg_ahb", "ref";
-+
-+ resets = <&gcc GCC_USB0_PHY_BCR>,
-+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
-+ reset-names = "phy","common";
-+ status = "disabled";
-+
-+ usb0_ssphy: phy@78200 {
-+ reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
-+ <0x0 0x00078400 0x0 0x200>, /* Rx */
-+ <0x0 0x00078800 0x0 0x1f8>, /* PCS */
-+ <0x0 0x00078600 0x0 0x044>; /* PCS misc */
-+ #phy-cells = <0>;
-+ #clock-cells = <0>;
-+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
-+ clock-names = "pipe0";
-+ clock-output-names = "gcc_usb0_pipe_clk_src";
-+ };
-+ };
-+
-+ qusb_phy_0: qusb@79000 {
-+ compatible = "qcom,ipq6018-qusb2-phy";
-+ reg = <0x0 0x00079000 0x0 0x180>;
-+ #phy-cells = <0>;
-+
-+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
-+ <&xo>;
-+ clock-names = "cfg_ahb", "ref";
-+
-+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
-+ status = "disabled";
-+ };
-+
-+ pcie_phy: phy@84000 {
-+ compatible = "qcom,ipq6018-qmp-pcie-phy";
-+ reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
-+ status = "disabled";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
-+ <&gcc GCC_PCIE0_AHB_CLK>;
-+ clock-names = "aux", "cfg_ahb";
-+
-+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
-+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
-+ reset-names = "phy",
-+ "common";
-+
-+ pcie_phy0: phy@84200 {
-+ reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
-+ <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
-+ <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
-+ <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
-+ #phy-cells = <0>;
-+
-+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-+ clock-names = "pipe0";
-+ clock-output-names = "gcc_pcie0_pipe_clk_src";
-+ #clock-cells = <0>;
-+ };
-+ };
-+
-+ mdio: mdio@90000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
-+ reg = <0x0 0x00090000 0x0 0x64>;
-+ clocks = <&gcc GCC_MDIO_AHB_CLK>;
-+ clock-names = "gcc_mdio_ahb_clk";
-+ status = "disabled";
-+ };
-+
- prng: qrng@e1000 {
- compatible = "qcom,prng-ee";
- reg = <0x0 0x000e3000 0x0 0x1000>;
-@@ -257,6 +375,41 @@
- reg = <0x0 0x01937000 0x0 0x21000>;
- };
-
-+ usb2: usb@70f8800 {
-+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-+ reg = <0x0 0x070F8800 0x0 0x400>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+ clocks = <&gcc GCC_USB1_MASTER_CLK>,
-+ <&gcc GCC_USB1_SLEEP_CLK>,
-+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
-+ clock-names = "core",
-+ "sleep",
-+ "mock_utmi";
-+
-+ assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
-+ <&gcc GCC_USB1_MOCK_UTMI_CLK>;
-+ assigned-clock-rates = <133330000>,
-+ <24000000>;
-+ resets = <&gcc GCC_USB1_BCR>;
-+ status = "disabled";
-+
-+ dwc_1: usb@7000000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x07000000 0x0 0xcd00>;
-+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
-+ phys = <&qusb_phy_1>;
-+ phy-names = "usb2-phy";
-+ tx-fifo-resize;
-+ snps,is-utmi-l1-suspend;
-+ snps,hird-threshold = /bits/ 8 <0x0>;
-+ snps,dis_u2_susphy_quirk;
-+ snps,dis_u3_susphy_quirk;
-+ dr_mode = "host";
-+ };
-+ };
-+
- blsp_dma: dma-controller@7884000 {
- compatible = "qcom,bam-v1.7.0";
- reg = <0x0 0x07884000 0x0 0x2b000>;
-@@ -366,6 +519,49 @@
- status = "disabled";
- };
-
-+ usb3: usb@8af8800 {
-+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-+ reg = <0x0 0x08af8800 0x0 0x400>;
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
-+ <&gcc GCC_USB0_MASTER_CLK>,
-+ <&gcc GCC_USB0_SLEEP_CLK>,
-+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-+ clock-names = "cfg_noc",
-+ "core",
-+ "sleep",
-+ "mock_utmi";
-+
-+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
-+ <&gcc GCC_USB0_MASTER_CLK>,
-+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-+ assigned-clock-rates = <133330000>,
-+ <133330000>,
-+ <24000000>;
-+
-+ resets = <&gcc GCC_USB0_BCR>;
-+ status = "disabled";
-+
-+ dwc_0: usb@8a00000 {
-+ compatible = "snps,dwc3";
-+ reg = <0x0 0x08a00000 0x0 0xcd00>;
-+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
-+ phy-names = "usb2-phy", "usb3-phy";
-+ clocks = <&xo>;
-+ clock-names = "ref";
-+ tx-fifo-resize;
-+ snps,is-utmi-l1-suspend;
-+ snps,hird-threshold = /bits/ 8 <0x0>;
-+ snps,dis_u2_susphy_quirk;
-+ snps,dis_u3_susphy_quirk;
-+ dr_mode = "host";
-+ };
-+ };
-+
- intc: interrupt-controller@b000000 {
- compatible = "qcom,msm-qgic2";
- #address-cells = <2>;
-@@ -386,105 +582,6 @@
- };
- };
-
-- pcie_phy: phy@84000 {
-- compatible = "qcom,ipq6018-qmp-pcie-phy";
-- reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
-- status = "disabled";
-- #address-cells = <2>;
-- #size-cells = <2>;
-- ranges;
--
-- clocks = <&gcc GCC_PCIE0_AUX_CLK>,
-- <&gcc GCC_PCIE0_AHB_CLK>;
-- clock-names = "aux", "cfg_ahb";
--
-- resets = <&gcc GCC_PCIE0_PHY_BCR>,
-- <&gcc GCC_PCIE0PHY_PHY_BCR>;
-- reset-names = "phy",
-- "common";
--
-- pcie_phy0: phy@84200 {
-- reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
-- <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
-- <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
-- <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
-- #phy-cells = <0>;
--
-- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
-- clock-names = "pipe0";
-- clock-output-names = "gcc_pcie0_pipe_clk_src";
-- #clock-cells = <0>;
-- };
-- };
--
-- pcie0: pci@20000000 {
-- compatible = "qcom,pcie-ipq6018";
-- reg = <0x0 0x20000000 0x0 0xf1d>,
-- <0x0 0x20000f20 0x0 0xa8>,
-- <0x0 0x20001000 0x0 0x1000>,
-- <0x0 0x80000 0x0 0x4000>,
-- <0x0 0x20100000 0x0 0x1000>;
-- reg-names = "dbi", "elbi", "atu", "parf", "config";
--
-- device_type = "pci";
-- linux,pci-domain = <0>;
-- bus-range = <0x00 0xff>;
-- num-lanes = <1>;
-- max-link-speed = <3>;
-- #address-cells = <3>;
-- #size-cells = <2>;
--
-- phys = <&pcie_phy0>;
-- phy-names = "pciephy";
--
-- ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
-- <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
--
-- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-- interrupt-names = "msi";
--
-- #interrupt-cells = <1>;
-- interrupt-map-mask = <0 0 0 0x7>;
-- interrupt-map = <0 0 0 1 &intc 0 75
-- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-- <0 0 0 2 &intc 0 78
-- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-- <0 0 0 3 &intc 0 79
-- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-- <0 0 0 4 &intc 0 83
-- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
--
-- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
-- <&gcc GCC_PCIE0_AXI_M_CLK>,
-- <&gcc GCC_PCIE0_AXI_S_CLK>,
-- <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
-- <&gcc PCIE0_RCHNG_CLK>;
-- clock-names = "iface",
-- "axi_m",
-- "axi_s",
-- "axi_bridge",
-- "rchng";
--
-- resets = <&gcc GCC_PCIE0_PIPE_ARES>,
-- <&gcc GCC_PCIE0_SLEEP_ARES>,
-- <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
-- <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
-- <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
-- <&gcc GCC_PCIE0_AHB_ARES>,
-- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
-- <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
-- reset-names = "pipe",
-- "sleep",
-- "sticky",
-- "axi_m",
-- "axi_s",
-- "ahb",
-- "axi_m_sticky",
-- "axi_s_sticky";
--
-- status = "disabled";
-- };
--
- watchdog@b017000 {
- compatible = "qcom,kpss-wdt";
- interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
-@@ -617,147 +714,74 @@
- };
- };
-
-- mdio: mdio@90000 {
-- #address-cells = <1>;
-- #size-cells = <0>;
-- compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
-- reg = <0x0 0x00090000 0x0 0x64>;
-- clocks = <&gcc GCC_MDIO_AHB_CLK>;
-- clock-names = "gcc_mdio_ahb_clk";
-- status = "disabled";
-- };
--
-- qusb_phy_1: qusb@59000 {
-- compatible = "qcom,ipq6018-qusb2-phy";
-- reg = <0x0 0x00059000 0x0 0x180>;
-- #phy-cells = <0>;
--
-- clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
-- <&xo>;
-- clock-names = "cfg_ahb", "ref";
--
-- resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
-- status = "disabled";
-- };
--
-- usb2: usb@70f8800 {
-- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-- reg = <0x0 0x070F8800 0x0 0x400>;
-- #address-cells = <2>;
-- #size-cells = <2>;
-- ranges;
-- clocks = <&gcc GCC_USB1_MASTER_CLK>,
-- <&gcc GCC_USB1_SLEEP_CLK>,
-- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
-- clock-names = "core",
-- "sleep",
-- "mock_utmi";
--
-- assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
-- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
-- assigned-clock-rates = <133330000>,
-- <24000000>;
-- resets = <&gcc GCC_USB1_BCR>;
-- status = "disabled";
--
-- dwc_1: usb@7000000 {
-- compatible = "snps,dwc3";
-- reg = <0x0 0x07000000 0x0 0xcd00>;
-- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
-- phys = <&qusb_phy_1>;
-- phy-names = "usb2-phy";
-- tx-fifo-resize;
-- snps,is-utmi-l1-suspend;
-- snps,hird-threshold = /bits/ 8 <0x0>;
-- snps,dis_u2_susphy_quirk;
-- snps,dis_u3_susphy_quirk;
-- dr_mode = "host";
-- };
-- };
-+ pcie0: pci@20000000 {
-+ compatible = "qcom,pcie-ipq6018";
-+ reg = <0x0 0x20000000 0x0 0xf1d>,
-+ <0x0 0x20000f20 0x0 0xa8>,
-+ <0x0 0x20001000 0x0 0x1000>,
-+ <0x0 0x80000 0x0 0x4000>,
-+ <0x0 0x20100000 0x0 0x1000>;
-+ reg-names = "dbi", "elbi", "atu", "parf", "config";
-
-- ssphy_0: ssphy@78000 {
-- compatible = "qcom,ipq6018-qmp-usb3-phy";
-- reg = <0x0 0x00078000 0x0 0x1c4>;
-- #address-cells = <2>;
-+ device_type = "pci";
-+ linux,pci-domain = <0>;
-+ bus-range = <0x00 0xff>;
-+ num-lanes = <1>;
-+ max-link-speed = <3>;
-+ #address-cells = <3>;
- #size-cells = <2>;
-- ranges;
--
-- clocks = <&gcc GCC_USB0_AUX_CLK>,
-- <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
-- clock-names = "aux", "cfg_ahb", "ref";
--
-- resets = <&gcc GCC_USB0_PHY_BCR>,
-- <&gcc GCC_USB3PHY_0_PHY_BCR>;
-- reset-names = "phy","common";
-- status = "disabled";
--
-- usb0_ssphy: phy@78200 {
-- reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
-- <0x0 0x00078400 0x0 0x200>, /* Rx */
-- <0x0 0x00078800 0x0 0x1f8>, /* PCS */
-- <0x0 0x00078600 0x0 0x044>; /* PCS misc */
-- #phy-cells = <0>;
-- #clock-cells = <0>;
-- clocks = <&gcc GCC_USB0_PIPE_CLK>;
-- clock-names = "pipe0";
-- clock-output-names = "gcc_usb0_pipe_clk_src";
-- };
-- };
-
-- qusb_phy_0: qusb@79000 {
-- compatible = "qcom,ipq6018-qusb2-phy";
-- reg = <0x0 0x00079000 0x0 0x180>;
-- #phy-cells = <0>;
-+ phys = <&pcie_phy0>;
-+ phy-names = "pciephy";
-
-- clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
-- <&xo>;
-- clock-names = "cfg_ahb", "ref";
-+ ranges = <0x81000000 0 0x20200000 0 0x20200000
-+ 0 0x10000>, /* downstream I/O */
-+ <0x82000000 0 0x20220000 0 0x20220000
-+ 0 0xfde0000>; /* non-prefetchable memory */
-
-- resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
-- status = "disabled";
-- };
-+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "msi";
-
-- usb3: usb@8af8800 {
-- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-- reg = <0x0 0x8af8800 0x0 0x400>;
-- #address-cells = <2>;
-- #size-cells = <2>;
-- ranges;
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0 0 0 0x7>;
-+ interrupt-map = <0 0 0 1 &intc 0 75
-+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-+ <0 0 0 2 &intc 0 78
-+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-+ <0 0 0 3 &intc 0 79
-+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-+ <0 0 0 4 &intc 0 83
-+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-
-- clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
-- <&gcc GCC_USB0_MASTER_CLK>,
-- <&gcc GCC_USB0_SLEEP_CLK>,
-- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-- clock-names = "cfg_noc",
-- "core",
-- "sleep",
-- "mock_utmi";
-+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
-+ <&gcc GCC_PCIE0_AXI_M_CLK>,
-+ <&gcc GCC_PCIE0_AXI_S_CLK>,
-+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
-+ <&gcc PCIE0_RCHNG_CLK>;
-+ clock-names = "iface",
-+ "axi_m",
-+ "axi_s",
-+ "axi_bridge",
-+ "rchng";
-
-- assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
-- <&gcc GCC_USB0_MASTER_CLK>,
-- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-- assigned-clock-rates = <133330000>,
-- <133330000>,
-- <24000000>;
-+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
-+ <&gcc GCC_PCIE0_SLEEP_ARES>,
-+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
-+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
-+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
-+ <&gcc GCC_PCIE0_AHB_ARES>,
-+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
-+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
-+ reset-names = "pipe",
-+ "sleep",
-+ "sticky",
-+ "axi_m",
-+ "axi_s",
-+ "ahb",
-+ "axi_m_sticky",
-+ "axi_s_sticky";
-
-- resets = <&gcc GCC_USB0_BCR>;
- status = "disabled";
--
-- dwc_0: usb@8a00000 {
-- compatible = "snps,dwc3";
-- reg = <0x0 0x8a00000 0x0 0xcd00>;
-- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-- phys = <&qusb_phy_0>, <&usb0_ssphy>;
-- phy-names = "usb2-phy", "usb3-phy";
-- clocks = <&xo>;
-- clock-names = "ref";
-- tx-fifo-resize;
-- snps,is-utmi-l1-suspend;
-- snps,hird-threshold = /bits/ 8 <0x0>;
-- snps,dis_u2_susphy_quirk;
-- snps,dis_u3_susphy_quirk;
-- dr_mode = "host";
-- };
- };
- };
-
-@@ -792,26 +816,4 @@
- #interrupt-cells = <2>;
- };
- };
--
-- rpm-glink {
-- compatible = "qcom,glink-rpm";
-- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
-- qcom,rpm-msg-ram = <&rpm_msg_ram>;
-- mboxes = <&apcs_glb 0>;
--
-- rpm_requests: glink-channel {
-- compatible = "qcom,rpm-ipq6018";
-- qcom,glink-channels = "rpm_requests";
--
-- regulators {
-- compatible = "qcom,rpm-mp5496-regulators";
--
-- ipq6018_s2: s2 {
-- regulator-min-microvolt = <725000>;
-- regulator-max-microvolt = <1062500>;
-- regulator-always-on;
-- };
-- };
-- };
-- };
- };
+++ /dev/null
-From 6db9ed9a128cbae1423d043f3debd8bfa77783fd Mon Sep 17 00:00:00 2001
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-Date: Mon, 2 Jan 2023 10:46:29 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq6018: Add/remove some newlines
-
-Some lines were broken very aggresively, presumably to fit under 80 chars
-and some places could have used a newline, particularly between subsequent
-nodes. Address all that and remove redundant comments near PCIe ranges
-while at it so as not to exceed 100 chars needlessly.
-
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++--------------
- 1 file changed, 12 insertions(+), 14 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -102,26 +102,31 @@
- opp-microvolt = <725000>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1056000000 {
- opp-hz = /bits/ 64 <1056000000>;
- opp-microvolt = <787500>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1320000000 {
- opp-hz = /bits/ 64 <1320000000>;
- opp-microvolt = <862500>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1440000000 {
- opp-hz = /bits/ 64 <1440000000>;
- opp-microvolt = <925000>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <987500>;
- clock-latency-ns = <200000>;
- };
-+
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1062500>;
-@@ -131,8 +136,7 @@
-
- pmuv8: pmu {
- compatible = "arm,cortex-a53-pmu";
-- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
-- IRQ_TYPE_LEVEL_HIGH)>;
-+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- psci: psci {
-@@ -734,24 +738,18 @@
- phys = <&pcie_phy0>;
- phy-names = "pciephy";
-
-- ranges = <0x81000000 0 0x20200000 0 0x20200000
-- 0 0x10000>, /* downstream I/O */
-- <0x82000000 0 0x20220000 0 0x20220000
-- 0 0xfde0000>; /* non-prefetchable memory */
-+ ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
-+ <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
-
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
-- interrupt-map = <0 0 0 1 &intc 0 75
-- IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-- <0 0 0 2 &intc 0 78
-- IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-- <0 0 0 3 &intc 0 79
-- IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-- <0 0 0 4 &intc 0 83
-- IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-+ interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-+ <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
-+ <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
-+ <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
-
- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
- <&gcc GCC_PCIE0_AXI_M_CLK>,
+++ /dev/null
-From 7356ae3e10abd1d71f06ff0b8a8e72aa7c955c57 Mon Sep 17 00:00:00 2001
-From: Konrad Dybcio <konrad.dybcio@linaro.org>
-Date: Mon, 2 Jan 2023 10:46:30 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq6018: Use lowercase hex
-
-One value escaped my previous lowercase hexification. Take care of it.
-
-Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230102094642.74254-6-konrad.dybcio@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -381,7 +381,7 @@
-
- usb2: usb@70f8800 {
- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
-- reg = <0x0 0x070F8800 0x0 0x400>;
-+ reg = <0x0 0x070f8800 0x0 0x400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+++ /dev/null
-From 679ee73bbee28cab441008f8cca38160cc8f3d05 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 8 Feb 2023 11:15:39 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq6018: align RPM G-Link node with
- bindings
-
-Bindings expect (and most of DTS use) the RPM G-Link node name to be
-"rpm-requests".
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230208101545.45711-1-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -176,7 +176,7 @@
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
- mboxes = <&apcs_glb 0>;
-
-- rpm_requests: glink-channel {
-+ rpm_requests: rpm-requests {
- compatible = "qcom,rpm-ipq6018";
- qcom,glink-channels = "rpm_requests";
-
+++ /dev/null
-From afa8eb675fc6dd606783ed2350de90927d6fb9d3 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 8 Mar 2023 13:59:01 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq6018-cp01-c1: drop SPI cs-select
-
-The SPI controller nodes do not use/allow cs-select property:
-
- ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('cs-select' was unexpected)
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230308125906.236885-6-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
-@@ -36,7 +36,6 @@
- };
-
- &blsp1_spi1 {
-- cs-select = <0>;
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
+++ /dev/null
-From 0cd4e90cb2dec02ff859f5c98f744f43a23aea65 Mon Sep 17 00:00:00 2001
-From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
-Date: Fri, 26 May 2023 16:36:53 +0530
-Subject: [PATCH] arm64: dts: qcom: add few more reserved memory region
-
-In IPQ SoCs, bootloader will collect the system RAM contents upon crash
-for the post morterm analysis. If we don't reserve the memory region used
-by bootloader, obviously linux will consume it and upon next boot on
-crash, bootloader will be loaded in the same region, which will lead to
-loose some of the data, sometimes we may miss out critical information.
-So lets reserve the region used by the bootloader.
-
-Similarly SBL copies some data into the reserved region and it will be
-used in the crash scenario. So reserve 1MB for SBL as well.
-
-While at it, drop the size padding in the reserved memory region,
-wherever applicable.
-
-Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230526110653.27777-4-quic_viswanat@quicinc.com
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++---
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++--
- 2 files changed, 25 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -154,18 +154,28 @@
- no-map;
- };
-
-+ bootloader@4a100000 {
-+ reg = <0x0 0x4a100000 0x0 0x400000>;
-+ no-map;
-+ };
-+
-+ sbl@4a500000 {
-+ reg = <0x0 0x4a500000 0x0 0x100000>;
-+ no-map;
-+ };
-+
- tz: memory@4a600000 {
-- reg = <0x0 0x4a600000 0x0 0x00400000>;
-+ reg = <0x0 0x4a600000 0x0 0x400000>;
- no-map;
- };
-
- smem_region: memory@4aa00000 {
-- reg = <0x0 0x4aa00000 0x0 0x00100000>;
-+ reg = <0x0 0x4aa00000 0x0 0x100000>;
- no-map;
- };
-
- q6_region: memory@4ab00000 {
-- reg = <0x0 0x4ab00000 0x0 0x05500000>;
-+ reg = <0x0 0x4ab00000 0x0 0x5500000>;
- no-map;
- };
- };
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -85,17 +85,27 @@
- #size-cells = <2>;
- ranges;
-
-+ bootloader@4a600000 {
-+ reg = <0x0 0x4a600000 0x0 0x400000>;
-+ no-map;
-+ };
-+
-+ sbl@4aa00000 {
-+ reg = <0x0 0x4aa00000 0x0 0x100000>;
-+ no-map;
-+ };
-+
- smem@4ab00000 {
- compatible = "qcom,smem";
-- reg = <0x0 0x4ab00000 0x0 0x00100000>;
-+ reg = <0x0 0x4ab00000 0x0 0x100000>;
- no-map;
-
- hwlocks = <&tcsr_mutex 3>;
- };
-
- memory@4ac00000 {
-+ reg = <0x0 0x4ac00000 0x0 0x400000>;
- no-map;
-- reg = <0x0 0x4ac00000 0x0 0x00400000>;
- };
- };
-
+++ /dev/null
-From 9b2406aaba7841863ac041225316c1ec1c86ea36 Mon Sep 17 00:00:00 2001
-From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
-Date: Fri, 26 May 2023 16:36:52 +0530
-Subject: [PATCH] arm64: dts: qcom: enable the download mode support
-
-Like any other Qualcomm SoCs, IPQ8074 and IPQ6018 also supports the
-download mode to collect the RAM dumps if system crashes, to perform
-the post mortem analysis. Add support for the same.
-
-Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230526110653.27777-3-quic_viswanat@quicinc.com
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++
- 2 files changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -90,6 +90,7 @@
- firmware {
- scm {
- compatible = "qcom,scm-ipq6018", "qcom,scm";
-+ qcom,dload-mode = <&tcsr 0x6100>;
- };
- };
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -112,6 +112,7 @@
- firmware {
- scm {
- compatible = "qcom,scm-ipq8074", "qcom,scm";
-+ qcom,dload-mode = <&tcsr 0x6100>;
- };
- };
-
-@@ -386,6 +387,11 @@
- #hwlock-cells = <1>;
- };
-
-+ tcsr: syscon@1937000 {
-+ compatible = "qcom,tcsr-ipq8074", "syscon";
-+ reg = <0x01937000 0x21000>;
-+ };
-+
- spmi_bus: spmi@200f000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0x0200f000 0x001000>,
+++ /dev/null
-From 085058786a7890dd44ec623fe5ac74db870f6b93 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 19 Apr 2023 23:18:39 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: correct qrng unit address
-
-Match unit-address to reg entry to fix dtbs W=1 warnings:
-
- Warning (simple_bus_reg): /soc/qrng@e1000: simple-bus unit address format error, expected "e3000"
-
-Fixes: 5bf635621245 ("arm64: dts: ipq6018: Add a few device nodes")
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230419211856.79332-1-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -312,7 +312,7 @@
- status = "disabled";
- };
-
-- prng: qrng@e1000 {
-+ prng: qrng@e3000 {
- compatible = "qcom,prng-ee";
- reg = <0x0 0x000e3000 0x0 0x1000>;
- clocks = <&gcc GCC_PRNG_AHB_CLK>;
+++ /dev/null
-From 393595d4ffbd0a1fafd5548f8de1b8487a037cf2 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Thu, 20 Apr 2023 08:36:04 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add unit address to soc node
-
-"soc" node is supposed to have unit address:
-
- Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230420063610.11068-1-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -209,7 +209,7 @@
- hwlocks = <&tcsr_mutex 3>;
- };
-
-- soc: soc {
-+ soc: soc@0 {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0 0 0 0 0x0 0xffffffff>;
+++ /dev/null
-From 546f0617a22a481f3ca1f7e058aea0c40517c64e Mon Sep 17 00:00:00 2001
-From: Kathiravan T <quic_kathirav@quicinc.com>
-Date: Fri, 26 May 2023 18:23:04 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add QFPROM node
-
-IPQ6018 has efuse region to determine the various HW quirks. Lets
-add the initial support and the individual fuses will be added as they
-are required.
-
-Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230526125305.19626-4-quic_kathirav@quicinc.com
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -312,6 +312,13 @@
- status = "disabled";
- };
-
-+ qfprom: efuse@a4000 {
-+ compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
-+ reg = <0x0 0x000a4000 0x0 0x2000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ };
-+
- prng: qrng@e3000 {
- compatible = "qcom,prng-ee";
- reg = <0x0 0x000e3000 0x0 0x1000>;
+++ /dev/null
-From b8420d478aa3fc739fcdba6b4b945850b356cb3b Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Sun, 16 Apr 2023 14:37:25 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: drop incorrect SPI bus
- spi-max-frequency
-
-The spi-max-frequency property belongs to SPI devices, not SPI
-controller:
-
- ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230416123730.300863-1-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -458,7 +458,6 @@
- #size-cells = <0>;
- reg = <0x0 0x078b5000 0x0 0x600>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-- spi-max-frequency = <50000000>;
- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
-@@ -473,7 +472,6 @@
- #size-cells = <0>;
- reg = <0x0 0x078b6000 0x0 0x600>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-- spi-max-frequency = <50000000>;
- clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
+++ /dev/null
-From e6e0e706940b64e3a77e0a4840037692f109bd5f Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Sun, 16 Apr 2023 14:37:26 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: drop incorrect SPI bus
- spi-max-frequency
-
-The spi-max-frequency property belongs to SPI devices, not SPI
-controller:
-
- ipq8074-hk01.dtb: spi@78b5000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected)
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230416123730.300863-2-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -487,7 +487,6 @@
- #size-cells = <0>;
- reg = <0x078b5000 0x600>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-- spi-max-frequency = <50000000>;
- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
+++ /dev/null
-From 56e5ae0116aef87273cf1812d608645b076e4f02 Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Tue, 25 Apr 2023 12:11:49 +0300
-Subject: [PATCH] clk: qcom: gcc-ipq6018: Use floor ops for sdcc clocks
-
-SDCC clocks must be rounded down to avoid overclocking the controller.
-
-Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support")
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/1682413909-24927-1-git-send-email-mantas@8devices.com
----
- drivers/clk/qcom/gcc-ipq6018.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/gcc-ipq6018.c
-+++ b/drivers/clk/qcom/gcc-ipq6018.c
-@@ -1702,7 +1702,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
- .name = "usb0_mock_utmi_clk_src",
- .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
- .num_parents = 4,
-- .ops = &clk_rcg2_ops,
-+ .ops = &clk_rcg2_floor_ops,
- },
- };
-
+++ /dev/null
-From 923f7d678b2ae3d522543058514d5605c185633b Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Mon, 17 Apr 2023 19:44:07 +0200
-Subject: [PATCH] clk: qcom: gcc-ipq6018: drop redundant F define
-
-The same exact F frequency table entry is defined in clk-rcg.h
-Drop the redundant define to cleanup code.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230417174408.23722-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/gcc-ipq6018.c | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq6018.c
-+++ b/drivers/clk/qcom/gcc-ipq6018.c
-@@ -26,8 +26,6 @@
- #include "clk-regmap-mux.h"
- #include "reset.h"
-
--#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
--
- enum {
- P_XO,
- P_BIAS_PLL,
+++ /dev/null
-From f4f0c8acee0e41c5fbae7a7ad06087668ddce0d6 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 26 May 2023 21:08:54 +0200
-Subject: [PATCH] clk: qcom: gcc-ipq6018: update UBI32 PLL
-
-Update the UBI32 alpha PLL config to the latest values from the downstream
-QCA 5.4 kernel.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230526190855.2941291-1-robimarko@gmail.com
----
- drivers/clk/qcom/gcc-ipq6018.c | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/gcc-ipq6018.c
-+++ b/drivers/clk/qcom/gcc-ipq6018.c
-@@ -4143,15 +4143,20 @@ static struct clk_branch gcc_dcc_clk = {
-
- static const struct alpha_pll_config ubi32_pll_config = {
- .l = 0x3e,
-- .alpha = 0x57,
-+ .alpha = 0x6667,
- .config_ctl_val = 0x240d6aa8,
- .config_ctl_hi_val = 0x3c2,
-+ .config_ctl_val = 0x240d4828,
-+ .config_ctl_hi_val = 0x6,
- .main_output_mask = BIT(0),
- .aux_output_mask = BIT(1),
- .pre_div_val = 0x0,
- .pre_div_mask = BIT(12),
- .post_div_val = 0x0,
- .post_div_mask = GENMASK(9, 8),
-+ .alpha_en_mask = BIT(24),
-+ .test_ctl_val = 0x1C0000C0,
-+ .test_ctl_hi_val = 0x4000,
- };
-
- static const struct alpha_pll_config nss_crypto_pll_config = {
+++ /dev/null
-From 5ae7899765607e97e5eb34486336898c8d9ec654 Mon Sep 17 00:00:00 2001
-From: Arnd Bergmann <arnd@arndb.de>
-Date: Thu, 1 Jun 2023 23:34:12 +0200
-Subject: [PATCH] clk: qcom: gcc-ipq6018: remove duplicate initializers
-
-A recent change added new initializers for .config_ctl_val and
-.config_ctl_hi_val but left the old values in place:
-
-drivers/clk/qcom/gcc-ipq6018.c:4155:27: error: initialized field overwritten [-Werror=override-init]
- 4155 | .config_ctl_val = 0x240d4828,
- | ^~~~~~~~~~
-drivers/clk/qcom/gcc-ipq6018.c:4156:30: error: initialized field overwritten [-Werror=override-init]
- 4156 | .config_ctl_hi_val = 0x6,
- | ^~~
-
-Remove the unused ones now to avoid confusion.
-
-Fixes: f4f0c8acee0e4 ("clk: qcom: gcc-ipq6018: update UBI32 PLL")
-Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-Reviewed-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230601213416.3373599-1-arnd@kernel.org
----
- drivers/clk/qcom/gcc-ipq6018.c | 2 --
- 1 file changed, 2 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq6018.c
-+++ b/drivers/clk/qcom/gcc-ipq6018.c
-@@ -4144,8 +4144,6 @@ static struct clk_branch gcc_dcc_clk = {
- static const struct alpha_pll_config ubi32_pll_config = {
- .l = 0x3e,
- .alpha = 0x6667,
-- .config_ctl_val = 0x240d6aa8,
-- .config_ctl_hi_val = 0x3c2,
- .config_ctl_val = 0x240d4828,
- .config_ctl_hi_val = 0x6,
- .main_output_mask = BIT(0),
+++ /dev/null
-From 8ddfa81d090c71fd6cb3cb8ca1d420c0da33a575 Mon Sep 17 00:00:00 2001
-From: Stephan Gerhold <stephan@gerhold.net>
-Date: Thu, 15 Jun 2023 18:50:42 +0200
-Subject: [PATCH] soc: qcom: Add RPM processor/subsystem driver
-
-Add a simple driver for the qcom,rpm-proc compatible that registers the
-"smd-edge" and populates other children defined in the device tree.
-
-Note that the DT schema belongs to the remoteproc subsystem while this
-driver is added inside soc/qcom. I argue that the RPM *is* a remoteproc,
-but as an implementation detail in Linux it can currently not benefit
-from anything provided by the remoteproc subsystem. The RPM firmware is
-usually already loaded and started by earlier components in the boot
-chain and is not meant to be ever restarted.
-
-To avoid breaking existing kernel configurations the driver is always
-built when smd-rpm.c is also built. They belong closely together anyway.
-To avoid build errors CONFIG_RPMSG_QCOM_SMD must be also built-in if
-rpm-proc is.
-
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
-Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-9-a07dcdefd918@gerhold.net
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- drivers/soc/qcom/Kconfig | 1 +
- drivers/soc/qcom/Makefile | 2 +-
- drivers/soc/qcom/rpm-proc.c | 77 +++++++++++++++++++++++++++++++++++++
- 3 files changed, 79 insertions(+), 1 deletion(-)
- create mode 100644 drivers/soc/qcom/rpm-proc.c
-
---- a/drivers/soc/qcom/Kconfig
-+++ b/drivers/soc/qcom/Kconfig
-@@ -153,6 +153,7 @@ config QCOM_SMD_RPM
- tristate "Qualcomm Resource Power Manager (RPM) over SMD"
- depends on ARCH_QCOM || COMPILE_TEST
- depends on RPMSG
-+ depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
- help
- If you say yes to this option, support will be included for the
- Resource Power Manager system found in the Qualcomm 8974 based
---- a/drivers/soc/qcom/Makefile
-+++ b/drivers/soc/qcom/Makefile
-@@ -14,7 +14,7 @@ obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_me
- obj-$(CONFIG_QCOM_RPMH) += qcom_rpmh.o
- qcom_rpmh-y += rpmh-rsc.o
- qcom_rpmh-y += rpmh.o
--obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o
-+obj-$(CONFIG_QCOM_SMD_RPM) += rpm-proc.o smd-rpm.o
- obj-$(CONFIG_QCOM_SMEM) += smem.o
- obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o
- obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
---- /dev/null
-+++ b/drivers/soc/qcom/rpm-proc.c
-@@ -0,0 +1,77 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/* Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> */
-+
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+#include <linux/rpmsg/qcom_smd.h>
-+
-+static int rpm_proc_probe(struct platform_device *pdev)
-+{
-+ struct qcom_smd_edge *edge = NULL;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *edge_node;
-+ int ret;
-+
-+ edge_node = of_get_child_by_name(dev->of_node, "smd-edge");
-+ if (edge_node) {
-+ edge = qcom_smd_register_edge(dev, edge_node);
-+ of_node_put(edge_node);
-+ if (IS_ERR(edge))
-+ return dev_err_probe(dev, PTR_ERR(edge),
-+ "Failed to register smd-edge\n");
-+ }
-+
-+ ret = devm_of_platform_populate(dev);
-+ if (ret) {
-+ dev_err(dev, "Failed to populate child devices: %d\n", ret);
-+ goto err;
-+ }
-+
-+ platform_set_drvdata(pdev, edge);
-+ return 0;
-+err:
-+ if (edge)
-+ qcom_smd_unregister_edge(edge);
-+ return ret;
-+}
-+
-+static void rpm_proc_remove(struct platform_device *pdev)
-+{
-+ struct qcom_smd_edge *edge = platform_get_drvdata(pdev);
-+
-+ if (edge)
-+ qcom_smd_unregister_edge(edge);
-+}
-+
-+static const struct of_device_id rpm_proc_of_match[] = {
-+ { .compatible = "qcom,rpm-proc", },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, rpm_proc_of_match);
-+
-+static struct platform_driver rpm_proc_driver = {
-+ .probe = rpm_proc_probe,
-+ .remove_new = rpm_proc_remove,
-+ .driver = {
-+ .name = "qcom-rpm-proc",
-+ .of_match_table = rpm_proc_of_match,
-+ },
-+};
-+
-+static int __init rpm_proc_init(void)
-+{
-+ return platform_driver_register(&rpm_proc_driver);
-+}
-+arch_initcall(rpm_proc_init);
-+
-+static void __exit rpm_proc_exit(void)
-+{
-+ platform_driver_unregister(&rpm_proc_driver);
-+}
-+module_exit(rpm_proc_exit);
-+
-+MODULE_DESCRIPTION("Qualcomm RPM processor/subsystem driver");
-+MODULE_AUTHOR("Stephan Gerhold <stephan@gerhold.net>");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 7e1acc8b92a3b67db1e5255adae2851d58d74434 Mon Sep 17 00:00:00 2001
-From: Stephan Gerhold <stephan@gerhold.net>
-Date: Thu, 15 Jun 2023 18:50:44 +0200
-Subject: [PATCH] arm64: dts: qcom: Add rpm-proc node for GLINK gplatforms
-
-Rather than having the RPM GLINK channels as the only child of a dummy
-top-level rpm-glink node, switch to representing the RPM as remoteproc
-like all the other remoteprocs (modem DSP, ...).
-
-This allows assigning additional subdevices to it like the MPM
-interrupt-controller or rpm-master-stats.
-
-Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # SM6375
-Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
-Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-11-a07dcdefd918@gerhold.net
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 ++++----
- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 28 +++--
- arch/arm64/boot/dts/qcom/msm8996.dtsi | 113 +++++++++----------
- arch/arm64/boot/dts/qcom/msm8998.dtsi | 102 ++++++++---------
- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 126 ++++++++++-----------
- arch/arm64/boot/dts/qcom/qcs404.dtsi | 152 +++++++++++++-------------
- arch/arm64/boot/dts/qcom/sdm630.dtsi | 132 +++++++++++-----------
- arch/arm64/boot/dts/qcom/sm6115.dtsi | 128 +++++++++++-----------
- arch/arm64/boot/dts/qcom/sm6125.dtsi | 140 ++++++++++++------------
- arch/arm64/boot/dts/qcom/sm6375.dtsi | 126 ++++++++++-----------
- 10 files changed, 566 insertions(+), 529 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -145,6 +145,32 @@
- method = "smc";
- };
-
-+ rpm: remoteproc {
-+ compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
-+
-+ glink-edge {
-+ compatible = "qcom,glink-rpm";
-+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
-+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
-+ mboxes = <&apcs_glb 0>;
-+
-+ rpm_requests: rpm-requests {
-+ compatible = "qcom,rpm-ipq6018";
-+ qcom,glink-channels = "rpm_requests";
-+
-+ regulators {
-+ compatible = "qcom,rpm-mp5496-regulators";
-+
-+ ipq6018_s2: s2 {
-+ regulator-min-microvolt = <725000>;
-+ regulator-max-microvolt = <1062500>;
-+ regulator-always-on;
-+ };
-+ };
-+ };
-+ };
-+ };
-+
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
-@@ -181,28 +207,6 @@
- };
- };
-
-- rpm-glink {
-- compatible = "qcom,glink-rpm";
-- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
-- qcom,rpm-msg-ram = <&rpm_msg_ram>;
-- mboxes = <&apcs_glb 0>;
--
-- rpm_requests: rpm-requests {
-- compatible = "qcom,rpm-ipq6018";
-- qcom,glink-channels = "rpm_requests";
--
-- regulators {
-- compatible = "qcom,rpm-mp5496-regulators";
--
-- ipq6018_s2: s2 {
-- regulator-min-microvolt = <725000>;
-- regulator-max-microvolt = <1062500>;
-- regulator-always-on;
-- };
-- };
-- };
-- };
--
- smem {
- compatible = "qcom,smem";
- memory-region = <&smem_region>;
+++ /dev/null
-From 0133c7af3aa0420778d106cb90db708cfa45f2c6 Mon Sep 17 00:00:00 2001
-From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
-Date: Thu, 14 Sep 2023 12:29:59 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock
- provider for mailbox
-
-While the kernel is booting up, APSS clock / CPU clock will be running
-at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
-APSS PLL will be configured to the rate based on the opp table and the
-source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
-consume the GPLL0, with this inclusion, CPU Freq correctly reports that
-CPU is running at 800MHz rather than 24MHz.
-
-Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-9-c8ceb1a37680@quicinc.com
-[bjorn: Updated commit message, as requested by Kathiravan]
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -618,8 +618,8 @@
- compatible = "qcom,ipq6018-apcs-apps-global";
- reg = <0x0 0x0b111000 0x0 0x1000>;
- #clock-cells = <1>;
-- clocks = <&a53pll>, <&xo>;
-- clock-names = "pll", "xo";
-+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
-+ clock-names = "pll", "xo", "gpll0";
- #mbox-cells = <1>;
- };
-
+++ /dev/null
-From 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 21 Oct 2023 13:55:18 +0200
-Subject: [PATCH] clk: qcom: gcc-ipq6018: add QUP6 I2C clock
-
-QUP6 I2C clock is listed in the dt bindings but it was never included in
-the GCC driver.
-So lets add support for it, it is marked as criticial as it is used by RPM
-to communicate to the external PMIC over I2C so this clock must not be
-disabled.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Link: https://lore.kernel.org/r/20231021115545.229060-1-robimarko@gmail.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq6018.c
-+++ b/drivers/clk/qcom/gcc-ipq6018.c
-@@ -2120,6 +2120,26 @@ static struct clk_branch gcc_blsp1_qup5_
- },
- };
-
-+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
-+ .halt_reg = 0x07010,
-+ .clkr = {
-+ .enable_reg = 0x07010,
-+ .enable_mask = BIT(0),
-+ .hw.init = &(struct clk_init_data){
-+ .name = "gcc_blsp1_qup6_i2c_apps_clk",
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
-+ .num_parents = 1,
-+ /*
-+ * RPM uses QUP6 I2C to communicate with the external
-+ * PMIC so it must not be disabled.
-+ */
-+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-+ .ops = &clk_branch2_ops,
-+ },
-+ },
-+};
-+
- static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
- .halt_reg = 0x0700c,
- .clkr = {
-@@ -4276,6 +4296,7 @@ static struct clk_regmap *gcc_ipq6018_cl
- [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
- [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
- [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
-+ [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
- [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
- [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
- [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+++ /dev/null
-From 83afcf14edb9217e58837eb119da96d734a4b3b1 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 21 Oct 2023 14:00:07 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM
-
-IPQ6018 comes in multiple SKU-s and some of them dont support all of the
-OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
-supported OPP-s based on the SoC dynamically.
-
-As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
-goes up to 1.5GHz and is marked as such via an eFuse.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Link: https://lore.kernel.org/r/20231021120048.231239-1-robimarko@gmail.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++-
- 1 file changed, 13 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -95,42 +95,49 @@
- };
-
- cpu_opp_table: opp-table-cpu {
-- compatible = "operating-points-v2";
-+ compatible = "operating-points-v2-kryo-cpu";
-+ nvmem-cells = <&cpu_speed_bin>;
- opp-shared;
-
- opp-864000000 {
- opp-hz = /bits/ 64 <864000000>;
- opp-microvolt = <725000>;
-+ opp-supported-hw = <0xf>;
- clock-latency-ns = <200000>;
- };
-
- opp-1056000000 {
- opp-hz = /bits/ 64 <1056000000>;
- opp-microvolt = <787500>;
-+ opp-supported-hw = <0xf>;
- clock-latency-ns = <200000>;
- };
-
- opp-1320000000 {
- opp-hz = /bits/ 64 <1320000000>;
- opp-microvolt = <862500>;
-+ opp-supported-hw = <0x3>;
- clock-latency-ns = <200000>;
- };
-
- opp-1440000000 {
- opp-hz = /bits/ 64 <1440000000>;
- opp-microvolt = <925000>;
-+ opp-supported-hw = <0x3>;
- clock-latency-ns = <200000>;
- };
-
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <987500>;
-+ opp-supported-hw = <0x1>;
- clock-latency-ns = <200000>;
- };
-
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1062500>;
-+ opp-supported-hw = <0x1>;
- clock-latency-ns = <200000>;
- };
- };
-@@ -321,6 +328,11 @@
- reg = <0x0 0x000a4000 0x0 0x2000>;
- #address-cells = <1>;
- #size-cells = <1>;
-+
-+ cpu_speed_bin: cpu-speed-bin@135 {
-+ reg = <0x135 0x1>;
-+ bits = <7 1>;
-+ };
- };
-
- prng: qrng@e3000 {
+++ /dev/null
-From e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Sun, 3 Dec 2023 23:39:14 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq6018: Add remaining QUP UART node
-
-Add node to support all the QUP UART node controller inside of IPQ6018.
-Some routers use these bus to connect Bluetooth chips.
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 50 +++++++++++++++++++++++++++
- 1 file changed, 50 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -458,6 +458,26 @@
- qcom,ee = <0>;
- };
-
-+ blsp1_uart1: serial@78af000 {
-+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+ reg = <0x0 0x78af000 0x0 0x200>;
-+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
-+ status = "disabled";
-+ };
-+
-+ blsp1_uart2: serial@78b0000 {
-+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+ reg = <0x0 0x78b0000 0x0 0x200>;
-+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
-+ status = "disabled";
-+ };
-+
- blsp1_uart3: serial@78b1000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0x0 0x078b1000 0x0 0x200>;
-@@ -466,6 +486,36 @@
- <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- status = "disabled";
-+ };
-+
-+ blsp1_uart4: serial@78b2000 {
-+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+ reg = <0x0 0x078b2000 0x0 0x200>;
-+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
-+ status = "disabled";
-+ };
-+
-+ blsp1_uart5: serial@78b3000 {
-+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+ reg = <0x0 0x78b3000 0x0 0x200>;
-+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
-+ status = "disabled";
-+ };
-+
-+ blsp1_uart6: serial@78b4000 {
-+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-+ reg = <0x0 0x078b4000 0x0 0x200>;
-+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
-+ status = "disabled";
- };
-
- blsp1_spi1: spi@78b5000 {
+++ /dev/null
-From 2c6597c72e9722ac020102d5af40126df0437b82 Mon Sep 17 00:00:00 2001
-From: Krishna Kurapati <quic_kriskura@quicinc.com>
-Date: Fri, 26 Jan 2024 00:29:18 +0530
-Subject: [PATCH] arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
-
-On several QUSB2 Targets, the hs_phy_irq mentioned is actually
-qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
-to qusb2_phy for such targets.
-
-In actuality, the hs_phy_irq is also present in these targets, but
-kept in for debug purposes in hw test environments. This is not
-triggered by default and its functionality is mutually exclusive
-to that of qusb2_phy interrupt.
-
-Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
-Add missing ss_phy_irq on some targets which allows for remote
-wakeup to work on a Super Speed link.
-
-Also modify order of interrupts in accordance to bindings update.
-Since driver looks up for interrupts by name and not by index, it
-is safe to modify order of these interrupts in the DT.
-
-Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
-Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
- arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +++++--
- arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++++--
- arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +++++--
- arch/arm64/boot/dts/qcom/sdm630.dtsi | 17 +++++++++++++----
- arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++--
- arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 +++++++--
- 8 files changed, 70 insertions(+), 14 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -430,6 +430,12 @@
- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
- assigned-clock-rates = <133330000>,
- <24000000>;
-+
-+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "pwr_event",
-+ "qusb2_phy";
-+
- resets = <&gcc GCC_USB1_BCR>;
- status = "disabled";
-
-@@ -628,6 +634,13 @@
- <133330000>,
- <24000000>;
-
-+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "pwr_event",
-+ "qusb2_phy",
-+ "ss_phy_irq";
-+
- resets = <&gcc GCC_USB0_BCR>;
- status = "disabled";
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -611,6 +611,13 @@
- <133330000>,
- <19200000>;
-
-+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "pwr_event",
-+ "qusb2_phy",
-+ "ss_phy_irq";
-+
- power-domains = <&gcc USB0_GDSC>;
-
- resets = <&gcc GCC_USB0_BCR>;
-@@ -653,6 +660,13 @@
- <133330000>,
- <19200000>;
-
-+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "pwr_event",
-+ "qusb2_phy",
-+ "ss_phy_irq";
-+
- power-domains = <&gcc USB1_GDSC>;
-
- resets = <&gcc GCC_USB1_BCR>;
+++ /dev/null
-From c3dc3d079d191c9149496b3c7fe1ece909386d93 Mon Sep 17 00:00:00 2001
-From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
-Date: Tue, 5 Sep 2023 15:25:35 +0530
-Subject: [PATCH] hwspinlock: qcom: Remove IPQ6018 SOC specific compatible
-
-IPQ6018 has 32 tcsr_mutex hwlock registers with stride 0x1000.
-The compatible string qcom,ipq6018-tcsr-mutex is mapped to
-of_msm8226_tcsr_mutex which has 32 locks configured with stride of 0x80
-and doesn't match the HW present in IPQ6018.
-
-Remove IPQ6018 specific compatible string so that it fallsback to
-of_tcsr_mutex data which maps to the correct configuration for IPQ6018.
-
-Fixes: 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older SoCs")
-Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Link: https://lore.kernel.org/r/20230905095535.1263113-3-quic_viswanat@quicinc.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- drivers/hwspinlock/qcom_hwspinlock.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/drivers/hwspinlock/qcom_hwspinlock.c
-+++ b/drivers/hwspinlock/qcom_hwspinlock.c
-@@ -115,7 +115,6 @@ static const struct of_device_id qcom_hw
- { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex },
- { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
- { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
-- { .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
- { .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
- { .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
- { .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+++ /dev/null
-From 0b17197055b528da22e9385200e61b847b499d48 Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Thu, 25 Jan 2024 11:04:11 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add tsens node
-
-IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add
-node for it.
-
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
-Link: https://lore.kernel.org/r/1706173452-1017-3-git-send-email-mantas@8devices.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -342,6 +342,16 @@
- clock-names = "core";
- };
-
-+ tsens: thermal-sensor@4a9000 {
-+ compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens";
-+ reg = <0x0 0x004a9000 0x0 0x1000>,
-+ <0x0 0x004a8000 0x0 0x1000>;
-+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "combined";
-+ #qcom,sensors = <16>;
-+ #thermal-sensor-cells = <1>;
-+ };
-+
- cryptobam: dma-controller@704000 {
- compatible = "qcom,bam-v1.7.0";
- reg = <0x0 0x00704000 0x0 0x20000>;
+++ /dev/null
-From 8f053e5616352943e16966f195f5a7a161e6fe7d Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Thu, 25 Jan 2024 11:04:12 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add thermal zones
-
-Add thermal zones to make use of thermal sensors data. For CPU zone,
-add cooling device that uses CPU frequency scaling.
-
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
-Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++
- 1 file changed, 121 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -9,6 +9,7 @@
- #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
- #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
- #include <dt-bindings/clock/qcom,apss-ipq.h>
-+#include <dt-bindings/thermal/thermal.h>
-
- / {
- #address-cells = <2>;
-@@ -43,6 +44,7 @@
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
-+ #cooling-cells = <2>;
- };
-
- CPU1: cpu@1 {
-@@ -55,6 +57,7 @@
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
-+ #cooling-cells = <2>;
- };
-
- CPU2: cpu@2 {
-@@ -67,6 +70,7 @@
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
-+ #cooling-cells = <2>;
- };
-
- CPU3: cpu@3 {
-@@ -79,6 +83,7 @@
- clock-names = "cpu";
- operating-points-v2 = <&cpu_opp_table>;
- cpu-supply = <&ipq6018_s2>;
-+ #cooling-cells = <2>;
- };
-
- L2_0: l2-cache {
-@@ -888,6 +893,122 @@
- };
- };
-
-+ thermal-zones {
-+ nss-top-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&tsens 4>;
-+
-+ trips {
-+ nss-top-critical {
-+ temperature = <125000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ nss-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&tsens 5>;
-+
-+ trips {
-+ nss-critical {
-+ temperature = <125000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ wcss-phya0-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&tsens 7>;
-+
-+ trips {
-+ wcss-phya0-critical {
-+ temperature = <125000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ wcss-phya1-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&tsens 8>;
-+
-+ trips {
-+ wcss-phya1-critical {
-+ temperature = <125000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ cpu-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&tsens 13>;
-+
-+ trips {
-+ cpu-critical {
-+ temperature = <125000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+
-+ cpu_alert: cpu-passive {
-+ temperature = <110000>;
-+ hysteresis = <1000>;
-+ type = "passive";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&cpu_alert>;
-+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
-+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+
-+ lpass-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&tsens 14>;
-+
-+ trips {
-+ lpass-critical {
-+ temperature = <125000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+
-+ ddrss-top-thermal {
-+ polling-delay-passive = <250>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&tsens 15>;
-+
-+ trips {
-+ ddrss-top-critical {
-+ temperature = <125000>;
-+ hysteresis = <1000>;
-+ type = "critical";
-+ };
-+ };
-+ };
-+ };
-+
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+++ /dev/null
-From fd712118aa1aa758da1fd1546b3f8a1b00e42cbc Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Tue, 23 Jan 2024 11:26:09 +0200
-Subject: [PATCH] clk: qcom: gcc-ipq6018: add qdss_at clock needed for wifi
- operation
-
-Without it system hangs upon wifi firmware load. It should be enabled by
-remoteproc/wifi driver. Bindings already exist for it, so add it based
-on vendor code.
-
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
-Link: https://lore.kernel.org/r/1706001970-26032-1-git-send-email-mantas@8devices.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- drivers/clk/qcom/gcc-ipq6018.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq6018.c
-+++ b/drivers/clk/qcom/gcc-ipq6018.c
-@@ -3523,6 +3523,22 @@ static struct clk_branch gcc_prng_ahb_cl
- },
- };
-
-+static struct clk_branch gcc_qdss_at_clk = {
-+ .halt_reg = 0x29024,
-+ .clkr = {
-+ .enable_reg = 0x29024,
-+ .enable_mask = BIT(0),
-+ .hw.init = &(struct clk_init_data){
-+ .name = "gcc_qdss_at_clk",
-+ .parent_hws = (const struct clk_hw *[]){
-+ &qdss_at_clk_src.clkr.hw },
-+ .num_parents = 1,
-+ .flags = CLK_SET_RATE_PARENT,
-+ .ops = &clk_branch2_ops,
-+ },
-+ },
-+};
-+
- static struct clk_branch gcc_qdss_dap_clk = {
- .halt_reg = 0x29084,
- .clkr = {
-@@ -4362,6 +4378,7 @@ static struct clk_regmap *gcc_ipq6018_cl
- [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
- [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
- [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
-+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
- [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
- [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
- [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
+++ /dev/null
-From 62a5df451ab911421da96655fcc4d1e269ff6e2f Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Tue, 23 Jan 2024 18:09:20 +0200
-Subject: [PATCH] phy: qcom-qmp-usb: fix serdes init sequence for IPQ6018
-
-Commit 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
-noted that IPQ6018 init is identical to IPQ8074. Yet downstream uses
-separate serdes init sequence for IPQ6018. Since already existing IPQ9574
-serdes init sequence is identical, just reuse it and fix failing USB3 mode
-in IPQ6018.
-
-Fixes: 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/1706026160-17520-3-git-send-email-mantas@8devices.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 20 +++++++++++++++++++-
- 1 file changed, 19 insertions(+), 1 deletion(-)
-
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -233,6 +233,43 @@ static const struct qmp_phy_init_tbl ipq
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
- };
-
-+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
-+};
-+
- static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-@@ -1591,6 +1628,26 @@ static const char * const qmp_phy_vreg_l
- "vdda-phy", "vdda-pll",
- };
-
-+static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
-+ .lanes = 1,
-+
-+ .serdes_tbl = ipq9574_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = ipq8074_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+};
-+
- static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
- .lanes = 1,
-
-@@ -2534,7 +2591,7 @@ static const struct of_device_id qmp_usb
- .data = &msm8996_usb3phy_cfg,
- }, {
- .compatible = "qcom,ipq6018-qmp-usb3-phy",
-- .data = &ipq8074_usb3phy_cfg,
-+ .data = &ipq6018_usb3phy_cfg,
- }, {
- .compatible = "qcom,sc7180-qmp-usb3-phy",
- .data = &sc7180_usb3phy_cfg,
+++ /dev/null
-From 6a25e70214fde6dcf900271c819c8d7fe7b9a4b0 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Thu, 23 Nov 2023 13:12:54 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP4 SPI node
-
-Add node to support the QUP4 SPI controller inside of IPQ8074.
-Some devices use this bus to communicate to a Bluetooth controller.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Link: https://lore.kernel.org/r/20231123121324.1046164-1-robimarko@gmail.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -529,6 +529,20 @@
- status = "disabled";
- };
-
-+ blsp1_spi4: spi@78b8000 {
-+ compatible = "qcom,spi-qup-v2.2.1";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x78b8000 0x600>;
-+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
-+ dmas = <&blsp_dma 18>, <&blsp_dma 19>;
-+ dma-names = "tx", "rx";
-+ status = "disabled";
-+ };
-+
- blsp1_i2c5: i2c@78b9000 {
- compatible = "qcom,i2c-qup-v2.2.1";
- #address-cells = <1>;
+++ /dev/null
-From 032be4f49dda786fea9e1501212f6cd09a7ded96 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 3 Nov 2022 14:49:43 +0100
-Subject: [PATCH] clk: qcom: clk-rcg2: introduce support for multiple conf for
- same freq
-
-Some RCG frequency can be reached by multiple configuration.
-
-We currently declare multiple configuration for the same frequency but
-that is not supported and always the first configuration will be taken.
-
-These multiple configuration are needed as based on the current parent
-configuration, it may be needed to use a different configuration to
-reach the same frequency.
-
-To handle this introduce 2 new macro, FM and C.
-
-- FM is used to declare an empty freq_tbl with just the frequency and an
- array of confs to insert all the config for the provided frequency.
-
-- C is used to declare a fre_conf where src, pre_div, m and n are
- provided.
-
-The driver is changed to handle this special freq_tbl and select the
-correct config by calculating the final rate and deciding based on the
-one that is less different than the requested one.
-
-Tested-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/clk-rcg.h | 14 ++++++-
- drivers/clk/qcom/clk-rcg2.c | 84 +++++++++++++++++++++++++++++++++----
- 2 files changed, 88 insertions(+), 10 deletions(-)
-
---- a/drivers/clk/qcom/clk-rcg.h
-+++ b/drivers/clk/qcom/clk-rcg.h
-@@ -7,7 +7,17 @@
- #include <linux/clk-provider.h>
- #include "clk-regmap.h"
-
--#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n), 0, NULL }
-+
-+#define FM(_f, _confs) { .freq = (_f), .confs_num = ARRAY_SIZE(_confs), .confs = (_confs) }
-+#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) }
-+
-+struct freq_conf {
-+ u8 src;
-+ u8 pre_div;
-+ u16 m;
-+ u16 n;
-+};
-
- struct freq_tbl {
- unsigned long freq;
-@@ -15,6 +25,8 @@ struct freq_tbl {
- u8 pre_div;
- u16 m;
- u16 n;
-+ int confs_num;
-+ const struct freq_conf *confs;
- };
-
- /**
---- a/drivers/clk/qcom/clk-rcg2.c
-+++ b/drivers/clk/qcom/clk-rcg2.c
-@@ -203,11 +203,60 @@ clk_rcg2_recalc_rate(struct clk_hw *hw,
- return __clk_rcg2_recalc_rate(hw, parent_rate, cfg);
- }
-
-+static void
-+clk_rcg2_select_conf(struct clk_hw *hw, struct freq_tbl *f_tbl,
-+ const struct freq_tbl *f, unsigned long req_rate)
-+{
-+ unsigned long best_rate = 0, parent_rate, rate;
-+ const struct freq_conf *conf, *best_conf;
-+ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-+ struct clk_hw *p;
-+ int index, i;
-+
-+ /* Search in each provided config the one that is near the wanted rate */
-+ for (i = 0, conf = f->confs; i < f->confs_num; i++, conf++) {
-+ index = qcom_find_src_index(hw, rcg->parent_map, conf->src);
-+ if (index < 0)
-+ continue;
-+
-+ p = clk_hw_get_parent_by_index(hw, index);
-+ if (!p)
-+ continue;
-+
-+ parent_rate = clk_hw_get_rate(p);
-+ rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div);
-+
-+ if (rate == req_rate) {
-+ best_conf = conf;
-+ break;
-+ }
-+
-+ if (abs(req_rate - rate) < abs(best_rate - rate)) {
-+ best_rate = rate;
-+ best_conf = conf;
-+ }
-+ }
-+
-+ /*
-+ * Very unlikely.
-+ * Force the first conf if we can't find a correct config.
-+ */
-+ if (unlikely(i == f->confs_num))
-+ best_conf = f->confs;
-+
-+ /* Apply the config */
-+ f_tbl->src = best_conf->src;
-+ f_tbl->pre_div = best_conf->pre_div;
-+ f_tbl->m = best_conf->m;
-+ f_tbl->n = best_conf->n;
-+}
-+
- static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
- struct clk_rate_request *req,
- enum freq_policy policy)
- {
- unsigned long clk_flags, rate = req->rate;
-+ struct freq_tbl f_tbl;
- struct clk_hw *p;
- struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- int index;
-@@ -226,7 +275,15 @@ static int _freq_tbl_determine_rate(stru
- if (!f)
- return -EINVAL;
-
-- index = qcom_find_src_index(hw, rcg->parent_map, f->src);
-+ f_tbl = *f;
-+ /*
-+ * A single freq may be reached by multiple configuration.
-+ * Try to find the bast one if we have this kind of freq_table.
-+ */
-+ if (f->confs)
-+ clk_rcg2_select_conf(hw, &f_tbl, f, rate);
-+
-+ index = qcom_find_src_index(hw, rcg->parent_map, f_tbl.src);
- if (index < 0)
- return index;
-
-@@ -236,18 +293,18 @@ static int _freq_tbl_determine_rate(stru
- return -EINVAL;
-
- if (clk_flags & CLK_SET_RATE_PARENT) {
-- rate = f->freq;
-- if (f->pre_div) {
-+ rate = f_tbl.freq;
-+ if (f_tbl.pre_div) {
- if (!rate)
- rate = req->rate;
- rate /= 2;
-- rate *= f->pre_div + 1;
-+ rate *= f_tbl.pre_div + 1;
- }
-
-- if (f->n) {
-+ if (f_tbl.n) {
- u64 tmp = rate;
-- tmp = tmp * f->n;
-- do_div(tmp, f->m);
-+ tmp = tmp * f_tbl.n;
-+ do_div(tmp, f_tbl.m);
- rate = tmp;
- }
- } else {
-@@ -255,7 +312,7 @@ static int _freq_tbl_determine_rate(stru
- }
- req->best_parent_hw = p;
- req->best_parent_rate = rate;
-- req->rate = f->freq;
-+ req->rate = f_tbl.freq;
-
- return 0;
- }
-@@ -351,6 +408,7 @@ static int __clk_rcg2_set_rate(struct cl
- {
- struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- const struct freq_tbl *f;
-+ struct freq_tbl f_tbl;
-
- switch (policy) {
- case FLOOR:
-@@ -366,7 +424,15 @@ static int __clk_rcg2_set_rate(struct cl
- if (!f)
- return -EINVAL;
-
-- return clk_rcg2_configure(rcg, f);
-+ f_tbl = *f;
-+ /*
-+ * A single freq may be reached by multiple configuration.
-+ * Try to find the best one if we have this kind of freq_table.
-+ */
-+ if (f->confs)
-+ clk_rcg2_select_conf(hw, &f_tbl, f, rate);
-+
-+ return clk_rcg2_configure(rcg, &f_tbl);
- }
-
- static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
+++ /dev/null
-From f778553f296792f4d1e8b3552603ad6116ea3eb3 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 3 Nov 2022 14:49:44 +0100
-Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple
- conf
-
-Rework nss_port5/6 to use the new multiple configuration implementation
-and correctly fix the clocks for these port under some corner case.
-
-This is particularly relevant for device that have 2.5G or 10G port
-connected to port5 or port 6 on ipq8074. As the parent are shared
-across multiple port it may be required to select the correct
-configuration to accomplish the desired clock. Without this patch such
-port doesn't work in some specific ethernet speed as the clock will be
-set to the wrong frequency as we just select the first configuration for
-the related frequency instead of selecting the best one.
-
-Tested-by: Robert Marko <robimarko@gmail.com> # ipq8074 Qnap QHora-301W
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/gcc-ipq8074.c | 64 +++++++++++++++++++++++++---------
- 1 file changed, 48 insertions(+), 16 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -1676,13 +1676,21 @@ static struct clk_regmap_div nss_port4_t
- },
- };
-
-+static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
-+ C(P_UNIPHY1_RX, 12.5, 0, 0),
-+ C(P_UNIPHY0_RX, 5, 0, 0),
-+};
-+
-+static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
-+ C(P_UNIPHY1_RX, 2.5, 0, 0),
-+ C(P_UNIPHY0_RX, 1, 0, 0),
-+};
-+
- static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
-- F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
-- F(25000000, P_UNIPHY0_RX, 5, 0, 0),
-+ FM(25000000, ftbl_nss_port5_rx_clk_src_25),
- F(78125000, P_UNIPHY1_RX, 4, 0, 0),
-- F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
-- F(125000000, P_UNIPHY0_RX, 1, 0, 0),
-+ FM(125000000, ftbl_nss_port5_rx_clk_src_125),
- F(156250000, P_UNIPHY1_RX, 2, 0, 0),
- F(312500000, P_UNIPHY1_RX, 1, 0, 0),
- { }
-@@ -1738,13 +1746,21 @@ static struct clk_regmap_div nss_port5_r
- },
- };
-
-+static struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
-+ C(P_UNIPHY1_TX, 12.5, 0, 0),
-+ C(P_UNIPHY0_TX, 5, 0, 0),
-+};
-+
-+static struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
-+ C(P_UNIPHY1_TX, 2.5, 0, 0),
-+ C(P_UNIPHY0_TX, 1, 0, 0),
-+};
-+
- static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
-- F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
-- F(25000000, P_UNIPHY0_TX, 5, 0, 0),
-+ FM(25000000, ftbl_nss_port5_tx_clk_src_25),
- F(78125000, P_UNIPHY1_TX, 4, 0, 0),
-- F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
-- F(125000000, P_UNIPHY0_TX, 1, 0, 0),
-+ FM(125000000, ftbl_nss_port5_tx_clk_src_125),
- F(156250000, P_UNIPHY1_TX, 2, 0, 0),
- F(312500000, P_UNIPHY1_TX, 1, 0, 0),
- { }
-@@ -1800,13 +1816,21 @@ static struct clk_regmap_div nss_port5_t
- },
- };
-
-+static struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
-+ C(P_UNIPHY2_RX, 5, 0, 0),
-+ C(P_UNIPHY2_RX, 12.5, 0, 0),
-+};
-+
-+static struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
-+ C(P_UNIPHY2_RX, 1, 0, 0),
-+ C(P_UNIPHY2_RX, 2.5, 0, 0),
-+};
-+
- static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
-- F(25000000, P_UNIPHY2_RX, 5, 0, 0),
-- F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
-+ FM(25000000, ftbl_nss_port6_rx_clk_src_25),
- F(78125000, P_UNIPHY2_RX, 4, 0, 0),
-- F(125000000, P_UNIPHY2_RX, 1, 0, 0),
-- F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
-+ FM(125000000, ftbl_nss_port6_rx_clk_src_125),
- F(156250000, P_UNIPHY2_RX, 2, 0, 0),
- F(312500000, P_UNIPHY2_RX, 1, 0, 0),
- { }
-@@ -1857,13 +1881,21 @@ static struct clk_regmap_div nss_port6_r
- },
- };
-
-+static struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
-+ C(P_UNIPHY2_TX, 5, 0, 0),
-+ C(P_UNIPHY2_TX, 12.5, 0, 0),
-+};
-+
-+static struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
-+ C(P_UNIPHY2_TX, 1, 0, 0),
-+ C(P_UNIPHY2_TX, 2.5, 0, 0),
-+};
-+
- static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
-- F(25000000, P_UNIPHY2_TX, 5, 0, 0),
-- F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
-+ FM(25000000, ftbl_nss_port6_tx_clk_src_25),
- F(78125000, P_UNIPHY2_TX, 4, 0, 0),
-- F(125000000, P_UNIPHY2_TX, 1, 0, 0),
-- F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
-+ FM(125000000, ftbl_nss_port6_tx_clk_src_125),
- F(156250000, P_UNIPHY2_TX, 2, 0, 0),
- F(312500000, P_UNIPHY2_TX, 1, 0, 0),
- { }
+++ /dev/null
-From ad2d07f71739351eeea1d8a120c0918e2c4b265f Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 22 Dec 2021 12:23:34 +0100
-Subject: [PATCH] arm64: dts: ipq8074: add reserved memory nodes
-
-IPQ8074 has multiple reserved memory ranges, if they are not defined
-then weird things tend to happen, board hangs and resets when PCI or
-WLAN is used etc.
-
-So, to avoid all of that add the reserved memory nodes from the downstream
-5.4 kernel from QCA.
-This is their default layout meant for devices with 1GB of RAM, but
-devices with lower ammounts can override the Q6 node.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 35 +++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -85,6 +85,16 @@
- #size-cells = <2>;
- ranges;
-
-+ nss@40000000 {
-+ no-map;
-+ reg = <0x0 0x40000000 0x0 0x01000000>;
-+ };
-+
-+ tzapp_region: tzapp@4a400000 {
-+ no-map;
-+ reg = <0x0 0x4a400000 0x0 0x00200000>;
-+ };
-+
- bootloader@4a600000 {
- reg = <0x0 0x4a600000 0x0 0x400000>;
- no-map;
-@@ -107,6 +117,21 @@
- reg = <0x0 0x4ac00000 0x0 0x400000>;
- no-map;
- };
-+
-+ q6_region: wcnss@4b000000 {
-+ no-map;
-+ reg = <0x0 0x4b000000 0x0 0x05f00000>;
-+ };
-+
-+ q6_etr_region: q6_etr_dump@50f00000 {
-+ no-map;
-+ reg = <0x0 0x50f00000 0x0 0x00100000>;
-+ };
-+
-+ m3_dump_region: m3_dump@51000000 {
-+ no-map;
-+ reg = <0x0 0x51000000 0x0 0x100000>;
-+ };
- };
-
- firmware {
+++ /dev/null
-From 8a576b5bc9f0555d1d970cacabcaa24a3b74fa57 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:15:01 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to
- GCC
-
-Pass QMP PCI PHY PIPE clocks to the GCC controller so it does not have to
-find them by matching globaly by name.
-
-If not passed directly, driver maintains backwards compatibility by then
-falling back to global lookup.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -399,8 +399,8 @@
- gcc: gcc@1800000 {
- compatible = "qcom,gcc-ipq8074";
- reg = <0x01800000 0x80000>;
-- clocks = <&xo>, <&sleep_clk>;
-- clock-names = "xo", "sleep_clk";
-+ clocks = <&xo>, <&sleep_clk>, <&pcie_phy0>, <&pcie_phy1>;
-+ clock-names = "xo", "sleep_clk", "pcie0_pipe", "pcie1_pipe";
- #clock-cells = <1>;
- #power-domain-cells = <1>;
- #reset-cells = <1>;
+++ /dev/null
-From fb1f6850be00d8dd8a54017be4c1336e224069ac Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:26:25 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: use msi-parent for PCIe
-
-Instead of hardcoding the IRQ, simply use msi-parent instead.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +++-----
- 1 file changed, 3 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -734,7 +734,7 @@
- reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
- ranges = <0 0xb00a000 0xffd>;
-
-- v2m@0 {
-+ gic_v2m0: v2m@0 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x0 0xffd>;
-@@ -847,8 +847,7 @@
- ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
- <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
-
-- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-- interrupt-names = "msi";
-+ msi-parent = <&gic_v2m0>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 142
-@@ -909,8 +908,7 @@
- ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
- <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
-
-- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-- interrupt-names = "msi";
-+ msi-parent = <&gic_v2m0>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 75
+++ /dev/null
-From 125681433c8e526356947acf572fe8ca8ad32291 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Date: Sat, 30 Jan 2021 10:50:05 +0530
-Subject: [PATCH] remoteproc: qcom: Add PRNG proxy clock
-
-PRNG clock is needed by the secure PIL, support for the same
-is added in subsequent patches.
-
-Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Signed-off-by: Sricharan R <sricharan@codeaurora.org>
-Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++--------
- 1 file changed, 47 insertions(+), 18 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -91,19 +91,6 @@ enum {
- WCSS_QCS404,
- };
-
--struct wcss_data {
-- const char *firmware_name;
-- unsigned int crash_reason_smem;
-- u32 version;
-- bool aon_reset_required;
-- bool wcss_q6_reset_required;
-- const char *ssr_name;
-- const char *sysmon_name;
-- int ssctl_id;
-- const struct rproc_ops *ops;
-- bool requires_force_stop;
--};
--
- struct q6v5_wcss {
- struct device *dev;
-
-@@ -128,6 +115,7 @@ struct q6v5_wcss {
- struct clk *qdsp6ss_xo_cbcr;
- struct clk *qdsp6ss_core_gfmux;
- struct clk *lcc_bcr_sleep;
-+ struct clk *prng_clk;
- struct regulator *cx_supply;
- struct qcom_sysmon *sysmon;
-
-@@ -151,6 +139,21 @@ struct q6v5_wcss {
- struct qcom_rproc_ssr ssr_subdev;
- };
-
-+struct wcss_data {
-+ int (*init_clock)(struct q6v5_wcss *wcss);
-+ int (*init_regulator)(struct q6v5_wcss *wcss);
-+ const char *firmware_name;
-+ unsigned int crash_reason_smem;
-+ u32 version;
-+ bool aon_reset_required;
-+ bool wcss_q6_reset_required;
-+ const char *ssr_name;
-+ const char *sysmon_name;
-+ int ssctl_id;
-+ const struct rproc_ops *ops;
-+ bool requires_force_stop;
-+};
-+
- static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
- {
- int ret;
-@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc
- struct q6v5_wcss *wcss = rproc->priv;
- int ret;
-
-+ ret = clk_prepare_enable(wcss->prng_clk);
-+ if (ret) {
-+ dev_err(wcss->dev, "prng clock enable failed\n");
-+ return ret;
-+ }
-+
- qcom_q6v5_prepare(&wcss->q6v5);
-
- /* Release Q6 and WCSS reset */
-@@ -733,6 +742,7 @@ static int q6v5_wcss_stop(struct rproc *
- return ret;
- }
-
-+ clk_disable_unprepare(wcss->prng_clk);
- qcom_q6v5_unprepare(&wcss->q6v5);
-
- return 0;
-@@ -900,7 +910,21 @@ static int q6v5_alloc_memory_region(stru
- return 0;
- }
-
--static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
-+static int ipq8074_init_clock(struct q6v5_wcss *wcss)
-+{
-+ int ret;
-+
-+ wcss->prng_clk = devm_clk_get(wcss->dev, "prng");
-+ if (IS_ERR(wcss->prng_clk)) {
-+ ret = PTR_ERR(wcss->prng_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(wcss->dev, "Failed to get prng clock\n");
-+ return ret;
-+ }
-+ return 0;
-+}
-+
-+static int qcs404_init_clock(struct q6v5_wcss *wcss)
- {
- int ret;
-
-@@ -990,7 +1014,7 @@ static int q6v5_wcss_init_clock(struct q
- return 0;
- }
-
--static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
-+static int qcs404_init_regulator(struct q6v5_wcss *wcss)
- {
- wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
- if (IS_ERR(wcss->cx_supply))
-@@ -1034,12 +1058,14 @@ static int q6v5_wcss_probe(struct platfo
- if (ret)
- goto free_rproc;
-
-- if (wcss->version == WCSS_QCS404) {
-- ret = q6v5_wcss_init_clock(wcss);
-+ if (desc->init_clock) {
-+ ret = desc->init_clock(wcss);
- if (ret)
- goto free_rproc;
-+ }
-
-- ret = q6v5_wcss_init_regulator(wcss);
-+ if (desc->init_regulator) {
-+ ret = desc->init_regulator(wcss);
- if (ret)
- goto free_rproc;
- }
-@@ -1087,6 +1113,7 @@ static int q6v5_wcss_remove(struct platf
- }
-
- static const struct wcss_data wcss_ipq8074_res_init = {
-+ .init_clock = ipq8074_init_clock,
- .firmware_name = "IPQ8074/q6_fw.mdt",
- .crash_reason_smem = WCSS_CRASH_REASON,
- .aon_reset_required = true,
-@@ -1096,6 +1123,8 @@ static const struct wcss_data wcss_ipq80
- };
-
- static const struct wcss_data wcss_qcs404_res_init = {
-+ .init_clock = qcs404_init_clock,
-+ .init_regulator = qcs404_init_regulator,
- .crash_reason_smem = WCSS_CRASH_REASON,
- .firmware_name = "wcnss.mdt",
- .version = WCSS_QCS404,
+++ /dev/null
-From 7358d42dfbdfdb5d4f1d0d4c2e5c2bb4143a29b0 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Date: Sat, 30 Jan 2021 10:50:06 +0530
-Subject: [PATCH] remoteproc: qcom: Add secure PIL support
-
-IPQ8074 uses secure PIL. Hence, adding the support for the same.
-
-Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Signed-off-by: Sricharan R <sricharan@codeaurora.org>
-Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 43 +++++++++++++++++++++++++++--
- 1 file changed, 40 insertions(+), 3 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -18,6 +18,7 @@
- #include <linux/regulator/consumer.h>
- #include <linux/reset.h>
- #include <linux/soc/qcom/mdt_loader.h>
-+#include <linux/qcom_scm.h>
- #include "qcom_common.h"
- #include "qcom_pil_info.h"
- #include "qcom_q6v5.h"
-@@ -86,6 +87,9 @@
- #define TCSR_WCSS_CLK_ENABLE 0x14
-
- #define MAX_HALT_REG 3
-+
-+#define WCNSS_PAS_ID 6
-+
- enum {
- WCSS_IPQ8074,
- WCSS_QCS404,
-@@ -134,6 +138,7 @@ struct q6v5_wcss {
- unsigned int crash_reason_smem;
- u32 version;
- bool requires_force_stop;
-+ bool need_mem_protection;
-
- struct qcom_rproc_glink glink_subdev;
- struct qcom_rproc_ssr ssr_subdev;
-@@ -152,6 +157,7 @@ struct wcss_data {
- int ssctl_id;
- const struct rproc_ops *ops;
- bool requires_force_stop;
-+ bool need_mem_protection;
- };
-
- static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
-@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc
-
- qcom_q6v5_prepare(&wcss->q6v5);
-
-+ if (wcss->need_mem_protection) {
-+ ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
-+ if (ret) {
-+ dev_err(wcss->dev, "wcss_reset failed\n");
-+ return ret;
-+ }
-+ goto wait_for_reset;
-+ }
-+
- /* Release Q6 and WCSS reset */
- ret = reset_control_deassert(wcss->wcss_reset);
- if (ret) {
-@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc
- if (ret)
- goto wcss_q6_reset;
-
-+wait_for_reset:
- ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
- if (ret == -ETIMEDOUT)
- dev_err(wcss->dev, "start timed out\n");
-@@ -718,6 +734,15 @@ static int q6v5_wcss_stop(struct rproc *
- struct q6v5_wcss *wcss = rproc->priv;
- int ret;
-
-+ if (wcss->need_mem_protection) {
-+ ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
-+ if (ret) {
-+ dev_err(wcss->dev, "not able to shutdown\n");
-+ return ret;
-+ }
-+ goto pas_done;
-+ }
-+
- /* WCSS powerdown */
- if (wcss->requires_force_stop) {
- ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
-@@ -742,6 +767,7 @@ static int q6v5_wcss_stop(struct rproc *
- return ret;
- }
-
-+pas_done:
- clk_disable_unprepare(wcss->prng_clk);
- qcom_q6v5_unprepare(&wcss->q6v5);
-
-@@ -765,9 +791,15 @@ static int q6v5_wcss_load(struct rproc *
- struct q6v5_wcss *wcss = rproc->priv;
- int ret;
-
-- ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
-- 0, wcss->mem_region, wcss->mem_phys,
-- wcss->mem_size, &wcss->mem_reloc);
-+ if (wcss->need_mem_protection)
-+ ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
-+ WCNSS_PAS_ID, wcss->mem_region,
-+ wcss->mem_phys, wcss->mem_size,
-+ &wcss->mem_reloc);
-+ else
-+ ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
-+ 0, wcss->mem_region, wcss->mem_phys,
-+ wcss->mem_size, &wcss->mem_reloc);
- if (ret)
- return ret;
-
-@@ -1036,6 +1068,9 @@ static int q6v5_wcss_probe(struct platfo
- if (!desc)
- return -EINVAL;
-
-+ if (desc->need_mem_protection && !qcom_scm_is_available())
-+ return -EPROBE_DEFER;
-+
- rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
- desc->firmware_name, sizeof(*wcss));
- if (!rproc) {
-@@ -1049,6 +1084,7 @@ static int q6v5_wcss_probe(struct platfo
-
- wcss->version = desc->version;
- wcss->requires_force_stop = desc->requires_force_stop;
-+ wcss->need_mem_protection = desc->need_mem_protection;
-
- ret = q6v5_wcss_init_mmio(wcss, pdev);
- if (ret)
-@@ -1120,6 +1156,7 @@ static const struct wcss_data wcss_ipq80
- .wcss_q6_reset_required = true,
- .ops = &q6v5_wcss_ipq8074_ops,
- .requires_force_stop = true,
-+ .need_mem_protection = true,
- };
-
- static const struct wcss_data wcss_qcs404_res_init = {
+++ /dev/null
-From b422c9d4f048b086ce83f44a7cfcddcce162897f Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Date: Sat, 30 Jan 2021 10:50:07 +0530
-Subject: [PATCH] remoteproc: qcom: Add support for split q6 + m3 wlan firmware
-
-IPQ8074 supports split firmware for q6 and m3 as well.
-So add support for loading the m3 firmware before q6.
-Now the drivers works fine for both split and unified
-firmwares.
-
-Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Signed-off-by: Sricharan R <sricharan@codeaurora.org>
-Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++----
- 1 file changed, 29 insertions(+), 4 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -139,6 +139,7 @@ struct q6v5_wcss {
- u32 version;
- bool requires_force_stop;
- bool need_mem_protection;
-+ const char *m3_firmware_name;
-
- struct qcom_rproc_glink glink_subdev;
- struct qcom_rproc_ssr ssr_subdev;
-@@ -147,7 +148,8 @@ struct q6v5_wcss {
- struct wcss_data {
- int (*init_clock)(struct q6v5_wcss *wcss);
- int (*init_regulator)(struct q6v5_wcss *wcss);
-- const char *firmware_name;
-+ const char *q6_firmware_name;
-+ const char *m3_firmware_name;
- unsigned int crash_reason_smem;
- u32 version;
- bool aon_reset_required;
-@@ -789,8 +791,29 @@ static void *q6v5_wcss_da_to_va(struct r
- static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
- {
- struct q6v5_wcss *wcss = rproc->priv;
-+ const struct firmware *m3_fw;
- int ret;
-
-+ if (wcss->m3_firmware_name) {
-+ ret = request_firmware(&m3_fw, wcss->m3_firmware_name,
-+ wcss->dev);
-+ if (ret)
-+ goto skip_m3;
-+
-+ ret = qcom_mdt_load_no_init(wcss->dev, m3_fw,
-+ wcss->m3_firmware_name, 0,
-+ wcss->mem_region, wcss->mem_phys,
-+ wcss->mem_size, &wcss->mem_reloc);
-+
-+ release_firmware(m3_fw);
-+
-+ if (ret) {
-+ dev_err(wcss->dev, "can't load m3_fw.bXX\n");
-+ return ret;
-+ }
-+ }
-+
-+skip_m3:
- if (wcss->need_mem_protection)
- ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
- WCNSS_PAS_ID, wcss->mem_region,
-@@ -1072,7 +1095,7 @@ static int q6v5_wcss_probe(struct platfo
- return -EPROBE_DEFER;
-
- rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
-- desc->firmware_name, sizeof(*wcss));
-+ desc->q6_firmware_name, sizeof(*wcss));
- if (!rproc) {
- dev_err(&pdev->dev, "failed to allocate rproc\n");
- return -ENOMEM;
-@@ -1085,6 +1108,7 @@ static int q6v5_wcss_probe(struct platfo
- wcss->version = desc->version;
- wcss->requires_force_stop = desc->requires_force_stop;
- wcss->need_mem_protection = desc->need_mem_protection;
-+ wcss->m3_firmware_name = desc->m3_firmware_name;
-
- ret = q6v5_wcss_init_mmio(wcss, pdev);
- if (ret)
-@@ -1150,7 +1174,8 @@ static int q6v5_wcss_remove(struct platf
-
- static const struct wcss_data wcss_ipq8074_res_init = {
- .init_clock = ipq8074_init_clock,
-- .firmware_name = "IPQ8074/q6_fw.mdt",
-+ .q6_firmware_name = "IPQ8074/q6_fw.mdt",
-+ .m3_firmware_name = "IPQ8074/m3_fw.mdt",
- .crash_reason_smem = WCSS_CRASH_REASON,
- .aon_reset_required = true,
- .wcss_q6_reset_required = true,
-@@ -1163,7 +1188,7 @@ static const struct wcss_data wcss_qcs40
- .init_clock = qcs404_init_clock,
- .init_regulator = qcs404_init_regulator,
- .crash_reason_smem = WCSS_CRASH_REASON,
-- .firmware_name = "wcnss.mdt",
-+ .q6_firmware_name = "wcnss.mdt",
- .version = WCSS_QCS404,
- .aon_reset_required = false,
- .wcss_q6_reset_required = false,
+++ /dev/null
-From 3a8f67b4770c817b04794c9a02e3f88f85d86280 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Date: Sat, 30 Jan 2021 10:50:08 +0530
-Subject: [PATCH] remoteproc: qcom: Add ssr subdevice identifier
-
-Add name for ssr subdevice on IPQ8074 SoC.
-
-Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Signed-off-by: Sricharan R <sricharan@codeaurora.org>
-Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -1179,6 +1179,7 @@ static const struct wcss_data wcss_ipq80
- .crash_reason_smem = WCSS_CRASH_REASON,
- .aon_reset_required = true,
- .wcss_q6_reset_required = true,
-+ .ssr_name = "q6wcss",
- .ops = &q6v5_wcss_ipq8074_ops,
- .requires_force_stop = true,
- .need_mem_protection = true,
+++ /dev/null
-From 8c73af6e8d78c66cfef0f551b00d375ec0b67ff3 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Date: Sat, 30 Jan 2021 10:50:09 +0530
-Subject: [PATCH] remoteproc: qcom: Update regmap offsets for halt register
-
-Fixed issue in reading halt-regs parameter from device-tree.
-
-Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Signed-off-by: Sricharan R <sricharan@codeaurora.org>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++--------
- 1 file changed, 14 insertions(+), 8 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -86,7 +86,7 @@
- #define TCSR_WCSS_CLK_MASK 0x1F
- #define TCSR_WCSS_CLK_ENABLE 0x14
-
--#define MAX_HALT_REG 3
-+#define MAX_HALT_REG 4
-
- #define WCNSS_PAS_ID 6
-
-@@ -154,6 +154,7 @@ struct wcss_data {
- u32 version;
- bool aon_reset_required;
- bool wcss_q6_reset_required;
-+ bool bcr_reset_required;
- const char *ssr_name;
- const char *sysmon_name;
- int ssctl_id;
-@@ -875,10 +876,13 @@ static int q6v5_wcss_init_reset(struct q
- }
- }
-
-- wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset");
-- if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
-- dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
-- return PTR_ERR(wcss->wcss_q6_bcr_reset);
-+ if (desc->bcr_reset_required) {
-+ wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev,
-+ "wcss_q6_bcr_reset");
-+ if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
-+ dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
-+ return PTR_ERR(wcss->wcss_q6_bcr_reset);
-+ }
- }
-
- return 0;
-@@ -929,9 +933,9 @@ static int q6v5_wcss_init_mmio(struct q6
- return -EINVAL;
- }
-
-- wcss->halt_q6 = halt_reg[0];
-- wcss->halt_wcss = halt_reg[1];
-- wcss->halt_nc = halt_reg[2];
-+ wcss->halt_q6 = halt_reg[1];
-+ wcss->halt_wcss = halt_reg[2];
-+ wcss->halt_nc = halt_reg[3];
-
- return 0;
- }
-@@ -1179,6 +1183,7 @@ static const struct wcss_data wcss_ipq80
- .crash_reason_smem = WCSS_CRASH_REASON,
- .aon_reset_required = true,
- .wcss_q6_reset_required = true,
-+ .bcr_reset_required = false,
- .ssr_name = "q6wcss",
- .ops = &q6v5_wcss_ipq8074_ops,
- .requires_force_stop = true,
-@@ -1193,6 +1198,7 @@ static const struct wcss_data wcss_qcs40
- .version = WCSS_QCS404,
- .aon_reset_required = false,
- .wcss_q6_reset_required = false,
-+ .bcr_reset_required = true,
- .ssr_name = "mpss",
- .sysmon_name = "wcnss",
- .ssctl_id = 0x12,
+++ /dev/null
-From ff7c6533ed8c4de58ed6c8aab03ea59c03eb4f31 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Date: Sat, 30 Jan 2021 10:50:10 +0530
-Subject: [PATCH] dt-bindings: clock: qcom: Add reset for WCSSAON
-
-Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
-
-Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Signed-off-by: Sricharan R <sricharan@codeaurora.org>
-Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
-Acked-by: Rob Herring <robh@kernel.org>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
----
- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-@@ -381,6 +381,7 @@
- #define GCC_NSSPORT4_RESET 143
- #define GCC_NSSPORT5_RESET 144
- #define GCC_NSSPORT6_RESET 145
-+#define GCC_WCSSAON_RESET 146
-
- #define USB0_GDSC 0
- #define USB1_GDSC 1
+++ /dev/null
-From 43d9788f546d24df22d8ba3fcc2497d7ccc198f3 Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Date: Sat, 30 Jan 2021 10:50:11 +0530
-Subject: [PATCH] clk: qcom: Add WCSSAON reset
-
-Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.
-
-Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Signed-off-by: Sricharan R <sricharan@codeaurora.org>
-Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/qcom/gcc-ipq8074.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -4711,6 +4711,7 @@ static const struct qcom_reset_map gcc_i
- [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
- [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
- [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
-+ [GCC_WCSSAON_RESET] = { 0x59010, 0 },
- };
-
- static struct gdsc *gcc_ipq8074_gdscs[] = {
+++ /dev/null
-From 406a332fd1bcc4e18d73cce390f56272fe9111d7 Mon Sep 17 00:00:00 2001
-From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
-Date: Fri, 17 Apr 2020 16:37:10 +0530
-Subject: [PATCH] remoteproc: wcss: disable auto boot for IPQ8074
-
-There is no need for remoteproc to boot automatically, ath11k will trigger
-booting when its probing.
-
-Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -161,6 +161,7 @@ struct wcss_data {
- const struct rproc_ops *ops;
- bool requires_force_stop;
- bool need_mem_protection;
-+ bool need_auto_boot;
- };
-
- static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
-@@ -1150,6 +1151,7 @@ static int q6v5_wcss_probe(struct platfo
- desc->sysmon_name,
- desc->ssctl_id);
-
-+ rproc->auto_boot = desc->need_auto_boot;
- ret = rproc_add(rproc);
- if (ret)
- goto free_rproc;
-@@ -1188,6 +1190,7 @@ static const struct wcss_data wcss_ipq80
- .ops = &q6v5_wcss_ipq8074_ops,
- .requires_force_stop = true,
- .need_mem_protection = true,
-+ .need_auto_boot = false,
- };
-
- static const struct wcss_data wcss_qcs404_res_init = {
-@@ -1204,6 +1207,7 @@ static const struct wcss_data wcss_qcs40
- .ssctl_id = 0x12,
- .ops = &q6v5_wcss_qcs404_ops,
- .requires_force_stop = false,
-+ .need_auto_boot = true,
- };
-
- static const struct of_device_id q6v5_wcss_of_match[] = {
+++ /dev/null
-From 7388400b8bd42f71d040dbf2fdbdcb834fcc0ede Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Date: Sat, 30 Jan 2021 10:50:13 +0530
-Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
-
-Enable remoteproc WCSS PIL driver with glink and ssr subdevices.
-Also enables smp2p and mailboxes required for IPC.
-
-Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Signed-off-by: Sricharan R <sricharan@codeaurora.org>
-Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 81 +++++++++++++++++++++++++++
- 1 file changed, 81 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -141,6 +141,32 @@
- };
- };
-
-+ wcss: smp2p-wcss {
-+ compatible = "qcom,smp2p";
-+ qcom,smem = <435>, <428>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <0 322 1>;
-+
-+ mboxes = <&apcs_glb 9>;
-+
-+ qcom,local-pid = <0>;
-+ qcom,remote-pid = <1>;
-+
-+ wcss_smp2p_out: master-kernel {
-+ qcom,entry-name = "master-kernel";
-+ qcom,smp2p-feature-ssr-ack;
-+ #qcom,smem-state-cells = <1>;
-+ };
-+
-+ wcss_smp2p_in: slave-kernel {
-+ qcom,entry-name = "slave-kernel";
-+
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+ };
-+ };
-+
- soc: soc {
- #address-cells = <0x1>;
- #size-cells = <0x1>;
-@@ -417,6 +443,11 @@
- reg = <0x01937000 0x21000>;
- };
-
-+ tcsr_q6: syscon@1945000 {
-+ compatible = "syscon";
-+ reg = <0x01945000 0xe000>;
-+ };
-+
- spmi_bus: spmi@200f000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0x0200f000 0x001000>,
-@@ -949,6 +980,56 @@
- "axi_s_sticky";
- status = "disabled";
- };
-+
-+ q6v5_wcss: q6v5_wcss@cd00000 {
-+ compatible = "qcom,ipq8074-wcss-pil";
-+ reg = <0x0cd00000 0x4040>,
-+ <0x004ab000 0x20>;
-+ reg-names = "qdsp6",
-+ "rmb";
-+ qca,auto-restart;
-+ qca,extended-intc;
-+ interrupts-extended = <&intc 0 325 1>,
-+ <&wcss_smp2p_in 0 0>,
-+ <&wcss_smp2p_in 1 0>,
-+ <&wcss_smp2p_in 2 0>,
-+ <&wcss_smp2p_in 3 0>;
-+ interrupt-names = "wdog",
-+ "fatal",
-+ "ready",
-+ "handover",
-+ "stop-ack";
-+
-+ resets = <&gcc GCC_WCSSAON_RESET>,
-+ <&gcc GCC_WCSS_BCR>,
-+ <&gcc GCC_WCSS_Q6_BCR>;
-+
-+ reset-names = "wcss_aon_reset",
-+ "wcss_reset",
-+ "wcss_q6_reset";
-+
-+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
-+ clock-names = "prng";
-+
-+ qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
-+
-+ qcom,smem-states = <&wcss_smp2p_out 0>,
-+ <&wcss_smp2p_out 1>;
-+ qcom,smem-state-names = "shutdown",
-+ "stop";
-+
-+ memory-region = <&q6_region>;
-+
-+ glink-edge {
-+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
-+ qcom,remote-pid = <1>;
-+ mboxes = <&apcs_glb 8>;
-+
-+ rpm_requests {
-+ qcom,glink-channels = "IPCRTR";
-+ };
-+ };
-+ };
- };
-
- timer {
+++ /dev/null
-From a67d1901741c162645eda0dbdc3a2c0c2aff5cf4 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 21 Dec 2021 14:49:36 +0100
-Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node
-
-IPQ8074 has a AHB based Q6v5 802.11ax radios that are supported
-by the ath11k.
-
-Add the required DT node to enable the built-in radios.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 111 ++++++++++++++++++++++++++
- 1 file changed, 111 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -1030,6 +1030,117 @@
- };
- };
- };
-+
-+ wifi: wifi@c0000000 {
-+ compatible = "qcom,ipq8074-wifi";
-+ reg = <0xc000000 0x2000000>;
-+
-+ interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
-+
-+ interrupt-names = "misc-pulse1",
-+ "misc-latch",
-+ "sw-exception",
-+ "ce0",
-+ "ce1",
-+ "ce2",
-+ "ce3",
-+ "ce4",
-+ "ce5",
-+ "ce6",
-+ "ce7",
-+ "ce8",
-+ "ce9",
-+ "ce10",
-+ "ce11",
-+ "host2wbm-desc-feed",
-+ "host2reo-re-injection",
-+ "host2reo-command",
-+ "host2rxdma-monitor-ring3",
-+ "host2rxdma-monitor-ring2",
-+ "host2rxdma-monitor-ring1",
-+ "reo2ost-exception",
-+ "wbm2host-rx-release",
-+ "reo2host-status",
-+ "reo2host-destination-ring4",
-+ "reo2host-destination-ring3",
-+ "reo2host-destination-ring2",
-+ "reo2host-destination-ring1",
-+ "rxdma2host-monitor-destination-mac3",
-+ "rxdma2host-monitor-destination-mac2",
-+ "rxdma2host-monitor-destination-mac1",
-+ "ppdu-end-interrupts-mac3",
-+ "ppdu-end-interrupts-mac2",
-+ "ppdu-end-interrupts-mac1",
-+ "rxdma2host-monitor-status-ring-mac3",
-+ "rxdma2host-monitor-status-ring-mac2",
-+ "rxdma2host-monitor-status-ring-mac1",
-+ "host2rxdma-host-buf-ring-mac3",
-+ "host2rxdma-host-buf-ring-mac2",
-+ "host2rxdma-host-buf-ring-mac1",
-+ "rxdma2host-destination-ring-mac3",
-+ "rxdma2host-destination-ring-mac2",
-+ "rxdma2host-destination-ring-mac1",
-+ "host2tcl-input-ring4",
-+ "host2tcl-input-ring3",
-+ "host2tcl-input-ring2",
-+ "host2tcl-input-ring1",
-+ "wbm2host-tx-completions-ring3",
-+ "wbm2host-tx-completions-ring2",
-+ "wbm2host-tx-completions-ring1",
-+ "tcl2host-status-ring";
-+ qcom,rproc = <&q6v5_wcss>;
-+ status = "disabled";
-+ };
- };
-
- timer {
+++ /dev/null
-From cb3ef99c1553565e1dc0301ccd5c1c0fa2d15c15 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 31 Dec 2021 17:56:14 +0100
-Subject: [PATCH] arm64: dts: ipq8074: add CPU clock
-
-Now that CPU clock is exposed and can be controlled, add the necessary
-properties to the CPU nodes.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -5,6 +5,7 @@
-
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
-+#include <dt-bindings/clock/qcom,apss-ipq.h>
-
- / {
- #address-cells = <2>;
-@@ -38,6 +39,8 @@
- reg = <0x0>;
- next-level-cache = <&L2_0>;
- enable-method = "psci";
-+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+ clock-names = "cpu";
- };
-
- CPU1: cpu@1 {
-@@ -46,6 +49,8 @@
- enable-method = "psci";
- reg = <0x1>;
- next-level-cache = <&L2_0>;
-+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+ clock-names = "cpu";
- };
-
- CPU2: cpu@2 {
-@@ -54,6 +59,8 @@
- enable-method = "psci";
- reg = <0x2>;
- next-level-cache = <&L2_0>;
-+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+ clock-names = "cpu";
- };
-
- CPU3: cpu@3 {
-@@ -62,6 +69,8 @@
- enable-method = "psci";
- reg = <0x3>;
- next-level-cache = <&L2_0>;
-+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
-+ clock-names = "cpu";
- };
-
- L2_0: l2-cache {
+++ /dev/null
-From 347ca56e86c99021fad059b9a8ef101245b8507e Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 31 Dec 2021 20:38:06 +0100
-Subject: [PATCH] arm64: dts: ipq8074: add cooling cells to CPU nodes
-
-Since there is CPU Freq support as well as thermal sensor support
-now for the IPQ8074, add cooling cells to CPU nodes so that they can
-be used as cooling devices using CPU Freq.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -41,6 +41,7 @@
- enable-method = "psci";
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
-+ #cooling-cells = <2>;
- };
-
- CPU1: cpu@1 {
-@@ -51,6 +52,7 @@
- next-level-cache = <&L2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
-+ #cooling-cells = <2>;
- };
-
- CPU2: cpu@2 {
-@@ -61,6 +63,7 @@
- next-level-cache = <&L2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
-+ #cooling-cells = <2>;
- };
-
- CPU3: cpu@3 {
-@@ -71,6 +74,7 @@
- next-level-cache = <&L2_0>;
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
-+ #cooling-cells = <2>;
- };
-
- L2_0: l2-cache {
+++ /dev/null
-From 04d2fc6a551bbd972a6428059b45ce79cb9de9d7 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 6 May 2022 22:38:24 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add QFPROM fuses
-
-Add the QFPROM node and CPR fuses.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 107 ++++++++++++++++++++++++++
- 1 file changed, 107 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -343,6 +343,113 @@
- status = "disabled";
- };
-
-+ qfprom: efuse@a4000 {
-+ compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
-+ reg = <0x000a4000 0x1000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ cpr_efuse_speedbin: speedbin@125 {
-+ reg = <0x125 0x1>;
-+ bits = <0 3>;
-+ };
-+
-+ cpr_efuse_boost_cfg: boost_cfg@125 {
-+ reg = <0x125 0x1>;
-+ bits = <3 3>;
-+ };
-+
-+ cpr_efuse_misc_volt_adj: misc_volt_adj@125 {
-+ reg = <0x125 0x1>;
-+ bits = <3 3>;
-+ };
-+
-+ cpr_efuse_boost_volt: boost_volt@126 {
-+ reg = <0x126 0x1>;
-+ bits = <6 1>;
-+ };
-+
-+ cpr_efuse_revision: revision@23e {
-+ reg = <0x23e 0x1>;
-+ bits = <5 3>;
-+ };
-+
-+ cpr_efuse_ro_sel0: rosel0@249 {
-+ reg = <0x249 0x1>;
-+ bits = <0 4>;
-+ };
-+
-+ cpr_efuse_ro_sel1: rosel1@248 {
-+ reg = <0x248 0x1>;
-+ bits = <4 4>;
-+ };
-+
-+ cpr_efuse_ro_sel2: rosel2@248 {
-+ reg = <0x248 0x2>;
-+ bits = <0 4>;
-+ };
-+
-+ cpr_efuse_ro_sel3: rosel3@249 {
-+ reg = <0x249 0x1>;
-+ bits = <4 4>;
-+ };
-+
-+ cpr_efuse_init_voltage0: ivoltage0@23a {
-+ reg = <0x23a 0x1>;
-+ bits = <2 6>;
-+ };
-+
-+ cpr_efuse_init_voltage1: ivoltage1@239 {
-+ reg = <0x239 0x2>;
-+ bits = <4 6>;
-+ };
-+
-+ cpr_efuse_init_voltage2: ivoltage2@238 {
-+ reg = <0x238 0x2>;
-+ bits = <6 6>;
-+ };
-+
-+ cpr_efuse_init_voltage3: ivoltage3@238 {
-+ reg = <0x238 0x1>;
-+ bits = <0 6>;
-+ };
-+
-+ cpr_efuse_quot0: quot0@244 {
-+ reg = <0x244 0x2>;
-+ bits = <0 12>;
-+ };
-+
-+ cpr_efuse_quot1: quot1@242 {
-+ reg = <0x242 0x2>;
-+ bits = <4 12>;
-+ };
-+
-+ cpr_efuse_quot2: quot2@241 {
-+ reg = <0x241 0x2>;
-+ bits = <0 12>;
-+ };
-+
-+ cpr_efuse_quot3: quot3@245 {
-+ reg = <0x245 0x2>;
-+ bits = <4 12>;
-+ };
-+
-+ cpr_efuse_quot0_offset: quot0_offset@23d {
-+ reg = <0x23d 0x2>;
-+ bits = <6 7>;
-+ };
-+
-+ cpr_efuse_quot1_offset: quot1_offset@23c {
-+ reg = <0x23c 0x2>;
-+ bits = <7 7>;
-+ };
-+
-+ cpr_efuse_quot2_offset: quot2_offset@23c {
-+ reg = <0x23c 0x1>;
-+ bits = <0 7>;
-+ };
-+ };
-+
- prng: rng@e3000 {
- compatible = "qcom,prng-ee";
- reg = <0x000e3000 0x1000>;
+++ /dev/null
-From a20c4e8738a00087aa5d53fe5148ed484e23d229 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 31 Dec 2022 13:56:26 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add CPU OPP table
-
-Now that there is NVMEM CPUFreq support for IPQ8074, we can add the OPP
-table for SoC.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 52 +++++++++++++++++++++++++++
- 1 file changed, 52 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -42,6 +42,7 @@
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- #cooling-cells = <2>;
-+ operating-points-v2 = <&cpu_opp_table>;
- };
-
- CPU1: cpu@1 {
-@@ -53,6 +54,7 @@
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- #cooling-cells = <2>;
-+ operating-points-v2 = <&cpu_opp_table>;
- };
-
- CPU2: cpu@2 {
-@@ -64,6 +66,7 @@
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- #cooling-cells = <2>;
-+ operating-points-v2 = <&cpu_opp_table>;
- };
-
- CPU3: cpu@3 {
-@@ -75,6 +78,7 @@
- clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
- clock-names = "cpu";
- #cooling-cells = <2>;
-+ operating-points-v2 = <&cpu_opp_table>;
- };
-
- L2_0: l2-cache {
-@@ -83,6 +87,54 @@
- };
- };
-
-+ cpu_opp_table: opp-table {
-+ compatible = "operating-points-v2-kryo-cpu";
-+ nvmem-cells = <&cpr_efuse_speedbin>;
-+ opp-shared;
-+
-+ opp-1017600000 {
-+ opp-hz = /bits/ 64 <1017600000>;
-+ opp-microvolt = <1>;
-+ opp-supported-hw = <0xf>;
-+ clock-latency-ns = <200000>;
-+ };
-+
-+ opp-1382400000 {
-+ opp-hz = /bits/ 64 <1382400000>;
-+ opp-microvolt = <2>;
-+ opp-supported-hw = <0xf>;
-+ clock-latency-ns = <200000>;
-+ };
-+
-+ opp-1651200000 {
-+ opp-hz = /bits/ 64 <1651200000>;
-+ opp-microvolt = <3>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <200000>;
-+ };
-+
-+ opp-1843200000 {
-+ opp-hz = /bits/ 64 <1843200000>;
-+ opp-microvolt = <4>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <200000>;
-+ };
-+
-+ opp-1920000000 {
-+ opp-hz = /bits/ 64 <1920000000>;
-+ opp-microvolt = <5>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <200000>;
-+ };
-+
-+ opp-2208000000 {
-+ opp-hz = /bits/ 64 <2208000000>;
-+ opp-microvolt = <6>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <200000>;
-+ };
-+ };
-+
- pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+++ /dev/null
-From 9dd19a9ae36bc60d58287d0c52e53024d484e64d Mon Sep 17 00:00:00 2001
-From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
-Date: Fri, 29 Jan 2021 22:41:59 +0530
-Subject: [PATCH 2/3] remoteproc: qcom: wcss: populate driver data for IPQ6018
-
-Populate hardcoded param using driver data for IPQ6018 SoCs.
-
-Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 19 +++++++++++++++++--
- 1 file changed, 17 insertions(+), 2 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -970,7 +970,7 @@ static int q6v5_alloc_memory_region(stru
- return 0;
- }
-
--static int ipq8074_init_clock(struct q6v5_wcss *wcss)
-+static int ipq_init_clock(struct q6v5_wcss *wcss)
- {
- int ret;
-
-@@ -1179,7 +1179,7 @@ static int q6v5_wcss_remove(struct platf
- }
-
- static const struct wcss_data wcss_ipq8074_res_init = {
-- .init_clock = ipq8074_init_clock,
-+ .init_clock = ipq_init_clock,
- .q6_firmware_name = "IPQ8074/q6_fw.mdt",
- .m3_firmware_name = "IPQ8074/m3_fw.mdt",
- .crash_reason_smem = WCSS_CRASH_REASON,
-@@ -1193,6 +1193,20 @@ static const struct wcss_data wcss_ipq80
- .need_auto_boot = false,
- };
-
-+static const struct wcss_data wcss_ipq6018_res_init = {
-+ .init_clock = ipq_init_clock,
-+ .q6_firmware_name = "IPQ6018/q6_fw.mdt",
-+ .m3_firmware_name = "IPQ6018/m3_fw.mdt",
-+ .crash_reason_smem = WCSS_CRASH_REASON,
-+ .aon_reset_required = true,
-+ .wcss_q6_reset_required = true,
-+ .bcr_reset_required = false,
-+ .ssr_name = "q6wcss",
-+ .ops = &q6v5_wcss_ipq8074_ops,
-+ .requires_force_stop = true,
-+ .need_mem_protection = true,
-+};
-+
- static const struct wcss_data wcss_qcs404_res_init = {
- .init_clock = qcs404_init_clock,
- .init_regulator = qcs404_init_regulator,
-@@ -1212,6 +1226,7 @@ static const struct wcss_data wcss_qcs40
-
- static const struct of_device_id q6v5_wcss_of_match[] = {
- { .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
-+ { .compatible = "qcom,ipq6018-wcss-pil", .data = &wcss_ipq6018_res_init },
- { .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init },
- { },
- };
+++ /dev/null
-From e4d7544ce092807e8c5aeb618cec30e2eb9b40c2 Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Mon, 24 Apr 2023 15:13:32 +0300
-Subject: [PATCH 3/3] arm64: dts: qcom: ipq6018: add SDHCI node
-
-IPQ6018 has one SD/eMMC controller, add node for it.
-
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
-Tested-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -469,6 +469,29 @@
- };
- };
-
-+ sdhc_1: mmc@7804000 {
-+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
-+ reg = <0x0 0x07804000 0x0 0x1000>,
-+ <0x0 0x07805000 0x0 0x1000>,
-+ <0x0 0x07808000 0x0 0x2000>;
-+ reg-names = "hc", "cqhci", "ice";
-+
-+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "hc_irq", "pwr_irq";
-+
-+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
-+ <&gcc GCC_SDCC1_APPS_CLK>,
-+ <&xo>,
-+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
-+ clock-names = "iface", "core", "xo", "ice";
-+
-+ resets = <&gcc GCC_SDCC1_BCR>;
-+ supports-cqe;
-+ bus-width = <8>;
-+ status = "disabled";
-+ };
-+
- blsp_dma: dma-controller@7884000 {
- compatible = "qcom,bam-v1.7.0";
- reg = <0x0 0x07884000 0x0 0x2b000>;
+++ /dev/null
-From d24bc08bfc66f47d6e0a294a080d62893a7696b5 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Thu, 18 Jan 2024 21:30:21 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq6018: add LDOA2 regulator
-
-Add LDOA2 regulator of MP5496 to support SDCC voltage scaling.
-
-Suggested-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -178,6 +178,11 @@
- regulator-max-microvolt = <1062500>;
- regulator-always-on;
- };
-+
-+ ipq6018_l2: l2 {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
- };
- };
- };
+++ /dev/null
-From 8d8b37d3af2bdccf0a37d2017d876bfc6ce42552 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Fri, 20 Oct 2023 23:18:21 +0800
-Subject: [PATCH 1/1] mtd: rawnand: add support for TH58NYG3S0HBAI4 NAND flash
-
-The Toshiba TH58NYG3S0HBAI4 is detected with 128 byte OOB while the flash
-has 256 bytes OOB. Since it is not an ONFI compliant NAND, the model name
-cannot be read from anywhere, add a static NAND ID entry to correct this.
-
-However, the NAND ID of this flash is inconsistent with the datasheet.
-The actual NAND ID is only 4 ID bytes, the last ID byte is missing.
-
-Datasheet available at (the ID table is on page 50):
-https://europe.kioxia.com/content/dam/kioxia/newidr/productinfo/datasheet/201910/DST_TH58NYG3S0HBAI4-TDE_EN_31565.pdf
-
-Datasheet NAND ID: {0x98, 0xa3, 0x91, 0x26, 0x76}
-Actual NAND ID: {0x98, 0xa3, 0x91, 0x26}
-
-It seems that this flash may be counterfeit, but another Toshiba flash
-also has the same problem. Maybe the driver has a bug, or some Toshiba
-nand flash is like this. Anyway, add a static NAND ID entry with only
-4 ID bytes as a hack to make sure it works.
-
-Tested on Arcadyan AW1000 flashed with OpenWrt.
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
----
- drivers/mtd/nand/raw/nand_ids.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/mtd/nand/raw/nand_ids.c
-+++ b/drivers/mtd/nand/raw/nand_ids.c
-@@ -55,6 +55,9 @@ struct nand_flash_dev nand_flash_ids[] =
- { .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} },
- SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664,
- NAND_ECC_INFO(40, SZ_1K) },
-+ {"TH58NYG3S0HBAI4 8G 1.8V 8-bit", /* Last ID bytes missing */
-+ { .id = {0x98, 0xa3, 0x91, 0x26} },
-+ SZ_4K, SZ_1K, SZ_256K, 0, 4, 256, NAND_ECC_INFO(8, SZ_512) },
- {"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
- { .id = {0x98, 0xdc, 0x91, 0x15, 0x76} },
- SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512) },
+++ /dev/null
-From 6c98adf98236b8644b8f5e1aa7af9f1a88ea2766 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 11 Apr 2022 14:38:08 +0200
-Subject: [PATCH] power: Add Qualcomm APM
-
-Add Qualcomm APM driver, which allows scaling cache and memory fabrics.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/power/Kconfig | 1 +
- drivers/power/Makefile | 1 +
- drivers/power/qcom/Kconfig | 7 +
- drivers/power/qcom/Makefile | 1 +
- drivers/power/qcom/apm.c | 944 +++++++++++++++++++++++++++++++++
- include/linux/power/qcom/apm.h | 48 ++
- 6 files changed, 1002 insertions(+)
- create mode 100644 drivers/power/qcom/Kconfig
- create mode 100644 drivers/power/qcom/Makefile
- create mode 100644 drivers/power/qcom/apm.c
- create mode 100644 include/linux/power/qcom/apm.h
-
---- a/drivers/power/Kconfig
-+++ b/drivers/power/Kconfig
-@@ -1,3 +1,4 @@
- # SPDX-License-Identifier: GPL-2.0-only
- source "drivers/power/reset/Kconfig"
- source "drivers/power/supply/Kconfig"
-+source "drivers/power/qcom/Kconfig"
---- a/drivers/power/Makefile
-+++ b/drivers/power/Makefile
-@@ -1,3 +1,4 @@
- # SPDX-License-Identifier: GPL-2.0-only
- obj-$(CONFIG_POWER_RESET) += reset/
- obj-$(CONFIG_POWER_SUPPLY) += supply/
-+obj-$(CONFIG_QCOM_APM) += qcom/
---- /dev/null
-+++ b/drivers/power/qcom/Kconfig
-@@ -0,0 +1,7 @@
-+config QCOM_APM
-+ bool "Qualcomm Technologies Inc platform specific APM driver"
-+ help
-+ Platform specific driver to manage the power source of
-+ memory arrays. Interfaces with regulator drivers to ensure
-+ SRAM Vmin requirements are met across different performance
-+ levels.
---- /dev/null
-+++ b/drivers/power/qcom/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_QCOM_APM) += apm.o
---- /dev/null
-+++ b/drivers/power/qcom/apm.c
-@@ -0,0 +1,944 @@
-+/*
-+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#define pr_fmt(fmt) "%s: " fmt, __func__
-+
-+#include <linux/debugfs.h>
-+#include <linux/delay.h>
-+#include <linux/of_device.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/string.h>
-+#include <linux/power/qcom/apm.h>
-+
-+/*
-+ * VDD_APCC
-+ * =============================================================
-+ * | VDD_MX | |
-+ * | ==========================|============= |
-+ * ___|___ ___|___ ___|___ ___|___ ___|___ ___|___
-+ * | | | | | | | | | | | |
-+ * | APCC | | MX HS | | MX HS | | APCC | | MX HS | | APCC |
-+ * | HS | | | | | | HS | | | | HS |
-+ * |_______| |_______| |_______| |_______| |_______| |_______|
-+ * |_________| |_________| |__________|
-+ * | | |
-+ * ______|_____ ______|_____ _______|_____
-+ * | | | | | |
-+ * | | | | | |
-+ * | CPU MEM | | L2 MEM | | L3 MEM |
-+ * | Arrays | | Arrays | | Arrays |
-+ * | | | | | |
-+ * |____________| |____________| |_____________|
-+ *
-+ */
-+
-+/* Register value definitions */
-+#define APCS_GFMUXA_SEL_VAL 0x13
-+#define APCS_GFMUXA_DESEL_VAL 0x03
-+#define MSM_APM_MX_MODE_VAL 0x00
-+#define MSM_APM_APCC_MODE_VAL 0x10
-+#define MSM_APM_MX_DONE_VAL 0x00
-+#define MSM_APM_APCC_DONE_VAL 0x03
-+#define MSM_APM_OVERRIDE_SEL_VAL 0xb0
-+#define MSM_APM_SEC_CLK_SEL_VAL 0x30
-+#define SPM_EVENT_SET_VAL 0x01
-+#define SPM_EVENT_CLEAR_VAL 0x00
-+
-+/* Register bit mask definitions */
-+#define MSM_APM_CTL_STS_MASK 0x0f
-+
-+/* Register offset definitions */
-+#define APCC_APM_MODE 0x00000098
-+#define APCC_APM_CTL_STS 0x000000a8
-+#define APCS_SPARE 0x00000068
-+#define APCS_VERSION 0x00000fd0
-+
-+#define HMSS_VERSION_1P2 0x10020000
-+
-+#define MSM_APM_SWITCH_TIMEOUT_US 10
-+#define SPM_WAKEUP_DELAY_US 2
-+#define SPM_EVENT_NUM 6
-+
-+#define MSM_APM_DRIVER_NAME "qcom,msm-apm"
-+
-+enum {
-+ MSM8996_ID,
-+ MSM8953_ID,
-+ IPQ807x_ID,
-+};
-+
-+struct msm_apm_ctrl_dev {
-+ struct list_head list;
-+ struct device *dev;
-+ enum msm_apm_supply supply;
-+ spinlock_t lock;
-+ void __iomem *reg_base;
-+ void __iomem *apcs_csr_base;
-+ void __iomem **apcs_spm_events_addr;
-+ void __iomem *apc0_pll_ctl_addr;
-+ void __iomem *apc1_pll_ctl_addr;
-+ u32 version;
-+ struct dentry *debugfs;
-+ u32 msm_id;
-+};
-+
-+#if defined(CONFIG_DEBUG_FS)
-+static struct dentry *apm_debugfs_base;
-+#endif
-+
-+static DEFINE_MUTEX(apm_ctrl_list_mutex);
-+static LIST_HEAD(apm_ctrl_list);
-+
-+/*
-+ * Get the resources associated with the APM controller from device tree
-+ * and remap all I/O addresses that are relevant to this HW revision.
-+ */
-+static int msm_apm_ctrl_devm_ioremap(struct platform_device *pdev,
-+ struct msm_apm_ctrl_dev *ctrl)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct resource *res;
-+ static const char *res_name[SPM_EVENT_NUM] = {
-+ "apc0-l2-spm",
-+ "apc1-l2-spm",
-+ "apc0-cpu0-spm",
-+ "apc0-cpu1-spm",
-+ "apc1-cpu0-spm",
-+ "apc1-cpu1-spm"
-+ };
-+ int i, ret = 0;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb");
-+ if (!res) {
-+ dev_err(dev, "Missing PM APCC Global register physical address");
-+ return -EINVAL;
-+ }
-+ ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res));
-+ if (!ctrl->reg_base) {
-+ dev_err(dev, "Failed to map PM APCC Global registers\n");
-+ return -ENOMEM;
-+ }
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs-csr");
-+ if (!res) {
-+ dev_err(dev, "Missing APCS CSR physical base address");
-+ return -EINVAL;
-+ }
-+ ctrl->apcs_csr_base = devm_ioremap(dev, res->start, resource_size(res));
-+ if (!ctrl->apcs_csr_base) {
-+ dev_err(dev, "Failed to map APCS CSR registers\n");
-+ return -ENOMEM;
-+ }
-+
-+ ctrl->version = readl_relaxed(ctrl->apcs_csr_base + APCS_VERSION);
-+
-+ if (ctrl->version >= HMSS_VERSION_1P2)
-+ return ret;
-+
-+ ctrl->apcs_spm_events_addr = devm_kzalloc(&pdev->dev,
-+ SPM_EVENT_NUM
-+ * sizeof(void __iomem *),
-+ GFP_KERNEL);
-+ if (!ctrl->apcs_spm_events_addr) {
-+ dev_err(dev, "Failed to allocate memory for APCS SPM event registers\n");
-+ return -ENOMEM;
-+ }
-+
-+ for (i = 0; i < SPM_EVENT_NUM; i++) {
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-+ res_name[i]);
-+ if (!res) {
-+ dev_err(dev, "Missing address for %s\n", res_name[i]);
-+ ret = -EINVAL;
-+ goto free_events;
-+ }
-+
-+ ctrl->apcs_spm_events_addr[i] = devm_ioremap(dev, res->start,
-+ resource_size(res));
-+ if (!ctrl->apcs_spm_events_addr[i]) {
-+ dev_err(dev, "Failed to map %s\n", res_name[i]);
-+ ret = -ENOMEM;
-+ goto free_events;
-+ }
-+
-+ dev_dbg(dev, "%s event phys: %pa virt:0x%p\n", res_name[i],
-+ &res->start, ctrl->apcs_spm_events_addr[i]);
-+ }
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-+ "apc0-pll-ctl");
-+ if (!res) {
-+ dev_err(dev, "Missing APC0 PLL CTL physical address\n");
-+ ret = -EINVAL;
-+ goto free_events;
-+ }
-+
-+ ctrl->apc0_pll_ctl_addr = devm_ioremap(dev,
-+ res->start,
-+ resource_size(res));
-+ if (!ctrl->apc0_pll_ctl_addr) {
-+ dev_err(dev, "Failed to map APC0 PLL CTL register\n");
-+ ret = -ENOMEM;
-+ goto free_events;
-+ }
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-+ "apc1-pll-ctl");
-+ if (!res) {
-+ dev_err(dev, "Missing APC1 PLL CTL physical address\n");
-+ ret = -EINVAL;
-+ goto free_events;
-+ }
-+
-+ ctrl->apc1_pll_ctl_addr = devm_ioremap(dev,
-+ res->start,
-+ resource_size(res));
-+ if (!ctrl->apc1_pll_ctl_addr) {
-+ dev_err(dev, "Failed to map APC1 PLL CTL register\n");
-+ ret = -ENOMEM;
-+ goto free_events;
-+ }
-+
-+ return ret;
-+
-+free_events:
-+ devm_kfree(dev, ctrl->apcs_spm_events_addr);
-+ return ret;
-+}
-+
-+/* 8953 register offset definition */
-+#define MSM8953_APM_DLY_CNTR 0x2ac
-+
-+/* Register field shift definitions */
-+#define APM_CTL_SEL_SWITCH_DLY_SHIFT 0
-+#define APM_CTL_RESUME_CLK_DLY_SHIFT 8
-+#define APM_CTL_HALT_CLK_DLY_SHIFT 16
-+#define APM_CTL_POST_HALT_DLY_SHIFT 24
-+
-+/* Register field mask definitions */
-+#define APM_CTL_SEL_SWITCH_DLY_MASK GENMASK(7, 0)
-+#define APM_CTL_RESUME_CLK_DLY_MASK GENMASK(15, 8)
-+#define APM_CTL_HALT_CLK_DLY_MASK GENMASK(23, 16)
-+#define APM_CTL_POST_HALT_DLY_MASK GENMASK(31, 24)
-+
-+/*
-+ * Get the resources associated with the msm8953 APM controller from
-+ * device tree, remap all I/O addresses, and program the initial
-+ * register configuration required for the 8953 APM controller device.
-+ */
-+static int msm8953_apm_ctrl_init(struct platform_device *pdev,
-+ struct msm_apm_ctrl_dev *ctrl)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct resource *res;
-+ u32 delay_counter, val = 0, regval = 0;
-+ int rc = 0;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb");
-+ if (!res) {
-+ dev_err(dev, "Missing PM APCC Global register physical address\n");
-+ return -ENODEV;
-+ }
-+ ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res));
-+ if (!ctrl->reg_base) {
-+ dev_err(dev, "Failed to map PM APCC Global registers\n");
-+ return -ENOMEM;
-+ }
-+
-+ /*
-+ * Initial APM register configuration required before starting
-+ * APM HW controller.
-+ */
-+ regval = readl_relaxed(ctrl->reg_base + MSM8953_APM_DLY_CNTR);
-+ val = regval;
-+
-+ if (of_find_property(dev->of_node, "qcom,apm-post-halt-delay", NULL)) {
-+ rc = of_property_read_u32(dev->of_node,
-+ "qcom,apm-post-halt-delay", &delay_counter);
-+ if (rc < 0) {
-+ dev_err(dev, "apm-post-halt-delay read failed, rc = %d",
-+ rc);
-+ return rc;
-+ }
-+
-+ val &= ~APM_CTL_POST_HALT_DLY_MASK;
-+ val |= (delay_counter << APM_CTL_POST_HALT_DLY_SHIFT)
-+ & APM_CTL_POST_HALT_DLY_MASK;
-+ }
-+
-+ if (of_find_property(dev->of_node, "qcom,apm-halt-clk-delay", NULL)) {
-+ rc = of_property_read_u32(dev->of_node,
-+ "qcom,apm-halt-clk-delay", &delay_counter);
-+ if (rc < 0) {
-+ dev_err(dev, "apm-halt-clk-delay read failed, rc = %d",
-+ rc);
-+ return rc;
-+ }
-+
-+ val &= ~APM_CTL_HALT_CLK_DLY_MASK;
-+ val |= (delay_counter << APM_CTL_HALT_CLK_DLY_SHIFT)
-+ & APM_CTL_HALT_CLK_DLY_MASK;
-+ }
-+
-+ if (of_find_property(dev->of_node, "qcom,apm-resume-clk-delay", NULL)) {
-+ rc = of_property_read_u32(dev->of_node,
-+ "qcom,apm-resume-clk-delay", &delay_counter);
-+ if (rc < 0) {
-+ dev_err(dev, "apm-resume-clk-delay read failed, rc = %d",
-+ rc);
-+ return rc;
-+ }
-+
-+ val &= ~APM_CTL_RESUME_CLK_DLY_MASK;
-+ val |= (delay_counter << APM_CTL_RESUME_CLK_DLY_SHIFT)
-+ & APM_CTL_RESUME_CLK_DLY_MASK;
-+ }
-+
-+ if (of_find_property(dev->of_node, "qcom,apm-sel-switch-delay", NULL)) {
-+ rc = of_property_read_u32(dev->of_node,
-+ "qcom,apm-sel-switch-delay", &delay_counter);
-+ if (rc < 0) {
-+ dev_err(dev, "apm-sel-switch-delay read failed, rc = %d",
-+ rc);
-+ return rc;
-+ }
-+
-+ val &= ~APM_CTL_SEL_SWITCH_DLY_MASK;
-+ val |= (delay_counter << APM_CTL_SEL_SWITCH_DLY_SHIFT)
-+ & APM_CTL_SEL_SWITCH_DLY_MASK;
-+ }
-+
-+ if (val != regval) {
-+ writel_relaxed(val, ctrl->reg_base + MSM8953_APM_DLY_CNTR);
-+ /* make sure write completes before return */
-+ mb();
-+ }
-+
-+ return rc;
-+}
-+
-+static int msm8996_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
-+{
-+ int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
-+ u32 regval;
-+ int ret = 0;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&ctrl_dev->lock, flags);
-+
-+ /* Perform revision-specific programming steps */
-+ if (ctrl_dev->version < HMSS_VERSION_1P2) {
-+ /* Clear SPM events */
-+ for (i = 0; i < SPM_EVENT_NUM; i++)
-+ writel_relaxed(SPM_EVENT_CLEAR_VAL,
-+ ctrl_dev->apcs_spm_events_addr[i]);
-+
-+ udelay(SPM_WAKEUP_DELAY_US);
-+
-+ /* Switch APC/CBF to GPLL0 clock */
-+ writel_relaxed(APCS_GFMUXA_SEL_VAL,
-+ ctrl_dev->apcs_csr_base + APCS_SPARE);
-+ ndelay(200);
-+ writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
-+ ctrl_dev->apc0_pll_ctl_addr);
-+ ndelay(200);
-+ writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
-+ ctrl_dev->apc1_pll_ctl_addr);
-+
-+ /* Ensure writes complete before proceeding */
-+ mb();
-+ }
-+
-+ /* Switch arrays to MX supply and wait for its completion */
-+ writel_relaxed(MSM_APM_MX_MODE_VAL, ctrl_dev->reg_base +
-+ APCC_APM_MODE);
-+
-+ /* Ensure write above completes before delaying */
-+ mb();
-+
-+ while (timeout > 0) {
-+ regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
-+ if ((regval & MSM_APM_CTL_STS_MASK) ==
-+ MSM_APM_MX_DONE_VAL)
-+ break;
-+
-+ udelay(1);
-+ timeout--;
-+ }
-+
-+ if (timeout == 0) {
-+ ret = -ETIMEDOUT;
-+ dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
-+ regval);
-+ }
-+
-+ /* Perform revision-specific programming steps */
-+ if (ctrl_dev->version < HMSS_VERSION_1P2) {
-+ /* Switch APC/CBF clocks to original source */
-+ writel_relaxed(APCS_GFMUXA_DESEL_VAL,
-+ ctrl_dev->apcs_csr_base + APCS_SPARE);
-+ ndelay(200);
-+ writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
-+ ctrl_dev->apc0_pll_ctl_addr);
-+ ndelay(200);
-+ writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
-+ ctrl_dev->apc1_pll_ctl_addr);
-+
-+ /* Complete clock source switch before SPM event sequence */
-+ mb();
-+
-+ /* Set SPM events */
-+ for (i = 0; i < SPM_EVENT_NUM; i++)
-+ writel_relaxed(SPM_EVENT_SET_VAL,
-+ ctrl_dev->apcs_spm_events_addr[i]);
-+ }
-+
-+ if (!ret) {
-+ ctrl_dev->supply = MSM_APM_SUPPLY_MX;
-+ dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n");
-+ }
-+
-+ spin_unlock_irqrestore(&ctrl_dev->lock, flags);
-+
-+ return ret;
-+}
-+
-+static int msm8996_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
-+{
-+ int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
-+ u32 regval;
-+ int ret = 0;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&ctrl_dev->lock, flags);
-+
-+ /* Perform revision-specific programming steps */
-+ if (ctrl_dev->version < HMSS_VERSION_1P2) {
-+ /* Clear SPM events */
-+ for (i = 0; i < SPM_EVENT_NUM; i++)
-+ writel_relaxed(SPM_EVENT_CLEAR_VAL,
-+ ctrl_dev->apcs_spm_events_addr[i]);
-+
-+ udelay(SPM_WAKEUP_DELAY_US);
-+
-+ /* Switch APC/CBF to GPLL0 clock */
-+ writel_relaxed(APCS_GFMUXA_SEL_VAL,
-+ ctrl_dev->apcs_csr_base + APCS_SPARE);
-+ ndelay(200);
-+ writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
-+ ctrl_dev->apc0_pll_ctl_addr);
-+ ndelay(200);
-+ writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
-+ ctrl_dev->apc1_pll_ctl_addr);
-+
-+ /* Ensure previous writes complete before proceeding */
-+ mb();
-+ }
-+
-+ /* Switch arrays to APCC supply and wait for its completion */
-+ writel_relaxed(MSM_APM_APCC_MODE_VAL, ctrl_dev->reg_base +
-+ APCC_APM_MODE);
-+
-+ /* Ensure write above completes before delaying */
-+ mb();
-+
-+ while (timeout > 0) {
-+ regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
-+ if ((regval & MSM_APM_CTL_STS_MASK) ==
-+ MSM_APM_APCC_DONE_VAL)
-+ break;
-+
-+ udelay(1);
-+ timeout--;
-+ }
-+
-+ if (timeout == 0) {
-+ ret = -ETIMEDOUT;
-+ dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
-+ regval);
-+ }
-+
-+ /* Perform revision-specific programming steps */
-+ if (ctrl_dev->version < HMSS_VERSION_1P2) {
-+ /* Set SPM events */
-+ for (i = 0; i < SPM_EVENT_NUM; i++)
-+ writel_relaxed(SPM_EVENT_SET_VAL,
-+ ctrl_dev->apcs_spm_events_addr[i]);
-+
-+ /* Complete SPM event sequence before clock source switch */
-+ mb();
-+
-+ /* Switch APC/CBF clocks to original source */
-+ writel_relaxed(APCS_GFMUXA_DESEL_VAL,
-+ ctrl_dev->apcs_csr_base + APCS_SPARE);
-+ ndelay(200);
-+ writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
-+ ctrl_dev->apc0_pll_ctl_addr);
-+ ndelay(200);
-+ writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
-+ ctrl_dev->apc1_pll_ctl_addr);
-+ }
-+
-+ if (!ret) {
-+ ctrl_dev->supply = MSM_APM_SUPPLY_APCC;
-+ dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n");
-+ }
-+
-+ spin_unlock_irqrestore(&ctrl_dev->lock, flags);
-+
-+ return ret;
-+}
-+
-+/* 8953 register value definitions */
-+#define MSM8953_APM_MX_MODE_VAL 0x00
-+#define MSM8953_APM_APCC_MODE_VAL 0x02
-+#define MSM8953_APM_MX_DONE_VAL 0x00
-+#define MSM8953_APM_APCC_DONE_VAL 0x03
-+
-+/* 8953 register offset definitions */
-+#define MSM8953_APCC_APM_MODE 0x000002a8
-+#define MSM8953_APCC_APM_CTL_STS 0x000002b0
-+
-+/* 8953 constants */
-+#define MSM8953_APM_SWITCH_TIMEOUT_US 500
-+
-+/* Register bit mask definitions */
-+#define MSM8953_APM_CTL_STS_MASK 0x1f
-+
-+static int msm8953_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
-+{
-+ int timeout = MSM8953_APM_SWITCH_TIMEOUT_US;
-+ u32 regval;
-+ int ret = 0;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&ctrl_dev->lock, flags);
-+
-+ /* Switch arrays to MX supply and wait for its completion */
-+ writel_relaxed(MSM8953_APM_MX_MODE_VAL, ctrl_dev->reg_base +
-+ MSM8953_APCC_APM_MODE);
-+
-+ /* Ensure write above completes before delaying */
-+ mb();
-+
-+ while (timeout > 0) {
-+ regval = readl_relaxed(ctrl_dev->reg_base +
-+ MSM8953_APCC_APM_CTL_STS);
-+ if ((regval & MSM8953_APM_CTL_STS_MASK) ==
-+ MSM8953_APM_MX_DONE_VAL)
-+ break;
-+
-+ udelay(1);
-+ timeout--;
-+ }
-+
-+ if (timeout == 0) {
-+ ret = -ETIMEDOUT;
-+ dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
-+ regval);
-+ } else {
-+ ctrl_dev->supply = MSM_APM_SUPPLY_MX;
-+ dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n");
-+ }
-+
-+ spin_unlock_irqrestore(&ctrl_dev->lock, flags);
-+
-+ return ret;
-+}
-+
-+static int msm8953_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
-+{
-+ int timeout = MSM8953_APM_SWITCH_TIMEOUT_US;
-+ u32 regval;
-+ int ret = 0;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&ctrl_dev->lock, flags);
-+
-+ /* Switch arrays to APCC supply and wait for its completion */
-+ writel_relaxed(MSM8953_APM_APCC_MODE_VAL, ctrl_dev->reg_base +
-+ MSM8953_APCC_APM_MODE);
-+
-+ /* Ensure write above completes before delaying */
-+ mb();
-+
-+ while (timeout > 0) {
-+ regval = readl_relaxed(ctrl_dev->reg_base +
-+ MSM8953_APCC_APM_CTL_STS);
-+ if ((regval & MSM8953_APM_CTL_STS_MASK) ==
-+ MSM8953_APM_APCC_DONE_VAL)
-+ break;
-+
-+ udelay(1);
-+ timeout--;
-+ }
-+
-+ if (timeout == 0) {
-+ ret = -ETIMEDOUT;
-+ dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
-+ regval);
-+ } else {
-+ ctrl_dev->supply = MSM_APM_SUPPLY_APCC;
-+ dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n");
-+ }
-+
-+ spin_unlock_irqrestore(&ctrl_dev->lock, flags);
-+
-+ return ret;
-+}
-+
-+static int msm_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
-+{
-+ int ret = 0;
-+
-+ switch (ctrl_dev->msm_id) {
-+ case MSM8996_ID:
-+ ret = msm8996_apm_switch_to_mx(ctrl_dev);
-+ break;
-+ case MSM8953_ID:
-+ case IPQ807x_ID:
-+ ret = msm8953_apm_switch_to_mx(ctrl_dev);
-+ break;
-+ }
-+
-+ return ret;
-+}
-+
-+static int msm_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
-+{
-+ int ret = 0;
-+
-+ switch (ctrl_dev->msm_id) {
-+ case MSM8996_ID:
-+ ret = msm8996_apm_switch_to_apcc(ctrl_dev);
-+ break;
-+ case MSM8953_ID:
-+ case IPQ807x_ID:
-+ ret = msm8953_apm_switch_to_apcc(ctrl_dev);
-+ break;
-+ }
-+
-+ return ret;
-+}
-+
-+/**
-+ * msm_apm_get_supply() - Returns the supply that is currently
-+ * powering the memory arrays
-+ * @ctrl_dev: Pointer to an MSM APM controller device
-+ *
-+ * Returns the supply currently selected by the APM.
-+ */
-+int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev)
-+{
-+ return ctrl_dev->supply;
-+}
-+EXPORT_SYMBOL(msm_apm_get_supply);
-+
-+/**
-+ * msm_apm_set_supply() - Perform the necessary steps to switch the voltage
-+ * source of the memory arrays to a given supply
-+ * @ctrl_dev: Pointer to an MSM APM controller device
-+ * @supply: Power rail to use as supply for the memory
-+ * arrays
-+ *
-+ * Returns 0 on success, -ETIMEDOUT on APM switch timeout, or -EPERM if
-+ * the supply is not supported.
-+ */
-+int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
-+ enum msm_apm_supply supply)
-+{
-+ int ret;
-+
-+ switch (supply) {
-+ case MSM_APM_SUPPLY_APCC:
-+ ret = msm_apm_switch_to_apcc(ctrl_dev);
-+ break;
-+ case MSM_APM_SUPPLY_MX:
-+ ret = msm_apm_switch_to_mx(ctrl_dev);
-+ break;
-+ default:
-+ ret = -EPERM;
-+ break;
-+ }
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL(msm_apm_set_supply);
-+
-+/**
-+ * msm_apm_ctrl_dev_get() - get a handle to the MSM APM controller linked to
-+ * the device in device tree
-+ * @dev: Pointer to the device
-+ *
-+ * The device must specify "qcom,apm-ctrl" property in its device tree
-+ * node which points to an MSM APM controller device node.
-+ *
-+ * Returns an MSM APM controller handle if successful or ERR_PTR on any error.
-+ * If the APM controller device hasn't probed yet, ERR_PTR(-EPROBE_DEFER) is
-+ * returned.
-+ */
-+struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev)
-+{
-+ struct msm_apm_ctrl_dev *ctrl_dev = NULL;
-+ struct msm_apm_ctrl_dev *dev_found = ERR_PTR(-EPROBE_DEFER);
-+ struct device_node *ctrl_node;
-+
-+ if (!dev || !dev->of_node) {
-+ pr_err("Invalid device node\n");
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ ctrl_node = of_parse_phandle(dev->of_node, "qcom,apm-ctrl", 0);
-+ if (!ctrl_node) {
-+ pr_err("Could not find qcom,apm-ctrl property in %s\n",
-+ dev->of_node->full_name);
-+ return ERR_PTR(-ENXIO);
-+ }
-+
-+ mutex_lock(&apm_ctrl_list_mutex);
-+ list_for_each_entry(ctrl_dev, &apm_ctrl_list, list) {
-+ if (ctrl_dev->dev && ctrl_dev->dev->of_node == ctrl_node) {
-+ dev_found = ctrl_dev;
-+ break;
-+ }
-+ }
-+ mutex_unlock(&apm_ctrl_list_mutex);
-+
-+ of_node_put(ctrl_node);
-+ return dev_found;
-+}
-+EXPORT_SYMBOL(msm_apm_ctrl_dev_get);
-+
-+#if defined(CONFIG_DEBUG_FS)
-+
-+static int apm_supply_dbg_open(struct inode *inode, struct file *filep)
-+{
-+ filep->private_data = inode->i_private;
-+
-+ return 0;
-+}
-+
-+static ssize_t apm_supply_dbg_read(struct file *filep, char __user *ubuf,
-+ size_t count, loff_t *ppos)
-+{
-+ struct msm_apm_ctrl_dev *ctrl_dev = filep->private_data;
-+ char buf[10];
-+ int len;
-+
-+ if (!ctrl_dev) {
-+ pr_err("invalid apm ctrl handle\n");
-+ return -ENODEV;
-+ }
-+
-+ if (ctrl_dev->supply == MSM_APM_SUPPLY_APCC)
-+ len = snprintf(buf, sizeof(buf), "APCC\n");
-+ else if (ctrl_dev->supply == MSM_APM_SUPPLY_MX)
-+ len = snprintf(buf, sizeof(buf), "MX\n");
-+ else
-+ len = snprintf(buf, sizeof(buf), "ERR\n");
-+
-+ return simple_read_from_buffer(ubuf, count, ppos, buf, len);
-+}
-+
-+static const struct file_operations apm_supply_fops = {
-+ .open = apm_supply_dbg_open,
-+ .read = apm_supply_dbg_read,
-+};
-+
-+static void apm_debugfs_base_init(void)
-+{
-+ apm_debugfs_base = debugfs_create_dir("msm-apm", NULL);
-+
-+ if (IS_ERR_OR_NULL(apm_debugfs_base))
-+ pr_err("msm-apm debugfs base directory creation failed\n");
-+}
-+
-+static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
-+{
-+ struct dentry *temp;
-+
-+ if (IS_ERR_OR_NULL(apm_debugfs_base)) {
-+ pr_err("Base directory missing, cannot create apm debugfs nodes\n");
-+ return;
-+ }
-+
-+ ctrl_dev->debugfs = debugfs_create_dir(dev_name(ctrl_dev->dev),
-+ apm_debugfs_base);
-+ if (IS_ERR_OR_NULL(ctrl_dev->debugfs)) {
-+ pr_err("%s debugfs directory creation failed\n",
-+ dev_name(ctrl_dev->dev));
-+ return;
-+ }
-+
-+ temp = debugfs_create_file("supply", S_IRUGO, ctrl_dev->debugfs,
-+ ctrl_dev, &apm_supply_fops);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ pr_err("supply mode creation failed\n");
-+ return;
-+ }
-+}
-+
-+static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
-+{
-+ if (!IS_ERR_OR_NULL(ctrl_dev->debugfs))
-+ debugfs_remove_recursive(ctrl_dev->debugfs);
-+}
-+
-+static void apm_debugfs_base_remove(void)
-+{
-+ debugfs_remove_recursive(apm_debugfs_base);
-+}
-+#else
-+
-+static void apm_debugfs_base_init(void)
-+{}
-+
-+static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
-+{}
-+
-+static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
-+{}
-+
-+static void apm_debugfs_base_remove(void)
-+{}
-+
-+#endif
-+
-+static struct of_device_id msm_apm_match_table[] = {
-+ {
-+ .compatible = "qcom,msm-apm",
-+ .data = (void *)(uintptr_t)MSM8996_ID,
-+ },
-+ {
-+ .compatible = "qcom,msm8953-apm",
-+ .data = (void *)(uintptr_t)MSM8953_ID,
-+ },
-+ {
-+ .compatible = "qcom,ipq807x-apm",
-+ .data = (void *)(uintptr_t)IPQ807x_ID,
-+ },
-+ {}
-+};
-+
-+static int msm_apm_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct msm_apm_ctrl_dev *ctrl;
-+ const struct of_device_id *match;
-+ int ret = 0;
-+
-+ dev_dbg(dev, "probing MSM Array Power Mux driver\n");
-+
-+ if (!dev->of_node) {
-+ dev_err(dev, "Device tree node is missing\n");
-+ return -ENODEV;
-+ }
-+
-+ match = of_match_device(msm_apm_match_table, dev);
-+ if (!match)
-+ return -ENODEV;
-+
-+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
-+ if (!ctrl) {
-+ dev_err(dev, "MSM APM controller memory allocation failed\n");
-+ return -ENOMEM;
-+ }
-+
-+ INIT_LIST_HEAD(&ctrl->list);
-+ spin_lock_init(&ctrl->lock);
-+ ctrl->dev = dev;
-+ ctrl->msm_id = (uintptr_t)match->data;
-+ platform_set_drvdata(pdev, ctrl);
-+
-+ switch (ctrl->msm_id) {
-+ case MSM8996_ID:
-+ ret = msm_apm_ctrl_devm_ioremap(pdev, ctrl);
-+ if (ret) {
-+ dev_err(dev, "Failed to add APM controller device\n");
-+ return ret;
-+ }
-+ break;
-+ case MSM8953_ID:
-+ case IPQ807x_ID:
-+ ret = msm8953_apm_ctrl_init(pdev, ctrl);
-+ if (ret) {
-+ dev_err(dev, "Failed to initialize APM controller device: ret=%d\n",
-+ ret);
-+ return ret;
-+ }
-+ break;
-+ default:
-+ dev_err(dev, "unable to add APM controller device for msm_id:%d\n",
-+ ctrl->msm_id);
-+ return -ENODEV;
-+ }
-+
-+ apm_debugfs_init(ctrl);
-+ mutex_lock(&apm_ctrl_list_mutex);
-+ list_add_tail(&ctrl->list, &apm_ctrl_list);
-+ mutex_unlock(&apm_ctrl_list_mutex);
-+
-+ dev_dbg(dev, "MSM Array Power Mux driver probe successful");
-+
-+ return ret;
-+}
-+
-+static int msm_apm_remove(struct platform_device *pdev)
-+{
-+ struct msm_apm_ctrl_dev *ctrl_dev;
-+
-+ ctrl_dev = platform_get_drvdata(pdev);
-+ if (ctrl_dev) {
-+ mutex_lock(&apm_ctrl_list_mutex);
-+ list_del(&ctrl_dev->list);
-+ mutex_unlock(&apm_ctrl_list_mutex);
-+ apm_debugfs_deinit(ctrl_dev);
-+ }
-+
-+ return 0;
-+}
-+
-+static struct platform_driver msm_apm_driver = {
-+ .driver = {
-+ .name = MSM_APM_DRIVER_NAME,
-+ .of_match_table = msm_apm_match_table,
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = msm_apm_probe,
-+ .remove = msm_apm_remove,
-+};
-+
-+static int __init msm_apm_init(void)
-+{
-+ apm_debugfs_base_init();
-+ return platform_driver_register(&msm_apm_driver);
-+}
-+
-+static void __exit msm_apm_exit(void)
-+{
-+ platform_driver_unregister(&msm_apm_driver);
-+ apm_debugfs_base_remove();
-+}
-+
-+arch_initcall(msm_apm_init);
-+module_exit(msm_apm_exit);
-+
-+MODULE_DESCRIPTION("MSM Array Power Mux driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/include/linux/power/qcom/apm.h
-@@ -0,0 +1,48 @@
-+/*
-+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __LINUX_POWER_QCOM_APM_H__
-+#define __LINUX_POWER_QCOM_APM_H__
-+
-+#include <linux/device.h>
-+#include <linux/err.h>
-+
-+/**
-+ * enum msm_apm_supply - supported power rails to supply memory arrays
-+ * %MSM_APM_SUPPLY_APCC: to enable selection of VDD_APCC rail as supply
-+ * %MSM_APM_SUPPLY_MX: to enable selection of VDD_MX rail as supply
-+ */
-+enum msm_apm_supply {
-+ MSM_APM_SUPPLY_APCC,
-+ MSM_APM_SUPPLY_MX,
-+};
-+
-+/* Handle used to identify an APM controller device */
-+struct msm_apm_ctrl_dev;
-+
-+#ifdef CONFIG_QCOM_APM
-+struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev);
-+int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
-+ enum msm_apm_supply supply);
-+int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev);
-+
-+#else
-+static inline struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev)
-+{ return ERR_PTR(-EPERM); }
-+static inline int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
-+ enum msm_apm_supply supply)
-+{ return -EPERM; }
-+static inline int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev)
-+{ return -EPERM; }
-+#endif
-+#endif
+++ /dev/null
-From c9df32c057e43e38c8113199e64f7a64f8d341df Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 11 Apr 2022 14:35:36 +0200
-Subject: [PATCH] regulator: add Qualcomm CPR regulators
-
-Allow building Qualcomm CPR regulators.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/regulator/Kconfig | 33 +
- drivers/regulator/Makefile | 3 +
- drivers/regulator/cpr3-npu-regulator.c | 695 +++
- drivers/regulator/cpr3-regulator.c | 5111 +++++++++++++++++++++++
- drivers/regulator/cpr3-regulator.h | 1211 ++++++
- drivers/regulator/cpr3-util.c | 2750 ++++++++++++
- drivers/regulator/cpr4-apss-regulator.c | 1819 ++++++++
- include/soc/qcom/socinfo.h | 463 ++
- 8 files changed, 12085 insertions(+)
- create mode 100644 drivers/regulator/cpr3-npu-regulator.c
- create mode 100644 drivers/regulator/cpr3-regulator.c
- create mode 100644 drivers/regulator/cpr3-regulator.h
- create mode 100644 drivers/regulator/cpr3-util.c
- create mode 100644 drivers/regulator/cpr4-apss-regulator.c
- create mode 100644 include/soc/qcom/socinfo.h
-
---- a/drivers/regulator/Kconfig
-+++ b/drivers/regulator/Kconfig
-@@ -1524,4 +1524,37 @@ config REGULATOR_QCOM_LABIBB
- boost regulator and IBB can be used as a negative boost regulator
- for LCD display panel.
-
-+config REGULATOR_CPR3
-+ bool "QCOM CPR3 regulator core support"
-+ help
-+ This driver supports Core Power Reduction (CPR) version 3 controllers
-+ which are used by some Qualcomm Technologies, Inc. SoCs to
-+ manage important voltage regulators. CPR3 controllers are capable of
-+ monitoring several ring oscillator sensing loops simultaneously. The
-+ CPR3 controller informs software when the silicon conditions require
-+ the supply voltage to be increased or decreased. On certain supply
-+ rails, the CPR3 controller is able to propagate the voltage increase
-+ or decrease requests all the way to the PMIC without software
-+ involvement.
-+
-+config REGULATOR_CPR3_NPU
-+ bool "QCOM CPR3 regulator for NPU"
-+ depends on OF && REGULATOR_CPR3
-+ help
-+ This driver supports Qualcomm Technologies, Inc. NPU CPR3
-+ regulator Which will always operate in open loop.
-+
-+config REGULATOR_CPR4_APSS
-+ bool "QCOM CPR4 regulator for APSS"
-+ depends on OF && REGULATOR_CPR3
-+ help
-+ This driver supports Qualcomm Technologies, Inc. APSS application
-+ processor specific features including memory array power mux (APM)
-+ switching, one CPR4 thread which monitor the two APSS clusters that
-+ are both powered by a shared supply, hardware closed-loop auto
-+ voltage stepping, voltage adjustments based on online core count,
-+ voltage adjustments based on temperature readings, and voltage
-+ adjustments for performance boost mode. This driver reads both initial
-+ voltage and CPR target quotient values out of hardware fuses.
-+
- endif
---- a/drivers/regulator/Makefile
-+++ b/drivers/regulator/Makefile
-@@ -110,6 +110,9 @@ obj-$(CONFIG_REGULATOR_QCOM_RPMH) += qco
- obj-$(CONFIG_REGULATOR_QCOM_SMD_RPM) += qcom_smd-regulator.o
- obj-$(CONFIG_REGULATOR_QCOM_SPMI) += qcom_spmi-regulator.o
- obj-$(CONFIG_REGULATOR_QCOM_USB_VBUS) += qcom_usb_vbus-regulator.o
-+obj-$(CONFIG_REGULATOR_CPR3) += cpr3-regulator.o cpr3-util.o
-+obj-$(CONFIG_REGULATOR_CPR3_NPU) += cpr3-npu-regulator.o
-+obj-$(CONFIG_REGULATOR_CPR4_APSS) += cpr4-apss-regulator.o
- obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o
- obj-$(CONFIG_REGULATOR_PCA9450) += pca9450-regulator.o
- obj-$(CONFIG_REGULATOR_PF8X00) += pf8x00-regulator.o
---- /dev/null
-+++ b/drivers/regulator/cpr3-npu-regulator.c
-@@ -0,0 +1,695 @@
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ *
-+ * Permission to use, copy, modify, and/or distribute this software for any
-+ * purpose with or without fee is hereby granted, provided that the above
-+ * copyright notice and this permission notice appear in all copies.
-+ *
-+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/platform_device.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/slab.h>
-+#include <linux/thermal.h>
-+
-+#include "cpr3-regulator.h"
-+
-+#define IPQ807x_NPU_FUSE_CORNERS 2
-+#define IPQ817x_NPU_FUSE_CORNERS 1
-+#define IPQ807x_NPU_FUSE_STEP_VOLT 8000
-+#define IPQ807x_NPU_VOLTAGE_FUSE_SIZE 6
-+#define IPQ807x_NPU_CPR_CLOCK_RATE 19200000
-+
-+#define IPQ807x_NPU_CPR_TCSR_START 6
-+#define IPQ807x_NPU_CPR_TCSR_END 7
-+
-+#define NPU_TSENS 5
-+
-+u32 g_valid_npu_fuse_count = IPQ807x_NPU_FUSE_CORNERS;
-+/**
-+ * struct cpr3_ipq807x_npu_fuses - NPU specific fuse data for IPQ807x
-+ * @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value
-+ * for each fuse corner (raw, not converted to a voltage)
-+ * This struct holds the values for all of the fuses read from memory.
-+ */
-+struct cpr3_ipq807x_npu_fuses {
-+ u64 init_voltage[IPQ807x_NPU_FUSE_CORNERS];
-+};
-+
-+/*
-+ * Constants which define the name of each fuse corner.
-+ */
-+enum cpr3_ipq807x_npu_fuse_corner {
-+ CPR3_IPQ807x_NPU_FUSE_CORNER_NOM = 0,
-+ CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO = 1,
-+};
-+
-+static const char * const cpr3_ipq807x_npu_fuse_corner_name[] = {
-+ [CPR3_IPQ807x_NPU_FUSE_CORNER_NOM] = "NOM",
-+ [CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO] = "TURBO",
-+};
-+
-+/*
-+ * IPQ807x NPU fuse parameter locations:
-+ *
-+ * Structs are organized with the following dimensions:
-+ * Outer: 0 to 1 for fuse corners from lowest to highest corner
-+ * Inner: large enough to hold the longest set of parameter segments which
-+ * fully defines a fuse parameter, +1 (for NULL termination).
-+ * Each segment corresponds to a contiguous group of bits from a
-+ * single fuse row. These segments are concatentated together in
-+ * order to form the full fuse parameter value. The segments for
-+ * a given parameter may correspond to different fuse rows.
-+ */
-+static struct cpr3_fuse_param
-+ipq807x_npu_init_voltage_param[IPQ807x_NPU_FUSE_CORNERS][2] = {
-+ {{73, 22, 27}, {} },
-+ {{73, 16, 21}, {} },
-+};
-+
-+/*
-+ * Open loop voltage fuse reference voltages in microvolts for IPQ807x
-+ */
-+static int
-+ipq807x_npu_fuse_ref_volt [IPQ807x_NPU_FUSE_CORNERS] = {
-+ 912000,
-+ 992000,
-+};
-+
-+/*
-+ * IPQ9574 (Few parameters are changed, remaining are same as IPQ807x)
-+ */
-+#define IPQ9574_NPU_FUSE_CORNERS 2
-+#define IPQ9574_NPU_FUSE_STEP_VOLT 10000
-+#define IPQ9574_NPU_CPR_CLOCK_RATE 24000000
-+
-+/*
-+ * fues parameters for IPQ9574
-+ */
-+static struct cpr3_fuse_param
-+ipq9574_npu_init_voltage_param[IPQ9574_NPU_FUSE_CORNERS][2] = {
-+ {{105, 12, 17}, {} },
-+ {{105, 6, 11}, {} },
-+};
-+
-+/*
-+ * Open loop voltage fuse reference voltages in microvolts for IPQ9574
-+ */
-+static int
-+ipq9574_npu_fuse_ref_volt [IPQ9574_NPU_FUSE_CORNERS] = {
-+ 862500,
-+ 987500,
-+};
-+
-+struct cpr3_controller *g_ctrl;
-+
-+void cpr3_npu_temp_notify(int sensor, int temp, int low_notif)
-+{
-+ u32 prev_sensor_state;
-+
-+ if (sensor != NPU_TSENS)
-+ return;
-+
-+ prev_sensor_state = g_ctrl->cur_sensor_state;
-+ if (low_notif)
-+ g_ctrl->cur_sensor_state |= BIT(sensor);
-+ else
-+ g_ctrl->cur_sensor_state &= ~BIT(sensor);
-+
-+ if (!prev_sensor_state && g_ctrl->cur_sensor_state)
-+ cpr3_handle_temp_open_loop_adjustment(g_ctrl, true);
-+ else if (prev_sensor_state && !g_ctrl->cur_sensor_state)
-+ cpr3_handle_temp_open_loop_adjustment(g_ctrl, false);
-+}
-+
-+/**
-+ * cpr3_ipq807x_npu_read_fuse_data() - load NPU specific fuse parameter values
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * This function allocates a cpr3_ipq807x_npu_fuses struct, fills it with
-+ * values read out of hardware fuses, and finally copies common fuse values
-+ * into the CPR3 regulator struct.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_ipq807x_npu_read_fuse_data(struct cpr3_regulator *vreg)
-+{
-+ void __iomem *base = vreg->thread->ctrl->fuse_base;
-+ struct cpr3_ipq807x_npu_fuses *fuse;
-+ int i, rc;
-+
-+ fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL);
-+ if (!fuse)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < g_valid_npu_fuse_count; i++) {
-+ rc = cpr3_read_fuse_param(base,
-+ vreg->cpr3_regulator_data->init_voltage_param[i],
-+ &fuse->init_voltage[i]);
-+ if (rc) {
-+ cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n",
-+ i, rc);
-+ return rc;
-+ }
-+ }
-+
-+ vreg->fuse_corner_count = g_valid_npu_fuse_count;
-+ vreg->platform_fuses = fuse;
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_npu_parse_corner_data() - parse NPU corner data from device tree
-+ * properties of the CPR3 regulator's device node
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_npu_parse_corner_data(struct cpr3_regulator *vreg)
-+{
-+ int rc;
-+
-+ rc = cpr3_parse_common_corner_data(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading corner data, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_ipq807x_npu_calculate_open_loop_voltages() - calculate the open-loop
-+ * voltage for each corner of a CPR3 regulator
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @temp_correction: Temperature based correction
-+ *
-+ * If open-loop voltage interpolation is allowed in device tree, then
-+ * this function calculates the open-loop voltage for a given corner using
-+ * linear interpolation. This interpolation is performed using the processor
-+ * frequencies of the lower and higher Fmax corners along with their fused
-+ * open-loop voltages.
-+ *
-+ * If open-loop voltage interpolation is not allowed, then this function uses
-+ * the Fmax fused open-loop voltage for all of the corners associated with a
-+ * given fuse corner.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_ipq807x_npu_calculate_open_loop_voltages(
-+ struct cpr3_regulator *vreg, bool temp_correction)
-+{
-+ struct cpr3_ipq807x_npu_fuses *fuse = vreg->platform_fuses;
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ int i, j, rc = 0;
-+ u64 freq_low, volt_low, freq_high, volt_high;
-+ int *fuse_volt;
-+ int *fmax_corner;
-+
-+ fuse_volt = kcalloc(vreg->fuse_corner_count, sizeof(*fuse_volt),
-+ GFP_KERNEL);
-+ fmax_corner = kcalloc(vreg->fuse_corner_count, sizeof(*fmax_corner),
-+ GFP_KERNEL);
-+ if (!fuse_volt || !fmax_corner) {
-+ rc = -ENOMEM;
-+ goto done;
-+ }
-+
-+ for (i = 0; i < vreg->fuse_corner_count; i++) {
-+ if (ctrl->cpr_global_setting == CPR_DISABLED)
-+ fuse_volt[i] = vreg->cpr3_regulator_data->fuse_ref_volt[i];
-+ else
-+ fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(
-+ vreg->cpr3_regulator_data->fuse_ref_volt[i],
-+ vreg->cpr3_regulator_data->fuse_step_volt,
-+ fuse->init_voltage[i],
-+ IPQ807x_NPU_VOLTAGE_FUSE_SIZE);
-+
-+ /* Log fused open-loop voltage values for debugging purposes. */
-+ cpr3_info(vreg, "fused %8s: open-loop=%7d uV\n",
-+ cpr3_ipq807x_npu_fuse_corner_name[i],
-+ fuse_volt[i]);
-+ }
-+
-+ rc = cpr3_determine_part_type(vreg,
-+ fuse_volt[CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO]);
-+ if (rc) {
-+ cpr3_err(vreg,
-+ "fused part type detection failed failed, rc=%d\n", rc);
-+ goto done;
-+ }
-+
-+ rc = cpr3_adjust_fused_open_loop_voltages(vreg, fuse_volt);
-+ if (rc) {
-+ cpr3_err(vreg,
-+ "fused open-loop voltage adjustment failed, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ if (temp_correction) {
-+ rc = cpr3_determine_temp_base_open_loop_correction(vreg,
-+ fuse_volt);
-+ if (rc) {
-+ cpr3_err(vreg,
-+ "temp open-loop voltage adj. failed, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+ for (i = 1; i < vreg->fuse_corner_count; i++) {
-+ if (fuse_volt[i] < fuse_volt[i - 1]) {
-+ cpr3_info(vreg,
-+ "fuse corner %d voltage=%d uV < fuse corner %d \
-+ voltage=%d uV; overriding: fuse corner %d \
-+ voltage=%d\n",
-+ i, fuse_volt[i], i - 1, fuse_volt[i - 1],
-+ i, fuse_volt[i - 1]);
-+ fuse_volt[i] = fuse_volt[i - 1];
-+ }
-+ }
-+
-+ /* Determine highest corner mapped to each fuse corner */
-+ j = vreg->fuse_corner_count - 1;
-+ for (i = vreg->corner_count - 1; i >= 0; i--) {
-+ if (vreg->corner[i].cpr_fuse_corner == j) {
-+ fmax_corner[j] = i;
-+ j--;
-+ }
-+ }
-+
-+ if (j >= 0) {
-+ cpr3_err(vreg, "invalid fuse corner mapping\n");
-+ rc = -EINVAL;
-+ goto done;
-+ }
-+
-+ /*
-+ * Interpolation is not possible for corners mapped to the lowest fuse
-+ * corner so use the fuse corner value directly.
-+ */
-+ for (i = 0; i <= fmax_corner[0]; i++)
-+ vreg->corner[i].open_loop_volt = fuse_volt[0];
-+
-+ /* Interpolate voltages for the higher fuse corners. */
-+ for (i = 1; i < vreg->fuse_corner_count; i++) {
-+ freq_low = vreg->corner[fmax_corner[i - 1]].proc_freq;
-+ volt_low = fuse_volt[i - 1];
-+ freq_high = vreg->corner[fmax_corner[i]].proc_freq;
-+ volt_high = fuse_volt[i];
-+
-+ for (j = fmax_corner[i - 1] + 1; j <= fmax_corner[i]; j++)
-+ vreg->corner[j].open_loop_volt = cpr3_interpolate(
-+ freq_low, volt_low, freq_high, volt_high,
-+ vreg->corner[j].proc_freq);
-+ }
-+
-+done:
-+ if (rc == 0) {
-+ cpr3_debug(vreg, "unadjusted per-corner open-loop voltages:\n");
-+ for (i = 0; i < vreg->corner_count; i++)
-+ cpr3_debug(vreg, "open-loop[%2d] = %d uV\n", i,
-+ vreg->corner[i].open_loop_volt);
-+
-+ rc = cpr3_adjust_open_loop_voltages(vreg);
-+ if (rc)
-+ cpr3_err(vreg,
-+ "open-loop voltage adjustment failed, rc=%d\n",
-+ rc);
-+ }
-+
-+ kfree(fuse_volt);
-+ kfree(fmax_corner);
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_npu_print_settings() - print out NPU CPR configuration settings into
-+ * the kernel log for debugging purposes
-+ * @vreg: Pointer to the CPR3 regulator
-+ */
-+static void cpr3_npu_print_settings(struct cpr3_regulator *vreg)
-+{
-+ struct cpr3_corner *corner;
-+ int i;
-+
-+ cpr3_debug(vreg,
-+ "Corner: Frequency (Hz), Fuse Corner, Floor (uV), \
-+ Open-Loop (uV), Ceiling (uV)\n");
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ corner = &vreg->corner[i];
-+ cpr3_debug(vreg, "%3d: %10u, %2d, %7d, %7d, %7d\n",
-+ i, corner->proc_freq, corner->cpr_fuse_corner,
-+ corner->floor_volt, corner->open_loop_volt,
-+ corner->ceiling_volt);
-+ }
-+
-+ if (vreg->thread->ctrl->apm)
-+ cpr3_debug(vreg, "APM threshold = %d uV, APM adjust = %d uV\n",
-+ vreg->thread->ctrl->apm_threshold_volt,
-+ vreg->thread->ctrl->apm_adj_volt);
-+}
-+
-+/**
-+ * cpr3_ipq807x_npu_calc_temp_based_ol_voltages() - Calculate the open loop
-+ * voltages based on temperature based correction margins
-+ * @vreg: Pointer to the CPR3 regulator
-+ */
-+
-+static int
-+cpr3_ipq807x_npu_calc_temp_based_ol_voltages(struct cpr3_regulator *vreg,
-+ bool temp_correction)
-+{
-+ int rc, i;
-+
-+ rc = cpr3_ipq807x_npu_calculate_open_loop_voltages(vreg,
-+ temp_correction);
-+ if (rc) {
-+ cpr3_err(vreg,
-+ "unable to calculate open-loop voltages, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ rc = cpr3_limit_open_loop_voltages(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "unable to limit open-loop voltages, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ cpr3_open_loop_voltage_as_ceiling(vreg);
-+
-+ rc = cpr3_limit_floor_voltages(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "unable to limit floor voltages, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ if (temp_correction)
-+ vreg->corner[i].cold_temp_open_loop_volt =
-+ vreg->corner[i].open_loop_volt;
-+ else
-+ vreg->corner[i].normal_temp_open_loop_volt =
-+ vreg->corner[i].open_loop_volt;
-+ }
-+
-+ cpr3_npu_print_settings(vreg);
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_npu_init_thread() - perform steps necessary to initialize the
-+ * configuration data for a CPR3 thread
-+ * @thread: Pointer to the CPR3 thread
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_npu_init_thread(struct cpr3_thread *thread)
-+{
-+ int rc;
-+
-+ rc = cpr3_parse_common_thread_data(thread);
-+ if (rc) {
-+ cpr3_err(thread->ctrl,
-+ "thread %u CPR thread data from DT- failed, rc=%d\n",
-+ thread->thread_id, rc);
-+ return rc;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_npu_init_regulator() - perform all steps necessary to initialize the
-+ * configuration data for a CPR3 regulator
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_npu_init_regulator(struct cpr3_regulator *vreg)
-+{
-+ struct cpr3_ipq807x_npu_fuses *fuse;
-+ int rc, cold_temp = 0;
-+ bool can_adj_cold_temp = cpr3_can_adjust_cold_temp(vreg);
-+
-+ rc = cpr3_ipq807x_npu_read_fuse_data(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ fuse = vreg->platform_fuses;
-+
-+ rc = cpr3_npu_parse_corner_data(vreg);
-+ if (rc) {
-+ cpr3_err(vreg,
-+ "Cannot read CPR corner data from DT, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ rc = cpr3_mem_acc_init(vreg);
-+ if (rc) {
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(vreg,
-+ "Cannot initialize mem-acc regulator settings, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ if (can_adj_cold_temp) {
-+ rc = cpr3_ipq807x_npu_calc_temp_based_ol_voltages(vreg, true);
-+ if (rc) {
-+ cpr3_err(vreg,
-+ "unable to calculate open-loop voltages, rc=%d\n", rc);
-+ return rc;
-+ }
-+ }
-+
-+ rc = cpr3_ipq807x_npu_calc_temp_based_ol_voltages(vreg, false);
-+ if (rc) {
-+ cpr3_err(vreg,
-+ "unable to calculate open-loop voltages, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ if (can_adj_cold_temp) {
-+ cpr3_info(vreg,
-+ "Normal and Cold condition init done. Default to normal.\n");
-+
-+ rc = cpr3_get_cold_temp_threshold(vreg, &cold_temp);
-+ if (rc) {
-+ cpr3_err(vreg,
-+ "Get cold temperature threshold failed, rc=%d\n", rc);
-+ return rc;
-+ }
-+ register_low_temp_notif(NPU_TSENS, cold_temp,
-+ cpr3_npu_temp_notify);
-+ }
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_npu_init_controller() - perform NPU CPR3 controller specific
-+ * initializations
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_npu_init_controller(struct cpr3_controller *ctrl)
-+{
-+ int rc;
-+
-+ rc = cpr3_parse_open_loop_common_ctrl_data(ctrl);
-+ if (rc) {
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(ctrl, "unable to parse common controller data, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ ctrl->ctrl_type = CPR_CTRL_TYPE_CPR3;
-+ ctrl->supports_hw_closed_loop = false;
-+
-+ return 0;
-+}
-+
-+static const struct cpr3_reg_data ipq807x_cpr_npu = {
-+ .cpr_valid_fuse_count = IPQ807x_NPU_FUSE_CORNERS,
-+ .init_voltage_param = ipq807x_npu_init_voltage_param,
-+ .fuse_ref_volt = ipq807x_npu_fuse_ref_volt,
-+ .fuse_step_volt = IPQ807x_NPU_FUSE_STEP_VOLT,
-+ .cpr_clk_rate = IPQ807x_NPU_CPR_CLOCK_RATE,
-+};
-+
-+static const struct cpr3_reg_data ipq817x_cpr_npu = {
-+ .cpr_valid_fuse_count = IPQ817x_NPU_FUSE_CORNERS,
-+ .init_voltage_param = ipq807x_npu_init_voltage_param,
-+ .fuse_ref_volt = ipq807x_npu_fuse_ref_volt,
-+ .fuse_step_volt = IPQ807x_NPU_FUSE_STEP_VOLT,
-+ .cpr_clk_rate = IPQ807x_NPU_CPR_CLOCK_RATE,
-+};
-+
-+static const struct cpr3_reg_data ipq9574_cpr_npu = {
-+ .cpr_valid_fuse_count = IPQ9574_NPU_FUSE_CORNERS,
-+ .init_voltage_param = ipq9574_npu_init_voltage_param,
-+ .fuse_ref_volt = ipq9574_npu_fuse_ref_volt,
-+ .fuse_step_volt = IPQ9574_NPU_FUSE_STEP_VOLT,
-+ .cpr_clk_rate = IPQ9574_NPU_CPR_CLOCK_RATE,
-+};
-+
-+static struct of_device_id cpr3_regulator_match_table[] = {
-+ {
-+ .compatible = "qcom,cpr3-ipq807x-npu-regulator",
-+ .data = &ipq807x_cpr_npu
-+ },
-+ {
-+ .compatible = "qcom,cpr3-ipq817x-npu-regulator",
-+ .data = &ipq817x_cpr_npu
-+ },
-+ {
-+ .compatible = "qcom,cpr3-ipq9574-npu-regulator",
-+ .data = &ipq9574_cpr_npu
-+ },
-+ {}
-+};
-+
-+static int cpr3_npu_regulator_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct cpr3_controller *ctrl;
-+ int i, rc;
-+ const struct of_device_id *match;
-+ struct cpr3_reg_data *cpr_data;
-+
-+ if (!dev->of_node) {
-+ dev_err(dev, "Device tree node is missing\n");
-+ return -EINVAL;
-+ }
-+
-+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
-+ if (!ctrl)
-+ return -ENOMEM;
-+ g_ctrl = ctrl;
-+
-+ match = of_match_device(cpr3_regulator_match_table, &pdev->dev);
-+ if (!match)
-+ return -ENODEV;
-+
-+ cpr_data = (struct cpr3_reg_data *)match->data;
-+ g_valid_npu_fuse_count = cpr_data->cpr_valid_fuse_count;
-+ dev_info(dev, "NPU CPR valid fuse count: %d\n", g_valid_npu_fuse_count);
-+ ctrl->cpr_clock_rate = cpr_data->cpr_clk_rate;
-+
-+ ctrl->dev = dev;
-+ /* Set to false later if anything precludes CPR operation. */
-+ ctrl->cpr_allowed_hw = true;
-+
-+ rc = of_property_read_string(dev->of_node, "qcom,cpr-ctrl-name",
-+ &ctrl->name);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to read qcom,cpr-ctrl-name, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = cpr3_map_fuse_base(ctrl, pdev);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not map fuse base address\n");
-+ return rc;
-+ }
-+
-+ rc = cpr3_read_tcsr_setting(ctrl, pdev, IPQ807x_NPU_CPR_TCSR_START,
-+ IPQ807x_NPU_CPR_TCSR_END);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not read CPR tcsr rsetting\n");
-+ return rc;
-+ }
-+
-+ rc = cpr3_allocate_threads(ctrl, 0, 0);
-+ if (rc) {
-+ cpr3_err(ctrl, "failed to allocate CPR thread array, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ if (ctrl->thread_count != 1) {
-+ cpr3_err(ctrl, "expected 1 thread but found %d\n",
-+ ctrl->thread_count);
-+ return -EINVAL;
-+ }
-+
-+ rc = cpr3_npu_init_controller(ctrl);
-+ if (rc) {
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(ctrl, "failed to initialize CPR controller parameters, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = cpr3_npu_init_thread(&ctrl->thread[0]);
-+ if (rc) {
-+ cpr3_err(ctrl, "thread initialization failed, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ for (i = 0; i < ctrl->thread[0].vreg_count; i++) {
-+ ctrl->thread[0].vreg[i].cpr3_regulator_data = cpr_data;
-+ rc = cpr3_npu_init_regulator(&ctrl->thread[0].vreg[i]);
-+ if (rc) {
-+ cpr3_err(&ctrl->thread[0].vreg[i], "regulator initialization failed, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ }
-+
-+ platform_set_drvdata(pdev, ctrl);
-+
-+ return cpr3_open_loop_regulator_register(pdev, ctrl);
-+}
-+
-+static int cpr3_npu_regulator_remove(struct platform_device *pdev)
-+{
-+ struct cpr3_controller *ctrl = platform_get_drvdata(pdev);
-+
-+ return cpr3_open_loop_regulator_unregister(ctrl);
-+}
-+
-+static struct platform_driver cpr3_npu_regulator_driver = {
-+ .driver = {
-+ .name = "qcom,cpr3-npu-regulator",
-+ .of_match_table = cpr3_regulator_match_table,
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = cpr3_npu_regulator_probe,
-+ .remove = cpr3_npu_regulator_remove,
-+};
-+
-+static int cpr3_regulator_init(void)
-+{
-+ return platform_driver_register(&cpr3_npu_regulator_driver);
-+}
-+arch_initcall(cpr3_regulator_init);
-+
-+static void cpr3_regulator_exit(void)
-+{
-+ platform_driver_unregister(&cpr3_npu_regulator_driver);
-+}
-+module_exit(cpr3_regulator_exit);
-+
-+MODULE_DESCRIPTION("QCOM CPR3 NPU regulator driver");
-+MODULE_LICENSE("Dual BSD/GPLv2");
-+MODULE_ALIAS("platform:npu-ipq807x");
---- /dev/null
-+++ b/drivers/regulator/cpr3-regulator.c
-@@ -0,0 +1,5111 @@
-+/*
-+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#define pr_fmt(fmt) "%s: " fmt, __func__
-+
-+#include <linux/bitops.h>
-+#include <linux/debugfs.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/ktime.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_opp.h>
-+#include <linux/slab.h>
-+#include <linux/sort.h>
-+#include <linux/string.h>
-+#include <linux/uaccess.h>
-+#include <linux/regulator/driver.h>
-+#include <linux/regulator/machine.h>
-+#include <linux/regulator/of_regulator.h>
-+#include <linux/panic_notifier.h>
-+
-+#include "cpr3-regulator.h"
-+
-+#define CPR3_REGULATOR_CORNER_INVALID (-1)
-+#define CPR3_RO_MASK GENMASK(CPR3_RO_COUNT - 1, 0)
-+
-+/* CPR3 registers */
-+#define CPR3_REG_CPR_CTL 0x4
-+#define CPR3_CPR_CTL_LOOP_EN_MASK BIT(0)
-+#define CPR3_CPR_CTL_LOOP_ENABLE BIT(0)
-+#define CPR3_CPR_CTL_LOOP_DISABLE 0
-+#define CPR3_CPR_CTL_IDLE_CLOCKS_MASK GENMASK(5, 1)
-+#define CPR3_CPR_CTL_IDLE_CLOCKS_SHIFT 1
-+#define CPR3_CPR_CTL_COUNT_MODE_MASK GENMASK(7, 6)
-+#define CPR3_CPR_CTL_COUNT_MODE_SHIFT 6
-+#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN 0
-+#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MAX 1
-+#define CPR3_CPR_CTL_COUNT_MODE_STAGGERED 2
-+#define CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_AGE 3
-+#define CPR3_CPR_CTL_COUNT_REPEAT_MASK GENMASK(31, 9)
-+#define CPR3_CPR_CTL_COUNT_REPEAT_SHIFT 9
-+
-+#define CPR3_REG_CPR_STATUS 0x8
-+#define CPR3_CPR_STATUS_BUSY_MASK BIT(0)
-+#define CPR3_CPR_STATUS_AGING_MEASUREMENT_MASK BIT(1)
-+
-+/*
-+ * This register is not present on controllers that support HW closed-loop
-+ * except CPR4 APSS controller.
-+ */
-+#define CPR3_REG_CPR_TIMER_AUTO_CONT 0xC
-+
-+#define CPR3_REG_CPR_STEP_QUOT 0x14
-+#define CPR3_CPR_STEP_QUOT_MIN_MASK GENMASK(5, 0)
-+#define CPR3_CPR_STEP_QUOT_MIN_SHIFT 0
-+#define CPR3_CPR_STEP_QUOT_MAX_MASK GENMASK(11, 6)
-+#define CPR3_CPR_STEP_QUOT_MAX_SHIFT 6
-+
-+#define CPR3_REG_GCNT(ro) (0xA0 + 0x4 * (ro))
-+
-+#define CPR3_REG_SENSOR_BYPASS_WRITE(sensor) (0xE0 + 0x4 * ((sensor) / 32))
-+#define CPR3_REG_SENSOR_BYPASS_WRITE_BANK(bank) (0xE0 + 0x4 * (bank))
-+
-+#define CPR3_REG_SENSOR_MASK_WRITE(sensor) (0x120 + 0x4 * ((sensor) / 32))
-+#define CPR3_REG_SENSOR_MASK_WRITE_BANK(bank) (0x120 + 0x4 * (bank))
-+#define CPR3_REG_SENSOR_MASK_READ(sensor) (0x140 + 0x4 * ((sensor) / 32))
-+
-+#define CPR3_REG_SENSOR_OWNER(sensor) (0x200 + 0x4 * (sensor))
-+
-+#define CPR3_REG_CONT_CMD 0x800
-+#define CPR3_CONT_CMD_ACK 0x1
-+#define CPR3_CONT_CMD_NACK 0x0
-+
-+#define CPR3_REG_THRESH(thread) (0x808 + 0x440 * (thread))
-+#define CPR3_THRESH_CONS_DOWN_MASK GENMASK(3, 0)
-+#define CPR3_THRESH_CONS_DOWN_SHIFT 0
-+#define CPR3_THRESH_CONS_UP_MASK GENMASK(7, 4)
-+#define CPR3_THRESH_CONS_UP_SHIFT 4
-+#define CPR3_THRESH_DOWN_THRESH_MASK GENMASK(12, 8)
-+#define CPR3_THRESH_DOWN_THRESH_SHIFT 8
-+#define CPR3_THRESH_UP_THRESH_MASK GENMASK(17, 13)
-+#define CPR3_THRESH_UP_THRESH_SHIFT 13
-+
-+#define CPR3_REG_RO_MASK(thread) (0x80C + 0x440 * (thread))
-+
-+#define CPR3_REG_RESULT0(thread) (0x810 + 0x440 * (thread))
-+#define CPR3_RESULT0_BUSY_MASK BIT(0)
-+#define CPR3_RESULT0_STEP_DN_MASK BIT(1)
-+#define CPR3_RESULT0_STEP_UP_MASK BIT(2)
-+#define CPR3_RESULT0_ERROR_STEPS_MASK GENMASK(7, 3)
-+#define CPR3_RESULT0_ERROR_STEPS_SHIFT 3
-+#define CPR3_RESULT0_ERROR_MASK GENMASK(19, 8)
-+#define CPR3_RESULT0_ERROR_SHIFT 8
-+#define CPR3_RESULT0_NEGATIVE_MASK BIT(20)
-+
-+#define CPR3_REG_RESULT1(thread) (0x814 + 0x440 * (thread))
-+#define CPR3_RESULT1_QUOT_MIN_MASK GENMASK(11, 0)
-+#define CPR3_RESULT1_QUOT_MIN_SHIFT 0
-+#define CPR3_RESULT1_QUOT_MAX_MASK GENMASK(23, 12)
-+#define CPR3_RESULT1_QUOT_MAX_SHIFT 12
-+#define CPR3_RESULT1_RO_MIN_MASK GENMASK(27, 24)
-+#define CPR3_RESULT1_RO_MIN_SHIFT 24
-+#define CPR3_RESULT1_RO_MAX_MASK GENMASK(31, 28)
-+#define CPR3_RESULT1_RO_MAX_SHIFT 28
-+
-+#define CPR3_REG_RESULT2(thread) (0x818 + 0x440 * (thread))
-+#define CPR3_RESULT2_STEP_QUOT_MIN_MASK GENMASK(5, 0)
-+#define CPR3_RESULT2_STEP_QUOT_MIN_SHIFT 0
-+#define CPR3_RESULT2_STEP_QUOT_MAX_MASK GENMASK(11, 6)
-+#define CPR3_RESULT2_STEP_QUOT_MAX_SHIFT 6
-+#define CPR3_RESULT2_SENSOR_MIN_MASK GENMASK(23, 16)
-+#define CPR3_RESULT2_SENSOR_MIN_SHIFT 16
-+#define CPR3_RESULT2_SENSOR_MAX_MASK GENMASK(31, 24)
-+#define CPR3_RESULT2_SENSOR_MAX_SHIFT 24
-+
-+#define CPR3_REG_IRQ_EN 0x81C
-+#define CPR3_REG_IRQ_CLEAR 0x820
-+#define CPR3_REG_IRQ_STATUS 0x824
-+#define CPR3_IRQ_UP BIT(3)
-+#define CPR3_IRQ_MID BIT(2)
-+#define CPR3_IRQ_DOWN BIT(1)
-+
-+#define CPR3_REG_TARGET_QUOT(thread, ro) \
-+ (0x840 + 0x440 * (thread) + 0x4 * (ro))
-+
-+/* Registers found only on controllers that support HW closed-loop. */
-+#define CPR3_REG_PD_THROTTLE 0xE8
-+#define CPR3_PD_THROTTLE_DISABLE 0x0
-+
-+#define CPR3_REG_HW_CLOSED_LOOP 0x3000
-+#define CPR3_HW_CLOSED_LOOP_ENABLE 0x0
-+#define CPR3_HW_CLOSED_LOOP_DISABLE 0x1
-+
-+#define CPR3_REG_CPR_TIMER_MID_CONT 0x3004
-+#define CPR3_REG_CPR_TIMER_UP_DN_CONT 0x3008
-+
-+#define CPR3_REG_LAST_MEASUREMENT 0x7F8
-+#define CPR3_LAST_MEASUREMENT_THREAD_DN_SHIFT 0
-+#define CPR3_LAST_MEASUREMENT_THREAD_UP_SHIFT 4
-+#define CPR3_LAST_MEASUREMENT_THREAD_DN(thread) \
-+ (BIT(thread) << CPR3_LAST_MEASUREMENT_THREAD_DN_SHIFT)
-+#define CPR3_LAST_MEASUREMENT_THREAD_UP(thread) \
-+ (BIT(thread) << CPR3_LAST_MEASUREMENT_THREAD_UP_SHIFT)
-+#define CPR3_LAST_MEASUREMENT_AGGR_DN BIT(8)
-+#define CPR3_LAST_MEASUREMENT_AGGR_MID BIT(9)
-+#define CPR3_LAST_MEASUREMENT_AGGR_UP BIT(10)
-+#define CPR3_LAST_MEASUREMENT_VALID BIT(11)
-+#define CPR3_LAST_MEASUREMENT_SAW_ERROR BIT(12)
-+#define CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK GENMASK(23, 16)
-+#define CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT 16
-+
-+/* CPR4 controller specific registers and bit definitions */
-+#define CPR4_REG_CPR_TIMER_CLAMP 0x10
-+#define CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN BIT(27)
-+
-+#define CPR4_REG_MISC 0x700
-+#define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK GENMASK(23, 20)
-+#define CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT 20
-+#define CPR4_MISC_TEMP_SENSOR_ID_START_MASK GENMASK(27, 24)
-+#define CPR4_MISC_TEMP_SENSOR_ID_START_SHIFT 24
-+#define CPR4_MISC_TEMP_SENSOR_ID_END_MASK GENMASK(31, 28)
-+#define CPR4_MISC_TEMP_SENSOR_ID_END_SHIFT 28
-+
-+#define CPR4_REG_SAW_ERROR_STEP_LIMIT 0x7A4
-+#define CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK GENMASK(4, 0)
-+#define CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT 0
-+#define CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK GENMASK(9, 5)
-+#define CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT 5
-+
-+#define CPR4_REG_MARGIN_TEMP_CORE_TIMERS 0x7A8
-+#define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK GENMASK(28, 18)
-+#define CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHIFT 18
-+
-+#define CPR4_REG_MARGIN_TEMP_CORE(core) (0x7AC + 0x4 * (core))
-+#define CPR4_MARGIN_TEMP_CORE_ADJ_MASK GENMASK(7, 0)
-+#define CPR4_MARGIN_TEMP_CORE_ADJ_SHIFT 8
-+
-+#define CPR4_REG_MARGIN_TEMP_POINT0N1 0x7F0
-+#define CPR4_MARGIN_TEMP_POINT0_MASK GENMASK(11, 0)
-+#define CPR4_MARGIN_TEMP_POINT0_SHIFT 0
-+#define CPR4_MARGIN_TEMP_POINT1_MASK GENMASK(23, 12)
-+#define CPR4_MARGIN_TEMP_POINT1_SHIFT 12
-+#define CPR4_REG_MARGIN_TEMP_POINT2 0x7F4
-+#define CPR4_MARGIN_TEMP_POINT2_MASK GENMASK(11, 0)
-+#define CPR4_MARGIN_TEMP_POINT2_SHIFT 0
-+
-+#define CPR4_REG_MARGIN_ADJ_CTL 0x7F8
-+#define CPR4_MARGIN_ADJ_CTL_BOOST_EN BIT(0)
-+#define CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN BIT(1)
-+#define CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN BIT(2)
-+#define CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN BIT(3)
-+#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK BIT(4)
-+#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE BIT(4)
-+#define CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE 0
-+#define CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN BIT(7)
-+#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN BIT(8)
-+#define CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_MASK GENMASK(16, 12)
-+#define CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_SHIFT 12
-+#define CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_MASK GENMASK(21, 19)
-+#define CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_SHIFT 19
-+#define CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK GENMASK(25, 22)
-+#define CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_SHIFT 22
-+#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_MASK GENMASK(31, 26)
-+#define CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_SHIFT 26
-+
-+#define CPR4_REG_CPR_MASK_THREAD(thread) (0x80C + 0x440 * (thread))
-+#define CPR4_CPR_MASK_THREAD_DISABLE_THREAD BIT(31)
-+#define CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK GENMASK(15, 0)
-+
-+/*
-+ * The amount of time to wait for the CPR controller to become idle when
-+ * performing an aging measurement.
-+ */
-+#define CPR3_AGING_MEASUREMENT_TIMEOUT_NS 5000000
-+
-+/*
-+ * The number of individual aging measurements to perform which are then
-+ * averaged together in order to determine the final aging adjustment value.
-+ */
-+#define CPR3_AGING_MEASUREMENT_ITERATIONS 16
-+
-+/*
-+ * Aging measurements for the aged and unaged ring oscillators take place a few
-+ * microseconds apart. If the vdd-supply voltage fluctuates between the two
-+ * measurements, then the difference between them will be incorrect. The
-+ * difference could end up too high or too low. This constant defines the
-+ * number of lowest and highest measurements to ignore when averaging.
-+ */
-+#define CPR3_AGING_MEASUREMENT_FILTER 3
-+
-+/*
-+ * The number of times to attempt the full aging measurement sequence before
-+ * declaring a measurement failure.
-+ */
-+#define CPR3_AGING_RETRY_COUNT 5
-+
-+/*
-+ * The maximum time to wait in microseconds for a CPR register write to
-+ * complete.
-+ */
-+#define CPR3_REGISTER_WRITE_DELAY_US 200
-+
-+static DEFINE_MUTEX(cpr3_controller_list_mutex);
-+static LIST_HEAD(cpr3_controller_list);
-+static struct dentry *cpr3_debugfs_base;
-+
-+/**
-+ * cpr3_read() - read four bytes from the memory address specified
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @offset: Offset in bytes from the CPR3 controller's base address
-+ *
-+ * Return: memory address value
-+ */
-+static inline u32 cpr3_read(struct cpr3_controller *ctrl, u32 offset)
-+{
-+ if (!ctrl->cpr_enabled) {
-+ cpr3_err(ctrl, "CPR register reads are not possible when CPR clocks are disabled\n");
-+ return 0;
-+ }
-+
-+ return readl_relaxed(ctrl->cpr_ctrl_base + offset);
-+}
-+
-+/**
-+ * cpr3_write() - write four bytes to the memory address specified
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @offset: Offset in bytes from the CPR3 controller's base address
-+ * @value: Value to write to the memory address
-+ *
-+ * Return: none
-+ */
-+static inline void cpr3_write(struct cpr3_controller *ctrl, u32 offset,
-+ u32 value)
-+{
-+ if (!ctrl->cpr_enabled) {
-+ cpr3_err(ctrl, "CPR register writes are not possible when CPR clocks are disabled\n");
-+ return;
-+ }
-+
-+ writel_relaxed(value, ctrl->cpr_ctrl_base + offset);
-+}
-+
-+/**
-+ * cpr3_masked_write() - perform a read-modify-write sequence so that only
-+ * masked bits are modified
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @offset: Offset in bytes from the CPR3 controller's base address
-+ * @mask: Mask identifying the bits that should be modified
-+ * @value: Value to write to the memory address
-+ *
-+ * Return: none
-+ */
-+static inline void cpr3_masked_write(struct cpr3_controller *ctrl, u32 offset,
-+ u32 mask, u32 value)
-+{
-+ u32 reg_val, orig_val;
-+
-+ if (!ctrl->cpr_enabled) {
-+ cpr3_err(ctrl, "CPR register writes are not possible when CPR clocks are disabled\n");
-+ return;
-+ }
-+
-+ reg_val = orig_val = readl_relaxed(ctrl->cpr_ctrl_base + offset);
-+ reg_val &= ~mask;
-+ reg_val |= value & mask;
-+
-+ if (reg_val != orig_val)
-+ writel_relaxed(reg_val, ctrl->cpr_ctrl_base + offset);
-+}
-+
-+/**
-+ * cpr3_ctrl_loop_enable() - enable the CPR sensing loop for a given controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: none
-+ */
-+static inline void cpr3_ctrl_loop_enable(struct cpr3_controller *ctrl)
-+{
-+ if (ctrl->cpr_enabled && !(ctrl->aggr_corner.sdelta
-+ && ctrl->aggr_corner.sdelta->allow_boost))
-+ cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL,
-+ CPR3_CPR_CTL_LOOP_EN_MASK, CPR3_CPR_CTL_LOOP_ENABLE);
-+}
-+
-+/**
-+ * cpr3_ctrl_loop_disable() - disable the CPR sensing loop for a given
-+ * controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: none
-+ */
-+static inline void cpr3_ctrl_loop_disable(struct cpr3_controller *ctrl)
-+{
-+ if (ctrl->cpr_enabled)
-+ cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL,
-+ CPR3_CPR_CTL_LOOP_EN_MASK, CPR3_CPR_CTL_LOOP_DISABLE);
-+}
-+
-+/**
-+ * cpr3_clock_enable() - prepare and enable all clocks used by this CPR3
-+ * controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_clock_enable(struct cpr3_controller *ctrl)
-+{
-+ int rc;
-+
-+ rc = clk_prepare_enable(ctrl->bus_clk);
-+ if (rc) {
-+ cpr3_err(ctrl, "failed to enable bus clock, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ rc = clk_prepare_enable(ctrl->iface_clk);
-+ if (rc) {
-+ cpr3_err(ctrl, "failed to enable interface clock, rc=%d\n", rc);
-+ clk_disable_unprepare(ctrl->bus_clk);
-+ return rc;
-+ }
-+
-+ rc = clk_prepare_enable(ctrl->core_clk);
-+ if (rc) {
-+ cpr3_err(ctrl, "failed to enable core clock, rc=%d\n", rc);
-+ clk_disable_unprepare(ctrl->iface_clk);
-+ clk_disable_unprepare(ctrl->bus_clk);
-+ return rc;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_clock_disable() - disable and unprepare all clocks used by this CPR3
-+ * controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: none
-+ */
-+static void cpr3_clock_disable(struct cpr3_controller *ctrl)
-+{
-+ clk_disable_unprepare(ctrl->core_clk);
-+ clk_disable_unprepare(ctrl->iface_clk);
-+ clk_disable_unprepare(ctrl->bus_clk);
-+}
-+
-+/**
-+ * cpr3_ctrl_clear_cpr4_config() - clear the CPR4 register configuration
-+ * programmed for current aggregated corner of a given controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static inline int cpr3_ctrl_clear_cpr4_config(struct cpr3_controller *ctrl)
-+{
-+ struct cpr4_sdelta *aggr_sdelta = ctrl->aggr_corner.sdelta;
-+ bool cpr_enabled = ctrl->cpr_enabled;
-+ int i, rc = 0;
-+
-+ if (!aggr_sdelta || !(aggr_sdelta->allow_core_count_adj
-+ || aggr_sdelta->allow_temp_adj || aggr_sdelta->allow_boost))
-+ /* cpr4 features are not enabled */
-+ return 0;
-+
-+ /* Ensure that CPR clocks are enabled before writing to registers. */
-+ if (!cpr_enabled) {
-+ rc = cpr3_clock_enable(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc);
-+ return rc;
-+ }
-+ ctrl->cpr_enabled = true;
-+ }
-+
-+ /*
-+ * Clear feature enable configuration made for current
-+ * aggregated corner.
-+ */
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK
-+ | CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN
-+ | CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN
-+ | CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN
-+ | CPR4_MARGIN_ADJ_CTL_BOOST_EN
-+ | CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK, 0);
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_MISC,
-+ CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK,
-+ 0 << CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT);
-+
-+ for (i = 0; i <= aggr_sdelta->max_core_count; i++) {
-+ /* Clear voltage margin adjustments programmed in TEMP_COREi */
-+ cpr3_write(ctrl, CPR4_REG_MARGIN_TEMP_CORE(i), 0);
-+ }
-+
-+ /* Turn off CPR clocks if they were off before this function call. */
-+ if (!cpr_enabled) {
-+ cpr3_clock_disable(ctrl);
-+ ctrl->cpr_enabled = false;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_closed_loop_enable() - enable logical CPR closed-loop operation
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_closed_loop_enable(struct cpr3_controller *ctrl)
-+{
-+ int rc;
-+
-+ if (!ctrl->cpr_allowed_hw || !ctrl->cpr_allowed_sw) {
-+ cpr3_err(ctrl, "cannot enable closed-loop CPR operation because it is disallowed\n");
-+ return -EPERM;
-+ } else if (ctrl->cpr_enabled) {
-+ /* Already enabled */
-+ return 0;
-+ } else if (ctrl->cpr_suspended) {
-+ /*
-+ * CPR must remain disabled as the system is entering suspend.
-+ */
-+ return 0;
-+ }
-+
-+ rc = cpr3_clock_enable(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to enable CPR clocks, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ ctrl->cpr_enabled = true;
-+ cpr3_debug(ctrl, "CPR closed-loop operation enabled\n");
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_closed_loop_disable() - disable logical CPR closed-loop operation
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static inline int cpr3_closed_loop_disable(struct cpr3_controller *ctrl)
-+{
-+ if (!ctrl->cpr_enabled) {
-+ /* Already disabled */
-+ return 0;
-+ }
-+
-+ cpr3_clock_disable(ctrl);
-+ ctrl->cpr_enabled = false;
-+ cpr3_debug(ctrl, "CPR closed-loop operation disabled\n");
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_get_gcnt() - returns the GCNT register value corresponding
-+ * to the clock rate and sensor time of the CPR3 controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: GCNT value
-+ */
-+static u32 cpr3_regulator_get_gcnt(struct cpr3_controller *ctrl)
-+{
-+ u64 temp;
-+ unsigned int remainder;
-+ u32 gcnt;
-+
-+ temp = (u64)ctrl->cpr_clock_rate * (u64)ctrl->sensor_time;
-+ remainder = do_div(temp, 1000000000);
-+ if (remainder)
-+ temp++;
-+ /*
-+ * GCNT == 0 corresponds to a single ref clock measurement interval so
-+ * offset GCNT values by 1.
-+ */
-+ gcnt = temp - 1;
-+
-+ return gcnt;
-+}
-+
-+/**
-+ * cpr3_regulator_init_thread() - performs hardware initialization of CPR
-+ * thread registers
-+ * @thread: Pointer to the CPR3 thread
-+ *
-+ * CPR interface/bus clocks must be enabled before calling this function.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_init_thread(struct cpr3_thread *thread)
-+{
-+ u32 reg;
-+
-+ reg = (thread->consecutive_up << CPR3_THRESH_CONS_UP_SHIFT)
-+ & CPR3_THRESH_CONS_UP_MASK;
-+ reg |= (thread->consecutive_down << CPR3_THRESH_CONS_DOWN_SHIFT)
-+ & CPR3_THRESH_CONS_DOWN_MASK;
-+ reg |= (thread->up_threshold << CPR3_THRESH_UP_THRESH_SHIFT)
-+ & CPR3_THRESH_UP_THRESH_MASK;
-+ reg |= (thread->down_threshold << CPR3_THRESH_DOWN_THRESH_SHIFT)
-+ & CPR3_THRESH_DOWN_THRESH_MASK;
-+
-+ cpr3_write(thread->ctrl, CPR3_REG_THRESH(thread->thread_id), reg);
-+
-+ /*
-+ * Mask all RO's initially so that unused thread doesn't contribute
-+ * to closed-loop voltage.
-+ */
-+ cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id),
-+ CPR3_RO_MASK);
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr4_regulator_init_temp_points() - performs hardware initialization of CPR4
-+ * registers to track tsen temperature data and also specify the
-+ * temperature band range values to apply different voltage margins
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * CPR interface/bus clocks must be enabled before calling this function.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_regulator_init_temp_points(struct cpr3_controller *ctrl)
-+{
-+ if (!ctrl->allow_temp_adj)
-+ return 0;
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_MISC,
-+ CPR4_MISC_TEMP_SENSOR_ID_START_MASK,
-+ ctrl->temp_sensor_id_start
-+ << CPR4_MISC_TEMP_SENSOR_ID_START_SHIFT);
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_MISC,
-+ CPR4_MISC_TEMP_SENSOR_ID_END_MASK,
-+ ctrl->temp_sensor_id_end
-+ << CPR4_MISC_TEMP_SENSOR_ID_END_SHIFT);
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT2,
-+ CPR4_MARGIN_TEMP_POINT2_MASK,
-+ (ctrl->temp_band_count == 4 ? ctrl->temp_points[2] : 0x7FF)
-+ << CPR4_MARGIN_TEMP_POINT2_SHIFT);
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT0N1,
-+ CPR4_MARGIN_TEMP_POINT1_MASK,
-+ (ctrl->temp_band_count >= 3 ? ctrl->temp_points[1] : 0x7FF)
-+ << CPR4_MARGIN_TEMP_POINT1_SHIFT);
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_POINT0N1,
-+ CPR4_MARGIN_TEMP_POINT0_MASK,
-+ (ctrl->temp_band_count >= 2 ? ctrl->temp_points[0] : 0x7FF)
-+ << CPR4_MARGIN_TEMP_POINT0_SHIFT);
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_init_cpr4() - performs hardware initialization at the
-+ * controller and thread level required for CPR4 operation.
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * CPR interface/bus clocks must be enabled before calling this function.
-+ * This function allocates sdelta structures and sdelta tables for aggregated
-+ * corners of the controller and its threads.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_init_cpr4(struct cpr3_controller *ctrl)
-+{
-+ struct cpr3_thread *thread;
-+ struct cpr3_regulator *vreg;
-+ struct cpr4_sdelta *sdelta;
-+ int i, j, ctrl_max_core_count, thread_max_core_count, rc = 0;
-+ bool ctrl_valid_sdelta, thread_valid_sdelta;
-+ u32 pmic_step_size = 1;
-+ int thread_id = 0;
-+ u64 temp;
-+
-+ if (ctrl->supports_hw_closed_loop) {
-+ if (ctrl->saw_use_unit_mV)
-+ pmic_step_size = ctrl->step_volt / 1000;
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_MASK,
-+ (pmic_step_size
-+ << CPR4_MARGIN_ADJ_CTL_PMIC_STEP_SIZE_SHIFT));
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT,
-+ CPR4_SAW_ERROR_STEP_LIMIT_DN_MASK,
-+ (ctrl->down_error_step_limit
-+ << CPR4_SAW_ERROR_STEP_LIMIT_DN_SHIFT));
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_SAW_ERROR_STEP_LIMIT,
-+ CPR4_SAW_ERROR_STEP_LIMIT_UP_MASK,
-+ (ctrl->up_error_step_limit
-+ << CPR4_SAW_ERROR_STEP_LIMIT_UP_SHIFT));
-+
-+ /*
-+ * Enable thread aggregation regardless of which threads are
-+ * enabled or disabled.
-+ */
-+ cpr3_masked_write(ctrl, CPR4_REG_CPR_TIMER_CLAMP,
-+ CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN,
-+ CPR4_CPR_TIMER_CLAMP_THREAD_AGGREGATION_EN);
-+
-+ switch (ctrl->thread_count) {
-+ case 0:
-+ /* Disable both threads */
-+ cpr3_masked_write(ctrl, CPR4_REG_CPR_MASK_THREAD(0),
-+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD
-+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK,
-+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD
-+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK);
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_CPR_MASK_THREAD(1),
-+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD
-+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK,
-+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD
-+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK);
-+ break;
-+ case 1:
-+ /* Disable unused thread */
-+ thread_id = ctrl->thread[0].thread_id ? 0 : 1;
-+ cpr3_masked_write(ctrl,
-+ CPR4_REG_CPR_MASK_THREAD(thread_id),
-+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD
-+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK,
-+ CPR4_CPR_MASK_THREAD_DISABLE_THREAD
-+ | CPR4_CPR_MASK_THREAD_RO_MASK4THREAD_MASK);
-+ break;
-+ }
-+ }
-+
-+ if (!ctrl->allow_core_count_adj && !ctrl->allow_temp_adj
-+ && !ctrl->allow_boost) {
-+ /*
-+ * Skip below configuration as none of the features
-+ * are enabled.
-+ */
-+ return rc;
-+ }
-+
-+ if (ctrl->supports_hw_closed_loop)
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN,
-+ CPR4_MARGIN_ADJ_CTL_TIMER_SETTLE_VOLTAGE_EN);
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_MASK,
-+ ctrl->step_quot_fixed
-+ << CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_STEP_QUOT_SHIFT);
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN,
-+ (ctrl->use_dynamic_step_quot
-+ ? CPR4_MARGIN_ADJ_CTL_PER_RO_KV_MARGIN_EN : 0));
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_MASK,
-+ ctrl->initial_temp_band
-+ << CPR4_MARGIN_ADJ_CTL_INITIAL_TEMP_BAND_SHIFT);
-+
-+ rc = cpr4_regulator_init_temp_points(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "initialize temp points failed, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ if (ctrl->voltage_settling_time) {
-+ /*
-+ * Configure the settling timer used to account for
-+ * one VDD supply step.
-+ */
-+ temp = (u64)ctrl->cpr_clock_rate
-+ * (u64)ctrl->voltage_settling_time;
-+ do_div(temp, 1000000000);
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_TEMP_CORE_TIMERS,
-+ CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_MASK,
-+ temp
-+ << CPR4_MARGIN_TEMP_CORE_TIMERS_SETTLE_VOLTAGE_COUNT_SHIFT);
-+ }
-+
-+ /*
-+ * Allocate memory for cpr4_sdelta structure and sdelta table for
-+ * controller aggregated corner by finding the maximum core count
-+ * used by any cpr3 regulators.
-+ */
-+ ctrl_max_core_count = 1;
-+ ctrl_valid_sdelta = false;
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ thread = &ctrl->thread[i];
-+
-+ /*
-+ * Allocate memory for cpr4_sdelta structure and sdelta table
-+ * for thread aggregated corner by finding the maximum core
-+ * count used by any cpr3 regulators of the thread.
-+ */
-+ thread_max_core_count = 1;
-+ thread_valid_sdelta = false;
-+ for (j = 0; j < thread->vreg_count; j++) {
-+ vreg = &thread->vreg[j];
-+ thread_max_core_count = max(thread_max_core_count,
-+ vreg->max_core_count);
-+ thread_valid_sdelta |= (vreg->allow_core_count_adj
-+ | vreg->allow_temp_adj
-+ | vreg->allow_boost);
-+ }
-+ if (thread_valid_sdelta) {
-+ sdelta = devm_kzalloc(ctrl->dev, sizeof(*sdelta),
-+ GFP_KERNEL);
-+ if (!sdelta)
-+ return -ENOMEM;
-+
-+ sdelta->table = devm_kcalloc(ctrl->dev,
-+ thread_max_core_count
-+ * ctrl->temp_band_count,
-+ sizeof(*sdelta->table),
-+ GFP_KERNEL);
-+ if (!sdelta->table)
-+ return -ENOMEM;
-+
-+ sdelta->boost_table = devm_kcalloc(ctrl->dev,
-+ ctrl->temp_band_count,
-+ sizeof(*sdelta->boost_table),
-+ GFP_KERNEL);
-+ if (!sdelta->boost_table)
-+ return -ENOMEM;
-+
-+ thread->aggr_corner.sdelta = sdelta;
-+ }
-+
-+ ctrl_valid_sdelta |= thread_valid_sdelta;
-+ ctrl_max_core_count = max(ctrl_max_core_count,
-+ thread_max_core_count);
-+ }
-+
-+ if (ctrl_valid_sdelta) {
-+ sdelta = devm_kzalloc(ctrl->dev, sizeof(*sdelta), GFP_KERNEL);
-+ if (!sdelta)
-+ return -ENOMEM;
-+
-+ sdelta->table = devm_kcalloc(ctrl->dev, ctrl_max_core_count
-+ * ctrl->temp_band_count,
-+ sizeof(*sdelta->table), GFP_KERNEL);
-+ if (!sdelta->table)
-+ return -ENOMEM;
-+
-+ sdelta->boost_table = devm_kcalloc(ctrl->dev,
-+ ctrl->temp_band_count,
-+ sizeof(*sdelta->boost_table),
-+ GFP_KERNEL);
-+ if (!sdelta->boost_table)
-+ return -ENOMEM;
-+
-+ ctrl->aggr_corner.sdelta = sdelta;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_write_temp_core_margin() - programs hardware SDELTA registers with
-+ * the voltage margin adjustments that need to be applied for
-+ * different online core-count and temperature bands.
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @addr: SDELTA register address
-+ * @temp_core_adj: Array of voltage margin values for different temperature
-+ * bands.
-+ *
-+ * CPR interface/bus clocks must be enabled before calling this function.
-+ *
-+ * Return: none
-+ */
-+static void cpr3_write_temp_core_margin(struct cpr3_controller *ctrl,
-+ int addr, int *temp_core_adj)
-+{
-+ int i, margin_steps;
-+ u32 reg = 0;
-+
-+ for (i = 0; i < ctrl->temp_band_count; i++) {
-+ margin_steps = max(min(temp_core_adj[i], 127), -128);
-+ reg |= (margin_steps & CPR4_MARGIN_TEMP_CORE_ADJ_MASK) <<
-+ (i * CPR4_MARGIN_TEMP_CORE_ADJ_SHIFT);
-+ }
-+
-+ cpr3_write(ctrl, addr, reg);
-+ cpr3_debug(ctrl, "sdelta offset=0x%08x, val=0x%08x\n", addr, reg);
-+}
-+
-+/**
-+ * cpr3_controller_program_sdelta() - programs hardware SDELTA registers with
-+ * the voltage margin adjustments that need to be applied at
-+ * different online core-count and temperature bands. Also,
-+ * programs hardware register configuration for per-online-core
-+ * and per-temperature based adjustments.
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * CPR interface/bus clocks must be enabled before calling this function.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_controller_program_sdelta(struct cpr3_controller *ctrl)
-+{
-+ struct cpr3_corner *corner = &ctrl->aggr_corner;
-+ struct cpr4_sdelta *sdelta = corner->sdelta;
-+ int i, index, max_core_count, rc = 0;
-+ bool cpr_enabled = ctrl->cpr_enabled;
-+
-+ if (!sdelta)
-+ /* cpr4_sdelta not defined for current aggregated corner */
-+ return 0;
-+
-+ if (ctrl->supports_hw_closed_loop && ctrl->cpr_enabled) {
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK,
-+ (ctrl->use_hw_closed_loop && !sdelta->allow_boost)
-+ ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE : 0);
-+ }
-+
-+ if (!sdelta->allow_core_count_adj && !sdelta->allow_temp_adj
-+ && !sdelta->allow_boost) {
-+ /*
-+ * Per-online-core, per-temperature and voltage boost
-+ * adjustments are disabled for this aggregation corner.
-+ */
-+ return 0;
-+ }
-+
-+ /* Ensure that CPR clocks are enabled before writing to registers. */
-+ if (!cpr_enabled) {
-+ rc = cpr3_clock_enable(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc);
-+ return rc;
-+ }
-+ ctrl->cpr_enabled = true;
-+ }
-+
-+ max_core_count = sdelta->max_core_count;
-+
-+ if (sdelta->allow_core_count_adj || sdelta->allow_temp_adj) {
-+ if (sdelta->allow_core_count_adj) {
-+ /* Program TEMP_CORE0 to same margins as TEMP_CORE1 */
-+ cpr3_write_temp_core_margin(ctrl,
-+ CPR4_REG_MARGIN_TEMP_CORE(0),
-+ &sdelta->table[0]);
-+ }
-+
-+ for (i = 0; i < max_core_count; i++) {
-+ index = i * sdelta->temp_band_count;
-+ /*
-+ * Program TEMP_COREi with voltage margin adjustments
-+ * that need to be applied when the number of cores
-+ * becomes i.
-+ */
-+ cpr3_write_temp_core_margin(ctrl,
-+ CPR4_REG_MARGIN_TEMP_CORE(
-+ sdelta->allow_core_count_adj
-+ ? i + 1 : max_core_count),
-+ &sdelta->table[index]);
-+ }
-+ }
-+
-+ if (sdelta->allow_boost) {
-+ /* Program only boost_num_cores row of SDELTA */
-+ cpr3_write_temp_core_margin(ctrl,
-+ CPR4_REG_MARGIN_TEMP_CORE(sdelta->boost_num_cores),
-+ &sdelta->boost_table[0]);
-+ }
-+
-+ if (!sdelta->allow_core_count_adj && !sdelta->allow_boost) {
-+ cpr3_masked_write(ctrl, CPR4_REG_MISC,
-+ CPR4_MISC_MARGIN_TABLE_ROW_SELECT_MASK,
-+ max_core_count
-+ << CPR4_MISC_MARGIN_TABLE_ROW_SELECT_SHIFT);
-+ }
-+
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_MASK
-+ | CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN
-+ | CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN
-+ | CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN
-+ | CPR4_MARGIN_ADJ_CTL_BOOST_EN,
-+ max_core_count << CPR4_MARGIN_ADJ_CTL_MAX_NUM_CORES_SHIFT
-+ | ((sdelta->allow_core_count_adj || sdelta->allow_boost)
-+ ? CPR4_MARGIN_ADJ_CTL_CORE_ADJ_EN : 0)
-+ | ((sdelta->allow_temp_adj && ctrl->supports_hw_closed_loop)
-+ ? CPR4_MARGIN_ADJ_CTL_TEMP_ADJ_EN : 0)
-+ | (((ctrl->use_hw_closed_loop && !sdelta->allow_boost)
-+ || !ctrl->supports_hw_closed_loop)
-+ ? CPR4_MARGIN_ADJ_CTL_KV_MARGIN_ADJ_EN : 0)
-+ | (sdelta->allow_boost
-+ ? CPR4_MARGIN_ADJ_CTL_BOOST_EN : 0));
-+
-+ /*
-+ * Ensure that all previous CPR register writes have completed before
-+ * continuing.
-+ */
-+ mb();
-+
-+ /* Turn off CPR clocks if they were off before this function call. */
-+ if (!cpr_enabled) {
-+ cpr3_clock_disable(ctrl);
-+ ctrl->cpr_enabled = false;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_init_ctrl() - performs hardware initialization of CPR
-+ * controller registers
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_init_ctrl(struct cpr3_controller *ctrl)
-+{
-+ int i, j, k, m, rc;
-+ u32 ro_used = 0;
-+ u32 gcnt, cont_dly, up_down_dly, val;
-+ u64 temp;
-+ char *mode;
-+
-+ if (ctrl->core_clk) {
-+ rc = clk_set_rate(ctrl->core_clk, ctrl->cpr_clock_rate);
-+ if (rc) {
-+ cpr3_err(ctrl, "clk_set_rate(core_clk, %u) failed, rc=%d\n",
-+ ctrl->cpr_clock_rate, rc);
-+ return rc;
-+ }
-+ }
-+
-+ rc = cpr3_clock_enable(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc);
-+ return rc;
-+ }
-+ ctrl->cpr_enabled = true;
-+
-+ /* Find all RO's used by any corner of any regulator. */
-+ for (i = 0; i < ctrl->thread_count; i++)
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++)
-+ for (k = 0; k < ctrl->thread[i].vreg[j].corner_count;
-+ k++)
-+ for (m = 0; m < CPR3_RO_COUNT; m++)
-+ if (ctrl->thread[i].vreg[j].corner[k].
-+ target_quot[m])
-+ ro_used |= BIT(m);
-+
-+ /* Configure the GCNT of the RO's that will be used */
-+ gcnt = cpr3_regulator_get_gcnt(ctrl);
-+ for (i = 0; i < CPR3_RO_COUNT; i++)
-+ if (ro_used & BIT(i))
-+ cpr3_write(ctrl, CPR3_REG_GCNT(i), gcnt);
-+
-+ /* Configure the loop delay time */
-+ temp = (u64)ctrl->cpr_clock_rate * (u64)ctrl->loop_time;
-+ do_div(temp, 1000000000);
-+ cont_dly = temp;
-+ if (ctrl->supports_hw_closed_loop
-+ && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3)
-+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, cont_dly);
-+ else
-+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT, cont_dly);
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ temp = (u64)ctrl->cpr_clock_rate *
-+ (u64)ctrl->up_down_delay_time;
-+ do_div(temp, 1000000000);
-+ up_down_dly = temp;
-+ if (ctrl->supports_hw_closed_loop)
-+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT,
-+ up_down_dly);
-+ cpr3_debug(ctrl, "up_down_dly=%u, up_down_delay_time=%u ns\n",
-+ up_down_dly, ctrl->up_down_delay_time);
-+ }
-+
-+ cpr3_debug(ctrl, "cpr_clock_rate=%u HZ, sensor_time=%u ns, loop_time=%u ns, gcnt=%u, cont_dly=%u\n",
-+ ctrl->cpr_clock_rate, ctrl->sensor_time, ctrl->loop_time,
-+ gcnt, cont_dly);
-+
-+ /* Configure CPR sensor operation */
-+ val = (ctrl->idle_clocks << CPR3_CPR_CTL_IDLE_CLOCKS_SHIFT)
-+ & CPR3_CPR_CTL_IDLE_CLOCKS_MASK;
-+ val |= (ctrl->count_mode << CPR3_CPR_CTL_COUNT_MODE_SHIFT)
-+ & CPR3_CPR_CTL_COUNT_MODE_MASK;
-+ val |= (ctrl->count_repeat << CPR3_CPR_CTL_COUNT_REPEAT_SHIFT)
-+ & CPR3_CPR_CTL_COUNT_REPEAT_MASK;
-+ cpr3_write(ctrl, CPR3_REG_CPR_CTL, val);
-+
-+ cpr3_debug(ctrl, "idle_clocks=%u, count_mode=%u, count_repeat=%u; CPR_CTL=0x%08X\n",
-+ ctrl->idle_clocks, ctrl->count_mode, ctrl->count_repeat, val);
-+
-+ /* Configure CPR default step quotients */
-+ val = (ctrl->step_quot_init_min << CPR3_CPR_STEP_QUOT_MIN_SHIFT)
-+ & CPR3_CPR_STEP_QUOT_MIN_MASK;
-+ val |= (ctrl->step_quot_init_max << CPR3_CPR_STEP_QUOT_MAX_SHIFT)
-+ & CPR3_CPR_STEP_QUOT_MAX_MASK;
-+ cpr3_write(ctrl, CPR3_REG_CPR_STEP_QUOT, val);
-+
-+ cpr3_debug(ctrl, "step_quot_min=%u, step_quot_max=%u; STEP_QUOT=0x%08X\n",
-+ ctrl->step_quot_init_min, ctrl->step_quot_init_max, val);
-+
-+ /* Configure the CPR sensor ownership */
-+ for (i = 0; i < ctrl->sensor_count; i++)
-+ cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(i),
-+ ctrl->sensor_owner[i]);
-+
-+ /* Configure per-thread registers */
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ rc = cpr3_regulator_init_thread(&ctrl->thread[i]);
-+ if (rc) {
-+ cpr3_err(ctrl, "CPR thread register initialization failed, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ }
-+
-+ if (ctrl->supports_hw_closed_loop) {
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK,
-+ ctrl->use_hw_closed_loop
-+ ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE
-+ : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE);
-+ } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP,
-+ ctrl->use_hw_closed_loop
-+ ? CPR3_HW_CLOSED_LOOP_ENABLE
-+ : CPR3_HW_CLOSED_LOOP_DISABLE);
-+
-+ cpr3_debug(ctrl, "PD_THROTTLE=0x%08X\n",
-+ ctrl->proc_clock_throttle);
-+ }
-+
-+ if ((ctrl->use_hw_closed_loop ||
-+ ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) &&
-+ ctrl->vdd_limit_regulator) {
-+ rc = regulator_enable(ctrl->vdd_limit_regulator);
-+ if (rc) {
-+ cpr3_err(ctrl, "CPR limit regulator enable failed, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ }
-+ }
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ rc = cpr3_regulator_init_cpr4(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "CPR4-specific controller initialization failed, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ }
-+
-+ /* Ensure that all register writes complete before disabling clocks. */
-+ wmb();
-+
-+ cpr3_clock_disable(ctrl);
-+ ctrl->cpr_enabled = false;
-+
-+ if (!ctrl->cpr_allowed_sw || !ctrl->cpr_allowed_hw)
-+ mode = "open-loop";
-+ else if (ctrl->supports_hw_closed_loop)
-+ mode = ctrl->use_hw_closed_loop
-+ ? "HW closed-loop" : "SW closed-loop";
-+ else
-+ mode = "closed-loop";
-+
-+ cpr3_info(ctrl, "Default CPR mode = %s", mode);
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_set_target_quot() - configure the target quotient for each
-+ * RO of the CPR3 thread and set the RO mask
-+ * @thread: Pointer to the CPR3 thread
-+ *
-+ * Return: none
-+ */
-+static void cpr3_regulator_set_target_quot(struct cpr3_thread *thread)
-+{
-+ u32 new_quot, last_quot;
-+ int i;
-+
-+ if (thread->aggr_corner.ro_mask == CPR3_RO_MASK
-+ && thread->last_closed_loop_aggr_corner.ro_mask == CPR3_RO_MASK) {
-+ /* Avoid writing target quotients since all RO's are masked. */
-+ return;
-+ } else if (thread->aggr_corner.ro_mask == CPR3_RO_MASK) {
-+ cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id),
-+ CPR3_RO_MASK);
-+ thread->last_closed_loop_aggr_corner.ro_mask = CPR3_RO_MASK;
-+ /*
-+ * Only the RO_MASK register needs to be written since all
-+ * RO's are masked.
-+ */
-+ return;
-+ } else if (thread->aggr_corner.ro_mask
-+ != thread->last_closed_loop_aggr_corner.ro_mask) {
-+ cpr3_write(thread->ctrl, CPR3_REG_RO_MASK(thread->thread_id),
-+ thread->aggr_corner.ro_mask);
-+ }
-+
-+ for (i = 0; i < CPR3_RO_COUNT; i++) {
-+ new_quot = thread->aggr_corner.target_quot[i];
-+ last_quot = thread->last_closed_loop_aggr_corner.target_quot[i];
-+ if (new_quot != last_quot)
-+ cpr3_write(thread->ctrl,
-+ CPR3_REG_TARGET_QUOT(thread->thread_id, i),
-+ new_quot);
-+ }
-+
-+ thread->last_closed_loop_aggr_corner = thread->aggr_corner;
-+
-+ return;
-+}
-+
-+/**
-+ * cpr3_update_vreg_closed_loop_volt() - update the last known settled
-+ * closed loop voltage for a CPR3 regulator
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @vdd_volt: Last known settled voltage in microvolts for the
-+ * VDD supply
-+ * @reg_last_measurement: Value read from the LAST_MEASUREMENT register
-+ *
-+ * Return: none
-+ */
-+static void cpr3_update_vreg_closed_loop_volt(struct cpr3_regulator *vreg,
-+ int vdd_volt, u32 reg_last_measurement)
-+{
-+ bool step_dn, step_up, aggr_step_up, aggr_step_dn, aggr_step_mid;
-+ bool valid, pd_valid, saw_error;
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ struct cpr3_corner *corner;
-+ u32 id;
-+
-+ if (vreg->last_closed_loop_corner == CPR3_REGULATOR_CORNER_INVALID)
-+ return;
-+ else
-+ corner = &vreg->corner[vreg->last_closed_loop_corner];
-+
-+ if (vreg->thread->last_closed_loop_aggr_corner.ro_mask
-+ == CPR3_RO_MASK || !vreg->aggregated) {
-+ return;
-+ } else if (!ctrl->cpr_enabled || !ctrl->last_corner_was_closed_loop) {
-+ return;
-+ } else if (ctrl->thread_count == 1
-+ && vdd_volt >= corner->floor_volt
-+ && vdd_volt <= corner->ceiling_volt) {
-+ corner->last_volt = vdd_volt;
-+ cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d\n",
-+ vreg->last_closed_loop_corner, corner->last_volt,
-+ vreg->last_closed_loop_corner,
-+ corner->ceiling_volt,
-+ vreg->last_closed_loop_corner,
-+ corner->floor_volt);
-+ return;
-+ } else if (!ctrl->supports_hw_closed_loop) {
-+ return;
-+ } else if (ctrl->ctrl_type != CPR_CTRL_TYPE_CPR3) {
-+ corner->last_volt = vdd_volt;
-+ cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d\n",
-+ vreg->last_closed_loop_corner, corner->last_volt,
-+ vreg->last_closed_loop_corner,
-+ corner->ceiling_volt,
-+ vreg->last_closed_loop_corner,
-+ corner->floor_volt);
-+ return;
-+ }
-+
-+ /* CPR clocks are on and HW closed loop is supported */
-+ valid = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_VALID);
-+ if (!valid) {
-+ cpr3_debug(vreg, "CPR_LAST_VALID_MEASUREMENT=0x%X valid bit not set\n",
-+ reg_last_measurement);
-+ return;
-+ }
-+
-+ id = vreg->thread->thread_id;
-+
-+ step_dn
-+ = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_THREAD_DN(id));
-+ step_up
-+ = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_THREAD_UP(id));
-+ aggr_step_dn = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_DN);
-+ aggr_step_mid
-+ = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_MID);
-+ aggr_step_up = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_AGGR_UP);
-+ saw_error = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_SAW_ERROR);
-+ pd_valid
-+ = !((((reg_last_measurement & CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK)
-+ >> CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT)
-+ & vreg->pd_bypass_mask) == vreg->pd_bypass_mask);
-+
-+ if (!pd_valid) {
-+ cpr3_debug(vreg, "CPR_LAST_VALID_MEASUREMENT=0x%X, all power domains bypassed\n",
-+ reg_last_measurement);
-+ return;
-+ } else if (step_dn && step_up) {
-+ cpr3_err(vreg, "both up and down status bits set, CPR_LAST_VALID_MEASUREMENT=0x%X\n",
-+ reg_last_measurement);
-+ return;
-+ } else if (aggr_step_dn && step_dn && vdd_volt < corner->last_volt
-+ && vdd_volt >= corner->floor_volt) {
-+ corner->last_volt = vdd_volt;
-+ } else if (aggr_step_up && step_up && vdd_volt > corner->last_volt
-+ && vdd_volt <= corner->ceiling_volt) {
-+ corner->last_volt = vdd_volt;
-+ } else if (aggr_step_mid
-+ && vdd_volt >= corner->floor_volt
-+ && vdd_volt <= corner->ceiling_volt) {
-+ corner->last_volt = vdd_volt;
-+ } else if (saw_error && (vdd_volt == corner->ceiling_volt
-+ || vdd_volt == corner->floor_volt)) {
-+ corner->last_volt = vdd_volt;
-+ } else {
-+ cpr3_debug(vreg, "last_volt not updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d, vdd_volt=%d, CPR_LAST_VALID_MEASUREMENT=0x%X\n",
-+ vreg->last_closed_loop_corner, corner->last_volt,
-+ vreg->last_closed_loop_corner,
-+ corner->ceiling_volt,
-+ vreg->last_closed_loop_corner, corner->floor_volt,
-+ vdd_volt, reg_last_measurement);
-+ return;
-+ }
-+
-+ cpr3_debug(vreg, "last_volt updated: last_volt[%d]=%d, ceiling_volt[%d]=%d, floor_volt[%d]=%d, CPR_LAST_VALID_MEASUREMENT=0x%X\n",
-+ vreg->last_closed_loop_corner, corner->last_volt,
-+ vreg->last_closed_loop_corner, corner->ceiling_volt,
-+ vreg->last_closed_loop_corner, corner->floor_volt,
-+ reg_last_measurement);
-+}
-+
-+/**
-+ * cpr3_regulator_mem_acc_bhs_used() - determines if mem-acc regulators powered
-+ * through a BHS are associated with the CPR3 controller or any of
-+ * the CPR3 regulators it controls.
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * This function determines if the CPR3 controller or any of its CPR3 regulators
-+ * need to manage mem-acc regulators that are currently powered through a BHS
-+ * and whose corner selection is based upon a particular voltage threshold.
-+ *
-+ * Return: true or false
-+ */
-+static bool cpr3_regulator_mem_acc_bhs_used(struct cpr3_controller *ctrl)
-+{
-+ struct cpr3_regulator *vreg;
-+ int i, j;
-+
-+ if (!ctrl->mem_acc_threshold_volt)
-+ return false;
-+
-+ if (ctrl->mem_acc_regulator)
-+ return true;
-+
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+
-+ if (vreg->mem_acc_regulator)
-+ return true;
-+ }
-+ }
-+
-+ return false;
-+}
-+
-+/**
-+ * cpr3_regulator_config_bhs_mem_acc() - configure the mem-acc regulator
-+ * settings for hardware blocks currently powered through the BHS.
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @new_volt: New voltage in microvolts that VDD supply needs to
-+ * end up at
-+ * @last_volt: Pointer to the last known voltage in microvolts for the
-+ * VDD supply
-+ * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max
-+ * corner aggregated from all CPR3 threads managed by the
-+ * CPR3 controller
-+ *
-+ * This function programs the mem-acc regulator corners for CPR3 regulators
-+ * whose LDO regulators are in bypassed state. The function also handles
-+ * CPR3 controllers which utilize mem-acc regulators that operate independently
-+ * from the LDO hardware and that must be programmed when the VDD supply
-+ * crosses a particular voltage threshold.
-+ *
-+ * Return: 0 on success, errno on failure. If the VDD supply voltage is
-+ * modified, last_volt is updated to reflect the new voltage setpoint.
-+ */
-+static int cpr3_regulator_config_bhs_mem_acc(struct cpr3_controller *ctrl,
-+ int new_volt, int *last_volt,
-+ struct cpr3_corner *aggr_corner)
-+{
-+ struct cpr3_regulator *vreg;
-+ int i, j, rc, mem_acc_corn, safe_volt;
-+ int mem_acc_volt = ctrl->mem_acc_threshold_volt;
-+ int ref_volt;
-+
-+ if (!cpr3_regulator_mem_acc_bhs_used(ctrl))
-+ return 0;
-+
-+ ref_volt = ctrl->use_hw_closed_loop ? aggr_corner->floor_volt :
-+ new_volt;
-+
-+ if (((*last_volt < mem_acc_volt && mem_acc_volt <= ref_volt) ||
-+ (*last_volt >= mem_acc_volt && mem_acc_volt > ref_volt))) {
-+ if (ref_volt < *last_volt)
-+ safe_volt = max(mem_acc_volt, aggr_corner->last_volt);
-+ else
-+ safe_volt = max(mem_acc_volt, *last_volt);
-+
-+ rc = regulator_set_voltage(ctrl->vdd_regulator, safe_volt,
-+ new_volt < *last_volt ?
-+ ctrl->aggr_corner.ceiling_volt :
-+ new_volt);
-+ if (rc) {
-+ cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n",
-+ safe_volt, rc);
-+ return rc;
-+ }
-+
-+ *last_volt = safe_volt;
-+
-+ mem_acc_corn = ref_volt < mem_acc_volt ?
-+ ctrl->mem_acc_corner_map[CPR3_MEM_ACC_LOW_CORNER] :
-+ ctrl->mem_acc_corner_map[CPR3_MEM_ACC_HIGH_CORNER];
-+
-+ if (ctrl->mem_acc_regulator) {
-+ rc = regulator_set_voltage(ctrl->mem_acc_regulator,
-+ mem_acc_corn, mem_acc_corn);
-+ if (rc) {
-+ cpr3_err(ctrl, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n",
-+ mem_acc_corn, rc);
-+ return rc;
-+ }
-+ }
-+
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+
-+ if (!vreg->mem_acc_regulator)
-+ continue;
-+
-+ rc = regulator_set_voltage(
-+ vreg->mem_acc_regulator, mem_acc_corn,
-+ mem_acc_corn);
-+ if (rc) {
-+ cpr3_err(vreg, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n",
-+ mem_acc_corn, rc);
-+ return rc;
-+ }
-+ }
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_switch_apm_mode() - switch the mode of the APM controller
-+ * associated with a given CPR3 controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @new_volt: New voltage in microvolts that VDD supply needs to
-+ * end up at
-+ * @last_volt: Pointer to the last known voltage in microvolts for the
-+ * VDD supply
-+ * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max
-+ * corner aggregated from all CPR3 threads managed by the
-+ * CPR3 controller
-+ *
-+ * This function requests a switch of the APM mode while guaranteeing
-+ * any LDO regulator hardware requirements are satisfied. The function must
-+ * be called once it is known a new VDD supply setpoint crosses the APM
-+ * voltage threshold.
-+ *
-+ * Return: 0 on success, errno on failure. If the VDD supply voltage is
-+ * modified, last_volt is updated to reflect the new voltage setpoint.
-+ */
-+static int cpr3_regulator_switch_apm_mode(struct cpr3_controller *ctrl,
-+ int new_volt, int *last_volt,
-+ struct cpr3_corner *aggr_corner)
-+{
-+ struct regulator *vdd = ctrl->vdd_regulator;
-+ int apm_volt = ctrl->apm_threshold_volt;
-+ int orig_last_volt = *last_volt;
-+ int rc;
-+
-+ rc = regulator_set_voltage(vdd, apm_volt, apm_volt);
-+ if (rc) {
-+ cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n",
-+ apm_volt, rc);
-+ return rc;
-+ }
-+
-+ *last_volt = apm_volt;
-+
-+ rc = msm_apm_set_supply(ctrl->apm, new_volt >= apm_volt
-+ ? ctrl->apm_high_supply : ctrl->apm_low_supply);
-+ if (rc) {
-+ cpr3_err(ctrl, "APM switch failed, rc=%d\n", rc);
-+ /* Roll back the voltage. */
-+ regulator_set_voltage(vdd, orig_last_volt, INT_MAX);
-+ *last_volt = orig_last_volt;
-+ return rc;
-+ }
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_config_voltage_crossings() - configure APM and mem-acc
-+ * settings depending upon a new VDD supply setpoint
-+ *
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @new_volt: New voltage in microvolts that VDD supply needs to
-+ * end up at
-+ * @last_volt: Pointer to the last known voltage in microvolts for the
-+ * VDD supply
-+ * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max
-+ * corner aggregated from all CPR3 threads managed by the
-+ * CPR3 controller
-+ *
-+ * This function handles the APM and mem-acc regulator reconfiguration if
-+ * the new VDD supply voltage will result in crossing their respective voltage
-+ * thresholds.
-+ *
-+ * Return: 0 on success, errno on failure. If the VDD supply voltage is
-+ * modified, last_volt is updated to reflect the new voltage setpoint.
-+ */
-+static int cpr3_regulator_config_voltage_crossings(struct cpr3_controller *ctrl,
-+ int new_volt, int *last_volt,
-+ struct cpr3_corner *aggr_corner)
-+{
-+ bool apm_crossing = false, mem_acc_crossing = false;
-+ bool mem_acc_bhs_used;
-+ int apm_volt = ctrl->apm_threshold_volt;
-+ int mem_acc_volt = ctrl->mem_acc_threshold_volt;
-+ int ref_volt, rc;
-+
-+ if (ctrl->apm && apm_volt > 0
-+ && ((*last_volt < apm_volt && apm_volt <= new_volt)
-+ || (*last_volt >= apm_volt && apm_volt > new_volt)))
-+ apm_crossing = true;
-+
-+ mem_acc_bhs_used = cpr3_regulator_mem_acc_bhs_used(ctrl);
-+
-+ ref_volt = ctrl->use_hw_closed_loop ? aggr_corner->floor_volt :
-+ new_volt;
-+
-+ if (mem_acc_bhs_used &&
-+ (((*last_volt < mem_acc_volt && mem_acc_volt <= ref_volt) ||
-+ (*last_volt >= mem_acc_volt && mem_acc_volt > ref_volt))))
-+ mem_acc_crossing = true;
-+
-+ if (apm_crossing && mem_acc_crossing) {
-+ if ((new_volt < *last_volt && apm_volt >= mem_acc_volt) ||
-+ (new_volt >= *last_volt && apm_volt < mem_acc_volt)) {
-+ rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt,
-+ last_volt,
-+ aggr_corner);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to switch APM mode\n");
-+ return rc;
-+ }
-+
-+ rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt,
-+ last_volt, aggr_corner);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n");
-+ return rc;
-+ }
-+ } else {
-+ rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt,
-+ last_volt, aggr_corner);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n");
-+ return rc;
-+ }
-+
-+ rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt,
-+ last_volt,
-+ aggr_corner);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to switch APM mode\n");
-+ return rc;
-+ }
-+ }
-+ } else if (apm_crossing) {
-+ rc = cpr3_regulator_switch_apm_mode(ctrl, new_volt, last_volt,
-+ aggr_corner);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to switch APM mode\n");
-+ return rc;
-+ }
-+ } else if (mem_acc_crossing) {
-+ rc = cpr3_regulator_config_bhs_mem_acc(ctrl, new_volt,
-+ last_volt, aggr_corner);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to configure BHS mem-acc settings\n");
-+ return rc;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_config_mem_acc() - configure the corner of the mem-acc
-+ * regulator associated with the CPR3 controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max
-+ * corner aggregated from all CPR3 threads managed by the
-+ * CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_config_mem_acc(struct cpr3_controller *ctrl,
-+ struct cpr3_corner *aggr_corner)
-+{
-+ int rc;
-+
-+ if (ctrl->mem_acc_regulator && aggr_corner->mem_acc_volt) {
-+ rc = regulator_set_voltage(ctrl->mem_acc_regulator,
-+ aggr_corner->mem_acc_volt,
-+ aggr_corner->mem_acc_volt);
-+ if (rc) {
-+ cpr3_err(ctrl, "regulator_set_voltage(mem_acc) == %d failed, rc=%d\n",
-+ aggr_corner->mem_acc_volt, rc);
-+ return rc;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_scale_vdd_voltage() - scale the CPR controlled VDD supply
-+ * voltage to the new level while satisfying any other hardware
-+ * requirements
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @new_volt: New voltage in microvolts that VDD supply needs to end
-+ * up at
-+ * @last_volt: Last known voltage in microvolts for the VDD supply
-+ * @aggr_corner: Pointer to the CPR3 corner which corresponds to the max
-+ * corner aggregated from all CPR3 threads managed by the
-+ * CPR3 controller
-+ *
-+ * This function scales the CPR controlled VDD supply voltage from its
-+ * current level to the new voltage that is specified. If the supply is
-+ * configured to use the APM and the APM threshold is crossed as a result of
-+ * the voltage scaling, then this function also stops at the APM threshold,
-+ * switches the APM source, and finally sets the final new voltage.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_scale_vdd_voltage(struct cpr3_controller *ctrl,
-+ int new_volt, int last_volt,
-+ struct cpr3_corner *aggr_corner)
-+{
-+ struct regulator *vdd = ctrl->vdd_regulator;
-+ int rc;
-+
-+ if (new_volt < last_volt) {
-+ rc = cpr3_regulator_config_mem_acc(ctrl, aggr_corner);
-+ if (rc)
-+ return rc;
-+ } else {
-+ /* Increasing VDD voltage */
-+ if (ctrl->system_regulator) {
-+ rc = regulator_set_voltage(ctrl->system_regulator,
-+ aggr_corner->system_volt, INT_MAX);
-+ if (rc) {
-+ cpr3_err(ctrl, "regulator_set_voltage(system) == %d failed, rc=%d\n",
-+ aggr_corner->system_volt, rc);
-+ return rc;
-+ }
-+ }
-+ }
-+
-+ rc = cpr3_regulator_config_voltage_crossings(ctrl, new_volt, &last_volt,
-+ aggr_corner);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to handle voltage threshold crossing configurations, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ /*
-+ * Subtract a small amount from the min_uV parameter so that the
-+ * set voltage request is not dropped by the framework due to being
-+ * duplicate. This is needed in order to switch from hardware
-+ * closed-loop to open-loop successfully.
-+ */
-+ rc = regulator_set_voltage(vdd, new_volt - (ctrl->cpr_enabled ? 0 : 1),
-+ aggr_corner->ceiling_volt);
-+ if (rc) {
-+ cpr3_err(ctrl, "regulator_set_voltage(vdd) == %d failed, rc=%d\n",
-+ new_volt, rc);
-+ return rc;
-+ }
-+
-+ if (new_volt == last_volt && ctrl->supports_hw_closed_loop
-+ && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ /*
-+ * CPR4 features enforce voltage reprogramming when the last
-+ * set voltage and new set voltage are same. This way, we can
-+ * ensure that SAW PMIC STATUS register is updated with newly
-+ * programmed voltage.
-+ */
-+ rc = regulator_sync_voltage(vdd);
-+ if (rc) {
-+ cpr3_err(ctrl, "regulator_sync_voltage(vdd) == %d failed, rc=%d\n",
-+ new_volt, rc);
-+ return rc;
-+ }
-+ }
-+
-+ if (new_volt >= last_volt) {
-+ rc = cpr3_regulator_config_mem_acc(ctrl, aggr_corner);
-+ if (rc)
-+ return rc;
-+ } else {
-+ /* Decreasing VDD voltage */
-+ if (ctrl->system_regulator) {
-+ rc = regulator_set_voltage(ctrl->system_regulator,
-+ aggr_corner->system_volt, INT_MAX);
-+ if (rc) {
-+ cpr3_err(ctrl, "regulator_set_voltage(system) == %d failed, rc=%d\n",
-+ aggr_corner->system_volt, rc);
-+ return rc;
-+ }
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_get_dynamic_floor_volt() - returns the current dynamic floor
-+ * voltage based upon static configurations and the state of all
-+ * power domains during the last CPR measurement
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @reg_last_measurement: Value read from the LAST_MEASUREMENT register
-+ *
-+ * When using HW closed-loop, the dynamic floor voltage is always returned
-+ * regardless of the current state of the power domains.
-+ *
-+ * Return: dynamic floor voltage in microvolts or 0 if dynamic floor is not
-+ * currently required
-+ */
-+static int cpr3_regulator_get_dynamic_floor_volt(struct cpr3_controller *ctrl,
-+ u32 reg_last_measurement)
-+{
-+ int dynamic_floor_volt = 0;
-+ struct cpr3_regulator *vreg;
-+ bool valid, pd_valid;
-+ u32 bypass_bits;
-+ int i, j;
-+
-+ if (!ctrl->supports_hw_closed_loop)
-+ return 0;
-+
-+ if (likely(!ctrl->use_hw_closed_loop)) {
-+ valid = !!(reg_last_measurement & CPR3_LAST_MEASUREMENT_VALID);
-+ bypass_bits
-+ = (reg_last_measurement & CPR3_LAST_MEASUREMENT_PD_BYPASS_MASK)
-+ >> CPR3_LAST_MEASUREMENT_PD_BYPASS_SHIFT;
-+ } else {
-+ /*
-+ * Ensure that the dynamic floor voltage is always used for
-+ * HW closed-loop since the conditions below cannot be evaluated
-+ * after each CPR measurement.
-+ */
-+ valid = false;
-+ bypass_bits = 0;
-+ }
-+
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+
-+ if (!vreg->uses_dynamic_floor)
-+ continue;
-+
-+ pd_valid = !((bypass_bits & vreg->pd_bypass_mask)
-+ == vreg->pd_bypass_mask);
-+
-+ if (!valid || !pd_valid)
-+ dynamic_floor_volt = max(dynamic_floor_volt,
-+ vreg->corner[
-+ vreg->dynamic_floor_corner].last_volt);
-+ }
-+ }
-+
-+ return dynamic_floor_volt;
-+}
-+
-+/**
-+ * cpr3_regulator_max_sdelta_diff() - returns the maximum voltage difference in
-+ * microvolts that can result from different operating conditions
-+ * for the specified sdelta struct
-+ * @sdelta: Pointer to the sdelta structure
-+ * @step_volt: Step size in microvolts between available set
-+ * points of the VDD supply.
-+ *
-+ * Return: voltage difference between the highest and lowest adjustments if
-+ * sdelta and sdelta->table are valid, else 0.
-+ */
-+static int cpr3_regulator_max_sdelta_diff(const struct cpr4_sdelta *sdelta,
-+ int step_volt)
-+{
-+ int i, j, index, sdelta_min = INT_MAX, sdelta_max = INT_MIN;
-+
-+ if (!sdelta || !sdelta->table)
-+ return 0;
-+
-+ for (i = 0; i < sdelta->max_core_count; i++) {
-+ for (j = 0; j < sdelta->temp_band_count; j++) {
-+ index = i * sdelta->temp_band_count + j;
-+ sdelta_min = min(sdelta_min, sdelta->table[index]);
-+ sdelta_max = max(sdelta_max, sdelta->table[index]);
-+ }
-+ }
-+
-+ return (sdelta_max - sdelta_min) * step_volt;
-+}
-+
-+/**
-+ * cpr3_regulator_aggregate_sdelta() - check open-loop voltages of current
-+ * aggregated corner and current corner of a given regulator
-+ * and adjust the sdelta strucuture data of aggregate corner.
-+ * @aggr_corner: Pointer to accumulated aggregated corner which
-+ * is both an input and an output
-+ * @corner: Pointer to the corner to be aggregated with
-+ * aggr_corner
-+ * @step_volt: Step size in microvolts between available set
-+ * points of the VDD supply.
-+ *
-+ * Return: none
-+ */
-+static void cpr3_regulator_aggregate_sdelta(
-+ struct cpr3_corner *aggr_corner,
-+ const struct cpr3_corner *corner, int step_volt)
-+{
-+ struct cpr4_sdelta *aggr_sdelta, *sdelta;
-+ int aggr_core_count, core_count, temp_band_count;
-+ u32 aggr_index, index;
-+ int i, j, sdelta_size, cap_steps, adjust_sdelta;
-+
-+ aggr_sdelta = aggr_corner->sdelta;
-+ sdelta = corner->sdelta;
-+
-+ if (aggr_corner->open_loop_volt < corner->open_loop_volt) {
-+ /*
-+ * Found the new dominant regulator as its open-loop requirement
-+ * is higher than previous dominant regulator. Calculate cap
-+ * voltage to limit the SDELTA values to make sure the runtime
-+ * (Core-count/temp) adjustments do not violate other
-+ * regulators' voltage requirements. Use cpr4_sdelta values of
-+ * new dominant regulator.
-+ */
-+ aggr_sdelta->cap_volt = min(aggr_sdelta->cap_volt,
-+ (corner->open_loop_volt -
-+ aggr_corner->open_loop_volt));
-+
-+ /* Clear old data in the sdelta table */
-+ sdelta_size = aggr_sdelta->max_core_count
-+ * aggr_sdelta->temp_band_count;
-+
-+ if (aggr_sdelta->allow_core_count_adj
-+ || aggr_sdelta->allow_temp_adj)
-+ memset(aggr_sdelta->table, 0, sdelta_size
-+ * sizeof(*aggr_sdelta->table));
-+
-+ if (sdelta->allow_temp_adj || sdelta->allow_core_count_adj) {
-+ /* Copy new data in sdelta table */
-+ sdelta_size = sdelta->max_core_count
-+ * sdelta->temp_band_count;
-+ if (sdelta->table)
-+ memcpy(aggr_sdelta->table, sdelta->table,
-+ sdelta_size * sizeof(*sdelta->table));
-+ }
-+
-+ if (sdelta->allow_boost) {
-+ memcpy(aggr_sdelta->boost_table, sdelta->boost_table,
-+ sdelta->temp_band_count
-+ * sizeof(*sdelta->boost_table));
-+ aggr_sdelta->boost_num_cores = sdelta->boost_num_cores;
-+ } else if (aggr_sdelta->allow_boost) {
-+ for (i = 0; i < aggr_sdelta->temp_band_count; i++) {
-+ adjust_sdelta = (corner->open_loop_volt
-+ - aggr_corner->open_loop_volt)
-+ / step_volt;
-+ aggr_sdelta->boost_table[i] += adjust_sdelta;
-+ aggr_sdelta->boost_table[i]
-+ = min(aggr_sdelta->boost_table[i], 0);
-+ }
-+ }
-+
-+ aggr_corner->open_loop_volt = corner->open_loop_volt;
-+ aggr_sdelta->allow_temp_adj = sdelta->allow_temp_adj;
-+ aggr_sdelta->allow_core_count_adj
-+ = sdelta->allow_core_count_adj;
-+ aggr_sdelta->max_core_count = sdelta->max_core_count;
-+ aggr_sdelta->temp_band_count = sdelta->temp_band_count;
-+ } else if (aggr_corner->open_loop_volt > corner->open_loop_volt) {
-+ /*
-+ * Adjust the cap voltage if the open-loop requirement of new
-+ * regulator is the next highest.
-+ */
-+ aggr_sdelta->cap_volt = min(aggr_sdelta->cap_volt,
-+ (aggr_corner->open_loop_volt
-+ - corner->open_loop_volt));
-+
-+ if (sdelta->allow_boost) {
-+ for (i = 0; i < aggr_sdelta->temp_band_count; i++) {
-+ adjust_sdelta = (aggr_corner->open_loop_volt
-+ - corner->open_loop_volt)
-+ / step_volt;
-+ aggr_sdelta->boost_table[i] =
-+ sdelta->boost_table[i] + adjust_sdelta;
-+ aggr_sdelta->boost_table[i]
-+ = min(aggr_sdelta->boost_table[i], 0);
-+ }
-+ aggr_sdelta->boost_num_cores = sdelta->boost_num_cores;
-+ }
-+ } else {
-+ /*
-+ * Found another dominant regulator with same open-loop
-+ * requirement. Make cap voltage to '0'. Disable core-count
-+ * adjustments as we couldn't support for both regulators.
-+ * Keep enable temp based adjustments if enabled for both
-+ * regulators and choose mininum margin adjustment values
-+ * between them.
-+ */
-+ aggr_sdelta->cap_volt = 0;
-+ aggr_sdelta->allow_core_count_adj = false;
-+
-+ if (aggr_sdelta->allow_temp_adj
-+ && sdelta->allow_temp_adj) {
-+ aggr_core_count = aggr_sdelta->max_core_count - 1;
-+ core_count = sdelta->max_core_count - 1;
-+ temp_band_count = sdelta->temp_band_count;
-+ for (j = 0; j < temp_band_count; j++) {
-+ aggr_index = aggr_core_count * temp_band_count
-+ + j;
-+ index = core_count * temp_band_count + j;
-+ aggr_sdelta->table[aggr_index] =
-+ min(aggr_sdelta->table[aggr_index],
-+ sdelta->table[index]);
-+ }
-+ } else {
-+ aggr_sdelta->allow_temp_adj = false;
-+ }
-+
-+ if (sdelta->allow_boost) {
-+ memcpy(aggr_sdelta->boost_table, sdelta->boost_table,
-+ sdelta->temp_band_count
-+ * sizeof(*sdelta->boost_table));
-+ aggr_sdelta->boost_num_cores = sdelta->boost_num_cores;
-+ }
-+ }
-+
-+ /* Keep non-dominant clients boost enable state */
-+ aggr_sdelta->allow_boost |= sdelta->allow_boost;
-+ if (aggr_sdelta->allow_boost)
-+ aggr_sdelta->allow_core_count_adj = false;
-+
-+ if (aggr_sdelta->cap_volt && !(aggr_sdelta->cap_volt == INT_MAX)) {
-+ core_count = aggr_sdelta->max_core_count;
-+ temp_band_count = aggr_sdelta->temp_band_count;
-+ /*
-+ * Convert cap voltage from uV to PMIC steps and use to limit
-+ * sdelta margin adjustments.
-+ */
-+ cap_steps = aggr_sdelta->cap_volt / step_volt;
-+ for (i = 0; i < core_count; i++)
-+ for (j = 0; j < temp_band_count; j++) {
-+ index = i * temp_band_count + j;
-+ aggr_sdelta->table[index] =
-+ min(aggr_sdelta->table[index],
-+ cap_steps);
-+ }
-+ }
-+}
-+
-+/**
-+ * cpr3_regulator_aggregate_corners() - aggregate two corners together
-+ * @aggr_corner: Pointer to accumulated aggregated corner which
-+ * is both an input and an output
-+ * @corner: Pointer to the corner to be aggregated with
-+ * aggr_corner
-+ * @aggr_quot: Flag indicating that target quotients should be
-+ * aggregated as well.
-+ * @step_volt: Step size in microvolts between available set
-+ * points of the VDD supply.
-+ *
-+ * Return: none
-+ */
-+static void cpr3_regulator_aggregate_corners(struct cpr3_corner *aggr_corner,
-+ const struct cpr3_corner *corner, bool aggr_quot,
-+ int step_volt)
-+{
-+ int i;
-+
-+ aggr_corner->ceiling_volt
-+ = max(aggr_corner->ceiling_volt, corner->ceiling_volt);
-+ aggr_corner->floor_volt
-+ = max(aggr_corner->floor_volt, corner->floor_volt);
-+ aggr_corner->last_volt
-+ = max(aggr_corner->last_volt, corner->last_volt);
-+ aggr_corner->system_volt
-+ = max(aggr_corner->system_volt, corner->system_volt);
-+ aggr_corner->mem_acc_volt
-+ = max(aggr_corner->mem_acc_volt, corner->mem_acc_volt);
-+ aggr_corner->irq_en |= corner->irq_en;
-+ aggr_corner->use_open_loop |= corner->use_open_loop;
-+
-+ if (aggr_quot) {
-+ aggr_corner->ro_mask &= corner->ro_mask;
-+
-+ for (i = 0; i < CPR3_RO_COUNT; i++)
-+ aggr_corner->target_quot[i]
-+ = max(aggr_corner->target_quot[i],
-+ corner->target_quot[i]);
-+ }
-+
-+ if (aggr_corner->sdelta && corner->sdelta
-+ && (aggr_corner->sdelta->table
-+ || aggr_corner->sdelta->boost_table)) {
-+ cpr3_regulator_aggregate_sdelta(aggr_corner, corner, step_volt);
-+ } else {
-+ aggr_corner->open_loop_volt
-+ = max(aggr_corner->open_loop_volt,
-+ corner->open_loop_volt);
-+ }
-+}
-+
-+/**
-+ * cpr3_regulator_update_ctrl_state() - update the state of the CPR controller
-+ * to reflect the corners used by all CPR3 regulators as well as
-+ * the CPR operating mode
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * This function aggregates the CPR parameters for all CPR3 regulators
-+ * associated with the VDD supply. Upon success, it sets the aggregated last
-+ * known good voltage.
-+ *
-+ * The VDD supply voltage will not be physically configured unless this
-+ * condition is met by at least one of the regulators of the controller:
-+ * regulator->vreg_enabled == true &&
-+ * regulator->current_corner != CPR3_REGULATOR_CORNER_INVALID
-+ *
-+ * CPR registers for the controller and each thread are updated as long as
-+ * ctrl->cpr_enabled == true.
-+ *
-+ * Note, CPR3 controller lock must be held by the caller.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int _cpr3_regulator_update_ctrl_state(struct cpr3_controller *ctrl)
-+{
-+ struct cpr3_corner aggr_corner = {};
-+ struct cpr3_thread *thread;
-+ struct cpr3_regulator *vreg;
-+ struct cpr4_sdelta *sdelta;
-+ bool valid = false;
-+ bool thread_valid;
-+ int i, j, rc, new_volt, vdd_volt, dynamic_floor_volt, last_corner_volt;
-+ u32 reg_last_measurement = 0, sdelta_size;
-+ int *sdelta_table, *boost_table;
-+
-+ last_corner_volt = 0;
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ rc = cpr3_ctrl_clear_cpr4_config(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ }
-+
-+ cpr3_ctrl_loop_disable(ctrl);
-+
-+ vdd_volt = regulator_get_voltage(ctrl->vdd_regulator);
-+ if (vdd_volt < 0) {
-+ cpr3_err(ctrl, "regulator_get_voltage(vdd) failed, rc=%d\n",
-+ vdd_volt);
-+ return vdd_volt;
-+ }
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ /*
-+ * Save aggregated corner open-loop voltage which was programmed
-+ * during last corner switch which is used when programming new
-+ * aggregated corner open-loop voltage.
-+ */
-+ last_corner_volt = ctrl->aggr_corner.open_loop_volt;
-+ }
-+
-+ if (ctrl->cpr_enabled && ctrl->use_hw_closed_loop &&
-+ ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3)
-+ reg_last_measurement
-+ = cpr3_read(ctrl, CPR3_REG_LAST_MEASUREMENT);
-+
-+ aggr_corner.sdelta = ctrl->aggr_corner.sdelta;
-+ if (aggr_corner.sdelta) {
-+ sdelta = aggr_corner.sdelta;
-+ sdelta_table = sdelta->table;
-+ if (sdelta_table) {
-+ sdelta_size = sdelta->max_core_count *
-+ sdelta->temp_band_count;
-+ memset(sdelta_table, 0, sdelta_size
-+ * sizeof(*sdelta_table));
-+ }
-+
-+ boost_table = sdelta->boost_table;
-+ if (boost_table)
-+ memset(boost_table, 0, sdelta->temp_band_count
-+ * sizeof(*boost_table));
-+
-+ memset(sdelta, 0, sizeof(*sdelta));
-+ sdelta->table = sdelta_table;
-+ sdelta->cap_volt = INT_MAX;
-+ sdelta->boost_table = boost_table;
-+ }
-+
-+ /* Aggregate the requests of all threads */
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ thread = &ctrl->thread[i];
-+ thread_valid = false;
-+
-+ sdelta = thread->aggr_corner.sdelta;
-+ if (sdelta) {
-+ sdelta_table = sdelta->table;
-+ if (sdelta_table) {
-+ sdelta_size = sdelta->max_core_count *
-+ sdelta->temp_band_count;
-+ memset(sdelta_table, 0, sdelta_size
-+ * sizeof(*sdelta_table));
-+ }
-+
-+ boost_table = sdelta->boost_table;
-+ if (boost_table)
-+ memset(boost_table, 0, sdelta->temp_band_count
-+ * sizeof(*boost_table));
-+
-+ memset(sdelta, 0, sizeof(*sdelta));
-+ sdelta->table = sdelta_table;
-+ sdelta->cap_volt = INT_MAX;
-+ sdelta->boost_table = boost_table;
-+ }
-+
-+ memset(&thread->aggr_corner, 0, sizeof(thread->aggr_corner));
-+ thread->aggr_corner.sdelta = sdelta;
-+ thread->aggr_corner.ro_mask = CPR3_RO_MASK;
-+
-+ for (j = 0; j < thread->vreg_count; j++) {
-+ vreg = &thread->vreg[j];
-+
-+ if (ctrl->cpr_enabled && ctrl->use_hw_closed_loop)
-+ cpr3_update_vreg_closed_loop_volt(vreg,
-+ vdd_volt, reg_last_measurement);
-+
-+ if (!vreg->vreg_enabled
-+ || vreg->current_corner
-+ == CPR3_REGULATOR_CORNER_INVALID) {
-+ /* Cannot participate in aggregation. */
-+ vreg->aggregated = false;
-+ continue;
-+ } else {
-+ vreg->aggregated = true;
-+ thread_valid = true;
-+ }
-+
-+ cpr3_regulator_aggregate_corners(&thread->aggr_corner,
-+ &vreg->corner[vreg->current_corner],
-+ true, ctrl->step_volt);
-+ }
-+
-+ valid |= thread_valid;
-+
-+ if (thread_valid)
-+ cpr3_regulator_aggregate_corners(&aggr_corner,
-+ &thread->aggr_corner,
-+ false, ctrl->step_volt);
-+ }
-+
-+ if (valid && ctrl->cpr_allowed_hw && ctrl->cpr_allowed_sw) {
-+ rc = cpr3_closed_loop_enable(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not enable CPR, rc=%d\n", rc);
-+ return rc;
-+ }
-+ } else {
-+ rc = cpr3_closed_loop_disable(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not disable CPR, rc=%d\n", rc);
-+ return rc;
-+ }
-+ }
-+
-+ /* No threads are enabled with a valid corner so exit. */
-+ if (!valid)
-+ return 0;
-+
-+ /*
-+ * When using CPR hardware closed-loop, the voltage may vary anywhere
-+ * between the floor and ceiling voltage without software notification.
-+ * Therefore, it is required that the floor to ceiling range for the
-+ * aggregated corner not intersect the APM threshold voltage. Adjust
-+ * the floor to ceiling range if this requirement is violated.
-+ *
-+ * The following algorithm is applied in the case that
-+ * floor < threshold <= ceiling:
-+ * if open_loop >= threshold - adj, then floor = threshold
-+ * else ceiling = threshold - step
-+ * where adj = an adjustment factor to ensure sufficient voltage margin
-+ * and step = VDD output step size
-+ *
-+ * The open-loop and last known voltages are also bounded by the new
-+ * floor or ceiling value as needed.
-+ */
-+ if (ctrl->use_hw_closed_loop
-+ && aggr_corner.ceiling_volt >= ctrl->apm_threshold_volt
-+ && aggr_corner.floor_volt < ctrl->apm_threshold_volt) {
-+
-+ if (aggr_corner.open_loop_volt
-+ >= ctrl->apm_threshold_volt - ctrl->apm_adj_volt)
-+ aggr_corner.floor_volt = ctrl->apm_threshold_volt;
-+ else
-+ aggr_corner.ceiling_volt
-+ = ctrl->apm_threshold_volt - ctrl->step_volt;
-+
-+ aggr_corner.last_volt
-+ = max(aggr_corner.last_volt, aggr_corner.floor_volt);
-+ aggr_corner.last_volt
-+ = min(aggr_corner.last_volt, aggr_corner.ceiling_volt);
-+ aggr_corner.open_loop_volt
-+ = max(aggr_corner.open_loop_volt, aggr_corner.floor_volt);
-+ aggr_corner.open_loop_volt
-+ = min(aggr_corner.open_loop_volt, aggr_corner.ceiling_volt);
-+ }
-+
-+ if (ctrl->use_hw_closed_loop
-+ && aggr_corner.ceiling_volt >= ctrl->mem_acc_threshold_volt
-+ && aggr_corner.floor_volt < ctrl->mem_acc_threshold_volt) {
-+ aggr_corner.floor_volt = ctrl->mem_acc_threshold_volt;
-+ aggr_corner.last_volt = max(aggr_corner.last_volt,
-+ aggr_corner.floor_volt);
-+ aggr_corner.open_loop_volt = max(aggr_corner.open_loop_volt,
-+ aggr_corner.floor_volt);
-+ }
-+
-+ if (ctrl->use_hw_closed_loop) {
-+ dynamic_floor_volt
-+ = cpr3_regulator_get_dynamic_floor_volt(ctrl,
-+ reg_last_measurement);
-+ if (aggr_corner.floor_volt < dynamic_floor_volt) {
-+ aggr_corner.floor_volt = dynamic_floor_volt;
-+ aggr_corner.last_volt = max(aggr_corner.last_volt,
-+ aggr_corner.floor_volt);
-+ aggr_corner.open_loop_volt
-+ = max(aggr_corner.open_loop_volt,
-+ aggr_corner.floor_volt);
-+ aggr_corner.ceiling_volt = max(aggr_corner.ceiling_volt,
-+ aggr_corner.floor_volt);
-+ }
-+ }
-+
-+ if (ctrl->cpr_enabled && ctrl->last_corner_was_closed_loop) {
-+ /*
-+ * Always program open-loop voltage for CPR4 controllers which
-+ * support hardware closed-loop. Storing the last closed loop
-+ * voltage in corner structure can still help with debugging.
-+ */
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3)
-+ new_volt = aggr_corner.last_volt;
-+ else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4
-+ && ctrl->supports_hw_closed_loop)
-+ new_volt = aggr_corner.open_loop_volt;
-+ else
-+ new_volt = min(aggr_corner.last_volt +
-+ cpr3_regulator_max_sdelta_diff(aggr_corner.sdelta,
-+ ctrl->step_volt),
-+ aggr_corner.ceiling_volt);
-+
-+ aggr_corner.last_volt = new_volt;
-+ } else {
-+ new_volt = aggr_corner.open_loop_volt;
-+ aggr_corner.last_volt = aggr_corner.open_loop_volt;
-+ }
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4
-+ && ctrl->supports_hw_closed_loop) {
-+ /*
-+ * Store last aggregated corner open-loop voltage in vdd_volt
-+ * which is used when programming current aggregated corner
-+ * required voltage.
-+ */
-+ vdd_volt = last_corner_volt;
-+ }
-+
-+ cpr3_debug(ctrl, "setting new voltage=%d uV\n", new_volt);
-+ rc = cpr3_regulator_scale_vdd_voltage(ctrl, new_volt,
-+ vdd_volt, &aggr_corner);
-+ if (rc) {
-+ cpr3_err(ctrl, "vdd voltage scaling failed, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ /* Only update registers if CPR is enabled. */
-+ if (ctrl->cpr_enabled) {
-+ if (ctrl->use_hw_closed_loop) {
-+ /* Hardware closed-loop */
-+
-+ /* Set ceiling and floor limits in hardware */
-+ rc = regulator_set_voltage(ctrl->vdd_limit_regulator,
-+ aggr_corner.floor_volt,
-+ aggr_corner.ceiling_volt);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not configure HW closed-loop voltage limits, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ } else {
-+ /* Software closed-loop */
-+
-+ /*
-+ * Disable UP or DOWN interrupts when at ceiling or
-+ * floor respectively.
-+ */
-+ if (new_volt == aggr_corner.floor_volt)
-+ aggr_corner.irq_en &= ~CPR3_IRQ_DOWN;
-+ if (new_volt == aggr_corner.ceiling_volt)
-+ aggr_corner.irq_en &= ~CPR3_IRQ_UP;
-+
-+ cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR,
-+ CPR3_IRQ_UP | CPR3_IRQ_DOWN);
-+ cpr3_write(ctrl, CPR3_REG_IRQ_EN, aggr_corner.irq_en);
-+ }
-+
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ cpr3_regulator_set_target_quot(&ctrl->thread[i]);
-+
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+
-+ if (vreg->vreg_enabled)
-+ vreg->last_closed_loop_corner
-+ = vreg->current_corner;
-+ }
-+ }
-+
-+ if (ctrl->proc_clock_throttle) {
-+ if (aggr_corner.ceiling_volt > aggr_corner.floor_volt
-+ && (ctrl->use_hw_closed_loop
-+ || new_volt < aggr_corner.ceiling_volt))
-+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE,
-+ ctrl->proc_clock_throttle);
-+ else
-+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE,
-+ CPR3_PD_THROTTLE_DISABLE);
-+ }
-+
-+ /*
-+ * Ensure that all CPR register writes complete before
-+ * re-enabling CPR loop operation.
-+ */
-+ wmb();
-+ } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4
-+ && ctrl->vdd_limit_regulator) {
-+ /* Set ceiling and floor limits in hardware */
-+ rc = regulator_set_voltage(ctrl->vdd_limit_regulator,
-+ aggr_corner.floor_volt,
-+ aggr_corner.ceiling_volt);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not configure HW closed-loop voltage limits, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ }
-+
-+ ctrl->aggr_corner = aggr_corner;
-+
-+ if (ctrl->allow_core_count_adj || ctrl->allow_temp_adj
-+ || ctrl->allow_boost) {
-+ rc = cpr3_controller_program_sdelta(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "failed to program sdelta, rc=%d\n", rc);
-+ return rc;
-+ }
-+ }
-+
-+ /*
-+ * Only enable the CPR controller if it is possible to set more than
-+ * one vdd-supply voltage.
-+ */
-+ if (aggr_corner.ceiling_volt > aggr_corner.floor_volt &&
-+ !aggr_corner.use_open_loop)
-+ cpr3_ctrl_loop_enable(ctrl);
-+
-+ ctrl->last_corner_was_closed_loop = ctrl->cpr_enabled;
-+ cpr3_debug(ctrl, "CPR configuration updated\n");
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_wait_for_idle() - wait for the CPR controller to no longer be
-+ * busy
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @max_wait_ns: Max wait time in nanoseconds
-+ *
-+ * Return: 0 on success or -ETIMEDOUT if the controller was still busy after
-+ * the maximum delay time
-+ */
-+static int cpr3_regulator_wait_for_idle(struct cpr3_controller *ctrl,
-+ s64 max_wait_ns)
-+{
-+ ktime_t start, end;
-+ s64 time_ns;
-+ u32 reg;
-+
-+ /*
-+ * Ensure that all previous CPR register writes have completed before
-+ * checking the status register.
-+ */
-+ mb();
-+
-+ start = ktime_get();
-+ do {
-+ end = ktime_get();
-+ time_ns = ktime_to_ns(ktime_sub(end, start));
-+ if (time_ns > max_wait_ns) {
-+ cpr3_err(ctrl, "CPR controller still busy after %lld us\n",
-+ div_s64(time_ns, 1000));
-+ return -ETIMEDOUT;
-+ }
-+ usleep_range(50, 100);
-+ reg = cpr3_read(ctrl, CPR3_REG_CPR_STATUS);
-+ } while (reg & CPR3_CPR_STATUS_BUSY_MASK);
-+
-+ return 0;
-+}
-+
-+/**
-+ * cmp_int() - int comparison function to be passed into the sort() function
-+ * which leads to ascending sorting
-+ * @a: First int value
-+ * @b: Second int value
-+ *
-+ * Return: >0 if a > b, 0 if a == b, <0 if a < b
-+ */
-+static int cmp_int(const void *a, const void *b)
-+{
-+ return *(int *)a - *(int *)b;
-+}
-+
-+/**
-+ * cpr3_regulator_measure_aging() - measure the quotient difference for the
-+ * specified CPR aging sensor
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @aging_sensor: Aging sensor to measure
-+ *
-+ * Note that vdd-supply must be configured to the aging reference voltage before
-+ * calling this function.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_measure_aging(struct cpr3_controller *ctrl,
-+ struct cpr3_aging_sensor_info *aging_sensor)
-+{
-+ u32 mask, reg, result, quot_min, quot_max, sel_min, sel_max;
-+ u32 quot_min_scaled, quot_max_scaled;
-+ u32 gcnt, gcnt_ref, gcnt0_restore, gcnt1_restore, irq_restore;
-+ u32 ro_mask_restore, cont_dly_restore, up_down_dly_restore = 0;
-+ int quot_delta, quot_delta_scaled, quot_delta_scaled_sum;
-+ int *quot_delta_results;
-+ int rc, rc2, i, aging_measurement_count, filtered_count;
-+ bool is_aging_measurement;
-+
-+ quot_delta_results = kcalloc(CPR3_AGING_MEASUREMENT_ITERATIONS,
-+ sizeof(*quot_delta_results), GFP_KERNEL);
-+ if (!quot_delta_results)
-+ return -ENOMEM;
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ rc = cpr3_ctrl_clear_cpr4_config(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n",
-+ rc);
-+ kfree(quot_delta_results);
-+ return rc;
-+ }
-+ }
-+
-+ cpr3_ctrl_loop_disable(ctrl);
-+
-+ /* Enable up, down, and mid CPR interrupts */
-+ irq_restore = cpr3_read(ctrl, CPR3_REG_IRQ_EN);
-+ cpr3_write(ctrl, CPR3_REG_IRQ_EN,
-+ CPR3_IRQ_UP | CPR3_IRQ_DOWN | CPR3_IRQ_MID);
-+
-+ /* Ensure that the aging sensor is assigned to CPR thread 0 */
-+ cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(aging_sensor->sensor_id), 0);
-+
-+ /* Switch from HW to SW closed-loop if necessary */
-+ if (ctrl->supports_hw_closed_loop) {
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK,
-+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE);
-+ } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP,
-+ CPR3_HW_CLOSED_LOOP_DISABLE);
-+ }
-+ }
-+
-+ /* Configure the GCNT for RO0 and RO1 that are used for aging */
-+ gcnt0_restore = cpr3_read(ctrl, CPR3_REG_GCNT(0));
-+ gcnt1_restore = cpr3_read(ctrl, CPR3_REG_GCNT(1));
-+ gcnt_ref = cpr3_regulator_get_gcnt(ctrl);
-+ gcnt = gcnt_ref * 3 / 2;
-+ cpr3_write(ctrl, CPR3_REG_GCNT(0), gcnt);
-+ cpr3_write(ctrl, CPR3_REG_GCNT(1), gcnt);
-+
-+ /* Unmask all RO's */
-+ ro_mask_restore = cpr3_read(ctrl, CPR3_REG_RO_MASK(0));
-+ cpr3_write(ctrl, CPR3_REG_RO_MASK(0), 0);
-+
-+ /*
-+ * Mask all sensors except for the one to measure and bypass all
-+ * sensors in collapsible domains.
-+ */
-+ for (i = 0; i <= ctrl->sensor_count / 32; i++) {
-+ mask = GENMASK(min(31, ctrl->sensor_count - i * 32), 0);
-+ if (aging_sensor->sensor_id / 32 >= i
-+ && aging_sensor->sensor_id / 32 < (i + 1))
-+ mask &= ~BIT(aging_sensor->sensor_id % 32);
-+ cpr3_write(ctrl, CPR3_REG_SENSOR_MASK_WRITE_BANK(i), mask);
-+ cpr3_write(ctrl, CPR3_REG_SENSOR_BYPASS_WRITE_BANK(i),
-+ aging_sensor->bypass_mask[i]);
-+ }
-+
-+ /* Set CPR loop delays to 0 us */
-+ if (ctrl->supports_hw_closed_loop
-+ && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ cont_dly_restore = cpr3_read(ctrl, CPR3_REG_CPR_TIMER_MID_CONT);
-+ up_down_dly_restore = cpr3_read(ctrl,
-+ CPR3_REG_CPR_TIMER_UP_DN_CONT);
-+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, 0);
-+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT, 0);
-+ } else {
-+ cont_dly_restore = cpr3_read(ctrl,
-+ CPR3_REG_CPR_TIMER_AUTO_CONT);
-+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT, 0);
-+ }
-+
-+ /* Set count mode to all-at-once min with no repeat */
-+ cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL,
-+ CPR3_CPR_CTL_COUNT_MODE_MASK | CPR3_CPR_CTL_COUNT_REPEAT_MASK,
-+ CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_MIN
-+ << CPR3_CPR_CTL_COUNT_MODE_SHIFT);
-+
-+ cpr3_ctrl_loop_enable(ctrl);
-+
-+ rc = cpr3_regulator_wait_for_idle(ctrl,
-+ CPR3_AGING_MEASUREMENT_TIMEOUT_NS);
-+ if (rc)
-+ goto cleanup;
-+
-+ /* Set count mode to all-at-once aging */
-+ cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL, CPR3_CPR_CTL_COUNT_MODE_MASK,
-+ CPR3_CPR_CTL_COUNT_MODE_ALL_AT_ONCE_AGE
-+ << CPR3_CPR_CTL_COUNT_MODE_SHIFT);
-+
-+ aging_measurement_count = 0;
-+ for (i = 0; i < CPR3_AGING_MEASUREMENT_ITERATIONS; i++) {
-+ /* Send CONT_NACK */
-+ cpr3_write(ctrl, CPR3_REG_CONT_CMD, CPR3_CONT_CMD_NACK);
-+
-+ rc = cpr3_regulator_wait_for_idle(ctrl,
-+ CPR3_AGING_MEASUREMENT_TIMEOUT_NS);
-+ if (rc)
-+ goto cleanup;
-+
-+ /* Check for PAGE_IS_AGE flag in status register */
-+ reg = cpr3_read(ctrl, CPR3_REG_CPR_STATUS);
-+ is_aging_measurement
-+ = reg & CPR3_CPR_STATUS_AGING_MEASUREMENT_MASK;
-+
-+ /* Read CPR measurement results */
-+ result = cpr3_read(ctrl, CPR3_REG_RESULT1(0));
-+ quot_min = (result & CPR3_RESULT1_QUOT_MIN_MASK)
-+ >> CPR3_RESULT1_QUOT_MIN_SHIFT;
-+ quot_max = (result & CPR3_RESULT1_QUOT_MAX_MASK)
-+ >> CPR3_RESULT1_QUOT_MAX_SHIFT;
-+ sel_min = (result & CPR3_RESULT1_RO_MIN_MASK)
-+ >> CPR3_RESULT1_RO_MIN_SHIFT;
-+ sel_max = (result & CPR3_RESULT1_RO_MAX_MASK)
-+ >> CPR3_RESULT1_RO_MAX_SHIFT;
-+
-+ /*
-+ * Scale the quotients so that they are equivalent to the fused
-+ * values. This accounts for the difference in measurement
-+ * interval times.
-+ */
-+ quot_min_scaled = quot_min * (gcnt_ref + 1) / (gcnt + 1);
-+ quot_max_scaled = quot_max * (gcnt_ref + 1) / (gcnt + 1);
-+
-+ if (sel_max == 1) {
-+ quot_delta = quot_max - quot_min;
-+ quot_delta_scaled = quot_max_scaled - quot_min_scaled;
-+ } else {
-+ quot_delta = quot_min - quot_max;
-+ quot_delta_scaled = quot_min_scaled - quot_max_scaled;
-+ }
-+
-+ if (is_aging_measurement)
-+ quot_delta_results[aging_measurement_count++]
-+ = quot_delta_scaled;
-+
-+ cpr3_debug(ctrl, "aging results: page_is_age=%u, sel_min=%u, sel_max=%u, quot_min=%u, quot_max=%u, quot_delta=%d, quot_min_scaled=%u, quot_max_scaled=%u, quot_delta_scaled=%d\n",
-+ is_aging_measurement, sel_min, sel_max, quot_min,
-+ quot_max, quot_delta, quot_min_scaled, quot_max_scaled,
-+ quot_delta_scaled);
-+ }
-+
-+ filtered_count
-+ = aging_measurement_count - CPR3_AGING_MEASUREMENT_FILTER * 2;
-+ if (filtered_count > 0) {
-+ sort(quot_delta_results, aging_measurement_count,
-+ sizeof(*quot_delta_results), cmp_int, NULL);
-+
-+ quot_delta_scaled_sum = 0;
-+ for (i = 0; i < filtered_count; i++)
-+ quot_delta_scaled_sum
-+ += quot_delta_results[i
-+ + CPR3_AGING_MEASUREMENT_FILTER];
-+
-+ aging_sensor->measured_quot_diff
-+ = quot_delta_scaled_sum / filtered_count;
-+ cpr3_info(ctrl, "average quotient delta=%d (count=%d)\n",
-+ aging_sensor->measured_quot_diff,
-+ filtered_count);
-+ } else {
-+ cpr3_err(ctrl, "%d aging measurements completed after %d iterations\n",
-+ aging_measurement_count,
-+ CPR3_AGING_MEASUREMENT_ITERATIONS);
-+ rc = -EBUSY;
-+ }
-+
-+cleanup:
-+ kfree(quot_delta_results);
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ rc2 = cpr3_ctrl_clear_cpr4_config(ctrl);
-+ if (rc2) {
-+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n",
-+ rc2);
-+ rc = rc2;
-+ }
-+ }
-+
-+ cpr3_ctrl_loop_disable(ctrl);
-+
-+ cpr3_write(ctrl, CPR3_REG_IRQ_EN, irq_restore);
-+
-+ cpr3_write(ctrl, CPR3_REG_RO_MASK(0), ro_mask_restore);
-+
-+ cpr3_write(ctrl, CPR3_REG_GCNT(0), gcnt0_restore);
-+ cpr3_write(ctrl, CPR3_REG_GCNT(1), gcnt1_restore);
-+
-+ if (ctrl->supports_hw_closed_loop
-+ && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_MID_CONT, cont_dly_restore);
-+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_UP_DN_CONT,
-+ up_down_dly_restore);
-+ } else {
-+ cpr3_write(ctrl, CPR3_REG_CPR_TIMER_AUTO_CONT,
-+ cont_dly_restore);
-+ }
-+
-+ for (i = 0; i <= ctrl->sensor_count / 32; i++) {
-+ cpr3_write(ctrl, CPR3_REG_SENSOR_MASK_WRITE_BANK(i), 0);
-+ cpr3_write(ctrl, CPR3_REG_SENSOR_BYPASS_WRITE_BANK(i), 0);
-+ }
-+
-+ cpr3_masked_write(ctrl, CPR3_REG_CPR_CTL,
-+ CPR3_CPR_CTL_COUNT_MODE_MASK | CPR3_CPR_CTL_COUNT_REPEAT_MASK,
-+ (ctrl->count_mode << CPR3_CPR_CTL_COUNT_MODE_SHIFT)
-+ | (ctrl->count_repeat << CPR3_CPR_CTL_COUNT_REPEAT_SHIFT));
-+
-+ cpr3_write(ctrl, CPR3_REG_SENSOR_OWNER(aging_sensor->sensor_id),
-+ ctrl->sensor_owner[aging_sensor->sensor_id]);
-+
-+ cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR,
-+ CPR3_IRQ_UP | CPR3_IRQ_DOWN | CPR3_IRQ_MID);
-+
-+ if (ctrl->supports_hw_closed_loop) {
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK,
-+ ctrl->use_hw_closed_loop
-+ ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE
-+ : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE);
-+ } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP,
-+ ctrl->use_hw_closed_loop
-+ ? CPR3_HW_CLOSED_LOOP_ENABLE
-+ : CPR3_HW_CLOSED_LOOP_DISABLE);
-+ }
-+ }
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_regulator_readjust_volt_and_quot() - readjust the target quotients as
-+ * well as the floor, ceiling, and open-loop voltages for the
-+ * regulator by removing the old adjustment and adding the new one
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @old_adjust_volt: Old aging adjustment voltage in microvolts
-+ * @new_adjust_volt: New aging adjustment voltage in microvolts
-+ *
-+ * Also reset the cached closed loop voltage (last_volt) to equal the open-loop
-+ * voltage for each corner.
-+ *
-+ * Return: None
-+ */
-+static void cpr3_regulator_readjust_volt_and_quot(struct cpr3_regulator *vreg,
-+ int old_adjust_volt, int new_adjust_volt)
-+{
-+ unsigned long long temp;
-+ int i, j, old_volt, new_volt, rounded_volt;
-+
-+ if (!vreg->aging_allowed)
-+ return;
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ temp = (unsigned long long)old_adjust_volt
-+ * (unsigned long long)vreg->corner[i].aging_derate;
-+ do_div(temp, 1000);
-+ old_volt = temp;
-+
-+ temp = (unsigned long long)new_adjust_volt
-+ * (unsigned long long)vreg->corner[i].aging_derate;
-+ do_div(temp, 1000);
-+ new_volt = temp;
-+
-+ old_volt = min(vreg->aging_max_adjust_volt, old_volt);
-+ new_volt = min(vreg->aging_max_adjust_volt, new_volt);
-+
-+ for (j = 0; j < CPR3_RO_COUNT; j++) {
-+ if (vreg->corner[i].target_quot[j] != 0) {
-+ vreg->corner[i].target_quot[j]
-+ += cpr3_quot_adjustment(
-+ vreg->corner[i].ro_scale[j],
-+ new_volt)
-+ - cpr3_quot_adjustment(
-+ vreg->corner[i].ro_scale[j],
-+ old_volt);
-+ }
-+ }
-+
-+ rounded_volt = CPR3_ROUND(new_volt,
-+ vreg->thread->ctrl->step_volt);
-+
-+ if (!vreg->aging_allow_open_loop_adj)
-+ rounded_volt = 0;
-+
-+ vreg->corner[i].ceiling_volt
-+ = vreg->corner[i].unaged_ceiling_volt + rounded_volt;
-+ vreg->corner[i].ceiling_volt = min(vreg->corner[i].ceiling_volt,
-+ vreg->corner[i].abs_ceiling_volt);
-+ vreg->corner[i].floor_volt
-+ = vreg->corner[i].unaged_floor_volt + rounded_volt;
-+ vreg->corner[i].floor_volt = min(vreg->corner[i].floor_volt,
-+ vreg->corner[i].ceiling_volt);
-+ vreg->corner[i].open_loop_volt
-+ = vreg->corner[i].unaged_open_loop_volt + rounded_volt;
-+ vreg->corner[i].open_loop_volt
-+ = min(vreg->corner[i].open_loop_volt,
-+ vreg->corner[i].ceiling_volt);
-+
-+ vreg->corner[i].last_volt = vreg->corner[i].open_loop_volt;
-+
-+ cpr3_debug(vreg, "corner %d: applying %d uV closed-loop and %d uV open-loop voltage margin adjustment\n",
-+ i, new_volt, rounded_volt);
-+ }
-+}
-+
-+/**
-+ * cpr3_regulator_set_aging_ref_adjustment() - adjust target quotients for the
-+ * regulators managed by this CPR controller to account for aging
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @ref_adjust_volt: New aging reference adjustment voltage in microvolts to
-+ * apply to all regulators managed by this CPR controller
-+ *
-+ * The existing aging adjustment as defined by ctrl->aging_ref_adjust_volt is
-+ * first removed and then the adjustment is applied. Lastly, the value of
-+ * ctrl->aging_ref_adjust_volt is updated to ref_adjust_volt.
-+ */
-+static void cpr3_regulator_set_aging_ref_adjustment(
-+ struct cpr3_controller *ctrl, int ref_adjust_volt)
-+{
-+ struct cpr3_regulator *vreg;
-+ int i, j;
-+
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+ cpr3_regulator_readjust_volt_and_quot(vreg,
-+ ctrl->aging_ref_adjust_volt, ref_adjust_volt);
-+ }
-+ }
-+
-+ ctrl->aging_ref_adjust_volt = ref_adjust_volt;
-+}
-+
-+/**
-+ * cpr3_regulator_aging_adjust() - adjust the target quotients for regulators
-+ * based on the output of CPR aging sensors
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_aging_adjust(struct cpr3_controller *ctrl)
-+{
-+ struct cpr3_regulator *vreg;
-+ struct cpr3_corner restore_aging_corner;
-+ struct cpr3_corner *corner;
-+ int *restore_current_corner;
-+ bool *restore_vreg_enabled;
-+ int i, j, id, rc, rc2, vreg_count, aging_volt, max_aging_volt = 0;
-+ u32 reg;
-+
-+ if (!ctrl->aging_required || !ctrl->cpr_enabled
-+ || ctrl->aggr_corner.ceiling_volt == 0
-+ || ctrl->aggr_corner.ceiling_volt > ctrl->aging_ref_volt)
-+ return 0;
-+
-+ for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+ vreg_count++;
-+
-+ if (vreg->aging_allowed && vreg->vreg_enabled
-+ && vreg->current_corner > vreg->aging_corner)
-+ return 0;
-+ }
-+ }
-+
-+ /* Verify that none of the aging sensors are currently masked. */
-+ for (i = 0; i < ctrl->aging_sensor_count; i++) {
-+ id = ctrl->aging_sensor[i].sensor_id;
-+ reg = cpr3_read(ctrl, CPR3_REG_SENSOR_MASK_READ(id));
-+ if (reg & BIT(id % 32))
-+ return 0;
-+ }
-+
-+ /*
-+ * Verify that the aging possible register (if specified) has an
-+ * acceptable value.
-+ */
-+ if (ctrl->aging_possible_reg) {
-+ reg = readl_relaxed(ctrl->aging_possible_reg);
-+ reg &= ctrl->aging_possible_mask;
-+ if (reg != ctrl->aging_possible_val)
-+ return 0;
-+ }
-+
-+ restore_current_corner = kcalloc(vreg_count,
-+ sizeof(*restore_current_corner), GFP_KERNEL);
-+ restore_vreg_enabled = kcalloc(vreg_count,
-+ sizeof(*restore_vreg_enabled), GFP_KERNEL);
-+ if (!restore_current_corner || !restore_vreg_enabled) {
-+ kfree(restore_current_corner);
-+ kfree(restore_vreg_enabled);
-+ return -ENOMEM;
-+ }
-+
-+ /* Force all regulators to the aging corner */
-+ for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++, vreg_count++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+
-+ restore_current_corner[vreg_count]
-+ = vreg->current_corner;
-+ restore_vreg_enabled[vreg_count]
-+ = vreg->vreg_enabled;
-+
-+ vreg->current_corner = vreg->aging_corner;
-+ vreg->vreg_enabled = true;
-+ }
-+ }
-+
-+ /* Force one of the regulators to require the aging reference voltage */
-+ vreg = &ctrl->thread[0].vreg[0];
-+ corner = &vreg->corner[vreg->current_corner];
-+ restore_aging_corner = *corner;
-+ corner->ceiling_volt = ctrl->aging_ref_volt;
-+ corner->floor_volt = ctrl->aging_ref_volt;
-+ corner->open_loop_volt = ctrl->aging_ref_volt;
-+ corner->last_volt = ctrl->aging_ref_volt;
-+
-+ /* Skip last_volt caching */
-+ ctrl->last_corner_was_closed_loop = false;
-+
-+ /* Set the vdd supply voltage to the aging reference voltage */
-+ rc = _cpr3_regulator_update_ctrl_state(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to force vdd-supply to the aging reference voltage=%d uV, rc=%d\n",
-+ ctrl->aging_ref_volt, rc);
-+ goto cleanup;
-+ }
-+
-+ if (ctrl->aging_vdd_mode) {
-+ rc = regulator_set_mode(ctrl->vdd_regulator,
-+ ctrl->aging_vdd_mode);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to configure vdd-supply for mode=%u, rc=%d\n",
-+ ctrl->aging_vdd_mode, rc);
-+ goto cleanup;
-+ }
-+ }
-+
-+ /* Perform aging measurement on all aging sensors */
-+ for (i = 0; i < ctrl->aging_sensor_count; i++) {
-+ for (j = 0; j < CPR3_AGING_RETRY_COUNT; j++) {
-+ rc = cpr3_regulator_measure_aging(ctrl,
-+ &ctrl->aging_sensor[i]);
-+ if (!rc)
-+ break;
-+ }
-+
-+ if (!rc) {
-+ aging_volt =
-+ cpr3_voltage_adjustment(
-+ ctrl->aging_sensor[i].ro_scale,
-+ ctrl->aging_sensor[i].measured_quot_diff
-+ - ctrl->aging_sensor[i].init_quot_diff);
-+ max_aging_volt = max(max_aging_volt, aging_volt);
-+ } else {
-+ cpr3_err(ctrl, "CPR aging measurement failed after %d tries, rc=%d\n",
-+ j, rc);
-+ ctrl->aging_failed = true;
-+ ctrl->aging_required = false;
-+ goto cleanup;
-+ }
-+ }
-+
-+cleanup:
-+ vreg = &ctrl->thread[0].vreg[0];
-+ vreg->corner[vreg->current_corner] = restore_aging_corner;
-+
-+ for (i = 0, vreg_count = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++, vreg_count++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+ vreg->current_corner
-+ = restore_current_corner[vreg_count];
-+ vreg->vreg_enabled = restore_vreg_enabled[vreg_count];
-+ }
-+ }
-+
-+ kfree(restore_current_corner);
-+ kfree(restore_vreg_enabled);
-+
-+ /* Adjust the CPR target quotients according to the aging measurement */
-+ if (!rc) {
-+ cpr3_regulator_set_aging_ref_adjustment(ctrl, max_aging_volt);
-+
-+ cpr3_info(ctrl, "aging measurement successful; aging reference adjustment voltage=%d uV\n",
-+ ctrl->aging_ref_adjust_volt);
-+ ctrl->aging_succeeded = true;
-+ ctrl->aging_required = false;
-+ }
-+
-+ if (ctrl->aging_complete_vdd_mode) {
-+ rc = regulator_set_mode(ctrl->vdd_regulator,
-+ ctrl->aging_complete_vdd_mode);
-+ if (rc)
-+ cpr3_err(ctrl, "unable to configure vdd-supply for mode=%u, rc=%d\n",
-+ ctrl->aging_complete_vdd_mode, rc);
-+ }
-+
-+ /* Skip last_volt caching */
-+ ctrl->last_corner_was_closed_loop = false;
-+
-+ /*
-+ * Restore vdd-supply to the voltage before the aging measurement and
-+ * restore the CPR3 controller hardware state.
-+ */
-+ rc2 = _cpr3_regulator_update_ctrl_state(ctrl);
-+
-+ /* Stop last_volt caching on for the next request */
-+ ctrl->last_corner_was_closed_loop = false;
-+
-+ return rc ? rc : rc2;
-+}
-+
-+/**
-+ * cpr3_regulator_update_ctrl_state() - update the state of the CPR controller
-+ * to reflect the corners used by all CPR3 regulators as well as
-+ * the CPR operating mode and perform aging adjustments if needed
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Note, CPR3 controller lock must be held by the caller.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_update_ctrl_state(struct cpr3_controller *ctrl)
-+{
-+ int rc;
-+
-+ rc = _cpr3_regulator_update_ctrl_state(ctrl);
-+ if (rc)
-+ return rc;
-+
-+ return cpr3_regulator_aging_adjust(ctrl);
-+}
-+
-+/**
-+ * cpr3_regulator_set_voltage() - set the voltage corner for the CPR3 regulator
-+ * associated with the regulator device
-+ * @rdev: Regulator device pointer for the cpr3-regulator
-+ * @corner: New voltage corner to set (offset by CPR3_CORNER_OFFSET)
-+ * @corner_max: Maximum voltage corner allowed (offset by
-+ * CPR3_CORNER_OFFSET)
-+ * @selector: Pointer which is filled with the selector value for the
-+ * corner
-+ *
-+ * This function is passed as a callback function into the regulator ops that
-+ * are registered for each cpr3-regulator device. The VDD voltage will not be
-+ * physically configured until both this function and cpr3_regulator_enable()
-+ * are called.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_set_voltage(struct regulator_dev *rdev,
-+ int corner, int corner_max, unsigned *selector)
-+{
-+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev);
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ int rc = 0;
-+ int last_corner;
-+
-+ corner -= CPR3_CORNER_OFFSET;
-+ corner_max -= CPR3_CORNER_OFFSET;
-+ *selector = corner;
-+
-+ mutex_lock(&ctrl->lock);
-+
-+ if (!vreg->vreg_enabled) {
-+ vreg->current_corner = corner;
-+ cpr3_debug(vreg, "stored corner=%d\n", corner);
-+ goto done;
-+ } else if (vreg->current_corner == corner) {
-+ goto done;
-+ }
-+
-+ last_corner = vreg->current_corner;
-+ vreg->current_corner = corner;
-+
-+ if (vreg->cpr4_regulator_data != NULL)
-+ if (vreg->cpr4_regulator_data->mem_acc_funcs != NULL)
-+ vreg->cpr4_regulator_data->mem_acc_funcs->set_mem_acc(rdev);
-+
-+ rc = cpr3_regulator_update_ctrl_state(ctrl);
-+ if (rc) {
-+ cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc);
-+ vreg->current_corner = last_corner;
-+ }
-+
-+ if (vreg->cpr4_regulator_data != NULL)
-+ if (vreg->cpr4_regulator_data->mem_acc_funcs != NULL)
-+ vreg->cpr4_regulator_data->mem_acc_funcs->clear_mem_acc(rdev);
-+
-+ cpr3_debug(vreg, "set corner=%d\n", corner);
-+done:
-+ mutex_unlock(&ctrl->lock);
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_handle_temp_open_loop_adjustment() - voltage based cold temperature
-+ *
-+ * @rdev: Regulator device pointer for the cpr3-regulator
-+ * @is_cold: Flag to denote enter/exit cold condition
-+ *
-+ * This function is adjusts voltage margin based on cold condition
-+ *
-+ * Return: 0 = success
-+ */
-+
-+int cpr3_handle_temp_open_loop_adjustment(struct cpr3_controller *ctrl,
-+ bool is_cold)
-+{
-+ int i ,j, k, rc;
-+ struct cpr3_regulator *vreg;
-+
-+ mutex_lock(&ctrl->lock);
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+ for (k = 0; k < vreg->corner_count; k++) {
-+ vreg->corner[k].open_loop_volt = is_cold ?
-+ vreg->corner[k].cold_temp_open_loop_volt :
-+ vreg->corner[k].normal_temp_open_loop_volt;
-+ }
-+ }
-+ }
-+ rc = cpr3_regulator_update_ctrl_state(ctrl);
-+ mutex_unlock(&ctrl->lock);
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_regulator_get_voltage() - get the voltage corner for the CPR3 regulator
-+ * associated with the regulator device
-+ * @rdev: Regulator device pointer for the cpr3-regulator
-+ *
-+ * This function is passed as a callback function into the regulator ops that
-+ * are registered for each cpr3-regulator device.
-+ *
-+ * Return: voltage corner value offset by CPR3_CORNER_OFFSET
-+ */
-+static int cpr3_regulator_get_voltage(struct regulator_dev *rdev)
-+{
-+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev);
-+
-+ if (vreg->current_corner == CPR3_REGULATOR_CORNER_INVALID)
-+ return CPR3_CORNER_OFFSET;
-+ else
-+ return vreg->current_corner + CPR3_CORNER_OFFSET;
-+}
-+
-+/**
-+ * cpr3_regulator_list_voltage() - return the voltage corner mapped to the
-+ * specified selector
-+ * @rdev: Regulator device pointer for the cpr3-regulator
-+ * @selector: Regulator selector
-+ *
-+ * This function is passed as a callback function into the regulator ops that
-+ * are registered for each cpr3-regulator device.
-+ *
-+ * Return: voltage corner value offset by CPR3_CORNER_OFFSET
-+ */
-+static int cpr3_regulator_list_voltage(struct regulator_dev *rdev,
-+ unsigned selector)
-+{
-+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev);
-+
-+ if (selector < vreg->corner_count)
-+ return selector + CPR3_CORNER_OFFSET;
-+ else
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_is_enabled() - return the enable state of the CPR3 regulator
-+ * @rdev: Regulator device pointer for the cpr3-regulator
-+ *
-+ * This function is passed as a callback function into the regulator ops that
-+ * are registered for each cpr3-regulator device.
-+ *
-+ * Return: true if regulator is enabled, false if regulator is disabled
-+ */
-+static int cpr3_regulator_is_enabled(struct regulator_dev *rdev)
-+{
-+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev);
-+
-+ return vreg->vreg_enabled;
-+}
-+
-+/**
-+ * cpr3_regulator_enable() - enable the CPR3 regulator
-+ * @rdev: Regulator device pointer for the cpr3-regulator
-+ *
-+ * This function is passed as a callback function into the regulator ops that
-+ * are registered for each cpr3-regulator device.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_enable(struct regulator_dev *rdev)
-+{
-+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev);
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ int rc = 0;
-+
-+ if (vreg->vreg_enabled == true)
-+ return 0;
-+
-+ mutex_lock(&ctrl->lock);
-+
-+ if (ctrl->system_regulator) {
-+ rc = regulator_enable(ctrl->system_regulator);
-+ if (rc) {
-+ cpr3_err(ctrl, "regulator_enable(system) failed, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+ rc = regulator_enable(ctrl->vdd_regulator);
-+ if (rc) {
-+ cpr3_err(vreg, "regulator_enable(vdd) failed, rc=%d\n", rc);
-+ goto done;
-+ }
-+
-+ vreg->vreg_enabled = true;
-+ rc = cpr3_regulator_update_ctrl_state(ctrl);
-+ if (rc) {
-+ cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc);
-+ regulator_disable(ctrl->vdd_regulator);
-+ vreg->vreg_enabled = false;
-+ goto done;
-+ }
-+
-+ cpr3_debug(vreg, "Enabled\n");
-+done:
-+ mutex_unlock(&ctrl->lock);
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_regulator_disable() - disable the CPR3 regulator
-+ * @rdev: Regulator device pointer for the cpr3-regulator
-+ *
-+ * This function is passed as a callback function into the regulator ops that
-+ * are registered for each cpr3-regulator device.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_disable(struct regulator_dev *rdev)
-+{
-+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev);
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ int rc, rc2;
-+
-+ if (vreg->vreg_enabled == false)
-+ return 0;
-+
-+ mutex_lock(&ctrl->lock);
-+ rc = regulator_disable(ctrl->vdd_regulator);
-+ if (rc) {
-+ cpr3_err(vreg, "regulator_disable(vdd) failed, rc=%d\n", rc);
-+ goto done;
-+ }
-+
-+ vreg->vreg_enabled = false;
-+ rc = cpr3_regulator_update_ctrl_state(ctrl);
-+ if (rc) {
-+ cpr3_err(vreg, "could not update CPR state, rc=%d\n", rc);
-+ rc2 = regulator_enable(ctrl->vdd_regulator);
-+ vreg->vreg_enabled = true;
-+ goto done;
-+ }
-+
-+ if (ctrl->system_regulator) {
-+ rc = regulator_disable(ctrl->system_regulator);
-+ if (rc) {
-+ cpr3_err(ctrl, "regulator_disable(system) failed, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+ cpr3_debug(vreg, "Disabled\n");
-+done:
-+ mutex_unlock(&ctrl->lock);
-+
-+ return rc;
-+}
-+
-+static struct regulator_ops cpr3_regulator_ops = {
-+ .enable = cpr3_regulator_enable,
-+ .disable = cpr3_regulator_disable,
-+ .is_enabled = cpr3_regulator_is_enabled,
-+ .set_voltage = cpr3_regulator_set_voltage,
-+ .get_voltage = cpr3_regulator_get_voltage,
-+ .list_voltage = cpr3_regulator_list_voltage,
-+};
-+
-+/**
-+ * cpr3_print_result() - print CPR measurement results to the kernel log for
-+ * debugging purposes
-+ * @thread: Pointer to the CPR3 thread
-+ *
-+ * Return: None
-+ */
-+static void cpr3_print_result(struct cpr3_thread *thread)
-+{
-+ struct cpr3_controller *ctrl = thread->ctrl;
-+ u32 result[3], busy, step_dn, step_up, error_steps, error, negative;
-+ u32 quot_min, quot_max, ro_min, ro_max, step_quot_min, step_quot_max;
-+ u32 sensor_min, sensor_max;
-+ char *sign;
-+
-+ result[0] = cpr3_read(ctrl, CPR3_REG_RESULT0(thread->thread_id));
-+ result[1] = cpr3_read(ctrl, CPR3_REG_RESULT1(thread->thread_id));
-+ result[2] = cpr3_read(ctrl, CPR3_REG_RESULT2(thread->thread_id));
-+
-+ busy = !!(result[0] & CPR3_RESULT0_BUSY_MASK);
-+ step_dn = !!(result[0] & CPR3_RESULT0_STEP_DN_MASK);
-+ step_up = !!(result[0] & CPR3_RESULT0_STEP_UP_MASK);
-+ error_steps = (result[0] & CPR3_RESULT0_ERROR_STEPS_MASK)
-+ >> CPR3_RESULT0_ERROR_STEPS_SHIFT;
-+ error = (result[0] & CPR3_RESULT0_ERROR_MASK)
-+ >> CPR3_RESULT0_ERROR_SHIFT;
-+ negative = !!(result[0] & CPR3_RESULT0_NEGATIVE_MASK);
-+
-+ quot_min = (result[1] & CPR3_RESULT1_QUOT_MIN_MASK)
-+ >> CPR3_RESULT1_QUOT_MIN_SHIFT;
-+ quot_max = (result[1] & CPR3_RESULT1_QUOT_MAX_MASK)
-+ >> CPR3_RESULT1_QUOT_MAX_SHIFT;
-+ ro_min = (result[1] & CPR3_RESULT1_RO_MIN_MASK)
-+ >> CPR3_RESULT1_RO_MIN_SHIFT;
-+ ro_max = (result[1] & CPR3_RESULT1_RO_MAX_MASK)
-+ >> CPR3_RESULT1_RO_MAX_SHIFT;
-+
-+ step_quot_min = (result[2] & CPR3_RESULT2_STEP_QUOT_MIN_MASK)
-+ >> CPR3_RESULT2_STEP_QUOT_MIN_SHIFT;
-+ step_quot_max = (result[2] & CPR3_RESULT2_STEP_QUOT_MAX_MASK)
-+ >> CPR3_RESULT2_STEP_QUOT_MAX_SHIFT;
-+ sensor_min = (result[2] & CPR3_RESULT2_SENSOR_MIN_MASK)
-+ >> CPR3_RESULT2_SENSOR_MIN_SHIFT;
-+ sensor_max = (result[2] & CPR3_RESULT2_SENSOR_MAX_MASK)
-+ >> CPR3_RESULT2_SENSOR_MAX_SHIFT;
-+
-+ sign = negative ? "-" : "";
-+ cpr3_debug(ctrl, "thread %u: busy=%u, step_dn=%u, step_up=%u, error_steps=%s%u, error=%s%u\n",
-+ thread->thread_id, busy, step_dn, step_up, sign, error_steps,
-+ sign, error);
-+ cpr3_debug(ctrl, "thread %u: quot_min=%u, quot_max=%u, ro_min=%u, ro_max=%u\n",
-+ thread->thread_id, quot_min, quot_max, ro_min, ro_max);
-+ cpr3_debug(ctrl, "thread %u: step_quot_min=%u, step_quot_max=%u, sensor_min=%u, sensor_max=%u\n",
-+ thread->thread_id, step_quot_min, step_quot_max, sensor_min,
-+ sensor_max);
-+}
-+
-+/**
-+ * cpr3_thread_busy() - returns if the specified CPR3 thread is busy taking
-+ * a measurement
-+ * @thread: Pointer to the CPR3 thread
-+ *
-+ * Return: CPR3 busy status
-+ */
-+static bool cpr3_thread_busy(struct cpr3_thread *thread)
-+{
-+ u32 result;
-+
-+ result = cpr3_read(thread->ctrl, CPR3_REG_RESULT0(thread->thread_id));
-+
-+ return !!(result & CPR3_RESULT0_BUSY_MASK);
-+}
-+
-+/**
-+ * cpr3_irq_handler() - CPR interrupt handler callback function used for
-+ * software closed-loop operation
-+ * @irq: CPR interrupt number
-+ * @data: Private data corresponding to the CPR3 controller
-+ * pointer
-+ *
-+ * This function increases or decreases the vdd supply voltage based upon the
-+ * CPR controller recommendation.
-+ *
-+ * Return: IRQ_HANDLED
-+ */
-+static irqreturn_t cpr3_irq_handler(int irq, void *data)
-+{
-+ struct cpr3_controller *ctrl = data;
-+ struct cpr3_corner *aggr = &ctrl->aggr_corner;
-+ u32 cont = CPR3_CONT_CMD_NACK;
-+ u32 reg_last_measurement = 0;
-+ struct cpr3_regulator *vreg;
-+ struct cpr3_corner *corner;
-+ unsigned long flags;
-+ int i, j, new_volt, last_volt, dynamic_floor_volt, rc;
-+ u32 irq_en, status, cpr_status, ctl;
-+ bool up, down;
-+
-+ mutex_lock(&ctrl->lock);
-+
-+ if (!ctrl->cpr_enabled) {
-+ cpr3_debug(ctrl, "CPR interrupt received but CPR is disabled\n");
-+ mutex_unlock(&ctrl->lock);
-+ return IRQ_HANDLED;
-+ } else if (ctrl->use_hw_closed_loop) {
-+ cpr3_debug(ctrl, "CPR interrupt received but CPR is using HW closed-loop\n");
-+ goto done;
-+ }
-+
-+ /*
-+ * CPR IRQ status checking and CPR controller disabling must happen
-+ * atomically and without invening delay in order to avoid an interrupt
-+ * storm caused by the handler racing with the CPR controller.
-+ */
-+ local_irq_save(flags);
-+ preempt_disable();
-+
-+ status = cpr3_read(ctrl, CPR3_REG_IRQ_STATUS);
-+ up = status & CPR3_IRQ_UP;
-+ down = status & CPR3_IRQ_DOWN;
-+
-+ if (!up && !down) {
-+ /*
-+ * Toggle the CPR controller off and then back on since the
-+ * hardware and software states are out of sync. This condition
-+ * occurs after an aging measurement completes as the CPR IRQ
-+ * physically triggers during the aging measurement but the
-+ * handler is stuck waiting on the mutex lock.
-+ */
-+ cpr3_ctrl_loop_disable(ctrl);
-+
-+ local_irq_restore(flags);
-+ preempt_enable();
-+
-+ /* Wait for the loop disable write to complete */
-+ mb();
-+
-+ /* Wait for BUSY=1 and LOOP_EN=0 in CPR controller registers. */
-+ for (i = 0; i < CPR3_REGISTER_WRITE_DELAY_US / 10; i++) {
-+ cpr_status = cpr3_read(ctrl, CPR3_REG_CPR_STATUS);
-+ ctl = cpr3_read(ctrl, CPR3_REG_CPR_CTL);
-+ if (cpr_status & CPR3_CPR_STATUS_BUSY_MASK
-+ && (ctl & CPR3_CPR_CTL_LOOP_EN_MASK)
-+ == CPR3_CPR_CTL_LOOP_DISABLE)
-+ break;
-+ udelay(10);
-+ }
-+ if (i == CPR3_REGISTER_WRITE_DELAY_US / 10)
-+ cpr3_debug(ctrl, "CPR controller not disabled after %d us\n",
-+ CPR3_REGISTER_WRITE_DELAY_US);
-+
-+ /* Clear interrupt status */
-+ cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR,
-+ CPR3_IRQ_UP | CPR3_IRQ_DOWN);
-+
-+ /* Wait for the interrupt clearing write to complete */
-+ mb();
-+
-+ /* Wait for IRQ_STATUS register to be cleared. */
-+ for (i = 0; i < CPR3_REGISTER_WRITE_DELAY_US / 10; i++) {
-+ status = cpr3_read(ctrl, CPR3_REG_IRQ_STATUS);
-+ if (!(status & (CPR3_IRQ_UP | CPR3_IRQ_DOWN)))
-+ break;
-+ udelay(10);
-+ }
-+ if (i == CPR3_REGISTER_WRITE_DELAY_US / 10)
-+ cpr3_debug(ctrl, "CPR interrupts not cleared after %d us\n",
-+ CPR3_REGISTER_WRITE_DELAY_US);
-+
-+ cpr3_ctrl_loop_enable(ctrl);
-+
-+ cpr3_debug(ctrl, "CPR interrupt received but no up or down status bit is set\n");
-+
-+ mutex_unlock(&ctrl->lock);
-+ return IRQ_HANDLED;
-+ } else if (up && down) {
-+ cpr3_debug(ctrl, "both up and down status bits set\n");
-+ /* The up flag takes precedence over the down flag. */
-+ down = false;
-+ }
-+
-+ if (ctrl->supports_hw_closed_loop)
-+ reg_last_measurement
-+ = cpr3_read(ctrl, CPR3_REG_LAST_MEASUREMENT);
-+ dynamic_floor_volt = cpr3_regulator_get_dynamic_floor_volt(ctrl,
-+ reg_last_measurement);
-+
-+ local_irq_restore(flags);
-+ preempt_enable();
-+
-+ irq_en = aggr->irq_en;
-+ last_volt = aggr->last_volt;
-+
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ if (cpr3_thread_busy(&ctrl->thread[i])) {
-+ cpr3_debug(ctrl, "CPR thread %u busy when it should be waiting for SW cont\n",
-+ ctrl->thread[i].thread_id);
-+ goto done;
-+ }
-+ }
-+
-+ new_volt = up ? last_volt + ctrl->step_volt
-+ : last_volt - ctrl->step_volt;
-+
-+ /* Re-enable UP/DOWN interrupt when its opposite is received. */
-+ irq_en |= up ? CPR3_IRQ_DOWN : CPR3_IRQ_UP;
-+
-+ if (new_volt > aggr->ceiling_volt) {
-+ new_volt = aggr->ceiling_volt;
-+ irq_en &= ~CPR3_IRQ_UP;
-+ cpr3_debug(ctrl, "limiting to ceiling=%d uV\n",
-+ aggr->ceiling_volt);
-+ } else if (new_volt < aggr->floor_volt) {
-+ new_volt = aggr->floor_volt;
-+ irq_en &= ~CPR3_IRQ_DOWN;
-+ cpr3_debug(ctrl, "limiting to floor=%d uV\n", aggr->floor_volt);
-+ }
-+
-+ if (down && new_volt < dynamic_floor_volt) {
-+ /*
-+ * The vdd-supply voltage should not be decreased below the
-+ * dynamic floor voltage. However, it is not necessary (and
-+ * counter productive) to force the voltage up to this level
-+ * if it happened to be below it since the closed-loop voltage
-+ * must have gotten there in a safe manner while the power
-+ * domains for the CPR3 regulator imposing the dynamic floor
-+ * were not bypassed.
-+ */
-+ new_volt = last_volt;
-+ irq_en &= ~CPR3_IRQ_DOWN;
-+ cpr3_debug(ctrl, "limiting to dynamic floor=%d uV\n",
-+ dynamic_floor_volt);
-+ }
-+
-+ for (i = 0; i < ctrl->thread_count; i++)
-+ cpr3_print_result(&ctrl->thread[i]);
-+
-+ cpr3_debug(ctrl, "%s: new_volt=%d uV, last_volt=%d uV\n",
-+ up ? "UP" : "DN", new_volt, last_volt);
-+
-+ if (ctrl->proc_clock_throttle && last_volt == aggr->ceiling_volt
-+ && new_volt < last_volt)
-+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE,
-+ ctrl->proc_clock_throttle);
-+
-+ if (new_volt != last_volt) {
-+ rc = cpr3_regulator_scale_vdd_voltage(ctrl, new_volt,
-+ last_volt,
-+ aggr);
-+ if (rc) {
-+ cpr3_err(ctrl, "scale_vdd() failed to set vdd=%d uV, rc=%d\n",
-+ new_volt, rc);
-+ goto done;
-+ }
-+ cont = CPR3_CONT_CMD_ACK;
-+
-+ /*
-+ * Update the closed-loop voltage for all regulators managed
-+ * by this CPR controller.
-+ */
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+ cpr3_update_vreg_closed_loop_volt(vreg,
-+ new_volt, reg_last_measurement);
-+ }
-+ }
-+ }
-+
-+ if (ctrl->proc_clock_throttle && new_volt == aggr->ceiling_volt)
-+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE,
-+ CPR3_PD_THROTTLE_DISABLE);
-+
-+ corner = &ctrl->thread[0].vreg[0].corner[
-+ ctrl->thread[0].vreg[0].current_corner];
-+
-+ if (irq_en != aggr->irq_en) {
-+ aggr->irq_en = irq_en;
-+ cpr3_write(ctrl, CPR3_REG_IRQ_EN, irq_en);
-+ }
-+
-+ aggr->last_volt = new_volt;
-+
-+done:
-+ /* Clear interrupt status */
-+ cpr3_write(ctrl, CPR3_REG_IRQ_CLEAR, CPR3_IRQ_UP | CPR3_IRQ_DOWN);
-+
-+ /* ACK or NACK the CPR controller */
-+ cpr3_write(ctrl, CPR3_REG_CONT_CMD, cont);
-+
-+ mutex_unlock(&ctrl->lock);
-+ return IRQ_HANDLED;
-+}
-+
-+/**
-+ * cpr3_ceiling_irq_handler() - CPR ceiling reached interrupt handler callback
-+ * function used for hardware closed-loop operation
-+ * @irq: CPR ceiling interrupt number
-+ * @data: Private data corresponding to the CPR3 controller
-+ * pointer
-+ *
-+ * This function disables processor clock throttling and closed-loop operation
-+ * when the ceiling voltage is reached.
-+ *
-+ * Return: IRQ_HANDLED
-+ */
-+static irqreturn_t cpr3_ceiling_irq_handler(int irq, void *data)
-+{
-+ struct cpr3_controller *ctrl = data;
-+ int volt;
-+
-+ mutex_lock(&ctrl->lock);
-+
-+ if (!ctrl->cpr_enabled) {
-+ cpr3_debug(ctrl, "CPR ceiling interrupt received but CPR is disabled\n");
-+ goto done;
-+ } else if (!ctrl->use_hw_closed_loop) {
-+ cpr3_debug(ctrl, "CPR ceiling interrupt received but CPR is using SW closed-loop\n");
-+ goto done;
-+ }
-+
-+ volt = regulator_get_voltage(ctrl->vdd_regulator);
-+ if (volt < 0) {
-+ cpr3_err(ctrl, "could not get vdd voltage, rc=%d\n", volt);
-+ goto done;
-+ } else if (volt != ctrl->aggr_corner.ceiling_volt) {
-+ cpr3_debug(ctrl, "CPR ceiling interrupt received but vdd voltage: %d uV != ceiling voltage: %d uV\n",
-+ volt, ctrl->aggr_corner.ceiling_volt);
-+ goto done;
-+ }
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ /*
-+ * Since the ceiling voltage has been reached, disable processor
-+ * clock throttling as well as CPR closed-loop operation.
-+ */
-+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE,
-+ CPR3_PD_THROTTLE_DISABLE);
-+ cpr3_ctrl_loop_disable(ctrl);
-+ cpr3_debug(ctrl, "CPR closed-loop and throttling disabled\n");
-+ }
-+
-+done:
-+ mutex_unlock(&ctrl->lock);
-+ return IRQ_HANDLED;
-+}
-+
-+/**
-+ * cpr3_regulator_vreg_register() - register a regulator device for a CPR3
-+ * regulator
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * This function initializes all regulator framework related structures and then
-+ * calls regulator_register() for the CPR3 regulator.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_vreg_register(struct cpr3_regulator *vreg)
-+{
-+ struct regulator_config config = {};
-+ struct regulator_desc *rdesc;
-+ struct regulator_init_data *init_data;
-+ int rc;
-+
-+ init_data = of_get_regulator_init_data(vreg->thread->ctrl->dev,
-+ vreg->of_node, &vreg->rdesc);
-+ if (!init_data) {
-+ cpr3_err(vreg, "regulator init data is missing\n");
-+ return -EINVAL;
-+ }
-+
-+ init_data->constraints.input_uV = init_data->constraints.max_uV;
-+ rdesc = &vreg->rdesc;
-+ init_data->constraints.valid_ops_mask |=
-+ REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS;
-+ rdesc->ops = &cpr3_regulator_ops;
-+
-+ rdesc->n_voltages = vreg->corner_count;
-+ rdesc->name = init_data->constraints.name;
-+ rdesc->owner = THIS_MODULE;
-+ rdesc->type = REGULATOR_VOLTAGE;
-+
-+ config.dev = vreg->thread->ctrl->dev;
-+ config.driver_data = vreg;
-+ config.init_data = init_data;
-+ config.of_node = vreg->of_node;
-+
-+ vreg->rdev = regulator_register(vreg->thread->ctrl->dev, rdesc, &config);
-+ if (IS_ERR(vreg->rdev)) {
-+ rc = PTR_ERR(vreg->rdev);
-+ cpr3_err(vreg, "regulator_register failed, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ return 0;
-+}
-+
-+static int debugfs_int_set(void *data, u64 val)
-+{
-+ *(int *)data = val;
-+ return 0;
-+}
-+
-+static int debugfs_int_get(void *data, u64 *val)
-+{
-+ *val = *(int *)data;
-+ return 0;
-+}
-+DEFINE_SIMPLE_ATTRIBUTE(fops_int, debugfs_int_get, debugfs_int_set, "%lld\n");
-+DEFINE_SIMPLE_ATTRIBUTE(fops_int_ro, debugfs_int_get, NULL, "%lld\n");
-+DEFINE_SIMPLE_ATTRIBUTE(fops_int_wo, NULL, debugfs_int_set, "%lld\n");
-+
-+/**
-+ * debugfs_create_int - create a debugfs file that is used to read and write a
-+ * signed int value
-+ * @name: Pointer to a string containing the name of the file to
-+ * create
-+ * @mode: The permissions that the file should have
-+ * @parent: Pointer to the parent dentry for this file. This should
-+ * be a directory dentry if set. If this parameter is
-+ * %NULL, then the file will be created in the root of the
-+ * debugfs filesystem.
-+ * @value: Pointer to the variable that the file should read to and
-+ * write from
-+ *
-+ * This function creates a file in debugfs with the given name that
-+ * contains the value of the variable @value. If the @mode variable is so
-+ * set, it can be read from, and written to.
-+ *
-+ * This function will return a pointer to a dentry if it succeeds. This
-+ * pointer must be passed to the debugfs_remove() function when the file is
-+ * to be removed. If an error occurs, %NULL will be returned.
-+ */
-+static struct dentry *debugfs_create_int(const char *name, umode_t mode,
-+ struct dentry *parent, int *value)
-+{
-+ /* if there are no write bits set, make read only */
-+ if (!(mode & S_IWUGO))
-+ return debugfs_create_file(name, mode, parent, value,
-+ &fops_int_ro);
-+ /* if there are no read bits set, make write only */
-+ if (!(mode & S_IRUGO))
-+ return debugfs_create_file(name, mode, parent, value,
-+ &fops_int_wo);
-+
-+ return debugfs_create_file(name, mode, parent, value, &fops_int);
-+}
-+
-+static int debugfs_bool_get(void *data, u64 *val)
-+{
-+ *val = *(bool *)data;
-+ return 0;
-+}
-+DEFINE_SIMPLE_ATTRIBUTE(fops_bool_ro, debugfs_bool_get, NULL, "%lld\n");
-+
-+/**
-+ * struct cpr3_debug_corner_info - data structure used by the
-+ * cpr3_debugfs_create_corner_int function
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @index: Pointer to the corner array index
-+ * @member_offset: Offset in bytes from the beginning of struct cpr3_corner
-+ * to the beginning of the value to be read from
-+ * @corner: Pointer to the CPR3 corner array
-+ */
-+struct cpr3_debug_corner_info {
-+ struct cpr3_regulator *vreg;
-+ int *index;
-+ size_t member_offset;
-+ struct cpr3_corner *corner;
-+};
-+
-+static int cpr3_debug_corner_int_get(void *data, u64 *val)
-+{
-+ struct cpr3_debug_corner_info *info = data;
-+ struct cpr3_controller *ctrl = info->vreg->thread->ctrl;
-+ int i;
-+
-+ mutex_lock(&ctrl->lock);
-+
-+ i = *info->index;
-+ if (i < 0)
-+ i = 0;
-+
-+ *val = *(int *)((char *)&info->vreg->corner[i] + info->member_offset);
-+
-+ mutex_unlock(&ctrl->lock);
-+
-+ return 0;
-+}
-+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_corner_int_fops, cpr3_debug_corner_int_get,
-+ NULL, "%lld\n");
-+
-+/**
-+ * cpr3_debugfs_create_corner_int - create a debugfs file that is used to read
-+ * a signed int value out of a CPR3 regulator's corner array
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @name: Pointer to a string containing the name of the file to
-+ * create
-+ * @mode: The permissions that the file should have
-+ * @parent: Pointer to the parent dentry for this file. This should
-+ * be a directory dentry if set. If this parameter is
-+ * %NULL, then the file will be created in the root of the
-+ * debugfs filesystem.
-+ * @index: Pointer to the corner array index
-+ * @member_offset: Offset in bytes from the beginning of struct cpr3_corner
-+ * to the beginning of the value to be read from
-+ *
-+ * This function creates a file in debugfs with the given name that
-+ * contains the value of the int type variable vreg->corner[index].member
-+ * where member_offset == offsetof(struct cpr3_corner, member).
-+ */
-+static struct dentry *cpr3_debugfs_create_corner_int(
-+ struct cpr3_regulator *vreg, const char *name, umode_t mode,
-+ struct dentry *parent, int *index, size_t member_offset)
-+{
-+ struct cpr3_debug_corner_info *info;
-+
-+ info = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*info), GFP_KERNEL);
-+ if (!info)
-+ return NULL;
-+
-+ info->vreg = vreg;
-+ info->index = index;
-+ info->member_offset = member_offset;
-+
-+ return debugfs_create_file(name, mode, parent, info,
-+ &cpr3_debug_corner_int_fops);
-+}
-+
-+static int cpr3_debug_quot_open(struct inode *inode, struct file *file)
-+{
-+ struct cpr3_debug_corner_info *info = inode->i_private;
-+ struct cpr3_thread *thread = info->vreg->thread;
-+ int size, i, pos;
-+ u32 *quot;
-+ char *buf;
-+
-+ /*
-+ * Max size:
-+ * - 10 digits + ' ' or '\n' = 11 bytes per number
-+ * - terminating '\0'
-+ */
-+ size = CPR3_RO_COUNT * 11;
-+ buf = kzalloc(size + 1, GFP_KERNEL);
-+ if (!buf)
-+ return -ENOMEM;
-+
-+ file->private_data = buf;
-+
-+ mutex_lock(&thread->ctrl->lock);
-+
-+ quot = info->corner[*info->index].target_quot;
-+
-+ for (i = 0, pos = 0; i < CPR3_RO_COUNT; i++)
-+ pos += scnprintf(buf + pos, size - pos, "%u%c",
-+ quot[i], i < CPR3_RO_COUNT - 1 ? ' ' : '\n');
-+
-+ mutex_unlock(&thread->ctrl->lock);
-+
-+ return nonseekable_open(inode, file);
-+}
-+
-+static ssize_t cpr3_debug_quot_read(struct file *file, char __user *buf,
-+ size_t len, loff_t *ppos)
-+{
-+ return simple_read_from_buffer(buf, len, ppos, file->private_data,
-+ strlen(file->private_data));
-+}
-+
-+static int cpr3_debug_quot_release(struct inode *inode, struct file *file)
-+{
-+ kfree(file->private_data);
-+
-+ return 0;
-+}
-+
-+static const struct file_operations cpr3_debug_quot_fops = {
-+ .owner = THIS_MODULE,
-+ .open = cpr3_debug_quot_open,
-+ .release = cpr3_debug_quot_release,
-+ .read = cpr3_debug_quot_read,
-+};
-+
-+/**
-+ * cpr3_regulator_debugfs_corner_add() - add debugfs files to expose
-+ * configuration data for the CPR corner
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @corner_dir: Pointer to the parent corner dentry for the new files
-+ * @index: Pointer to the corner array index
-+ *
-+ * Return: none
-+ */
-+static void cpr3_regulator_debugfs_corner_add(struct cpr3_regulator *vreg,
-+ struct dentry *corner_dir, int *index)
-+{
-+ struct cpr3_debug_corner_info *info;
-+ struct dentry *temp;
-+
-+ temp = cpr3_debugfs_create_corner_int(vreg, "floor_volt", S_IRUGO,
-+ corner_dir, index, offsetof(struct cpr3_corner, floor_volt));
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(vreg, "floor_volt debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = cpr3_debugfs_create_corner_int(vreg, "ceiling_volt", S_IRUGO,
-+ corner_dir, index, offsetof(struct cpr3_corner, ceiling_volt));
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(vreg, "ceiling_volt debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = cpr3_debugfs_create_corner_int(vreg, "open_loop_volt", S_IRUGO,
-+ corner_dir, index,
-+ offsetof(struct cpr3_corner, open_loop_volt));
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(vreg, "open_loop_volt debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = cpr3_debugfs_create_corner_int(vreg, "last_volt", S_IRUGO,
-+ corner_dir, index, offsetof(struct cpr3_corner, last_volt));
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(vreg, "last_volt debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ info = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*info), GFP_KERNEL);
-+ if (!info)
-+ return;
-+
-+ info->vreg = vreg;
-+ info->index = index;
-+ info->corner = vreg->corner;
-+
-+ temp = debugfs_create_file("target_quots", S_IRUGO, corner_dir,
-+ info, &cpr3_debug_quot_fops);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(vreg, "target_quots debugfs file creation failed\n");
-+ return;
-+ }
-+}
-+
-+/**
-+ * cpr3_debug_corner_index_set() - debugfs callback used to change the
-+ * value of the CPR3 regulator debug_corner index
-+ * @data: Pointer to private data which is equal to the CPR3
-+ * regulator pointer
-+ * @val: New value for debug_corner
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_debug_corner_index_set(void *data, u64 val)
-+{
-+ struct cpr3_regulator *vreg = data;
-+
-+ if (val < CPR3_CORNER_OFFSET || val > vreg->corner_count) {
-+ cpr3_err(vreg, "invalid corner index %llu; allowed values: %d-%d\n",
-+ val, CPR3_CORNER_OFFSET, vreg->corner_count);
-+ return -EINVAL;
-+ }
-+
-+ mutex_lock(&vreg->thread->ctrl->lock);
-+ vreg->debug_corner = val - CPR3_CORNER_OFFSET;
-+ mutex_unlock(&vreg->thread->ctrl->lock);
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_debug_corner_index_get() - debugfs callback used to retrieve
-+ * the value of the CPR3 regulator debug_corner index
-+ * @data: Pointer to private data which is equal to the CPR3
-+ * regulator pointer
-+ * @val: Output parameter written with the value of
-+ * debug_corner
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_debug_corner_index_get(void *data, u64 *val)
-+{
-+ struct cpr3_regulator *vreg = data;
-+
-+ *val = vreg->debug_corner + CPR3_CORNER_OFFSET;
-+
-+ return 0;
-+}
-+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_corner_index_fops,
-+ cpr3_debug_corner_index_get,
-+ cpr3_debug_corner_index_set,
-+ "%llu\n");
-+
-+/**
-+ * cpr3_debug_current_corner_index_get() - debugfs callback used to retrieve
-+ * the value of the CPR3 regulator current_corner index
-+ * @data: Pointer to private data which is equal to the CPR3
-+ * regulator pointer
-+ * @val: Output parameter written with the value of
-+ * current_corner
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_debug_current_corner_index_get(void *data, u64 *val)
-+{
-+ struct cpr3_regulator *vreg = data;
-+
-+ *val = vreg->current_corner + CPR3_CORNER_OFFSET;
-+
-+ return 0;
-+}
-+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_current_corner_index_fops,
-+ cpr3_debug_current_corner_index_get,
-+ NULL, "%llu\n");
-+
-+/**
-+ * cpr3_regulator_debugfs_vreg_add() - add debugfs files to expose configuration
-+ * data for the CPR3 regulator
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @thread_dir CPR3 thread debugfs directory handle
-+ *
-+ * Return: none
-+ */
-+static void cpr3_regulator_debugfs_vreg_add(struct cpr3_regulator *vreg,
-+ struct dentry *thread_dir)
-+{
-+ struct dentry *temp, *corner_dir, *vreg_dir;
-+
-+ vreg_dir = debugfs_create_dir(vreg->name, thread_dir);
-+ if (IS_ERR_OR_NULL(vreg_dir)) {
-+ cpr3_err(vreg, "%s debugfs directory creation failed\n",
-+ vreg->name);
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("speed_bin_fuse", S_IRUGO, vreg_dir,
-+ &vreg->speed_bin_fuse);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(vreg, "speed_bin_fuse debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("cpr_rev_fuse", S_IRUGO, vreg_dir,
-+ &vreg->cpr_rev_fuse);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(vreg, "cpr_rev_fuse debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("fuse_combo", S_IRUGO, vreg_dir,
-+ &vreg->fuse_combo);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(vreg, "fuse_combo debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("corner_count", S_IRUGO, vreg_dir,
-+ &vreg->corner_count);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(vreg, "corner_count debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ corner_dir = debugfs_create_dir("corner", vreg_dir);
-+ if (IS_ERR_OR_NULL(corner_dir)) {
-+ cpr3_err(vreg, "corner debugfs directory creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_file("index", S_IRUGO | S_IWUSR, corner_dir,
-+ vreg, &cpr3_debug_corner_index_fops);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(vreg, "index debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ cpr3_regulator_debugfs_corner_add(vreg, corner_dir,
-+ &vreg->debug_corner);
-+
-+ corner_dir = debugfs_create_dir("current_corner", vreg_dir);
-+ if (IS_ERR_OR_NULL(corner_dir)) {
-+ cpr3_err(vreg, "current_corner debugfs directory creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_file("index", S_IRUGO, corner_dir,
-+ vreg, &cpr3_debug_current_corner_index_fops);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(vreg, "index debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ cpr3_regulator_debugfs_corner_add(vreg, corner_dir,
-+ &vreg->current_corner);
-+}
-+
-+/**
-+ * cpr3_regulator_debugfs_thread_add() - add debugfs files to expose
-+ * configuration data for the CPR thread
-+ * @thread: Pointer to the CPR3 thread
-+ *
-+ * Return: none
-+ */
-+static void cpr3_regulator_debugfs_thread_add(struct cpr3_thread *thread)
-+{
-+ struct cpr3_controller *ctrl = thread->ctrl;
-+ struct dentry *aggr_dir, *temp, *thread_dir;
-+ struct cpr3_debug_corner_info *info;
-+ char buf[20];
-+ int *index;
-+ int i;
-+
-+ scnprintf(buf, sizeof(buf), "thread%u", thread->thread_id);
-+ thread_dir = debugfs_create_dir(buf, thread->ctrl->debugfs);
-+ if (IS_ERR_OR_NULL(thread_dir)) {
-+ cpr3_err(ctrl, "thread %u %s debugfs directory creation failed\n",
-+ thread->thread_id, buf);
-+ return;
-+ }
-+
-+ aggr_dir = debugfs_create_dir("max_aggregated_params", thread_dir);
-+ if (IS_ERR_OR_NULL(aggr_dir)) {
-+ cpr3_err(ctrl, "thread %u max_aggregated_params debugfs directory creation failed\n",
-+ thread->thread_id);
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("floor_volt", S_IRUGO, aggr_dir,
-+ &thread->aggr_corner.floor_volt);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "thread %u aggr floor_volt debugfs file creation failed\n",
-+ thread->thread_id);
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("ceiling_volt", S_IRUGO, aggr_dir,
-+ &thread->aggr_corner.ceiling_volt);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "thread %u aggr ceiling_volt debugfs file creation failed\n",
-+ thread->thread_id);
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("open_loop_volt", S_IRUGO, aggr_dir,
-+ &thread->aggr_corner.open_loop_volt);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "thread %u aggr open_loop_volt debugfs file creation failed\n",
-+ thread->thread_id);
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("last_volt", S_IRUGO, aggr_dir,
-+ &thread->aggr_corner.last_volt);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "thread %u aggr last_volt debugfs file creation failed\n",
-+ thread->thread_id);
-+ return;
-+ }
-+
-+ info = devm_kzalloc(thread->ctrl->dev, sizeof(*info), GFP_KERNEL);
-+ index = devm_kzalloc(thread->ctrl->dev, sizeof(*index), GFP_KERNEL);
-+ if (!info || !index)
-+ return;
-+ *index = 0;
-+ info->vreg = &thread->vreg[0];
-+ info->index = index;
-+ info->corner = &thread->aggr_corner;
-+
-+ temp = debugfs_create_file("target_quots", S_IRUGO, aggr_dir,
-+ info, &cpr3_debug_quot_fops);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "thread %u target_quots debugfs file creation failed\n",
-+ thread->thread_id);
-+ return;
-+ }
-+
-+ for (i = 0; i < thread->vreg_count; i++)
-+ cpr3_regulator_debugfs_vreg_add(&thread->vreg[i], thread_dir);
-+}
-+
-+/**
-+ * cpr3_debug_closed_loop_enable_set() - debugfs callback used to change the
-+ * value of the CPR controller cpr_allowed_sw flag which enables or
-+ * disables closed-loop operation
-+ * @data: Pointer to private data which is equal to the CPR
-+ * controller pointer
-+ * @val: New value for cpr_allowed_sw
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_debug_closed_loop_enable_set(void *data, u64 val)
-+{
-+ struct cpr3_controller *ctrl = data;
-+ bool enable = !!val;
-+ int rc;
-+
-+ mutex_lock(&ctrl->lock);
-+
-+ if (ctrl->cpr_allowed_sw == enable)
-+ goto done;
-+
-+ if (enable && !ctrl->cpr_allowed_hw) {
-+ cpr3_err(ctrl, "CPR closed-loop operation is not allowed\n");
-+ goto done;
-+ }
-+
-+ ctrl->cpr_allowed_sw = enable;
-+
-+ rc = cpr3_regulator_update_ctrl_state(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not change CPR enable state=%u, rc=%d\n",
-+ enable, rc);
-+ goto done;
-+ }
-+
-+ if (ctrl->proc_clock_throttle && !ctrl->cpr_enabled) {
-+ rc = cpr3_clock_enable(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "clock enable failed, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ ctrl->cpr_enabled = true;
-+
-+ cpr3_write(ctrl, CPR3_REG_PD_THROTTLE,
-+ CPR3_PD_THROTTLE_DISABLE);
-+
-+ cpr3_clock_disable(ctrl);
-+ ctrl->cpr_enabled = false;
-+ }
-+
-+ cpr3_debug(ctrl, "closed-loop=%s\n", enable ? "enabled" : "disabled");
-+done:
-+ mutex_unlock(&ctrl->lock);
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_debug_closed_loop_enable_get() - debugfs callback used to retrieve
-+ * the value of the CPR controller cpr_allowed_sw flag which
-+ * indicates if closed-loop operation is enabled
-+ * @data: Pointer to private data which is equal to the CPR
-+ * controller pointer
-+ * @val: Output parameter written with the value of
-+ * cpr_allowed_sw
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_debug_closed_loop_enable_get(void *data, u64 *val)
-+{
-+ struct cpr3_controller *ctrl = data;
-+
-+ *val = ctrl->cpr_allowed_sw;
-+
-+ return 0;
-+}
-+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_closed_loop_enable_fops,
-+ cpr3_debug_closed_loop_enable_get,
-+ cpr3_debug_closed_loop_enable_set,
-+ "%llu\n");
-+
-+/**
-+ * cpr3_debug_hw_closed_loop_enable_set() - debugfs callback used to change the
-+ * value of the CPR controller use_hw_closed_loop flag which
-+ * switches between software closed-loop and hardware closed-loop
-+ * operation for CPR3 and CPR4 controllers and between open-loop
-+ * and full hardware closed-loop operation for CPRh controllers.
-+ * @data: Pointer to private data which is equal to the CPR
-+ * controller pointer
-+ * @val: New value for use_hw_closed_loop
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_debug_hw_closed_loop_enable_set(void *data, u64 val)
-+{
-+ struct cpr3_controller *ctrl = data;
-+ bool use_hw_closed_loop = !!val;
-+ struct cpr3_regulator *vreg;
-+ bool cpr_enabled;
-+ int i, j, k, rc;
-+
-+ mutex_lock(&ctrl->lock);
-+
-+ if (ctrl->use_hw_closed_loop == use_hw_closed_loop)
-+ goto done;
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ rc = cpr3_ctrl_clear_cpr4_config(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+ cpr3_ctrl_loop_disable(ctrl);
-+
-+ ctrl->use_hw_closed_loop = use_hw_closed_loop;
-+
-+ cpr_enabled = ctrl->cpr_enabled;
-+
-+ /* Ensure that CPR clocks are enabled before writing to registers. */
-+ if (!cpr_enabled) {
-+ rc = cpr3_clock_enable(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "clock enable failed, rc=%d\n", rc);
-+ goto done;
-+ }
-+ ctrl->cpr_enabled = true;
-+ }
-+
-+ if (ctrl->use_hw_closed_loop)
-+ cpr3_write(ctrl, CPR3_REG_IRQ_EN, 0);
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ cpr3_masked_write(ctrl, CPR4_REG_MARGIN_ADJ_CTL,
-+ CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_EN_MASK,
-+ ctrl->use_hw_closed_loop
-+ ? CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_ENABLE
-+ : CPR4_MARGIN_ADJ_CTL_HW_CLOSED_LOOP_DISABLE);
-+ } else if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ cpr3_write(ctrl, CPR3_REG_HW_CLOSED_LOOP,
-+ ctrl->use_hw_closed_loop
-+ ? CPR3_HW_CLOSED_LOOP_ENABLE
-+ : CPR3_HW_CLOSED_LOOP_DISABLE);
-+ }
-+
-+ /* Turn off CPR clocks if they were off before this function call. */
-+ if (!cpr_enabled) {
-+ cpr3_clock_disable(ctrl);
-+ ctrl->cpr_enabled = false;
-+ }
-+
-+ if (ctrl->use_hw_closed_loop && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ rc = regulator_enable(ctrl->vdd_limit_regulator);
-+ if (rc) {
-+ cpr3_err(ctrl, "CPR limit regulator enable failed, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ } else if (!ctrl->use_hw_closed_loop
-+ && ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ rc = regulator_disable(ctrl->vdd_limit_regulator);
-+ if (rc) {
-+ cpr3_err(ctrl, "CPR limit regulator disable failed, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+ /*
-+ * Due to APM and mem-acc floor restriction constraints,
-+ * the closed-loop voltage may be different when using
-+ * software closed-loop vs hardware closed-loop. Therefore,
-+ * reset the cached closed-loop voltage for all corners to the
-+ * corresponding open-loop voltage when switching between
-+ * SW and HW closed-loop mode.
-+ */
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+ for (k = 0; k < vreg->corner_count; k++)
-+ vreg->corner[k].last_volt
-+ = vreg->corner[k].open_loop_volt;
-+ }
-+ }
-+
-+ /* Skip last_volt caching */
-+ ctrl->last_corner_was_closed_loop = false;
-+
-+ rc = cpr3_regulator_update_ctrl_state(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not change CPR HW closed-loop enable state=%u, rc=%d\n",
-+ use_hw_closed_loop, rc);
-+ goto done;
-+ }
-+
-+ cpr3_debug(ctrl, "CPR mode=%s\n",
-+ use_hw_closed_loop ?
-+ "HW closed-loop" : "SW closed-loop");
-+done:
-+ mutex_unlock(&ctrl->lock);
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_debug_hw_closed_loop_enable_get() - debugfs callback used to retrieve
-+ * the value of the CPR controller use_hw_closed_loop flag which
-+ * indicates if hardware closed-loop operation is being used in
-+ * place of software closed-loop operation
-+ * @data: Pointer to private data which is equal to the CPR
-+ * controller pointer
-+ * @val: Output parameter written with the value of
-+ * use_hw_closed_loop
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_debug_hw_closed_loop_enable_get(void *data, u64 *val)
-+{
-+ struct cpr3_controller *ctrl = data;
-+
-+ *val = ctrl->use_hw_closed_loop;
-+
-+ return 0;
-+}
-+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_hw_closed_loop_enable_fops,
-+ cpr3_debug_hw_closed_loop_enable_get,
-+ cpr3_debug_hw_closed_loop_enable_set,
-+ "%llu\n");
-+
-+/**
-+ * cpr3_debug_trigger_aging_measurement_set() - debugfs callback used to trigger
-+ * another CPR measurement
-+ * @data: Pointer to private data which is equal to the CPR
-+ * controller pointer
-+ * @val: Unused
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_debug_trigger_aging_measurement_set(void *data, u64 val)
-+{
-+ struct cpr3_controller *ctrl = data;
-+ int rc;
-+
-+ mutex_lock(&ctrl->lock);
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ rc = cpr3_ctrl_clear_cpr4_config(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+ cpr3_ctrl_loop_disable(ctrl);
-+
-+ cpr3_regulator_set_aging_ref_adjustment(ctrl, INT_MAX);
-+ ctrl->aging_required = true;
-+ ctrl->aging_succeeded = false;
-+ ctrl->aging_failed = false;
-+
-+ rc = cpr3_regulator_update_ctrl_state(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not update the CPR controller state, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+
-+done:
-+ mutex_unlock(&ctrl->lock);
-+ return 0;
-+}
-+DEFINE_SIMPLE_ATTRIBUTE(cpr3_debug_trigger_aging_measurement_fops,
-+ NULL,
-+ cpr3_debug_trigger_aging_measurement_set,
-+ "%llu\n");
-+
-+/**
-+ * cpr3_regulator_debugfs_ctrl_add() - add debugfs files to expose configuration
-+ * data for the CPR controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: none
-+ */
-+static void cpr3_regulator_debugfs_ctrl_add(struct cpr3_controller *ctrl)
-+{
-+ struct dentry *temp, *aggr_dir;
-+ int i;
-+
-+ /* Add cpr3-regulator base directory if it isn't present already. */
-+ if (cpr3_debugfs_base == NULL) {
-+ cpr3_debugfs_base = debugfs_create_dir("cpr3-regulator", NULL);
-+ if (IS_ERR_OR_NULL(cpr3_debugfs_base)) {
-+ cpr3_err(ctrl, "cpr3-regulator debugfs base directory creation failed\n");
-+ cpr3_debugfs_base = NULL;
-+ return;
-+ }
-+ }
-+
-+ ctrl->debugfs = debugfs_create_dir(ctrl->name, cpr3_debugfs_base);
-+ if (IS_ERR_OR_NULL(ctrl->debugfs)) {
-+ cpr3_err(ctrl, "cpr3-regulator controller debugfs directory creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_file("cpr_closed_loop_enable", S_IRUGO | S_IWUSR,
-+ ctrl->debugfs, ctrl,
-+ &cpr3_debug_closed_loop_enable_fops);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "cpr_closed_loop_enable debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ if (ctrl->supports_hw_closed_loop) {
-+ temp = debugfs_create_file("use_hw_closed_loop",
-+ S_IRUGO | S_IWUSR, ctrl->debugfs, ctrl,
-+ &cpr3_debug_hw_closed_loop_enable_fops);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "use_hw_closed_loop debugfs file creation failed\n");
-+ return;
-+ }
-+ }
-+
-+ temp = debugfs_create_int("thread_count", S_IRUGO, ctrl->debugfs,
-+ &ctrl->thread_count);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "thread_count debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ if (ctrl->apm) {
-+ temp = debugfs_create_int("apm_threshold_volt", S_IRUGO,
-+ ctrl->debugfs, &ctrl->apm_threshold_volt);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "apm_threshold_volt debugfs file creation failed\n");
-+ return;
-+ }
-+ }
-+
-+ if (ctrl->aging_required || ctrl->aging_succeeded
-+ || ctrl->aging_failed) {
-+ temp = debugfs_create_int("aging_adj_volt", S_IRUGO,
-+ ctrl->debugfs, &ctrl->aging_ref_adjust_volt);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "aging_adj_volt debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_file("aging_succeeded", S_IRUGO,
-+ ctrl->debugfs, &ctrl->aging_succeeded, &fops_bool_ro);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "aging_succeeded debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_file("aging_failed", S_IRUGO,
-+ ctrl->debugfs, &ctrl->aging_failed, &fops_bool_ro);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "aging_failed debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_file("aging_trigger", S_IWUSR,
-+ ctrl->debugfs, ctrl,
-+ &cpr3_debug_trigger_aging_measurement_fops);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "aging_trigger debugfs file creation failed\n");
-+ return;
-+ }
-+ }
-+
-+ aggr_dir = debugfs_create_dir("max_aggregated_voltages", ctrl->debugfs);
-+ if (IS_ERR_OR_NULL(aggr_dir)) {
-+ cpr3_err(ctrl, "max_aggregated_voltages debugfs directory creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("floor_volt", S_IRUGO, aggr_dir,
-+ &ctrl->aggr_corner.floor_volt);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "aggr floor_volt debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("ceiling_volt", S_IRUGO, aggr_dir,
-+ &ctrl->aggr_corner.ceiling_volt);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "aggr ceiling_volt debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("open_loop_volt", S_IRUGO, aggr_dir,
-+ &ctrl->aggr_corner.open_loop_volt);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "aggr open_loop_volt debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ temp = debugfs_create_int("last_volt", S_IRUGO, aggr_dir,
-+ &ctrl->aggr_corner.last_volt);
-+ if (IS_ERR_OR_NULL(temp)) {
-+ cpr3_err(ctrl, "aggr last_volt debugfs file creation failed\n");
-+ return;
-+ }
-+
-+ for (i = 0; i < ctrl->thread_count; i++)
-+ cpr3_regulator_debugfs_thread_add(&ctrl->thread[i]);
-+}
-+
-+/**
-+ * cpr3_regulator_debugfs_ctrl_remove() - remove debugfs files for the CPR
-+ * controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Note, this function must be called after the controller has been removed from
-+ * cpr3_controller_list and while the cpr3_controller_list_mutex lock is held.
-+ *
-+ * Return: none
-+ */
-+static void cpr3_regulator_debugfs_ctrl_remove(struct cpr3_controller *ctrl)
-+{
-+ if (list_empty(&cpr3_controller_list)) {
-+ debugfs_remove_recursive(cpr3_debugfs_base);
-+ cpr3_debugfs_base = NULL;
-+ } else {
-+ debugfs_remove_recursive(ctrl->debugfs);
-+ }
-+}
-+
-+/**
-+ * cpr3_regulator_init_ctrl_data() - performs initialization of CPR controller
-+ * elements
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_init_ctrl_data(struct cpr3_controller *ctrl)
-+{
-+ /* Read the initial vdd voltage from hardware. */
-+ ctrl->aggr_corner.last_volt
-+ = regulator_get_voltage(ctrl->vdd_regulator);
-+ if (ctrl->aggr_corner.last_volt < 0) {
-+ cpr3_err(ctrl, "regulator_get_voltage(vdd) failed, rc=%d\n",
-+ ctrl->aggr_corner.last_volt);
-+ return ctrl->aggr_corner.last_volt;
-+ }
-+ ctrl->aggr_corner.open_loop_volt = ctrl->aggr_corner.last_volt;
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_init_vreg_data() - performs initialization of common CPR3
-+ * regulator elements and validate aging configurations
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_init_vreg_data(struct cpr3_regulator *vreg)
-+{
-+ int i, j;
-+ bool init_aging;
-+
-+ vreg->current_corner = CPR3_REGULATOR_CORNER_INVALID;
-+ vreg->last_closed_loop_corner = CPR3_REGULATOR_CORNER_INVALID;
-+
-+ init_aging = vreg->aging_allowed && vreg->thread->ctrl->aging_required;
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ vreg->corner[i].last_volt = vreg->corner[i].open_loop_volt;
-+ vreg->corner[i].irq_en = CPR3_IRQ_UP | CPR3_IRQ_DOWN;
-+
-+ vreg->corner[i].ro_mask = 0;
-+ for (j = 0; j < CPR3_RO_COUNT; j++) {
-+ if (vreg->corner[i].target_quot[j] == 0)
-+ vreg->corner[i].ro_mask |= BIT(j);
-+ }
-+
-+ if (init_aging) {
-+ vreg->corner[i].unaged_floor_volt
-+ = vreg->corner[i].floor_volt;
-+ vreg->corner[i].unaged_ceiling_volt
-+ = vreg->corner[i].ceiling_volt;
-+ vreg->corner[i].unaged_open_loop_volt
-+ = vreg->corner[i].open_loop_volt;
-+ }
-+
-+ if (vreg->aging_allowed) {
-+ if (vreg->corner[i].unaged_floor_volt <= 0) {
-+ cpr3_err(vreg, "invalid unaged_floor_volt[%d] = %d\n",
-+ i, vreg->corner[i].unaged_floor_volt);
-+ return -EINVAL;
-+ }
-+ if (vreg->corner[i].unaged_ceiling_volt <= 0) {
-+ cpr3_err(vreg, "invalid unaged_ceiling_volt[%d] = %d\n",
-+ i, vreg->corner[i].unaged_ceiling_volt);
-+ return -EINVAL;
-+ }
-+ if (vreg->corner[i].unaged_open_loop_volt <= 0) {
-+ cpr3_err(vreg, "invalid unaged_open_loop_volt[%d] = %d\n",
-+ i, vreg->corner[i].unaged_open_loop_volt);
-+ return -EINVAL;
-+ }
-+ }
-+ }
-+
-+ if (vreg->aging_allowed && vreg->corner[vreg->aging_corner].ceiling_volt
-+ > vreg->thread->ctrl->aging_ref_volt) {
-+ cpr3_err(vreg, "aging corner %d ceiling voltage = %d > aging ref voltage = %d uV\n",
-+ vreg->aging_corner,
-+ vreg->corner[vreg->aging_corner].ceiling_volt,
-+ vreg->thread->ctrl->aging_ref_volt);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_suspend() - perform common required CPR3 power down steps
-+ * before the system enters suspend
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_regulator_suspend(struct cpr3_controller *ctrl)
-+{
-+ int rc;
-+
-+ mutex_lock(&ctrl->lock);
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ rc = cpr3_ctrl_clear_cpr4_config(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n",
-+ rc);
-+ mutex_unlock(&ctrl->lock);
-+ return rc;
-+ }
-+ }
-+
-+ cpr3_ctrl_loop_disable(ctrl);
-+
-+ rc = cpr3_closed_loop_disable(ctrl);
-+ if (rc)
-+ cpr3_err(ctrl, "could not disable CPR, rc=%d\n", rc);
-+
-+ ctrl->cpr_suspended = true;
-+
-+ mutex_unlock(&ctrl->lock);
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_resume() - perform common required CPR3 power up steps after
-+ * the system resumes from suspend
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_regulator_resume(struct cpr3_controller *ctrl)
-+{
-+ int rc;
-+
-+ mutex_lock(&ctrl->lock);
-+
-+ ctrl->cpr_suspended = false;
-+ rc = cpr3_regulator_update_ctrl_state(ctrl);
-+ if (rc)
-+ cpr3_err(ctrl, "could not enable CPR, rc=%d\n", rc);
-+
-+ mutex_unlock(&ctrl->lock);
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_regulator_validate_controller() - verify the data passed in via the
-+ * cpr3_controller data structure
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_regulator_validate_controller(struct cpr3_controller *ctrl)
-+{
-+ struct cpr3_thread *thread;
-+ struct cpr3_regulator *vreg;
-+ int i, j, allow_boost_vreg_count = 0;
-+
-+ if (!ctrl->vdd_regulator) {
-+ cpr3_err(ctrl, "vdd regulator missing\n");
-+ return -EINVAL;
-+ } else if (ctrl->sensor_count <= 0
-+ || ctrl->sensor_count > CPR3_MAX_SENSOR_COUNT) {
-+ cpr3_err(ctrl, "invalid CPR sensor count=%d\n",
-+ ctrl->sensor_count);
-+ return -EINVAL;
-+ } else if (!ctrl->sensor_owner) {
-+ cpr3_err(ctrl, "CPR sensor ownership table missing\n");
-+ return -EINVAL;
-+ }
-+
-+ if (ctrl->aging_required) {
-+ for (i = 0; i < ctrl->aging_sensor_count; i++) {
-+ if (ctrl->aging_sensor[i].sensor_id
-+ >= ctrl->sensor_count) {
-+ cpr3_err(ctrl, "aging_sensor[%d] id=%u is not in the value range 0-%d",
-+ i, ctrl->aging_sensor[i].sensor_id,
-+ ctrl->sensor_count - 1);
-+ return -EINVAL;
-+ }
-+ }
-+ }
-+
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ thread = &ctrl->thread[i];
-+ for (j = 0; j < thread->vreg_count; j++) {
-+ vreg = &thread->vreg[j];
-+ if (vreg->allow_boost)
-+ allow_boost_vreg_count++;
-+ }
-+ }
-+
-+ if (allow_boost_vreg_count > 1) {
-+ /*
-+ * Boost feature is not allowed to be used for more
-+ * than one CPR3 regulator of a CPR3 controller.
-+ */
-+ cpr3_err(ctrl, "Boost feature is enabled for more than one regulator\n");
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_panic_callback() - panic notification callback function. This function
-+ * is invoked when a kernel panic occurs.
-+ * @nfb: Notifier block pointer of CPR3 controller
-+ * @event: Value passed unmodified to notifier function
-+ * @data: Pointer passed unmodified to notifier function
-+ *
-+ * Return: NOTIFY_OK
-+ */
-+static int cpr3_panic_callback(struct notifier_block *nfb,
-+ unsigned long event, void *data)
-+{
-+ struct cpr3_controller *ctrl = container_of(nfb,
-+ struct cpr3_controller, panic_notifier);
-+ struct cpr3_panic_regs_info *regs_info = ctrl->panic_regs_info;
-+ struct cpr3_reg_info *reg;
-+ int i = 0;
-+
-+ for (i = 0; i < regs_info->reg_count; i++) {
-+ reg = &(regs_info->regs[i]);
-+ reg->value = readl_relaxed(reg->virt_addr);
-+ pr_err("%s[0x%08x] = 0x%08x\n", reg->name, reg->addr,
-+ reg->value);
-+ }
-+ /*
-+ * Barrier to ensure that the information has been updated in the
-+ * structure.
-+ */
-+ mb();
-+
-+ return NOTIFY_OK;
-+}
-+
-+/**
-+ * cpr3_regulator_register() - register the regulators for a CPR3 controller and
-+ * perform CPR hardware initialization
-+ * @pdev: Platform device pointer for the CPR3 controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_regulator_register(struct platform_device *pdev,
-+ struct cpr3_controller *ctrl)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct resource *res;
-+ int i, j, rc;
-+
-+ if (!dev->of_node) {
-+ dev_err(dev, "%s: Device tree node is missing\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ if (!ctrl || !ctrl->name) {
-+ dev_err(dev, "%s: CPR controller data is missing\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ rc = cpr3_regulator_validate_controller(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "controller validation failed, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ mutex_init(&ctrl->lock);
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpr_ctrl");
-+ if (!res || !res->start) {
-+ cpr3_err(ctrl, "CPR controller address is missing\n");
-+ return -ENXIO;
-+ }
-+ ctrl->cpr_ctrl_base = devm_ioremap(dev, res->start, resource_size(res));
-+
-+ if (ctrl->aging_possible_mask) {
-+ /*
-+ * Aging possible register address is required if an aging
-+ * possible mask has been specified.
-+ */
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-+ "aging_allowed");
-+ if (!res || !res->start) {
-+ cpr3_err(ctrl, "CPR aging allowed address is missing\n");
-+ return -ENXIO;
-+ }
-+ ctrl->aging_possible_reg = devm_ioremap(dev, res->start,
-+ resource_size(res));
-+ }
-+
-+ ctrl->irq = platform_get_irq_byname(pdev, "cpr");
-+ if (ctrl->irq < 0) {
-+ cpr3_err(ctrl, "missing CPR interrupt\n");
-+ return ctrl->irq;
-+ }
-+
-+ if (ctrl->supports_hw_closed_loop) {
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ ctrl->ceiling_irq = platform_get_irq_byname(pdev,
-+ "ceiling");
-+ if (ctrl->ceiling_irq < 0) {
-+ cpr3_err(ctrl, "missing ceiling interrupt\n");
-+ return ctrl->ceiling_irq;
-+ }
-+ }
-+ }
-+
-+ rc = cpr3_regulator_init_ctrl_data(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "CPR controller data initialization failed, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ rc = cpr3_regulator_init_vreg_data(
-+ &ctrl->thread[i].vreg[j]);
-+ if (rc)
-+ return rc;
-+ cpr3_print_quots(&ctrl->thread[i].vreg[j]);
-+ }
-+ }
-+
-+ /*
-+ * Add the maximum possible aging voltage margin until it is possible
-+ * to perform an aging measurement.
-+ */
-+ if (ctrl->aging_required)
-+ cpr3_regulator_set_aging_ref_adjustment(ctrl, INT_MAX);
-+
-+ rc = cpr3_regulator_init_ctrl(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "CPR controller initialization failed, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ /* Register regulator devices for all threads. */
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ rc = cpr3_regulator_vreg_register(
-+ &ctrl->thread[i].vreg[j]);
-+ if (rc) {
-+ cpr3_err(&ctrl->thread[i].vreg[j], "failed to register regulator, rc=%d\n",
-+ rc);
-+ goto free_regulators;
-+ }
-+ }
-+ }
-+
-+ rc = devm_request_threaded_irq(dev, ctrl->irq, NULL,
-+ cpr3_irq_handler,
-+ IRQF_ONESHOT |
-+ IRQF_TRIGGER_RISING,
-+ "cpr3", ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not request IRQ %d, rc=%d\n",
-+ ctrl->irq, rc);
-+ goto free_regulators;
-+ }
-+
-+ if (ctrl->supports_hw_closed_loop &&
-+ ctrl->ctrl_type == CPR_CTRL_TYPE_CPR3) {
-+ rc = devm_request_threaded_irq(dev, ctrl->ceiling_irq, NULL,
-+ cpr3_ceiling_irq_handler,
-+ IRQF_ONESHOT | IRQF_TRIGGER_RISING,
-+ "cpr3_ceiling", ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not request ceiling IRQ %d, rc=%d\n",
-+ ctrl->ceiling_irq, rc);
-+ goto free_regulators;
-+ }
-+ }
-+
-+ mutex_lock(&cpr3_controller_list_mutex);
-+ cpr3_regulator_debugfs_ctrl_add(ctrl);
-+ list_add(&ctrl->list, &cpr3_controller_list);
-+ mutex_unlock(&cpr3_controller_list_mutex);
-+
-+ if (ctrl->panic_regs_info) {
-+ /* Register panic notification call back */
-+ ctrl->panic_notifier.notifier_call = cpr3_panic_callback;
-+ atomic_notifier_chain_register(&panic_notifier_list,
-+ &ctrl->panic_notifier);
-+ }
-+
-+ return 0;
-+
-+free_regulators:
-+ for (i = 0; i < ctrl->thread_count; i++)
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++)
-+ if (!IS_ERR_OR_NULL(ctrl->thread[i].vreg[j].rdev))
-+ regulator_unregister(
-+ ctrl->thread[i].vreg[j].rdev);
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_open_loop_regulator_register() - register the regulators for a CPR3
-+ * controller which will always work in Open loop and
-+ * won't support close loop.
-+ * @pdev: Platform device pointer for the CPR3 controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_open_loop_regulator_register(struct platform_device *pdev,
-+ struct cpr3_controller *ctrl)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct cpr3_regulator *vreg;
-+ int i, j, rc;
-+
-+ if (!dev->of_node) {
-+ dev_err(dev, "%s: Device tree node is missing\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ if (!ctrl || !ctrl->name) {
-+ dev_err(dev, "%s: CPR controller data is missing\n", __func__);
-+ return -EINVAL;
-+ }
-+
-+ if (!ctrl->vdd_regulator) {
-+ cpr3_err(ctrl, "vdd regulator missing\n");
-+ return -EINVAL;
-+ }
-+
-+ mutex_init(&ctrl->lock);
-+
-+ rc = cpr3_regulator_init_ctrl_data(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "CPR controller data initialization failed, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ vreg = &ctrl->thread[i].vreg[j];
-+ vreg->corner[i].last_volt =
-+ vreg->corner[i].open_loop_volt;
-+ }
-+ }
-+
-+ /* Register regulator devices for all threads. */
-+ for (i = 0; i < ctrl->thread_count; i++) {
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++) {
-+ rc = cpr3_regulator_vreg_register(
-+ &ctrl->thread[i].vreg[j]);
-+ if (rc) {
-+ cpr3_err(&ctrl->thread[i].vreg[j], "failed to register regulator, rc=%d\n",
-+ rc);
-+ goto free_regulators;
-+ }
-+ }
-+ }
-+
-+ mutex_lock(&cpr3_controller_list_mutex);
-+ list_add(&ctrl->list, &cpr3_controller_list);
-+ mutex_unlock(&cpr3_controller_list_mutex);
-+
-+ return 0;
-+
-+free_regulators:
-+ for (i = 0; i < ctrl->thread_count; i++)
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++)
-+ if (!IS_ERR_OR_NULL(ctrl->thread[i].vreg[j].rdev))
-+ regulator_unregister(
-+ ctrl->thread[i].vreg[j].rdev);
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_regulator_unregister() - unregister the regulators for a CPR3 controller
-+ * and perform CPR hardware shutdown
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_regulator_unregister(struct cpr3_controller *ctrl)
-+{
-+ int i, j, rc = 0;
-+
-+ mutex_lock(&cpr3_controller_list_mutex);
-+ list_del(&ctrl->list);
-+ cpr3_regulator_debugfs_ctrl_remove(ctrl);
-+ mutex_unlock(&cpr3_controller_list_mutex);
-+
-+ if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) {
-+ rc = cpr3_ctrl_clear_cpr4_config(ctrl);
-+ if (rc)
-+ cpr3_err(ctrl, "failed to clear CPR4 configuration,rc=%d\n",
-+ rc);
-+ }
-+
-+ cpr3_ctrl_loop_disable(ctrl);
-+
-+ cpr3_closed_loop_disable(ctrl);
-+
-+ if (ctrl->vdd_limit_regulator) {
-+ regulator_disable(ctrl->vdd_limit_regulator);
-+ }
-+
-+ for (i = 0; i < ctrl->thread_count; i++)
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++)
-+ regulator_unregister(ctrl->thread[i].vreg[j].rdev);
-+
-+ if (ctrl->panic_notifier.notifier_call)
-+ atomic_notifier_chain_unregister(&panic_notifier_list,
-+ &ctrl->panic_notifier);
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_open_loop_regulator_unregister() - unregister the regulators for a CPR3
-+ * open loop controller and perform CPR hardware shutdown
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_open_loop_regulator_unregister(struct cpr3_controller *ctrl)
-+{
-+ int i, j;
-+
-+ mutex_lock(&cpr3_controller_list_mutex);
-+ list_del(&ctrl->list);
-+ mutex_unlock(&cpr3_controller_list_mutex);
-+
-+ if (ctrl->vdd_limit_regulator) {
-+ regulator_disable(ctrl->vdd_limit_regulator);
-+ }
-+
-+ for (i = 0; i < ctrl->thread_count; i++)
-+ for (j = 0; j < ctrl->thread[i].vreg_count; j++)
-+ regulator_unregister(ctrl->thread[i].vreg[j].rdev);
-+
-+ if (ctrl->panic_notifier.notifier_call)
-+ atomic_notifier_chain_unregister(&panic_notifier_list,
-+ &ctrl->panic_notifier);
-+
-+ return 0;
-+}
---- /dev/null
-+++ b/drivers/regulator/cpr3-regulator.h
-@@ -0,0 +1,1211 @@
-+/*
-+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#ifndef __REGULATOR_CPR3_REGULATOR_H__
-+#define __REGULATOR_CPR3_REGULATOR_H__
-+
-+#include <linux/clk.h>
-+#include <linux/mutex.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/types.h>
-+#include <linux/power/qcom/apm.h>
-+#include <linux/regulator/driver.h>
-+
-+struct cpr3_controller;
-+struct cpr3_thread;
-+
-+/**
-+ * struct cpr3_fuse_param - defines one contiguous segment of a fuse parameter
-+ * that is contained within a given row.
-+ * @row: Fuse row number
-+ * @bit_start: The first bit within the row of the fuse parameter segment
-+ * @bit_end: The last bit within the row of the fuse parameter segment
-+ *
-+ * Each fuse row is 64 bits in length. bit_start and bit_end may take values
-+ * from 0 to 63. bit_start must be less than or equal to bit_end.
-+ */
-+struct cpr3_fuse_param {
-+ unsigned row;
-+ unsigned bit_start;
-+ unsigned bit_end;
-+};
-+
-+/* Each CPR3 sensor has 16 ring oscillators */
-+#define CPR3_RO_COUNT 16
-+
-+/* The maximum number of sensors that can be present on a single CPR loop. */
-+#define CPR3_MAX_SENSOR_COUNT 256
-+
-+/* This constant is used when allocating array printing buffers. */
-+#define MAX_CHARS_PER_INT 10
-+
-+/**
-+ * struct cpr4_sdelta - CPR4 controller specific data structure for the sdelta
-+ * adjustment table which is used to adjust the VDD supply
-+ * voltage automatically based upon the temperature and/or
-+ * the number of online CPU cores.
-+ * @allow_core_count_adj: Core count adjustments are allowed.
-+ * @allow_temp_adj: Temperature based adjustments are allowed.
-+ * @max_core_count: Maximum number of cores considered for core count
-+ * adjustment logic.
-+ * @temp_band_count: Number of temperature bands considered for temperature
-+ * based adjustment logic.
-+ * @cap_volt: CAP in uV to apply to SDELTA margins with multiple
-+ * cpr3-regulators defined for single controller.
-+ * @table: SDELTA table with per-online-core and temperature based
-+ * adjustments of size (max_core_count * temp_band_count)
-+ * Outer: core count
-+ * Inner: temperature band
-+ * Each element has units of VDD supply steps. Positive
-+ * values correspond to a reduction in voltage and negative
-+ * value correspond to an increase (this follows the SDELTA
-+ * register semantics).
-+ * @allow_boost: Voltage boost allowed.
-+ * @boost_num_cores: The number of online cores at which the boost voltage
-+ * adjustments will be applied
-+ * @boost_table: SDELTA table with boost voltage adjustments of size
-+ * temp_band_count. Each element has units of VDD supply
-+ * steps. Positive values correspond to a reduction in
-+ * voltage and negative value correspond to an increase
-+ * (this follows the SDELTA register semantics).
-+ */
-+struct cpr4_sdelta {
-+ bool allow_core_count_adj;
-+ bool allow_temp_adj;
-+ int max_core_count;
-+ int temp_band_count;
-+ int cap_volt;
-+ int *table;
-+ bool allow_boost;
-+ int boost_num_cores;
-+ int *boost_table;
-+};
-+
-+/**
-+ * struct cpr3_corner - CPR3 virtual voltage corner data structure
-+ * @floor_volt: CPR closed-loop floor voltage in microvolts
-+ * @ceiling_volt: CPR closed-loop ceiling voltage in microvolts
-+ * @open_loop_volt: CPR open-loop voltage (i.e. initial voltage) in
-+ * microvolts
-+ * @last_volt: Last known settled CPR closed-loop voltage which is used
-+ * when switching to a new corner
-+ * @abs_ceiling_volt: The absolute CPR closed-loop ceiling voltage in
-+ * microvolts. This is used to limit the ceiling_volt
-+ * value when it is increased as a result of aging
-+ * adjustment.
-+ * @unaged_floor_volt: The CPR closed-loop floor voltage in microvolts before
-+ * any aging adjustment is performed
-+ * @unaged_ceiling_volt: The CPR closed-loop ceiling voltage in microvolts
-+ * before any aging adjustment is performed
-+ * @unaged_open_loop_volt: The CPR open-loop voltage (i.e. initial voltage) in
-+ * microvolts before any aging adjusment is performed
-+ * @system_volt: The system-supply voltage in microvolts or corners or
-+ * levels
-+ * @mem_acc_volt: The mem-acc-supply voltage in corners
-+ * @proc_freq: Processor frequency in Hertz. For CPR rev. 3 and 4
-+ * conrollers, this field is only used by platform specific
-+ * CPR3 driver for interpolation. For CPRh-compliant
-+ * controllers, this frequency is also utilized by the
-+ * clock driver to determine the corner to CPU clock
-+ * frequency mappings.
-+ * @cpr_fuse_corner: Fused corner index associated with this virtual corner
-+ * (only used by platform specific CPR3 driver for
-+ * mapping purposes)
-+ * @target_quot: Array of target quotient values to use for each ring
-+ * oscillator (RO) for this corner. A value of 0 should be
-+ * specified as the target quotient for each RO that is
-+ * unused by this corner.
-+ * @ro_scale: Array of CPR ring oscillator (RO) scaling factors. The
-+ * scaling factor for each RO is defined from RO0 to RO15
-+ * with units of QUOT/V. A value of 0 may be specified for
-+ * an RO that is unused.
-+ * @ro_mask: Bitmap where each of the 16 LSBs indicate if the
-+ * corresponding ROs should be masked for this corner
-+ * @irq_en: Bitmap of the CPR interrupts to enable for this corner
-+ * @aging_derate: The amount to derate the aging voltage adjustment
-+ * determined for the reference corner in units of uV/mV.
-+ * E.g. a value of 900 would imply that the adjustment for
-+ * this corner should be 90% (900/1000) of that for the
-+ * reference corner.
-+ * @use_open_loop: Boolean indicating that open-loop (i.e CPR disabled) as
-+ * opposed to closed-loop operation must be used for this
-+ * corner on CPRh controllers.
-+ * @sdelta: The CPR4 controller specific data for this corner. This
-+ * field is applicable for CPR4 controllers.
-+ *
-+ * The value of last_volt is initialized inside of the cpr3_regulator_register()
-+ * call with the open_loop_volt value. It can later be updated to the settled
-+ * VDD supply voltage. The values for unaged_floor_volt, unaged_ceiling_volt,
-+ * and unaged_open_loop_volt are initialized inside of cpr3_regulator_register()
-+ * if ctrl->aging_required == true. These three values must be pre-initialized
-+ * if cpr3_regulator_register() is called with ctrl->aging_required == false and
-+ * ctrl->aging_succeeded == true.
-+ *
-+ * The values of ro_mask and irq_en are initialized inside of the
-+ * cpr3_regulator_register() call.
-+ */
-+struct cpr3_corner {
-+ int floor_volt;
-+ int ceiling_volt;
-+ int cold_temp_open_loop_volt;
-+ int normal_temp_open_loop_volt;
-+ int open_loop_volt;
-+ int last_volt;
-+ int abs_ceiling_volt;
-+ int unaged_floor_volt;
-+ int unaged_ceiling_volt;
-+ int unaged_open_loop_volt;
-+ int system_volt;
-+ int mem_acc_volt;
-+ u32 proc_freq;
-+ int cpr_fuse_corner;
-+ u32 target_quot[CPR3_RO_COUNT];
-+ u32 ro_scale[CPR3_RO_COUNT];
-+ u32 ro_mask;
-+ u32 irq_en;
-+ int aging_derate;
-+ bool use_open_loop;
-+ struct cpr4_sdelta *sdelta;
-+};
-+
-+/**
-+ * struct cprh_corner_band - CPRh controller specific data structure which
-+ * encapsulates the range of corners and the SDELTA
-+ * adjustment table to be applied to the corners within
-+ * the min and max bounds of the corner band.
-+ * @corner: Corner number which defines the corner band boundary
-+ * @sdelta: The SDELTA adjustment table which contains core-count
-+ * and temp based margin adjustments that are applicable
-+ * to the corner band.
-+ */
-+struct cprh_corner_band {
-+ int corner;
-+ struct cpr4_sdelta *sdelta;
-+};
-+
-+/**
-+ * struct cpr3_fuse_parameters - CPR4 fuse specific data structure which has
-+ * the required fuse parameters need for Close Loop CPR
-+ * @(*apss_ro_sel_param)[2]: Pointer to RO select fuse details
-+ * @(*apss_init_voltage_param)[2]: Pointer to Target voltage fuse details
-+ * @(*apss_target_quot_param)[2]: Pointer to Target quot fuse details
-+ * @(*apss_quot_offset_param)[2]: Pointer to quot offset fuse details
-+ * @cpr_fusing_rev_param: Pointer to CPR revision fuse details
-+ * @apss_speed_bin_param: Pointer to Speed bin fuse details
-+ * @cpr_boost_fuse_cfg_param: Pointer to Boost fuse cfg details
-+ * @apss_boost_fuse_volt_param: Pointer to Boost fuse volt details
-+ * @misc_fuse_volt_adj_param: Pointer to Misc fuse volt fuse details
-+ */
-+struct cpr3_fuse_parameters {
-+ struct cpr3_fuse_param (*apss_ro_sel_param)[2];
-+ struct cpr3_fuse_param (*apss_init_voltage_param)[2];
-+ struct cpr3_fuse_param (*apss_target_quot_param)[2];
-+ struct cpr3_fuse_param (*apss_quot_offset_param)[2];
-+ struct cpr3_fuse_param *cpr_fusing_rev_param;
-+ struct cpr3_fuse_param *apss_speed_bin_param;
-+ struct cpr3_fuse_param *cpr_boost_fuse_cfg_param;
-+ struct cpr3_fuse_param *apss_boost_fuse_volt_param;
-+ struct cpr3_fuse_param *misc_fuse_volt_adj_param;
-+};
-+
-+struct cpr4_mem_acc_func {
-+ void (*set_mem_acc)(struct regulator_dev *);
-+ void (*clear_mem_acc)(struct regulator_dev *);
-+};
-+
-+/**
-+ * struct cpr4_reg_data - CPR4 regulator specific data structure which is
-+ * target specific
-+ * @cpr_valid_fuse_count: Number of valid fuse corners
-+ * @fuse_ref_volt: Pointer to fuse reference voltage
-+ * @fuse_step_volt: CPR step voltage available in fuse
-+ * @cpr_clk_rate: CPR clock rate
-+ * @boost_fuse_ref_volt: Boost fuse reference voltage
-+ * @boost_ceiling_volt: Boost ceiling voltage
-+ * @boost_floor_volt: Boost floor voltage
-+ * @cpr3_fuse_params: Pointer to CPR fuse parameters
-+ * @mem_acc_funcs: Pointer to MEM ACC set/clear functions
-+ **/
-+struct cpr4_reg_data {
-+ u32 cpr_valid_fuse_count;
-+ int *fuse_ref_volt;
-+ u32 fuse_step_volt;
-+ u32 cpr_clk_rate;
-+ int boost_fuse_ref_volt;
-+ int boost_ceiling_volt;
-+ int boost_floor_volt;
-+ struct cpr3_fuse_parameters *cpr3_fuse_params;
-+ struct cpr4_mem_acc_func *mem_acc_funcs;
-+};
-+/**
-+ * struct cpr3_reg_data - CPR3 regulator specific data structure which is
-+ * target specific
-+ * @cpr_valid_fuse_count: Number of valid fuse corners
-+ * @(*init_voltage_param)[2]: Pointer to Target voltage fuse details
-+ * @fuse_ref_volt: Pointer to fuse reference voltage
-+ * @fuse_step_volt: CPR step voltage available in fuse
-+ * @cpr_clk_rate: CPR clock rate
-+ * @cpr3_fuse_params: Pointer to CPR fuse parameters
-+ **/
-+struct cpr3_reg_data {
-+ u32 cpr_valid_fuse_count;
-+ struct cpr3_fuse_param (*init_voltage_param)[2];
-+ int *fuse_ref_volt;
-+ u32 fuse_step_volt;
-+ u32 cpr_clk_rate;
-+};
-+
-+/**
-+ * struct cpr3_regulator - CPR3 logical regulator instance associated with a
-+ * given CPR3 hardware thread
-+ * @of_node: Device node associated with the device tree child node
-+ * of this CPR3 regulator
-+ * @thread: Pointer to the CPR3 thread which manages this CPR3
-+ * regulator
-+ * @name: Unique name for this CPR3 regulator which is filled
-+ * using the device tree regulator-name property
-+ * @rdesc: Regulator description for this CPR3 regulator
-+ * @rdev: Regulator device pointer for the regulator registered
-+ * for this CPR3 regulator
-+ * @mem_acc_regulator: Pointer to the optional mem-acc supply regulator used
-+ * to manage memory circuitry settings based upon CPR3
-+ * regulator output voltage.
-+ * @corner: Array of all corners supported by this CPR3 regulator
-+ * @corner_count: The number of elements in the corner array
-+ * @corner_band: Array of all corner bands supported by CPRh compatible
-+ * controllers
-+ * @cpr4_regulator_data Target specific cpr4 regulator data
-+ * @cpr3_regulator_data Target specific cpr3 regulator data
-+ * @corner_band_count: The number of elements in the corner band array
-+ * @platform_fuses: Pointer to platform specific CPR fuse data (only used by
-+ * platform specific CPR3 driver)
-+ * @speed_bin_fuse: Value read from the speed bin fuse parameter
-+ * @speed_bins_supported: The number of speed bins supported by the device tree
-+ * configuration for this CPR3 regulator
-+ * @cpr_rev_fuse: Value read from the CPR fusing revision fuse parameter
-+ * @fuse_combo: Platform specific enum value identifying the specific
-+ * combination of fuse values found on a given chip
-+ * @fuse_combos_supported: The number of fuse combinations supported by the
-+ * device tree configuration for this CPR3 regulator
-+ * @fuse_corner_count: Number of corners defined by fuse parameters
-+ * @fuse_corner_map: Array of length fuse_corner_count which specifies the
-+ * highest corner associated with each fuse corner. Note
-+ * that each element must correspond to a valid corner
-+ * and that element values must be strictly increasing.
-+ * Also, it is acceptable for the lowest fuse corner to map
-+ * to a corner other than the lowest. Likewise, it is
-+ * acceptable for the highest fuse corner to map to a
-+ * corner other than the highest.
-+ * @fuse_combo_corner_sum: The sum of the corner counts across all fuse combos
-+ * @fuse_combo_offset: The device tree property array offset for the selected
-+ * fuse combo
-+ * @speed_bin_corner_sum: The sum of the corner counts across all speed bins
-+ * This may be specified as 0 if per speed bin parsing
-+ * support is not required.
-+ * @speed_bin_offset: The device tree property array offset for the selected
-+ * speed bin
-+ * @fuse_combo_corner_band_sum: The sum of the corner band counts across all
-+ * fuse combos
-+ * @fuse_combo_corner_band_offset: The device tree property array offset for
-+ * the corner band count corresponding to the selected
-+ * fuse combo
-+ * @speed_bin_corner_band_sum: The sum of the corner band counts across all
-+ * speed bins. This may be specified as 0 if per speed bin
-+ * parsing support is not required
-+ * @speed_bin_corner_band_offset: The device tree property array offset for the
-+ * corner band count corresponding to the selected speed
-+ * bin
-+ * @pd_bypass_mask: Bit mask of power domains associated with this CPR3
-+ * regulator
-+ * @dynamic_floor_corner: Index identifying the voltage corner for the CPR3
-+ * regulator whose last_volt value should be used as the
-+ * global CPR floor voltage if all of the power domains
-+ * associated with this CPR3 regulator are bypassed
-+ * @uses_dynamic_floor: Boolean flag indicating that dynamic_floor_corner should
-+ * be utilized for the CPR3 regulator
-+ * @current_corner: Index identifying the currently selected voltage corner
-+ * for the CPR3 regulator or less than 0 if no corner has
-+ * been requested
-+ * @last_closed_loop_corner: Index identifying the last voltage corner for the
-+ * CPR3 regulator which was configured when operating in
-+ * CPR closed-loop mode or less than 0 if no corner has
-+ * been requested. CPR registers are only written to when
-+ * using closed-loop mode.
-+ * @aggregated: Boolean flag indicating that this CPR3 regulator
-+ * participated in the last aggregation event
-+ * @debug_corner: Index identifying voltage corner used for displaying
-+ * corner configuration values in debugfs
-+ * @vreg_enabled: Boolean defining the enable state of the CPR3
-+ * regulator's regulator within the regulator framework.
-+ * @aging_allowed: Boolean defining if CPR aging adjustments are allowed
-+ * for this CPR3 regulator given the fuse combo of the
-+ * device
-+ * @aging_allow_open_loop_adj: Boolean defining if the open-loop voltage of each
-+ * corner of this regulator should be adjusted as a result
-+ * of an aging measurement. This flag can be set to false
-+ * when the open-loop voltage adjustments have been
-+ * specified such that they include the maximum possible
-+ * aging adjustment. This flag is only used if
-+ * aging_allowed == true.
-+ * @aging_corner: The corner that should be configured for this regulator
-+ * when an aging measurement is performed.
-+ * @aging_max_adjust_volt: The maximum aging voltage margin in microvolts that
-+ * may be added to the target quotients of this regulator.
-+ * A value of 0 may be specified if this regulator does not
-+ * require any aging adjustment.
-+ * @allow_core_count_adj: Core count adjustments are allowed for this regulator.
-+ * @allow_temp_adj: Temperature based adjustments are allowed for this
-+ * regulator.
-+ * @max_core_count: Maximum number of cores considered for core count
-+ * adjustment logic.
-+ * @allow_boost: Voltage boost allowed for this regulator.
-+ *
-+ * This structure contains both configuration and runtime state data. The
-+ * elements current_corner, last_closed_loop_corner, aggregated, debug_corner,
-+ * and vreg_enabled are state variables.
-+ */
-+struct cpr3_regulator {
-+ struct device_node *of_node;
-+ struct cpr3_thread *thread;
-+ const char *name;
-+ struct regulator_desc rdesc;
-+ struct regulator_dev *rdev;
-+ struct regulator *mem_acc_regulator;
-+ struct cpr3_corner *corner;
-+ int corner_count;
-+ struct cprh_corner_band *corner_band;
-+ struct cpr4_reg_data *cpr4_regulator_data;
-+ struct cpr3_reg_data *cpr3_regulator_data;
-+ u32 corner_band_count;
-+
-+ void *platform_fuses;
-+ int speed_bin_fuse;
-+ int speed_bins_supported;
-+ int cpr_rev_fuse;
-+ int part_type;
-+ int part_type_supported;
-+ int fuse_combo;
-+ int fuse_combos_supported;
-+ int fuse_corner_count;
-+ int *fuse_corner_map;
-+ int fuse_combo_corner_sum;
-+ int fuse_combo_offset;
-+ int speed_bin_corner_sum;
-+ int speed_bin_offset;
-+ int fuse_combo_corner_band_sum;
-+ int fuse_combo_corner_band_offset;
-+ int speed_bin_corner_band_sum;
-+ int speed_bin_corner_band_offset;
-+ u32 pd_bypass_mask;
-+ int dynamic_floor_corner;
-+ bool uses_dynamic_floor;
-+
-+ int current_corner;
-+ int last_closed_loop_corner;
-+ bool aggregated;
-+ int debug_corner;
-+ bool vreg_enabled;
-+
-+ bool aging_allowed;
-+ bool aging_allow_open_loop_adj;
-+ int aging_corner;
-+ int aging_max_adjust_volt;
-+
-+ bool allow_core_count_adj;
-+ bool allow_temp_adj;
-+ int max_core_count;
-+ bool allow_boost;
-+};
-+
-+/**
-+ * struct cpr3_thread - CPR3 hardware thread data structure
-+ * @thread_id: Hardware thread ID
-+ * @of_node: Device node associated with the device tree child node
-+ * of this CPR3 thread
-+ * @ctrl: Pointer to the CPR3 controller which manages this thread
-+ * @vreg: Array of CPR3 regulators handled by the CPR3 thread
-+ * @vreg_count: Number of elements in the vreg array
-+ * @aggr_corner: CPR corner containing the in process aggregated voltage
-+ * and target quotient configurations which will be applied
-+ * @last_closed_loop_aggr_corner: CPR corner containing the most recent
-+ * configurations which were written into hardware
-+ * registers when operating in closed loop mode (i.e. with
-+ * CPR enabled)
-+ * @consecutive_up: The number of consecutive CPR step up events needed to
-+ * to trigger an up interrupt
-+ * @consecutive_down: The number of consecutive CPR step down events needed to
-+ * to trigger a down interrupt
-+ * @up_threshold: The number CPR error steps required to generate an up
-+ * event
-+ * @down_threshold: The number CPR error steps required to generate a down
-+ * event
-+ *
-+ * This structure contains both configuration and runtime state data. The
-+ * elements aggr_corner and last_closed_loop_aggr_corner are state variables.
-+ */
-+struct cpr3_thread {
-+ u32 thread_id;
-+ struct device_node *of_node;
-+ struct cpr3_controller *ctrl;
-+ struct cpr3_regulator *vreg;
-+ int vreg_count;
-+ struct cpr3_corner aggr_corner;
-+ struct cpr3_corner last_closed_loop_aggr_corner;
-+
-+ u32 consecutive_up;
-+ u32 consecutive_down;
-+ u32 up_threshold;
-+ u32 down_threshold;
-+};
-+
-+/* Per CPR controller data */
-+/**
-+ * enum cpr3_mem_acc_corners - Constants which define the number of mem-acc
-+ * regulator corners available in the mem-acc corner map array.
-+ * %CPR3_MEM_ACC_LOW_CORNER: Index in mem-acc corner map array mapping to the
-+ * mem-acc regulator corner
-+ * to be used for low voltage vdd supply
-+ * %CPR3_MEM_ACC_HIGH_CORNER: Index in mem-acc corner map array mapping to the
-+ * mem-acc regulator corner to be used for high
-+ * voltage vdd supply
-+ * %CPR3_MEM_ACC_CORNERS: Number of elements in the mem-acc corner map
-+ * array
-+ */
-+enum cpr3_mem_acc_corners {
-+ CPR3_MEM_ACC_LOW_CORNER = 0,
-+ CPR3_MEM_ACC_HIGH_CORNER = 1,
-+ CPR3_MEM_ACC_CORNERS = 2,
-+};
-+
-+/**
-+ * enum cpr3_count_mode - CPR3 controller count mode which defines the
-+ * method that CPR sensor data is acquired
-+ * %CPR3_COUNT_MODE_ALL_AT_ONCE_MIN: Capture all CPR sensor readings
-+ * simultaneously and report the minimum
-+ * value seen in successive measurements
-+ * %CPR3_COUNT_MODE_ALL_AT_ONCE_MAX: Capture all CPR sensor readings
-+ * simultaneously and report the maximum
-+ * value seen in successive measurements
-+ * %CPR3_COUNT_MODE_STAGGERED: Read one sensor at a time in a
-+ * sequential fashion
-+ * %CPR3_COUNT_MODE_ALL_AT_ONCE_AGE: Capture all CPR aging sensor readings
-+ * simultaneously.
-+ */
-+enum cpr3_count_mode {
-+ CPR3_COUNT_MODE_ALL_AT_ONCE_MIN = 0,
-+ CPR3_COUNT_MODE_ALL_AT_ONCE_MAX = 1,
-+ CPR3_COUNT_MODE_STAGGERED = 2,
-+ CPR3_COUNT_MODE_ALL_AT_ONCE_AGE = 3,
-+};
-+
-+/**
-+ * enum cpr_controller_type - supported CPR controller hardware types
-+ * %CPR_CTRL_TYPE_CPR3: HW has CPR3 controller
-+ * %CPR_CTRL_TYPE_CPR4: HW has CPR4 controller
-+ */
-+enum cpr_controller_type {
-+ CPR_CTRL_TYPE_CPR3,
-+ CPR_CTRL_TYPE_CPR4,
-+};
-+
-+/**
-+ * cpr_setting - supported CPR global settings
-+ * %CPR_DEFAULT: default mode from dts will be used
-+ * %CPR_DISABLED: ceiling voltage will be used for all the corners
-+ * %CPR_OPEN_LOOP_EN: CPR will work in OL
-+ * %CPR_CLOSED_LOOP_EN: CPR will work in CL, if supported
-+ */
-+enum cpr_setting {
-+ CPR_DEFAULT = 0,
-+ CPR_DISABLED = 1,
-+ CPR_OPEN_LOOP_EN = 2,
-+ CPR_CLOSED_LOOP_EN = 3,
-+};
-+
-+/**
-+ * struct cpr3_aging_sensor_info - CPR3 aging sensor information
-+ * @sensor_id The index of the CPR3 sensor to be used in the aging
-+ * measurement.
-+ * @ro_scale The CPR ring oscillator (RO) scaling factor for the
-+ * aging sensor with units of QUOT/V.
-+ * @init_quot_diff: The fused quotient difference between aged and un-aged
-+ * paths that was measured at manufacturing time.
-+ * @measured_quot_diff: The quotient difference measured at runtime.
-+ * @bypass_mask: Bit mask of the CPR sensors that must be bypassed during
-+ * the aging measurement for this sensor
-+ *
-+ * This structure contains both configuration and runtime state data. The
-+ * element measured_quot_diff is a state variable.
-+ */
-+struct cpr3_aging_sensor_info {
-+ u32 sensor_id;
-+ u32 ro_scale;
-+ int init_quot_diff;
-+ int measured_quot_diff;
-+ u32 bypass_mask[CPR3_MAX_SENSOR_COUNT / 32];
-+};
-+
-+/**
-+ * struct cpr3_reg_info - Register information data structure
-+ * @name: Register name
-+ * @addr: Register physical address
-+ * @value: Register content
-+ * @virt_addr: Register virtual address
-+ *
-+ * This data structure is used to dump some critical register contents
-+ * when the device crashes due to a kernel panic.
-+ */
-+struct cpr3_reg_info {
-+ const char *name;
-+ u32 addr;
-+ u32 value;
-+ void __iomem *virt_addr;
-+};
-+
-+/**
-+ * struct cpr3_panic_regs_info - Data structure to dump critical register
-+ * contents.
-+ * @reg_count: Number of elements in the regs array
-+ * @regs: Array of critical registers information
-+ *
-+ * This data structure is used to dump critical register contents when
-+ * the device crashes due to a kernel panic.
-+ */
-+struct cpr3_panic_regs_info {
-+ int reg_count;
-+ struct cpr3_reg_info *regs;
-+};
-+
-+/**
-+ * struct cpr3_controller - CPR3 controller data structure
-+ * @dev: Device pointer for the CPR3 controller device
-+ * @name: Unique name for the CPR3 controller
-+ * @ctrl_id: Controller ID corresponding to the VDD supply number
-+ * that this CPR3 controller manages.
-+ * @cpr_ctrl_base: Virtual address of the CPR3 controller base register
-+ * @fuse_base: Virtual address of fuse row 0
-+ * @aging_possible_reg: Virtual address of an optional platform-specific
-+ * register that must be ready to determine if it is
-+ * possible to perform an aging measurement.
-+ * @list: list head used in a global cpr3-regulator list so that
-+ * cpr3-regulator structs can be found easily in RAM dumps
-+ * @thread: Array of CPR3 threads managed by the CPR3 controller
-+ * @thread_count: Number of elements in the thread array
-+ * @sensor_owner: Array of thread IDs indicating which thread owns a given
-+ * CPR sensor
-+ * @sensor_count: The number of CPR sensors found on the CPR loop managed
-+ * by this CPR controller. Must be equal to the number of
-+ * elements in the sensor_owner array
-+ * @soc_revision: Revision number of the SoC. This may be unused by
-+ * platforms that do not have different behavior for
-+ * different SoC revisions.
-+ * @lock: Mutex lock used to ensure mutual exclusion between
-+ * all of the threads associated with the controller
-+ * @vdd_regulator: Pointer to the VDD supply regulator which this CPR3
-+ * controller manages
-+ * @system_regulator: Pointer to the optional system-supply regulator upon
-+ * which the VDD supply regulator depends.
-+ * @mem_acc_regulator: Pointer to the optional mem-acc supply regulator used
-+ * to manage memory circuitry settings based upon the
-+ * VDD supply output voltage.
-+ * @vdd_limit_regulator: Pointer to the VDD supply limit regulator which is used
-+ * for hardware closed-loop in order specify ceiling and
-+ * floor voltage limits (platform specific)
-+ * @system_supply_max_volt: Voltage in microvolts which corresponds to the
-+ * absolute ceiling voltage of the system-supply
-+ * @mem_acc_threshold_volt: mem-acc threshold voltage in microvolts
-+ * @mem_acc_corner_map: mem-acc regulator corners mapping to low and high
-+ * voltage mem-acc settings for the memories powered by
-+ * this CPR3 controller and its associated CPR3 regulators
-+ * @mem_acc_crossover_volt: Voltage in microvolts corresponding to the voltage
-+ * that the VDD supply must be set to while a MEM ACC
-+ * switch is in progress. This element must be initialized
-+ * for CPRh controllers when a MEM ACC threshold voltage is
-+ * defined.
-+ * @core_clk: Pointer to the CPR3 controller core clock
-+ * @iface_clk: Pointer to the CPR3 interface clock (platform specific)
-+ * @bus_clk: Pointer to the CPR3 bus clock (platform specific)
-+ * @irq: CPR interrupt number
-+ * @irq_affinity_mask: The cpumask for the CPUs which the CPR interrupt should
-+ * have affinity for
-+ * @cpu_hotplug_notifier: CPU hotplug notifier used to reset IRQ affinity when a
-+ * CPU is brought back online
-+ * @ceiling_irq: Interrupt number for the interrupt that is triggered
-+ * when hardware closed-loop attempts to exceed the ceiling
-+ * voltage
-+ * @apm: Handle to the array power mux (APM)
-+ * @apm_threshold_volt: Voltage in microvolts which defines the threshold
-+ * voltage to determine the APM supply selection for
-+ * each corner
-+ * @apm_crossover_volt: Voltage in microvolts corresponding to the voltage that
-+ * the VDD supply must be set to while an APM switch is in
-+ * progress. This element must be initialized for CPRh
-+ * controllers when an APM threshold voltage is defined
-+ * @apm_adj_volt: Minimum difference between APM threshold voltage and
-+ * open-loop voltage which allows the APM threshold voltage
-+ * to be used as a ceiling
-+ * @apm_high_supply: APM supply to configure if VDD voltage is greater than
-+ * or equal to the APM threshold voltage
-+ * @apm_low_supply: APM supply to configure if the VDD voltage is less than
-+ * the APM threshold voltage
-+ * @base_volt: Minimum voltage in microvolts supported by the VDD
-+ * supply managed by this CPR controller
-+ * @corner_switch_delay_time: The delay time in nanoseconds used by the CPR
-+ * controller to wait for voltage settling before
-+ * acknowledging the OSM block after corner changes
-+ * @cpr_clock_rate: CPR reference clock frequency in Hz.
-+ * @sensor_time: The time in nanoseconds that each sensor takes to
-+ * perform a measurement.
-+ * @loop_time: The time in nanoseconds between consecutive CPR
-+ * measurements.
-+ * @up_down_delay_time: The time to delay in nanoseconds between consecutive CPR
-+ * measurements when the last measurement recommended
-+ * increasing or decreasing the vdd-supply voltage.
-+ * (platform specific)
-+ * @idle_clocks: Number of CPR reference clock ticks that the CPR
-+ * controller waits in transitional states.
-+ * @step_quot_init_min: The default minimum CPR step quotient value. The step
-+ * quotient is the number of additional ring oscillator
-+ * ticks observed when increasing one step in vdd-supply
-+ * output voltage.
-+ * @step_quot_init_max: The default maximum CPR step quotient value.
-+ * @step_volt: Step size in microvolts between available set points
-+ * of the VDD supply
-+ * @down_error_step_limit: CPR4 hardware closed-loop down error step limit which
-+ * defines the maximum number of VDD supply regulator steps
-+ * that the voltage may be reduced as the result of a
-+ * single CPR measurement.
-+ * @up_error_step_limit: CPR4 hardware closed-loop up error step limit which
-+ * defines the maximum number of VDD supply regulator steps
-+ * that the voltage may be increased as the result of a
-+ * single CPR measurement.
-+ * @count_mode: CPR controller count mode
-+ * @count_repeat: Number of times to perform consecutive sensor
-+ * measurements when using all-at-once count modes.
-+ * @proc_clock_throttle: Defines the processor clock frequency throttling
-+ * register value to use. This can be used to reduce the
-+ * clock frequency when a power domain exits a low power
-+ * mode until CPR settles at a new voltage.
-+ * (platform specific)
-+ * @cpr_allowed_hw: Boolean which indicates if closed-loop CPR operation is
-+ * permitted for a given chip based upon hardware fuse
-+ * values
-+ * @cpr_allowed_sw: Boolean which indicates if closed-loop CPR operation is
-+ * permitted based upon software policies
-+ * @supports_hw_closed_loop: Boolean which indicates if this CPR3/4 controller
-+ * physically supports hardware closed-loop CPR operation
-+ * @use_hw_closed_loop: Boolean which indicates that this controller will be
-+ * using hardware closed-loop operation in place of
-+ * software closed-loop operation.
-+ * @ctrl_type: CPR controller type
-+ * @saw_use_unit_mV: Boolean which indicates the unit used in SAW PVC
-+ * interface is mV.
-+ * @aggr_corner: CPR corner containing the most recently aggregated
-+ * voltage configurations which are being used currently
-+ * @cpr_enabled: Boolean which indicates that the CPR controller is
-+ * enabled and operating in closed-loop mode. CPR clocks
-+ * have been prepared and enabled whenever this flag is
-+ * true.
-+ * @last_corner_was_closed_loop: Boolean indicating if the last known corners
-+ * were updated during closed loop operation.
-+ * @cpr_suspended: Boolean which indicates that CPR has been temporarily
-+ * disabled while enterring system suspend.
-+ * @debugfs: Pointer to the debugfs directory of this CPR3 controller
-+ * @aging_ref_volt: Reference voltage in microvolts to configure when
-+ * performing CPR aging measurements.
-+ * @aging_vdd_mode: vdd-supply regulator mode to configure before performing
-+ * a CPR aging measurement. It should be one of
-+ * REGULATOR_MODE_*.
-+ * @aging_complete_vdd_mode: vdd-supply regulator mode to configure after
-+ * performing a CPR aging measurement. It should be one of
-+ * REGULATOR_MODE_*.
-+ * @aging_ref_adjust_volt: The reference aging voltage margin in microvolts that
-+ * should be added to the target quotients of the
-+ * regulators managed by this controller after derating.
-+ * @aging_required: Flag which indicates that a CPR aging measurement still
-+ * needs to be performed for this CPR3 controller.
-+ * @aging_succeeded: Flag which indicates that a CPR aging measurement has
-+ * completed successfully.
-+ * @aging_failed: Flag which indicates that a CPR aging measurement has
-+ * failed to complete successfully.
-+ * @aging_sensor: Array of CPR3 aging sensors which are used to perform
-+ * aging measurements at a runtime.
-+ * @aging_sensor_count: Number of elements in the aging_sensor array
-+ * @aging_possible_mask: Optional bitmask used to mask off the
-+ * aging_possible_reg register.
-+ * @aging_possible_val: Optional value that the masked aging_possible_reg
-+ * register must have in order for a CPR aging measurement
-+ * to be possible.
-+ * @step_quot_fixed: Fixed step quotient value used for target quotient
-+ * adjustment if use_dynamic_step_quot is not set.
-+ * This parameter is only relevant for CPR4 controllers
-+ * when using the per-online-core or per-temperature
-+ * adjustments.
-+ * @initial_temp_band: Temperature band used for calculation of base-line
-+ * target quotients (fused).
-+ * @use_dynamic_step_quot: Boolean value which indicates that margin adjustment
-+ * of target quotient will be based on the step quotient
-+ * calculated dynamically in hardware for each RO.
-+ * @allow_core_count_adj: Core count adjustments are allowed for this controller
-+ * @allow_temp_adj: Temperature based adjustments are allowed for
-+ * this controller
-+ * @allow_boost: Voltage boost allowed for this controller.
-+ * @temp_band_count: Number of temperature bands used for temperature based
-+ * adjustment logic
-+ * @temp_points: Array of temperature points in decidegrees Celsius used
-+ * to specify the ranges for selected temperature bands.
-+ * The array must have (temp_band_count - 1) elements
-+ * allocated.
-+ * @temp_sensor_id_start: Start ID of temperature sensors used for temperature
-+ * based adjustments.
-+ * @temp_sensor_id_end: End ID of temperature sensors used for temperature
-+ * based adjustments.
-+ * @voltage_settling_time: The time in nanoseconds that it takes for the
-+ * VDD supply voltage to settle after being increased or
-+ * decreased by step_volt microvolts which is used when
-+ * SDELTA voltage margin adjustments are applied.
-+ * @cpr_global_setting: Global setting for this CPR controller
-+ * @panic_regs_info: Array of panic registers information which provides the
-+ * list of registers to dump when the device crashes.
-+ * @panic_notifier: Notifier block registered to global panic notifier list.
-+ *
-+ * This structure contains both configuration and runtime state data. The
-+ * elements cpr_allowed_sw, use_hw_closed_loop, aggr_corner, cpr_enabled,
-+ * last_corner_was_closed_loop, cpr_suspended, aging_ref_adjust_volt,
-+ * aging_required, aging_succeeded, and aging_failed are state variables.
-+ *
-+ * The apm* elements do not need to be initialized if the VDD supply managed by
-+ * the CPR3 controller does not utilize an APM.
-+ *
-+ * The elements step_quot_fixed, initial_temp_band, allow_core_count_adj,
-+ * allow_temp_adj and temp* need to be initialized for CPR4 controllers which
-+ * are using per-online-core or per-temperature adjustments.
-+ */
-+struct cpr3_controller {
-+ struct device *dev;
-+ const char *name;
-+ int ctrl_id;
-+ void __iomem *cpr_ctrl_base;
-+ void __iomem *fuse_base;
-+ void __iomem *aging_possible_reg;
-+ struct list_head list;
-+ struct cpr3_thread *thread;
-+ int thread_count;
-+ u8 *sensor_owner;
-+ int sensor_count;
-+ int soc_revision;
-+ struct mutex lock;
-+ struct regulator *vdd_regulator;
-+ struct regulator *system_regulator;
-+ struct regulator *mem_acc_regulator;
-+ struct regulator *vdd_limit_regulator;
-+ int system_supply_max_volt;
-+ int mem_acc_threshold_volt;
-+ int mem_acc_corner_map[CPR3_MEM_ACC_CORNERS];
-+ int mem_acc_crossover_volt;
-+ struct clk *core_clk;
-+ struct clk *iface_clk;
-+ struct clk *bus_clk;
-+ int irq;
-+ struct cpumask irq_affinity_mask;
-+ struct notifier_block cpu_hotplug_notifier;
-+ int ceiling_irq;
-+ struct msm_apm_ctrl_dev *apm;
-+ int apm_threshold_volt;
-+ int apm_crossover_volt;
-+ int apm_adj_volt;
-+ enum msm_apm_supply apm_high_supply;
-+ enum msm_apm_supply apm_low_supply;
-+ int base_volt;
-+ u32 corner_switch_delay_time;
-+ u32 cpr_clock_rate;
-+ u32 sensor_time;
-+ u32 loop_time;
-+ u32 up_down_delay_time;
-+ u32 idle_clocks;
-+ u32 step_quot_init_min;
-+ u32 step_quot_init_max;
-+ int step_volt;
-+ u32 down_error_step_limit;
-+ u32 up_error_step_limit;
-+ enum cpr3_count_mode count_mode;
-+ u32 count_repeat;
-+ u32 proc_clock_throttle;
-+ bool cpr_allowed_hw;
-+ bool cpr_allowed_sw;
-+ bool supports_hw_closed_loop;
-+ bool use_hw_closed_loop;
-+ enum cpr_controller_type ctrl_type;
-+ bool saw_use_unit_mV;
-+ struct cpr3_corner aggr_corner;
-+ bool cpr_enabled;
-+ bool last_corner_was_closed_loop;
-+ bool cpr_suspended;
-+ struct dentry *debugfs;
-+
-+ int aging_ref_volt;
-+ unsigned int aging_vdd_mode;
-+ unsigned int aging_complete_vdd_mode;
-+ int aging_ref_adjust_volt;
-+ bool aging_required;
-+ bool aging_succeeded;
-+ bool aging_failed;
-+ struct cpr3_aging_sensor_info *aging_sensor;
-+ int aging_sensor_count;
-+ u32 cur_sensor_state;
-+ u32 aging_possible_mask;
-+ u32 aging_possible_val;
-+
-+ u32 step_quot_fixed;
-+ u32 initial_temp_band;
-+ bool use_dynamic_step_quot;
-+ bool allow_core_count_adj;
-+ bool allow_temp_adj;
-+ bool allow_boost;
-+ int temp_band_count;
-+ int *temp_points;
-+ u32 temp_sensor_id_start;
-+ u32 temp_sensor_id_end;
-+ u32 voltage_settling_time;
-+ enum cpr_setting cpr_global_setting;
-+ struct cpr3_panic_regs_info *panic_regs_info;
-+ struct notifier_block panic_notifier;
-+};
-+
-+/* Used for rounding voltages to the closest physically available set point. */
-+#define CPR3_ROUND(n, d) (DIV_ROUND_UP(n, d) * (d))
-+
-+#define cpr3_err(cpr3_thread, message, ...) \
-+ pr_err("%s: " message, (cpr3_thread)->name, ##__VA_ARGS__)
-+#define cpr3_info(cpr3_thread, message, ...) \
-+ pr_info("%s: " message, (cpr3_thread)->name, ##__VA_ARGS__)
-+#define cpr3_debug(cpr3_thread, message, ...) \
-+ pr_debug("%s: " message, (cpr3_thread)->name, ##__VA_ARGS__)
-+
-+/*
-+ * Offset subtracted from voltage corner values passed in from the regulator
-+ * framework in order to get internal voltage corner values. This is needed
-+ * since the regulator framework treats 0 as an error value at regulator
-+ * registration time.
-+ */
-+#define CPR3_CORNER_OFFSET 1
-+
-+#ifdef CONFIG_REGULATOR_CPR3
-+
-+int cpr3_regulator_register(struct platform_device *pdev,
-+ struct cpr3_controller *ctrl);
-+int cpr3_open_loop_regulator_register(struct platform_device *pdev,
-+ struct cpr3_controller *ctrl);
-+int cpr3_regulator_unregister(struct cpr3_controller *ctrl);
-+int cpr3_open_loop_regulator_unregister(struct cpr3_controller *ctrl);
-+int cpr3_regulator_suspend(struct cpr3_controller *ctrl);
-+int cpr3_regulator_resume(struct cpr3_controller *ctrl);
-+
-+int cpr3_allocate_threads(struct cpr3_controller *ctrl, u32 min_thread_id,
-+ u32 max_thread_id);
-+int cpr3_map_fuse_base(struct cpr3_controller *ctrl,
-+ struct platform_device *pdev);
-+int cpr3_read_tcsr_setting(struct cpr3_controller *ctrl,
-+ struct platform_device *pdev, u8 start, u8 end);
-+int cpr3_read_fuse_param(void __iomem *fuse_base_addr,
-+ const struct cpr3_fuse_param *param, u64 *param_value);
-+int cpr3_convert_open_loop_voltage_fuse(int ref_volt, int step_volt, u32 fuse,
-+ int fuse_len);
-+u64 cpr3_interpolate(u64 x1, u64 y1, u64 x2, u64 y2, u64 x);
-+int cpr3_parse_array_property(struct cpr3_regulator *vreg,
-+ const char *prop_name, int tuple_size, u32 *out);
-+int cpr3_parse_corner_array_property(struct cpr3_regulator *vreg,
-+ const char *prop_name, int tuple_size, u32 *out);
-+int cpr3_parse_corner_band_array_property(struct cpr3_regulator *vreg,
-+ const char *prop_name, int tuple_size, u32 *out);
-+int cpr3_parse_common_corner_data(struct cpr3_regulator *vreg);
-+int cpr3_parse_thread_u32(struct cpr3_thread *thread, const char *propname,
-+ u32 *out_value, u32 value_min, u32 value_max);
-+int cpr3_parse_ctrl_u32(struct cpr3_controller *ctrl, const char *propname,
-+ u32 *out_value, u32 value_min, u32 value_max);
-+int cpr3_parse_common_thread_data(struct cpr3_thread *thread);
-+int cpr3_parse_common_ctrl_data(struct cpr3_controller *ctrl);
-+int cpr3_parse_open_loop_common_ctrl_data(struct cpr3_controller *ctrl);
-+int cpr3_limit_open_loop_voltages(struct cpr3_regulator *vreg);
-+void cpr3_open_loop_voltage_as_ceiling(struct cpr3_regulator *vreg);
-+int cpr3_limit_floor_voltages(struct cpr3_regulator *vreg);
-+void cpr3_print_quots(struct cpr3_regulator *vreg);
-+int cpr3_determine_part_type(struct cpr3_regulator *vreg, int fuse_volt);
-+int cpr3_determine_temp_base_open_loop_correction(struct cpr3_regulator *vreg,
-+ int *fuse_volt);
-+int cpr3_adjust_fused_open_loop_voltages(struct cpr3_regulator *vreg,
-+ int *fuse_volt);
-+int cpr3_adjust_open_loop_voltages(struct cpr3_regulator *vreg);
-+int cpr3_quot_adjustment(int ro_scale, int volt_adjust);
-+int cpr3_voltage_adjustment(int ro_scale, int quot_adjust);
-+int cpr3_parse_closed_loop_voltage_adjustments(struct cpr3_regulator *vreg,
-+ u64 *ro_sel, int *volt_adjust,
-+ int *volt_adjust_fuse, int *ro_scale);
-+int cpr4_parse_core_count_temp_voltage_adj(struct cpr3_regulator *vreg,
-+ bool use_corner_band);
-+int cpr3_apm_init(struct cpr3_controller *ctrl);
-+int cpr3_mem_acc_init(struct cpr3_regulator *vreg);
-+void cprh_adjust_voltages_for_apm(struct cpr3_regulator *vreg);
-+void cprh_adjust_voltages_for_mem_acc(struct cpr3_regulator *vreg);
-+int cpr3_adjust_target_quotients(struct cpr3_regulator *vreg,
-+ int *fuse_volt_adjust);
-+int cpr3_handle_temp_open_loop_adjustment(struct cpr3_controller *ctrl,
-+ bool is_cold);
-+int cpr3_get_cold_temp_threshold(struct cpr3_regulator *vreg, int *cold_temp);
-+bool cpr3_can_adjust_cold_temp(struct cpr3_regulator *vreg);
-+
-+#else
-+
-+static inline int cpr3_regulator_register(struct platform_device *pdev,
-+ struct cpr3_controller *ctrl)
-+{
-+ return -ENXIO;
-+}
-+
-+static inline int
-+cpr3_open_loop_regulator_register(struct platform_device *pdev,
-+ struct cpr3_controller *ctrl);
-+{
-+ return -ENXIO;
-+}
-+
-+static inline int cpr3_regulator_unregister(struct cpr3_controller *ctrl)
-+{
-+ return -ENXIO;
-+}
-+
-+static inline int
-+cpr3_open_loop_regulator_unregister(struct cpr3_controller *ctrl)
-+{
-+ return -ENXIO;
-+}
-+
-+static inline int cpr3_regulator_suspend(struct cpr3_controller *ctrl)
-+{
-+ return -ENXIO;
-+}
-+
-+static inline int cpr3_regulator_resume(struct cpr3_controller *ctrl)
-+{
-+ return -ENXIO;
-+}
-+
-+static inline int cpr3_get_thread_name(struct cpr3_thread *thread,
-+ struct device_node *thread_node)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_allocate_threads(struct cpr3_controller *ctrl,
-+ u32 min_thread_id, u32 max_thread_id)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_map_fuse_base(struct cpr3_controller *ctrl,
-+ struct platform_device *pdev)
-+{
-+ return -ENXIO;
-+}
-+
-+static inline int cpr3_read_tcsr_setting(struct cpr3_controller *ctrl,
-+ struct platform_device *pdev, u8 start, u8 end)
-+{
-+ return 0;
-+}
-+
-+static inline int cpr3_read_fuse_param(void __iomem *fuse_base_addr,
-+ const struct cpr3_fuse_param *param, u64 *param_value)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_convert_open_loop_voltage_fuse(int ref_volt,
-+ int step_volt, u32 fuse, int fuse_len)
-+{
-+ return -EPERM;
-+}
-+
-+static inline u64 cpr3_interpolate(u64 x1, u64 y1, u64 x2, u64 y2, u64 x)
-+{
-+ return 0;
-+}
-+
-+static inline int cpr3_parse_array_property(struct cpr3_regulator *vreg,
-+ const char *prop_name, int tuple_size, u32 *out)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_parse_corner_array_property(struct cpr3_regulator *vreg,
-+ const char *prop_name, int tuple_size, u32 *out)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_parse_corner_band_array_property(
-+ struct cpr3_regulator *vreg, const char *prop_name,
-+ int tuple_size, u32 *out)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_parse_common_corner_data(struct cpr3_regulator *vreg)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_parse_thread_u32(struct cpr3_thread *thread,
-+ const char *propname, u32 *out_value, u32 value_min,
-+ u32 value_max)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_parse_ctrl_u32(struct cpr3_controller *ctrl,
-+ const char *propname, u32 *out_value, u32 value_min,
-+ u32 value_max)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_parse_common_thread_data(struct cpr3_thread *thread)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_parse_common_ctrl_data(struct cpr3_controller *ctrl)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int
-+cpr3_parse_open_loop_common_ctrl_data(struct cpr3_controller *ctrl)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_limit_open_loop_voltages(struct cpr3_regulator *vreg)
-+{
-+ return -EPERM;
-+}
-+
-+static inline void cpr3_open_loop_voltage_as_ceiling(
-+ struct cpr3_regulator *vreg)
-+{
-+ return;
-+}
-+
-+static inline int cpr3_limit_floor_voltages(struct cpr3_regulator *vreg)
-+{
-+ return -EPERM;
-+}
-+
-+static inline void cpr3_print_quots(struct cpr3_regulator *vreg)
-+{
-+ return;
-+}
-+
-+static inline int
-+cpr3_determine_part_type(struct cpr3_regulator *vreg, int fuse_volt)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int
-+cpr3_determine_temp_base_open_loop_correction(struct cpr3_regulator *vreg,
-+ int *fuse_volt)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_adjust_fused_open_loop_voltages(
-+ struct cpr3_regulator *vreg, int *fuse_volt)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_adjust_open_loop_voltages(struct cpr3_regulator *vreg)
-+{
-+ return -EPERM;
-+}
-+
-+static inline int cpr3_quot_adjustment(int ro_scale, int volt_adjust)
-+{
-+ return 0;
-+}
-+
-+static inline int cpr3_voltage_adjustment(int ro_scale, int quot_adjust)
-+{
-+ return 0;
-+}
-+
-+static inline int cpr3_parse_closed_loop_voltage_adjustments(
-+ struct cpr3_regulator *vreg, u64 *ro_sel,
-+ int *volt_adjust, int *volt_adjust_fuse, int *ro_scale)
-+{
-+ return 0;
-+}
-+
-+static inline int cpr4_parse_core_count_temp_voltage_adj(
-+ struct cpr3_regulator *vreg, bool use_corner_band)
-+{
-+ return 0;
-+}
-+
-+static inline int cpr3_apm_init(struct cpr3_controller *ctrl)
-+{
-+ return 0;
-+}
-+
-+static inline int cpr3_mem_acc_init(struct cpr3_regulator *vreg)
-+{
-+ return 0;
-+}
-+
-+static inline void cprh_adjust_voltages_for_apm(struct cpr3_regulator *vreg)
-+{
-+}
-+
-+static inline void cprh_adjust_voltages_for_mem_acc(struct cpr3_regulator *vreg)
-+{
-+}
-+
-+static inline int cpr3_adjust_target_quotients(struct cpr3_regulator *vreg,
-+ int *fuse_volt_adjust)
-+{
-+ return 0;
-+}
-+
-+static inline int
-+cpr3_handle_temp_open_loop_adjustment(struct cpr3_controller *ctrl,
-+ bool is_cold)
-+{
-+ return 0;
-+}
-+
-+static inline bool
-+cpr3_can_adjust_cold_temp(struct cpr3_regulator *vreg)
-+{
-+ return false;
-+}
-+
-+static inline int
-+cpr3_get_cold_temp_threshold(struct cpr3_regulator *vreg, int *cold_temp)
-+{
-+ return 0;
-+}
-+#endif /* CONFIG_REGULATOR_CPR3 */
-+
-+#endif /* __REGULATOR_CPR_REGULATOR_H__ */
---- /dev/null
-+++ b/drivers/regulator/cpr3-util.c
-@@ -0,0 +1,2750 @@
-+/*
-+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+/*
-+ * This file contains utility functions to be used by platform specific CPR3
-+ * regulator drivers.
-+ */
-+
-+#define pr_fmt(fmt) "%s: " fmt, __func__
-+
-+#include <linux/cpumask.h>
-+#include <linux/device.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/types.h>
-+
-+#include <soc/qcom/socinfo.h>
-+
-+#include "cpr3-regulator.h"
-+
-+#define BYTES_PER_FUSE_ROW 8
-+#define MAX_FUSE_ROW_BIT 63
-+
-+#define CPR3_CONSECUTIVE_UP_DOWN_MIN 0
-+#define CPR3_CONSECUTIVE_UP_DOWN_MAX 15
-+#define CPR3_UP_DOWN_THRESHOLD_MIN 0
-+#define CPR3_UP_DOWN_THRESHOLD_MAX 31
-+#define CPR3_STEP_QUOT_MIN 0
-+#define CPR3_STEP_QUOT_MAX 63
-+#define CPR3_IDLE_CLOCKS_MIN 0
-+#define CPR3_IDLE_CLOCKS_MAX 31
-+
-+/* This constant has units of uV/mV so 1000 corresponds to 100%. */
-+#define CPR3_AGING_DERATE_UNITY 1000
-+
-+/**
-+ * cpr3_allocate_regulators() - allocate and initialize CPR3 regulators for a
-+ * given thread based upon device tree data
-+ * @thread: Pointer to the CPR3 thread
-+ *
-+ * This function allocates the thread->vreg array based upon the number of
-+ * device tree regulator subnodes. It also initializes generic elements of each
-+ * regulator struct such as name, of_node, and thread.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_allocate_regulators(struct cpr3_thread *thread)
-+{
-+ struct device_node *node;
-+ int i, rc;
-+
-+ thread->vreg_count = 0;
-+
-+ for_each_available_child_of_node(thread->of_node, node) {
-+ thread->vreg_count++;
-+ }
-+
-+ thread->vreg = devm_kcalloc(thread->ctrl->dev, thread->vreg_count,
-+ sizeof(*thread->vreg), GFP_KERNEL);
-+ if (!thread->vreg)
-+ return -ENOMEM;
-+
-+ i = 0;
-+ for_each_available_child_of_node(thread->of_node, node) {
-+ thread->vreg[i].of_node = node;
-+ thread->vreg[i].thread = thread;
-+
-+ rc = of_property_read_string(node, "regulator-name",
-+ &thread->vreg[i].name);
-+ if (rc) {
-+ dev_err(thread->ctrl->dev, "could not find regulator name, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ i++;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_allocate_threads() - allocate and initialize CPR3 threads for a given
-+ * controller based upon device tree data
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @min_thread_id: Minimum allowed hardware thread ID for this controller
-+ * @max_thread_id: Maximum allowed hardware thread ID for this controller
-+ *
-+ * This function allocates the ctrl->thread array based upon the number of
-+ * device tree thread subnodes. It also initializes generic elements of each
-+ * thread struct such as thread_id, of_node, ctrl, and vreg array.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_allocate_threads(struct cpr3_controller *ctrl, u32 min_thread_id,
-+ u32 max_thread_id)
-+{
-+ struct device *dev = ctrl->dev;
-+ struct device_node *thread_node;
-+ int i, j, rc;
-+
-+ ctrl->thread_count = 0;
-+
-+ for_each_available_child_of_node(dev->of_node, thread_node) {
-+ ctrl->thread_count++;
-+ }
-+
-+ ctrl->thread = devm_kcalloc(dev, ctrl->thread_count,
-+ sizeof(*ctrl->thread), GFP_KERNEL);
-+ if (!ctrl->thread)
-+ return -ENOMEM;
-+
-+ i = 0;
-+ for_each_available_child_of_node(dev->of_node, thread_node) {
-+ ctrl->thread[i].of_node = thread_node;
-+ ctrl->thread[i].ctrl = ctrl;
-+
-+ rc = of_property_read_u32(thread_node, "qcom,cpr-thread-id",
-+ &ctrl->thread[i].thread_id);
-+ if (rc) {
-+ dev_err(dev, "could not read DT property qcom,cpr-thread-id, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ if (ctrl->thread[i].thread_id < min_thread_id ||
-+ ctrl->thread[i].thread_id > max_thread_id) {
-+ dev_err(dev, "invalid thread id = %u; not within [%u, %u]\n",
-+ ctrl->thread[i].thread_id, min_thread_id,
-+ max_thread_id);
-+ return -EINVAL;
-+ }
-+
-+ /* Verify that the thread ID is unique for all child nodes. */
-+ for (j = 0; j < i; j++) {
-+ if (ctrl->thread[j].thread_id
-+ == ctrl->thread[i].thread_id) {
-+ dev_err(dev, "duplicate thread id = %u found\n",
-+ ctrl->thread[i].thread_id);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ rc = cpr3_allocate_regulators(&ctrl->thread[i]);
-+ if (rc)
-+ return rc;
-+
-+ i++;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_map_fuse_base() - ioremap the base address of the fuse region
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @pdev: Platform device pointer for the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_map_fuse_base(struct cpr3_controller *ctrl,
-+ struct platform_device *pdev)
-+{
-+ struct resource *res;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fuse_base");
-+ if (!res || !res->start) {
-+ dev_err(&pdev->dev, "fuse base address is missing\n");
-+ return -ENXIO;
-+ }
-+
-+ ctrl->fuse_base = devm_ioremap(&pdev->dev, res->start,
-+ resource_size(res));
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_read_tcsr_setting - reads the CPR setting bits from TCSR register
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @pdev: Platform device pointer for the CPR3 controller
-+ * @start: start bit in TCSR register
-+ * @end: end bit in TCSR register
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_read_tcsr_setting(struct cpr3_controller *ctrl,
-+ struct platform_device *pdev, u8 start, u8 end)
-+{
-+ struct resource *res;
-+ void __iomem *tcsr_reg;
-+ u32 val;
-+
-+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-+ "cpr_tcsr_reg");
-+ if (!res || !res->start)
-+ return 0;
-+
-+ tcsr_reg = ioremap(res->start, resource_size(res));
-+ if (!tcsr_reg) {
-+ dev_err(&pdev->dev, "tcsr ioremap failed\n");
-+ return 0;
-+ }
-+
-+ val = readl_relaxed(tcsr_reg);
-+ val &= GENMASK(end, start);
-+ val >>= start;
-+
-+ switch (val) {
-+ case 1:
-+ ctrl->cpr_global_setting = CPR_DISABLED;
-+ break;
-+ case 2:
-+ ctrl->cpr_global_setting = CPR_OPEN_LOOP_EN;
-+ break;
-+ case 3:
-+ ctrl->cpr_global_setting = CPR_CLOSED_LOOP_EN;
-+ break;
-+ default:
-+ ctrl->cpr_global_setting = CPR_DEFAULT;
-+ }
-+
-+ iounmap(tcsr_reg);
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_read_fuse_param() - reads a CPR3 fuse parameter out of eFuses
-+ * @fuse_base_addr: Virtual memory address of the eFuse base address
-+ * @param: Null terminated array of fuse param segments to read
-+ * from
-+ * @param_value: Output with value read from the eFuses
-+ *
-+ * This function reads from each of the parameter segments listed in the param
-+ * array and concatenates their values together. Reading stops when an element
-+ * is reached which has all 0 struct values. The total number of bits specified
-+ * for the fuse parameter across all segments must be less than or equal to 64.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_read_fuse_param(void __iomem *fuse_base_addr,
-+ const struct cpr3_fuse_param *param, u64 *param_value)
-+{
-+ u64 fuse_val, val;
-+ int bits;
-+ int bits_total = 0;
-+
-+ *param_value = 0;
-+
-+ while (param->row || param->bit_start || param->bit_end) {
-+ if (param->bit_start > param->bit_end
-+ || param->bit_end > MAX_FUSE_ROW_BIT) {
-+ pr_err("Invalid fuse parameter segment: row=%u, start=%u, end=%u\n",
-+ param->row, param->bit_start, param->bit_end);
-+ return -EINVAL;
-+ }
-+
-+ bits = param->bit_end - param->bit_start + 1;
-+ if (bits_total + bits > 64) {
-+ pr_err("Invalid fuse parameter segments; total bits = %d\n",
-+ bits_total + bits);
-+ return -EINVAL;
-+ }
-+
-+ fuse_val = readq_relaxed(fuse_base_addr
-+ + param->row * BYTES_PER_FUSE_ROW);
-+ val = (fuse_val >> param->bit_start) & ((1ULL << bits) - 1);
-+ *param_value |= val << bits_total;
-+ bits_total += bits;
-+
-+ param++;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_convert_open_loop_voltage_fuse() - converts an open loop voltage fuse
-+ * value into an absolute voltage with units of microvolts
-+ * @ref_volt: Reference voltage in microvolts
-+ * @step_volt: The step size in microvolts of the fuse LSB
-+ * @fuse: Open loop voltage fuse value
-+ * @fuse_len: The bit length of the fuse value
-+ *
-+ * The MSB of the fuse parameter corresponds to a sign bit. If it is set, then
-+ * the lower bits correspond to the number of steps to go down from the
-+ * reference voltage. If it is not set, then the lower bits correspond to the
-+ * number of steps to go up from the reference voltage.
-+ */
-+int cpr3_convert_open_loop_voltage_fuse(int ref_volt, int step_volt, u32 fuse,
-+ int fuse_len)
-+{
-+ int sign, steps;
-+
-+ sign = (fuse & (1 << (fuse_len - 1))) ? -1 : 1;
-+ steps = fuse & ((1 << (fuse_len - 1)) - 1);
-+
-+ return ref_volt + sign * steps * step_volt;
-+}
-+
-+/**
-+ * cpr3_interpolate() - performs linear interpolation
-+ * @x1 Lower known x value
-+ * @y1 Lower known y value
-+ * @x2 Upper known x value
-+ * @y2 Upper known y value
-+ * @x Intermediate x value
-+ *
-+ * Returns y where (x, y) falls on the line between (x1, y1) and (x2, y2).
-+ * It is required that x1 < x2, y1 <= y2, and x1 <= x <= x2. If these
-+ * conditions are not met, then y2 will be returned.
-+ */
-+u64 cpr3_interpolate(u64 x1, u64 y1, u64 x2, u64 y2, u64 x)
-+{
-+ u64 temp;
-+
-+ if (x1 >= x2 || y1 > y2 || x1 > x || x > x2)
-+ return y2;
-+
-+ temp = (x2 - x) * (y2 - y1);
-+ do_div(temp, (u32)(x2 - x1));
-+
-+ return y2 - temp;
-+}
-+
-+/**
-+ * cpr3_parse_array_property() - fill an array from a portion of the values
-+ * specified for a device tree property
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @prop_name: The name of the device tree property to read from
-+ * @tuple_size: The number of elements in each tuple
-+ * @out: Output data array which must be of size tuple_size
-+ *
-+ * cpr3_parse_common_corner_data() must be called for vreg before this function
-+ * is called so that fuse combo and speed bin size elements are initialized.
-+ *
-+ * Three formats are supported for the device tree property:
-+ * 1. Length == tuple_size
-+ * (reading begins at index 0)
-+ * 2. Length == tuple_size * vreg->fuse_combos_supported
-+ * (reading begins at index tuple_size * vreg->fuse_combo)
-+ * 3. Length == tuple_size * vreg->speed_bins_supported
-+ * (reading begins at index tuple_size * vreg->speed_bin_fuse)
-+ *
-+ * All other property lengths are treated as errors.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_parse_array_property(struct cpr3_regulator *vreg,
-+ const char *prop_name, int tuple_size, u32 *out)
-+{
-+ struct device_node *node = vreg->of_node;
-+ int len = 0;
-+ int i, offset, rc;
-+
-+ if (!of_find_property(node, prop_name, &len)) {
-+ cpr3_err(vreg, "property %s is missing\n", prop_name);
-+ return -EINVAL;
-+ }
-+
-+ if (len == tuple_size * sizeof(u32)) {
-+ offset = 0;
-+ } else if (len == tuple_size * vreg->fuse_combos_supported
-+ * sizeof(u32)) {
-+ offset = tuple_size * vreg->fuse_combo;
-+ } else if (vreg->speed_bins_supported > 0 &&
-+ len == tuple_size * vreg->speed_bins_supported * sizeof(u32)) {
-+ offset = tuple_size * vreg->speed_bin_fuse;
-+ } else {
-+ if (vreg->speed_bins_supported > 0)
-+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu, %zu, or %zu\n",
-+ prop_name, len,
-+ tuple_size * sizeof(u32),
-+ tuple_size * vreg->speed_bins_supported
-+ * sizeof(u32),
-+ tuple_size * vreg->fuse_combos_supported
-+ * sizeof(u32));
-+ else
-+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n",
-+ prop_name, len,
-+ tuple_size * sizeof(u32),
-+ tuple_size * vreg->fuse_combos_supported
-+ * sizeof(u32));
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < tuple_size; i++) {
-+ rc = of_property_read_u32_index(node, prop_name, offset + i,
-+ &out[i]);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading property %s, rc=%d\n",
-+ prop_name, rc);
-+ return rc;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_parse_corner_array_property() - fill a per-corner array from a portion
-+ * of the values specified for a device tree property
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @prop_name: The name of the device tree property to read from
-+ * @tuple_size: The number of elements in each per-corner tuple
-+ * @out: Output data array which must be of size:
-+ * tuple_size * vreg->corner_count
-+ *
-+ * cpr3_parse_common_corner_data() must be called for vreg before this function
-+ * is called so that fuse combo and speed bin size elements are initialized.
-+ *
-+ * Three formats are supported for the device tree property:
-+ * 1. Length == tuple_size * vreg->corner_count
-+ * (reading begins at index 0)
-+ * 2. Length == tuple_size * vreg->fuse_combo_corner_sum
-+ * (reading begins at index tuple_size * vreg->fuse_combo_offset)
-+ * 3. Length == tuple_size * vreg->speed_bin_corner_sum
-+ * (reading begins at index tuple_size * vreg->speed_bin_offset)
-+ *
-+ * All other property lengths are treated as errors.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_parse_corner_array_property(struct cpr3_regulator *vreg,
-+ const char *prop_name, int tuple_size, u32 *out)
-+{
-+ struct device_node *node = vreg->of_node;
-+ int len = 0;
-+ int i, offset, rc;
-+
-+ if (!of_find_property(node, prop_name, &len)) {
-+ cpr3_err(vreg, "property %s is missing\n", prop_name);
-+ return -EINVAL;
-+ }
-+
-+ if (len == tuple_size * vreg->corner_count * sizeof(u32)) {
-+ offset = 0;
-+ } else if (len == tuple_size * vreg->fuse_combo_corner_sum
-+ * sizeof(u32)) {
-+ offset = tuple_size * vreg->fuse_combo_offset;
-+ } else if (vreg->speed_bin_corner_sum > 0 &&
-+ len == tuple_size * vreg->speed_bin_corner_sum * sizeof(u32)) {
-+ offset = tuple_size * vreg->speed_bin_offset;
-+ } else {
-+ if (vreg->speed_bin_corner_sum > 0)
-+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu, %zu, or %zu\n",
-+ prop_name, len,
-+ tuple_size * vreg->corner_count * sizeof(u32),
-+ tuple_size * vreg->speed_bin_corner_sum
-+ * sizeof(u32),
-+ tuple_size * vreg->fuse_combo_corner_sum
-+ * sizeof(u32));
-+ else
-+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n",
-+ prop_name, len,
-+ tuple_size * vreg->corner_count * sizeof(u32),
-+ tuple_size * vreg->fuse_combo_corner_sum
-+ * sizeof(u32));
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < tuple_size * vreg->corner_count; i++) {
-+ rc = of_property_read_u32_index(node, prop_name, offset + i,
-+ &out[i]);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading property %s, rc=%d\n",
-+ prop_name, rc);
-+ return rc;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_parse_corner_band_array_property() - fill a per-corner band array
-+ * from a portion of the values specified for a device tree
-+ * property
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @prop_name: The name of the device tree property to read from
-+ * @tuple_size: The number of elements in each per-corner band tuple
-+ * @out: Output data array which must be of size:
-+ * tuple_size * vreg->corner_band_count
-+ *
-+ * cpr3_parse_common_corner_data() must be called for vreg before this function
-+ * is called so that fuse combo and speed bin size elements are initialized.
-+ * In addition, corner band fuse combo and speed bin sum and offset elements
-+ * must be initialized prior to executing this function.
-+ *
-+ * Three formats are supported for the device tree property:
-+ * 1. Length == tuple_size * vreg->corner_band_count
-+ * (reading begins at index 0)
-+ * 2. Length == tuple_size * vreg->fuse_combo_corner_band_sum
-+ * (reading begins at index tuple_size *
-+ * vreg->fuse_combo_corner_band_offset)
-+ * 3. Length == tuple_size * vreg->speed_bin_corner_band_sum
-+ * (reading begins at index tuple_size *
-+ * vreg->speed_bin_corner_band_offset)
-+ *
-+ * All other property lengths are treated as errors.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_parse_corner_band_array_property(struct cpr3_regulator *vreg,
-+ const char *prop_name, int tuple_size, u32 *out)
-+{
-+ struct device_node *node = vreg->of_node;
-+ int len = 0;
-+ int i, offset, rc;
-+
-+ if (!of_find_property(node, prop_name, &len)) {
-+ cpr3_err(vreg, "property %s is missing\n", prop_name);
-+ return -EINVAL;
-+ }
-+
-+ if (len == tuple_size * vreg->corner_band_count * sizeof(u32)) {
-+ offset = 0;
-+ } else if (len == tuple_size * vreg->fuse_combo_corner_band_sum
-+ * sizeof(u32)) {
-+ offset = tuple_size * vreg->fuse_combo_corner_band_offset;
-+ } else if (vreg->speed_bin_corner_band_sum > 0 &&
-+ len == tuple_size * vreg->speed_bin_corner_band_sum *
-+ sizeof(u32)) {
-+ offset = tuple_size * vreg->speed_bin_corner_band_offset;
-+ } else {
-+ if (vreg->speed_bin_corner_band_sum > 0)
-+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu, %zu, or %zu\n",
-+ prop_name, len,
-+ tuple_size * vreg->corner_band_count *
-+ sizeof(u32),
-+ tuple_size * vreg->speed_bin_corner_band_sum
-+ * sizeof(u32),
-+ tuple_size * vreg->fuse_combo_corner_band_sum
-+ * sizeof(u32));
-+ else
-+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n",
-+ prop_name, len,
-+ tuple_size * vreg->corner_band_count *
-+ sizeof(u32),
-+ tuple_size * vreg->fuse_combo_corner_band_sum
-+ * sizeof(u32));
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < tuple_size * vreg->corner_band_count; i++) {
-+ rc = of_property_read_u32_index(node, prop_name, offset + i,
-+ &out[i]);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading property %s, rc=%d\n",
-+ prop_name, rc);
-+ return rc;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_parse_common_corner_data() - parse common CPR3 properties relating to
-+ * the corners supported by a CPR3 regulator from device tree
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * This function reads, validates, and utilizes the following device tree
-+ * properties: qcom,cpr-fuse-corners, qcom,cpr-fuse-combos, qcom,cpr-speed-bins,
-+ * qcom,cpr-speed-bin-corners, qcom,cpr-corners, qcom,cpr-voltage-ceiling,
-+ * qcom,cpr-voltage-floor, qcom,corner-frequencies,
-+ * and qcom,cpr-corner-fmax-map.
-+ *
-+ * It initializes these CPR3 regulator elements: corner, corner_count,
-+ * fuse_combos_supported, fuse_corner_map, and speed_bins_supported. It
-+ * initializes these elements for each corner: ceiling_volt, floor_volt,
-+ * proc_freq, and cpr_fuse_corner.
-+ *
-+ * It requires that the following CPR3 regulator elements be initialized before
-+ * being called: fuse_corner_count, fuse_combo, and speed_bin_fuse.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_parse_common_corner_data(struct cpr3_regulator *vreg)
-+{
-+ struct device_node *node = vreg->of_node;
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ u32 max_fuse_combos, fuse_corners, aging_allowed = 0;
-+ u32 max_speed_bins = 0;
-+ u32 *combo_corners;
-+ u32 *speed_bin_corners;
-+ u32 *temp;
-+ int i, j, rc;
-+
-+ rc = of_property_read_u32(node, "qcom,cpr-fuse-corners", &fuse_corners);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading property qcom,cpr-fuse-corners, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ if (vreg->fuse_corner_count != fuse_corners) {
-+ cpr3_err(vreg, "device tree config supports %d fuse corners but the hardware has %d fuse corners\n",
-+ fuse_corners, vreg->fuse_corner_count);
-+ return -EINVAL;
-+ }
-+
-+ rc = of_property_read_u32(node, "qcom,cpr-fuse-combos",
-+ &max_fuse_combos);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading property qcom,cpr-fuse-combos, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ /*
-+ * Sanity check against arbitrarily large value to avoid excessive
-+ * memory allocation.
-+ */
-+ if (max_fuse_combos > 100 || max_fuse_combos == 0) {
-+ cpr3_err(vreg, "qcom,cpr-fuse-combos is invalid: %u\n",
-+ max_fuse_combos);
-+ return -EINVAL;
-+ }
-+
-+ if (vreg->fuse_combo >= max_fuse_combos) {
-+ cpr3_err(vreg, "device tree config supports fuse combos 0-%u but the hardware has combo %d\n",
-+ max_fuse_combos - 1, vreg->fuse_combo);
-+ BUG_ON(1);
-+ return -EINVAL;
-+ }
-+
-+ vreg->fuse_combos_supported = max_fuse_combos;
-+
-+ of_property_read_u32(node, "qcom,cpr-speed-bins", &max_speed_bins);
-+
-+ /*
-+ * Sanity check against arbitrarily large value to avoid excessive
-+ * memory allocation.
-+ */
-+ if (max_speed_bins > 100) {
-+ cpr3_err(vreg, "qcom,cpr-speed-bins is invalid: %u\n",
-+ max_speed_bins);
-+ return -EINVAL;
-+ }
-+
-+ if (max_speed_bins && vreg->speed_bin_fuse >= max_speed_bins) {
-+ cpr3_err(vreg, "device tree config supports speed bins 0-%u but the hardware has speed bin %d\n",
-+ max_speed_bins - 1, vreg->speed_bin_fuse);
-+ BUG();
-+ return -EINVAL;
-+ }
-+
-+ vreg->speed_bins_supported = max_speed_bins;
-+
-+ combo_corners = kcalloc(vreg->fuse_combos_supported,
-+ sizeof(*combo_corners), GFP_KERNEL);
-+ if (!combo_corners)
-+ return -ENOMEM;
-+
-+ rc = of_property_read_u32_array(node, "qcom,cpr-corners", combo_corners,
-+ vreg->fuse_combos_supported);
-+ if (rc == -EOVERFLOW) {
-+ /* Single value case */
-+ rc = of_property_read_u32(node, "qcom,cpr-corners",
-+ combo_corners);
-+ for (i = 1; i < vreg->fuse_combos_supported; i++)
-+ combo_corners[i] = combo_corners[0];
-+ }
-+ if (rc) {
-+ cpr3_err(vreg, "error reading property qcom,cpr-corners, rc=%d\n",
-+ rc);
-+ kfree(combo_corners);
-+ return rc;
-+ }
-+
-+ vreg->fuse_combo_offset = 0;
-+ vreg->fuse_combo_corner_sum = 0;
-+ for (i = 0; i < vreg->fuse_combos_supported; i++) {
-+ vreg->fuse_combo_corner_sum += combo_corners[i];
-+ if (i < vreg->fuse_combo)
-+ vreg->fuse_combo_offset += combo_corners[i];
-+ }
-+
-+ vreg->corner_count = combo_corners[vreg->fuse_combo];
-+
-+ kfree(combo_corners);
-+
-+ vreg->speed_bin_offset = 0;
-+ vreg->speed_bin_corner_sum = 0;
-+ if (vreg->speed_bins_supported > 0) {
-+ speed_bin_corners = kcalloc(vreg->speed_bins_supported,
-+ sizeof(*speed_bin_corners), GFP_KERNEL);
-+ if (!speed_bin_corners)
-+ return -ENOMEM;
-+
-+ rc = of_property_read_u32_array(node,
-+ "qcom,cpr-speed-bin-corners", speed_bin_corners,
-+ vreg->speed_bins_supported);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading property qcom,cpr-speed-bin-corners, rc=%d\n",
-+ rc);
-+ kfree(speed_bin_corners);
-+ return rc;
-+ }
-+
-+ for (i = 0; i < vreg->speed_bins_supported; i++) {
-+ vreg->speed_bin_corner_sum += speed_bin_corners[i];
-+ if (i < vreg->speed_bin_fuse)
-+ vreg->speed_bin_offset += speed_bin_corners[i];
-+ }
-+
-+ if (speed_bin_corners[vreg->speed_bin_fuse]
-+ != vreg->corner_count) {
-+ cpr3_err(vreg, "qcom,cpr-corners and qcom,cpr-speed-bin-corners conflict on number of corners: %d vs %u\n",
-+ vreg->corner_count,
-+ speed_bin_corners[vreg->speed_bin_fuse]);
-+ kfree(speed_bin_corners);
-+ return -EINVAL;
-+ }
-+
-+ kfree(speed_bin_corners);
-+ }
-+
-+ vreg->corner = devm_kcalloc(ctrl->dev, vreg->corner_count,
-+ sizeof(*vreg->corner), GFP_KERNEL);
-+ temp = kcalloc(vreg->corner_count, sizeof(*temp), GFP_KERNEL);
-+ if (!vreg->corner || !temp)
-+ return -ENOMEM;
-+
-+ rc = cpr3_parse_corner_array_property(vreg, "qcom,cpr-voltage-ceiling",
-+ 1, temp);
-+ if (rc)
-+ goto free_temp;
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ vreg->corner[i].ceiling_volt
-+ = CPR3_ROUND(temp[i], ctrl->step_volt);
-+ vreg->corner[i].abs_ceiling_volt = vreg->corner[i].ceiling_volt;
-+ }
-+
-+ rc = cpr3_parse_corner_array_property(vreg, "qcom,cpr-voltage-floor",
-+ 1, temp);
-+ if (rc)
-+ goto free_temp;
-+ for (i = 0; i < vreg->corner_count; i++)
-+ vreg->corner[i].floor_volt
-+ = CPR3_ROUND(temp[i], ctrl->step_volt);
-+
-+ /* Validate ceiling and floor values */
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ if (vreg->corner[i].floor_volt
-+ > vreg->corner[i].ceiling_volt) {
-+ cpr3_err(vreg, "CPR floor[%d]=%d > ceiling[%d]=%d uV\n",
-+ i, vreg->corner[i].floor_volt,
-+ i, vreg->corner[i].ceiling_volt);
-+ rc = -EINVAL;
-+ goto free_temp;
-+ }
-+ }
-+
-+ /* Load optional system-supply voltages */
-+ if (of_find_property(vreg->of_node, "qcom,system-voltage", NULL)) {
-+ rc = cpr3_parse_corner_array_property(vreg,
-+ "qcom,system-voltage", 1, temp);
-+ if (rc)
-+ goto free_temp;
-+ for (i = 0; i < vreg->corner_count; i++)
-+ vreg->corner[i].system_volt = temp[i];
-+ }
-+
-+ rc = cpr3_parse_corner_array_property(vreg, "qcom,corner-frequencies",
-+ 1, temp);
-+ if (rc)
-+ goto free_temp;
-+ for (i = 0; i < vreg->corner_count; i++)
-+ vreg->corner[i].proc_freq = temp[i];
-+
-+ /* Validate frequencies */
-+ for (i = 1; i < vreg->corner_count; i++) {
-+ if (vreg->corner[i].proc_freq
-+ < vreg->corner[i - 1].proc_freq) {
-+ cpr3_err(vreg, "invalid frequency: freq[%d]=%u < freq[%d]=%u\n",
-+ i, vreg->corner[i].proc_freq, i - 1,
-+ vreg->corner[i - 1].proc_freq);
-+ rc = -EINVAL;
-+ goto free_temp;
-+ }
-+ }
-+
-+ vreg->fuse_corner_map = devm_kcalloc(ctrl->dev, vreg->fuse_corner_count,
-+ sizeof(*vreg->fuse_corner_map), GFP_KERNEL);
-+ if (!vreg->fuse_corner_map) {
-+ rc = -ENOMEM;
-+ goto free_temp;
-+ }
-+
-+ rc = cpr3_parse_array_property(vreg, "qcom,cpr-corner-fmax-map",
-+ vreg->fuse_corner_count, temp);
-+ if (rc)
-+ goto free_temp;
-+ for (i = 0; i < vreg->fuse_corner_count; i++) {
-+ vreg->fuse_corner_map[i] = temp[i] - CPR3_CORNER_OFFSET;
-+ if (temp[i] < CPR3_CORNER_OFFSET
-+ || temp[i] > vreg->corner_count + CPR3_CORNER_OFFSET) {
-+ cpr3_err(vreg, "invalid corner value specified in qcom,cpr-corner-fmax-map: %u\n",
-+ temp[i]);
-+ rc = -EINVAL;
-+ goto free_temp;
-+ } else if (i > 0 && temp[i - 1] >= temp[i]) {
-+ cpr3_err(vreg, "invalid corner %u less than or equal to previous corner %u\n",
-+ temp[i], temp[i - 1]);
-+ rc = -EINVAL;
-+ goto free_temp;
-+ }
-+ }
-+ if (temp[vreg->fuse_corner_count - 1] != vreg->corner_count)
-+ cpr3_debug(vreg, "Note: highest Fmax corner %u in qcom,cpr-corner-fmax-map does not match highest supported corner %d\n",
-+ temp[vreg->fuse_corner_count - 1],
-+ vreg->corner_count);
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ for (j = 0; j < vreg->fuse_corner_count; j++) {
-+ if (i + CPR3_CORNER_OFFSET <= temp[j]) {
-+ vreg->corner[i].cpr_fuse_corner = j;
-+ break;
-+ }
-+ }
-+ if (j == vreg->fuse_corner_count) {
-+ /*
-+ * Handle the case where the highest fuse corner maps
-+ * to a corner below the highest corner.
-+ */
-+ vreg->corner[i].cpr_fuse_corner
-+ = vreg->fuse_corner_count - 1;
-+ }
-+ }
-+
-+ if (of_find_property(vreg->of_node,
-+ "qcom,allow-aging-voltage-adjustment", NULL)) {
-+ rc = cpr3_parse_array_property(vreg,
-+ "qcom,allow-aging-voltage-adjustment",
-+ 1, &aging_allowed);
-+ if (rc)
-+ goto free_temp;
-+
-+ vreg->aging_allowed = aging_allowed;
-+ }
-+
-+ if (of_find_property(vreg->of_node,
-+ "qcom,allow-aging-open-loop-voltage-adjustment", NULL)) {
-+ rc = cpr3_parse_array_property(vreg,
-+ "qcom,allow-aging-open-loop-voltage-adjustment",
-+ 1, &aging_allowed);
-+ if (rc)
-+ goto free_temp;
-+
-+ vreg->aging_allow_open_loop_adj = aging_allowed;
-+ }
-+
-+ if (vreg->aging_allowed) {
-+ if (ctrl->aging_ref_volt <= 0) {
-+ cpr3_err(ctrl, "qcom,cpr-aging-ref-voltage must be specified\n");
-+ rc = -EINVAL;
-+ goto free_temp;
-+ }
-+
-+ rc = cpr3_parse_array_property(vreg,
-+ "qcom,cpr-aging-max-voltage-adjustment",
-+ 1, &vreg->aging_max_adjust_volt);
-+ if (rc)
-+ goto free_temp;
-+
-+ rc = cpr3_parse_array_property(vreg,
-+ "qcom,cpr-aging-ref-corner", 1, &vreg->aging_corner);
-+ if (rc) {
-+ goto free_temp;
-+ } else if (vreg->aging_corner < CPR3_CORNER_OFFSET
-+ || vreg->aging_corner > vreg->corner_count - 1
-+ + CPR3_CORNER_OFFSET) {
-+ cpr3_err(vreg, "aging reference corner=%d not in range [%d, %d]\n",
-+ vreg->aging_corner, CPR3_CORNER_OFFSET,
-+ vreg->corner_count - 1 + CPR3_CORNER_OFFSET);
-+ rc = -EINVAL;
-+ goto free_temp;
-+ }
-+ vreg->aging_corner -= CPR3_CORNER_OFFSET;
-+
-+ if (of_find_property(vreg->of_node, "qcom,cpr-aging-derate",
-+ NULL)) {
-+ rc = cpr3_parse_corner_array_property(vreg,
-+ "qcom,cpr-aging-derate", 1, temp);
-+ if (rc)
-+ goto free_temp;
-+
-+ for (i = 0; i < vreg->corner_count; i++)
-+ vreg->corner[i].aging_derate = temp[i];
-+ } else {
-+ for (i = 0; i < vreg->corner_count; i++)
-+ vreg->corner[i].aging_derate
-+ = CPR3_AGING_DERATE_UNITY;
-+ }
-+ }
-+
-+free_temp:
-+ kfree(temp);
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_parse_thread_u32() - parse the specified property from the CPR3 thread's
-+ * device tree node and verify that it is within the allowed limits
-+ * @thread: Pointer to the CPR3 thread
-+ * @propname: The name of the device tree property to read
-+ * @out_value: The output pointer to fill with the value read
-+ * @value_min: The minimum allowed property value
-+ * @value_max: The maximum allowed property value
-+ *
-+ * This function prints a verbose error message if the property is missing or
-+ * has a value which is not within the specified range.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_parse_thread_u32(struct cpr3_thread *thread, const char *propname,
-+ u32 *out_value, u32 value_min, u32 value_max)
-+{
-+ int rc;
-+
-+ rc = of_property_read_u32(thread->of_node, propname, out_value);
-+ if (rc) {
-+ cpr3_err(thread->ctrl, "thread %u error reading property %s, rc=%d\n",
-+ thread->thread_id, propname, rc);
-+ return rc;
-+ }
-+
-+ if (*out_value < value_min || *out_value > value_max) {
-+ cpr3_err(thread->ctrl, "thread %u %s=%u is invalid; allowed range: [%u, %u]\n",
-+ thread->thread_id, propname, *out_value, value_min,
-+ value_max);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_parse_ctrl_u32() - parse the specified property from the CPR3
-+ * controller's device tree node and verify that it is within the
-+ * allowed limits
-+ * @ctrl: Pointer to the CPR3 controller
-+ * @propname: The name of the device tree property to read
-+ * @out_value: The output pointer to fill with the value read
-+ * @value_min: The minimum allowed property value
-+ * @value_max: The maximum allowed property value
-+ *
-+ * This function prints a verbose error message if the property is missing or
-+ * has a value which is not within the specified range.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_parse_ctrl_u32(struct cpr3_controller *ctrl, const char *propname,
-+ u32 *out_value, u32 value_min, u32 value_max)
-+{
-+ int rc;
-+
-+ rc = of_property_read_u32(ctrl->dev->of_node, propname, out_value);
-+ if (rc) {
-+ cpr3_err(ctrl, "error reading property %s, rc=%d\n",
-+ propname, rc);
-+ return rc;
-+ }
-+
-+ if (*out_value < value_min || *out_value > value_max) {
-+ cpr3_err(ctrl, "%s=%u is invalid; allowed range: [%u, %u]\n",
-+ propname, *out_value, value_min, value_max);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_parse_common_thread_data() - parse common CPR3 thread properties from
-+ * device tree
-+ * @thread: Pointer to the CPR3 thread
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_parse_common_thread_data(struct cpr3_thread *thread)
-+{
-+ int rc;
-+
-+ rc = cpr3_parse_thread_u32(thread, "qcom,cpr-consecutive-up",
-+ &thread->consecutive_up, CPR3_CONSECUTIVE_UP_DOWN_MIN,
-+ CPR3_CONSECUTIVE_UP_DOWN_MAX);
-+ if (rc)
-+ return rc;
-+
-+ rc = cpr3_parse_thread_u32(thread, "qcom,cpr-consecutive-down",
-+ &thread->consecutive_down, CPR3_CONSECUTIVE_UP_DOWN_MIN,
-+ CPR3_CONSECUTIVE_UP_DOWN_MAX);
-+ if (rc)
-+ return rc;
-+
-+ rc = cpr3_parse_thread_u32(thread, "qcom,cpr-up-threshold",
-+ &thread->up_threshold, CPR3_UP_DOWN_THRESHOLD_MIN,
-+ CPR3_UP_DOWN_THRESHOLD_MAX);
-+ if (rc)
-+ return rc;
-+
-+ rc = cpr3_parse_thread_u32(thread, "qcom,cpr-down-threshold",
-+ &thread->down_threshold, CPR3_UP_DOWN_THRESHOLD_MIN,
-+ CPR3_UP_DOWN_THRESHOLD_MAX);
-+ if (rc)
-+ return rc;
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_parse_irq_affinity() - parse CPR IRQ affinity information
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_parse_irq_affinity(struct cpr3_controller *ctrl)
-+{
-+ struct device_node *cpu_node;
-+ int i, cpu;
-+ int len = 0;
-+
-+ if (!of_find_property(ctrl->dev->of_node, "qcom,cpr-interrupt-affinity",
-+ &len)) {
-+ /* No IRQ affinity required */
-+ return 0;
-+ }
-+
-+ len /= sizeof(u32);
-+
-+ for (i = 0; i < len; i++) {
-+ cpu_node = of_parse_phandle(ctrl->dev->of_node,
-+ "qcom,cpr-interrupt-affinity", i);
-+ if (!cpu_node) {
-+ cpr3_err(ctrl, "could not find CPU node %d\n", i);
-+ return -EINVAL;
-+ }
-+
-+ for_each_possible_cpu(cpu) {
-+ if (of_get_cpu_node(cpu, NULL) == cpu_node) {
-+ cpumask_set_cpu(cpu, &ctrl->irq_affinity_mask);
-+ break;
-+ }
-+ }
-+ of_node_put(cpu_node);
-+ }
-+
-+ return 0;
-+}
-+
-+static int cpr3_panic_notifier_init(struct cpr3_controller *ctrl)
-+{
-+ struct device_node *node = ctrl->dev->of_node;
-+ struct cpr3_panic_regs_info *panic_regs_info;
-+ struct cpr3_reg_info *regs;
-+ int i, reg_count, len, rc = 0;
-+
-+ if (!of_find_property(node, "qcom,cpr-panic-reg-addr-list", &len)) {
-+ /* panic register address list not specified */
-+ return rc;
-+ }
-+
-+ reg_count = len / sizeof(u32);
-+ if (!reg_count) {
-+ cpr3_err(ctrl, "qcom,cpr-panic-reg-addr-list has invalid len = %d\n",
-+ len);
-+ return -EINVAL;
-+ }
-+
-+ if (!of_find_property(node, "qcom,cpr-panic-reg-name-list", NULL)) {
-+ cpr3_err(ctrl, "property qcom,cpr-panic-reg-name-list not specified\n");
-+ return -EINVAL;
-+ }
-+
-+ len = of_property_count_strings(node, "qcom,cpr-panic-reg-name-list");
-+ if (reg_count != len) {
-+ cpr3_err(ctrl, "qcom,cpr-panic-reg-name-list should have %d strings\n",
-+ reg_count);
-+ return -EINVAL;
-+ }
-+
-+ panic_regs_info = devm_kzalloc(ctrl->dev, sizeof(*panic_regs_info),
-+ GFP_KERNEL);
-+ if (!panic_regs_info)
-+ return -ENOMEM;
-+
-+ regs = devm_kcalloc(ctrl->dev, reg_count, sizeof(*regs), GFP_KERNEL);
-+ if (!regs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < reg_count; i++) {
-+ rc = of_property_read_string_index(node,
-+ "qcom,cpr-panic-reg-name-list", i,
-+ &(regs[i].name));
-+ if (rc) {
-+ cpr3_err(ctrl, "error reading property qcom,cpr-panic-reg-name-list, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = of_property_read_u32_index(node,
-+ "qcom,cpr-panic-reg-addr-list", i,
-+ &(regs[i].addr));
-+ if (rc) {
-+ cpr3_err(ctrl, "error reading property qcom,cpr-panic-reg-addr-list, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ regs[i].virt_addr = devm_ioremap(ctrl->dev, regs[i].addr, 0x4);
-+ if (!regs[i].virt_addr) {
-+ pr_err("Unable to map panic register addr 0x%08x\n",
-+ regs[i].addr);
-+ return -EINVAL;
-+ }
-+ regs[i].value = 0xFFFFFFFF;
-+ }
-+
-+ panic_regs_info->reg_count = reg_count;
-+ panic_regs_info->regs = regs;
-+ ctrl->panic_regs_info = panic_regs_info;
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_parse_common_ctrl_data() - parse common CPR3 controller properties from
-+ * device tree
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_parse_common_ctrl_data(struct cpr3_controller *ctrl)
-+{
-+ int rc;
-+
-+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-sensor-time",
-+ &ctrl->sensor_time, 0, UINT_MAX);
-+ if (rc)
-+ return rc;
-+
-+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-loop-time",
-+ &ctrl->loop_time, 0, UINT_MAX);
-+ if (rc)
-+ return rc;
-+
-+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-idle-cycles",
-+ &ctrl->idle_clocks, CPR3_IDLE_CLOCKS_MIN,
-+ CPR3_IDLE_CLOCKS_MAX);
-+ if (rc)
-+ return rc;
-+
-+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-step-quot-init-min",
-+ &ctrl->step_quot_init_min, CPR3_STEP_QUOT_MIN,
-+ CPR3_STEP_QUOT_MAX);
-+ if (rc)
-+ return rc;
-+
-+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-step-quot-init-max",
-+ &ctrl->step_quot_init_max, CPR3_STEP_QUOT_MIN,
-+ CPR3_STEP_QUOT_MAX);
-+ if (rc)
-+ return rc;
-+
-+ rc = of_property_read_u32(ctrl->dev->of_node, "qcom,voltage-step",
-+ &ctrl->step_volt);
-+ if (rc) {
-+ cpr3_err(ctrl, "error reading property qcom,voltage-step, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ if (ctrl->step_volt <= 0) {
-+ cpr3_err(ctrl, "qcom,voltage-step=%d is invalid\n",
-+ ctrl->step_volt);
-+ return -EINVAL;
-+ }
-+
-+ rc = cpr3_parse_ctrl_u32(ctrl, "qcom,cpr-count-mode",
-+ &ctrl->count_mode, CPR3_COUNT_MODE_ALL_AT_ONCE_MIN,
-+ CPR3_COUNT_MODE_STAGGERED);
-+ if (rc)
-+ return rc;
-+
-+ /* Count repeat is optional */
-+ ctrl->count_repeat = 0;
-+ of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-count-repeat",
-+ &ctrl->count_repeat);
-+
-+ ctrl->cpr_allowed_sw =
-+ of_property_read_bool(ctrl->dev->of_node, "qcom,cpr-enable") ||
-+ ctrl->cpr_global_setting == CPR_CLOSED_LOOP_EN;
-+
-+ rc = cpr3_parse_irq_affinity(ctrl);
-+ if (rc)
-+ return rc;
-+
-+ /* Aging reference voltage is optional */
-+ ctrl->aging_ref_volt = 0;
-+ of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-aging-ref-voltage",
-+ &ctrl->aging_ref_volt);
-+
-+ /* Aging possible bitmask is optional */
-+ ctrl->aging_possible_mask = 0;
-+ of_property_read_u32(ctrl->dev->of_node,
-+ "qcom,cpr-aging-allowed-reg-mask",
-+ &ctrl->aging_possible_mask);
-+
-+ if (ctrl->aging_possible_mask) {
-+ /*
-+ * Aging possible register value required if bitmask is
-+ * specified
-+ */
-+ rc = cpr3_parse_ctrl_u32(ctrl,
-+ "qcom,cpr-aging-allowed-reg-value",
-+ &ctrl->aging_possible_val, 0, UINT_MAX);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ if (of_find_property(ctrl->dev->of_node, "clock-names", NULL)) {
-+ ctrl->core_clk = devm_clk_get(ctrl->dev, "core_clk");
-+ if (IS_ERR(ctrl->core_clk)) {
-+ rc = PTR_ERR(ctrl->core_clk);
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(ctrl, "unable request core clock, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ }
-+
-+ rc = cpr3_panic_notifier_init(ctrl);
-+ if (rc)
-+ return rc;
-+
-+ if (of_find_property(ctrl->dev->of_node, "vdd-supply", NULL)) {
-+ ctrl->vdd_regulator = devm_regulator_get(ctrl->dev, "vdd");
-+ if (IS_ERR(ctrl->vdd_regulator)) {
-+ rc = PTR_ERR(ctrl->vdd_regulator);
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(ctrl, "unable to request vdd regulator, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ } else {
-+ cpr3_err(ctrl, "vdd supply is not defined\n");
-+ return -ENODEV;
-+ }
-+
-+ ctrl->system_regulator = devm_regulator_get_optional(ctrl->dev,
-+ "system");
-+ if (IS_ERR(ctrl->system_regulator)) {
-+ rc = PTR_ERR(ctrl->system_regulator);
-+ if (rc != -EPROBE_DEFER) {
-+ rc = 0;
-+ ctrl->system_regulator = NULL;
-+ } else {
-+ return rc;
-+ }
-+ }
-+
-+ ctrl->mem_acc_regulator = devm_regulator_get_optional(ctrl->dev,
-+ "mem-acc");
-+ if (IS_ERR(ctrl->mem_acc_regulator)) {
-+ rc = PTR_ERR(ctrl->mem_acc_regulator);
-+ if (rc != -EPROBE_DEFER) {
-+ rc = 0;
-+ ctrl->mem_acc_regulator = NULL;
-+ } else {
-+ return rc;
-+ }
-+ }
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_parse_open_loop_common_ctrl_data() - parse common open loop CPR3
-+ * controller properties from device tree
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_parse_open_loop_common_ctrl_data(struct cpr3_controller *ctrl)
-+{
-+ int rc;
-+
-+ rc = of_property_read_u32(ctrl->dev->of_node, "qcom,voltage-step",
-+ &ctrl->step_volt);
-+ if (rc) {
-+ cpr3_err(ctrl, "error reading property qcom,voltage-step, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ if (ctrl->step_volt <= 0) {
-+ cpr3_err(ctrl, "qcom,voltage-step=%d is invalid\n",
-+ ctrl->step_volt);
-+ return -EINVAL;
-+ }
-+
-+ if (of_find_property(ctrl->dev->of_node, "vdd-supply", NULL)) {
-+ ctrl->vdd_regulator = devm_regulator_get(ctrl->dev, "vdd");
-+ if (IS_ERR(ctrl->vdd_regulator)) {
-+ rc = PTR_ERR(ctrl->vdd_regulator);
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(ctrl, "unable to request vdd regulator, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ } else {
-+ cpr3_err(ctrl, "vdd supply is not defined\n");
-+ return -ENODEV;
-+ }
-+
-+ ctrl->system_regulator = devm_regulator_get_optional(ctrl->dev,
-+ "system");
-+ if (IS_ERR(ctrl->system_regulator)) {
-+ rc = PTR_ERR(ctrl->system_regulator);
-+ if (rc != -EPROBE_DEFER) {
-+ rc = 0;
-+ ctrl->system_regulator = NULL;
-+ } else {
-+ return rc;
-+ }
-+ } else {
-+ rc = regulator_enable(ctrl->system_regulator);
-+ }
-+
-+ ctrl->mem_acc_regulator = devm_regulator_get_optional(ctrl->dev,
-+ "mem-acc");
-+ if (IS_ERR(ctrl->mem_acc_regulator)) {
-+ rc = PTR_ERR(ctrl->mem_acc_regulator);
-+ if (rc != -EPROBE_DEFER) {
-+ rc = 0;
-+ ctrl->mem_acc_regulator = NULL;
-+ } else {
-+ return rc;
-+ }
-+ }
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_limit_open_loop_voltages() - modify the open-loop voltage of each corner
-+ * so that it fits within the floor to ceiling
-+ * voltage range of the corner
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * This function clips the open-loop voltage for each corner so that it is
-+ * limited to the floor to ceiling range. It also rounds each open-loop voltage
-+ * so that it corresponds to a set point available to the underlying regulator.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_limit_open_loop_voltages(struct cpr3_regulator *vreg)
-+{
-+ int i, volt;
-+
-+ cpr3_debug(vreg, "open-loop voltages after trimming and rounding:\n");
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ volt = CPR3_ROUND(vreg->corner[i].open_loop_volt,
-+ vreg->thread->ctrl->step_volt);
-+ if (volt < vreg->corner[i].floor_volt)
-+ volt = vreg->corner[i].floor_volt;
-+ else if (volt > vreg->corner[i].ceiling_volt)
-+ volt = vreg->corner[i].ceiling_volt;
-+ vreg->corner[i].open_loop_volt = volt;
-+ cpr3_debug(vreg, "corner[%2d]: open-loop=%d uV\n", i, volt);
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_open_loop_voltage_as_ceiling() - configures the ceiling voltage for each
-+ * corner to equal the open-loop voltage if the relevant device
-+ * tree property is found for the CPR3 regulator
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * This function assumes that the the open-loop voltage for each corner has
-+ * already been rounded to the nearest allowed set point and that it falls
-+ * within the floor to ceiling range.
-+ *
-+ * Return: none
-+ */
-+void cpr3_open_loop_voltage_as_ceiling(struct cpr3_regulator *vreg)
-+{
-+ int i;
-+
-+ if (!of_property_read_bool(vreg->of_node,
-+ "qcom,cpr-scaled-open-loop-voltage-as-ceiling"))
-+ return;
-+
-+ for (i = 0; i < vreg->corner_count; i++)
-+ vreg->corner[i].ceiling_volt
-+ = vreg->corner[i].open_loop_volt;
-+}
-+
-+/**
-+ * cpr3_limit_floor_voltages() - raise the floor voltage of each corner so that
-+ * the optional maximum floor to ceiling voltage range specified in
-+ * device tree is satisfied
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * This function also ensures that the open-loop voltage for each corner falls
-+ * within the final floor to ceiling voltage range and that floor voltages
-+ * increase monotonically.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_limit_floor_voltages(struct cpr3_regulator *vreg)
-+{
-+ char *prop = "qcom,cpr-floor-to-ceiling-max-range";
-+ int i, floor_new;
-+ u32 *floor_range;
-+ int rc = 0;
-+
-+ if (!of_find_property(vreg->of_node, prop, NULL))
-+ goto enforce_monotonicity;
-+
-+ floor_range = kcalloc(vreg->corner_count, sizeof(*floor_range),
-+ GFP_KERNEL);
-+ if (!floor_range)
-+ return -ENOMEM;
-+
-+ rc = cpr3_parse_corner_array_property(vreg, prop, 1, floor_range);
-+ if (rc)
-+ goto free_floor_adjust;
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ if ((s32)floor_range[i] >= 0) {
-+ floor_new = CPR3_ROUND(vreg->corner[i].ceiling_volt
-+ - floor_range[i],
-+ vreg->thread->ctrl->step_volt);
-+
-+ vreg->corner[i].floor_volt = max(floor_new,
-+ vreg->corner[i].floor_volt);
-+ if (vreg->corner[i].open_loop_volt
-+ < vreg->corner[i].floor_volt)
-+ vreg->corner[i].open_loop_volt
-+ = vreg->corner[i].floor_volt;
-+ }
-+ }
-+
-+free_floor_adjust:
-+ kfree(floor_range);
-+
-+enforce_monotonicity:
-+ /* Ensure that floor voltages increase monotonically. */
-+ for (i = 1; i < vreg->corner_count; i++) {
-+ if (vreg->corner[i].floor_volt
-+ < vreg->corner[i - 1].floor_volt) {
-+ cpr3_debug(vreg, "corner %d floor voltage=%d uV < corner %d voltage=%d uV; overriding: corner %d voltage=%d\n",
-+ i, vreg->corner[i].floor_volt,
-+ i - 1, vreg->corner[i - 1].floor_volt,
-+ i, vreg->corner[i - 1].floor_volt);
-+ vreg->corner[i].floor_volt
-+ = vreg->corner[i - 1].floor_volt;
-+
-+ if (vreg->corner[i].open_loop_volt
-+ < vreg->corner[i].floor_volt)
-+ vreg->corner[i].open_loop_volt
-+ = vreg->corner[i].floor_volt;
-+ if (vreg->corner[i].ceiling_volt
-+ < vreg->corner[i].floor_volt)
-+ vreg->corner[i].ceiling_volt
-+ = vreg->corner[i].floor_volt;
-+ }
-+ }
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_print_quots() - print CPR target quotients into the kernel log for
-+ * debugging purposes
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * Return: none
-+ */
-+void cpr3_print_quots(struct cpr3_regulator *vreg)
-+{
-+ int i, j, pos;
-+ size_t buflen;
-+ char *buf;
-+
-+ buflen = sizeof(*buf) * CPR3_RO_COUNT * (MAX_CHARS_PER_INT + 2);
-+ buf = kzalloc(buflen, GFP_KERNEL);
-+ if (!buf)
-+ return;
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ for (j = 0, pos = 0; j < CPR3_RO_COUNT; j++)
-+ pos += scnprintf(buf + pos, buflen - pos, " %u",
-+ vreg->corner[i].target_quot[j]);
-+ cpr3_debug(vreg, "target quots[%2d]:%s\n", i, buf);
-+ }
-+
-+ kfree(buf);
-+}
-+
-+/**
-+ * cpr3_determine_part_type() - determine the part type (SS/TT/FF).
-+ *
-+ * qcom,cpr-part-types prop tells the number of part types for which correction
-+ * voltages are different. Another prop qcom,cpr-parts-voltage will contain the
-+ * open loop fuse voltage which will be compared with this part voltage
-+ * and accordingly part type will de determined.
-+ *
-+ * if qcom,cpr-part-types has value n, then qcom,cpr-parts-voltage will be
-+ * array of n - 1 elements which will contain the voltage in increasing order.
-+ * This function compares the fused volatge with all these voltage and returns
-+ * the first index for which the fused volatge is greater.
-+ *
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @fuse_volt: fused open loop voltage which will be compared with
-+ * qcom,cpr-parts-voltage array
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_determine_part_type(struct cpr3_regulator *vreg, int fuse_volt)
-+{
-+ int i, rc, len;
-+ u32 volt;
-+ int soc_version_major;
-+ char prop_name[100];
-+ const char prop_name_def[] = "qcom,cpr-parts-voltage";
-+ const char prop_name_v2[] = "qcom,cpr-parts-voltage-v2";
-+
-+ soc_version_major = read_ipq_soc_version_major();
-+ BUG_ON(soc_version_major <= 0);
-+
-+ if (of_property_read_u32(vreg->of_node, "qcom,cpr-part-types",
-+ &vreg->part_type_supported))
-+ return 0;
-+
-+ if (soc_version_major > 1)
-+ strlcpy(prop_name, prop_name_v2, sizeof(prop_name_v2));
-+ else
-+ strlcpy(prop_name, prop_name_def, sizeof(prop_name_def));
-+
-+ if (!of_find_property(vreg->of_node, prop_name, &len)) {
-+ cpr3_err(vreg, "property %s is missing\n", prop_name);
-+ return -EINVAL;
-+ }
-+
-+ if (len != (vreg->part_type_supported - 1) * sizeof(u32)) {
-+ cpr3_err(vreg, "wrong len in qcom,cpr-parts-voltage\n");
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < vreg->part_type_supported - 1; i++) {
-+ rc = of_property_read_u32_index(vreg->of_node,
-+ prop_name, i, &volt);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading property %s, rc=%d\n",
-+ prop_name, rc);
-+ return rc;
-+ }
-+
-+ if (fuse_volt < volt)
-+ break;
-+ }
-+
-+ vreg->part_type = i;
-+ return 0;
-+}
-+
-+int cpr3_determine_temp_base_open_loop_correction(struct cpr3_regulator *vreg,
-+ int *fuse_volt)
-+{
-+ int i, rc, prev_volt;
-+ int *volt_adjust;
-+ char prop_str[75];
-+ int soc_version_major = read_ipq_soc_version_major();
-+
-+ BUG_ON(soc_version_major <= 0);
-+
-+ if (vreg->part_type_supported) {
-+ if (soc_version_major > 1)
-+ snprintf(prop_str, sizeof(prop_str),
-+ "qcom,cpr-cold-temp-voltage-adjustment-v2-%d",
-+ vreg->part_type);
-+ else
-+ snprintf(prop_str, sizeof(prop_str),
-+ "qcom,cpr-cold-temp-voltage-adjustment-%d",
-+ vreg->part_type);
-+ } else {
-+ strlcpy(prop_str, "qcom,cpr-cold-temp-voltage-adjustment",
-+ sizeof(prop_str));
-+ }
-+
-+ if (!of_find_property(vreg->of_node, prop_str, NULL)) {
-+ /* No adjustment required. */
-+ cpr3_info(vreg, "No cold temperature adjustment required.\n");
-+ return 0;
-+ }
-+
-+ volt_adjust = kcalloc(vreg->fuse_corner_count, sizeof(*volt_adjust),
-+ GFP_KERNEL);
-+ if (!volt_adjust)
-+ return -ENOMEM;
-+
-+ rc = cpr3_parse_array_property(vreg, prop_str,
-+ vreg->fuse_corner_count, volt_adjust);
-+ if (rc) {
-+ cpr3_err(vreg, "could not load cold temp voltage adjustments, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+
-+ for (i = 0; i < vreg->fuse_corner_count; i++) {
-+ if (volt_adjust[i]) {
-+ prev_volt = fuse_volt[i];
-+ fuse_volt[i] += volt_adjust[i];
-+ cpr3_debug(vreg,
-+ "adjusted fuse corner %d open-loop voltage: %d -> %d uV\n",
-+ i, prev_volt, fuse_volt[i]);
-+ }
-+ }
-+
-+done:
-+ kfree(volt_adjust);
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_can_adjust_cold_temp() - Is cold temperature adjustment available
-+ *
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * This function checks the cold temperature threshold is available
-+ *
-+ * Return: true on cold temperature threshold is available, else false
-+ */
-+bool cpr3_can_adjust_cold_temp(struct cpr3_regulator *vreg)
-+{
-+ char prop_str[75];
-+ int soc_version_major = read_ipq_soc_version_major();
-+
-+ BUG_ON(soc_version_major <= 0);
-+
-+ if (soc_version_major > 1)
-+ strlcpy(prop_str, "qcom,cpr-cold-temp-threshold-v2",
-+ sizeof(prop_str));
-+ else
-+ strlcpy(prop_str, "qcom,cpr-cold-temp-threshold",
-+ sizeof(prop_str));
-+
-+ if (!of_find_property(vreg->of_node, prop_str, NULL)) {
-+ /* No adjustment required. */
-+ return false;
-+ } else
-+ return true;
-+}
-+
-+/**
-+ * cpr3_get_cold_temp_threshold() - get cold temperature threshold
-+ *
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @cold_temp: cold temperature read.
-+ *
-+ * This function reads the cold temperature threshold below which
-+ * cold temperature adjustment margins will be applied.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_get_cold_temp_threshold(struct cpr3_regulator *vreg, int *cold_temp)
-+{
-+ int rc;
-+ u32 temp;
-+ char req_prop_str[75], prop_str[75];
-+ int soc_version_major = read_ipq_soc_version_major();
-+
-+ BUG_ON(soc_version_major <= 0);
-+
-+ if (vreg->part_type_supported) {
-+ if (soc_version_major > 1)
-+ snprintf(req_prop_str, sizeof(req_prop_str),
-+ "qcom,cpr-cold-temp-voltage-adjustment-v2-%d",
-+ vreg->part_type);
-+ else
-+ snprintf(req_prop_str, sizeof(req_prop_str),
-+ "qcom,cpr-cold-temp-voltage-adjustment-%d",
-+ vreg->part_type);
-+ } else {
-+ strlcpy(req_prop_str, "qcom,cpr-cold-temp-voltage-adjustment",
-+ sizeof(req_prop_str));
-+ }
-+
-+ if (soc_version_major > 1)
-+ strlcpy(prop_str, "qcom,cpr-cold-temp-threshold-v2",
-+ sizeof(prop_str));
-+ else
-+ strlcpy(prop_str, "qcom,cpr-cold-temp-threshold",
-+ sizeof(prop_str));
-+
-+ if (!of_find_property(vreg->of_node, req_prop_str, NULL)) {
-+ /* No adjustment required. */
-+ cpr3_info(vreg, "Cold temperature adjustment not required.\n");
-+ return 0;
-+ }
-+
-+ if (!of_find_property(vreg->of_node, prop_str, NULL)) {
-+ /* No adjustment required. */
-+ cpr3_err(vreg, "Missing %s required for %s\n",
-+ prop_str, req_prop_str);
-+ return -EINVAL;
-+ }
-+
-+ rc = of_property_read_u32(vreg->of_node, prop_str, &temp);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading property %s, rc=%d\n",
-+ prop_str, rc);
-+ return rc;
-+ }
-+
-+ *cold_temp = temp;
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_adjust_fused_open_loop_voltages() - adjust the fused open-loop voltages
-+ * for each fuse corner according to device tree values
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @fuse_volt: Pointer to an array of the fused open-loop voltage
-+ * values
-+ *
-+ * Voltage values in fuse_volt are modified in place.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_adjust_fused_open_loop_voltages(struct cpr3_regulator *vreg,
-+ int *fuse_volt)
-+{
-+ int i, rc, prev_volt;
-+ int *volt_adjust;
-+ char prop_str[75];
-+ int soc_version_major = read_ipq_soc_version_major();
-+
-+ BUG_ON(soc_version_major <= 0);
-+
-+ if (vreg->part_type_supported) {
-+ if (soc_version_major > 1)
-+ snprintf(prop_str, sizeof(prop_str),
-+ "qcom,cpr-open-loop-voltage-fuse-adjustment-v2-%d",
-+ vreg->part_type);
-+ else
-+ snprintf(prop_str, sizeof(prop_str),
-+ "qcom,cpr-open-loop-voltage-fuse-adjustment-%d",
-+ vreg->part_type);
-+ } else {
-+ strlcpy(prop_str, "qcom,cpr-open-loop-voltage-fuse-adjustment",
-+ sizeof(prop_str));
-+ }
-+
-+ if (!of_find_property(vreg->of_node, prop_str, NULL)) {
-+ /* No adjustment required. */
-+ return 0;
-+ }
-+
-+ volt_adjust = kcalloc(vreg->fuse_corner_count, sizeof(*volt_adjust),
-+ GFP_KERNEL);
-+ if (!volt_adjust)
-+ return -ENOMEM;
-+
-+ rc = cpr3_parse_array_property(vreg,
-+ prop_str, vreg->fuse_corner_count, volt_adjust);
-+ if (rc) {
-+ cpr3_err(vreg, "could not load open-loop fused voltage adjustments, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+
-+ for (i = 0; i < vreg->fuse_corner_count; i++) {
-+ if (volt_adjust[i]) {
-+ prev_volt = fuse_volt[i];
-+ fuse_volt[i] += volt_adjust[i];
-+ cpr3_debug(vreg, "adjusted fuse corner %d open-loop voltage: %d --> %d uV\n",
-+ i, prev_volt, fuse_volt[i]);
-+ }
-+ }
-+
-+done:
-+ kfree(volt_adjust);
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_adjust_open_loop_voltages() - adjust the open-loop voltages for each
-+ * corner according to device tree values
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_adjust_open_loop_voltages(struct cpr3_regulator *vreg)
-+{
-+ int i, rc, prev_volt, min_volt;
-+ int *volt_adjust, *volt_diff;
-+
-+ if (!of_find_property(vreg->of_node,
-+ "qcom,cpr-open-loop-voltage-adjustment", NULL)) {
-+ /* No adjustment required. */
-+ return 0;
-+ }
-+
-+ volt_adjust = kcalloc(vreg->corner_count, sizeof(*volt_adjust),
-+ GFP_KERNEL);
-+ volt_diff = kcalloc(vreg->corner_count, sizeof(*volt_diff), GFP_KERNEL);
-+ if (!volt_adjust || !volt_diff) {
-+ rc = -ENOMEM;
-+ goto done;
-+ }
-+
-+ rc = cpr3_parse_corner_array_property(vreg,
-+ "qcom,cpr-open-loop-voltage-adjustment", 1, volt_adjust);
-+ if (rc) {
-+ cpr3_err(vreg, "could not load open-loop voltage adjustments, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ if (volt_adjust[i]) {
-+ prev_volt = vreg->corner[i].open_loop_volt;
-+ vreg->corner[i].open_loop_volt += volt_adjust[i];
-+ cpr3_debug(vreg, "adjusted corner %d open-loop voltage: %d --> %d uV\n",
-+ i, prev_volt, vreg->corner[i].open_loop_volt);
-+ }
-+ }
-+
-+ if (of_find_property(vreg->of_node,
-+ "qcom,cpr-open-loop-voltage-min-diff", NULL)) {
-+ rc = cpr3_parse_corner_array_property(vreg,
-+ "qcom,cpr-open-loop-voltage-min-diff", 1, volt_diff);
-+ if (rc) {
-+ cpr3_err(vreg, "could not load minimum open-loop voltage differences, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+ /*
-+ * Ensure that open-loop voltages increase monotonically with respect
-+ * to configurable minimum allowed differences.
-+ */
-+ for (i = 1; i < vreg->corner_count; i++) {
-+ min_volt = vreg->corner[i - 1].open_loop_volt + volt_diff[i];
-+ if (vreg->corner[i].open_loop_volt < min_volt) {
-+ cpr3_debug(vreg, "adjusted corner %d open-loop voltage=%d uV < corner %d voltage=%d uV + min diff=%d uV; overriding: corner %d voltage=%d\n",
-+ i, vreg->corner[i].open_loop_volt,
-+ i - 1, vreg->corner[i - 1].open_loop_volt,
-+ volt_diff[i], i, min_volt);
-+ vreg->corner[i].open_loop_volt = min_volt;
-+ }
-+ }
-+
-+done:
-+ kfree(volt_diff);
-+ kfree(volt_adjust);
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_quot_adjustment() - returns the quotient adjustment value resulting from
-+ * the specified voltage adjustment and RO scaling factor
-+ * @ro_scale: The CPR ring oscillator (RO) scaling factor with units
-+ * of QUOT/V
-+ * @volt_adjust: The amount to adjust the voltage by in units of
-+ * microvolts. This value may be positive or negative.
-+ */
-+int cpr3_quot_adjustment(int ro_scale, int volt_adjust)
-+{
-+ unsigned long long temp;
-+ int quot_adjust;
-+ int sign = 1;
-+
-+ if (ro_scale < 0) {
-+ sign = -sign;
-+ ro_scale = -ro_scale;
-+ }
-+
-+ if (volt_adjust < 0) {
-+ sign = -sign;
-+ volt_adjust = -volt_adjust;
-+ }
-+
-+ temp = (unsigned long long)ro_scale * (unsigned long long)volt_adjust;
-+ do_div(temp, 1000000);
-+
-+ quot_adjust = temp;
-+ quot_adjust *= sign;
-+
-+ return quot_adjust;
-+}
-+
-+/**
-+ * cpr3_voltage_adjustment() - returns the voltage adjustment value resulting
-+ * from the specified quotient adjustment and RO scaling factor
-+ * @ro_scale: The CPR ring oscillator (RO) scaling factor with units
-+ * of QUOT/V
-+ * @quot_adjust: The amount to adjust the quotient by in units of
-+ * QUOT. This value may be positive or negative.
-+ */
-+int cpr3_voltage_adjustment(int ro_scale, int quot_adjust)
-+{
-+ unsigned long long temp;
-+ int volt_adjust;
-+ int sign = 1;
-+
-+ if (ro_scale < 0) {
-+ sign = -sign;
-+ ro_scale = -ro_scale;
-+ }
-+
-+ if (quot_adjust < 0) {
-+ sign = -sign;
-+ quot_adjust = -quot_adjust;
-+ }
-+
-+ if (ro_scale == 0)
-+ return 0;
-+
-+ temp = (unsigned long long)quot_adjust * 1000000;
-+ do_div(temp, ro_scale);
-+
-+ volt_adjust = temp;
-+ volt_adjust *= sign;
-+
-+ return volt_adjust;
-+}
-+
-+/**
-+ * cpr3_parse_closed_loop_voltage_adjustments() - load per-fuse-corner and
-+ * per-corner closed-loop adjustment values from device tree
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @ro_sel: Array of ring oscillator values selected for each
-+ * fuse corner
-+ * @volt_adjust: Pointer to array which will be filled with the
-+ * per-corner closed-loop adjustment voltages
-+ * @volt_adjust_fuse: Pointer to array which will be filled with the
-+ * per-fuse-corner closed-loop adjustment voltages
-+ * @ro_scale: Pointer to array which will be filled with the
-+ * per-fuse-corner RO scaling factor values with units of
-+ * QUOT/V
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_parse_closed_loop_voltage_adjustments(
-+ struct cpr3_regulator *vreg, u64 *ro_sel,
-+ int *volt_adjust, int *volt_adjust_fuse, int *ro_scale)
-+{
-+ int i, rc;
-+ u32 *ro_all_scale;
-+
-+ char volt_adj[] = "qcom,cpr-closed-loop-voltage-adjustment";
-+ char volt_fuse_adj[] = "qcom,cpr-closed-loop-voltage-fuse-adjustment";
-+ char ro_scaling[] = "qcom,cpr-ro-scaling-factor";
-+
-+ if (!of_find_property(vreg->of_node, volt_adj, NULL)
-+ && !of_find_property(vreg->of_node, volt_fuse_adj, NULL)
-+ && !vreg->aging_allowed) {
-+ /* No adjustment required. */
-+ return 0;
-+ } else if (!of_find_property(vreg->of_node, ro_scaling, NULL)) {
-+ cpr3_err(vreg, "Missing %s required for closed-loop voltage adjustment.\n",
-+ ro_scaling);
-+ return -EINVAL;
-+ }
-+
-+ ro_all_scale = kcalloc(vreg->fuse_corner_count * CPR3_RO_COUNT,
-+ sizeof(*ro_all_scale), GFP_KERNEL);
-+ if (!ro_all_scale)
-+ return -ENOMEM;
-+
-+ rc = cpr3_parse_array_property(vreg, ro_scaling,
-+ vreg->fuse_corner_count * CPR3_RO_COUNT, ro_all_scale);
-+ if (rc) {
-+ cpr3_err(vreg, "could not load RO scaling factors, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+
-+ for (i = 0; i < vreg->fuse_corner_count; i++)
-+ ro_scale[i] = ro_all_scale[i * CPR3_RO_COUNT + ro_sel[i]];
-+
-+ for (i = 0; i < vreg->corner_count; i++)
-+ memcpy(vreg->corner[i].ro_scale,
-+ &ro_all_scale[vreg->corner[i].cpr_fuse_corner * CPR3_RO_COUNT],
-+ sizeof(*ro_all_scale) * CPR3_RO_COUNT);
-+
-+ if (of_find_property(vreg->of_node, volt_fuse_adj, NULL)) {
-+ rc = cpr3_parse_array_property(vreg, volt_fuse_adj,
-+ vreg->fuse_corner_count, volt_adjust_fuse);
-+ if (rc) {
-+ cpr3_err(vreg, "could not load closed-loop fused voltage adjustments, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+ if (of_find_property(vreg->of_node, volt_adj, NULL)) {
-+ rc = cpr3_parse_corner_array_property(vreg, volt_adj,
-+ 1, volt_adjust);
-+ if (rc) {
-+ cpr3_err(vreg, "could not load closed-loop voltage adjustments, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+done:
-+ kfree(ro_all_scale);
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_apm_init() - initialize APM data for a CPR3 controller
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * This function loads memory array power mux (APM) data from device tree
-+ * if it is present and requests a handle to the appropriate APM controller
-+ * device.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_apm_init(struct cpr3_controller *ctrl)
-+{
-+ struct device_node *node = ctrl->dev->of_node;
-+ int rc;
-+
-+ if (!of_find_property(node, "qcom,apm-ctrl", NULL)) {
-+ /* No APM used */
-+ return 0;
-+ }
-+
-+ ctrl->apm = msm_apm_ctrl_dev_get(ctrl->dev);
-+ if (IS_ERR(ctrl->apm)) {
-+ rc = PTR_ERR(ctrl->apm);
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(ctrl, "APM get failed, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ rc = of_property_read_u32(node, "qcom,apm-threshold-voltage",
-+ &ctrl->apm_threshold_volt);
-+ if (rc) {
-+ cpr3_err(ctrl, "error reading qcom,apm-threshold-voltage, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ ctrl->apm_threshold_volt
-+ = CPR3_ROUND(ctrl->apm_threshold_volt, ctrl->step_volt);
-+
-+ /* No error check since this is an optional property. */
-+ of_property_read_u32(node, "qcom,apm-hysteresis-voltage",
-+ &ctrl->apm_adj_volt);
-+ ctrl->apm_adj_volt = CPR3_ROUND(ctrl->apm_adj_volt, ctrl->step_volt);
-+
-+ ctrl->apm_high_supply = MSM_APM_SUPPLY_APCC;
-+ ctrl->apm_low_supply = MSM_APM_SUPPLY_MX;
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr3_mem_acc_init() - initialize mem-acc regulator data for
-+ * a CPR3 regulator
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_mem_acc_init(struct cpr3_regulator *vreg)
-+{
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ u32 *temp;
-+ int i, rc;
-+
-+ if (!ctrl->mem_acc_regulator) {
-+ cpr3_info(ctrl, "not using memory accelerator regulator\n");
-+ return 0;
-+ }
-+
-+ temp = kcalloc(vreg->corner_count, sizeof(*temp), GFP_KERNEL);
-+ if (!temp)
-+ return -ENOMEM;
-+
-+ rc = cpr3_parse_corner_array_property(vreg, "qcom,mem-acc-voltage",
-+ 1, temp);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not load mem-acc corners, rc=%d\n", rc);
-+ } else {
-+ for (i = 0; i < vreg->corner_count; i++)
-+ vreg->corner[i].mem_acc_volt = temp[i];
-+ }
-+
-+ kfree(temp);
-+ return rc;
-+}
-+
-+/**
-+ * cpr4_load_core_and_temp_adj() - parse amount of voltage adjustment for
-+ * per-online-core and per-temperature voltage adjustment for a
-+ * given corner or corner band from device tree.
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @num: Corner number or corner band number
-+ * @use_corner_band: Boolean indicating if the CPR3 regulator supports
-+ * adjustments per corner band
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_load_core_and_temp_adj(struct cpr3_regulator *vreg,
-+ int num, bool use_corner_band)
-+{
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ struct cpr4_sdelta *sdelta;
-+ int sdelta_size, i, j, pos, rc = 0;
-+ char str[75];
-+ size_t buflen;
-+ char *buf;
-+
-+ sdelta = use_corner_band ? vreg->corner_band[num].sdelta :
-+ vreg->corner[num].sdelta;
-+
-+ if (!sdelta->allow_core_count_adj && !sdelta->allow_temp_adj) {
-+ /* corner doesn't need sdelta table */
-+ sdelta->max_core_count = 0;
-+ sdelta->temp_band_count = 0;
-+ return rc;
-+ }
-+
-+ sdelta_size = sdelta->max_core_count * sdelta->temp_band_count;
-+ if (use_corner_band)
-+ snprintf(str, sizeof(str),
-+ "corner_band=%d core_config_count=%d temp_band_count=%d sdelta_size=%d\n",
-+ num, sdelta->max_core_count,
-+ sdelta->temp_band_count, sdelta_size);
-+ else
-+ snprintf(str, sizeof(str),
-+ "corner=%d core_config_count=%d temp_band_count=%d sdelta_size=%d\n",
-+ num, sdelta->max_core_count,
-+ sdelta->temp_band_count, sdelta_size);
-+
-+ cpr3_debug(vreg, "%s", str);
-+
-+ sdelta->table = devm_kcalloc(ctrl->dev, sdelta_size,
-+ sizeof(*sdelta->table), GFP_KERNEL);
-+ if (!sdelta->table)
-+ return -ENOMEM;
-+
-+ if (use_corner_band)
-+ snprintf(str, sizeof(str),
-+ "qcom,cpr-corner-band%d-temp-core-voltage-adjustment",
-+ num + CPR3_CORNER_OFFSET);
-+ else
-+ snprintf(str, sizeof(str),
-+ "qcom,cpr-corner%d-temp-core-voltage-adjustment",
-+ num + CPR3_CORNER_OFFSET);
-+
-+ rc = cpr3_parse_array_property(vreg, str, sdelta_size,
-+ sdelta->table);
-+ if (rc) {
-+ cpr3_err(vreg, "could not load %s, rc=%d\n", str, rc);
-+ return rc;
-+ }
-+
-+ /*
-+ * Convert sdelta margins from uV to PMIC steps and apply negation to
-+ * follow the SDELTA register semantics.
-+ */
-+ for (i = 0; i < sdelta_size; i++)
-+ sdelta->table[i] = -(sdelta->table[i] / ctrl->step_volt);
-+
-+ buflen = sizeof(*buf) * sdelta_size * (MAX_CHARS_PER_INT + 2);
-+ buf = kzalloc(buflen, GFP_KERNEL);
-+ if (!buf)
-+ return rc;
-+
-+ for (i = 0; i < sdelta->max_core_count; i++) {
-+ for (j = 0, pos = 0; j < sdelta->temp_band_count; j++)
-+ pos += scnprintf(buf + pos, buflen - pos, " %u",
-+ sdelta->table[i * sdelta->temp_band_count + j]);
-+ cpr3_debug(vreg, "sdelta[%d]:%s\n", i, buf);
-+ }
-+
-+ kfree(buf);
-+ return rc;
-+}
-+
-+/**
-+ * cpr4_parse_core_count_temp_voltage_adj() - parse configuration data for
-+ * per-online-core and per-temperature voltage adjustment for
-+ * a CPR3 regulator from device tree.
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @use_corner_band: Boolean indicating if the CPR3 regulator supports
-+ * adjustments per corner band
-+ *
-+ * This function supports parsing of per-online-core and per-temperature
-+ * adjustments per corner or per corner band. CPR controllers which support
-+ * corner bands apply the same adjustments to all corners within a corner band.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr4_parse_core_count_temp_voltage_adj(
-+ struct cpr3_regulator *vreg, bool use_corner_band)
-+{
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ struct device_node *node = vreg->of_node;
-+ struct cpr3_corner *corner;
-+ struct cpr4_sdelta *sdelta;
-+ int i, sdelta_table_count, rc = 0;
-+ int *allow_core_count_adj = NULL, *allow_temp_adj = NULL;
-+ char prop_str[75];
-+
-+ if (of_find_property(node, use_corner_band ?
-+ "qcom,corner-band-allow-temp-adjustment"
-+ : "qcom,corner-allow-temp-adjustment", NULL)) {
-+ if (!ctrl->allow_temp_adj) {
-+ cpr3_err(ctrl, "Temperature adjustment configurations missing\n");
-+ return -EINVAL;
-+ }
-+
-+ vreg->allow_temp_adj = true;
-+ }
-+
-+ if (of_find_property(node, use_corner_band ?
-+ "qcom,corner-band-allow-core-count-adjustment"
-+ : "qcom,corner-allow-core-count-adjustment",
-+ NULL)) {
-+ rc = of_property_read_u32(node, "qcom,max-core-count",
-+ &vreg->max_core_count);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading qcom,max-core-count, rc=%d\n",
-+ rc);
-+ return -EINVAL;
-+ }
-+
-+ vreg->allow_core_count_adj = true;
-+ ctrl->allow_core_count_adj = true;
-+ }
-+
-+ if (!vreg->allow_temp_adj && !vreg->allow_core_count_adj) {
-+ /*
-+ * Both per-online-core and temperature based adjustments are
-+ * disabled for this regulator.
-+ */
-+ return 0;
-+ } else if (!vreg->allow_core_count_adj) {
-+ /*
-+ * Only per-temperature voltage adjusments are allowed.
-+ * Keep max core count value as 1 to allocate SDELTA.
-+ */
-+ vreg->max_core_count = 1;
-+ }
-+
-+ if (vreg->allow_core_count_adj) {
-+ allow_core_count_adj = kcalloc(vreg->corner_count,
-+ sizeof(*allow_core_count_adj),
-+ GFP_KERNEL);
-+ if (!allow_core_count_adj)
-+ return -ENOMEM;
-+
-+ snprintf(prop_str, sizeof(prop_str), "%s", use_corner_band ?
-+ "qcom,corner-band-allow-core-count-adjustment" :
-+ "qcom,corner-allow-core-count-adjustment");
-+
-+ rc = use_corner_band ?
-+ cpr3_parse_corner_band_array_property(vreg, prop_str,
-+ 1, allow_core_count_adj) :
-+ cpr3_parse_corner_array_property(vreg, prop_str,
-+ 1, allow_core_count_adj);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading %s, rc=%d\n", prop_str,
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+ if (vreg->allow_temp_adj) {
-+ allow_temp_adj = kcalloc(vreg->corner_count,
-+ sizeof(*allow_temp_adj), GFP_KERNEL);
-+ if (!allow_temp_adj) {
-+ rc = -ENOMEM;
-+ goto done;
-+ }
-+
-+ snprintf(prop_str, sizeof(prop_str), "%s", use_corner_band ?
-+ "qcom,corner-band-allow-temp-adjustment" :
-+ "qcom,corner-allow-temp-adjustment");
-+
-+ rc = use_corner_band ?
-+ cpr3_parse_corner_band_array_property(vreg, prop_str,
-+ 1, allow_temp_adj) :
-+ cpr3_parse_corner_array_property(vreg, prop_str,
-+ 1, allow_temp_adj);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading %s, rc=%d\n", prop_str,
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+ sdelta_table_count = use_corner_band ? vreg->corner_band_count :
-+ vreg->corner_count;
-+
-+ for (i = 0; i < sdelta_table_count; i++) {
-+ sdelta = devm_kzalloc(ctrl->dev, sizeof(*corner->sdelta),
-+ GFP_KERNEL);
-+ if (!sdelta) {
-+ rc = -ENOMEM;
-+ goto done;
-+ }
-+
-+ if (allow_core_count_adj)
-+ sdelta->allow_core_count_adj = allow_core_count_adj[i];
-+ if (allow_temp_adj)
-+ sdelta->allow_temp_adj = allow_temp_adj[i];
-+ sdelta->max_core_count = vreg->max_core_count;
-+ sdelta->temp_band_count = ctrl->temp_band_count;
-+
-+ if (use_corner_band)
-+ vreg->corner_band[i].sdelta = sdelta;
-+ else
-+ vreg->corner[i].sdelta = sdelta;
-+
-+ rc = cpr4_load_core_and_temp_adj(vreg, i, use_corner_band);
-+ if (rc) {
-+ cpr3_err(vreg, "corner/band %d core and temp adjustment loading failed, rc=%d\n",
-+ i, rc);
-+ goto done;
-+ }
-+ }
-+
-+done:
-+ kfree(allow_core_count_adj);
-+ kfree(allow_temp_adj);
-+
-+ return rc;
-+}
-+
-+/**
-+ * cprh_adjust_voltages_for_apm() - adjust per-corner floor and ceiling voltages
-+ * so that they do not overlap the APM threshold voltage.
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * The memory array power mux (APM) must be configured for a specific supply
-+ * based upon where the VDD voltage lies with respect to the APM threshold
-+ * voltage. When using CPR hardware closed-loop, the voltage may vary anywhere
-+ * between the floor and ceiling voltage without software notification.
-+ * Therefore, it is required that the floor to ceiling range for every corner
-+ * not intersect the APM threshold voltage. This function adjusts the floor to
-+ * ceiling range for each corner which violates this requirement.
-+ *
-+ * The following algorithm is applied:
-+ * if floor < threshold <= ceiling:
-+ * if open_loop >= threshold, then floor = threshold - adj
-+ * else ceiling = threshold - step
-+ * where:
-+ * adj = APM hysteresis voltage established to minimize the number of
-+ * corners with artificially increased floor voltages
-+ * step = voltage in microvolts of a single step of the VDD supply
-+ *
-+ * The open-loop voltage is also bounded by the new floor or ceiling value as
-+ * needed.
-+ *
-+ * Return: none
-+ */
-+void cprh_adjust_voltages_for_apm(struct cpr3_regulator *vreg)
-+{
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ struct cpr3_corner *corner;
-+ int i, adj, threshold, prev_ceiling, prev_floor, prev_open_loop;
-+
-+ if (!ctrl->apm_threshold_volt) {
-+ /* APM not being used. */
-+ return;
-+ }
-+
-+ ctrl->apm_threshold_volt = CPR3_ROUND(ctrl->apm_threshold_volt,
-+ ctrl->step_volt);
-+ ctrl->apm_adj_volt = CPR3_ROUND(ctrl->apm_adj_volt, ctrl->step_volt);
-+
-+ threshold = ctrl->apm_threshold_volt;
-+ adj = ctrl->apm_adj_volt;
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ corner = &vreg->corner[i];
-+
-+ if (threshold <= corner->floor_volt
-+ || threshold > corner->ceiling_volt)
-+ continue;
-+
-+ prev_floor = corner->floor_volt;
-+ prev_ceiling = corner->ceiling_volt;
-+ prev_open_loop = corner->open_loop_volt;
-+
-+ if (corner->open_loop_volt >= threshold) {
-+ corner->floor_volt = max(corner->floor_volt,
-+ threshold - adj);
-+ if (corner->open_loop_volt < corner->floor_volt)
-+ corner->open_loop_volt = corner->floor_volt;
-+ } else {
-+ corner->ceiling_volt = threshold - ctrl->step_volt;
-+ }
-+
-+ if (corner->floor_volt != prev_floor
-+ || corner->ceiling_volt != prev_ceiling
-+ || corner->open_loop_volt != prev_open_loop)
-+ cpr3_debug(vreg, "APM threshold=%d, APM adj=%d changed corner %d voltages; prev: floor=%d, ceiling=%d, open-loop=%d; new: floor=%d, ceiling=%d, open-loop=%d\n",
-+ threshold, adj, i, prev_floor, prev_ceiling,
-+ prev_open_loop, corner->floor_volt,
-+ corner->ceiling_volt, corner->open_loop_volt);
-+ }
-+}
-+
-+/**
-+ * cprh_adjust_voltages_for_mem_acc() - adjust per-corner floor and ceiling
-+ * voltages so that they do not intersect the MEM ACC threshold
-+ * voltage
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * The following algorithm is applied:
-+ * if floor < threshold <= ceiling:
-+ * if open_loop >= threshold, then floor = threshold
-+ * else ceiling = threshold - step
-+ * where:
-+ * step = voltage in microvolts of a single step of the VDD supply
-+ *
-+ * The open-loop voltage is also bounded by the new floor or ceiling value as
-+ * needed.
-+ *
-+ * Return: none
-+ */
-+void cprh_adjust_voltages_for_mem_acc(struct cpr3_regulator *vreg)
-+{
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ struct cpr3_corner *corner;
-+ int i, threshold, prev_ceiling, prev_floor, prev_open_loop;
-+
-+ if (!ctrl->mem_acc_threshold_volt) {
-+ /* MEM ACC not being used. */
-+ return;
-+ }
-+
-+ ctrl->mem_acc_threshold_volt = CPR3_ROUND(ctrl->mem_acc_threshold_volt,
-+ ctrl->step_volt);
-+
-+ threshold = ctrl->mem_acc_threshold_volt;
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ corner = &vreg->corner[i];
-+
-+ if (threshold <= corner->floor_volt
-+ || threshold > corner->ceiling_volt)
-+ continue;
-+
-+ prev_floor = corner->floor_volt;
-+ prev_ceiling = corner->ceiling_volt;
-+ prev_open_loop = corner->open_loop_volt;
-+
-+ if (corner->open_loop_volt >= threshold) {
-+ corner->floor_volt = max(corner->floor_volt, threshold);
-+ if (corner->open_loop_volt < corner->floor_volt)
-+ corner->open_loop_volt = corner->floor_volt;
-+ } else {
-+ corner->ceiling_volt = threshold - ctrl->step_volt;
-+ }
-+
-+ if (corner->floor_volt != prev_floor
-+ || corner->ceiling_volt != prev_ceiling
-+ || corner->open_loop_volt != prev_open_loop)
-+ cpr3_debug(vreg, "MEM ACC threshold=%d changed corner %d voltages; prev: floor=%d, ceiling=%d, open-loop=%d; new: floor=%d, ceiling=%d, open-loop=%d\n",
-+ threshold, i, prev_floor, prev_ceiling,
-+ prev_open_loop, corner->floor_volt,
-+ corner->ceiling_volt, corner->open_loop_volt);
-+ }
-+}
-+
-+/**
-+ * cpr3_apply_closed_loop_offset_voltages() - modify the closed-loop voltage
-+ * adjustments by the amounts that are needed for this
-+ * fuse combo
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @volt_adjust: Array of closed-loop voltage adjustment values of length
-+ * vreg->corner_count which is further adjusted based upon
-+ * offset voltage fuse values.
-+ * @fuse_volt_adjust: Fused closed-loop voltage adjustment values of length
-+ * vreg->fuse_corner_count.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr3_apply_closed_loop_offset_voltages(struct cpr3_regulator *vreg,
-+ int *volt_adjust, int *fuse_volt_adjust)
-+{
-+ u32 *corner_map;
-+ int rc = 0, i;
-+
-+ if (!of_find_property(vreg->of_node,
-+ "qcom,cpr-fused-closed-loop-voltage-adjustment-map", NULL)) {
-+ /* No closed-loop offset required. */
-+ return 0;
-+ }
-+
-+ corner_map = kcalloc(vreg->corner_count, sizeof(*corner_map),
-+ GFP_KERNEL);
-+ if (!corner_map)
-+ return -ENOMEM;
-+
-+ rc = cpr3_parse_corner_array_property(vreg,
-+ "qcom,cpr-fused-closed-loop-voltage-adjustment-map",
-+ 1, corner_map);
-+ if (rc)
-+ goto done;
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ if (corner_map[i] == 0) {
-+ continue;
-+ } else if (corner_map[i] > vreg->fuse_corner_count) {
-+ cpr3_err(vreg, "corner %d mapped to invalid fuse corner: %u\n",
-+ i, corner_map[i]);
-+ rc = -EINVAL;
-+ goto done;
-+ }
-+
-+ volt_adjust[i] += fuse_volt_adjust[corner_map[i] - 1];
-+ }
-+
-+done:
-+ kfree(corner_map);
-+ return rc;
-+}
-+
-+/**
-+ * cpr3_enforce_inc_quotient_monotonicity() - Ensure that target quotients
-+ * increase monotonically from lower to higher corners
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static void cpr3_enforce_inc_quotient_monotonicity(struct cpr3_regulator *vreg)
-+{
-+ int i, j;
-+
-+ for (i = 1; i < vreg->corner_count; i++) {
-+ for (j = 0; j < CPR3_RO_COUNT; j++) {
-+ if (vreg->corner[i].target_quot[j]
-+ && vreg->corner[i].target_quot[j]
-+ < vreg->corner[i - 1].target_quot[j]) {
-+ cpr3_debug(vreg, "corner %d RO%u target quot=%u < corner %d RO%u target quot=%u; overriding: corner %d RO%u target quot=%u\n",
-+ i, j,
-+ vreg->corner[i].target_quot[j],
-+ i - 1, j,
-+ vreg->corner[i - 1].target_quot[j],
-+ i, j,
-+ vreg->corner[i - 1].target_quot[j]);
-+ vreg->corner[i].target_quot[j]
-+ = vreg->corner[i - 1].target_quot[j];
-+ }
-+ }
-+ }
-+}
-+
-+/**
-+ * cpr3_enforce_dec_quotient_monotonicity() - Ensure that target quotients
-+ * decrease monotonically from higher to lower corners
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static void cpr3_enforce_dec_quotient_monotonicity(struct cpr3_regulator *vreg)
-+{
-+ int i, j;
-+
-+ for (i = vreg->corner_count - 2; i >= 0; i--) {
-+ for (j = 0; j < CPR3_RO_COUNT; j++) {
-+ if (vreg->corner[i + 1].target_quot[j]
-+ && vreg->corner[i].target_quot[j]
-+ > vreg->corner[i + 1].target_quot[j]) {
-+ cpr3_debug(vreg, "corner %d RO%u target quot=%u > corner %d RO%u target quot=%u; overriding: corner %d RO%u target quot=%u\n",
-+ i, j,
-+ vreg->corner[i].target_quot[j],
-+ i + 1, j,
-+ vreg->corner[i + 1].target_quot[j],
-+ i, j,
-+ vreg->corner[i + 1].target_quot[j]);
-+ vreg->corner[i].target_quot[j]
-+ = vreg->corner[i + 1].target_quot[j];
-+ }
-+ }
-+ }
-+}
-+
-+/**
-+ * _cpr3_adjust_target_quotients() - adjust the target quotients for each
-+ * corner of the regulator according to input adjustment and
-+ * scaling arrays
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @volt_adjust: Pointer to an array of closed-loop voltage adjustments
-+ * with units of microvolts. The array must have
-+ * vreg->corner_count number of elements.
-+ * @ro_scale: Pointer to a flattened 2D array of RO scaling factors.
-+ * The array must have an inner dimension of CPR3_RO_COUNT
-+ * and an outer dimension of vreg->corner_count
-+ * @label: Null terminated string providing a label for the type
-+ * of adjustment.
-+ *
-+ * Return: true if any corners received a positive voltage adjustment (> 0),
-+ * else false
-+ */
-+static bool _cpr3_adjust_target_quotients(struct cpr3_regulator *vreg,
-+ const int *volt_adjust, const int *ro_scale, const char *label)
-+{
-+ int i, j, quot_adjust;
-+ bool is_increasing = false;
-+ u32 prev_quot;
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ for (j = 0; j < CPR3_RO_COUNT; j++) {
-+ if (vreg->corner[i].target_quot[j]) {
-+ quot_adjust = cpr3_quot_adjustment(
-+ ro_scale[i * CPR3_RO_COUNT + j],
-+ volt_adjust[i]);
-+ if (quot_adjust) {
-+ prev_quot = vreg->corner[i].
-+ target_quot[j];
-+ vreg->corner[i].target_quot[j]
-+ += quot_adjust;
-+ cpr3_debug(vreg, "adjusted corner %d RO%d target quot %s: %u --> %u (%d uV)\n",
-+ i, j, label, prev_quot,
-+ vreg->corner[i].target_quot[j],
-+ volt_adjust[i]);
-+ }
-+ }
-+ }
-+ if (volt_adjust[i] > 0)
-+ is_increasing = true;
-+ }
-+
-+ return is_increasing;
-+}
-+
-+/**
-+ * cpr3_adjust_target_quotients() - adjust the target quotients for each
-+ * corner according to device tree values and fuse values
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @fuse_volt_adjust: Fused closed-loop voltage adjustment values of length
-+ * vreg->fuse_corner_count. This parameter could be null
-+ * pointer when no fused adjustments are needed.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+int cpr3_adjust_target_quotients(struct cpr3_regulator *vreg,
-+ int *fuse_volt_adjust)
-+{
-+ int i, rc;
-+ int *volt_adjust, *ro_scale;
-+ bool explicit_adjustment, fused_adjustment, is_increasing;
-+
-+ explicit_adjustment = of_find_property(vreg->of_node,
-+ "qcom,cpr-closed-loop-voltage-adjustment", NULL);
-+ fused_adjustment = of_find_property(vreg->of_node,
-+ "qcom,cpr-fused-closed-loop-voltage-adjustment-map", NULL);
-+
-+ if (!explicit_adjustment && !fused_adjustment && !vreg->aging_allowed) {
-+ /* No adjustment required. */
-+ return 0;
-+ } else if (!of_find_property(vreg->of_node,
-+ "qcom,cpr-ro-scaling-factor", NULL)) {
-+ cpr3_err(vreg, "qcom,cpr-ro-scaling-factor is required for closed-loop voltage adjustment, but is missing\n");
-+ return -EINVAL;
-+ }
-+
-+ volt_adjust = kcalloc(vreg->corner_count, sizeof(*volt_adjust),
-+ GFP_KERNEL);
-+ ro_scale = kcalloc(vreg->corner_count * CPR3_RO_COUNT,
-+ sizeof(*ro_scale), GFP_KERNEL);
-+ if (!volt_adjust || !ro_scale) {
-+ rc = -ENOMEM;
-+ goto done;
-+ }
-+
-+ rc = cpr3_parse_corner_array_property(vreg,
-+ "qcom,cpr-ro-scaling-factor", CPR3_RO_COUNT, ro_scale);
-+ if (rc) {
-+ cpr3_err(vreg, "could not load RO scaling factors, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+
-+ for (i = 0; i < vreg->corner_count; i++)
-+ memcpy(vreg->corner[i].ro_scale, &ro_scale[i * CPR3_RO_COUNT],
-+ sizeof(*ro_scale) * CPR3_RO_COUNT);
-+
-+ if (explicit_adjustment) {
-+ rc = cpr3_parse_corner_array_property(vreg,
-+ "qcom,cpr-closed-loop-voltage-adjustment",
-+ 1, volt_adjust);
-+ if (rc) {
-+ cpr3_err(vreg, "could not load closed-loop voltage adjustments, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+
-+ _cpr3_adjust_target_quotients(vreg, volt_adjust, ro_scale,
-+ "from DT");
-+ cpr3_enforce_inc_quotient_monotonicity(vreg);
-+ }
-+
-+ if (fused_adjustment && fuse_volt_adjust) {
-+ memset(volt_adjust, 0,
-+ sizeof(*volt_adjust) * vreg->corner_count);
-+
-+ rc = cpr3_apply_closed_loop_offset_voltages(vreg, volt_adjust,
-+ fuse_volt_adjust);
-+ if (rc) {
-+ cpr3_err(vreg, "could not apply fused closed-loop voltage reductions, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+
-+ is_increasing = _cpr3_adjust_target_quotients(vreg, volt_adjust,
-+ ro_scale, "from fuse");
-+ if (is_increasing)
-+ cpr3_enforce_inc_quotient_monotonicity(vreg);
-+ else
-+ cpr3_enforce_dec_quotient_monotonicity(vreg);
-+ }
-+
-+done:
-+ kfree(volt_adjust);
-+ kfree(ro_scale);
-+ return rc;
-+}
---- /dev/null
-+++ b/drivers/regulator/cpr4-apss-regulator.c
-@@ -0,0 +1,1819 @@
-+/*
-+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#define pr_fmt(fmt) "%s: " fmt, __func__
-+
-+#include <linux/bitops.h>
-+#include <linux/debugfs.h>
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_opp.h>
-+#include <linux/slab.h>
-+#include <linux/string.h>
-+#include <linux/uaccess.h>
-+#include <linux/regulator/driver.h>
-+#include <linux/regulator/machine.h>
-+#include <linux/regulator/of_regulator.h>
-+
-+#include "cpr3-regulator.h"
-+
-+#define IPQ807x_APSS_FUSE_CORNERS 4
-+#define IPQ817x_APPS_FUSE_CORNERS 2
-+#define IPQ6018_APSS_FUSE_CORNERS 4
-+#define IPQ9574_APSS_FUSE_CORNERS 4
-+
-+u32 g_valid_fuse_count = IPQ807x_APSS_FUSE_CORNERS;
-+
-+/**
-+ * struct cpr4_ipq807x_apss_fuses - APSS specific fuse data for IPQ807x
-+ * @ro_sel: Ring oscillator select fuse parameter value for each
-+ * fuse corner
-+ * @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value
-+ * for each fuse corner (raw, not converted to a voltage)
-+ * @target_quot: CPR target quotient fuse parameter value for each fuse
-+ * corner
-+ * @quot_offset: CPR target quotient offset fuse parameter value for each
-+ * fuse corner (raw, not unpacked) used for target quotient
-+ * interpolation
-+ * @speed_bin: Application processor speed bin fuse parameter value for
-+ * the given chip
-+ * @cpr_fusing_rev: CPR fusing revision fuse parameter value
-+ * @boost_cfg: CPR boost configuration fuse parameter value
-+ * @boost_voltage: CPR boost voltage fuse parameter value (raw, not
-+ * converted to a voltage)
-+ *
-+ * This struct holds the values for all of the fuses read from memory.
-+ */
-+struct cpr4_ipq807x_apss_fuses {
-+ u64 ro_sel[IPQ807x_APSS_FUSE_CORNERS];
-+ u64 init_voltage[IPQ807x_APSS_FUSE_CORNERS];
-+ u64 target_quot[IPQ807x_APSS_FUSE_CORNERS];
-+ u64 quot_offset[IPQ807x_APSS_FUSE_CORNERS];
-+ u64 speed_bin;
-+ u64 cpr_fusing_rev;
-+ u64 boost_cfg;
-+ u64 boost_voltage;
-+ u64 misc;
-+};
-+
-+/*
-+ * fuse combo = fusing revision + 8 * (speed bin)
-+ * where: fusing revision = 0 - 7 and speed bin = 0 - 7
-+ */
-+#define CPR4_IPQ807x_APSS_FUSE_COMBO_COUNT 64
-+
-+/*
-+ * Constants which define the name of each fuse corner.
-+ */
-+enum cpr4_ipq807x_apss_fuse_corner {
-+ CPR4_IPQ807x_APSS_FUSE_CORNER_SVS = 0,
-+ CPR4_IPQ807x_APSS_FUSE_CORNER_NOM = 1,
-+ CPR4_IPQ807x_APSS_FUSE_CORNER_TURBO = 2,
-+ CPR4_IPQ807x_APSS_FUSE_CORNER_STURBO = 3,
-+};
-+
-+static const char * const cpr4_ipq807x_apss_fuse_corner_name[] = {
-+ [CPR4_IPQ807x_APSS_FUSE_CORNER_SVS] = "SVS",
-+ [CPR4_IPQ807x_APSS_FUSE_CORNER_NOM] = "NOM",
-+ [CPR4_IPQ807x_APSS_FUSE_CORNER_TURBO] = "TURBO",
-+ [CPR4_IPQ807x_APSS_FUSE_CORNER_STURBO] = "STURBO",
-+};
-+
-+/*
-+ * IPQ807x APSS fuse parameter locations:
-+ *
-+ * Structs are organized with the following dimensions:
-+ * Outer: 0 to 3 for fuse corners from lowest to highest corner
-+ * Inner: large enough to hold the longest set of parameter segments which
-+ * fully defines a fuse parameter, +1 (for NULL termination).
-+ * Each segment corresponds to a contiguous group of bits from a
-+ * single fuse row. These segments are concatentated together in
-+ * order to form the full fuse parameter value. The segments for
-+ * a given parameter may correspond to different fuse rows.
-+ */
-+static struct cpr3_fuse_param
-+ipq807x_apss_ro_sel_param[IPQ807x_APSS_FUSE_CORNERS][2] = {
-+ {{73, 8, 11}, {} },
-+ {{73, 4, 7}, {} },
-+ {{73, 0, 3}, {} },
-+ {{73, 12, 15}, {} },
-+};
-+
-+static struct cpr3_fuse_param
-+ipq807x_apss_init_voltage_param[IPQ807x_APSS_FUSE_CORNERS][2] = {
-+ {{71, 18, 23}, {} },
-+ {{71, 12, 17}, {} },
-+ {{71, 6, 11}, {} },
-+ {{71, 0, 5}, {} },
-+};
-+
-+static struct cpr3_fuse_param
-+ipq807x_apss_target_quot_param[IPQ807x_APSS_FUSE_CORNERS][2] = {
-+ {{72, 32, 43}, {} },
-+ {{72, 20, 31}, {} },
-+ {{72, 8, 19}, {} },
-+ {{72, 44, 55}, {} },
-+};
-+
-+static struct cpr3_fuse_param
-+ipq807x_apss_quot_offset_param[IPQ807x_APSS_FUSE_CORNERS][2] = {
-+ {{} },
-+ {{71, 46, 52}, {} },
-+ {{71, 39, 45}, {} },
-+ {{71, 32, 38}, {} },
-+};
-+
-+static struct cpr3_fuse_param ipq807x_cpr_fusing_rev_param[] = {
-+ {71, 53, 55},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq807x_apss_speed_bin_param[] = {
-+ {36, 40, 42},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq807x_cpr_boost_fuse_cfg_param[] = {
-+ {36, 43, 45},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq807x_apss_boost_fuse_volt_param[] = {
-+ {71, 0, 5},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq807x_misc_fuse_volt_adj_param[] = {
-+ {36, 54, 54},
-+ {},
-+};
-+
-+static struct cpr3_fuse_parameters ipq807x_fuse_params = {
-+ .apss_ro_sel_param = ipq807x_apss_ro_sel_param,
-+ .apss_init_voltage_param = ipq807x_apss_init_voltage_param,
-+ .apss_target_quot_param = ipq807x_apss_target_quot_param,
-+ .apss_quot_offset_param = ipq807x_apss_quot_offset_param,
-+ .cpr_fusing_rev_param = ipq807x_cpr_fusing_rev_param,
-+ .apss_speed_bin_param = ipq807x_apss_speed_bin_param,
-+ .cpr_boost_fuse_cfg_param = ipq807x_cpr_boost_fuse_cfg_param,
-+ .apss_boost_fuse_volt_param = ipq807x_apss_boost_fuse_volt_param,
-+ .misc_fuse_volt_adj_param = ipq807x_misc_fuse_volt_adj_param
-+};
-+
-+/*
-+ * The number of possible values for misc fuse is
-+ * 2^(#bits defined for misc fuse)
-+ */
-+#define IPQ807x_MISC_FUSE_VAL_COUNT BIT(1)
-+
-+/*
-+ * Open loop voltage fuse reference voltages in microvolts for IPQ807x
-+ */
-+static int ipq807x_apss_fuse_ref_volt
-+ [IPQ807x_APSS_FUSE_CORNERS] = {
-+ 720000,
-+ 864000,
-+ 992000,
-+ 1064000,
-+};
-+
-+#define IPQ807x_APSS_FUSE_STEP_VOLT 8000
-+#define IPQ807x_APSS_VOLTAGE_FUSE_SIZE 6
-+#define IPQ807x_APSS_QUOT_OFFSET_SCALE 5
-+
-+#define IPQ807x_APSS_CPR_SENSOR_COUNT 6
-+
-+#define IPQ807x_APSS_CPR_CLOCK_RATE 19200000
-+
-+#define IPQ807x_APSS_MAX_TEMP_POINTS 3
-+#define IPQ807x_APSS_TEMP_SENSOR_ID_START 4
-+#define IPQ807x_APSS_TEMP_SENSOR_ID_END 13
-+/*
-+ * Boost voltage fuse reference and ceiling voltages in microvolts for
-+ * IPQ807x.
-+ */
-+#define IPQ807x_APSS_BOOST_FUSE_REF_VOLT 1140000
-+#define IPQ807x_APSS_BOOST_CEILING_VOLT 1140000
-+#define IPQ807x_APSS_BOOST_FLOOR_VOLT 900000
-+#define MAX_BOOST_CONFIG_FUSE_VALUE 8
-+
-+#define IPQ807x_APSS_CPR_SDELTA_CORE_COUNT 15
-+
-+#define IPQ807x_APSS_CPR_TCSR_START 8
-+#define IPQ807x_APSS_CPR_TCSR_END 9
-+
-+/*
-+ * Array of integer values mapped to each of the boost config fuse values to
-+ * indicate boost enable/disable status.
-+ */
-+static bool boost_fuse[MAX_BOOST_CONFIG_FUSE_VALUE] = {0, 1, 1, 1, 1, 1, 1, 1};
-+
-+/*
-+ * IPQ6018 (Few parameters are changed, remaining are same as IPQ807x)
-+ */
-+#define IPQ6018_APSS_FUSE_STEP_VOLT 12500
-+#define IPQ6018_APSS_CPR_CLOCK_RATE 24000000
-+
-+static struct cpr3_fuse_param
-+ipq6018_apss_ro_sel_param[IPQ6018_APSS_FUSE_CORNERS][2] = {
-+ {{75, 8, 11}, {} },
-+ {{75, 4, 7}, {} },
-+ {{75, 0, 3}, {} },
-+ {{75, 12, 15}, {} },
-+};
-+
-+static struct cpr3_fuse_param
-+ipq6018_apss_init_voltage_param[IPQ6018_APSS_FUSE_CORNERS][2] = {
-+ {{73, 18, 23}, {} },
-+ {{73, 12, 17}, {} },
-+ {{73, 6, 11}, {} },
-+ {{73, 0, 5}, {} },
-+};
-+
-+static struct cpr3_fuse_param
-+ipq6018_apss_target_quot_param[IPQ6018_APSS_FUSE_CORNERS][2] = {
-+ {{74, 32, 43}, {} },
-+ {{74, 20, 31}, {} },
-+ {{74, 8, 19}, {} },
-+ {{74, 44, 55}, {} },
-+};
-+
-+static struct cpr3_fuse_param
-+ipq6018_apss_quot_offset_param[IPQ6018_APSS_FUSE_CORNERS][2] = {
-+ {{} },
-+ {{73, 48, 55}, {} },
-+ {{73, 40, 47}, {} },
-+ {{73, 32, 39}, {} },
-+};
-+
-+static struct cpr3_fuse_param ipq6018_cpr_fusing_rev_param[] = {
-+ {75, 16, 18},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq6018_apss_speed_bin_param[] = {
-+ {36, 40, 42},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq6018_cpr_boost_fuse_cfg_param[] = {
-+ {36, 43, 45},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq6018_apss_boost_fuse_volt_param[] = {
-+ {73, 0, 5},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq6018_misc_fuse_volt_adj_param[] = {
-+ {36, 54, 54},
-+ {},
-+};
-+
-+static struct cpr3_fuse_parameters ipq6018_fuse_params = {
-+ .apss_ro_sel_param = ipq6018_apss_ro_sel_param,
-+ .apss_init_voltage_param = ipq6018_apss_init_voltage_param,
-+ .apss_target_quot_param = ipq6018_apss_target_quot_param,
-+ .apss_quot_offset_param = ipq6018_apss_quot_offset_param,
-+ .cpr_fusing_rev_param = ipq6018_cpr_fusing_rev_param,
-+ .apss_speed_bin_param = ipq6018_apss_speed_bin_param,
-+ .cpr_boost_fuse_cfg_param = ipq6018_cpr_boost_fuse_cfg_param,
-+ .apss_boost_fuse_volt_param = ipq6018_apss_boost_fuse_volt_param,
-+ .misc_fuse_volt_adj_param = ipq6018_misc_fuse_volt_adj_param
-+};
-+
-+
-+/*
-+ * Boost voltage fuse reference and ceiling voltages in microvolts for
-+ * IPQ6018.
-+ */
-+#define IPQ6018_APSS_BOOST_FUSE_REF_VOLT 1140000
-+#define IPQ6018_APSS_BOOST_CEILING_VOLT 1140000
-+#define IPQ6018_APSS_BOOST_FLOOR_VOLT 900000
-+
-+/*
-+ * Open loop voltage fuse reference voltages in microvolts for IPQ807x
-+ */
-+static int ipq6018_apss_fuse_ref_volt
-+ [IPQ6018_APSS_FUSE_CORNERS] = {
-+ 725000,
-+ 862500,
-+ 987500,
-+ 1062500,
-+};
-+
-+/*
-+ * IPQ6018 Memory ACC settings on TCSR
-+ *
-+ * Turbo_L1: write TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0 0x10
-+ * write TCSR_CUSTOM_VDDAPC0_ACC_1 0x1
-+ * Other modes: write TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0 0x0
-+ * write TCSR_CUSTOM_VDDAPC0_ACC_1 0x0
-+ *
-+ */
-+#define IPQ6018_APSS_MEM_ACC_TCSR_COUNT 2
-+#define TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0 0x1946178
-+#define TCSR_CUSTOM_VDDAPC0_ACC_1 0x1946124
-+
-+struct mem_acc_tcsr {
-+ u32 phy_addr;
-+ void __iomem *ioremap_addr;
-+ u32 value;
-+};
-+
-+static struct mem_acc_tcsr ipq6018_mem_acc_tcsr[IPQ6018_APSS_MEM_ACC_TCSR_COUNT] = {
-+ {TCSR_MEM_ACC_SW_OVERRIDE_LEGACY_APC0, NULL, 0x10},
-+ {TCSR_CUSTOM_VDDAPC0_ACC_1, NULL, 0x1},
-+};
-+
-+/*
-+ * IPQ9574 (Few parameters are changed, remaining are same as IPQ6018)
-+ */
-+#define IPQ9574_APSS_FUSE_STEP_VOLT 10000
-+
-+static struct cpr3_fuse_param
-+ipq9574_apss_ro_sel_param[IPQ9574_APSS_FUSE_CORNERS][2] = {
-+ {{107, 4, 7}, {} },
-+ {{107, 0, 3}, {} },
-+ {{106, 4, 7}, {} },
-+ {{106, 0, 3}, {} },
-+};
-+
-+static struct cpr3_fuse_param
-+ipq9574_apss_init_voltage_param[IPQ9574_APSS_FUSE_CORNERS][2] = {
-+ {{104, 24, 29}, {} },
-+ {{104, 18, 23}, {} },
-+ {{104, 12, 17}, {} },
-+ {{104, 6, 11}, {} },
-+};
-+
-+static struct cpr3_fuse_param
-+ipq9574_apss_target_quot_param[IPQ9574_APSS_FUSE_CORNERS][2] = {
-+ {{106, 32, 43}, {} },
-+ {{106, 20, 31}, {} },
-+ {{106, 8, 19}, {} },
-+ {{106, 44, 55}, {} },
-+};
-+
-+static struct cpr3_fuse_param
-+ipq9574_apss_quot_offset_param[IPQ9574_APSS_FUSE_CORNERS][2] = {
-+ {{} },
-+ {{105, 48, 55}, {} },
-+ {{105, 40, 47}, {} },
-+ {{105, 32, 39}, {} },
-+};
-+
-+static struct cpr3_fuse_param ipq9574_cpr_fusing_rev_param[] = {
-+ {107, 8, 10},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq9574_apss_speed_bin_param[] = {
-+ {0, 40, 42},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq9574_cpr_boost_fuse_cfg_param[] = {
-+ {0, 43, 45},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq9574_apss_boost_fuse_volt_param[] = {
-+ {104, 0, 5},
-+ {},
-+};
-+
-+static struct cpr3_fuse_param ipq9574_misc_fuse_volt_adj_param[] = {
-+ {0, 54, 54},
-+ {},
-+};
-+
-+static struct cpr3_fuse_parameters ipq9574_fuse_params = {
-+ .apss_ro_sel_param = ipq9574_apss_ro_sel_param,
-+ .apss_init_voltage_param = ipq9574_apss_init_voltage_param,
-+ .apss_target_quot_param = ipq9574_apss_target_quot_param,
-+ .apss_quot_offset_param = ipq9574_apss_quot_offset_param,
-+ .cpr_fusing_rev_param = ipq9574_cpr_fusing_rev_param,
-+ .apss_speed_bin_param = ipq9574_apss_speed_bin_param,
-+ .cpr_boost_fuse_cfg_param = ipq9574_cpr_boost_fuse_cfg_param,
-+ .apss_boost_fuse_volt_param = ipq9574_apss_boost_fuse_volt_param,
-+ .misc_fuse_volt_adj_param = ipq9574_misc_fuse_volt_adj_param
-+};
-+
-+/*
-+ * Open loop voltage fuse reference voltages in microvolts for IPQ9574
-+ */
-+static int ipq9574_apss_fuse_ref_volt
-+ [IPQ9574_APSS_FUSE_CORNERS] = {
-+ 725000,
-+ 862500,
-+ 987500,
-+ 1062500,
-+};
-+
-+/**
-+ * cpr4_ipq807x_apss_read_fuse_data() - load APSS specific fuse parameter values
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * This function allocates a cpr4_ipq807x_apss_fuses struct, fills it with
-+ * values read out of hardware fuses, and finally copies common fuse values
-+ * into the CPR3 regulator struct.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_ipq807x_apss_read_fuse_data(struct cpr3_regulator *vreg)
-+{
-+ void __iomem *base = vreg->thread->ctrl->fuse_base;
-+ struct cpr4_ipq807x_apss_fuses *fuse;
-+ int i, rc;
-+
-+ fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL);
-+ if (!fuse)
-+ return -ENOMEM;
-+
-+ rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->apss_speed_bin_param,
-+ &fuse->speed_bin);
-+ if (rc) {
-+ cpr3_err(vreg, "Unable to read speed bin fuse, rc=%d\n", rc);
-+ return rc;
-+ }
-+ cpr3_info(vreg, "speed bin = %llu\n", fuse->speed_bin);
-+
-+ rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->cpr_fusing_rev_param,
-+ &fuse->cpr_fusing_rev);
-+ if (rc) {
-+ cpr3_err(vreg, "Unable to read CPR fusing revision fuse, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev);
-+
-+ rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->misc_fuse_volt_adj_param,
-+ &fuse->misc);
-+ if (rc) {
-+ cpr3_err(vreg, "Unable to read misc voltage adjustment fuse, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ cpr3_info(vreg, "CPR misc fuse value = %llu\n", fuse->misc);
-+ if (fuse->misc >= IPQ807x_MISC_FUSE_VAL_COUNT) {
-+ cpr3_err(vreg, "CPR misc fuse value = %llu, should be < %lu\n",
-+ fuse->misc, IPQ807x_MISC_FUSE_VAL_COUNT);
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < g_valid_fuse_count; i++) {
-+ rc = cpr3_read_fuse_param(base,
-+ vreg->cpr4_regulator_data->cpr3_fuse_params->apss_init_voltage_param[i],
-+ &fuse->init_voltage[i]);
-+ if (rc) {
-+ cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n",
-+ i, rc);
-+ return rc;
-+ }
-+
-+ rc = cpr3_read_fuse_param(base,
-+ vreg->cpr4_regulator_data->cpr3_fuse_params->apss_target_quot_param[i],
-+ &fuse->target_quot[i]);
-+ if (rc) {
-+ cpr3_err(vreg, "Unable to read fuse-corner %d target quotient fuse, rc=%d\n",
-+ i, rc);
-+ return rc;
-+ }
-+
-+ rc = cpr3_read_fuse_param(base,
-+ vreg->cpr4_regulator_data->cpr3_fuse_params->apss_ro_sel_param[i],
-+ &fuse->ro_sel[i]);
-+ if (rc) {
-+ cpr3_err(vreg, "Unable to read fuse-corner %d RO select fuse, rc=%d\n",
-+ i, rc);
-+ return rc;
-+ }
-+
-+ rc = cpr3_read_fuse_param(base,
-+ vreg->cpr4_regulator_data->cpr3_fuse_params->apss_quot_offset_param[i],
-+ &fuse->quot_offset[i]);
-+ if (rc) {
-+ cpr3_err(vreg, "Unable to read fuse-corner %d quotient offset fuse, rc=%d\n",
-+ i, rc);
-+ return rc;
-+ }
-+ }
-+
-+ rc = cpr3_read_fuse_param(base, vreg->cpr4_regulator_data->cpr3_fuse_params->cpr_boost_fuse_cfg_param,
-+ &fuse->boost_cfg);
-+ if (rc) {
-+ cpr3_err(vreg, "Unable to read CPR boost config fuse, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ cpr3_info(vreg, "Voltage boost fuse config = %llu boost = %s\n",
-+ fuse->boost_cfg, boost_fuse[fuse->boost_cfg]
-+ ? "enable" : "disable");
-+
-+ rc = cpr3_read_fuse_param(base,
-+ vreg->cpr4_regulator_data->cpr3_fuse_params->apss_boost_fuse_volt_param,
-+ &fuse->boost_voltage);
-+ if (rc) {
-+ cpr3_err(vreg, "failed to read boost fuse voltage, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ vreg->fuse_combo = fuse->cpr_fusing_rev + 8 * fuse->speed_bin;
-+ if (vreg->fuse_combo >= CPR4_IPQ807x_APSS_FUSE_COMBO_COUNT) {
-+ cpr3_err(vreg, "invalid CPR fuse combo = %d found\n",
-+ vreg->fuse_combo);
-+ return -EINVAL;
-+ }
-+
-+ vreg->speed_bin_fuse = fuse->speed_bin;
-+ vreg->cpr_rev_fuse = fuse->cpr_fusing_rev;
-+ vreg->fuse_corner_count = g_valid_fuse_count;
-+ vreg->platform_fuses = fuse;
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr4_apss_parse_corner_data() - parse APSS corner data from device tree
-+ * properties of the CPR3 regulator's device node
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_apss_parse_corner_data(struct cpr3_regulator *vreg)
-+{
-+ struct device_node *node = vreg->of_node;
-+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses;
-+ u32 *temp = NULL;
-+ int i, rc;
-+
-+ rc = cpr3_parse_common_corner_data(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading corner data, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ /* If fuse has incorrect RO Select values and dtsi has "qcom,cpr-ro-sel"
-+ * entry with RO select values other than zero, then dtsi values will
-+ * be used.
-+ */
-+ if (of_find_property(node, "qcom,cpr-ro-sel", NULL)) {
-+ temp = kcalloc(vreg->fuse_corner_count, sizeof(*temp),
-+ GFP_KERNEL);
-+ if (!temp)
-+ return -ENOMEM;
-+
-+ rc = cpr3_parse_array_property(vreg, "qcom,cpr-ro-sel",
-+ vreg->fuse_corner_count, temp);
-+ if (rc)
-+ goto done;
-+
-+ for (i = 0; i < vreg->fuse_corner_count; i++) {
-+ if (temp[i] != 0)
-+ fuse->ro_sel[i] = temp[i];
-+ }
-+ }
-+done:
-+ kfree(temp);
-+ return rc;
-+}
-+
-+/**
-+ * cpr4_apss_parse_misc_fuse_voltage_adjustments() - fill an array from a
-+ * portion of the voltage adjustments specified based on
-+ * miscellaneous fuse bits.
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @volt_adjust: Voltage adjustment output data array which must be
-+ * of size vreg->corner_count
-+ *
-+ * cpr3_parse_common_corner_data() must be called for vreg before this function
-+ * is called so that speed bin size elements are initialized.
-+ *
-+ * Two formats are supported for the device tree property:
-+ * 1. Length == tuple_list_size * vreg->corner_count
-+ * (reading begins at index 0)
-+ * 2. Length == tuple_list_size * vreg->speed_bin_corner_sum
-+ * (reading begins at index tuple_list_size * vreg->speed_bin_offset)
-+ *
-+ * Here, tuple_list_size is the number of possible values for misc fuse.
-+ * All other property lengths are treated as errors.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_apss_parse_misc_fuse_voltage_adjustments(
-+ struct cpr3_regulator *vreg, u32 *volt_adjust)
-+{
-+ struct device_node *node = vreg->of_node;
-+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses;
-+ int tuple_list_size = IPQ807x_MISC_FUSE_VAL_COUNT;
-+ int i, offset, rc, len = 0;
-+ const char *prop_name = "qcom,cpr-misc-fuse-voltage-adjustment";
-+
-+ if (!of_find_property(node, prop_name, &len)) {
-+ cpr3_err(vreg, "property %s is missing\n", prop_name);
-+ return -EINVAL;
-+ }
-+
-+ if (len == tuple_list_size * vreg->corner_count * sizeof(u32)) {
-+ offset = 0;
-+ } else if (vreg->speed_bin_corner_sum > 0 &&
-+ len == tuple_list_size * vreg->speed_bin_corner_sum
-+ * sizeof(u32)) {
-+ offset = tuple_list_size * vreg->speed_bin_offset
-+ + fuse->misc * vreg->corner_count;
-+ } else {
-+ if (vreg->speed_bin_corner_sum > 0)
-+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu or %zu\n",
-+ prop_name, len,
-+ tuple_list_size * vreg->corner_count
-+ * sizeof(u32),
-+ tuple_list_size * vreg->speed_bin_corner_sum
-+ * sizeof(u32));
-+ else
-+ cpr3_err(vreg, "property %s has invalid length=%d, should be %zu\n",
-+ prop_name, len,
-+ tuple_list_size * vreg->corner_count
-+ * sizeof(u32));
-+ return -EINVAL;
-+ }
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ rc = of_property_read_u32_index(node, prop_name, offset + i,
-+ &volt_adjust[i]);
-+ if (rc) {
-+ cpr3_err(vreg, "error reading property %s, rc=%d\n",
-+ prop_name, rc);
-+ return rc;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr4_ipq807x_apss_calculate_open_loop_voltages() - calculate the open-loop
-+ * voltage for each corner of a CPR3 regulator
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * If open-loop voltage interpolation is allowed in device tree, then
-+ * this function calculates the open-loop voltage for a given corner using
-+ * linear interpolation. This interpolation is performed using the processor
-+ * frequencies of the lower and higher Fmax corners along with their fused
-+ * open-loop voltages.
-+ *
-+ * If open-loop voltage interpolation is not allowed, then this function uses
-+ * the Fmax fused open-loop voltage for all of the corners associated with a
-+ * given fuse corner.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_ipq807x_apss_calculate_open_loop_voltages(
-+ struct cpr3_regulator *vreg)
-+{
-+ struct device_node *node = vreg->of_node;
-+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses;
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ int i, j, rc = 0;
-+ bool allow_interpolation;
-+ u64 freq_low, volt_low, freq_high, volt_high;
-+ int *fuse_volt, *misc_adj_volt;
-+ int *fmax_corner;
-+
-+ fuse_volt = kcalloc(vreg->fuse_corner_count, sizeof(*fuse_volt),
-+ GFP_KERNEL);
-+ fmax_corner = kcalloc(vreg->fuse_corner_count, sizeof(*fmax_corner),
-+ GFP_KERNEL);
-+ if (!fuse_volt || !fmax_corner) {
-+ rc = -ENOMEM;
-+ goto done;
-+ }
-+
-+ for (i = 0; i < vreg->fuse_corner_count; i++) {
-+ if (ctrl->cpr_global_setting == CPR_DISABLED)
-+ fuse_volt[i] = vreg->cpr4_regulator_data->fuse_ref_volt[i];
-+ else
-+ fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(
-+ vreg->cpr4_regulator_data->fuse_ref_volt[i],
-+ vreg->cpr4_regulator_data->fuse_step_volt,
-+ fuse->init_voltage[i],
-+ IPQ807x_APSS_VOLTAGE_FUSE_SIZE);
-+
-+ /* Log fused open-loop voltage values for debugging purposes. */
-+ cpr3_info(vreg, "fused %8s: open-loop=%7d uV\n",
-+ cpr4_ipq807x_apss_fuse_corner_name[i],
-+ fuse_volt[i]);
-+ }
-+
-+ rc = cpr3_determine_part_type(vreg,
-+ fuse_volt[vreg->fuse_corner_count - 1]);
-+ if (rc) {
-+ cpr3_err(vreg, "fused part type detection failed failed, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+
-+ rc = cpr3_adjust_fused_open_loop_voltages(vreg, fuse_volt);
-+ if (rc) {
-+ cpr3_err(vreg, "fused open-loop voltage adjustment failed, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+
-+ allow_interpolation = of_property_read_bool(node,
-+ "qcom,allow-voltage-interpolation");
-+
-+ for (i = 1; i < vreg->fuse_corner_count; i++) {
-+ if (fuse_volt[i] < fuse_volt[i - 1]) {
-+ cpr3_info(vreg, "fuse corner %d voltage=%d uV < fuse corner %d voltage=%d uV; overriding: fuse corner %d voltage=%d\n",
-+ i, fuse_volt[i], i - 1, fuse_volt[i - 1],
-+ i, fuse_volt[i - 1]);
-+ fuse_volt[i] = fuse_volt[i - 1];
-+ }
-+ }
-+
-+ if (!allow_interpolation) {
-+ /* Use fused open-loop voltage for lower frequencies. */
-+ for (i = 0; i < vreg->corner_count; i++)
-+ vreg->corner[i].open_loop_volt
-+ = fuse_volt[vreg->corner[i].cpr_fuse_corner];
-+ goto done;
-+ }
-+
-+ /* Determine highest corner mapped to each fuse corner */
-+ j = vreg->fuse_corner_count - 1;
-+ for (i = vreg->corner_count - 1; i >= 0; i--) {
-+ if (vreg->corner[i].cpr_fuse_corner == j) {
-+ fmax_corner[j] = i;
-+ j--;
-+ }
-+ }
-+ if (j >= 0) {
-+ cpr3_err(vreg, "invalid fuse corner mapping\n");
-+ rc = -EINVAL;
-+ goto done;
-+ }
-+
-+ /*
-+ * Interpolation is not possible for corners mapped to the lowest fuse
-+ * corner so use the fuse corner value directly.
-+ */
-+ for (i = 0; i <= fmax_corner[0]; i++)
-+ vreg->corner[i].open_loop_volt = fuse_volt[0];
-+
-+ /* Interpolate voltages for the higher fuse corners. */
-+ for (i = 1; i < vreg->fuse_corner_count; i++) {
-+ freq_low = vreg->corner[fmax_corner[i - 1]].proc_freq;
-+ volt_low = fuse_volt[i - 1];
-+ freq_high = vreg->corner[fmax_corner[i]].proc_freq;
-+ volt_high = fuse_volt[i];
-+
-+ for (j = fmax_corner[i - 1] + 1; j <= fmax_corner[i]; j++)
-+ vreg->corner[j].open_loop_volt = cpr3_interpolate(
-+ freq_low, volt_low, freq_high, volt_high,
-+ vreg->corner[j].proc_freq);
-+ }
-+
-+done:
-+ if (rc == 0) {
-+ cpr3_debug(vreg, "unadjusted per-corner open-loop voltages:\n");
-+ for (i = 0; i < vreg->corner_count; i++)
-+ cpr3_debug(vreg, "open-loop[%2d] = %d uV\n", i,
-+ vreg->corner[i].open_loop_volt);
-+
-+ rc = cpr3_adjust_open_loop_voltages(vreg);
-+ if (rc)
-+ cpr3_err(vreg, "open-loop voltage adjustment failed, rc=%d\n",
-+ rc);
-+
-+ if (of_find_property(node,
-+ "qcom,cpr-misc-fuse-voltage-adjustment",
-+ NULL)) {
-+ misc_adj_volt = kcalloc(vreg->corner_count,
-+ sizeof(*misc_adj_volt), GFP_KERNEL);
-+ if (!misc_adj_volt) {
-+ rc = -ENOMEM;
-+ goto _exit;
-+ }
-+
-+ rc = cpr4_apss_parse_misc_fuse_voltage_adjustments(vreg,
-+ misc_adj_volt);
-+ if (rc) {
-+ cpr3_err(vreg, "qcom,cpr-misc-fuse-voltage-adjustment reading failed, rc=%d\n",
-+ rc);
-+ kfree(misc_adj_volt);
-+ goto _exit;
-+ }
-+
-+ for (i = 0; i < vreg->corner_count; i++)
-+ vreg->corner[i].open_loop_volt
-+ += misc_adj_volt[i];
-+ kfree(misc_adj_volt);
-+ }
-+ }
-+
-+_exit:
-+ kfree(fuse_volt);
-+ kfree(fmax_corner);
-+ return rc;
-+}
-+
-+/**
-+ * cpr4_ipq807x_apss_set_no_interpolation_quotients() - use the fused target
-+ * quotient values for lower frequencies.
-+ * @vreg: Pointer to the CPR3 regulator
-+ * @volt_adjust: Pointer to array of per-corner closed-loop adjustment
-+ * voltages
-+ * @volt_adjust_fuse: Pointer to array of per-fuse-corner closed-loop
-+ * adjustment voltages
-+ * @ro_scale: Pointer to array of per-fuse-corner RO scaling factor
-+ * values with units of QUOT/V
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_ipq807x_apss_set_no_interpolation_quotients(
-+ struct cpr3_regulator *vreg, int *volt_adjust,
-+ int *volt_adjust_fuse, int *ro_scale)
-+{
-+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses;
-+ u32 quot, ro;
-+ int quot_adjust;
-+ int i, fuse_corner;
-+
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ fuse_corner = vreg->corner[i].cpr_fuse_corner;
-+ quot = fuse->target_quot[fuse_corner];
-+ quot_adjust = cpr3_quot_adjustment(ro_scale[fuse_corner],
-+ volt_adjust_fuse[fuse_corner] +
-+ volt_adjust[i]);
-+ ro = fuse->ro_sel[fuse_corner];
-+ vreg->corner[i].target_quot[ro] = quot + quot_adjust;
-+ cpr3_debug(vreg, "corner=%d RO=%u target quot=%u\n",
-+ i, ro, quot);
-+
-+ if (quot_adjust)
-+ cpr3_debug(vreg, "adjusted corner %d RO%u target quot: %u --> %u (%d uV)\n",
-+ i, ro, quot, vreg->corner[i].target_quot[ro],
-+ volt_adjust_fuse[fuse_corner] +
-+ volt_adjust[i]);
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr4_ipq807x_apss_calculate_target_quotients() - calculate the CPR target
-+ * quotient for each corner of a CPR3 regulator
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * If target quotient interpolation is allowed in device tree, then this
-+ * function calculates the target quotient for a given corner using linear
-+ * interpolation. This interpolation is performed using the processor
-+ * frequencies of the lower and higher Fmax corners along with the fused
-+ * target quotient and quotient offset of the higher Fmax corner.
-+ *
-+ * If target quotient interpolation is not allowed, then this function uses
-+ * the Fmax fused target quotient for all of the corners associated with a
-+ * given fuse corner.
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_ipq807x_apss_calculate_target_quotients(
-+ struct cpr3_regulator *vreg)
-+{
-+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses;
-+ int rc;
-+ bool allow_interpolation;
-+ u64 freq_low, freq_high, prev_quot;
-+ u64 *quot_low;
-+ u64 *quot_high;
-+ u32 quot, ro;
-+ int i, j, fuse_corner, quot_adjust;
-+ int *fmax_corner;
-+ int *volt_adjust, *volt_adjust_fuse, *ro_scale;
-+ int *voltage_adj_misc;
-+
-+ /* Log fused quotient values for debugging purposes. */
-+ for (i = CPR4_IPQ807x_APSS_FUSE_CORNER_SVS;
-+ i < vreg->fuse_corner_count; i++)
-+ cpr3_info(vreg, "fused %8s: quot[%2llu]=%4llu, quot_offset[%2llu]=%4llu\n",
-+ cpr4_ipq807x_apss_fuse_corner_name[i],
-+ fuse->ro_sel[i], fuse->target_quot[i],
-+ fuse->ro_sel[i], fuse->quot_offset[i] *
-+ IPQ807x_APSS_QUOT_OFFSET_SCALE);
-+
-+ allow_interpolation = of_property_read_bool(vreg->of_node,
-+ "qcom,allow-quotient-interpolation");
-+
-+ volt_adjust = kcalloc(vreg->corner_count, sizeof(*volt_adjust),
-+ GFP_KERNEL);
-+ volt_adjust_fuse = kcalloc(vreg->fuse_corner_count,
-+ sizeof(*volt_adjust_fuse), GFP_KERNEL);
-+ ro_scale = kcalloc(vreg->fuse_corner_count, sizeof(*ro_scale),
-+ GFP_KERNEL);
-+ fmax_corner = kcalloc(vreg->fuse_corner_count, sizeof(*fmax_corner),
-+ GFP_KERNEL);
-+ quot_low = kcalloc(vreg->fuse_corner_count, sizeof(*quot_low),
-+ GFP_KERNEL);
-+ quot_high = kcalloc(vreg->fuse_corner_count, sizeof(*quot_high),
-+ GFP_KERNEL);
-+ if (!volt_adjust || !volt_adjust_fuse || !ro_scale ||
-+ !fmax_corner || !quot_low || !quot_high) {
-+ rc = -ENOMEM;
-+ goto done;
-+ }
-+
-+ rc = cpr3_parse_closed_loop_voltage_adjustments(vreg, &fuse->ro_sel[0],
-+ volt_adjust, volt_adjust_fuse, ro_scale);
-+ if (rc) {
-+ cpr3_err(vreg, "could not load closed-loop voltage adjustments, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+
-+ if (of_find_property(vreg->of_node,
-+ "qcom,cpr-misc-fuse-voltage-adjustment", NULL)) {
-+ voltage_adj_misc = kcalloc(vreg->corner_count,
-+ sizeof(*voltage_adj_misc), GFP_KERNEL);
-+ if (!voltage_adj_misc) {
-+ rc = -ENOMEM;
-+ goto done;
-+ }
-+
-+ rc = cpr4_apss_parse_misc_fuse_voltage_adjustments(vreg,
-+ voltage_adj_misc);
-+ if (rc) {
-+ cpr3_err(vreg, "qcom,cpr-misc-fuse-voltage-adjustment reading failed, rc=%d\n",
-+ rc);
-+ kfree(voltage_adj_misc);
-+ goto done;
-+ }
-+
-+ for (i = 0; i < vreg->corner_count; i++)
-+ volt_adjust[i] += voltage_adj_misc[i];
-+
-+ kfree(voltage_adj_misc);
-+ }
-+
-+ if (!allow_interpolation) {
-+ /* Use fused target quotients for lower frequencies. */
-+ return cpr4_ipq807x_apss_set_no_interpolation_quotients(
-+ vreg, volt_adjust, volt_adjust_fuse, ro_scale);
-+ }
-+
-+ /* Determine highest corner mapped to each fuse corner */
-+ j = vreg->fuse_corner_count - 1;
-+ for (i = vreg->corner_count - 1; i >= 0; i--) {
-+ if (vreg->corner[i].cpr_fuse_corner == j) {
-+ fmax_corner[j] = i;
-+ j--;
-+ }
-+ }
-+ if (j >= 0) {
-+ cpr3_err(vreg, "invalid fuse corner mapping\n");
-+ rc = -EINVAL;
-+ goto done;
-+ }
-+
-+ /*
-+ * Interpolation is not possible for corners mapped to the lowest fuse
-+ * corner so use the fuse corner value directly.
-+ */
-+ i = CPR4_IPQ807x_APSS_FUSE_CORNER_SVS;
-+ quot_adjust = cpr3_quot_adjustment(ro_scale[i], volt_adjust_fuse[i]);
-+ quot = fuse->target_quot[i] + quot_adjust;
-+ quot_high[i] = quot_low[i] = quot;
-+ ro = fuse->ro_sel[i];
-+ if (quot_adjust)
-+ cpr3_debug(vreg, "adjusted fuse corner %d RO%u target quot: %llu --> %u (%d uV)\n",
-+ i, ro, fuse->target_quot[i], quot, volt_adjust_fuse[i]);
-+
-+ for (i = 0; i <= fmax_corner[CPR4_IPQ807x_APSS_FUSE_CORNER_SVS];
-+ i++)
-+ vreg->corner[i].target_quot[ro] = quot;
-+
-+ for (i = CPR4_IPQ807x_APSS_FUSE_CORNER_NOM;
-+ i < vreg->fuse_corner_count; i++) {
-+ quot_high[i] = fuse->target_quot[i];
-+ if (fuse->ro_sel[i] == fuse->ro_sel[i - 1])
-+ quot_low[i] = quot_high[i - 1];
-+ else
-+ quot_low[i] = quot_high[i]
-+ - fuse->quot_offset[i]
-+ * IPQ807x_APSS_QUOT_OFFSET_SCALE;
-+ if (quot_high[i] < quot_low[i]) {
-+ cpr3_debug(vreg, "quot_high[%d]=%llu < quot_low[%d]=%llu; overriding: quot_high[%d]=%llu\n",
-+ i, quot_high[i], i, quot_low[i],
-+ i, quot_low[i]);
-+ quot_high[i] = quot_low[i];
-+ }
-+ }
-+
-+ /* Perform per-fuse-corner target quotient adjustment */
-+ for (i = 1; i < vreg->fuse_corner_count; i++) {
-+ quot_adjust = cpr3_quot_adjustment(ro_scale[i],
-+ volt_adjust_fuse[i]);
-+ if (quot_adjust) {
-+ prev_quot = quot_high[i];
-+ quot_high[i] += quot_adjust;
-+ cpr3_debug(vreg, "adjusted fuse corner %d RO%llu target quot: %llu --> %llu (%d uV)\n",
-+ i, fuse->ro_sel[i], prev_quot, quot_high[i],
-+ volt_adjust_fuse[i]);
-+ }
-+
-+ if (fuse->ro_sel[i] == fuse->ro_sel[i - 1])
-+ quot_low[i] = quot_high[i - 1];
-+ else
-+ quot_low[i] += cpr3_quot_adjustment(ro_scale[i],
-+ volt_adjust_fuse[i - 1]);
-+
-+ if (quot_high[i] < quot_low[i]) {
-+ cpr3_debug(vreg, "quot_high[%d]=%llu < quot_low[%d]=%llu after adjustment; overriding: quot_high[%d]=%llu\n",
-+ i, quot_high[i], i, quot_low[i],
-+ i, quot_low[i]);
-+ quot_high[i] = quot_low[i];
-+ }
-+ }
-+
-+ /* Interpolate voltages for the higher fuse corners. */
-+ for (i = 1; i < vreg->fuse_corner_count; i++) {
-+ freq_low = vreg->corner[fmax_corner[i - 1]].proc_freq;
-+ freq_high = vreg->corner[fmax_corner[i]].proc_freq;
-+
-+ ro = fuse->ro_sel[i];
-+ for (j = fmax_corner[i - 1] + 1; j <= fmax_corner[i]; j++)
-+ vreg->corner[j].target_quot[ro] = cpr3_interpolate(
-+ freq_low, quot_low[i], freq_high, quot_high[i],
-+ vreg->corner[j].proc_freq);
-+ }
-+
-+ /* Perform per-corner target quotient adjustment */
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ fuse_corner = vreg->corner[i].cpr_fuse_corner;
-+ ro = fuse->ro_sel[fuse_corner];
-+ quot_adjust = cpr3_quot_adjustment(ro_scale[fuse_corner],
-+ volt_adjust[i]);
-+ if (quot_adjust) {
-+ prev_quot = vreg->corner[i].target_quot[ro];
-+ vreg->corner[i].target_quot[ro] += quot_adjust;
-+ cpr3_debug(vreg, "adjusted corner %d RO%u target quot: %llu --> %u (%d uV)\n",
-+ i, ro, prev_quot,
-+ vreg->corner[i].target_quot[ro],
-+ volt_adjust[i]);
-+ }
-+ }
-+
-+ /* Ensure that target quotients increase monotonically */
-+ for (i = 1; i < vreg->corner_count; i++) {
-+ ro = fuse->ro_sel[vreg->corner[i].cpr_fuse_corner];
-+ if (fuse->ro_sel[vreg->corner[i - 1].cpr_fuse_corner] == ro
-+ && vreg->corner[i].target_quot[ro]
-+ < vreg->corner[i - 1].target_quot[ro]) {
-+ cpr3_debug(vreg, "adjusted corner %d RO%u target quot=%u < adjusted corner %d RO%u target quot=%u; overriding: corner %d RO%u target quot=%u\n",
-+ i, ro, vreg->corner[i].target_quot[ro],
-+ i - 1, ro, vreg->corner[i - 1].target_quot[ro],
-+ i, ro, vreg->corner[i - 1].target_quot[ro]);
-+ vreg->corner[i].target_quot[ro]
-+ = vreg->corner[i - 1].target_quot[ro];
-+ }
-+ }
-+
-+done:
-+ kfree(volt_adjust);
-+ kfree(volt_adjust_fuse);
-+ kfree(ro_scale);
-+ kfree(fmax_corner);
-+ kfree(quot_low);
-+ kfree(quot_high);
-+ return rc;
-+}
-+
-+/**
-+ * cpr4_apss_print_settings() - print out APSS CPR configuration settings into
-+ * the kernel log for debugging purposes
-+ * @vreg: Pointer to the CPR3 regulator
-+ */
-+static void cpr4_apss_print_settings(struct cpr3_regulator *vreg)
-+{
-+ struct cpr3_corner *corner;
-+ int i;
-+
-+ cpr3_debug(vreg, "Corner: Frequency (Hz), Fuse Corner, Floor (uV), Open-Loop (uV), Ceiling (uV)\n");
-+ for (i = 0; i < vreg->corner_count; i++) {
-+ corner = &vreg->corner[i];
-+ cpr3_debug(vreg, "%3d: %10u, %2d, %7d, %7d, %7d\n",
-+ i, corner->proc_freq, corner->cpr_fuse_corner,
-+ corner->floor_volt, corner->open_loop_volt,
-+ corner->ceiling_volt);
-+ }
-+
-+ if (vreg->thread->ctrl->apm)
-+ cpr3_debug(vreg, "APM threshold = %d uV, APM adjust = %d uV\n",
-+ vreg->thread->ctrl->apm_threshold_volt,
-+ vreg->thread->ctrl->apm_adj_volt);
-+}
-+
-+/**
-+ * cpr4_apss_init_thread() - perform steps necessary to initialize the
-+ * configuration data for a CPR3 thread
-+ * @thread: Pointer to the CPR3 thread
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_apss_init_thread(struct cpr3_thread *thread)
-+{
-+ int rc;
-+
-+ rc = cpr3_parse_common_thread_data(thread);
-+ if (rc) {
-+ cpr3_err(thread->ctrl, "thread %u unable to read CPR thread data from device tree, rc=%d\n",
-+ thread->thread_id, rc);
-+ return rc;
-+ }
-+
-+ return 0;
-+}
-+
-+/**
-+ * cpr4_apss_parse_temp_adj_properties() - parse temperature based
-+ * adjustment properties from device tree.
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_apss_parse_temp_adj_properties(struct cpr3_controller *ctrl)
-+{
-+ struct device_node *of_node = ctrl->dev->of_node;
-+ int rc, i, len, temp_point_count;
-+
-+ if (!of_find_property(of_node, "qcom,cpr-temp-point-map", &len)) {
-+ /*
-+ * Temperature based adjustments are not defined. Single
-+ * temperature band is still valid for per-online-core
-+ * adjustments.
-+ */
-+ ctrl->temp_band_count = 1;
-+ return 0;
-+ }
-+
-+ temp_point_count = len / sizeof(u32);
-+ if (temp_point_count <= 0 ||
-+ temp_point_count > IPQ807x_APSS_MAX_TEMP_POINTS) {
-+ cpr3_err(ctrl, "invalid number of temperature points %d > %d (max)\n",
-+ temp_point_count, IPQ807x_APSS_MAX_TEMP_POINTS);
-+ return -EINVAL;
-+ }
-+
-+ ctrl->temp_points = devm_kcalloc(ctrl->dev, temp_point_count,
-+ sizeof(*ctrl->temp_points), GFP_KERNEL);
-+ if (!ctrl->temp_points)
-+ return -ENOMEM;
-+
-+ rc = of_property_read_u32_array(of_node, "qcom,cpr-temp-point-map",
-+ ctrl->temp_points, temp_point_count);
-+ if (rc) {
-+ cpr3_err(ctrl, "error reading property qcom,cpr-temp-point-map, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ for (i = 0; i < temp_point_count; i++)
-+ cpr3_debug(ctrl, "Temperature Point %d=%d\n", i,
-+ ctrl->temp_points[i]);
-+
-+ /*
-+ * If t1, t2, and t3 are the temperature points, then the temperature
-+ * bands are: (-inf, t1], (t1, t2], (t2, t3], and (t3, inf).
-+ */
-+ ctrl->temp_band_count = temp_point_count + 1;
-+ cpr3_debug(ctrl, "Number of temp bands =%d\n", ctrl->temp_band_count);
-+
-+ rc = of_property_read_u32(of_node, "qcom,cpr-initial-temp-band",
-+ &ctrl->initial_temp_band);
-+ if (rc) {
-+ cpr3_err(ctrl, "error reading qcom,cpr-initial-temp-band, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ if (ctrl->initial_temp_band >= ctrl->temp_band_count) {
-+ cpr3_err(ctrl, "Initial temperature band value %d should be in range [0 - %d]\n",
-+ ctrl->initial_temp_band, ctrl->temp_band_count - 1);
-+ return -EINVAL;
-+ }
-+
-+ ctrl->temp_sensor_id_start = IPQ807x_APSS_TEMP_SENSOR_ID_START;
-+ ctrl->temp_sensor_id_end = IPQ807x_APSS_TEMP_SENSOR_ID_END;
-+ ctrl->allow_temp_adj = true;
-+ return rc;
-+}
-+
-+/**
-+ * cpr4_apss_parse_boost_properties() - parse configuration data for boost
-+ * voltage adjustment for CPR3 regulator from device tree.
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_apss_parse_boost_properties(struct cpr3_regulator *vreg)
-+{
-+ struct cpr3_controller *ctrl = vreg->thread->ctrl;
-+ struct cpr4_ipq807x_apss_fuses *fuse = vreg->platform_fuses;
-+ struct cpr3_corner *corner;
-+ int i, boost_voltage, final_boost_volt, rc = 0;
-+ int *boost_table = NULL, *boost_temp_adj = NULL;
-+ int boost_voltage_adjust = 0, boost_num_cores = 0;
-+ u32 boost_allowed = 0;
-+
-+ if (!boost_fuse[fuse->boost_cfg])
-+ /* Voltage boost is disabled in fuse */
-+ return 0;
-+
-+ if (of_find_property(vreg->of_node, "qcom,allow-boost", NULL)) {
-+ rc = cpr3_parse_array_property(vreg, "qcom,allow-boost", 1,
-+ &boost_allowed);
-+ if (rc)
-+ return rc;
-+ }
-+
-+ if (!boost_allowed) {
-+ /* Voltage boost is not enabled for this regulator */
-+ return 0;
-+ }
-+
-+ boost_voltage = cpr3_convert_open_loop_voltage_fuse(
-+ vreg->cpr4_regulator_data->boost_fuse_ref_volt,
-+ vreg->cpr4_regulator_data->fuse_step_volt,
-+ fuse->boost_voltage,
-+ IPQ807x_APSS_VOLTAGE_FUSE_SIZE);
-+
-+ /* Log boost voltage value for debugging purposes. */
-+ cpr3_info(vreg, "Boost open-loop=%7d uV\n", boost_voltage);
-+
-+ if (of_find_property(vreg->of_node,
-+ "qcom,cpr-boost-voltage-fuse-adjustment", NULL)) {
-+ rc = cpr3_parse_array_property(vreg,
-+ "qcom,cpr-boost-voltage-fuse-adjustment",
-+ 1, &boost_voltage_adjust);
-+ if (rc) {
-+ cpr3_err(vreg, "qcom,cpr-boost-voltage-fuse-adjustment reading failed, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ boost_voltage += boost_voltage_adjust;
-+ /* Log boost voltage value for debugging purposes. */
-+ cpr3_info(vreg, "Adjusted boost open-loop=%7d uV\n",
-+ boost_voltage);
-+ }
-+
-+ /* Limit boost voltage value between ceiling and floor voltage limits */
-+ boost_voltage = min(boost_voltage, vreg->cpr4_regulator_data->boost_ceiling_volt);
-+ boost_voltage = max(boost_voltage, vreg->cpr4_regulator_data->boost_floor_volt);
-+
-+ /*
-+ * The boost feature can only be used for the highest voltage corner.
-+ * Also, keep core-count adjustments disabled when the boost feature
-+ * is enabled.
-+ */
-+ corner = &vreg->corner[vreg->corner_count - 1];
-+ if (!corner->sdelta) {
-+ /*
-+ * If core-count/temp adjustments are not defined, the cpr4
-+ * sdelta for this corner will not be allocated. Allocate it
-+ * here for boost configuration.
-+ */
-+ corner->sdelta = devm_kzalloc(ctrl->dev,
-+ sizeof(*corner->sdelta), GFP_KERNEL);
-+ if (!corner->sdelta)
-+ return -ENOMEM;
-+ }
-+ corner->sdelta->temp_band_count = ctrl->temp_band_count;
-+
-+ rc = of_property_read_u32(vreg->of_node, "qcom,cpr-num-boost-cores",
-+ &boost_num_cores);
-+ if (rc) {
-+ cpr3_err(vreg, "qcom,cpr-num-boost-cores reading failed, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ if (boost_num_cores <= 0 ||
-+ boost_num_cores > IPQ807x_APSS_CPR_SDELTA_CORE_COUNT) {
-+ cpr3_err(vreg, "Invalid boost number of cores = %d\n",
-+ boost_num_cores);
-+ return -EINVAL;
-+ }
-+ corner->sdelta->boost_num_cores = boost_num_cores;
-+
-+ boost_table = devm_kcalloc(ctrl->dev, corner->sdelta->temp_band_count,
-+ sizeof(*boost_table), GFP_KERNEL);
-+ if (!boost_table)
-+ return -ENOMEM;
-+
-+ if (of_find_property(vreg->of_node,
-+ "qcom,cpr-boost-temp-adjustment", NULL)) {
-+ boost_temp_adj = kcalloc(corner->sdelta->temp_band_count,
-+ sizeof(*boost_temp_adj), GFP_KERNEL);
-+ if (!boost_temp_adj)
-+ return -ENOMEM;
-+
-+ rc = cpr3_parse_array_property(vreg,
-+ "qcom,cpr-boost-temp-adjustment",
-+ corner->sdelta->temp_band_count,
-+ boost_temp_adj);
-+ if (rc) {
-+ cpr3_err(vreg, "qcom,cpr-boost-temp-adjustment reading failed, rc=%d\n",
-+ rc);
-+ goto done;
-+ }
-+ }
-+
-+ for (i = 0; i < corner->sdelta->temp_band_count; i++) {
-+ /* Apply static adjustments to boost voltage */
-+ final_boost_volt = boost_voltage + (boost_temp_adj == NULL
-+ ? 0 : boost_temp_adj[i]);
-+ /*
-+ * Limit final adjusted boost voltage value between ceiling
-+ * and floor voltage limits
-+ */
-+ final_boost_volt = min(final_boost_volt,
-+ vreg->cpr4_regulator_data->boost_ceiling_volt);
-+ final_boost_volt = max(final_boost_volt,
-+ vreg->cpr4_regulator_data->boost_floor_volt);
-+
-+ boost_table[i] = (corner->open_loop_volt - final_boost_volt)
-+ / ctrl->step_volt;
-+ cpr3_debug(vreg, "Adjusted boost voltage margin for temp band %d = %d steps\n",
-+ i, boost_table[i]);
-+ }
-+
-+ corner->ceiling_volt = vreg->cpr4_regulator_data->boost_ceiling_volt;
-+ corner->sdelta->boost_table = boost_table;
-+ corner->sdelta->allow_boost = true;
-+ corner->sdelta->allow_core_count_adj = false;
-+ vreg->allow_boost = true;
-+ ctrl->allow_boost = true;
-+done:
-+ kfree(boost_temp_adj);
-+ return rc;
-+}
-+
-+/**
-+ * cpr4_apss_init_regulator() - perform all steps necessary to initialize the
-+ * configuration data for a CPR3 regulator
-+ * @vreg: Pointer to the CPR3 regulator
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_apss_init_regulator(struct cpr3_regulator *vreg)
-+{
-+ struct cpr4_ipq807x_apss_fuses *fuse;
-+ int rc;
-+
-+ rc = cpr4_ipq807x_apss_read_fuse_data(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ fuse = vreg->platform_fuses;
-+
-+ rc = cpr4_apss_parse_corner_data(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "unable to read CPR corner data from device tree, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = cpr3_mem_acc_init(vreg);
-+ if (rc) {
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(vreg, "unable to initialize mem-acc regulator settings, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = cpr4_ipq807x_apss_calculate_open_loop_voltages(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "unable to calculate open-loop voltages, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = cpr3_limit_open_loop_voltages(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "unable to limit open-loop voltages, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ cpr3_open_loop_voltage_as_ceiling(vreg);
-+
-+ rc = cpr3_limit_floor_voltages(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "unable to limit floor voltages, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ rc = cpr4_ipq807x_apss_calculate_target_quotients(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "unable to calculate target quotients, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = cpr4_parse_core_count_temp_voltage_adj(vreg, false);
-+ if (rc) {
-+ cpr3_err(vreg, "unable to parse temperature and core count voltage adjustments, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ if (vreg->allow_core_count_adj && (vreg->max_core_count <= 0
-+ || vreg->max_core_count >
-+ IPQ807x_APSS_CPR_SDELTA_CORE_COUNT)) {
-+ cpr3_err(vreg, "qcom,max-core-count has invalid value = %d\n",
-+ vreg->max_core_count);
-+ return -EINVAL;
-+ }
-+
-+ rc = cpr4_apss_parse_boost_properties(vreg);
-+ if (rc) {
-+ cpr3_err(vreg, "unable to parse boost adjustments, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ cpr4_apss_print_settings(vreg);
-+
-+ return rc;
-+}
-+
-+/**
-+ * cpr4_apss_init_controller() - perform APSS CPR4 controller specific
-+ * initializations
-+ * @ctrl: Pointer to the CPR3 controller
-+ *
-+ * Return: 0 on success, errno on failure
-+ */
-+static int cpr4_apss_init_controller(struct cpr3_controller *ctrl)
-+{
-+ int rc;
-+
-+ rc = cpr3_parse_common_ctrl_data(ctrl);
-+ if (rc) {
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(ctrl, "unable to parse common controller data, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = of_property_read_u32(ctrl->dev->of_node,
-+ "qcom,cpr-down-error-step-limit",
-+ &ctrl->down_error_step_limit);
-+ if (rc) {
-+ cpr3_err(ctrl, "error reading qcom,cpr-down-error-step-limit, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = of_property_read_u32(ctrl->dev->of_node,
-+ "qcom,cpr-up-error-step-limit",
-+ &ctrl->up_error_step_limit);
-+ if (rc) {
-+ cpr3_err(ctrl, "error reading qcom,cpr-up-error-step-limit, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ /*
-+ * Use fixed step quotient if specified otherwise use dynamic
-+ * calculated per RO step quotient
-+ */
-+ of_property_read_u32(ctrl->dev->of_node, "qcom,cpr-step-quot-fixed",
-+ &ctrl->step_quot_fixed);
-+ ctrl->use_dynamic_step_quot = ctrl->step_quot_fixed ? false : true;
-+
-+ ctrl->saw_use_unit_mV = of_property_read_bool(ctrl->dev->of_node,
-+ "qcom,cpr-saw-use-unit-mV");
-+
-+ of_property_read_u32(ctrl->dev->of_node,
-+ "qcom,cpr-voltage-settling-time",
-+ &ctrl->voltage_settling_time);
-+
-+ if (of_find_property(ctrl->dev->of_node, "vdd-limit-supply", NULL)) {
-+ ctrl->vdd_limit_regulator =
-+ devm_regulator_get(ctrl->dev, "vdd-limit");
-+ if (IS_ERR(ctrl->vdd_limit_regulator)) {
-+ rc = PTR_ERR(ctrl->vdd_limit_regulator);
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(ctrl, "unable to request vdd-limit regulator, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ }
-+
-+ rc = cpr3_apm_init(ctrl);
-+ if (rc) {
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(ctrl, "unable to initialize APM settings, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = cpr4_apss_parse_temp_adj_properties(ctrl);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to parse temperature adjustment properties, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ ctrl->sensor_count = IPQ807x_APSS_CPR_SENSOR_COUNT;
-+
-+ /*
-+ * APSS only has one thread (0) per controller so the zeroed
-+ * array does not need further modification.
-+ */
-+ ctrl->sensor_owner = devm_kcalloc(ctrl->dev, ctrl->sensor_count,
-+ sizeof(*ctrl->sensor_owner), GFP_KERNEL);
-+ if (!ctrl->sensor_owner)
-+ return -ENOMEM;
-+
-+ ctrl->ctrl_type = CPR_CTRL_TYPE_CPR4;
-+ ctrl->supports_hw_closed_loop = false;
-+ ctrl->use_hw_closed_loop = of_property_read_bool(ctrl->dev->of_node,
-+ "qcom,cpr-hw-closed-loop");
-+ return 0;
-+}
-+
-+static int cpr4_apss_regulator_suspend(struct platform_device *pdev,
-+ pm_message_t state)
-+{
-+ struct cpr3_controller *ctrl = platform_get_drvdata(pdev);
-+
-+ return cpr3_regulator_suspend(ctrl);
-+}
-+
-+static int cpr4_apss_regulator_resume(struct platform_device *pdev)
-+{
-+ struct cpr3_controller *ctrl = platform_get_drvdata(pdev);
-+
-+ return cpr3_regulator_resume(ctrl);
-+}
-+
-+static void ipq6018_set_mem_acc(struct regulator_dev *rdev)
-+{
-+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev);
-+
-+ ipq6018_mem_acc_tcsr[0].ioremap_addr =
-+ ioremap(ipq6018_mem_acc_tcsr[0].phy_addr, 0x4);
-+ ipq6018_mem_acc_tcsr[1].ioremap_addr =
-+ ioremap(ipq6018_mem_acc_tcsr[1].phy_addr, 0x4);
-+
-+ if ((ipq6018_mem_acc_tcsr[0].ioremap_addr != NULL) &&
-+ (ipq6018_mem_acc_tcsr[1].ioremap_addr != NULL) &&
-+ (vreg->current_corner == (vreg->corner_count - CPR3_CORNER_OFFSET))) {
-+
-+ writel_relaxed(ipq6018_mem_acc_tcsr[0].value,
-+ ipq6018_mem_acc_tcsr[0].ioremap_addr);
-+ writel_relaxed(ipq6018_mem_acc_tcsr[1].value,
-+ ipq6018_mem_acc_tcsr[1].ioremap_addr);
-+ }
-+}
-+
-+static void ipq6018_clr_mem_acc(struct regulator_dev *rdev)
-+{
-+ struct cpr3_regulator *vreg = rdev_get_drvdata(rdev);
-+
-+ if ((ipq6018_mem_acc_tcsr[0].ioremap_addr != NULL) &&
-+ (ipq6018_mem_acc_tcsr[1].ioremap_addr != NULL) &&
-+ (vreg->current_corner != vreg->corner_count - CPR3_CORNER_OFFSET)) {
-+ writel_relaxed(0x0, ipq6018_mem_acc_tcsr[0].ioremap_addr);
-+ writel_relaxed(0x0, ipq6018_mem_acc_tcsr[1].ioremap_addr);
-+ }
-+
-+ iounmap(ipq6018_mem_acc_tcsr[0].ioremap_addr);
-+ iounmap(ipq6018_mem_acc_tcsr[1].ioremap_addr);
-+}
-+
-+static struct cpr4_mem_acc_func ipq6018_mem_acc_funcs = {
-+ .set_mem_acc = ipq6018_set_mem_acc,
-+ .clear_mem_acc = ipq6018_clr_mem_acc
-+};
-+
-+static const struct cpr4_reg_data ipq807x_cpr_apss = {
-+ .cpr_valid_fuse_count = IPQ807x_APSS_FUSE_CORNERS,
-+ .fuse_ref_volt = ipq807x_apss_fuse_ref_volt,
-+ .fuse_step_volt = IPQ807x_APSS_FUSE_STEP_VOLT,
-+ .cpr_clk_rate = IPQ807x_APSS_CPR_CLOCK_RATE,
-+ .boost_fuse_ref_volt= IPQ807x_APSS_BOOST_FUSE_REF_VOLT,
-+ .boost_ceiling_volt= IPQ807x_APSS_BOOST_CEILING_VOLT,
-+ .boost_floor_volt= IPQ807x_APSS_BOOST_FLOOR_VOLT,
-+ .cpr3_fuse_params = &ipq807x_fuse_params,
-+ .mem_acc_funcs = NULL,
-+};
-+
-+static const struct cpr4_reg_data ipq817x_cpr_apss = {
-+ .cpr_valid_fuse_count = IPQ817x_APPS_FUSE_CORNERS,
-+ .fuse_ref_volt = ipq807x_apss_fuse_ref_volt,
-+ .fuse_step_volt = IPQ807x_APSS_FUSE_STEP_VOLT,
-+ .cpr_clk_rate = IPQ807x_APSS_CPR_CLOCK_RATE,
-+ .boost_fuse_ref_volt= IPQ807x_APSS_BOOST_FUSE_REF_VOLT,
-+ .boost_ceiling_volt= IPQ807x_APSS_BOOST_CEILING_VOLT,
-+ .boost_floor_volt= IPQ807x_APSS_BOOST_FLOOR_VOLT,
-+ .cpr3_fuse_params = &ipq807x_fuse_params,
-+ .mem_acc_funcs = NULL,
-+};
-+
-+static const struct cpr4_reg_data ipq6018_cpr_apss = {
-+ .cpr_valid_fuse_count = IPQ6018_APSS_FUSE_CORNERS,
-+ .fuse_ref_volt = ipq6018_apss_fuse_ref_volt,
-+ .fuse_step_volt = IPQ6018_APSS_FUSE_STEP_VOLT,
-+ .cpr_clk_rate = IPQ6018_APSS_CPR_CLOCK_RATE,
-+ .boost_fuse_ref_volt = IPQ6018_APSS_BOOST_FUSE_REF_VOLT,
-+ .boost_ceiling_volt = IPQ6018_APSS_BOOST_CEILING_VOLT,
-+ .boost_floor_volt = IPQ6018_APSS_BOOST_FLOOR_VOLT,
-+ .cpr3_fuse_params = &ipq6018_fuse_params,
-+ .mem_acc_funcs = &ipq6018_mem_acc_funcs,
-+};
-+
-+static const struct cpr4_reg_data ipq9574_cpr_apss = {
-+ .cpr_valid_fuse_count = IPQ9574_APSS_FUSE_CORNERS,
-+ .fuse_ref_volt = ipq9574_apss_fuse_ref_volt,
-+ .fuse_step_volt = IPQ9574_APSS_FUSE_STEP_VOLT,
-+ .cpr_clk_rate = IPQ6018_APSS_CPR_CLOCK_RATE,
-+ .boost_fuse_ref_volt = IPQ6018_APSS_BOOST_FUSE_REF_VOLT,
-+ .boost_ceiling_volt = IPQ6018_APSS_BOOST_CEILING_VOLT,
-+ .boost_floor_volt = IPQ6018_APSS_BOOST_FLOOR_VOLT,
-+ .cpr3_fuse_params = &ipq9574_fuse_params,
-+ .mem_acc_funcs = NULL,
-+};
-+
-+static struct of_device_id cpr4_regulator_match_table[] = {
-+ {
-+ .compatible = "qcom,cpr4-ipq807x-apss-regulator",
-+ .data = &ipq807x_cpr_apss
-+ },
-+ {
-+ .compatible = "qcom,cpr4-ipq817x-apss-regulator",
-+ .data = &ipq817x_cpr_apss
-+ },
-+ {
-+ .compatible = "qcom,cpr4-ipq6018-apss-regulator",
-+ .data = &ipq6018_cpr_apss
-+ },
-+ {
-+ .compatible = "qcom,cpr4-ipq9574-apss-regulator",
-+ .data = &ipq9574_cpr_apss
-+ },
-+ {}
-+};
-+
-+static int cpr4_apss_regulator_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct cpr3_controller *ctrl;
-+ const struct of_device_id *match;
-+ struct cpr4_reg_data *cpr_data;
-+ int i, rc;
-+
-+ if (!dev->of_node) {
-+ dev_err(dev, "Device tree node is missing\n");
-+ return -EINVAL;
-+ }
-+
-+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
-+ if (!ctrl)
-+ return -ENOMEM;
-+
-+ match = of_match_device(cpr4_regulator_match_table, &pdev->dev);
-+ if (!match)
-+ return -ENODEV;
-+
-+ cpr_data = (struct cpr4_reg_data *)match->data;
-+ g_valid_fuse_count = cpr_data->cpr_valid_fuse_count;
-+ dev_info(dev, "CPR valid fuse count: %d\n", g_valid_fuse_count);
-+ ctrl->cpr_clock_rate = cpr_data->cpr_clk_rate;
-+
-+ ctrl->dev = dev;
-+ /* Set to false later if anything precludes CPR operation. */
-+ ctrl->cpr_allowed_hw = true;
-+
-+ rc = of_property_read_string(dev->of_node, "qcom,cpr-ctrl-name",
-+ &ctrl->name);
-+ if (rc) {
-+ cpr3_err(ctrl, "unable to read qcom,cpr-ctrl-name, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = cpr3_map_fuse_base(ctrl, pdev);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not map fuse base address\n");
-+ return rc;
-+ }
-+
-+ rc = cpr3_read_tcsr_setting(ctrl, pdev, IPQ807x_APSS_CPR_TCSR_START,
-+ IPQ807x_APSS_CPR_TCSR_END);
-+ if (rc) {
-+ cpr3_err(ctrl, "could not read CPR tcsr setting\n");
-+ return rc;
-+ }
-+
-+ rc = cpr3_allocate_threads(ctrl, 0, 0);
-+ if (rc) {
-+ cpr3_err(ctrl, "failed to allocate CPR thread array, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ if (ctrl->thread_count != 1) {
-+ cpr3_err(ctrl, "expected 1 thread but found %d\n",
-+ ctrl->thread_count);
-+ return -EINVAL;
-+ }
-+
-+ rc = cpr4_apss_init_controller(ctrl);
-+ if (rc) {
-+ if (rc != -EPROBE_DEFER)
-+ cpr3_err(ctrl, "failed to initialize CPR controller parameters, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+
-+ rc = cpr4_apss_init_thread(&ctrl->thread[0]);
-+ if (rc) {
-+ cpr3_err(ctrl, "thread initialization failed, rc=%d\n", rc);
-+ return rc;
-+ }
-+
-+ for (i = 0; i < ctrl->thread[0].vreg_count; i++) {
-+ ctrl->thread[0].vreg[i].cpr4_regulator_data = cpr_data;
-+ rc = cpr4_apss_init_regulator(&ctrl->thread[0].vreg[i]);
-+ if (rc) {
-+ cpr3_err(&ctrl->thread[0].vreg[i], "regulator initialization failed, rc=%d\n",
-+ rc);
-+ return rc;
-+ }
-+ }
-+
-+ platform_set_drvdata(pdev, ctrl);
-+
-+ return cpr3_regulator_register(pdev, ctrl);
-+}
-+
-+static int cpr4_apss_regulator_remove(struct platform_device *pdev)
-+{
-+ struct cpr3_controller *ctrl = platform_get_drvdata(pdev);
-+
-+ return cpr3_regulator_unregister(ctrl);
-+}
-+
-+static struct platform_driver cpr4_apss_regulator_driver = {
-+ .driver = {
-+ .name = "qcom,cpr4-apss-regulator",
-+ .of_match_table = cpr4_regulator_match_table,
-+ .owner = THIS_MODULE,
-+ },
-+ .probe = cpr4_apss_regulator_probe,
-+ .remove = cpr4_apss_regulator_remove,
-+ .suspend = cpr4_apss_regulator_suspend,
-+ .resume = cpr4_apss_regulator_resume,
-+};
-+
-+static int cpr4_regulator_init(void)
-+{
-+ return platform_driver_register(&cpr4_apss_regulator_driver);
-+}
-+
-+static void cpr4_regulator_exit(void)
-+{
-+ platform_driver_unregister(&cpr4_apss_regulator_driver);
-+}
-+
-+MODULE_DESCRIPTION("CPR4 APSS regulator driver");
-+MODULE_LICENSE("GPL v2");
-+
-+arch_initcall(cpr4_regulator_init);
-+module_exit(cpr4_regulator_exit);
---- /dev/null
-+++ b/include/soc/qcom/socinfo.h
-@@ -0,0 +1,463 @@
-+/* Copyright (c) 2009-2014, 2016, 2020, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ */
-+
-+#ifndef _ARCH_ARM_MACH_MSM_SOCINFO_H_
-+#define _ARCH_ARM_MACH_MSM_SOCINFO_H_
-+
-+#include <linux/of.h>
-+
-+#define CPU_IPQ8074 323
-+#define CPU_IPQ8072 342
-+#define CPU_IPQ8076 343
-+#define CPU_IPQ8078 344
-+#define CPU_IPQ8070 375
-+#define CPU_IPQ8071 376
-+
-+#define CPU_IPQ8072A 389
-+#define CPU_IPQ8074A 390
-+#define CPU_IPQ8076A 391
-+#define CPU_IPQ8078A 392
-+#define CPU_IPQ8070A 395
-+#define CPU_IPQ8071A 396
-+
-+#define CPU_IPQ8172 397
-+#define CPU_IPQ8173 398
-+#define CPU_IPQ8174 399
-+
-+#define CPU_IPQ6018 402
-+#define CPU_IPQ6028 403
-+#define CPU_IPQ6000 421
-+#define CPU_IPQ6010 422
-+#define CPU_IPQ6005 453
-+
-+#define CPU_IPQ5010 446
-+#define CPU_IPQ5018 447
-+#define CPU_IPQ5028 448
-+#define CPU_IPQ5000 503
-+#define CPU_IPQ0509 504
-+#define CPU_IPQ0518 505
-+
-+#define CPU_IPQ9514 510
-+#define CPU_IPQ9554 512
-+#define CPU_IPQ9570 513
-+#define CPU_IPQ9574 514
-+#define CPU_IPQ9550 511
-+#define CPU_IPQ9510 521
-+
-+static inline int read_ipq_soc_version_major(void)
-+{
-+ const int *prop;
-+ prop = of_get_property(of_find_node_by_path("/"), "soc_version_major",
-+ NULL);
-+
-+ if (!prop)
-+ return -EINVAL;
-+
-+ return le32_to_cpu(*prop);
-+}
-+
-+static inline int read_ipq_cpu_type(void)
-+{
-+ const int *prop;
-+ prop = of_get_property(of_find_node_by_path("/"), "cpu_type", NULL);
-+ /*
-+ * Return Default CPU type if "cpu_type" property is not found in DTSI
-+ */
-+ if (!prop)
-+ return CPU_IPQ8074;
-+
-+ return le32_to_cpu(*prop);
-+}
-+
-+static inline int cpu_is_ipq8070(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8070;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8071(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8071;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8072(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8072;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8074(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8074;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8076(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8076;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8078(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8078;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8072a(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8072A;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8074a(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8074A;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8076a(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8076A;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8078a(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8078A;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8070a(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8070A;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8071a(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8071A;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8172(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8172;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8173(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8173;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq8174(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ8174;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq6018(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ6018;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq6028(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ6028;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq6000(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ6000;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq6010(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ6010;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq6005(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ6005;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq5010(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ5010;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq5018(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ5018;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq5028(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ5028;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq5000(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ5000;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq0509(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ0509;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq0518(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ0518;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq9514(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ9514;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq9554(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ9554;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq9570(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ9570;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq9574(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ9574;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq9550(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ9550;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq9510(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return read_ipq_cpu_type() == CPU_IPQ9510;
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq807x(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return cpu_is_ipq8072() || cpu_is_ipq8074() ||
-+ cpu_is_ipq8076() || cpu_is_ipq8078() ||
-+ cpu_is_ipq8070() || cpu_is_ipq8071() ||
-+ cpu_is_ipq8072a() || cpu_is_ipq8074a() ||
-+ cpu_is_ipq8076a() || cpu_is_ipq8078a() ||
-+ cpu_is_ipq8070a() || cpu_is_ipq8071a() ||
-+ cpu_is_ipq8172() || cpu_is_ipq8173() ||
-+ cpu_is_ipq8174();
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq60xx(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return cpu_is_ipq6018() || cpu_is_ipq6028() ||
-+ cpu_is_ipq6000() || cpu_is_ipq6010() ||
-+ cpu_is_ipq6005();
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq50xx(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return cpu_is_ipq5010() || cpu_is_ipq5018() ||
-+ cpu_is_ipq5028() || cpu_is_ipq5000() ||
-+ cpu_is_ipq0509() || cpu_is_ipq0518();
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_ipq95xx(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return cpu_is_ipq9514() || cpu_is_ipq9554() ||
-+ cpu_is_ipq9570() || cpu_is_ipq9574() ||
-+ cpu_is_ipq9550() || cpu_is_ipq9510();
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_nss_crypto_enabled(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return cpu_is_ipq807x() || cpu_is_ipq60xx() ||
-+ cpu_is_ipq50xx() || cpu_is_ipq9570() ||
-+ cpu_is_ipq9550() || cpu_is_ipq9574() ||
-+ cpu_is_ipq9554();
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_internal_wifi_enabled(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return cpu_is_ipq807x() || cpu_is_ipq60xx() ||
-+ cpu_is_ipq50xx() || cpu_is_ipq9514() ||
-+ cpu_is_ipq9554() || cpu_is_ipq9574();
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_uniphy1_enabled(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return cpu_is_ipq807x() || cpu_is_ipq60xx() ||
-+ cpu_is_ipq9554() || cpu_is_ipq9570() ||
-+ cpu_is_ipq9574() || cpu_is_ipq9550();
-+#else
-+ return 0;
-+#endif
-+}
-+
-+static inline int cpu_is_uniphy2_enabled(void)
-+{
-+#ifdef CONFIG_ARCH_QCOM
-+ return cpu_is_ipq807x() || cpu_is_ipq9570() ||
-+ cpu_is_ipq9574();
-+#else
-+ return 0;
-+#endif
-+}
-+
-+#endif /* _ARCH_ARM_MACH_MSM_SOCINFO_H_ */
+++ /dev/null
-From 6baf7e4abcea6f7ac21eccf072a20078b39d064c Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 9 Feb 2022 23:13:26 +0100
-Subject: [PATCH] arm64: dts: ipq8074: add label to clocks
-
-Add label to clocks node as that makes it easy to add the NSS fixed
-clocks that are required in their DTSI.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -15,7 +15,7 @@
- compatible = "qcom,ipq8074";
- interrupt-parent = <&intc>;
-
-- clocks {
-+ clocks: clocks {
- sleep_clk: sleep_clk {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
+++ /dev/null
-From 563db68137475d011b355bfe674d1b7a24778091 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 8 Oct 2022 22:26:31 +0200
-Subject: [PATCH] psci: dont advertise OSI support for IPQ6018
-
-Some older IPQ60xx SoC series boards ship with TrustZone/QSEE firmware
-older than TZ.WNS.5.1-00084 which will advertise OSI[1] but are broken
-and trying to use OSI will cause the board to hang until WDT kicks in.
-
-So workaround it by checking for SoC compatible and returning false so
-OSI is not used.
-
-[1] https://www.spinics.net/lists/linux-arm-msm/msg79916.html
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/firmware/psci/psci.c | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/drivers/firmware/psci/psci.c
-+++ b/drivers/firmware/psci/psci.c
-@@ -87,6 +87,18 @@ static inline bool psci_has_ext_power_st
-
- bool psci_has_osi_support(void)
- {
-+ /*
-+ * Some older IPQ60xx SoC series boards ship with
-+ * TrustZone/QSEE firmware older than TZ.WNS.5.1-00084
-+ * which will advertise OSI but is broken and trying
-+ * to use OSI will cause the board to hang until WDT
-+ * kicks in.
-+ * So workaround it by checking for SoC compatible
-+ * and returning false so OSI is not used.
-+ */
-+ if (of_machine_is_compatible("qcom,ipq6018"))
-+ return false;
-+
- return psci_cpu_suspend_feature & PSCI_1_0_OS_INITIATED;
- }
-
+++ /dev/null
-From 0c5b5243ad55ae744e790ba90c5ad37a93bd1377 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 11 Oct 2022 23:38:45 +0200
-Subject: [PATCH] clk: qcom: ipq6018: workaround networking clock parenting
-
-Currently, networking clocks are only looked up by fw_name however,
-these are registered and setup by SSDK and are not available to the
-GCC driver at all, so work around that by providing a global name
-fallback.
-
-While we are here, provide global fallback for bias_pll_cc_clk and
-bias_pll_nss_noc_clk as well as these are fixed clocks also not available
-to the driver.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/clk/qcom/gcc-ipq6018.c | 39 +++++++++++++++++-----------------
- 1 file changed, 19 insertions(+), 20 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq6018.c
-+++ b/drivers/clk/qcom/gcc-ipq6018.c
-@@ -361,7 +361,7 @@ static const struct freq_tbl ftbl_nss_pp
-
- static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
- { .fw_name = "xo" },
-- { .fw_name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- { .hw = &gpll0.clkr.hw },
- { .hw = &gpll4.clkr.hw },
- { .hw = &nss_crypto_pll.clkr.hw },
-@@ -527,12 +527,12 @@ static const struct freq_tbl ftbl_nss_po
- static const struct clk_parent_data
- gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
- { .fw_name = "xo" },
-- { .fw_name = "uniphy0_gcc_rx_clk" },
-- { .fw_name = "uniphy0_gcc_tx_clk" },
-- { .fw_name = "uniphy1_gcc_rx_clk" },
-- { .fw_name = "uniphy1_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
-+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .fw_name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map
-@@ -574,12 +574,12 @@ static const struct freq_tbl ftbl_nss_po
- static const struct clk_parent_data
- gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
- { .fw_name = "xo" },
-- { .fw_name = "uniphy0_gcc_tx_clk" },
-- { .fw_name = "uniphy0_gcc_rx_clk" },
-- { .fw_name = "uniphy1_gcc_tx_clk" },
-- { .fw_name = "uniphy1_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
-+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .fw_name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map
-@@ -715,10 +715,10 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
- { .fw_name = "xo" },
-- { .fw_name = "uniphy0_gcc_rx_clk" },
-- { .fw_name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .fw_name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
-@@ -751,10 +751,10 @@ static const struct freq_tbl ftbl_nss_po
-
- static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
- { .fw_name = "xo" },
-- { .fw_name = "uniphy0_gcc_tx_clk" },
-- { .fw_name = "uniphy0_gcc_rx_clk" },
-+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
-+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
- { .hw = &ubi32_pll.clkr.hw },
-- { .fw_name = "bias_pll_cc_clk" },
-+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
- };
-
- static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
-@@ -1898,12 +1898,11 @@ static const struct freq_tbl ftbl_ubi32_
- { }
- };
-
--static const struct clk_parent_data
-- gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
-+static const struct clk_parent_data gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
- { .fw_name = "xo" },
- { .hw = &gpll0.clkr.hw },
- { .hw = &gpll2.clkr.hw },
-- { .fw_name = "bias_pll_nss_noc_clk" },
-+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
- };
-
- static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
+++ /dev/null
-From 505f9c8653fc218ca47a153ec58ebc16bef5502f Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Tue, 16 Jan 2024 10:42:40 +0200
-Subject: [PATCH 16/19] remoteproc: q6v5_wcss: change ssr name for ipq6018 wifi
- subsystem
-
-On IPQ6018 this string ends up being sent to RPM when remoteproc stops
-(on crash or rmmod ath11k). "q6wcss" is not a valid name (not found by
-`strings` in rpm.mbn), so this causes RPM do 'something' (presumably crash)
-causing a system reboot followed by hang in XBL, with no WDT running.
-Let's change ssr_name to a more sensible 'wcnss', that does not cause such
-issues.
-
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -1143,8 +1143,8 @@ static int q6v5_wcss_probe(struct platfo
- if (ret)
- goto free_rproc;
-
-- qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss");
-- qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss");
-+ qcom_add_glink_subdev(rproc, &wcss->glink_subdev, desc->ssr_name);
-+ qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, desc->ssr_name);
-
- if (desc->ssctl_id)
- wcss->sysmon = qcom_add_sysmon_subdev(rproc,
-@@ -1201,7 +1201,7 @@ static const struct wcss_data wcss_ipq60
- .aon_reset_required = true,
- .wcss_q6_reset_required = true,
- .bcr_reset_required = false,
-- .ssr_name = "q6wcss",
-+ .ssr_name = "wcnss",
- .ops = &q6v5_wcss_ipq8074_ops,
- .requires_force_stop = true,
- .need_mem_protection = true,
+++ /dev/null
-From 153c74fc80b9f33ed1a50d7790bf6979fdceb370 Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Tue, 16 Jan 2024 11:41:06 +0200
-Subject: [PATCH 19/19] arm64: dts: qcom: ipq6018: add wifi node
-
-IPQ6018 has a AHB based Q6v5 802.11ax radios that are supported
-by the ath11k.
-
-Add the required DT node to enable the built-in radios.
-
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 96 +++++++++++++++++++++++++++++++++++
- 1 file changed, 96 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -807,6 +807,102 @@
- };
- };
-
-+ wifi: wifi@c000000 {
-+ compatible = "qcom,ipq6018-wifi";
-+ reg = <0x0 0xc000000 0x0 0x1000000>;
-+ qcom,rproc = <&q6v5_wcss>;
-+ interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
-+ interrupt-names = "misc-pulse1", "misc-latch", "sw-exception",
-+ "watchdog", "ce0", "ce1", "ce2", "ce3", "ce4",
-+ "ce5", "ce6", "ce7", "ce8", "ce9", "ce10",
-+ "ce11", "host2wbm-desc-feed",
-+ "host2reo-re-injection", "host2reo-command",
-+ "host2rxdma-monitor-ring3",
-+ "host2rxdma-monitor-ring2",
-+ "host2rxdma-monitor-ring1",
-+ "reo2ost-exception", "wbm2host-rx-release",
-+ "reo2host-status",
-+ "reo2host-destination-ring4",
-+ "reo2host-destination-ring3",
-+ "reo2host-destination-ring2",
-+ "reo2host-destination-ring1",
-+ "rxdma2host-monitor-destination-mac3",
-+ "rxdma2host-monitor-destination-mac2",
-+ "rxdma2host-monitor-destination-mac1",
-+ "ppdu-end-interrupts-mac3",
-+ "ppdu-end-interrupts-mac2",
-+ "ppdu-end-interrupts-mac1",
-+ "rxdma2host-monitor-status-ring-mac3",
-+ "rxdma2host-monitor-status-ring-mac2",
-+ "rxdma2host-monitor-status-ring-mac1",
-+ "host2rxdma-host-buf-ring-mac3",
-+ "host2rxdma-host-buf-ring-mac2",
-+ "host2rxdma-host-buf-ring-mac1",
-+ "rxdma2host-destination-ring-mac3",
-+ "rxdma2host-destination-ring-mac2",
-+ "rxdma2host-destination-ring-mac1",
-+ "host2tcl-input-ring4",
-+ "host2tcl-input-ring3",
-+ "host2tcl-input-ring2",
-+ "host2tcl-input-ring1",
-+ "wbm2host-tx-completions-ring3",
-+ "wbm2host-tx-completions-ring2",
-+ "wbm2host-tx-completions-ring1",
-+ "tcl2host-status-ring";
-+ status = "disabled";
-+ };
-+
- q6v5_wcss: remoteproc@cd00000 {
- compatible = "qcom,ipq6018-wcss-pil";
- reg = <0x0 0x0cd00000 0x0 0x4040>,
+++ /dev/null
-From d93936f175bd914067df8f63f5fbe6e3b77bb4d2 Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Tue, 23 May 2023 14:46:28 +0300
-Subject: [PATCH 11/19] soc: qcom: fix smp2p ack on ipq6018
-
-IPQ6018 seem to need different ack mechanism for smp2p messaging. This
-fixes q6v5_wcss remoteproc firmware reloading. Without this first load
-is OK, but subsequent loads would hang and fail to complete.
-
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
- drivers/soc/qcom/smp2p.c | 6 +++++-
- 2 files changed, 6 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -1155,6 +1155,7 @@
-
- wcss_smp2p_out: master-kernel {
- qcom,entry-name = "master-kernel";
-+ qcom,smp2p-feature-ssr-ack;
- #qcom,smem-state-cells = <1>;
- };
-
---- a/drivers/soc/qcom/smp2p.c
-+++ b/drivers/soc/qcom/smp2p.c
-@@ -158,6 +158,8 @@ struct qcom_smp2p {
-
- struct list_head inbound;
- struct list_head outbound;
-+
-+ bool need_ssr_ack;
- };
-
- static void qcom_smp2p_kick(struct qcom_smp2p *smp2p)
-@@ -306,7 +308,7 @@ static irqreturn_t qcom_smp2p_intr(int i
- ack_restart = qcom_smp2p_check_ssr(smp2p);
- qcom_smp2p_notify_in(smp2p);
-
-- if (ack_restart)
-+ if (ack_restart || smp2p->need_ssr_ack)
- qcom_smp2p_do_ssr_ack(smp2p);
- }
-
-@@ -427,6 +429,7 @@ static int qcom_smp2p_outbound_entry(str
-
- /* Make the logical entry reference the physical value */
- entry->value = &out->entries[out->valid_entries].value;
-+ smp2p->need_ssr_ack = of_property_read_bool(node, "qcom,smp2p-feature-ssr-ack");
-
- out->valid_entries++;
-
+++ /dev/null
-From 87dbcc69a7e3fe6ccddf4fe9bdbf51330f5e4a77 Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Tue, 23 Jan 2024 11:04:04 +0200
-Subject: [PATCH] remoteproc: qcom_q6v5_wcss: add optional qdss_at clock
-
-IPQ6018 needs QDSS_AT clock enabled when loading wifi. Optionally enable it
-when provided by DT.
-
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
----
- drivers/remoteproc/qcom_q6v5_wcss.c | 24 ++++++++++++++++++++++++
- 1 file changed, 24 insertions(+)
-
---- a/drivers/remoteproc/qcom_q6v5_wcss.c
-+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
-@@ -120,6 +120,7 @@ struct q6v5_wcss {
- struct clk *qdsp6ss_core_gfmux;
- struct clk *lcc_bcr_sleep;
- struct clk *prng_clk;
-+ struct clk *qdss_clk;
- struct regulator *cx_supply;
- struct qcom_sysmon *sysmon;
-
-@@ -259,6 +260,9 @@ static int q6v5_wcss_start(struct rproc
- return ret;
- }
-
-+ if (wcss->qdss_clk)
-+ clk_prepare_enable(wcss->qdss_clk);
-+
- qcom_q6v5_prepare(&wcss->q6v5);
-
- if (wcss->need_mem_protection) {
-@@ -772,6 +776,8 @@ static int q6v5_wcss_stop(struct rproc *
- }
-
- pas_done:
-+ if (wcss->qdss_clk)
-+ clk_disable_unprepare(wcss->qdss_clk);
- clk_disable_unprepare(wcss->prng_clk);
- qcom_q6v5_unprepare(&wcss->q6v5);
-
-@@ -981,6 +987,12 @@ static int ipq_init_clock(struct q6v5_wc
- dev_err(wcss->dev, "Failed to get prng clock\n");
- return ret;
- }
-+
-+ wcss->qdss_clk = devm_clk_get(wcss->dev, "qdss");
-+ if (IS_ERR(wcss->qdss_clk)) {
-+ wcss->qdss_clk = NULL;
-+ }
-+
- return 0;
- }
-
+++ /dev/null
-From 71f30e25d21ae4981ecef6653a4ba7dfeb80db7b Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Tue, 23 Jan 2024 11:04:57 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: assign QDSS_AT clock to wifi remoteproc
-
-IPQ6018 needs to enable QDSS_AT clock when loading wifi firmware,
-add it to wifi remoteproc clock list.
-
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 ++++++++-------
- 1 file changed, 9 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -928,8 +928,8 @@
- "wcss_reset",
- "wcss_q6_reset";
-
-- clocks = <&gcc GCC_PRNG_AHB_CLK>;
-- clock-names = "prng";
-+ clocks = <&gcc GCC_PRNG_AHB_CLK>, <&gcc GCC_QDSS_AT_CLK>;
-+ clock-names = "prng", "qdss" ;
-
- qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
-
+++ /dev/null
-From c67a1814bb1d0df290cf1e3f9c966f04aa41b9b9 Mon Sep 17 00:00:00 2001
-From: Mantas Pucka <mantas@8devices.com>
-Date: Tue, 30 Jan 2024 12:43:56 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq6018: change voltage to perf levels for
- CPR4 driver
-
-Current CPR4 driver requires opp-microvolt to be an abstract
-performance level instead of actual voltage level.
-
-Signed-off-by: Mantas Pucka <mantas@8devices.com>
----
- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
-@@ -106,42 +106,42 @@
-
- opp-864000000 {
- opp-hz = /bits/ 64 <864000000>;
-- opp-microvolt = <725000>;
-+ opp-microvolt = <1>;
- opp-supported-hw = <0xf>;
- clock-latency-ns = <200000>;
- };
-
- opp-1056000000 {
- opp-hz = /bits/ 64 <1056000000>;
-- opp-microvolt = <787500>;
-+ opp-microvolt = <2>;
- opp-supported-hw = <0xf>;
- clock-latency-ns = <200000>;
- };
-
- opp-1320000000 {
- opp-hz = /bits/ 64 <1320000000>;
-- opp-microvolt = <862500>;
-+ opp-microvolt = <3>;
- opp-supported-hw = <0x3>;
- clock-latency-ns = <200000>;
- };
-
- opp-1440000000 {
- opp-hz = /bits/ 64 <1440000000>;
-- opp-microvolt = <925000>;
-+ opp-microvolt = <4>;
- opp-supported-hw = <0x3>;
- clock-latency-ns = <200000>;
- };
-
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
-- opp-microvolt = <987500>;
-+ opp-microvolt = <5>;
- opp-supported-hw = <0x1>;
- clock-latency-ns = <200000>;
- };
-
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
-- opp-microvolt = <1062500>;
-+ opp-microvolt = <6>;
- opp-supported-hw = <0x1>;
- clock-latency-ns = <200000>;
- };
--- /dev/null
+From 5f78d9213ae753e2242b0f6a5d4a5e98e55ddc76 Mon Sep 17 00:00:00 2001
+From: Paweł Owoc <frut3k7@gmail.com>
+Date: Wed, 13 Mar 2024 11:27:06 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins
+
+gpio16 will only be used for LCD support, as its NAND/LCDC data[8]
+so its bit 9 of the parallel QPIC interface, and ONFI NAND is only 8
+or 16-bit with only 8-bit one being supported in our case so that pin
+is unused.
+
+It should be dropped from the default NAND pinctrl configuration
+as its unused and only needed for LCD.
+
+Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
+Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
+Link: https://lore.kernel.org/r/20240313102713.1727458-1-frut3k7@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -372,7 +372,7 @@
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+- "gpio15", "gpio16", "gpio17";
++ "gpio15", "gpio17";
+ function = "qpic";
+ drive-strength = <8>;
+ bias-disable;
SUBTARGETS:=mt7620 mt7621 mt76x8 rt288x rt305x rt3883
FEATURES:=squashfs gpio
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
define Target/Description
Build firmware images for Ralink RT288x/RT3xxx based boards.
--- /dev/null
+#include "mt7620a.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ rfkill {
+ label = "rfkill";
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RFKILL>;
+ };
+ };
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <30000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x20000>;
+ read-only;
+ };
+
+ partition@20000 {
+ compatible = "tplink,firmware";
+ label = "firmware";
+ reg = <0x20000 0x7a0000>;
+ };
+
+ partition@7c0000 {
+ label = "config";
+ reg = <0x7c0000 0x10000>;
+ read-only;
+ };
+
+ partition@7d0000 {
+ label = "rom";
+ reg = <0x7d0000 0x10000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_rom_f100: macaddr@f100 {
+ compatible = "mac-base";
+ reg = <0xf100 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ partition@7e0000 {
+ label = "romfile";
+ reg = <0x7e0000 0x10000>;
+ read-only;
+ };
+
+ partition@7f0000 {
+ label = "radio";
+ reg = <0x7f0000 0x10000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_radio_0: eeprom@0 {
+ reg = <0x0 0x200>;
+ };
+
+ eeprom_radio_8000: eeprom@8000 {
+ reg = <0x8000 0x200>;
+ };
+ };
+ };
+ };
+ };
+};
+
+ðernet {
+ pinctrl-names = "default";
+
+ nvmem-cells = <&macaddr_rom_f100 0>;
+ nvmem-cell-names = "mac-address";
+
+ mediatek,portmap = "wllll";
+};
+
+&ehci {
+ status = "okay";
+};
+
+&ohci {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
+&pcie0 {
+ wifi: mt76@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ ieee80211-freq-limit = <5000000 6000000>;
+ };
+};
-#include "mt7620a.dtsi"
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
+#include "mt7620a_tplink_8m.dtsi"
+
/ {
compatible = "tplink,archer-c2-v1", "ralink,mt7620a-soc";
model = "TP-Link Archer C2 v1";
led-upgrade = &led_wps;
};
- chosen {
- bootargs = "console=ttyS0,115200";
- };
leds {
compatible = "gpio-leds";
- lan {
+ led-0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
- usb {
+ led-1 {
function = LED_FUNCTION_USB;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
linux,default-trigger = "usbport";
};
- led_wps: wps {
+ led_wps: led-2 {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
- wan {
+ led-3 {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
};
- wlan {
+ led-4 {
function = LED_FUNCTION_WLAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
};
};
- keys {
- compatible = "gpio-keys";
-
- reset_wps {
- label = "reset_wps";
- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- rfkill {
- label = "rfkill";
- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- };
- };
-
rtl8367rb {
compatible = "realtek,rtl8367b";
cpu_port = <6>;
};
};
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <30000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- partition@20000 {
- compatible = "tplink,firmware";
- label = "firmware";
- reg = <0x20000 0x7a0000>;
- };
-
- partition@7c0000 {
- label = "config";
- reg = <0x7c0000 0x10000>;
- read-only;
- };
-
- partition@7d0000 {
- label = "rom";
- reg = <0x7d0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_rom_f100: macaddr@f100 {
- compatible = "mac-base";
- reg = <0xf100 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@7e0000 {
- label = "romfile";
- reg = <0x7e0000 0x10000>;
- read-only;
- };
-
- partition@7f0000 {
- label = "radio";
- reg = <0x7f0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- eeprom_radio_0: eeprom@0 {
- reg = <0x0 0x200>;
- };
-
- eeprom_radio_8000: eeprom@8000 {
- reg = <0x8000 0x200>;
- };
- };
- };
- };
+&state_default {
+ gpio {
+ groups = "i2c", "uartf", "wled", "ephy", "spi refclk";
+ function = "gpio";
};
};
};
};
-&gpio1 {
- status = "okay";
-};
-
-&gpio2 {
- status = "okay";
-};
-
-&gpio3 {
- status = "okay";
-};
-
-&state_default {
- gpio {
- groups = "i2c", "uartf", "wled", "ephy", "spi refclk";
- function = "gpio";
- };
-};
&wmac {
nvmem-cells = <&eeprom_radio_0>, <&macaddr_rom_f100 0>;
nvmem-cell-names = "eeprom", "mac-address";
};
-&ehci {
- status = "okay";
-};
-
-&ohci {
- status = "okay";
-};
-
-&pcie {
- status = "okay";
-};
-
-&pcie0 {
- mt76@0,0 {
- reg = <0x0000 0 0 0 0>;
- nvmem-cells = <&eeprom_radio_8000>, <&macaddr_rom_f100 (-1)>;
- nvmem-cell-names = "eeprom", "mac-address";
- };
+&wifi {
+ nvmem-cells = <&eeprom_radio_8000>, <&macaddr_rom_f100 (-1)>;
+ nvmem-cell-names = "eeprom", "mac-address";
};
#include <dt-bindings/leds/common.h>
-#include "mt7620a_tplink_archer.dtsi"
+#include "mt7620a_tplink_8m.dtsi"
/ {
compatible = "tplink,archer-c20-v1", "ralink,mt7620a-soc";
leds {
compatible = "gpio-leds";
- lan {
+ led-0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
- led_power: power {
+ led_power: led-1 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
- usb {
+ led-2 {
function = LED_FUNCTION_USB;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "usbport";
};
- wan {
+ led-3 {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
};
- wan_orange {
+ led-4 {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_ORANGE>;
gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};
- wlan5g {
- label = "blue:wlan5g";
+ led-5 {
+ function = LED_FUNCTION_WLAN_5GHZ;
+ color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
- wlan2g {
- label = "blue:wlan2g";
+ led-6 {
+ function = LED_FUNCTION_WLAN_2GHZ;
+ color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
- wps {
+ led-7 {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
#include <dt-bindings/leds/common.h>
-#include "mt7620a_tplink_archer.dtsi"
+#include "mt7620a_tplink_8m.dtsi"
/ {
compatible = "tplink,archer-c20i", "ralink,mt7620a-soc";
leds {
compatible = "gpio-leds";
- lan {
+ led-0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
- usb {
+ led-1 {
function = LED_FUNCTION_USB;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
linux,default-trigger = "usbport";
};
- led_wps: wps {
+ led_wps: led-2 {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
- wan {
+ led-3 {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
};
- wlan {
+ led-4 {
function = LED_FUNCTION_WLAN;
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
#include <dt-bindings/leds/common.h>
-#include "mt7620a_tplink_archer.dtsi"
+#include "mt7620a_tplink_8m.dtsi"
/ {
compatible = "tplink,archer-c5-v4", "ralink,mt7620a-soc";
#include <dt-bindings/leds/common.h>
-#include "mt7620a_tplink_archer.dtsi"
+#include "mt7620a_tplink_8m.dtsi"
/ {
compatible = "tplink,archer-c50-v1", "ralink,mt7620a-soc";
leds {
compatible = "gpio-leds";
- lan {
+ led-0 {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
- led_power: power {
+ led_power: led-1 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
default-state = "on";
};
- usb {
+ led-2 {
function = LED_FUNCTION_USB;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
linux,default-trigger = "usbport";
};
- wan {
+ led-3 {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
};
- wan_orange {
+ led-4 {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_ORANGE>;
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
};
- wlan5g {
- label = "green:wlan5g";
+ led-5 {
+ function = LED_FUNCTION_WLAN_5GHZ;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
- wlan2g {
- label = "green:wlan2g";
+ led-6 {
+ function = LED_FUNCTION_WLAN_2GHZ;
+ color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
- wps {
+ led-7 {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+++ /dev/null
-#include "mt7620a.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- chosen {
- bootargs = "console=ttyS0,115200";
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- rfkill {
- label = "rfkill";
- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- };
- };
-};
-
-&gpio1 {
- status = "okay";
-};
-
-&gpio2 {
- status = "okay";
-};
-
-&gpio3 {
- status = "okay";
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <30000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- partition@20000 {
- compatible = "tplink,firmware";
- label = "firmware";
- reg = <0x20000 0x7a0000>;
- };
-
- partition@7c0000 {
- label = "config";
- reg = <0x7c0000 0x10000>;
- read-only;
- };
-
- partition@7d0000 {
- label = "rom";
- reg = <0x7d0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_rom_f100: macaddr@f100 {
- compatible = "mac-base";
- reg = <0xf100 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@7e0000 {
- label = "romfile";
- reg = <0x7e0000 0x10000>;
- read-only;
- };
-
- partition@7f0000 {
- label = "radio";
- reg = <0x7f0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- eeprom_radio_0: eeprom@0 {
- reg = <0x0 0x200>;
- };
-
- eeprom_radio_8000: eeprom@8000 {
- reg = <0x8000 0x200>;
- };
- };
- };
- };
- };
-};
-
-ðernet {
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_rom_f100 0>;
- nvmem-cell-names = "mac-address";
-
- mediatek,portmap = "wllll";
-};
-
-&ehci {
- status = "okay";
-};
-
-&ohci {
- status = "okay";
-};
-
-&wmac {
- nvmem-cells = <&eeprom_radio_0>;
- nvmem-cell-names = "eeprom";
-};
-
-&pcie {
- status = "okay";
-};
-
-&pcie0 {
- wifi: mt76@0,0 {
- reg = <0x0000 0 0 0 0>;
- nvmem-cells = <&eeprom_radio_8000>;
- nvmem-cell-names = "eeprom";
- ieee80211-freq-limit = <5000000 6000000>;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/leds/common.h>
+
+#include "mt7620a_tplink_8m.dtsi"
+
+/ {
+ compatible = "tplink,ec220-g5-v2", "ralink,mt7620a-soc";
+ model = "TP-Link EC220-G5 v2";
+
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ label-mac-device = ðernet;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power: led-0 {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_ORANGE>;
+ gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
+ };
+
+ led-3 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ };
+
+ led-4 {
+ function = LED_FUNCTION_WLAN_2GHZ;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ led-5 {
+ function = LED_FUNCTION_WLAN_5GHZ;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy1tpt";
+ };
+
+ led-6 {
+ function = LED_FUNCTION_WPS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ rfkill {
+ label = "rfkill";
+ gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RFKILL>;
+ };
+ };
+
+ rtl8367s {
+ compatible = "realtek,rtl8367b";
+ cpu_port = <7>;
+ realtek,extif2 = <1 0 1 1 1 1 1 1 2>;
+ mii-bus = <&mdio0>;
+ phy-id = <29>;
+ };
+};
+
+&spi0 {
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&state_default {
+ gpio {
+ groups = "i2c", "uartf", "ephy", "rgmii2";
+ function = "gpio";
+ };
+};
+
+ðernet {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins &mdio_pins>;
+
+ port@5 {
+ status = "okay";
+ mediatek,fixed-link = <1000 1 1 1>;
+ phy-mode = "rgmii";
+ };
+
+ mdio0: mdio-bus {
+ status = "okay";
+ reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <10000>;
+ };
+};
+
+&ehci {
+ status = "disabled";
+};
+
+&ohci {
+ status = "disabled";
+};
+
+&wmac {
+ pinctrl-names = "default", "pa_gpio";
+ pinctrl-0 = <&pa_pins>;
+ pinctrl-1 = <&pa_gpio_pins>;
+
+ nvmem-cells = <&eeprom_radio_0>, <&macaddr_rom_f100 0>;
+ nvmem-cell-names = "eeprom", "mac-address";
+};
+
+
+&wifi {
+ nvmem-cells = <&eeprom_radio_8000>, <&macaddr_rom_f100 2>;
+ nvmem-cell-names = "eeprom", "mac-address";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "mt7620a.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "wavlink,wl-wn531g3", "ralink,mt7620a-soc";
+ model = "Wavlink WL-WN531G3";
+
+ aliases {
+ led-boot = &led_status_blue;
+ led-failsafe = &led_status_red;
+ led-running = &led_status_blue;
+ led-upgrade = &led_status_red;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ turbo {
+ label = "turbo";
+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_1>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ touchlink {
+ label = "touchlink";
+ gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status_blue: led_status_blue {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_status_red: led_status_red {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&ehci {
+ status = "okay";
+};
+
+&ohci {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x30000>;
+ read-only;
+ };
+
+ partition@30000 {
+ label = "u-boot-env";
+ reg = <0x30000 0x10000>;
+ read-only;
+ };
+
+ factory: partition@40000 {
+ label = "factory";
+ reg = <0x40000 0x10000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_factory_28: macaddr@28 {
+ reg = <0x28 0x6>;
+ };
+
+ macaddr_factory_2e: macaddr@2e {
+ reg = <0x2e 0x6>;
+ };
+
+ eeprom_radio_0: eeprom@0 {
+ reg = <0x0 0x200>;
+ };
+
+ eeprom_radio_8000: eeprom@8000 {
+ reg = <0x8000 0x200>;
+ };
+ };
+ };
+
+ partition@50000 {
+ label = "params";
+ reg = <0x50000 0x10000>;
+ read-only;
+ };
+
+ partition@60000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x60000 0x7a0000>;
+ };
+ };
+ };
+};
+
+ðernet {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins>, <&rgmii2_pins>, <&mdio_pins>;
+
+ nvmem-cells = <&macaddr_factory_28>;
+ nvmem-cell-names = "mac-address";
+
+ mediatek,portmap = "llllw";
+
+ port@4 {
+ status = "okay";
+ phy-handle = <&phy4>;
+ phy-mode = "rgmii";
+
+ nvmem-cells = <&macaddr_factory_2e>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port@5 {
+ status = "okay";
+ phy-handle = <&phy5>;
+ phy-mode = "rgmii";
+ };
+
+ mdio-bus {
+ status = "okay";
+
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ phy-mode = "rgmii";
+ };
+
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ phy-mode = "rgmii";
+ };
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&pcie0 {
+ mt76@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cells = <&eeprom_radio_8000>;
+ nvmem-cell-names = "eeprom";
+ ieee80211-freq-limit = <5000000 6000000>;
+ };
+};
+
+&gsw {
+ mediatek,port4-gmac;
+};
+
+&wmac {
+ nvmem-cells = <&eeprom_radio_0>;
+ nvmem-cell-names = "eeprom";
+};
+
+&state_default {
+ gpio {
+ groups = "i2c", "uartf";
+ function = "gpio";
+ };
+};
#interrupt-cells = <1>;
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ interrupts = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupts = <1>;
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ interrupts = <2>;
+ };
+
+ ethphy3: ethernet-phy@3 {
+ reg = <3>;
+ interrupts = <3>;
+ };
+
+ ethphy4: ethernet-phy@4 {
+ reg = <4>;
+ interrupts = <4>;
+ };
+ };
+
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
reg = <0>;
label = "lan0";
+ phy-handle = <ðphy0>;
};
port@1 {
status = "disabled";
reg = <1>;
label = "lan1";
+ phy-handle = <ðphy1>;
};
port@2 {
status = "disabled";
reg = <2>;
label = "lan2";
+ phy-handle = <ðphy2>;
};
port@3 {
status = "disabled";
reg = <3>;
label = "lan3";
+ phy-handle = <ðphy3>;
};
port@4 {
status = "disabled";
reg = <4>;
label = "lan4";
+ phy-handle = <ðphy4>;
};
port@6 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy4>;
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&pcie {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
status = "okay";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&gmac0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy4>;
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&pcie {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy4>;
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy4>;
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include <dt-bindings/leds/common.h>
-
-#include "mt7621_dlink_dir-xx60-a1.dtsi"
+#include "mt7621_dlink_dir_nand_128m.dtsi"
/ {
compatible = "dlink,dir-1960-a1", "mediatek,mt7621-soc";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_dlink_dir_nand_128m.dtsi"
+
+/ {
+ compatible = "dlink,dir-2150-a1", "mediatek,mt7621-soc";
+ model = "D-Link DIR-2150 A1";
+};
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include "mt7621_dlink_dir-xx60-a1.dtsi"
+#include "mt7621_dlink_dir_nand_128m.dtsi"
/ {
compatible = "dlink,dir-2640-a1", "mediatek,mt7621-soc";
};
&leds {
- usb2_white {
- label = "white:usb2";
+ led-4 {
+ function = LED_FUNCTION_USB;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <2>;
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
trigger-sources = <&ehci_port2>;
linux,default-trigger = "usbport";
};
- usb3_white {
- label = "white:usb3";
+ led-5 {
+ function = LED_FUNCTION_USB;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <3>;
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
trigger-sources = <&xhci_ehci_port1>;
linux,default-trigger = "usbport";
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include "mt7621_dlink_dir-xx60-a1.dtsi"
+#include "mt7621_dlink_dir_nand_128m.dtsi"
/ {
compatible = "dlink,dir-2660-a1", "mediatek,mt7621-soc";
};
&leds {
- usb2_white {
- label = "white:usb2";
+ led-4 {
+ function = LED_FUNCTION_USB;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <2>;
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
trigger-sources = <&ehci_port2>;
linux,default-trigger = "usbport";
};
- usb3_white {
- label = "white:usb3";
+ led-5 {
+ function = LED_FUNCTION_USB;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <3>;
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
trigger-sources = <&xhci_ehci_port1>;
linux,default-trigger = "usbport";
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_dlink_dir_nand_128m.dtsi"
+
+/ {
+ compatible = "dlink,dir-3040-a1", "mediatek,mt7621-soc";
+ model = "D-Link DIR-3040 A1";
+};
+
+&wps {
+ gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+};
+
+&leds {
+ led-4 {
+ function = LED_FUNCTION_USB;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <2>;
+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&ehci_port2>;
+ linux,default-trigger = "usbport";
+ };
+
+ led-5 {
+ function = LED_FUNCTION_USB;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <3>;
+ gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+ trigger-sources = <&xhci_ehci_port1>;
+ linux,default-trigger = "usbport";
+ };
+
+ led-6 {
+ function = LED_FUNCTION_WLAN_2GHZ;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0radio";
+ };
+
+ led-7 {
+ function = LED_FUNCTION_WLAN_5GHZ;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <0>;
+ gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy1radio";
+ };
+
+ led-8 {
+ function = LED_FUNCTION_WLAN_5GHZ;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <1>;
+ gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy2radio";
+ };
+};
+
+&wifi0 {
+ nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_e000 1>;
+ nvmem-cell-names = "eeprom", "mac-address";
+ ieee80211-freq-limit;
+ /delete-property/ ieee80211-freq-limit;
+};
+
+&wifi1 {
+ nvmem-cells = <&eeprom_factory_8000>, <&macaddr_factory_e000 3>;
+ nvmem-cell-names = "eeprom", "mac-address";
+};
leds {
compatible = "gpio-leds";
- led_power_orange: power_orange {
+ led_power_orange: led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_ORANGE>;
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
};
- led_power_white: power_white {
+ led_power_white: led-1 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
- led_net_orange: net_orange {
- label = "orange:net";
+ led_net_orange: led-2 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_ORANGE>;
gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
};
- net_white {
- label = "white:net";
+ led-3 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_WHITE>;
gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
};
- usb2_white {
- label = "white:usb2";
+ led-4 {
+ function = LED_FUNCTION_USB;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <2>;
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
trigger-sources = <&ehci_port2>;
linux,default-trigger = "usbport";
};
- usb3_white {
- label = "white:usb3";
+ led-5 {
+ function = LED_FUNCTION_USB;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <3>;
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
trigger-sources = <&xhci_ehci_port1>;
linux,default-trigger = "usbport";
};
- wlan2g {
- label = "white:wlan2g";
+ led-6 {
+ function = LED_FUNCTION_WLAN_2GHZ;
+ color = <LED_COLOR_ID_WHITE>;
gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0radio";
};
- wlan5glb {
- label = "white:wlan5glb";
+ led-7 {
+ function = LED_FUNCTION_WLAN_5GHZ;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <0>;
gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1radio";
};
- wlan5ghb {
- label = "white:wlan5ghb";
+ led-8 {
+ function = LED_FUNCTION_WLAN_5GHZ;
+ color = <LED_COLOR_ID_WHITE>;
+ function-enumerator = <1>;
gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy2radio";
};
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "mt7621.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- aliases {
- label-mac-device = &gmac0;
- led-boot = &led_power_orange;
- led-failsafe = &led_power_white;
- led-running = &led_power_white;
- led-upgrade = &led_net_orange;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds: leds {
- compatible = "gpio-leds";
-
- led_power_orange: power_orange {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
- };
-
- led_power_white: power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
- };
-
- led_net_orange: net_orange {
- label = "orange:net";
- gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
- };
-
- net_white {
- label = "white:net";
- gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Bootloader";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "config";
- reg = <0x80000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "factory";
- reg = <0x100000 0x40000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- eeprom_factory_0: eeprom@0 {
- reg = <0x0 0x4da8>;
- };
-
- eeprom_factory_8000: eeprom@8000 {
- reg = <0x8000 0x4da8>;
- };
-
- macaddr_factory_e000: macaddr@e000 {
- compatible = "mac-base";
- reg = <0xe000 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@140000 {
- label = "config2";
- reg = <0x140000 0x40000>;
- read-only;
- };
-
- partition@180000 {
- label = "firmware";
- compatible = "openwrt,uimage", "denx,uimage";
- openwrt,padding = <96>;
- reg = <0x180000 0x2800000>;
- };
-
- partition@2980000 {
- label = "private";
- reg = <0x2980000 0x2000000>;
- read-only;
- };
-
- partition@4980000 {
- label = "firmware2";
- reg = <0x4980000 0x2800000>;
- };
-
- partition@7180000 {
- label = "mydlink";
- reg = <0x7180000 0x600000>;
- read-only;
- };
-
- partition@7780000 {
- label = "reserved";
- reg = <0x7780000 0x880000>;
- read-only;
- };
- };
-};
-
-&pcie {
- status = "okay";
-};
-
-&pcie0 {
- wifi0: wifi@0,0 {
- compatible = "mediatek,mt76";
- reg = <0x0000 0 0 0 0>;
- nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_e000 1>;
- nvmem-cell-names = "eeprom", "mac-address";
- ieee80211-freq-limit = <2400000 2500000>;
-
- led {
- led-active-low;
- };
- };
-};
-
-&pcie1 {
- wifi1: wifi@0,0 {
- compatible = "mediatek,mt76";
- reg = <0x0000 0 0 0 0>;
- nvmem-cells = <&eeprom_factory_8000>, <&macaddr_factory_e000 2>;
- nvmem-cell-names = "eeprom", "mac-address";
- ieee80211-freq-limit = <5000000 6000000>;
-
- led {
- led-active-low;
- };
- };
-};
-
-&gmac0 {
- nvmem-cells = <&macaddr_factory_e000 0>;
- nvmem-cell-names = "mac-address";
-};
-
-&gmac1 {
- status = "okay";
- label = "wan";
- phy-handle = <ðphy4>;
-
- nvmem-cells = <&macaddr_factory_e000 3>;
- nvmem-cell-names = "mac-address";
-};
-
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
-};
-
-&switch0 {
- ports {
- port@0 {
- status = "okay";
- label = "lan4";
- };
-
- port@1 {
- status = "okay";
- label = "lan3";
- };
-
- port@2 {
- status = "okay";
- label = "lan2";
- };
-
- port@3 {
- status = "okay";
- label = "lan1";
- };
- };
-};
-
-&state_default {
- gpio {
- groups = "i2c", "uart3", "jtag", "wdt";
- function = "gpio";
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ label-mac-device = &gmac0;
+ led-boot = &led_power_orange;
+ led-failsafe = &led_power_white;
+ led-running = &led_power_white;
+ led-upgrade = &led_net_orange;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps: wps {
+ label = "wps";
+ gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ led_power_orange: led-0 {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_ORANGE>;
+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+ };
+
+ led_power_white: led-1 {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+ };
+
+ led_net_orange: led-2 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_ORANGE>;
+ gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+ };
+
+ led-3 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&nand {
+ status = "okay";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "Bootloader";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "config";
+ reg = <0x80000 0x80000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "factory";
+ reg = <0x100000 0x40000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory_0: eeprom@0 {
+ reg = <0x0 0x4da8>;
+ };
+
+ eeprom_factory_8000: eeprom@8000 {
+ reg = <0x8000 0x4da8>;
+ };
+
+ macaddr_factory_e000: macaddr@e000 {
+ compatible = "mac-base";
+ reg = <0xe000 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ partition@140000 {
+ label = "config2";
+ reg = <0x140000 0x40000>;
+ read-only;
+ };
+
+ partition@180000 {
+ label = "firmware";
+ compatible = "openwrt,uimage", "denx,uimage";
+ openwrt,padding = <96>;
+ reg = <0x180000 0x2800000>;
+ };
+
+ partition@2980000 {
+ label = "private";
+ reg = <0x2980000 0x2000000>;
+ read-only;
+ };
+
+ partition@4980000 {
+ label = "firmware2";
+ reg = <0x4980000 0x2800000>;
+ };
+
+ partition@7180000 {
+ label = "mydlink";
+ reg = <0x7180000 0x600000>;
+ read-only;
+ };
+
+ partition@7780000 {
+ label = "reserved";
+ reg = <0x7780000 0x880000>;
+ read-only;
+ };
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&pcie0 {
+ wifi0: wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_e000 1>;
+ nvmem-cell-names = "eeprom", "mac-address";
+ ieee80211-freq-limit = <2400000 2500000>;
+
+ led {
+ led-active-low;
+ };
+ };
+};
+
+&pcie1 {
+ wifi1: wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cells = <&eeprom_factory_8000>, <&macaddr_factory_e000 2>;
+ nvmem-cell-names = "eeprom", "mac-address";
+ ieee80211-freq-limit = <5000000 6000000>;
+
+ led {
+ led-active-low;
+ };
+ };
+};
+
+&gmac0 {
+ nvmem-cells = <&macaddr_factory_e000 0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&gmac1 {
+ status = "okay";
+ label = "wan";
+ phy-handle = <ðphy4>;
+
+ nvmem-cells = <&macaddr_factory_e000 3>;
+ nvmem-cell-names = "mac-address";
+};
+
+ðphy4 {
+ /delete-property/ interrupts;
+};
+
+&switch0 {
+ ports {
+ port@0 {
+ status = "okay";
+ label = "lan4";
+ };
+
+ port@1 {
+ status = "okay";
+ label = "lan3";
+ };
+
+ port@2 {
+ status = "okay";
+ label = "lan2";
+ };
+
+ port@3 {
+ status = "okay";
+ label = "lan1";
+ };
+ };
+};
+
+&state_default {
+ gpio {
+ groups = "i2c", "uart3", "jtag", "wdt";
+ function = "gpio";
+ };
+};
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_elecom_wrc-gs-1pci.dtsi"
+
+/ {
+ compatible = "elecom,wmc-m1267gst2", "mediatek,mt7621-soc";
+ model = "ELECOM WMC-M1267GST2";
+};
+
+&gmac0 {
+ nvmem-cells = <&macaddr_factory_fff4>;
+ nvmem-cell-names = "mac-address";
+};
+
+&gmac1 {
+ nvmem-cells = <&macaddr_factory_fffa>;
+ nvmem-cell-names = "mac-address";
+};
+
+&partitions {
+ partition@50000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x50000 0x1800000>;
+ };
+
+ partition@1850000 {
+ label = "tm_pattern";
+ reg = <0x1850000 0x400000>;
+ read-only;
+ };
+
+ partition@1c50000 {
+ label = "tm_key";
+ reg = <0x1c50000 0x100000>;
+ read-only;
+ };
+
+ partition@1d50000 {
+ label = "nvram";
+ reg = <0x1d50000 0xb0000>;
+ read-only;
+ };
+
+ partition@1e00000 {
+ label = "user_data";
+ reg = <0x1e00000 0x200000>;
+ read-only;
+ };
+};
+
+&wifi {
+ nvmem-cells = <&macaddr_factory_4 (-1)>;
+ nvmem-cell-names = "mac-address";
+};
+
+&factory {
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_factory_4: macaddr@4 {
+ compatible = "mac-base";
+ reg = <0x4 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ macaddr_factory_fff4: macaddr@fff4 {
+ reg = <0xfff4 0x6>;
+ };
+
+ macaddr_factory_fffa: macaddr@fffa {
+ reg = <0xfffa 0x6>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_elecom_wrc-gs-1pci.dtsi"
+
+/ {
+ compatible = "elecom,wmc-s1267gs2", "mediatek,mt7621-soc";
+ model = "ELECOM WMC-S1267GS2";
+
+ aliases {
+ /*
+ * A MAC address printed to the label is an address of
+ * 5 GHz band on stock firmware, but there is no
+ * per-band MAC address support on Linux Kernel and that
+ * address is not assigned to any wlan devices now.
+ */
+ /delete-property/ label-mac-device;
+ };
+};
+
+&gmac0 {
+ nvmem-cells = <&macaddr_factory_fff4>;
+ nvmem-cell-names = "mac-address";
+};
+
+&gmac1 {
+ status = "disabled";
+};
+
+&partitions {
+ partition@50000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x50000 0x1800000>;
+ };
+
+ partition@1850000 {
+ label = "tm_pattern";
+ reg = <0x1850000 0x400000>;
+ read-only;
+ };
+
+ partition@1c50000 {
+ label = "tm_key";
+ reg = <0x1c50000 0x100000>;
+ read-only;
+ };
+
+ partition@1d50000 {
+ label = "nvram";
+ reg = <0x1d50000 0xb0000>;
+ read-only;
+ };
+
+ partition@1e00000 {
+ label = "user_data";
+ reg = <0x1e00000 0x200000>;
+ read-only;
+ };
+};
+
+&wifi {
+ nvmem-cells = <&macaddr_factory_4 (-1)>;
+ nvmem-cell-names = "mac-address";
+};
+
+&factory {
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_factory_4: macaddr@4 {
+ compatible = "mac-base";
+ reg = <0x4 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ macaddr_factory_fff4: macaddr@fff4 {
+ reg = <0xfff4 0x6>;
+ };
+ };
+};
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy4>;
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&nand {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&nand {
phy-handle = <ðphy4>;
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy4>;
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "jdcloud,re-cp-02", "mediatek,mt7621-soc";
+ model = "JDCloud RE-CP-02";
+
+ aliases {
+ label-mac-device = &gmac0;
+ led-boot = &led_status_blue;
+ led-failsafe = &led_status_red;
+ led-running = &led_status_green;
+ led-upgrade = &led_status_blue;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status_red: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_blue: led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_green: led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "wps";
+ gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+
+ reset {
+ label = "reset";
+ gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition@40000 {
+ compatible = "u-boot,env";
+ label = "Config";
+ reg = <0x40000 0x10000>;
+ };
+
+ partition@50000 {
+ label = "Factory";
+ reg = <0x50000 0x40000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory_0: eeprom@0 {
+ reg = <0x0 0xe00>;
+ };
+
+ macaddr_factory_3fff4: macaddr@3fff4 {
+ reg = <0x3fff4 0x6>;
+ };
+
+ macaddr_factory_3fffa: macaddr@3fffa {
+ reg = <0x3fffa 0x6>;
+ };
+ };
+ };
+
+ partition@90000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x90000 0xf70000>;
+ };
+ };
+ };
+};
+
+&state_default {
+ gpio {
+ groups = "uart3", "jtag", "wdt";
+ function = "gpio";
+ };
+};
+
+&sdhci {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
+&pcie1 {
+ wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cells = <&eeprom_factory_0>;
+ nvmem-cell-names = "eeprom";
+ mediatek,disable-radar-background;
+ };
+};
+
+&gmac0 {
+ nvmem-cells = <&macaddr_factory_3fff4>;
+ nvmem-cell-names = "mac-address";
+};
+
+&gmac1 {
+ status = "okay";
+ label = "wan";
+ phy-handle = <ðphy4>;
+
+ nvmem-cells = <&macaddr_factory_3fffa>;
+ nvmem-cell-names = "mac-address";
+};
+
+ðphy4 {
+ /delete-property/ interrupts;
+};
+
+&switch0 {
+ ports {
+ port@1 {
+ status = "okay";
+ label = "lan1";
+ };
+
+ port@2 {
+ status = "okay";
+ label = "lan2";
+ };
+
+ port@3 {
+ status = "okay";
+ label = "lan3";
+ };
+ };
+};
+
+&xhci {
+ status = "disabled";
+};
};
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&gmac0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy4>;
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy4>;
};
-&mdio {
- ethernet-phy@0 {
- status = "disabled";
- };
+ðphy0 {
+ interrupts = <0>;
+};
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy4>;
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
};
};
-ðernet {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>;
-};
-
&gmac0 {
nvmem-cells = <&macaddr_custom_40 0>;
nvmem-cell-names = "mac-address";
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy4>;
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&pcie {
status = "okay";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&gmac0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
};
};
-
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&state_default {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
-
&switch0 {
ports {
port@1 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy0>;
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
phy-handle = <ðphy4>;
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
-};
-
&pcie {
status = "okay";
};
};
};
-&gmac0 {
- nvmem-cells = <&macaddr_factory_3fff4>;
- nvmem-cell-names = "mac-address";
-};
-
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
-};
-
&switch0 {
ports {
port@3 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
-
&switch0 {
gpio-controller;
#gpio-cells = <2>;
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&nand {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
+ðphy4 {
+ /delete-property/ interrupts;
};
&switch0 {
nvmem-cell-names = "mac-address";
};
-&mdio {
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
+ðphy0 {
+ /delete-property/ interrupts;
};
&pcie {
};
&wmac {
- nvmem-cells = <&macaddr_factory_1f100>;
- nvmem-cell-names = "mac-address";
+ status = "okay";
+
+ nvmem-cells = <&eeprom_factory_20000>, <&macaddr_factory_1f100 0>;
+ nvmem-cell-names = "eeprom", "mac-address";
};
ðernet {
- nvmem-cells = <&macaddr_factory_1f100>;
+ nvmem-cells = <&macaddr_factory_1f100 0>;
nvmem-cell-names = "mac-address";
};
#size-cells = <1>;
macaddr_factory_1f100: macaddr@1f100 {
+ compatible = "mac-base";
reg = <0x1f100 0x6>;
+ #nvmem-cell-cells = <1>;
};
};
};
};
&wmac {
- nvmem-cells = <&macaddr_factory_1f100>;
- nvmem-cell-names = "mac-address";
+ status = "okay";
+
+ nvmem-cells = <&eeprom_factory_20000>, <&macaddr_factory_1f100 0>;
+ nvmem-cell-names = "eeprom", "mac-address";
};
ðernet {
- nvmem-cells = <&macaddr_factory_1f100>;
+ nvmem-cells = <&macaddr_factory_1f100 0>;
nvmem-cell-names = "mac-address";
};
#size-cells = <1>;
macaddr_factory_1f100: macaddr@1f100 {
+ compatible = "mac-base";
reg = <0x1f100 0x6>;
+ #nvmem-cell-cells = <1>;
};
};
};
do {
data_src = &hwstats->tx_bytes;
data_dst = data;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
start = u64_stats_fetch_begin(&hwstats->syncp);
-#else
- start = u64_stats_fetch_begin_irq(&hwstats->syncp);
-#endif
for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)
*data_dst++ = *data_src++;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
} while (u64_stats_fetch_retry(&hwstats->syncp, start));
-#else
- } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
-#endif
}
static struct ethtool_ops fe_ethtool_ops = {
}
do {
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
start = u64_stats_fetch_begin(&hwstats->syncp);
-#else
- start = u64_stats_fetch_begin_irq(&hwstats->syncp);
-#endif
storage->rx_packets = hwstats->rx_packets;
storage->tx_packets = hwstats->tx_packets;
storage->rx_bytes = hwstats->rx_bytes;
storage->rx_crc_errors = hwstats->rx_fcs_errors;
storage->rx_errors = hwstats->rx_checksum_errors;
storage->tx_aborted_errors = hwstats->tx_skip;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
} while (u64_stats_fetch_retry(&hwstats->syncp, start));
-#else
- } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
-#endif
storage->tx_errors = priv->netdev->stats.tx_errors;
storage->rx_dropped = priv->netdev->stats.rx_dropped;
#include <linux/dma-mapping.h>
#include <linux/phy.h>
#include <linux/ethtool.h>
-#include <linux/version.h>
enum fe_reg {
FE_REG_PDMA_GLO_CFG = 0,
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
-#include <linux/version.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio/driver.h>
#include <linux/pinctrl/pinconf.h>
gpiochip->set_multiple = aw9523_gpio_set_multiple;
gpiochip->set_config = gpiochip_generic_config;
gpiochip->parent = dev;
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
gpiochip->fwnode = dev->fwnode;
-#else
- gpiochip->of_node = dev->of_node;
-#endif
gpiochip->owner = THIS_MODULE;
gpiochip->can_sleep = true;
return regmap_reinit_cache(awi->regmap, &aw9523_regmap);
}
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
static int aw9523_probe(struct i2c_client *client)
-#else
-static int aw9523_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
-#endif
{
struct device *dev = &client->dev;
struct pinctrl_desc *pdesc;
endef
TARGET_DEVICES += tplink_archer-mr200
+define Device/tplink_ec220-g5-v2
+ $(Device/tplink-v2)
+ SOC := mt7620a
+ IMAGE_SIZE := 7808k
+ TPLINK_FLASHLAYOUT := 8Mmtk
+ TPLINK_HWID := 0x02015a15
+ TPLINK_HWREV := 0x55000600
+ TPLINK_HWREVADD := 0x03000000
+ IMAGES += tftp-recovery.bin
+ IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)
+ DEVICE_MODEL := EC220-G5
+ DEVICE_VARIANT := v2
+ DEVICE_PACKAGES := kmod-mt76x2 kmod-switch-rtl8367b
+endef
+TARGET_DEVICES += tplink_ec220-g5-v2
+
define Device/tplink_re200-v1
$(Device/tplink-v1)
SOC := mt7620a
endef
TARGET_DEVICES += wavlink_wl-wn530hg4
+define Device/wavlink_wl-wn531g3
+ SOC := mt7620a
+ IMAGE_SIZE := 7808k
+ DEVICE_VENDOR := Wavlink
+ DEVICE_MODEL := WL-WN531G3
+ DEVICE_PACKAGES := kmod-mt76x2 kmod-phy-realtek kmod-usb2 kmod-usb-ohci
+endef
+TARGET_DEVICES += wavlink_wl-wn531g3
+
define Device/wavlink_wl-wn535k1
SOC := mt7620a
IMAGE_SIZE := 7360k
check-size | append-metadata
endef
-define Device/dlink_dir-xx60-a1
+define Device/dlink_dir_nand_128m
$(Device/nand)
IMAGE_SIZE := 40960k
DEVICE_VENDOR := D-Link
TARGET_DEVICES += dlink_dir-1935-a1
define Device/dlink_dir-1960-a1
- $(Device/dlink_dir-xx60-a1)
+ $(Device/dlink_dir_nand_128m)
DEVICE_MODEL := DIR-1960
DEVICE_VARIANT := A1
endef
TARGET_DEVICES += dlink_dir-1960-a1
+define Device/dlink_dir-2150-a1
+ $(Device/dlink_dir_nand_128m)
+ DEVICE_MODEL := DIR-2150
+ DEVICE_VARIANT := A1
+ DEVICE_PACKAGES += kmod-mt7603 -kmod-usb3 -kmod-usb-ledtrig-usbport
+ IMAGES += factory.bin
+ IMAGE/factory.bin := $$(IMAGE/recovery.bin) | dlink-sge-image $$(DEVICE_MODEL)
+endef
+TARGET_DEVICES += dlink_dir-2150-a1
+
define Device/dlink_dir-2640-a1
- $(Device/dlink_dir-xx60-a1)
+ $(Device/dlink_dir_nand_128m)
DEVICE_MODEL := DIR-2640
DEVICE_VARIANT := A1
endef
TARGET_DEVICES += dlink_dir-2640-a1
define Device/dlink_dir-2660-a1
- $(Device/dlink_dir-xx60-a1)
+ $(Device/dlink_dir_nand_128m)
DEVICE_MODEL := DIR-2660
DEVICE_VARIANT := A1
endef
TARGET_DEVICES += dlink_dir-2660-a1
+define Device/dlink_dir-3040-a1
+ $(Device/dlink_dir_nand_128m)
+ DEVICE_MODEL := DIR-3040
+ DEVICE_VARIANT := A1
+endef
+TARGET_DEVICES += dlink_dir-3040-a1
+
define Device/dlink_dir-3060-a1
- $(Device/dlink_dir-xx60-a1)
+ $(Device/dlink_dir_nand_128m)
DEVICE_MODEL := DIR-3060
DEVICE_VARIANT := A1
endef
TARGET_DEVICES += dlink_dir-853-a1
define Device/dlink_dir-853-a3
- $(Device/dlink_dir-xx60-a1)
+ $(Device/dlink_dir_nand_128m)
DEVICE_MODEL := DIR-853
DEVICE_VARIANT := A3
IMAGES += factory.bin
endef
TARGET_DEVICES += edimax_rg21s
-define Device/elecom_wrc-1167ghbk2-s
+define Device/elecom_wrc-gs
$(Device/dsa-migration)
- IMAGE_SIZE := 15488k
+ $(Device/uimage-lzma-loader)
DEVICE_VENDOR := ELECOM
- DEVICE_MODEL := WRC-1167GHBK2-S
IMAGES += factory.bin
IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \
- elecom-wrc-gs-factory WRC-1167GHBK2-S 0.00
+ elecom-wrc-gs-factory $$$$(ELECOM_HWNAME) 0.00 -N | \
+ append-string MT7621_ELECOM_$$$$(ELECOM_HWNAME)
DEVICE_PACKAGES := kmod-mt7615-firmware -uboot-envtools
endef
-TARGET_DEVICES += elecom_wrc-1167ghbk2-s
-define Device/elecom_wrc-gs
+define Device/elecom_wmc-m1267gst2
+ $(Device/elecom_wrc-gs)
+ IMAGE_SIZE := 24576k
+ DEVICE_MODEL := WMC-M1267GST2
+ ELECOM_HWNAME := WMC-DLGST2
+endef
+TARGET_DEVICES += elecom_wmc-m1267gst2
+
+define Device/elecom_wmc-s1267gs2
+ $(Device/elecom_wrc-gs)
+ IMAGE_SIZE := 24576k
+ DEVICE_MODEL := WMC-S1267GS2
+ ELECOM_HWNAME := WMC-DLGST2
+endef
+TARGET_DEVICES += elecom_wmc-s1267gs2
+
+define Device/elecom_wrc-1167ghbk2-s
$(Device/dsa-migration)
- $(Device/uimage-lzma-loader)
+ IMAGE_SIZE := 15488k
DEVICE_VENDOR := ELECOM
+ DEVICE_MODEL := WRC-1167GHBK2-S
IMAGES += factory.bin
IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \
- elecom-wrc-gs-factory $$$$(ELECOM_HWNAME) 0.00 -N | \
- append-string MT7621_ELECOM_$$$$(ELECOM_HWNAME)
+ elecom-wrc-gs-factory WRC-1167GHBK2-S 0.00
DEVICE_PACKAGES := kmod-mt7615-firmware -uboot-envtools
endef
+TARGET_DEVICES += elecom_wrc-1167ghbk2-s
define Device/elecom_wrc-1167gs2-b
$(Device/elecom_wrc-gs)
endef
TARGET_DEVICES += jcg_y2
+define Device/jdcloud_re-cp-02
+ $(Device/dsa-migration)
+ IMAGE_SIZE := 16000k
+ DEVICE_VENDOR := JD-Cloud
+ DEVICE_MODEL := RE-CP-02
+ DEVICE_PACKAGES := kmod-mt7915-firmware kmod-sdhci-mt7620
+endef
+TARGET_DEVICES += jdcloud_re-cp-02
+
define Device/keenetic_kn-3010
$(Device/dsa-migration)
$(Device/uimage-lzma-loader)
ucidef_set_led_netdev "lan" "lan" "white:lan" "eth0.1"
ucidef_set_led_netdev "wan" "wan" "white:wan" "usb0"
;;
+tplink,ec220-g5-v2)
+ ucidef_set_led_switch "lan" "lan" "green:lan" "switch1" "0x17"
+ ucidef_set_led_switch "wan" "wan" "orange:wan" "switch1" "0x08"
+ ;;
tplink,re200-v1)
ucidef_set_led_netdev "lan" "lan" "green:lan" "eth0"
;;
"0:lan" "1:lan" "2:lan" "3:lan" "6t@eth0"
ucidef_set_interface_wan "usb0"
;;
+ tplink,ec220-g5-v2)
+ ucidef_add_switch "switch0"
+ ucidef_add_switch_attr "switch0" "enable" "0"
+ ucidef_add_switch "switch1" \
+ "0:lan:3" "1:lan:2" "2:lan:1" "4:lan:4" "3:wan" "7@eth0"
+ ;;
+ wavlink,wl-wn531g3)
+ ucidef_add_switch "switch0" \
+ "0:lan:4" "1:lan:3" "2:lan:2" "5:lan:1" "4:wan" "6@eth0"
+ ;;
wavlink,wl-wn535k1)
ucidef_add_switch "switch0" \
"2:lan:2" "5:lan:1" "4:wan" "6@eth0"
tplink,archer-c20i|\
tplink,archer-c5-v4|\
tplink,archer-c50-v1|\
- tplink,archer-mr200)
+ tplink,archer-mr200|\
+ tplink,ec220-g5-v2)
wan_mac=$(macaddr_add "$(mtd_get_mac_binary rom 0xf100)" 1)
;;
+ wavlink,wl-wn531g3|\
+ zbtlink,zbt-we1026-5g-16m)
+ label_mac=$(mtd_get_mac_binary factory 0x4)
+ ;;
wavlink,wl-wn535k1)
wan_mac=$(mtd_get_mac_binary factory 0x2e)
label_mac=$(mtd_get_mac_binary factory 0x8004)
;;
- zbtlink,zbt-we1026-5g-16m)
- label_mac=$(mtd_get_mac_binary factory 0x4)
- ;;
zyxel,keenetic-lite-iii-a)
lan_mac=$(mtd_get_mac_binary RF-EEPROM 0x4)
wan_mac=$(mtd_get_mac_binary RF-EEPROM 0x28)
+++ /dev/null
-CONFIG_AR8216_PHY=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_SYSTICK_QUIRK=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_MTMIPS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-# CONFIG_DTB_OMEGA2P is not set
-CONFIG_DTB_RT_NONE=y
-# CONFIG_DTB_VOCORE2 is not set
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_CDEV=y
-# CONFIG_GPIO_MT7621 is not set
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_WATCHDOG=y
-# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MT7621_WDT is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_JIMAGE_FW=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_VIRT_CONCAT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK_GSW_MT7620=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MDIO_MT7620=y
-CONFIG_NET_RALINK_MT7620=y
-# CONFIG_NET_RALINK_RT3050 is not set
-CONFIG_NET_RALINK_SOC=y
-CONFIG_NET_SELFTESTS=y
-# CONFIG_NET_VENDOR_MEDIATEK is not set
-CONFIG_NET_VENDOR_RALINK=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-# CONFIG_PHY_MT7621_PCI is not set
-CONFIG_PHY_RALINK_USB=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_AW9523 is not set
-CONFIG_PINCTRL_MT7620=y
-CONFIG_PINCTRL_RALINK=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RALINK=y
-CONFIG_RALINK_WDT=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWCONFIG_LEDS=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "green:rssihigh" "wlan1" "76" "100"
;;
dlink,dir-1960-a1|\
+dlink,dir-2150-a1|\
dlink,dir-2640-a1|\
dlink,dir-2660-a1)
- ucidef_set_led_netdev "wan" "wan" "white:net" "wan"
+ ucidef_set_led_netdev "wan" "wan" "white:wan" "wan"
;;
+dlink,dir-3040-a1|\
dlink,dir-3060-a1)
- ucidef_set_led_netdev "net_white" "WAN Link" "white:net" "wan" "link"
- ucidef_set_led_netdev "net_orange" "WAN Activity" "orange:net" "wan" "tx rx"
+ ucidef_set_led_netdev "net_white" "WAN Link" "white:wan" "wan" "link"
+ ucidef_set_led_netdev "net_orange" "WAN Activity" "orange:wan" "wan" "tx rx"
;;
dlink,dir-853-a1|\
dlink,dir-853-a3)
dlink,covr-x1860-a1)
ucidef_set_interfaces_lan_wan "ethernet" "internet"
;;
+ elecom,wmc-s1267gs2|\
+ linksys,re6500|\
+ netgear,wac104|\
+ zyxel,lte3301-plus)
+ ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
+ ;;
gnubee,gb-pc1)
ucidef_set_interface_lan "ethblack ethblue"
;;
gnubee,gb-pc2)
ucidef_set_interface_lan "ethblack ethblue ethyellow"
;;
- linksys,re6500|\
- netgear,wac104|\
- zyxel,lte3301-plus)
- ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
- ;;
mikrotik,routerboard-750gr3)
ucidef_set_interfaces_lan_wan "lan2 lan3 lan4 lan5" "wan"
;;
[ "$PHYNBR" = "1" ] && \
macaddr_add $hw_mac_addr 4 > /sys${DEVPATH}/macaddress
;;
+ dlink,dir-3040-a1)
+ lan_mac_addr="$(mtd_get_mac_binary factory 0xe000)"
+ [ "$PHYNBR" = "0" ] && \
+ macaddr_add $lan_mac_addr 2 > /sys${DEVPATH}/macaddress
+ ;;
dlink,dir-853-a3)
[ "$PHYNBR" = "0" ] && \
macaddr_setbit_la "$(mtd_get_mac_binary factory 0xe000)" \
$((0xff)) ]] || printf '\xff' | dd of=/dev/mtdblock3 \
count=1 bs=1 seek=$((0x20001))
;;
+ jdcloud,re-cp-02)
+ echo -e "bootcount 0\nbootlimit 5\nupgrade_available 1" | /usr/sbin/fw_setenv -s -
+ ;;
linksys,e5600|\
linksys,ea6350-v4|\
linksys,ea7300-v1|\
board=$(board_name)
case "$board" in
+dlink,dir-1960-a1|\
+dlink,dir-2640-a1|\
+dlink,dir-2660-a1|\
+dlink,dir-3040-a1|\
+dlink,dir-3060-a1)
+ migrate_leds ':net=:wan'
+ ;;
tplink,archer-a6-v3|\
tplink,archer-c6-v3)
migrate_leds ':wifi2g$=:wlan-2' ':wifi5g$=:wlan-5'
dlink,covr-x1860-a1|\
dlink,dap-x1860-a1|\
dlink,dir-1960-a1|\
+ dlink,dir-2150-a1|\
dlink,dir-2640-a1|\
dlink,dir-2660-a1|\
+ dlink,dir-3040-a1|\
dlink,dir-3060-a1|\
dlink,dir-853-a3|\
etisalat,s3|\
+++ /dev/null
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_AT803X_PHY=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOARD_SCACHE=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKSRC_MIPS_GIC=y
-CONFIG_CLK_MT7621=y
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_MIPSR2_IRQ_EI=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DIMLIB=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_MT7621=y
-# CONFIG_GPIO_RALINK is not set
-CONFIG_GPIO_WATCHDOG=y
-# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
-CONFIG_GRO_CELLS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_MT7621=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIATEK_GE_PHY=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIKROTIK=y
-CONFIG_MIKROTIK_RB_SYSFS=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-CONFIG_MIPS_CM=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_CPC=y
-CONFIG_MIPS_CPS=y
-# CONFIG_MIPS_CPS_NS16550_BOOL is not set
-CONFIG_MIPS_CPU_SCACHE=y
-CONFIG_MIPS_GIC=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-CONFIG_MIPS_MT=y
-CONFIG_MIPS_MT_FPAFF=y
-CONFIG_MIPS_MT_SMP=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_NR_CPU_NR_MAP=4
-CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MT7621_WDT=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_MT7621=y
-CONFIG_MTD_NAND_MTK_BMT=y
-# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_ROUTERBOOT_PARTS=y
-CONFIG_MTD_SERCOMM_PARTS=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SPLIT_MINOR_FW=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_TRX_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_VIRT_CONCAT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
-CONFIG_NET_DSA_MT7530_MDIO=y
-# CONFIG_NET_DSA_MT7530_MMIO is not set
-CONFIG_NET_DSA_TAG_MTK=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NET_VENDOR_MEDIATEK=y
-# CONFIG_NET_VENDOR_RALINK is not set
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_POOL_STATS=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCIE_MT7621=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_DRIVERS_GENERIC=y
-CONFIG_PCS_MTK_LYNXI=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_MT7621_PCI=y
-# CONFIG_PHY_RALINK_USB is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AW9523=y
-CONFIG_PINCTRL_MT7621=y
-CONFIG_PINCTRL_RALINK=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_SX150X=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QCOM_NET_PHYLIB=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RALINK=y
-# CONFIG_RALINK_WDT is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BQ32K=y
-CONFIG_RTC_DRV_PCF8563=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_SMT=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-CONFIG_SMP_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-# CONFIG_SOC_MT7620 is not set
-CONFIG_SOC_MT7621=y
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT7621=y
-# CONFIG_SPI_RT2880 is not set
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SYNC_R4K=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_HIGHMEM=y
-CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_MIPS_CPS=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_SYS_SUPPORTS_SCHED_SMT=y
-CONFIG_SYS_SUPPORTS_SMP=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WEAK_ORDERING=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_SYSTICK_QUIRK=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_MTMIPS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-# CONFIG_DTB_OMEGA2P is not set
-CONFIG_DTB_RT_NONE=y
-# CONFIG_DTB_VOCORE2 is not set
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_MT7621=y
-# CONFIG_GPIO_RALINK is not set
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MT7621_WDT=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_TPLINK_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_VIRT_CONCAT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK_ESW_RT3050=y
-# CONFIG_NET_RALINK_MT7620 is not set
-CONFIG_NET_RALINK_RT3050=y
-CONFIG_NET_RALINK_SOC=y
-CONFIG_NET_SELFTESTS=y
-# CONFIG_NET_VENDOR_MEDIATEK is not set
-CONFIG_NET_VENDOR_RALINK=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-# CONFIG_PHY_MT7621_PCI is not set
-CONFIG_PHY_RALINK_USB=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_AW9523 is not set
-CONFIG_PINCTRL_MT7620=y
-CONFIG_PINCTRL_RALINK=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RALINK=y
-# CONFIG_RALINK_WDT is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_8250_RUNTIME_UARTS=3
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_MT7621=y
-# CONFIG_SPI_RT2880 is not set
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWCONFIG_LEDS=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
+++ /dev/null
-From 35dcae535afc153fa83f2fe51c0812536c192c58 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 6 Feb 2023 09:33:05 +0100
-Subject: [PATCH] clk: ralink: fix 'mt7621_gate_is_enabled()' function
-
-Compiling clock driver with CONFIG_UBSAN enabled shows the following trace:
-
-UBSAN: shift-out-of-bounds in drivers/clk/ralink/clk-mt7621.c:121:15
-shift exponent 131072 is too large for 32-bit type 'long unsigned int'
-CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.86 #0
-Stack : ...
-
-Call Trace:
-[<80009a58>] show_stack+0x38/0x118
-[<8045ce04>] dump_stack_lvl+0x60/0x80
-[<80458868>] ubsan_epilogue+0x10/0x54
-[<804590e0>] __ubsan_handle_shift_out_of_bounds+0x118/0x190
-[<804c9a10>] mt7621_gate_is_enabled+0x98/0xa0
-[<804bb774>] clk_core_is_enabled+0x34/0x90
-[<80aad73c>] clk_disable_unused_subtree+0x98/0x1e4
-[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
-[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
-[<80aad900>] clk_disable_unused+0x78/0x120
-[<80002030>] do_one_initcall+0x54/0x1f0
-[<80a922a4>] kernel_init_freeable+0x280/0x31c
-[<808047c4>] kernel_init+0x20/0x118
-[<80003e58>] ret_from_kernel_thread+0x14/0x1c
-
-Shifting a value (131032) larger than the type (32 bit unsigned integer)
-is undefined behaviour in C.
-
-The problem is in 'mt7621_gate_is_enabled()' function which is using the
-'BIT()' kernel macro with the bit index for the clock gate to check if the
-bit is set. When the clock gates structure is created driver is already
-setting 'bit_idx' using 'BIT()' macro, so we are wrongly applying an extra
-'BIT()' mask here. Removing it solve the problem and makes this function
-correct. However when clock gating is correctly working, the kernel starts
-disabling those clocks that are not requested. Some drivers for this SoC
-are older than this clock driver itself. So to avoid the kernel to disable
-clocks that have been enabled until now, we must apply 'CLK_IS_CRITICAL'
-flag on gates initialization code.
-
-Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Link: https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/ralink/clk-mt7621.c | 10 ++++++++--
- 1 file changed, 8 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/ralink/clk-mt7621.c
-+++ b/drivers/clk/ralink/clk-mt7621.c
-@@ -121,7 +121,7 @@ static int mt7621_gate_is_enabled(struct
- if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val))
- return 0;
-
-- return val & BIT(clk_gate->bit_idx);
-+ return val & clk_gate->bit_idx;
- }
-
- static const struct clk_ops mt7621_gate_ops = {
-@@ -133,8 +133,14 @@ static const struct clk_ops mt7621_gate_
- static int mt7621_gate_ops_init(struct device *dev,
- struct mt7621_gate *sclk)
- {
-+ /*
-+ * There are drivers for this SoC that are older
-+ * than clock driver and are not prepared for the clock.
-+ * We don't want the kernel to disable anything so we
-+ * add CLK_IS_CRITICAL flag here.
-+ */
- struct clk_init_data init = {
-- .flags = CLK_SET_RATE_PARENT,
-+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
- .num_parents = 1,
- .parent_names = &sclk->parent_name,
- .ops = &mt7621_gate_ops,
+++ /dev/null
-From 612616e6381929e7f9e303f8b8ad3655cc101516 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:33 +0200
-Subject: [PATCH 1/9] dt-bindings: clock: add mtmips SoCs system controller
-
-Adds device tree binding documentation for system controller node present
-in Mediatek MIPS and Ralink SOCs. This node is a clock and reset provider
-for the rest of the world. This covers RT2880, RT3050, RT3052, RT3350,
-RT3883, RT5350, MT7620, MT7628 and MT7688 SoCs.
-
-Reviewed-by: Rob Herring <robh@kernel.org>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- .../bindings/clock/mediatek,mtmips-sysc.yaml | 64 ++++++++++++++++++++++
- 1 file changed, 64 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
-@@ -0,0 +1,64 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MTMIPS SoCs System Controller
-+
-+maintainers:
-+ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
-+
-+description: |
-+ MediaTek MIPS and Ralink SoCs provides a system controller to allow
-+ to access to system control registers. These registers include clock
-+ and reset related ones so this node is both clock and reset provider
-+ for the rest of the world.
-+
-+ These SoCs have an XTAL from where the cpu clock is
-+ provided as well as derived clocks for the bus and the peripherals.
-+
-+properties:
-+ compatible:
-+ items:
-+ - enum:
-+ - ralink,mt7620-sysc
-+ - ralink,mt7628-sysc
-+ - ralink,mt7688-sysc
-+ - ralink,rt2880-sysc
-+ - ralink,rt3050-sysc
-+ - ralink,rt3052-sysc
-+ - ralink,rt3352-sysc
-+ - ralink,rt3883-sysc
-+ - ralink,rt5350-sysc
-+ - const: syscon
-+
-+ reg:
-+ maxItems: 1
-+
-+ '#clock-cells':
-+ description:
-+ The first cell indicates the clock number.
-+ const: 1
-+
-+ '#reset-cells':
-+ description:
-+ The first cell indicates the reset bit within the register.
-+ const: 1
-+
-+required:
-+ - compatible
-+ - reg
-+ - '#clock-cells'
-+ - '#reset-cells'
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ syscon@0 {
-+ compatible = "ralink,rt5350-sysc", "syscon";
-+ reg = <0x0 0x100>;
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ };
+++ /dev/null
-From 6f3b15586eef736831abe6a14f2a6906bc0dc074 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:34 +0200
-Subject: [PATCH 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs
-
-Until now, clock related code for old ralink SoCs was based in fixed clocks
-using 'clk_register_fixed_rate' and 'clkdev_create' directly doing in code
-and not using device tree at all for their definition. Including this driver
-is an effort to be able to define proper clocks using device tree and also
-cleaning all the clock and reset related code from 'arch/mips/ralink' dir.
-This clock and reset driver covers all the ralink SoCs but MT7621 which is
-the newest and provides gating and some differences that make it different
-from its predecesors. It has its own driver since some time ago. The ralink
-SoCs we are taking about are RT2880, RT3050, RT3052, RT3350, RT3352, RT3883,
-RT5350, MT7620, MT7628 and MT7688. Mostly the code in this new driver has
-been extracted from 'arch/mips/ralink' and cleanly put using kernel clock
-driver APIs. The clock plans for this SoCs only talks about relation between
-CPU frequency and BUS frequency. This relation is different depending on the
-particular SoC. CPU clock is derived from XTAL frequencies.
-
-Depending on the SoC we have the following frequencies:
-* RT2880 SoC:
- - XTAL: 40 MHz.
- - CPU: 250, 266, 280 or 300 MHz.
- - BUS: CPU / 2 MHz.
-* RT3050, RT3052, RT3350:
- - XTAL: 40 MHz.
- - CPU: 320 or 384 MHz.
- - BUS: CPU / 3 MHz.
-* RT3352:
- - XTAL: 40 MHz.
- - CPU: 384 or 400 MHz.
- - BUS: CPU / 3 MHz.
- - PERIPH: 40 MHz.
-* RT3383:
- - XTAL: 40 MHz.
- - CPU: 250, 384, 480 or 500 MHz.
- - BUS: Depends on RAM Type and CPU:
- + RAM DDR2: 125. ELSE 83 MHz.
- + RAM DDR2: 128. ELSE 96 MHz.
- + RAM DDR2: 160. ELSE 120 MHz.
- + RAM DDR2: 166. ELSE 125 MHz.
-* RT5350:
- - XTAL: 40 MHz.
- - CPU: 300, 320 or 360 MHz.
- - BUS: CPU / 3, CPU / 4, CPU / 3 MHz.
- - PERIPH: 40 MHz.
-* MT7628 and MT7688:
- - XTAL: 20 MHz or 40 MHz.
- - CPU: 575 or 580 MHz.
- - BUS: CPU / 3.
- - PCMI2S: 480 MHz.
- - PERIPH: 40 MHz.
-* MT7620:
- - XTAL: 20 MHz or 40 MHz.
- - PLL: XTAL, 480, 600 MHz.
- - CPU: depends on PLL and some mult and dividers.
- - BUS: depends on PLL and some mult and dividers.
- - PERIPH: 40 or XTAL MHz.
-
-MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of
-register reads and predividers. To derive CPU and BUS frequencies in the
-MT7620 SoC 'mt7620_calc_rate()' helper is used.
-
-In the case XTAL can have different frequencies and we need a different
-clock frequency for peripherals 'periph' clock in introduced.
-
-The rest of the peripherals present in the SoC just follow their parent
-frequencies.
-
-With this information the clk driver will provide all the clock and reset
-functionality from a set of hardcoded clocks allowing to define a nice
-device tree without fixed clocks.
-
-Acked-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- drivers/clk/ralink/Kconfig | 7 +
- drivers/clk/ralink/Makefile | 1 +
- drivers/clk/ralink/clk-mtmips.c | 1115 +++++++++++++++++++++++++++++++++++++++
- 3 files changed, 1123 insertions(+)
- create mode 100644 drivers/clk/ralink/clk-mtmips.c
-
---- a/drivers/clk/ralink/Kconfig
-+++ b/drivers/clk/ralink/Kconfig
-@@ -9,3 +9,10 @@ config CLK_MT7621
- select MFD_SYSCON
- help
- This driver supports MediaTek MT7621 basic clocks.
-+
-+config CLK_MTMIPS
-+ bool "Clock driver for MTMIPS SoCs"
-+ depends on SOC_RT305X || SOC_RT288X || SOC_RT3883 || SOC_MT7620 || COMPILE_TEST
-+ select MFD_SYSCON
-+ help
-+ This driver supports MTMIPS basic clocks.
---- a/drivers/clk/ralink/Makefile
-+++ b/drivers/clk/ralink/Makefile
-@@ -1,2 +1,3 @@
- # SPDX-License-Identifier: GPL-2.0
- obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
-+obj-$(CONFIG_CLK_MTMIPS) += clk-mtmips.o
---- /dev/null
-+++ b/drivers/clk/ralink/clk-mtmips.c
-@@ -0,0 +1,1115 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * MTMIPS SoCs Clock Driver
-+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-+ */
-+
-+#include <linux/bitops.h>
-+#include <linux/clk-provider.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/reset-controller.h>
-+#include <linux/slab.h>
-+
-+/* Configuration registers */
-+#define SYSC_REG_SYSTEM_CONFIG 0x10
-+#define SYSC_REG_CLKCFG0 0x2c
-+#define SYSC_REG_RESET_CTRL 0x34
-+#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
-+#define SYSC_REG_CPLL_CONFIG0 0x54
-+#define SYSC_REG_CPLL_CONFIG1 0x58
-+
-+/* RT2880 SoC */
-+#define RT2880_CONFIG_CPUCLK_SHIFT 20
-+#define RT2880_CONFIG_CPUCLK_MASK 0x3
-+#define RT2880_CONFIG_CPUCLK_250 0x0
-+#define RT2880_CONFIG_CPUCLK_266 0x1
-+#define RT2880_CONFIG_CPUCLK_280 0x2
-+#define RT2880_CONFIG_CPUCLK_300 0x3
-+
-+/* RT305X SoC */
-+#define RT305X_SYSCFG_CPUCLK_SHIFT 18
-+#define RT305X_SYSCFG_CPUCLK_MASK 0x1
-+#define RT305X_SYSCFG_CPUCLK_LOW 0x0
-+#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
-+
-+/* RT3352 SoC */
-+#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
-+#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
-+#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
-+#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
-+
-+/* RT3383 SoC */
-+#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
-+#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
-+#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
-+#define RT3883_SYSCFG0_CPUCLK_250 0x0
-+#define RT3883_SYSCFG0_CPUCLK_384 0x1
-+#define RT3883_SYSCFG0_CPUCLK_480 0x2
-+#define RT3883_SYSCFG0_CPUCLK_500 0x3
-+
-+/* RT5350 SoC */
-+#define RT5350_CLKCFG0_XTAL_SEL BIT(20)
-+#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
-+#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
-+#define RT5350_SYSCFG0_CPUCLK_360 0x0
-+#define RT5350_SYSCFG0_CPUCLK_320 0x2
-+#define RT5350_SYSCFG0_CPUCLK_300 0x3
-+
-+/* MT7620 and MT76x8 SoCs */
-+#define MT7620_XTAL_FREQ_SEL BIT(6)
-+#define CPLL_CFG0_SW_CFG BIT(31)
-+#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
-+#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
-+#define CPLL_CFG0_LC_CURFCK BIT(15)
-+#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
-+#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
-+#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
-+#define CPLL_CFG1_CPU_AUX1 BIT(25)
-+#define CPLL_CFG1_CPU_AUX0 BIT(24)
-+#define CLKCFG0_PERI_CLK_SEL BIT(4)
-+#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
-+#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
-+#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
-+#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
-+#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
-+#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
-+#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
-+#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
-+
-+/* clock scaling */
-+#define CLKCFG_FDIV_MASK 0x1f00
-+#define CLKCFG_FDIV_USB_VAL 0x0300
-+#define CLKCFG_FFRAC_MASK 0x001f
-+#define CLKCFG_FFRAC_USB_VAL 0x0003
-+
-+struct mtmips_clk;
-+struct mtmips_clk_fixed;
-+struct mtmips_clk_factor;
-+
-+struct mtmips_clk_data {
-+ struct mtmips_clk *clk_base;
-+ size_t num_clk_base;
-+ struct mtmips_clk_fixed *clk_fixed;
-+ size_t num_clk_fixed;
-+ struct mtmips_clk_factor *clk_factor;
-+ size_t num_clk_factor;
-+ struct mtmips_clk *clk_periph;
-+ size_t num_clk_periph;
-+};
-+
-+struct mtmips_clk_priv {
-+ struct regmap *sysc;
-+ const struct mtmips_clk_data *data;
-+};
-+
-+struct mtmips_clk {
-+ struct clk_hw hw;
-+ struct mtmips_clk_priv *priv;
-+};
-+
-+struct mtmips_clk_fixed {
-+ const char *name;
-+ const char *parent;
-+ unsigned long rate;
-+ struct clk_hw *hw;
-+};
-+
-+struct mtmips_clk_factor {
-+ const char *name;
-+ const char *parent;
-+ int mult;
-+ int div;
-+ unsigned long flags;
-+ struct clk_hw *hw;
-+};
-+
-+static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ return parent_rate;
-+}
-+
-+static const struct clk_ops mtmips_periph_clk_ops = {
-+ .recalc_rate = mtmips_pherip_clk_rate,
-+};
-+
-+#define CLK_PERIPH(_name, _parent) { \
-+ .init = &(const struct clk_init_data) { \
-+ .name = _name, \
-+ .ops = &mtmips_periph_clk_ops, \
-+ .parent_data = &(const struct clk_parent_data) {\
-+ .name = _parent, \
-+ .fw_name = _parent \
-+ }, \
-+ .num_parents = 1, \
-+ /* \
-+ * There are drivers for these SoCs that are \
-+ * older than clock driver and are not prepared \
-+ * for the clock. We don't want the kernel to \
-+ * disable anything so we add CLK_IS_CRITICAL \
-+ * flag here. \
-+ */ \
-+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL \
-+ }, \
-+}
-+
-+static struct mtmips_clk rt2880_pherip_clks[] = {
-+ { CLK_PERIPH("300100.timer", "bus") },
-+ { CLK_PERIPH("300120.watchdog", "bus") },
-+ { CLK_PERIPH("300500.uart", "bus") },
-+ { CLK_PERIPH("300900.i2c", "bus") },
-+ { CLK_PERIPH("300c00.uartlite", "bus") },
-+ { CLK_PERIPH("400000.ethernet", "bus") },
-+ { CLK_PERIPH("480000.wmac", "xtal") }
-+};
-+
-+static struct mtmips_clk rt305x_pherip_clks[] = {
-+ { CLK_PERIPH("10000100.timer", "bus") },
-+ { CLK_PERIPH("10000120.watchdog", "bus") },
-+ { CLK_PERIPH("10000500.uart", "bus") },
-+ { CLK_PERIPH("10000900.i2c", "bus") },
-+ { CLK_PERIPH("10000a00.i2s", "bus") },
-+ { CLK_PERIPH("10000b00.spi", "bus") },
-+ { CLK_PERIPH("10000b40.spi", "bus") },
-+ { CLK_PERIPH("10000c00.uartlite", "bus") },
-+ { CLK_PERIPH("10100000.ethernet", "bus") },
-+ { CLK_PERIPH("10180000.wmac", "xtal") }
-+};
-+
-+static struct mtmips_clk rt5350_pherip_clks[] = {
-+ { CLK_PERIPH("10000100.timer", "bus") },
-+ { CLK_PERIPH("10000120.watchdog", "bus") },
-+ { CLK_PERIPH("10000500.uart", "periph") },
-+ { CLK_PERIPH("10000900.i2c", "periph") },
-+ { CLK_PERIPH("10000a00.i2s", "periph") },
-+ { CLK_PERIPH("10000b00.spi", "bus") },
-+ { CLK_PERIPH("10000b40.spi", "bus") },
-+ { CLK_PERIPH("10000c00.uartlite", "periph") },
-+ { CLK_PERIPH("10100000.ethernet", "bus") },
-+ { CLK_PERIPH("10180000.wmac", "xtal") }
-+};
-+
-+static struct mtmips_clk mt7620_pherip_clks[] = {
-+ { CLK_PERIPH("10000100.timer", "periph") },
-+ { CLK_PERIPH("10000120.watchdog", "periph") },
-+ { CLK_PERIPH("10000500.uart", "periph") },
-+ { CLK_PERIPH("10000900.i2c", "periph") },
-+ { CLK_PERIPH("10000a00.i2s", "periph") },
-+ { CLK_PERIPH("10000b00.spi", "bus") },
-+ { CLK_PERIPH("10000b40.spi", "bus") },
-+ { CLK_PERIPH("10000c00.uartlite", "periph") },
-+ { CLK_PERIPH("10180000.wmac", "xtal") }
-+};
-+
-+static struct mtmips_clk mt76x8_pherip_clks[] = {
-+ { CLK_PERIPH("10000100.timer", "periph") },
-+ { CLK_PERIPH("10000120.watchdog", "periph") },
-+ { CLK_PERIPH("10000900.i2c", "periph") },
-+ { CLK_PERIPH("10000a00.i2s", "pcmi2s") },
-+ { CLK_PERIPH("10000b00.spi", "bus") },
-+ { CLK_PERIPH("10000b40.spi", "bus") },
-+ { CLK_PERIPH("10000c00.uart0", "periph") },
-+ { CLK_PERIPH("10000d00.uart1", "periph") },
-+ { CLK_PERIPH("10000e00.uart2", "periph") },
-+ { CLK_PERIPH("10300000.wmac", "xtal") }
-+};
-+
-+static int mtmips_register_pherip_clocks(struct device_node *np,
-+ struct clk_hw_onecell_data *clk_data,
-+ struct mtmips_clk_priv *priv)
-+{
-+ struct clk_hw **hws = clk_data->hws;
-+ struct mtmips_clk *sclk;
-+ size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed +
-+ priv->data->num_clk_factor;
-+ int ret, i;
-+
-+ for (i = 0; i < priv->data->num_clk_periph; i++) {
-+ int idx = idx_start + i;
-+
-+ sclk = &priv->data->clk_periph[i];
-+ ret = of_clk_hw_register(np, &sclk->hw);
-+ if (ret) {
-+ pr_err("Couldn't register peripheral clock %d\n", idx);
-+ goto err_clk_unreg;
-+ }
-+
-+ hws[idx] = &sclk->hw;
-+ }
-+
-+ return 0;
-+
-+err_clk_unreg:
-+ while (--i >= 0) {
-+ sclk = &priv->data->clk_periph[i];
-+ clk_hw_unregister(&sclk->hw);
-+ }
-+ return ret;
-+}
-+
-+#define CLK_FIXED(_name, _parent, _rate) \
-+ { \
-+ .name = _name, \
-+ .parent = _parent, \
-+ .rate = _rate \
-+ }
-+
-+static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
-+ CLK_FIXED("xtal", NULL, 40000000)
-+};
-+
-+static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
-+ CLK_FIXED("periph", "xtal", 40000000)
-+};
-+
-+static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
-+ CLK_FIXED("pcmi2s", "xtal", 480000000),
-+ CLK_FIXED("periph", "xtal", 40000000)
-+};
-+
-+static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data,
-+ struct mtmips_clk_priv *priv)
-+{
-+ struct clk_hw **hws = clk_data->hws;
-+ struct mtmips_clk_fixed *sclk;
-+ size_t idx_start = priv->data->num_clk_base;
-+ int ret, i;
-+
-+ for (i = 0; i < priv->data->num_clk_fixed; i++) {
-+ int idx = idx_start + i;
-+
-+ sclk = &priv->data->clk_fixed[i];
-+ sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name,
-+ sclk->parent, 0,
-+ sclk->rate);
-+ if (IS_ERR(sclk->hw)) {
-+ pr_err("Couldn't register fixed clock %d\n", idx);
-+ goto err_clk_unreg;
-+ }
-+
-+ hws[idx] = sclk->hw;
-+ }
-+
-+ return 0;
-+
-+err_clk_unreg:
-+ while (--i >= 0) {
-+ sclk = &priv->data->clk_fixed[i];
-+ clk_hw_unregister_fixed_rate(sclk->hw);
-+ }
-+ return ret;
-+}
-+
-+#define CLK_FACTOR(_name, _parent, _mult, _div) \
-+ { \
-+ .name = _name, \
-+ .parent = _parent, \
-+ .mult = _mult, \
-+ .div = _div, \
-+ .flags = CLK_SET_RATE_PARENT \
-+ }
-+
-+static struct mtmips_clk_factor rt2880_factor_clocks[] = {
-+ CLK_FACTOR("bus", "cpu", 1, 2)
-+};
-+
-+static struct mtmips_clk_factor rt305x_factor_clocks[] = {
-+ CLK_FACTOR("bus", "cpu", 1, 3)
-+};
-+
-+static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
-+ struct mtmips_clk_priv *priv)
-+{
-+ struct clk_hw **hws = clk_data->hws;
-+ struct mtmips_clk_factor *sclk;
-+ size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed;
-+ int ret, i;
-+
-+ for (i = 0; i < priv->data->num_clk_factor; i++) {
-+ int idx = idx_start + i;
-+
-+ sclk = &priv->data->clk_factor[i];
-+ sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name,
-+ sclk->parent, sclk->flags,
-+ sclk->mult, sclk->div);
-+ if (IS_ERR(sclk->hw)) {
-+ pr_err("Couldn't register factor clock %d\n", idx);
-+ goto err_clk_unreg;
-+ }
-+
-+ hws[idx] = sclk->hw;
-+ }
-+
-+ return 0;
-+
-+err_clk_unreg:
-+ while (--i >= 0) {
-+ sclk = &priv->data->clk_factor[i];
-+ clk_hw_unregister_fixed_factor(sclk->hw);
-+ }
-+ return ret;
-+}
-+
-+static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw)
-+{
-+ return container_of(hw, struct mtmips_clk, hw);
-+}
-+
-+static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ u32 val;
-+
-+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val);
-+ if (!(val & RT5350_CLKCFG0_XTAL_SEL))
-+ return 20000000;
-+
-+ return 40000000;
-+}
-+
-+static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw,
-+ unsigned long xtal_clk)
-+{
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ u32 t;
-+
-+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+ t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK;
-+
-+ switch (t) {
-+ case RT5350_SYSCFG0_CPUCLK_360:
-+ return 360000000;
-+ case RT5350_SYSCFG0_CPUCLK_320:
-+ return 320000000;
-+ case RT5350_SYSCFG0_CPUCLK_300:
-+ return 300000000;
-+ default:
-+ BUG();
-+ }
-+}
-+
-+static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ if (parent_rate == 320000000)
-+ return parent_rate / 4;
-+
-+ return parent_rate / 3;
-+}
-+
-+static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw,
-+ unsigned long xtal_clk)
-+{
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ u32 t;
-+
-+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+ t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK;
-+
-+ switch (t) {
-+ case RT3352_SYSCFG0_CPUCLK_LOW:
-+ return 384000000;
-+ case RT3352_SYSCFG0_CPUCLK_HIGH:
-+ return 400000000;
-+ default:
-+ BUG();
-+ }
-+}
-+
-+static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw,
-+ unsigned long xtal_clk)
-+{
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ u32 t;
-+
-+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+ t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK;
-+
-+ switch (t) {
-+ case RT305X_SYSCFG_CPUCLK_LOW:
-+ return 320000000;
-+ case RT305X_SYSCFG_CPUCLK_HIGH:
-+ return 384000000;
-+ default:
-+ BUG();
-+ }
-+}
-+
-+static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw,
-+ unsigned long xtal_clk)
-+{
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ u32 t;
-+
-+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+ t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK;
-+
-+ switch (t) {
-+ case RT3883_SYSCFG0_CPUCLK_250:
-+ return 250000000;
-+ case RT3883_SYSCFG0_CPUCLK_384:
-+ return 384000000;
-+ case RT3883_SYSCFG0_CPUCLK_480:
-+ return 480000000;
-+ case RT3883_SYSCFG0_CPUCLK_500:
-+ return 500000000;
-+ default:
-+ BUG();
-+ }
-+}
-+
-+static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ u32 ddr2;
-+ u32 t;
-+
-+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+ ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
-+
-+ switch (parent_rate) {
-+ case 250000000:
-+ return (ddr2) ? 125000000 : 83000000;
-+ case 384000000:
-+ return (ddr2) ? 128000000 : 96000000;
-+ case 480000000:
-+ return (ddr2) ? 160000000 : 120000000;
-+ case 500000000:
-+ return (ddr2) ? 166000000 : 125000000;
-+ default:
-+ WARN_ON_ONCE(parent_rate == 0);
-+ return parent_rate / 4;
-+ }
-+}
-+
-+static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw,
-+ unsigned long xtal_clk)
-+{
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ u32 t;
-+
-+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+ t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK;
-+
-+ switch (t) {
-+ case RT2880_CONFIG_CPUCLK_250:
-+ return 250000000;
-+ case RT2880_CONFIG_CPUCLK_266:
-+ return 266000000;
-+ case RT2880_CONFIG_CPUCLK_280:
-+ return 280000000;
-+ case RT2880_CONFIG_CPUCLK_300:
-+ return 300000000;
-+ default:
-+ BUG();
-+ }
-+}
-+
-+static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
-+{
-+ u64 t;
-+
-+ t = ref_rate;
-+ t *= mul;
-+ t = div_u64(t, div);
-+
-+ return t;
-+}
-+
-+static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ static const u32 clk_divider[] = { 2, 3, 4, 8 };
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ unsigned long cpu_pll;
-+ u32 t;
-+ u32 mul;
-+ u32 div;
-+
-+ regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t);
-+ if (t & CPLL_CFG0_BYPASS_REF_CLK) {
-+ cpu_pll = parent_rate;
-+ } else if ((t & CPLL_CFG0_SW_CFG) == 0) {
-+ cpu_pll = 600000000;
-+ } else {
-+ mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
-+ CPLL_CFG0_PLL_MULT_RATIO_MASK;
-+ mul += 24;
-+ if (t & CPLL_CFG0_LC_CURFCK)
-+ mul *= 2;
-+
-+ div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
-+ CPLL_CFG0_PLL_DIV_RATIO_MASK;
-+
-+ WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider));
-+
-+ cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]);
-+ }
-+
-+ regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t);
-+ if (t & CPLL_CFG1_CPU_AUX1)
-+ return parent_rate;
-+
-+ if (t & CPLL_CFG1_CPU_AUX0)
-+ return 480000000;
-+
-+ return cpu_pll;
-+}
-+
-+static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ u32 t;
-+ u32 mul;
-+ u32 div;
-+
-+ regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
-+ mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
-+ div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
-+ CPU_SYS_CLKCFG_CPU_FDIV_MASK;
-+
-+ return mt7620_calc_rate(parent_rate, mul, div);
-+}
-+
-+static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ static const u32 ocp_dividers[16] = {
-+ [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
-+ [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
-+ [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
-+ [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
-+ [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
-+ };
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ u32 t;
-+ u32 ocp_ratio;
-+ u32 div;
-+
-+ regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
-+ ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
-+ CPU_SYS_CLKCFG_OCP_RATIO_MASK;
-+
-+ if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers)))
-+ return parent_rate;
-+
-+ div = ocp_dividers[ocp_ratio];
-+
-+ if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
-+ return parent_rate;
-+
-+ return parent_rate / div;
-+}
-+
-+static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ u32 t;
-+
-+ regmap_read(sysc, SYSC_REG_CLKCFG0, &t);
-+ if (t & CLKCFG0_PERI_CLK_SEL)
-+ return parent_rate;
-+
-+ return 40000000;
-+}
-+
-+static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ struct mtmips_clk *clk = to_mtmips_clk(hw);
-+ struct regmap *sysc = clk->priv->sysc;
-+ u32 t;
-+
-+ regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
-+ if (t & MT7620_XTAL_FREQ_SEL)
-+ return 40000000;
-+
-+ return 20000000;
-+}
-+
-+static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw,
-+ unsigned long xtal_clk)
-+{
-+ if (xtal_clk == 40000000)
-+ return 580000000;
-+
-+ return 575000000;
-+}
-+
-+#define CLK_BASE(_name, _parent, _recalc) { \
-+ .init = &(const struct clk_init_data) { \
-+ .name = _name, \
-+ .ops = &(const struct clk_ops) { \
-+ .recalc_rate = _recalc, \
-+ }, \
-+ .parent_data = &(const struct clk_parent_data) { \
-+ .name = _parent, \
-+ .fw_name = _parent \
-+ }, \
-+ .num_parents = _parent ? 1 : 0 \
-+ }, \
-+}
-+
-+static struct mtmips_clk rt2880_clks_base[] = {
-+ { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
-+};
-+
-+static struct mtmips_clk rt305x_clks_base[] = {
-+ { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
-+};
-+
-+static struct mtmips_clk rt3352_clks_base[] = {
-+ { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
-+ { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) }
-+};
-+
-+static struct mtmips_clk rt3883_clks_base[] = {
-+ { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
-+ { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
-+};
-+
-+static struct mtmips_clk rt5350_clks_base[] = {
-+ { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
-+ { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) },
-+ { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) }
-+};
-+
-+static struct mtmips_clk mt7620_clks_base[] = {
-+ { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
-+ { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) },
-+ { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) },
-+ { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) },
-+ { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) }
-+};
-+
-+static struct mtmips_clk mt76x8_clks_base[] = {
-+ { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
-+ { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) }
-+};
-+
-+static int mtmips_register_clocks(struct device_node *np,
-+ struct clk_hw_onecell_data *clk_data,
-+ struct mtmips_clk_priv *priv)
-+{
-+ struct clk_hw **hws = clk_data->hws;
-+ struct mtmips_clk *sclk;
-+ int ret, i;
-+
-+ for (i = 0; i < priv->data->num_clk_base; i++) {
-+ sclk = &priv->data->clk_base[i];
-+ sclk->priv = priv;
-+ ret = of_clk_hw_register(np, &sclk->hw);
-+ if (ret) {
-+ pr_err("Couldn't register top clock %i\n", i);
-+ goto err_clk_unreg;
-+ }
-+
-+ hws[i] = &sclk->hw;
-+ }
-+
-+ return 0;
-+
-+err_clk_unreg:
-+ while (--i >= 0) {
-+ sclk = &priv->data->clk_base[i];
-+ clk_hw_unregister(&sclk->hw);
-+ }
-+ return ret;
-+}
-+
-+static const struct mtmips_clk_data rt2880_clk_data = {
-+ .clk_base = rt2880_clks_base,
-+ .num_clk_base = ARRAY_SIZE(rt2880_clks_base),
-+ .clk_fixed = rt305x_fixed_clocks,
-+ .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
-+ .clk_factor = rt2880_factor_clocks,
-+ .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),
-+ .clk_periph = rt2880_pherip_clks,
-+ .num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data rt305x_clk_data = {
-+ .clk_base = rt305x_clks_base,
-+ .num_clk_base = ARRAY_SIZE(rt305x_clks_base),
-+ .clk_fixed = rt305x_fixed_clocks,
-+ .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
-+ .clk_factor = rt305x_factor_clocks,
-+ .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
-+ .clk_periph = rt305x_pherip_clks,
-+ .num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data rt3352_clk_data = {
-+ .clk_base = rt3352_clks_base,
-+ .num_clk_base = ARRAY_SIZE(rt3352_clks_base),
-+ .clk_fixed = rt3352_fixed_clocks,
-+ .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
-+ .clk_factor = rt305x_factor_clocks,
-+ .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
-+ .clk_periph = rt5350_pherip_clks,
-+ .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data rt3883_clk_data = {
-+ .clk_base = rt3883_clks_base,
-+ .num_clk_base = ARRAY_SIZE(rt3883_clks_base),
-+ .clk_fixed = rt305x_fixed_clocks,
-+ .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
-+ .clk_factor = NULL,
-+ .num_clk_factor = 0,
-+ .clk_periph = rt5350_pherip_clks,
-+ .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data rt5350_clk_data = {
-+ .clk_base = rt5350_clks_base,
-+ .num_clk_base = ARRAY_SIZE(rt5350_clks_base),
-+ .clk_fixed = rt3352_fixed_clocks,
-+ .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
-+ .clk_factor = NULL,
-+ .num_clk_factor = 0,
-+ .clk_periph = rt5350_pherip_clks,
-+ .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data mt7620_clk_data = {
-+ .clk_base = mt7620_clks_base,
-+ .num_clk_base = ARRAY_SIZE(mt7620_clks_base),
-+ .clk_fixed = NULL,
-+ .num_clk_fixed = 0,
-+ .clk_factor = NULL,
-+ .num_clk_factor = 0,
-+ .clk_periph = mt7620_pherip_clks,
-+ .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
-+};
-+
-+static const struct mtmips_clk_data mt76x8_clk_data = {
-+ .clk_base = mt76x8_clks_base,
-+ .num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
-+ .clk_fixed = mt76x8_fixed_clocks,
-+ .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
-+ .clk_factor = rt305x_factor_clocks,
-+ .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
-+ .clk_periph = mt76x8_pherip_clks,
-+ .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
-+};
-+
-+static const struct of_device_id mtmips_of_match[] = {
-+ {
-+ .compatible = "ralink,rt2880-sysc",
-+ .data = &rt2880_clk_data,
-+ },
-+ {
-+ .compatible = "ralink,rt3050-sysc",
-+ .data = &rt305x_clk_data,
-+ },
-+ {
-+ .compatible = "ralink,rt3052-sysc",
-+ .data = &rt305x_clk_data,
-+ },
-+ {
-+ .compatible = "ralink,rt3352-sysc",
-+ .data = &rt3352_clk_data,
-+ },
-+ {
-+ .compatible = "ralink,rt3883-sysc",
-+ .data = &rt3883_clk_data,
-+ },
-+ {
-+ .compatible = "ralink,rt5350-sysc",
-+ .data = &rt5350_clk_data,
-+ },
-+ {
-+ .compatible = "ralink,mt7620-sysc",
-+ .data = &mt7620_clk_data,
-+ },
-+ {
-+ .compatible = "ralink,mt7628-sysc",
-+ .data = &mt76x8_clk_data,
-+ },
-+ {
-+ .compatible = "ralink,mt7688-sysc",
-+ .data = &mt76x8_clk_data,
-+ },
-+ {}
-+};
-+
-+static void __init mtmips_clk_regs_init(struct device_node *node,
-+ struct mtmips_clk_priv *priv)
-+{
-+ u32 t;
-+
-+ if (!of_device_is_compatible(node, "ralink,mt7620-sysc"))
-+ return;
-+
-+ /*
-+ * When the CPU goes into sleep mode, the BUS
-+ * clock will be too low for USB to function properly.
-+ * Adjust the busses fractional divider to fix this
-+ */
-+ regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
-+ t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
-+ t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
-+ regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t);
-+}
-+
-+static void __init mtmips_clk_init(struct device_node *node)
-+{
-+ const struct of_device_id *match;
-+ const struct mtmips_clk_data *data;
-+ struct mtmips_clk_priv *priv;
-+ struct clk_hw_onecell_data *clk_data;
-+ int ret, i, count;
-+
-+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return;
-+
-+ priv->sysc = syscon_node_to_regmap(node);
-+ if (IS_ERR(priv->sysc)) {
-+ pr_err("Could not get sysc syscon regmap\n");
-+ goto free_clk_priv;
-+ }
-+
-+ mtmips_clk_regs_init(node, priv);
-+
-+ match = of_match_node(mtmips_of_match, node);
-+ if (WARN_ON(!match))
-+ return;
-+
-+ data = match->data;
-+ priv->data = data;
-+ count = priv->data->num_clk_base + priv->data->num_clk_fixed +
-+ priv->data->num_clk_factor + priv->data->num_clk_periph;
-+ clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL);
-+ if (!clk_data)
-+ goto free_clk_priv;
-+
-+ ret = mtmips_register_clocks(node, clk_data, priv);
-+ if (ret) {
-+ pr_err("Couldn't register top clocks\n");
-+ goto free_clk_data;
-+ }
-+
-+ ret = mtmips_register_fixed_clocks(clk_data, priv);
-+ if (ret) {
-+ pr_err("Couldn't register fixed clocks\n");
-+ goto unreg_clk_top;
-+ }
-+
-+ ret = mtmips_register_factor_clocks(clk_data, priv);
-+ if (ret) {
-+ pr_err("Couldn't register factor clocks\n");
-+ goto unreg_clk_fixed;
-+ }
-+
-+ ret = mtmips_register_pherip_clocks(node, clk_data, priv);
-+ if (ret) {
-+ pr_err("Couldn't register peripheral clocks\n");
-+ goto unreg_clk_factor;
-+ }
-+
-+ clk_data->num = count;
-+
-+ ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
-+ if (ret) {
-+ pr_err("Couldn't add clk hw provider\n");
-+ goto unreg_clk_periph;
-+ }
-+
-+ return;
-+
-+unreg_clk_periph:
-+ for (i = 0; i < priv->data->num_clk_periph; i++) {
-+ struct mtmips_clk *sclk = &priv->data->clk_periph[i];
-+
-+ clk_hw_unregister(&sclk->hw);
-+ }
-+
-+unreg_clk_factor:
-+ for (i = 0; i < priv->data->num_clk_factor; i++) {
-+ struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i];
-+
-+ clk_hw_unregister_fixed_factor(sclk->hw);
-+ }
-+
-+unreg_clk_fixed:
-+ for (i = 0; i < priv->data->num_clk_fixed; i++) {
-+ struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i];
-+
-+ clk_hw_unregister_fixed_rate(sclk->hw);
-+ }
-+
-+unreg_clk_top:
-+ for (i = 0; i < priv->data->num_clk_base; i++) {
-+ struct mtmips_clk *sclk = &priv->data->clk_base[i];
-+
-+ clk_hw_unregister(&sclk->hw);
-+ }
-+
-+free_clk_data:
-+ kfree(clk_data);
-+
-+free_clk_priv:
-+ kfree(priv);
-+}
-+CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init);
-+CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init);
-+
-+struct mtmips_rst {
-+ struct reset_controller_dev rcdev;
-+ struct regmap *sysc;
-+};
-+
-+static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev)
-+{
-+ return container_of(dev, struct mtmips_rst, rcdev);
-+}
-+
-+static int mtmips_assert_device(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct mtmips_rst *data = to_mtmips_rst(rcdev);
-+ struct regmap *sysc = data->sysc;
-+
-+ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
-+}
-+
-+static int mtmips_deassert_device(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct mtmips_rst *data = to_mtmips_rst(rcdev);
-+ struct regmap *sysc = data->sysc;
-+
-+ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
-+}
-+
-+static int mtmips_reset_device(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ int ret;
-+
-+ ret = mtmips_assert_device(rcdev, id);
-+ if (ret < 0)
-+ return ret;
-+
-+ return mtmips_deassert_device(rcdev, id);
-+}
-+
-+static int mtmips_rst_xlate(struct reset_controller_dev *rcdev,
-+ const struct of_phandle_args *reset_spec)
-+{
-+ unsigned long id = reset_spec->args[0];
-+
-+ if (id == 0 || id >= rcdev->nr_resets)
-+ return -EINVAL;
-+
-+ return id;
-+}
-+
-+static const struct reset_control_ops reset_ops = {
-+ .reset = mtmips_reset_device,
-+ .assert = mtmips_assert_device,
-+ .deassert = mtmips_deassert_device
-+};
-+
-+static int mtmips_reset_init(struct device *dev, struct regmap *sysc)
-+{
-+ struct mtmips_rst *rst_data;
-+
-+ rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
-+ if (!rst_data)
-+ return -ENOMEM;
-+
-+ rst_data->sysc = sysc;
-+ rst_data->rcdev.ops = &reset_ops;
-+ rst_data->rcdev.owner = THIS_MODULE;
-+ rst_data->rcdev.nr_resets = 32;
-+ rst_data->rcdev.of_reset_n_cells = 1;
-+ rst_data->rcdev.of_xlate = mtmips_rst_xlate;
-+ rst_data->rcdev.of_node = dev_of_node(dev);
-+
-+ return devm_reset_controller_register(dev, &rst_data->rcdev);
-+}
-+
-+static int mtmips_clk_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct device *dev = &pdev->dev;
-+ struct mtmips_clk_priv *priv;
-+ int ret;
-+
-+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->sysc = syscon_node_to_regmap(np);
-+ if (IS_ERR(priv->sysc))
-+ return dev_err_probe(dev, PTR_ERR(priv->sysc),
-+ "Could not get sysc syscon regmap\n");
-+
-+ ret = mtmips_reset_init(dev, priv->sysc);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Could not init reset controller\n");
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mtmips_clk_of_match[] = {
-+ { .compatible = "ralink,rt2880-reset" },
-+ { .compatible = "ralink,rt2880-sysc" },
-+ { .compatible = "ralink,rt3050-sysc" },
-+ { .compatible = "ralink,rt3052-sysc" },
-+ { .compatible = "ralink,rt3352-sysc" },
-+ { .compatible = "ralink,rt3883-sysc" },
-+ { .compatible = "ralink,rt5350-sysc" },
-+ { .compatible = "ralink,mt7620-sysc" },
-+ { .compatible = "ralink,mt7628-sysc" },
-+ { .compatible = "ralink,mt7688-sysc" },
-+ {}
-+};
-+
-+static struct platform_driver mtmips_clk_driver = {
-+ .probe = mtmips_clk_probe,
-+ .driver = {
-+ .name = "mtmips-clk",
-+ .of_match_table = mtmips_clk_of_match,
-+ },
-+};
-+
-+static int __init mtmips_clk_reset_init(void)
-+{
-+ return platform_driver_register(&mtmips_clk_driver);
-+}
-+arch_initcall(mtmips_clk_reset_init);
+++ /dev/null
-From ffcdf47379eae86dc8f8f02c62994dacf2c9038e Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:35 +0200
-Subject: [PATCH 3/9] mips: ralink: rt288x: remove clock related code
-
-A properly clock driver for ralink SoCs has been added. Hence there is no
-need to have clock related code in 'arch/mips/ralink' folder anymore.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mach-ralink/rt288x.h | 10 ----------
- arch/mips/ralink/rt288x.c | 31 ------------------------------
- 2 files changed, 41 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/rt288x.h
-+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
-@@ -17,7 +17,6 @@
- #define SYSC_REG_CHIP_NAME1 0x04
- #define SYSC_REG_CHIP_ID 0x0c
- #define SYSC_REG_SYSTEM_CONFIG 0x10
--#define SYSC_REG_CLKCFG 0x30
-
- #define RT2880_CHIP_NAME0 0x38325452
- #define RT2880_CHIP_NAME1 0x20203038
-@@ -26,15 +25,6 @@
- #define CHIP_ID_ID_SHIFT 8
- #define CHIP_ID_REV_MASK 0xff
-
--#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
--#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
--#define SYSTEM_CONFIG_CPUCLK_250 0x0
--#define SYSTEM_CONFIG_CPUCLK_266 0x1
--#define SYSTEM_CONFIG_CPUCLK_280 0x2
--#define SYSTEM_CONFIG_CPUCLK_300 0x3
--
--#define CLKCFG_SRAM_CS_N_WDT BIT(9)
--
- #define RT2880_SDRAM_BASE 0x08000000
- #define RT2880_MEM_SIZE_MIN 2
- #define RT2880_MEM_SIZE_MAX 128
---- a/arch/mips/ralink/rt288x.c
-+++ b/arch/mips/ralink/rt288x.c
-@@ -17,37 +17,6 @@
-
- #include "common.h"
-
--void __init ralink_clk_init(void)
--{
-- unsigned long cpu_rate, wmac_rate = 40000000;
-- u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
-- t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
--
-- switch (t) {
-- case SYSTEM_CONFIG_CPUCLK_250:
-- cpu_rate = 250000000;
-- break;
-- case SYSTEM_CONFIG_CPUCLK_266:
-- cpu_rate = 266666667;
-- break;
-- case SYSTEM_CONFIG_CPUCLK_280:
-- cpu_rate = 280000000;
-- break;
-- case SYSTEM_CONFIG_CPUCLK_300:
-- cpu_rate = 300000000;
-- break;
-- }
--
-- ralink_clk_add("cpu", cpu_rate);
-- ralink_clk_add("300100.timer", cpu_rate / 2);
-- ralink_clk_add("300120.watchdog", cpu_rate / 2);
-- ralink_clk_add("300500.uart", cpu_rate / 2);
-- ralink_clk_add("300900.i2c", cpu_rate / 2);
-- ralink_clk_add("300c00.uartlite", cpu_rate / 2);
-- ralink_clk_add("400000.ethernet", cpu_rate / 2);
-- ralink_clk_add("480000.wmac", wmac_rate);
--}
--
- void __init ralink_of_remap(void)
- {
- rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
+++ /dev/null
-From daf73c70f69386fb15960526772ef584a4efcaf2 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:36 +0200
-Subject: [PATCH 4/9] mips: ralink: rt305x: remove clock related code
-
-A properly clock driver for ralink SoCs has been added. Hence there is no
-need to have clock related code in 'arch/mips/ralink' folder anymore.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mach-ralink/rt305x.h | 21 --------
- arch/mips/ralink/rt305x.c | 78 ------------------------------
- 2 files changed, 99 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/rt305x.h
-+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
-@@ -66,26 +66,9 @@ static inline int soc_is_rt5350(void)
- #define CHIP_ID_ID_SHIFT 8
- #define CHIP_ID_REV_MASK 0xff
-
--#define RT305X_SYSCFG_CPUCLK_SHIFT 18
--#define RT305X_SYSCFG_CPUCLK_MASK 0x1
--#define RT305X_SYSCFG_CPUCLK_LOW 0x0
--#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
--
- #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
--#define RT305X_SYSCFG_CPUCLK_MASK 0x1
- #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
-
--#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
--#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
--#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
--#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
--
--#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
--#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
--#define RT5350_SYSCFG0_CPUCLK_360 0x0
--#define RT5350_SYSCFG0_CPUCLK_320 0x2
--#define RT5350_SYSCFG0_CPUCLK_300 0x3
--
- #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
- #define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
- #define RT5350_SYSCFG0_DRAM_SIZE_2M 0
-@@ -116,13 +99,9 @@ static inline int soc_is_rt5350(void)
-
- #define RT3352_SYSC_REG_SYSCFG0 0x010
- #define RT3352_SYSC_REG_SYSCFG1 0x014
--#define RT3352_SYSC_REG_CLKCFG1 0x030
- #define RT3352_SYSC_REG_RSTCTRL 0x034
- #define RT3352_SYSC_REG_USB_PS 0x05c
-
--#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
--#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
--#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
- #define RT3352_RSTCTRL_UHST BIT(22)
- #define RT3352_RSTCTRL_UDEV BIT(25)
- #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -53,84 +53,6 @@ static unsigned long rt5350_get_mem_size
- return ret;
- }
-
--void __init ralink_clk_init(void)
--{
-- unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
-- unsigned long wmac_rate = 40000000;
--
-- u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
--
-- if (soc_is_rt305x() || soc_is_rt3350()) {
-- t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
-- RT305X_SYSCFG_CPUCLK_MASK;
-- switch (t) {
-- case RT305X_SYSCFG_CPUCLK_LOW:
-- cpu_rate = 320000000;
-- break;
-- case RT305X_SYSCFG_CPUCLK_HIGH:
-- cpu_rate = 384000000;
-- break;
-- }
-- sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
-- } else if (soc_is_rt3352()) {
-- t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
-- RT3352_SYSCFG0_CPUCLK_MASK;
-- switch (t) {
-- case RT3352_SYSCFG0_CPUCLK_LOW:
-- cpu_rate = 384000000;
-- break;
-- case RT3352_SYSCFG0_CPUCLK_HIGH:
-- cpu_rate = 400000000;
-- break;
-- }
-- sys_rate = wdt_rate = cpu_rate / 3;
-- uart_rate = 40000000;
-- } else if (soc_is_rt5350()) {
-- t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
-- RT5350_SYSCFG0_CPUCLK_MASK;
-- switch (t) {
-- case RT5350_SYSCFG0_CPUCLK_360:
-- cpu_rate = 360000000;
-- sys_rate = cpu_rate / 3;
-- break;
-- case RT5350_SYSCFG0_CPUCLK_320:
-- cpu_rate = 320000000;
-- sys_rate = cpu_rate / 4;
-- break;
-- case RT5350_SYSCFG0_CPUCLK_300:
-- cpu_rate = 300000000;
-- sys_rate = cpu_rate / 3;
-- break;
-- default:
-- BUG();
-- }
-- uart_rate = 40000000;
-- wdt_rate = sys_rate;
-- } else {
-- BUG();
-- }
--
-- if (soc_is_rt3352() || soc_is_rt5350()) {
-- u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
--
-- if (!(val & RT3352_CLKCFG0_XTAL_SEL))
-- wmac_rate = 20000000;
-- }
--
-- ralink_clk_add("cpu", cpu_rate);
-- ralink_clk_add("sys", sys_rate);
-- ralink_clk_add("10000900.i2c", uart_rate);
-- ralink_clk_add("10000a00.i2s", uart_rate);
-- ralink_clk_add("10000b00.spi", sys_rate);
-- ralink_clk_add("10000b40.spi", sys_rate);
-- ralink_clk_add("10000100.timer", wdt_rate);
-- ralink_clk_add("10000120.watchdog", wdt_rate);
-- ralink_clk_add("10000500.uart", uart_rate);
-- ralink_clk_add("10000c00.uartlite", uart_rate);
-- ralink_clk_add("10100000.ethernet", sys_rate);
-- ralink_clk_add("10180000.wmac", wmac_rate);
--}
--
- void __init ralink_of_remap(void)
- {
- rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
+++ /dev/null
-From 7cd1bb48885449a9323c7ff0f10012925e93b4e1 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:37 +0200
-Subject: [PATCH 5/9] mips: ralink: rt3883: remove clock related code
-
-A properly clock driver for ralink SoCs has been added. Hence there is no
-need to have clock related code in 'arch/mips/ralink' folder anymore.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mach-ralink/rt3883.h | 8 ------
- arch/mips/ralink/rt3883.c | 44 ------------------------------
- 2 files changed, 52 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/rt3883.h
-+++ b/arch/mips/include/asm/mach-ralink/rt3883.h
-@@ -90,14 +90,6 @@
- #define RT3883_REVID_VER_ID_SHIFT 8
- #define RT3883_REVID_ECO_ID_MASK 0x0f
-
--#define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
--#define RT3883_SYSCFG0_CPUCLK_SHIFT 8
--#define RT3883_SYSCFG0_CPUCLK_MASK 0x3
--#define RT3883_SYSCFG0_CPUCLK_250 0x0
--#define RT3883_SYSCFG0_CPUCLK_384 0x1
--#define RT3883_SYSCFG0_CPUCLK_480 0x2
--#define RT3883_SYSCFG0_CPUCLK_500 0x3
--
- #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
- #define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
- #define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -17,50 +17,6 @@
-
- #include "common.h"
-
--void __init ralink_clk_init(void)
--{
-- unsigned long cpu_rate, sys_rate;
-- u32 syscfg0;
-- u32 clksel;
-- u32 ddr2;
--
-- syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
-- clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
-- RT3883_SYSCFG0_CPUCLK_MASK);
-- ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
--
-- switch (clksel) {
-- case RT3883_SYSCFG0_CPUCLK_250:
-- cpu_rate = 250000000;
-- sys_rate = (ddr2) ? 125000000 : 83000000;
-- break;
-- case RT3883_SYSCFG0_CPUCLK_384:
-- cpu_rate = 384000000;
-- sys_rate = (ddr2) ? 128000000 : 96000000;
-- break;
-- case RT3883_SYSCFG0_CPUCLK_480:
-- cpu_rate = 480000000;
-- sys_rate = (ddr2) ? 160000000 : 120000000;
-- break;
-- case RT3883_SYSCFG0_CPUCLK_500:
-- cpu_rate = 500000000;
-- sys_rate = (ddr2) ? 166000000 : 125000000;
-- break;
-- }
--
-- ralink_clk_add("cpu", cpu_rate);
-- ralink_clk_add("10000100.timer", sys_rate);
-- ralink_clk_add("10000120.watchdog", sys_rate);
-- ralink_clk_add("10000500.uart", 40000000);
-- ralink_clk_add("10000900.i2c", 40000000);
-- ralink_clk_add("10000a00.i2s", 40000000);
-- ralink_clk_add("10000b00.spi", sys_rate);
-- ralink_clk_add("10000b40.spi", sys_rate);
-- ralink_clk_add("10000c00.uartlite", 40000000);
-- ralink_clk_add("10100000.ethernet", sys_rate);
-- ralink_clk_add("10180000.wmac", 40000000);
--}
--
- void __init ralink_of_remap(void)
- {
- rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
+++ /dev/null
-From 04b153abdfcbaba70ceef5a846067d4447fd0078 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:38 +0200
-Subject: [PATCH 6/9] mips: ralink: mt7620: remove clock related code
-
-A proper clock driver for ralink SoCs has been added. Hence there is no
-need to have clock related code in 'arch/mips/ralink' folder anymore.
-Since this is the last clock related code removal, remove also remaining
-prototypes in 'common.h' header file.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mach-ralink/mt7620.h | 35 -----
- arch/mips/ralink/common.h | 3 -
- arch/mips/ralink/mt7620.c | 226 -----------------------------
- 3 files changed, 264 deletions(-)
-
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -19,52 +19,17 @@
- #define SYSC_REG_CHIP_REV 0x0c
- #define SYSC_REG_SYSTEM_CONFIG0 0x10
- #define SYSC_REG_SYSTEM_CONFIG1 0x14
--#define SYSC_REG_CLKCFG0 0x2c
--#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
--#define SYSC_REG_CPLL_CONFIG0 0x54
--#define SYSC_REG_CPLL_CONFIG1 0x58
-
- #define MT7620_CHIP_NAME0 0x3637544d
- #define MT7620_CHIP_NAME1 0x20203032
- #define MT7628_CHIP_NAME1 0x20203832
-
--#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
--
- #define CHIP_REV_PKG_MASK 0x1
- #define CHIP_REV_PKG_SHIFT 16
- #define CHIP_REV_VER_MASK 0xf
- #define CHIP_REV_VER_SHIFT 8
- #define CHIP_REV_ECO_MASK 0xf
-
--#define CLKCFG0_PERI_CLK_SEL BIT(4)
--
--#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
--#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
--#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
--#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
--#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
--#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
--#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
--#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
--#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
--#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
--#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
--#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
--#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
--#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
--#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
--
--#define CPLL_CFG0_SW_CFG BIT(31)
--#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
--#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
--#define CPLL_CFG0_LC_CURFCK BIT(15)
--#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
--#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
--#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
--
--#define CPLL_CFG1_CPU_AUX1 BIT(25)
--#define CPLL_CFG1_CPU_AUX0 BIT(24)
--
- #define SYSCFG0_DRAM_TYPE_MASK 0x3
- #define SYSCFG0_DRAM_TYPE_SHIFT 4
- #define SYSCFG0_DRAM_TYPE_SDRAM 0
---- a/arch/mips/ralink/common.h
-+++ b/arch/mips/ralink/common.h
-@@ -23,9 +23,6 @@ extern struct ralink_soc_info soc_info;
-
- extern void ralink_of_remap(void);
-
--extern void ralink_clk_init(void);
--extern void ralink_clk_add(const char *dev, unsigned long rate);
--
- extern void ralink_rst_init(void);
-
- extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -34,12 +34,6 @@
- #define PMU1_CFG 0x8C
- #define DIG_SW_SEL BIT(25)
-
--/* clock scaling */
--#define CLKCFG_FDIV_MASK 0x1f00
--#define CLKCFG_FDIV_USB_VAL 0x0300
--#define CLKCFG_FFRAC_MASK 0x001f
--#define CLKCFG_FFRAC_USB_VAL 0x0003
--
- /* EFUSE bits */
- #define EFUSE_MT7688 0x100000
-
-@@ -49,226 +43,6 @@
- /* does the board have sdram or ddram */
- static int dram_type;
-
--static __init u32
--mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
--{
-- u64 t;
--
-- t = ref_rate;
-- t *= mul;
-- do_div(t, div);
--
-- return t;
--}
--
--#define MHZ(x) ((x) * 1000 * 1000)
--
--static __init unsigned long
--mt7620_get_xtal_rate(void)
--{
-- u32 reg;
--
-- reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
-- if (reg & SYSCFG0_XTAL_FREQ_SEL)
-- return MHZ(40);
--
-- return MHZ(20);
--}
--
--static __init unsigned long
--mt7620_get_periph_rate(unsigned long xtal_rate)
--{
-- u32 reg;
--
-- reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
-- if (reg & CLKCFG0_PERI_CLK_SEL)
-- return xtal_rate;
--
-- return MHZ(40);
--}
--
--static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
--
--static __init unsigned long
--mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
--{
-- u32 reg;
-- u32 mul;
-- u32 div;
--
-- reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
-- if (reg & CPLL_CFG0_BYPASS_REF_CLK)
-- return xtal_rate;
--
-- if ((reg & CPLL_CFG0_SW_CFG) == 0)
-- return MHZ(600);
--
-- mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
-- CPLL_CFG0_PLL_MULT_RATIO_MASK;
-- mul += 24;
-- if (reg & CPLL_CFG0_LC_CURFCK)
-- mul *= 2;
--
-- div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
-- CPLL_CFG0_PLL_DIV_RATIO_MASK;
--
-- WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
--
-- return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
--}
--
--static __init unsigned long
--mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
--{
-- u32 reg;
--
-- reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
-- if (reg & CPLL_CFG1_CPU_AUX1)
-- return xtal_rate;
--
-- if (reg & CPLL_CFG1_CPU_AUX0)
-- return MHZ(480);
--
-- return cpu_pll_rate;
--}
--
--static __init unsigned long
--mt7620_get_cpu_rate(unsigned long pll_rate)
--{
-- u32 reg;
-- u32 mul;
-- u32 div;
--
-- reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
--
-- mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
-- div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
-- CPU_SYS_CLKCFG_CPU_FDIV_MASK;
--
-- return mt7620_calc_rate(pll_rate, mul, div);
--}
--
--static const u32 mt7620_ocp_dividers[16] __initconst = {
-- [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
-- [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
-- [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
-- [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
-- [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
--};
--
--static __init unsigned long
--mt7620_get_dram_rate(unsigned long pll_rate)
--{
-- if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
-- return pll_rate / 4;
--
-- return pll_rate / 3;
--}
--
--static __init unsigned long
--mt7620_get_sys_rate(unsigned long cpu_rate)
--{
-- u32 reg;
-- u32 ocp_ratio;
-- u32 div;
--
-- reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
--
-- ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
-- CPU_SYS_CLKCFG_OCP_RATIO_MASK;
--
-- if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
-- return cpu_rate;
--
-- div = mt7620_ocp_dividers[ocp_ratio];
-- if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
-- return cpu_rate;
--
-- return cpu_rate / div;
--}
--
--void __init ralink_clk_init(void)
--{
-- unsigned long xtal_rate;
-- unsigned long cpu_pll_rate;
-- unsigned long pll_rate;
-- unsigned long cpu_rate;
-- unsigned long sys_rate;
-- unsigned long dram_rate;
-- unsigned long periph_rate;
-- unsigned long pcmi2s_rate;
--
-- xtal_rate = mt7620_get_xtal_rate();
--
--#define RFMT(label) label ":%lu.%03luMHz "
--#define RINT(x) ((x) / 1000000)
--#define RFRAC(x) (((x) / 1000) % 1000)
--
-- if (is_mt76x8()) {
-- if (xtal_rate == MHZ(40))
-- cpu_rate = MHZ(580);
-- else
-- cpu_rate = MHZ(575);
-- dram_rate = sys_rate = cpu_rate / 3;
-- periph_rate = MHZ(40);
-- pcmi2s_rate = MHZ(480);
--
-- ralink_clk_add("10000d00.uartlite", periph_rate);
-- ralink_clk_add("10000e00.uartlite", periph_rate);
-- } else {
-- cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
-- pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
--
-- cpu_rate = mt7620_get_cpu_rate(pll_rate);
-- dram_rate = mt7620_get_dram_rate(pll_rate);
-- sys_rate = mt7620_get_sys_rate(cpu_rate);
-- periph_rate = mt7620_get_periph_rate(xtal_rate);
-- pcmi2s_rate = periph_rate;
--
-- pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
-- RINT(xtal_rate), RFRAC(xtal_rate),
-- RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
-- RINT(pll_rate), RFRAC(pll_rate));
--
-- ralink_clk_add("10000500.uart", periph_rate);
-- }
--
-- pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
-- RINT(cpu_rate), RFRAC(cpu_rate),
-- RINT(dram_rate), RFRAC(dram_rate),
-- RINT(sys_rate), RFRAC(sys_rate),
-- RINT(periph_rate), RFRAC(periph_rate));
--#undef RFRAC
--#undef RINT
--#undef RFMT
--
-- ralink_clk_add("cpu", cpu_rate);
-- ralink_clk_add("10000100.timer", periph_rate);
-- ralink_clk_add("10000120.watchdog", periph_rate);
-- ralink_clk_add("10000900.i2c", periph_rate);
-- ralink_clk_add("10000a00.i2s", pcmi2s_rate);
-- ralink_clk_add("10000b00.spi", sys_rate);
-- ralink_clk_add("10000b40.spi", sys_rate);
-- ralink_clk_add("10000c00.uartlite", periph_rate);
-- ralink_clk_add("10000d00.uart1", periph_rate);
-- ralink_clk_add("10000e00.uart2", periph_rate);
-- ralink_clk_add("10180000.wmac", xtal_rate);
--
-- if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
-- /*
-- * When the CPU goes into sleep mode, the BUS clock will be
-- * too low for USB to function properly. Adjust the busses
-- * fractional divider to fix this
-- */
-- u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
--
-- val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
-- val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
--
-- rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
-- }
--}
--
- void __init ralink_of_remap(void)
- {
- rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
+++ /dev/null
-From 201ddc05777cd8e084b508bcdda22214bfe2895e Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:39 +0200
-Subject: [PATCH 7/9] mips: ralink: remove reset related code
-
-A proper clock driver for ralink SoCs has been added. This driver is also
-a reset provider for the SoC. Hence there is no need to have reset related
-code in 'arch/mips/ralink' folder anymore. The only code that remains is
-the one related with mips_reboot_setup where a PCI reset is performed.
-We maintain this because I cannot test old ralink board with PCI to be
-sure all works if we remove also this code.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/ralink/common.h | 2 --
- arch/mips/ralink/of.c | 4 ----
- arch/mips/ralink/reset.c | 61 -----------------------------------------------
- 3 files changed, 67 deletions(-)
-
---- a/arch/mips/ralink/common.h
-+++ b/arch/mips/ralink/common.h
-@@ -23,8 +23,6 @@ extern struct ralink_soc_info soc_info;
-
- extern void ralink_of_remap(void);
-
--extern void ralink_rst_init(void);
--
- extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
-
- __iomem void *plat_of_remap_node(const char *node);
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -81,10 +81,6 @@ static int __init plat_of_setup(void)
- {
- __dt_register_buses(soc_info.compatible, "palmbus");
-
-- /* make sure that the reset controller is setup early */
-- if (ralink_soc != MT762X_SOC_MT7621AT)
-- ralink_rst_init();
--
- return 0;
- }
-
---- a/arch/mips/ralink/reset.c
-+++ b/arch/mips/ralink/reset.c
-@@ -10,7 +10,6 @@
- #include <linux/io.h>
- #include <linux/of.h>
- #include <linux/delay.h>
--#include <linux/reset-controller.h>
-
- #include <asm/reboot.h>
-
-@@ -22,66 +21,6 @@
- #define RSTCTL_RESET_PCI BIT(26)
- #define RSTCTL_RESET_SYSTEM BIT(0)
-
--static int ralink_assert_device(struct reset_controller_dev *rcdev,
-- unsigned long id)
--{
-- u32 val;
--
-- if (id == 0)
-- return -1;
--
-- val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-- val |= BIT(id);
-- rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
--
-- return 0;
--}
--
--static int ralink_deassert_device(struct reset_controller_dev *rcdev,
-- unsigned long id)
--{
-- u32 val;
--
-- if (id == 0)
-- return -1;
--
-- val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-- val &= ~BIT(id);
-- rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
--
-- return 0;
--}
--
--static int ralink_reset_device(struct reset_controller_dev *rcdev,
-- unsigned long id)
--{
-- ralink_assert_device(rcdev, id);
-- return ralink_deassert_device(rcdev, id);
--}
--
--static const struct reset_control_ops reset_ops = {
-- .reset = ralink_reset_device,
-- .assert = ralink_assert_device,
-- .deassert = ralink_deassert_device,
--};
--
--static struct reset_controller_dev reset_dev = {
-- .ops = &reset_ops,
-- .owner = THIS_MODULE,
-- .nr_resets = 32,
-- .of_reset_n_cells = 1,
--};
--
--void ralink_rst_init(void)
--{
-- reset_dev.of_node = of_find_compatible_node(NULL, NULL,
-- "ralink,rt2880-reset");
-- if (!reset_dev.of_node)
-- pr_err("Failed to find reset controller node");
-- else
-- reset_controller_register(&reset_dev);
--}
--
- static void ralink_restart(char *command)
- {
- if (IS_ENABLED(CONFIG_PCI)) {
+++ /dev/null
-From ad38c17b0c26ae2108b50ac1eb0281a2e1ce08e9 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:40 +0200
-Subject: [PATCH 8/9] mips: ralink: get cpu rate from new driver code
-
-At very early stage on boot, there is a need to set 'mips_hpt_frequency'.
-This timer frequency is a half of the CPU frequency. To get clocks properly
-set we need to call to 'of_clk_init()' and properly get cpu clock frequency
-afterwards. Depending on the SoC, CPU clock index and compatible differs, so
-use them to get the proper clock frm the clock provider. Hence, adapt code
-to be aligned with new clock driver.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/ralink/clk.c | 61 ++++++++++++++++++++++++++++++++++++++++++--------
- 1 file changed, 52 insertions(+), 9 deletions(-)
-
---- a/arch/mips/ralink/clk.c
-+++ b/arch/mips/ralink/clk.c
-@@ -11,29 +11,72 @@
- #include <linux/clkdev.h>
- #include <linux/clk.h>
- #include <linux/clk-provider.h>
-+#include <asm/mach-ralink/ralink_regs.h>
-
- #include <asm/time.h>
-
- #include "common.h"
-
--void ralink_clk_add(const char *dev, unsigned long rate)
-+static const char *clk_cpu(int *idx)
- {
-- struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate);
--
-- if (!clk)
-- panic("failed to add clock");
--
-- clkdev_create(clk, NULL, "%s", dev);
-+ switch (ralink_soc) {
-+ case RT2880_SOC:
-+ *idx = 0;
-+ return "ralink,rt2880-sysc";
-+ case RT3883_SOC:
-+ *idx = 0;
-+ return "ralink,rt3883-sysc";
-+ case RT305X_SOC_RT3050:
-+ *idx = 0;
-+ return "ralink,rt3050-sysc";
-+ case RT305X_SOC_RT3052:
-+ *idx = 0;
-+ return "ralink,rt3052-sysc";
-+ case RT305X_SOC_RT3350:
-+ *idx = 1;
-+ return "ralink,rt3350-sysc";
-+ case RT305X_SOC_RT3352:
-+ *idx = 1;
-+ return "ralink,rt3352-sysc";
-+ case RT305X_SOC_RT5350:
-+ *idx = 1;
-+ return "ralink,rt5350-sysc";
-+ case MT762X_SOC_MT7620A:
-+ *idx = 2;
-+ return "ralink,mt7620-sysc";
-+ case MT762X_SOC_MT7620N:
-+ *idx = 2;
-+ return "ralink,mt7620-sysc";
-+ case MT762X_SOC_MT7628AN:
-+ *idx = 1;
-+ return "ralink,mt7628-sysc";
-+ case MT762X_SOC_MT7688:
-+ *idx = 1;
-+ return "ralink,mt7688-sysc";
-+ default:
-+ *idx = -1;
-+ return "invalid";
-+ }
- }
-
- void __init plat_time_init(void)
- {
-+ struct of_phandle_args clkspec;
-+ const char *compatible;
- struct clk *clk;
-+ int cpu_clk_idx;
-
- ralink_of_remap();
-
-- ralink_clk_init();
-- clk = clk_get_sys("cpu", NULL);
-+ compatible = clk_cpu(&cpu_clk_idx);
-+ if (cpu_clk_idx == -1)
-+ panic("unable to get CPU clock index");
-+
-+ of_clk_init(NULL);
-+ clkspec.np = of_find_compatible_node(NULL, NULL, compatible);
-+ clkspec.args_count = 1;
-+ clkspec.args[0] = cpu_clk_idx;
-+ clk = of_clk_get_from_provider(&clkspec);
- if (IS_ERR(clk))
- panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
- pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
+++ /dev/null
-From fc15a7193a4d37d79e873fa06cc423180ddd2ddf Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 19 Jun 2023 06:09:41 +0200
-Subject: [PATCH 9/9] MAINTAINERS: add Mediatek MTMIPS Clock maintainer
-
-Adding myself as maintainer for Mediatek MTMIPS clock driver.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- MAINTAINERS | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -13021,6 +13021,12 @@ S: Maintained
- F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
- F: drivers/clk/ralink/clk-mt7621.c
-
-+MEDIATEK MTMIPS CLOCK DRIVER
-+M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-+S: Maintained
-+F: Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
-+F: drivers/clk/ralink/clk-mtmips.c
-+
- MEDIATEK MT7621/28/88 I2C DRIVER
- M: Stefan Roese <sr@denx.de>
- L: linux-i2c@vger.kernel.org
+++ /dev/null
-From fd99ac5055d4705e91c73d1adba18bc71c8511a8 Mon Sep 17 00:00:00 2001
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Tue, 20 Jun 2023 19:44:32 +0800
-Subject: [PATCH] mips: ralink: introduce commonly used remap node function
-
-The ralink_of_remap() function is repeated several times on SoC specific
-source files. They have the same structure, but just differ in compatible
-strings. In order to make commonly use of these codes, this patch
-introduces a newly designed mtmips_of_remap_node() function to match and
-remap all supported system controller and memory controller nodes.
-
-Build and run tested on MT7620 and MT7628.
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
-Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/ralink/common.h | 2 --
- arch/mips/ralink/mt7620.c | 9 ---------
- arch/mips/ralink/mt7621.c | 9 ---------
- arch/mips/ralink/of.c | 42 +++++++++++++++++++++++++++++++++++-------
- arch/mips/ralink/rt288x.c | 9 ---------
- arch/mips/ralink/rt305x.c | 9 ---------
- arch/mips/ralink/rt3883.c | 9 ---------
- 7 files changed, 35 insertions(+), 54 deletions(-)
-
---- a/arch/mips/ralink/common.h
-+++ b/arch/mips/ralink/common.h
-@@ -25,6 +25,4 @@ extern void ralink_of_remap(void);
-
- extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
-
--__iomem void *plat_of_remap_node(const char *node);
--
- #endif /* _RALINK_COMMON_H__ */
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -43,15 +43,6 @@
- /* does the board have sdram or ddram */
- static int dram_type;
-
--void __init ralink_of_remap(void)
--{
-- rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
-- rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
--
-- if (!rt_sysc_membase || !rt_memc_membase)
-- panic("Failed to remap core resources");
--}
--
- static __init void
- mt7620_dram_init(struct ralink_soc_info *soc_info)
- {
---- a/arch/mips/ralink/mt7621.c
-+++ b/arch/mips/ralink/mt7621.c
-@@ -89,15 +89,6 @@ static void __init mt7621_memory_detect(
- memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
- }
-
--void __init ralink_of_remap(void)
--{
-- rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
-- rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
--
-- if (!rt_sysc_membase || !rt_memc_membase)
-- panic("Failed to remap core resources");
--}
--
- static unsigned int __init mt7621_get_soc_name0(void)
- {
- return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -29,28 +29,56 @@ __iomem void *rt_sysc_membase;
- __iomem void *rt_memc_membase;
- EXPORT_SYMBOL_GPL(rt_sysc_membase);
-
--__iomem void *plat_of_remap_node(const char *node)
-+static const struct of_device_id mtmips_memc_match[] = {
-+ { .compatible = "mediatek,mt7621-memc" },
-+ { .compatible = "ralink,mt7620a-memc" },
-+ { .compatible = "ralink,rt2880-memc" },
-+ { .compatible = "ralink,rt3050-memc" },
-+ { .compatible = "ralink,rt3883-memc" },
-+ {}
-+};
-+
-+static const struct of_device_id mtmips_sysc_match[] = {
-+ { .compatible = "mediatek,mt7621-sysc" },
-+ { .compatible = "ralink,mt7620a-sysc" },
-+ { .compatible = "ralink,rt2880-sysc" },
-+ { .compatible = "ralink,rt3050-sysc" },
-+ { .compatible = "ralink,rt3883-sysc" },
-+ {}
-+};
-+
-+static __iomem void *
-+mtmips_of_remap_node(const struct of_device_id *match, const char *type)
- {
- struct resource res;
- struct device_node *np;
-
-- np = of_find_compatible_node(NULL, NULL, node);
-+ np = of_find_matching_node(NULL, match);
- if (!np)
-- panic("Failed to find %s node", node);
-+ panic("Failed to find %s controller node", type);
-
- if (of_address_to_resource(np, 0, &res))
-- panic("Failed to get resource for %s", node);
--
-- of_node_put(np);
-+ panic("Failed to get resource for %s node", np->name);
-
- if (!request_mem_region(res.start,
- resource_size(&res),
- res.name))
-- panic("Failed to request resources for %s", node);
-+ panic("Failed to request resources for %s node", np->name);
-+
-+ of_node_put(np);
-
- return ioremap(res.start, resource_size(&res));
- }
-
-+void __init ralink_of_remap(void)
-+{
-+ rt_sysc_membase = mtmips_of_remap_node(mtmips_sysc_match, "system");
-+ rt_memc_membase = mtmips_of_remap_node(mtmips_memc_match, "memory");
-+
-+ if (!rt_sysc_membase || !rt_memc_membase)
-+ panic("Failed to remap core resources");
-+}
-+
- void __init plat_mem_setup(void)
- {
- void *dtb;
---- a/arch/mips/ralink/rt288x.c
-+++ b/arch/mips/ralink/rt288x.c
-@@ -17,15 +17,6 @@
-
- #include "common.h"
-
--void __init ralink_of_remap(void)
--{
-- rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
-- rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
--
-- if (!rt_sysc_membase || !rt_memc_membase)
-- panic("Failed to remap core resources");
--}
--
- void __init prom_soc_init(struct ralink_soc_info *soc_info)
- {
- void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
---- a/arch/mips/ralink/rt305x.c
-+++ b/arch/mips/ralink/rt305x.c
-@@ -53,15 +53,6 @@ static unsigned long rt5350_get_mem_size
- return ret;
- }
-
--void __init ralink_of_remap(void)
--{
-- rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
-- rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
--
-- if (!rt_sysc_membase || !rt_memc_membase)
-- panic("Failed to remap core resources");
--}
--
- void __init prom_soc_init(struct ralink_soc_info *soc_info)
- {
- void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
---- a/arch/mips/ralink/rt3883.c
-+++ b/arch/mips/ralink/rt3883.c
-@@ -17,15 +17,6 @@
-
- #include "common.h"
-
--void __init ralink_of_remap(void)
--{
-- rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
-- rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
--
-- if (!rt_sysc_membase || !rt_memc_membase)
-- panic("Failed to remap core resources");
--}
--
- void __init prom_soc_init(struct ralink_soc_info *soc_info)
- {
- void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
+++ /dev/null
-From 6e68dae946e3a0333fbde5487ce163142ca10ae0 Mon Sep 17 00:00:00 2001
-From: Nathan Chancellor <nathan@kernel.org>
-Date: Thu, 22 Jun 2023 15:56:19 +0000
-Subject: clk: ralink: mtmips: Fix uninitialized use of ret in
- mtmips_register_{fixed,factor}_clocks()
-
-Clang warns:
-
- drivers/clk/ralink/clk-mtmips.c:309:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
- 309 | return ret;
- | ^~~
- drivers/clk/ralink/clk-mtmips.c:285:9: note: initialize the variable 'ret' to silence this warning
- 285 | int ret, i;
- | ^
- | = 0
- drivers/clk/ralink/clk-mtmips.c:359:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
- 359 | return ret;
- | ^~~
- drivers/clk/ralink/clk-mtmips.c:335:9: note: initialize the variable 'ret' to silence this warning
- 335 | int ret, i;
- | ^
- | = 0
- 2 errors generated.
-
-Set ret to the return value of clk_hw_register_fixed_rate() using the
-PTR_ERR() macro, which ensures ret is not used uninitialized, clearing
-up the warning.
-
-Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
-Closes: https://github.com/ClangBuiltLinux/linux/issues/1879
-Signed-off-by: Nathan Chancellor <nathan@kernel.org>
-Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
-Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- drivers/clk/ralink/clk-mtmips.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/clk/ralink/clk-mtmips.c
-+++ b/drivers/clk/ralink/clk-mtmips.c
-@@ -292,6 +292,7 @@ static int mtmips_register_fixed_clocks(
- sclk->parent, 0,
- sclk->rate);
- if (IS_ERR(sclk->hw)) {
-+ ret = PTR_ERR(sclk->hw);
- pr_err("Couldn't register fixed clock %d\n", idx);
- goto err_clk_unreg;
- }
-@@ -342,6 +343,7 @@ static int mtmips_register_factor_clocks
- sclk->parent, sclk->flags,
- sclk->mult, sclk->div);
- if (IS_ERR(sclk->hw)) {
-+ ret = PTR_ERR(sclk->hw);
- pr_err("Couldn't register factor clock %d\n", idx);
- goto err_clk_unreg;
- }
+++ /dev/null
-From 670f77f76f650b1b341d31d009cc2fb03a4d1fcf Mon Sep 17 00:00:00 2001
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Fri, 23 Jun 2023 08:17:48 +0800
-Subject: mips: ralink: match all supported system controller compatible
- strings
-
-Recently, A new clock and reset controller driver has been introduced to
-the ralink mips target[1]. It provides proper system control and adds more
-SoC specific compatible strings. In order to better initialize CPUs, this
-patch removes the outdated "ralink,mt7620a-sysc" and add all dt-binding
-documented compatible strings to the system controller match table.
-
-[1] https://lore.kernel.org/all/20230619040941.1340372-1-sergio.paracuellos@gmail.com/
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
-Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/ralink/of.c | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -40,10 +40,15 @@ static const struct of_device_id mtmips_
-
- static const struct of_device_id mtmips_sysc_match[] = {
- { .compatible = "mediatek,mt7621-sysc" },
-- { .compatible = "ralink,mt7620a-sysc" },
-+ { .compatible = "ralink,mt7620-sysc" },
-+ { .compatible = "ralink,mt7628-sysc" },
-+ { .compatible = "ralink,mt7688-sysc" },
- { .compatible = "ralink,rt2880-sysc" },
- { .compatible = "ralink,rt3050-sysc" },
-+ { .compatible = "ralink,rt3052-sysc" },
-+ { .compatible = "ralink,rt3352-sysc" },
- { .compatible = "ralink,rt3883-sysc" },
-+ { .compatible = "ralink,rt5350-sysc" },
- {}
- };
-
+++ /dev/null
-From 783c7cb4659b53b5e1b809dac5e8cdf250145919 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Tue, 14 Feb 2023 11:39:35 +0100
-Subject: [PATCH 1/2] watchdog: mt7621-wdt: avoid static global declarations
-
-Instead of using static global definitions in driver code, refactor code
-introducing a new watchdog driver data structure and use it along the
-code.
-
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Link: https://lore.kernel.org/r/20230214103936.1061078-5-sergio.paracuellos@gmail.com
-[groeck: unsigned -> unsigned int]
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/mt7621_wdt.c | 102 +++++++++++++++++++++++++++---------------
- 1 file changed, 65 insertions(+), 37 deletions(-)
-
---- a/drivers/watchdog/mt7621_wdt.c
-+++ b/drivers/watchdog/mt7621_wdt.c
-@@ -31,8 +31,11 @@
- #define TMR1CTL_RESTART BIT(9)
- #define TMR1CTL_PRESCALE_SHIFT 16
-
--static void __iomem *mt7621_wdt_base;
--static struct reset_control *mt7621_wdt_reset;
-+struct mt7621_wdt_data {
-+ void __iomem *base;
-+ struct reset_control *rst;
-+ struct watchdog_device wdt;
-+};
-
- static bool nowayout = WATCHDOG_NOWAYOUT;
- module_param(nowayout, bool, 0);
-@@ -40,27 +43,31 @@ MODULE_PARM_DESC(nowayout,
- "Watchdog cannot be stopped once started (default="
- __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-
--static inline void rt_wdt_w32(unsigned reg, u32 val)
-+static inline void rt_wdt_w32(void __iomem *base, unsigned int reg, u32 val)
- {
-- iowrite32(val, mt7621_wdt_base + reg);
-+ iowrite32(val, base + reg);
- }
-
--static inline u32 rt_wdt_r32(unsigned reg)
-+static inline u32 rt_wdt_r32(void __iomem *base, unsigned int reg)
- {
-- return ioread32(mt7621_wdt_base + reg);
-+ return ioread32(base + reg);
- }
-
- static int mt7621_wdt_ping(struct watchdog_device *w)
- {
-- rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
-+ struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
-+
-+ rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
-
- return 0;
- }
-
- static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
- {
-+ struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
-+
- w->timeout = t;
-- rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
-+ rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000);
- mt7621_wdt_ping(w);
-
- return 0;
-@@ -68,29 +75,31 @@ static int mt7621_wdt_set_timeout(struct
-
- static int mt7621_wdt_start(struct watchdog_device *w)
- {
-+ struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
- u32 t;
-
- /* set the prescaler to 1ms == 1000us */
-- rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
-+ rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
-
- mt7621_wdt_set_timeout(w, w->timeout);
-
-- t = rt_wdt_r32(TIMER_REG_TMR1CTL);
-+ t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
- t |= TMR1CTL_ENABLE;
-- rt_wdt_w32(TIMER_REG_TMR1CTL, t);
-+ rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
-
- return 0;
- }
-
- static int mt7621_wdt_stop(struct watchdog_device *w)
- {
-+ struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
- u32 t;
-
- mt7621_wdt_ping(w);
-
-- t = rt_wdt_r32(TIMER_REG_TMR1CTL);
-+ t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL);
- t &= ~TMR1CTL_ENABLE;
-- rt_wdt_w32(TIMER_REG_TMR1CTL, t);
-+ rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, t);
-
- return 0;
- }
-@@ -105,7 +114,9 @@ static int mt7621_wdt_bootcause(void)
-
- static int mt7621_wdt_is_running(struct watchdog_device *w)
- {
-- return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
-+ struct mt7621_wdt_data *drvdata = watchdog_get_drvdata(w);
-+
-+ return !!(rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE);
- }
-
- static const struct watchdog_info mt7621_wdt_info = {
-@@ -121,30 +132,39 @@ static const struct watchdog_ops mt7621_
- .set_timeout = mt7621_wdt_set_timeout,
- };
-
--static struct watchdog_device mt7621_wdt_dev = {
-- .info = &mt7621_wdt_info,
-- .ops = &mt7621_wdt_ops,
-- .min_timeout = 1,
-- .max_timeout = 0xfffful / 1000,
--};
--
- static int mt7621_wdt_probe(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
-- mt7621_wdt_base = devm_platform_ioremap_resource(pdev, 0);
-- if (IS_ERR(mt7621_wdt_base))
-- return PTR_ERR(mt7621_wdt_base);
--
-- mt7621_wdt_reset = devm_reset_control_get_exclusive(dev, NULL);
-- if (!IS_ERR(mt7621_wdt_reset))
-- reset_control_deassert(mt7621_wdt_reset);
--
-- mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause();
--
-- watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout,
-- dev);
-- watchdog_set_nowayout(&mt7621_wdt_dev, nowayout);
-- if (mt7621_wdt_is_running(&mt7621_wdt_dev)) {
-+ struct watchdog_device *mt7621_wdt;
-+ struct mt7621_wdt_data *drvdata;
-+ int err;
-+
-+ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
-+ if (!drvdata)
-+ return -ENOMEM;
-+
-+ drvdata->base = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(drvdata->base))
-+ return PTR_ERR(drvdata->base);
-+
-+ drvdata->rst = devm_reset_control_get_exclusive(dev, NULL);
-+ if (!IS_ERR(drvdata->rst))
-+ reset_control_deassert(drvdata->rst);
-+
-+ mt7621_wdt = &drvdata->wdt;
-+ mt7621_wdt->info = &mt7621_wdt_info;
-+ mt7621_wdt->ops = &mt7621_wdt_ops;
-+ mt7621_wdt->min_timeout = 1;
-+ mt7621_wdt->max_timeout = 0xfffful / 1000;
-+ mt7621_wdt->parent = dev;
-+
-+ mt7621_wdt->bootstatus = mt7621_wdt_bootcause();
-+
-+ watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev);
-+ watchdog_set_nowayout(mt7621_wdt, nowayout);
-+ watchdog_set_drvdata(mt7621_wdt, drvdata);
-+
-+ if (mt7621_wdt_is_running(mt7621_wdt)) {
- /*
- * Make sure to apply timeout from watchdog core, taking
- * the prescaler of this driver here into account (the
-@@ -154,17 +174,25 @@ static int mt7621_wdt_probe(struct platf
- * we first disable the watchdog, set the new prescaler
- * and timeout, and then re-enable the watchdog.
- */
-- mt7621_wdt_stop(&mt7621_wdt_dev);
-- mt7621_wdt_start(&mt7621_wdt_dev);
-- set_bit(WDOG_HW_RUNNING, &mt7621_wdt_dev.status);
-+ mt7621_wdt_stop(mt7621_wdt);
-+ mt7621_wdt_start(mt7621_wdt);
-+ set_bit(WDOG_HW_RUNNING, &mt7621_wdt->status);
- }
-
-- return devm_watchdog_register_device(dev, &mt7621_wdt_dev);
-+ err = devm_watchdog_register_device(dev, &drvdata->wdt);
-+ if (err)
-+ return err;
-+
-+ platform_set_drvdata(pdev, drvdata);
-+
-+ return 0;
- }
-
- static void mt7621_wdt_shutdown(struct platform_device *pdev)
- {
-- mt7621_wdt_stop(&mt7621_wdt_dev);
-+ struct mt7621_wdt_data *drvdata = platform_get_drvdata(pdev);
-+
-+ mt7621_wdt_stop(&drvdata->wdt);
- }
-
- static const struct of_device_id mt7621_wdt_match[] = {
+++ /dev/null
-From ff8ec4ac39ad413b580d611dbf68e1d8a82eba56 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Tue, 14 Feb 2023 11:39:36 +0100
-Subject: [PATCH 2/2] watchdog: mt7621-wdt: avoid ralink architecture dependent code
-
-MT7621 SoC has a system controller node. Watchdog need to access to reset
-status register. Ralink architecture and related driver are old and from
-the beggining they are using some architecture dependent operations for
-accessing this shared registers through 'asm/mach-ralink/ralink_regs.h'
-header file. However this is not ideal from a driver perspective which can
-just access to the system controller registers in an arch independent way
-using regmap syscon APIs. Update Kconfig accordingly to select new added
-dependencies and allow driver to be compile tested.
-
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20230214103936.1061078-6-sergio.paracuellos@gmail.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/Kconfig | 4 +++-
- drivers/watchdog/mt7621_wdt.c | 22 +++++++++++++++++-----
- 2 files changed, 20 insertions(+), 6 deletions(-)
-
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -1865,7 +1865,9 @@ config GXP_WATCHDOG
- config MT7621_WDT
- tristate "Mediatek SoC watchdog"
- select WATCHDOG_CORE
-- depends on SOC_MT7620 || SOC_MT7621
-+ select REGMAP_MMIO
-+ select MFD_SYSCON
-+ depends on SOC_MT7620 || SOC_MT7621 || COMPILE_TEST
- help
- Hardware driver for the Mediatek/Ralink MT7621/8 SoC Watchdog Timer.
-
---- a/drivers/watchdog/mt7621_wdt.c
-+++ b/drivers/watchdog/mt7621_wdt.c
-@@ -15,8 +15,8 @@
- #include <linux/moduleparam.h>
- #include <linux/platform_device.h>
- #include <linux/mod_devicetable.h>
--
--#include <asm/mach-ralink/ralink_regs.h>
-+#include <linux/mfd/syscon.h>
-+#include <linux/regmap.h>
-
- #define SYSC_RSTSTAT 0x38
- #define WDT_RST_CAUSE BIT(1)
-@@ -34,6 +34,7 @@
- struct mt7621_wdt_data {
- void __iomem *base;
- struct reset_control *rst;
-+ struct regmap *sysc;
- struct watchdog_device wdt;
- };
-
-@@ -104,9 +105,12 @@ static int mt7621_wdt_stop(struct watchd
- return 0;
- }
-
--static int mt7621_wdt_bootcause(void)
-+static int mt7621_wdt_bootcause(struct mt7621_wdt_data *d)
- {
-- if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
-+ u32 val;
-+
-+ regmap_read(d->sysc, SYSC_RSTSTAT, &val);
-+ if (val & WDT_RST_CAUSE)
- return WDIOF_CARDRESET;
-
- return 0;
-@@ -134,6 +138,7 @@ static const struct watchdog_ops mt7621_
-
- static int mt7621_wdt_probe(struct platform_device *pdev)
- {
-+ struct device_node *np = pdev->dev.of_node;
- struct device *dev = &pdev->dev;
- struct watchdog_device *mt7621_wdt;
- struct mt7621_wdt_data *drvdata;
-@@ -143,6 +148,13 @@ static int mt7621_wdt_probe(struct platf
- if (!drvdata)
- return -ENOMEM;
-
-+ drvdata->sysc = syscon_regmap_lookup_by_phandle(np, "mediatek,sysctl");
-+ if (IS_ERR(drvdata->sysc)) {
-+ drvdata->sysc = syscon_regmap_lookup_by_compatible("mediatek,mt7621-sysc");
-+ if (IS_ERR(drvdata->sysc))
-+ return PTR_ERR(drvdata->sysc);
-+ }
-+
- drvdata->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(drvdata->base))
- return PTR_ERR(drvdata->base);
-@@ -158,7 +170,7 @@ static int mt7621_wdt_probe(struct platf
- mt7621_wdt->max_timeout = 0xfffful / 1000;
- mt7621_wdt->parent = dev;
-
-- mt7621_wdt->bootstatus = mt7621_wdt_bootcause();
-+ mt7621_wdt->bootstatus = mt7621_wdt_bootcause(drvdata);
-
- watchdog_init_timeout(mt7621_wdt, mt7621_wdt->max_timeout, dev);
- watchdog_set_nowayout(mt7621_wdt, nowayout);
+++ /dev/null
-From 9f9a035e6156a57d9da062b26d2a48d031744a1e Mon Sep 17 00:00:00 2001
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Tue, 20 Jun 2023 18:43:22 +0800
-Subject: [PATCH 1/2] mips: pci-mt7620: do not print NFTS register value as
- error log
-
-These codes are used to read NFTS_TIMEOUT_DELAY register value and
-write it into kernel log after writing the register. they are only
-used for debugging during driver development, so there is no need
-to keep them now.
-
-Tested on MT7628AN router Motorola MWR03.
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
-Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/pci/pci-mt7620.c | 3 ---
- 1 file changed, 3 deletions(-)
-
---- a/arch/mips/pci/pci-mt7620.c
-+++ b/arch/mips/pci/pci-mt7620.c
-@@ -274,9 +274,6 @@ static int mt7628_pci_hw_init(struct pla
- val |= 0x50 << 8;
- pci_config_write(NULL, 0, 0x70c, 4, val);
-
-- pci_config_read(NULL, 0, 0x70c, 4, &val);
-- dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
--
- return 0;
- }
-
+++ /dev/null
-From 89ec9bbe60b61cc6ae3eddd6d4f43e128f8a88de Mon Sep 17 00:00:00 2001
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Tue, 20 Jun 2023 18:43:23 +0800
-Subject: [PATCH 2/2] mips: pci-mt7620: use dev_info() to log PCIe device
- detection result
-
-Usually, We only need to print the error log when there is a PCIe card but
-initialization fails. Whether the driver finds the PCIe card or not is the
-expected behavior. So it's better to log these information with dev_info().
-
-Tested on MT7628AN router Motorola MWR03.
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
-Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/pci/pci-mt7620.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/mips/pci/pci-mt7620.c
-+++ b/arch/mips/pci/pci-mt7620.c
-@@ -331,7 +331,7 @@ static int mt7620_pci_probe(struct platf
- rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
- if (ralink_soc == MT762X_SOC_MT7620A)
- rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
-- dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
-+ dev_info(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
- return -1;
- }
-
-@@ -374,7 +374,7 @@ int pcibios_map_irq(const struct pci_dev
- dev->bus->number, slot);
- return 0;
- }
-- dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
-+ dev_info(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
- dev->bus->number, slot, irq);
-
- /* configure the cache line size to 0x14 */
+++ /dev/null
-From 50233e105a0332ec0f3bc83180c416e6b200471e Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Fri, 24 Mar 2023 08:37:33 +0100
-Subject: PCI: mt7621: Use dev_info() to log PCIe card detection
-
-When there is no card plugged on a PCIe port a log reporting that
-the port will be disabled is flagged as an error (dev_err()).
-
-Since this is not an error at all, change the log level by using
-dev_info() instead.
-
-Link: https://lore.kernel.org/r/20230324073733.1596231-1-sergio.paracuellos@gmail.com
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
----
- drivers/pci/controller/pcie-mt7621.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/pci/controller/pcie-mt7621.c
-+++ b/drivers/pci/controller/pcie-mt7621.c
-@@ -378,8 +378,8 @@ static int mt7621_pcie_init_ports(struct
- u32 slot = port->slot;
-
- if (!mt7621_pcie_port_is_linkup(port)) {
-- dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
-- slot);
-+ dev_info(dev, "pcie%d no card, disable it (RST & CLK)\n",
-+ slot);
- mt7621_control_assert(port);
- port->enabled = false;
- num_disabled++;
+++ /dev/null
---- a/drivers/net/ethernet/Kconfig
-+++ b/drivers/net/ethernet/Kconfig
-@@ -166,6 +166,7 @@ source "drivers/net/ethernet/pensando/Kc
- source "drivers/net/ethernet/qlogic/Kconfig"
- source "drivers/net/ethernet/brocade/Kconfig"
- source "drivers/net/ethernet/qualcomm/Kconfig"
-+source "drivers/net/ethernet/ralink/Kconfig"
- source "drivers/net/ethernet/rdc/Kconfig"
- source "drivers/net/ethernet/realtek/Kconfig"
- source "drivers/net/ethernet/renesas/Kconfig"
---- a/drivers/net/ethernet/Makefile
-+++ b/drivers/net/ethernet/Makefile
-@@ -77,6 +77,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES)
- obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
- obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
- obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/
-+obj-$(CONFIG_NET_VENDOR_RALINK) += ralink/
- obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
- obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/
- obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
+++ /dev/null
---- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -61,4 +61,16 @@ static inline int mt7620_get_eco(void)
- return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
- }
-
-+static inline int mt7620_get_chipver(void)
-+{
-+ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_VER_SHIFT) &
-+ CHIP_REV_VER_MASK;
-+}
-+
-+static inline int mt7620_get_pkg(void)
-+{
-+ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_PKG_SHIFT) &
-+ CHIP_REV_PKG_MASK;
-+}
-+
- #endif
+++ /dev/null
-From ce3d4a4111a5f7e6b4e74bceae5faa6ce388e8ec Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 14 Jul 2013 23:08:11 +0200
-Subject: [PATCH 05/53] MIPS: use set_mode() to enable/disable the cevt-r4k
- irq
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Kconfig | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -1,12 +1,17 @@
- # SPDX-License-Identifier: GPL-2.0
- if RALINK
-
-+config CEVT_SYSTICK_QUIRK
-+ bool
-+ default n
-+
- config CLKEVT_RT3352
- bool
- depends on SOC_RT305X || SOC_MT7620
- default y
- select TIMER_OF
- select CLKSRC_MMIO
-+ select CEVT_SYSTICK_QUIRK
-
- config RALINK_ILL_ACC
- bool
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -16,6 +16,31 @@
- #include <asm/time.h>
- #include <asm/cevt-r4k.h>
-
-+#ifdef CONFIG_CEVT_SYSTICK_QUIRK
-+static int mips_state_oneshot(struct clock_event_device *evt)
-+{
-+ unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
-+ if (!cp0_timer_irq_installed) {
-+ cp0_timer_irq_installed = 1;
-+ if (request_irq(evt->irq, c0_compare_interrupt, flags, "timer",
-+ c0_compare_interrupt))
-+ pr_err("Failed to request irq %d (timer)\n", evt->irq);
-+ }
-+
-+ return 0;
-+}
-+
-+static int mips_state_shutdown(struct clock_event_device *evt)
-+{
-+ if (cp0_timer_irq_installed) {
-+ cp0_timer_irq_installed = 0;
-+ free_irq(evt->irq, NULL);
-+ }
-+
-+ return 0;
-+}
-+#endif
-+
- static int mips_next_event(unsigned long delta,
- struct clock_event_device *evt)
- {
-@@ -292,7 +317,9 @@ core_initcall(r4k_register_cpufreq_notif
-
- int r4k_clockevent_init(void)
- {
-+#ifndef CONFIG_CEVT_SYSTICK_QUIRK
- unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
-+#endif
- unsigned int cpu = smp_processor_id();
- struct clock_event_device *cd;
- unsigned int irq, min_delta;
-@@ -322,11 +349,16 @@ int r4k_clockevent_init(void)
- cd->rating = 300;
- cd->irq = irq;
- cd->cpumask = cpumask_of(cpu);
-+#ifdef CONFIG_CEVT_SYSTICK_QUIRK
-+ cd->set_state_shutdown = mips_state_shutdown;
-+ cd->set_state_oneshot = mips_state_oneshot;
-+#endif
- cd->set_next_event = mips_next_event;
- cd->event_handler = mips_event_handler;
-
- clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);
-
-+#ifndef CONFIG_CEVT_SYSTICK_QUIRK
- if (cp0_timer_irq_installed)
- return 0;
-
-@@ -335,6 +367,7 @@ int r4k_clockevent_init(void)
- if (request_irq(irq, c0_compare_interrupt, flags, "timer",
- c0_compare_interrupt))
- pr_err("Failed to request irq %d (timer)\n", irq);
-+#endif
-
- return 0;
- }
+++ /dev/null
-From bd30f19a006fb52bac80c6463c49dd2f4159f4ac Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 16:26:41 +0200
-Subject: [PATCH 06/53] MIPS: ralink: add cpu frequency scaling
-
-This feature will break udelay() and cause the delay loop to have longer delays
-when the frequency is scaled causing a performance hit.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/cevt-rt3352.c | 38 ++++++++++++++++++++++++++++++++++++++
- 1 file changed, 38 insertions(+)
-
---- a/arch/mips/ralink/cevt-rt3352.c
-+++ b/arch/mips/ralink/cevt-rt3352.c
-@@ -29,6 +29,10 @@
- /* enable the counter */
- #define CFG_CNT_EN 0x1
-
-+/* mt7620 frequency scaling defines */
-+#define CLK_LUT_CFG 0x40
-+#define SLEEP_EN BIT(31)
-+
- struct systick_device {
- void __iomem *membase;
- struct clock_event_device dev;
-@@ -36,21 +40,53 @@ struct systick_device {
- int freq_scale;
- };
-
-+static void (*systick_freq_scaling)(struct systick_device *sdev, int status);
-+
- static int systick_set_oneshot(struct clock_event_device *evt);
- static int systick_shutdown(struct clock_event_device *evt);
-
-+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
-+{
-+ if (sdev->freq_scale == status)
-+ return;
-+
-+ sdev->freq_scale = status;
-+
-+ pr_info("%s: %s autosleep mode\n", sdev->dev.name,
-+ (status) ? ("enable") : ("disable"));
-+ if (status)
-+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
-+ else
-+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
-+}
-+
-+static inline unsigned int read_count(struct systick_device *sdev)
-+{
-+ return ioread32(sdev->membase + SYSTICK_COUNT);
-+}
-+
-+static inline unsigned int read_compare(struct systick_device *sdev)
-+{
-+ return ioread32(sdev->membase + SYSTICK_COMPARE);
-+}
-+
-+static inline void write_compare(struct systick_device *sdev, unsigned int val)
-+{
-+ iowrite32(val, sdev->membase + SYSTICK_COMPARE);
-+}
-+
- static int systick_next_event(unsigned long delta,
- struct clock_event_device *evt)
- {
- struct systick_device *sdev;
-- u32 count;
-+ int res;
-
- sdev = container_of(evt, struct systick_device, dev);
-- count = ioread32(sdev->membase + SYSTICK_COUNT);
-- count = (count + delta) % SYSTICK_FREQ;
-- iowrite32(count, sdev->membase + SYSTICK_COMPARE);
-+ delta += read_count(sdev);
-+ write_compare(sdev, delta);
-+ res = ((int)(read_count(sdev) - delta) >= 0) ? -ETIME : 0;
-
-- return 0;
-+ return res;
- }
-
- static void systick_event_handler(struct clock_event_device *dev)
-@@ -60,20 +96,25 @@ static void systick_event_handler(struct
-
- static irqreturn_t systick_interrupt(int irq, void *dev_id)
- {
-- struct clock_event_device *dev = (struct clock_event_device *) dev_id;
-+ int ret = 0;
-+ struct clock_event_device *cdev;
-+ struct systick_device *sdev;
-
-- dev->event_handler(dev);
-+ if (read_c0_cause() & STATUSF_IP7) {
-+ cdev = (struct clock_event_device *) dev_id;
-+ sdev = container_of(cdev, struct systick_device, dev);
-+
-+ /* Clear Count/Compare Interrupt */
-+ write_compare(sdev, read_compare(sdev));
-+ cdev->event_handler(cdev);
-+ ret = 1;
-+ }
-
-- return IRQ_HANDLED;
-+ return IRQ_RETVAL(ret);
- }
-
- static struct systick_device systick = {
- .dev = {
-- /*
-- * cevt-r4k uses 300, make sure systick
-- * gets used if available
-- */
-- .rating = 310,
- .features = CLOCK_EVT_FEAT_ONESHOT,
- .set_next_event = systick_next_event,
- .set_state_shutdown = systick_shutdown,
-@@ -91,7 +132,13 @@ static int systick_shutdown(struct clock
- if (sdev->irq_requested)
- free_irq(systick.dev.irq, &systick.dev);
- sdev->irq_requested = 0;
-- iowrite32(0, systick.membase + SYSTICK_CONFIG);
-+ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
-+
-+ if (systick_freq_scaling)
-+ systick_freq_scaling(sdev, 0);
-+
-+ if (systick_freq_scaling)
-+ systick_freq_scaling(sdev, 1);
-
- return 0;
- }
-@@ -116,33 +163,46 @@ static int systick_set_oneshot(struct cl
- return 0;
- }
-
-+static const struct of_device_id systick_match[] = {
-+ { .compatible = "ralink,mt7620a-systick", .data = mt7620_freq_scaling},
-+ {},
-+};
-+
- static int __init ralink_systick_init(struct device_node *np)
- {
-- int ret;
-+ const struct of_device_id *match;
-+ int rating = 200;
-
- systick.membase = of_iomap(np, 0);
- if (!systick.membase)
- return -ENXIO;
-
-- systick.dev.name = np->name;
-- clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
-- systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
-- systick.dev.max_delta_ticks = 0x7fff;
-- systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
-- systick.dev.min_delta_ticks = 0x3;
-+ match = of_match_node(systick_match, np);
-+ if (match) {
-+ systick_freq_scaling = match->data;
-+ /*
-+ * cevt-r4k uses 300, make sure systick
-+ * gets used if available
-+ */
-+ rating = 310;
-+ }
-+
-+ /* enable counter than register clock source */
-+ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
-+ clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
-+ SYSTICK_FREQ, rating, 16, clocksource_mmio_readl_up);
-+
-+ /* register clock event */
- systick.dev.irq = irq_of_parse_and_map(np, 0);
- if (!systick.dev.irq) {
- pr_err("%pOFn: request_irq failed", np);
- return -EINVAL;
- }
-
-- ret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
-- SYSTICK_FREQ, 301, 16,
-- clocksource_mmio_readl_up);
-- if (ret)
-- return ret;
--
-- clockevents_register_device(&systick.dev);
-+ systick.dev.name = np->name;
-+ systick.dev.rating = rating;
-+ systick.dev.cpumask = cpumask_of(0);
-+ clockevents_config_and_register(&systick.dev, SYSTICK_FREQ, 0x3, 0x7fff);
-
- pr_info("%pOFn: running - mult: %d, shift: %d\n",
- np, systick.dev.mult, systick.dev.shift);
+++ /dev/null
-From f15d27f9c90ede4b16eb37f9ae573ef81c2b6996 Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Thu, 31 Dec 2020 18:49:12 +0100
-Subject: [PATCH] MIPS: add bootargs-override property
-
-Add support for the bootargs-override property to the chosen node
-similar to the one used on ipq806x or mpc85xx.
-
-This is necessary, as the U-Boot used on some boards, notably the
-Ubiquiti UniFi 6 Lite, overwrite the bootargs property of the chosen
-node leading to a kernel panic when loading OpenWrt.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- arch/mips/kernel/setup.c | 30 ++++++++++++++++++++++++++++++
- 1 file changed, 30 insertions(+)
-
---- a/arch/mips/kernel/setup.c
-+++ b/arch/mips/kernel/setup.c
-@@ -557,8 +557,28 @@ static int __init bootcmdline_scan_chose
-
- #endif /* CONFIG_OF_EARLY_FLATTREE */
-
-+static int __init bootcmdline_scan_chosen_override(unsigned long node, const char *uname,
-+ int depth, void *data)
-+{
-+ bool *dt_bootargs = data;
-+ const char *p;
-+ int l;
-+
-+ if (depth != 1 || !data || strcmp(uname, "chosen") != 0)
-+ return 0;
-+
-+ p = of_get_flat_dt_prop(node, "bootargs-override", &l);
-+ if (p != NULL && l > 0) {
-+ strlcpy(boot_command_line, p, COMMAND_LINE_SIZE);
-+ *dt_bootargs = true;
-+ }
-+
-+ return 1;
-+}
-+
- static void __init bootcmdline_init(void)
- {
-+ bool dt_bootargs_override = false;
- bool dt_bootargs = false;
-
- /*
-@@ -572,6 +592,14 @@ static void __init bootcmdline_init(void
- }
-
- /*
-+ * If bootargs-override in the chosen node is set, use this as the
-+ * command line
-+ */
-+ of_scan_flat_dt(bootcmdline_scan_chosen_override, &dt_bootargs_override);
-+ if (dt_bootargs_override)
-+ return;
-+
-+ /*
- * If the user specified a built-in command line &
- * MIPS_CMDLINE_BUILTIN_EXTEND, then the built-in command line is
- * prepended to arguments from the bootloader or DT so we'll copy them
+++ /dev/null
-From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:15:32 +0100
-Subject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/kernel/setup.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/kernel/setup.c
-+++ b/arch/mips/kernel/setup.c
-@@ -699,7 +699,6 @@ static void __init arch_mem_init(char **
- mips_reserve_vmcore();
-
- mips_parse_crashkernel();
-- device_tree_init();
-
- /*
- * In order to reduce the possibility of kernel panic when failed to
-@@ -834,6 +833,7 @@ void __init setup_arch(char **cmdline_p)
-
- cpu_cache_init();
- paging_init();
-+ device_tree_init();
-
- memblock_dump_all();
-
+++ /dev/null
-From 9e6ce539092a1dd605a20bf73c655a9de58d8641 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:18:05 +0100
-Subject: [PATCH 15/53] arch: mips: do not select illegal access driver by
- default
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/Kconfig | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -14,9 +14,9 @@ config CLKEVT_RT3352
- select CEVT_SYSTICK_QUIRK
-
- config RALINK_ILL_ACC
-- bool
-+ bool "illegal access irq"
- depends on SOC_RT305X
-- default y
-+ default n
-
- config IRQ_INTC
- bool
+++ /dev/null
-From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001
-From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Date: Wed, 7 Apr 2021 13:07:38 -0700
-Subject: [PATCH] MIPS: add support for buggy MT7621S core detection
-
-Most MT7621 SoCs have 2 cores, which is detected and supported properly
-by CPS.
-
-Unfortunately, MT7621 SoC has a less common S variant with only one core.
-On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when
-starting SMP. CPULAUNCH registers can be used in that case to detect the
-absence of the second core and override the GCR_CONFIG PCORES field.
-
-Rework a long-standing OpenWrt patch to override the value of
-mips_cps_numcores on single-core MT7621 systems.
-
-Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
-MT7621 device (Netgear R6220).
-
-Original 4.14 OpenWrt patch:
-Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7
-Current 5.10 OpenWrt patch:
-Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904
-
-Suggested-by: Felix Fietkau <nbd@nbd.name>
-Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-
- 1 file changed, 22 insertions(+), 1 deletion(-)
-
---- a/arch/mips/include/asm/mips-cps.h
-+++ b/arch/mips/include/asm/mips-cps.h
-@@ -11,6 +11,8 @@
- #include <linux/io.h>
- #include <linux/types.h>
-
-+#include <asm/mips-boards/launch.h>
-+
- extern unsigned long __cps_access_bad_size(void)
- __compiletime_error("Bad size for CPS accessor");
-
-@@ -162,12 +164,31 @@ static inline uint64_t mips_cps_cluster_
- */
- static inline unsigned int mips_cps_numcores(unsigned int cluster)
- {
-+ unsigned int ncores;
-+
- if (!mips_cm_present())
- return 0;
-
- /* Add one before masking to handle 0xff indicating no cores */
-- return FIELD_GET(CM_GCR_CONFIG_PCORES,
-+ ncores = FIELD_GET(CM_GCR_CONFIG_PCORES,
- mips_cps_cluster_config(cluster) + 1);
-+
-+ if (IS_ENABLED(CONFIG_SOC_MT7621)) {
-+ struct cpulaunch *launch;
-+
-+ /*
-+ * Ralink MT7621S SoC is single core, but the GCR_CONFIG method
-+ * always reports 2 cores. Check the second core's LAUNCH_FREADY
-+ * flag to detect if the second core is missing. This method
-+ * only works before the core has been started.
-+ */
-+ launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
-+ launch += 2; /* MT7621 has 2 VPEs per core */
-+ if (!(launch->flags & LAUNCH_FREADY))
-+ ncores = 1;
-+ }
-+
-+ return ncores;
- }
-
- /**
+++ /dev/null
---- a/arch/mips/ralink/irq-gic.c
-+++ b/arch/mips/ralink/irq-gic.c
-@@ -13,6 +13,12 @@
-
- int get_c0_perfcount_int(void)
- {
-+ /*
-+ * Performance counter events are routed through GIC.
-+ * Prevent them from firing on CPU IRQ7 as well
-+ */
-+ clear_c0_status(IE_SW0 << 7);
-+
- return gic_get_c0_perfcount_int();
- }
- EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
+++ /dev/null
-From ee9081b2726a5ca8cde5497afdc5425e21ff8f8b Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 15 Jul 2013 00:39:21 +0200
-Subject: [PATCH 37/53] mtd: cfi cmdset 0002 force word write
-
----
- drivers/mtd/chips/cfi_cmdset_0002.c | 9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/drivers/mtd/chips/cfi_cmdset_0002.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
-@@ -40,7 +40,7 @@
- #include <linux/mtd/xip.h>
-
- #define AMD_BOOTLOC_BUG
--#define FORCE_WORD_WRITE 0
-+#define FORCE_WORD_WRITE 1
-
- #define MAX_RETRIES 3
-
+++ /dev/null
-From 52d14545d2fc276b1bf9ccf48d4612fab6edfb6a Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Thu, 6 May 2021 17:49:55 +0200
-Subject: [PATCH] mtd: spi-nor: Add support for BoHong bh25q128as
-
-Add MTD support for the BoHong bh25q128as SPI NOR chip.
-The chip has 16MB of total capacity, divided into a total of 256
-sectors, each 64KB sized. The chip also supports 4KB sectors.
-Additionally, it supports dual and quad read modes.
-
-Functionality was verified on an Tenbay WR1800K / MTK MT7621 board.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- drivers/mtd/spi-nor/Makefile | 1 +
- drivers/mtd/spi-nor/bohong.c | 21 +++++++++++++++++++++
- drivers/mtd/spi-nor/core.c | 1 +
- drivers/mtd/spi-nor/core.h | 1 +
- 4 files changed, 24 insertions(+)
- create mode 100644 drivers/mtd/spi-nor/bohong.c
-
---- a/drivers/mtd/spi-nor/Makefile
-+++ b/drivers/mtd/spi-nor/Makefile
-@@ -2,6 +2,7 @@
-
- spi-nor-objs := core.o sfdp.o swp.o otp.o sysfs.o
- spi-nor-objs += atmel.o
-+spi-nor-objs += bohong.o
- spi-nor-objs += catalyst.o
- spi-nor-objs += eon.o
- spi-nor-objs += esmt.o
---- /dev/null
-+++ b/drivers/mtd/spi-nor/bohong.c
-@@ -0,0 +1,21 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2005, Intec Automation Inc.
-+ * Copyright (C) 2014, Freescale Semiconductor, Inc.
-+ */
-+
-+#include <linux/mtd/spi-nor.h>
-+
-+#include "core.h"
-+
-+static const struct flash_info bohong_parts[] = {
-+ /* BoHong Microelectronics */
-+ { "bh25q128as", INFO(0x684018, 0, 64 * 1024, 256)
-+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-+};
-+
-+const struct spi_nor_manufacturer spi_nor_bohong = {
-+ .name = "bohong",
-+ .parts = bohong_parts,
-+ .nparts = ARRAY_SIZE(bohong_parts),
-+};
---- a/drivers/mtd/spi-nor/core.c
-+++ b/drivers/mtd/spi-nor/core.c
-@@ -1620,6 +1620,7 @@ int spi_nor_sr2_bit7_quad_enable(struct
-
- static const struct spi_nor_manufacturer *manufacturers[] = {
- &spi_nor_atmel,
-+ &spi_nor_bohong,
- &spi_nor_catalyst,
- &spi_nor_eon,
- &spi_nor_esmt,
---- a/drivers/mtd/spi-nor/core.h
-+++ b/drivers/mtd/spi-nor/core.h
-@@ -617,6 +617,7 @@ struct sfdp {
-
- /* Manufacturer drivers. */
- extern const struct spi_nor_manufacturer spi_nor_atmel;
-+extern const struct spi_nor_manufacturer spi_nor_bohong;
- extern const struct spi_nor_manufacturer spi_nor_catalyst;
- extern const struct spi_nor_manufacturer spi_nor_eon;
- extern const struct spi_nor_manufacturer spi_nor_esmt;
+++ /dev/null
-From e84e2430ee0e483842b4ff013ae8a6e7e2fa2734 Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 1 Apr 2020 02:07:58 +0800
-Subject: [PATCH 1/2] mtd: rawnand: add driver support for MT7621 nand
- flash controller
-
-This patch adds NAND flash controller driver for MediaTek MT7621 SoC.
-
-The NAND flash controller is similar with controllers described in
-mtk_nand.c, except that the controller from MT7621 doesn't support DMA
-transmission, and some registers' offset and fields are different.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- drivers/mtd/nand/raw/Kconfig | 8 +
- drivers/mtd/nand/raw/Makefile | 1 +
- drivers/mtd/nand/raw/mt7621_nand.c | 1348 ++++++++++++++++++++++++++++++++++++
- 3 files changed, 1357 insertions(+)
- create mode 100644 drivers/mtd/nand/raw/mt7621_nand.c
-
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -352,6 +352,14 @@ config MTD_NAND_QCOM
- Enables support for NAND flash chips on SoCs containing the EBI2 NAND
- controller. This controller is found on IPQ806x SoC.
-
-+config MTD_NAND_MT7621
-+ tristate "MT7621 NAND controller"
-+ depends on SOC_MT7621 || COMPILE_TEST
-+ depends on HAS_IOMEM
-+ help
-+ Enables support for NAND controller on MT7621 SoC.
-+ This driver uses PIO mode for data transmission instead of DMA mode.
-+
- config MTD_NAND_MTK
- tristate "MTK NAND controller"
- depends on MTD_NAND_ECC_MEDIATEK
---- a/drivers/mtd/nand/raw/Makefile
-+++ b/drivers/mtd/nand/raw/Makefile
-@@ -48,6 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n
- obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
- obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
-+obj-$(CONFIG_MTD_NAND_MT7621) += mt7621_nand.o
- obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o
- obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o
- obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
+++ /dev/null
-From 3d5f4da8296b23eb3abf8b13122b0d06a215e79c Mon Sep 17 00:00:00 2001
-From: Weijie Gao <weijie.gao@mediatek.com>
-Date: Wed, 1 Apr 2020 02:07:59 +0800
-Subject: [PATCH 2/2] dt-bindings: add documentation for mt7621-nand driver
-
-This patch adds documentation for MediaTek MT7621 NAND flash controller
-driver.
-
-Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
----
- .../bindings/mtd/mediatek,mt7621-nfc.yaml | 68 ++++++++++++++++++++++
- 1 file changed, 68 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
-@@ -0,0 +1,68 @@
-+# SPDX-License-Identifier: GPL-2.0
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/mtd/mediatek,mt7621-nfc.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: MediaTek MT7621 SoC NAND Flash Controller (NFC) DT binding
-+
-+maintainers:
-+ - Weijie Gao <weijie.gao@mediatek.com>
-+
-+description: |
-+ This driver uses a single node to describe both NAND Flash controller
-+ interface (NFI) and ECC engine for MT7621 SoC.
-+ MT7621 supports only one chip select.
-+
-+properties:
-+ "#address-cells": false
-+ "#size-cells": false
-+
-+ compatible:
-+ enum:
-+ - mediatek,mt7621-nfc
-+
-+ reg:
-+ items:
-+ - description: Register base of NFI core
-+ - description: Register base of ECC engine
-+
-+ reg-names:
-+ items:
-+ - const: nfi
-+ - const: ecc
-+
-+ clocks:
-+ items:
-+ - description: Source clock for NFI core, fixed 125MHz
-+
-+ clock-names:
-+ items:
-+ - const: nfi_clk
-+
-+required:
-+ - compatible
-+ - reg
-+ - reg-names
-+ - clocks
-+ - clock-names
-+
-+examples:
-+ - |
-+ nficlock: nficlock {
-+ #clock-cells = <0>;
-+ compatible = "fixed-clock";
-+
-+ clock-frequency = <125000000>;
-+ };
-+
-+ nand@1e003000 {
-+ compatible = "mediatek,mt7621-nfc";
-+
-+ reg = <0x1e003000 0x800
-+ 0x1e003800 0x800>;
-+ reg-names = "nfi", "ecc";
-+
-+ clocks = <&nficlock>;
-+ clock-names = "nfi_clk";
-+ };
+++ /dev/null
-From bd0f89de5476ca25e73fae829ba3e1dafae1d90d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= <opensource@vdorst.com>
-Date: Fri, 21 Jun 2019 10:04:05 +0200
-Subject: [PATCH] net: ethernet: mediatek: support net-labels
-
-With this patch, device name can be set within dts file in the same way as dsa
-port can.
-Add: label = "wan"; to GMAC node.
-
-Signed-off-by: René van Dorst <opensource@vdorst.com>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4643,6 +4643,7 @@ static const struct net_device_ops mtk_n
-
- static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
- {
-+ const char *name = of_get_property(np, "label", NULL);
- const __be32 *_id = of_get_property(np, "reg", NULL);
- struct device_node *pcs_np;
- phy_interface_t phy_mode;
-@@ -4840,6 +4841,9 @@ static int mtk_add_mac(struct mtk_eth *e
- register_netdevice_notifier(&mac->device_notifier);
- }
-
-+ if (name)
-+ strlcpy(eth->netdev[id]->name, name, IFNAMSIZ);
-+
- return 0;
-
- free_netdev:
+++ /dev/null
-From ffbb1b37a3e1ce1a5c574a6bd4f5aede8bc468ac Mon Sep 17 00:00:00 2001
-From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Date: Sat, 27 Feb 2021 20:20:07 -0800
-Subject: [PATCH] Revert "net: phy: simplify phy_link_change arguments"
-
-This reverts commit a307593a644443db12888f45eed0dafb5869e2cc.
-
-This brings back the do_carrier flags used by the (hacky) next patch,
-still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c
----
- drivers/net/phy/phy.c | 12 ++++++------
- drivers/net/phy/phy_device.c | 12 +++++++-----
- drivers/net/phy/phylink.c | 3 ++-
- include/linux/phy.h | 2 +-
- 4 files changed, 16 insertions(+), 13 deletions(-)
-
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -71,13 +71,13 @@ static void phy_process_state_change(str
-
- static void phy_link_up(struct phy_device *phydev)
- {
-- phydev->phy_link_change(phydev, true);
-+ phydev->phy_link_change(phydev, true, true);
- phy_led_trigger_change_speed(phydev);
- }
-
--static void phy_link_down(struct phy_device *phydev)
-+static void phy_link_down(struct phy_device *phydev, bool do_carrier)
- {
-- phydev->phy_link_change(phydev, false);
-+ phydev->phy_link_change(phydev, false, do_carrier);
- phy_led_trigger_change_speed(phydev);
- }
-
-@@ -595,7 +595,7 @@ int phy_start_cable_test(struct phy_devi
- goto out;
-
- /* Mark the carrier down until the test is complete */
-- phy_link_down(phydev);
-+ phy_link_down(phydev, true);
-
- netif_testing_on(dev);
- err = phydev->drv->cable_test_start(phydev);
-@@ -666,7 +666,7 @@ int phy_start_cable_test_tdr(struct phy_
- goto out;
-
- /* Mark the carrier down until the test is complete */
-- phy_link_down(phydev);
-+ phy_link_down(phydev, true);
-
- netif_testing_on(dev);
- err = phydev->drv->cable_test_tdr_start(phydev, config);
-@@ -738,7 +738,7 @@ static int phy_check_link_status(struct
- phy_link_up(phydev);
- } else if (!phydev->link && phydev->state != PHY_NOLINK) {
- phydev->state = PHY_NOLINK;
-- phy_link_down(phydev);
-+ phy_link_down(phydev, true);
- }
-
- return 0;
-@@ -1224,7 +1224,7 @@ void phy_state_machine(struct work_struc
- case PHY_HALTED:
- if (phydev->link) {
- phydev->link = 0;
-- phy_link_down(phydev);
-+ phy_link_down(phydev, true);
- }
- do_suspend = true;
- break;
---- a/drivers/net/phy/phy_device.c
-+++ b/drivers/net/phy/phy_device.c
-@@ -1037,14 +1037,16 @@ struct phy_device *phy_find_first(struct
- }
- EXPORT_SYMBOL(phy_find_first);
-
--static void phy_link_change(struct phy_device *phydev, bool up)
-+static void phy_link_change(struct phy_device *phydev, bool up, bool do_carrier)
- {
- struct net_device *netdev = phydev->attached_dev;
-
-- if (up)
-- netif_carrier_on(netdev);
-- else
-- netif_carrier_off(netdev);
-+ if (do_carrier) {
-+ if (up)
-+ netif_carrier_on(netdev);
-+ else
-+ netif_carrier_off(netdev);
-+ }
- phydev->adjust_link(netdev);
- if (phydev->mii_ts && phydev->mii_ts->link_state)
- phydev->mii_ts->link_state(phydev->mii_ts, phydev);
---- a/drivers/net/phy/phylink.c
-+++ b/drivers/net/phy/phylink.c
-@@ -1687,7 +1687,8 @@ bool phylink_expects_phy(struct phylink
- }
- EXPORT_SYMBOL_GPL(phylink_expects_phy);
-
--static void phylink_phy_change(struct phy_device *phydev, bool up)
-+static void phylink_phy_change(struct phy_device *phydev, bool up,
-+ bool do_carrier)
- {
- struct phylink *pl = phydev->phylink;
- bool tx_pause, rx_pause;
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -739,7 +739,7 @@ struct phy_device {
-
- int pma_extable;
-
-- void (*phy_link_change)(struct phy_device *phydev, bool up);
-+ void (*phy_link_change)(struct phy_device *, bool up, bool do_carrier);
- void (*adjust_link)(struct net_device *dev);
-
- #if IS_ENABLED(CONFIG_MACSEC)
+++ /dev/null
-From 0b6eb1e68290243d439ee330ea8d0b239a5aec69 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:38:50 +0100
-Subject: [PATCH 34/53] NET: multi phy support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/phy/phy.c | 9 ++++++---
- include/linux/phy.h | 1 +
- 2 files changed, 7 insertions(+), 3 deletions(-)
-
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -738,7 +738,10 @@ static int phy_check_link_status(struct
- phy_link_up(phydev);
- } else if (!phydev->link && phydev->state != PHY_NOLINK) {
- phydev->state = PHY_NOLINK;
-- phy_link_down(phydev, true);
-+ if (!phydev->no_auto_carrier_off)
-+ phy_link_down(phydev, true);
-+ else
-+ phy_link_down(phydev, false);
- }
-
- return 0;
-@@ -1224,7 +1227,10 @@ void phy_state_machine(struct work_struc
- case PHY_HALTED:
- if (phydev->link) {
- phydev->link = 0;
-- phy_link_down(phydev, true);
-+ if (!phydev->no_auto_carrier_off)
-+ phy_link_down(phydev, true);
-+ else
-+ phy_link_down(phydev, false);
- }
- do_suspend = true;
- break;
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -647,6 +647,7 @@ struct phy_device {
- unsigned downshifted_rate:1;
- unsigned is_on_sfp_module:1;
- unsigned mac_managed_pm:1;
-+ unsigned no_auto_carrier_off:1;
-
- unsigned autoneg:1;
- /* The most recently read link state */
+++ /dev/null
-From d94fc5ce1dc395747c3934ecffcdec0396583755 Mon Sep 17 00:00:00 2001
-From: Nick Hainke <vincent@systemli.org>
-Date: Fri, 26 May 2023 19:46:33 +0200
-Subject: [PATCH] dmaengine: mediatek: add HSDMA support for mt7621
-
-Commit 87dd67f496f7 ("staging: mt7621-dma: remove driver from tree")
-removed the mt7621-dma driver. Move the driver from staging to the
-folder "drivers/dma/mediatek" containing already other mediatek dma
-driver implementations and maintain it downstream in OpenWrt.
-
-This patch will not be sent to upstream linux. It is just a workaround.
-
-Signed-off-by: Nick Hainke <vincent@systemli.org>
----
- drivers/dma/mediatek/Kconfig | 6 ++++++
- drivers/dma/mediatek/Makefile | 1 +
- 2 files changed, 7 insertions(+)
-
---- a/drivers/dma/mediatek/Kconfig
-+++ b/drivers/dma/mediatek/Kconfig
-@@ -36,3 +36,9 @@ config MTK_UART_APDMA
- When SERIAL_8250_MT6577 is enabled, and if you want to use DMA,
- you can enable the config. The DMA engine can only be used
- with MediaTek SoCs.
-+
-+config MTK_HSDMA
-+ tristate "MTK HSDMA support"
-+ depends on RALINK && SOC_MT7621
-+ select DMA_ENGINE
-+ select DMA_VIRTUAL_CHANNELS
---- a/drivers/dma/mediatek/Makefile
-+++ b/drivers/dma/mediatek/Makefile
-@@ -2,3 +2,4 @@
- obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o
- obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
- obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
-+obj-$(CONFIG_MTK_HSDMA) += hsdma-mt7621.o
+++ /dev/null
-From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 19:45:30 +0200
-Subject: [PATCH 26/53] DT: Add documentation for gpio-ralink
-
-Describe gpio-ralink binding.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: devicetree@vger.kernel.org
-Cc: linux-gpio@vger.kernel.org
----
- .../devicetree/bindings/gpio/gpio-ralink.txt | 40 ++++++++++++++++++++
- 1 file changed, 40 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-@@ -0,0 +1,40 @@
-+Ralink SoC GPIO controller bindings
-+
-+Required properties:
-+- compatible:
-+ - "ralink,rt2880-gpio" for Ralink controllers
-+- #gpio-cells : Should be two.
-+ - first cell is the pin number
-+ - second cell is used to specify optional parameters (unused)
-+- gpio-controller : Marks the device node as a GPIO controller
-+- reg : Physical base address and length of the controller's registers
-+- interrupt-parent: phandle to the INTC device node
-+- interrupts : Specify the INTC interrupt number
-+- ngpios : Specify the number of GPIOs
-+- ralink,register-map : The register layout depends on the GPIO bank and actual
-+ SoC type. Register offsets need to be in this order.
-+ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
-+
-+Optional properties:
-+- ralink,gpio-base : Specify the GPIO chips base number
-+
-+Example:
-+
-+ gpio0: gpio@600 {
-+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
-+
-+ #gpio-cells = <2>;
-+ gpio-controller;
-+
-+ reg = <0x600 0x34>;
-+
-+ interrupt-parent = <&intc>;
-+ interrupts = <6>;
-+
-+ ngpios = <24>;
-+ ralink,gpio-base = <0>;
-+ ralink,register-map = [ 00 04 08 0c
-+ 20 24 28 2c
-+ 30 34 ];
-+
-+ };
+++ /dev/null
-From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 4 Aug 2014 20:36:29 +0200
-Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC
-
-Add gpio driver for Ralink SoC. This driver makes the gpio core on
-RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-mips@linux-mips.org
-Cc: linux-gpio@vger.kernel.org
----
- arch/mips/include/asm/mach-ralink/gpio.h | 24 ++
- drivers/gpio/Kconfig | 6 +
- drivers/gpio/Makefile | 1 +
- drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++
- 4 files changed, 386 insertions(+)
- create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
- create mode 100644 drivers/gpio/gpio-ralink.c
-
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/gpio.h
-@@ -0,0 +1,24 @@
-+/*
-+ * Ralink SoC GPIO API support
-+ *
-+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ */
-+
-+#ifndef __ASM_MACH_RALINK_GPIO_H
-+#define __ASM_MACH_RALINK_GPIO_H
-+
-+#define ARCH_NR_GPIOS 128
-+#include <asm-generic/gpio.h>
-+
-+#define gpio_get_value __gpio_get_value
-+#define gpio_set_value __gpio_set_value
-+#define gpio_cansleep __gpio_cansleep
-+#define gpio_to_irq __gpio_to_irq
-+
-+#endif /* __ASM_MACH_RALINK_GPIO_H */
---- a/drivers/gpio/Kconfig
-+++ b/drivers/gpio/Kconfig
-@@ -585,6 +585,12 @@ config GPIO_SNPS_CREG
- where only several fields in register belong to GPIO lines and
- each GPIO line owns a field with different length and on/off value.
-
-+config GPIO_RALINK
-+ bool "Ralink GPIO Support"
-+ depends on RALINK
-+ help
-+ Say yes here to support the Ralink SoC GPIO device
-+
- config GPIO_SPEAR_SPICS
- bool "ST SPEAr13xx SPI Chip Select as GPIO support"
- depends on PLAT_SPEAR
---- a/drivers/gpio/Makefile
-+++ b/drivers/gpio/Makefile
-@@ -122,6 +122,7 @@ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisos
- obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
- obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
- obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
-+obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
- obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o
- obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
- obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
---- /dev/null
-+++ b/drivers/gpio/gpio-ralink.c
-@@ -0,0 +1,341 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/gpio.h>
-+#include <linux/spinlock.h>
-+#include <linux/platform_device.h>
-+#include <linux/of_irq.h>
-+#include <linux/irqdomain.h>
-+#include <linux/interrupt.h>
-+
-+enum ralink_gpio_reg {
-+ GPIO_REG_INT = 0,
-+ GPIO_REG_EDGE,
-+ GPIO_REG_RENA,
-+ GPIO_REG_FENA,
-+ GPIO_REG_DATA,
-+ GPIO_REG_DIR,
-+ GPIO_REG_POL,
-+ GPIO_REG_SET,
-+ GPIO_REG_RESET,
-+ GPIO_REG_TOGGLE,
-+ GPIO_REG_MAX
-+};
-+
-+struct ralink_gpio_chip {
-+ struct gpio_chip chip;
-+ u8 regs[GPIO_REG_MAX];
-+
-+ spinlock_t lock;
-+ void __iomem *membase;
-+ struct irq_domain *domain;
-+ int irq;
-+
-+ u32 rising;
-+ u32 falling;
-+};
-+
-+#define MAP_MAX 4
-+static struct irq_domain *irq_map[MAP_MAX];
-+static int irq_map_count;
-+static atomic_t irq_refcount = ATOMIC_INIT(0);
-+
-+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
-+{
-+ struct ralink_gpio_chip *rg;
-+
-+ rg = container_of(chip, struct ralink_gpio_chip, chip);
-+
-+ return rg;
-+}
-+
-+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
-+{
-+ iowrite32(val, rg->membase + rg->regs[reg]);
-+}
-+
-+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
-+{
-+ return ioread32(rg->membase + rg->regs[reg]);
-+}
-+
-+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+ rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
-+}
-+
-+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+ return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
-+}
-+
-+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
-+ t &= ~BIT(offset);
-+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int ralink_gpio_direction_output(struct gpio_chip *chip,
-+ unsigned offset, int value)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+ unsigned long flags;
-+ u32 t;
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ ralink_gpio_set(chip, offset, value);
-+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
-+ t |= BIT(offset);
-+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
-+{
-+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
-+
-+ if (rg->irq < 1)
-+ return -1;
-+
-+ return irq_create_mapping(rg->domain, pin);
-+}
-+
-+static void ralink_gpio_irq_handler(struct irq_desc *desc)
-+{
-+ int i;
-+
-+ for (i = 0; i < irq_map_count; i++) {
-+ struct irq_domain *domain = irq_map[i];
-+ struct ralink_gpio_chip *rg;
-+ unsigned long pending;
-+ int bit;
-+
-+ rg = (struct ralink_gpio_chip *) domain->host_data;
-+ pending = rt_gpio_r32(rg, GPIO_REG_INT);
-+
-+ for_each_set_bit(bit, &pending, rg->chip.ngpio) {
-+ u32 map = irq_find_mapping(domain, bit);
-+ generic_handle_irq(map);
-+ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
-+ }
-+ }
-+}
-+
-+static void ralink_gpio_irq_unmask(struct irq_data *d)
-+{
-+ struct ralink_gpio_chip *rg;
-+ unsigned long flags;
-+ u32 rise, fall;
-+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
-+ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
-+ rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static void ralink_gpio_irq_mask(struct irq_data *d)
-+{
-+ struct ralink_gpio_chip *rg;
-+ unsigned long flags;
-+ u32 rise, fall;
-+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
-+ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
-+
-+ spin_lock_irqsave(&rg->lock, flags);
-+ rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
-+ rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
-+ spin_unlock_irqrestore(&rg->lock, flags);
-+}
-+
-+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
-+{
-+ struct ralink_gpio_chip *rg;
-+ u32 mask = BIT(d->hwirq);
-+
-+ rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+
-+ if (type == IRQ_TYPE_PROBE) {
-+ if ((rg->rising | rg->falling) & mask)
-+ return 0;
-+
-+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-+ }
-+
-+ if (type & IRQ_TYPE_EDGE_RISING)
-+ rg->rising |= mask;
-+ else
-+ rg->rising &= ~mask;
-+
-+ if (type & IRQ_TYPE_EDGE_FALLING)
-+ rg->falling |= mask;
-+ else
-+ rg->falling &= ~mask;
-+
-+ return 0;
-+}
-+
-+static struct irq_chip ralink_gpio_irq_chip = {
-+ .name = "GPIO",
-+ .irq_unmask = ralink_gpio_irq_unmask,
-+ .irq_mask = ralink_gpio_irq_mask,
-+ .irq_mask_ack = ralink_gpio_irq_mask,
-+ .irq_set_type = ralink_gpio_irq_type,
-+};
-+
-+static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
-+{
-+ irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
-+ irq_set_handler_data(irq, d);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops irq_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = gpio_map,
-+};
-+
-+static void ralink_gpio_irq_init(struct device_node *np,
-+ struct ralink_gpio_chip *rg)
-+{
-+ if (irq_map_count >= MAP_MAX)
-+ return;
-+
-+ rg->irq = irq_of_parse_and_map(np, 0);
-+ if (!rg->irq)
-+ return;
-+
-+ rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
-+ &irq_domain_ops, rg);
-+ if (!rg->domain) {
-+ dev_err(rg->chip.parent, "irq_domain_add_linear failed\n");
-+ return;
-+ }
-+
-+ irq_map[irq_map_count++] = rg->domain;
-+
-+ rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
-+ rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
-+
-+ if (!atomic_read(&irq_refcount))
-+ irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
-+ atomic_inc(&irq_refcount);
-+
-+ dev_info(rg->chip.parent, "registering %d irq handlers\n", rg->chip.ngpio);
-+}
-+
-+static int ralink_gpio_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ struct ralink_gpio_chip *rg;
-+ const __be32 *ngpio, *gpiobase;
-+
-+ if (!res) {
-+ dev_err(&pdev->dev, "failed to find resource\n");
-+ return -ENOMEM;
-+ }
-+
-+ rg = devm_kzalloc(&pdev->dev,
-+ sizeof(struct ralink_gpio_chip), GFP_KERNEL);
-+ if (!rg)
-+ return -ENOMEM;
-+
-+ rg->membase = devm_ioremap_resource(&pdev->dev, res);
-+ if (!rg->membase) {
-+ dev_err(&pdev->dev, "cannot remap I/O memory region\n");
-+ return -ENOMEM;
-+ }
-+
-+ if (of_property_read_u8_array(np, "ralink,register-map",
-+ rg->regs, GPIO_REG_MAX)) {
-+ dev_err(&pdev->dev, "failed to read register definition\n");
-+ return -EINVAL;
-+ }
-+
-+ ngpio = of_get_property(np, "ngpios", NULL);
-+ if (!ngpio) {
-+ dev_err(&pdev->dev, "failed to read number of pins\n");
-+ return -EINVAL;
-+ }
-+
-+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
-+ if (gpiobase)
-+ rg->chip.base = be32_to_cpu(*gpiobase);
-+ else
-+ rg->chip.base = -1;
-+
-+ spin_lock_init(&rg->lock);
-+
-+ rg->chip.parent = &pdev->dev;
-+ rg->chip.label = dev_name(&pdev->dev);
-+ rg->chip.of_node = np;
-+ rg->chip.ngpio = be32_to_cpu(*ngpio);
-+ rg->chip.direction_input = ralink_gpio_direction_input;
-+ rg->chip.direction_output = ralink_gpio_direction_output;
-+ rg->chip.get = ralink_gpio_get;
-+ rg->chip.set = ralink_gpio_set;
-+ rg->chip.request = gpiochip_generic_request;
-+ rg->chip.to_irq = ralink_gpio_to_irq;
-+ rg->chip.free = gpiochip_generic_free;
-+
-+ /* set polarity to low for all lines */
-+ rt_gpio_w32(rg, GPIO_REG_POL, 0);
-+
-+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
-+
-+ ralink_gpio_irq_init(np, rg);
-+
-+ return gpiochip_add(&rg->chip);
-+}
-+
-+static const struct of_device_id ralink_gpio_match[] = {
-+ { .compatible = "ralink,rt2880-gpio" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, ralink_gpio_match);
-+
-+static struct platform_driver ralink_gpio_driver = {
-+ .probe = ralink_gpio_probe,
-+ .driver = {
-+ .name = "rt2880_gpio",
-+ .owner = THIS_MODULE,
-+ .of_match_table = ralink_gpio_match,
-+ },
-+};
-+
-+static int __init ralink_gpio_init(void)
-+{
-+ return platform_driver_register(&ralink_gpio_driver);
-+}
-+
-+subsys_initcall(ralink_gpio_init);
+++ /dev/null
-From 57fa7f2f4ef6f78ce1d30509c0d111aa3791b524 Mon Sep 17 00:00:00 2001
-From: Daniel Santos <daniel.santos@pobox.com>
-Date: Sun, 4 Nov 2018 20:24:32 -0600
-Subject: gpio-ralink: Add support for GPIO as interrupt-controller
-
-Signed-off-by: Daniel Santos <daniel.santos@pobox.com>
----
- Documentation/devicetree/bindings/gpio/gpio-ralink.txt | 6 ++++++
- drivers/gpio/gpio-ralink.c | 2 +-
- 2 files changed, 7 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
-@@ -17,6 +17,9 @@ Required properties:
-
- Optional properties:
- - ralink,gpio-base : Specify the GPIO chips base number
-+- interrupt-controller : marks this as an interrupt controller
-+- #interrupt-cells : a standard two-cell interrupt flag, see
-+ interrupt-controller/interrupts.txt
-
- Example:
-
-@@ -28,6 +31,9 @@ Example:
-
- reg = <0x600 0x34>;
-
-+ interrupt-controller;
-+ #interrupt-cells = <2>;
-+
- interrupt-parent = <&intc>;
- interrupts = <6>;
-
---- a/drivers/gpio/gpio-ralink.c
-+++ b/drivers/gpio/gpio-ralink.c
-@@ -220,7 +220,7 @@ static int gpio_map(struct irq_domain *d
- }
-
- static const struct irq_domain_ops irq_domain_ops = {
-- .xlate = irq_domain_xlate_onecell,
-+ .xlate = irq_domain_xlate_twocell,
- .map = gpio_map,
- };
-
+++ /dev/null
-From: AngeloGioacchino Del Regno
- <angelogioacchino.delregno@somainline.org>
-To: linus.walleij@linaro.org
-Cc: linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org,
- marijn.suijten@somainline.org, martin.botka@somainline.org,
- phone-devel@vger.kernel.org, linux-gpio@vger.kernel.org,
- devicetree@vger.kernel.org, robh+dt@kernel.org,
- AngeloGioacchino Del Regno
- <angelogioacchino.delregno@somainline.org>
-Subject: [PATCH v5 1/2] pinctrl: Add driver for Awinic AW9523/B I2C GPIO
- Expander
-Date: Mon, 25 Jan 2021 19:22:18 +0100
-
-The Awinic AW9523(B) is a multi-function I2C gpio expander in a
-TQFN-24L package, featuring PWM (max 37mA per pin, or total max
-power 3.2Watts) for LED driving capability.
-
-It has two ports with 8 pins per port (for a total of 16 pins),
-configurable as either PWM with 1/256 stepping or GPIO input/output,
-1.8V logic input; each GPIO can be configured as input or output
-independently from each other.
-
-This IC also has an internal interrupt controller, which is capable
-of generating an interrupt for each GPIO, depending on the
-configuration, and will raise an interrupt on the INTN pin to
-advertise this to an external interrupt controller.
-
-Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
----
- drivers/pinctrl/Kconfig | 17 +
- drivers/pinctrl/Makefile | 1 +
- drivers/pinctrl/pinctrl-aw9523.c | 1122 ++++++++++++++++++++++++++++++
- 3 files changed, 1140 insertions(+)
- create mode 100644 drivers/pinctrl/pinctrl-aw9523.c
-
---- a/drivers/pinctrl/Kconfig
-+++ b/drivers/pinctrl/Kconfig
-@@ -113,6 +113,24 @@ config PINCTRL_AT91PIO4
- Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4
- controller available on sama5d2 SoC.
-
-+config PINCTRL_AW9523
-+ bool "Awinic AW9523/AW9523B I2C GPIO expander pinctrl driver"
-+ depends on OF && I2C
-+ select PINMUX
-+ select PINCONF
-+ select GENERIC_PINCONF
-+ select GPIOLIB
-+ select GPIOLIB_IRQCHIP
-+ select REGMAP
-+ select REGMAP_I2C
-+ help
-+ The Awinic AW9523/AW9523B is a multi-function I2C GPIO
-+ expander with PWM functionality. This driver bundles a
-+ pinctrl driver to select the function muxing and a GPIO
-+ driver to handle GPIO, when the GPIO function is selected.
-+
-+ Say yes to enable pinctrl and GPIO support for the AW9523(B).
-+
- config PINCTRL_AXP209
- tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
- depends on MFD_AXP20X
---- a/drivers/pinctrl/Makefile
-+++ b/drivers/pinctrl/Makefile
-@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl
- obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
- obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
- obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
-+obj-$(CONFIG_PINCTRL_AW9523) += pinctrl-aw9523.o
- obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o
- obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o
- obj-$(CONFIG_PINCTRL_CY8C95X0) += pinctrl-cy8c95x0.o
+++ /dev/null
-From: Shiji Yang <yangshiji66@outlook.com>
-Date: Wed, 26 Jul 2023 01:32:55 +0800
-Subject: [PATCH] pinctrl: mtmips: support requesting different functions for
- same group
-
-Sometimes pinctrl consumers may request different functions for the
-same pin group in different situations. This patch can help to reset
-the group function flag when requesting a different function.
-
-Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
----
- drivers/pinctrl/ralink/pinctrl-ralink.c | 21 +++++++++++++++++----
- 1 file changed, 17 insertions(+), 4 deletions(-)
-
---- a/drivers/pinctrl/ralink/pinctrl-ralink.c
-+++ b/drivers/pinctrl/ralink/pinctrl-ralink.c
-@@ -123,11 +123,24 @@ static int ralink_pmx_group_enable(struc
- int i;
- int shift;
-
-- /* dont allow double use */
-+ /*
-+ * for the same pin group, if request a different function,
-+ * then clear the group function flag and continue, else exit.
-+ */
- if (p->groups[group].enabled) {
-- dev_err(p->dev, "%s is already enabled\n",
-- p->groups[group].name);
-- return 0;
-+ for (i = 0; i < p->groups[group].func_count; i++) {
-+ if (p->groups[group].func[i].enabled == 1) {
-+ if (!strcmp(p->func[func]->name,
-+ p->groups[group].func[i].name))
-+ return 0;
-+ p->groups[group].func[i].enabled = 0;
-+ break;
-+ }
-+ }
-+
-+ /* exit if request the "gpio" function again */
-+ if (i == p->groups[group].func_count && func == 0)
-+ return 0;
- }
-
- p->groups[group].enabled = 1;
+++ /dev/null
-From 975e76214cd2516eb6cfff4c3eec581872645e88 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 19 Sep 2013 01:50:59 +0200
-Subject: [PATCH 31/53] uvc: add iPassion iP2970 support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/media/usb/uvc/uvc_driver.c | 12 +++
- drivers/media/usb/uvc/uvc_status.c | 2 +
- drivers/media/usb/uvc/uvc_video.c | 147 ++++++++++++++++++++++++++++++++++++
- drivers/media/usb/uvc/uvcvideo.h | 5 +-
- 4 files changed, 165 insertions(+), 1 deletion(-)
-
---- a/drivers/media/usb/uvc/uvc_driver.c
-+++ b/drivers/media/usb/uvc/uvc_driver.c
-@@ -2981,6 +2981,18 @@ static const struct usb_device_id uvc_id
- .bInterfaceSubClass = 1,
- .bInterfaceProtocol = 0,
- .driver_info = UVC_INFO_META(V4L2_META_FMT_D4XX) },
-+ /* iPassion iP2970 */
-+ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE
-+ | USB_DEVICE_ID_MATCH_INT_INFO,
-+ .idVendor = 0x1B3B,
-+ .idProduct = 0x2970,
-+ .bInterfaceClass = USB_CLASS_VIDEO,
-+ .bInterfaceSubClass = 1,
-+ .bInterfaceProtocol = 0,
-+ .driver_info = UVC_QUIRK_PROBE_MINMAX
-+ | UVC_QUIRK_STREAM_NO_FID
-+ | UVC_QUIRK_MOTION
-+ | UVC_QUIRK_SINGLE_ISO },
- /* Generic USB Video Class */
- { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_UNDEFINED) },
- { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) },
---- a/drivers/media/usb/uvc/uvc_status.c
-+++ b/drivers/media/usb/uvc/uvc_status.c
-@@ -223,6 +223,7 @@ static void uvc_status_complete(struct u
- if (uvc_event_control(urb, status, len))
- /* The URB will be resubmitted in work context. */
- return;
-+ dev->motion = 1;
- break;
- }
-
-@@ -271,6 +272,7 @@ int uvc_status_init(struct uvc_device *d
- }
-
- pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress);
-+ dev->motion = 0;
-
- /*
- * For high-speed interrupt endpoints, the bInterval value is used as
---- a/drivers/media/usb/uvc/uvc_video.c
-+++ b/drivers/media/usb/uvc/uvc_video.c
-@@ -19,6 +19,11 @@
- #include <linux/wait.h>
- #include <linux/atomic.h>
- #include <asm/unaligned.h>
-+#include <linux/skbuff.h>
-+#include <linux/kobject.h>
-+#include <linux/netlink.h>
-+#include <linux/kobject.h>
-+#include <linux/workqueue.h>
-
- #include <media/v4l2-common.h>
-
-@@ -1231,9 +1236,149 @@ static void uvc_video_decode_data(struct
- uvc_urb->async_operations++;
- }
-
-+struct bh_priv {
-+ unsigned long seen;
-+};
-+
-+struct bh_event {
-+ const char *name;
-+ struct sk_buff *skb;
-+ struct work_struct work;
-+};
-+
-+#define BH_ERR(fmt, args...) printk(KERN_ERR "%s: " fmt, "webcam", ##args )
-+#define BH_DBG(fmt, args...) do {} while (0)
-+#define BH_SKB_SIZE 2048
-+
-+extern u64 uevent_next_seqnum(void);
-+static int seen = 0;
-+
-+static int bh_event_add_var(struct bh_event *event, int argv,
-+ const char *format, ...)
-+{
-+ static char buf[128];
-+ char *s;
-+ va_list args;
-+ int len;
-+
-+ if (argv)
-+ return 0;
-+
-+ va_start(args, format);
-+ len = vsnprintf(buf, sizeof(buf), format, args);
-+ va_end(args);
-+
-+ if (len >= sizeof(buf)) {
-+ BH_ERR("buffer size too small\n");
-+ WARN_ON(1);
-+ return -ENOMEM;
-+ }
-+
-+ s = skb_put(event->skb, len + 1);
-+ strcpy(s, buf);
-+
-+ BH_DBG("added variable '%s'\n", s);
-+
-+ return 0;
-+}
-+
-+static int motion_hotplug_fill_event(struct bh_event *event)
-+{
-+ int s = jiffies;
-+ int ret;
-+
-+ if (!seen)
-+ seen = jiffies;
-+
-+ ret = bh_event_add_var(event, 0, "HOME=%s", "/");
-+ if (ret)
-+ return ret;
-+
-+ ret = bh_event_add_var(event, 0, "PATH=%s",
-+ "/sbin:/bin:/usr/sbin:/usr/bin");
-+ if (ret)
-+ return ret;
-+
-+ ret = bh_event_add_var(event, 0, "SUBSYSTEM=usb");
-+ if (ret)
-+ return ret;
-+
-+ ret = bh_event_add_var(event, 0, "ACTION=motion");
-+ if (ret)
-+ return ret;
-+
-+ ret = bh_event_add_var(event, 0, "SEEN=%d", s - seen);
-+ if (ret)
-+ return ret;
-+ seen = s;
-+
-+ ret = bh_event_add_var(event, 0, "SEQNUM=%llu", uevent_next_seqnum());
-+
-+ return ret;
-+}
-+
-+static void motion_hotplug_work(struct work_struct *work)
-+{
-+ struct bh_event *event = container_of(work, struct bh_event, work);
-+ int ret = 0;
-+
-+ event->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL);
-+ if (!event->skb)
-+ goto out_free_event;
-+
-+ ret = bh_event_add_var(event, 0, "%s@", "add");
-+ if (ret)
-+ goto out_free_skb;
-+
-+ ret = motion_hotplug_fill_event(event);
-+ if (ret)
-+ goto out_free_skb;
-+
-+ NETLINK_CB(event->skb).dst_group = 1;
-+ broadcast_uevent(event->skb, 0, 1, GFP_KERNEL);
-+
-+out_free_skb:
-+ if (ret) {
-+ BH_ERR("work error %d\n", ret);
-+ kfree_skb(event->skb);
-+ }
-+out_free_event:
-+ kfree(event);
-+}
-+
-+static int motion_hotplug_create_event(void)
-+{
-+ struct bh_event *event;
-+
-+ event = kzalloc(sizeof(*event), GFP_KERNEL);
-+ if (!event)
-+ return -ENOMEM;
-+
-+ event->name = "motion";
-+
-+ INIT_WORK(&event->work, (void *)(void *)motion_hotplug_work);
-+ schedule_work(&event->work);
-+
-+ return 0;
-+}
-+
-+#define MOTION_FLAG_OFFSET 4
- static void uvc_video_decode_end(struct uvc_streaming *stream,
- struct uvc_buffer *buf, const u8 *data, int len)
- {
-+ if ((stream->dev->quirks & UVC_QUIRK_MOTION) &&
-+ (data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) {
-+ u8 *mem;
-+ buf->state = UVC_BUF_STATE_READY;
-+ mem = (u8 *) (buf->mem + MOTION_FLAG_OFFSET);
-+ if ( stream->dev->motion ) {
-+ stream->dev->motion = 0;
-+ motion_hotplug_create_event();
-+ } else {
-+ *mem &= 0x7f;
-+ }
-+ }
-+
- /* Mark the buffer as done if the EOF marker is set. */
- if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) {
- uvc_dbg(stream->dev, FRAME, "Frame complete (EOF found)\n");
-@@ -1815,6 +1960,8 @@ static int uvc_init_video_isoc(struct uv
- if (npackets == 0)
- return -ENOMEM;
-
-+ if (stream->dev->quirks & UVC_QUIRK_SINGLE_ISO)
-+ npackets = 1;
- size = npackets * psize;
-
- for_each_uvc_urb(uvc_urb, stream) {
---- a/drivers/media/usb/uvc/uvcvideo.h
-+++ b/drivers/media/usb/uvc/uvcvideo.h
-@@ -75,6 +75,8 @@
- #define UVC_QUIRK_FORCE_Y8 0x00000800
- #define UVC_QUIRK_FORCE_BPP 0x00001000
- #define UVC_QUIRK_WAKE_AUTOSUSPEND 0x00002000
-+#define UVC_QUIRK_MOTION 0x00004000
-+#define UVC_QUIRK_SINGLE_ISO 0x00008000
-
- /* Format flags */
- #define UVC_FMT_FLAG_COMPRESSED 0x00000001
-@@ -562,6 +564,7 @@ struct uvc_device {
- u8 *status;
- struct input_dev *input;
- char input_phys[64];
-+ int motion;
-
- struct uvc_ctrl_work {
- struct work_struct work;
+++ /dev/null
-From da6015e7f19d749f135f7ac55c4ec47b06faa868 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 9 Aug 2013 20:12:59 +0200
-Subject: [PATCH 41/53] DT: Add documentation for spi-rt2880
-
-Describe the SPI master found on the MIPS based Ralink RT2880 SoC.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- .../devicetree/bindings/spi/spi-rt2880.txt | 28 ++++++++++++++++++++
- 1 file changed, 28 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt
-@@ -0,0 +1,28 @@
-+Ralink SoC RT2880 SPI master controller.
-+
-+This SPI controller is found on most wireless SoCs made by ralink.
-+
-+Required properties:
-+- compatible : "ralink,rt2880-spi"
-+- reg : The register base for the controller.
-+- #address-cells : <1>, as required by generic SPI binding.
-+- #size-cells : <0>, also as required by generic SPI binding.
-+
-+Child nodes as per the generic SPI binding.
-+
-+Example:
-+
-+ spi@b00 {
-+ compatible = "ralink,rt2880-spi";
-+ reg = <0xb00 0x100>;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ m25p80@0 {
-+ compatible = "m25p80";
-+ reg = <0>;
-+ spi-max-frequency = <10000000>;
-+ };
-+ };
-+
+++ /dev/null
-From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 11:15:12 +0100
-Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver
-
-Add the driver needed to make SPI work on Ralink SoC.
-
-Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
-Acked-by: John Crispin <blogic@openwrt.org>
----
- drivers/spi/Kconfig | 6 +
- drivers/spi/Makefile | 1 +
- drivers/spi/spi-rt2880.c | 530 ++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 537 insertions(+)
- create mode 100644 drivers/spi/spi-rt2880.c
-
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -823,6 +823,12 @@ config SPI_QCOM_GENI
- This driver can also be built as a module. If so, the module
- will be called spi-geni-qcom.
-
-+config SPI_RT2880
-+ tristate "Ralink RT288x SPI Controller"
-+ depends on RALINK
-+ help
-+ This selects a driver for the Ralink RT288x/RT305x SPI Controller.
-+
- config SPI_S3C24XX
- tristate "Samsung S3C24XX series SPI"
- depends on ARCH_S3C24XX
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
- obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
- obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
- obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
-+obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o
- obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
- spi-s3c24xx-hw-y := spi-s3c24xx.o
- obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o
---- /dev/null
-+++ b/drivers/spi/spi-rt2880.c
-@@ -0,0 +1,535 @@
-+/*
-+ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
-+ *
-+ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
-+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
-+ *
-+ * Some parts are based on spi-orion.c:
-+ * Author: Shadi Ammouri <shadi@marvell.com>
-+ * Copyright (C) 2007-2008 Marvell Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/reset.h>
-+#include <linux/spi/spi.h>
-+#include <linux/platform_device.h>
-+#include <linux/gpio.h>
-+
-+#define DRIVER_NAME "spi-rt2880"
-+
-+#define RAMIPS_SPI_STAT 0x00
-+#define RAMIPS_SPI_CFG 0x10
-+#define RAMIPS_SPI_CTL 0x14
-+#define RAMIPS_SPI_DATA 0x20
-+#define RAMIPS_SPI_ADDR 0x24
-+#define RAMIPS_SPI_BS 0x28
-+#define RAMIPS_SPI_USER 0x2C
-+#define RAMIPS_SPI_TXFIFO 0x30
-+#define RAMIPS_SPI_RXFIFO 0x34
-+#define RAMIPS_SPI_FIFO_STAT 0x38
-+#define RAMIPS_SPI_MODE 0x3C
-+#define RAMIPS_SPI_DEV_OFFSET 0x40
-+#define RAMIPS_SPI_DMA 0x80
-+#define RAMIPS_SPI_DMASTAT 0x84
-+#define RAMIPS_SPI_ARBITER 0xF0
-+
-+/* SPISTAT register bit field */
-+#define SPISTAT_BUSY BIT(0)
-+
-+/* SPICFG register bit field */
-+#define SPICFG_ADDRMODE BIT(12)
-+#define SPICFG_RXENVDIS BIT(11)
-+#define SPICFG_RXCAP BIT(10)
-+#define SPICFG_SPIENMODE BIT(9)
-+#define SPICFG_MSBFIRST BIT(8)
-+#define SPICFG_SPICLKPOL BIT(6)
-+#define SPICFG_RXCLKEDGE_FALLING BIT(5)
-+#define SPICFG_TXCLKEDGE_FALLING BIT(4)
-+#define SPICFG_HIZSPI BIT(3)
-+#define SPICFG_SPICLK_PRESCALE_MASK 0x7
-+#define SPICFG_SPICLK_DIV2 0
-+#define SPICFG_SPICLK_DIV4 1
-+#define SPICFG_SPICLK_DIV8 2
-+#define SPICFG_SPICLK_DIV16 3
-+#define SPICFG_SPICLK_DIV32 4
-+#define SPICFG_SPICLK_DIV64 5
-+#define SPICFG_SPICLK_DIV128 6
-+#define SPICFG_SPICLK_DISABLE 7
-+
-+/* SPICTL register bit field */
-+#define SPICTL_START BIT(4)
-+#define SPICTL_HIZSDO BIT(3)
-+#define SPICTL_STARTWR BIT(2)
-+#define SPICTL_STARTRD BIT(1)
-+#define SPICTL_SPIENA BIT(0)
-+
-+/* SPIUSER register bit field */
-+#define SPIUSER_USERMODE BIT(21)
-+#define SPIUSER_INSTR_PHASE BIT(20)
-+#define SPIUSER_ADDR_PHASE_MASK 0x7
-+#define SPIUSER_ADDR_PHASE_OFFSET 17
-+#define SPIUSER_MODE_PHASE BIT(16)
-+#define SPIUSER_DUMMY_PHASE_MASK 0x3
-+#define SPIUSER_DUMMY_PHASE_OFFSET 14
-+#define SPIUSER_DATA_PHASE_MASK 0x3
-+#define SPIUSER_DATA_PHASE_OFFSET 12
-+#define SPIUSER_DATA_READ (BIT(0) << SPIUSER_DATA_PHASE_OFFSET)
-+#define SPIUSER_DATA_WRITE (BIT(1) << SPIUSER_DATA_PHASE_OFFSET)
-+#define SPIUSER_ADDR_TYPE_OFFSET 9
-+#define SPIUSER_MODE_TYPE_OFFSET 6
-+#define SPIUSER_DUMMY_TYPE_OFFSET 3
-+#define SPIUSER_DATA_TYPE_OFFSET 0
-+#define SPIUSER_TRANSFER_MASK 0x7
-+#define SPIUSER_TRANSFER_SINGLE BIT(0)
-+#define SPIUSER_TRANSFER_DUAL BIT(1)
-+#define SPIUSER_TRANSFER_QUAD BIT(2)
-+
-+#define SPIUSER_TRANSFER_TYPE(type) ( \
-+ (type << SPIUSER_ADDR_TYPE_OFFSET) | \
-+ (type << SPIUSER_MODE_TYPE_OFFSET) | \
-+ (type << SPIUSER_DUMMY_TYPE_OFFSET) | \
-+ (type << SPIUSER_DATA_TYPE_OFFSET) \
-+)
-+
-+/* SPIFIFOSTAT register bit field */
-+#define SPIFIFOSTAT_TXEMPTY BIT(19)
-+#define SPIFIFOSTAT_RXEMPTY BIT(18)
-+#define SPIFIFOSTAT_TXFULL BIT(17)
-+#define SPIFIFOSTAT_RXFULL BIT(16)
-+#define SPIFIFOSTAT_FIFO_MASK 0xff
-+#define SPIFIFOSTAT_TX_OFFSET 8
-+#define SPIFIFOSTAT_RX_OFFSET 0
-+
-+#define SPI_FIFO_DEPTH 16
-+
-+/* SPIMODE register bit field */
-+#define SPIMODE_MODE_OFFSET 24
-+#define SPIMODE_DUMMY_OFFSET 0
-+
-+/* SPIARB register bit field */
-+#define SPICTL_ARB_EN BIT(31)
-+#define SPICTL_CSCTL1 BIT(16)
-+#define SPI1_POR BIT(1)
-+#define SPI0_POR BIT(0)
-+
-+#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \
-+ SPI_CS_HIGH)
-+
-+static atomic_t hw_reset_count = ATOMIC_INIT(0);
-+
-+struct rt2880_spi {
-+ struct spi_master *master;
-+ void __iomem *base;
-+ u32 speed;
-+ u16 wait_loops;
-+ u16 mode;
-+ struct clk *clk;
-+};
-+
-+static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
-+{
-+ return spi_master_get_devdata(spi->master);
-+}
-+
-+static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
-+{
-+ return ioread32(rs->base + reg);
-+}
-+
-+static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,
-+ const u32 val)
-+{
-+ iowrite32(val, rs->base + reg);
-+}
-+
-+static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
-+{
-+ void __iomem *addr = rs->base + reg;
-+
-+ iowrite32((ioread32(addr) | mask), addr);
-+}
-+
-+static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
-+{
-+ void __iomem *addr = rs->base + reg;
-+
-+ iowrite32((ioread32(addr) & ~mask), addr);
-+}
-+
-+static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed)
-+{
-+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
-+ u32 rate;
-+ u32 prescale;
-+
-+ /*
-+ * the supported rates are: 2, 4, 8, ... 128
-+ * round up as we look for equal or less speed
-+ */
-+ rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed);
-+ rate = roundup_pow_of_two(rate);
-+
-+ /* Convert the rate to SPI clock divisor value. */
-+ prescale = ilog2(rate / 2);
-+
-+ /* some tolerance. double and add 100 */
-+ rs->wait_loops = (8 * HZ * loops_per_jiffy) /
-+ (clk_get_rate(rs->clk) / rate);
-+ rs->wait_loops = (rs->wait_loops << 1) + 100;
-+ rs->speed = speed;
-+
-+ dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n",
-+ clk_get_rate(rs->clk) / rate, speed, rate, prescale,
-+ rs->wait_loops);
-+
-+ return prescale;
-+}
-+
-+static u32 get_arbiter_offset(struct spi_master *master)
-+{
-+ u32 offset;
-+
-+ offset = RAMIPS_SPI_ARBITER;
-+ if (master->bus_num == 1)
-+ offset -= RAMIPS_SPI_DEV_OFFSET;
-+
-+ return offset;
-+}
-+
-+static void rt2880_spi_set_cs(struct spi_device *spi, bool enable)
-+{
-+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
-+
-+ if (enable)
-+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
-+ else
-+ rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
-+}
-+
-+static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)
-+{
-+ int loop = rs->wait_loops * len;
-+
-+ while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)
-+ cpu_relax();
-+
-+ if (loop)
-+ return 0;
-+
-+ return -ETIMEDOUT;
-+}
-+
-+static void rt2880_dump_reg(struct spi_master *master)
-+{
-+ struct rt2880_spi *rs = spi_master_get_devdata(master);
-+
-+ dev_dbg(&master->dev, "stat: %08x, cfg: %08x, ctl: %08x, " \
-+ "data: %08x, arb: %08x\n",
-+ rt2880_spi_read(rs, RAMIPS_SPI_STAT),
-+ rt2880_spi_read(rs, RAMIPS_SPI_CFG),
-+ rt2880_spi_read(rs, RAMIPS_SPI_CTL),
-+ rt2880_spi_read(rs, RAMIPS_SPI_DATA),
-+ rt2880_spi_read(rs, get_arbiter_offset(master)));
-+}
-+
-+static int rt2880_spi_transfer_one(struct spi_master *master,
-+ struct spi_device *spi, struct spi_transfer *xfer)
-+{
-+ struct rt2880_spi *rs = spi_master_get_devdata(master);
-+ unsigned len;
-+ const u8 *tx = xfer->tx_buf;
-+ u8 *rx = xfer->rx_buf;
-+ int err = 0;
-+
-+ /* change clock speed */
-+ if (unlikely(rs->speed != xfer->speed_hz)) {
-+ u32 reg;
-+ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
-+ reg &= ~SPICFG_SPICLK_PRESCALE_MASK;
-+ reg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz);
-+ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
-+ }
-+
-+ if (tx) {
-+ len = xfer->len;
-+ while (len-- > 0) {
-+ rt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++);
-+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
-+ err = rt2880_spi_wait_ready(rs, 1);
-+ if (err) {
-+ dev_err(&spi->dev, "TX failed, err=%d\n", err);
-+ goto out;
-+ }
-+ }
-+ }
-+
-+ if (rx) {
-+ len = xfer->len;
-+ while (len-- > 0) {
-+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
-+ err = rt2880_spi_wait_ready(rs, 1);
-+ if (err) {
-+ dev_err(&spi->dev, "RX failed, err=%d\n", err);
-+ goto out;
-+ }
-+ *rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
-+ }
-+ }
-+
-+out:
-+ return err;
-+}
-+
-+/* copy from spi.c */
-+static void spi_set_cs(struct spi_device *spi, bool enable)
-+{
-+ if (spi->mode & SPI_CS_HIGH)
-+ enable = !enable;
-+
-+ if (spi->cs_gpiod)
-+ gpiod_set_value(spi->cs_gpiod, !enable);
-+ else if (spi->master->set_cs)
-+ spi->master->set_cs(spi, !enable);
-+}
-+
-+static int rt2880_spi_setup(struct spi_device *spi)
-+{
-+ struct spi_master *master = spi->master;
-+ struct rt2880_spi *rs = spi_master_get_devdata(master);
-+ u32 reg, old_reg, arbit_off;
-+
-+ if ((spi->max_speed_hz > master->max_speed_hz) ||
-+ (spi->max_speed_hz < master->min_speed_hz)) {
-+ dev_err(&spi->dev, "invalide requested speed %d Hz\n",
-+ spi->max_speed_hz);
-+ return -EINVAL;
-+ }
-+
-+ if (!(master->bits_per_word_mask &
-+ BIT(spi->bits_per_word - 1))) {
-+ dev_err(&spi->dev, "invalide bits_per_word %d\n",
-+ spi->bits_per_word);
-+ return -EINVAL;
-+ }
-+
-+ /* the hardware seems can't work on mode0 force it to mode3 */
-+ if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {
-+ dev_warn(&spi->dev, "force spi mode3\n");
-+ spi->mode |= SPI_MODE_3;
-+ }
-+
-+ /* chip polarity */
-+ arbit_off = get_arbiter_offset(master);
-+ reg = old_reg = rt2880_spi_read(rs, arbit_off);
-+ if (spi->mode & SPI_CS_HIGH) {
-+ switch (master->bus_num) {
-+ case 1:
-+ reg |= SPI1_POR;
-+ break;
-+ default:
-+ reg |= SPI0_POR;
-+ break;
-+ }
-+ } else {
-+ switch (master->bus_num) {
-+ case 1:
-+ reg &= ~SPI1_POR;
-+ break;
-+ default:
-+ reg &= ~SPI0_POR;
-+ break;
-+ }
-+ }
-+
-+ /* enable spi1 */
-+ if (master->bus_num == 1)
-+ reg |= SPICTL_ARB_EN;
-+
-+ if (reg != old_reg)
-+ rt2880_spi_write(rs, arbit_off, reg);
-+
-+ /* deselected the spi device */
-+ spi_set_cs(spi, false);
-+
-+ rt2880_dump_reg(master);
-+
-+ return 0;
-+}
-+
-+static int rt2880_spi_prepare_message(struct spi_master *master,
-+ struct spi_message *msg)
-+{
-+ struct rt2880_spi *rs = spi_master_get_devdata(master);
-+ struct spi_device *spi = msg->spi;
-+ u32 reg;
-+
-+ if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz))
-+ return 0;
-+
-+#if 0
-+ /* set spido to tri-state */
-+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO);
-+#endif
-+
-+ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
-+
-+ reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL |
-+ SPICFG_RXCLKEDGE_FALLING |
-+ SPICFG_TXCLKEDGE_FALLING |
-+ SPICFG_SPICLK_PRESCALE_MASK);
-+
-+ /* MSB */
-+ if (!(spi->mode & SPI_LSB_FIRST))
-+ reg |= SPICFG_MSBFIRST;
-+
-+ /* spi mode */
-+ switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
-+ case SPI_MODE_0:
-+ reg |= SPICFG_TXCLKEDGE_FALLING;
-+ break;
-+ case SPI_MODE_1:
-+ reg |= SPICFG_RXCLKEDGE_FALLING;
-+ break;
-+ case SPI_MODE_2:
-+ reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
-+ break;
-+ case SPI_MODE_3:
-+ reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
-+ break;
-+ }
-+ rs->mode = spi->mode;
-+
-+#if 0
-+ /* set spiclk and spiena to tri-state */
-+ reg |= SPICFG_HIZSPI;
-+#endif
-+
-+ /* clock divide */
-+ reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz);
-+
-+ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
-+
-+ return 0;
-+}
-+
-+static int rt2880_spi_probe(struct platform_device *pdev)
-+{
-+ struct spi_master *master;
-+ struct rt2880_spi *rs;
-+ void __iomem *base;
-+ struct resource *r;
-+ struct clk *clk;
-+ int ret;
-+
-+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ base = devm_ioremap_resource(&pdev->dev, r);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ clk = devm_clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(clk)) {
-+ dev_err(&pdev->dev, "unable to get SYS clock\n");
-+ return PTR_ERR(clk);
-+ }
-+
-+ ret = clk_prepare_enable(clk);
-+ if (ret)
-+ goto err_clk;
-+
-+ master = spi_alloc_master(&pdev->dev, sizeof(*rs));
-+ if (master == NULL) {
-+ dev_dbg(&pdev->dev, "master allocation failed\n");
-+ ret = -ENOMEM;
-+ goto err_clk;
-+ }
-+
-+ master->dev.of_node = pdev->dev.of_node;
-+ master->mode_bits = RT2880_SPI_MODE_BITS;
-+ master->bits_per_word_mask = SPI_BPW_MASK(8);
-+ master->min_speed_hz = clk_get_rate(clk) / 128;
-+ master->max_speed_hz = clk_get_rate(clk) / 2;
-+ master->flags = SPI_MASTER_HALF_DUPLEX;
-+ master->setup = rt2880_spi_setup;
-+ master->prepare_message = rt2880_spi_prepare_message;
-+ master->set_cs = rt2880_spi_set_cs;
-+ master->transfer_one = rt2880_spi_transfer_one,
-+
-+ dev_set_drvdata(&pdev->dev, master);
-+
-+ rs = spi_master_get_devdata(master);
-+ rs->master = master;
-+ rs->base = base;
-+ rs->clk = clk;
-+
-+ if (atomic_inc_return(&hw_reset_count) == 1) {
-+ ret = device_reset(&pdev->dev);
-+ if (ret) {
-+ dev_err(&pdev->dev, "device_reset error.\n");
-+ goto err_master;
-+ }
-+ }
-+
-+ ret = devm_spi_register_master(&pdev->dev, master);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "devm_spi_register_master error.\n");
-+ goto err_master;
-+ }
-+
-+ return ret;
-+
-+err_master:
-+ spi_master_put(master);
-+ kfree(master);
-+err_clk:
-+ clk_disable_unprepare(clk);
-+
-+ return ret;
-+}
-+
-+static int rt2880_spi_remove(struct platform_device *pdev)
-+{
-+ struct spi_master *master;
-+ struct rt2880_spi *rs;
-+
-+ master = dev_get_drvdata(&pdev->dev);
-+ rs = spi_master_get_devdata(master);
-+
-+ clk_disable_unprepare(rs->clk);
-+ atomic_dec(&hw_reset_count);
-+
-+ return 0;
-+}
-+
-+MODULE_ALIAS("platform:" DRIVER_NAME);
-+
-+static const struct of_device_id rt2880_spi_match[] = {
-+ { .compatible = "ralink,rt2880-spi" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, rt2880_spi_match);
-+
-+static struct platform_driver rt2880_spi_driver = {
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .owner = THIS_MODULE,
-+ .of_match_table = rt2880_spi_match,
-+ },
-+ .probe = rt2880_spi_probe,
-+ .remove = rt2880_spi_remove,
-+};
-+
-+module_platform_driver(rt2880_spi_driver);
-+
-+MODULE_DESCRIPTION("Ralink SPI driver");
-+MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
-+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:52:56 +0100
-Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++
- drivers/i2c/busses/Kconfig | 4 +
- drivers/i2c/busses/Makefile | 1 +
- drivers/i2c/busses/i2c-ralink.c | 327 ++++++++++++++++++++
- 4 files changed, 359 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
- create mode 100644 drivers/i2c/busses/i2c-ralink.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
-@@ -0,0 +1,27 @@
-+I2C for Ralink platforms
-+
-+Required properties :
-+- compatible : Must be "link,rt3052-i2c"
-+- reg: physical base address of the controller and length of memory mapped
-+ region.
-+- #address-cells = <1>;
-+- #size-cells = <0>;
-+
-+Optional properties:
-+- Child nodes conforming to i2c bus binding
-+
-+Example :
-+
-+palmbus@10000000 {
-+ i2c@900 {
-+ compatible = "link,rt3052-i2c";
-+ reg = <0x900 0x100>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ hwmon@4b {
-+ compatible = "national,lm92";
-+ reg = <0x4b>;
-+ };
-+ };
-+};
---- a/drivers/i2c/busses/Kconfig
-+++ b/drivers/i2c/busses/Kconfig
-@@ -998,6 +998,11 @@ config I2C_RK3X
- This driver can also be built as a module. If so, the module will
- be called i2c-rk3x.
-
-+config I2C_RALINK
-+ tristate "Ralink I2C Controller"
-+ depends on RALINK && !SOC_MT7621
-+ select OF_I2C
-+
- config I2C_RZV2M
- tristate "Renesas RZ/V2M adapter"
- depends on ARCH_RENESAS || COMPILE_TEST
---- a/drivers/i2c/busses/Makefile
-+++ b/drivers/i2c/busses/Makefile
-@@ -95,6 +95,7 @@ obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pc
- obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
- obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
- obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
-+obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
- obj-$(CONFIG_I2C_QCOM_CCI) += i2c-qcom-cci.o
- obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o
- obj-$(CONFIG_I2C_QUP) += i2c-qup.o
---- /dev/null
-+++ b/drivers/i2c/busses/i2c-ralink.c
-@@ -0,0 +1,440 @@
-+/*
-+ * drivers/i2c/busses/i2c-ralink.c
-+ *
-+ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
-+ * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
-+ *
-+ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
-+ * (C) 2014 Sittisak <sittisaks@hotmail.com>
-+ *
-+ * This software is licensed under the terms of the GNU General Public
-+ * License version 2, as published by the Free Software Foundation, and
-+ * may be copied, distributed, and modified under those terms.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/reset.h>
-+#include <linux/delay.h>
-+#include <linux/slab.h>
-+#include <linux/init.h>
-+#include <linux/errno.h>
-+#include <linux/platform_device.h>
-+#include <linux/of_platform.h>
-+#include <linux/i2c.h>
-+#include <linux/io.h>
-+#include <linux/err.h>
-+#include <linux/clk.h>
-+
-+#define REG_CONFIG_REG 0x00
-+#define REG_CLKDIV_REG 0x04
-+#define REG_DEVADDR_REG 0x08
-+#define REG_ADDR_REG 0x0C
-+#define REG_DATAOUT_REG 0x10
-+#define REG_DATAIN_REG 0x14
-+#define REG_STATUS_REG 0x18
-+#define REG_STARTXFR_REG 0x1C
-+#define REG_BYTECNT_REG 0x20
-+
-+/* REG_CONFIG_REG */
-+#define I2C_ADDRLEN_OFFSET 5
-+#define I2C_DEVADLEN_OFFSET 2
-+#define I2C_ADDRLEN_MASK 0x3
-+#define I2C_ADDR_DIS BIT(1)
-+#define I2C_DEVADDR_DIS BIT(0)
-+#define I2C_ADDRLEN_8 (7 << I2C_ADDRLEN_OFFSET)
-+#define I2C_DEVADLEN_7 (6 << I2C_DEVADLEN_OFFSET)
-+#define I2C_CONF_DEFAULT (I2C_ADDRLEN_8 | I2C_DEVADLEN_7)
-+
-+/* REG_CLKDIV_REG */
-+#define I2C_CLKDIV_MASK 0xffff
-+
-+/* REG_DEVADDR_REG */
-+#define I2C_DEVADDR_MASK 0x7f
-+
-+/* REG_ADDR_REG */
-+#define I2C_ADDR_MASK 0xff
-+
-+/* REG_STATUS_REG */
-+#define I2C_STARTERR BIT(4)
-+#define I2C_ACKERR BIT(3)
-+#define I2C_DATARDY BIT(2)
-+#define I2C_SDOEMPTY BIT(1)
-+#define I2C_BUSY BIT(0)
-+
-+/* REG_STARTXFR_REG */
-+#define NOSTOP_CMD BIT(2)
-+#define NODATA_CMD BIT(1)
-+#define READ_CMD BIT(0)
-+
-+/* REG_BYTECNT_REG */
-+#define BYTECNT_MAX 64
-+#define SET_BYTECNT(x) (x - 1)
-+
-+/* timeout waiting for I2C devices to respond (clock streching) */
-+#define TIMEOUT_MS 1000
-+#define DELAY_INTERVAL_US 100
-+
-+struct rt_i2c {
-+ void __iomem *base;
-+ struct clk *clk;
-+ struct device *dev;
-+ struct i2c_adapter adap;
-+ u32 cur_clk;
-+ u32 clk_div;
-+ u32 flags;
-+};
-+
-+static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg)
-+{
-+ iowrite32(val, i2c->base + reg);
-+}
-+
-+static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg)
-+{
-+ return ioread32(i2c->base + reg);
-+}
-+
-+static int poll_down_timeout(void __iomem *addr, u32 mask)
-+{
-+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
-+
-+ do {
-+ if (!(readl_relaxed(addr) & mask))
-+ return 0;
-+
-+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
-+ } while (time_before(jiffies, timeout));
-+
-+ return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
-+}
-+
-+static int rt_i2c_wait_idle(struct rt_i2c *i2c)
-+{
-+ int ret;
-+
-+ ret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY);
-+ if (ret < 0)
-+ dev_dbg(i2c->dev, "idle err(%d)\n", ret);
-+
-+ return ret;
-+}
-+
-+static int poll_up_timeout(void __iomem *addr, u32 mask)
-+{
-+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
-+ u32 status;
-+
-+ do {
-+ status = readl_relaxed(addr);
-+
-+ /* check error status */
-+ if (status & I2C_STARTERR)
-+ return -EAGAIN;
-+ else if (status & I2C_ACKERR)
-+ return -ENXIO;
-+ else if (status & mask)
-+ return 0;
-+
-+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
-+ } while (time_before(jiffies, timeout));
-+
-+ return -ETIMEDOUT;
-+}
-+
-+static int rt_i2c_wait_rx_done(struct rt_i2c *i2c)
-+{
-+ int ret;
-+
-+ ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY);
-+ if (ret < 0)
-+ dev_dbg(i2c->dev, "rx err(%d)\n", ret);
-+
-+ return ret;
-+}
-+
-+static int rt_i2c_wait_tx_done(struct rt_i2c *i2c)
-+{
-+ int ret;
-+
-+ ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY);
-+ if (ret < 0)
-+ dev_dbg(i2c->dev, "tx err(%d)\n", ret);
-+
-+ return ret;
-+}
-+
-+static void rt_i2c_reset(struct rt_i2c *i2c)
-+{
-+ int ret;
-+
-+ ret = device_reset(i2c->adap.dev.parent);
-+ if (ret)
-+ dev_err(i2c->dev, "Failed to reset device");
-+
-+ barrier();
-+ rt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG);
-+}
-+
-+static void rt_i2c_dump_reg(struct rt_i2c *i2c)
-+{
-+ dev_dbg(i2c->dev, "conf %08x, clkdiv %08x, devaddr %08x, " \
-+ "addr %08x, dataout %08x, datain %08x, " \
-+ "status %08x, startxfr %08x, bytecnt %08x\n",
-+ rt_i2c_r32(i2c, REG_CONFIG_REG),
-+ rt_i2c_r32(i2c, REG_CLKDIV_REG),
-+ rt_i2c_r32(i2c, REG_DEVADDR_REG),
-+ rt_i2c_r32(i2c, REG_ADDR_REG),
-+ rt_i2c_r32(i2c, REG_DATAOUT_REG),
-+ rt_i2c_r32(i2c, REG_DATAIN_REG),
-+ rt_i2c_r32(i2c, REG_STATUS_REG),
-+ rt_i2c_r32(i2c, REG_STARTXFR_REG),
-+ rt_i2c_r32(i2c, REG_BYTECNT_REG));
-+}
-+
-+static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
-+ int num)
-+{
-+ struct rt_i2c *i2c;
-+ struct i2c_msg *pmsg;
-+ unsigned char addr;
-+ int i, j, ret;
-+ u32 cmd;
-+
-+ i2c = i2c_get_adapdata(adap);
-+
-+ for (i = 0; i < num; i++) {
-+ pmsg = &msgs[i];
-+ if (i == (num - 1))
-+ cmd = 0;
-+ else
-+ cmd = NOSTOP_CMD;
-+
-+ dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x, stop: %d\n",
-+ pmsg->addr, pmsg->len, pmsg->flags,
-+ (cmd == 0)? 1 : 0);
-+
-+ /* wait hardware idle */
-+ if ((ret = rt_i2c_wait_idle(i2c)))
-+ goto err_timeout;
-+
-+ if (pmsg->flags & I2C_M_TEN) {
-+ rt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG);
-+ /* 10 bits address */
-+ addr = 0x78 | ((pmsg->addr >> 8) & 0x03);
-+ rt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK,
-+ REG_DEVADDR_REG);
-+ rt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK,
-+ REG_ADDR_REG);
-+ } else {
-+ rt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS,
-+ REG_CONFIG_REG);
-+ /* 7 bits address */
-+ rt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
-+ REG_DEVADDR_REG);
-+ }
-+
-+ /* buffer length */
-+ if (pmsg->len == 0)
-+ cmd |= NODATA_CMD;
-+ else
-+ rt_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
-+ REG_BYTECNT_REG);
-+
-+ j = 0;
-+ if (pmsg->flags & I2C_M_RD) {
-+ cmd |= READ_CMD;
-+ /* start transfer */
-+ barrier();
-+ rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
-+ do {
-+ /* wait */
-+ if ((ret = rt_i2c_wait_rx_done(i2c)))
-+ goto err_timeout;
-+ /* read data */
-+ if (pmsg->len)
-+ pmsg->buf[j] = rt_i2c_r32(i2c,
-+ REG_DATAIN_REG);
-+ j++;
-+ } while (j < pmsg->len);
-+ } else {
-+ do {
-+ /* write data */
-+ if (pmsg->len)
-+ rt_i2c_w32(i2c, pmsg->buf[j],
-+ REG_DATAOUT_REG);
-+ /* start transfer */
-+ if (j == 0) {
-+ barrier();
-+ rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
-+ }
-+ /* wait */
-+ if ((ret = rt_i2c_wait_tx_done(i2c)))
-+ goto err_timeout;
-+ j++;
-+ } while (j < pmsg->len);
-+ }
-+ }
-+ /* the return value is number of executed messages */
-+ ret = i;
-+
-+ return ret;
-+
-+err_timeout:
-+ rt_i2c_dump_reg(i2c);
-+ rt_i2c_reset(i2c);
-+ return ret;
-+}
-+
-+static u32 rt_i2c_func(struct i2c_adapter *a)
-+{
-+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-+}
-+
-+static const struct i2c_algorithm rt_i2c_algo = {
-+ .master_xfer = rt_i2c_master_xfer,
-+ .functionality = rt_i2c_func,
-+};
-+
-+static const struct of_device_id i2c_rt_dt_ids[] = {
-+ { .compatible = "ralink,rt2880-i2c" },
-+ { /* sentinel */ }
-+};
-+
-+MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
-+
-+static struct i2c_adapter_quirks rt_i2c_quirks = {
-+ .max_write_len = BYTECNT_MAX,
-+ .max_read_len = BYTECNT_MAX,
-+};
-+
-+static int rt_i2c_init(struct rt_i2c *i2c)
-+{
-+ u32 reg;
-+
-+ /* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */
-+ i2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) /
-+ (2 * i2c->cur_clk);
-+ if (i2c->clk_div < 8)
-+ i2c->clk_div = 8;
-+ if (i2c->clk_div > I2C_CLKDIV_MASK)
-+ i2c->clk_div = I2C_CLKDIV_MASK;
-+
-+ /* check support combinde/repeated start message */
-+ rt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG);
-+ reg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD;
-+
-+ rt_i2c_reset(i2c);
-+
-+ return reg;
-+}
-+
-+static int rt_i2c_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ struct rt_i2c *i2c;
-+ struct i2c_adapter *adap;
-+ const struct of_device_id *match;
-+ int ret, restart;
-+
-+ match = of_match_device(i2c_rt_dt_ids, &pdev->dev);
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev, "no memory resource found\n");
-+ return -ENODEV;
-+ }
-+
-+ i2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL);
-+ if (!i2c) {
-+ dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
-+ return -ENOMEM;
-+ }
-+
-+ i2c->base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(i2c->base))
-+ return PTR_ERR(i2c->base);
-+
-+ i2c->clk = devm_clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(i2c->clk)) {
-+ dev_err(&pdev->dev, "no clock defined\n");
-+ return -ENODEV;
-+ }
-+ clk_prepare_enable(i2c->clk);
-+ i2c->dev = &pdev->dev;
-+
-+ if (of_property_read_u32(pdev->dev.of_node,
-+ "clock-frequency", &i2c->cur_clk))
-+ i2c->cur_clk = 100000;
-+
-+ adap = &i2c->adap;
-+ adap->owner = THIS_MODULE;
-+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
-+ adap->algo = &rt_i2c_algo;
-+ adap->retries = 3;
-+ adap->dev.parent = &pdev->dev;
-+ i2c_set_adapdata(adap, i2c);
-+ adap->dev.of_node = pdev->dev.of_node;
-+ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
-+ adap->quirks = &rt_i2c_quirks;
-+
-+ platform_set_drvdata(pdev, i2c);
-+
-+ restart = rt_i2c_init(i2c);
-+
-+ ret = i2c_add_adapter(adap);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "failed to add adapter\n");
-+ clk_disable_unprepare(i2c->clk);
-+ return ret;
-+ }
-+
-+ dev_info(&pdev->dev, "clock %uKHz, re-start %ssupport\n",
-+ i2c->cur_clk/1000, restart ? "" : "not ");
-+
-+ return ret;
-+}
-+
-+static int rt_i2c_remove(struct platform_device *pdev)
-+{
-+ struct rt_i2c *i2c = platform_get_drvdata(pdev);
-+
-+ i2c_del_adapter(&i2c->adap);
-+ clk_disable_unprepare(i2c->clk);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver rt_i2c_driver = {
-+ .probe = rt_i2c_probe,
-+ .remove = rt_i2c_remove,
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = "i2c-ralink",
-+ .of_match_table = i2c_rt_dt_ids,
-+ },
-+};
-+
-+static int __init i2c_rt_init (void)
-+{
-+ return platform_driver_register(&rt_i2c_driver);
-+}
-+subsys_initcall(i2c_rt_init);
-+
-+static void __exit i2c_rt_exit (void)
-+{
-+ platform_driver_unregister(&rt_i2c_driver);
-+}
-+module_exit(i2c_rt_exit);
-+
-+MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
-+MODULE_DESCRIPTION("Ralink I2c host driver");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:Ralink-I2C");
+++ /dev/null
-From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 13 Nov 2014 19:08:40 +0100
-Subject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/mmc/host/Kconfig | 2 +
- drivers/mmc/host/Makefile | 1 +
- drivers/mmc/host/mtk-mmc/Kconfig | 16 +
- drivers/mmc/host/mtk-mmc/Makefile | 42 +
- drivers/mmc/host/mtk-mmc/board.h | 137 ++
- drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++
- drivers/mmc/host/mtk-mmc/dbg.h | 156 ++
- drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++
- drivers/mmc/host/mtk-mmc/sd.c | 3060 ++++++++++++++++++++++++++++++++++
- 9 files changed, 4762 insertions(+)
- create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig
- create mode 100644 drivers/mmc/host/mtk-mmc/Makefile
- create mode 100644 drivers/mmc/host/mtk-mmc/board.h
- create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c
- create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h
- create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h
- create mode 100644 drivers/mmc/host/mtk-mmc/sd.c
-
---- a/drivers/mmc/host/Kconfig
-+++ b/drivers/mmc/host/Kconfig
-@@ -1102,6 +1102,8 @@ config MMC_OWL
- config MMC_SDHCI_EXTERNAL_DMA
- bool
-
-+source "drivers/mmc/host/mtk-mmc/Kconfig"
-+
- config MMC_LITEX
- tristate "LiteX MMC Host Controller support"
- depends on ((PPC_MICROWATT || LITEX) && OF && HAVE_CLK) || COMPILE_TEST
---- a/drivers/mmc/host/Makefile
-+++ b/drivers/mmc/host/Makefile
-@@ -3,6 +3,7 @@
- # Makefile for MMC/SD host controller drivers
- #
-
-+obj-$(CONFIG_MTK_MMC) += mtk-mmc/
- obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o
- armmmci-y := mmci.o
- armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
+++ /dev/null
-From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:31:47 +0100
-Subject: [PATCH 48/53] asoc: add mt7620 support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/ralink/of.c | 2 +
- sound/soc/Kconfig | 1 +
- sound/soc/Makefile | 1 +
- sound/soc/ralink/Kconfig | 15 ++
- sound/soc/ralink/Makefile | 11 +
- sound/soc/ralink/mt7620-i2s.c | 436 ++++++++++++++++++++++++++++++++++++++
- sound/soc/ralink/mt7620-wm8960.c | 233 ++++++++++++++++++++
- 7 files changed, 699 insertions(+)
- create mode 100644 sound/soc/ralink/Kconfig
- create mode 100644 sound/soc/ralink/Makefile
- create mode 100644 sound/soc/ralink/mt7620-i2s.c
- create mode 100644 sound/soc/ralink/mt7620-wm8960.c
-
---- a/sound/soc/Kconfig
-+++ b/sound/soc/Kconfig
-@@ -86,6 +86,7 @@ source "sound/soc/mxs/Kconfig"
- source "sound/soc/pxa/Kconfig"
- source "sound/soc/qcom/Kconfig"
- source "sound/soc/rockchip/Kconfig"
-+source "sound/soc/ralink/Kconfig"
- source "sound/soc/samsung/Kconfig"
- source "sound/soc/sh/Kconfig"
- source "sound/soc/sof/Kconfig"
---- a/sound/soc/Makefile
-+++ b/sound/soc/Makefile
-@@ -54,6 +54,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/
- obj-$(CONFIG_SND_SOC) += pxa/
- obj-$(CONFIG_SND_SOC) += qcom/
- obj-$(CONFIG_SND_SOC) += rockchip/
-+obj-$(CONFIG_SND_SOC) += ralink/
- obj-$(CONFIG_SND_SOC) += samsung/
- obj-$(CONFIG_SND_SOC) += sh/
- obj-$(CONFIG_SND_SOC) += sof/
---- /dev/null
-+++ b/sound/soc/ralink/Kconfig
-@@ -0,0 +1,8 @@
-+config SND_RALINK_SOC_I2S
-+ depends on RALINK && SND_SOC && !SOC_RT288X
-+ select SND_SOC_GENERIC_DMAENGINE_PCM
-+ select REGMAP_MMIO
-+ tristate "SoC Audio (I2S protocol) for Ralink SoC"
-+ help
-+ Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek
-+ based boards.
---- /dev/null
-+++ b/sound/soc/ralink/Makefile
-@@ -0,0 +1,6 @@
-+#
-+# Ralink/MediaTek Platform Support
-+#
-+snd-soc-ralink-i2s-objs := ralink-i2s.o
-+
-+obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o
---- /dev/null
-+++ b/sound/soc/ralink/ralink-i2s.c
-@@ -0,0 +1,968 @@
-+/*
-+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
-+ * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ *
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/regmap.h>
-+#include <linux/reset.h>
-+#include <linux/debugfs.h>
-+#include <linux/of_device.h>
-+#include <sound/pcm_params.h>
-+#include <sound/dmaengine_pcm.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define DRV_NAME "ralink-i2s"
-+
-+#define I2S_REG_CFG0 0x00
-+#define I2S_REG_INT_STATUS 0x04
-+#define I2S_REG_INT_EN 0x08
-+#define I2S_REG_FF_STATUS 0x0c
-+#define I2S_REG_WREG 0x10
-+#define I2S_REG_RREG 0x14
-+#define I2S_REG_CFG1 0x18
-+#define I2S_REG_DIVCMP 0x20
-+#define I2S_REG_DIVINT 0x24
-+
-+/* I2S_REG_CFG0 */
-+#define I2S_REG_CFG0_EN BIT(31)
-+#define I2S_REG_CFG0_DMA_EN BIT(30)
-+#define I2S_REG_CFG0_BYTE_SWAP BIT(28)
-+#define I2S_REG_CFG0_TX_EN BIT(24)
-+#define I2S_REG_CFG0_RX_EN BIT(20)
-+#define I2S_REG_CFG0_SLAVE BIT(16)
-+#define I2S_REG_CFG0_RX_THRES 12
-+#define I2S_REG_CFG0_TX_THRES 4
-+#define I2S_REG_CFG0_THRES_MASK (0xf << I2S_REG_CFG0_RX_THRES) | \
-+ (4 << I2S_REG_CFG0_TX_THRES)
-+#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \
-+ (4 << I2S_REG_CFG0_TX_THRES)
-+/* RT305x */
-+#define I2S_REG_CFG0_CLK_DIS BIT(8)
-+#define I2S_REG_CFG0_TXCH_SWAP BIT(3)
-+#define I2S_REG_CFG0_TXCH1_OFF BIT(2)
-+#define I2S_REG_CFG0_TXCH0_OFF BIT(1)
-+#define I2S_REG_CFG0_SLAVE_EN BIT(0)
-+/* RT3883 */
-+#define I2S_REG_CFG0_RXCH_SWAP BIT(11)
-+#define I2S_REG_CFG0_RXCH1_OFF BIT(10)
-+#define I2S_REG_CFG0_RXCH0_OFF BIT(9)
-+#define I2S_REG_CFG0_WS_INV BIT(0)
-+/* MT7628 */
-+#define I2S_REG_CFG0_FMT_LE BIT(29)
-+#define I2S_REG_CFG0_SYS_BE BIT(28)
-+#define I2S_REG_CFG0_NORM_24 BIT(18)
-+#define I2S_REG_CFG0_DATA_24 BIT(17)
-+
-+/* I2S_REG_INT_STATUS */
-+#define I2S_REG_INT_RX_FAULT BIT(7)
-+#define I2S_REG_INT_RX_OVRUN BIT(6)
-+#define I2S_REG_INT_RX_UNRUN BIT(5)
-+#define I2S_REG_INT_RX_THRES BIT(4)
-+#define I2S_REG_INT_TX_FAULT BIT(3)
-+#define I2S_REG_INT_TX_OVRUN BIT(2)
-+#define I2S_REG_INT_TX_UNRUN BIT(1)
-+#define I2S_REG_INT_TX_THRES BIT(0)
-+#define I2S_REG_INT_TX_MASK 0xf
-+#define I2S_REG_INT_RX_MASK 0xf0
-+
-+/* I2S_REG_INT_STATUS */
-+#define I2S_RX_AVCNT(x) ((x >> 4) & 0xf)
-+#define I2S_TX_AVCNT(x) (x & 0xf)
-+/* MT7628 */
-+#define MT7628_I2S_RX_AVCNT(x) ((x >> 8) & 0x1f)
-+#define MT7628_I2S_TX_AVCNT(x) (x & 0x1f)
-+
-+/* I2S_REG_CFG1 */
-+#define I2S_REG_CFG1_LBK BIT(31)
-+#define I2S_REG_CFG1_EXTLBK BIT(30)
-+/* RT3883 */
-+#define I2S_REG_CFG1_LEFT_J BIT(0)
-+#define I2S_REG_CFG1_RIGHT_J BIT(1)
-+#define I2S_REG_CFG1_FMT_MASK 0x3
-+
-+/* I2S_REG_DIVCMP */
-+#define I2S_REG_DIVCMP_CLKEN BIT(31)
-+#define I2S_REG_DIVCMP_DIVCOMP_MASK 0x1ff
-+
-+/* I2S_REG_DIVINT */
-+#define I2S_REG_DIVINT_MASK 0x3ff
-+
-+/* BCLK dividers */
-+#define RALINK_I2S_DIVCMP 0
-+#define RALINK_I2S_DIVINT 1
-+
-+/* FIFO */
-+#define RALINK_I2S_FIFO_SIZE 32
-+
-+/* feature flags */
-+#define RALINK_FLAGS_TXONLY BIT(0)
-+#define RALINK_FLAGS_LEFT_J BIT(1)
-+#define RALINK_FLAGS_RIGHT_J BIT(2)
-+#define RALINK_FLAGS_ENDIAN BIT(3)
-+#define RALINK_FLAGS_24BIT BIT(4)
-+
-+#define RALINK_I2S_INT_EN 0
-+
-+struct ralink_i2s_stats {
-+ u32 dmafault;
-+ u32 overrun;
-+ u32 underrun;
-+ u32 belowthres;
-+};
-+
-+struct ralink_i2s {
-+ struct device *dev;
-+ void __iomem *regs;
-+ struct clk *clk;
-+ struct regmap *regmap;
-+ u32 flags;
-+ unsigned int fmt;
-+ u16 txdma_req;
-+ u16 rxdma_req;
-+
-+ struct snd_dmaengine_dai_dma_data playback_dma_data;
-+ struct snd_dmaengine_dai_dma_data capture_dma_data;
-+
-+ struct dentry *dbg_dir;
-+ struct dentry *dbg_stats;
-+ struct ralink_i2s_stats txstats;
-+ struct ralink_i2s_stats rxstats;
-+};
-+
-+static void ralink_i2s_dump_regs(struct ralink_i2s *i2s)
-+{
-+ u32 buf[10];
-+ int ret;
-+
-+ ret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0,
-+ buf, ARRAY_SIZE(buf));
-+
-+ dev_dbg(i2s->dev, "CFG0: %08x, INTSTAT: %08x, INTEN: %08x, " \
-+ "FFSTAT: %08x, WREG: %08x, RREG: %08x, " \
-+ "CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\n",
-+ buf[0], buf[1], buf[2], buf[3], buf[4],
-+ buf[5], buf[6], buf[8], buf[9]);
-+}
-+
-+static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai,
-+ int clk_id, unsigned int freq, int dir)
-+{
-+ return 0;
-+}
-+
-+static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate)
-+{
-+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ unsigned long clk = clk_get_rate(i2s->clk);
-+ int div;
-+ uint32_t data;
-+
-+ /* disable clock at slave mode */
-+ if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
-+ SND_SOC_DAIFMT_CBM_CFM) {
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+ I2S_REG_CFG0_CLK_DIS,
-+ I2S_REG_CFG0_CLK_DIS);
-+ return 0;
-+ }
-+
-+ /* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */
-+ div = (clk / rate ) - 1;
-+
-+ data = rt_sysc_r32(0x30);
-+ data &= (0xff << 8);
-+ data |= (0x1 << 15) | (div << 8);
-+ rt_sysc_w32(data, 0x30);
-+
-+ /* enable clock */
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0);
-+
-+ dev_dbg(i2s->dev, "clk: %lu, rate: %u, div: %d\n",
-+ clk, rate, div);
-+
-+ return 0;
-+}
-+
-+static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate)
-+{
-+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ unsigned long clk = clk_get_rate(i2s->clk);
-+ int divint, divcomp;
-+
-+ /* disable clock at slave mode */
-+ if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
-+ SND_SOC_DAIFMT_CBM_CFM) {
-+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
-+ I2S_REG_DIVCMP_CLKEN, 0);
-+ return 0;
-+ }
-+
-+ /* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */
-+ clk = clk / (2 * 2 * width);
-+ divint = clk / rate;
-+ divcomp = ((clk % rate) * 512) / rate;
-+
-+ if ((divint > I2S_REG_DIVINT_MASK) ||
-+ (divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK))
-+ return -EINVAL;
-+
-+ regmap_update_bits(i2s->regmap, I2S_REG_DIVINT,
-+ I2S_REG_DIVINT_MASK, divint);
-+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
-+ I2S_REG_DIVCMP_DIVCOMP_MASK, divcomp);
-+
-+ /* enable clock */
-+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN,
-+ I2S_REG_DIVCMP_CLKEN);
-+
-+ dev_dbg(i2s->dev, "clk: %lu, rate: %u, int: %d, comp: %d\n",
-+ clk_get_rate(i2s->clk), rate, divint, divcomp);
-+
-+ return 0;
-+}
-+
-+static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
-+{
-+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ unsigned int cfg0 = 0, cfg1 = 0;
-+
-+ /* set master/slave audio interface */
-+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-+ case SND_SOC_DAIFMT_CBM_CFM:
-+ if (i2s->flags & RALINK_FLAGS_TXONLY)
-+ cfg0 |= I2S_REG_CFG0_SLAVE_EN;
-+ else
-+ cfg0 |= I2S_REG_CFG0_SLAVE;
-+ break;
-+ case SND_SOC_DAIFMT_CBS_CFS:
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ /* interface format */
-+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
-+ case SND_SOC_DAIFMT_I2S:
-+ break;
-+ case SND_SOC_DAIFMT_RIGHT_J:
-+ if (i2s->flags & RALINK_FLAGS_RIGHT_J) {
-+ cfg1 |= I2S_REG_CFG1_RIGHT_J;
-+ break;
-+ }
-+ return -EINVAL;
-+ case SND_SOC_DAIFMT_LEFT_J:
-+ if (i2s->flags & RALINK_FLAGS_LEFT_J) {
-+ cfg1 |= I2S_REG_CFG1_LEFT_J;
-+ break;
-+ }
-+ return -EINVAL;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ /* clock inversion */
-+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
-+ case SND_SOC_DAIFMT_NB_NF:
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ if (i2s->flags & RALINK_FLAGS_TXONLY) {
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+ I2S_REG_CFG0_SLAVE_EN, cfg0);
-+ } else {
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+ I2S_REG_CFG0_SLAVE, cfg0);
-+ }
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG1,
-+ I2S_REG_CFG1_FMT_MASK, cfg1);
-+ i2s->fmt = fmt;
-+
-+ return 0;
-+}
-+
-+static int ralink_i2s_startup(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+
-+ if (snd_soc_dai_active(dai))
-+ return 0;
-+
-+ /* setup status interrupt */
-+#if (RALINK_I2S_INT_EN)
-+ regmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff);
-+#else
-+ regmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0);
-+#endif
-+
-+ /* enable */
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+ I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
-+ I2S_REG_CFG0_THRES_MASK,
-+ I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
-+ I2S_REG_CFG0_DFT_THRES);
-+
-+ return 0;
-+}
-+
-+static void ralink_i2s_shutdown(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+
-+ /* If both streams are stopped, disable module and clock */
-+ if (snd_soc_dai_active(dai))
-+ return;
-+
-+ /*
-+ * datasheet mention when disable all control regs are cleared
-+ * to initial values. need reinit at startup.
-+ */
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0);
-+}
-+
-+static int ralink_i2s_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
-+{
-+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ int width;
-+ int ret;
-+
-+ width = params_width(params);
-+ switch (width) {
-+ case 16:
-+ if (i2s->flags & RALINK_FLAGS_24BIT)
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+ I2S_REG_CFG0_DATA_24, 0);
-+ break;
-+ case 24:
-+ if (i2s->flags & RALINK_FLAGS_24BIT) {
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+ I2S_REG_CFG0_DATA_24,
-+ I2S_REG_CFG0_DATA_24);
-+ break;
-+ }
-+ return -EINVAL;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ switch (params_channels(params)) {
-+ case 2:
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ if (i2s->flags & RALINK_FLAGS_ENDIAN) {
-+ /* system endian */
-+#ifdef SNDRV_LITTLE_ENDIAN
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+ I2S_REG_CFG0_SYS_BE, 0);
-+#else
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+ I2S_REG_CFG0_SYS_BE,
-+ I2S_REG_CFG0_SYS_BE);
-+#endif
-+
-+ /* data endian */
-+ switch (params_format(params)) {
-+ case SNDRV_PCM_FORMAT_S16_LE:
-+ case SNDRV_PCM_FORMAT_S24_LE:
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+ I2S_REG_CFG0_FMT_LE,
-+ I2S_REG_CFG0_FMT_LE);
-+ break;
-+ case SNDRV_PCM_FORMAT_S16_BE:
-+ case SNDRV_PCM_FORMAT_S24_BE:
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
-+ I2S_REG_CFG0_FMT_LE, 0);
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+ }
-+
-+ /* setup bclk rate */
-+ if (i2s->flags & RALINK_FLAGS_TXONLY)
-+ ret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params));
-+ else
-+ ret = ralink_i2s_set_bclk(dai, width, params_rate(params));
-+
-+ return ret;
-+}
-+
-+static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
-+ struct snd_soc_dai *dai)
-+{
-+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+ unsigned int mask, val;
-+
-+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+ mask = I2S_REG_CFG0_TX_EN;
-+ else
-+ mask = I2S_REG_CFG0_RX_EN;
-+
-+ switch (cmd) {
-+ case SNDRV_PCM_TRIGGER_START:
-+ case SNDRV_PCM_TRIGGER_RESUME:
-+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+ val = mask;
-+ break;
-+ case SNDRV_PCM_TRIGGER_STOP:
-+ case SNDRV_PCM_TRIGGER_SUSPEND:
-+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+ val = 0;
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val);
-+
-+ return 0;
-+}
-+
-+static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s,
-+ struct resource *res)
-+{
-+ struct snd_dmaengine_dai_dma_data *dma_data;
-+
-+ /* Playback */
-+ dma_data = &i2s->playback_dma_data;
-+ dma_data->addr = res->start + I2S_REG_WREG;
-+ dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ dma_data->maxburst = 1;
-+
-+ if (i2s->flags & RALINK_FLAGS_TXONLY)
-+ return;
-+
-+ /* Capture */
-+ dma_data = &i2s->capture_dma_data;
-+ dma_data->addr = res->start + I2S_REG_RREG;
-+ dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ dma_data->maxburst = 1;
-+}
-+
-+static int ralink_i2s_dai_probe(struct snd_soc_dai *dai)
-+{
-+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
-+
-+ snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
-+ &i2s->capture_dma_data);
-+
-+ return 0;
-+}
-+
-+static int ralink_i2s_dai_remove(struct snd_soc_dai *dai)
-+{
-+ return 0;
-+}
-+
-+static const struct snd_soc_dai_ops ralink_i2s_dai_ops = {
-+ .set_sysclk = ralink_i2s_set_sysclk,
-+ .set_fmt = ralink_i2s_set_fmt,
-+ .startup = ralink_i2s_startup,
-+ .shutdown = ralink_i2s_shutdown,
-+ .hw_params = ralink_i2s_hw_params,
-+ .trigger = ralink_i2s_trigger,
-+};
-+
-+static struct snd_soc_dai_driver ralink_i2s_dai = {
-+ .name = DRV_NAME,
-+ .probe = ralink_i2s_dai_probe,
-+ .remove = ralink_i2s_dai_remove,
-+ .ops = &ralink_i2s_dai_ops,
-+ .capture = {
-+ .stream_name = "I2S Capture",
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rate_min = 5512,
-+ .rate_max = 192000,
-+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
-+ },
-+ .playback = {
-+ .stream_name = "I2S Playback",
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .rate_min = 5512,
-+ .rate_max = 192000,
-+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
-+ },
-+ .symmetric_rate = 1,
-+};
-+
-+static struct snd_pcm_hardware ralink_pcm_hardware = {
-+ .info = SNDRV_PCM_INFO_MMAP |
-+ SNDRV_PCM_INFO_MMAP_VALID |
-+ SNDRV_PCM_INFO_INTERLEAVED |
-+ SNDRV_PCM_INFO_BLOCK_TRANSFER,
-+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
-+ .channels_min = 2,
-+ .channels_max = 2,
-+ .period_bytes_min = PAGE_SIZE,
-+ .period_bytes_max = PAGE_SIZE * 2,
-+ .periods_min = 2,
-+ .periods_max = 128,
-+ .buffer_bytes_max = 128 * 1024,
-+ .fifo_size = RALINK_I2S_FIFO_SIZE,
-+};
-+
-+static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = {
-+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
-+ .pcm_hardware = &ralink_pcm_hardware,
-+ .prealloc_buffer_size = 256 * PAGE_SIZE,
-+};
-+
-+static const struct snd_soc_component_driver ralink_i2s_component = {
-+ .name = DRV_NAME,
-+};
-+
-+static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg)
-+{
-+ return true;
-+}
-+
-+static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case I2S_REG_INT_STATUS:
-+ case I2S_REG_FF_STATUS:
-+ return true;
-+ }
-+ return false;
-+}
-+
-+static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg)
-+{
-+ switch (reg) {
-+ case I2S_REG_FF_STATUS:
-+ case I2S_REG_RREG:
-+ return false;
-+ }
-+ return true;
-+}
-+
-+static const struct regmap_config ralink_i2s_regmap_config = {
-+ .reg_bits = 32,
-+ .reg_stride = 4,
-+ .val_bits = 32,
-+ .writeable_reg = ralink_i2s_writeable_reg,
-+ .readable_reg = ralink_i2s_readable_reg,
-+ .volatile_reg = ralink_i2s_volatile_reg,
-+ .max_register = I2S_REG_DIVINT,
-+};
-+
-+#if (RALINK_I2S_INT_EN)
-+static irqreturn_t ralink_i2s_irq(int irq, void *devid)
-+{
-+ struct ralink_i2s *i2s = devid;
-+ u32 status;
-+
-+ regmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status);
-+ if (unlikely(!status))
-+ return IRQ_NONE;
-+
-+ /* tx stats */
-+ if (status & I2S_REG_INT_TX_MASK) {
-+ if (status & I2S_REG_INT_TX_THRES)
-+ i2s->txstats.belowthres++;
-+ if (status & I2S_REG_INT_TX_UNRUN)
-+ i2s->txstats.underrun++;
-+ if (status & I2S_REG_INT_TX_OVRUN)
-+ i2s->txstats.overrun++;
-+ if (status & I2S_REG_INT_TX_FAULT)
-+ i2s->txstats.dmafault++;
-+ }
-+
-+ /* rx stats */
-+ if (status & I2S_REG_INT_RX_MASK) {
-+ if (status & I2S_REG_INT_RX_THRES)
-+ i2s->rxstats.belowthres++;
-+ if (status & I2S_REG_INT_RX_UNRUN)
-+ i2s->rxstats.underrun++;
-+ if (status & I2S_REG_INT_RX_OVRUN)
-+ i2s->rxstats.overrun++;
-+ if (status & I2S_REG_INT_RX_FAULT)
-+ i2s->rxstats.dmafault++;
-+ }
-+
-+ /* clean status bits */
-+ regmap_write(i2s->regmap, I2S_REG_INT_STATUS, status);
-+
-+ return IRQ_HANDLED;
-+}
-+#endif
-+
-+#if IS_ENABLED(CONFIG_DEBUG_FS)
-+static int ralink_i2s_stats_show(struct seq_file *s, void *unused)
-+{
-+ struct ralink_i2s *i2s = s->private;
-+
-+ seq_printf(s, "tx stats\n");
-+ seq_printf(s, "\tbelow threshold\t%u\n", i2s->txstats.belowthres);
-+ seq_printf(s, "\tunder run\t%u\n", i2s->txstats.underrun);
-+ seq_printf(s, "\tover run\t%u\n", i2s->txstats.overrun);
-+ seq_printf(s, "\tdma fault\t%u\n", i2s->txstats.dmafault);
-+
-+ seq_printf(s, "rx stats\n");
-+ seq_printf(s, "\tbelow threshold\t%u\n", i2s->rxstats.belowthres);
-+ seq_printf(s, "\tunder run\t%u\n", i2s->rxstats.underrun);
-+ seq_printf(s, "\tover run\t%u\n", i2s->rxstats.overrun);
-+ seq_printf(s, "\tdma fault\t%u\n", i2s->rxstats.dmafault);
-+
-+ ralink_i2s_dump_regs(i2s);
-+
-+ return 0;
-+}
-+
-+static int ralink_i2s_stats_open(struct inode *inode, struct file *file)
-+{
-+ return single_open(file, ralink_i2s_stats_show, inode->i_private);
-+}
-+
-+static const struct file_operations ralink_i2s_stats_ops = {
-+ .open = ralink_i2s_stats_open,
-+ .read = seq_read,
-+ .llseek = seq_lseek,
-+ .release = single_release,
-+};
-+
-+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
-+{
-+ i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL);
-+ if (!i2s->dbg_dir)
-+ return -ENOMEM;
-+
-+ i2s->dbg_stats = debugfs_create_file("stats", S_IRUGO,
-+ i2s->dbg_dir, i2s, &ralink_i2s_stats_ops);
-+ if (!i2s->dbg_stats) {
-+ debugfs_remove(i2s->dbg_dir);
-+ return -ENOMEM;
-+ }
-+
-+ return 0;
-+}
-+
-+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
-+{
-+ debugfs_remove(i2s->dbg_stats);
-+ debugfs_remove(i2s->dbg_dir);
-+}
-+#else
-+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
-+{
-+ return 0;
-+}
-+
-+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
-+{
-+}
-+#endif
-+
-+/*
-+ * TODO: these refclk setup functions should use
-+ * clock framework instead. hardcode it now.
-+ */
-+static void rt3350_refclk_setup(void)
-+{
-+ uint32_t data;
-+
-+ /* set refclk output 12Mhz clock */
-+ data = rt_sysc_r32(0x2c);
-+ data |= (0x1 << 8);
-+ rt_sysc_w32(data, 0x2c);
-+}
-+
-+static void rt3883_refclk_setup(void)
-+{
-+ uint32_t data;
-+
-+ /* set refclk output 12Mhz clock */
-+ data = rt_sysc_r32(0x2c);
-+ data &= ~(0x3 << 13);
-+ data |= (0x1 << 13);
-+ rt_sysc_w32(data, 0x2c);
-+}
-+
-+static void rt3552_refclk_setup(void)
-+{
-+ uint32_t data;
-+
-+ /* set refclk output 12Mhz clock */
-+ data = rt_sysc_r32(0x2c);
-+ data &= ~(0xf << 8);
-+ data |= (0x3 << 8);
-+ rt_sysc_w32(data, 0x2c);
-+}
-+
-+static void mt7620_refclk_setup(void)
-+{
-+ uint32_t data;
-+
-+ /* set refclk output 12Mhz clock */
-+ data = rt_sysc_r32(0x2c);
-+ data &= ~(0x7 << 9);
-+ data |= 0x1 << 9;
-+ rt_sysc_w32(data, 0x2c);
-+}
-+
-+static void mt7621_refclk_setup(void)
-+{
-+ uint32_t data;
-+
-+ /* set refclk output 12Mhz clock */
-+ data = rt_sysc_r32(0x2c);
-+ data &= ~(0x1f << 18);
-+ data |= (0x19 << 18);
-+ data &= ~(0x1f << 12);
-+ data |= (0x1 << 12);
-+ data &= ~(0x7 << 9);
-+ data |= (0x5 << 9);
-+ rt_sysc_w32(data, 0x2c);
-+}
-+
-+static void mt7628_refclk_setup(void)
-+{
-+ uint32_t data;
-+
-+ /* set i2s and refclk digital pad */
-+ data = rt_sysc_r32(0x3c);
-+ data |= 0x1f;
-+ rt_sysc_w32(data, 0x3c);
-+
-+ /* Adjust REFCLK0's driving strength */
-+ data = rt_sysc_r32(0x1354);
-+ data &= ~(0x1 << 5);
-+ rt_sysc_w32(data, 0x1354);
-+ data = rt_sysc_r32(0x1364);
-+ data |= ~(0x1 << 5);
-+ rt_sysc_w32(data, 0x1364);
-+
-+ /* set refclk output 12Mhz clock */
-+ data = rt_sysc_r32(0x2c);
-+ data &= ~(0x7 << 9);
-+ data |= 0x1 << 9;
-+ rt_sysc_w32(data, 0x2c);
-+}
-+
-+struct rt_i2s_data {
-+ u32 flags;
-+ void (*refclk_setup)(void);
-+};
-+
-+struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY };
-+struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY,
-+ .refclk_setup = rt3350_refclk_setup };
-+struct rt_i2s_data rt3883_i2s_data = {
-+ .flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J),
-+ .refclk_setup = rt3883_refclk_setup };
-+struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup};
-+struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup};
-+struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup};
-+struct rt_i2s_data mt7628_i2s_data = {
-+ .flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT |
-+ RALINK_FLAGS_LEFT_J),
-+ .refclk_setup = mt7628_refclk_setup};
-+
-+static const struct of_device_id ralink_i2s_match_table[] = {
-+ { .compatible = "ralink,rt3050-i2s",
-+ .data = (void *)&rt3050_i2s_data },
-+ { .compatible = "ralink,rt3350-i2s",
-+ .data = (void *)&rt3350_i2s_data },
-+ { .compatible = "ralink,rt3883-i2s",
-+ .data = (void *)&rt3883_i2s_data },
-+ { .compatible = "ralink,rt3352-i2s",
-+ .data = (void *)&rt3352_i2s_data },
-+ { .compatible = "mediatek,mt7620-i2s",
-+ .data = (void *)&mt7620_i2s_data },
-+ { .compatible = "mediatek,mt7621-i2s",
-+ .data = (void *)&mt7621_i2s_data },
-+ { .compatible = "mediatek,mt7628-i2s",
-+ .data = (void *)&mt7628_i2s_data },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, ralink_i2s_match_table);
-+
-+static int ralink_i2s_probe(struct platform_device *pdev)
-+{
-+ const struct of_device_id *match;
-+ struct device_node *np = pdev->dev.of_node;
-+ struct ralink_i2s *i2s;
-+ struct resource *res;
-+ int irq, ret;
-+ u32 dma_req;
-+ struct rt_i2s_data *data;
-+
-+ i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
-+ if (!i2s)
-+ return -ENOMEM;
-+
-+ platform_set_drvdata(pdev, i2s);
-+ i2s->dev = &pdev->dev;
-+
-+ match = of_match_device(ralink_i2s_match_table, &pdev->dev);
-+ if (!match)
-+ return -EINVAL;
-+ data = (struct rt_i2s_data *)match->data;
-+ i2s->flags = data->flags;
-+ /* setup out 12Mhz refclk to codec as mclk */
-+ if (data->refclk_setup)
-+ data->refclk_setup();
-+
-+ if (of_property_read_u32(np, "txdma-req", &dma_req)) {
-+ dev_err(&pdev->dev, "no txdma-req define\n");
-+ return -EINVAL;
-+ }
-+ i2s->txdma_req = (u16)dma_req;
-+ if (!(i2s->flags & RALINK_FLAGS_TXONLY)) {
-+ if (of_property_read_u32(np, "rxdma-req", &dma_req)) {
-+ dev_err(&pdev->dev, "no rxdma-req define\n");
-+ return -EINVAL;
-+ }
-+ i2s->rxdma_req = (u16)dma_req;
-+ }
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ i2s->regs = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(i2s->regs))
-+ return PTR_ERR(i2s->regs);
-+
-+ i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
-+ &ralink_i2s_regmap_config);
-+ if (IS_ERR(i2s->regmap)) {
-+ dev_err(&pdev->dev, "regmap init failed\n");
-+ return PTR_ERR(i2s->regmap);
-+ }
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ dev_err(&pdev->dev, "failed to get irq\n");
-+ return -EINVAL;
-+ }
-+
-+#if (RALINK_I2S_INT_EN)
-+ ret = devm_request_irq(&pdev->dev, irq, ralink_i2s_irq,
-+ 0, dev_name(&pdev->dev), i2s);
-+ if (ret) {
-+ dev_err(&pdev->dev, "failed to request irq\n");
-+ return ret;
-+ }
-+#endif
-+
-+ i2s->clk = devm_clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(i2s->clk)) {
-+ dev_err(&pdev->dev, "no clock defined\n");
-+ return PTR_ERR(i2s->clk);
-+ }
-+
-+ ret = clk_prepare_enable(i2s->clk);
-+ if (ret)
-+ return ret;
-+
-+ ralink_i2s_init_dma_data(i2s, res);
-+
-+ ret = device_reset(&pdev->dev);
-+ if (ret) {
-+ dev_err(&pdev->dev, "failed to reset device\n");
-+ goto err_clk_disable;
-+ }
-+
-+ ret = ralink_i2s_debugfs_create(i2s);
-+ if (ret) {
-+ dev_err(&pdev->dev, "create debugfs failed\n");
-+ goto err_clk_disable;
-+ }
-+
-+ /* enable 24bits support */
-+ if (i2s->flags & RALINK_FLAGS_24BIT) {
-+ ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE;
-+ ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE;
-+ }
-+
-+ /* enable big endian support */
-+ if (i2s->flags & RALINK_FLAGS_ENDIAN) {
-+ ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE;
-+ ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE;
-+ ralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE;
-+ if (i2s->flags & RALINK_FLAGS_24BIT) {
-+ ralink_i2s_dai.capture.formats |=
-+ SNDRV_PCM_FMTBIT_S24_BE;
-+ ralink_i2s_dai.playback.formats |=
-+ SNDRV_PCM_FMTBIT_S24_BE;
-+ ralink_pcm_hardware.formats |=
-+ SNDRV_PCM_FMTBIT_S24_BE;
-+ }
-+ }
-+
-+ /* disable capture support */
-+ if (i2s->flags & RALINK_FLAGS_TXONLY)
-+ memset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture),
-+ 0);
-+
-+ ret = devm_snd_soc_register_component(&pdev->dev, &ralink_i2s_component,
-+ &ralink_i2s_dai, 1);
-+ if (ret)
-+ goto err_debugfs;
-+
-+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
-+ &ralink_dmaengine_pcm_config,
-+ SND_DMAENGINE_PCM_FLAG_COMPAT);
-+ if (ret)
-+ goto err_debugfs;
-+
-+ dev_info(i2s->dev, "mclk %luMHz\n", clk_get_rate(i2s->clk) / 1000000);
-+
-+ return 0;
-+
-+err_debugfs:
-+ ralink_i2s_debugfs_remove(i2s);
-+
-+err_clk_disable:
-+ clk_disable_unprepare(i2s->clk);
-+
-+ return ret;
-+}
-+
-+static int ralink_i2s_remove(struct platform_device *pdev)
-+{
-+ struct ralink_i2s *i2s = platform_get_drvdata(pdev);
-+
-+ ralink_i2s_debugfs_remove(i2s);
-+ clk_disable_unprepare(i2s->clk);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver ralink_i2s_driver = {
-+ .probe = ralink_i2s_probe,
-+ .remove = ralink_i2s_remove,
-+ .driver = {
-+ .name = DRV_NAME,
-+ .of_match_table = ralink_i2s_match_table,
-+ },
-+};
-+module_platform_driver(ralink_i2s_driver);
-+
-+MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
-+MODULE_DESCRIPTION("Ralink/MediaTek I2S driver");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:" DRV_NAME);
+++ /dev/null
-From a7eb46e0ea4a11e4dfb56ab129bf816d1059a6c5 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:31:08 +0100
-Subject: [PATCH 51/53] serial: add ugly custom baud rate hack
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/tty/serial/serial_core.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/tty/serial/serial_core.c
-+++ b/drivers/tty/serial/serial_core.c
-@@ -445,6 +445,9 @@ uart_get_baud_rate(struct uart_port *por
- break;
- }
-
-+ if (tty_termios_baud_rate(termios) == 2500000)
-+ return 250000;
-+
- for (try = 0; try < 2; try++) {
- baud = tty_termios_baud_rate(termios);
-
+++ /dev/null
-From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 7 Dec 2015 17:16:50 +0100
-Subject: [PATCH 52/53] pwm: add mediatek support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/pwm/Kconfig | 9 +++
- drivers/pwm/Makefile | 1 +
- drivers/pwm/pwm-mediatek.c | 173 ++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 183 insertions(+)
- create mode 100644 drivers/pwm/pwm-mediatek.c
-
---- a/drivers/pwm/Kconfig
-+++ b/drivers/pwm/Kconfig
-@@ -393,6 +393,15 @@ config PWM_MEDIATEK
- To compile this driver as a module, choose M here: the module
- will be called pwm-mediatek.
-
-+config PWM_MEDIATEK_RAMIPS
-+ tristate "Mediatek PWM support"
-+ depends on RALINK && OF
-+ help
-+ Generic PWM framework driver for Mediatek ARM SoC.
-+
-+ To compile this driver as a module, choose M here: the module
-+ will be called pwm-mxs.
-+
- config PWM_MXS
- tristate "Freescale MXS PWM support"
- depends on ARCH_MXS || COMPILE_TEST
---- a/drivers/pwm/Makefile
-+++ b/drivers/pwm/Makefile
-@@ -34,6 +34,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p
- obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
- obj-$(CONFIG_PWM_MESON) += pwm-meson.o
- obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
-+obj-$(CONFIG_PWM_MEDIATEK_RAMIPS) += pwm-mediatek-ramips.o
- obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
- obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
- obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
---- /dev/null
-+++ b/drivers/pwm/pwm-mediatek-ramips.c
-@@ -0,0 +1,197 @@
-+/*
-+ * Mediatek Pulse Width Modulator driver
-+ *
-+ * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/ioport.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/pwm.h>
-+#include <linux/slab.h>
-+#include <linux/types.h>
-+
-+#define NUM_PWM 4
-+
-+/* PWM registers and bits definitions */
-+#define PWMCON 0x00
-+#define PWMHDUR 0x04
-+#define PWMLDUR 0x08
-+#define PWMGDUR 0x0c
-+#define PWMWAVENUM 0x28
-+#define PWMDWIDTH 0x2c
-+#define PWMTHRES 0x30
-+
-+/**
-+ * struct mtk_pwm_chip - struct representing pwm chip
-+ *
-+ * @mmio_base: base address of pwm chip
-+ * @chip: linux pwm chip representation
-+ */
-+struct mtk_pwm_chip {
-+ void __iomem *mmio_base;
-+ struct pwm_chip chip;
-+};
-+
-+static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
-+{
-+ return container_of(chip, struct mtk_pwm_chip, chip);
-+}
-+
-+static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
-+ unsigned long offset)
-+{
-+ return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
-+}
-+
-+static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
-+ unsigned int num, unsigned long offset,
-+ unsigned long val)
-+{
-+ iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
-+}
-+
-+static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
-+ int duty_ns, int period_ns)
-+{
-+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
-+ u32 resolution = 100 / 4;
-+ u32 clkdiv = 0;
-+
-+ while (period_ns / resolution > 8191) {
-+ clkdiv++;
-+ resolution *= 2;
-+ }
-+
-+ if (clkdiv > 7)
-+ return -1;
-+
-+ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
-+ mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
-+ mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
-+ return 0;
-+}
-+
-+static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
-+{
-+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
-+ u32 val;
-+
-+ val = ioread32(pc->mmio_base);
-+ val |= BIT(pwm->hwpwm);
-+ iowrite32(val, pc->mmio_base);
-+
-+ return 0;
-+}
-+
-+static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
-+{
-+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
-+ u32 val;
-+
-+ val = ioread32(pc->mmio_base);
-+ val &= ~BIT(pwm->hwpwm);
-+ iowrite32(val, pc->mmio_base);
-+}
-+
-+static int mtk_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
-+ const struct pwm_state *state)
-+{
-+ int err;
-+ bool enabled = pwm->state.enabled;
-+
-+ if (!state->enabled) {
-+ if (enabled)
-+ mtk_pwm_disable(chip, pwm);
-+
-+ return 0;
-+ }
-+
-+ err = mtk_pwm_config(pwm->chip, pwm,
-+ state->duty_cycle, state->period);
-+ if (err)
-+ return err;
-+
-+ if (!enabled)
-+ err = mtk_pwm_enable(chip, pwm);
-+
-+ return err;
-+}
-+
-+static const struct pwm_ops mtk_pwm_ops = {
-+ .apply = mtk_pwm_apply,
-+ .owner = THIS_MODULE,
-+};
-+
-+static int mtk_pwm_probe(struct platform_device *pdev)
-+{
-+ struct mtk_pwm_chip *pc;
-+ struct resource *r;
-+ int ret;
-+
-+ pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
-+ if (!pc)
-+ return -ENOMEM;
-+
-+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
-+ if (IS_ERR(pc->mmio_base))
-+ return PTR_ERR(pc->mmio_base);
-+
-+ platform_set_drvdata(pdev, pc);
-+
-+ pc->chip.dev = &pdev->dev;
-+ pc->chip.ops = &mtk_pwm_ops;
-+ pc->chip.base = -1;
-+ pc->chip.npwm = NUM_PWM;
-+
-+ ret = pwmchip_add(&pc->chip);
-+ if (ret < 0)
-+ dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
-+
-+ return ret;
-+}
-+
-+static int mtk_pwm_remove(struct platform_device *pdev)
-+{
-+ struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
-+ int i;
-+
-+ for (i = 0; i < NUM_PWM; i++)
-+ pwm_disable(&pc->chip.pwms[i]);
-+
-+ pwmchip_remove(&pc->chip);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mtk_pwm_of_match[] = {
-+ { .compatible = "mediatek,mt7628-pwm" },
-+ { }
-+};
-+
-+MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
-+
-+static struct platform_driver mtk_pwm_driver = {
-+ .driver = {
-+ .name = "mtk-pwm",
-+ .owner = THIS_MODULE,
-+ .of_match_table = mtk_pwm_of_match,
-+ },
-+ .probe = mtk_pwm_probe,
-+ .remove = mtk_pwm_remove,
-+};
-+
-+module_platform_driver(mtk_pwm_driver);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-+MODULE_ALIAS("platform:mtk-pwm");
+++ /dev/null
---- a/drivers/usb/dwc2/platform.c
-+++ b/drivers/usb/dwc2/platform.c
-@@ -462,6 +462,12 @@ static int dwc2_driver_probe(struct plat
- if (retval)
- return retval;
-
-+ /* Enable USB port before any regs access */
-+ if (readl(hsotg->regs + PCGCTL) & 0x0f) {
-+ writel(0x00, hsotg->regs + PCGCTL);
-+ /* TODO: mdelay(25) here? vendor driver don't use it */
-+ }
-+
- hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
-
- retval = dwc2_get_dr_mode(hsotg);
+++ /dev/null
---- a/drivers/misc/Makefile
-+++ b/drivers/misc/Makefile
-@@ -50,6 +50,7 @@ obj-$(CONFIG_ECHO) += echo/
- obj-$(CONFIG_CXL_BASE) += cxl/
- obj-$(CONFIG_DW_XDATA_PCIE) += dw-xdata-pcie.o
- obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
-+obj-$(CONFIG_SOC_MT7620) += linkit.o
- obj-$(CONFIG_OCXL) += ocxl/
- obj-$(CONFIG_BCM_VK) += bcm-vk/
- obj-y += cardreader/
---- /dev/null
-+++ b/drivers/misc/linkit.c
-@@ -0,0 +1,84 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * publishhed by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/of.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/gpio.h>
-+
-+#define LINKIT_LATCH_GPIO 11
-+
-+struct linkit_hw_data {
-+ char board[16];
-+ char rev[16];
-+};
-+
-+static void sanify_string(char *s)
-+{
-+ int i;
-+
-+ for (i = 0; i < 15; i++)
-+ if (s[i] <= 0x20)
-+ s[i] = '\0';
-+ s[15] = '\0';
-+}
-+
-+static int linkit_probe(struct platform_device *pdev)
-+{
-+ struct linkit_hw_data hw;
-+ struct mtd_info *mtd;
-+ size_t retlen;
-+ int ret;
-+
-+ mtd = get_mtd_device_nm("factory");
-+ if (IS_ERR(mtd))
-+ return PTR_ERR(mtd);
-+
-+ ret = mtd_read(mtd, 0x400, sizeof(hw), &retlen, (u_char *) &hw);
-+ put_mtd_device(mtd);
-+
-+ sanify_string(hw.board);
-+ sanify_string(hw.rev);
-+
-+ dev_info(&pdev->dev, "Version : %s\n", hw.board);
-+ dev_info(&pdev->dev, "Revision : %s\n", hw.rev);
-+
-+ if (!strcmp(hw.board, "LINKITS7688")) {
-+ dev_info(&pdev->dev, "setting up bootstrap latch\n");
-+
-+ if (devm_gpio_request(&pdev->dev, LINKIT_LATCH_GPIO, "bootstrap")) {
-+ dev_err(&pdev->dev, "failed to setup bootstrap gpio\n");
-+ return -1;
-+ }
-+ gpio_direction_output(LINKIT_LATCH_GPIO, 0);
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id linkit_match[] = {
-+ { .compatible = "mediatek,linkit" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, linkit_match);
-+
-+static struct platform_driver linkit_driver = {
-+ .probe = linkit_probe,
-+ .driver = {
-+ .name = "mtk-linkit",
-+ .owner = THIS_MODULE,
-+ .of_match_table = linkit_match,
-+ },
-+};
-+
-+int __init linkit_init(void)
-+{
-+ return platform_driver_register(&linkit_driver);
-+}
-+late_initcall_sync(linkit_init);
+++ /dev/null
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/Kconfig
-@@ -0,0 +1,64 @@
-+# SPDX-License-Identifier: GPL-2.0
-+config CRYPTO_DEV_EIP93_SKCIPHER
-+ tristate
-+
-+config CRYPTO_DEV_EIP93_HMAC
-+ tristate
-+
-+config CRYPTO_DEV_EIP93
-+ tristate "Support for EIP93 crypto HW accelerators"
-+ depends on SOC_MT7621 || COMPILE_TEST
-+ help
-+ EIP93 have various crypto HW accelerators. Select this if
-+ you want to use the EIP93 modules for any of the crypto algorithms.
-+
-+if CRYPTO_DEV_EIP93
-+
-+config CRYPTO_DEV_EIP93_AES
-+ bool "Register AES algorithm implementations with the Crypto API"
-+ default y
-+ select CRYPTO_DEV_EIP93_SKCIPHER
-+ select CRYPTO_LIB_AES
-+ select CRYPTO_SKCIPHER
-+ help
-+ Selecting this will offload AES - ECB, CBC and CTR crypto
-+ to the EIP-93 crypto engine.
-+
-+config CRYPTO_DEV_EIP93_DES
-+ bool "Register legacy DES / 3DES algorithm with the Crypto API"
-+ default y
-+ select CRYPTO_DEV_EIP93_SKCIPHER
-+ select CRYPTO_LIB_DES
-+ select CRYPTO_SKCIPHER
-+ help
-+ Selecting this will offload DES and 3DES ECB and CBC
-+ crypto to the EIP-93 crypto engine.
-+
-+config CRYPTO_DEV_EIP93_AEAD
-+ bool "Register AEAD algorithm with the Crypto API"
-+ default y
-+ select CRYPTO_DEV_EIP93_HMAC
-+ select CRYPTO_AEAD
-+ select CRYPTO_AUTHENC
-+ select CRYPTO_MD5
-+ select CRYPTO_SHA1
-+ select CRYPTO_SHA256
-+ help
-+ Selecting this will offload AEAD authenc(hmac(x), cipher(y))
-+ crypto to the EIP-93 crypto engine.
-+
-+config CRYPTO_DEV_EIP93_GENERIC_SW_MAX_LEN
-+ int "Max skcipher software fallback length"
-+ default 256
-+ help
-+ Max length of crypt request which
-+ will fallback to software crypt of skcipher *except* AES-128.
-+
-+config CRYPTO_DEV_EIP93_AES_128_SW_MAX_LEN
-+ int "Max AES-128 skcipher software fallback length"
-+ default 512
-+ help
-+ Max length of crypt request which
-+ will fallback to software crypt of AES-128 skcipher.
-+
-+endif
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/Makefile
-@@ -0,0 +1,7 @@
-+obj-$(CONFIG_CRYPTO_DEV_EIP93) += crypto-hw-eip93.o
-+
-+crypto-hw-eip93-y += eip93-main.o eip93-common.o
-+
-+crypto-hw-eip93-$(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER) += eip93-cipher.o
-+crypto-hw-eip93-$(CONFIG_CRYPTO_DEV_EIP93_AEAD) += eip93-aead.o
-+
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-aead.c
-@@ -0,0 +1,768 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+
-+#include <crypto/aead.h>
-+#include <crypto/aes.h>
-+#include <crypto/authenc.h>
-+#include <crypto/ctr.h>
-+#include <crypto/hmac.h>
-+#include <crypto/internal/aead.h>
-+#include <crypto/md5.h>
-+#include <crypto/null.h>
-+#include <crypto/sha1.h>
-+#include <crypto/sha2.h>
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+#include <crypto/internal/des.h>
-+#endif
-+
-+#include <linux/crypto.h>
-+#include <linux/dma-mapping.h>
-+
-+#include "eip93-aead.h"
-+#include "eip93-cipher.h"
-+#include "eip93-common.h"
-+#include "eip93-regs.h"
-+
-+void mtk_aead_handle_result(struct crypto_async_request *async, int err)
-+{
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
-+ struct mtk_device *mtk = ctx->mtk;
-+ struct aead_request *req = aead_request_cast(async);
-+ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
-+
-+ mtk_unmap_dma(mtk, rctx, req->src, req->dst);
-+ mtk_handle_result(mtk, rctx, req->iv);
-+
-+ if (err == 1)
-+ err = -EBADMSG;
-+ /* let software handle anti-replay errors */
-+ if (err == 4)
-+ err = 0;
-+
-+ aead_request_complete(req, err);
-+}
-+
-+static int mtk_aead_send_req(struct crypto_async_request *async)
-+{
-+ struct aead_request *req = aead_request_cast(async);
-+ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
-+ int err;
-+
-+ err = check_valid_request(rctx);
-+ if (err) {
-+ aead_request_complete(req, err);
-+ return err;
-+ }
-+
-+ return mtk_send_req(async, req->iv, rctx);
-+}
-+
-+/* Crypto aead API functions */
-+static int mtk_aead_cra_init(struct crypto_tfm *tfm)
-+{
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
-+ struct mtk_alg_template, alg.aead.base);
-+ u32 flags = tmpl->flags;
-+ char *alg_base;
-+
-+ crypto_aead_set_reqsize(__crypto_aead_cast(tfm),
-+ sizeof(struct mtk_cipher_reqctx));
-+
-+ ctx->mtk = tmpl->mtk;
-+ ctx->in_first = true;
-+ ctx->out_first = true;
-+
-+ ctx->sa_in = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
-+ if (!ctx->sa_in)
-+ return -ENOMEM;
-+
-+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+
-+ ctx->sa_out = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
-+ if (!ctx->sa_out)
-+ return -ENOMEM;
-+
-+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+
-+ /* software workaround for now */
-+ if (IS_HASH_MD5(flags))
-+ alg_base = "md5";
-+ if (IS_HASH_SHA1(flags))
-+ alg_base = "sha1";
-+ if (IS_HASH_SHA224(flags))
-+ alg_base = "sha224";
-+ if (IS_HASH_SHA256(flags))
-+ alg_base = "sha256";
-+
-+ ctx->shash = crypto_alloc_shash(alg_base, 0, CRYPTO_ALG_NEED_FALLBACK);
-+
-+ if (IS_ERR(ctx->shash)) {
-+ dev_err(ctx->mtk->dev, "base driver %s could not be loaded.\n",
-+ alg_base);
-+ return PTR_ERR(ctx->shash);
-+ }
-+
-+ return 0;
-+}
-+
-+static void mtk_aead_cra_exit(struct crypto_tfm *tfm)
-+{
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+
-+ if (ctx->shash)
-+ crypto_free_shash(ctx->shash);
-+
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+ kfree(ctx->sa_in);
-+ kfree(ctx->sa_out);
-+}
-+
-+static int mtk_aead_setkey(struct crypto_aead *ctfm, const u8 *key,
-+ unsigned int len)
-+{
-+ struct crypto_tfm *tfm = crypto_aead_tfm(ctfm);
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
-+ struct mtk_alg_template, alg.skcipher.base);
-+ u32 flags = tmpl->flags;
-+ u32 nonce = 0;
-+ struct crypto_authenc_keys keys;
-+ struct crypto_aes_ctx aes;
-+ struct saRecord_s *saRecord = ctx->sa_out;
-+ int sa_size = sizeof(struct saRecord_s);
-+ int err = -EINVAL;
-+
-+
-+ if (crypto_authenc_extractkeys(&keys, key, len))
-+ return err;
-+
-+ if (IS_RFC3686(flags)) {
-+ if (keys.enckeylen < CTR_RFC3686_NONCE_SIZE)
-+ return err;
-+
-+ keys.enckeylen -= CTR_RFC3686_NONCE_SIZE;
-+ memcpy(&nonce, keys.enckey + keys.enckeylen,
-+ CTR_RFC3686_NONCE_SIZE);
-+ }
-+
-+ switch ((flags & MTK_ALG_MASK)) {
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+ case MTK_ALG_DES:
-+ err = verify_aead_des_key(ctfm, keys.enckey, keys.enckeylen);
-+ break;
-+ case MTK_ALG_3DES:
-+ if (keys.enckeylen != DES3_EDE_KEY_SIZE)
-+ return -EINVAL;
-+
-+ err = verify_aead_des3_key(ctfm, keys.enckey, keys.enckeylen);
-+ break;
-+#endif
-+ case MTK_ALG_AES:
-+ err = aes_expandkey(&aes, keys.enckey, keys.enckeylen);
-+ }
-+ if (err)
-+ return err;
-+
-+ ctx->blksize = crypto_aead_blocksize(ctfm);
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, sa_size,
-+ DMA_TO_DEVICE);
-+
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, sa_size,
-+ DMA_TO_DEVICE);
-+ /* Encryption key */
-+ mtk_set_saRecord(saRecord, keys.enckeylen, flags);
-+ saRecord->saCmd0.bits.opCode = 1;
-+ saRecord->saCmd0.bits.digestLength = ctx->authsize >> 2;
-+
-+ memcpy(saRecord->saKey, keys.enckey, keys.enckeylen);
-+ ctx->saNonce = nonce;
-+ saRecord->saNonce = nonce;
-+
-+ /* authentication key */
-+ err = mtk_authenc_setkey(ctx->shash, saRecord, keys.authkey,
-+ keys.authkeylen);
-+
-+ saRecord->saCmd0.bits.direction = 0;
-+ memcpy(ctx->sa_in, saRecord, sa_size);
-+ ctx->sa_in->saCmd0.bits.direction = 1;
-+ ctx->sa_in->saCmd1.bits.copyDigest = 0;
-+
-+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, sa_size,
-+ DMA_TO_DEVICE);
-+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, sa_size,
-+ DMA_TO_DEVICE);
-+ ctx->in_first = true;
-+ ctx->out_first = true;
-+
-+ return err;
-+}
-+
-+static int mtk_aead_setauthsize(struct crypto_aead *ctfm,
-+ unsigned int authsize)
-+{
-+ struct crypto_tfm *tfm = crypto_aead_tfm(ctfm);
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+
-+ ctx->authsize = authsize;
-+ ctx->sa_in->saCmd0.bits.digestLength = ctx->authsize >> 2;
-+ ctx->sa_out->saCmd0.bits.digestLength = ctx->authsize >> 2;
-+
-+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+ return 0;
-+}
-+
-+static void mtk_aead_setassoc(struct mtk_crypto_ctx *ctx,
-+ struct aead_request *req, bool in)
-+{
-+ struct saRecord_s *saRecord;
-+
-+ if (in) {
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+ saRecord = ctx->sa_in;
-+ saRecord->saCmd1.bits.hashCryptOffset = req->assoclen >> 2;
-+
-+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+ ctx->assoclen_in = req->assoclen;
-+ } else {
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+ saRecord = ctx->sa_out;
-+ saRecord->saCmd1.bits.hashCryptOffset = req->assoclen >> 2;
-+
-+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+ ctx->assoclen_out = req->assoclen;
-+ }
-+}
-+
-+static int mtk_aead_crypt(struct aead_request *req)
-+{
-+ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
-+ struct crypto_async_request *async = &req->base;
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+ struct crypto_aead *aead = crypto_aead_reqtfm(req);
-+
-+ rctx->textsize = req->cryptlen;
-+ rctx->blksize = ctx->blksize;
-+ rctx->assoclen = req->assoclen;
-+ rctx->authsize = ctx->authsize;
-+ rctx->sg_src = req->src;
-+ rctx->sg_dst = req->dst;
-+ rctx->ivsize = crypto_aead_ivsize(aead);
-+ rctx->flags |= MTK_DESC_AEAD;
-+
-+ if IS_DECRYPT(rctx->flags)
-+ rctx->textsize -= rctx->authsize;
-+
-+ return mtk_aead_send_req(async);
-+}
-+
-+static int mtk_aead_encrypt(struct aead_request *req)
-+{
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
-+ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
-+ struct mtk_alg_template, alg.aead.base);
-+
-+ rctx->flags = tmpl->flags;
-+ rctx->flags |= MTK_ENCRYPT;
-+ if (ctx->out_first) {
-+ mtk_aead_setassoc(ctx, req, false);
-+ ctx->out_first = false;
-+ }
-+
-+ if (req->assoclen != ctx->assoclen_out) {
-+ dev_err(ctx->mtk->dev, "Request AAD length error\n");
-+ return -EINVAL;
-+ }
-+
-+ rctx->saRecord_base = ctx->sa_base_out;
-+
-+ return mtk_aead_crypt(req);
-+}
-+
-+static int mtk_aead_decrypt(struct aead_request *req)
-+{
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
-+ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
-+ struct mtk_alg_template, alg.aead.base);
-+
-+ rctx->flags = tmpl->flags;
-+ rctx->flags |= MTK_DECRYPT;
-+ if (ctx->in_first) {
-+ mtk_aead_setassoc(ctx, req, true);
-+ ctx->in_first = false;
-+ }
-+
-+ if (req->assoclen != ctx->assoclen_in) {
-+ dev_err(ctx->mtk->dev, "Request AAD length error\n");
-+ return -EINVAL;
-+ }
-+
-+ rctx->saRecord_base = ctx->sa_base_in;
-+
-+ return mtk_aead_crypt(req);
-+}
-+
-+/* Available authenc algorithms in this module */
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_aes = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_AES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = AES_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = MD5_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(md5),cbc(aes))",
-+ .cra_driver_name =
-+ "authenc(hmac(md5-eip93), cbc(aes-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = AES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_aes = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_AES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = AES_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA1_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha1),cbc(aes))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha1-eip93),cbc(aes-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = AES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_aes = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_AES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = AES_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA224_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha224),cbc(aes))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha224-eip93),cbc(aes-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = AES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_aes = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_AES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = AES_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA256_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha256),cbc(aes))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha256-eip93),cbc(aes-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = AES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_md5_rfc3686_aes = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 |
-+ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = CTR_RFC3686_IV_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = MD5_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(md5),rfc3686(ctr(aes)))",
-+ .cra_driver_name =
-+ "authenc(hmac(md5-eip93),rfc3686(ctr(aes-eip93)))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = 1,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_rfc3686_aes = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 |
-+ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = CTR_RFC3686_IV_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA1_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha1),rfc3686(ctr(aes)))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha1-eip93),rfc3686(ctr(aes-eip93)))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = 1,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_rfc3686_aes = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 |
-+ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = CTR_RFC3686_IV_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA224_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha224),rfc3686(ctr(aes)))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha224-eip93),rfc3686(ctr(aes-eip93)))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = 1,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_rfc3686_aes = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 |
-+ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = CTR_RFC3686_IV_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA256_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha256),rfc3686(ctr(aes)))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha256-eip93),rfc3686(ctr(aes-eip93)))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = 1,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_DES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = DES_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = MD5_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(md5),cbc(des))",
-+ .cra_driver_name =
-+ "authenc(hmac(md5-eip93),cbc(des-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_DES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = DES_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA1_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha1),cbc(des))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha1-eip93),cbc(des-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_DES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = DES_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA224_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha224),cbc(des))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha224-eip93),cbc(des-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_DES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = DES_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA256_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha256),cbc(des))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha256-eip93),cbc(des-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des3_ede = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_3DES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = DES3_EDE_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = MD5_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
-+ .cra_driver_name =
-+ "authenc(hmac(md5-eip93),cbc(des3_ede-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0x0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des3_ede = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_3DES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = DES3_EDE_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA1_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha1-eip93),cbc(des3_ede-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0x0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des3_ede = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_3DES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = DES3_EDE_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA224_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha224-eip93),cbc(des3_ede-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0x0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des3_ede = {
-+ .type = MTK_ALG_TYPE_AEAD,
-+ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_3DES,
-+ .alg.aead = {
-+ .setkey = mtk_aead_setkey,
-+ .encrypt = mtk_aead_encrypt,
-+ .decrypt = mtk_aead_decrypt,
-+ .ivsize = DES3_EDE_BLOCK_SIZE,
-+ .setauthsize = mtk_aead_setauthsize,
-+ .maxauthsize = SHA256_DIGEST_SIZE,
-+ .base = {
-+ .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
-+ .cra_driver_name =
-+ "authenc(hmac(sha256-eip93),cbc(des3_ede-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0x0,
-+ .cra_init = mtk_aead_cra_init,
-+ .cra_exit = mtk_aead_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+#endif
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-aead.h
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef _EIP93_AEAD_H_
-+#define _EIP93_AEAD_H_
-+
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_rfc3686_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_rfc3686_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_rfc3686_aes;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_rfc3686_aes;
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des3_ede;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des3_ede;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des3_ede;
-+extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des3_ede;
-+#endif
-+
-+void mtk_aead_handle_result(struct crypto_async_request *async, int err);
-+
-+#endif /* _EIP93_AEAD_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-aes.h
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef _EIP93_AES_H_
-+#define _EIP93_AES_H_
-+
-+extern struct mtk_alg_template mtk_alg_ecb_aes;
-+extern struct mtk_alg_template mtk_alg_cbc_aes;
-+extern struct mtk_alg_template mtk_alg_ctr_aes;
-+extern struct mtk_alg_template mtk_alg_rfc3686_aes;
-+
-+#endif /* _EIP93_AES_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-cipher.c
-@@ -0,0 +1,483 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+#include <crypto/aes.h>
-+#include <crypto/ctr.h>
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+#include <crypto/internal/des.h>
-+#endif
-+#include <linux/dma-mapping.h>
-+
-+#include "eip93-cipher.h"
-+#include "eip93-common.h"
-+#include "eip93-regs.h"
-+
-+void mtk_skcipher_handle_result(struct crypto_async_request *async, int err)
-+{
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
-+ struct mtk_device *mtk = ctx->mtk;
-+ struct skcipher_request *req = skcipher_request_cast(async);
-+ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
-+
-+ mtk_unmap_dma(mtk, rctx, req->src, req->dst);
-+ mtk_handle_result(mtk, rctx, req->iv);
-+
-+ skcipher_request_complete(req, err);
-+}
-+
-+static inline bool mtk_skcipher_is_fallback(const struct crypto_tfm *tfm,
-+ u32 flags)
-+{
-+ return (tfm->__crt_alg->cra_flags & CRYPTO_ALG_NEED_FALLBACK) &&
-+ !IS_RFC3686(flags);
-+}
-+
-+static int mtk_skcipher_send_req(struct crypto_async_request *async)
-+{
-+ struct skcipher_request *req = skcipher_request_cast(async);
-+ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
-+ int err;
-+
-+ err = check_valid_request(rctx);
-+
-+ if (err) {
-+ skcipher_request_complete(req, err);
-+ return err;
-+ }
-+
-+ return mtk_send_req(async, req->iv, rctx);
-+}
-+
-+/* Crypto skcipher API functions */
-+static int mtk_skcipher_cra_init(struct crypto_tfm *tfm)
-+{
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
-+ struct mtk_alg_template, alg.skcipher.base);
-+ bool fallback = mtk_skcipher_is_fallback(tfm, tmpl->flags);
-+
-+ if (fallback) {
-+ ctx->fallback = crypto_alloc_skcipher(
-+ crypto_tfm_alg_name(tfm), 0, CRYPTO_ALG_NEED_FALLBACK);
-+ if (IS_ERR(ctx->fallback))
-+ return PTR_ERR(ctx->fallback);
-+ }
-+
-+ crypto_skcipher_set_reqsize(
-+ __crypto_skcipher_cast(tfm),
-+ sizeof(struct mtk_cipher_reqctx) +
-+ (fallback ? crypto_skcipher_reqsize(ctx->fallback) :
-+ 0));
-+
-+ ctx->mtk = tmpl->mtk;
-+
-+ ctx->sa_in = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
-+ if (!ctx->sa_in)
-+ return -ENOMEM;
-+
-+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+
-+ ctx->sa_out = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
-+ if (!ctx->sa_out)
-+ return -ENOMEM;
-+
-+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+ return 0;
-+}
-+
-+static void mtk_skcipher_cra_exit(struct crypto_tfm *tfm)
-+{
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
-+ sizeof(struct saRecord_s), DMA_TO_DEVICE);
-+ kfree(ctx->sa_in);
-+ kfree(ctx->sa_out);
-+
-+ crypto_free_skcipher(ctx->fallback);
-+}
-+
-+static int mtk_skcipher_setkey(struct crypto_skcipher *ctfm, const u8 *key,
-+ unsigned int len)
-+{
-+ struct crypto_tfm *tfm = crypto_skcipher_tfm(ctfm);
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
-+ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
-+ struct mtk_alg_template, alg.skcipher.base);
-+ struct saRecord_s *saRecord = ctx->sa_out;
-+ u32 flags = tmpl->flags;
-+ u32 nonce = 0;
-+ unsigned int keylen = len;
-+ int sa_size = sizeof(struct saRecord_s);
-+ int err = -EINVAL;
-+
-+ if (!key || !keylen)
-+ return err;
-+
-+ ctx->keylen = keylen;
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+ if (IS_RFC3686(flags)) {
-+ if (len < CTR_RFC3686_NONCE_SIZE)
-+ return err;
-+
-+ keylen = len - CTR_RFC3686_NONCE_SIZE;
-+ memcpy(&nonce, key + keylen, CTR_RFC3686_NONCE_SIZE);
-+ }
-+#endif
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+ if (flags & MTK_ALG_DES) {
-+ ctx->blksize = DES_BLOCK_SIZE;
-+ err = verify_skcipher_des_key(ctfm, key);
-+ }
-+ if (flags & MTK_ALG_3DES) {
-+ ctx->blksize = DES3_EDE_BLOCK_SIZE;
-+ err = verify_skcipher_des3_key(ctfm, key);
-+ }
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+ if (flags & MTK_ALG_AES) {
-+ struct crypto_aes_ctx aes;
-+ bool fallback = mtk_skcipher_is_fallback(tfm, flags);
-+
-+ if (fallback && !IS_RFC3686(flags)) {
-+ err = crypto_skcipher_setkey(ctx->fallback, key,
-+ keylen);
-+ if (err)
-+ return err;
-+ }
-+
-+ ctx->blksize = AES_BLOCK_SIZE;
-+ err = aes_expandkey(&aes, key, keylen);
-+ }
-+#endif
-+ if (err)
-+ return err;
-+
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, sa_size,
-+ DMA_TO_DEVICE);
-+
-+ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, sa_size,
-+ DMA_TO_DEVICE);
-+
-+ mtk_set_saRecord(saRecord, keylen, flags);
-+
-+ memcpy(saRecord->saKey, key, keylen);
-+ ctx->saNonce = nonce;
-+ saRecord->saNonce = nonce;
-+ saRecord->saCmd0.bits.direction = 0;
-+
-+ memcpy(ctx->sa_in, saRecord, sa_size);
-+ ctx->sa_in->saCmd0.bits.direction = 1;
-+
-+ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, sa_size,
-+ DMA_TO_DEVICE);
-+
-+ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, sa_size,
-+ DMA_TO_DEVICE);
-+ return err;
-+}
-+
-+static int mtk_skcipher_crypt(struct skcipher_request *req, bool encrypt)
-+{
-+ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
-+ struct crypto_async_request *async = &req->base;
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+ struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
-+ bool fallback = mtk_skcipher_is_fallback(req->base.tfm, rctx->flags);
-+
-+ if (!req->cryptlen)
-+ return 0;
-+
-+ /*
-+ * ECB and CBC algorithms require message lengths to be
-+ * multiples of block size.
-+ */
-+ if (IS_ECB(rctx->flags) || IS_CBC(rctx->flags))
-+ if (!IS_ALIGNED(req->cryptlen,
-+ crypto_skcipher_blocksize(skcipher)))
-+ return -EINVAL;
-+
-+ if (fallback &&
-+ req->cryptlen <= (AES_KEYSIZE_128 ?
-+ CONFIG_CRYPTO_DEV_EIP93_AES_128_SW_MAX_LEN :
-+ CONFIG_CRYPTO_DEV_EIP93_GENERIC_SW_MAX_LEN)) {
-+ skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
-+ skcipher_request_set_callback(&rctx->fallback_req,
-+ req->base.flags,
-+ req->base.complete,
-+ req->base.data);
-+ skcipher_request_set_crypt(&rctx->fallback_req, req->src,
-+ req->dst, req->cryptlen, req->iv);
-+ return encrypt ? crypto_skcipher_encrypt(&rctx->fallback_req) :
-+ crypto_skcipher_decrypt(&rctx->fallback_req);
-+ }
-+
-+ rctx->assoclen = 0;
-+ rctx->textsize = req->cryptlen;
-+ rctx->authsize = 0;
-+ rctx->sg_src = req->src;
-+ rctx->sg_dst = req->dst;
-+ rctx->ivsize = crypto_skcipher_ivsize(skcipher);
-+ rctx->blksize = ctx->blksize;
-+ rctx->flags |= MTK_DESC_SKCIPHER;
-+ if (!IS_ECB(rctx->flags))
-+ rctx->flags |= MTK_DESC_DMA_IV;
-+
-+ return mtk_skcipher_send_req(async);
-+}
-+
-+static int mtk_skcipher_encrypt(struct skcipher_request *req)
-+{
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
-+ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
-+ struct mtk_alg_template, alg.skcipher.base);
-+
-+ rctx->flags = tmpl->flags;
-+ rctx->flags |= MTK_ENCRYPT;
-+ rctx->saRecord_base = ctx->sa_base_out;
-+
-+ return mtk_skcipher_crypt(req, true);
-+}
-+
-+static int mtk_skcipher_decrypt(struct skcipher_request *req)
-+{
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
-+ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
-+ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
-+ struct mtk_alg_template, alg.skcipher.base);
-+
-+ rctx->flags = tmpl->flags;
-+ rctx->flags |= MTK_DECRYPT;
-+ rctx->saRecord_base = ctx->sa_base_in;
-+
-+ return mtk_skcipher_crypt(req, false);
-+}
-+
-+/* Available algorithms in this module */
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+struct mtk_alg_template mtk_alg_ecb_aes = {
-+ .type = MTK_ALG_TYPE_SKCIPHER,
-+ .flags = MTK_MODE_ECB | MTK_ALG_AES,
-+ .alg.skcipher = {
-+ .setkey = mtk_skcipher_setkey,
-+ .encrypt = mtk_skcipher_encrypt,
-+ .decrypt = mtk_skcipher_decrypt,
-+ .min_keysize = AES_MIN_KEY_SIZE,
-+ .max_keysize = AES_MAX_KEY_SIZE,
-+ .ivsize = 0,
-+ .base = {
-+ .cra_name = "ecb(aes)",
-+ .cra_driver_name = "ecb(aes-eip93)",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_NEED_FALLBACK |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = AES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0xf,
-+ .cra_init = mtk_skcipher_cra_init,
-+ .cra_exit = mtk_skcipher_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_cbc_aes = {
-+ .type = MTK_ALG_TYPE_SKCIPHER,
-+ .flags = MTK_MODE_CBC | MTK_ALG_AES,
-+ .alg.skcipher = {
-+ .setkey = mtk_skcipher_setkey,
-+ .encrypt = mtk_skcipher_encrypt,
-+ .decrypt = mtk_skcipher_decrypt,
-+ .min_keysize = AES_MIN_KEY_SIZE,
-+ .max_keysize = AES_MAX_KEY_SIZE,
-+ .ivsize = AES_BLOCK_SIZE,
-+ .base = {
-+ .cra_name = "cbc(aes)",
-+ .cra_driver_name = "cbc(aes-eip93)",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_NEED_FALLBACK |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = AES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0xf,
-+ .cra_init = mtk_skcipher_cra_init,
-+ .cra_exit = mtk_skcipher_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_ctr_aes = {
-+ .type = MTK_ALG_TYPE_SKCIPHER,
-+ .flags = MTK_MODE_CTR | MTK_ALG_AES,
-+ .alg.skcipher = {
-+ .setkey = mtk_skcipher_setkey,
-+ .encrypt = mtk_skcipher_encrypt,
-+ .decrypt = mtk_skcipher_decrypt,
-+ .min_keysize = AES_MIN_KEY_SIZE,
-+ .max_keysize = AES_MAX_KEY_SIZE,
-+ .ivsize = AES_BLOCK_SIZE,
-+ .base = {
-+ .cra_name = "ctr(aes)",
-+ .cra_driver_name = "ctr(aes-eip93)",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_NEED_FALLBACK |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = 1,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0xf,
-+ .cra_init = mtk_skcipher_cra_init,
-+ .cra_exit = mtk_skcipher_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_rfc3686_aes = {
-+ .type = MTK_ALG_TYPE_SKCIPHER,
-+ .flags = MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
-+ .alg.skcipher = {
-+ .setkey = mtk_skcipher_setkey,
-+ .encrypt = mtk_skcipher_encrypt,
-+ .decrypt = mtk_skcipher_decrypt,
-+ .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
-+ .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
-+ .ivsize = CTR_RFC3686_IV_SIZE,
-+ .base = {
-+ .cra_name = "rfc3686(ctr(aes))",
-+ .cra_driver_name = "rfc3686(ctr(aes-eip93))",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_NEED_FALLBACK |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = 1,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0xf,
-+ .cra_init = mtk_skcipher_cra_init,
-+ .cra_exit = mtk_skcipher_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+struct mtk_alg_template mtk_alg_ecb_des = {
-+ .type = MTK_ALG_TYPE_SKCIPHER,
-+ .flags = MTK_MODE_ECB | MTK_ALG_DES,
-+ .alg.skcipher = {
-+ .setkey = mtk_skcipher_setkey,
-+ .encrypt = mtk_skcipher_encrypt,
-+ .decrypt = mtk_skcipher_decrypt,
-+ .min_keysize = DES_KEY_SIZE,
-+ .max_keysize = DES_KEY_SIZE,
-+ .ivsize = 0,
-+ .base = {
-+ .cra_name = "ecb(des)",
-+ .cra_driver_name = "ebc(des-eip93)",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_skcipher_cra_init,
-+ .cra_exit = mtk_skcipher_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_cbc_des = {
-+ .type = MTK_ALG_TYPE_SKCIPHER,
-+ .flags = MTK_MODE_CBC | MTK_ALG_DES,
-+ .alg.skcipher = {
-+ .setkey = mtk_skcipher_setkey,
-+ .encrypt = mtk_skcipher_encrypt,
-+ .decrypt = mtk_skcipher_decrypt,
-+ .min_keysize = DES_KEY_SIZE,
-+ .max_keysize = DES_KEY_SIZE,
-+ .ivsize = DES_BLOCK_SIZE,
-+ .base = {
-+ .cra_name = "cbc(des)",
-+ .cra_driver_name = "cbc(des-eip93)",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_skcipher_cra_init,
-+ .cra_exit = mtk_skcipher_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_ecb_des3_ede = {
-+ .type = MTK_ALG_TYPE_SKCIPHER,
-+ .flags = MTK_MODE_ECB | MTK_ALG_3DES,
-+ .alg.skcipher = {
-+ .setkey = mtk_skcipher_setkey,
-+ .encrypt = mtk_skcipher_encrypt,
-+ .decrypt = mtk_skcipher_decrypt,
-+ .min_keysize = DES3_EDE_KEY_SIZE,
-+ .max_keysize = DES3_EDE_KEY_SIZE,
-+ .ivsize = 0,
-+ .base = {
-+ .cra_name = "ecb(des3_ede)",
-+ .cra_driver_name = "ecb(des3_ede-eip93)",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_skcipher_cra_init,
-+ .cra_exit = mtk_skcipher_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+
-+struct mtk_alg_template mtk_alg_cbc_des3_ede = {
-+ .type = MTK_ALG_TYPE_SKCIPHER,
-+ .flags = MTK_MODE_CBC | MTK_ALG_3DES,
-+ .alg.skcipher = {
-+ .setkey = mtk_skcipher_setkey,
-+ .encrypt = mtk_skcipher_encrypt,
-+ .decrypt = mtk_skcipher_decrypt,
-+ .min_keysize = DES3_EDE_KEY_SIZE,
-+ .max_keysize = DES3_EDE_KEY_SIZE,
-+ .ivsize = DES3_EDE_BLOCK_SIZE,
-+ .base = {
-+ .cra_name = "cbc(des3_ede)",
-+ .cra_driver_name = "cbc(des3_ede-eip93)",
-+ .cra_priority = MTK_CRA_PRIORITY,
-+ .cra_flags = CRYPTO_ALG_ASYNC |
-+ CRYPTO_ALG_KERN_DRIVER_ONLY,
-+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
-+ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
-+ .cra_alignmask = 0,
-+ .cra_init = mtk_skcipher_cra_init,
-+ .cra_exit = mtk_skcipher_cra_exit,
-+ .cra_module = THIS_MODULE,
-+ },
-+ },
-+};
-+#endif
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-cipher.h
-@@ -0,0 +1,66 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef _EIP93_CIPHER_H_
-+#define _EIP93_CIPHER_H_
-+
-+#include "eip93-main.h"
-+
-+struct mtk_crypto_ctx {
-+ struct mtk_device *mtk;
-+ struct saRecord_s *sa_in;
-+ dma_addr_t sa_base_in;
-+ struct saRecord_s *sa_out;
-+ dma_addr_t sa_base_out;
-+ uint32_t saNonce;
-+ int blksize;
-+ /* AEAD specific */
-+ unsigned int authsize;
-+ unsigned int assoclen_in;
-+ unsigned int assoclen_out;
-+ bool in_first;
-+ bool out_first;
-+ struct crypto_shash *shash;
-+ unsigned int keylen;
-+ struct crypto_skcipher *fallback;
-+};
-+
-+struct mtk_cipher_reqctx {
-+ unsigned long flags;
-+ unsigned int blksize;
-+ unsigned int ivsize;
-+ unsigned int textsize;
-+ unsigned int assoclen;
-+ unsigned int authsize;
-+ dma_addr_t saRecord_base;
-+ struct saState_s *saState;
-+ dma_addr_t saState_base;
-+ uint32_t saState_idx;
-+ struct eip93_descriptor_s *cdesc;
-+ struct scatterlist *sg_src;
-+ struct scatterlist *sg_dst;
-+ int src_nents;
-+ int dst_nents;
-+ struct saState_s *saState_ctr;
-+ dma_addr_t saState_base_ctr;
-+ uint32_t saState_ctr_idx;
-+ struct skcipher_request fallback_req; // keep at the end
-+};
-+
-+int check_valid_request(struct mtk_cipher_reqctx *rctx);
-+
-+void mtk_unmap_dma(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
-+ struct scatterlist *reqsrc, struct scatterlist *reqdst);
-+
-+void mtk_skcipher_handle_result(struct crypto_async_request *async, int err);
-+
-+int mtk_send_req(struct crypto_async_request *async,
-+ const u8 *reqiv, struct mtk_cipher_reqctx *rctx);
-+
-+void mtk_handle_result(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
-+ u8 *reqiv);
-+
-+#endif /* _EIP93_CIPHER_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-common.c
-@@ -0,0 +1,749 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+
-+#include <crypto/aes.h>
-+#include <crypto/ctr.h>
-+#include <crypto/hmac.h>
-+#include <crypto/sha1.h>
-+#include <crypto/sha2.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/scatterlist.h>
-+
-+#include "eip93-cipher.h"
-+#include "eip93-common.h"
-+#include "eip93-main.h"
-+#include "eip93-regs.h"
-+
-+inline void *mtk_ring_next_wptr(struct mtk_device *mtk,
-+ struct mtk_desc_ring *ring)
-+{
-+ void *ptr = ring->write;
-+
-+ if ((ring->write == ring->read - ring->offset) ||
-+ (ring->read == ring->base && ring->write == ring->base_end))
-+ return ERR_PTR(-ENOMEM);
-+
-+ if (ring->write == ring->base_end)
-+ ring->write = ring->base;
-+ else
-+ ring->write += ring->offset;
-+
-+ return ptr;
-+}
-+
-+inline void *mtk_ring_next_rptr(struct mtk_device *mtk,
-+ struct mtk_desc_ring *ring)
-+{
-+ void *ptr = ring->read;
-+
-+ if (ring->write == ring->read)
-+ return ERR_PTR(-ENOENT);
-+
-+ if (ring->read == ring->base_end)
-+ ring->read = ring->base;
-+ else
-+ ring->read += ring->offset;
-+
-+ return ptr;
-+}
-+
-+inline int mtk_put_descriptor(struct mtk_device *mtk,
-+ struct eip93_descriptor_s *desc)
-+{
-+ struct eip93_descriptor_s *cdesc;
-+ struct eip93_descriptor_s *rdesc;
-+ unsigned long irqflags;
-+
-+ spin_lock_irqsave(&mtk->ring->write_lock, irqflags);
-+
-+ rdesc = mtk_ring_next_wptr(mtk, &mtk->ring->rdr);
-+
-+ if (IS_ERR(rdesc)) {
-+ spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
-+ return -ENOENT;
-+ }
-+
-+ cdesc = mtk_ring_next_wptr(mtk, &mtk->ring->cdr);
-+
-+ if (IS_ERR(cdesc)) {
-+ spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
-+ return -ENOENT;
-+ }
-+
-+ memset(rdesc, 0, sizeof(struct eip93_descriptor_s));
-+ memcpy(cdesc, desc, sizeof(struct eip93_descriptor_s));
-+
-+ atomic_dec(&mtk->ring->free);
-+ spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
-+
-+ return 0;
-+}
-+
-+inline void *mtk_get_descriptor(struct mtk_device *mtk)
-+{
-+ struct eip93_descriptor_s *cdesc;
-+ void *ptr;
-+ unsigned long irqflags;
-+
-+ spin_lock_irqsave(&mtk->ring->read_lock, irqflags);
-+
-+ cdesc = mtk_ring_next_rptr(mtk, &mtk->ring->cdr);
-+
-+ if (IS_ERR(cdesc)) {
-+ spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
-+ return ERR_PTR(-ENOENT);
-+ }
-+
-+ memset(cdesc, 0, sizeof(struct eip93_descriptor_s));
-+
-+ ptr = mtk_ring_next_rptr(mtk, &mtk->ring->rdr);
-+ if (IS_ERR(ptr)) {
-+ spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
-+ return ERR_PTR(-ENOENT);
-+ }
-+
-+ atomic_inc(&mtk->ring->free);
-+ spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
-+
-+ return ptr;
-+}
-+
-+inline int mtk_get_free_saState(struct mtk_device *mtk)
-+{
-+ struct mtk_state_pool *saState_pool;
-+ int i;
-+
-+ for (i = 0; i < MTK_RING_SIZE; i++) {
-+ saState_pool = &mtk->ring->saState_pool[i];
-+ if (saState_pool->in_use == false) {
-+ saState_pool->in_use = true;
-+ return i;
-+ }
-+
-+ }
-+
-+ return -ENOENT;
-+}
-+
-+static inline void mtk_free_sg_copy(const int len, struct scatterlist **sg)
-+{
-+ if (!*sg || !len)
-+ return;
-+
-+ free_pages((unsigned long)sg_virt(*sg), get_order(len));
-+ kfree(*sg);
-+ *sg = NULL;
-+}
-+
-+static inline int mtk_make_sg_copy(struct scatterlist *src,
-+ struct scatterlist **dst,
-+ const uint32_t len, const bool copy)
-+{
-+ void *pages;
-+
-+ *dst = kmalloc(sizeof(**dst), GFP_KERNEL);
-+ if (!*dst)
-+ return -ENOMEM;
-+
-+
-+ pages = (void *)__get_free_pages(GFP_KERNEL | GFP_DMA,
-+ get_order(len));
-+
-+ if (!pages) {
-+ kfree(*dst);
-+ *dst = NULL;
-+ return -ENOMEM;
-+ }
-+
-+ sg_init_table(*dst, 1);
-+ sg_set_buf(*dst, pages, len);
-+
-+ /* copy only as requested */
-+ if (copy)
-+ sg_copy_to_buffer(src, sg_nents(src), pages, len);
-+
-+ return 0;
-+}
-+
-+static inline bool mtk_is_sg_aligned(struct scatterlist *sg, u32 len,
-+ const int blksize)
-+{
-+ int nents;
-+
-+ for (nents = 0; sg; sg = sg_next(sg), ++nents) {
-+ if (!IS_ALIGNED(sg->offset, 4))
-+ return false;
-+
-+ if (len <= sg->length) {
-+ if (!IS_ALIGNED(len, blksize))
-+ return false;
-+
-+ return true;
-+ }
-+
-+ if (!IS_ALIGNED(sg->length, blksize))
-+ return false;
-+
-+ len -= sg->length;
-+ }
-+ return false;
-+}
-+
-+int check_valid_request(struct mtk_cipher_reqctx *rctx)
-+{
-+ struct scatterlist *src = rctx->sg_src;
-+ struct scatterlist *dst = rctx->sg_dst;
-+ uint32_t src_nents, dst_nents;
-+ u32 textsize = rctx->textsize;
-+ u32 authsize = rctx->authsize;
-+ u32 blksize = rctx->blksize;
-+ u32 totlen_src = rctx->assoclen + rctx->textsize;
-+ u32 totlen_dst = rctx->assoclen + rctx->textsize;
-+ u32 copy_len;
-+ bool src_align, dst_align;
-+ int err = -EINVAL;
-+
-+ if (!IS_CTR(rctx->flags)) {
-+ if (!IS_ALIGNED(textsize, blksize))
-+ return err;
-+ }
-+
-+ if (authsize) {
-+ if (IS_ENCRYPT(rctx->flags))
-+ totlen_dst += authsize;
-+ else
-+ totlen_src += authsize;
-+ }
-+
-+ src_nents = sg_nents_for_len(src, totlen_src);
-+ dst_nents = sg_nents_for_len(dst, totlen_dst);
-+
-+ if (src == dst) {
-+ src_nents = max(src_nents, dst_nents);
-+ dst_nents = src_nents;
-+ if (unlikely((totlen_src || totlen_dst) && (src_nents <= 0)))
-+ return err;
-+
-+ } else {
-+ if (unlikely(totlen_src && (src_nents <= 0)))
-+ return err;
-+
-+ if (unlikely(totlen_dst && (dst_nents <= 0)))
-+ return err;
-+ }
-+
-+ if (authsize) {
-+ if (dst_nents == 1 && src_nents == 1) {
-+ src_align = mtk_is_sg_aligned(src, totlen_src, blksize);
-+ if (src == dst)
-+ dst_align = src_align;
-+ else
-+ dst_align = mtk_is_sg_aligned(dst,
-+ totlen_dst, blksize);
-+ } else {
-+ src_align = false;
-+ dst_align = false;
-+ }
-+ } else {
-+ src_align = mtk_is_sg_aligned(src, totlen_src, blksize);
-+ if (src == dst)
-+ dst_align = src_align;
-+ else
-+ dst_align = mtk_is_sg_aligned(dst, totlen_dst, blksize);
-+ }
-+
-+ copy_len = max(totlen_src, totlen_dst);
-+ if (!src_align) {
-+ err = mtk_make_sg_copy(src, &rctx->sg_src, copy_len, true);
-+ if (err)
-+ return err;
-+ }
-+
-+ if (!dst_align) {
-+ err = mtk_make_sg_copy(dst, &rctx->sg_dst, copy_len, false);
-+ if (err)
-+ return err;
-+ }
-+
-+ rctx->src_nents = sg_nents_for_len(rctx->sg_src, totlen_src);
-+ rctx->dst_nents = sg_nents_for_len(rctx->sg_dst, totlen_dst);
-+
-+ return 0;
-+}
-+/*
-+ * Set saRecord function:
-+ * Even saRecord is set to "0", keep " = 0" for readability.
-+ */
-+void mtk_set_saRecord(struct saRecord_s *saRecord, const unsigned int keylen,
-+ const u32 flags)
-+{
-+ saRecord->saCmd0.bits.ivSource = 2;
-+ if (IS_ECB(flags))
-+ saRecord->saCmd0.bits.saveIv = 0;
-+ else
-+ saRecord->saCmd0.bits.saveIv = 1;
-+
-+ saRecord->saCmd0.bits.opGroup = 0;
-+ saRecord->saCmd0.bits.opCode = 0;
-+
-+ switch ((flags & MTK_ALG_MASK)) {
-+ case MTK_ALG_AES:
-+ saRecord->saCmd0.bits.cipher = 3;
-+ saRecord->saCmd1.bits.aesKeyLen = keylen >> 3;
-+ break;
-+ case MTK_ALG_3DES:
-+ saRecord->saCmd0.bits.cipher = 1;
-+ break;
-+ case MTK_ALG_DES:
-+ saRecord->saCmd0.bits.cipher = 0;
-+ break;
-+ default:
-+ saRecord->saCmd0.bits.cipher = 15;
-+ }
-+
-+ switch ((flags & MTK_HASH_MASK)) {
-+ case MTK_HASH_SHA256:
-+ saRecord->saCmd0.bits.hash = 3;
-+ break;
-+ case MTK_HASH_SHA224:
-+ saRecord->saCmd0.bits.hash = 2;
-+ break;
-+ case MTK_HASH_SHA1:
-+ saRecord->saCmd0.bits.hash = 1;
-+ break;
-+ case MTK_HASH_MD5:
-+ saRecord->saCmd0.bits.hash = 0;
-+ break;
-+ default:
-+ saRecord->saCmd0.bits.hash = 15;
-+ }
-+
-+ saRecord->saCmd0.bits.hdrProc = 0;
-+ saRecord->saCmd0.bits.padType = 3;
-+ saRecord->saCmd0.bits.extPad = 0;
-+ saRecord->saCmd0.bits.scPad = 0;
-+
-+ switch ((flags & MTK_MODE_MASK)) {
-+ case MTK_MODE_CBC:
-+ saRecord->saCmd1.bits.cipherMode = 1;
-+ break;
-+ case MTK_MODE_CTR:
-+ saRecord->saCmd1.bits.cipherMode = 2;
-+ break;
-+ case MTK_MODE_ECB:
-+ saRecord->saCmd1.bits.cipherMode = 0;
-+ break;
-+ }
-+
-+ saRecord->saCmd1.bits.byteOffset = 0;
-+ saRecord->saCmd1.bits.hashCryptOffset = 0;
-+ saRecord->saCmd0.bits.digestLength = 0;
-+ saRecord->saCmd1.bits.copyPayload = 0;
-+
-+ if (IS_HMAC(flags)) {
-+ saRecord->saCmd1.bits.hmac = 1;
-+ saRecord->saCmd1.bits.copyDigest = 1;
-+ saRecord->saCmd1.bits.copyHeader = 1;
-+ } else {
-+ saRecord->saCmd1.bits.hmac = 0;
-+ saRecord->saCmd1.bits.copyDigest = 0;
-+ saRecord->saCmd1.bits.copyHeader = 0;
-+ }
-+
-+ saRecord->saCmd1.bits.seqNumCheck = 0;
-+ saRecord->saSpi = 0x0;
-+ saRecord->saSeqNumMask[0] = 0xFFFFFFFF;
-+ saRecord->saSeqNumMask[1] = 0x0;
-+}
-+
-+/*
-+ * Poor mans Scatter/gather function:
-+ * Create a Descriptor for every segment to avoid copying buffers.
-+ * For performance better to wait for hardware to perform multiple DMA
-+ *
-+ */
-+static inline int mtk_scatter_combine(struct mtk_device *mtk,
-+ struct mtk_cipher_reqctx *rctx,
-+ u32 datalen, u32 split, int offsetin)
-+{
-+ struct eip93_descriptor_s *cdesc = rctx->cdesc;
-+ struct scatterlist *sgsrc = rctx->sg_src;
-+ struct scatterlist *sgdst = rctx->sg_dst;
-+ unsigned int remainin = sg_dma_len(sgsrc);
-+ unsigned int remainout = sg_dma_len(sgdst);
-+ dma_addr_t saddr = sg_dma_address(sgsrc);
-+ dma_addr_t daddr = sg_dma_address(sgdst);
-+ dma_addr_t stateAddr;
-+ u32 srcAddr, dstAddr, len, n;
-+ bool nextin = false;
-+ bool nextout = false;
-+ int offsetout = 0;
-+ int ndesc_cdr = 0, err;
-+
-+ if (IS_ECB(rctx->flags))
-+ rctx->saState_base = 0;
-+
-+ if (split < datalen) {
-+ stateAddr = rctx->saState_base_ctr;
-+ n = split;
-+ } else {
-+ stateAddr = rctx->saState_base;
-+ n = datalen;
-+ }
-+
-+ do {
-+ if (nextin) {
-+ sgsrc = sg_next(sgsrc);
-+ remainin = sg_dma_len(sgsrc);
-+ if (remainin == 0)
-+ continue;
-+
-+ saddr = sg_dma_address(sgsrc);
-+ offsetin = 0;
-+ nextin = false;
-+ }
-+
-+ if (nextout) {
-+ sgdst = sg_next(sgdst);
-+ remainout = sg_dma_len(sgdst);
-+ if (remainout == 0)
-+ continue;
-+
-+ daddr = sg_dma_address(sgdst);
-+ offsetout = 0;
-+ nextout = false;
-+ }
-+ srcAddr = saddr + offsetin;
-+ dstAddr = daddr + offsetout;
-+
-+ if (remainin == remainout) {
-+ len = remainin;
-+ if (len > n) {
-+ len = n;
-+ remainin -= n;
-+ remainout -= n;
-+ offsetin += n;
-+ offsetout += n;
-+ } else {
-+ nextin = true;
-+ nextout = true;
-+ }
-+ } else if (remainin < remainout) {
-+ len = remainin;
-+ if (len > n) {
-+ len = n;
-+ remainin -= n;
-+ remainout -= n;
-+ offsetin += n;
-+ offsetout += n;
-+ } else {
-+ offsetout += len;
-+ remainout -= len;
-+ nextin = true;
-+ }
-+ } else {
-+ len = remainout;
-+ if (len > n) {
-+ len = n;
-+ remainin -= n;
-+ remainout -= n;
-+ offsetin += n;
-+ offsetout += n;
-+ } else {
-+ offsetin += len;
-+ remainin -= len;
-+ nextout = true;
-+ }
-+ }
-+ n -= len;
-+
-+ cdesc->srcAddr = srcAddr;
-+ cdesc->dstAddr = dstAddr;
-+ cdesc->stateAddr = stateAddr;
-+ cdesc->peLength.bits.peReady = 0;
-+ cdesc->peLength.bits.byPass = 0;
-+ cdesc->peLength.bits.length = len;
-+ cdesc->peLength.bits.hostReady = 1;
-+
-+ if (n == 0) {
-+ n = datalen - split;
-+ split = datalen;
-+ stateAddr = rctx->saState_base;
-+ }
-+
-+ if (n == 0)
-+ cdesc->userId |= MTK_DESC_LAST;
-+
-+ /* Loop - Delay - No need to rollback
-+ * Maybe refine by slowing down at MTK_RING_BUSY
-+ */
-+again:
-+ err = mtk_put_descriptor(mtk, cdesc);
-+ if (err) {
-+ udelay(500);
-+ goto again;
-+ }
-+ /* Writing new descriptor count starts DMA action */
-+ writel(1, mtk->base + EIP93_REG_PE_CD_COUNT);
-+
-+ ndesc_cdr++;
-+ } while (n);
-+
-+ return -EINPROGRESS;
-+}
-+
-+int mtk_send_req(struct crypto_async_request *async,
-+ const u8 *reqiv, struct mtk_cipher_reqctx *rctx)
-+{
-+ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
-+ struct mtk_device *mtk = ctx->mtk;
-+ struct scatterlist *src = rctx->sg_src;
-+ struct scatterlist *dst = rctx->sg_dst;
-+ struct saState_s *saState;
-+ struct mtk_state_pool *saState_pool;
-+ struct eip93_descriptor_s cdesc;
-+ u32 flags = rctx->flags;
-+ int idx;
-+ int offsetin = 0, err = -ENOMEM;
-+ u32 datalen = rctx->assoclen + rctx->textsize;
-+ u32 split = datalen;
-+ u32 start, end, ctr, blocks;
-+ u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
-+
-+ rctx->saState_ctr = NULL;
-+ rctx->saState = NULL;
-+
-+ if (IS_ECB(flags))
-+ goto skip_iv;
-+
-+ memcpy(iv, reqiv, rctx->ivsize);
-+
-+ if (!IS_ALIGNED((u32)reqiv, rctx->ivsize) || IS_RFC3686(flags)) {
-+ rctx->flags &= ~MTK_DESC_DMA_IV;
-+ flags = rctx->flags;
-+ }
-+
-+ if (IS_DMA_IV(flags)) {
-+ rctx->saState = (void *)reqiv;
-+ } else {
-+ idx = mtk_get_free_saState(mtk);
-+ if (idx < 0)
-+ goto send_err;
-+ saState_pool = &mtk->ring->saState_pool[idx];
-+ rctx->saState_idx = idx;
-+ rctx->saState = saState_pool->base;
-+ rctx->saState_base = saState_pool->base_dma;
-+ memcpy(rctx->saState->stateIv, iv, rctx->ivsize);
-+ }
-+
-+ saState = rctx->saState;
-+
-+ if (IS_RFC3686(flags)) {
-+ saState->stateIv[0] = ctx->saNonce;
-+ saState->stateIv[1] = iv[0];
-+ saState->stateIv[2] = iv[1];
-+ saState->stateIv[3] = cpu_to_be32(1);
-+ } else if (!IS_HMAC(flags) && IS_CTR(flags)) {
-+ /* Compute data length. */
-+ blocks = DIV_ROUND_UP(rctx->textsize, AES_BLOCK_SIZE);
-+ ctr = be32_to_cpu(iv[3]);
-+ /* Check 32bit counter overflow. */
-+ start = ctr;
-+ end = start + blocks - 1;
-+ if (end < start) {
-+ split = AES_BLOCK_SIZE * -start;
-+ /*
-+ * Increment the counter manually to cope with
-+ * the hardware counter overflow.
-+ */
-+ iv[3] = 0xffffffff;
-+ crypto_inc((u8 *)iv, AES_BLOCK_SIZE);
-+ idx = mtk_get_free_saState(mtk);
-+ if (idx < 0)
-+ goto free_state;
-+ saState_pool = &mtk->ring->saState_pool[idx];
-+ rctx->saState_ctr_idx = idx;
-+ rctx->saState_ctr = saState_pool->base;
-+ rctx->saState_base_ctr = saState_pool->base_dma;
-+
-+ memcpy(rctx->saState_ctr->stateIv, reqiv, rctx->ivsize);
-+ memcpy(saState->stateIv, iv, rctx->ivsize);
-+ }
-+ }
-+
-+ if (IS_DMA_IV(flags)) {
-+ rctx->saState_base = dma_map_single(mtk->dev, (void *)reqiv,
-+ rctx->ivsize, DMA_TO_DEVICE);
-+ if (dma_mapping_error(mtk->dev, rctx->saState_base))
-+ goto free_state;
-+ }
-+skip_iv:
-+ cdesc.peCrtlStat.bits.hostReady = 1;
-+ cdesc.peCrtlStat.bits.prngMode = 0;
-+ cdesc.peCrtlStat.bits.hashFinal = 0;
-+ cdesc.peCrtlStat.bits.padCrtlStat = 0;
-+ cdesc.peCrtlStat.bits.peReady = 0;
-+ cdesc.saAddr = rctx->saRecord_base;
-+ cdesc.arc4Addr = (uint32_t)async;
-+ cdesc.userId = flags;
-+ rctx->cdesc = &cdesc;
-+
-+ /* map DMA_BIDIRECTIONAL to invalidate cache on destination
-+ * implies __dma_cache_wback_inv
-+ */
-+ dma_map_sg(mtk->dev, dst, rctx->dst_nents, DMA_BIDIRECTIONAL);
-+ if (src != dst)
-+ dma_map_sg(mtk->dev, src, rctx->src_nents, DMA_TO_DEVICE);
-+
-+ err = mtk_scatter_combine(mtk, rctx, datalen, split, offsetin);
-+
-+ return err;
-+
-+free_state:
-+ if (rctx->saState) {
-+ saState_pool = &mtk->ring->saState_pool[rctx->saState_idx];
-+ saState_pool->in_use = false;
-+ }
-+
-+ if (rctx->saState_ctr) {
-+ saState_pool = &mtk->ring->saState_pool[rctx->saState_ctr_idx];
-+ saState_pool->in_use = false;
-+ }
-+send_err:
-+ return err;
-+}
-+
-+void mtk_unmap_dma(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
-+ struct scatterlist *reqsrc, struct scatterlist *reqdst)
-+{
-+ u32 len = rctx->assoclen + rctx->textsize;
-+ u32 authsize = rctx->authsize;
-+ u32 flags = rctx->flags;
-+ u32 *otag;
-+ int i;
-+
-+ if (rctx->sg_src == rctx->sg_dst) {
-+ dma_unmap_sg(mtk->dev, rctx->sg_dst, rctx->dst_nents,
-+ DMA_BIDIRECTIONAL);
-+ goto process_tag;
-+ }
-+
-+ dma_unmap_sg(mtk->dev, rctx->sg_src, rctx->src_nents,
-+ DMA_TO_DEVICE);
-+
-+ if (rctx->sg_src != reqsrc)
-+ mtk_free_sg_copy(len + rctx->authsize, &rctx->sg_src);
-+
-+ dma_unmap_sg(mtk->dev, rctx->sg_dst, rctx->dst_nents,
-+ DMA_BIDIRECTIONAL);
-+
-+ /* SHA tags need conversion from net-to-host */
-+process_tag:
-+ if (IS_DECRYPT(flags))
-+ authsize = 0;
-+
-+ if (authsize) {
-+ if (!IS_HASH_MD5(flags)) {
-+ otag = sg_virt(rctx->sg_dst) + len;
-+ for (i = 0; i < (authsize / 4); i++)
-+ otag[i] = ntohl(otag[i]);
-+ }
-+ }
-+
-+ if (rctx->sg_dst != reqdst) {
-+ sg_copy_from_buffer(reqdst, sg_nents(reqdst),
-+ sg_virt(rctx->sg_dst), len + authsize);
-+ mtk_free_sg_copy(len + rctx->authsize, &rctx->sg_dst);
-+ }
-+}
-+
-+void mtk_handle_result(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
-+ u8 *reqiv)
-+{
-+ struct mtk_state_pool *saState_pool;
-+
-+ if (IS_DMA_IV(rctx->flags))
-+ dma_unmap_single(mtk->dev, rctx->saState_base, rctx->ivsize,
-+ DMA_TO_DEVICE);
-+
-+ if (!IS_ECB(rctx->flags))
-+ memcpy(reqiv, rctx->saState->stateIv, rctx->ivsize);
-+
-+ if ((rctx->saState) && !(IS_DMA_IV(rctx->flags))) {
-+ saState_pool = &mtk->ring->saState_pool[rctx->saState_idx];
-+ saState_pool->in_use = false;
-+ }
-+
-+ if (rctx->saState_ctr) {
-+ saState_pool = &mtk->ring->saState_pool[rctx->saState_ctr_idx];
-+ saState_pool->in_use = false;
-+ }
-+}
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
-+/* basically this is set hmac - key */
-+int mtk_authenc_setkey(struct crypto_shash *cshash, struct saRecord_s *sa,
-+ const u8 *authkey, unsigned int authkeylen)
-+{
-+ int bs = crypto_shash_blocksize(cshash);
-+ int ds = crypto_shash_digestsize(cshash);
-+ int ss = crypto_shash_statesize(cshash);
-+ u8 *ipad, *opad;
-+ unsigned int i, err;
-+
-+ SHASH_DESC_ON_STACK(shash, cshash);
-+
-+ shash->tfm = cshash;
-+
-+ /* auth key
-+ *
-+ * EIP93 can only authenticate with hash of the key
-+ * do software shash until EIP93 hash function complete.
-+ */
-+ ipad = kcalloc(2, SHA256_BLOCK_SIZE + ss, GFP_KERNEL);
-+ if (!ipad)
-+ return -ENOMEM;
-+
-+ opad = ipad + SHA256_BLOCK_SIZE + ss;
-+
-+ if (authkeylen > bs) {
-+ err = crypto_shash_digest(shash, authkey,
-+ authkeylen, ipad);
-+ if (err)
-+ return err;
-+
-+ authkeylen = ds;
-+ } else
-+ memcpy(ipad, authkey, authkeylen);
-+
-+ memset(ipad + authkeylen, 0, bs - authkeylen);
-+ memcpy(opad, ipad, bs);
-+
-+ for (i = 0; i < bs; i++) {
-+ ipad[i] ^= HMAC_IPAD_VALUE;
-+ opad[i] ^= HMAC_OPAD_VALUE;
-+ }
-+
-+ err = crypto_shash_init(shash) ?:
-+ crypto_shash_update(shash, ipad, bs) ?:
-+ crypto_shash_export(shash, ipad) ?:
-+ crypto_shash_init(shash) ?:
-+ crypto_shash_update(shash, opad, bs) ?:
-+ crypto_shash_export(shash, opad);
-+
-+ if (err)
-+ return err;
-+
-+ /* add auth key */
-+ memcpy(&sa->saIDigest, ipad, SHA256_DIGEST_SIZE);
-+ memcpy(&sa->saODigest, opad, SHA256_DIGEST_SIZE);
-+
-+ kfree(ipad);
-+ return 0;
-+}
-+#endif
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-common.h
-@@ -0,0 +1,28 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+
-+#ifndef _EIP93_COMMON_H_
-+#define _EIP93_COMMON_H_
-+
-+#include "eip93-main.h"
-+
-+inline int mtk_put_descriptor(struct mtk_device *mtk,
-+ struct eip93_descriptor_s *desc);
-+
-+inline void *mtk_get_descriptor(struct mtk_device *mtk);
-+
-+inline int mtk_get_free_saState(struct mtk_device *mtk);
-+
-+void mtk_set_saRecord(struct saRecord_s *saRecord, const unsigned int keylen,
-+ const u32 flags);
-+
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
-+int mtk_authenc_setkey(struct crypto_shash *cshash, struct saRecord_s *sa,
-+ const u8 *authkey, unsigned int authkeylen);
-+#endif
-+
-+#endif /* _EIP93_COMMON_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-des.h
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef _EIP93_DES_H_
-+#define _EIP93_DES_H_
-+
-+extern struct mtk_alg_template mtk_alg_ecb_des;
-+extern struct mtk_alg_template mtk_alg_cbc_des;
-+extern struct mtk_alg_template mtk_alg_ecb_des3_ede;
-+extern struct mtk_alg_template mtk_alg_cbc_des3_ede;
-+
-+#endif /* _EIP93_DES_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-main.c
-@@ -0,0 +1,467 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+
-+#include <linux/atomic.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/spinlock.h>
-+
-+#include "eip93-main.h"
-+#include "eip93-regs.h"
-+#include "eip93-common.h"
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER)
-+#include "eip93-cipher.h"
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+#include "eip93-aes.h"
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+#include "eip93-des.h"
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
-+#include "eip93-aead.h"
-+#endif
-+
-+static struct mtk_alg_template *mtk_algs[] = {
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+ &mtk_alg_ecb_des,
-+ &mtk_alg_cbc_des,
-+ &mtk_alg_ecb_des3_ede,
-+ &mtk_alg_cbc_des3_ede,
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+ &mtk_alg_ecb_aes,
-+ &mtk_alg_cbc_aes,
-+ &mtk_alg_ctr_aes,
-+ &mtk_alg_rfc3686_aes,
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+ &mtk_alg_authenc_hmac_md5_cbc_des,
-+ &mtk_alg_authenc_hmac_sha1_cbc_des,
-+ &mtk_alg_authenc_hmac_sha224_cbc_des,
-+ &mtk_alg_authenc_hmac_sha256_cbc_des,
-+ &mtk_alg_authenc_hmac_md5_cbc_des3_ede,
-+ &mtk_alg_authenc_hmac_sha1_cbc_des3_ede,
-+ &mtk_alg_authenc_hmac_sha224_cbc_des3_ede,
-+ &mtk_alg_authenc_hmac_sha256_cbc_des3_ede,
-+#endif
-+ &mtk_alg_authenc_hmac_md5_cbc_aes,
-+ &mtk_alg_authenc_hmac_sha1_cbc_aes,
-+ &mtk_alg_authenc_hmac_sha224_cbc_aes,
-+ &mtk_alg_authenc_hmac_sha256_cbc_aes,
-+ &mtk_alg_authenc_hmac_md5_rfc3686_aes,
-+ &mtk_alg_authenc_hmac_sha1_rfc3686_aes,
-+ &mtk_alg_authenc_hmac_sha224_rfc3686_aes,
-+ &mtk_alg_authenc_hmac_sha256_rfc3686_aes,
-+#endif
-+};
-+
-+inline void mtk_irq_disable(struct mtk_device *mtk, u32 mask)
-+{
-+ __raw_writel(mask, mtk->base + EIP93_REG_MASK_DISABLE);
-+}
-+
-+inline void mtk_irq_enable(struct mtk_device *mtk, u32 mask)
-+{
-+ __raw_writel(mask, mtk->base + EIP93_REG_MASK_ENABLE);
-+}
-+
-+inline void mtk_irq_clear(struct mtk_device *mtk, u32 mask)
-+{
-+ __raw_writel(mask, mtk->base + EIP93_REG_INT_CLR);
-+}
-+
-+static void mtk_unregister_algs(unsigned int i)
-+{
-+ unsigned int j;
-+
-+ for (j = 0; j < i; j++) {
-+ switch (mtk_algs[j]->type) {
-+ case MTK_ALG_TYPE_SKCIPHER:
-+ crypto_unregister_skcipher(&mtk_algs[j]->alg.skcipher);
-+ break;
-+ case MTK_ALG_TYPE_AEAD:
-+ crypto_unregister_aead(&mtk_algs[j]->alg.aead);
-+ break;
-+ }
-+ }
-+}
-+
-+static int mtk_register_algs(struct mtk_device *mtk)
-+{
-+ unsigned int i;
-+ int err = 0;
-+
-+ for (i = 0; i < ARRAY_SIZE(mtk_algs); i++) {
-+ mtk_algs[i]->mtk = mtk;
-+
-+ switch (mtk_algs[i]->type) {
-+ case MTK_ALG_TYPE_SKCIPHER:
-+ err = crypto_register_skcipher(&mtk_algs[i]->alg.skcipher);
-+ break;
-+ case MTK_ALG_TYPE_AEAD:
-+ err = crypto_register_aead(&mtk_algs[i]->alg.aead);
-+ break;
-+ }
-+ if (err)
-+ goto fail;
-+ }
-+
-+ return 0;
-+
-+fail:
-+ mtk_unregister_algs(i);
-+
-+ return err;
-+}
-+
-+static void mtk_handle_result_descriptor(struct mtk_device *mtk)
-+{
-+ struct crypto_async_request *async;
-+ struct eip93_descriptor_s *rdesc;
-+ bool last_entry;
-+ u32 flags;
-+ int handled, ready, err;
-+ union peCrtlStat_w done1;
-+ union peLength_w done2;
-+
-+get_more:
-+ handled = 0;
-+
-+ ready = readl(mtk->base + EIP93_REG_PE_RD_COUNT) & GENMASK(10, 0);
-+
-+ if (!ready) {
-+ mtk_irq_clear(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
-+ mtk_irq_enable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
-+ return;
-+ }
-+
-+ last_entry = false;
-+
-+ while (ready) {
-+ rdesc = mtk_get_descriptor(mtk);
-+ if (IS_ERR(rdesc)) {
-+ dev_err(mtk->dev, "Ndesc: %d nreq: %d\n",
-+ handled, ready);
-+ err = -EIO;
-+ break;
-+ }
-+ /* make sure DMA is finished writing */
-+ do {
-+ done1.word = READ_ONCE(rdesc->peCrtlStat.word);
-+ done2.word = READ_ONCE(rdesc->peLength.word);
-+ } while ((!done1.bits.peReady) || (!done2.bits.peReady));
-+
-+ err = rdesc->peCrtlStat.bits.errStatus;
-+
-+ flags = rdesc->userId;
-+ async = (struct crypto_async_request *)rdesc->arc4Addr;
-+
-+ writel(1, mtk->base + EIP93_REG_PE_RD_COUNT);
-+ mtk_irq_clear(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
-+
-+ handled++;
-+ ready--;
-+
-+ if (flags & MTK_DESC_LAST) {
-+ last_entry = true;
-+ break;
-+ }
-+ }
-+
-+ if (!last_entry)
-+ goto get_more;
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER)
-+ if (flags & MTK_DESC_SKCIPHER)
-+ mtk_skcipher_handle_result(async, err);
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
-+ if (flags & MTK_DESC_AEAD)
-+ mtk_aead_handle_result(async, err);
-+#endif
-+ goto get_more;
-+}
-+
-+static void mtk_done_task(unsigned long data)
-+{
-+ struct mtk_device *mtk = (struct mtk_device *)data;
-+
-+ mtk_handle_result_descriptor(mtk);
-+}
-+
-+static irqreturn_t mtk_irq_handler(int irq, void *dev_id)
-+{
-+ struct mtk_device *mtk = (struct mtk_device *)dev_id;
-+ u32 irq_status;
-+
-+ irq_status = readl(mtk->base + EIP93_REG_INT_MASK_STAT);
-+
-+ if (irq_status & EIP93_INT_PE_RDRTHRESH_REQ) {
-+ mtk_irq_disable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
-+ tasklet_schedule(&mtk->ring->done_task);
-+ return IRQ_HANDLED;
-+ }
-+
-+ mtk_irq_clear(mtk, irq_status);
-+ if (irq_status)
-+ mtk_irq_disable(mtk, irq_status);
-+
-+ return IRQ_NONE;
-+}
-+
-+static void mtk_initialize(struct mtk_device *mtk)
-+{
-+ union peConfig_w peConfig;
-+ union peEndianCfg_w peEndianCfg;
-+ union peIntCfg_w peIntCfg;
-+ union peClockCfg_w peClockCfg;
-+ union peBufThresh_w peBufThresh;
-+ union peRingThresh_w peRingThresh;
-+
-+ /* Reset Engine and setup Mode */
-+ peConfig.word = 0;
-+ peConfig.bits.resetPE = 1;
-+ peConfig.bits.resetRing = 1;
-+ peConfig.bits.peMode = 3;
-+ peConfig.bits.enCDRupdate = 1;
-+
-+ writel(peConfig.word, mtk->base + EIP93_REG_PE_CONFIG);
-+
-+ udelay(10);
-+
-+ peConfig.bits.resetPE = 0;
-+ peConfig.bits.resetRing = 0;
-+
-+ writel(peConfig.word, mtk->base + EIP93_REG_PE_CONFIG);
-+
-+ /* Initialize the BYTE_ORDER_CFG register */
-+ peEndianCfg.word = 0;
-+ writel(peEndianCfg.word, mtk->base + EIP93_REG_PE_ENDIAN_CONFIG);
-+
-+ /* Initialize the INT_CFG register */
-+ peIntCfg.word = 0;
-+ writel(peIntCfg.word, mtk->base + EIP93_REG_INT_CFG);
-+
-+ /* Config Clocks */
-+ peClockCfg.word = 0;
-+ peClockCfg.bits.enPEclk = 1;
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
-+ peClockCfg.bits.enDESclk = 1;
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
-+ peClockCfg.bits.enAESclk = 1;
-+#endif
-+#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
-+ peClockCfg.bits.enHASHclk = 1;
-+#endif
-+ writel(peClockCfg.word, mtk->base + EIP93_REG_PE_CLOCK_CTRL);
-+
-+ /* Config DMA thresholds */
-+ peBufThresh.word = 0;
-+ peBufThresh.bits.inputBuffer = 128;
-+ peBufThresh.bits.outputBuffer = 128;
-+
-+ writel(peBufThresh.word, mtk->base + EIP93_REG_PE_BUF_THRESH);
-+
-+ /* Clear/ack all interrupts before disable all */
-+ mtk_irq_clear(mtk, 0xFFFFFFFF);
-+ mtk_irq_disable(mtk, 0xFFFFFFFF);
-+
-+ /* Config Ring Threshold */
-+ peRingThresh.word = 0;
-+ peRingThresh.bits.CDRThresh = MTK_RING_SIZE - MTK_RING_BUSY;
-+ peRingThresh.bits.RDRThresh = 0;
-+ peRingThresh.bits.RDTimeout = 5;
-+ peRingThresh.bits.enTimeout = 1;
-+
-+ writel(peRingThresh.word, mtk->base + EIP93_REG_PE_RING_THRESH);
-+}
-+
-+static void mtk_desc_free(struct mtk_device *mtk)
-+{
-+ writel(0, mtk->base + EIP93_REG_PE_RING_CONFIG);
-+ writel(0, mtk->base + EIP93_REG_PE_CDR_BASE);
-+ writel(0, mtk->base + EIP93_REG_PE_RDR_BASE);
-+}
-+
-+static int mtk_set_ring(struct mtk_device *mtk, struct mtk_desc_ring *ring,
-+ int Offset)
-+{
-+ ring->offset = Offset;
-+ ring->base = dmam_alloc_coherent(mtk->dev, Offset * MTK_RING_SIZE,
-+ &ring->base_dma, GFP_KERNEL);
-+ if (!ring->base)
-+ return -ENOMEM;
-+
-+ ring->write = ring->base;
-+ ring->base_end = ring->base + Offset * (MTK_RING_SIZE - 1);
-+ ring->read = ring->base;
-+
-+ return 0;
-+}
-+
-+static int mtk_desc_init(struct mtk_device *mtk)
-+{
-+ struct mtk_state_pool *saState_pool;
-+ struct mtk_desc_ring *cdr = &mtk->ring->cdr;
-+ struct mtk_desc_ring *rdr = &mtk->ring->rdr;
-+ union peRingCfg_w peRingCfg;
-+ int RingOffset, err, i;
-+
-+ RingOffset = sizeof(struct eip93_descriptor_s);
-+
-+ err = mtk_set_ring(mtk, cdr, RingOffset);
-+ if (err)
-+ return err;
-+
-+ err = mtk_set_ring(mtk, rdr, RingOffset);
-+ if (err)
-+ return err;
-+
-+ writel((u32)cdr->base_dma, mtk->base + EIP93_REG_PE_CDR_BASE);
-+ writel((u32)rdr->base_dma, mtk->base + EIP93_REG_PE_RDR_BASE);
-+
-+ peRingCfg.word = 0;
-+ peRingCfg.bits.ringSize = MTK_RING_SIZE - 1;
-+ peRingCfg.bits.ringOffset = RingOffset / 4;
-+
-+ writel(peRingCfg.word, mtk->base + EIP93_REG_PE_RING_CONFIG);
-+
-+ atomic_set(&mtk->ring->free, MTK_RING_SIZE - 1);
-+ /* Create State record DMA pool */
-+ RingOffset = sizeof(struct saState_s);
-+ mtk->ring->saState = dmam_alloc_coherent(mtk->dev,
-+ RingOffset * MTK_RING_SIZE,
-+ &mtk->ring->saState_dma, GFP_KERNEL);
-+ if (!mtk->ring->saState)
-+ return -ENOMEM;
-+
-+ mtk->ring->saState_pool = devm_kcalloc(mtk->dev, 1,
-+ sizeof(struct mtk_state_pool) * MTK_RING_SIZE,
-+ GFP_KERNEL);
-+
-+ for (i = 0; i < MTK_RING_SIZE; i++) {
-+ saState_pool = &mtk->ring->saState_pool[i];
-+ saState_pool->base = mtk->ring->saState + (i * RingOffset);
-+ saState_pool->base_dma = mtk->ring->saState_dma + (i * RingOffset);
-+ saState_pool->in_use = false;
-+ }
-+
-+ return 0;
-+}
-+
-+static void mtk_cleanup(struct mtk_device *mtk)
-+{
-+ tasklet_kill(&mtk->ring->done_task);
-+
-+ /* Clear/ack all interrupts before disable all */
-+ mtk_irq_clear(mtk, 0xFFFFFFFF);
-+ mtk_irq_disable(mtk, 0xFFFFFFFF);
-+
-+ writel(0, mtk->base + EIP93_REG_PE_CLOCK_CTRL);
-+
-+ mtk_desc_free(mtk);
-+}
-+
-+static int mtk_crypto_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct mtk_device *mtk;
-+ struct resource *res;
-+ int err;
-+
-+ mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
-+ if (!mtk)
-+ return -ENOMEM;
-+
-+ mtk->dev = dev;
-+ platform_set_drvdata(pdev, mtk);
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ mtk->base = devm_ioremap_resource(&pdev->dev, res);
-+
-+ if (IS_ERR(mtk->base))
-+ return PTR_ERR(mtk->base);
-+
-+ mtk->irq = platform_get_irq(pdev, 0);
-+
-+ if (mtk->irq < 0)
-+ return mtk->irq;
-+
-+ err = devm_request_threaded_irq(mtk->dev, mtk->irq, mtk_irq_handler,
-+ NULL, IRQF_ONESHOT,
-+ dev_name(mtk->dev), mtk);
-+
-+ mtk->ring = devm_kcalloc(mtk->dev, 1, sizeof(*mtk->ring), GFP_KERNEL);
-+
-+ if (!mtk->ring)
-+ return -ENOMEM;
-+
-+ err = mtk_desc_init(mtk);
-+ if (err)
-+ return err;
-+
-+ tasklet_init(&mtk->ring->done_task, mtk_done_task, (unsigned long)mtk);
-+
-+ spin_lock_init(&mtk->ring->read_lock);
-+ spin_lock_init(&mtk->ring->write_lock);
-+
-+ mtk_initialize(mtk);
-+
-+ /* Init. finished, enable RDR interupt */
-+ mtk_irq_enable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
-+
-+ err = mtk_register_algs(mtk);
-+ if (err) {
-+ mtk_cleanup(mtk);
-+ return err;
-+ }
-+
-+ dev_info(mtk->dev, "EIP93 Crypto Engine Initialized.");
-+
-+ return 0;
-+}
-+
-+static int mtk_crypto_remove(struct platform_device *pdev)
-+{
-+ struct mtk_device *mtk = platform_get_drvdata(pdev);
-+
-+ mtk_unregister_algs(ARRAY_SIZE(mtk_algs));
-+ mtk_cleanup(mtk);
-+ dev_info(mtk->dev, "EIP93 removed.\n");
-+
-+ return 0;
-+}
-+
-+#if defined(CONFIG_OF)
-+static const struct of_device_id mtk_crypto_of_match[] = {
-+ { .compatible = "mediatek,mtk-eip93", },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, mtk_crypto_of_match);
-+#endif
-+
-+static struct platform_driver mtk_crypto_driver = {
-+ .probe = mtk_crypto_probe,
-+ .remove = mtk_crypto_remove,
-+ .driver = {
-+ .name = "mtk-eip93",
-+ .of_match_table = of_match_ptr(mtk_crypto_of_match),
-+ },
-+};
-+module_platform_driver(mtk_crypto_driver);
-+
-+MODULE_AUTHOR("Richard van Schagen <vschagen@cs.com>");
-+MODULE_ALIAS("platform:" KBUILD_MODNAME);
-+MODULE_DESCRIPTION("Mediatek EIP-93 crypto engine driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-main.h
-@@ -0,0 +1,146 @@
-+/* SPDX-License-Identifier: GPL-2.0
-+ *
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef _EIP93_MAIN_H_
-+#define _EIP93_MAIN_H_
-+
-+#include <crypto/internal/aead.h>
-+#include <crypto/internal/hash.h>
-+#include <crypto/internal/rng.h>
-+#include <crypto/internal/skcipher.h>
-+#include <linux/device.h>
-+#include <linux/interrupt.h>
-+
-+#define MTK_RING_SIZE 512
-+#define MTK_RING_BUSY 32
-+#define MTK_CRA_PRIORITY 1500
-+
-+/* cipher algorithms */
-+#define MTK_ALG_DES BIT(0)
-+#define MTK_ALG_3DES BIT(1)
-+#define MTK_ALG_AES BIT(2)
-+#define MTK_ALG_MASK GENMASK(2, 0)
-+/* hash and hmac algorithms */
-+#define MTK_HASH_MD5 BIT(3)
-+#define MTK_HASH_SHA1 BIT(4)
-+#define MTK_HASH_SHA224 BIT(5)
-+#define MTK_HASH_SHA256 BIT(6)
-+#define MTK_HASH_HMAC BIT(7)
-+#define MTK_HASH_MASK GENMASK(6, 3)
-+/* cipher modes */
-+#define MTK_MODE_CBC BIT(8)
-+#define MTK_MODE_ECB BIT(9)
-+#define MTK_MODE_CTR BIT(10)
-+#define MTK_MODE_RFC3686 BIT(11)
-+#define MTK_MODE_MASK GENMASK(10, 8)
-+
-+/* cipher encryption/decryption operations */
-+#define MTK_ENCRYPT BIT(12)
-+#define MTK_DECRYPT BIT(13)
-+
-+#define MTK_BUSY BIT(14)
-+
-+/* descriptor flags */
-+#define MTK_DESC_ASYNC BIT(31)
-+#define MTK_DESC_SKCIPHER BIT(30)
-+#define MTK_DESC_AEAD BIT(29)
-+#define MTK_DESC_AHASH BIT(28)
-+#define MTK_DESC_PRNG BIT(27)
-+#define MTK_DESC_FAKE_HMAC BIT(26)
-+#define MTK_DESC_LAST BIT(25)
-+#define MTK_DESC_FINISH BIT(24)
-+#define MTK_DESC_IPSEC BIT(23)
-+#define MTK_DESC_DMA_IV BIT(22)
-+
-+#define IS_DES(flags) (flags & MTK_ALG_DES)
-+#define IS_3DES(flags) (flags & MTK_ALG_3DES)
-+#define IS_AES(flags) (flags & MTK_ALG_AES)
-+
-+#define IS_HASH_MD5(flags) (flags & MTK_HASH_MD5)
-+#define IS_HASH_SHA1(flags) (flags & MTK_HASH_SHA1)
-+#define IS_HASH_SHA224(flags) (flags & MTK_HASH_SHA224)
-+#define IS_HASH_SHA256(flags) (flags & MTK_HASH_SHA256)
-+#define IS_HMAC(flags) (flags & MTK_HASH_HMAC)
-+
-+#define IS_CBC(mode) (mode & MTK_MODE_CBC)
-+#define IS_ECB(mode) (mode & MTK_MODE_ECB)
-+#define IS_CTR(mode) (mode & MTK_MODE_CTR)
-+#define IS_RFC3686(mode) (mode & MTK_MODE_RFC3686)
-+
-+#define IS_BUSY(flags) (flags & MTK_BUSY)
-+#define IS_DMA_IV(flags) (flags & MTK_DESC_DMA_IV)
-+
-+#define IS_ENCRYPT(dir) (dir & MTK_ENCRYPT)
-+#define IS_DECRYPT(dir) (dir & MTK_DECRYPT)
-+
-+#define IS_CIPHER(flags) (flags & (MTK_ALG_DES || \
-+ MTK_ALG_3DES || \
-+ MTK_ALG_AES))
-+
-+#define IS_HASH(flags) (flags & (MTK_HASH_MD5 || \
-+ MTK_HASH_SHA1 || \
-+ MTK_HASH_SHA224 || \
-+ MTK_HASH_SHA256))
-+
-+/**
-+ * struct mtk_device - crypto engine device structure
-+ */
-+struct mtk_device {
-+ void __iomem *base;
-+ struct device *dev;
-+ struct clk *clk;
-+ int irq;
-+ struct mtk_ring *ring;
-+ struct mtk_state_pool *saState_pool;
-+};
-+
-+struct mtk_desc_ring {
-+ void *base;
-+ void *base_end;
-+ dma_addr_t base_dma;
-+ /* write and read pointers */
-+ void *read;
-+ void *write;
-+ /* descriptor element offset */
-+ u32 offset;
-+};
-+
-+struct mtk_state_pool {
-+ void *base;
-+ dma_addr_t base_dma;
-+ bool in_use;
-+};
-+
-+struct mtk_ring {
-+ struct tasklet_struct done_task;
-+ /* command/result rings */
-+ struct mtk_desc_ring cdr;
-+ struct mtk_desc_ring rdr;
-+ spinlock_t write_lock;
-+ spinlock_t read_lock;
-+ atomic_t free;
-+ /* saState */
-+ struct mtk_state_pool *saState_pool;
-+ void *saState;
-+ dma_addr_t saState_dma;
-+};
-+
-+enum mtk_alg_type {
-+ MTK_ALG_TYPE_AEAD,
-+ MTK_ALG_TYPE_SKCIPHER,
-+};
-+
-+struct mtk_alg_template {
-+ struct mtk_device *mtk;
-+ enum mtk_alg_type type;
-+ u32 flags;
-+ union {
-+ struct aead_alg aead;
-+ struct skcipher_alg skcipher;
-+ } alg;
-+};
-+
-+#endif /* _EIP93_MAIN_H_ */
---- /dev/null
-+++ b/drivers/crypto/mtk-eip93/eip93-regs.h
-@@ -0,0 +1,382 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Copyright (C) 2019 - 2021
-+ *
-+ * Richard van Schagen <vschagen@icloud.com>
-+ */
-+#ifndef REG_EIP93_H
-+#define REG_EIP93_H
-+
-+#define EIP93_REG_WIDTH 4
-+/*-----------------------------------------------------------------------------
-+ * Register Map
-+ */
-+#define DESP_BASE 0x0000000
-+#define EIP93_REG_PE_CTRL_STAT ((DESP_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_SOURCE_ADDR ((DESP_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_DEST_ADDR ((DESP_BASE)+(0x02 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_SA_ADDR ((DESP_BASE)+(0x03 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_ADDR ((DESP_BASE)+(0x04 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_USER_ID ((DESP_BASE)+(0x06 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_LENGTH ((DESP_BASE)+(0x07 * EIP93_REG_WIDTH))
-+
-+//PACKET ENGINE RING configuration registers
-+#define PE_RNG_BASE 0x0000080
-+
-+#define EIP93_REG_PE_CDR_BASE ((PE_RNG_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_RDR_BASE ((PE_RNG_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_RING_CONFIG ((PE_RNG_BASE)+(0x02 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_RING_THRESH ((PE_RNG_BASE)+(0x03 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_CD_COUNT ((PE_RNG_BASE)+(0x04 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_RD_COUNT ((PE_RNG_BASE)+(0x05 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_RING_RW_PNTR ((PE_RNG_BASE)+(0x06 * EIP93_REG_WIDTH))
-+
-+//PACKET ENGINE configuration registers
-+#define PE_CFG_BASE 0x0000100
-+#define EIP93_REG_PE_CONFIG ((PE_CFG_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_STATUS ((PE_CFG_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_BUF_THRESH ((PE_CFG_BASE)+(0x03 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_INBUF_COUNT ((PE_CFG_BASE)+(0x04 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_OUTBUF_COUNT ((PE_CFG_BASE)+(0x05 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_BUF_RW_PNTR ((PE_CFG_BASE)+(0x06 * EIP93_REG_WIDTH))
-+
-+//PACKET ENGINE endian config
-+#define EN_CFG_BASE 0x00001CC
-+#define EIP93_REG_PE_ENDIAN_CONFIG ((EN_CFG_BASE)+(0x00 * EIP93_REG_WIDTH))
-+
-+//EIP93 CLOCK control registers
-+#define CLOCK_BASE 0x01E8
-+#define EIP93_REG_PE_CLOCK_CTRL ((CLOCK_BASE)+(0x00 * EIP93_REG_WIDTH))
-+
-+//EIP93 Device Option and Revision Register
-+#define REV_BASE 0x01F4
-+#define EIP93_REG_PE_OPTION_1 ((REV_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_OPTION_0 ((REV_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PE_REVISION ((REV_BASE)+(0x02 * EIP93_REG_WIDTH))
-+
-+//EIP93 Interrupt Control Register
-+#define INT_BASE 0x0200
-+#define EIP93_REG_INT_UNMASK_STAT ((INT_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_INT_MASK_STAT ((INT_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_INT_CLR ((INT_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_INT_MASK ((INT_BASE)+(0x02 * EIP93_REG_WIDTH))
-+#define EIP93_REG_INT_CFG ((INT_BASE)+(0x03 * EIP93_REG_WIDTH))
-+#define EIP93_REG_MASK_ENABLE ((INT_BASE)+(0X04 * EIP93_REG_WIDTH))
-+#define EIP93_REG_MASK_DISABLE ((INT_BASE)+(0X05 * EIP93_REG_WIDTH))
-+
-+//EIP93 SA Record register
-+#define SA_BASE 0x0400
-+#define EIP93_REG_SA_CMD_0 ((SA_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_SA_CMD_1 ((SA_BASE)+(0x01 * EIP93_REG_WIDTH))
-+
-+//#define EIP93_REG_SA_READY ((SA_BASE)+(31 * EIP93_REG_WIDTH))
-+
-+//State save register
-+#define STATE_BASE 0x0500
-+#define EIP93_REG_STATE_IV_0 ((STATE_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_STATE_IV_1 ((STATE_BASE)+(0x01 * EIP93_REG_WIDTH))
-+
-+#define EIP93_PE_ARC4STATE_BASEADDR_REG 0x0700
-+
-+//RAM buffer start address
-+#define EIP93_INPUT_BUFFER 0x0800
-+#define EIP93_OUTPUT_BUFFER 0x0800
-+
-+//EIP93 PRNG Configuration Register
-+#define PRNG_BASE 0x0300
-+#define EIP93_REG_PRNG_STAT ((PRNG_BASE)+(0x00 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_CTRL ((PRNG_BASE)+(0x01 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_SEED_0 ((PRNG_BASE)+(0x02 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_SEED_1 ((PRNG_BASE)+(0x03 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_SEED_2 ((PRNG_BASE)+(0x04 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_SEED_3 ((PRNG_BASE)+(0x05 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_KEY_0 ((PRNG_BASE)+(0x06 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_KEY_1 ((PRNG_BASE)+(0x07 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_KEY_2 ((PRNG_BASE)+(0x08 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_KEY_3 ((PRNG_BASE)+(0x09 * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_RES_0 ((PRNG_BASE)+(0x0A * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_RES_1 ((PRNG_BASE)+(0x0B * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_RES_2 ((PRNG_BASE)+(0x0C * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_RES_3 ((PRNG_BASE)+(0x0D * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_LFSR_0 ((PRNG_BASE)+(0x0E * EIP93_REG_WIDTH))
-+#define EIP93_REG_PRNG_LFSR_1 ((PRNG_BASE)+(0x0F * EIP93_REG_WIDTH))
-+
-+/*-----------------------------------------------------------------------------
-+ * Constants & masks
-+ */
-+
-+#define EIP93_SUPPORTED_INTERRUPTS_MASK 0xffff7f00
-+#define EIP93_PRNG_DT_TEXT_LOWERHALF 0xDEAD
-+#define EIP93_PRNG_DT_TEXT_UPPERHALF 0xC0DE
-+#define EIP93_10BITS_MASK 0X3FF
-+#define EIP93_12BITS_MASK 0XFFF
-+#define EIP93_4BITS_MASK 0X04
-+#define EIP93_20BITS_MASK 0xFFFFF
-+
-+#define EIP93_MIN_DESC_DONE_COUNT 0
-+#define EIP93_MAX_DESC_DONE_COUNT 15
-+
-+#define EIP93_MIN_DESC_PENDING_COUNT 0
-+#define EIP93_MAX_DESC_PENDING_COUNT 1023
-+
-+#define EIP93_MIN_TIMEOUT_COUNT 0
-+#define EIP93_MAX_TIMEOUT_COUNT 15
-+
-+#define EIP93_MIN_PE_INPUT_THRESHOLD 1
-+#define EIP93_MAX_PE_INPUT_THRESHOLD 511
-+
-+#define EIP93_MIN_PE_OUTPUT_THRESHOLD 1
-+#define EIP93_MAX_PE_OUTPUT_THRESHOLD 432
-+
-+#define EIP93_MIN_PE_RING_SIZE 1
-+#define EIP93_MAX_PE_RING_SIZE 1023
-+
-+#define EIP93_MIN_PE_DESCRIPTOR_SIZE 7
-+#define EIP93_MAX_PE_DESCRIPTOR_SIZE 15
-+
-+//3DES keys,seed,known data and its result
-+#define EIP93_KEY_0 0x133b3454
-+#define EIP93_KEY_1 0x5e5b890b
-+#define EIP93_KEY_2 0x5eb30757
-+#define EIP93_KEY_3 0x93ab15f7
-+#define EIP93_SEED_0 0x62c4bf5e
-+#define EIP93_SEED_1 0x972667c8
-+#define EIP93_SEED_2 0x6345bf67
-+#define EIP93_SEED_3 0xcb3482bf
-+#define EIP93_LFSR_0 0xDEADC0DE
-+#define EIP93_LFSR_1 0xBEEFF00D
-+
-+/*-----------------------------------------------------------------------------
-+ * EIP93 device initialization specifics
-+ */
-+
-+/*----------------------------------------------------------------------------
-+ * Byte Order Reversal Mechanisms Supported in EIP93
-+ * EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word
-+ * EIP93_BO_REVERSE_WORD : reverse the byte order within a word
-+ * EIP93_BO_REVERSE_DUAL_WORD : reverse the byte order within a dual-word
-+ * EIP93_BO_REVERSE_QUAD_WORD : reverse the byte order within a quad-word
-+ */
-+enum EIP93_Byte_Order_Value_t {
-+ EIP93_BO_REVERSE_HALF_WORD = 1,
-+ EIP93_BO_REVERSE_WORD = 2,
-+ EIP93_BO_REVERSE_DUAL_WORD = 4,
-+ EIP93_BO_REVERSE_QUAD_WORD = 8,
-+};
-+
-+/*----------------------------------------------------------------------------
-+ * Byte Order Reversal Mechanisms Supported in EIP93 for Target Data
-+ * EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word
-+ * EIP93_BO_REVERSE_WORD : reverse the byte order within a word
-+ */
-+enum EIP93_Byte_Order_Value_TD_t {
-+ EIP93_BO_REVERSE_HALF_WORD_TD = 1,
-+ EIP93_BO_REVERSE_WORD_TD = 2,
-+};
-+
-+// BYTE_ORDER_CFG register values
-+#define EIP93_BYTE_ORDER_PD EIP93_BO_REVERSE_WORD
-+#define EIP93_BYTE_ORDER_SA EIP93_BO_REVERSE_WORD
-+#define EIP93_BYTE_ORDER_DATA EIP93_BO_REVERSE_WORD
-+#define EIP93_BYTE_ORDER_TD EIP93_BO_REVERSE_WORD_TD
-+
-+// INT_CFG register values
-+#define EIP93_INT_HOST_OUTPUT_TYPE 0
-+#define EIP93_INT_PULSE_CLEAR 0
-+
-+/*
-+ * Interrupts of EIP93
-+ */
-+
-+enum EIP93_InterruptSource_t {
-+ EIP93_INT_PE_CDRTHRESH_REQ = BIT(0),
-+ EIP93_INT_PE_RDRTHRESH_REQ = BIT(1),
-+ EIP93_INT_PE_OPERATION_DONE = BIT(9),
-+ EIP93_INT_PE_INBUFTHRESH_REQ = BIT(10),
-+ EIP93_INT_PE_OUTBURTHRSH_REQ = BIT(11),
-+ EIP93_INT_PE_PRNG_IRQ = BIT(12),
-+ EIP93_INT_PE_ERR_REG = BIT(13),
-+ EIP93_INT_PE_RD_DONE_IRQ = BIT(16),
-+};
-+
-+union peConfig_w {
-+ u32 word;
-+ struct {
-+ u32 resetPE :1;
-+ u32 resetRing :1;
-+ u32 reserved :6;
-+ u32 peMode :2;
-+ u32 enCDRupdate :1;
-+ u32 reserved2 :5;
-+ u32 swapCDRD :1;
-+ u32 swapSA :1;
-+ u32 swapData :1;
-+ u32 reserved3 :13;
-+ } bits;
-+} __packed;
-+
-+union peEndianCfg_w {
-+ u32 word;
-+ struct {
-+ u32 masterByteSwap :8;
-+ u32 reserved :8;
-+ u32 targetByteSwap :8;
-+ u32 reserved2 :8;
-+ } bits;
-+} __packed;
-+
-+union peIntCfg_w {
-+ u32 word;
-+ struct {
-+ u32 PulseClear :1;
-+ u32 IntType :1;
-+ u32 reserved :30;
-+ } bits;
-+} __packed;
-+
-+union peClockCfg_w {
-+ u32 word;
-+ struct {
-+ u32 enPEclk :1;
-+ u32 enDESclk :1;
-+ u32 enAESclk :1;
-+ u32 reserved :1;
-+ u32 enHASHclk :1;
-+ u32 reserved2 :27;
-+ } bits;
-+} __packed;
-+
-+union peBufThresh_w {
-+ u32 word;
-+ struct {
-+ u32 inputBuffer :8;
-+ u32 reserved :8;
-+ u32 outputBuffer :8;
-+ u32 reserved2 :8;
-+ } bits;
-+} __packed;
-+
-+union peRingThresh_w {
-+ u32 word;
-+ struct {
-+ u32 CDRThresh :10;
-+ u32 reserved :6;
-+ u32 RDRThresh :10;
-+ u32 RDTimeout :4;
-+ u32 reserved2 :1;
-+ u32 enTimeout :1;
-+ } bits;
-+} __packed;
-+
-+union peRingCfg_w {
-+ u32 word;
-+ struct {
-+ u32 ringSize :10;
-+ u32 reserved :6;
-+ u32 ringOffset :8;
-+ u32 reserved2 :8;
-+ } bits;
-+} __packed;
-+
-+union saCmd0 {
-+ u32 word;
-+ struct {
-+ u32 opCode :3;
-+ u32 direction :1;
-+ u32 opGroup :2;
-+ u32 padType :2;
-+ u32 cipher :4;
-+ u32 hash :4;
-+ u32 reserved2 :1;
-+ u32 scPad :1;
-+ u32 extPad :1;
-+ u32 hdrProc :1;
-+ u32 digestLength :4;
-+ u32 ivSource :2;
-+ u32 hashSource :2;
-+ u32 saveIv :1;
-+ u32 saveHash :1;
-+ u32 reserved1 :2;
-+ } bits;
-+} __packed;
-+
-+union saCmd1 {
-+ u32 word;
-+ struct {
-+ u32 copyDigest :1;
-+ u32 copyHeader :1;
-+ u32 copyPayload :1;
-+ u32 copyPad :1;
-+ u32 reserved4 :4;
-+ u32 cipherMode :2;
-+ u32 reserved3 :1;
-+ u32 sslMac :1;
-+ u32 hmac :1;
-+ u32 byteOffset :1;
-+ u32 reserved2 :2;
-+ u32 hashCryptOffset :8;
-+ u32 aesKeyLen :3;
-+ u32 reserved1 :1;
-+ u32 aesDecKey :1;
-+ u32 seqNumCheck :1;
-+ u32 reserved0 :2;
-+ } bits;
-+} __packed;
-+
-+struct saRecord_s {
-+ union saCmd0 saCmd0;
-+ union saCmd1 saCmd1;
-+ u32 saKey[8];
-+ u32 saIDigest[8];
-+ u32 saODigest[8];
-+ u32 saSpi;
-+ u32 saSeqNum[2];
-+ u32 saSeqNumMask[2];
-+ u32 saNonce;
-+} __packed;
-+
-+struct saState_s {
-+ u32 stateIv[4];
-+ u32 stateByteCnt[2];
-+ u32 stateIDigest[8];
-+} __packed;
-+
-+union peCrtlStat_w {
-+ u32 word;
-+ struct {
-+ u32 hostReady :1;
-+ u32 peReady :1;
-+ u32 reserved :1;
-+ u32 initArc4 :1;
-+ u32 hashFinal :1;
-+ u32 haltMode :1;
-+ u32 prngMode :2;
-+ u32 padValue :8;
-+ u32 errStatus :8;
-+ u32 padCrtlStat :8;
-+ } bits;
-+} __packed;
-+
-+union peLength_w {
-+ u32 word;
-+ struct {
-+ u32 length :20;
-+ u32 reserved :2;
-+ u32 hostReady :1;
-+ u32 peReady :1;
-+ u32 byPass :8;
-+ } bits;
-+} __packed;
-+
-+struct eip93_descriptor_s {
-+ union peCrtlStat_w peCrtlStat;
-+ u32 srcAddr;
-+ u32 dstAddr;
-+ u32 saAddr;
-+ u32 stateAddr;
-+ u32 arc4Addr;
-+ u32 userId;
-+ union peLength_w peLength;
-+} __packed;
-+
-+#endif
---- a/drivers/crypto/Kconfig
-+++ b/drivers/crypto/Kconfig
-@@ -824,4 +824,6 @@ config CRYPTO_DEV_SA2UL
- source "drivers/crypto/keembay/Kconfig"
- source "drivers/crypto/aspeed/Kconfig"
-
-+source "drivers/crypto/mtk-eip93/Kconfig"
-+
- endif # CRYPTO_HW
---- a/drivers/crypto/Makefile
-+++ b/drivers/crypto/Makefile
-@@ -53,3 +53,4 @@ obj-y += xilinx/
- obj-y += hisilicon/
- obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
- obj-y += keembay/
-+obj-$(CONFIG_CRYPTO_DEV_EIP93) += mtk-eip93/
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
-@@ -563,8 +563,28 @@ static int __init bootcmdline_scan_chose
+@@ -564,8 +564,28 @@ static int __init bootcmdline_scan_chose
#endif /* CONFIG_OF_EARLY_FLATTREE */
bool dt_bootargs = false;
/*
-@@ -578,6 +598,14 @@ static void __init bootcmdline_init(void
+@@ -579,6 +599,14 @@ static void __init bootcmdline_init(void
}
/*
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
-@@ -705,7 +705,6 @@ static void __init arch_mem_init(char **
+@@ -706,7 +706,6 @@ static void __init arch_mem_init(char **
mips_reserve_vmcore();
mips_parse_crashkernel();
/*
* In order to reduce the possibility of kernel panic when failed to
-@@ -841,6 +840,7 @@ void __init setup_arch(char **cmdline_p)
+@@ -842,6 +841,7 @@ void __init setup_arch(char **cmdline_p)
cpu_cache_init();
paging_init();
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
-@@ -467,6 +467,9 @@ uart_get_baud_rate(struct uart_port *por
+@@ -480,6 +480,9 @@ uart_get_baud_rate(struct uart_port *por
break;
}
+++ /dev/null
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLK_MTMIPS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT2880_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_RALINK=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IP17XX_PHY=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_AUTO_PFN_OFFSET=y
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_L1_CACHE_SHIFT=4
-CONFIG_MIPS_L1_CACHE_SHIFT_4=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_LZMA_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_SPLIT_WRGG_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MDIO_RT2880=y
-CONFIG_NET_RALINK_RT2880=y
-CONFIG_NET_RALINK_SOC=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_VENDOR_RALINK=y
-CONFIG_NLS=m
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-# CONFIG_PHY_MT7621_PCI is not set
-# CONFIG_PHY_RALINK_USB is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_AW9523 is not set
-CONFIG_PINCTRL_RALINK=y
-CONFIG_PINCTRL_RT2880=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RALINK=y
-CONFIG_RALINK_WDT=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SOC_MT7620 is not set
-# CONFIG_SOC_MT7621 is not set
-CONFIG_SOC_RT288X=y
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB=m
-CONFIG_USB_COMMON=m
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_HCD_PLATFORM=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_PLATFORM=m
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
+++ /dev/null
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_SYSTICK_QUIRK=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_MTMIPS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT305X_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_WATCHDOG=y
-# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_JIMAGE_FW=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK_ESW_RT3050=y
-CONFIG_NET_RALINK_RT3050=y
-CONFIG_NET_RALINK_SOC=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_VENDOR_RALINK=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-# CONFIG_PHY_MT7621_PCI is not set
-CONFIG_PHY_RALINK_USB=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_AW9523 is not set
-CONFIG_PINCTRL_RALINK=y
-CONFIG_PINCTRL_RT305X=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RALINK=y
-# CONFIG_RALINK_ILL_ACC is not set
-CONFIG_RALINK_WDT=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SOC_MT7620 is not set
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-CONFIG_SOC_RT305X=y
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
+++ /dev/null
-CONFIG_AR8216_PHY=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLK_MTMIPS=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_DIEI=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_RIXI=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CPU_SUPPORTS_MSA=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_PINCTRL=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT3883_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_RALINK=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_INTC=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-# CONFIG_MIPS_NO_APPENDED_DTB is not set
-CONFIG_MIPS_RAW_APPENDED_DTB=y
-CONFIG_MIPS_SPRAM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
-CONFIG_MTD_SPLIT_SEAMA_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MDIO_RT2880=y
-CONFIG_NET_RALINK_RT3883=y
-CONFIG_NET_RALINK_SOC=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_VENDOR_RALINK=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-# CONFIG_PHY_MT7621_PCI is not set
-CONFIG_PHY_RALINK_USB=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_AW9523 is not set
-CONFIG_PINCTRL_RALINK=y
-CONFIG_PINCTRL_RT3883=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RALINK=y
-CONFIG_RALINK_WDT=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RTL8366_SMI=y
-CONFIG_RTL8367B_PHY=y
-CONFIG_RTL8367_PHY=y
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SOC_MT7620 is not set
-# CONFIG_SOC_MT7621 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-CONFIG_SOC_RT3883=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_MT7621 is not set
-CONFIG_SPI_RT2880=y
-CONFIG_SRCU=y
-CONFIG_SWCONFIG=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=2
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
ucidef_set_poe 60 "$(filter_port_list "$lan_list" "lan9 lan10")"
;;
hpe,1920-8g-poe-65w)
- ucidef_set_poe 65 "$(filter_port_list_reversed "$lan_list" "lan9 lan10")"
+ ucidef_set_poe 65 "$(filter_port_list_reverse "$lan_list" "lan9 lan10")"
;;
hpe,1920-8g-poe-180w)
- ucidef_set_poe 180 "$(filter_port_list_reversed "$lan_list" "lan9 lan10")"
+ ucidef_set_poe 180 "$(filter_port_list_reverse "$lan_list" "lan9 lan10")"
;;
netgear,gs110tpp-v1)
ucidef_set_poe 130 "$(filter_port_list "$lan_list" "lan9 lan10")"
zyxel,gs1900-8hp-v2)
ucidef_set_poe 70 "$lan_list"
;;
+zyxel,gs1900-24ep)
+ ucidef_set_poe 130 "lan1 lan2 lan3 lan4 lan5 lan6 lan7 lan8 lan9 lan10 lan11 lan12"
+ ;;
zyxel,gs1900-24hp-v1|\
zyxel,gs1900-24hp-v2)
ucidef_set_poe 170 "$(filter_port_list "$lan_list" "lan25 lan26")"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-24ep", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-24EP Switch";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&mdio {
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+};
+
+&switch0 {
+ ports {
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+ };
+};
priv->r->set_receive_management_action(i, BPDU, TRAP2CPU);
}
+static void rtl83xx_setup_lldp_traps(struct rtl838x_switch_priv *priv)
+{
+ for (int i = 0; i < priv->cpu_port; i++)
+ priv->r->set_receive_management_action(i, LLDP, TRAP2CPU);
+}
+
static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
int port, bool enable)
{
rtl83xx_vlan_setup(priv);
rtl83xx_setup_bpdu_traps(priv);
+ rtl83xx_setup_lldp_traps(priv);
ds->configure_vlan_while_not_filtering = true;
sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2));
break;
- case LLTP:
+ case LLDP:
sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
- RTL838X_RMA_LLTP_CTRL + ((port >> 4) << 2));
+ RTL838X_RMA_LLDP_CTRL + ((port >> 4) << 2));
break;
default:
break;
PTP,
PTP_UDP,
PTP_ETH2,
- LLTP,
+ LLDP,
EAPOL,
GRATARP,
} rma_ctrl_t;
#define RTL930X_RMA_PTP_CTRL (0x9E88)
#define RTL931X_RMA_PTP_CTRL (0x8834)
-#define RTL838X_RMA_LLTP_CTRL (0x4340)
-#define RTL839X_RMA_LLTP_CTRL (0x124C)
-#define RTL930X_RMA_LLTP_CTRL (0x9EFC)
-#define RTL931X_RMA_LLTP_CTRL (0x8918)
+#define RTL838X_RMA_LLDP_CTRL (0x4340)
+#define RTL839X_RMA_LLDP_CTRL (0x124C)
+#define RTL930X_RMA_LLDP_CTRL (0x9EFC)
+#define RTL931X_RMA_LLDP_CTRL (0x8918)
#define RTL930X_RMA_EAPOL_CTRL (0x9F08)
#define RTL931X_RMA_EAPOL_CTRL (0x8930)
sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
RTL839X_RMA_PTP_CTRL + ((port >> 4) << 2));
break;
- case LLTP:
+ case LLDP:
sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
- RTL839X_RMA_LLTP_CTRL + ((port >> 4) << 2));
+ RTL839X_RMA_LLDP_CTRL + ((port >> 4) << 2));
break;
default:
break;
case PTP_ETH2:
sw_w32_mask(3, value, RTL931X_RMA_PTP_CTRL + (port << 2));
break;
- case LLTP:
- sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_LLTP_CTRL + ((port / 10) << 2));
+ case LLDP:
+ sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_LLDP_CTRL + ((port / 10) << 2));
break;
case EAPOL:
sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_EAPOL_CTRL + ((port / 10) << 2));
int err;
struct rtl838x_eth_priv *priv = bus->priv;
- if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
+ if (priv->phy_is_internal[mii_id])
return rtl839x_read_sds_phy(mii_id, regnum);
if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
struct rtl838x_eth_priv *priv = bus->priv;
int err;
- if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
+ if (priv->phy_is_internal[mii_id])
return rtl839x_write_sds_phy(mii_id, regnum, value);
if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {
/* external RTL821X PHY uses register 0x1e to select media page */
#define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
+#define RTL821X_CHIP_ID 0x6276
+
#define RTL821X_MEDIA_PAGE_AUTO 0
#define RTL821X_MEDIA_PAGE_COPPER 1
#define RTL821X_MEDIA_PAGE_FIBRE 3
/* Read internal PHY ID */
phy_write_paged(phydev, 31, 27, 0x0002);
val = phy_read_paged(phydev, 31, 28);
- if (val != 0x6276) {
+ if (val != RTL821X_CHIP_ID) {
phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
return -1;
}
phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
val = phy_read_paged(phydev, 0x1f, 0x1c);
- if (val != 0x6276) {
+ if (val != RTL821X_CHIP_ID) {
phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
return -1;
}
endef
TARGET_DEVICES += zyxel_gs1900-24e
+define Device/zyxel_gs1900-24ep
+ $(Device/zyxel_gs1900)
+ SOC := rtl8382
+ DEVICE_MODEL := GS1900-24EP
+ ZYXEL_VERS := ABTO
+ DEVICE_PACKAGES += realtek-poe
+endef
+TARGET_DEVICES += zyxel_gs1900-24ep
+
define Device/zyxel_gs1900-24hp-v1
$(Device/zyxel_gs1900)
SOC := rtl8382
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -15896,6 +15896,13 @@ S: Maintained
+@@ -15903,6 +15903,13 @@ S: Maintained
F: include/sound/rt*.h
F: sound/soc/codecs/rt*
FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
SUBTARGETS:=armv8
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
define Target/Description
Build firmware image for Rockchip SoC devices.
friendlyarm,nanopi-r5s)
ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0'
;;
+ sinovoip,rk3568-bpi-r2pro)
+ ucidef_set_interfaces_lan_wan 'lan0 lan1 lan2 lan3' 'eth0'
+ ;;
*)
ucidef_set_interface_lan 'eth0'
;;
;;
friendlyarm,nanopi-r2c-plus|\
friendlyarm,nanopi-r4s|\
- friendlyarm,nanopi-r5s)
+ friendlyarm,nanopi-r5s|\
+ sinovoip,rk3568-bpi-r2pro)
wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1)
lan_mac=$(macaddr_add "$wan_mac" 1)
;;
set_interface_core 20 "eth1"
;;
friendlyarm,nanopi-r5c|\
-radxa,e25)
+radxa,e25|\
+sinovoip,rk3568-bpi-r2pro)
set_interface_core 2 "eth0"
set_interface_core 4 "eth1"
;;
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=33
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARC_EMAC_CORE=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CNP=y
-CONFIG_ARM64_EPAN=y
-CONFIG_ARM64_ERRATUM_2051678=y
-CONFIG_ARM64_ERRATUM_2054223=y
-CONFIG_ARM64_ERRATUM_2067961=y
-CONFIG_ARM64_ERRATUM_2077057=y
-CONFIG_ARM64_ERRATUM_2658417=y
-CONFIG_ARM64_ERRATUM_819472=y
-CONFIG_ARM64_ERRATUM_824069=y
-CONFIG_ARM64_ERRATUM_826319=y
-CONFIG_ARM64_ERRATUM_827319=y
-CONFIG_ARM64_ERRATUM_832075=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_ERRATUM_858921=y
-CONFIG_ARM64_HW_AFDBM=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PAN=y
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_ARM64_RAS_EXTN=y
-CONFIG_ARM64_SME=y
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=48
-# CONFIG_ARM64_VA_BITS_39 is not set
-CONFIG_ARM64_VA_BITS_48=y
-CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
-CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MHU=y
-CONFIG_ARM_MHU_V2=y
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
-CONFIG_ARM_SCMI_CPUFREQ=y
-CONFIG_ARM_SCMI_HAVE_SHMEM=y
-CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
-CONFIG_ARM_SCMI_POWER_CONTROL=y
-CONFIG_ARM_SCMI_POWER_DOMAIN=y
-CONFIG_ARM_SCMI_PROTOCOL=y
-CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
-CONFIG_ARM_SCMI_TRANSPORT_SMC=y
-CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
-CONFIG_ARM_SCPI_CPUFREQ=y
-CONFIG_ARM_SCPI_POWER_DOMAIN=y
-CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_ARM_SMMU=y
-CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
-# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
-CONFIG_ARM_SMMU_V3=y
-# CONFIG_ARM_SMMU_V3_SVA is not set
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GPIO=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BRCMSTB_GISB_ARB=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CHARGER_GPIO=y
-# CONFIG_CHARGER_RK817 is not set
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_PX30=y
-CONFIG_CLK_RK3308=y
-CONFIG_CLK_RK3328=y
-CONFIG_CLK_RK3368=y
-CONFIG_CLK_RK3399=y
-CONFIG_CLK_RK3568=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_RK808=y
-CONFIG_COMMON_CLK_ROCKCHIP=y
-CONFIG_COMMON_CLK_SCMI=y
-CONFIG_COMMON_CLK_SCPI=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_ISOLATION=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRASH_DUMP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC64=y
-CONFIG_CRC64_ROCKSOFT=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRC64_ROCKSOFT=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
-CONFIG_CRYPTO_CRYPTD=y
-# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_POLYVAL=y
-CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SM3=y
-CONFIG_CRYPTO_SM3_NEON=y
-CONFIG_CRYPTO_SM4=y
-CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
-CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEVFREQ_GOV_PASSIVE is not set
-CONFIG_DEVFREQ_GOV_PERFORMANCE=y
-CONFIG_DEVFREQ_GOV_POWERSAVE=y
-CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
-CONFIG_DEVFREQ_GOV_USERSPACE=y
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DEVMEM=y
-# CONFIG_DEVPORT is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_GENPD=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DWMAC_DWC_QOS_ETH=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_DWMAC_ROCKCHIP=y
-CONFIG_DW_WATCHDOG=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EMAC_ROCKCHIP=y
-CONFIG_ENERGY_MODEL=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FANOTIFY=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FORTIFY_SOURCE is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_DWAPB=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_ROCKCHIP=y
-CONFIG_GPIO_SYSCON=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HOTPLUG_PCI=y
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_PCIE is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_HWMON=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HW_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_RK3X=y
-CONFIG_IIO=y
-# CONFIG_IIO_SCMI is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_INDIRECT_PIO=y
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_LEDS=y
-CONFIG_INPUT_MATRIXKMAP=y
-CONFIG_INPUT_RK805_PWRKEY=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
-CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
-CONFIG_IOMMU_DMA=y
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOMMU_IO_PGTABLE=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_DART is not set
-CONFIG_IOMMU_IO_PGTABLE_LPAE=y
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IO_STRICT_DEVMEM is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JUMP_LABEL=y
-CONFIG_KALLSYMS=y
-CONFIG_KCMP=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEXEC_FILE=y
-CONFIG_KSM=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_SYSCON=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_PANIC=y
-CONFIG_LIBCRC32C=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MDIO_BUS_MUX_GPIO=y
-CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_KHADAS_MCU is not set
-CONFIG_MFD_RK808=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=32
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_DW=y
-# CONFIG_MMC_DW_BLUEFIELD is not set
-# CONFIG_MMC_DW_EXYNOS is not set
-# CONFIG_MMC_DW_HI3798CV200 is not set
-# CONFIG_MMC_DW_K3 is not set
-# CONFIG_MMC_DW_PCI is not set
-CONFIG_MMC_DW_PLTFM=y
-CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_ARASAN=y
-CONFIG_MMC_SDHCI_OF_DWCMSHC=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MOTORCOMM_PHY=y
-CONFIG_MQ_IOSCHED_DEADLINE=y
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=256
-CONFIG_NVMEM=y
-CONFIG_NVMEM_ROCKCHIP_EFUSE=y
-# CONFIG_NVMEM_ROCKCHIP_OTP is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVME_CORE=y
-# CONFIG_NVME_HWMON is not set
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DYNAMIC=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_OVERLAY=y
-CONFIG_OF_RESOLVE=y
-# CONFIG_OVERLAY_FS_XINO_AUTO is not set
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_PME=y
-CONFIG_PCIE_ROCKCHIP=y
-CONFIG_PCIE_ROCKCHIP_DW_HOST=y
-CONFIG_PCIE_ROCKCHIP_HOST=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_STUB=y
-CONFIG_PCS_XPCS=y
-CONFIG_PGTABLE_LEVELS=4
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_ROCKCHIP_DP=y
-# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
-CONFIG_PHY_ROCKCHIP_EMMC=y
-# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
-# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
-# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
-CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
-CONFIG_PHY_ROCKCHIP_PCIE=y
-CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
-CONFIG_PHY_ROCKCHIP_TYPEC=y
-CONFIG_PHY_ROCKCHIP_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_RK805=y
-CONFIG_PINCTRL_ROCKCHIP=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PL330_DMA=y
-CONFIG_PLATFORM_MHU=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_PM_OPP=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_SUPPLY_HWMON=y
-CONFIG_PPS=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_BUILD=y
-CONFIG_PREEMPT_COUNT=y
-# CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
-CONFIG_PRINTK_TIME=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_VMCORE=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ROCKCHIP=y
-CONFIG_PWM_SYSFS=y
-# CONFIG_QFMT_V2 is not set
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-CONFIG_RAID_ATTRS=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-# CONFIG_RAVE_SP_CORE is not set
-CONFIG_RCU_TRACE=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ARM_SCMI=y
-CONFIG_REGULATOR_FAN53555=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_REGULATOR_RK808=y
-CONFIG_RELOCATABLE=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SCMI=y
-CONFIG_RFS_ACCEL=y
-CONFIG_ROCKCHIP_GRF=y
-CONFIG_ROCKCHIP_IODOMAIN=y
-CONFIG_ROCKCHIP_IOMMU=y
-CONFIG_ROCKCHIP_MBOX=y
-CONFIG_ROCKCHIP_PHY=y
-CONFIG_ROCKCHIP_PM_DOMAINS=y
-# CONFIG_ROCKCHIP_SARADC is not set
-CONFIG_ROCKCHIP_THERMAL=y
-CONFIG_ROCKCHIP_TIMER=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RSEQ=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_RK808=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_NVMEM=y
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_SCSI_SAS_ATTRS=y
-CONFIG_SCSI_SAS_HOST_SMP=y
-CONFIG_SCSI_SAS_LIBSAS=y
-# CONFIG_SECURITY_DMESG_RESTRICT is not set
-CONFIG_SENSORS_ARM_SCMI=y
-CONFIG_SENSORS_ARM_SCPI=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_AMBAKMI=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_DYNAMIC=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_ROCKCHIP=y
-CONFIG_SPI_ROCKCHIP_SFC=y
-CONFIG_SPI_SPIDEV=y
-# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
-CONFIG_SQUASHFS_DECOMP_SINGLE=y
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FILE_CACHE=y
-# CONFIG_SQUASHFS_FILE_DIRECT is not set
-CONFIG_SRAM=y
-CONFIG_SRCU=y
-CONFIG_STACKPROTECTOR=y
-CONFIG_STACKPROTECTOR_PER_TASK=y
-CONFIG_STACKPROTECTOR_STRONG=y
-CONFIG_STACKTRACE=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_STRICT_DEVMEM=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_SWAP is not set
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFS_SYSCALL=y
-# CONFIG_TEXTSEARCH is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_EMULATION=y
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-CONFIG_TRANS_TABLE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TYPEC=y
-# CONFIG_TYPEC_ANX7411 is not set
-CONFIG_TYPEC_FUSB302=y
-# CONFIG_TYPEC_HD3SS3220 is not set
-# CONFIG_TYPEC_MUX_FSA4480 is not set
-# CONFIG_TYPEC_MUX_PI3USB30532 is not set
-# CONFIG_TYPEC_RT1719 is not set
-# CONFIG_TYPEC_STUSB160X is not set
-# CONFIG_TYPEC_TCPCI is not set
-CONFIG_TYPEC_TCPM=y
-# CONFIG_TYPEC_TPS6598X is not set
-# CONFIG_TYPEC_WUSB3801 is not set
-# CONFIG_UACCE is not set
-# CONFIG_UCLAMP_TASK is not set
-# CONFIG_UEVENT_HELPER is not set
-CONFIG_UNINLINE_SPIN_UNLOCK=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_HOST=y
-CONFIG_USB_DWC3_OF_SIMPLE=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-CONFIG_USB_HID=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PLATFORM=y
-# CONFIG_VIRTIO_MENU is not set
-CONFIG_VMAP_STACK=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XARRAY_MULTI=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
--- /dev/null
+CONFIG_64BIT=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=10
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_SELECTS_KEXEC_FILE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARC_EMAC_CORE=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_EPAN=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_858921=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=48
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_MHU=y
+CONFIG_ARM_MHU_V2=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
+CONFIG_ARM_SCMI_CPUFREQ=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_POWER_CONTROL=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CHARGER_GPIO=y
+# CONFIG_CHARGER_RK817 is not set
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3568=y
+CONFIG_CLK_RK3588=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC64=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_POLYVAL=y
+CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SM3=y
+CONFIG_CRYPTO_SM3_NEON=y
+CONFIG_CRYPTO_SM4=y
+CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
+CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DEVMEM=y
+# CONFIG_DEVPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_GENPD=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_ROCKCHIP=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EMAC_ROCKCHIP=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FORTIFY_SOURCE is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FUNCTION_ALIGNMENT=4
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_ROCKCHIP=y
+CONFIG_GPIO_SYSCON=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HWMON=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_ROCKCHIP=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_RK3X=y
+CONFIG_IIO=y
+# CONFIG_IIO_SCMI is not set
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INDIRECT_PIO=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_RK805_PWRKEY=y
+# CONFIG_IOMMUFD is not set
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_IO_PGTABLE=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_DART is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_FILE=y
+CONFIG_KSM=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIATEK_GE_PHY=y
+# CONFIG_MEDIATEK_GE_SOC_PHY is not set
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_KHADAS_MCU is not set
+CONFIG_MFD_RK8XX=y
+CONFIG_MFD_RK8XX_I2C=y
+CONFIG_MFD_RK8XX_SPI=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_DW=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_MQ_IOSCHED_DEADLINE=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_FLAGS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_MT7530_MDIO=y
+CONFIG_NET_DSA_MT7530_MMIO=y
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=256
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+# CONFIG_NVMEM_ROCKCHIP_OTP is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVME_CORE=y
+# CONFIG_NVME_HWMON is not set
+# CONFIG_NVME_MULTIPATH is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
+# CONFIG_OVERLAY_FS_XINO_AUTO is not set
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_PME=y
+CONFIG_PCIE_ROCKCHIP=y
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+CONFIG_PCIE_ROCKCHIP_HOST=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_STUB=y
+CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PCS_XPCS=y
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_ROCKCHIP_DP=y
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
+CONFIG_PHY_ROCKCHIP_EMMC=y
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RK805=y
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PL330_DMA=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PPS=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_RAID_ATTRS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_RCU_TRACE=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ARM_SCMI=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
+CONFIG_RFS_ACCEL=y
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_ROCKCHIP_MBOX=y
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_ROCKCHIP_SARADC is not set
+CONFIG_ROCKCHIP_THERMAL=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_HYM8563=y
+CONFIG_RTC_DRV_RK808=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SENSORS_ARM_SCMI=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_ROCKCHIP_SFC=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SRAM=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKTRACE=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_SWAP is not set
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFS_SYSCALL=y
+# CONFIG_TEXTSEARCH is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TRANS_TABLE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TYPEC=y
+# CONFIG_TYPEC_ANX7411 is not set
+CONFIG_TYPEC_FUSB302=y
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_MUX_FSA4480 is not set
+# CONFIG_TYPEC_MUX_GPIO_SBU is not set
+# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# CONFIG_TYPEC_RT1719 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+# CONFIG_TYPEC_TCPCI is not set
+CONFIG_TYPEC_TCPM=y
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_TYPEC_WUSB3801 is not set
+# CONFIG_UCLAMP_TASK is not set
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_HOST=y
+CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
endef
TARGET_DEVICES += radxa_rock-pi-e
+define Device/sinovoip_bpi-r2-pro
+ DEVICE_VENDOR := Sinovoip
+ DEVICE_MODEL := Bananapi-R2 Pro
+ SOC := rk3568
+ SUPPORTED_DEVICES := sinovoip,rk3568-bpi-r2pro
+ DEVICE_PACKAGES := kmod-ata-ahci-dwc
+endef
+TARGET_DEVICES += sinovoip_bpi-r2-pro
+
define Device/xunlong_orangepi-r1-plus
DEVICE_VENDOR := Xunlong
DEVICE_MODEL := Orange Pi R1 Plus
+++ /dev/null
-From b75a52b0dda353aeefb4830a320589a363f49579 Mon Sep 17 00:00:00 2001
-From: Shawn Lin <shawn.lin@rock-chips.com>
-Date: Thu, 2 Feb 2023 08:35:16 +0800
-Subject: [PATCH] mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for
- rockchip platform
-
-For Rockchip platform, DLL bypass bit and start bit need to be set if
-DLL is not locked. And adjust pre-change delay to 0x3 for better signal
-test result.
-
-Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
-Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
---- a/drivers/mmc/host/sdhci-of-dwcmshc.c
-+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
-@@ -48,6 +48,7 @@
- #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
- #define DWCMSHC_EMMC_DLL_START_POINT 16
- #define DWCMSHC_EMMC_DLL_INC 8
-+#define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
- #define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
- #define DLL_TXCLK_TAPNUM_DEFAULT 0x10
- #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
-@@ -60,6 +61,7 @@
- #define DLL_RXCLK_NO_INVERTER 1
- #define DLL_RXCLK_INVERTER 0
- #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
-+#define DLL_RXCLK_ORI_GATE BIT(31)
- #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
- #define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
- #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
-@@ -234,9 +236,12 @@ static void dwcmshc_rk3568_set_clock(str
- sdhci_writel(host, extra, reg);
-
- if (clock <= 52000000) {
-- /* Disable DLL and reset both of sample and drive clock */
-- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
-- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
-+ /*
-+ * Disable DLL and reset both of sample and drive clock.
-+ * The bypass bit and start bit need to be set if DLL is not locked.
-+ */
-+ sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
-+ sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
- sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
- /*
-@@ -279,7 +284,7 @@ static void dwcmshc_rk3568_set_clock(str
- }
-
- extra = 0x1 << 16 | /* tune clock stop en */
-- 0x2 << 17 | /* pre-change delay */
-+ 0x3 << 17 | /* pre-change delay */
- 0x3 << 19; /* post-change delay */
- sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
-
+++ /dev/null
-From 49502408007b77ff290ce62e6218cefaeedcb31a Mon Sep 17 00:00:00 2001
-From: Vasily Khoruzhick <anarsoul@gmail.com>
-Date: Thu, 9 Mar 2023 17:03:49 -0800
-Subject: [PATCH] mmc: sdhci-of-dwcmshc: properly determine max clock on
- Rockchip
-
-Currently .get_max_clock returns the current clock rate for cclk_emmc
-on rk35xx, thus max clock gets set to whatever bootloader set it to.
-
-In case of u-boot, it is intentionally reset to 50 MHz if it boots
-from eMMC, see mmc_deinit() in u-boot sources. As a result, HS200 and
-HS400 modes are never selected by Linux, because dwcmshc_rk35xx_postinit
-clears appropriate caps if host->mmc->f_max is < 52MHz
-
-cclk_emmc is not a fixed clock on rk35xx, so using
-sdhci_pltfm_clk_get_max_clock is not appropriate here.
-
-Implement rk35xx_get_max_clock that returns actual max clock for cclk_emmc.
-
-Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Acked-by: Adrian Hunter <adrian.hunter@intel.com>
-Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/sdhci-of-dwcmshc.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/drivers/mmc/host/sdhci-of-dwcmshc.c
-+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
-@@ -126,6 +126,13 @@ static unsigned int dwcmshc_get_max_cloc
- return pltfm_host->clock;
- }
-
-+static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
-+{
-+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-+
-+ return clk_round_rate(pltfm_host->clk, ULONG_MAX);
-+}
-+
- static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
- struct mmc_request *mrq)
- {
-@@ -343,7 +350,7 @@ static const struct sdhci_ops sdhci_dwcm
- .set_clock = dwcmshc_rk3568_set_clock,
- .set_bus_width = sdhci_set_bus_width,
- .set_uhs_signaling = dwcmshc_set_uhs_signaling,
-- .get_max_clock = sdhci_pltfm_clk_get_max_clock,
-+ .get_max_clock = rk35xx_get_max_clock,
- .reset = rk35xx_sdhci_reset,
- .adma_write_desc = dwcmshc_adma_write_desc,
- };
+++ /dev/null
-From 004589ff9df5b75672a78b6c3c4cba93202b14c9 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 25 Mar 2023 15:40:20 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C
-
-The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
-chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 40 +++++++++++++++++++
- 2 files changed, 41 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
-@@ -0,0 +1,40 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3328-nanopi-r2s.dts"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R2C";
-+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
-+};
-+
-+&gmac2io {
-+ phy-handle = <&yt8521s>;
-+ tx_delay = <0x22>;
-+ rx_delay = <0x12>;
-+
-+ mdio {
-+ /delete-node/ ethernet-phy@1;
-+
-+ yt8521s: ethernet-phy@3 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <3>;
-+
-+ motorcomm,clk-out-frequency-hz = <125000000>;
-+ motorcomm,keep-pll-enabled;
-+ motorcomm,auto-sleep-disabled;
-+
-+ pinctrl-0 = <ð_phy_reset_pin>;
-+ pinctrl-names = "default";
-+ reset-assert-us = <10000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+};
+++ /dev/null
-From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Sat, 3 Dec 2022 15:41:49 +0800
-Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus
-
-Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
-
-This device is similar to the NanoPi R2S, and has a 16MB
-SPI NOR (mx25l12805d). The reset button is changed to
-directly reset the power supply, another detail is that
-both network ports have independent MAC addresses.
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++
- 2 files changed, 374 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-@@ -0,0 +1,373 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Based on rk3328-nanopi-r2s.dts, which is:
-+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
-+ */
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include "rk3328.dtsi"
-+
-+/ {
-+ model = "Xunlong Orange Pi R1 Plus";
-+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
-+
-+ aliases {
-+ ethernet1 = &rtl8153;
-+ mmc0 = &sdmmc;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ gmac_clk: gmac-clock {
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ clock-output-names = "gmac_clkin";
-+ #clock-cells = <0>;
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
-+ pinctrl-names = "default";
-+
-+ led-0 {
-+ function = LED_FUNCTION_LAN;
-+ color = <LED_COLOR_ID_GREEN>;
-+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ led-1 {
-+ function = LED_FUNCTION_STATUS;
-+ color = <LED_COLOR_ID_RED>;
-+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "heartbeat";
-+ };
-+
-+ led-2 {
-+ function = LED_FUNCTION_WAN;
-+ color = <LED_COLOR_ID_GREEN>;
-+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+
-+ vcc_sd: sdmmc-regulator {
-+ compatible = "regulator-fixed";
-+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
-+ pinctrl-0 = <&sdmmc0m1_pin>;
-+ pinctrl-names = "default";
-+ regulator-name = "vcc_sd";
-+ regulator-boot-on;
-+ vin-supply = <&vcc_io>;
-+ };
-+
-+ vcc_sys: vcc-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vdd_5v_lan: vdd-5v-lan-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-0 = <&lan_vdd_pin>;
-+ pinctrl-names = "default";
-+ regulator-name = "vdd_5v_lan";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ vin-supply = <&vcc_sys>;
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&display_subsystem {
-+ status = "disabled";
-+};
-+
-+&gmac2io {
-+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
-+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
-+ clock_in_out = "input";
-+ phy-handle = <&rtl8211e>;
-+ phy-mode = "rgmii";
-+ phy-supply = <&vcc_io>;
-+ pinctrl-0 = <&rgmiim1_pins>;
-+ pinctrl-names = "default";
-+ snps,aal;
-+ rx_delay = <0x18>;
-+ tx_delay = <0x24>;
-+ status = "okay";
-+
-+ mdio {
-+ compatible = "snps,dwmac-mdio";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ rtl8211e: ethernet-phy@1 {
-+ reg = <1>;
-+ pinctrl-0 = <ð_phy_reset_pin>;
-+ pinctrl-names = "default";
-+ reset-assert-us = <10000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+};
-+
-+&i2c1 {
-+ status = "okay";
-+
-+ rk805: pmic@18 {
-+ compatible = "rockchip,rk805";
-+ reg = <0x18>;
-+ interrupt-parent = <&gpio1>;
-+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <1>;
-+ clock-output-names = "xin32k", "rk805-clkout2";
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ pinctrl-0 = <&pmic_int_l>;
-+ pinctrl-names = "default";
-+ rockchip,system-power-controller;
-+ wakeup-source;
-+
-+ vcc1-supply = <&vcc_sys>;
-+ vcc2-supply = <&vcc_sys>;
-+ vcc3-supply = <&vcc_sys>;
-+ vcc4-supply = <&vcc_sys>;
-+ vcc5-supply = <&vcc_io>;
-+ vcc6-supply = <&vcc_sys>;
-+
-+ regulators {
-+ vdd_log: DCDC_REG1 {
-+ regulator-name = "vdd_log";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1450000>;
-+ regulator-ramp-delay = <12500>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1000000>;
-+ };
-+ };
-+
-+ vdd_arm: DCDC_REG2 {
-+ regulator-name = "vdd_arm";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1450000>;
-+ regulator-ramp-delay = <12500>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <950000>;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc_io: DCDC_REG4 {
-+ regulator-name = "vcc_io";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcc_18: LDO_REG1 {
-+ regulator-name = "vcc_18";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcc18_emmc: LDO_REG2 {
-+ regulator-name = "vcc18_emmc";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vdd_10: LDO_REG3 {
-+ regulator-name = "vdd_10";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1000000>;
-+ regulator-max-microvolt = <1000000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1000000>;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&io_domains {
-+ pmuio-supply = <&vcc_io>;
-+ vccio1-supply = <&vcc_io>;
-+ vccio2-supply = <&vcc18_emmc>;
-+ vccio3-supply = <&vcc_io>;
-+ vccio4-supply = <&vcc_io>;
-+ vccio5-supply = <&vcc_io>;
-+ vccio6-supply = <&vcc_io>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ gmac2io {
-+ eth_phy_reset_pin: eth-phy-reset-pin {
-+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+ };
-+
-+ leds {
-+ lan_led_pin: lan-led-pin {
-+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ sys_led_pin: sys-led-pin {
-+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wan_led_pin: wan-led-pin {
-+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ lan {
-+ lan_vdd_pin: lan-vdd-pin {
-+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int_l: pmic-int-l {
-+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+};
-+
-+&pwm2 {
-+ status = "okay";
-+};
-+
-+&sdmmc {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-+ pinctrl-names = "default";
-+ vmmc-supply = <&vcc_sd>;
-+ status = "okay";
-+};
-+
-+&spi0 {
-+ status = "okay";
-+
-+ flash@0 {
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <50000000>;
-+ };
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <0>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&u2phy {
-+ status = "okay";
-+};
-+
-+&u2phy_host {
-+ status = "okay";
-+};
-+
-+&u2phy_otg {
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb20_otg {
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
-+&usbdrd3 {
-+ dr_mode = "host";
-+ status = "okay";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ /* Second port is for USB 3.0 */
-+ rtl8153: device@2 {
-+ compatible = "usbbda,8153";
-+ reg = <2>;
-+ };
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
+++ /dev/null
-From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 25 Mar 2023 15:40:22 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS
-
-The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
-the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
-identical to OrangePi R1 Plus.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++
- 2 files changed, 41 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-@@ -0,0 +1,40 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
-+ * (http://www.orangepi.org)
-+ *
-+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3328-orangepi-r1-plus.dts"
-+
-+/ {
-+ model = "Xunlong Orange Pi R1 Plus LTS";
-+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
-+};
-+
-+&gmac2io {
-+ phy-handle = <&yt8531c>;
-+ tx_delay = <0x19>;
-+ rx_delay = <0x05>;
-+
-+ mdio {
-+ /delete-node/ ethernet-phy@1;
-+
-+ yt8531c: ethernet-phy@0 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <0>;
-+
-+ motorcomm,clk-out-frequency-hz = <125000000>;
-+ motorcomm,keep-pll-enabled;
-+ motorcomm,auto-sleep-disabled;
-+
-+ pinctrl-0 = <ð_phy_reset_pin>;
-+ pinctrl-names = "default";
-+ reset-assert-us = <15000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+};
+++ /dev/null
-From c6629b9a6738a64507478527da6c7b83c10a6d2c Mon Sep 17 00:00:00 2001
-From: Vasily Khoruzhick <anarsoul@gmail.com>
-Date: Tue, 7 Mar 2023 22:32:40 -0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyElec Nanopi R5S
-
-FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device.
-
-Board Specifications
-- Rockchip RK3568
-- 2 or 4GB LPDDR4X
-- 8GB or 16GB eMMC, SD card slot
-- GbE LAN (Native)
-- 2x 2.5G LAN (PCIe)
-- M.2 Connector
-- HDMI 2.0, MIPI DSI/CSI
-- 2xUSB 3.0 Host
-- USB Type C PD, 5V/9V/12V
-- GPIO: 12-pin 0.5mm FPC connector
-
-Based on Tianling Shen's <cnsztl@gmail.com> work.
-
-Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Link: https://lore.kernel.org/r/20230308063240.107178-2-anarsoul@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 713 ++++++++++++++++++
- 2 files changed, 714 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -74,4 +74,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -0,0 +1,713 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyelec.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R5S";
-+ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
-+
-+ aliases {
-+ ethernet0 = &gmac0;
-+ mmc0 = &sdmmc0;
-+ mmc1 = &sdhci;
-+ };
-+
-+ chosen: chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ hdmi-con {
-+ compatible = "hdmi-connector";
-+ type = "a";
-+
-+ port {
-+ hdmi_con_in: endpoint {
-+ remote-endpoint = <&hdmi_out_con>;
-+ };
-+ };
-+ };
-+
-+ gpio-leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
-+
-+ led-lan1 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_LAN;
-+ function-enumerator = <1>;
-+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ led-lan2 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_LAN;
-+ function-enumerator = <2>;
-+ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ power_led: led-power {
-+ color = <LED_COLOR_ID_RED>;
-+ function = LED_FUNCTION_POWER;
-+ linux,default-trigger = "heartbeat";
-+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ led-wan {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_WAN;
-+ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+
-+ vdd_usbc: vdd-usbc-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vdd_usbc";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vcc3v3_sys: vcc3v3-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc5v0_sys: vcc5v0-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc3v3_pcie: vcc3v3-pcie-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_pcie";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ enable-active-high;
-+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-+ startup-delay-us = <200000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc5v0_usb: vcc5v0-usb-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_usb";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb_host_en>;
-+ regulator-name = "vcc5v0_usb_host";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_usb>;
-+ };
-+
-+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
-+ regulator-name = "vcc5v0_usb_otg";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_usb>;
-+ };
-+
-+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+};
-+
-+&combphy0 {
-+ status = "okay";
-+};
-+
-+&combphy1 {
-+ status = "okay";
-+};
-+
-+&combphy2 {
-+ status = "okay";
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gmac0 {
-+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
-+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
-+ assigned-clock-rates = <0>, <125000000>;
-+ clock_in_out = "output";
-+ phy-handle = <&rgmii_phy0>;
-+ phy-mode = "rgmii-id";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac0_miim
-+ &gmac0_tx_bus2
-+ &gmac0_rx_bus2
-+ &gmac0_rgmii_clk
-+ &gmac0_rgmii_bus>;
-+ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
-+ snps,reset-active-low;
-+ /* Reset time is 15ms, 50ms for rtl8211f */
-+ snps,reset-delays-us = <0 15000 50000>;
-+ tx_delay = <0x3c>;
-+ rx_delay = <0x2f>;
-+ status = "okay";
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu>;
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ avdd-0v9-supply = <&vdda0v9_image>;
-+ avdd-1v8-supply = <&vcca1v8_image>;
-+ status = "okay";
-+};
-+
-+&hdmi_in {
-+ hdmi_in_vp0: endpoint {
-+ remote-endpoint = <&vp0_out_hdmi>;
-+ };
-+};
-+
-+&hdmi_out {
-+ hdmi_out_con: endpoint {
-+ remote-endpoint = <&hdmi_con_in>;
-+ };
-+};
-+
-+&hdmi_sound {
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ vdd_cpu: regulator@1c {
-+ compatible = "tcs,tcs4525";
-+ reg = <0x1c>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1150000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ rk809: pmic@20 {
-+ compatible = "rockchip,rk809";
-+ reg = <0x20>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int>;
-+ rockchip,system-power-controller;
-+ vcc1-supply = <&vcc3v3_sys>;
-+ vcc2-supply = <&vcc3v3_sys>;
-+ vcc3-supply = <&vcc3v3_sys>;
-+ vcc4-supply = <&vcc3v3_sys>;
-+ vcc5-supply = <&vcc3v3_sys>;
-+ vcc6-supply = <&vcc3v3_sys>;
-+ vcc7-supply = <&vcc3v3_sys>;
-+ vcc8-supply = <&vcc3v3_sys>;
-+ vcc9-supply = <&vcc3v3_sys>;
-+ wakeup-source;
-+
-+ regulators {
-+ vdd_logic: DCDC_REG1 {
-+ regulator-name = "vdd_logic";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_gpu: DCDC_REG2 {
-+ regulator-name = "vdd_gpu";
-+ regulator-always-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vdd_npu: DCDC_REG4 {
-+ regulator-name = "vdd_npu";
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8: DCDC_REG5 {
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_image: LDO_REG1 {
-+ regulator-name = "vdda0v9_image";
-+ regulator-min-microvolt = <950000>;
-+ regulator-max-microvolt = <950000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda_0v9: LDO_REG2 {
-+ regulator-name = "vdda_0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_pmu: LDO_REG3 {
-+ regulator-name = "vdda0v9_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vccio_acodec: LDO_REG4 {
-+ regulator-name = "vccio_acodec";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd: LDO_REG5 {
-+ regulator-name = "vccio_sd";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_pmu: LDO_REG6 {
-+ regulator-name = "vcc3v3_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcca_1v8: LDO_REG7 {
-+ regulator-name = "vcca_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca1v8_pmu: LDO_REG8 {
-+ regulator-name = "vcca1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcca1v8_image: LDO_REG9 {
-+ regulator-name = "vcca1v8_image";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_3v3: SWITCH_REG1 {
-+ regulator-name = "vcc_3v3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_sd: SWITCH_REG2 {
-+ regulator-name = "vcc3v3_sd";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+
-+ };
-+};
-+
-+&i2c5 {
-+ status = "okay";
-+
-+ hym8563: rtc@51 {
-+ compatible = "haoyu,hym8563";
-+ reg = <0x51>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <0>;
-+ clock-output-names = "rtcic_32kout";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hym8563_int>;
-+ wakeup-source;
-+ };
-+};
-+
-+&i2s0_8ch {
-+ status = "okay";
-+};
-+
-+&i2s1_8ch {
-+ rockchip,trcm-sync-tx-only;
-+ status = "okay";
-+};
-+
-+&mdio0 {
-+ rgmii_phy0: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ pinctrl-0 = <ð_phy0_reset_pin>;
-+ pinctrl-names = "default";
-+ reset-assert-us = <10000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
-+ };
-+};
-+
-+&pcie2x1 {
-+ num-lanes = <1>;
-+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+};
-+
-+&pcie30phy {
-+ data-lanes = <1 2>;
-+ status = "okay";
-+};
-+
-+&pcie3x1 {
-+ num-lanes = <1>;
-+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie>;
-+ status = "okay";
-+};
-+
-+&pcie3x2 {
-+ num-lanes = <1>;
-+ num-ib-windows = <8>;
-+ num-ob-windows = <8>;
-+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ gmac0 {
-+ eth_phy0_reset_pin: eth-phy0-reset-pin {
-+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+ };
-+
-+ gpio-leds {
-+ lan1_led_pin: lan1-led-pin {
-+ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ lan2_led_pin: lan2-led-pin {
-+ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ power_led_pin: power-led-pin {
-+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wan_led_pin: wan-led-pin {
-+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ hym8563 {
-+ hym8563_int: hym8563-int {
-+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int: pmic-int {
-+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ usb {
-+ vcc5v0_usb_host_en: vcc5v0-usb-host-en {
-+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
-+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pmu_io_domains {
-+ pmuio1-supply = <&vcc3v3_pmu>;
-+ pmuio2-supply = <&vcc3v3_pmu>;
-+ vccio1-supply = <&vccio_acodec>;
-+ vccio3-supply = <&vccio_sd>;
-+ vccio4-supply = <&vcc_1v8>;
-+ vccio5-supply = <&vcc_3v3>;
-+ vccio6-supply = <&vcc_1v8>;
-+ vccio7-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ max-frequency = <200000000>;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
-+ status = "okay";
-+};
-+
-+&sdmmc0 {
-+ max-frequency = <150000000>;
-+ no-sdio;
-+ no-mmc;
-+ bus-width = <4>;
-+ cap-mmc-highspeed;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ vmmc-supply = <&vcc3v3_sd>;
-+ vqmmc-supply = <&vccio_sd>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <1>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ extcon = <&usb2phy0>;
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+ status = "okay";
-+};
-+
-+&usb2phy0 {
-+ status = "okay";
-+};
-+
-+&usb2phy0_host {
-+ phy-supply = <&vcc5v0_usb_host>;
-+ status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+ status = "okay";
-+};
-+
-+&usb2phy1 {
-+ status = "okay";
-+};
-+
-+&usb2phy1_host {
-+ phy-supply = <&vcc5v0_usb_otg>;
-+ status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+ status = "okay";
-+};
-+
-+&vop {
-+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+ status = "okay";
-+};
-+
-+&vop_mmu {
-+ status = "okay";
-+};
-+
-+&vp0 {
-+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+ remote-endpoint = <&hdmi_in_vp0>;
-+ };
-+};
+++ /dev/null
-From c8ec73b05a95d9f0969ae0f28dd8799a54fcdfc7 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:41 +0800
-Subject: [PATCH] arm64: dts: rockchip: create common dtsi for NanoPi R5 series
-
-Create common dtsi for the FriendlyElec NanoPi R5 series.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-2-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 575 +----------------
- .../boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 596 ++++++++++++++++++
- 2 files changed, 597 insertions(+), 574 deletions(-)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -7,12 +7,7 @@
- */
-
- /dts-v1/;
--#include <dt-bindings/gpio/gpio.h>
--#include <dt-bindings/input/input.h>
--#include <dt-bindings/leds/common.h>
--#include <dt-bindings/pinctrl/rockchip.h>
--#include <dt-bindings/soc/rockchip,vop2.h>
--#include "rk3568.dtsi"
-+#include "rk3568-nanopi-r5s.dtsi"
-
- / {
- model = "FriendlyElec NanoPi R5S";
-@@ -20,23 +15,6 @@
-
- aliases {
- ethernet0 = &gmac0;
-- mmc0 = &sdmmc0;
-- mmc1 = &sdhci;
-- };
--
-- chosen: chosen {
-- stdout-path = "serial2:1500000n8";
-- };
--
-- hdmi-con {
-- compatible = "hdmi-connector";
-- type = "a";
--
-- port {
-- hdmi_con_in: endpoint {
-- remote-endpoint = <&hdmi_out_con>;
-- };
-- };
- };
-
- gpio-leds {
-@@ -71,130 +49,6 @@
- gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
- };
- };
--
-- vdd_usbc: vdd-usbc-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vdd_usbc";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- };
--
-- vcc3v3_sys: vcc3v3-sys-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc3v3_sys";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- vin-supply = <&vdd_usbc>;
-- };
--
-- vcc5v0_sys: vcc5v0-sys-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc5v0_sys";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vdd_usbc>;
-- };
--
-- vcc3v3_pcie: vcc3v3-pcie-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc3v3_pcie";
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- enable-active-high;
-- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-- startup-delay-us = <200000>;
-- vin-supply = <&vcc5v0_sys>;
-- };
--
-- vcc5v0_usb: vcc5v0-usb-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc5v0_usb";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vdd_usbc>;
-- };
--
-- vcc5v0_usb_host: vcc5v0-usb-host-regulator {
-- compatible = "regulator-fixed";
-- enable-active-high;
-- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&vcc5v0_usb_host_en>;
-- regulator-name = "vcc5v0_usb_host";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vcc5v0_usb>;
-- };
--
-- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
-- compatible = "regulator-fixed";
-- enable-active-high;
-- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&vcc5v0_usb_otg_en>;
-- regulator-name = "vcc5v0_usb_otg";
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vcc5v0_usb>;
-- };
--
-- pcie30_avdd0v9: pcie30-avdd0v9-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "pcie30_avdd0v9";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <900000>;
-- regulator-max-microvolt = <900000>;
-- vin-supply = <&vcc3v3_sys>;
-- };
--
-- pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "pcie30_avdd1v8";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-- vin-supply = <&vcc3v3_sys>;
-- };
--};
--
--&combphy0 {
-- status = "okay";
--};
--
--&combphy1 {
-- status = "okay";
--};
--
--&combphy2 {
-- status = "okay";
--};
--
--&cpu0 {
-- cpu-supply = <&vdd_cpu>;
--};
--
--&cpu1 {
-- cpu-supply = <&vdd_cpu>;
--};
--
--&cpu2 {
-- cpu-supply = <&vdd_cpu>;
--};
--
--&cpu3 {
-- cpu-supply = <&vdd_cpu>;
- };
-
- &gmac0 {
-@@ -219,292 +73,6 @@
- status = "okay";
- };
-
--&gpu {
-- mali-supply = <&vdd_gpu>;
-- status = "okay";
--};
--
--&hdmi {
-- avdd-0v9-supply = <&vdda0v9_image>;
-- avdd-1v8-supply = <&vcca1v8_image>;
-- status = "okay";
--};
--
--&hdmi_in {
-- hdmi_in_vp0: endpoint {
-- remote-endpoint = <&vp0_out_hdmi>;
-- };
--};
--
--&hdmi_out {
-- hdmi_out_con: endpoint {
-- remote-endpoint = <&hdmi_con_in>;
-- };
--};
--
--&hdmi_sound {
-- status = "okay";
--};
--
--&i2c0 {
-- status = "okay";
--
-- vdd_cpu: regulator@1c {
-- compatible = "tcs,tcs4525";
-- reg = <0x1c>;
-- fcs,suspend-voltage-selector = <1>;
-- regulator-name = "vdd_cpu";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <800000>;
-- regulator-max-microvolt = <1150000>;
-- regulator-ramp-delay = <2300>;
-- vin-supply = <&vcc5v0_sys>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- rk809: pmic@20 {
-- compatible = "rockchip,rk809";
-- reg = <0x20>;
-- interrupt-parent = <&gpio0>;
-- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-- #clock-cells = <1>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pmic_int>;
-- rockchip,system-power-controller;
-- vcc1-supply = <&vcc3v3_sys>;
-- vcc2-supply = <&vcc3v3_sys>;
-- vcc3-supply = <&vcc3v3_sys>;
-- vcc4-supply = <&vcc3v3_sys>;
-- vcc5-supply = <&vcc3v3_sys>;
-- vcc6-supply = <&vcc3v3_sys>;
-- vcc7-supply = <&vcc3v3_sys>;
-- vcc8-supply = <&vcc3v3_sys>;
-- vcc9-supply = <&vcc3v3_sys>;
-- wakeup-source;
--
-- regulators {
-- vdd_logic: DCDC_REG1 {
-- regulator-name = "vdd_logic";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-init-microvolt = <900000>;
-- regulator-initial-mode = <0x2>;
-- regulator-min-microvolt = <500000>;
-- regulator-max-microvolt = <1350000>;
-- regulator-ramp-delay = <6001>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdd_gpu: DCDC_REG2 {
-- regulator-name = "vdd_gpu";
-- regulator-always-on;
-- regulator-init-microvolt = <900000>;
-- regulator-initial-mode = <0x2>;
-- regulator-min-microvolt = <500000>;
-- regulator-max-microvolt = <1350000>;
-- regulator-ramp-delay = <6001>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc_ddr: DCDC_REG3 {
-- regulator-name = "vcc_ddr";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-initial-mode = <0x2>;
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- };
-- };
--
-- vdd_npu: DCDC_REG4 {
-- regulator-name = "vdd_npu";
-- regulator-init-microvolt = <900000>;
-- regulator-initial-mode = <0x2>;
-- regulator-min-microvolt = <500000>;
-- regulator-max-microvolt = <1350000>;
-- regulator-ramp-delay = <6001>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc_1v8: DCDC_REG5 {
-- regulator-name = "vcc_1v8";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdda0v9_image: LDO_REG1 {
-- regulator-name = "vdda0v9_image";
-- regulator-min-microvolt = <950000>;
-- regulator-max-microvolt = <950000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdda_0v9: LDO_REG2 {
-- regulator-name = "vdda_0v9";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <900000>;
-- regulator-max-microvolt = <900000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdda0v9_pmu: LDO_REG3 {
-- regulator-name = "vdda0v9_pmu";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <900000>;
-- regulator-max-microvolt = <900000>;
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <900000>;
-- };
-- };
--
-- vccio_acodec: LDO_REG4 {
-- regulator-name = "vccio_acodec";
-- regulator-always-on;
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vccio_sd: LDO_REG5 {
-- regulator-name = "vccio_sd";
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <3300000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc3v3_pmu: LDO_REG6 {
-- regulator-name = "vcc3v3_pmu";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <3300000>;
-- };
-- };
--
-- vcca_1v8: LDO_REG7 {
-- regulator-name = "vcca_1v8";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcca1v8_pmu: LDO_REG8 {
-- regulator-name = "vcca1v8_pmu";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <1800000>;
-- };
-- };
--
-- vcca1v8_image: LDO_REG9 {
-- regulator-name = "vcca1v8_image";
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc_3v3: SWITCH_REG1 {
-- regulator-name = "vcc_3v3";
-- regulator-always-on;
-- regulator-boot-on;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc3v3_sd: SWITCH_REG2 {
-- regulator-name = "vcc3v3_sd";
-- regulator-always-on;
-- regulator-boot-on;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
-- };
--
-- };
--};
--
--&i2c5 {
-- status = "okay";
--
-- hym8563: rtc@51 {
-- compatible = "haoyu,hym8563";
-- reg = <0x51>;
-- interrupt-parent = <&gpio0>;
-- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-- #clock-cells = <0>;
-- clock-output-names = "rtcic_32kout";
-- pinctrl-names = "default";
-- pinctrl-0 = <&hym8563_int>;
-- wakeup-source;
-- };
--};
--
--&i2s0_8ch {
-- status = "okay";
--};
--
--&i2s1_8ch {
-- rockchip,trcm-sync-tx-only;
-- status = "okay";
--};
--
- &mdio0 {
- rgmii_phy0: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
-@@ -568,146 +136,5 @@
- rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
--
-- hym8563 {
-- hym8563_int: hym8563-int {
-- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-- };
-- };
--
-- pmic {
-- pmic_int: pmic-int {
-- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-- };
-- };
--
-- usb {
-- vcc5v0_usb_host_en: vcc5v0-usb-host-en {
-- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
--
-- vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
-- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
-- };
--};
--
--&pmu_io_domains {
-- pmuio1-supply = <&vcc3v3_pmu>;
-- pmuio2-supply = <&vcc3v3_pmu>;
-- vccio1-supply = <&vccio_acodec>;
-- vccio3-supply = <&vccio_sd>;
-- vccio4-supply = <&vcc_1v8>;
-- vccio5-supply = <&vcc_3v3>;
-- vccio6-supply = <&vcc_1v8>;
-- vccio7-supply = <&vcc_3v3>;
-- status = "okay";
--};
--
--&saradc {
-- vref-supply = <&vcca_1v8>;
-- status = "okay";
--};
--
--&sdhci {
-- bus-width = <8>;
-- max-frequency = <200000000>;
-- non-removable;
-- pinctrl-names = "default";
-- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
-- status = "okay";
--};
--
--&sdmmc0 {
-- max-frequency = <150000000>;
-- no-sdio;
-- no-mmc;
-- bus-width = <4>;
-- cap-mmc-highspeed;
-- cap-sd-highspeed;
-- disable-wp;
-- vmmc-supply = <&vcc3v3_sd>;
-- vqmmc-supply = <&vccio_sd>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-- status = "okay";
--};
--
--&tsadc {
-- rockchip,hw-tshut-mode = <1>;
-- rockchip,hw-tshut-polarity = <0>;
-- status = "okay";
--};
--
--&uart2 {
-- status = "okay";
--};
--
--&usb_host0_ehci {
-- status = "okay";
--};
--
--&usb_host0_ohci {
-- status = "okay";
--};
--
--&usb_host0_xhci {
-- extcon = <&usb2phy0>;
-- dr_mode = "host";
-- status = "okay";
--};
--
--&usb_host1_ehci {
-- status = "okay";
--};
--
--&usb_host1_ohci {
-- status = "okay";
- };
-
--&usb_host1_xhci {
-- status = "okay";
--};
--
--&usb2phy0 {
-- status = "okay";
--};
--
--&usb2phy0_host {
-- phy-supply = <&vcc5v0_usb_host>;
-- status = "okay";
--};
--
--&usb2phy0_otg {
-- status = "okay";
--};
--
--&usb2phy1 {
-- status = "okay";
--};
--
--&usb2phy1_host {
-- phy-supply = <&vcc5v0_usb_otg>;
-- status = "okay";
--};
--
--&usb2phy1_otg {
-- status = "okay";
--};
--
--&vop {
-- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-- status = "okay";
--};
--
--&vop_mmu {
-- status = "okay";
--};
--
--&vp0 {
-- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-- remote-endpoint = <&hdmi_in_vp0>;
-- };
--};
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-@@ -0,0 +1,596 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyelec.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+ aliases {
-+ mmc0 = &sdmmc0;
-+ mmc1 = &sdhci;
-+ };
-+
-+ chosen: chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ hdmi-con {
-+ compatible = "hdmi-connector";
-+ type = "a";
-+
-+ port {
-+ hdmi_con_in: endpoint {
-+ remote-endpoint = <&hdmi_out_con>;
-+ };
-+ };
-+ };
-+
-+ vdd_usbc: vdd-usbc-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vdd_usbc";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vcc3v3_sys: vcc3v3-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc5v0_sys: vcc5v0-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc3v3_pcie: vcc3v3-pcie-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_pcie";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ enable-active-high;
-+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-+ startup-delay-us = <200000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc5v0_usb: vcc5v0-usb-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_usb";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb_host_en>;
-+ regulator-name = "vcc5v0_usb_host";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_usb>;
-+ };
-+
-+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
-+ regulator-name = "vcc5v0_usb_otg";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_usb>;
-+ };
-+
-+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+};
-+
-+&combphy0 {
-+ status = "okay";
-+};
-+
-+&combphy1 {
-+ status = "okay";
-+};
-+
-+&combphy2 {
-+ status = "okay";
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu>;
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ avdd-0v9-supply = <&vdda0v9_image>;
-+ avdd-1v8-supply = <&vcca1v8_image>;
-+ status = "okay";
-+};
-+
-+&hdmi_in {
-+ hdmi_in_vp0: endpoint {
-+ remote-endpoint = <&vp0_out_hdmi>;
-+ };
-+};
-+
-+&hdmi_out {
-+ hdmi_out_con: endpoint {
-+ remote-endpoint = <&hdmi_con_in>;
-+ };
-+};
-+
-+&hdmi_sound {
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ vdd_cpu: regulator@1c {
-+ compatible = "tcs,tcs4525";
-+ reg = <0x1c>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1150000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ rk809: pmic@20 {
-+ compatible = "rockchip,rk809";
-+ reg = <0x20>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int>;
-+ rockchip,system-power-controller;
-+ vcc1-supply = <&vcc3v3_sys>;
-+ vcc2-supply = <&vcc3v3_sys>;
-+ vcc3-supply = <&vcc3v3_sys>;
-+ vcc4-supply = <&vcc3v3_sys>;
-+ vcc5-supply = <&vcc3v3_sys>;
-+ vcc6-supply = <&vcc3v3_sys>;
-+ vcc7-supply = <&vcc3v3_sys>;
-+ vcc8-supply = <&vcc3v3_sys>;
-+ vcc9-supply = <&vcc3v3_sys>;
-+ wakeup-source;
-+
-+ regulators {
-+ vdd_logic: DCDC_REG1 {
-+ regulator-name = "vdd_logic";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_gpu: DCDC_REG2 {
-+ regulator-name = "vdd_gpu";
-+ regulator-always-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vdd_npu: DCDC_REG4 {
-+ regulator-name = "vdd_npu";
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8: DCDC_REG5 {
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_image: LDO_REG1 {
-+ regulator-name = "vdda0v9_image";
-+ regulator-min-microvolt = <950000>;
-+ regulator-max-microvolt = <950000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda_0v9: LDO_REG2 {
-+ regulator-name = "vdda_0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_pmu: LDO_REG3 {
-+ regulator-name = "vdda0v9_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vccio_acodec: LDO_REG4 {
-+ regulator-name = "vccio_acodec";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd: LDO_REG5 {
-+ regulator-name = "vccio_sd";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_pmu: LDO_REG6 {
-+ regulator-name = "vcc3v3_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcca_1v8: LDO_REG7 {
-+ regulator-name = "vcca_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca1v8_pmu: LDO_REG8 {
-+ regulator-name = "vcca1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcca1v8_image: LDO_REG9 {
-+ regulator-name = "vcca1v8_image";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_3v3: SWITCH_REG1 {
-+ regulator-name = "vcc_3v3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_sd: SWITCH_REG2 {
-+ regulator-name = "vcc3v3_sd";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+
-+ };
-+};
-+
-+&i2c5 {
-+ status = "okay";
-+
-+ hym8563: rtc@51 {
-+ compatible = "haoyu,hym8563";
-+ reg = <0x51>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <0>;
-+ clock-output-names = "rtcic_32kout";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hym8563_int>;
-+ wakeup-source;
-+ };
-+};
-+
-+&i2s0_8ch {
-+ status = "okay";
-+};
-+
-+&i2s1_8ch {
-+ rockchip,trcm-sync-tx-only;
-+ status = "okay";
-+};
-+
-+&pcie30phy {
-+ data-lanes = <1 2>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ hym8563 {
-+ hym8563_int: hym8563-int {
-+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int: pmic-int {
-+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ usb {
-+ vcc5v0_usb_host_en: vcc5v0-usb-host-en {
-+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
-+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pmu_io_domains {
-+ pmuio1-supply = <&vcc3v3_pmu>;
-+ pmuio2-supply = <&vcc3v3_pmu>;
-+ vccio1-supply = <&vccio_acodec>;
-+ vccio3-supply = <&vccio_sd>;
-+ vccio4-supply = <&vcc_1v8>;
-+ vccio5-supply = <&vcc_3v3>;
-+ vccio6-supply = <&vcc_1v8>;
-+ vccio7-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ max-frequency = <200000000>;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
-+ status = "okay";
-+};
-+
-+&sdmmc0 {
-+ max-frequency = <150000000>;
-+ no-sdio;
-+ no-mmc;
-+ bus-width = <4>;
-+ cap-mmc-highspeed;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ vmmc-supply = <&vcc3v3_sd>;
-+ vqmmc-supply = <&vccio_sd>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <1>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ extcon = <&usb2phy0>;
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+ status = "okay";
-+};
-+
-+&usb2phy0 {
-+ status = "okay";
-+};
-+
-+&usb2phy0_host {
-+ phy-supply = <&vcc5v0_usb_host>;
-+ status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+ status = "okay";
-+};
-+
-+&usb2phy1 {
-+ status = "okay";
-+};
-+
-+&usb2phy1_host {
-+ phy-supply = <&vcc5v0_usb_otg>;
-+ status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+ status = "okay";
-+};
-+
-+&vop {
-+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+ status = "okay";
-+};
-+
-+&vop_mmu {
-+ status = "okay";
-+};
-+
-+&vp0 {
-+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+ remote-endpoint = <&hdmi_in_vp0>;
-+ };
-+};
+++ /dev/null
-From 31425b1fadb2040b359e52ffc24c049a78d56c96 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:44 +0800
-Subject: [PATCH] arm64: dts: rockchip: fix gmac support for NanoPi R5S
-
-- Changed phy-mode to rgmii.
-
-- Fixed pull type in pinctrl for gmac0.
-
-- Removed duplicate properties in mdio node.
- These properties are defined in the gmac0 node already.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-5-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -57,7 +57,7 @@
- assigned-clock-rates = <0>, <125000000>;
- clock_in_out = "output";
- phy-handle = <&rgmii_phy0>;
-- phy-mode = "rgmii-id";
-+ phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac0_miim
- &gmac0_tx_bus2
-@@ -79,9 +79,6 @@
- reg = <1>;
- pinctrl-0 = <ð_phy0_reset_pin>;
- pinctrl-names = "default";
-- reset-assert-us = <10000>;
-- reset-deassert-us = <50000>;
-- reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
- };
- };
-
-@@ -115,7 +112,7 @@
- &pinctrl {
- gmac0 {
- eth_phy0_reset_pin: eth-phy0-reset-pin {
-- rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
-+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
+++ /dev/null
-From 975e9bbad11950fc8276f1fa260d8bf2c341aa41 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:45 +0800
-Subject: [PATCH] arm64: dts: rockchip: remove I2S1 TDM node for the NanoPi R5
- series
-
-This is for the audio output which does not exist on the boards.
-Also disable regulator-always-on for vccio_acodec since it's only
-used by the audio output.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-6-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 6 ------
- 1 file changed, 6 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-@@ -330,7 +330,6 @@
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
-- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
-@@ -441,11 +440,6 @@
- status = "okay";
- };
-
--&i2s1_8ch {
-- rockchip,trcm-sync-tx-only;
-- status = "okay";
--};
--
- &pcie30phy {
- data-lanes = <1 2>;
- status = "okay";
+++ /dev/null
-From 05620031408ac6cfc6d5c048431827e49aa0ade1 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:43 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R5C
-
-FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device.
-
-Specification:
-- Rockchip RK3568
-- 1/4GB LPDDR4X RAM
-- 8/32GB eMMC
-- SD card slot
-- M.2 Connector
-- 2x USB 3.0 Port
-- 2x 2500 Base-T (PCIe, r8125)
-- HDMI 2.0
-- MIPI DSI/CSI
-- USB Type C 5V
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-4-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 112 ++++++++++++++++++
- 2 files changed, 113 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -74,5 +74,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-@@ -0,0 +1,112 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyelec.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3568-nanopi-r5s.dtsi"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R5C";
-+ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
-+
-+ gpio-keys {
-+ compatible = "gpio-keys";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&reset_button_pin>;
-+
-+ button-reset {
-+ debounce-interval = <50>;
-+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
-+ label = "reset";
-+ linux,code = <KEY_RESTART>;
-+ };
-+ };
-+
-+ gpio-leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
-+
-+ led-lan {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_LAN;
-+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ power_led: led-power {
-+ color = <LED_COLOR_ID_RED>;
-+ function = LED_FUNCTION_POWER;
-+ linux,default-trigger = "heartbeat";
-+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ led-wan {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_WAN;
-+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ led-wlan {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_WLAN;
-+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+};
-+
-+&pcie2x1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie20_reset_pin>;
-+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+};
-+
-+&pcie3x1 {
-+ num-lanes = <1>;
-+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie>;
-+ status = "okay";
-+};
-+
-+&pcie3x2 {
-+ num-lanes = <1>;
-+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ gpio-leds {
-+ lan_led_pin: lan-led-pin {
-+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ power_led_pin: power-led-pin {
-+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wan_led_pin: wan-led-pin {
-+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wlan_led_pin: wlan-led-pin {
-+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie {
-+ pcie20_reset_pin: pcie20-reset-pin {
-+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ rockchip-key {
-+ reset_button_pin: reset-button-pin {
-+ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+};
+++ /dev/null
-From 5325593377f07de31f7e473a9677a28a04c891f3 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Thu, 11 May 2023 00:18:50 +0800
-Subject: [PATCH] arm64: dts: rockchip: fix button reset pin for nanopi r5c
-
-The reset pin was wrongly assigned due to a copy/paste error,
-fix it to match actual gpio pin.
-
-While at it, remove a blank line from nanopi r5s dts.
-
-Fixes: 05620031408a ("arm64: dts: rockchip: Add FriendlyARM NanoPi R5C")
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230510161850.4866-1-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts | 2 +-
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 1 -
- 2 files changed, 1 insertion(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-@@ -106,7 +106,7 @@
-
- rockchip-key {
- reset_button_pin: reset-button-pin {
-- rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
-+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
- };
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -134,4 +134,3 @@
- };
- };
- };
--
+++ /dev/null
-From fc5a80a432607d05e85bba37971712405f75c546 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 16 Dec 2023 12:07:23 +0800
-Subject: [PATCH] arm64: dts: rockchip: configure eth pad driver strength
- for orangepi r1 plus lts
-
-The default strength is not enough to provide stable connection
-under 3.3v LDO voltage.
-
-Fixes: 387b3bbac5ea ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS")
-Cc: stable@vger.kernel.org # 6.6+
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20231216040723.17864-1-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-@@ -26,9 +26,11 @@
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
-
-+ motorcomm,auto-sleep-disabled;
- motorcomm,clk-out-frequency-hz = <125000000>;
- motorcomm,keep-pll-enabled;
-- motorcomm,auto-sleep-disabled;
-+ motorcomm,rx-clk-drv-microamp = <5020>;
-+ motorcomm,rx-data-drv-microamp = <5020>;
-
- pinctrl-0 = <ð_phy_reset_pin>;
- pinctrl-names = "default";
+++ /dev/null
-From 096ebfb74b19f2d4bdcbc33ae02e857ff4b3e0a0 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Thu, 12 Jan 2023 16:29:02 +0530
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa Compute Module 3 IO board
-
-Radxa Compute Module 3(CM3) IO board is an application board from Radxa
-and is compatible with Raspberry Pi CM4 IO form factor.
-
-Specification:
-- 1x HDMI,
-- 2x MIPI DSI
-- 2x MIPI CSI2
-- 1x eDP
-- 1x PCIe card
-- 2x SATA
-- 2x USB 2.0 Host
-- 1x USB 3.0
-- 1x USB 2.0 OTG
-- Phone jack
-- microSD slot
-- 40-pin GPIO expansion header
-- 12V DC
-
-Radxa CM3 needs to mount on top of this IO board in order to create
-complete Radxa CM3 IO board platform.
-
-Add support for Radxa CM3 IO Board.
-
-Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
-Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230112105902.192852-3-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 179 ++++++++++++++++++
- 2 files changed, 180 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -0,0 +1,179 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2022 Radxa Limited
-+ * Copyright (c) 2022 Amarula Solutions(India)
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3566.dtsi"
-+#include "rk3566-radxa-cm3.dtsi"
-+
-+/ {
-+ model = "Radxa Compute Module 3(CM3) IO Board";
-+ compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
-+
-+ aliases {
-+ mmc1 = &sdmmc0;
-+ };
-+
-+ chosen: chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ hdmi-con {
-+ compatible = "hdmi-connector";
-+ type = "a";
-+
-+ port {
-+ hdmi_con_in: endpoint {
-+ remote-endpoint = <&hdmi_out_con>;
-+ };
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ led-1 {
-+ gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>;
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_ACTIVITY;
-+ linux,default-trigger = "heartbeat";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pi_nled_activity>;
-+ };
-+ };
-+
-+ vcc5v0_usb30: vcc5v0-usb30-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_usb30";
-+ enable-active-high;
-+ gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb30_en_h>;
-+ regulator-always-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc_sys>;
-+ };
-+
-+ vcca1v8_image: vcca1v8-image-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcca1v8_image";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc_1v8_p>;
-+ };
-+
-+ vdda0v9_image: vdda0v9-image-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcca0v9_image";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ vin-supply = <&vdda_0v9>;
-+ };
-+};
-+
-+&combphy1 {
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ avdd-0v9-supply = <&vdda0v9_image>;
-+ avdd-1v8-supply = <&vcca1v8_image>;
-+ status = "okay";
-+};
-+
-+&hdmi_in {
-+ hdmi_in_vp0: endpoint {
-+ remote-endpoint = <&vp0_out_hdmi>;
-+ };
-+};
-+
-+&hdmi_out {
-+ hdmi_out_con: endpoint {
-+ remote-endpoint = <&hdmi_con_in>;
-+ };
-+};
-+
-+&hdmi_sound {
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ leds {
-+ pi_nled_activity: pi-nled-activity {
-+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ sdcard {
-+ sdmmc_pwren: sdmmc-pwren {
-+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ usb {
-+ vcc5v0_usb30_en_h: vcc5v0-host-en-h {
-+ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&sdmmc0 {
-+ bus-width = <4>;
-+ cap-mmc-highspeed;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ vqmmc-supply = <&vccio_sd>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb2phy0_host {
-+ phy-supply = <&vcc5v0_usb30>;
-+ status = "okay";
-+};
-+
-+&usb2phy1_host {
-+ status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+ status = "okay";
-+};
-+
-+&vop {
-+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+ status = "okay";
-+};
-+
-+&vop_mmu {
-+ status = "okay";
-+};
-+
-+&vp0 {
-+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+ remote-endpoint = <&hdmi_in_vp0>;
-+ };
-+};
+++ /dev/null
-From d211665c5a833873ee37e501af58adbf028e6b5f Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 13 May 2023 21:53:07 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C Plus
-
-The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
-eMMC flash (8G) included.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230513135307.26554-2-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts | 33 ++++++++++++++++++++++
- 2 files changed, 34 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
-@@ -0,0 +1,33 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3328-nanopi-r2c.dts"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R2C Plus";
-+ compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
-+
-+ aliases {
-+ mmc1 = &emmc;
-+ };
-+};
-+
-+&emmc {
-+ bus-width = <8>;
-+ cap-mmc-highspeed;
-+ max-frequency = <150000000>;
-+ mmc-ddr-1_8v;
-+ mmc-hs200-1_8v;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-+ vmmc-supply = <&vcc_io_33>;
-+ vqmmc-supply = <&vcc18_emmc>;
-+ status = "okay";
-+};
+++ /dev/null
-From cc52bfc04726a574fc4440bbbe0c710890e7040a Mon Sep 17 00:00:00 2001
-From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Date: Wed, 25 Jan 2023 21:40:22 +0530
-Subject: [PATCH] arm64: dts: rockchip: Enable Ethernet for Radxa CM3 IO
-
-Add ethernet nodes for enabling gmac1 on the Radxa CM3 IO board.
-
-Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230125161023.12115-1-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 93 +++++++++++++++++++
- 1 file changed, 93 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -21,6 +21,13 @@
- stdout-path = "serial2:1500000n8";
- };
-
-+ gmac1_clkin: external-gmac1-clock {
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ clock-output-names = "gmac1_clkin";
-+ #clock-cells = <0>;
-+ };
-+
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-@@ -83,6 +90,29 @@
- status = "okay";
- };
-
-+&gmac1 {
-+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
-+ assigned-clock-rates = <0>, <125000000>;
-+ clock_in_out = "input";
-+ phy-handle = <&rgmii_phy1>;
-+ phy-mode = "rgmii";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac1m0_miim
-+ &gmac1m0_tx_bus2
-+ &gmac1m0_rx_bus2
-+ &gmac1m0_rgmii_clk
-+ &gmac1m0_rgmii_bus
-+ &gmac1m0_clkinout>;
-+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
-+ snps,reset-active-low;
-+ /* Reset time is 20ms, 100ms for rtl8211f */
-+ snps,reset-delays-us = <0 20000 100000>;
-+ tx_delay = <0x46>;
-+ rx_delay = <0x2e>;
-+ status = "okay";
-+};
-+
- &hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
-@@ -105,7 +135,70 @@
- status = "okay";
- };
-
-+&mdio1 {
-+ rgmii_phy1: ethernet-phy@0 {
-+ compatible="ethernet-phy-ieee802.3-c22";
-+ reg= <0x0>;
-+ };
-+};
-+
- &pinctrl {
-+ gmac1 {
-+ gmac1m0_miim: gmac1m0-miim {
-+ rockchip,pins =
-+ /* gmac1_mdcm0 */
-+ <3 RK_PC4 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_mdiom0 */
-+ <3 RK_PC5 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+
-+ gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
-+ rockchip,pins =
-+ /* gmac1_rxd0m0 */
-+ <3 RK_PB1 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_rxd1m0 */
-+ <3 RK_PB2 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_rxdvcrsm0 */
-+ <3 RK_PB3 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+
-+ gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
-+ rockchip,pins =
-+ /* gmac1_txd0m0 */
-+ <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_txd1m0 */
-+ <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_txenm0 */
-+ <3 RK_PB7 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+
-+ gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
-+ rockchip,pins =
-+ /* gmac1_rxclkm0 */
-+ <3 RK_PA7 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_txclkm0 */
-+ <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+
-+ gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
-+ rockchip,pins =
-+ /* gmac1_rxd2m0 */
-+ <3 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_rxd3m0 */
-+ <3 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_txd2m0 */
-+ <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_txd3m0 */
-+ <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+
-+ gmac1m0_clkinout: gmac1m0-clkinout {
-+ rockchip,pins =
-+ /* gmac1_mclkinoutm0 */
-+ <3 RK_PC0 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+ };
-+
- leds {
- pi_nled_activity: pi-nled-activity {
- rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+++ /dev/null
-From 7469ab529bcad50490f6ff651c3e4f03bfa88fe0 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Thu, 12 Jan 2023 16:29:01 +0530
-Subject: [PATCH] arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Radxa Compute Module 3(CM3) is one of the modules from a series
-System On Module based on the Radxa ROCK 3 series and is compatible
-with Raspberry Pi CM4 pinout and form factor.
-
-Specification:
-- Rockchip RK3566
-- up to 8GB LPDDR4
-- up to 128GB high performance eMMC
-- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless,
- BT 5.0, BLE with onboard and external antenna.
-- Gigabit Ethernet PHY
-
-Radxa CM3 needs to mount on top of this IO board in order to create
-complete Radxa CM3 IO board platform.
-
-Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is
-possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board.
-
-Add support for Radxa CM3.
-
-Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230112105902.192852-2-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 345 ++++++++++++++++++
- 1 file changed, 345 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-@@ -0,0 +1,345 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2022 Radxa Limited
-+ * Copyright (c) 2022 Amarula Solutions(India)
-+ */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+
-+/ {
-+ compatible = "radxa,radxa-cm3", "rockchip,rk3566";
-+
-+ aliases {
-+ mmc0 = &sdhci;
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ led-0 {
-+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_STATUS;
-+ linux,default-trigger = "timer";
-+ default-state = "on";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&user_led2>;
-+ };
-+ };
-+
-+ vcc_sys: vcc-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vcc_1v8: vcc-1v8-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc_1v8_p>;
-+ };
-+
-+ vcc_3v3: vcc-3v3-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_3v3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ vcca_1v8: vcca-1v8-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcca_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc_1v8_p>;
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu_npu>;
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ vdd_cpu: regulator@1c {
-+ compatible = "tcs,tcs4525";
-+ reg = <0x1c>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1390000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ rk817: pmic@20 {
-+ compatible = "rockchip,rk817";
-+ reg = <0x20>;
-+ #clock-cells = <1>;
-+ clock-output-names = "rk817-clkout1", "rk817-clkout2";
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int_l>;
-+ rockchip,system-power-controller;
-+ wakeup-source;
-+
-+ vcc1-supply = <&vcc_sys>;
-+ vcc2-supply = <&vcc_sys>;
-+ vcc3-supply = <&vcc_sys>;
-+ vcc4-supply = <&vcc_sys>;
-+ vcc5-supply = <&vcc_sys>;
-+ vcc6-supply = <&vcc_sys>;
-+ vcc7-supply = <&vcc_sys>;
-+
-+ regulators {
-+ vdd_logic: DCDC_REG1 {
-+ regulator-name = "vdd_logic";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vdd_gpu_npu: DCDC_REG2 {
-+ regulator-name = "vdd_gpu_npu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_sys: DCDC_REG4 {
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcca1v8_pmu: LDO_REG1 {
-+ regulator-name = "vcca1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vdda_0v9: LDO_REG2 {
-+ regulator-name = "vdda_0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_pmu: LDO_REG3 {
-+ regulator-name = "vdda0v9_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vccio_acodec: LDO_REG4 {
-+ regulator-name = "vccio_acodec";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd: LDO_REG5 {
-+ regulator-name = "vccio_sd";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_pmu: LDO_REG6 {
-+ regulator-name = "vcc3v3_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcc_1v8_p: LDO_REG7 {
-+ regulator-name = "vcc_1v8_p";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc1v8_dvp: LDO_REG8 {
-+ regulator-name = "vcc1v8_dvp";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc2v8_dvp: LDO_REG9 {
-+ regulator-name = "vcc2v8_dvp";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <2800000>;
-+ regulator-max-microvolt = <2800000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ };
-+ };
-+};
-+
-+&pinctrl {
-+ pmic {
-+ pmic_int_l: pmic-int-l {
-+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ leds {
-+ user_led2: user-led2 {
-+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pmu_io_domains {
-+ pmuio1-supply = <&vcc3v3_pmu>;
-+ pmuio2-supply = <&vcc_3v3>;
-+ vccio1-supply = <&vccio_acodec>;
-+ vccio2-supply = <&vcc_1v8>;
-+ vccio3-supply = <&vccio_sd>;
-+ vccio4-supply = <&vcc_1v8>;
-+ vccio5-supply = <&vcc_3v3>;
-+ vccio6-supply = <&vcc_3v3>;
-+ vccio7-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ max-frequency = <200000000>;
-+ mmc-hs200-1_8v;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-+ vmmc-supply = <&vcc_3v3>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "okay";
-+};
-+
-+&usb2phy0 {
-+ status = "okay";
-+};
-+
-+&usb2phy1 {
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <1>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
+++ /dev/null
-From af5a803bf212e077e5fb7a1d4cf6be02f74a74ca Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Wed, 25 Jan 2023 21:40:23 +0530
-Subject: [PATCH] arm64: dts: rockchip: rk3566: Enable WiFi, BT support for
- Radxa CM3
-
-Radxa Compute Module 3 has an onboard AW_CM256SM WiFi/BT module.
-
-Add nodes for enabling it.
-
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230125161023.12115-2-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 80 +++++++++++++++++++
- 1 file changed, 80 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-@@ -66,6 +66,15 @@
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8_p>;
- };
-+
-+ sdio_pwrseq: pwrseq-sdio {
-+ compatible = "mmc-pwrseq-simple";
-+ clocks = <&rk817 1>;
-+ clock-names = "ext_clock";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_reg_on_h>;
-+ reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
-+ };
- };
-
- &cpu0 {
-@@ -287,6 +296,20 @@
- };
-
- &pinctrl {
-+ bluetooth {
-+ bt_host_wake_h: bt-host-wake-h {
-+ rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ bt_reg_on_h: bt-reg-on-h {
-+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ bt_wake_host_h: bt-wake-host-h {
-+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-@@ -298,6 +321,16 @@
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-+
-+ wifi {
-+ wifi_reg_on_h: wifi-reg-on-h {
-+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wifi_host_wake_h: wifi-host-wake-h {
-+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
- };
-
- &pmu_io_domains {
-@@ -318,6 +351,34 @@
- status = "okay";
- };
-
-+&sdmmc1 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ bus-width = <4>;
-+ disable-wp;
-+ cap-sd-highspeed;
-+ cap-sdio-irq;
-+ keep-power-in-suspend;
-+ mmc-pwrseq = <&sdio_pwrseq>;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc_3v3>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "okay";
-+
-+ wifi@1 {
-+ compatible = "brcm,bcm43455-fmac";
-+ reg = <1>;
-+ interrupt-parent = <&gpio2>;
-+ interrupts = <RK_PC1 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "host-wake";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_host_wake_h>;
-+ };
-+};
-+
- &sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
-@@ -330,6 +391,25 @@
- status = "okay";
- };
-
-+&uart1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
-+ status = "okay";
-+
-+ bluetooth {
-+ compatible = "brcm,bcm4345c5";
-+ clocks = <&rk817 1>;
-+ clock-names = "lpo";
-+ device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
-+ host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
-+ reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>;
-+ vbat-supply = <&vcc_3v3>;
-+ vddio-supply = <&vcc_1v8>;
-+ };
-+};
-+
- &usb2phy0 {
- status = "okay";
- };
+++ /dev/null
-From 477ed3ade6a46e445b4e2348b710c51df4f6f4b1 Mon Sep 17 00:00:00 2001
-From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Date: Thu, 23 Feb 2023 19:29:29 +0530
-Subject: [PATCH] arm64: dts: rockchip: Enable USB OTG for rk3566 Radxa CM3
-
-Enable USB OTG support for Radxa Compute Module 3 IO Board
-
-Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230223135929.630787-1-abbaraju.manojsai@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -254,6 +254,14 @@
- status = "okay";
- };
-
-+&usb2phy0_otg {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ status = "okay";
-+};
-+
- &vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+++ /dev/null
-From 8f19828844f20b22182719cf53be64f8c955aee8 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Mon, 23 Jan 2023 12:46:50 +0530
-Subject: [PATCH] arm64: dts: rockchip: Fix compatible for Radxa CM3
-
-The compatible string "radxa,radxa-cm3" referring the product name
-as "Radxa Radxa CM3" but the actual product name is "Radxa CM3".
-
-Fix the compatible strings.
-
-Fixes: 24a28d3eb07d ("dt-bindings: arm: rockchip: Add Radxa Compute Module 3")
-Fixes: 7469ab529bca ("arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3")
-Fixes: 096ebfb74b19 ("arm64: dts: rockchip: Add Radxa Compute Module 3 IO board")
-Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20230123071654.73139-1-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 2 +-
- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -11,7 +11,7 @@
-
- / {
- model = "Radxa Compute Module 3(CM3) IO Board";
-- compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
-+ compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
-
- aliases {
- mmc1 = &sdmmc0;
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-@@ -8,7 +8,7 @@
- #include <dt-bindings/leds/common.h>
-
- / {
-- compatible = "radxa,radxa-cm3", "rockchip,rk3566";
-+ compatible = "radxa,cm3", "rockchip,rk3566";
-
- aliases {
- mmc0 = &sdhci;
+++ /dev/null
-From f99a75f11f46a24dabb33e90893eebf61dca0566 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Sun, 2 Jul 2023 20:52:42 +0200
-Subject: [PATCH] arm64: dts: rockchip: minor whitespace cleanup around '='
-
-The DTS code coding style expects exactly one space before and after '='
-sign.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20230702185242.44421-1-krzysztof.kozlowski@linaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 4 ++--
- 1 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -137,8 +137,8 @@
-
- &mdio1 {
- rgmii_phy1: ethernet-phy@0 {
-- compatible="ethernet-phy-ieee802.3-c22";
-- reg= <0x0>;
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <0x0>;
- };
- };
-
+++ /dev/null
-From 36d9b3ae708e865cdab95692db5a24c5d975383d Mon Sep 17 00:00:00 2001
-From: Dragan Simic <dsimic@manjaro.org>
-Date: Tue, 12 Dec 2023 09:01:39 +0100
-Subject: [PATCH] arm64: dts: rockchip: Add ethernet0 alias to the dts for
- RK3566 boards
-
-Add ethernet0 alias to the board dts files for a few supported RK3566 boards
-that had it missing. Also, remove the ethernet0 alias from one RK3566 SoM
-dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to
-the dependent board dts files, which actually enable the GMAC.
-
-Signed-off-by: Dragan Simic <dsimic@manjaro.org>
-Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 1 +
- 1 files changed, 1 insertions(+), 0 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -14,6 +14,7 @@
- compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
-
- aliases {
-+ ethernet0 = &gmac1;
- mmc1 = &sdmmc0;
- };
-
+++ /dev/null
-From 2bf2f4d9f673013a58109626b87329310537a611 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Fri, 9 Dec 2022 18:25:24 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa CM3I E25
-
-Radxa E25 is a network application carrier board for the Radxa CM3
-Industrial (CM3I) SoM, which is based on the Rockchip RK3568 SoC.
-
-It has the following features:
-
-- MicroSD card socket, on board eMMC flash
-- 2x 2.5GbE Realtek RTL8125B Ethernet transceiver
-- 1x USB Type-C port (Power and Serial console)
-- 1x USB 3.0 OTG port
-- mini PCIe socket (USB or PCIe)
-- ngff PCIe socket (USB or SATA)
-- 1x User LED and 16x RGB LEDs
-- 26-pin expansion header
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Link: https://lore.kernel.org/r/20221209102524.129367-3-amadeus@jmu.edu.cn
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 416 ++++++++++++++++++
- .../boot/dts/rockchip/rk3568-radxa-e25.dts | 229 ++++++++++
- 3 files changed, 646 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -78,4 +78,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bp
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
-@@ -0,0 +1,416 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+ model = "Radxa CM3 Industrial Board";
-+ compatible = "radxa,cm3i", "rockchip,rk3568";
-+
-+ aliases {
-+ mmc0 = &sdhci;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial2:115200n8";
-+ };
-+
-+ gpio-leds {
-+ compatible = "gpio-leds";
-+
-+ led_user: led-0 {
-+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+ function = LED_FUNCTION_HEARTBEAT;
-+ color = <LED_COLOR_ID_GREEN>;
-+ linux,default-trigger = "heartbeat";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&led_user_en>;
-+ };
-+ };
-+
-+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ vcc3v3_sys: vcc3v3-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v_input>;
-+ };
-+
-+ vcc5v0_sys: vcc5v0-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v_input>;
-+ };
-+
-+ /* labeled +5v_input in schematic */
-+ vcc5v_input: vcc5v-input-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v_input";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+};
-+
-+&combphy0 {
-+ status = "okay";
-+};
-+
-+&combphy1 {
-+ status = "okay";
-+};
-+
-+&combphy2 {
-+ status = "okay";
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&display_subsystem {
-+ status = "disabled";
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu>;
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ vdd_cpu: regulator@1c {
-+ compatible = "tcs,tcs4525";
-+ reg = <0x1c>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1150000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v_input>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ rk809: pmic@20 {
-+ compatible = "rockchip,rk809";
-+ reg = <0x20>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int>;
-+ rockchip,system-power-controller;
-+ wakeup-source;
-+
-+ vcc1-supply = <&vcc3v3_sys>;
-+ vcc2-supply = <&vcc3v3_sys>;
-+ vcc3-supply = <&vcc3v3_sys>;
-+ vcc4-supply = <&vcc3v3_sys>;
-+ vcc5-supply = <&vcc3v3_sys>;
-+ vcc6-supply = <&vcc3v3_sys>;
-+ vcc7-supply = <&vcc3v3_sys>;
-+ vcc8-supply = <&vcc3v3_sys>;
-+ vcc9-supply = <&vcc3v3_sys>;
-+
-+ regulators {
-+ vdd_logic: DCDC_REG1 {
-+ regulator-name = "vdd_logic";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_gpu: DCDC_REG2 {
-+ regulator-name = "vdd_gpu";
-+ regulator-always-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vdd_npu: DCDC_REG4 {
-+ regulator-name = "vdd_npu";
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8: DCDC_REG5 {
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_image: LDO_REG1 {
-+ regulator-name = "vdda0v9_image";
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda_0v9: LDO_REG2 {
-+ regulator-name = "vdda_0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_pmu: LDO_REG3 {
-+ regulator-name = "vdda0v9_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vccio_acodec: LDO_REG4 {
-+ regulator-name = "vccio_acodec";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd: LDO_REG5 {
-+ regulator-name = "vccio_sd";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_pmu: LDO_REG6 {
-+ regulator-name = "vcc3v3_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcca_1v8: LDO_REG7 {
-+ regulator-name = "vcca_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca1v8_pmu: LDO_REG8 {
-+ regulator-name = "vcca1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcca1v8_image: LDO_REG9 {
-+ regulator-name = "vcca1v8_image";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_3v3: SWITCH_REG1 {
-+ regulator-name = "vcc_3v3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_sd: SWITCH_REG2 {
-+ regulator-name = "vcc3v3_sd";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&pinctrl {
-+ leds {
-+ led_user_en: led_user_en {
-+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int: pmic_int {
-+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+};
-+
-+&pmu_io_domains {
-+ pmuio1-supply = <&vcc3v3_pmu>;
-+ pmuio2-supply = <&vcc3v3_pmu>;
-+ vccio1-supply = <&vccio_acodec>;
-+ vccio2-supply = <&vcc_1v8>;
-+ vccio3-supply = <&vccio_sd>;
-+ vccio4-supply = <&vcc_1v8>;
-+ vccio5-supply = <&vcc_3v3>;
-+ vccio6-supply = <&vcc_1v8>;
-+ vccio7-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ max-frequency = <200000000>;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-+ vmmc-supply = <&vcc_3v3>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <1>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb2phy0 {
-+ status = "okay";
-+};
-+
-+&usb2phy1 {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ extcon = <&usb2phy0>;
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -0,0 +1,229 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+#include "rk3568-radxa-cm3i.dtsi"
-+
-+/ {
-+ model = "Radxa E25";
-+ compatible = "radxa,e25", "rockchip,rk3568";
-+
-+ aliases {
-+ mmc0 = &sdmmc0;
-+ mmc1 = &sdhci;
-+ };
-+
-+ pwm-leds {
-+ compatible = "pwm-leds-multicolor";
-+
-+ multi-led {
-+ color = <LED_COLOR_ID_RGB>;
-+ max-brightness = <255>;
-+
-+ led-red {
-+ color = <LED_COLOR_ID_RED>;
-+ pwms = <&pwm1 0 1000000 0>;
-+ };
-+
-+ led-green {
-+ color = <LED_COLOR_ID_GREEN>;
-+ pwms = <&pwm2 0 1000000 0>;
-+ };
-+
-+ led-blue {
-+ color = <LED_COLOR_ID_BLUE>;
-+ pwms = <&pwm12 0 1000000 0>;
-+ };
-+ };
-+ };
-+
-+ vbus_typec: vbus-typec-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vbus_typec_en>;
-+ regulator-name = "vbus_typec";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc3v3_minipcie: vcc3v3-minipcie-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&minipcie_enable_h>;
-+ regulator-name = "vcc3v3_minipcie";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc3v3_ngff: vcc3v3-ngff-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&ngffpcie_enable_h>;
-+ regulator-name = "vcc3v3_ngff";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ /* actually fed by vcc5v0_sys, dependent
-+ * on pi6c clock generator
-+ */
-+ vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie30x1_enable_h>;
-+ regulator-name = "vcc3v3_pcie30x1";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc3v3_pi6c_05>;
-+ };
-+
-+ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_enable_h>;
-+ regulator-name = "vcc3v3_pcie";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+};
-+
-+&pcie2x1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie20_reset_h>;
-+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
-+ status = "okay";
-+};
-+
-+&pcie30phy {
-+ data-lanes = <1 2>;
-+ status = "okay";
-+};
-+
-+&pcie3x1 {
-+ num-lanes = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie30x1m0_pins>;
-+ reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie30x1>;
-+ status = "okay";
-+};
-+
-+&pcie3x2 {
-+ num-lanes = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie30x2_reset_h>;
-+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ pcie {
-+ pcie20_reset_h: pcie20-reset-h {
-+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie30x1_enable_h: pcie30x1-enable-h {
-+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie30x2_reset_h: pcie30x2-reset-h {
-+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie_enable_h: pcie-enable-h {
-+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ usb {
-+ minipcie_enable_h: minipcie-enable-h {
-+ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ ngffpcie_enable_h: ngffpcie-enable-h {
-+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ vbus_typec_en: vbus_typec_en {
-+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pwm1 {
-+ status = "okay";
-+};
-+
-+&pwm2 {
-+ status = "okay";
-+};
-+
-+&pwm12 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pwm12m1_pins>;
-+ status = "okay";
-+};
-+
-+&sdmmc0 {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-+ /* Also used in pcie30x1_clkreqnm0 */
-+ disable-wp;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc3v3_sd>;
-+ vqmmc-supply = <&vccio_sd>;
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+ status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+ phy-supply = <&vbus_typec>;
-+ status = "okay";
-+};
-+
-+&usb2phy1_host {
-+ phy-supply = <&vcc3v3_minipcie>;
-+ status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+ phy-supply = <&vcc3v3_ngff>;
-+ status = "okay";
-+};
+++ /dev/null
-From c80992abd2877590059e9cb254213c16824e2106 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Wed, 18 Jan 2023 13:34:53 +0530
-Subject: [PATCH] arm64: dts: rockchip: Update eMMC, SD aliases for Radxa SoM
- boards
-
-Radxa has produced Compute Modules like RK3399pro VMARC and CM3i with
-onboarding eMMC flash, so the eMMC is the primary MMC device.
-
-On the other hand, Rockchip boot orders start from eMMC from an MMC
-device perspective.
-
-Mark, the eMMC has mmc0 to satisfy the above two conditions.
-
-Reported-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230118080454.11643-1-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 4 ++--
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 3 +--
- 2 files changed, 3 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
-@@ -13,8 +13,8 @@
- compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
-
- aliases {
-- mmc0 = &sdmmc;
-- mmc1 = &sdhci;
-+ mmc0 = &sdhci;
-+ mmc1 = &sdmmc;
- };
-
- vcc3v3_pcie: vcc-pcie-regulator {
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -8,8 +8,7 @@
- compatible = "radxa,e25", "rockchip,rk3568";
-
- aliases {
-- mmc0 = &sdmmc0;
-- mmc1 = &sdhci;
-+ mmc1 = &sdmmc0;
- };
-
- pwm-leds {
+++ /dev/null
-From c4d2b02d63ee38b381fbc886c02eecfec4f981cc Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Mon, 23 Jan 2023 12:46:51 +0530
-Subject: [PATCH] arm64: dts: rockchip: Add missing CM3i fallback compatible
- for Radxa E25
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In order to function the Radxa E25 Carrier board, it is mandatory to
-mount the Radxa CM3i module.
-
-Add Radxa CM3i compatible as fallback compatible to string to satisfy
-the Module and Carrier board topology.
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Cc: Chukun Pan <amadeus@jmu.edu.cn>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230123071654.73139-2-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -5,7 +5,7 @@
-
- / {
- model = "Radxa E25";
-- compatible = "radxa,e25", "rockchip,rk3568";
-+ compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
-
- aliases {
- mmc1 = &sdmmc0;
+++ /dev/null
-From ef9134d9bbce071c9e4ebdcbb6f8fb1a5dd0a67e Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Mon, 23 Jan 2023 12:46:53 +0530
-Subject: [PATCH] arm64: dts: rockchip: Correct the model name for Radxa E25
-
-Radxa E25 is a Carrier board, so update the model name for Radxa E25
-as suggested by the Radxa website.
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Cc: Chukun Pan <amadeus@jmu.edu.cn>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230123071654.73139-4-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -4,7 +4,7 @@
- #include "rk3568-radxa-cm3i.dtsi"
-
- / {
-- model = "Radxa E25";
-+ model = "Radxa E25 Carrier Board";
- compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
-
- aliases {
+++ /dev/null
-From a87852e37f782257ebc57cc44a0d3fbf806471f6 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 24 Jul 2023 14:52:16 +0000
-Subject: [PATCH] arm64: dts: rockchip: Fix PCIe regulators on Radxa E25
-
-Despite its name, the regulator vcc3v3_pcie30x1 has nothing to do with
-pcie30x1. Instead, it supply power to VBAT1-5 on the M.2 KEY B port as
-seen on page 8 of the schematic [1].
-
-pcie30x1 is used for the mini PCIe slot, and as seen on page 9 the
-vcc3v3_minipcie regulator is instead related to pcie30x1.
-
-The M.2 KEY B port can be used for WWAN USB2 modules or SATA drives.
-
-Use correct regulator vcc3v3_minipcie for pcie30x1.
-
-[1] https://dl.radxa.com/cm3p/e25/radxa-e25-v1.4-sch.pdf
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20230724145213.3833099-1-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -47,6 +47,9 @@
- vin-supply = <&vcc5v0_sys>;
- };
-
-+ /* actually fed by vcc5v0_sys, dependent
-+ * on pi6c clock generator
-+ */
- vcc3v3_minipcie: vcc3v3-minipcie-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
-@@ -54,9 +57,9 @@
- pinctrl-names = "default";
- pinctrl-0 = <&minipcie_enable_h>;
- regulator-name = "vcc3v3_minipcie";
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vcc5v0_sys>;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc3v3_pi6c_05>;
- };
-
- vcc3v3_ngff: vcc3v3-ngff-regulator {
-@@ -71,9 +74,6 @@
- vin-supply = <&vcc5v0_sys>;
- };
-
-- /* actually fed by vcc5v0_sys, dependent
-- * on pi6c clock generator
-- */
- vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
-@@ -83,7 +83,7 @@
- regulator-name = "vcc3v3_pcie30x1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-- vin-supply = <&vcc3v3_pi6c_05>;
-+ vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
-@@ -117,7 +117,7 @@
- pinctrl-names = "default";
- pinctrl-0 = <&pcie30x1m0_pins>;
- reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
-- vpcie3v3-supply = <&vcc3v3_pcie30x1>;
-+ vpcie3v3-supply = <&vcc3v3_minipcie>;
- status = "okay";
- };
-
+++ /dev/null
-From 2bdfe84fbd57a4ed9fd65a67210442559ce078f0 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 24 Jul 2023 14:52:16 +0000
-Subject: [PATCH] arm64: dts: rockchip: Enable SATA on Radxa E25
-
-The M.2 KEY B port can be used for WWAN USB2 modules or SATA drives.
-
-Enable sata1 node to fix use of SATA drives on the M.2 slot.
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20230724145213.3833099-1-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -99,6 +99,10 @@
- };
- };
-
-+&combphy1 {
-+ phy-supply = <&vcc3v3_pcie30x1>;
-+};
-+
- &pcie2x1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie20_reset_h>;
-@@ -178,6 +182,10 @@
- status = "okay";
- };
-
-+&sata1 {
-+ status = "okay";
-+};
-+
- &sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
+++ /dev/null
-From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Fri, 10 Jul 2020 21:38:20 +0200
-Subject: [PATCH] rockchip: use system LED for OpenWrt
-
-Use the SYS LED on the casing for showing system status.
-
-This patch is kept separate from the NanoPi R2S support patch, as i plan
-on submitting the device support upstream.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -6,6 +6,7 @@
- /dts-v1/;
-
- #include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
- #include <dt-bindings/gpio/gpio.h>
- #include "rk3328.dtsi"
-
-@@ -16,6 +17,11 @@
- aliases {
- ethernet1 = &rtl8153;
- mmc0 = &sdmmc;
-+
-+ led-boot = &sys_led;
-+ led-failsafe = &sys_led;
-+ led-running = &sys_led;
-+ led-upgrade = &sys_led;
- };
-
- chosen {
-@@ -48,19 +54,22 @@
- pinctrl-names = "default";
-
- lan_led: led-0 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_LAN;
- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-- label = "nanopi-r2s:green:lan";
- };
-
- sys_led: led-1 {
-+ color = <LED_COLOR_ID_RED>;
-+ function = LED_FUNCTION_STATUS;
- gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
-- label = "nanopi-r2s:red:sys";
- default-state = "on";
- };
-
- wan_led: led-2 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_WAN;
- gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
-- label = "nanopi-r2s:green:wan";
- };
- };
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-@@ -13,6 +13,11 @@
- aliases {
- mmc0 = &sdmmc;
- mmc1 = &emmc;
-+
-+ led-boot = &power_led;
-+ led-failsafe = &power_led;
-+ led-running = &power_led;
-+ led-upgrade = &power_led;
- };
-
- chosen {
+++ /dev/null
-From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Sun, 26 Jul 2020 13:32:59 +0200
-Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
-
-This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
-NanoPi R2S. Add the correct value for the RTL8153 LED configuration
-register to match the blink behavior of the other port on the device.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
- 1 file changed, 1 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -406,6 +406,7 @@
- rtl8153: device@2 {
- compatible = "usbbda,8153";
- reg = <2>;
-+ realtek,led-data = <0x87>;
- };
- };
-
+++ /dev/null
-From: David Bauer <mail@david-bauer.net>
-Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S
-
-The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting
-while U-Boot requires the card to be in 3.3V mode.
-
-Remove UHS support from the SD controller so the card remains in 3.3V
-mode. This reduces transfer speeds but ensures a reboot whether from
-userspace or following a kernel panic is always working.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
-@@ -335,7 +335,6 @@
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
-- sd-uhs-sdr104;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vcc_sdio>;
- status = "okay";
---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -112,6 +112,11 @@
- status = "disabled";
- };
-
-+&sdmmc {
-+ /delete-property/ sd-uhs-sdr104;
-+ cap-sd-highspeed;
-+};
-+
- &u2phy0_host {
- phy-supply = <&vdd_5v>;
- };
+++ /dev/null
---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -19,6 +19,13 @@
- model = "FriendlyElec NanoPi R4S";
- compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
-
-+ aliases {
-+ led-boot = &sys_led;
-+ led-failsafe = &sys_led;
-+ led-running = &sys_led;
-+ led-upgrade = &sys_led;
-+ };
-+
- /delete-node/ display-subsystem;
-
- gpio-leds {
+++ /dev/null
-From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Fri, 19 May 2023 12:10:52 +0800
-Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1
- Plus
-
-Add OpenWrt's LED aliases for showing system status.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
----
- .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++--------
- 1 file changed, 9 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-@@ -17,6 +17,11 @@
- aliases {
- ethernet1 = &rtl8153;
- mmc0 = &sdmmc;
-+
-+ led-boot = &status_led;
-+ led-failsafe = &status_led;
-+ led-running = &status_led;
-+ led-upgrade = &status_led;
- };
-
- chosen {
-@@ -41,11 +46,10 @@
- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
- };
-
-- led-1 {
-+ status_led: led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
-- linux,default-trigger = "heartbeat";
- };
-
- led-2 {
+++ /dev/null
-From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Fri, 19 May 2023 12:38:04 +0800
-Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1
- Plus
-
-Add the correct value for the RTL8153 LED configuration register to
-match the blink behavior of the other port on the device.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
----
- arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-@@ -365,6 +365,7 @@
- rtl8153: device@2 {
- compatible = "usbbda,8153";
- reg = <2>;
-+ realtek,led-data = <0x87>;
- };
- };
-
+++ /dev/null
---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
-@@ -15,6 +15,13 @@
- model = "FriendlyElec NanoPC-T4";
- compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
-
-+ aliases {
-+ led-boot = &status_led;
-+ led-failsafe = &status_led;
-+ led-running = &status_led;
-+ led-upgrade = &status_led;
-+ };
-+
- vcc12v0_sys: vcc12v0-sys {
- compatible = "regulator-fixed";
- regulator-always-on;
+++ /dev/null
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Tue Jun 20 16:45:27 2023 +0800
-Subject: [PATCH] arm64: dts: rockchip: Update LED properties for NanoPi R5
- series
-
-Add OpenWrt's LED aliases for showing system status.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
----
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-@@ -40,7 +40,6 @@
- power_led: led-power {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_POWER;
-- linux,default-trigger = "heartbeat";
- gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
- };
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -39,7 +39,6 @@
- power_led: led-power {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_POWER;
-- linux,default-trigger = "heartbeat";
- gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
- };
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-@@ -18,6 +18,11 @@
- aliases {
- mmc0 = &sdmmc0;
- mmc1 = &sdhci;
-+
-+ led-boot = &power_led;
-+ led-failsafe = &power_led;
-+ led-running = &power_led;
-+ led-upgrade = &power_led;
- };
-
- chosen: chosen {
+++ /dev/null
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Marius Durbaca <mariusd84@gmail.com>
-Date: Tue Feb 20 15:05:27 2024 +0200
-Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa
-CM3 IO board
-
-Add OpenWrt's LED aliases for showing system status.
-
-Suggested-by: Tianling Shen <cnsztl@immortalwrt.org>
-Signed-off-by: Marius Durbaca <mariusd84@gmail.com>
----
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -16,6 +16,10 @@
- aliases {
- ethernet0 = &gmac1;
- mmc1 = &sdmmc0;
-+ led-boot = &status_led;
-+ led-failsafe = &status_led;
-+ led-running = &status_led;
-+ led-upgrade = &status_led;
- };
-
- chosen: chosen {
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-@@ -17,7 +17,7 @@
- leds {
- compatible = "gpio-leds";
-
-- led-0 {
-+ status_led: led-0 {
- gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
+++ /dev/null
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: Marius Durbaca <mariusd84@gmail.com>
-Date: Tue Feb 27 16:25:27 2024 +0200
-Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa
-E25
-
-Add OpenWrt's LED aliases for showing system status.
-
-Signed-off-by: Marius Durbaca <mariusd84@gmail.com>
----
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -9,6 +9,10 @@
-
- aliases {
- mmc1 = &sdmmc0;
-+ led-boot = &led_user;
-+ led-failsafe = &led_user;
-+ led-running = &led_user;
-+ led-upgrade = &led_user;
- };
-
- pwm-leds {
--- /dev/null
+From 36d9b3ae708e865cdab95692db5a24c5d975383d Mon Sep 17 00:00:00 2001
+From: Dragan Simic <dsimic@manjaro.org>
+Date: Tue, 12 Dec 2023 09:01:39 +0100
+Subject: [PATCH] arm64: dts: rockchip: Add ethernet0 alias to the dts for
+ RK3566 boards
+
+Add ethernet0 alias to the board dts files for a few supported RK3566 boards
+that had it missing. Also, remove the ethernet0 alias from one RK3566 SoM
+dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to
+the dependent board dts files, which actually enable the GMAC.
+
+Signed-off-by: Dragan Simic <dsimic@manjaro.org>
+Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 1 +
+ 1 files changed, 1 insertions(+), 0 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -14,6 +14,7 @@
+ compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
+
+ aliases {
++ ethernet0 = &gmac1;
+ mmc1 = &sdmmc0;
+ };
+
--- /dev/null
+From 437644753208092f642b7669c69da606aa07dfb4 Mon Sep 17 00:00:00 2001
+From: Tim Lunn <tim@feathertop.org>
+Date: Wed, 14 Feb 2024 15:07:30 +1100
+Subject: [PATCH] arm64: dts: rockchip: adjust vendor on Banana Pi R2 Pro board
+
+Adjust compatible string to match the board vendor of Sinovoip
+
+Signed-off-by: Tim Lunn <tim@feathertop.org>
+Reviewed-by: Dragan Simic <dsimic@manjaro.org>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20240214040731.3069111-4-tim@feathertop.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -13,7 +13,7 @@
+
+ / {
+ model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
+- compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
++ compatible = "sinovoip,rk3568-bpi-r2pro", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
--- /dev/null
+From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Fri, 10 Jul 2020 21:38:20 +0200
+Subject: [PATCH] rockchip: use system LED for OpenWrt
+
+Use the SYS LED on the casing for showing system status.
+
+This patch is kept separate from the NanoPi R2S support patch, as i plan
+on submitting the device support upstream.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -6,6 +6,7 @@
+ /dts-v1/;
+
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include "rk3328.dtsi"
+
+@@ -16,6 +17,11 @@
+ aliases {
+ ethernet1 = &rtl8153;
+ mmc0 = &sdmmc;
++
++ led-boot = &sys_led;
++ led-failsafe = &sys_led;
++ led-running = &sys_led;
++ led-upgrade = &sys_led;
+ };
+
+ chosen {
+@@ -48,19 +54,22 @@
+ pinctrl-names = "default";
+
+ lan_led: led-0 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_LAN;
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+- label = "nanopi-r2s:green:lan";
+ };
+
+ sys_led: led-1 {
++ color = <LED_COLOR_ID_RED>;
++ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+- label = "nanopi-r2s:red:sys";
+ default-state = "on";
+ };
+
+ wan_led: led-2 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_WAN;
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+- label = "nanopi-r2s:green:wan";
+ };
+ };
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -13,6 +13,11 @@
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &emmc;
++
++ led-boot = &power_led;
++ led-failsafe = &power_led;
++ led-running = &power_led;
++ led-upgrade = &power_led;
+ };
+
+ chosen {
--- /dev/null
+From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 26 Jul 2020 13:32:59 +0200
+Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
+
+This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
+NanoPi R2S. Add the correct value for the RTL8153 LED configuration
+register to match the blink behavior of the other port on the device.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
+ 1 file changed, 1 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -406,6 +406,7 @@
+ rtl8153: device@2 {
+ compatible = "usbbda,8153";
+ reg = <2>;
++ realtek,led-data = <0x87>;
+ };
+ };
+
--- /dev/null
+From: David Bauer <mail@david-bauer.net>
+Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S
+
+The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting
+while U-Boot requires the card to be in 3.3V mode.
+
+Remove UHS support from the SD controller so the card remains in 3.3V
+mode. This reduces transfer speeds but ensures a reboot whether from
+userspace or following a kernel panic is always working.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -335,7 +335,6 @@
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+- sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_sdio>;
+ status = "okay";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -112,6 +112,11 @@
+ status = "disabled";
+ };
+
++&sdmmc {
++ /delete-property/ sd-uhs-sdr104;
++ cap-sd-highspeed;
++};
++
+ &u2phy0_host {
+ phy-supply = <&vdd_5v>;
+ };
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -19,6 +19,13 @@
+ model = "FriendlyElec NanoPi R4S";
+ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
+
++ aliases {
++ led-boot = &sys_led;
++ led-failsafe = &sys_led;
++ led-running = &sys_led;
++ led-upgrade = &sys_led;
++ };
++
+ /delete-node/ display-subsystem;
+
+ gpio-leds {
--- /dev/null
+From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Fri, 19 May 2023 12:10:52 +0800
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1
+ Plus
+
+Add OpenWrt's LED aliases for showing system status.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+---
+ .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++--------
+ 1 file changed, 9 insertions(+), 8 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+@@ -17,6 +17,11 @@
+ aliases {
+ ethernet1 = &rtl8153;
+ mmc0 = &sdmmc;
++
++ led-boot = &status_led;
++ led-failsafe = &status_led;
++ led-running = &status_led;
++ led-upgrade = &status_led;
+ };
+
+ chosen {
+@@ -41,11 +46,10 @@
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ };
+
+- led-1 {
++ status_led: led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+
+ led-2 {
--- /dev/null
+From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Fri, 19 May 2023 12:38:04 +0800
+Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1
+ Plus
+
+Add the correct value for the RTL8153 LED configuration register to
+match the blink behavior of the other port on the device.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+@@ -365,6 +365,7 @@
+ rtl8153: device@2 {
+ compatible = "usbbda,8153";
+ reg = <2>;
++ realtek,led-data = <0x87>;
+ };
+ };
+
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
+@@ -15,6 +15,13 @@
+ model = "FriendlyElec NanoPC-T4";
+ compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
+
++ aliases {
++ led-boot = &status_led;
++ led-failsafe = &status_led;
++ led-running = &status_led;
++ led-upgrade = &status_led;
++ };
++
+ vcc12v0_sys: vcc12v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Tue Jun 20 16:45:27 2023 +0800
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for NanoPi R5
+ series
+
+Add OpenWrt's LED aliases for showing system status.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
+@@ -40,7 +40,6 @@
+ power_led: led-power {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+- linux,default-trigger = "heartbeat";
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+@@ -39,7 +39,6 @@
+ power_led: led-power {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+- linux,default-trigger = "heartbeat";
+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ };
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
+@@ -18,6 +18,11 @@
+ aliases {
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
++
++ led-boot = &power_led;
++ led-failsafe = &power_led;
++ led-running = &power_led;
++ led-upgrade = &power_led;
+ };
+
+ chosen: chosen {
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Marius Durbaca <mariusd84@gmail.com>
+Date: Tue Feb 20 15:05:27 2024 +0200
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa
+CM3 IO board
+
+Add OpenWrt's LED aliases for showing system status.
+
+Suggested-by: Tianling Shen <cnsztl@immortalwrt.org>
+Signed-off-by: Marius Durbaca <mariusd84@gmail.com>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -16,6 +16,10 @@
+ aliases {
+ ethernet0 = &gmac1;
+ mmc1 = &sdmmc0;
++ led-boot = &status_led;
++ led-failsafe = &status_led;
++ led-running = &status_led;
++ led-upgrade = &status_led;
+ };
+
+ chosen: chosen {
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+@@ -17,7 +17,7 @@
+ leds {
+ compatible = "gpio-leds";
+
+- led-0 {
++ status_led: led-0 {
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Marius Durbaca <mariusd84@gmail.com>
+Date: Tue Feb 27 16:25:27 2024 +0200
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa
+E25
+
+Add OpenWrt's LED aliases for showing system status.
+
+Signed-off-by: Marius Durbaca <mariusd84@gmail.com>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+@@ -9,6 +9,10 @@
+
+ aliases {
+ mmc1 = &sdmmc0;
++ led-boot = &led_user;
++ led-failsafe = &led_user;
++ led-running = &led_user;
++ led-upgrade = &led_user;
+ };
+
+ pwm-leds {
--- /dev/null
+From patchwork Sat Nov 12 14:10:58 2022
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Aurelien Jarno <aurelien@aurel32.net>
+X-Patchwork-Id: 13041222
+Return-Path:
+ <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>
+X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
+ aws-us-west-2-korg-lkml-1.web.codeaurora.org
+From: Aurelien Jarno <aurelien@aurel32.net>
+To: Olivia Mackall <olivia@selenic.com>,
+ Herbert Xu <herbert@gondor.apana.org.au>,
+ Rob Herring <robh+dt@kernel.org>,
+ Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+ Heiko Stuebner <heiko@sntech.de>,
+ Philipp Zabel <p.zabel@pengutronix.de>,
+ Lin Jinhan <troy.lin@rock-chips.com>
+Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR
+ CORE),
+ devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE
+ BINDINGS),
+ linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC
+ support),
+ linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support),
+ linux-kernel@vger.kernel.org (open list),
+ Aurelien Jarno <aurelien@aurel32.net>
+Subject: [PATCH v1 2/3] hwrng: add Rockchip SoC hwrng driver
+Date: Sat, 12 Nov 2022 15:10:58 +0100
+Message-Id: <20221112141059.3802506-3-aurelien@aurel32.net>
+In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net>
+References: <20221112141059.3802506-1-aurelien@aurel32.net>
+MIME-Version: 1.0
+List-Id: <linux-arm-kernel.lists.infradead.org>
+
+Rockchip SoCs used to have a random number generator as part of their
+crypto device, and support for it has to be added to the corresponding
+driver. However newer Rockchip SoCs like the RK356x have an independent
+True Random Number Generator device. This patch adds a driver for it,
+greatly inspired from the downstream driver.
+
+The TRNG device does not seem to have a signal conditionner and the FIPS
+140-2 test returns a lot of failures. They can be reduced by increasing
+RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value
+has been adjusted to get ~90% of successes and the quality value has
+been set accordingly.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+---
+ drivers/char/hw_random/Kconfig | 14 ++
+ drivers/char/hw_random/Makefile | 1 +
+ drivers/char/hw_random/rockchip-rng.c | 251 ++++++++++++++++++++++++++
+ 3 files changed, 266 insertions(+)
+ create mode 100644 drivers/char/hw_random/rockchip-rng.c
+
+--- a/drivers/char/hw_random/Kconfig
++++ b/drivers/char/hw_random/Kconfig
+@@ -573,6 +573,20 @@ config HW_RANDOM_JH7110
+ To compile this driver as a module, choose M here.
+ The module will be called jh7110-trng.
+
++config HW_RANDOM_ROCKCHIP
++ tristate "Rockchip True Random Number Generator"
++ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
++ depends on HAS_IOMEM
++ default HW_RANDOM
++ help
++ This driver provides kernel-side support for the True Random Number
++ Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
++
++ To compile this driver as a module, choose M here: the
++ module will be called rockchip-rng.
++
++ If unsure, say Y.
++
+ endif # HW_RANDOM
+
+ config UML_RANDOM
+--- a/drivers/char/hw_random/Makefile
++++ b/drivers/char/hw_random/Makefile
+@@ -48,4 +48,5 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe
+ obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
+ obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
+ obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
++obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
+ obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
+--- /dev/null
++++ b/drivers/char/hw_random/rockchip-rng.c
+@@ -0,0 +1,251 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs
++ *
++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2022, Aurelien Jarno
++ * Authors:
++ * Lin Jinhan <troy.lin@rock-chips.com>
++ * Aurelien Jarno <aurelien@aurel32.net>
++ */
++#include <linux/clk.h>
++#include <linux/hw_random.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#define RK_RNG_AUTOSUSPEND_DELAY 100
++#define RK_RNG_MAX_BYTE 32
++#define RK_RNG_POLL_PERIOD_US 100
++#define RK_RNG_POLL_TIMEOUT_US 10000
++
++/*
++ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is
++ * a tradeoff between speed and quality and has been adjusted to get a quality
++ * of ~900 (~90% of FIPS 140-2 successes).
++ */
++#define RK_RNG_SAMPLE_CNT 1000
++
++/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
++#define TRNG_RST_CTL 0x0004
++#define TRNG_RNG_CTL 0x0400
++#define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4)
++#define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4)
++#define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4)
++#define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2)
++#define TRNG_RNG_CTL_ENABLE BIT(1)
++#define TRNG_RNG_CTL_START BIT(0)
++#define TRNG_RNG_SAMPLE_CNT 0x0404
++#define TRNG_RNG_DOUT_0 0x0410
++#define TRNG_RNG_DOUT_1 0x0414
++#define TRNG_RNG_DOUT_2 0x0418
++#define TRNG_RNG_DOUT_3 0x041c
++#define TRNG_RNG_DOUT_4 0x0420
++#define TRNG_RNG_DOUT_5 0x0424
++#define TRNG_RNG_DOUT_6 0x0428
++#define TRNG_RNG_DOUT_7 0x042c
++
++struct rk_rng {
++ struct hwrng rng;
++ void __iomem *base;
++ struct reset_control *rst;
++ int clk_num;
++ struct clk_bulk_data *clk_bulks;
++};
++
++/* The mask determine the bits that are updated */
++static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
++{
++ writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL);
++}
++
++static int rk_rng_init(struct hwrng *rng)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++ u32 reg;
++ int ret;
++
++ /* start clocks */
++ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
++ if (ret < 0) {
++ dev_err((struct device *) rk_rng->rng.priv,
++ "Failed to enable clks %d\n", ret);
++ return ret;
++ }
++
++ /* set the sample period */
++ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
++
++ /* set osc ring speed and enable it */
++ reg = TRNG_RNG_CTL_LEN_256_BIT |
++ TRNG_RNG_CTL_OSC_RING_SPEED_0 |
++ TRNG_RNG_CTL_ENABLE;
++ rk_rng_write_ctl(rk_rng, reg, 0xffff);
++
++ return 0;
++}
++
++static void rk_rng_cleanup(struct hwrng *rng)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++ u32 reg;
++
++ /* stop TRNG */
++ reg = 0;
++ rk_rng_write_ctl(rk_rng, reg, 0xffff);
++
++ /* stop clocks */
++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
++}
++
++static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++ u32 reg;
++ int ret = 0;
++ int i;
++
++ pm_runtime_get_sync((struct device *) rk_rng->rng.priv);
++
++ /* Start collecting random data */
++ reg = TRNG_RNG_CTL_START;
++ rk_rng_write_ctl(rk_rng, reg, reg);
++
++ ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
++ !(reg & TRNG_RNG_CTL_START),
++ RK_RNG_POLL_PERIOD_US,
++ RK_RNG_POLL_TIMEOUT_US);
++ if (ret < 0)
++ goto out;
++
++ /* Read random data stored in big endian in the registers */
++ ret = min_t(size_t, max, RK_RNG_MAX_BYTE);
++ for (i = 0; i < ret; i += 4) {
++ reg = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i);
++ *(u32 *)(buf + i) = be32_to_cpu(reg);
++ }
++
++out:
++ pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
++ pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
++
++ return ret;
++}
++
++static int rk_rng_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct rk_rng *rk_rng;
++ int ret;
++
++ rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL);
++ if (!rk_rng)
++ return -ENOMEM;
++
++ rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(rk_rng->base))
++ return PTR_ERR(rk_rng->base);
++
++ rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
++ if (rk_rng->clk_num < 0)
++ return dev_err_probe(dev, rk_rng->clk_num,
++ "Failed to get clks property\n");
++
++ rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false);
++ if (IS_ERR(rk_rng->rst))
++ return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
++ "Failed to get reset property\n");
++
++ reset_control_assert(rk_rng->rst);
++ udelay(2);
++ reset_control_deassert(rk_rng->rst);
++
++ platform_set_drvdata(pdev, rk_rng);
++
++ rk_rng->rng.name = dev_driver_string(dev);
++#ifndef CONFIG_PM
++ rk_rng->rng.init = rk_rng_init;
++ rk_rng->rng.cleanup = rk_rng_cleanup;
++#endif
++ rk_rng->rng.read = rk_rng_read;
++ rk_rng->rng.priv = (unsigned long) dev;
++ rk_rng->rng.quality = 900;
++
++ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
++ pm_runtime_use_autosuspend(dev);
++ pm_runtime_enable(dev);
++
++ ret = devm_hwrng_register(dev, &rk_rng->rng);
++ if (ret)
++ return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
++
++ dev_info(&pdev->dev, "Registered Rockchip hwrng\n");
++
++ return 0;
++}
++
++static int rk_rng_remove(struct platform_device *pdev)
++{
++ pm_runtime_disable(&pdev->dev);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int rk_rng_runtime_suspend(struct device *dev)
++{
++ struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++ rk_rng_cleanup(&rk_rng->rng);
++
++ return 0;
++}
++
++static int rk_rng_runtime_resume(struct device *dev)
++{
++ struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++ return rk_rng_init(&rk_rng->rng);
++}
++#endif
++
++static const struct dev_pm_ops rk_rng_pm_ops = {
++ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
++ rk_rng_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++ pm_runtime_force_resume)
++};
++
++static const struct of_device_id rk_rng_dt_match[] = {
++ {
++ .compatible = "rockchip,rk3568-rng",
++ },
++ {},
++};
++
++MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
++
++static struct platform_driver rk_rng_driver = {
++ .driver = {
++ .name = "rockchip-rng",
++ .pm = &rk_rng_pm_ops,
++ .of_match_table = rk_rng_dt_match,
++ },
++ .probe = rk_rng_probe,
++ .remove = rk_rng_remove,
++};
++
++module_platform_driver(rk_rng_driver);
++
++MODULE_DESCRIPTION("Rockchip True Random Number Generator driver");
++MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>, Aurelien Jarno <aurelien@aurel32.net>");
++MODULE_LICENSE("GPL v2");
--- /dev/null
+From patchwork Sat Nov 12 14:10:59 2022
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Aurelien Jarno <aurelien@aurel32.net>
+X-Patchwork-Id: 13041221
+From: Aurelien Jarno <aurelien@aurel32.net>
+To: Olivia Mackall <olivia@selenic.com>,
+ Herbert Xu <herbert@gondor.apana.org.au>,
+ Rob Herring <robh+dt@kernel.org>,
+ Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+ Heiko Stuebner <heiko@sntech.de>,
+ Philipp Zabel <p.zabel@pengutronix.de>,
+ Lin Jinhan <troy.lin@rock-chips.com>
+Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR
+ CORE),
+ devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE
+ BINDINGS),
+ linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC
+ support),
+ linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support),
+ linux-kernel@vger.kernel.org (open list),
+ Aurelien Jarno <aurelien@aurel32.net>
+Subject: [PATCH v1 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x
+Date: Sat, 12 Nov 2022 15:10:59 +0100
+Message-Id: <20221112141059.3802506-4-aurelien@aurel32.net>
+In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net>
+References: <20221112141059.3802506-1-aurelien@aurel32.net>
+MIME-Version: 1.0
+List-Id: <linux-arm-kernel.lists.infradead.org>
+
+Enable the just added Rockchip RNG driver for RK356x SoCs.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1807,6 +1807,15 @@
+ };
+ };
+
++ rng: rng@fe388000 {
++ compatible = "rockchip,rk3568-rng";
++ reg = <0x0 0xfe388000 0x0 0x4000>;
++ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
++ clock-names = "trng_clk", "trng_hclk";
++ resets = <&cru SRST_TRNG_NS>;
++ reset-names = "reset";
++ };
++
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3568-pinctrl";
+ rockchip,grf = <&grf>;
KERNELNAME:=Image dtbs
SUBTARGETS:=generic
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_ARCH_CLOCKSOURCE_INIT=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_RV64I=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ASN1=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_ATA=y
-CONFIG_ATA_VERBOSE_ERROR=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CAVIUM_PTP=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
-CONFIG_CLK_SIFIVE=y
-CONFIG_CLK_SIFIVE_PRCI=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CLZ_TAB=y
-CONFIG_CMODEL_MEDANY=y
-# CONFIG_CMODEL_MEDLOW is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_COMPAT_BRK=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPU_ISOLATION=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC7=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECHAINIV=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EDAC=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_LEGACY_SYSFS=y
-CONFIG_EDAC_SIFIVE=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=m
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_COCO_SECRET is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_GENERIC_STUB=y
-CONFIG_EFI_PARAMS_FROM_FDT=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-# CONFIG_EFI_ZBOOT is not set
-CONFIG_ELF_CORE=y
-CONFIG_ERRATA_SIFIVE=y
-CONFIG_ERRATA_SIFIVE_CIP_1200=y
-CONFIG_ERRATA_SIFIVE_CIP_453=y
-# CONFIG_ERRATA_THEAD is not set
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_FAILOVER=y
-CONFIG_FAT_FS=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FPU=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_INJECTION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_CDEV_V1=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_SIFIVE=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HOTPLUG_PCI=y
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_HOTPLUG_PCI_SHPC=y
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_RISCV_SBI=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_OCORES=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IO_URING=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KEYS=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MACB=y
-# CONFIG_MACB_PCI is not set
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICROSEMI_PHY=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_CADENCE=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SPI=y
-CONFIG_MMIOWB=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MODULE_SECTIONS=y
-CONFIG_MPILIB=y
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NONPORTABLE is not set
-CONFIG_NR_CPUS=8
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DMA_DEFAULT_COHERENT=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OID_REGISTRY=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xff60000000000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEAER_INJECT=m
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DPC=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_ECRC=y
-CONFIG_PCIE_FU740=y
-CONFIG_PCIE_PTM=y
-CONFIG_PCIE_XILINX=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_SW_SWITCHTEC=y
-CONFIG_PGTABLE_LEVELS=5
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PORTABLE=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_POWER_RESET_RESTART=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_SIFIVE=y
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_TRACE=y
-CONFIG_RD_GZIP=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-# CONFIG_RESET_ATTACK_MITIGATION is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RISCV=y
-CONFIG_RISCV_ALTERNATIVE=y
-# CONFIG_RISCV_BOOT_SPINWAIT is not set
-CONFIG_RISCV_DMA_NONCOHERENT=y
-CONFIG_RISCV_INTC=y
-CONFIG_RISCV_ISA_C=y
-CONFIG_RISCV_ISA_SVPBMT=y
-CONFIG_RISCV_ISA_ZICBOM=y
-CONFIG_RISCV_SBI=y
-CONFIG_RISCV_SBI_V01=y
-CONFIG_RISCV_TIMER=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_EFI is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_DEBUG=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_SIFIVE=y
-CONFIG_SERIAL_SIFIVE_CONSOLE=y
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SIFIVE_CCACHE=y
-CONFIG_SIFIVE_PLIC=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
-CONFIG_SOC_SIFIVE=y
-# CONFIG_SOC_STARFIVE is not set
-# CONFIG_SOC_VIRT is not set
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_SIFIVE=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_SYSFB_SIMPLEFB is not set
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TOOLCHAIN_HAS_ZICBOM=y
-CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
-CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TUNE_GENERIC=y
-CONFIG_UCS2_STRING=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_HID=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PCI=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_VFAT_FS=y
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VMAP_STACK=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
--- /dev/null
+CONFIG_64BIT=y
+# CONFIG_ACPI is not set
+CONFIG_ARCH_CLOCKSOURCE_INIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_RV64I=y
+# CONFIG_ARCH_THEAD is not set
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ATA=y
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_AX45MP_L2_CACHE is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CAVIUM_PTP=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
+CONFIG_CLK_SIFIVE=y
+CONFIG_CLK_SIFIVE_PRCI=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMODEL_MEDANY=y
+# CONFIG_CMODEL_MEDLOW is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC7=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EDAC=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_SIFIVE=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_COCO_SECRET is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_ZBOOT is not set
+CONFIG_ELF_CORE=y
+# CONFIG_ERRATA_ANDES is not set
+CONFIG_ERRATA_SIFIVE=y
+CONFIG_ERRATA_SIFIVE_CIP_1200=y
+CONFIG_ERRATA_SIFIVE_CIP_453=y
+# CONFIG_ERRATA_THEAD is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_FAILOVER=y
+CONFIG_FAT_FS=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_AUTOSELECT=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FPU=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_INJECTION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_SIFIVE=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_RISCV_SBI=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_OCORES=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMUFD is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IO_URING=y
+CONFIG_IRQ_STACKS=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KEYS=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MACB=y
+# CONFIG_MACB_PCI is not set
+CONFIG_MACB_USE_HWSTAMP=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_CADENCE=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SPI=y
+CONFIG_MMIOWB=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MODULE_SECTIONS=y
+CONFIG_MPILIB=y
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NONPORTABLE is not set
+CONFIG_NR_CPUS=8
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DMA_DEFAULT_COHERENT=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OID_REGISTRY=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xff60000000000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEAER_INJECT=m
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DPC=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_ECRC=y
+CONFIG_PCIE_FU740=y
+CONFIG_PCIE_PTM=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_SW_SWITCHTEC=y
+CONFIG_PGTABLE_LEVELS=5
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PORTABLE=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_RESTART=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_SIFIVE=y
+CONFIG_PWM_SYSFS=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_TRACE=y
+CONFIG_RD_GZIP=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SIMPLE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RISCV=y
+CONFIG_RISCV_ALTERNATIVE=y
+# CONFIG_RISCV_BOOT_SPINWAIT is not set
+CONFIG_RISCV_DMA_NONCOHERENT=y
+CONFIG_RISCV_INTC=y
+CONFIG_RISCV_ISA_C=y
+CONFIG_RISCV_ISA_FALLBACK=y
+CONFIG_RISCV_ISA_SVNAPOT=y
+CONFIG_RISCV_ISA_SVPBMT=y
+CONFIG_RISCV_ISA_V=y
+CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y
+CONFIG_RISCV_ISA_ZBB=y
+CONFIG_RISCV_ISA_ZICBOZ=y
+CONFIG_RISCV_ISA_ZICBOM=y
+CONFIG_RISCV_SBI=y
+CONFIG_RISCV_SBI_V01=y
+CONFIG_RISCV_TIMER=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_EFI is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SIFIVE=y
+CONFIG_SERIAL_SIFIVE_CONSOLE=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SIFIVE_CCACHE=y
+CONFIG_SIFIVE_PLIC=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
+CONFIG_SOC_SIFIVE=y
+# CONFIG_SOC_STARFIVE is not set
+# CONFIG_SOC_VIRT is not set
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_SIFIVE=y
+CONFIG_SRCU=y
+CONFIG_STACKTRACE=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_THREAD_SIZE_ORDER=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TOOLCHAIN_HAS_ZICBOM=y
+CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
+CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TUNE_GENERIC=y
+CONFIG_UCS2_STRING=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_HID=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_VFAT_FS=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+++ /dev/null
-From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Wed, 17 Feb 2021 06:06:14 -0800
-Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
- sifive,u74-mc
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
-+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
-@@ -39,7 +39,7 @@
- };
- };
- cpu1: cpu@1 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
-@@ -63,7 +63,7 @@
- };
- };
- cpu2: cpu@2 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
-@@ -87,7 +87,7 @@
- };
- };
- cpu3: cpu@3 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
-@@ -111,7 +111,7 @@
- };
- };
- cpu4: cpu@4 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
+++ /dev/null
-From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Mon, 13 Sep 2021 02:18:30 -0700
-Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node
-
-Add gpio-poweroff node to allow powering off the system.
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-@@ -86,6 +86,11 @@
- };
- };
- };
-+
-+ gpio-poweroff {
-+ compatible = "gpio-poweroff";
-+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
-+ };
- };
-
- &uart0 {
+++ /dev/null
-From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Fri, 14 May 2021 05:27:51 -0700
-Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
-
-Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/Kconfig | 8 +++++
- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++
- .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
- 3 files changed, 47 insertions(+)
-
---- a/arch/riscv/Kconfig
-+++ b/arch/riscv/Kconfig
-@@ -711,6 +711,14 @@ config PORTABLE
- select OF
- select MMU
-
-+menu "CPU Power Management"
-+
-+source "drivers/cpuidle/Kconfig"
-+
-+source "drivers/cpufreq/Kconfig"
-+
-+endmenu
-+
- menu "Power management options"
-
- source "kernel/power/Kconfig"
---- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-@@ -30,6 +30,7 @@
- i-cache-size = <16384>;
- reg = <0>;
- riscv,isa = "rv64imac";
-+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- status = "disabled";
- cpu0_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -54,6 +55,7 @@
- reg = <1>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu1_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -78,6 +80,7 @@
- reg = <2>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu2_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -102,6 +105,7 @@
- reg = <3>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu3_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -126,6 +130,7 @@
- reg = <4>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu4_intc: interrupt-controller {
- #interrupt-cells = <1>;
---- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-@@ -80,6 +80,40 @@
- label = "d4";
- };
- };
-+
-+ fu540_c000_opp_table: opp-table {
-+ compatible = "operating-points-v2";
-+ opp-shared;
-+
-+ opp-350000000 {
-+ opp-hz = /bits/ 64 <350000000>;
-+ };
-+ opp-700000000 {
-+ opp-hz = /bits/ 64 <700000000>;
-+ };
-+ opp-999999999 {
-+ opp-hz = /bits/ 64 <999999999>;
-+ };
-+ opp-1400000000 {
-+ opp-hz = /bits/ 64 <1400000000>;
-+ };
-+ };
-+};
-+
-+&cpu0 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu1 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu2 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu3 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu4 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
- };
-
- &uart0 {
--- /dev/null
+From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
+From: David Abdurachmanov <david.abdurachmanov@sifive.com>
+Date: Wed, 17 Feb 2021 06:06:14 -0800
+Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
+ sifive,u74-mc
+
+Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
+---
+ arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
++++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+@@ -39,7 +39,7 @@
+ };
+ };
+ cpu1: cpu@1 {
+- compatible = "sifive,bullet0", "riscv";
++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+@@ -63,7 +63,7 @@
+ };
+ };
+ cpu2: cpu@2 {
+- compatible = "sifive,bullet0", "riscv";
++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+@@ -87,7 +87,7 @@
+ };
+ };
+ cpu3: cpu@3 {
+- compatible = "sifive,bullet0", "riscv";
++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+@@ -111,7 +111,7 @@
+ };
+ };
+ cpu4: cpu@4 {
+- compatible = "sifive,bullet0", "riscv";
++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
--- /dev/null
+From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001
+From: David Abdurachmanov <david.abdurachmanov@sifive.com>
+Date: Mon, 13 Sep 2021 02:18:30 -0700
+Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node
+
+Add gpio-poweroff node to allow powering off the system.
+
+Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
+---
+ arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
++++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
+@@ -86,6 +86,11 @@
+ };
+ };
+ };
++
++ gpio-poweroff {
++ compatible = "gpio-poweroff";
++ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
++ };
+ };
+
+ &uart0 {
--- /dev/null
+From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
+From: David Abdurachmanov <david.abdurachmanov@sifive.com>
+Date: Fri, 14 May 2021 05:27:51 -0700
+Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
+
+Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
+
+Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
+---
+ arch/riscv/Kconfig | 8 +++++
+ arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++
+ .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
+ 3 files changed, 47 insertions(+)
+
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -896,6 +896,14 @@ config PORTABLE
+ select MMU
+ select OF
+
++menu "CPU Power Management"
++
++source "drivers/cpuidle/Kconfig"
++
++source "drivers/cpufreq/Kconfig"
++
++endmenu
++
+ menu "Power management options"
+
+ source "kernel/power/Kconfig"
+--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
++++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+@@ -30,6 +30,7 @@
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
++ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
+ status = "disabled";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+@@ -54,6 +55,7 @@
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
++ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
+ next-level-cache = <&l2cache>;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+@@ -78,6 +80,7 @@
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
++ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
+ next-level-cache = <&l2cache>;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+@@ -102,6 +105,7 @@
+ reg = <3>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
++ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
+ next-level-cache = <&l2cache>;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+@@ -126,6 +130,7 @@
+ reg = <4>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
++ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
+ next-level-cache = <&l2cache>;
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
++++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+@@ -80,6 +80,40 @@
+ label = "d4";
+ };
+ };
++
++ fu540_c000_opp_table: opp-table {
++ compatible = "operating-points-v2";
++ opp-shared;
++
++ opp-350000000 {
++ opp-hz = /bits/ 64 <350000000>;
++ };
++ opp-700000000 {
++ opp-hz = /bits/ 64 <700000000>;
++ };
++ opp-999999999 {
++ opp-hz = /bits/ 64 <999999999>;
++ };
++ opp-1400000000 {
++ opp-hz = /bits/ 64 <1400000000>;
++ };
++ };
++};
++
++&cpu0 {
++ operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu1 {
++ operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu2 {
++ operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu3 {
++ operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu4 {
++ operating-points-v2 = <&fu540_c000_opp_table>;
+ };
+
+ &uart0 {
ARCH:=arm
BOARD:=sunxi
BOARDNAME:=Allwinner ARM SoCs
-FEATURES:=fpu usb ext4 display rootfs-part rtc squashfs
+FEATURES:=usb ext4 display rootfs-part rtc squashfs
SUBTARGETS:=cortexa8 cortexa7 cortexa53
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
KERNELNAME:=zImage dtbs
lamobo,lamobo-r1)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan
;;
- olimex,a20-olinuxino-micro)
+ olimex,a13-olinuxino-micro)
ucidef_set_interface_lan "wlan0"
;;
xunlong,orangepi-r1)
+++ /dev/null
-# CONFIG_AHCI_SUNXI is not set
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_FORCE_MAX_ORDER=11
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=416
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_SUNXI_MC_SMP=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_ARM_CCI=y
-CONFIG_ARM_CCI400_COMMON=y
-CONFIG_ARM_CCI400_PORT_CTRL=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_ERRATA_643719=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_LPAE=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_AXP20X_POWER=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CAN=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLK_SUNXI=y
-CONFIG_CLK_SUNXI_CLOCKS=y
-CONFIG_CLK_SUNXI_PRCM_SUN6I=y
-CONFIG_CLK_SUNXI_PRCM_SUN8I=y
-CONFIG_CLK_SUNXI_PRCM_SUN9I=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONNECTOR=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_ALLWINNER=y
-CONFIG_CRYPTO_DEV_SUN4I_SS=y
-# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
-CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
-# CONFIG_CRYPTO_DEV_SUN8I_CE is not set
-# CONFIG_CRYPTO_DEV_SUN8I_SS is not set
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SUN4I=y
-CONFIG_DMA_SUN6I=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DVB_CORE=y
-CONFIG_DWMAC_GENERIC=y
-# CONFIG_DWMAC_SUN8I is not set
-CONFIG_DWMAC_SUNXI=y
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ELF_CORE=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FAT_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_FOREIGN_ENDIAN=y
-CONFIG_FB_LITTLE_ENDIAN=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_TILEBLITTING=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FRAME_WARN=2048
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_I2C_SUN6I_P2WI=y
-CONFIG_IIO=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_AXP20X_PEK=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KEYBOARD_SUN4I_LRADC=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_KSM=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_PLATFORM=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_MACH_SUN4I=y
-CONFIG_MACH_SUN5I=y
-CONFIG_MACH_SUN6I=y
-CONFIG_MACH_SUN7I=y
-CONFIG_MACH_SUN8I=y
-CONFIG_MACH_SUN9I=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_SUN4I=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_ATTACH=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_TEST_SUPPORT=y
-CONFIG_MEDIA_TUNER=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_AXP20X=y
-CONFIG_MFD_AXP20X_I2C=y
-CONFIG_MFD_AXP20X_RSB=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SUN6I_PRCM=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SUNXI=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_VENDOR_ALLWINNER=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=8
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SUNXI_SID=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PCS_XPCS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_SUN4I_USB=y
-# CONFIG_PHY_SUN50I_USB3 is not set
-# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
-CONFIG_PHY_SUN9I_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AXP209=y
-# CONFIG_PINCTRL_SUN20I_D1 is not set
-CONFIG_PINCTRL_SUN4I_A10=y
-# CONFIG_PINCTRL_SUN50I_A100 is not set
-# CONFIG_PINCTRL_SUN50I_A100_R is not set
-# CONFIG_PINCTRL_SUN50I_A64 is not set
-# CONFIG_PINCTRL_SUN50I_A64_R is not set
-# CONFIG_PINCTRL_SUN50I_H5 is not set
-# CONFIG_PINCTRL_SUN50I_H6 is not set
-# CONFIG_PINCTRL_SUN50I_H616 is not set
-# CONFIG_PINCTRL_SUN50I_H616_R is not set
-# CONFIG_PINCTRL_SUN50I_H6_R is not set
-CONFIG_PINCTRL_SUN5I=y
-CONFIG_PINCTRL_SUN6I_A31=y
-CONFIG_PINCTRL_SUN6I_A31_R=y
-CONFIG_PINCTRL_SUN8I_A23=y
-CONFIG_PINCTRL_SUN8I_A23_R=y
-CONFIG_PINCTRL_SUN8I_A33=y
-CONFIG_PINCTRL_SUN8I_A83T=y
-CONFIG_PINCTRL_SUN8I_A83T_R=y
-CONFIG_PINCTRL_SUN8I_H3=y
-CONFIG_PINCTRL_SUN8I_H3_R=y
-CONFIG_PINCTRL_SUN8I_V3S=y
-CONFIG_PINCTRL_SUN9I_A80=y
-CONFIG_PINCTRL_SUN9I_A80_R=y
-CONFIG_PINCTRL_SUNXI=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_OPP=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_SUN4I=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_AXP20X=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_REGULATOR_SY8106A=y
-CONFIG_RELAY=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_SUNXI=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SATA_HOST=y
-CONFIG_SATA_PMP=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SDIO_UART=y
-CONFIG_SECURITYFS=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=8
-CONFIG_SERIAL_8250_RUNTIME_UARTS=8
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SND=y
-CONFIG_SND_COMPRESS_OFFLOAD=y
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_PCM=y
-CONFIG_SND_SIMPLE_CARD=y
-CONFIG_SND_SIMPLE_CARD_UTILS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SUN4I_I2S is not set
-# CONFIG_SND_SUN4I_SPDIF is not set
-# CONFIG_SND_SUN50I_DMIC is not set
-# CONFIG_SND_SUN8I_CODEC is not set
-# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_SUN4I=y
-CONFIG_SPI_SUN6I=y
-CONFIG_SRCU=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_SUN4I_A10_CCU=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_SUN4I_TIMER=y
-CONFIG_SUN5I_CCU=y
-CONFIG_SUN5I_HSTIMER=y
-CONFIG_SUN6I_A31_CCU=y
-# CONFIG_SUN6I_RTC_CCU is not set
-CONFIG_SUN8I_A23_CCU=y
-CONFIG_SUN8I_A33_CCU=y
-CONFIG_SUN8I_A83T_CCU=y
-CONFIG_SUN8I_DE2_CCU=y
-CONFIG_SUN8I_H3_CCU=y
-CONFIG_SUN8I_R40_CCU=y
-CONFIG_SUN8I_R_CCU=y
-CONFIG_SUN8I_THERMAL=y
-CONFIG_SUN8I_V3S_CCU=y
-CONFIG_SUN9I_A80_CCU=y
-CONFIG_SUNXI_CCU=y
-CONFIG_SUNXI_MBUS=y
-CONFIG_SUNXI_RSB=y
-CONFIG_SUNXI_SRAM=y
-CONFIG_SUNXI_WATCHDOG=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_TOUCHSCREEN_SUN4I=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_DWC2=y
-CONFIG_USB_DWC2_HOST=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USERIO=y
-CONFIG_USE_OF=y
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VHOST=y
-CONFIG_VHOST_IOTLB=y
-CONFIG_VHOST_NET=y
-# CONFIG_VIDEO_SUN4I_CSI is not set
-# CONFIG_VIDEO_SUN6I_CSI is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
--- /dev/null
+# CONFIG_AHCI_SUNXI is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=11
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=416
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SUNXI_MC_SMP=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_CCI=y
+CONFIG_ARM_CCI400_COMMON=y
+CONFIG_ARM_CCI400_PORT_CTRL=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_AXP20X_POWER=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CAN=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_SUNXI=y
+CONFIG_CLK_SUNXI_CLOCKS=y
+CONFIG_CLK_SUNXI_PRCM_SUN6I=y
+CONFIG_CLK_SUNXI_PRCM_SUN8I=y
+CONFIG_CLK_SUNXI_PRCM_SUN9I=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_ALLWINNER=y
+CONFIG_CRYPTO_DEV_SUN4I_SS=y
+# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
+CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
+# CONFIG_CRYPTO_DEV_SUN8I_CE is not set
+# CONFIG_CRYPTO_DEV_SUN8I_SS is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_SUN4I=y
+CONFIG_DMA_SUN6I=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DVB_CORE=y
+CONFIG_DWMAC_GENERIC=y
+# CONFIG_DWMAC_SUN8I is not set
+CONFIG_DWMAC_SUNXI=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_ELF_CORE=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_FOREIGN_ENDIAN=y
+CONFIG_FB_LITTLE_ENDIAN=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIO_CDEV=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_SUN6I_P2WI=y
+CONFIG_IIO=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_AXP20X_PEK=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KEYBOARD_SUN4I_LRADC=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_KSM=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_MACH_SUN4I=y
+CONFIG_MACH_SUN5I=y
+CONFIG_MACH_SUN6I=y
+CONFIG_MACH_SUN7I=y
+CONFIG_MACH_SUN8I=y
+CONFIG_MACH_SUN9I=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_SUN4I=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_TEST_SUPPORT=y
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_AXP20X_RSB=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_ALLWINNER=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=8
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PCS_XPCS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_SUN4I_USB=y
+# CONFIG_PHY_SUN50I_USB3 is not set
+# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
+CONFIG_PHY_SUN9I_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AXP209=y
+# CONFIG_PINCTRL_SUN20I_D1 is not set
+CONFIG_PINCTRL_SUN4I_A10=y
+# CONFIG_PINCTRL_SUN50I_A100 is not set
+# CONFIG_PINCTRL_SUN50I_A100_R is not set
+# CONFIG_PINCTRL_SUN50I_A64 is not set
+# CONFIG_PINCTRL_SUN50I_A64_R is not set
+# CONFIG_PINCTRL_SUN50I_H5 is not set
+# CONFIG_PINCTRL_SUN50I_H6 is not set
+# CONFIG_PINCTRL_SUN50I_H616 is not set
+# CONFIG_PINCTRL_SUN50I_H616_R is not set
+# CONFIG_PINCTRL_SUN50I_H6_R is not set
+CONFIG_PINCTRL_SUN5I=y
+CONFIG_PINCTRL_SUN6I_A31=y
+CONFIG_PINCTRL_SUN6I_A31_R=y
+CONFIG_PINCTRL_SUN8I_A23=y
+CONFIG_PINCTRL_SUN8I_A23_R=y
+CONFIG_PINCTRL_SUN8I_A33=y
+CONFIG_PINCTRL_SUN8I_A83T=y
+CONFIG_PINCTRL_SUN8I_A83T_R=y
+CONFIG_PINCTRL_SUN8I_H3=y
+CONFIG_PINCTRL_SUN8I_H3_R=y
+CONFIG_PINCTRL_SUN8I_V3S=y
+CONFIG_PINCTRL_SUN9I_A80=y
+CONFIG_PINCTRL_SUN9I_A80_R=y
+CONFIG_PINCTRL_SUNXI=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_SUN4I=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RATIONAL=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_SY8106A=y
+CONFIG_RELAY=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SIMPLE=y
+CONFIG_RESET_SUNXI=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_HOST=y
+CONFIG_SATA_PMP=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SDIO_UART=y
+CONFIG_SECURITYFS=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=8
+CONFIG_SERIAL_8250_RUNTIME_UARTS=8
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SND=y
+CONFIG_SND_COMPRESS_OFFLOAD=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SIMPLE_CARD_UTILS=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SUN4I_I2S is not set
+# CONFIG_SND_SUN4I_SPDIF is not set
+# CONFIG_SND_SUN50I_DMIC is not set
+# CONFIG_SND_SUN8I_CODEC is not set
+# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_SUN4I=y
+CONFIG_SPI_SUN6I=y
+CONFIG_SRCU=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+# CONFIG_SUN20I_GPADC is not set
+# CONFIG_SUN20I_PPU is not set
+CONFIG_SUN4I_A10_CCU=y
+# CONFIG_SUN4I_EMAC is not set
+CONFIG_SUN4I_TIMER=y
+CONFIG_SUN5I_CCU=y
+CONFIG_SUN5I_HSTIMER=y
+CONFIG_SUN6I_A31_CCU=y
+# CONFIG_SUN6I_RTC_CCU is not set
+CONFIG_SUN8I_A23_CCU=y
+CONFIG_SUN8I_A33_CCU=y
+CONFIG_SUN8I_A83T_CCU=y
+CONFIG_SUN8I_DE2_CCU=y
+CONFIG_SUN8I_H3_CCU=y
+CONFIG_SUN8I_R40_CCU=y
+CONFIG_SUN8I_R_CCU=y
+CONFIG_SUN8I_THERMAL=y
+CONFIG_SUN8I_V3S_CCU=y
+CONFIG_SUN9I_A80_CCU=y
+CONFIG_SUNXI_CCU=y
+CONFIG_SUNXI_MBUS=y
+CONFIG_SUNXI_RSB=y
+CONFIG_SUNXI_SRAM=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TOUCHSCREEN_SUN4I=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_HOST=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USERIO=y
+CONFIG_USE_OF=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VHOST=y
+CONFIG_VHOST_IOTLB=y
+CONFIG_VHOST_NET=y
+# CONFIG_VIDEO_SUN4I_CSI is not set
+# CONFIG_VIDEO_SUN6I_CSI is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_ERRATUM_2051678=y
-CONFIG_ARM64_ERRATUM_2077057=y
-CONFIG_ARM64_ERRATUM_2658417=y
-CONFIG_ARM64_ERRATUM_2054223=y
-CONFIG_ARM64_ERRATUM_2067961=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_BLAKE2S=y
-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_SHA1_ARM64_CE=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DWMAC_SUN8I=y
-CONFIG_EEPROM_AT24=y
-CONFIG_FRAME_POINTER=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MICREL_PHY=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MOTORCOMM_PHY=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_IOPORT_MAP=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PHY_SUN50I_USB3=y
-CONFIG_PINCTRL_SUN50I_A100=y
-CONFIG_PINCTRL_SUN50I_A100_R=y
-CONFIG_PINCTRL_SUN50I_A64=y
-CONFIG_PINCTRL_SUN50I_A64_R=y
-CONFIG_PINCTRL_SUN50I_H5=y
-CONFIG_PINCTRL_SUN50I_H6=y
-CONFIG_PINCTRL_SUN50I_H6_R=y
-CONFIG_PINCTRL_SUN50I_H616=y
-CONFIG_PINCTRL_SUN50I_H616_R=y
-# CONFIG_PREEMPT_DYNAMIC is not set
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-# CONFIG_SCHED_CLUSTER is not set
-# CONFIG_SHADOW_CALL_STACK is not set
-# CONFIG_SND_SUN50I_CODEC_ANALOG is not set
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SUN50I_A100_CCU=y
-CONFIG_SUN50I_A100_R_CCU=y
-CONFIG_SUN50I_A64_CCU=y
-CONFIG_SUN50I_DE2_BUS=y
-CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
-CONFIG_SUN50I_H616_CCU=y
-CONFIG_SUN50I_H6_CCU=y
-CONFIG_SUN50I_H6_R_CCU=y
-# CONFIG_SUN6I_RTC_CCU is not set
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB_MUSB_DUAL_ROLE=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_SUNXI=y
-CONFIG_USB_PHY=y
-CONFIG_VMAP_STACK=y
-CONFIG_ZONE_DMA32=y
-CONFIG_SURFACE_PLATFORMS=y
-# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
-# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
-# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
-# CONFIG_PAGE_TABLE_CHECK is not set
-CONFIG_RANDOMIZE_KSTACK_OFFSET=y
-# CONFIG_ARCH_NXP is not set
--- /dev/null
+CONFIG_64BIT=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_BLAKE2S=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DWMAC_SUN8I=y
+CONFIG_EEPROM_AT24=y
+CONFIG_FRAME_POINTER=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MICREL_PHY=y
+# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PHY_SUN50I_USB3=y
+CONFIG_PINCTRL_SUN50I_A100=y
+CONFIG_PINCTRL_SUN50I_A100_R=y
+CONFIG_PINCTRL_SUN50I_A64=y
+CONFIG_PINCTRL_SUN50I_A64_R=y
+CONFIG_PINCTRL_SUN50I_H5=y
+CONFIG_PINCTRL_SUN50I_H6=y
+CONFIG_PINCTRL_SUN50I_H6_R=y
+CONFIG_PINCTRL_SUN50I_H616=y
+CONFIG_PINCTRL_SUN50I_H616_R=y
+# CONFIG_PREEMPT_DYNAMIC is not set
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+# CONFIG_SCHED_CLUSTER is not set
+# CONFIG_SHADOW_CALL_STACK is not set
+# CONFIG_SND_SUN50I_CODEC_ANALOG is not set
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SUN50I_A100_CCU=y
+CONFIG_SUN50I_A100_R_CCU=y
+CONFIG_SUN50I_A64_CCU=y
+CONFIG_SUN50I_DE2_BUS=y
+CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
+CONFIG_SUN50I_H616_CCU=y
+CONFIG_SUN50I_H6_CCU=y
+CONFIG_SUN50I_H6_R_CCU=y
+# CONFIG_SUN6I_RTC_CCU is not set
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB_MUSB_DUAL_ROLE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB_PHY=y
+CONFIG_VMAP_STACK=y
+CONFIG_ZONE_DMA32=y
+CONFIG_SURFACE_PLATFORMS=y
+# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
+# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
+# CONFIG_PAGE_TABLE_CHECK is not set
+CONFIG_RANDOMIZE_KSTACK_OFFSET=y
+# CONFIG_ARCH_NXP is not set
BOARDNAME:=Allwinner A64/H5/H6/H616
CPU_TYPE:=cortex-a53
KERNELNAME:=Image dtbs
+FEATURES+=fpu
\ No newline at end of file
+++ /dev/null
-CONFIG_B53=y
-CONFIG_B53_MDIO_DRIVER=y
-CONFIG_CRYPTO_BLAKE2S_ARM=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_DWMAC_SUN8I=y
-CONFIG_GRO_CELLS=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-# CONFIG_MACH_SUN4I is not set
-# CONFIG_MACH_SUN5I is not set
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MICREL_PHY=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_TAG_BRCM=y
-CONFIG_NET_DSA_TAG_BRCM_COMMON=y
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_RTC_DRV_SUN6I=y
-CONFIG_USB_MUSB_DUAL_ROLE=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_SUNXI=y
-CONFIG_USB_PHY=y
--- /dev/null
+CONFIG_B53=y
+CONFIG_B53_MDIO_DRIVER=y
+CONFIG_CRYPTO_BLAKE2S_ARM=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_DWMAC_SUN8I=y
+CONFIG_GRO_CELLS=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+# CONFIG_MACH_SUN4I is not set
+# CONFIG_MACH_SUN5I is not set
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MICREL_PHY=y
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_SUN20I_D1_CCU=y
+CONFIG_SUN20I_D1_R_CCU=y
+CONFIG_USB_MUSB_DUAL_ROLE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB_PHY=y
BOARDNAME:=Allwinner A20/A3x/H3/R40
CPU_TYPE:=cortex-a7
CPU_SUBTYPE:=neon-vfpv4
+FEATURES+=fpu
+++ /dev/null
-# CONFIG_ARM_LPAE is not set
-CONFIG_CRYPTO_BLAKE2S_ARM=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-# CONFIG_MACH_SUN6I is not set
-# CONFIG_MACH_SUN7I is not set
-# CONFIG_MACH_SUN8I is not set
-# CONFIG_MACH_SUN9I is not set
-CONFIG_PGTABLE_LEVELS=2
-# CONFIG_PHY_SUN9I_USB is not set
-# CONFIG_SPI_SUN6I is not set
-# CONFIG_SUN8I_A83T_CCU is not set
-# CONFIG_SUN8I_THERMAL is not set
--- /dev/null
+# CONFIG_ARM_LPAE is not set
+CONFIG_CRYPTO_BLAKE2S_ARM=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+# CONFIG_MACH_SUN6I is not set
+# CONFIG_MACH_SUN7I is not set
+# CONFIG_MACH_SUN8I is not set
+# CONFIG_MACH_SUN9I is not set
+CONFIG_PGTABLE_LEVELS=2
+# CONFIG_PHY_SUN9I_USB is not set
+# CONFIG_SPI_SUN6I is not set
+# CONFIG_SUN8I_A83T_CCU is not set
+# CONFIG_SUN8I_THERMAL is not set
BOARDNAME:=Allwinner A1x
CPU_TYPE:=cortex-a8
CPU_SUBTYPE:=vfpv3
+FEATURES+=fpu
FAT32_BLOCKS=$(shell echo $$(($(CONFIG_SUNXI_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))
DEVICE_VARS := SUNXI_DTS SUNXI_DTS_DIR
-KERNEL_LOADADDR:=0x40008000
define Build/sunxi-sdcard
rm -f $@.boot
KERNEL := kernel-bin | uImage none
IMAGES := sdcard.img.gz
IMAGE/sdcard.img.gz := sunxi-sdcard | append-metadata | gzip
- SUNXI_DTS_DIR :=
+ SUNXI_DTS_DIR :=allwinner/
SUNXI_DTS = $$(SUNXI_DTS_DIR)$$(SOC)-$(lastword $(subst _, ,$(1)))
endef
# Copyright (C) 2013-2016 OpenWrt.org
# Copyright (C) 2016 Yousong Zhou
+KERNEL_LOADADDR:=0x40008000
+
define Device/sun50i
SUNXI_DTS_DIR := allwinner/
KERNEL_NAME := Image
# Copyright (C) 2013-2019 OpenWrt.org
# Copyright (C) 2016 Yousong Zhou
+KERNEL_LOADADDR:=0x40008000
+
define Device/cubietech_cubieboard2
DEVICE_VENDOR := Cubietech
DEVICE_MODEL := Cubieboard2
endef
TARGET_DEVICES += lemaker_bananapro
+define Device/licheepi_licheepi-zero-dock
+ DEVICE_VENDOR := LicheePi
+ DEVICE_MODEL := Zero with Dock (V3s)
+ DEVICE_PACKAGES:=kmod-rtc-sunxi
+ SOC := sun8i-v3s
+endef
+TARGET_DEVICES += licheepi_licheepi-zero-dock
+
define Device/linksprite_pcduino3
DEVICE_VENDOR := LinkSprite
DEVICE_MODEL := pcDuino3
# Copyright (C) 2013-2016 OpenWrt.org
# Copyright (C) 2016 Yousong Zhou
+KERNEL_LOADADDR:=0x40008000
+
define Device/cubietech_a10-cubieboard
DEVICE_VENDOR := Cubietech
DEVICE_MODEL := Cubieboard
DEVICE_PACKAGES:=kmod-rtl8192cu
SUPPORTED_DEVICES:=olimex,a13-olinuxino
SOC := sun5i-a13
- SUNXI_DTS := sun5i-a13-olinuxino
+ SUNXI_DTS := $$(SUNXI_DTS_DIR)sun5i-a13-olinuxino
endef
TARGET_DEVICES += olimex_a13-olimex-som
+++ /dev/null
-From 28a1a6474c5053bae01bd29946b4d5ede539176b Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 31 Oct 2022 11:13:52 +0000
-Subject: [PATCH] dt-bindings: usb: Add H616 compatible string
-
-The Allwinner H616 contains four fully OHCI/EHCI compatible USB host
-controllers, so just add their compatible strings to the list of
-generic OHCI/EHCI controllers.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20221031111358.3387297-2-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
- Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
-+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
-@@ -30,6 +30,7 @@ properties:
- - allwinner,sun4i-a10-ehci
- - allwinner,sun50i-a64-ehci
- - allwinner,sun50i-h6-ehci
-+ - allwinner,sun50i-h616-ehci
- - allwinner,sun5i-a13-ehci
- - allwinner,sun6i-a31-ehci
- - allwinner,sun7i-a20-ehci
---- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
-+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
-@@ -20,6 +20,7 @@ properties:
- - allwinner,sun4i-a10-ohci
- - allwinner,sun50i-a64-ohci
- - allwinner,sun50i-h6-ohci
-+ - allwinner,sun50i-h616-ohci
- - allwinner,sun5i-a13-ohci
- - allwinner,sun6i-a31-ohci
- - allwinner,sun7i-a20-ohci
+++ /dev/null
-From 6964affe65066651eca21e97247d3b7cac5153dc Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 31 Oct 2022 11:13:53 +0000
-Subject: [PATCH] dt-bindings: phy: Add special clock for Allwinner H616 PHY
-
-The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
-some resources from port 2's PHY and HCI IP. In particular the PMU clock
-for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
-register of port 2. To allow each USB port to be controlled
-independently of port 2, we need a handle to that particular PMU clock
-in the *PHY* node, as the HCI and PHY part might be handled by separate
-drivers.
-
-Add that clock to the requirements of the H616 PHY binding, so that a
-PHY driver can apply the quirk in isolation, without requiring help from
-port 2's HCI driver.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20221031111358.3387297-3-andre.przywara@arm.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
---- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
-+++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
-@@ -36,18 +36,22 @@ properties:
- - const: pmu3
-
- clocks:
-+ minItems: 4
- items:
- - description: USB OTG PHY bus clock
- - description: USB Host 0 PHY bus clock
- - description: USB Host 1 PHY bus clock
- - description: USB Host 2 PHY bus clock
-+ - description: PMU clock for host port 2
-
- clock-names:
-+ minItems: 4
- items:
- - const: usb0_phy
- - const: usb1_phy
- - const: usb2_phy
- - const: usb3_phy
-+ - const: pmu2_clk
-
- resets:
- items:
-@@ -96,6 +100,28 @@ required:
- - resets
- - reset-names
-
-+allOf:
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ enum:
-+ - allwinner,sun50i-h616-usb-phy
-+ then:
-+ properties:
-+ clocks:
-+ minItems: 5
-+
-+ clock-names:
-+ minItems: 5
-+ else:
-+ properties:
-+ clocks:
-+ maxItems: 4
-+
-+ clock-names:
-+ maxItems: 4
-+
- additionalProperties: false
-
- examples:
+++ /dev/null
-From f40cf244c3feb4e1a442f8029b691add2c65b3ab Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 31 Oct 2022 11:13:56 +0000
-Subject: [PATCH] arm64: dts: allwinner: h616: Add USB nodes
-
-Add the nodes for the MUSB and the four USB host controllers to the SoC
-.dtsi, along with the PHY node needed to bind all of them together.
-
-EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires
-some quirks (handled in the driver).
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20221031111358.3387297-6-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
- 1 file changed, 160 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-@@ -504,6 +504,166 @@
- };
- };
-
-+ usbotg: usb@5100000 {
-+ compatible = "allwinner,sun50i-h616-musb",
-+ "allwinner,sun8i-h3-musb";
-+ reg = <0x05100000 0x0400>;
-+ clocks = <&ccu CLK_BUS_OTG>;
-+ resets = <&ccu RST_BUS_OTG>;
-+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "mc";
-+ phys = <&usbphy 0>;
-+ phy-names = "usb";
-+ extcon = <&usbphy 0>;
-+ status = "disabled";
-+ };
-+
-+ usbphy: phy@5100400 {
-+ compatible = "allwinner,sun50i-h616-usb-phy";
-+ reg = <0x05100400 0x24>,
-+ <0x05101800 0x14>,
-+ <0x05200800 0x14>,
-+ <0x05310800 0x14>,
-+ <0x05311800 0x14>;
-+ reg-names = "phy_ctrl",
-+ "pmu0",
-+ "pmu1",
-+ "pmu2",
-+ "pmu3";
-+ clocks = <&ccu CLK_USB_PHY0>,
-+ <&ccu CLK_USB_PHY1>,
-+ <&ccu CLK_USB_PHY2>,
-+ <&ccu CLK_USB_PHY3>,
-+ <&ccu CLK_BUS_EHCI2>;
-+ clock-names = "usb0_phy",
-+ "usb1_phy",
-+ "usb2_phy",
-+ "usb3_phy",
-+ "pmu2_clk";
-+ resets = <&ccu RST_USB_PHY0>,
-+ <&ccu RST_USB_PHY1>,
-+ <&ccu RST_USB_PHY2>,
-+ <&ccu RST_USB_PHY3>;
-+ reset-names = "usb0_reset",
-+ "usb1_reset",
-+ "usb2_reset",
-+ "usb3_reset";
-+ status = "disabled";
-+ #phy-cells = <1>;
-+ };
-+
-+ ehci0: usb@5101000 {
-+ compatible = "allwinner,sun50i-h616-ehci",
-+ "generic-ehci";
-+ reg = <0x05101000 0x100>;
-+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI0>,
-+ <&ccu CLK_BUS_EHCI0>,
-+ <&ccu CLK_USB_OHCI0>;
-+ resets = <&ccu RST_BUS_OHCI0>,
-+ <&ccu RST_BUS_EHCI0>;
-+ phys = <&usbphy 0>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci0: usb@5101400 {
-+ compatible = "allwinner,sun50i-h616-ohci",
-+ "generic-ohci";
-+ reg = <0x05101400 0x100>;
-+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI0>,
-+ <&ccu CLK_USB_OHCI0>;
-+ resets = <&ccu RST_BUS_OHCI0>;
-+ phys = <&usbphy 0>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ehci1: usb@5200000 {
-+ compatible = "allwinner,sun50i-h616-ehci",
-+ "generic-ehci";
-+ reg = <0x05200000 0x100>;
-+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI1>,
-+ <&ccu CLK_BUS_EHCI1>,
-+ <&ccu CLK_USB_OHCI1>;
-+ resets = <&ccu RST_BUS_OHCI1>,
-+ <&ccu RST_BUS_EHCI1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci1: usb@5200400 {
-+ compatible = "allwinner,sun50i-h616-ohci",
-+ "generic-ohci";
-+ reg = <0x05200400 0x100>;
-+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI1>,
-+ <&ccu CLK_USB_OHCI1>;
-+ resets = <&ccu RST_BUS_OHCI1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ehci2: usb@5310000 {
-+ compatible = "allwinner,sun50i-h616-ehci",
-+ "generic-ehci";
-+ reg = <0x05310000 0x100>;
-+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI2>,
-+ <&ccu CLK_BUS_EHCI2>,
-+ <&ccu CLK_USB_OHCI2>;
-+ resets = <&ccu RST_BUS_OHCI2>,
-+ <&ccu RST_BUS_EHCI2>;
-+ phys = <&usbphy 2>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci2: usb@5310400 {
-+ compatible = "allwinner,sun50i-h616-ohci",
-+ "generic-ohci";
-+ reg = <0x05310400 0x100>;
-+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI2>,
-+ <&ccu CLK_USB_OHCI2>;
-+ resets = <&ccu RST_BUS_OHCI2>;
-+ phys = <&usbphy 2>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ehci3: usb@5311000 {
-+ compatible = "allwinner,sun50i-h616-ehci",
-+ "generic-ehci";
-+ reg = <0x05311000 0x100>;
-+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI3>,
-+ <&ccu CLK_BUS_EHCI3>,
-+ <&ccu CLK_USB_OHCI3>;
-+ resets = <&ccu RST_BUS_OHCI3>,
-+ <&ccu RST_BUS_EHCI3>;
-+ phys = <&usbphy 3>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci3: usb@5311400 {
-+ compatible = "allwinner,sun50i-h616-ohci",
-+ "generic-ohci";
-+ reg = <0x05311400 0x100>;
-+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI3>,
-+ <&ccu CLK_USB_OHCI3>;
-+ resets = <&ccu RST_BUS_OHCI3>;
-+ phys = <&usbphy 3>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
- rtc: rtc@7000000 {
- compatible = "allwinner,sun50i-h616-rtc";
- reg = <0x07000000 0x400>;
+++ /dev/null
-From db5f028309ede13767e2ba356c1975ac37a4fd6c Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 31 Oct 2022 11:13:57 +0000
-Subject: [PATCH] arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
-
-The OrangePi Zero 2 has one USB-A host port, VBUS is provided by
-a GPIO controlled regulator.
-The USB-C port is meant to power the board, but is also connected to
-the USB 0 port, which we configure as an MUSB peripheral.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20221031111358.3387297-7-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- .../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++++++++++++++++
- 1 file changed, 41 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-@@ -49,8 +49,24 @@
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-+
-+ reg_usb1_vbus: regulator-usb1-vbus {
-+ compatible = "regulator-fixed";
-+ regulator-name = "usb1-vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <®_vcc5v>;
-+ enable-active-high;
-+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
-+ };
-+};
-+
-+&ehci1 {
-+ status = "okay";
- };
-
-+/* USB 2 & 3 are on headers only. */
-+
- &emac0 {
- pinctrl-names = "default";
- pinctrl-0 = <&ext_rgmii_pins>;
-@@ -76,6 +92,10 @@
- status = "okay";
- };
-
-+&ohci1 {
-+ status = "okay";
-+};
-+
- &r_rsb {
- status = "okay";
-
-@@ -211,3 +231,24 @@
- pinctrl-0 = <&uart0_ph_pins>;
- status = "okay";
- };
-+
-+&usbotg {
-+ /*
-+ * PHY0 pins are connected to a USB-C socket, but a role switch
-+ * is not implemented: both CC pins are pulled to GND.
-+ * The VBUS pins power the device, so a fixed peripheral mode
-+ * is the best choice.
-+ * The board can be powered via GPIOs, in this case port0 *can*
-+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
-+ * then provided by the GPIOs. Any user of this setup would
-+ * need to adjust the DT accordingly: dr_mode set to "host",
-+ * enabling OHCI0 and EHCI0.
-+ */
-+ dr_mode = "peripheral";
-+ status = "okay";
-+};
-+
-+&usbphy {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ status = "okay";
-+};
+++ /dev/null
-From 322bf103204b8f786547acbeed85569254e7088f Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Fri, 4 Aug 2023 18:08:54 +0100
-Subject: [PATCH] arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT
-
-The Orange Pi Zero 2 got a successor (Zero 3), which shares quite some
-DT nodes with the Zero 2, but comes with a different PMIC.
-
-Move the common parts (except the PMIC) into a new shared file, and
-include that from the existing board .dts file.
-
-No functional change, the generated DTB is the same, except for some
-phandle numbering differences.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20230804170856.1237202-2-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- .../allwinner/sun50i-h616-orangepi-zero.dtsi | 134 ++++++++++++++++++
- .../allwinner/sun50i-h616-orangepi-zero2.dts | 119 +---------------
- 2 files changed, 135 insertions(+), 118 deletions(-)
- create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
-
---- /dev/null
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
-@@ -0,0 +1,134 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+/*
-+ * Copyright (C) 2020 Arm Ltd.
-+ *
-+ * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3.
-+ * Excludes PMIC nodes and properties, since they are different between the two.
-+ */
-+
-+#include "sun50i-h616.dtsi"
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include <dt-bindings/leds/common.h>
-+
-+/ {
-+ aliases {
-+ ethernet0 = &emac0;
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ led-0 {
-+ function = LED_FUNCTION_POWER;
-+ color = <LED_COLOR_ID_RED>;
-+ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
-+ default-state = "on";
-+ };
-+
-+ led-1 {
-+ function = LED_FUNCTION_STATUS;
-+ color = <LED_COLOR_ID_GREEN>;
-+ gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
-+ };
-+ };
-+
-+ reg_vcc5v: vcc5v {
-+ /* board wide 5V supply directly from the USB-C socket */
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc-5v";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ regulator-always-on;
-+ };
-+
-+ reg_usb1_vbus: regulator-usb1-vbus {
-+ compatible = "regulator-fixed";
-+ regulator-name = "usb1-vbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <®_vcc5v>;
-+ enable-active-high;
-+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
-+ };
-+};
-+
-+&ehci1 {
-+ status = "okay";
-+};
-+
-+/* USB 2 & 3 are on headers only. */
-+
-+&emac0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&ext_rgmii_pins>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&ext_rgmii_phy>;
-+ allwinner,rx-delay-ps = <3100>;
-+ allwinner,tx-delay-ps = <700>;
-+ status = "okay";
-+};
-+
-+&mdio0 {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ };
-+};
-+
-+&mmc0 {
-+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-+ bus-width = <4>;
-+ status = "okay";
-+};
-+
-+&ohci1 {
-+ status = "okay";
-+};
-+
-+&spi0 {
-+ status = "okay";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
-+
-+ flash@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <40000000>;
-+ };
-+};
-+
-+&uart0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_ph_pins>;
-+ status = "okay";
-+};
-+
-+&usbotg {
-+ /*
-+ * PHY0 pins are connected to a USB-C socket, but a role switch
-+ * is not implemented: both CC pins are pulled to GND.
-+ * The VBUS pins power the device, so a fixed peripheral mode
-+ * is the best choice.
-+ * The board can be powered via GPIOs, in this case port0 *can*
-+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
-+ * then provided by the GPIOs. Any user of this setup would
-+ * need to adjust the DT accordingly: dr_mode set to "host",
-+ * enabling OHCI0 and EHCI0.
-+ */
-+ dr_mode = "peripheral";
-+ status = "okay";
-+};
-+
-+&usbphy {
-+ usb1_vbus-supply = <®_usb1_vbus>;
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-@@ -5,95 +5,19 @@
-
- /dts-v1/;
-
--#include "sun50i-h616.dtsi"
--
--#include <dt-bindings/gpio/gpio.h>
--#include <dt-bindings/interrupt-controller/arm-gic.h>
--#include <dt-bindings/leds/common.h>
-+#include "sun50i-h616-orangepi-zero.dtsi"
-
- / {
- model = "OrangePi Zero2";
- compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
--
-- aliases {
-- ethernet0 = &emac0;
-- serial0 = &uart0;
-- };
--
-- chosen {
-- stdout-path = "serial0:115200n8";
-- };
--
-- leds {
-- compatible = "gpio-leds";
--
-- led-0 {
-- function = LED_FUNCTION_POWER;
-- color = <LED_COLOR_ID_RED>;
-- gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
-- default-state = "on";
-- };
--
-- led-1 {
-- function = LED_FUNCTION_STATUS;
-- color = <LED_COLOR_ID_GREEN>;
-- gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
-- };
-- };
--
-- reg_vcc5v: vcc5v {
-- /* board wide 5V supply directly from the USB-C socket */
-- compatible = "regulator-fixed";
-- regulator-name = "vcc-5v";
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- regulator-always-on;
-- };
--
-- reg_usb1_vbus: regulator-usb1-vbus {
-- compatible = "regulator-fixed";
-- regulator-name = "usb1-vbus";
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <®_vcc5v>;
-- enable-active-high;
-- gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
-- };
--};
--
--&ehci1 {
-- status = "okay";
- };
-
--/* USB 2 & 3 are on headers only. */
--
- &emac0 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&ext_rgmii_pins>;
-- phy-mode = "rgmii";
-- phy-handle = <&ext_rgmii_phy>;
- phy-supply = <®_dcdce>;
-- allwinner,rx-delay-ps = <3100>;
-- allwinner,tx-delay-ps = <700>;
-- status = "okay";
--};
--
--&mdio0 {
-- ext_rgmii_phy: ethernet-phy@1 {
-- compatible = "ethernet-phy-ieee802.3-c22";
-- reg = <1>;
-- };
- };
-
- &mmc0 {
- vmmc-supply = <®_dcdce>;
-- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-- bus-width = <4>;
-- status = "okay";
--};
--
--&ohci1 {
-- status = "okay";
- };
-
- &r_rsb {
-@@ -211,44 +135,3 @@
- vcc-ph-supply = <®_aldo1>;
- vcc-pi-supply = <®_aldo1>;
- };
--
--&spi0 {
-- status = "okay";
-- pinctrl-names = "default";
-- pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
--
-- flash@0 {
-- #address-cells = <1>;
-- #size-cells = <1>;
-- compatible = "jedec,spi-nor";
-- reg = <0>;
-- spi-max-frequency = <40000000>;
-- };
--};
--
--&uart0 {
-- pinctrl-names = "default";
-- pinctrl-0 = <&uart0_ph_pins>;
-- status = "okay";
--};
--
--&usbotg {
-- /*
-- * PHY0 pins are connected to a USB-C socket, but a role switch
-- * is not implemented: both CC pins are pulled to GND.
-- * The VBUS pins power the device, so a fixed peripheral mode
-- * is the best choice.
-- * The board can be powered via GPIOs, in this case port0 *can*
-- * act as a host (with a cable/adapter ignoring CC), as VBUS is
-- * then provided by the GPIOs. Any user of this setup would
-- * need to adjust the DT accordingly: dr_mode set to "host",
-- * enabling OHCI0 and EHCI0.
-- */
-- dr_mode = "peripheral";
-- status = "okay";
--};
--
--&usbphy {
-- usb1_vbus-supply = <®_usb1_vbus>;
-- status = "okay";
--};
+++ /dev/null
-From f1b3ddb3ecc2eec1f912383e01156c226daacfab Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Fri, 4 Aug 2023 18:08:56 +0100
-Subject: [PATCH] arm64: dts: allwinner: h616: Add OrangePi Zero 3 board
- support
-
-The OrangePi Zero 3 is a development board based on the Allwinner H618 SoC,
-which seems to be just an H616 with more L2 cache. The board itself is a
-slightly updated version of the Orange Pi Zero 2. It features:
-- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
-- 1/1.5/2/4 GiB LPDDR4 DRAM SKUs (only up to 1GB on the Zero2)
-- AXP313a PMIC (more capable AXP305 on the Zero2)
-- Raspberry-Pi-1 compatible GPIO header
-- extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
-- 1 USB 2.0 host port
-- 1 USB 2.0 type C port (power supply + OTG)
-- MicroSD slot
-- on-board 16MiB bootable SPI NOR flash (only 2MB on the Zero2)
-- 1Gbps Ethernet port (via Motorcomm YT8531 PHY) (RTL8211 on the Zero2)
-- micro-HDMI port
-- (yet) unsupported Allwinner WiFi/BT chip
-
-Add the devicetree file describing the currently supported features,
-namely LEDs, SD card, PMIC, SPI flash, USB. Ethernet seems unstable at
-the moment, though the basic functionality works.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20230804170856.1237202-4-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- arch/arm64/boot/dts/allwinner/Makefile | 1 +
- .../allwinner/sun50i-h618-orangepi-zero3.dts | 94 +++++++++++++++++++
- 2 files changed, 95 insertions(+)
- create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
-
---- a/arch/arm64/boot/dts/allwinner/Makefile
-+++ b/arch/arm64/boot/dts/allwinner/Makefile
-@@ -40,3 +40,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-ta
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
-@@ -0,0 +1,94 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+/*
-+ * Copyright (C) 2023 Arm Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "sun50i-h616-orangepi-zero.dtsi"
-+
-+/ {
-+ model = "OrangePi Zero3";
-+ compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
-+};
-+
-+&emac0 {
-+ phy-supply = <®_dldo1>;
-+};
-+
-+&ext_rgmii_phy {
-+ motorcomm,clk-out-frequency-hz = <125000000>;
-+};
-+
-+&mmc0 {
-+ /*
-+ * The schematic shows the card detect pin wired up to PF6, via an
-+ * inverter, but it just doesn't work.
-+ */
-+ broken-cd;
-+ vmmc-supply = <®_dldo1>;
-+};
-+
-+&r_i2c {
-+ status = "okay";
-+
-+ axp313: pmic@36 {
-+ compatible = "x-powers,axp313a";
-+ reg = <0x36>;
-+ #interrupt-cells = <1>;
-+ interrupt-controller;
-+ interrupt-parent = <&pio>;
-+ interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */
-+
-+ vin1-supply = <®_vcc5v>;
-+ vin2-supply = <®_vcc5v>;
-+ vin3-supply = <®_vcc5v>;
-+
-+ regulators {
-+ /* Supplies VCC-PLL, so needs to be always on. */
-+ reg_aldo1: aldo1 {
-+ regulator-always-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-name = "vcc1v8";
-+ };
-+
-+ /* Supplies VCC-IO, so needs to be always on. */
-+ reg_dldo1: dldo1 {
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-name = "vcc3v3";
-+ };
-+
-+ reg_dcdc1: dcdc1 {
-+ regulator-always-on;
-+ regulator-min-microvolt = <810000>;
-+ regulator-max-microvolt = <990000>;
-+ regulator-name = "vdd-gpu-sys";
-+ };
-+
-+ reg_dcdc2: dcdc2 {
-+ regulator-always-on;
-+ regulator-min-microvolt = <810000>;
-+ regulator-max-microvolt = <1100000>;
-+ regulator-name = "vdd-cpu";
-+ };
-+
-+ reg_dcdc3: dcdc3 {
-+ regulator-always-on;
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1100000>;
-+ regulator-name = "vdd-dram";
-+ };
-+ };
-+ };
-+};
-+
-+&pio {
-+ vcc-pc-supply = <®_dldo1>;
-+ vcc-pf-supply = <®_dldo1>;
-+ vcc-pg-supply = <®_aldo1>;
-+ vcc-ph-supply = <®_dldo1>;
-+ vcc-pi-supply = <®_dldo1>;
-+};
+++ /dev/null
-From b9622937d95809ef89904583191571a9fa326402 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Sun, 29 Oct 2023 15:40:09 +0800
-Subject: [PATCH] arm64: dts: allwinner: h616: update emac for Orange Pi Zero 3
-
-The current emac setting is not suitable for Orange Pi Zero 3,
-move it back to Orange Pi Zero 2 DT. Also update phy mode and
-delay values for emac on Orange Pi Zero 3.
-With these changes, Ethernet now looks stable.
-
-Fixes: 322bf103204b ("arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT")
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20231029074009.7820-2-amadeus@jmu.edu.cn
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 3 ---
- arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 3 +++
- arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts | 2 ++
- 3 files changed, 5 insertions(+), 3 deletions(-)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
-@@ -68,10 +68,7 @@
- &emac0 {
- pinctrl-names = "default";
- pinctrl-0 = <&ext_rgmii_pins>;
-- phy-mode = "rgmii";
- phy-handle = <&ext_rgmii_phy>;
-- allwinner,rx-delay-ps = <3100>;
-- allwinner,tx-delay-ps = <700>;
- status = "okay";
- };
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
-@@ -13,6 +13,9 @@
- };
-
- &emac0 {
-+ allwinner,rx-delay-ps = <3100>;
-+ allwinner,tx-delay-ps = <700>;
-+ phy-mode = "rgmii";
- phy-supply = <®_dcdce>;
- };
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
-@@ -13,6 +13,8 @@
- };
-
- &emac0 {
-+ allwinner,tx-delay-ps = <700>;
-+ phy-mode = "rgmii-rxid";
- phy-supply = <®_dldo1>;
- };
-
+++ /dev/null
-From 951992797378a2177946400438f4d23c9fceae5b Mon Sep 17 00:00:00 2001
-From: Martin Botka <martin.botka@somainline.org>
-Date: Tue, 12 Sep 2023 14:25:13 +0200
-Subject: [PATCH] arm64: dts: allwinner: h616: Add SID controller node
-
-Add node for the H616 SID controller
-
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20230912-sid-h616-v3-2-ee18e1c5bbb5@somainline.org
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-@@ -133,6 +133,13 @@
- #reset-cells = <1>;
- };
-
-+ sid: efuse@3006000 {
-+ compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
-+ reg = <0x03006000 0x1000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ };
-+
- watchdog: watchdog@30090a0 {
- compatible = "allwinner,sun50i-h616-wdt",
- "allwinner,sun6i-a31-wdt";
+++ /dev/null
-From 898d96c5464b69af44f6407c5de81ebc349d574b Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 19 Feb 2024 15:36:33 +0000
-Subject: [PATCH] soc: sunxi: sram: export register 0 for THS on H616
-
-The Allwinner H616 SoC contains a mysterious bit at register offset 0x0
-in the SRAM control block. If bit 16 is set (the reset value), the
-temperature readings of the THS are way off, leading to reports about
-200C, at normal ambient temperatures. Clearing this bits brings the
-reported values down to the expected values.
-The BSP code clears this bit in firmware (U-Boot), and has an explicit
-comment about this, but offers no real explanation.
-
-Experiments in U-Boot show that register 0x0 has no effect on the SRAM C
-visibility: all tested bit settings still allow full read and write
-access by the CPU to the whole of SRAM C. Only bit 24 of the register at
-offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling
-the THS switch functionality as an SRAM region would not reflect reality.
-
-Since we should not rely on firmware settings, allow other code (the THS
-driver) to access this register, by exporting it through the already
-existing regmap. This mimics what we already do for the LDO control and
-the EMAC register.
-
-To avoid concurrent accesses to the same register at the same time, by
-the SRAM switch code and the regmap code, use the same lock to protect
-the access. The regmap subsystem allows to use an existing lock, so we
-just need to hook in there.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-2-andre.przywara@arm.com
----
- drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/drivers/soc/sunxi/sunxi_sram.c
-+++ b/drivers/soc/sunxi/sunxi_sram.c
-@@ -284,6 +284,7 @@ EXPORT_SYMBOL(sunxi_sram_release);
- struct sunxi_sramc_variant {
- int num_emac_clocks;
- bool has_ldo_ctrl;
-+ bool has_ths_offset;
- };
-
- static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
-@@ -305,8 +306,10 @@ static const struct sunxi_sramc_variant
-
- static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
- .num_emac_clocks = 2,
-+ .has_ths_offset = true,
- };
-
-+#define SUNXI_SRAM_THS_OFFSET_REG 0x0
- #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
- #define SUNXI_SYS_LDO_CTRL_REG 0x150
-
-@@ -315,6 +318,8 @@ static bool sunxi_sram_regmap_accessible
- {
- const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
-
-+ if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset)
-+ return true;
- if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
- reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
- return true;
-@@ -324,6 +329,20 @@ static bool sunxi_sram_regmap_accessible
- return false;
- }
-
-+static void sunxi_sram_lock(void *_lock)
-+{
-+ spinlock_t *lock = _lock;
-+
-+ spin_lock(lock);
-+}
-+
-+static void sunxi_sram_unlock(void *_lock)
-+{
-+ spinlock_t *lock = _lock;
-+
-+ spin_unlock(lock);
-+}
-+
- static struct regmap_config sunxi_sram_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
-@@ -333,6 +352,9 @@ static struct regmap_config sunxi_sram_r
- /* other devices have no business accessing other registers */
- .readable_reg = sunxi_sram_regmap_accessible_reg,
- .writeable_reg = sunxi_sram_regmap_accessible_reg,
-+ .lock = sunxi_sram_lock,
-+ .unlock = sunxi_sram_unlock,
-+ .lock_arg = &sram_lock,
- };
-
- static int __init sunxi_sram_probe(struct platform_device *pdev)
+++ /dev/null
-From ebbf19e36d021f253425344b4d4b987f3b7d9be5 Mon Sep 17 00:00:00 2001
-From: Maxim Kiselev <bigunclemax@gmail.com>
-Date: Mon, 18 Dec 2023 00:06:23 +0300
-Subject: [PATCH] thermal/drivers/sun8i: Add D1/T113s THS controller support
-
-This patch adds a thermal sensor controller support for the D1/T113s,
-which is similar to the one on H6, but with only one sensor and
-different scale and offset values.
-
-Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Reviewed-by: Andre Przywara <andre.przywara@arm.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20231217210629.131486-3-bigunclemax@gmail.com
----
- drivers/thermal/sun8i_thermal.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -610,6 +610,18 @@ static const struct ths_thermal_chip sun
- .calc_temp = sun8i_ths_calc_temp,
- };
-
-+static const struct ths_thermal_chip sun20i_d1_ths = {
-+ .sensor_num = 1,
-+ .has_bus_clk_reset = true,
-+ .offset = 188552,
-+ .scale = 673,
-+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
-+ .calibrate = sun50i_h6_ths_calibrate,
-+ .init = sun50i_h6_thermal_init,
-+ .irq_ack = sun50i_h6_irq_ack,
-+ .calc_temp = sun8i_ths_calc_temp,
-+};
-+
- static const struct of_device_id of_ths_match[] = {
- { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
- { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
-@@ -618,6 +630,7 @@ static const struct of_device_id of_ths_
- { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
- { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
- { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
-+ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
- { /* sentinel */ },
- };
- MODULE_DEVICE_TABLE(of, of_ths_match);
+++ /dev/null
-From 14f118aa50fe7c7c7330f56d007ecacca487cea8 Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 19 Feb 2024 15:36:35 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Explain unknown H6 register value
-
-So far we were ORing in some "unknown" value into the THS control
-register on the Allwinner H6. This part of the register is not explained
-in the H6 manual, but the H616 manual details those bits, and on closer
-inspection the THS IP blocks in both SoCs seem very close:
-- The BSP code for both SoCs writes the same values into THS_CTRL.
-- The reset values of at least the first three registers are the same.
-
-Replace the "unknown" value with its proper meaning: "acquire time",
-most probably the sample part of the sample & hold circuit of the ADC,
-according to its explanation in the H616 manual.
-
-No functional change, just a macro rename and adjustment.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-4-andre.przywara@arm.com
----
- drivers/thermal/sun8i_thermal.c | 29 ++++++++++++++++-------------
- 1 file changed, 16 insertions(+), 13 deletions(-)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -50,7 +50,8 @@
- #define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16)
- #define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8)
-
--#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16)
-+#define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & ((x) - 1))
-+#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x) ((GENMASK(15, 0) & ((x) - 1)) << 16)
- #define SUN50I_THS_FILTER_EN BIT(2)
- #define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
- #define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12)
-@@ -410,25 +411,27 @@ static int sun8i_h3_thermal_init(struct
- return 0;
- }
-
--/*
-- * Without this undocumented value, the returned temperatures would
-- * be higher than real ones by about 20C.
-- */
--#define SUN50I_H6_CTRL0_UNK 0x0000002f
--
- static int sun50i_h6_thermal_init(struct ths_device *tmdev)
- {
- int val;
-
- /*
-- * T_acq = 20us
-- * clkin = 24MHz
-- *
-- * x = T_acq * clkin - 1
-- * = 479
-+ * The manual recommends an overall sample frequency of 50 KHz (20us,
-+ * 480 cycles at 24 MHz), which provides plenty of time for both the
-+ * acquisition time (>24 cycles) and the actual conversion time
-+ * (>14 cycles).
-+ * The lower half of the CTRL register holds the "acquire time", in
-+ * clock cycles, which the manual recommends to be 2us:
-+ * 24MHz * 2us = 48 cycles.
-+ * The high half of THS_CTRL encodes the sample frequency, in clock
-+ * cycles: 24MHz * 20us = 480 cycles.
-+ * This is explained in the H616 manual, but apparently wrongly
-+ * described in the H6 manual, although the BSP code does the same
-+ * for both SoCs.
- */
- regmap_write(tmdev->regmap, SUN50I_THS_CTRL0,
-- SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479));
-+ SUN50I_THS_CTRL0_T_ACQ(48) |
-+ SUN50I_THS_CTRL0_T_SAMPLE_PER(480));
- /* average over 4 samples */
- regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC,
- SUN50I_THS_FILTER_EN |
+++ /dev/null
-From 6c04a419a4c5fb18edefc44dd676fb95c7f6c55d Mon Sep 17 00:00:00 2001
-From: Maksim Kiselev <bigunclemax@gmail.com>
-Date: Mon, 19 Feb 2024 15:36:36 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Extend H6 calibration to support 4
- sensors
-
-The H616 SoC resembles the H6 thermal sensor controller, with a few
-changes like four sensors.
-
-Extend sun50i_h6_ths_calibrate() function to support calibration of
-these sensors.
-
-Co-developed-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
-Reviewed-by: Andre Przywara <andre.przywara@arm.com>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-5-andre.przywara@arm.com
----
- drivers/thermal/sun8i_thermal.c | 28 ++++++++++++++++++++--------
- 1 file changed, 20 insertions(+), 8 deletions(-)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -224,16 +224,21 @@ static int sun50i_h6_ths_calibrate(struc
- struct device *dev = tmdev->dev;
- int i, ft_temp;
-
-- if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num)
-+ if (!caldata[0])
- return -EINVAL;
-
- /*
- * efuse layout:
- *
-- * 0 11 16 32
-- * +-------+-------+-------+
-- * |temp| |sensor0|sensor1|
-- * +-------+-------+-------+
-+ * 0 11 16 27 32 43 48 57
-+ * +----------+-----------+-----------+-----------+
-+ * | temp | |sensor0| |sensor1| |sensor2| |
-+ * +----------+-----------+-----------+-----------+
-+ * ^ ^ ^
-+ * | | |
-+ * | | sensor3[11:8]
-+ * | sensor3[7:4]
-+ * sensor3[3:0]
- *
- * The calibration data on the H6 is the ambient temperature and
- * sensor values that are filled during the factory test stage.
-@@ -246,9 +251,16 @@ static int sun50i_h6_ths_calibrate(struc
- ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
-
- for (i = 0; i < tmdev->chip->sensor_num; i++) {
-- int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
-- int cdata, offset;
-- int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
-+ int sensor_reg, sensor_temp, cdata, offset;
-+
-+ if (i == 3)
-+ sensor_reg = (caldata[1] >> 12)
-+ | ((caldata[2] >> 12) << 4)
-+ | ((caldata[3] >> 12) << 8);
-+ else
-+ sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
-+
-+ sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
-
- /*
- * Calibration data is CALIBRATE_DEFAULT - (calculated
+++ /dev/null
-From f8b54d1120b81ed57bed96cc8e814ba08886d1e5 Mon Sep 17 00:00:00 2001
-From: Andre Przywara <andre.przywara@arm.com>
-Date: Mon, 19 Feb 2024 15:36:37 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Add SRAM register access code
-
-The Allwinner H616 SoC needs to clear a bit in one register in the SRAM
-controller, to report reasonable temperature values. On reset, bit 16 in
-register 0x3000000 is set, which leads to the driver reporting
-temperatures around 200C. Clearing this bit brings the values down to the
-expected range. The BSP code does a one-time write in U-Boot, with a
-comment just mentioning the effect on the THS, but offering no further
-explanation.
-
-To not rely on firmware to set things up for us, add code that queries
-the SRAM controller device via a DT phandle link, then clear just this
-single bit.
-
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-6-andre.przywara@arm.com
----
- drivers/thermal/sun8i_thermal.c | 51 +++++++++++++++++++++++++++++++++
- 1 file changed, 51 insertions(+)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -15,6 +15,7 @@
- #include <linux/module.h>
- #include <linux/nvmem-consumer.h>
- #include <linux/of_device.h>
-+#include <linux/of_platform.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
- #include <linux/reset.h>
-@@ -68,6 +69,7 @@ struct tsensor {
- struct ths_thermal_chip {
- bool has_mod_clk;
- bool has_bus_clk_reset;
-+ bool needs_sram;
- int sensor_num;
- int offset;
- int scale;
-@@ -85,12 +87,16 @@ struct ths_device {
- const struct ths_thermal_chip *chip;
- struct device *dev;
- struct regmap *regmap;
-+ struct regmap_field *sram_regmap_field;
- struct reset_control *reset;
- struct clk *bus_clk;
- struct clk *mod_clk;
- struct tsensor sensor[MAX_SENSOR_NUM];
- };
-
-+/* The H616 needs to have a bit 16 in the SRAM control register cleared. */
-+static const struct reg_field sun8i_ths_sram_reg_field = REG_FIELD(0x0, 16, 16);
-+
- /* Temp Unit: millidegree Celsius */
- static int sun8i_ths_calc_temp(struct ths_device *tmdev,
- int id, int reg)
-@@ -337,6 +343,34 @@ static void sun8i_ths_reset_control_asse
- reset_control_assert(data);
- }
-
-+static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node)
-+{
-+ struct device_node *sram_node;
-+ struct platform_device *sram_pdev;
-+ struct regmap *regmap = NULL;
-+
-+ sram_node = of_parse_phandle(node, "allwinner,sram", 0);
-+ if (!sram_node)
-+ return ERR_PTR(-ENODEV);
-+
-+ sram_pdev = of_find_device_by_node(sram_node);
-+ if (!sram_pdev) {
-+ /* platform device might not be probed yet */
-+ regmap = ERR_PTR(-EPROBE_DEFER);
-+ goto out_put_node;
-+ }
-+
-+ /* If no regmap is found then the other device driver is at fault */
-+ regmap = dev_get_regmap(&sram_pdev->dev, NULL);
-+ if (!regmap)
-+ regmap = ERR_PTR(-EINVAL);
-+
-+ platform_device_put(sram_pdev);
-+out_put_node:
-+ of_node_put(sram_node);
-+ return regmap;
-+}
-+
- static int sun8i_ths_resource_init(struct ths_device *tmdev)
- {
- struct device *dev = tmdev->dev;
-@@ -381,6 +415,19 @@ static int sun8i_ths_resource_init(struc
- if (ret)
- return ret;
-
-+ if (tmdev->chip->needs_sram) {
-+ struct regmap *regmap;
-+
-+ regmap = sun8i_ths_get_sram_regmap(dev->of_node);
-+ if (IS_ERR(regmap))
-+ return PTR_ERR(regmap);
-+ tmdev->sram_regmap_field = devm_regmap_field_alloc(dev,
-+ regmap,
-+ sun8i_ths_sram_reg_field);
-+ if (IS_ERR(tmdev->sram_regmap_field))
-+ return PTR_ERR(tmdev->sram_regmap_field);
-+ }
-+
- ret = sun8i_ths_calibrate(tmdev);
- if (ret)
- return ret;
-@@ -427,6 +474,10 @@ static int sun50i_h6_thermal_init(struct
- {
- int val;
-
-+ /* The H616 needs to have a bit in the SRAM control register cleared. */
-+ if (tmdev->sram_regmap_field)
-+ regmap_field_write(tmdev->sram_regmap_field, 0);
-+
- /*
- * The manual recommends an overall sample frequency of 50 KHz (20us,
- * 480 cycles at 24 MHz), which provides plenty of time for both the
+++ /dev/null
-From e7dbfa19572a1440a2e67ef70f94ff204849a0a8 Mon Sep 17 00:00:00 2001
-From: Martin Botka <martin.botka@somainline.org>
-Date: Mon, 19 Feb 2024 15:36:38 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Add support for H616 THS controller
-
-Add support for the thermal sensor found in H616 SoCs, is the same as
-the H6 thermal sensor controller, but with four sensors.
-Also the registers readings are wrong, unless a bit in the first SYS_CFG
-register cleared, so set exercise the SRAM regmap to take care of that.
-
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240219153639.179814-7-andre.przywara@arm.com
----
- drivers/thermal/sun8i_thermal.c | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -688,6 +688,20 @@ static const struct ths_thermal_chip sun
- .calc_temp = sun8i_ths_calc_temp,
- };
-
-+static const struct ths_thermal_chip sun50i_h616_ths = {
-+ .sensor_num = 4,
-+ .has_bus_clk_reset = true,
-+ .needs_sram = true,
-+ .ft_deviation = 8000,
-+ .offset = 263655,
-+ .scale = 810,
-+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
-+ .calibrate = sun50i_h6_ths_calibrate,
-+ .init = sun50i_h6_thermal_init,
-+ .irq_ack = sun50i_h6_irq_ack,
-+ .calc_temp = sun8i_ths_calc_temp,
-+};
-+
- static const struct of_device_id of_ths_match[] = {
- { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
- { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
-@@ -697,6 +711,7 @@ static const struct of_device_id of_ths_
- { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
- { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
- { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
-+ { .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths },
- { /* sentinel */ },
- };
- MODULE_DEVICE_TABLE(of, of_ths_match);
+++ /dev/null
-From 9ac53d5532cc4bb595bbee86ccba2172ccc336c3 Mon Sep 17 00:00:00 2001
-From: Mark Brown <broonie@kernel.org>
-Date: Tue, 23 Jan 2024 23:33:07 +0000
-Subject: [PATCH] thermal/drivers/sun8i: Don't fail probe due to zone
- registration failure
-
-Currently the sun8i thermal driver will fail to probe if any of the
-thermal zones it is registering fails to register with the thermal core.
-Since we currently do not define any trip points for the GPU thermal
-zones on at least A64 or H5 this means that we have no thermal support
-on these platforms:
-
-[ 1.698703] thermal_sys: Failed to find 'trips' node
-[ 1.698707] thermal_sys: Failed to find trip points for thermal-sensor id=1
-
-even though the main CPU thermal zone on both SoCs is fully configured.
-This does not seem ideal, while we may not be able to use all the zones
-it seems better to have those zones which are usable be operational.
-Instead just carry on registering zones if we get any non-deferral
-error, allowing use of those zones which are usable.
-
-This means that we also need to update the interrupt handler to not
-attempt to notify the core for events on zones which we have not
-registered, I didn't see an ability to mask individual interrupts and
-I would expect that interrupts would still be indicated in the ISR even
-if they were masked.
-
-Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20240123-thermal-sun8i-registration-v3-1-3e5771b1bbdd@kernel.org
----
- drivers/thermal/sun8i_thermal.c | 16 ++++++++++++++--
- 1 file changed, 14 insertions(+), 2 deletions(-)
-
---- a/drivers/thermal/sun8i_thermal.c
-+++ b/drivers/thermal/sun8i_thermal.c
-@@ -197,6 +197,9 @@ static irqreturn_t sun8i_irq_thread(int
- int i;
-
- for_each_set_bit(i, &irq_bitmap, tmdev->chip->sensor_num) {
-+ /* We allow some zones to not register. */
-+ if (IS_ERR(tmdev->sensor[i].tzd))
-+ continue;
- thermal_zone_device_update(tmdev->sensor[i].tzd,
- THERMAL_EVENT_UNSPECIFIED);
- }
-@@ -531,8 +534,17 @@ static int sun8i_ths_register(struct ths
- i,
- &tmdev->sensor[i],
- &ths_ops);
-- if (IS_ERR(tmdev->sensor[i].tzd))
-- return PTR_ERR(tmdev->sensor[i].tzd);
-+
-+ /*
-+ * If an individual zone fails to register for reasons
-+ * other than probe deferral (eg, a bad DT) then carry
-+ * on, other zones might register successfully.
-+ */
-+ if (IS_ERR(tmdev->sensor[i].tzd)) {
-+ if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER)
-+ return PTR_ERR(tmdev->sensor[i].tzd);
-+ continue;
-+ }
-
- if (devm_thermal_add_hwmon_sysfs(tmdev->sensor[i].tzd))
- dev_warn(tmdev->dev,
+++ /dev/null
-From f4318af40544b8e7ff5a6b667ede60e6cf808262 Mon Sep 17 00:00:00 2001
-From: Martin Botka <martin.botka@somainline.org>
-Date: Mon, 19 Feb 2024 15:36:39 +0000
-Subject: [PATCH] arm64: dts: allwinner: h616: Add thermal sensor and zones
-
-There are four thermal sensors:
-- CPU
-- GPU
-- VE
-- DRAM
-
-Add the thermal sensor configuration and the thermal zones.
-
-Signed-off-by: Martin Botka <martin.botka@somainline.org>
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Link: https://lore.kernel.org/r/20240219153639.179814-8-andre.przywara@arm.com
-Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
----
- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 88 +++++++++++++++++++
- 1 file changed, 88 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
-@@ -9,6 +9,7 @@
- #include <dt-bindings/clock/sun6i-rtc.h>
- #include <dt-bindings/reset/sun50i-h616-ccu.h>
- #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
-+#include <dt-bindings/thermal/thermal.h>
-
- / {
- interrupt-parent = <&gic>;
-@@ -138,6 +139,10 @@
- reg = <0x03006000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-+
-+ ths_calibration: thermal-sensor-calibration@14 {
-+ reg = <0x14 0x8>;
-+ };
- };
-
- watchdog: watchdog@30090a0 {
-@@ -511,6 +516,19 @@
- };
- };
-
-+ ths: thermal-sensor@5070400 {
-+ compatible = "allwinner,sun50i-h616-ths";
-+ reg = <0x05070400 0x400>;
-+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_THS>;
-+ clock-names = "bus";
-+ resets = <&ccu RST_BUS_THS>;
-+ nvmem-cells = <&ths_calibration>;
-+ nvmem-cell-names = "calibration";
-+ allwinner,sram = <&syscon>;
-+ #thermal-sensor-cells = <1>;
-+ };
-+
- usbotg: usb@5100000 {
- compatible = "allwinner,sun50i-h616-musb",
- "allwinner,sun8i-h3-musb";
-@@ -755,4 +773,74 @@
- #size-cells = <0>;
- };
- };
-+
-+ thermal-zones {
-+ cpu-thermal {
-+ polling-delay-passive = <500>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&ths 2>;
-+ sustainable-power = <1000>;
-+
-+ trips {
-+ cpu_threshold: cpu-trip-0 {
-+ temperature = <60000>;
-+ type = "passive";
-+ hysteresis = <0>;
-+ };
-+ cpu_target: cpu-trip-1 {
-+ temperature = <70000>;
-+ type = "passive";
-+ hysteresis = <0>;
-+ };
-+ cpu_critical: cpu-trip-2 {
-+ temperature = <110000>;
-+ type = "critical";
-+ hysteresis = <0>;
-+ };
-+ };
-+ };
-+
-+ gpu-thermal {
-+ polling-delay-passive = <500>;
-+ polling-delay = <1000>;
-+ thermal-sensors = <&ths 0>;
-+ sustainable-power = <1100>;
-+
-+ trips {
-+ gpu_temp_critical: gpu-trip-0 {
-+ temperature = <110000>;
-+ type = "critical";
-+ hysteresis = <0>;
-+ };
-+ };
-+ };
-+
-+ ve-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&ths 1>;
-+
-+ trips {
-+ ve_temp_critical: ve-trip-0 {
-+ temperature = <110000>;
-+ type = "critical";
-+ hysteresis = <0>;
-+ };
-+ };
-+ };
-+
-+ ddr-thermal {
-+ polling-delay-passive = <0>;
-+ polling-delay = <0>;
-+ thermal-sensors = <&ths 3>;
-+
-+ trips {
-+ ddr_temp_critical: ddr-trip-0 {
-+ temperature = <110000>;
-+ type = "critical";
-+ hysteresis = <0>;
-+ };
-+ };
-+ };
-+ };
- };
+++ /dev/null
-From a896bc1d79e3c00f0aacfe225499d811775616f3 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Sun, 10 Oct 2021 21:50:17 +0800
-Subject: [PATCH] arm64: allwinner: add OF node for USB eth on NanoPi R1S H5
-
-This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
-NanoPi R1S H5. Add the correct value for the RTL8153 LED configuration
-register to match the blink behavior of the other port on the device.
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
----
- arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
-@@ -116,6 +116,13 @@
-
- &ehci1 {
- status = "okay";
-+
-+ usb-eth@1 {
-+ compatible = "realtek,rtl8153";
-+ reg = <1>;
-+
-+ realtek,led-data = <0x78>;
-+ };
- };
-
- &ehci2 {
+++ /dev/null
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
-@@ -59,7 +59,7 @@
-
- key-sw4 {
- label = "sw4";
-- linux,code = <BTN_0>;
-+ linux,code = <KEY_POWER>;
- gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
- wakeup-source;
- };
-@@ -220,7 +220,7 @@
- };
-
- &usb_otg {
-- dr_mode = "otg";
-+ dr_mode = "host";
- status = "okay";
- };
-
+++ /dev/null
-From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001
-From: Oskari Lemmela <oskari@lemmela.net>
-Date: Mon, 31 Dec 2018 07:44:49 +0200
-Subject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions.
-
-First 896kB to u-boot. Enough space for SPL, u-boot and ATF.
-Next 128kB to u-boot environment and rest to firmware.
-
-Firmware partition is compatible FIT image dynamic splitting.
-
-Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
----
- .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
-@@ -58,6 +58,28 @@
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
-+
-+ partitions {
-+ compatible = "fixed-partitions";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "u-boot";
-+ reg = <0x000000 0x0E0000>;
-+ };
-+
-+ partition@e0000 {
-+ label = "u-boot-env";
-+ reg = <0x0E0000 0x020000>;
-+ };
-+
-+ partition@100000 {
-+ compatible = "denx,fit";
-+ label = "firmware";
-+ reg = <0x100000 0xF00000>;
-+ };
-+ };
- };
- };
-
+++ /dev/null
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -1352,6 +1352,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
- sun8i-a83t-cubietruck-plus.dtb \
- sun8i-a83t-tbs-a711.dtb \
- sun8i-h2-plus-bananapi-m2-zero.dtb \
-+ sun8i-h2-plus-bananapi-p2-zero.dtb \
- sun8i-h2-plus-libretech-all-h3-cc.dtb \
- sun8i-h2-plus-orangepi-r1.dtb \
- sun8i-h2-plus-orangepi-zero.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-p2-zero.dts
-@@ -0,0 +1,279 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (C) 2023 Zoltan HERPAI <wigyori@uid0.hu>
-+ *
-+ * Based on sun8i-h2-plus-bananapi-m2-zero.dts, which is:
-+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
-+ */
-+
-+/dts-v1/;
-+#include "sun8i-h3.dtsi"
-+#include "sunxi-common-regulators.dtsi"
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+
-+/ {
-+ model = "Banana Pi BPI-P2-Zero";
-+ compatible = "sinovoip,bpi-p2-zero", "allwinner,sun8i-h2-plus";
-+
-+ aliases {
-+ serial0 = &uart0;
-+ serial1 = &uart1;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ connector {
-+ compatible = "hdmi-connector";
-+ type = "c";
-+
-+ port {
-+ hdmi_con_in: endpoint {
-+ remote-endpoint = <&hdmi_out_con>;
-+ };
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ pwr_led {
-+ label = "bananapi-p2-zero:red:pwr";
-+ gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
-+ default-state = "on";
-+ };
-+ };
-+
-+ gpio_keys {
-+ compatible = "gpio-keys";
-+
-+ sw4 {
-+ label = "power";
-+ linux,code = <BTN_0>;
-+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+
-+ reg_vdd_cpux: vdd-cpux-regulator {
-+ compatible = "regulator-gpio";
-+ regulator-name = "vdd-cpux";
-+ regulator-type = "voltage";
-+ regulator-boot-on;
-+ regulator-always-on;
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1300000>;
-+ regulator-ramp-delay = <50>; /* 4ms */
-+
-+ gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
-+ enable-active-high;
-+ gpios-states = <0x1>;
-+ states = <1100000 0>, <1300000 1>;
-+ };
-+
-+ reg_vcc_dram: vcc-dram {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc-dram";
-+ regulator-min-microvolt = <1500000>;
-+ regulator-max-microvolt = <1500000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ enable-active-high;
-+ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
-+ vin-supply = <®_vcc5v0>;
-+ };
-+
-+ reg_vcc1v2: vcc1v2 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc1v2";
-+ regulator-min-microvolt = <1200000>;
-+ regulator-max-microvolt = <1200000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ enable-active-high;
-+ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
-+ vin-supply = <®_vcc5v0>;
-+ };
-+
-+ poweroff {
-+ compatible = "regulator-poweroff";
-+ cpu-supply = <®_vcc1v2>;
-+ };
-+
-+ wifi_pwrseq: wifi_pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
-+ clocks = <&rtc 1>;
-+ clock-names = "ext_clock";
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <®_vdd_cpux>;
-+};
-+
-+&de {
-+ status = "okay";
-+};
-+
-+&ehci0 {
-+ status = "okay";
-+};
-+
-+&emac {
-+ phy-handle = <&int_mii_phy>;
-+ phy-mode = "mii";
-+ allwinner,leds-active-low;
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ status = "okay";
-+};
-+
-+&hdmi_out {
-+ hdmi_out_con: endpoint {
-+ remote-endpoint = <&hdmi_con_in>;
-+ };
-+};
-+
-+&mmc0 {
-+ vmmc-supply = <®_vcc3v3>;
-+ bus-width = <4>;
-+ /*
-+ * On the production batch of this board the card detect GPIO is
-+ * high active (card inserted), although on the early samples it's
-+ * low active.
-+ */
-+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-+ status = "okay";
-+};
-+
-+&mmc1 {
-+ vmmc-supply = <®_vcc3v3>;
-+ vqmmc-supply = <®_vcc3v3>;
-+ mmc-pwrseq = <&wifi_pwrseq>;
-+ bus-width = <4>;
-+ non-removable;
-+ status = "okay";
-+
-+ brcmf: wifi@1 {
-+ reg = <1>;
-+ compatible = "brcm,bcm4329-fmac";
-+ interrupt-parent = <&pio>;
-+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
-+ interrupt-names = "host-wake";
-+ };
-+};
-+
-+&ohci0 {
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart0_pa_pins>;
-+ status = "okay";
-+};
-+
-+&uart1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
-+ uart-has-rtscts;
-+ status = "okay";
-+
-+ bluetooth {
-+ compatible = "brcm,bcm43438-bt";
-+ max-speed = <1500000>;
-+ clocks = <&rtc 1>;
-+ clock-names = "lpo";
-+ vbat-supply = <®_vcc3v3>;
-+ vddio-supply = <®_vcc3v3>;
-+ device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
-+ host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
-+ shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
-+ };
-+
-+};
-+
-+&pio {
-+ gpio-line-names =
-+ /* PA */
-+ "CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15",
-+ "CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29",
-+ "CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05",
-+ "CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16",
-+ "CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27",
-+ "CON2-P40", "CON2-P38", "", "",
-+ "", "", "", "", "", "", "", "",
-+
-+ /* PB */
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+
-+ /* PC */
-+ "CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24",
-+ "CON2-P18", "", "", "CON2-P26",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+
-+ /* PD */
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "CSI-PWR-EN", "",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+
-+ /* PE */
-+ "CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07",
-+ "CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20",
-+ "CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12",
-+ "CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+
-+ /* PF */
-+ "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
-+ "SDC0-D2", "SDC0-DET", "",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+
-+ /* PG */
-+ "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
-+ "WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX",
-+ "BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP",
-+ "BT-RST-N", "AP-WAKE-BT", "", "",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "";
-+};
-+
-+&r_pio {
-+ gpio-line-names =
-+ /* PL */
-+ "", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36",
-+ "VCC-IO-EN", "USB0-ID", "WL-PWR-EN",
-+ "PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "",
-+ "", "", "", "", "", "", "", "",
-+ "", "", "", "", "", "", "", "";
-+};
-+
-+&usb_otg {
-+ dr_mode = "otg";
-+ status = "okay";
-+};
-+
-+&usbphy {
-+ usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
-+ /*
-+ * There're two micro-USB connectors, one is power-only and another is
-+ * OTG. The Vbus of these two connectors are connected together, so
-+ * the external USB device will be powered just by the power input
-+ * from the power-only USB port.
-+ */
-+ status = "okay";
-+};
+++ /dev/null
-From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
-Date: Thu, 26 Mar 2020 10:09:19 +0100
-Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add status LED aliases
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Petr Štetiar <ynezz@true.cz>
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
-@@ -15,6 +15,10 @@
- aliases {
- ethernet0 = &emac;
- serial0 = &uart0;
-+ led-boot = &led_user;
-+ led-failsafe = &led_user;
-+ led-running = &led_user;
-+ led-upgrade = &led_user;
- };
-
- chosen {
-@@ -35,7 +39,7 @@
- leds {
- compatible = "gpio-leds";
-
-- led-0 {
-+ led_user: led-0 {
- label = "a64-olinuxino:red:user";
- gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
- };
+++ /dev/null
-From 1845163a052efac124f00656eb72f38947630a42 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Sun, 10 Oct 2021 21:50:18 +0800
-Subject: [PATCH] arm64: dts: allwinner: NanoPi R1S H5: add status LED aliases
-
-Use the SYS LED on the casing for showing system status.
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
----
- arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
-@@ -23,6 +23,11 @@
- ethernet0 = &emac;
- ethernet1 = &rtl8189etv;
- serial0 = &uart0;
-+
-+ led-boot = &led_sys;
-+ led-failsafe = &led_sys;
-+ led-running = &led_sys;
-+ led-upgrade = &led_sys;
- };
-
- chosen {
-@@ -38,7 +43,7 @@
- gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
- };
-
-- led-1 {
-+ led_sys: led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+++ /dev/null
---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
-@@ -41,3 +41,7 @@
- reg = <1>;
- };
- };
-+
-+&pwm {
-+ status = "okay";
-+};
+++ /dev/null
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
-@@ -42,6 +42,11 @@
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-+
-+ wifi_pwrseq: wifi_pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
-+ };
- };
-
- &ac_power_supply {
-@@ -102,6 +107,21 @@
- reg = <1>;
- };
- };
-+
-+&mmc1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mmc1_pins>;
-+ vmmc-supply = <®_dldo4>;
-+ vqmmc-supply = <®_eldo1>;
-+ mmc-pwrseq = <&wifi_pwrseq>;
-+ bus-width = <4>;
-+ non-removable;
-+ status = "okay";
-+
-+ rtl8723cs: wifi@1 {
-+ reg = <1>;
-+ };
-+};
-
- &mmc2 {
- pinctrl-names = "default";
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
-@@ -35,6 +35,11 @@
- };
- };
- };
-+
-+ wifi_pwrseq: wifi_pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
-+ };
- };
-
- &codec {
-@@ -124,6 +129,21 @@
- status = "okay";
- };
-
-+&mmc1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&mmc1_pins>;
-+ vmmc-supply = <®_dldo4>;
-+ vqmmc-supply = <®_eldo1>;
-+ mmc-pwrseq = <&wifi_pwrseq>;
-+ bus-width = <4>;
-+ non-removable;
-+ status = "okay";
-+
-+ rtl8723cs: wifi@1 {
-+ reg = <1>;
-+ };
-+};
-+
- &ohci0 {
- status = "okay";
- };
--- /dev/null
+From 951992797378a2177946400438f4d23c9fceae5b Mon Sep 17 00:00:00 2001
+From: Martin Botka <martin.botka@somainline.org>
+Date: Tue, 12 Sep 2023 14:25:13 +0200
+Subject: [PATCH] arm64: dts: allwinner: h616: Add SID controller node
+
+Add node for the H616 SID controller
+
+Signed-off-by: Martin Botka <martin.botka@somainline.org>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Link: https://lore.kernel.org/r/20230912-sid-h616-v3-2-ee18e1c5bbb5@somainline.org
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -133,6 +133,13 @@
+ #reset-cells = <1>;
+ };
+
++ sid: efuse@3006000 {
++ compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
++ reg = <0x03006000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ };
++
+ watchdog: watchdog@30090a0 {
+ compatible = "allwinner,sun50i-h616-wdt",
+ "allwinner,sun6i-a31-wdt";
--- /dev/null
+From 898d96c5464b69af44f6407c5de81ebc349d574b Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 19 Feb 2024 15:36:33 +0000
+Subject: [PATCH] soc: sunxi: sram: export register 0 for THS on H616
+
+The Allwinner H616 SoC contains a mysterious bit at register offset 0x0
+in the SRAM control block. If bit 16 is set (the reset value), the
+temperature readings of the THS are way off, leading to reports about
+200C, at normal ambient temperatures. Clearing this bits brings the
+reported values down to the expected values.
+The BSP code clears this bit in firmware (U-Boot), and has an explicit
+comment about this, but offers no real explanation.
+
+Experiments in U-Boot show that register 0x0 has no effect on the SRAM C
+visibility: all tested bit settings still allow full read and write
+access by the CPU to the whole of SRAM C. Only bit 24 of the register at
+offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling
+the THS switch functionality as an SRAM region would not reflect reality.
+
+Since we should not rely on firmware settings, allow other code (the THS
+driver) to access this register, by exporting it through the already
+existing regmap. This mimics what we already do for the LDO control and
+the EMAC register.
+
+To avoid concurrent accesses to the same register at the same time, by
+the SRAM switch code and the regmap code, use the same lock to protect
+the access. The regmap subsystem allows to use an existing lock, so we
+just need to hook in there.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-2-andre.przywara@arm.com
+---
+ drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/drivers/soc/sunxi/sunxi_sram.c
++++ b/drivers/soc/sunxi/sunxi_sram.c
+@@ -287,6 +287,7 @@ EXPORT_SYMBOL(sunxi_sram_release);
+ struct sunxi_sramc_variant {
+ int num_emac_clocks;
+ bool has_ldo_ctrl;
++ bool has_ths_offset;
+ };
+
+ static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
+@@ -308,8 +309,10 @@ static const struct sunxi_sramc_variant
+
+ static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
+ .num_emac_clocks = 2,
++ .has_ths_offset = true,
+ };
+
++#define SUNXI_SRAM_THS_OFFSET_REG 0x0
+ #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
+ #define SUNXI_SYS_LDO_CTRL_REG 0x150
+
+@@ -318,6 +321,8 @@ static bool sunxi_sram_regmap_accessible
+ {
+ const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
+
++ if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset)
++ return true;
+ if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
+ reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
+ return true;
+@@ -327,6 +332,20 @@ static bool sunxi_sram_regmap_accessible
+ return false;
+ }
+
++static void sunxi_sram_lock(void *_lock)
++{
++ spinlock_t *lock = _lock;
++
++ spin_lock(lock);
++}
++
++static void sunxi_sram_unlock(void *_lock)
++{
++ spinlock_t *lock = _lock;
++
++ spin_unlock(lock);
++}
++
+ static struct regmap_config sunxi_sram_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+@@ -336,6 +355,9 @@ static struct regmap_config sunxi_sram_r
+ /* other devices have no business accessing other registers */
+ .readable_reg = sunxi_sram_regmap_accessible_reg,
+ .writeable_reg = sunxi_sram_regmap_accessible_reg,
++ .lock = sunxi_sram_lock,
++ .unlock = sunxi_sram_unlock,
++ .lock_arg = &sram_lock,
+ };
+
+ static int __init sunxi_sram_probe(struct platform_device *pdev)
--- /dev/null
+From ebbf19e36d021f253425344b4d4b987f3b7d9be5 Mon Sep 17 00:00:00 2001
+From: Maxim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 18 Dec 2023 00:06:23 +0300
+Subject: [PATCH] thermal/drivers/sun8i: Add D1/T113s THS controller support
+
+This patch adds a thermal sensor controller support for the D1/T113s,
+which is similar to the one on H6, but with only one sensor and
+different scale and offset values.
+
+Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231217210629.131486-3-bigunclemax@gmail.com
+---
+ drivers/thermal/sun8i_thermal.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -606,6 +606,18 @@ static const struct ths_thermal_chip sun
+ .calc_temp = sun8i_ths_calc_temp,
+ };
+
++static const struct ths_thermal_chip sun20i_d1_ths = {
++ .sensor_num = 1,
++ .has_bus_clk_reset = true,
++ .offset = 188552,
++ .scale = 673,
++ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
++ .calibrate = sun50i_h6_ths_calibrate,
++ .init = sun50i_h6_thermal_init,
++ .irq_ack = sun50i_h6_irq_ack,
++ .calc_temp = sun8i_ths_calc_temp,
++};
++
+ static const struct of_device_id of_ths_match[] = {
+ { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
+ { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+@@ -614,6 +626,7 @@ static const struct of_device_id of_ths_
+ { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
+ { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
+ { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
++ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
+ { /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, of_ths_match);
--- /dev/null
+From 14f118aa50fe7c7c7330f56d007ecacca487cea8 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 19 Feb 2024 15:36:35 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Explain unknown H6 register value
+
+So far we were ORing in some "unknown" value into the THS control
+register on the Allwinner H6. This part of the register is not explained
+in the H6 manual, but the H616 manual details those bits, and on closer
+inspection the THS IP blocks in both SoCs seem very close:
+- The BSP code for both SoCs writes the same values into THS_CTRL.
+- The reset values of at least the first three registers are the same.
+
+Replace the "unknown" value with its proper meaning: "acquire time",
+most probably the sample part of the sample & hold circuit of the ADC,
+according to its explanation in the H616 manual.
+
+No functional change, just a macro rename and adjustment.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-4-andre.przywara@arm.com
+---
+ drivers/thermal/sun8i_thermal.c | 29 ++++++++++++++++-------------
+ 1 file changed, 16 insertions(+), 13 deletions(-)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -50,7 +50,8 @@
+ #define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16)
+ #define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8)
+
+-#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16)
++#define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & ((x) - 1))
++#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x) ((GENMASK(15, 0) & ((x) - 1)) << 16)
+ #define SUN50I_THS_FILTER_EN BIT(2)
+ #define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
+ #define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12)
+@@ -410,25 +411,27 @@ static int sun8i_h3_thermal_init(struct
+ return 0;
+ }
+
+-/*
+- * Without this undocumented value, the returned temperatures would
+- * be higher than real ones by about 20C.
+- */
+-#define SUN50I_H6_CTRL0_UNK 0x0000002f
+-
+ static int sun50i_h6_thermal_init(struct ths_device *tmdev)
+ {
+ int val;
+
+ /*
+- * T_acq = 20us
+- * clkin = 24MHz
+- *
+- * x = T_acq * clkin - 1
+- * = 479
++ * The manual recommends an overall sample frequency of 50 KHz (20us,
++ * 480 cycles at 24 MHz), which provides plenty of time for both the
++ * acquisition time (>24 cycles) and the actual conversion time
++ * (>14 cycles).
++ * The lower half of the CTRL register holds the "acquire time", in
++ * clock cycles, which the manual recommends to be 2us:
++ * 24MHz * 2us = 48 cycles.
++ * The high half of THS_CTRL encodes the sample frequency, in clock
++ * cycles: 24MHz * 20us = 480 cycles.
++ * This is explained in the H616 manual, but apparently wrongly
++ * described in the H6 manual, although the BSP code does the same
++ * for both SoCs.
+ */
+ regmap_write(tmdev->regmap, SUN50I_THS_CTRL0,
+- SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479));
++ SUN50I_THS_CTRL0_T_ACQ(48) |
++ SUN50I_THS_CTRL0_T_SAMPLE_PER(480));
+ /* average over 4 samples */
+ regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC,
+ SUN50I_THS_FILTER_EN |
--- /dev/null
+From 6c04a419a4c5fb18edefc44dd676fb95c7f6c55d Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 19 Feb 2024 15:36:36 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Extend H6 calibration to support 4
+ sensors
+
+The H616 SoC resembles the H6 thermal sensor controller, with a few
+changes like four sensors.
+
+Extend sun50i_h6_ths_calibrate() function to support calibration of
+these sensors.
+
+Co-developed-by: Martin Botka <martin.botka@somainline.org>
+Signed-off-by: Martin Botka <martin.botka@somainline.org>
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-5-andre.przywara@arm.com
+---
+ drivers/thermal/sun8i_thermal.c | 28 ++++++++++++++++++++--------
+ 1 file changed, 20 insertions(+), 8 deletions(-)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -222,16 +222,21 @@ static int sun50i_h6_ths_calibrate(struc
+ struct device *dev = tmdev->dev;
+ int i, ft_temp;
+
+- if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num)
++ if (!caldata[0])
+ return -EINVAL;
+
+ /*
+ * efuse layout:
+ *
+- * 0 11 16 32
+- * +-------+-------+-------+
+- * |temp| |sensor0|sensor1|
+- * +-------+-------+-------+
++ * 0 11 16 27 32 43 48 57
++ * +----------+-----------+-----------+-----------+
++ * | temp | |sensor0| |sensor1| |sensor2| |
++ * +----------+-----------+-----------+-----------+
++ * ^ ^ ^
++ * | | |
++ * | | sensor3[11:8]
++ * | sensor3[7:4]
++ * sensor3[3:0]
+ *
+ * The calibration data on the H6 is the ambient temperature and
+ * sensor values that are filled during the factory test stage.
+@@ -244,9 +249,16 @@ static int sun50i_h6_ths_calibrate(struc
+ ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
+
+ for (i = 0; i < tmdev->chip->sensor_num; i++) {
+- int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
+- int cdata, offset;
+- int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
++ int sensor_reg, sensor_temp, cdata, offset;
++
++ if (i == 3)
++ sensor_reg = (caldata[1] >> 12)
++ | ((caldata[2] >> 12) << 4)
++ | ((caldata[3] >> 12) << 8);
++ else
++ sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
++
++ sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
+
+ /*
+ * Calibration data is CALIBRATE_DEFAULT - (calculated
--- /dev/null
+From f8b54d1120b81ed57bed96cc8e814ba08886d1e5 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 19 Feb 2024 15:36:37 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Add SRAM register access code
+
+The Allwinner H616 SoC needs to clear a bit in one register in the SRAM
+controller, to report reasonable temperature values. On reset, bit 16 in
+register 0x3000000 is set, which leads to the driver reporting
+temperatures around 200C. Clearing this bit brings the values down to the
+expected range. The BSP code does a one-time write in U-Boot, with a
+comment just mentioning the effect on the THS, but offering no further
+explanation.
+
+To not rely on firmware to set things up for us, add code that queries
+the SRAM controller device via a DT phandle link, then clear just this
+single bit.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-6-andre.przywara@arm.com
+---
+ drivers/thermal/sun8i_thermal.c | 51 +++++++++++++++++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -15,6 +15,7 @@
+ #include <linux/module.h>
+ #include <linux/nvmem-consumer.h>
+ #include <linux/of.h>
++#include <linux/of_platform.h>
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ #include <linux/reset.h>
+@@ -66,6 +67,7 @@ struct tsensor {
+ struct ths_thermal_chip {
+ bool has_mod_clk;
+ bool has_bus_clk_reset;
++ bool needs_sram;
+ int sensor_num;
+ int offset;
+ int scale;
+@@ -83,12 +85,16 @@ struct ths_device {
+ const struct ths_thermal_chip *chip;
+ struct device *dev;
+ struct regmap *regmap;
++ struct regmap_field *sram_regmap_field;
+ struct reset_control *reset;
+ struct clk *bus_clk;
+ struct clk *mod_clk;
+ struct tsensor sensor[MAX_SENSOR_NUM];
+ };
+
++/* The H616 needs to have a bit 16 in the SRAM control register cleared. */
++static const struct reg_field sun8i_ths_sram_reg_field = REG_FIELD(0x0, 16, 16);
++
+ /* Temp Unit: millidegree Celsius */
+ static int sun8i_ths_calc_temp(struct ths_device *tmdev,
+ int id, int reg)
+@@ -337,6 +343,34 @@ static void sun8i_ths_reset_control_asse
+ reset_control_assert(data);
+ }
+
++static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node)
++{
++ struct device_node *sram_node;
++ struct platform_device *sram_pdev;
++ struct regmap *regmap = NULL;
++
++ sram_node = of_parse_phandle(node, "allwinner,sram", 0);
++ if (!sram_node)
++ return ERR_PTR(-ENODEV);
++
++ sram_pdev = of_find_device_by_node(sram_node);
++ if (!sram_pdev) {
++ /* platform device might not be probed yet */
++ regmap = ERR_PTR(-EPROBE_DEFER);
++ goto out_put_node;
++ }
++
++ /* If no regmap is found then the other device driver is at fault */
++ regmap = dev_get_regmap(&sram_pdev->dev, NULL);
++ if (!regmap)
++ regmap = ERR_PTR(-EINVAL);
++
++ platform_device_put(sram_pdev);
++out_put_node:
++ of_node_put(sram_node);
++ return regmap;
++}
++
+ static int sun8i_ths_resource_init(struct ths_device *tmdev)
+ {
+ struct device *dev = tmdev->dev;
+@@ -381,6 +415,19 @@ static int sun8i_ths_resource_init(struc
+ if (ret)
+ return ret;
+
++ if (tmdev->chip->needs_sram) {
++ struct regmap *regmap;
++
++ regmap = sun8i_ths_get_sram_regmap(dev->of_node);
++ if (IS_ERR(regmap))
++ return PTR_ERR(regmap);
++ tmdev->sram_regmap_field = devm_regmap_field_alloc(dev,
++ regmap,
++ sun8i_ths_sram_reg_field);
++ if (IS_ERR(tmdev->sram_regmap_field))
++ return PTR_ERR(tmdev->sram_regmap_field);
++ }
++
+ ret = sun8i_ths_calibrate(tmdev);
+ if (ret)
+ return ret;
+@@ -427,6 +474,10 @@ static int sun50i_h6_thermal_init(struct
+ {
+ int val;
+
++ /* The H616 needs to have a bit in the SRAM control register cleared. */
++ if (tmdev->sram_regmap_field)
++ regmap_field_write(tmdev->sram_regmap_field, 0);
++
+ /*
+ * The manual recommends an overall sample frequency of 50 KHz (20us,
+ * 480 cycles at 24 MHz), which provides plenty of time for both the
--- /dev/null
+From e7dbfa19572a1440a2e67ef70f94ff204849a0a8 Mon Sep 17 00:00:00 2001
+From: Martin Botka <martin.botka@somainline.org>
+Date: Mon, 19 Feb 2024 15:36:38 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Add support for H616 THS controller
+
+Add support for the thermal sensor found in H616 SoCs, is the same as
+the H6 thermal sensor controller, but with four sensors.
+Also the registers readings are wrong, unless a bit in the first SYS_CFG
+register cleared, so set exercise the SRAM regmap to take care of that.
+
+Signed-off-by: Martin Botka <martin.botka@somainline.org>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-7-andre.przywara@arm.com
+---
+ drivers/thermal/sun8i_thermal.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -684,6 +684,20 @@ static const struct ths_thermal_chip sun
+ .calc_temp = sun8i_ths_calc_temp,
+ };
+
++static const struct ths_thermal_chip sun50i_h616_ths = {
++ .sensor_num = 4,
++ .has_bus_clk_reset = true,
++ .needs_sram = true,
++ .ft_deviation = 8000,
++ .offset = 263655,
++ .scale = 810,
++ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
++ .calibrate = sun50i_h6_ths_calibrate,
++ .init = sun50i_h6_thermal_init,
++ .irq_ack = sun50i_h6_irq_ack,
++ .calc_temp = sun8i_ths_calc_temp,
++};
++
+ static const struct of_device_id of_ths_match[] = {
+ { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
+ { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+@@ -693,6 +707,7 @@ static const struct of_device_id of_ths_
+ { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
+ { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
+ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
++ { .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths },
+ { /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, of_ths_match);
--- /dev/null
+From 9ac53d5532cc4bb595bbee86ccba2172ccc336c3 Mon Sep 17 00:00:00 2001
+From: Mark Brown <broonie@kernel.org>
+Date: Tue, 23 Jan 2024 23:33:07 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Don't fail probe due to zone
+ registration failure
+
+Currently the sun8i thermal driver will fail to probe if any of the
+thermal zones it is registering fails to register with the thermal core.
+Since we currently do not define any trip points for the GPU thermal
+zones on at least A64 or H5 this means that we have no thermal support
+on these platforms:
+
+[ 1.698703] thermal_sys: Failed to find 'trips' node
+[ 1.698707] thermal_sys: Failed to find trip points for thermal-sensor id=1
+
+even though the main CPU thermal zone on both SoCs is fully configured.
+This does not seem ideal, while we may not be able to use all the zones
+it seems better to have those zones which are usable be operational.
+Instead just carry on registering zones if we get any non-deferral
+error, allowing use of those zones which are usable.
+
+This means that we also need to update the interrupt handler to not
+attempt to notify the core for events on zones which we have not
+registered, I didn't see an ability to mask individual interrupts and
+I would expect that interrupts would still be indicated in the ISR even
+if they were masked.
+
+Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240123-thermal-sun8i-registration-v3-1-3e5771b1bbdd@kernel.org
+---
+ drivers/thermal/sun8i_thermal.c | 16 ++++++++++++++--
+ 1 file changed, 14 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -195,6 +195,9 @@ static irqreturn_t sun8i_irq_thread(int
+ int i;
+
+ for_each_set_bit(i, &irq_bitmap, tmdev->chip->sensor_num) {
++ /* We allow some zones to not register. */
++ if (IS_ERR(tmdev->sensor[i].tzd))
++ continue;
+ thermal_zone_device_update(tmdev->sensor[i].tzd,
+ THERMAL_EVENT_UNSPECIFIED);
+ }
+@@ -531,8 +534,17 @@ static int sun8i_ths_register(struct ths
+ i,
+ &tmdev->sensor[i],
+ &ths_ops);
+- if (IS_ERR(tmdev->sensor[i].tzd))
+- return PTR_ERR(tmdev->sensor[i].tzd);
++
++ /*
++ * If an individual zone fails to register for reasons
++ * other than probe deferral (eg, a bad DT) then carry
++ * on, other zones might register successfully.
++ */
++ if (IS_ERR(tmdev->sensor[i].tzd)) {
++ if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER)
++ return PTR_ERR(tmdev->sensor[i].tzd);
++ continue;
++ }
+
+ devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd);
+ }
--- /dev/null
+From f4318af40544b8e7ff5a6b667ede60e6cf808262 Mon Sep 17 00:00:00 2001
+From: Martin Botka <martin.botka@somainline.org>
+Date: Mon, 19 Feb 2024 15:36:39 +0000
+Subject: [PATCH] arm64: dts: allwinner: h616: Add thermal sensor and zones
+
+There are four thermal sensors:
+- CPU
+- GPU
+- VE
+- DRAM
+
+Add the thermal sensor configuration and the thermal zones.
+
+Signed-off-by: Martin Botka <martin.botka@somainline.org>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Link: https://lore.kernel.org/r/20240219153639.179814-8-andre.przywara@arm.com
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 88 +++++++++++++++++++
+ 1 file changed, 88 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/clock/sun6i-rtc.h>
+ #include <dt-bindings/reset/sun50i-h616-ccu.h>
+ #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
++#include <dt-bindings/thermal/thermal.h>
+
+ / {
+ interrupt-parent = <&gic>;
+@@ -138,6 +139,10 @@
+ reg = <0x03006000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
++
++ ths_calibration: thermal-sensor-calibration@14 {
++ reg = <0x14 0x8>;
++ };
+ };
+
+ watchdog: watchdog@30090a0 {
+@@ -511,6 +516,19 @@
+ };
+ };
+
++ ths: thermal-sensor@5070400 {
++ compatible = "allwinner,sun50i-h616-ths";
++ reg = <0x05070400 0x400>;
++ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_THS>;
++ clock-names = "bus";
++ resets = <&ccu RST_BUS_THS>;
++ nvmem-cells = <&ths_calibration>;
++ nvmem-cell-names = "calibration";
++ allwinner,sram = <&syscon>;
++ #thermal-sensor-cells = <1>;
++ };
++
+ usbotg: usb@5100000 {
+ compatible = "allwinner,sun50i-h616-musb",
+ "allwinner,sun8i-h3-musb";
+@@ -755,4 +773,74 @@
+ #size-cells = <0>;
+ };
+ };
++
++ thermal-zones {
++ cpu-thermal {
++ polling-delay-passive = <500>;
++ polling-delay = <1000>;
++ thermal-sensors = <&ths 2>;
++ sustainable-power = <1000>;
++
++ trips {
++ cpu_threshold: cpu-trip-0 {
++ temperature = <60000>;
++ type = "passive";
++ hysteresis = <0>;
++ };
++ cpu_target: cpu-trip-1 {
++ temperature = <70000>;
++ type = "passive";
++ hysteresis = <0>;
++ };
++ cpu_critical: cpu-trip-2 {
++ temperature = <110000>;
++ type = "critical";
++ hysteresis = <0>;
++ };
++ };
++ };
++
++ gpu-thermal {
++ polling-delay-passive = <500>;
++ polling-delay = <1000>;
++ thermal-sensors = <&ths 0>;
++ sustainable-power = <1100>;
++
++ trips {
++ gpu_temp_critical: gpu-trip-0 {
++ temperature = <110000>;
++ type = "critical";
++ hysteresis = <0>;
++ };
++ };
++ };
++
++ ve-thermal {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&ths 1>;
++
++ trips {
++ ve_temp_critical: ve-trip-0 {
++ temperature = <110000>;
++ type = "critical";
++ hysteresis = <0>;
++ };
++ };
++ };
++
++ ddr-thermal {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&ths 3>;
++
++ trips {
++ ddr_temp_critical: ddr-trip-0 {
++ temperature = <110000>;
++ type = "critical";
++ hysteresis = <0>;
++ };
++ };
++ };
++ };
+ };
--- /dev/null
+From a896bc1d79e3c00f0aacfe225499d811775616f3 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Sun, 10 Oct 2021 21:50:17 +0800
+Subject: [PATCH] arm64: allwinner: add OF node for USB eth on NanoPi R1S H5
+
+This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
+NanoPi R1S H5. Add the correct value for the RTL8153 LED configuration
+register to match the blink behavior of the other port on the device.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
+@@ -116,6 +116,13 @@
+
+ &ehci1 {
+ status = "okay";
++
++ usb-eth@1 {
++ compatible = "realtek,rtl8153";
++ reg = <1>;
++
++ realtek,led-data = <0x78>;
++ };
+ };
+
+ &ehci2 {
--- /dev/null
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -60,7 +60,7 @@
+
+ key-sw4 {
+ label = "sw4";
+- linux,code = <BTN_0>;
++ linux,code = <KEY_POWER>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+@@ -221,7 +221,7 @@
+ };
+
+ &usb_otg {
+- dr_mode = "otg";
++ dr_mode = "host";
+ status = "okay";
+ };
+
--- /dev/null
+From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001
+From: Oskari Lemmela <oskari@lemmela.net>
+Date: Mon, 31 Dec 2018 07:44:49 +0200
+Subject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions.
+
+First 896kB to u-boot. Enough space for SPL, u-boot and ATF.
+Next 128kB to u-boot environment and rest to firmware.
+
+Firmware partition is compatible FIT image dynamic splitting.
+
+Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
+---
+ .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
+@@ -58,6 +58,28 @@
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "u-boot";
++ reg = <0x000000 0x0E0000>;
++ };
++
++ partition@e0000 {
++ label = "u-boot-env";
++ reg = <0x0E0000 0x020000>;
++ };
++
++ partition@100000 {
++ compatible = "denx,fit";
++ label = "firmware";
++ reg = <0x100000 0xF00000>;
++ };
++ };
+ };
+ };
+
--- /dev/null
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -280,6 +280,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ sun8i-a83t-cubietruck-plus.dtb \
+ sun8i-a83t-tbs-a711.dtb \
+ sun8i-h2-plus-bananapi-m2-zero.dtb \
++ sun8i-h2-plus-bananapi-p2-zero.dtb \
+ sun8i-h2-plus-libretech-all-h3-cc.dtb \
+ sun8i-h2-plus-orangepi-r1.dtb \
+ sun8i-h2-plus-orangepi-zero.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-p2-zero.dts
+@@ -0,0 +1,279 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2023 Zoltan HERPAI <wigyori@uid0.hu>
++ *
++ * Based on sun8i-h2-plus-bananapi-m2-zero.dts, which is:
++ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
++ */
++
++/dts-v1/;
++#include "sun8i-h3.dtsi"
++#include "sunxi-common-regulators.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "Banana Pi BPI-P2-Zero";
++ compatible = "sinovoip,bpi-p2-zero", "allwinner,sun8i-h2-plus";
++
++ aliases {
++ serial0 = &uart0;
++ serial1 = &uart1;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ connector {
++ compatible = "hdmi-connector";
++ type = "c";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ pwr_led {
++ label = "bananapi-p2-zero:red:pwr";
++ gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
++ default-state = "on";
++ };
++ };
++
++ gpio_keys {
++ compatible = "gpio-keys";
++
++ sw4 {
++ label = "power";
++ linux,code = <BTN_0>;
++ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ reg_vdd_cpux: vdd-cpux-regulator {
++ compatible = "regulator-gpio";
++ regulator-name = "vdd-cpux";
++ regulator-type = "voltage";
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1300000>;
++ regulator-ramp-delay = <50>; /* 4ms */
++
++ gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
++ enable-active-high;
++ gpios-states = <0x1>;
++ states = <1100000 0>, <1300000 1>;
++ };
++
++ reg_vcc_dram: vcc-dram {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc-dram";
++ regulator-min-microvolt = <1500000>;
++ regulator-max-microvolt = <1500000>;
++ regulator-always-on;
++ regulator-boot-on;
++ enable-active-high;
++ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++ vin-supply = <®_vcc5v0>;
++ };
++
++ reg_vcc1v2: vcc1v2 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc1v2";
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-always-on;
++ regulator-boot-on;
++ enable-active-high;
++ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++ vin-supply = <®_vcc5v0>;
++ };
++
++ poweroff {
++ compatible = "regulator-poweroff";
++ cpu-supply = <®_vcc1v2>;
++ };
++
++ wifi_pwrseq: wifi_pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++ clocks = <&rtc 1>;
++ clock-names = "ext_clock";
++ };
++};
++
++&cpu0 {
++ cpu-supply = <®_vdd_cpux>;
++};
++
++&de {
++ status = "okay";
++};
++
++&ehci0 {
++ status = "okay";
++};
++
++&emac {
++ phy-handle = <&int_mii_phy>;
++ phy-mode = "mii";
++ allwinner,leds-active-low;
++ status = "okay";
++};
++
++&hdmi {
++ status = "okay";
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
++&mmc0 {
++ vmmc-supply = <®_vcc3v3>;
++ bus-width = <4>;
++ /*
++ * On the production batch of this board the card detect GPIO is
++ * high active (card inserted), although on the early samples it's
++ * low active.
++ */
++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
++ status = "okay";
++};
++
++&mmc1 {
++ vmmc-supply = <®_vcc3v3>;
++ vqmmc-supply = <®_vcc3v3>;
++ mmc-pwrseq = <&wifi_pwrseq>;
++ bus-width = <4>;
++ non-removable;
++ status = "okay";
++
++ brcmf: wifi@1 {
++ reg = <1>;
++ compatible = "brcm,bcm4329-fmac";
++ interrupt-parent = <&pio>;
++ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
++ interrupt-names = "host-wake";
++ };
++};
++
++&ohci0 {
++ status = "okay";
++};
++
++&uart0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0_pa_pins>;
++ status = "okay";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++ uart-has-rtscts;
++ status = "okay";
++
++ bluetooth {
++ compatible = "brcm,bcm43438-bt";
++ max-speed = <1500000>;
++ clocks = <&rtc 1>;
++ clock-names = "lpo";
++ vbat-supply = <®_vcc3v3>;
++ vddio-supply = <®_vcc3v3>;
++ device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
++ host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
++ shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++ };
++
++};
++
++&pio {
++ gpio-line-names =
++ /* PA */
++ "CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15",
++ "CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29",
++ "CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05",
++ "CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16",
++ "CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27",
++ "CON2-P40", "CON2-P38", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PB */
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PC */
++ "CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24",
++ "CON2-P18", "", "", "CON2-P26",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PD */
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "CSI-PWR-EN", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PE */
++ "CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07",
++ "CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20",
++ "CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12",
++ "CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PF */
++ "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
++ "SDC0-D2", "SDC0-DET", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PG */
++ "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
++ "WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX",
++ "BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP",
++ "BT-RST-N", "AP-WAKE-BT", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "";
++};
++
++&r_pio {
++ gpio-line-names =
++ /* PL */
++ "", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36",
++ "VCC-IO-EN", "USB0-ID", "WL-PWR-EN",
++ "PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "";
++};
++
++&usb_otg {
++ dr_mode = "otg";
++ status = "okay";
++};
++
++&usbphy {
++ usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++ /*
++ * There're two micro-USB connectors, one is power-only and another is
++ * OTG. The Vbus of these two connectors are connected together, so
++ * the external USB device will be powered just by the power input
++ * from the power-only USB port.
++ */
++ status = "okay";
++};
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
+Date: Thu, 26 Mar 2020 10:09:19 +0100
+Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add status LED aliases
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+@@ -15,6 +15,10 @@
+ aliases {
+ ethernet0 = &emac;
+ serial0 = &uart0;
++ led-boot = &led_user;
++ led-failsafe = &led_user;
++ led-running = &led_user;
++ led-upgrade = &led_user;
+ };
+
+ chosen {
+@@ -35,7 +39,7 @@
+ leds {
+ compatible = "gpio-leds";
+
+- led-0 {
++ led_user: led-0 {
+ label = "a64-olinuxino:red:user";
+ gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
+ };
--- /dev/null
+From 1845163a052efac124f00656eb72f38947630a42 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Sun, 10 Oct 2021 21:50:18 +0800
+Subject: [PATCH] arm64: dts: allwinner: NanoPi R1S H5: add status LED aliases
+
+Use the SYS LED on the casing for showing system status.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
+@@ -23,6 +23,11 @@
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189etv;
+ serial0 = &uart0;
++
++ led-boot = &led_sys;
++ led-failsafe = &led_sys;
++ led-running = &led_sys;
++ led-upgrade = &led_sys;
+ };
+
+ chosen {
+@@ -38,7 +43,7 @@
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+- led-1 {
++ led_sys: led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
--- /dev/null
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
+@@ -41,3 +41,7 @@
+ reg = <1>;
+ };
+ };
++
++&pwm {
++ status = "okay";
++};
--- /dev/null
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+@@ -42,6 +42,11 @@
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
++
++ wifi_pwrseq: wifi_pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
++ };
+ };
+
+ &ac_power_supply {
+@@ -102,6 +107,21 @@
+ reg = <1>;
+ };
+ };
++
++&mmc1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&mmc1_pins>;
++ vmmc-supply = <®_dldo4>;
++ vqmmc-supply = <®_eldo1>;
++ mmc-pwrseq = <&wifi_pwrseq>;
++ bus-width = <4>;
++ non-removable;
++ status = "okay";
++
++ rtl8723cs: wifi@1 {
++ reg = <1>;
++ };
++};
+
+ &mmc2 {
+ pinctrl-names = "default";
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -35,6 +35,11 @@
+ };
+ };
+ };
++
++ wifi_pwrseq: wifi_pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
++ };
+ };
+
+ &codec {
+@@ -124,6 +129,21 @@
+ status = "okay";
+ };
+
++&mmc1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&mmc1_pins>;
++ vmmc-supply = <®_dldo4>;
++ vqmmc-supply = <®_eldo1>;
++ mmc-pwrseq = <&wifi_pwrseq>;
++ bus-width = <4>;
++ non-removable;
++ status = "okay";
++
++ rtl8723cs: wifi@1 {
++ reg = <1>;
++ };
++};
++
+ &ohci0 {
+ status = "okay";
+ };
-n '$(DEVICE_TITLE) OpenWrt bootscript' \
-d $(BOOT_SCRIPT) \
$@.boot/boot.scr
+ $(CP) $@ $@.rootfs
SIGNATURE="$(IMG_PART_SIGNATURE)" \
$(SCRIPT_DIR)/gen_image_generic.sh \
$@ \
$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
- $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
+ $(CONFIG_TARGET_ROOTFS_PARTSIZE) $@.rootfs \
2048
$(if $(UBOOT),dd if=$(STAGING_DIR_IMAGE)/$(UBOOT).img of=$@ bs=512 skip=1 seek=1 conv=notrunc)
define Device/Default
BOOT_SCRIPT := generic-bootscript
IMAGES := sdcard.img.gz
- IMAGE/sdcard.img.gz := tegra-sdcard | gzip | append-metadata
+ IMAGE/sdcard.img.gz := append-rootfs | pad-extra 128k | tegra-sdcard | gzip | append-metadata
KERNEL_NAME := zImage
KERNEL := kernel-bin
PROFILES := Default
DEVICE_VENDOR := CompuLab
DEVICE_MODEL := TrimSlice
DEVICE_DTS := tegra20-trimslice
- DEVICE_PACKAGES := kmod-r8169 kmod-rt2800-usb kmod-rtc-em3027 \
- kmod-usb-storage wpad-basic-mbedtls
+ DEVICE_PACKAGES := kmod-leds-gpio kmod-r8169 kmod-rt2800-usb \
+ kmod-rtc-em3027 kmod-usb-hid kmod-usb-storage wpad-basic-mbedtls
UBOOT := trimslice-mmc
endef
TARGET_DEVICES += compulab_trimslice
part uuid ${devtype} ${devnum}:2 ptuuid
-setenv bootargs "root=PARTUUID=${ptuuid} rw rootwait console=ttyS0,115200 console=tty0"
+setenv bootargs "root=PARTUUID=${ptuuid} rw rootwait"
load ${devtype} ${devnum}:${bootpart} ${kernel_addr_r} zImage
load ${devtype} ${devnum}:${bootpart} ${fdt_addr_r} ${soc}-${board}.dtb
CONFIG_INTEL_IOMMU=y
# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set
CONFIG_INTEL_IOMMU_FLOPPY_WA=y
+CONFIG_INTEL_IOMMU_PERF_EVENTS=y
# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set
# CONFIG_INTEL_IOMMU_SVM is not set
# CONFIG_INTEL_IPS is not set
CONFIG_MICROCODE_LATE_LOADING=y
CONFIG_MIGRATION=y
CONFIG_MITIGATION_RFDS=y
+CONFIG_MITIGATION_SPECTRE_BHI=y
# CONFIG_MK6 is not set
# CONFIG_MK7 is not set
# CONFIG_MK8 is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_SUP_AMD=y
CONFIG_CPU_SUP_CENTAUR=y
CONFIG_CPU_SUP_CYRIX_32=y
CONFIG_MICROCODE_LATE_LOADING=y
CONFIG_MIGRATION=y
CONFIG_MITIGATION_RFDS=y
+CONFIG_MITIGATION_SPECTRE_BHI=y
# CONFIG_MK6 is not set
# CONFIG_MK7 is not set
# CONFIG_MK8 is not set
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
CONFIG_NEED_SG_DMA_LENGTH=y
# CONFIG_NET5501 is not set
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
# CONFIG_NET_NS is not set
+CONFIG_NET_XGRESS=y
CONFIG_NLS=y
# CONFIG_NMI_CHECK_CPU is not set
# CONFIG_NOHIGHMEM is not set
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_PC104=y
# CONFIG_PC8736x_GPIO is not set
# CONFIG_PC87413_WDT is not set
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_SPARSE_IRQ=y
-CONFIG_SPECULATION_MITIGATIONS=y
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
# CONFIG_STATIC_CALL_SELFTEST is not set
# CONFIG_STRICT_SIGALTSTACK_SIZE is not set
Build firmware image for Zynq 7000 SoC devices.
endef
-KERNEL_PATCHVER:=5.15
+KERNEL_PATCHVER:=6.1
include $(INCLUDE_DIR)/target.mk
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_ALTERA_FREEZE_BRIDGE is not set
-# CONFIG_ALTERA_PR_IP_CORE is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=1024
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_VEXPRESS=y
-CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y
-# CONFIG_ARCH_VEXPRESS_SPC is not set
-CONFIG_ARCH_ZYNQ=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_ERRATA_643719=y
-CONFIG_ARM_ERRATA_720789=y
-CONFIG_ARM_ERRATA_754322=y
-CONFIG_ARM_ERRATA_754327=y
-CONFIG_ARM_ERRATA_764369=y
-CONFIG_ARM_ERRATA_775420=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GLOBAL_TIMER=y
-CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_PL172_MPMC is not set
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_TIMER_SP804=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_ARM_ZYNQ_CPUIDLE=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-# CONFIG_AXI_DMAC is not set
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_PM=y
-CONFIG_BOUNCE=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CADENCE_TTC_TIMER=y
-CONFIG_CADENCE_WATCHDOG=y
-CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_VERSATILE=y
-CONFIG_CLK_SP810=y
-CONFIG_CLK_VEXPRESS_OSC=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_SI570=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONNECTOR=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-# CONFIG_CPUFREQ_DT is not set
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DRM=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_E1000E=y
-CONFIG_EDAC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_LEGACY_SYSFS=y
-CONFIG_EDAC_SUPPORT=y
-# CONFIG_EDAC_SYNOPSYS is not set
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_AT25=y
-CONFIG_ELF_CORE=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_F2FS_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-# CONFIG_FB_XILINX is not set
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FPGA=y
-CONFIG_FPGA_BRIDGE=y
-# CONFIG_FPGA_DFL is not set
-# CONFIG_FPGA_MGR_ALTERA_CVP is not set
-# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
-# CONFIG_FPGA_MGR_ICE40_SPI is not set
-# CONFIG_FPGA_MGR_MACHXO2_SPI is not set
-# CONFIG_FPGA_MGR_XILINX_SPI is not set
-CONFIG_FPGA_MGR_ZYNQ_FPGA=y
-CONFIG_FPGA_REGION=y
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_ZYNQ=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAVE_SMP=y
-CONFIG_HDMI=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CADENCE=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PCA954x=y
-CONFIG_ICST=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_MOUSE=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_SPARSEKMAP=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-CONFIG_JBD2=y
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_KCMP=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_GPIO_POLLED=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_CAMERA=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LEDS_TRIGGER_TRANSIENT=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MACB=y
-# CONFIG_MACB_PCI is not set
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MARVELL_PHY=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MDIO_GPIO is not set
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_VEXPRESS_SYSREG=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_ARASAN=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODULE_STRIPPED is not set
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_CYAPA is not set
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_BYD=y
-CONFIG_MOUSE_PS2_CYPRESS=y
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-CONFIG_MOUSE_PS2_FOCALTECH=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_NET_VENDOR_VIA is not set
-CONFIG_NLS=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NO_IOPORT_MAP=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-# CONFIG_OF_FPGA_REGION is not set
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PCI=y
-CONFIG_PCIE_XILINX=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PINCTRL_ZYNQ=y
-CONFIG_PL310_ERRATA_588369=y
-CONFIG_PL310_ERRATA_727915=y
-CONFIG_PL310_ERRATA_753970=y
-CONFIG_PL310_ERRATA_769419=y
-CONFIG_PL330_DMA=y
-# CONFIG_PL353_SMC is not set
-CONFIG_PLAT_VERSATILE=y
-CONFIG_PM=y
-CONFIG_PMBUS=y
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_VEXPRESS=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_R8169=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_VEXPRESS is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_ZYNQ=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_PCF8563=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_SMT=y
-CONFIG_SENSORS_PMBUS=y
-CONFIG_SENSORS_UCD9000=y
-CONFIG_SENSORS_UCD9200=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_XILINX_PS_UART=y
-CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
-CONFIG_SERIO=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_CADENCE=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_XILINX=y
-CONFIG_SPI_ZYNQ_QSPI=y
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-# CONFIG_TEXTSEARCH is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UIO=y
-# CONFIG_UIO_AEC is not set
-# CONFIG_UIO_CIF is not set
-# CONFIG_UIO_DMEM_GENIRQ is not set
-# CONFIG_UIO_MF624 is not set
-# CONFIG_UIO_NETX is not set
-# CONFIG_UIO_PCI_GENERIC is not set
-CONFIG_UIO_PDRV_GENIRQ=y
-# CONFIG_UIO_PRUSS is not set
-# CONFIG_UIO_SERCOS3 is not set
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_XILINX=y
-CONFIG_USB_HID=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_OTG=y
-CONFIG_USB_OTG_FSM=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USB_ULPI_VIEWPORT=y
-CONFIG_USE_OF=y
-CONFIG_VEXPRESS_CONFIG=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VITESSE_PHY=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_CONSOLE_SLEEP=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XILINX_EMACLITE=y
-# CONFIG_XILINX_INTC is not set
-# CONFIG_XILINX_PR_DECOUPLER is not set
-CONFIG_XILINX_WATCHDOG=y
-CONFIG_XILINX_XADC=y
-CONFIG_XPS=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_ARMTHUMB=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_ALTERA_FREEZE_BRIDGE is not set
+# CONFIG_ALTERA_PR_IP_CORE is not set
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=1024
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y
+# CONFIG_ARCH_VEXPRESS_SPC is not set
+CONFIG_ARCH_ZYNQ=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GLOBAL_TIMER=y
+CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_PL172_MPMC is not set
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ARM_ZYNQ_CPUIDLE=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_AXI_DMAC is not set
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CADENCE_TTC_TIMER=y
+CONFIG_CADENCE_WATCHDOG=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_VERSATILE=y
+CONFIG_CLK_ICST=y
+CONFIG_CLK_SP810=y
+CONFIG_CLK_VEXPRESS_OSC=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_SI570=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+# CONFIG_CPUFREQ_DT is not set
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_NOMODESET=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_E1000E=y
+CONFIG_EDAC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_SUPPORT=y
+# CONFIG_EDAC_SYNOPSYS is not set
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_ELF_CORE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FB=y
+CONFIG_FB_CMDLINE=y
+# CONFIG_FB_XILINX is not set
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FPGA=y
+CONFIG_FPGA_BRIDGE=y
+# CONFIG_FPGA_DFL is not set
+# CONFIG_FPGA_MGR_ALTERA_CVP is not set
+# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
+# CONFIG_FPGA_MGR_ICE40_SPI is not set
+# CONFIG_FPGA_MGR_MACHXO2_SPI is not set
+# CONFIG_FPGA_MGR_MICROCHIP_SPI is not set
+# CONFIG_FPGA_MGR_XILINX_SPI is not set
+CONFIG_FPGA_MGR_ZYNQ_FPGA=y
+CONFIG_FPGA_REGION=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_ZYNQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAVE_SMP=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CADENCE=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_INPUT_VIVALDIFMAP=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_KCMP=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MACB=y
+# CONFIG_MACB_PCI is not set
+CONFIG_MACB_USE_HWSTAMP=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_STRIPPED is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+CONFIG_NLS=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+# CONFIG_OF_FPGA_REGION is not set
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PCI=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL_ZYNQ=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PL330_DMA=y
+# CONFIG_PL353_SMC is not set
+CONFIG_PLAT_VERSATILE=y
+CONFIG_PM=y
+CONFIG_PMBUS=y
+CONFIG_PM_CLK=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_R8169=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VEXPRESS is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_ZYNQ=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+CONFIG_SENSORS_PMBUS=y
+CONFIG_SENSORS_UCD9000=y
+CONFIG_SENSORS_UCD9200=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIO=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_CADENCE=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_XILINX=y
+CONFIG_SPI_ZYNQ_QSPI=y
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SRCU=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_TEXTSEARCH is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UIO=y
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_CIF is not set
+# CONFIG_UIO_DMEM_GENIRQ is not set
+# CONFIG_UIO_MF624 is not set
+# CONFIG_UIO_NETX is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_UIO_PRUSS is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_XILINX=y
+CONFIG_USB_HID=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USE_OF=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VITESSE_PHY=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XILINX_EMACLITE=y
+# CONFIG_XILINX_PR_DECOUPLER is not set
+CONFIG_XILINX_WATCHDOG=y
+CONFIG_XILINX_XADC=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
LLVM_VERSION := $(shell cat $(STAGING_DIR_HOST)/llvm-bpf/.llvm-version)
LLVM_BPF_PREFIX := llvm-bpf-$(LLVM_VERSION).$(HOST_OS)-$(HOST_ARCH)
-LLVM_TAR := $(BIN_DIR)/$(LLVM_BPF_PREFIX).tar.xz
+LLVM_TAR := $(BIN_DIR)/$(LLVM_BPF_PREFIX).tar.zst
$(LLVM_TAR): $(STAGING_DIR_HOST)/llvm-bpf/.llvm-version
tar -C $(STAGING_DIR_HOST) \
- -I '$(STAGING_DIR_HOST)/bin/xz -7e -T$(if $(filter 1,$(NPROC)),2,0)' \
+ -I '$(STAGING_DIR_HOST)/bin/zstd -T0 --ultra -20' \
$(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") \
-cf $@.tmp llvm-bpf $(LLVM_BPF_PREFIX)
mv $@.tmp $@
kernel/asm-offsets.s \
kernel/module.lds
+ifeq ($(LINUX_KARCH),powerpc)
+ KERNEL_FILES_ARCH += lib/crtsavres.o
+endif
+
KERNEL_FILES_BASE := \
.config \
Makefile \
all: compile
-$(BIN_DIR)/$(SDK_NAME).tar.xz: clean
+$(BIN_DIR)/$(SDK_NAME).tar.zst: clean
mkdir -p \
$(SDK_BUILD_DIR)/dl \
$(SDK_BUILD_DIR)/package \
find $(SDK_BUILD_DIR) -name .svn | $(XARGS) rm -rf
find $(SDK_BUILD_DIR) -name CVS | $(XARGS) rm -rf
-make -C $(SDK_BUILD_DIR)/scripts/config clean
+
(cd $(BUILD_DIR); \
- tar -I '$(STAGING_DIR_HOST)/bin/xz -7e -T$(if $(filter 1,$(NPROC)),2,0)' -cf $@ $(SDK_NAME) \
+ tar -I '$(STAGING_DIR_HOST)/bin/zstd -T0 --ultra -20' -cf $@ $(SDK_NAME) \
--mtime="$(shell date --date=@$(SOURCE_DATE_EPOCH))"; \
)
download:
prepare:
-compile: $(BIN_DIR)/$(SDK_NAME).tar.xz
+compile: $(BIN_DIR)/$(SDK_NAME).tar.zst
install: compile
clean:
- rm -rf $(SDK_BUILD_DIR) $(BIN_DIR)/$(SDK_NAME).tar.xz
+ rm -rf $(SDK_BUILD_DIR) $(BIN_DIR)/$(SDK_NAME).tar.zst
TOOLCHAIN_PREFIX:=$(TOOLCHAIN_BUILD_DIR)/toolchain-$(ARCH)$(ARCH_SUFFIX)_gcc-$(GCCV)$(DIR_SUFFIX)
-$(BIN_DIR)/$(TOOLCHAIN_NAME).tar.xz: clean
+$(BIN_DIR)/$(TOOLCHAIN_NAME).tar.zst: clean
mkdir -p $(TOOLCHAIN_BUILD_DIR)
$(TAR) -cf - -C $(TOPDIR)/staging_dir/ \
$(foreach exclude,$(EXCLUDE_DIRS),--exclude="$(exclude)") \
find $(TOOLCHAIN_BUILD_DIR) -name CVS | $(XARGS) rm -rf
mkdir -p $(BIN_DIR)
(cd $(BUILD_DIR); \
- tar -I '$(STAGING_DIR_HOST)/bin/xz -7e -T$(if $(filter 1,$(NPROC)),2,0)' -cf $@ $(TOOLCHAIN_NAME) \
+ tar -I '$(STAGING_DIR_HOST)/bin/zstd -T0 --ultra -20' -cf $@ $(TOOLCHAIN_NAME) \
--mtime="$(shell date --date=@$(SOURCE_DATE_EPOCH))"; \
)
download:
prepare:
-compile: $(BIN_DIR)/$(TOOLCHAIN_NAME).tar.xz
+compile: $(BIN_DIR)/$(TOOLCHAIN_NAME).tar.zst
install: compile
clean:
- rm -rf $(TOOLCHAIN_BUILD_DIR) $(BIN_DIR)/$(TOOLCHAIN_NAME).tar.xz
+ rm -rf $(TOOLCHAIN_BUILD_DIR) $(BIN_DIR)/$(TOOLCHAIN_NAME).tar.zst
default "arm-unknown-linux-gnu" if arm
default "armeb-unknown-linux-gnu" if armeb
default "i486-unknown-linux-gnu" if i386
+ default "loongarch64-unknown-linux-gnu" if loongarch64
default "mips-unknown-linux-gnu" if mips
default "mipsel-unknown-linux-gnu" if mipsel
default "powerpc-unknown-linux-gnu" if powerpc
default "arm-unknown-linux-gnu-" if arm
default "armeb-unknown-linux-gnu-" if armeb
default "i486-unknown-linux-gnu-" if i386
+ default "loongarch64-unknown-linux-gnu-" if loongarch64
default "mips-unknown-linux-gnu-" if mips
default "mipsel-unknown-linux-gnu-" if mipsel
default "powerpc-unknown-linux-gnu-" if powerpc
default "/opt/cross/arm-unknown-linux-gnu" if arm
default "/opt/cross/armeb-unknown-linux-gnu" if armeb
default "/opt/cross/i486-unknown-linux-gnu" if i386
+ default "/opt/cross/loongarch64-unknown-linux-gnu" if loongarch64
default "/opt/cross/mips-unknown-linux-gnu" if mips
default "/opt/cross/mipsel-unknown-linux-gnu" if mipsel
default "/opt/cross/powerpc-unknown-linux-gnu" if powerpc
choice
prompt "Binutils Version" if TOOLCHAINOPTS
- default BINUTILS_USE_VERSION_2_40
+ default BINUTILS_USE_VERSION_2_42
help
Select the version of binutils you wish to use.
bool
config BINUTILS_VERSION_2_40
- default y if !TOOLCHAINOPTS
bool
config BINUTILS_VERSION_2_41
bool
config BINUTILS_VERSION_2_42
+ default y if !TOOLCHAINOPTS
bool
config BINUTILS_VERSION
config GCC_USE_VERSION_13
bool "gcc 13.x"
-endchoice
-config GCC_USE_DEFAULT_VERSION
- bool
- default y if !TOOLCHAINOPTS || GCC_USE_VERSION_13
- imply KERNEL_WERROR
+ config GCC_USE_VERSION_14
+ bool "gcc 14.x"
+endchoice
config GCC_USE_GRAPHITE
bool
default y if GCC_USE_VERSION_12
bool
+config GCC_VERSION_14
+ default y if GCC_USE_VERSION_14
+ bool
+
config GCC_VERSION
string
default EXTERNAL_GCC_VERSION if EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN
default "11.3.0" if GCC_VERSION_11
default "12.3.0" if GCC_VERSION_12
+ default "14.1.0" if GCC_VERSION_14
default "13.2.0"
+
+config GCC_USE_DEFAULT_VERSION
+ bool
+ default y if !TOOLCHAINOPTS || GCC_USE_VERSION_13
+ imply KERNEL_WERROR
PKG_HASH:=e275e76442a6067341a27f04c5c6b83d8613144004c0413528863dc6b5c743da
endif
+ifeq ($(PKG_VERSION),14.1.0)
+ PKG_HASH:=e283c654987afe3de9d8080bc0bd79534b5ca0d681a73a11ff2b5d3767426840
+endif
+
PATCH_DIR=../patches-$(GCC_MAJOR_VERSION).x
BUGURL=http://bugs.openwrt.org/
--- /dev/null
+From a80c68a08604b0ac625ac7fc59eae40b551b1176 Mon Sep 17 00:00:00 2001
+From: Peng Fan <fanpeng@loongson.cn>
+Date: Wed, 19 Apr 2023 16:23:42 +0800
+Subject: [PATCH] LoongArch: Fix MUSL_DYNAMIC_LINKER
+
+The system based on musl has no '/lib64', so change it.
+
+https://wiki.musl-libc.org/guidelines-for-distributions.html,
+"Multilib/multi-arch" section of this introduces it.
+
+gcc/
+ * config/loongarch/gnu-user.h (MUSL_DYNAMIC_LINKER): Redefine.
+
+Signed-off-by: Peng Fan <fanpeng@loongson.cn>
+Suggested-by: Xi Ruoyao <xry111@xry111.site>
+---
+ gcc/config/loongarch/gnu-user.h | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h
+index aecaa02a199..fa1a5211419 100644
+--- a/gcc/config/loongarch/gnu-user.h
++++ b/gcc/config/loongarch/gnu-user.h
+@@ -33,9 +33,14 @@ along with GCC; see the file COPYING3. If not see
+ #define GLIBC_DYNAMIC_LINKER \
+ "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1"
+
++#define MUSL_ABI_SPEC \
++ "%{mabi=lp64d:-lp64d}" \
++ "%{mabi=lp64f:-lp64f}" \
++ "%{mabi=lp64s:-lp64s}"
++
+ #undef MUSL_DYNAMIC_LINKER
+ #define MUSL_DYNAMIC_LINKER \
+- "/lib" ABI_GRLEN_SPEC "/ld-musl-loongarch-" ABI_SPEC ".so.1"
++ "/lib/ld-musl-loongarch" ABI_GRLEN_SPEC MUSL_ABI_SPEC ".so.1"
+
+ #undef GNU_USER_TARGET_LINK_SPEC
+ #define GNU_USER_TARGET_LINK_SPEC \
+--
+2.39.3
--- /dev/null
+From 8bccee51f0deac64b79cd9ad75df599422f4c8ff Mon Sep 17 00:00:00 2001
+From: Lulu Cheng <chenglulu@loongson.cn>
+Date: Sat, 18 Nov 2023 11:04:42 +0800
+Subject: [PATCH] LoongArch: Modify MUSL_DYNAMIC_LINKER.
+
+Use no suffix at all in the musl dynamic linker name for hard
+float ABI. Use -sf and -sp suffixes in musl dynamic linker name
+for soft float and single precision ABIs. The following table
+outlines the musl interpreter names for the LoongArch64 ABI names.
+
+musl interpreter | LoongArch64 ABI
+--------------------------- | -----------------
+ld-musl-loongarch64.so.1 | loongarch64-lp64d
+ld-musl-loongarch64-sp.so.1 | loongarch64-lp64f
+ld-musl-loongarch64-sf.so.1 | loongarch64-lp64s
+
+gcc/ChangeLog:
+
+ * config/loongarch/gnu-user.h (MUSL_ABI_SPEC): Modify suffix.
+---
+ gcc/config/loongarch/gnu-user.h | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h
+index 9616d6e8a0b..e9f4bcef1d4 100644
+--- a/gcc/config/loongarch/gnu-user.h
++++ b/gcc/config/loongarch/gnu-user.h
+@@ -34,9 +34,9 @@ along with GCC; see the file COPYING3. If not see
+ "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1"
+
+ #define MUSL_ABI_SPEC \
+- "%{mabi=lp64d:-lp64d}" \
+- "%{mabi=lp64f:-lp64f}" \
+- "%{mabi=lp64s:-lp64s}"
++ "%{mabi=lp64d:}" \
++ "%{mabi=lp64f:-sp}" \
++ "%{mabi=lp64s:-sf}"
+
+ #undef MUSL_DYNAMIC_LINKER
+ #define MUSL_DYNAMIC_LINKER \
+--
+2.39.3
+
--- /dev/null
+commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun Oct 19 21:45:51 2014 +0000
+
+ gcc: do not assume that the Mac OS X filesystem is case insensitive
+
+ Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+
+ SVN-Revision: 42973
+
+--- a/include/filenames.h
++++ b/include/filenames.h
+@@ -44,11 +44,6 @@ extern "C" {
+ # define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c)
+ # define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f)
+ #else /* not DOSish */
+-# if defined(__APPLE__)
+-# ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM
+-# define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1
+-# endif
+-# endif /* __APPLE__ */
+ # define HAS_DRIVE_SPEC(f) (0)
+ # define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c)
+ # define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f)
--- /dev/null
+--- a/gcc/real.h
++++ b/gcc/real.h
+@@ -77,8 +77,10 @@ struct GTY(()) real_value {
+ + (REAL_VALUE_TYPE_SIZE%HOST_BITS_PER_WIDE_INT ? 1 : 0)) /* round up */
+
+ /* Verify the guess. */
++#ifndef __LP64__
+ extern char test_real_width
+ [sizeof (REAL_VALUE_TYPE) <= REAL_WIDTH * sizeof (HOST_WIDE_INT) ? 1 : -1];
++#endif
+
+ /* Calculate the format for CONST_DOUBLE. We need as many slots as
+ are necessary to overlay a REAL_VALUE_TYPE on them. This could be
--- /dev/null
+commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2
+Author: Luka Perkov <luka@openwrt.org>
+Date: Tue Feb 26 16:16:33 2013 +0000
+
+ gcc: don't build documentation
+
+ This closes #13039.
+
+ Signed-off-by: Luka Perkov <luka@openwrt.org>
+
+ SVN-Revision: 35807
+
+--- a/gcc/Makefile.in
++++ b/gcc/Makefile.in
+@@ -3549,18 +3549,10 @@ doc/gcc.info: $(TEXI_GCC_FILES)
+ doc/gccint.info: $(TEXI_GCCINT_FILES)
+ doc/cppinternals.info: $(TEXI_CPPINT_FILES)
+
+-doc/%.info: %.texi
+- if [ x$(BUILD_INFO) = xinfo ]; then \
+- $(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \
+- -I $(gcc_docdir)/include -o $@ $<; \
+- fi
++doc/%.info:
+
+ # Duplicate entry to handle renaming of gccinstall.info
+-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES)
+- if [ x$(BUILD_INFO) = xinfo ]; then \
+- $(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \
+- -I $(gcc_docdir)/include -o $@ $<; \
+- fi
++doc/gccinstall.info:
+
+ doc/cpp.dvi: $(TEXI_CPP_FILES)
+ doc/gcc.dvi: $(TEXI_GCC_FILES)
--- /dev/null
+Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.
+MIPS16 functions have a static assembler prologue which clobbers
+registers v0 and v1. Add these register clobbers to function call
+instructions.
+
+--- a/gcc/config/mips/mips.cc
++++ b/gcc/config/mips/mips.cc
+@@ -3227,6 +3227,12 @@ mips_emit_call_insn (rtx pattern, rtx or
+ emit_insn (gen_update_got_version ());
+ }
+
++ if (TARGET_MIPS16 && TARGET_USE_GOT)
++ {
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);
++ clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));
++ }
++
+ if (TARGET_MIPS16
+ && TARGET_EXPLICIT_RELOCS
+ && TARGET_CALL_CLOBBERED_GP)
--- /dev/null
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -985,7 +985,9 @@ proper position among the other output f
+ #endif
+
+ #ifndef LINK_SSP_SPEC
+-#ifdef TARGET_LIBC_PROVIDES_SSP
++#if DEFAULT_LIBC == LIBC_MUSL
++#define LINK_SSP_SPEC "-lssp_nonshared"
++#elif defined(TARGET_LIBC_PROVIDES_SSP)
+ #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
+ "|fstack-protector-strong|fstack-protector-explicit:}"
+ #else
--- /dev/null
+commit ecf7671b769fe96f7b5134be442089f8bdba55d2
+Author: Felix Fietkau <nbd@nbd.name>
+Date: Thu Aug 4 20:29:45 2016 +0200
+
+gcc: add a patch to generate better code with Os on mips
+
+Also happens to reduce compressed code size a bit
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+
+--- a/gcc/config/mips/mips.cc
++++ b/gcc/config/mips/mips.cc
+@@ -20444,7 +20444,7 @@ mips_option_override (void)
+ flag_pcc_struct_return = 0;
+
+ /* Decide which rtx_costs structure to use. */
+- if (optimize_size)
++ if (0 && optimize_size)
+ mips_cost = &mips_rtx_cost_optimize_size;
+ else
+ mips_cost = &mips_rtx_cost_data[mips_tune];
--- /dev/null
+commit 8570c4be394cff7282f332f97da2ff569a927ddb
+Author: Imre Kaloz <kaloz@openwrt.org>
+Date: Wed Feb 2 20:06:12 2011 +0000
+
+ fixup arm soft-float symbols
+
+ SVN-Revision: 25325
+
+--- a/libgcc/config/arm/t-linux
++++ b/libgcc/config/arm/t-linux
+@@ -1,6 +1,10 @@
+ LIB1ASMSRC = arm/lib1funcs.S
+ LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \
+- _ctzsi2 _arm_addsubdf3 _arm_addsubsf3
++ _ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \
++ _arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \
++ _arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \
++ _arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \
++ _arm_fixsfsi _arm_fixunssfsi
+
+ # Just for these, we omit the frame pointer since it makes such a big
+ # difference.
+--- a/gcc/config/arm/linux-elf.h
++++ b/gcc/config/arm/linux-elf.h
+@@ -58,8 +58,6 @@
+ %{shared:-lc} \
+ %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
+
+-#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
+-
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #define LINUX_TARGET_LINK_SPEC "%{h*} \
--- /dev/null
+commit c96312958c0621e72c9b32da5bc224ffe2161384
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Mon Oct 19 23:26:09 2009 +0000
+
+ gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow)
+
+ SVN-Revision: 18086
+
+--- a/libgcc/Makefile.in
++++ b/libgcc/Makefile.in
+@@ -940,11 +940,12 @@ $(libgcov-driver-objects): %$(objext): $
+
+ # Static libraries.
+ libgcc.a: $(libgcc-objects)
++libgcc_pic.a: $(libgcc-s-objects)
+ libgcov.a: $(libgcov-objects)
+ libunwind.a: $(libunwind-objects)
+ libgcc_eh.a: $(libgcc-eh-objects)
+
+-libgcc.a libgcov.a libunwind.a libgcc_eh.a:
++libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a:
+ -rm -f $@
+
+ objects="$(objects)"; \
+@@ -968,7 +969,7 @@ all: libunwind.a
+ endif
+
+ ifeq ($(enable_shared),yes)
+-all: libgcc_eh.a libgcc_s$(SHLIB_EXT)
++all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT)
+ ifneq ($(LIBUNWIND),)
+ all: libunwind$(SHLIB_EXT)
+ libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT)
+@@ -1174,6 +1175,10 @@ install-shared:
+ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a
+ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a
+
++ $(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/
++ chmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a
++ $(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a
++
+ $(subst @multilib_dir@,$(MULTIDIR),$(subst \
+ @shlib_base_name@,libgcc_s,$(subst \
+ @shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL))))
--- /dev/null
+commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc
+Author: Imre Kaloz <kaloz@openwrt.org>
+Date: Wed Feb 2 19:34:36 2011 +0000
+
+ add armv4 fixup patches
+
+ SVN-Revision: 25322
+
+
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -88,10 +88,15 @@
+ #define MUSL_DYNAMIC_LINKER \
+ "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1"
+
++/* For armv4 we pass --fix-v4bx to linker to support EABI */
++#undef TARGET_FIX_V4BX_SPEC
++#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\
++ "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
++
+ /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
+ use the GNU/Linux version, not the generic BPABI version. */
+ #undef LINK_SPEC
+-#define LINK_SPEC EABI_LINK_SPEC \
++#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC \
+ LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC, \
+ LINUX_TARGET_LINK_SPEC " " ANDROID_LINK_SPEC)
+
--- /dev/null
+commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun Feb 12 20:25:47 2012 +0000
+
+ gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary
+
+ SVN-Revision: 30486
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -129,10 +129,6 @@
+ "%{Ofast|ffast-math|funsafe-math-optimizations:%{!shared:crtfastmath.o%s}} " \
+ LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC)
+
+-/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we
+- do not use -lfloat. */
+-#undef LIBGCC_SPEC
+-
+ /* Clear the instruction cache from `beg' to `end'. This is
+ implemented in lib1funcs.S, so ensure an error if this definition
+ is used. */
+--- a/gcc/config/linux.h
++++ b/gcc/config/linux.h
+@@ -58,6 +58,10 @@ see the files COPYING3 and COPYING.RUNTI
+ builtin_assert ("system=posix"); \
+ } while (0)
+
++#ifndef LIBGCC_SPEC
++#define LIBGCC_SPEC "%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}"
++#endif
++
+ /* Determine which dynamic linker to use depending on whether GLIBC or
+ uClibc or Bionic or musl is the default C library and whether
+ -muclibc or -mglibc or -mbionic or -mmusl has been passed to change
+--- a/libgcc/mkmap-symver.awk
++++ b/libgcc/mkmap-symver.awk
+@@ -136,5 +136,5 @@ function output(lib) {
+ else if (inherit[lib])
+ printf("} %s;\n", inherit[lib]);
+ else
+- printf ("\n local:\n\t*;\n};\n");
++ printf ("\n\t*;\n};\n");
+ }
+--- a/gcc/config/rs6000/linux.h
++++ b/gcc/config/rs6000/linux.h
+@@ -70,6 +70,9 @@
+ #undef CPP_OS_DEFAULT_SPEC
+ #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)"
+
++#undef LIBGCC_SPEC
++#define LIBGCC_SPEC "%{!static:%{!static-libgcc:-lgcc_s}} -lgcc"
++
+ #undef LINK_SHLIB_SPEC
+ #define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}} \
+ %{static-pie:-static -pie --no-dynamic-linker -z text}"
--- /dev/null
+commit 64661de100da1ec1061ef3e5e400285dce115e6b
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Sun May 10 13:16:35 2015 +0000
+
+ gcc: add some size optimization patches
+
+ Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+
+ SVN-Revision: 45664
+
+--- a/libgcc/config/t-libunwind
++++ b/libgcc/config/t-libunwind
+@@ -2,8 +2,7 @@
+
+ HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER
+
+-LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \
+- $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c
++LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
+ LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c
+
+ # Override the default value from t-slibgcc-elf-ver and mention -lunwind
--- /dev/null
+--- a/gcc/config/rs6000/rs6000-logue.cc
++++ b/gcc/config/rs6000/rs6000-logue.cc
+@@ -344,7 +344,7 @@ rs6000_savres_strategy (rs6000_stack_t *
+ /* Define cutoff for using out-of-line functions to save registers. */
+ if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
+ {
+- if (!optimize_size)
++ if (1)
+ {
+ strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
+ strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
--- /dev/null
+--- a/libgcc/crtstuff.c
++++ b/libgcc/crtstuff.c
+@@ -152,7 +152,7 @@ call_ ## FUNC (void) \
+ #endif
+
+ #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF)
+-# define USE_TM_CLONE_REGISTRY 1
++# define USE_TM_CLONE_REGISTRY 0
+ #elif !defined(USE_TM_CLONE_REGISTRY)
+ # define USE_TM_CLONE_REGISTRY 0
+ #endif
--- /dev/null
+--- a/libgcc/config/mips/t-mips16
++++ b/libgcc/config/mips/t-mips16
+@@ -42,3 +42,6 @@ SYNC_CFLAGS = -mno-mips16
+
+ # Version these symbols if building libgcc.so.
+ SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver
++
++CRTSTUFF_T_CFLAGS += -mno-mips16
++CRTSTUFF_T_CFLAGS_S += -mno-mips16
--- /dev/null
+commit 99368862e44740ff4fd33760893f04e14f9dbdf1
+Author: Felix Fietkau <nbd@openwrt.org>
+Date: Tue Jul 31 00:52:27 2007 +0000
+
+ Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly
+
+ SVN-Revision: 8256
+
+ This patch brings over a feature from MirBSD:
+ * -fhonour-copts
+ If this option is not given, it's warned (depending
+ on environment variables). This is to catch errors
+ of misbuilt packages which override CFLAGS themselves.
+
+ This patch was authored by Thorsten Glaser <tg at mirbsd.de>
+ with copyright assignment to the FSF in effect.
+
+--- a/gcc/c-family/c-opts.cc
++++ b/gcc/c-family/c-opts.cc
+@@ -108,6 +108,9 @@ static size_t include_cursor;
+ /* Whether any standard preincluded header has been preincluded. */
+ static bool done_preinclude;
+
++/* Check if a port honours COPTS. */
++static int honour_copts = 0;
++
+ static void handle_OPT_d (const char *);
+ static void set_std_cxx98 (int);
+ static void set_std_cxx11 (int);
+@@ -498,6 +501,12 @@ c_common_handle_option (size_t scode, co
+ flag_no_builtin = !value;
+ break;
+
++ case OPT_fhonour_copts:
++ if (c_language == clk_c) {
++ honour_copts++;
++ }
++ break;
++
+ case OPT_fconstant_string_class_:
+ constant_string_class_name = arg;
+ break;
+@@ -1291,6 +1300,47 @@ c_common_init (void)
+ return false;
+ }
+
++ if (c_language == clk_c) {
++ char *ev = getenv ("GCC_HONOUR_COPTS");
++ int evv;
++ if (ev == NULL)
++ evv = -1;
++ else if ((*ev == '0') || (*ev == '\0'))
++ evv = 0;
++ else if (*ev == '1')
++ evv = 1;
++ else if (*ev == '2')
++ evv = 2;
++ else if (*ev == 's')
++ evv = -1;
++ else {
++ warning (0, "unknown GCC_HONOUR_COPTS value, assuming 1");
++ evv = 1; /* maybe depend this on something like MIRBSD_NATIVE? */
++ }
++ if (evv == 1) {
++ if (honour_copts == 0) {
++ error ("someone does not honour COPTS at all in lenient mode");
++ return false;
++ } else if (honour_copts != 1) {
++ warning (0, "someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ }
++ } else if (evv == 2) {
++ if (honour_copts == 0) {
++ error ("someone does not honour COPTS at all in strict mode");
++ return false;
++ } else if (honour_copts != 1) {
++ error ("someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ return false;
++ }
++ } else if (evv == 0) {
++ if (honour_copts != 1)
++ inform (UNKNOWN_LOCATION, "someone does not honour COPTS correctly, passed %d times",
++ honour_copts);
++ }
++ }
++
+ return true;
+ }
+
+--- a/gcc/c-family/c.opt
++++ b/gcc/c-family/c.opt
+@@ -1910,6 +1910,9 @@ C++ ObjC++ Optimization Alias(fexception
+ fhonor-std
+ C++ ObjC++ WarnRemoved
+
++fhonour-copts
++C ObjC C++ ObjC++ RejectNegative
++
+ fhosted
+ C ObjC
+ Assume normal C execution environment.
+--- a/gcc/common.opt
++++ b/gcc/common.opt
+@@ -1881,6 +1881,9 @@ Enum(hardcfr_check_noreturn_calls) Strin
+ EnumValue
+ Enum(hardcfr_check_noreturn_calls) String(always) Value(HCFRNR_ALWAYS)
+
++fhonour-copts
++Common RejectNegative
++
+ ; Nonzero means ignore `#ident' directives. 0 means handle them.
+ ; Generate position-independent code for executables if possible
+ ; On SVR4 targets, it also controls whether or not to emit a
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -10597,6 +10597,17 @@ This option is only supported for C and
+
+ This warning is upgraded to an error by @option{-pedantic-errors}.
+
++@item -fhonour-copts
++@opindex fhonour-copts
++If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not
++given at least once, and warn if it is given more than once.
++If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not
++given exactly once.
++If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option
++is not given exactly once.
++The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}.
++This flag and environment variable only affect the C language.
++
+ @opindex Wstack-protector
+ @opindex Wno-stack-protector
+ @item -Wstack-protector
+--- a/gcc/opts.cc
++++ b/gcc/opts.cc
+@@ -2833,6 +2833,9 @@ common_handle_option (struct gcc_options
+ add_comma_separated_to_vector (&opts->x_flag_ignored_attributes, arg);
+ break;
+
++ case OPT_fhonour_copts:
++ break;
++
+ case OPT_Werror:
+ dc->set_warning_as_error_requested (value);
+ break;
--- /dev/null
+Author: Jo-Philipp Wich <jow@openwrt.org>
+Date: Sat Apr 21 03:02:39 2012 +0000
+
+ gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset
+
+ SVN-Revision: 31390
+
+--- a/gcc/gcc.cc
++++ b/gcc/gcc.cc
+@@ -10319,8 +10319,10 @@ getenv_spec_function (int argc, const ch
+ }
+
+ if (!value)
+- fatal_error (input_location,
+- "environment variable %qs not defined", varname);
++ {
++ warning (input_location, "environment variable %qs not defined", varname);
++ value = "";
++ }
+
+ /* We have to escape every character of the environment variable so
+ they are not interpreted as active spec characters. A
--- /dev/null
+From dda6b050cd74a352670787a294596a9c56c21327 Mon Sep 17 00:00:00 2001
+From: Yousong Zhou <yszhou4tech@gmail.com>
+Date: Fri, 4 May 2018 18:20:53 +0800
+Subject: [PATCH] gotools: fix compilation when making cross compiler
+
+libgo is "the runtime support library for the Go programming language.
+This library is intended for use with the Go frontend."
+
+gccgo will link target files with libgo.so which depends on libgcc_s.so.1, but
+the linker will complain that it cannot find it. That's because shared libgcc
+is not present in the install directory yet. libgo.so was made without problem
+because gcc will emit -lgcc_s when compiled with -shared option. When gotools
+were being made, it was supplied with -static-libgcc thus no link option was
+provided. Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec
+for linking with libgo.so
+
+- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation
+- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html
+
+When 3-pass GCC compilation is used, shared libgcc runtime libraries will be
+available after gcc pass2 completed and will meet the gotools link requirement
+at gcc pass3
+---
+ gotools/Makefile.am | 4 +++-
+ gotools/Makefile.in | 4 +++-
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/gotools/Makefile.am
++++ b/gotools/Makefile.am
+@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+
+ libgodir = ../$(target_noncanonical)/libgo
++libgccdir = ../$(target_noncanonical)/libgcc
+ LIBGODEP = $(libgodir)/libgo.la
+
+ LIBGOTOOL = $(libgodir)/libgotool.a
+@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+
+ AM_GOCFLAGS = -I $(libgodir)
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \
++ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s
+ GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+
+ libgosrcdir = $(srcdir)/../libgo/go
+--- a/gotools/Makefile.in
++++ b/gotools/Makefile.in
+@@ -337,6 +337,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd
+ PWD_COMMAND = $${PWDCMD-pwd}
+ STAMP = echo timestamp >
+ libgodir = ../$(target_noncanonical)/libgo
++libgccdir = ../$(target_noncanonical)/libgcc
+ LIBGODEP = $(libgodir)/libgo.la
+ LIBGOTOOL = $(libgodir)/libgotool.a
+ @NATIVE_FALSE@GOCOMPILER = $(GOC)
+@@ -346,7 +347,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a
+ GOCFLAGS = $(CFLAGS_FOR_TARGET)
+ GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)
+ AM_GOCFLAGS = -I $(libgodir)
+-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs
++AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \
++ -L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s
+ GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@
+ libgosrcdir = $(srcdir)/../libgo/go
+ cmdsrcdir = $(libgosrcdir)/cmd
--- /dev/null
+commit 9c6e71079b46ad5433165feaa2001450f2017b56
+Author: Przemysław Buczkowski <prem@prem.moe>
+Date: Mon Aug 16 13:16:21 2021 +0100
+
+ GCC: Patch for Apple Silicon compatibility
+
+ This patch fixes a linker error occuring when compiling
+ the cross-compiler on macOS and ARM64 architecture.
+
+ Adapted from:
+ https://github.com/richfelker/musl-cross-make/issues/116#issuecomment-823612404
+
+ Change-Id: Ia3ee98a163bbb62689f42e2da83a5ef36beb0913
+ Reviewed-on: https://review.haiku-os.org/c/buildtools/+/4329
+ Reviewed-by: John Scipione <jscipione@gmail.com>
+ Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
+
+--- a/gcc/config/aarch64/aarch64.h
++++ b/gcc/config/aarch64/aarch64.h
+@@ -1410,7 +1410,7 @@ extern enum aarch64_code_model aarch64_c
+
+ /* Extra specs when building a native AArch64-hosted compiler.
+ Option rewriting rules based on host system. */
+-#if defined(__aarch64__)
++#if defined(__aarch64__) && ! defined(__APPLE__)
+ extern const char *host_detect_local_cpu (int argc, const char **argv);
+ #define HAVE_LOCAL_CPU_DETECT
+ # define EXTRA_SPEC_FUNCTIONS \
+--- a/gcc/config/host-darwin.cc
++++ b/gcc/config/host-darwin.cc
+@@ -23,6 +23,8 @@
+ #include "options.h"
+ #include "diagnostic-core.h"
+ #include "config/host-darwin.h"
++#include "hosthooks.h"
++#include "hosthooks-def.h"
+ #include <errno.h>
+
+ /* For Darwin (macOS only) platforms, without ASLR (PIE) enabled on the
+@@ -181,3 +183,5 @@ darwin_gt_pch_use_address (void *&addr,
+
+ return 1;
+ }
++
++const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;
include $(TOPDIR)/rules.mk
PKG_NAME:=glibc
-PKG_VERSION:=2.37
+PKG_VERSION:=2.38
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
-PKG_SOURCE_VERSION:=eee7525d35ec16bbe81435e41079ab72519d825c
-PKG_MIRROR_HASH:=fad5a67d9622b75bce5e3e8c91b07a6df0bf8b21cb001a6d06019a6ce4cff31f
+PKG_SOURCE_VERSION:=e9f05fa1c62c8044ff025963498063f73eb51c5f
+PKG_MIRROR_HASH:=fd61eb2caea0d4100638b8aa8285b0f1bc23af921c376516307c9ab8ac307739
PKG_SOURCE_URL:=https://sourceware.org/git/glibc.git
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.xz
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.zst
PKG_CPE_ID:=cpe:/a:gnu:glibc
HOST_BUILD_DIR:=$(BUILD_DIR_TOOLCHAIN)/$(PKG_SOURCE_SUBDIR)
--without-gd \
--without-cvs \
--enable-add-ons \
+ --enable-crypt \
--$(if $(CONFIG_SOFT_FLOAT),without,with)-fp \
$(if $(CONFIG_PKG_CC_STACKPROTECTOR_REGULAR),--enable-stack-protector=yes) \
$(if $(CONFIG_PKG_CC_STACKPROTECTOR_STRONG),--enable-stack-protector=strong) \
$(if $(CONFIG_PKG_CC_STACKPROTECTOR_ALL),--enable-stack-protector=all) \
$(if $(CONFIG_PKG_RELRO_FULL),--enable-bind-now) \
+ $(if $(CONFIG_PKG_FORTIFY_SOURCE_1),--enable-fortify-source=1) \
+ $(if $(CONFIG_PKG_FORTIFY_SOURCE_2),--enable-fortify-source=2) \
--enable-kernel=5.15.0
export libc_cv_ssp=no
int totfails = 0;
int main (int argc, char *argv[]);
-@@ -119,13 +103,3 @@ put8 (char *cp)
+@@ -123,13 +107,3 @@ put8 (char *cp)
printf("%02x", t);
}
}
* Encode Binary Data:: Encoding and Decoding of Binary Data.
* Argz and Envz Vectors:: Null-separated string vectors.
@end menu
-@@ -2423,73 +2423,73 @@ functionality under a different name, su
+@@ -2512,73 +2512,73 @@ functionality under a different name, su
systems it may be in @file{strings.h} instead.
@end deftypefun
range [FROM - N + 1, FROM - 1]. If N is odd the first byte in FROM
--- a/stdlib/stdlib.h
+++ b/stdlib/stdlib.h
-@@ -984,6 +984,12 @@ extern int getsubopt (char **__restrict
+@@ -1103,6 +1103,12 @@ extern int getsubopt (char **__restrict
#endif
--- a/Makeconfig
+++ b/Makeconfig
-@@ -631,6 +631,9 @@ else
+@@ -632,6 +632,9 @@ else
default-rpath = $(libdir)
endif
include $(INCLUDE_DIR)/target.mk
PKG_NAME:=musl
-PKG_VERSION:=1.2.4
+PKG_VERSION:=1.2.5
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://musl.libc.org/releases/
-PKG_HASH:=7a35eae33d5372a7c0da1188de798726f68825513b7ae3ebe97aaaa52114f039
+PKG_HASH:=a9a118bbe84d8764da0ea0d28b3ab3fae8477fc7e4085d90102b8596fc7c75e4
PKG_CPE_ID:=cpe:/a:musl-libc:musl
LIBC_SO_VERSION:=$(PKG_VERSION)
--- /dev/null
+--- a/Makefile
++++ b/Makefile
+@@ -218,6 +218,7 @@ $(DESTDIR)$(includedir)/%: $(srcdir)/inc
+
+ $(DESTDIR)$(LDSO_PATHNAME): $(DESTDIR)$(libdir)/libc.so
+ $(INSTALL) -D -l libc.so $@ || true
++ $(if $(filter loongarch64,$(ARCH)$(SUBARCH)),$(INSTALL) -D -l libc.so $(subst $(ARCH)$(SUBARCH).so.1,loongarch-lp64d.so.1,$@) || true)
+
+ install-libs: $(ALL_LIBS:lib/%=$(DESTDIR)$(libdir)/%) $(if $(SHARED_LIBS),$(DESTDIR)$(LDSO_PATHNAME),)
+
"ucs2\0\0\314"
+#ifdef FULL_ICONV
"eucjp\0\0\320"
- "shiftjis\0sjis\0\0\321"
+ "shiftjis\0sjis\0cp932\0\0\321"
"iso2022jp\0\0\322"
@@ -56,6 +57,7 @@ static const unsigned char charmaps[] =
"gb2312\0\0\332"
PKG_SOURCE_URL:=https://www.nasm.us/pub/nasm/releasebuilds/$(PKG_VERSION)/
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_HASH:=c77745f4802375efeee2ec5c0ad6b7f037ea9c87c92b149a9637ff099f162558
-PKG_CPE_ID:=cpe:/a:nasm:nasm
+PKG_CPE_ID:=cpe:/a:nasm:netwide_assembler
HOST_BUILD_PARALLEL:=1
endef
+define Host/SetToolchainInfo
+ if [ -f $(CONFIG_TOOLCHAIN_ROOT)/info.mk ]; then \
+ $(CP) $(CONFIG_TOOLCHAIN_ROOT)/info.mk $(TOOLCHAIN_DIR)/; \
+ else \
+ $(SED) 's,GCC_VERSION=.*,GCC_VERSION=$(CONFIG_GCC_VERSION),' $(TOOLCHAIN_DIR)/info.mk; \
+ fi
+endef
+
define Host/Prepare
$(call toolchain_test,CONFIG_SOFT_FLOAT,softfloat)
$(call toolchain_test,CONFIG_IPV6,ipv6)
define Host/Install
$(call toolchain_util,--wrap "$(TOOLCHAIN_DIR)/bin")
+ $(call Host/SetToolchainInfo)
endef
define Host/Clean
rm -rf $(TOOLCHAIN_DIR)/bin
+ rm -rf $(TOOLCHAIN_DIR)/info.mk
endef
$(eval $(call HostBuild))
--- /dev/null
+--- a/src/files.c
++++ b/src/files.c
+@@ -560,9 +560,9 @@ pkgdatadir (void)
+ char const *
+ m4path (void)
+ {
+- char const *m4 = getenv ("M4");
++ char const *m4 = getenv ("STAGING_DIR_HOST");
+ if (m4)
+- return m4;
++ return strcat(getenv ("STAGING_DIR_HOST"), "/bin/m4");
+
+ /* We don't use relocate2() to store the temporary buffer and re-use
+ it, because m4path() is only called once. */
+--- a/src/getargs.c
++++ b/src/getargs.c
+@@ -373,11 +373,13 @@ usage (int status)
+ A --long option is required.
+ Otherwise, add exceptions to ../build-aux/cross-options.pl. */
+
+- printf (_("Usage: %s [OPTION]... FILE\n"), program_name);
++ printf (_("Usage: STAGING_DIR_HOST=... %s [OPTION]... FILE\n"), program_name);
+ fputs (_("\
+ Generate a deterministic LR or generalized LR (GLR) parser employing\n\
+ LALR(1), IELR(1), or canonical LR(1) parser tables.\n\
+ \n\
++Environment Variable STAGING_DIR_HOST controls path to m4\n\
++\n\
+ "), stdout);
+
+ fputs (_("\
+@@ -450,6 +452,11 @@ Output Files:\n\
+ -M, --file-prefix-map=OLD=NEW replace prefix OLD with NEW when writing file paths\n\
+ in output files\n\
+ "), stdout);
++
++ fputs (_("\
++Environment Variables:\n\
++ STAGING_DIR_HOST Path to m4 is [STAGING_DIR_HOST]/bin/m4\n\
++"), stdout);
+ putc ('\n', stdout);
+
+ argmatch_report_usage (stdout);
PKG_NAME:=coreutils
PKG_CPE_ID:=cpe:/a:gnu:coreutils
-PKG_VERSION:=9.3
+PKG_VERSION:=9.5
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=@GNU/coreutils
-PKG_HASH:=a33d2c0bc49be3c79a4794944dcd87103bf497b53a14bafcd431c8ca53975252
+PKG_HASH:=767ae6a22950ec42f3ba5f7c1de79dd27800ee8e9b8642da5dedb5974a1741e5
HOST_BUILD_PARALLEL := 1
export GNULIB_SRCDIR:=$(HOST_GNULIB_SRCDIR)
+HOST_GNULIB_SKIP := \
+ lib/nstrftime.c \
+ lib/fprintftime.c \
+ lib/locale.in.h
+
HOST_CONFIGURE_ARGS += \
+ --disable-year2038 \
--enable-install-program=$(subst $(space),$(comma),$(strip $(PKG_PROGRAMS)))
HOST_MAKE_FLAGS += \
define Host/Configure
$(if $(QUILT),$(call Host/Bootstrap))
- -$(CP) $(HOST_BUILD_DIR)/lib/time.in.h~ $(HOST_BUILD_DIR)/lib/time.in.h # @GNULIB_TIME@ not defined
+ $(foreach src,$(HOST_GNULIB_SKIP),mv -f $(HOST_BUILD_DIR)/$(src)~ $(HOST_BUILD_DIR)/$(src) || true; )
$(call Host/Configure/Default)
endef
--- a/bootstrap
+++ b/bootstrap
-@@ -278,7 +278,7 @@ check_exists() {
+@@ -244,7 +244,7 @@ check_exists() {
($2 --version </dev/null)
fi
else
fi
test $? -lt 126
-@@ -563,7 +563,7 @@ p
+@@ -309,7 +309,7 @@ p
q'
get_version() {
$app --version >/dev/null 2>&1 || { $app --version; return 1; }
-@@ -620,13 +620,13 @@ check_versions() {
+@@ -366,13 +366,13 @@ check_versions() {
if [ "$req_ver" = "-" ]; then
# Merely require app to exist; not all prereq apps are well-behaved
# so we have to rely on $? rather than get_version.
if [ ! "$inst_ver" ]; then
warn_ "Error: '$app' not found"
ret=1
-@@ -923,7 +923,7 @@ version_controlled_file() {
- # two just-pre-run programs.
+@@ -1157,7 +1157,7 @@ autogen()
+ # two just-pre-run programs.
- # Import from gettext.
--with_gettext=yes
-+with_gettext=no
- grep '^[ ]*AM_GNU_GETTEXT_VERSION(' configure.ac >/dev/null || \
- with_gettext=no
+ # Import from gettext.
+- with_gettext=yes
++ with_gettext=no
+ grep '^[ ]*AM_GNU_GETTEXT_VERSION(' configure.ac >/dev/null || \
+ with_gettext=no
PKG_SOURCE_URL:=https://fedorapeople.org/~acme/dwarves/
PKG_HASH:=1d8c9a1c2d42e06cc121a70a39c4f621fd28f15c476ed1b7c7b226f41fdd32df
+PKG_MAINTAINER:=Tony Ambardar <itugrok@yahoo.com>
PKG_LICENSE:=GPL-2.0-only
PKG_LICENSE_FILES:=COPYING
include $(TOPDIR)/rules.mk
PKG_NAME:=elfutils
-PKG_VERSION:=0.189
-PKG_RELEASE:=1
+PKG_VERSION:=0.191
+PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://sourceware.org/$(PKG_NAME)/ftp/$(PKG_VERSION)
-PKG_HASH:=39bd8f1a338e2b7cd4abc3ff11a0eddc6e690f69578a57478d8179b4148708c8
+PKG_HASH:=df76db71366d1d708365fc7a6c60ca48398f14367eb2b8954efc8897147ad871
PKG_LICENSE:=GPL-3.0-or-later
PKG_LICENSE_FILES:=COPYING COPYING-GPLV2 COPYING-LGPLV3
PKG_FIXUP:=autoreconf
PKG_INSTALL:=1
+PKG_SUBDIRS := \
+ libgnu \
+ config \
+ lib \
+ libelf \
+ libcpu \
+ backends \
+ libebl \
+ libdwelf \
+ libdwfl \
+ libdw
+
+PKG_GNULIB_BASE:=libgnu
+
+PKG_GNULIB_ARGS = \
+ --dir=$(HOST_BUILD_DIR) \
+ --local-dir=$(STAGING_DIR_HOST)/share/gnulib \
+ --source-base=$(PKG_GNULIB_BASE) \
+ --libtool \
+ --avoid=reallocarray \
+ --import
+
+PKG_GNULIB_MODS = \
+ argp \
+ fts \
+ obstack \
+ progname \
+ strchrnul \
+ tsearch
+
include $(INCLUDE_DIR)/host-build.mk
ifeq ($(HOST_OS),Darwin)
Hooks/HostConfigure/Pre := Host/Gnulib $(Hooks/HostConfigure/Pre)
define Host/Gnulib
- cd $(HOST_BUILD_DIR); $(STAGING_DIR_HOST)/bin/gnulib-tool --libtool --source-base=libgnu --import argp obstack fts strchrnul progname tsearch;
+ $(STAGING_DIR_HOST)/bin/gnulib-tool $(PKG_GNULIB_ARGS) $(PKG_GNULIB_MODS);
ln -sf ../lib/eu-config.h $(HOST_BUILD_DIR)/libgnu/;
endef
+define Host/Compile
+ $(call Host/Compile/Default,SUBDIRS='$$$$(wildcard $(PKG_SUBDIRS))')
+endef
+
+define Host/Install
+ $(call Host/Compile/Default,install SUBDIRS='$$$$(wildcard $(PKG_SUBDIRS))')
+endef
+
define Host/Uninstall
-$(call Host/Compile/Default,uninstall)
endef
+++ b/configure.ac
@@ -20,6 +20,7 @@ dnl You should have received a copy of
dnl along with this program. If not, see <http://www.gnu.org/licenses/>.
- AC_INIT([elfutils],[0.189],[https://sourceware.org/bugzilla],[elfutils],[http://elfutils.org/])
+ AC_INIT([elfutils],[0.191],[https://sourceware.org/bugzilla],[elfutils],[http://elfutils.org/])
+AC_CONFIG_MACRO_DIRS([m4])
dnl Workaround for older autoconf < 2.64
-AC_CONFIG_FILES([config/Makefile])
+AC_CONFIG_FILES([config/Makefile libgnu/Makefile])
- AC_COPYRIGHT([Copyright (C) 1996-2023 The elfutils developers.])
+ AC_COPYRIGHT([Copyright (C) 1996-2024 The elfutils developers.])
-AC_PREREQ(2.63) dnl Minimum Autoconf version required.
+AC_PREREQ(2.64) dnl Minimum Autoconf version required.
dnl The directories with content.
dnl Documentation.
---- a/Makefile.am
-+++ b/Makefile.am
-@@ -26,11 +26,11 @@ AM_MAKEFLAGS = --no-print-directory
-
- pkginclude_HEADERS = version.h
-
--SUBDIRS = config lib libelf libcpu backends libebl libdwelf libdwfl libdw \
-- libasm debuginfod src po doc tests
-+SUBDIRS = libgnu config lib libelf libcpu backends libebl libdwelf libdwfl libdw
-
- EXTRA_DIST = elfutils.spec GPG-KEY NOTES CONTRIBUTING \
-- COPYING COPYING-GPLV2 COPYING-LGPLV3
-+ COPYING COPYING-GPLV2 COPYING-LGPLV3 \
-+ m4/gnulib-cache.m4
-
- # Make sure the test install uses lib64 when $LIB will yield lib64.
- # Make sure the test build uses the same compiler, which on e.g. ppc64
--- a/libelf/elf_update.c
+++ b/libelf/elf_update.c
@@ -37,6 +37,33 @@
write_file (Elf *elf, int64_t size, int change_bo, size_t shnum)
--- a/lib/eu-config.h
+++ b/lib/eu-config.h
-@@ -52,14 +52,18 @@
- # define rwlock_unlock(lock) ((void) (lock))
+@@ -59,14 +59,18 @@
+ # define once(once_control, init_routine) init_routine()
#endif /* USE_LOCKS */
-#include <libintl.h>
#ifdef __i386__
# define internal_function __attribute__ ((regparm (3), stdcall))
-@@ -70,12 +74,7 @@
+@@ -77,12 +81,7 @@
#define internal_strong_alias(name, aliasname) \
extern __typeof (name) aliasname __attribute__ ((alias (#name))) internal_function;
#ifdef HAVE_GCC_STRUCT
#define attribute_packed \
-@@ -159,7 +158,7 @@ asm (".section predict_data, \"aw\"; .pr
+@@ -166,7 +165,7 @@ asm (".section predict_data, \"aw\"; .pr
#endif
/* Avoid PLT entries. */
+{
+ return ppc_check_object_attribute(ebl, vendor, tag, value, tag_name, value_name);
+}
---- a/lib/libeu.h
-+++ b/lib/libeu.h
-@@ -45,4 +45,11 @@ extern char *xasprintf(const char *fmt,
- extern uint32_t crc32 (uint32_t crc, unsigned char *buf, size_t len);
- extern int crc32_file (int fd, uint32_t *resp);
-
-+#ifdef __APPLE__
-+static inline void tdestroy(void *root __attribute__ ((unused)),
-+ void (*freekey)(void *) __attribute__ ((unused)))
-+{
-+}
-+#endif
-+
- #endif
--- a/libdwfl/libdwflP.h
+++ b/libdwfl/libdwflP.h
-@@ -31,6 +31,8 @@
+@@ -31,6 +31,7 @@
#include <libdwfl.h>
#include <libebl.h>
+#include <libeu.h>
-+#include <libgen.h>
#include <assert.h>
#include <dirent.h>
#include <errno.h>
+#endif
--- a/libdw/libdwP.h
+++ b/libdw/libdwP.h
-@@ -32,8 +32,10 @@
+@@ -32,10 +32,10 @@
#include <stdbool.h>
#include <pthread.h>
+#include <libeu.h>
#include <libdw.h>
#include <dwarf.h>
-+#include <libgen.h>
-
+-
/* Known location expressions already decoded. */
+ struct loc_s
+ {
--- a/libdw/Makefile.am
+++ b/libdw/Makefile.am
@@ -34,14 +34,12 @@ endif
modules = i386 sh x86_64 ia64 alpha arm aarch64 sparc ppc ppc64 s390 \
m68k bpf riscv csky loongarch arc
-@@ -100,17 +100,13 @@ loongarch_SRCS = loongarch_init.c loonga
+@@ -102,17 +102,13 @@ loongarch_SRCS = loongarch_init.c loonga
arc_SRCS = arc_init.c arc_symbol.c
+++ b/src/Makefile.am
@@ -29,9 +29,9 @@ bin_PROGRAMS = readelf nm size strip elf
elfcmp objdump ranlib strings ar unstrip stack elfcompress \
- elfclassify
+ elfclassify srcfiles
-noinst_LIBRARIES = libar.a
+noinst_LTLIBRARIES = libar.la
EXTRA_DIST = arlib.h debugpred.h
-@@ -39,17 +39,11 @@ bin_SCRIPTS = make-debug-archive
+@@ -39,27 +39,16 @@ bin_SCRIPTS = make-debug-archive
EXTRA_DIST += make-debug-archive.in
CLEANFILES += make-debug-archive
-if BUILD_STATIC
-libasm = ../libasm/libasm.a
-libdw = ../libdw/libdw.a -lz $(zip_LIBS) $(libelf) -ldl -lpthread
--libelf = ../libelf/libelf.a -lz
+-libelf = ../libelf/libelf.a -lz $(zstd_LIBS)
++libasm = ../libasm/libasm.la
++libdw = ../libdw/libdw.la -lz $(zip_LIBS) $(libelf) -ldl -lpthread
++libelf = ../libelf/libelf.la -lz $(zstd_LIBS)
+ if LIBDEBUGINFOD
+-libdebuginfod = ../debuginfod/libdebuginfod.a -lpthread $(libcurl_LIBS)
++libdebuginfod = ../debuginfod/libdebuginfod.la -lpthread $(libcurl_LIBS)
+ else
+ libdebuginfod =
+ endif
-else
-libasm = ../libasm/libasm.so
-libdw = ../libdw/libdw.so
-libelf = ../libelf/libelf.so
+-if LIBDEBUGINFOD
+-libdebuginfod = ../debuginfod/libdebuginfod.so
+-else
+-libdebuginfod =
+-endif
-endif
-libebl = ../libebl/libebl.a ../backends/libebl_backends.a ../libcpu/libcpu.a
-libeu = ../lib/libeu.a
-+libasm = ../libasm/libasm.la
-+libdw = ../libdw/libdw.la -lz $(zip_LIBS) $(libelf) -ldl -lpthread
-+libelf = ../libelf/libelf.la
+libebl = ../libebl/libebl.la ../backends/libebl_backends.la ../libcpu/libcpu.la
+libeu = ../lib/libeu.la
if DEMANGLE
demanglelib = -lstdc++
-@@ -77,9 +71,9 @@ findtextrel_LDADD = $(libdw) $(libelf) $
+@@ -87,9 +76,9 @@ findtextrel_LDADD = $(libdw) $(libelf) $
addr2line_LDADD = $(libdw) $(libelf) $(libeu) $(argp_LDADD) $(demanglelib)
elfcmp_LDADD = $(libebl) $(libdw) $(libelf) $(libeu) $(argp_LDADD)
objdump_LDADD = $(libasm) $(libebl) $(libdw) $(libelf) $(libeu) $(argp_LDADD)
elfcompress_LDADD = $(libebl) $(libelf) $(libdw) $(libeu) $(argp_LDADD)
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
-@@ -662,17 +662,11 @@ installcheck-local:
+@@ -689,17 +689,11 @@ installcheck-local:
TESTS_ENVIRONMENT="$(installed_TESTS_ENVIRONMENT)" \
LOG_COMPILER="$(installed_LOG_COMPILER)" check-TESTS
-if BUILD_STATIC
-libdw = ../libdw/libdw.a -lz $(zip_LIBS) $(libelf) $(libebl) -ldl -lpthread
--libelf = ../libelf/libelf.a -lz
+-libelf = ../libelf/libelf.a -lz $(zstd_LIBS)
-libasm = ../libasm/libasm.a
-else
-libdw = ../libdw/libdw.so
Cflags: -I${includedir}
Requires.private: zlib @LIBZSTD@
+--- a/lib/next_prime.c
++++ b/lib/next_prime.c
+@@ -27,6 +27,7 @@
+ the GNU Lesser General Public License along with this program. If
+ not, see <http://www.gnu.org/licenses/>. */
+
++#include <config.h>
+ #include <stddef.h>
+
+
include $(TOPDIR)/rules.mk
PKG_NAME:=expat
-PKG_CPE_ID:=cpe:/a:libexpat:expat
+PKG_CPE_ID:=cpe:/a:libexpat:libexpat
PKG_VERSION:=2.6.2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
include $(TOPDIR)/rules.mk
PKG_NAME:=flex
-PKG_CPE_ID:=cpe:/a:flex_project:flex
+PKG_CPE_ID:=cpe:/a:westes:flex
PKG_VERSION:=2.6.4
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
--- /dev/null
+From bfba6445a778007f40af5cbfbe725e12c0fcafc6 Mon Sep 17 00:00:00 2001
+From: Tomas Volf <~@wolfsden.cz>
+Date: Tue, 5 Mar 2024 22:25:20 +0100
+Subject: [PATCH] gm_utils.cpp: Call clear instead of empty.
+
+Since the intention seem to be to erase the next word, I believe calling empty
+was a mistake and it should have been clear. Empty does nothing in this
+context.
+
+* src/gm_utils.cpp (wrap_cstr): Call clear.
+---
+ src/gm_utils.cpp | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/src/gm_utils.cpp
++++ b/src/gm_utils.cpp
+@@ -311,7 +311,7 @@ void wrap_cstr(string& wrapped, unsigned
+ // trim leading spaces
+ std::size_t pos = next_word.find_first_not_of(' ');
+ if( pos == std::string::npos )
+- next_word.empty();
++ next_word.clear();
+ else if( pos )
+ next_word.erase( 0, pos );
+
--- /dev/null
+From a3d0a0419a35bef9b80a6a12432ab30e2d1e0f5a Mon Sep 17 00:00:00 2001
+From: Tomas Volf <~@wolfsden.cz>
+Date: Tue, 5 Mar 2024 22:27:42 +0100
+Subject: [PATCH] gm_utils.h: Drop std::unary_function.
+
+I am not sure what it does, it is deprecated/removed (depending on C++ version)
+and the advice seems to be that is just is not necessary. So just remove it.
+
+* src/gm_utils.h (print_f, pair_print_f): Drop std::unary_function.
+---
+ src/gm_utils.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/src/gm_utils.h
++++ b/src/gm_utils.h
+@@ -117,7 +117,7 @@ bool string_contains(const char *s, cons
+ * Function object to print something into a stream (to be used with for_each)
+ */
+ template<class T>
+-struct print_f : public std::unary_function<T, void>
++struct print_f
+ {
+ print_f(std::ostream& out, const string &s = ", ") : os(out), sep(s) {}
+ void operator() (T x) { os << x << sep; }
+@@ -129,7 +129,7 @@ struct print_f : public std::unary_funct
+ * Function object to print a pair into two streams (to be used with for_each)
+ */
+ template<class T>
+-struct pair_print_f : public std::unary_function<T, void>
++struct pair_print_f
+ {
+ pair_print_f(std::ostream& out1, std::ostream& out2, const string &s = ", ") :
+ os1(out1), os2(out2), sep(s) {}
PKG_NAME:=gnulib
PKG_CPE_ID:=cpe:/a:gnu:$(PKG_NAME)
-PKG_VERSION:=f9a4ee73c3e7b544f640d0d04b55983d3a7b894e# # master
+PKG_VERSION:=c99c8d491850dc3a6e0b8604a2729d8bc5c0eff1# # stable-202401
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://git.savannah.gnu.org/cgit/$(PKG_NAME).git/snapshot
-PKG_HASH:=514716d58987a9c0de0d69fb22d42bcd19edf80eed099882a004ff162060f1a8
+PKG_HASH:=8e6f4a907d9677b55fd452e1340a3e030a6f530b138d420c11975da33f086b1e
include $(INCLUDE_DIR)/host-build.mk
if [ ! "$inst_ver" ]; then
warn_ "Error: '$app' not found"
ret=1
-@@ -1135,7 +1135,7 @@ autogen()
+@@ -1157,7 +1157,7 @@ autogen()
# two just-pre-run programs.
# Import from gettext.
--- /dev/null
+--- a/lib/search.in.h
++++ b/lib/search.in.h
+@@ -112,6 +112,11 @@ _GL_CXXALIASWARN (lsearch);
+ # define twalk rpl_twalk
+ # endif
+ # endif
++# if @REPLACE_TDESTROY@
++# if !(defined __cplusplus && defined GNULIB_NAMESPACE)
++# define tdestroy rpl_tdestroy
++# endif
++# endif
+
+ /* See <https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/search.h.html>
+ <https://pubs.opengroup.org/onlinepubs/9699919799/functions/tsearch.html>
+@@ -137,6 +142,7 @@ extern "C" {
+ # if !GNULIB_defined_search_fn_types
+ typedef int (*_gl_search_compar_fn) (const void *, const void *);
+ typedef void (*_gl_search_action_fn) (const void *, VISIT, int);
++typedef void (*_gl_search_free_fn) (void *);
+ # define GNULIB_defined_search_fn_types 1
+ # endif
+ # ifdef __cplusplus
+@@ -252,9 +258,36 @@ _GL_CXXALIAS_SYS (twalk, void,
+ _GL_CXXALIASWARN (twalk);
+ # endif
+
++/* Removes the whole tree pointed to by root,
++ freeing all resources allocated by the tsearch() function.
++ The FREE_NODE function is called:
++ - For the data in each tree node.
++ - Even when no such work is necessary, to a function doing nothing
++ The arguments passed to FREE_NODE are:
++ 1. The pointer to the data. */
++# if @REPLACE_TDESTROY@
++_GL_FUNCDECL_RPL (tdestroy, void,
++ (void *vroot, _gl_search_free_fn freefct)
++ _GL_ARG_NONNULL ((2)));
++_GL_CXXALIAS_RPL (tdestroy, void,
++ (void *vroot, _gl_search_free_fn freefct));
++# else
++# if !@HAVE_TDESTROY@
++_GL_FUNCDECL_SYS (tdestroy, void,
++ (void *vroot, _gl_search_free_fn freefct)
++ _GL_ARG_NONNULL ((2)));
++# endif
++_GL_CXXALIAS_SYS (tdestroy, void,
++ (void *vroot, _gl_search_free_fn freefct));
++# endif
++# if __GLIBC__ >= 2
++_GL_CXXALIASWARN (tdestroy);
++# endif
++
+ /* Flags used by tsearch.c. */
+ # define GNULIB_defined_tsearch (@REPLACE_TSEARCH@ || !@HAVE_TSEARCH@)
+ # define GNULIB_defined_twalk (@REPLACE_TWALK@ || !@HAVE_TWALK@)
++# define GNULIB_defined_tdestroy (@REPLACE_TDESTROY@ || !@HAVE_TDESTROY@)
+
+ #elif defined GNULIB_POSIXCHECK
+ # undef tsearch
+@@ -277,6 +310,11 @@ _GL_WARN_ON_USE (tdelete, "tdelete is un
+ _GL_WARN_ON_USE (twalk, "twalk is unportable - "
+ "use gnulib module tsearch for portability");
+ # endif
++# undef tdestroy
++# if HAVE_RAW_DECL_TDESTROY
++_GL_WARN_ON_USE (tdestroy, "tdestroy is unportable - "
++ "use gnulib module tsearch for portability");
++# endif
+ #endif
+
+
+--- a/lib/tsearch.c
++++ b/lib/tsearch.c
+@@ -98,12 +98,14 @@
+
+ typedef int (*__compar_fn_t) (const void *, const void *);
+ typedef void (*__action_fn_t) (const void *, VISIT, int);
++typedef void (*__free_fn_t) (void *);
+
+ #ifndef weak_alias
+ # define __tsearch tsearch
+ # define __tfind tfind
+ # define __tdelete tdelete
+ # define __twalk twalk
++# define __tdestroy tdestroy
+ #endif
+
+ #ifndef internal_function
+@@ -656,7 +658,7 @@ weak_alias (__twalk, twalk)
+ #endif /* GNULIB_defined_twalk */
+
+
+-#ifdef _LIBC
++#if defined(_LIBC) || GNULIB_defined_tdestroy
+
+ /* The standardized functions miss an important functionality: the
+ tree cannot be removed easily. We provide a function to do this. */
+@@ -683,6 +685,8 @@ __tdestroy (void *vroot, __free_fn_t fre
+ if (root != NULL)
+ tdestroy_recurse (root, freefct);
+ }
++#ifdef weak_alias
+ weak_alias (__tdestroy, tdestroy)
++#endif
+
+-#endif /* _LIBC */
++#endif /* defined(_LIBC) || GNULIB_defined_tdestroy */
+--- a/m4/search_h.m4
++++ b/m4/search_h.m4
+@@ -39,7 +39,7 @@ AC_DEFUN_ONCE([gl_SEARCH_H],
+ dnl Check for declarations of anything we want to poison if the
+ dnl corresponding gnulib module is not in use.
+ gl_WARN_ON_USE_PREPARE([[#include <search.h>
+- ]], [tdelete tfind tsearch twalk])
++ ]], [tdelete tfind tsearch twalk tdestroy])
+
+ AC_REQUIRE([AC_C_RESTRICT])
+ ])
+@@ -75,8 +75,10 @@ AC_DEFUN([gl_SEARCH_H_DEFAULTS],
+ gl_MODULE_INDICATOR_INIT_VARIABLE([GNULIB_MDA_LFIND], [1])
+ gl_MODULE_INDICATOR_INIT_VARIABLE([GNULIB_MDA_LSEARCH], [1])
+ dnl Assume proper GNU behavior unless another module says otherwise.
+- HAVE_TSEARCH=1; AC_SUBST([HAVE_TSEARCH])
+- HAVE_TWALK=1; AC_SUBST([HAVE_TWALK])
+- REPLACE_TSEARCH=0; AC_SUBST([REPLACE_TSEARCH])
+- REPLACE_TWALK=0; AC_SUBST([REPLACE_TWALK])
++ HAVE_TSEARCH=1; AC_SUBST([HAVE_TSEARCH])
++ HAVE_TWALK=1; AC_SUBST([HAVE_TWALK])
++ HAVE_TDESTROY=1; AC_SUBST([HAVE_TDESTROY])
++ REPLACE_TSEARCH=0; AC_SUBST([REPLACE_TSEARCH])
++ REPLACE_TWALK=0; AC_SUBST([REPLACE_TWALK])
++ REPLACE_TDESTROY=0; AC_SUBST([REPLACE_TDESTROY])
+ ])
+--- a/m4/tsearch.m4
++++ b/m4/tsearch.m4
+@@ -9,6 +9,7 @@ AC_DEFUN([gl_FUNC_TSEARCH],
+ AC_REQUIRE([gl_SEARCH_H_DEFAULTS])
+ gl_CHECK_FUNCS_ANDROID([tsearch], [[#include <search.h>]])
+ gl_CHECK_FUNCS_ANDROID([twalk], [[#include <search.h>]])
++ gl_CHECK_FUNCS_ANDROID([tdestroy], [[#include <search.h>]])
+ if test $ac_cv_func_tsearch = yes; then
+ dnl On OpenBSD 4.0, the return value of tdelete() is incorrect.
+ AC_REQUIRE([AC_PROG_CC])
+@@ -50,6 +51,7 @@ main ()
+ *no)
+ REPLACE_TSEARCH=1
+ REPLACE_TWALK=1
++ REPLACE_TDESTROY=1
+ ;;
+ esac
+ else
+@@ -64,6 +66,12 @@ main ()
+ future*) REPLACE_TWALK=1 ;;
+ esac
+ fi
++ if test $ac_cv_func_tdestroy != yes; then
++ HAVE_TDESTROY=0
++ case "$gl_cv_onwards_func_tdestroy" in
++ future*) REPLACE_TDESTROY=1 ;;
++ esac
++ fi
+ ])
+
+ # Prerequisites of lib/tsearch.c.
+--- a/modules/search
++++ b/modules/search
+@@ -37,8 +37,10 @@ search.h: search.in.h $(top_builddir)/co
+ -e 's/@''GNULIB_MDA_LSEARCH''@/$(GNULIB_MDA_LSEARCH)/g' \
+ -e 's|@''HAVE_TSEARCH''@|$(HAVE_TSEARCH)|g' \
+ -e 's|@''HAVE_TWALK''@|$(HAVE_TWALK)|g' \
++ -e 's|@''HAVE_TDESTROY''@|$(HAVE_TDESTROY)|g' \
+ -e 's|@''REPLACE_TSEARCH''@|$(REPLACE_TSEARCH)|g' \
+ -e 's|@''REPLACE_TWALK''@|$(REPLACE_TWALK)|g' \
++ -e 's|@''REPLACE_TDESTROY''@|$(REPLACE_TDESTROY)|g' \
+ -e '/definitions of _GL_FUNCDECL_RPL/r $(CXXDEFS_H)' \
+ -e '/definition of _GL_ARG_NONNULL/r $(ARG_NONNULL_H)' \
+ -e '/definition of _GL_WARN_ON_USE/r $(WARN_ON_USE_H)' \
+--- a/modules/tsearch
++++ b/modules/tsearch
+@@ -11,7 +11,12 @@ search
+ configure.ac:
+ gl_FUNC_TSEARCH
+ gl_CONDITIONAL([GL_COND_OBJ_TSEARCH],
+- [test $HAVE_TSEARCH = 0 || test $HAVE_TWALK = 0 || test $REPLACE_TSEARCH = 1 || test $REPLACE_TWALK = 1])
++ [test $HAVE_TSEARCH = 0 ||
++ test $HAVE_TWALK = 0 ||
++ test $HAVE_TDESTROY = 0 ||
++ test $REPLACE_TSEARCH = 1 ||
++ test $REPLACE_TWALK = 1 ||
++ test $REPLACE_TDESTROY = 1])
+ AM_COND_IF([GL_COND_OBJ_TSEARCH], [
+ gl_PREREQ_TSEARCH
+ ])
--- /dev/null
+--- a/lib/ialloc.h
++++ b/lib/ialloc.h
+@@ -106,6 +106,8 @@ icalloc (idx_t n, idx_t s)
+ return calloc (n, s);
+ }
+
++#if GNULIB_REALLOCARRAY
++
+ /* ireallocarray (ptr, num, size) is like reallocarray (ptr, num, size).
+ It returns a non-NULL pointer to num * size bytes of memory.
+ Upon failure, it returns NULL with errno set. */
+@@ -131,6 +133,8 @@ ireallocarray (void *p, idx_t n, idx_t s
+ return _gl_alloc_nomem ();
+ }
+
++#endif /* GNULIB_REALLOCARRAY */
++
+ #ifdef __cplusplus
+ }
+ #endif
+--- a/lib/xmalloc.c
++++ b/lib/xmalloc.c
+@@ -51,12 +51,16 @@ ximalloc (idx_t s)
+ return nonnull (imalloc (s));
+ }
+
++#if GNULIB_REALLOCARRAY
++
+ char *
+ xcharalloc (size_t n)
+ {
+ return XNMALLOC (n, char);
+ }
+
++#endif /* GNULIB_REALLOCARRAY */
++
+ /* Change the size of an allocated block of memory P to S bytes,
+ with error checking. */
+
+@@ -75,6 +79,8 @@ xirealloc (void *p, idx_t s)
+ return nonnull (irealloc (p, s));
+ }
+
++#if GNULIB_REALLOCARRAY
++
+ /* Change the size of an allocated block of memory P to an array of N
+ objects each of S bytes, with error checking. */
+
+@@ -205,6 +211,8 @@ x2nrealloc (void *p, size_t *pn, size_t
+ return p;
+ }
+
++#endif /* GNULIB_REALLOCARRAY */
++
+ /* Grow PA, which points to an array of *PN items, and return the
+ location of the reallocated array, updating *PN to reflect its
+ new size. The new array will contain at least N_INCR_MIN more
+--- a/lib/xalloc.h
++++ b/lib/xalloc.h
+@@ -129,6 +129,7 @@ char *xstrdup (char const *str)
+ # define XCALLOC(n, t) \
+ ((t *) (sizeof (t) == 1 ? xzalloc (n) : xcalloc (n, sizeof (t))))
+
++# if GNULIB_REALLOCARRAY
+
+ /* Allocate an array of N objects, each with S bytes of memory,
+ dynamically, with error checking. S must be nonzero. */
+@@ -156,6 +157,8 @@ char *xcharalloc (size_t n)
+ _GL_ATTRIBUTE_MALLOC _GL_ATTRIBUTE_DEALLOC_FREE
+ _GL_ATTRIBUTE_ALLOC_SIZE ((1)) _GL_ATTRIBUTE_RETURNS_NONNULL;
+
++# endif /* GNULIB_REALLOCARRAY */
++
+ #endif /* GNULIB_XALLOC */
+
+
+--- a/lib/safe-alloc.h
++++ b/lib/safe-alloc.h
+@@ -36,6 +36,8 @@ _GL_INLINE_HEADER_BEGIN
+ # define SAFE_ALLOC_INLINE _GL_INLINE
+ #endif
+
++#if GNULIB_REALLOCARRAY
++
+ /* Don't call these directly - use the macros below. */
+ SAFE_ALLOC_INLINE void *
+ safe_alloc_realloc_n (void *ptr, size_t count, size_t size)
+@@ -51,6 +53,9 @@ safe_alloc_realloc_n (void *ptr, size_t
+ #endif
+ return ptr;
+ }
++
++#endif /* GNULIB_REALLOCARRAY */
++
+ _GL_ATTRIBUTE_NODISCARD SAFE_ALLOC_INLINE int
+ safe_alloc_check (void *ptr)
+ {
+@@ -84,6 +89,8 @@ safe_alloc_check (void *ptr)
+ #define ALLOC_N(ptr, count) \
+ safe_alloc_check ((ptr) = calloc (count, sizeof *(ptr)))
+
++#if GNULIB_REALLOCARRAY
++
+ /**
+ * ALLOC_N_UNINITIALIZED:
+ * @ptr: pointer to allocated memory
+@@ -112,6 +119,8 @@ safe_alloc_check (void *ptr)
+ #define REALLOC_N(ptr, count) \
+ safe_alloc_check ((ptr) = safe_alloc_realloc_n (ptr, count, sizeof *(ptr)))
+
++#endif /* GNULIB_REALLOCARRAY */
++
+ /**
+ * FREE:
+ * @ptr: pointer holding address to be freed
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef __ASM_GENERIC_BITS_PER_LONG
+#define __ASM_GENERIC_BITS_PER_LONG
+
+#ifndef __BITS_PER_LONG
+/*
+ * In order to keep safe and avoid regression, only unify uapi
+ * bitsperlong.h for some archs which are using newer toolchains
+ * that have the definitions of __CHAR_BIT__ and __SIZEOF_LONG__.
+ * See the following link for more info:
+ * https://lore.kernel.org/linux-arch/b9624545-2c80-49a1-ac3c-39264a591f7b@app.fastmail.com/
+ */
+#if defined(__CHAR_BIT__) && defined(__SIZEOF_LONG__)
+#define __BITS_PER_LONG (__CHAR_BIT__ * __SIZEOF_LONG__)
+#else
+/*
+ * There seems to be no way of detecting this automatically from user
+ * space, so 64 bit architectures should override this in their
+ * bitsperlong.h. In particular, an architecture that supports
+ * both 32 and 64 bit user space must not rely on CONFIG_64BIT
+ * to decide it, but rather check a compiler provided macro.
+ */
+#define __BITS_PER_LONG 32
+#endif
+#endif
+
+#endif /* __ASM_GENERIC_BITS_PER_LONG */
--- /dev/null
+#ifndef __ASM_BYTEORDER_H
+#define __ASM_BYTEORDER_H
+
+#include <endian.h>
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#include <linux/byteorder/little_endian.h>
+#else
+#include <linux/byteorder/big_endian.h>
+#endif
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _ASM_GENERIC_ERRNO_BASE_H
+#define _ASM_GENERIC_ERRNO_BASE_H
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Argument list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _ASM_GENERIC_ERRNO_H
+#define _ASM_GENERIC_ERRNO_H
+
+#include <asm/errno-base.h>
+
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+
+/*
+ * This error code is special: arch syscall entry code will return
+ * -ENOSYS if users try to call a syscall that doesn't exist. To keep
+ * failures of syscalls that really do exist distinguishable from
+ * failures due to attempts to use a nonexistent syscall, syscall
+ * implementations should refrain from returning -ENOSYS.
+ */
+#define ENOSYS 38 /* Invalid system call number */
+
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+
+#define EDEADLOCK EDEADLK
+
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+#define ECANCELED 125 /* Operation Canceled */
+#define ENOKEY 126 /* Required key not available */
+#define EKEYEXPIRED 127 /* Key has expired */
+#define EKEYREVOKED 128 /* Key has been revoked */
+#define EKEYREJECTED 129 /* Key was rejected by service */
+
+/* for robust mutexes */
+#define EOWNERDEAD 130 /* Owner died */
+#define ENOTRECOVERABLE 131 /* State not recoverable */
+
+#define ERFKILL 132 /* Operation not possible due to RF-kill */
+
+#define EHWPOISON 133 /* Memory page has hardware error */
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef __ASM_GENERIC_POSIX_TYPES_H
+#define __ASM_GENERIC_POSIX_TYPES_H
+
+#include <asm/bitsperlong.h>
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.
+ *
+ * First the types that are often defined in different ways across
+ * architectures, so that you can override them.
+ */
+
+#ifndef __kernel_long_t
+typedef long __kernel_long_t;
+typedef unsigned long __kernel_ulong_t;
+#endif
+
+#ifndef __kernel_ino_t
+typedef __kernel_ulong_t __kernel_ino_t;
+#endif
+
+#ifndef __kernel_mode_t
+typedef unsigned int __kernel_mode_t;
+#endif
+
+#ifndef __kernel_pid_t
+typedef int __kernel_pid_t;
+#endif
+
+#ifndef __kernel_ipc_pid_t
+typedef int __kernel_ipc_pid_t;
+#endif
+
+#ifndef __kernel_uid_t
+typedef unsigned int __kernel_uid_t;
+typedef unsigned int __kernel_gid_t;
+#endif
+
+#ifndef __kernel_suseconds_t
+typedef __kernel_long_t __kernel_suseconds_t;
+#endif
+
+#ifndef __kernel_daddr_t
+typedef int __kernel_daddr_t;
+#endif
+
+#ifndef __kernel_uid32_t
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+#endif
+
+#ifndef __kernel_old_uid_t
+typedef __kernel_uid_t __kernel_old_uid_t;
+typedef __kernel_gid_t __kernel_old_gid_t;
+#endif
+
+#ifndef __kernel_old_dev_t
+typedef unsigned int __kernel_old_dev_t;
+#endif
+
+/*
+ * Most 32 bit architectures use "unsigned int" size_t,
+ * and all 64 bit architectures use "unsigned long" size_t.
+ */
+#ifndef __kernel_size_t
+#if __BITS_PER_LONG != 64
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+#else
+typedef __kernel_ulong_t __kernel_size_t;
+typedef __kernel_long_t __kernel_ssize_t;
+typedef __kernel_long_t __kernel_ptrdiff_t;
+#endif
+#endif
+
+#ifndef __kernel_fsid_t
+typedef struct {
+ int val[2];
+} __kernel_fsid_t;
+#endif
+
+/*
+ * anything below here should be completely generic
+ */
+typedef __kernel_long_t __kernel_off_t;
+typedef long long __kernel_loff_t;
+typedef __kernel_long_t __kernel_old_time_t;
+typedef __kernel_long_t __kernel_time_t;
+typedef long long __kernel_time64_t;
+typedef __kernel_long_t __kernel_clock_t;
+typedef int __kernel_timer_t;
+typedef int __kernel_clockid_t;
+typedef char * __kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+
+#endif /* __ASM_GENERIC_POSIX_TYPES_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _ASM_GENERIC_SWAB_H
+#define _ASM_GENERIC_SWAB_H
+
+#include <asm/bitsperlong.h>
+
+/*
+ * 32 bit architectures typically (but not always) want to
+ * set __SWAB_64_THRU_32__. In user space, this is only
+ * valid if the compiler supports 64 bit data types.
+ */
+
+#if __BITS_PER_LONG == 32
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#define __SWAB_64_THRU_32__
+#endif
+#endif
+
+#endif /* _ASM_GENERIC_SWAB_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H
+#define _LINUX_BYTEORDER_BIG_ENDIAN_H
+
+#ifndef __BIG_ENDIAN
+#define __BIG_ENDIAN 4321
+#endif
+#ifndef __BIG_ENDIAN_BITFIELD
+#define __BIG_ENDIAN_BITFIELD
+#endif
+
+#include <linux/stddef.h>
+#include <linux/types.h>
+#include <linux/swab.h>
+
+#define __constant_htonl(x) ((__be32)(__u32)(x))
+#define __constant_ntohl(x) ((__u32)(__be32)(x))
+#define __constant_htons(x) ((__be16)(__u16)(x))
+#define __constant_ntohs(x) ((__u16)(__be16)(x))
+#define __constant_cpu_to_le64(x) ((__le64)___constant_swab64((x)))
+#define __constant_le64_to_cpu(x) ___constant_swab64((__u64)(__le64)(x))
+#define __constant_cpu_to_le32(x) ((__le32)___constant_swab32((x)))
+#define __constant_le32_to_cpu(x) ___constant_swab32((__u32)(__le32)(x))
+#define __constant_cpu_to_le16(x) ((__le16)___constant_swab16((x)))
+#define __constant_le16_to_cpu(x) ___constant_swab16((__u16)(__le16)(x))
+#define __constant_cpu_to_be64(x) ((__be64)(__u64)(x))
+#define __constant_be64_to_cpu(x) ((__u64)(__be64)(x))
+#define __constant_cpu_to_be32(x) ((__be32)(__u32)(x))
+#define __constant_be32_to_cpu(x) ((__u32)(__be32)(x))
+#define __constant_cpu_to_be16(x) ((__be16)(__u16)(x))
+#define __constant_be16_to_cpu(x) ((__u16)(__be16)(x))
+#define __cpu_to_le64(x) ((__le64)__swab64((x)))
+#define __le64_to_cpu(x) __swab64((__u64)(__le64)(x))
+#define __cpu_to_le32(x) ((__le32)__swab32((x)))
+#define __le32_to_cpu(x) __swab32((__u32)(__le32)(x))
+#define __cpu_to_le16(x) ((__le16)__swab16((x)))
+#define __le16_to_cpu(x) __swab16((__u16)(__le16)(x))
+#define __cpu_to_be64(x) ((__be64)(__u64)(x))
+#define __be64_to_cpu(x) ((__u64)(__be64)(x))
+#define __cpu_to_be32(x) ((__be32)(__u32)(x))
+#define __be32_to_cpu(x) ((__u32)(__be32)(x))
+#define __cpu_to_be16(x) ((__be16)(__u16)(x))
+#define __be16_to_cpu(x) ((__u16)(__be16)(x))
+
+static __always_inline __le64 __cpu_to_le64p(const __u64 *p)
+{
+ return (__le64)__swab64p(p);
+}
+static __always_inline __u64 __le64_to_cpup(const __le64 *p)
+{
+ return __swab64p((__u64 *)p);
+}
+static __always_inline __le32 __cpu_to_le32p(const __u32 *p)
+{
+ return (__le32)__swab32p(p);
+}
+static __always_inline __u32 __le32_to_cpup(const __le32 *p)
+{
+ return __swab32p((__u32 *)p);
+}
+static __always_inline __le16 __cpu_to_le16p(const __u16 *p)
+{
+ return (__le16)__swab16p(p);
+}
+static __always_inline __u16 __le16_to_cpup(const __le16 *p)
+{
+ return __swab16p((__u16 *)p);
+}
+static __always_inline __be64 __cpu_to_be64p(const __u64 *p)
+{
+ return (__be64)*p;
+}
+static __always_inline __u64 __be64_to_cpup(const __be64 *p)
+{
+ return (__u64)*p;
+}
+static __always_inline __be32 __cpu_to_be32p(const __u32 *p)
+{
+ return (__be32)*p;
+}
+static __always_inline __u32 __be32_to_cpup(const __be32 *p)
+{
+ return (__u32)*p;
+}
+static __always_inline __be16 __cpu_to_be16p(const __u16 *p)
+{
+ return (__be16)*p;
+}
+static __always_inline __u16 __be16_to_cpup(const __be16 *p)
+{
+ return (__u16)*p;
+}
+#define __cpu_to_le64s(x) __swab64s((x))
+#define __le64_to_cpus(x) __swab64s((x))
+#define __cpu_to_le32s(x) __swab32s((x))
+#define __le32_to_cpus(x) __swab32s((x))
+#define __cpu_to_le16s(x) __swab16s((x))
+#define __le16_to_cpus(x) __swab16s((x))
+#define __cpu_to_be64s(x) do { (void)(x); } while (0)
+#define __be64_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_be32s(x) do { (void)(x); } while (0)
+#define __be32_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_be16s(x) do { (void)(x); } while (0)
+#define __be16_to_cpus(x) do { (void)(x); } while (0)
+
+
+#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
--- /dev/null
+#include <asm/errno.h>
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+
+#ifndef __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN 1234
+#endif
+#ifndef __LITTLE_ENDIAN_BITFIELD
+#define __LITTLE_ENDIAN_BITFIELD
+#endif
+
+#include <linux/stddef.h>
+#include <linux/types.h>
+#include <linux/swab.h>
+
+#define __constant_htonl(x) ((__be32)___constant_swab32((x)))
+#define __constant_ntohl(x) ___constant_swab32((__be32)(x))
+#define __constant_htons(x) ((__be16)___constant_swab16((x)))
+#define __constant_ntohs(x) ___constant_swab16((__be16)(x))
+#define __constant_cpu_to_le64(x) ((__le64)(__u64)(x))
+#define __constant_le64_to_cpu(x) ((__u64)(__le64)(x))
+#define __constant_cpu_to_le32(x) ((__le32)(__u32)(x))
+#define __constant_le32_to_cpu(x) ((__u32)(__le32)(x))
+#define __constant_cpu_to_le16(x) ((__le16)(__u16)(x))
+#define __constant_le16_to_cpu(x) ((__u16)(__le16)(x))
+#define __constant_cpu_to_be64(x) ((__be64)___constant_swab64((x)))
+#define __constant_be64_to_cpu(x) ___constant_swab64((__u64)(__be64)(x))
+#define __constant_cpu_to_be32(x) ((__be32)___constant_swab32((x)))
+#define __constant_be32_to_cpu(x) ___constant_swab32((__u32)(__be32)(x))
+#define __constant_cpu_to_be16(x) ((__be16)___constant_swab16((x)))
+#define __constant_be16_to_cpu(x) ___constant_swab16((__u16)(__be16)(x))
+#define __cpu_to_le64(x) ((__le64)(__u64)(x))
+#define __le64_to_cpu(x) ((__u64)(__le64)(x))
+#define __cpu_to_le32(x) ((__le32)(__u32)(x))
+#define __le32_to_cpu(x) ((__u32)(__le32)(x))
+#define __cpu_to_le16(x) ((__le16)(__u16)(x))
+#define __le16_to_cpu(x) ((__u16)(__le16)(x))
+#define __cpu_to_be64(x) ((__be64)__swab64((x)))
+#define __be64_to_cpu(x) __swab64((__u64)(__be64)(x))
+#define __cpu_to_be32(x) ((__be32)__swab32((x)))
+#define __be32_to_cpu(x) __swab32((__u32)(__be32)(x))
+#define __cpu_to_be16(x) ((__be16)__swab16((x)))
+#define __be16_to_cpu(x) __swab16((__u16)(__be16)(x))
+
+static __always_inline __le64 __cpu_to_le64p(const __u64 *p)
+{
+ return (__le64)*p;
+}
+static __always_inline __u64 __le64_to_cpup(const __le64 *p)
+{
+ return (__u64)*p;
+}
+static __always_inline __le32 __cpu_to_le32p(const __u32 *p)
+{
+ return (__le32)*p;
+}
+static __always_inline __u32 __le32_to_cpup(const __le32 *p)
+{
+ return (__u32)*p;
+}
+static __always_inline __le16 __cpu_to_le16p(const __u16 *p)
+{
+ return (__le16)*p;
+}
+static __always_inline __u16 __le16_to_cpup(const __le16 *p)
+{
+ return (__u16)*p;
+}
+static __always_inline __be64 __cpu_to_be64p(const __u64 *p)
+{
+ return (__be64)__swab64p(p);
+}
+static __always_inline __u64 __be64_to_cpup(const __be64 *p)
+{
+ return __swab64p((__u64 *)p);
+}
+static __always_inline __be32 __cpu_to_be32p(const __u32 *p)
+{
+ return (__be32)__swab32p(p);
+}
+static __always_inline __u32 __be32_to_cpup(const __be32 *p)
+{
+ return __swab32p((__u32 *)p);
+}
+static __always_inline __be16 __cpu_to_be16p(const __u16 *p)
+{
+ return (__be16)__swab16p(p);
+}
+static __always_inline __u16 __be16_to_cpup(const __be16 *p)
+{
+ return __swab16p((__u16 *)p);
+}
+#define __cpu_to_le64s(x) do { (void)(x); } while (0)
+#define __le64_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_le32s(x) do { (void)(x); } while (0)
+#define __le32_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_le16s(x) do { (void)(x); } while (0)
+#define __le16_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_be64s(x) __swab64s((x))
+#define __be64_to_cpus(x) __swab64s((x))
+#define __cpu_to_be32s(x) __swab32s((x))
+#define __be32_to_cpus(x) __swab32s((x))
+#define __cpu_to_be16s(x) __swab16s((x))
+#define __be16_to_cpus(x) __swab16s((x))
+
+
+#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _UAPI_LINUX_STDDEF_H
+#define _UAPI_LINUX_STDDEF_H
+
+#ifndef __always_inline
+#define __always_inline inline
+#endif
+
+/**
+ * __struct_group() - Create a mirrored named and anonyomous struct
+ *
+ * @TAG: The tag name for the named sub-struct (usually empty)
+ * @NAME: The identifier name of the mirrored sub-struct
+ * @ATTRS: Any struct attributes (usually empty)
+ * @MEMBERS: The member declarations for the mirrored structs
+ *
+ * Used to create an anonymous union of two structs with identical layout
+ * and size: one anonymous and one named. The former's members can be used
+ * normally without sub-struct naming, and the latter can be used to
+ * reason about the start, end, and size of the group of struct members.
+ * The named struct can also be explicitly tagged for layer reuse, as well
+ * as both having struct attributes appended.
+ */
+#define __struct_group(TAG, NAME, ATTRS, MEMBERS...) \
+ union { \
+ struct { MEMBERS } ATTRS; \
+ struct TAG { MEMBERS } ATTRS NAME; \
+ } ATTRS
+
+#ifdef __cplusplus
+/* sizeof(struct{}) is 1 in C++, not 0, can't use C version of the macro. */
+#define __DECLARE_FLEX_ARRAY(T, member) \
+ T member[0]
+#else
+/**
+ * __DECLARE_FLEX_ARRAY() - Declare a flexible array usable in a union
+ *
+ * @TYPE: The type of each flexible array element
+ * @NAME: The name of the flexible array member
+ *
+ * In order to have a flexible array member in a union or alone in a
+ * struct, it needs to be wrapped in an anonymous struct with at least 1
+ * named member, but that member can be empty.
+ */
+#define __DECLARE_FLEX_ARRAY(TYPE, NAME) \
+ struct { \
+ struct { } __empty_ ## NAME; \
+ TYPE NAME[]; \
+ }
+#endif
+
+#ifndef __counted_by
+#define __counted_by(m)
+#endif
+
+#endif /* _UAPI_LINUX_STDDEF_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _LINUX_SWAB_H
+#define _LINUX_SWAB_H
+
+#include <linux/types.h>
+#include <linux/stddef.h>
+#include <asm/bitsperlong.h>
+#include <asm/swab.h>
+
+/*
+ * casts are necessary for constants, because we never know how for sure
+ * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.
+ */
+#define ___constant_swab16(x) ((__u16)( \
+ (((__u16)(x) & (__u16)0x00ffU) << 8) | \
+ (((__u16)(x) & (__u16)0xff00U) >> 8)))
+
+#define ___constant_swab32(x) ((__u32)( \
+ (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
+ (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \
+ (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \
+ (((__u32)(x) & (__u32)0xff000000UL) >> 24)))
+
+#define ___constant_swab64(x) ((__u64)( \
+ (((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \
+ (((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \
+ (((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \
+ (((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \
+ (((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \
+ (((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \
+ (((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \
+ (((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56)))
+
+#define ___constant_swahw32(x) ((__u32)( \
+ (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \
+ (((__u32)(x) & (__u32)0xffff0000UL) >> 16)))
+
+#define ___constant_swahb32(x) ((__u32)( \
+ (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \
+ (((__u32)(x) & (__u32)0xff00ff00UL) >> 8)))
+
+/*
+ * Implement the following as inlines, but define the interface using
+ * macros to allow constant folding when possible:
+ * ___swab16, ___swab32, ___swab64, ___swahw32, ___swahb32
+ */
+
+static __inline__ __u16 __fswab16(__u16 val)
+{
+#if defined (__arch_swab16)
+ return __arch_swab16(val);
+#else
+ return ___constant_swab16(val);
+#endif
+}
+
+static __inline__ __u32 __fswab32(__u32 val)
+{
+#if defined(__arch_swab32)
+ return __arch_swab32(val);
+#else
+ return ___constant_swab32(val);
+#endif
+}
+
+static __inline__ __u64 __fswab64(__u64 val)
+{
+#if defined (__arch_swab64)
+ return __arch_swab64(val);
+#elif defined(__SWAB_64_THRU_32__)
+ __u32 h = val >> 32;
+ __u32 l = val & ((1ULL << 32) - 1);
+ return (((__u64)__fswab32(l)) << 32) | ((__u64)(__fswab32(h)));
+#else
+ return ___constant_swab64(val);
+#endif
+}
+
+static __inline__ __u32 __fswahw32(__u32 val)
+{
+#ifdef __arch_swahw32
+ return __arch_swahw32(val);
+#else
+ return ___constant_swahw32(val);
+#endif
+}
+
+static __inline__ __u32 __fswahb32(__u32 val)
+{
+#ifdef __arch_swahb32
+ return __arch_swahb32(val);
+#else
+ return ___constant_swahb32(val);
+#endif
+}
+
+/**
+ * __swab16 - return a byteswapped 16-bit value
+ * @x: value to byteswap
+ */
+#ifdef __HAVE_BUILTIN_BSWAP16__
+#define __swab16(x) (__u16)__builtin_bswap16((__u16)(x))
+#else
+#define __swab16(x) \
+ (__u16)(__builtin_constant_p(x) ? \
+ ___constant_swab16(x) : \
+ __fswab16(x))
+#endif
+
+/**
+ * __swab32 - return a byteswapped 32-bit value
+ * @x: value to byteswap
+ */
+#ifdef __HAVE_BUILTIN_BSWAP32__
+#define __swab32(x) (__u32)__builtin_bswap32((__u32)(x))
+#else
+#define __swab32(x) \
+ (__u32)(__builtin_constant_p(x) ? \
+ ___constant_swab32(x) : \
+ __fswab32(x))
+#endif
+
+/**
+ * __swab64 - return a byteswapped 64-bit value
+ * @x: value to byteswap
+ */
+#ifdef __HAVE_BUILTIN_BSWAP64__
+#define __swab64(x) (__u64)__builtin_bswap64((__u64)(x))
+#else
+#define __swab64(x) \
+ (__u64)(__builtin_constant_p(x) ? \
+ ___constant_swab64(x) : \
+ __fswab64(x))
+#endif
+
+static __always_inline unsigned long __swab(const unsigned long y)
+{
+#if __BITS_PER_LONG == 64
+ return __swab64(y);
+#else /* __BITS_PER_LONG == 32 */
+ return __swab32(y);
+#endif
+}
+
+/**
+ * __swahw32 - return a word-swapped 32-bit value
+ * @x: value to wordswap
+ *
+ * __swahw32(0x12340000) is 0x00001234
+ */
+#define __swahw32(x) \
+ (__builtin_constant_p((__u32)(x)) ? \
+ ___constant_swahw32(x) : \
+ __fswahw32(x))
+
+/**
+ * __swahb32 - return a high and low byte-swapped 32-bit value
+ * @x: value to byteswap
+ *
+ * __swahb32(0x12345678) is 0x34127856
+ */
+#define __swahb32(x) \
+ (__builtin_constant_p((__u32)(x)) ? \
+ ___constant_swahb32(x) : \
+ __fswahb32(x))
+
+/**
+ * __swab16p - return a byteswapped 16-bit value from a pointer
+ * @p: pointer to a naturally-aligned 16-bit value
+ */
+static __always_inline __u16 __swab16p(const __u16 *p)
+{
+#ifdef __arch_swab16p
+ return __arch_swab16p(p);
+#else
+ return __swab16(*p);
+#endif
+}
+
+/**
+ * __swab32p - return a byteswapped 32-bit value from a pointer
+ * @p: pointer to a naturally-aligned 32-bit value
+ */
+static __always_inline __u32 __swab32p(const __u32 *p)
+{
+#ifdef __arch_swab32p
+ return __arch_swab32p(p);
+#else
+ return __swab32(*p);
+#endif
+}
+
+/**
+ * __swab64p - return a byteswapped 64-bit value from a pointer
+ * @p: pointer to a naturally-aligned 64-bit value
+ */
+static __always_inline __u64 __swab64p(const __u64 *p)
+{
+#ifdef __arch_swab64p
+ return __arch_swab64p(p);
+#else
+ return __swab64(*p);
+#endif
+}
+
+/**
+ * __swahw32p - return a wordswapped 32-bit value from a pointer
+ * @p: pointer to a naturally-aligned 32-bit value
+ *
+ * See __swahw32() for details of wordswapping.
+ */
+static __inline__ __u32 __swahw32p(const __u32 *p)
+{
+#ifdef __arch_swahw32p
+ return __arch_swahw32p(p);
+#else
+ return __swahw32(*p);
+#endif
+}
+
+/**
+ * __swahb32p - return a high and low byteswapped 32-bit value from a pointer
+ * @p: pointer to a naturally-aligned 32-bit value
+ *
+ * See __swahb32() for details of high/low byteswapping.
+ */
+static __inline__ __u32 __swahb32p(const __u32 *p)
+{
+#ifdef __arch_swahb32p
+ return __arch_swahb32p(p);
+#else
+ return __swahb32(*p);
+#endif
+}
+
+/**
+ * __swab16s - byteswap a 16-bit value in-place
+ * @p: pointer to a naturally-aligned 16-bit value
+ */
+static __inline__ void __swab16s(__u16 *p)
+{
+#ifdef __arch_swab16s
+ __arch_swab16s(p);
+#else
+ *p = __swab16p(p);
+#endif
+}
+/**
+ * __swab32s - byteswap a 32-bit value in-place
+ * @p: pointer to a naturally-aligned 32-bit value
+ */
+static __always_inline void __swab32s(__u32 *p)
+{
+#ifdef __arch_swab32s
+ __arch_swab32s(p);
+#else
+ *p = __swab32p(p);
+#endif
+}
+
+/**
+ * __swab64s - byteswap a 64-bit value in-place
+ * @p: pointer to a naturally-aligned 64-bit value
+ */
+static __always_inline void __swab64s(__u64 *p)
+{
+#ifdef __arch_swab64s
+ __arch_swab64s(p);
+#else
+ *p = __swab64p(p);
+#endif
+}
+
+/**
+ * __swahw32s - wordswap a 32-bit value in-place
+ * @p: pointer to a naturally-aligned 32-bit value
+ *
+ * See __swahw32() for details of wordswapping
+ */
+static __inline__ void __swahw32s(__u32 *p)
+{
+#ifdef __arch_swahw32s
+ __arch_swahw32s(p);
+#else
+ *p = __swahw32p(p);
+#endif
+}
+
+/**
+ * __swahb32s - high and low byteswap a 32-bit value in-place
+ * @p: pointer to a naturally-aligned 32-bit value
+ *
+ * See __swahb32() for details of high and low byte swapping
+ */
+static __inline__ void __swahb32s(__u32 *p)
+{
+#ifdef __arch_swahb32s
+ __arch_swahb32s(p);
+#else
+ *p = __swahb32p(p);
+#endif
+}
+
+
+#endif /* _LINUX_SWAB_H */
include $(TOPDIR)/rules.mk
PKG_NAME:=libdeflate
-PKG_VERSION:=1.19
-PKG_RELEASE:=1
+PKG_VERSION:=1.20
+PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/ebiggers/libdeflate/releases/download/v$(PKG_VERSION)
-PKG_HASH:=d9bb9bdd8cc5a8c1f7f6226fa0053dd72861e15f366e7ff7d0d191eac16d66f3
+PKG_HASH:=c52cf0239fd644d71c9e88613dd7431a5306ebee1280c5791c71ca264869250a
include $(INCLUDE_DIR)/host-build.mk
--- /dev/null
+From e522b1d09d3536ddc15459b4259150f4a53ee65a Mon Sep 17 00:00:00 2001
+From: Eric Biggers <ebiggers@google.com>
+Date: Thu, 4 Apr 2024 20:16:33 -0400
+Subject: [PATCH] lib/x86: increase AVX-VNNI gcc prerequisite to 12.1
+
+Although gcc 11.1 supports AVX-VNNI, a popular distro pairs it with a
+binutils version that does not. Require gcc 12 instead.
+
+Resolves https://github.com/ebiggers/libdeflate/issues/365
+---
+ lib/x86/adler32_impl.h | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/lib/x86/adler32_impl.h
++++ b/lib/x86/adler32_impl.h
+@@ -52,8 +52,15 @@
+ /*
+ * AVX-VNNI implementation. This is used on CPUs that have AVX2 and AVX-VNNI
+ * but don't have AVX-512, for example Intel Alder Lake.
++ *
++ * Unusually for a new CPU feature, gcc added support for the AVX-VNNI
++ * intrinsics (in gcc 11.1) slightly before binutils added support for
++ * assembling AVX-VNNI instructions (in binutils 2.36). Distros can reasonably
++ * have gcc 11 with binutils 2.35. Because of this issue, we check for gcc 12
++ * instead of gcc 11. (libdeflate supports direct compilation without a
++ * configure step, so checking the binutils version is not always an option.)
+ */
+-#if GCC_PREREQ(11, 1) || CLANG_PREREQ(12, 0, 13000000) || MSVC_PREREQ(1930)
++#if GCC_PREREQ(12, 1) || CLANG_PREREQ(12, 0, 13000000) || MSVC_PREREQ(1930)
+ # define adler32_x86_avx2_vnni adler32_x86_avx2_vnni
+ # define SUFFIX _avx2_vnni
+ # define ATTRIBUTES _target_attribute("avx2,avxvnni")
include $(TOPDIR)/rules.mk
PKG_NAME:=missing-macros
-PKG_RELEASE:=11
+PKG_RELEASE:=12
include $(INCLUDE_DIR)/host-build.mk
$(INSTALL_DATA) ./src/m4/*.m4 $(STAGING_DIR_HOST)/share/aclocal/
$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin
$(INSTALL_BIN) ./src/bin/* $(STAGING_DIR_HOST)/bin/
+ $(LN) makeinfo $(STAGING_DIR_HOST)/bin/texi2any
+ $(LN) makeinfo $(STAGING_DIR_HOST)/bin/texi2pdf
+ $(LN) makeinfo $(STAGING_DIR_HOST)/bin/texi2dvi
+ $(LN) makeinfo $(STAGING_DIR_HOST)/bin/pdftexi2dvi
+ $(LN) makeinfo $(STAGING_DIR_HOST)/bin/texi2html
endef
$(eval $(call HostBuild))
include $(TOPDIR)/rules.mk
PKG_NAME:=mold
-PKG_VERSION:=2.3.2
+PKG_VERSION:=2.31.0
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL_FILE:=v$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/rui314/mold/archive/refs/tags
-PKG_HASH:=db172c0e97606565a81e37995bf5c911606d3f3b9f3829e92cd26985c9b0ed3b
+PKG_HASH:=3dc3af83a5d22a4b29971bfad17261851d426961c665480e2ca294e5c74aa1e5
include $(INCLUDE_DIR)/host-build.mk
include $(INCLUDE_DIR)/cmake.mk
--keep-system-cflags \
--keep-system-libs \
--define-variable=prefix="${STAGING_PREFIX}" \
+--define-variable=prefix_host="${STAGING_DIR_HOST}" \
+--define-variable=prefix_hostpkg="${STAGING_DIR_HOSTPKG}" \
--define-variable=exec_prefix="${STAGING_PREFIX}" \
--define-variable=bindir="${STAGING_PREFIX}/bin" \
$PKG_CONFIG_EXTRAARGS "$@"
PKG_LICENSE:=Zlib
PKG_LICENSE_FILES:=README
-PKG_CPE_ID:=cpe:/a:gnu:zlib
+PKG_CPE_ID:=cpe:/a:zlib:zlib
HOST_BUILD_PARALLEL:=1
HOSTCC:= $(HOSTCC_NOCACHE)
-HOST_CFLAGS += \
- -DZSTDCLI_CLEVEL_MAX=20
+HOST_CFLAGS += $(HOST_FPIC)
HOST_MAKE_FLAGS += \
BACKTRACE=0 \
endef
define Host/Install
- +$(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/lib install-mt-pc install-static install-includes PREFIX=$(HOST_BUILD_PREFIX)
+ +$(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/lib install-static install-includes PREFIX=$(HOST_BUILD_PREFIX)
+ +$(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/lib install-pc MT=1 PREFIX=$(HOST_BUILD_PREFIX)
+$(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/programs install PREFIX=$(HOST_BUILD_PREFIX)
endef
--- /dev/null
+From f1f1ae369a4cefd3474b3528e8d1847b18750605 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sat, 6 Apr 2024 14:41:54 +0200
+Subject: [PATCH] Provide variant pkg-config file for multi-threaded static lib
+
+Multi-threaded static library require -pthread to correctly link and works.
+The pkg-config we provide tho only works with dynamic multi-threaded library
+and won't provide the correct libs and cflags values if lib-mt is used.
+
+To handle this, introduce an env variable MT to permit advanced user to
+install and generate a correct pkg-config file for lib-mt or detect if
+lib-mt target is called.
+
+With MT env set on calling make install-pc, libzstd.pc.in is a
+pkg-config file for a multi-threaded static library.
+
+On calling make lib-mt, a libzstd.pc is generated for a multi-threaded
+static library as it's what asked by the user by forcing it.
+
+libzstd.pc is changed to PHONY to force regeneration of it on calling
+lib targets or install-pc to handle case where the same directory is
+used for mixed compilation.
+
+This was notice while migrating from meson to make build system where
+meson generates a correct .pc file while make doesn't.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ lib/Makefile | 20 +++++++++++++++++++-
+ lib/README.md | 4 ++++
+ lib/libzstd.pc.in | 4 ++--
+ 3 files changed, 25 insertions(+), 3 deletions(-)
+
+--- a/lib/Makefile
++++ b/lib/Makefile
+@@ -63,6 +63,8 @@ CPPFLAGS_DYNLIB += -DZSTD_MULTITHREAD #
+ LDFLAGS_DYNLIB += -pthread
+ CPPFLAGS_STATICLIB += # static library build defaults to single-threaded
+
++# pkg-config Libs.private points to LDFLAGS_DYNLIB
++PCLIB := $(LDFLAGS_DYNLIB)
+
+ ifeq ($(findstring GCC,$(CCVER)),GCC)
+ decompress/zstd_decompress_block.o : CFLAGS+=-fno-tree-vectorize
+@@ -186,12 +188,15 @@ lib : libzstd.a libzstd
+ %-mt : CPPFLAGS_DYNLIB := -DZSTD_MULTITHREAD
+ %-mt : CPPFLAGS_STATICLIB := -DZSTD_MULTITHREAD
+ %-mt : LDFLAGS_DYNLIB := -pthread
++%-mt : PCLIB :=
++%-mt : PCMTLIB := $(LDFLAGS_DYNLIB)
+ %-mt : %
+ @echo multi-threaded build completed
+
+ %-nomt : CPPFLAGS_DYNLIB :=
+ %-nomt : LDFLAGS_DYNLIB :=
+ %-nomt : CPPFLAGS_STATICLIB :=
++%-nomt : PCLIB :=
+ %-nomt : %
+ @echo single-threaded build completed
+
+@@ -292,6 +297,14 @@ PCLIBPREFIX := $(if $(findstring $(LIBDI
+ # to PREFIX, rather than as a resolved value.
+ PCEXEC_PREFIX := $(if $(HAS_EXPLICIT_EXEC_PREFIX),$(EXEC_PREFIX),$${prefix})
+
++
++ifneq ($(MT),)
++ PCLIB :=
++ PCMTLIB := $(LDFLAGS_DYNLIB)
++else
++ PCLIB := $(LDFLAGS_DYNLIB)
++endif
++
+ ifneq (,$(filter $(UNAME),FreeBSD NetBSD DragonFly))
+ PKGCONFIGDIR ?= $(PREFIX)/libdata/pkgconfig
+ else
+@@ -308,6 +321,10 @@ INSTALL_PROGRAM ?= $(INSTALL)
+ INSTALL_DATA ?= $(INSTALL) -m 644
+
+
++# pkg-config library define.
++# For static single-threaded library declare -pthread in Libs.private
++# For static multi-threaded library declare -pthread in Libs and Cflags
++.PHONY: libzstd.pc
+ libzstd.pc: libzstd.pc.in
+ @echo creating pkgconfig
+ @sed \
+@@ -316,7 +333,8 @@ libzstd.pc: libzstd.pc.in
+ -e 's|@INCLUDEDIR@|$(PCINCPREFIX)$(PCINCDIR)|' \
+ -e 's|@LIBDIR@|$(PCLIBPREFIX)$(PCLIBDIR)|' \
+ -e 's|@VERSION@|$(VERSION)|' \
+- -e 's|@LIBS_PRIVATE@|$(LDFLAGS_DYNLIB)|' \
++ -e 's|@LIBS_MT@|$(PCMTLIB)|' \
++ -e 's|@LIBS_PRIVATE@|$(PCLIB)|' \
+ $< >$@
+
+ .PHONY: install
+--- a/lib/README.md
++++ b/lib/README.md
+@@ -27,12 +27,16 @@ Enabling multithreading requires 2 condi
+
+ For convenience, we provide a build target to generate multi and single threaded libraries:
+ - Force enable multithreading on both dynamic and static libraries by appending `-mt` to the target, e.g. `make lib-mt`.
++ Note that the `.pc` generated on calling `make lib-mt` will already include the require Libs and Cflags.
+ - Force disable multithreading on both dynamic and static libraries by appending `-nomt` to the target, e.g. `make lib-nomt`.
+ - By default, as mentioned before, dynamic library is multithreaded, and static library is single-threaded, e.g. `make lib`.
+
+ When linking a POSIX program with a multithreaded version of `libzstd`,
+ note that it's necessary to invoke the `-pthread` flag during link stage.
+
++The `.pc` generated from `make install` or `make install-pc` always assume a single-threaded static library
++is compiled. To correctly generate a `.pc` for the multi-threaded static library, set `MT=1` as ENV variable.
++
+ Multithreading capabilities are exposed
+ via the [advanced API defined in `lib/zstd.h`](https://github.com/facebook/zstd/blob/v1.4.3/lib/zstd.h#L351).
+
+--- a/lib/libzstd.pc.in
++++ b/lib/libzstd.pc.in
+@@ -11,6 +11,6 @@ Name: zstd
+ Description: fast lossless compression algorithm library
+ URL: https://facebook.github.io/zstd/
+ Version: @VERSION@
+-Libs: -L${libdir} -lzstd
++Libs: -L${libdir} -lzstd @LIBS_MT@
+ Libs.private: @LIBS_PRIVATE@
+-Cflags: -I${includedir}
++Cflags: -I${includedir} @LIBS_MT@
+++ /dev/null
-From 5886e6a45b3c20c8d8f837657d1506b580434136 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 6 Apr 2024 14:41:54 +0200
-Subject: [PATCH] Provide variant pkg-config file for multi-threaded static lib
-
-Multi-threaded static library require -pthread to correctly link and works.
-The pkg-config we provide tho only works with dynamic multi-threaded library
-and won't provide the correct libs and cflags values if lib-mt is used.
-
-To handle this, introduce a variant of libzstd.pc.in, mt-libzstd.pc.in
-and intoduce a new make target, install-mt-pc to permit advanced user to
-install and generate a correct pkg-config file for lib-mt.
-
-This was notice while migrating from meson to make build system where
-meson generates a correct .pc file while make doesn't.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- lib/Makefile | 16 ++++++++++++++++
- lib/README.md | 4 ++++
- lib/mt-libzstd.pc.in | 15 +++++++++++++++
- 3 files changed, 35 insertions(+)
- create mode 100644 lib/mt-libzstd.pc.in
-
-diff --git a/lib/Makefile b/lib/Makefile
-index 8bfdade9..4933f0e9 100644
---- a/lib/Makefile
-+++ b/lib/Makefile
-@@ -319,6 +319,17 @@ libzstd.pc: libzstd.pc.in
- -e 's|@LIBS_PRIVATE@|$(LDFLAGS_DYNLIB)|' \
- $< >$@
-
-+mt-libzstd.pc: mt-libzstd.pc.in
-+ @echo creating pkgconfig
-+ @sed \
-+ -e 's|@PREFIX@|$(PREFIX)|' \
-+ -e 's|@EXEC_PREFIX@|$(PCEXEC_PREFIX)|' \
-+ -e 's|@INCLUDEDIR@|$(PCINCPREFIX)$(PCINCDIR)|' \
-+ -e 's|@LIBDIR@|$(PCLIBPREFIX)$(PCLIBDIR)|' \
-+ -e 's|@VERSION@|$(VERSION)|' \
-+ -e 's|@LIBS_PRIVATE@|$(LDFLAGS_DYNLIB)|' \
-+ $< >$@
-+
- .PHONY: install
- install: install-pc install-static install-shared install-includes
- @echo zstd static and shared library installed
-@@ -328,6 +339,11 @@ install-pc: libzstd.pc
- [ -e $(DESTDIR)$(PKGCONFIGDIR) ] || $(INSTALL) -d -m 755 $(DESTDIR)$(PKGCONFIGDIR)/
- $(INSTALL_DATA) libzstd.pc $(DESTDIR)$(PKGCONFIGDIR)/
-
-+.PHONY: install-mt-pc
-+install-mt-pc: mt-libzstd.pc
-+ [ -e $(DESTDIR)$(PKGCONFIGDIR) ] || $(INSTALL) -d -m 755 $(DESTDIR)$(PKGCONFIGDIR)/
-+ $(INSTALL_DATA) mt-libzstd.pc $(DESTDIR)$(PKGCONFIGDIR)/libzstd.pc
-+
- .PHONY: install-static
- install-static:
- # only generate libzstd.a if it's not already present
-diff --git a/lib/README.md b/lib/README.md
-index a560f06c..3038bc7a 100644
---- a/lib/README.md
-+++ b/lib/README.md
-@@ -33,6 +33,10 @@ For convenience, we provide a build target to generate multi and single threaded
- When linking a POSIX program with a multithreaded version of `libzstd`,
- note that it's necessary to invoke the `-pthread` flag during link stage.
-
-+The `.pc` generated from `make install` or `make install-pc` always assume a single-threaded static library
-+is compiled. If `make lib-mt` is used, to correctly generate a `.pc` for the multi-threaded static library,
-+`make install-mt-pc` is needed.
-+
- Multithreading capabilities are exposed
- via the [advanced API defined in `lib/zstd.h`](https://github.com/facebook/zstd/blob/v1.4.3/lib/zstd.h#L351).
-
-diff --git a/lib/mt-libzstd.pc.in b/lib/mt-libzstd.pc.in
-new file mode 100644
-index 00000000..cd93301a
---- /dev/null
-+++ b/lib/mt-libzstd.pc.in
-@@ -0,0 +1,15 @@
-+# ZSTD - standard compression algorithm
-+# Copyright (c) Meta Platforms, Inc. and affiliates.
-+# BSD 2-Clause License (https://opensource.org/licenses/bsd-license.php)
-+
-+prefix=@PREFIX@
-+exec_prefix=@EXEC_PREFIX@
-+includedir=@INCLUDEDIR@
-+libdir=@LIBDIR@
-+
-+Name: zstd
-+Description: fast lossless compression algorithm library
-+URL: https://facebook.github.io/zstd/
-+Version: @VERSION@
-+Libs: -L${libdir} -lzstd @LIBS_PRIVATE@
-+Cflags: -I${includedir} @LIBS_PRIVATE@
---
-2.43.0
-
projects / openwrt / staging / xback.git / commitdiff