realtek: clock driver: cosmetic fixes

Especially do the following:

- Fix wrong DRAM function definitions (although never used).
- Print speed ranges during startup only if changing is really supported.
- Add some namespace prefixes.
- Use kernel common type "unsigned long" for clock rate

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[SPDX already has right comment type, keep it]
Signed-off-by: Sander Vanheule <sander@svanheule.net>

diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
index 8a8b5f4ced1d0fb597b8d4bbcd869b89292407e0..dc6df141f03900d2cded0ab97dddde90c39ddc9a 100644 (file)
--- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
+++ b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
@@ -34,15 +34,13 @@
 #define RTCL_DDR2              2
 #define RTCL_DDR3              3
 
-#define REG_CTRL0              0
-#define REG_CTRL1              1
-#define REG_COUNT              2
+#define RTCL_REGCNT            2
 
 #define RTCL_XTAL_RATE         25000000
 
 #define RTCL_SOC_CLK(soc, clk) ((soc << 8) + clk)
 
-static const int rtcl_regs[RTCL_SOCCNT][REG_COUNT][CLK_COUNT] = {
+static const int rtcl_regs[RTCL_SOCCNT][RTCL_REGCNT][CLK_COUNT] = {
        {
                {
                        RTL_SW_CORE_BASE + RTL838X_PLL_CPU_CTRL0,
@@ -74,7 +72,7 @@ static const int rtcl_regs[RTCL_SOCCNT][REG_COUNT][CLK_COUNT] = {
        }
 
 struct rtcl_reg_set {
-       unsigned int rate;
+       unsigned long rate;
        unsigned int ctrl0;
        unsigned int ctrl1;
 };
@@ -175,11 +173,7 @@ struct rtcl_rtab_set {
        const struct rtcl_reg_set *rset;
 };
 
-#define RTCL_RTAB_SET(_rset)                   \
-       {                                       \
-               .count = ARRAY_SIZE(_rset),     \
-               .rset = _rset,                  \
-       }
+#define RTCL_RTAB_SET(_rset) { .count = ARRAY_SIZE(_rset), .rset = _rset }
 
 static const struct rtcl_rtab_set rtcl_rtab_set[RTCL_SOCCNT][CLK_COUNT] = {
        {
@@ -287,13 +281,13 @@ struct rtcl_ccu *rtcl_ccu;
 extern void    rtcl_838x_dram_start(void);
 extern int     rtcl_838x_dram_size;
 
-extern void    (*rtcl_838x_dram_set_rate)(int clk_idx, int ctrl0, int ctrl1);
+extern void    rtcl_838x_dram_set_rate(int clk_idx, int ctrl0, int ctrl1);
 static void    (*rtcl_838x_sram_set_rate)(int clk_idx, int ctrl0, int ctrl1);
 
 extern void    rtcl_839x_dram_start(void);
 extern int     rtcl_839x_dram_size;
 
-extern void    (*rtcl_839x_dram_set_rate)(int clk_idx, int ctrl0, int ctrl1);
+extern void    rtcl_839x_dram_set_rate(int clk_idx, int ctrl0, int ctrl1);
 static void    (*rtcl_839x_sram_set_rate)(int clk_idx, int ctrl0, int ctrl1);
 
 /*
@@ -490,12 +484,14 @@ int rtcl_register_clkhw(int clk_idx)
        int ret;
        struct clk *clk;
        struct clk_init_data hw_init = { };
+       struct clk_parent_data parent_data = { };
        struct rtcl_clk *rclk = &rtcl_ccu->clks[clk_idx];
-       struct clk_parent_data parent_data = { .fw_name = rtcl_clk_info[clk_idx].parent_name };
 
        rclk->idx = clk_idx;
        rclk->hw.init = &hw_init;
 
+       parent_data.fw_name = rtcl_clk_info[clk_idx].parent_name;
+
        hw_init.num_parents = 1;
        hw_init.ops = &rtcl_clk_ops;
        hw_init.parent_data = &parent_data;
@@ -671,6 +667,8 @@ void rtcl_ccu_log_late(void)
 
        for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) {
                rclk = &rtcl_ccu->clks[clk_idx];
+               if (rclk->min == rclk->max)
+                       continue;
                overclock |= rclk->max > rclk->startup;
                sprintf(clkinfo, ", %s %lu-%lu MHz", rtcl_clk_info[clk_idx].display_name,
                        rclk->min / 1000000, rclk->max / 1000000);