Merge "Explicitly disable the SPME bit in MDCR_EL3" into integration

[project/bcm63xx/atf.git] / readme.rst

diff --git a/readme.rst b/readme.rst
index 6846419978ec99d2221a27f71275f922af15b16f..b5038084d2da09b9c96cb6e18cb6e6a5bb2dff3d 100644 (file)
--- a/readme.rst
+++ b/readme.rst
@@ -156,8 +156,8 @@ Functionality
    The use of pointer authentication in the normal world is enabled whenever
    architectural support is available, without the need for additional build
    flags. Use of pointer authentication in the secure world remains an
-   experimental configuration at this time and requires the ``ENABLE_PAUTH``
-   build flag to be set.
+   experimental configuration at this time and requires the
+   ``BRANCH_PROTECTION`` option to be set to non-zero.
 
 -  Position-Independent Executable (PIE) support. Initially for BL31 only, with
    further support to be added in a future release.
@@ -198,8 +198,8 @@ The FVP models used are Version 11.6 Build 45, unless otherwise stated.
 -  ``FVP_Base_Cortex-A76x4``
 -  ``FVP_Base_Cortex-A76AEx4``
 -  ``FVP_Base_Cortex-A76AEx8``
+-  ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
 -  ``FVP_Base_Neoverse-N1x4``
--  ``FVP_Base_Deimos``
 -  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
 -  ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
 -  ``FVP_RD_E1Edge`` (Version 11.3 build 42)
@@ -222,7 +222,7 @@ All the above platforms have been tested with `Linaro Release 18.04`_.
 
 This release also contains the following platform support:
 
--  Allwinner sun50i_a64 and sun50i_h6
+-  Allwinner sun50i (A64, H5, and H6) SoCs
 -  Amlogic Meson S905 (GXBB)
 -  Amlogic Meson S905x (GXL)
 -  Arm Juno Software Development Platform