starfive: add new target for StarFive JH7100/7110 SoC
[openwrt/staging/nbd.git] / target / linux / starfive / patches-6.1 / 1004-RISC-V-Add-StarFive-JH7100-audio-clock-node.patch
1 From 6a9196186f9630006c3db022bcc0bd5796f4fae5 Mon Sep 17 00:00:00 2001
2 From: Emil Renner Berthing <kernel@esmil.dk>
3 Date: Sat, 20 Nov 2021 17:13:22 +0100
4 Subject: [PATCH 1004/1024] RISC-V: Add StarFive JH7100 audio clock node
5
6 Add device tree node for the audio clocks on the StarFive JH7100 RISC-V
7 SoC.
8
9 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
10 ---
11 arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++
12 1 file changed, 10 insertions(+)
13
14 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
15 +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
16 @@ -133,6 +133,16 @@
17 riscv,ndev = <133>;
18 };
19
20 + audclk: clock-controller@10480000 {
21 + compatible = "starfive,jh7100-audclk";
22 + reg = <0x0 0x10480000 0x0 0x10000>;
23 + clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
24 + <&clkgen JH7100_CLK_AUDIO_12288>,
25 + <&clkgen JH7100_CLK_DOM7AHB_BUS>;
26 + clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
27 + #clock-cells = <1>;
28 + };
29 +
30 clkgen: clock-controller@11800000 {
31 compatible = "starfive,jh7100-clkgen";
32 reg = <0x0 0x11800000 0x0 0x10000>;