target/linux/starfive/patches-6.1/0098-riscv-dts-starfive-Add-full-support-for-JH7110-and-V.patch

   1 From 16e358dcf5e072c82f643d11add5b7e55b36a6f8 Mon Sep 17 00:00:00 2001
   2 From: "shanlong.li" <shanlong.li@starfivetech.com>
   3 Date: Wed, 31 May 2023 01:53:31 -0700
   4 Subject: [PATCH 098/122] riscv: dts: starfive: Add full support for JH7110 and
   5  VisionFive 2 board
   6
   7 Merge all StarFive dts patches together.
   8
   9 Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
  10 ---
  11  .../jh7110-starfive-visionfive-2-v1.3b.dts    |   8 +-
  12  .../jh7110-starfive-visionfive-2.dtsi         | 338 ++++++++++++
  13  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 506 +++++++++++++++++-
  14  3 files changed, 847 insertions(+), 5 deletions(-)
  15
  16 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
  17 +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
  18 @@ -28,8 +28,8 @@
  19         motorcomm,tx-clk-adj-enabled;
  20         motorcomm,tx-clk-100-inverted;
  21         motorcomm,tx-clk-1000-inverted;
  22 -       rx-clk-driver-strength = <0x6>;
  23 -       rx-data-driver-strength = <0x3>;
  24 +       motorcomm,rx-clk-driver-strength = <0x6>;
  25 +       motorcomm,rx-data-driver-strength = <0x3>;
  26         rx-internal-delay-ps = <1500>;
  27         tx-internal-delay-ps = <1500>;
  28  };
  29 @@ -37,8 +37,8 @@
  30  &phy1 {
  31         motorcomm,tx-clk-adj-enabled;
  32         motorcomm,tx-clk-100-inverted;
  33 -       rx-clk-driver-strength = <0x6>;
  34 -       rx-data-driver-strength = <0x3>;
  35 +       motorcomm,rx-clk-driver-strength = <0x6>;
  36 +       motorcomm,rx-data-driver-strength = <0x3>;
  37         rx-internal-delay-ps = <300>;
  38         tx-internal-delay-ps = <0>;
  39  };
  40 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
  41 +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
  42 @@ -33,11 +33,64 @@
  43                 reg = <0x0 0x40000000 0x1 0x0>;
  44         };
  45
  46 +       reserved-memory {
  47 +               #address-cells = <2>;
  48 +               #size-cells = <2>;
  49 +               ranges;
  50 +
  51 +               linux,cma {
  52 +                       compatible = "shared-dma-pool";
  53 +                       reusable;
  54 +                       size = <0x0 0x20000000>;
  55 +                       alignment = <0x0 0x1000>;
  56 +                       alloc-ranges = <0x0 0x80000000 0x0 0x20000000>;
  57 +                       linux,cma-default;
  58 +               };
  59 +       };
  60 +
  61 +       thermal-zones {
  62 +               cpu-thermal {
  63 +                       polling-delay-passive = <250>;
  64 +                       polling-delay = <15000>;
  65 +
  66 +                       thermal-sensors = <&sfctemp>;
  67 +
  68 +                       cooling-maps {
  69 +                       };
  70 +
  71 +                       trips {
  72 +                               cpu_alert0: cpu_alert0 {
  73 +                                       /* milliCelsius */
  74 +                                       temperature = <75000>;
  75 +                                       hysteresis = <2000>;
  76 +                                       type = "passive";
  77 +                               };
  78 +
  79 +                               cpu_crit: cpu_crit {
  80 +                                       /* milliCelsius */
  81 +                                       temperature = <90000>;
  82 +                                       hysteresis = <2000>;
  83 +                                       type = "critical";
  84 +                               };
  85 +                       };
  86 +               };
  87 +       };
  88 +
  89         gpio-restart {
  90                 compatible = "gpio-restart";
  91                 gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
  92                 priority = <224>;
  93         };
  94 +
  95 +       clk_ext_camera: clk_ext_camera {
  96 +               compatible = "fixed-clock";
  97 +               #clock-cells = <0>;
  98 +               clock-frequency = <24000000>;
  99 +       };
 100 +};
 101 +
 102 +&dvp_clk {
 103 +       clock-frequency = <74250000>;
 104  };
 105
 106  &gmac0_rgmii_rxin {
 107 @@ -56,6 +109,10 @@
 108         clock-frequency = <50000000>;
 109  };
 110
 111 +&hdmitx0_pixelclk {
 112 +       clock-frequency = <297000000>;
 113 +};
 114 +
 115  &i2srx_bclk_ext {
 116         clock-frequency = <12288000>;
 117  };
 118 @@ -88,6 +145,39 @@
 119         clock-frequency = <49152000>;
 120  };
 121
 122 +&csi2rx {
 123 +       status = "okay";
 124 +
 125 +       assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
 126 +       assigned-clock-rates = <297000000>;
 127 +
 128 +       ports {
 129 +               #address-cells = <1>;
 130 +               #size-cells = <0>;
 131 +
 132 +               port@0 {
 133 +                       reg = <0>;
 134 +
 135 +                       csi2rx_from_imx219: endpoint {
 136 +                               remote-endpoint = <&imx219_to_csi2rx>;
 137 +                               bus-type = <4>;
 138 +                               clock-lanes = <0>;
 139 +                               data-lanes = <1 2>;
 140 +                               status = "okay";
 141 +                       };
 142 +               };
 143 +
 144 +               port@1 {
 145 +                       reg = <1>;
 146 +
 147 +                       csi2rx_to_vin: endpoint {
 148 +                               remote-endpoint = <&vin_from_csi2rx>;
 149 +                               status = "okay";
 150 +                       };
 151 +               };
 152 +       };
 153 +};
 154 +
 155  &gmac0 {
 156         phy-handle = <&phy0>;
 157         phy-mode = "rgmii-id";
 158 @@ -148,6 +238,20 @@
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&i2c5_pins>;
 161         status = "okay";
 162 +
 163 +       axp15060: pmic@36 {
 164 +               compatible = "x-powers,axp15060";
 165 +               reg = <0x36>;
 166 +
 167 +               regulators {
 168 +                       vdd_cpu: dcdc2 {
 169 +                               regulator-always-on;
 170 +                               regulator-min-microvolt = <500000>;
 171 +                               regulator-max-microvolt = <1540000>;
 172 +                               regulator-name = "vdd-cpu";
 173 +                       };
 174 +               };
 175 +       };
 176  };
 177
 178  &i2c6 {
 179 @@ -158,6 +262,121 @@
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&i2c6_pins>;
 182         status = "okay";
 183 +
 184 +       imx219: imx219@10 {
 185 +               compatible = "sony,imx219";
 186 +               reg = <0x10>;
 187 +               clocks = <&clk_ext_camera>;
 188 +               reset-gpio = <&sysgpio 18 0>;
 189 +               rotation = <0>;
 190 +               orientation = <1>;
 191 +
 192 +               port {
 193 +                       imx219_to_csi2rx: endpoint {
 194 +                               remote-endpoint = <&csi2rx_from_imx219>;
 195 +                               bus-type = <4>;
 196 +                               clock-lanes = <0>;
 197 +                               data-lanes = <1 2>;
 198 +                               link-frequencies = /bits/ 64 <456000000>;
 199 +                       };
 200 +               };
 201 +       };
 202 +};
 203 +
 204 +&mmc0 {
 205 +       max-frequency = <100000000>;
 206 +       bus-width = <8>;
 207 +       cap-mmc-highspeed;
 208 +       mmc-ddr-1_8v;
 209 +       mmc-hs200-1_8v;
 210 +       non-removable;
 211 +       cap-mmc-hw-reset;
 212 +       post-power-on-delay-ms = <200>;
 213 +       status = "okay";
 214 +};
 215 +
 216 +&mmc1 {
 217 +       max-frequency = <100000000>;
 218 +       bus-width = <4>;
 219 +       no-sdio;
 220 +       no-mmc;
 221 +       broken-cd;
 222 +       cap-sd-highspeed;
 223 +       post-power-on-delay-ms = <200>;
 224 +       status = "okay";
 225 +};
 226 +
 227 +&pcie0 {
 228 +       pinctrl-names = "default";
 229 +       reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
 230 +       phys = <&pciephy0>;
 231 +       status = "okay";
 232 +};
 233 +
 234 +&pcie1 {
 235 +       pinctrl-names = "default";
 236 +       reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
 237 +       phys = <&pciephy1>;
 238 +       status = "okay";
 239 +};
 240 +
 241 +&ptc {
 242 +       pinctrl-names = "default";
 243 +       pinctrl-0 = <&pwm_pins>;
 244 +       status = "okay";
 245 +};
 246 +
 247 +&qspi {
 248 +       #address-cells = <1>;
 249 +       #size-cells = <0>;
 250 +
 251 +       nor_flash: flash@0 {
 252 +               compatible = "jedec,spi-nor";
 253 +               reg=<0>;
 254 +               cdns,read-delay = <5>;
 255 +               spi-max-frequency = <12000000>;
 256 +               cdns,tshsl-ns = <1>;
 257 +               cdns,tsd2d-ns = <1>;
 258 +               cdns,tchsh-ns = <1>;
 259 +               cdns,tslch-ns = <1>;
 260 +
 261 +               partitions {
 262 +                       compatible = "fixed-partitions";
 263 +                       #address-cells = <1>;
 264 +                       #size-cells = <1>;
 265 +
 266 +                       spl@0 {
 267 +                               reg = <0x0 0x20000>;
 268 +                       };
 269 +                       uboot@100000 {
 270 +                               reg = <0x100000 0x300000>;
 271 +                       };
 272 +                       data@f00000 {
 273 +                               reg = <0xf00000 0x100000>;
 274 +                       };
 275 +               };
 276 +       };
 277 +};
 278 +
 279 +&stfcamss {
 280 +       status = "okay";
 281 +
 282 +       ports {
 283 +               #address-cells = <1>;
 284 +               #size-cells = <0>;
 285 +
 286 +               port@1 {
 287 +                       reg = <1>;
 288 +                       #address-cells = <1>;
 289 +                       #size-cells = <0>;
 290 +
 291 +                       vin_from_csi2rx: endpoint@1 {
 292 +                               reg = <1>;
 293 +                               remote-endpoint = <&csi2rx_to_vin>;
 294 +                               status = "okay";
 295 +                       };
 296 +               };
 297 +       };
 298  };
 299
 300  &sysgpio {
 301 @@ -217,6 +436,98 @@
 302                 };
 303         };
 304
 305 +       pcie0_wake_default: pcie0_wake_default {
 306 +               wake-pins {
 307 +                       pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
 308 +                       bias-disable;
 309 +                       drive-strength = <2>;
 310 +                       input-enable;
 311 +                       input-schmitt-disable;
 312 +                       slew-rate = <0>;
 313 +               };
 314 +       };
 315 +
 316 +       pcie0_clkreq_default: pcie0_clkreq_default {
 317 +               clkreq-pins {
 318 +                       bias-disable;
 319 +                       pinmux = <GPIOMUX(27, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
 320 +                       drive-strength = <2>;
 321 +                       input-enable;
 322 +                       input-schmitt-disable;
 323 +                       slew-rate = <0>;
 324 +               };
 325 +       };
 326 +
 327 +       pcie1_wake_default: pcie1_wake_default {
 328 +               wake-pins {
 329 +                       bias-disable;
 330 +                       pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
 331 +                       drive-strength = <2>;
 332 +                       input-enable;
 333 +                       input-schmitt-disable;
 334 +                       slew-rate = <0>;
 335 +               };
 336 +       };
 337 +
 338 +       pcie1_clkreq_default: pcie1_clkreq_default {
 339 +               clkreq-pins {
 340 +                       bias-disable;
 341 +                       pinmux = <GPIOMUX(29, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
 342 +                       drive-strength = <2>;
 343 +                       input-enable;
 344 +                       input-schmitt-disable;
 345 +                       slew-rate = <0>;
 346 +               };
 347 +       };
 348 +
 349 +       pwm_pins: pwm-0 {
 350 +               pwm-pins {
 351 +                       pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
 352 +                                       GPOEN_SYS_PWM0_CHANNEL0, GPI_NONE)>,
 353 +                                       <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
 354 +                                       GPOEN_SYS_PWM0_CHANNEL1, GPI_NONE)>;
 355 +                       bias-disable;
 356 +                       drive-strength = <12>;
 357 +                       input-disable;
 358 +                       input-schmitt-disable;
 359 +                       slew-rate = <0>;
 360 +               };
 361 +       };
 362 +
 363 +       tdm0_pins: tdm0-pins {
 364 +               tdm0-pins-tx {
 365 +                       pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD,
 366 +                                             GPOEN_ENABLE,
 367 +                                             GPI_NONE)>;
 368 +                       bias-pull-up;
 369 +                       drive-strength = <2>;
 370 +                       input-disable;
 371 +                       input-schmitt-disable;
 372 +                       slew-rate = <0>;
 373 +               };
 374 +
 375 +               tdm0-pins-rx {
 376 +                       pinmux = <GPIOMUX(61, GPOUT_HIGH,
 377 +                                             GPOEN_DISABLE,
 378 +                                             GPI_SYS_TDM_RXD)>;
 379 +                       input-enable;
 380 +               };
 381 +
 382 +               tdm0-pins-sync {
 383 +                       pinmux = <GPIOMUX(63, GPOUT_HIGH,
 384 +                                             GPOEN_DISABLE,
 385 +                                             GPI_SYS_TDM_SYNC)>;
 386 +                       input-enable;
 387 +               };
 388 +
 389 +               tdm0-pins-pcmclk {
 390 +                       pinmux = <GPIOMUX(38, GPOUT_HIGH,
 391 +                                             GPOEN_DISABLE,
 392 +                                             GPI_SYS_TDM_CLK)>;
 393 +                       input-enable;
 394 +               };
 395 +       };
 396 +
 397         uart0_pins: uart0-0 {
 398                 tx-pins {
 399                         pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
 400 @@ -242,8 +553,35 @@
 401         };
 402  };
 403
 404 +&tdm {
 405 +       pinctrl-names = "default";
 406 +       pinctrl-0 = <&tdm0_pins>;
 407 +       status = "okay";
 408 +};
 409 +
 410  &uart0 {
 411         pinctrl-names = "default";
 412         pinctrl-0 = <&uart0_pins>;
 413         status = "okay";
 414  };
 415 +
 416 +&usb0 {
 417 +       dr_mode = "peripheral";
 418 +       status = "okay";
 419 +};
 420 +
 421 +&U74_1 {
 422 +       cpu-supply = <&vdd_cpu>;
 423 +};
 424 +
 425 +&U74_2 {
 426 +       cpu-supply = <&vdd_cpu>;
 427 +};
 428 +
 429 +&U74_3 {
 430 +       cpu-supply = <&vdd_cpu>;
 431 +};
 432 +
 433 +&U74_4 {
 434 +       cpu-supply = <&vdd_cpu>;
 435 +};
 436 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
 437 +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
 438 @@ -6,6 +6,7 @@
 439
 440  /dts-v1/;
 441  #include <dt-bindings/clock/starfive,jh7110-crg.h>
 442 +#include <dt-bindings/power/starfive,jh7110-pmu.h>
 443  #include <dt-bindings/reset/starfive,jh7110-crg.h>
 444
 445  / {
 446 @@ -53,6 +54,9 @@
 447                         next-level-cache = <&ccache>;
 448                         riscv,isa = "rv64imafdc_zba_zbb";
 449                         tlb-split;
 450 +                       operating-points-v2 = <&cpu_opp>;
 451 +                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
 452 +                       clock-names = "cpu";
 453
 454                         cpu1_intc: interrupt-controller {
 455                                 compatible = "riscv,cpu-intc";
 456 @@ -79,6 +83,9 @@
 457                         next-level-cache = <&ccache>;
 458                         riscv,isa = "rv64imafdc_zba_zbb";
 459                         tlb-split;
 460 +                       operating-points-v2 = <&cpu_opp>;
 461 +                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
 462 +                       clock-names = "cpu";
 463
 464                         cpu2_intc: interrupt-controller {
 465                                 compatible = "riscv,cpu-intc";
 466 @@ -105,6 +112,9 @@
 467                         next-level-cache = <&ccache>;
 468                         riscv,isa = "rv64imafdc_zba_zbb";
 469                         tlb-split;
 470 +                       operating-points-v2 = <&cpu_opp>;
 471 +                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
 472 +                       clock-names = "cpu";
 473
 474                         cpu3_intc: interrupt-controller {
 475                                 compatible = "riscv,cpu-intc";
 476 @@ -131,6 +141,9 @@
 477                         next-level-cache = <&ccache>;
 478                         riscv,isa = "rv64imafdc_zba_zbb";
 479                         tlb-split;
 480 +                       operating-points-v2 = <&cpu_opp>;
 481 +                       clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
 482 +                       clock-names = "cpu";
 483
 484                         cpu4_intc: interrupt-controller {
 485                                 compatible = "riscv,cpu-intc";
 486 @@ -164,6 +177,33 @@
 487                 };
 488         };
 489
 490 +       cpu_opp: opp-table-0 {
 491 +                       compatible = "operating-points-v2";
 492 +                       opp-shared;
 493 +                       opp-375000000 {
 494 +                                       opp-hz = /bits/ 64 <375000000>;
 495 +                                       opp-microvolt = <800000>;
 496 +                       };
 497 +                       opp-500000000 {
 498 +                                       opp-hz = /bits/ 64 <500000000>;
 499 +                                       opp-microvolt = <800000>;
 500 +                       };
 501 +                       opp-750000000 {
 502 +                                       opp-hz = /bits/ 64 <750000000>;
 503 +                                       opp-microvolt = <800000>;
 504 +                       };
 505 +                       opp-1500000000 {
 506 +                                       opp-hz = /bits/ 64 <1500000000>;
 507 +                                       opp-microvolt = <1040000>;
 508 +                       };
 509 +       };
 510 +
 511 +       dvp_clk: dvp-clock {
 512 +               compatible = "fixed-clock";
 513 +               clock-output-names = "dvp_clk";
 514 +               #clock-cells = <0>;
 515 +       };
 516 +
 517         gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
 518                 compatible = "fixed-clock";
 519                 clock-output-names = "gmac0_rgmii_rxin";
 520 @@ -188,6 +228,12 @@
 521                 #clock-cells = <0>;
 522         };
 523
 524 +       hdmitx0_pixelclk: hdmitx0-pixel-clock {
 525 +               compatible = "fixed-clock";
 526 +               clock-output-names = "hdmitx0_pixelclk";
 527 +               #clock-cells = <0>;
 528 +       };
 529 +
 530         i2srx_bclk_ext: i2srx-bclk-ext-clock {
 531                 compatible = "fixed-clock";
 532                 clock-output-names = "i2srx_bclk_ext";
 533 @@ -360,6 +406,99 @@
 534                         status = "disabled";
 535                 };
 536
 537 +               tdm: tdm@10090000 {
 538 +                       compatible = "starfive,jh7110-tdm";
 539 +                       reg = <0x0 0x10090000 0x0 0x1000>;
 540 +                       clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
 541 +                                <&syscrg JH7110_SYSCLK_TDM_APB>,
 542 +                                <&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
 543 +                                <&syscrg JH7110_SYSCLK_TDM_TDM>,
 544 +                                <&syscrg JH7110_SYSCLK_MCLK_INNER>,
 545 +                                <&tdm_ext>;
 546 +                       clock-names = "tdm_ahb", "tdm_apb",
 547 +                                     "tdm_internal", "tdm",
 548 +                                     "mclk_inner", "tdm_ext";
 549 +                       resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
 550 +                                <&syscrg JH7110_SYSRST_TDM_APB>,
 551 +                                <&syscrg JH7110_SYSRST_TDM_CORE>;
 552 +                       dmas = <&dma 20>, <&dma 21>;
 553 +                       dma-names = "rx","tx";
 554 +                       #sound-dai-cells = <0>;
 555 +                       status = "disabled";
 556 +               };
 557 +
 558 +               usb0: usb@10100000 {
 559 +                       compatible = "starfive,jh7110-usb";
 560 +                       ranges = <0x0 0x0 0x10100000 0x100000>;
 561 +                       #address-cells = <1>;
 562 +                       #size-cells = <1>;
 563 +                       starfive,stg-syscon = <&stg_syscon 0x4>;
 564 +                       clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
 565 +                                <&stgcrg JH7110_STGCLK_USB0_STB>,
 566 +                                <&stgcrg JH7110_STGCLK_USB0_APB>,
 567 +                                <&stgcrg JH7110_STGCLK_USB0_AXI>,
 568 +                                <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
 569 +                       clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
 570 +                       resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
 571 +                                <&stgcrg JH7110_STGRST_USB0_APB>,
 572 +                                <&stgcrg JH7110_STGRST_USB0_AXI>,
 573 +                                <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
 574 +                       reset-names = "pwrup", "apb", "axi", "utmi_apb";
 575 +                       status = "disabled";
 576 +
 577 +                       usb_cdns3: usb@0 {
 578 +                               compatible = "cdns,usb3";
 579 +                               reg = <0x0 0x10000>,
 580 +                                     <0x10000 0x10000>,
 581 +                                     <0x20000 0x10000>;
 582 +                               reg-names = "otg", "xhci", "dev";
 583 +                               interrupts = <100>, <108>, <110>;
 584 +                               interrupt-names = "host", "peripheral", "otg";
 585 +                               phys = <&usbphy0>;
 586 +                               phy-names = "cdns3,usb2-phy";
 587 +                       };
 588 +               };
 589 +
 590 +               usbphy0: phy@10200000 {
 591 +                       compatible = "starfive,jh7110-usb-phy";
 592 +                       reg = <0x0 0x10200000 0x0 0x10000>;
 593 +                       clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
 594 +                                <&stgcrg JH7110_STGCLK_USB0_APP_125>;
 595 +                       clock-names = "125m", "app_125m";
 596 +                       #phy-cells = <0>;
 597 +               };
 598 +
 599 +               pciephy0: phy@10210000 {
 600 +                       compatible = "starfive,jh7110-pcie-phy";
 601 +                       reg = <0x0 0x10210000 0x0 0x10000>;
 602 +                       #phy-cells = <0>;
 603 +               };
 604 +
 605 +               pciephy1: phy@10220000 {
 606 +                       compatible = "starfive,jh7110-pcie-phy";
 607 +                       reg = <0x0 0x10220000 0x0 0x10000>;
 608 +                       #phy-cells = <0>;
 609 +               };
 610 +
 611 +               stgcrg: clock-controller@10230000 {
 612 +                       compatible = "starfive,jh7110-stgcrg";
 613 +                       reg = <0x0 0x10230000 0x0 0x10000>;
 614 +                       clocks = <&osc>,
 615 +                                <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
 616 +                                <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
 617 +                                <&syscrg JH7110_SYSCLK_USB_125M>,
 618 +                                <&syscrg JH7110_SYSCLK_CPU_BUS>,
 619 +                                <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
 620 +                                <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
 621 +                                <&syscrg JH7110_SYSCLK_APB_BUS>;
 622 +                       clock-names = "osc", "hifi4_core",
 623 +                                     "stg_axiahb", "usb_125m",
 624 +                                     "cpu_bus", "hifi4_axi",
 625 +                                     "nocstg_bus", "apb_bus";
 626 +                       #clock-cells = <1>;
 627 +                       #reset-cells = <1>;
 628 +               };
 629 +
 630                 stg_syscon: syscon@10240000 {
 631                         compatible = "starfive,jh7110-stg-syscon", "syscon";
 632                         reg = <0x0 0x10240000 0x0 0x1000>;
 633 @@ -452,6 +591,45 @@
 634                         status = "disabled";
 635                 };
 636
 637 +               ptc: pwm@120d0000 {
 638 +                       compatible = "starfive,jh7110-pwm";
 639 +                       reg = <0x0 0x120d0000 0x0 0x10000>;
 640 +                       clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
 641 +                       resets = <&syscrg JH7110_SYSRST_PWM_APB>;
 642 +                       #pwm-cells=<3>;
 643 +                       status = "disabled";
 644 +               };
 645 +
 646 +               sfctemp: temperature-sensor@120e0000 {
 647 +                       compatible = "starfive,jh7110-temp";
 648 +                       reg = <0x0 0x120e0000 0x0 0x10000>;
 649 +                       clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
 650 +                                <&syscrg JH7110_SYSCLK_TEMP_APB>;
 651 +                       clock-names = "sense", "bus";
 652 +                       resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
 653 +                                <&syscrg JH7110_SYSRST_TEMP_APB>;
 654 +                       reset-names = "sense", "bus";
 655 +                       #thermal-sensor-cells = <0>;
 656 +               };
 657 +
 658 +               qspi: spi@13010000 {
 659 +                       compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
 660 +                       reg = <0x0 0x13010000 0x0 0x10000
 661 +                              0x0 0x21000000 0x0 0x400000>;
 662 +                       interrupts = <25>;
 663 +                       clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
 664 +                                <&syscrg JH7110_SYSCLK_QSPI_AHB>,
 665 +                                <&syscrg JH7110_SYSCLK_QSPI_APB>;
 666 +                       clock-names = "qspi-ref", "qspi-ahb", "qspi-apb";
 667 +                       resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
 668 +                                <&syscrg JH7110_SYSRST_QSPI_AHB>,
 669 +                                <&syscrg JH7110_SYSRST_QSPI_REF>;
 670 +                       reset-names = "qspi", "qspi-ocp", "rstc_ref";
 671 +                       cdns,fifo-depth = <256>;
 672 +                       cdns,fifo-width = <4>;
 673 +                       cdns,trigger-address = <0x0>;
 674 +               };
 675 +
 676                 syscrg: clock-controller@13020000 {
 677                         compatible = "starfive,jh7110-syscrg";
 678                         reg = <0x0 0x13020000 0x0 0x10000>;
 679 @@ -496,6 +674,107 @@
 680                         #gpio-cells = <2>;
 681                 };
 682
 683 +               timer@13050000 {
 684 +                       compatible = "starfive,jh7110-timer";
 685 +                       reg = <0x0 0x13050000 0x0 0x10000>;
 686 +                       interrupts = <69>, <70>, <71> ,<72>;
 687 +                       clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
 688 +                                <&syscrg JH7110_SYSCLK_TIMER0>,
 689 +                                <&syscrg JH7110_SYSCLK_TIMER1>,
 690 +                                <&syscrg JH7110_SYSCLK_TIMER2>,
 691 +                                <&syscrg JH7110_SYSCLK_TIMER3>;
 692 +                       clock-names = "apb", "ch0", "ch1",
 693 +                                     "ch2", "ch3";
 694 +                       resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
 695 +                                <&syscrg JH7110_SYSRST_TIMER0>,
 696 +                                <&syscrg JH7110_SYSRST_TIMER1>,
 697 +                                <&syscrg JH7110_SYSRST_TIMER2>,
 698 +                                <&syscrg JH7110_SYSRST_TIMER3>;
 699 +                       reset-names = "apb", "ch0", "ch1",
 700 +                                     "ch2", "ch3";
 701 +               };
 702 +
 703 +               watchdog@13070000 {
 704 +                       compatible = "starfive,jh7110-wdt";
 705 +                       reg = <0x0 0x13070000 0x0 0x10000>;
 706 +                       clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
 707 +                                <&syscrg JH7110_SYSCLK_WDT_CORE>;
 708 +                       clock-names = "apb", "core";
 709 +                       resets = <&syscrg JH7110_SYSRST_WDT_APB>,
 710 +                                <&syscrg JH7110_SYSRST_WDT_CORE>;
 711 +               };
 712 +
 713 +               crypto: crypto@16000000 {
 714 +                       compatible = "starfive,jh7110-crypto";
 715 +                       reg = <0x0 0x16000000 0x0 0x4000>;
 716 +                       clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 717 +                                <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 718 +                       clock-names = "hclk", "ahb";
 719 +                       interrupts = <28>;
 720 +                       resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 721 +                       dmas = <&sdma 1 2>, <&sdma 0 2>;
 722 +                       dma-names = "tx", "rx";
 723 +                       status = "disabled";
 724 +               };
 725 +
 726 +               sdma: dma@16008000 {
 727 +                       compatible = "arm,pl080", "arm,primecell";
 728 +                       arm,primecell-periphid = <0x00041080>;
 729 +                       reg = <0x0 0x16008000 0x0 0x4000>;
 730 +                       interrupts = <29>;
 731 +                       clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 732 +                                <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 733 +                       clock-names = "hclk", "apb_pclk";
 734 +                       resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 735 +                       lli-bus-interface-ahb1;
 736 +                       mem-bus-interface-ahb1;
 737 +                       memcpy-burst-size = <256>;
 738 +                       memcpy-bus-width = <32>;
 739 +                       #dma-cells = <2>;
 740 +               };
 741 +
 742 +               rng: rng@1600c000 {
 743 +                       compatible = "starfive,jh7110-trng";
 744 +                       reg = <0x0 0x1600C000 0x0 0x4000>;
 745 +                       clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 746 +                                <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 747 +                       clock-names = "hclk", "ahb";
 748 +                       resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 749 +                       interrupts = <30>;
 750 +               };
 751 +
 752 +               mmc0: mmc@16010000 {
 753 +                       compatible = "starfive,jh7110-mmc";
 754 +                       reg = <0x0 0x16010000 0x0 0x10000>;
 755 +                       clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
 756 +                                <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
 757 +                       clock-names = "biu","ciu";
 758 +                       resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
 759 +                       reset-names = "reset";
 760 +                       interrupts = <74>;
 761 +                       fifo-depth = <32>;
 762 +                       fifo-watermark-aligned;
 763 +                       data-addr = <0>;
 764 +                       starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
 765 +                       status = "disabled";
 766 +               };
 767 +
 768 +               mmc1: mmc@16020000 {
 769 +                       compatible = "starfive,jh7110-mmc";
 770 +                       reg = <0x0 0x16020000 0x0 0x10000>;
 771 +                       clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
 772 +                                <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
 773 +                       clock-names = "biu","ciu";
 774 +                       resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
 775 +                       reset-names = "reset";
 776 +                       interrupts = <75>;
 777 +                       fifo-depth = <32>;
 778 +                       fifo-watermark-aligned;
 779 +                       data-addr = <0>;
 780 +                       starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
 781 +                       status = "disabled";
 782 +               };
 783 +
 784                 gmac0: ethernet@16030000 {
 785                         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
 786                         reg = <0x0 0x16030000 0x0 0x10000>;
 787 @@ -558,6 +837,24 @@
 788                         status = "disabled";
 789                 };
 790
 791 +               dma: dma-controller@16050000 {
 792 +                       compatible = "starfive,jh7110-axi-dma";
 793 +                       reg = <0x0 0x16050000 0x0 0x10000>;
 794 +                       clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
 795 +                                <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
 796 +                       clock-names = "core-clk", "cfgr-clk";
 797 +                       resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
 798 +                                <&stgcrg JH7110_STGRST_DMA1P_AHB>;
 799 +                       interrupts = <73>;
 800 +                       #dma-cells = <1>;
 801 +                       dma-channels = <4>;
 802 +                       snps,dma-masters = <1>;
 803 +                       snps,data-width = <3>;
 804 +                       snps,block-size = <65536 65536 65536 65536>;
 805 +                       snps,priority = <0 1 2 3>;
 806 +                       snps,axi-max-burst-len = <16>;
 807 +               };
 808 +
 809                 aoncrg: clock-controller@17000000 {
 810                         compatible = "starfive,jh7110-aoncrg";
 811                         reg = <0x0 0x17000000 0x0 0x10000>;
 812 @@ -576,8 +873,9 @@
 813                 };
 814
 815                 aon_syscon: syscon@17010000 {
 816 -                       compatible = "starfive,jh7110-aon-syscon", "syscon", "simple-mfd";
 817 +                       compatible = "starfive,jh7110-aon-syscon", "syscon";
 818                         reg = <0x0 0x17010000 0x0 0x1000>;
 819 +                       #power-domain-cells = <1>;
 820                 };
 821
 822                 aongpio: pinctrl@17020000 {
 823 @@ -590,5 +888,211 @@
 824                         gpio-controller;
 825                         #gpio-cells = <2>;
 826                 };
 827 +
 828 +               pwrc: power-controller@17030000 {
 829 +                       compatible = "starfive,jh7110-pmu";
 830 +                       reg = <0x0 0x17030000 0x0 0x10000>;
 831 +                       interrupts = <111>;
 832 +                       #power-domain-cells = <1>;
 833 +               };
 834 +
 835 +               csi2rx: csi-bridge@19800000 {
 836 +                       compatible = "starfive,jh7110-csi2rx";
 837 +                       reg = <0x0 0x19800000 0x0 0x10000>;
 838 +                       clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>,
 839 +                                <&ispcrg JH7110_ISPCLK_VIN_APB>,
 840 +                                <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>,
 841 +                                <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>,
 842 +                                <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>,
 843 +                                <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>;
 844 +                       clock-names = "sys_clk", "p_clk",
 845 +                                "pixel_if0_clk", "pixel_if1_clk",
 846 +                                "pixel_if2_clk", "pixel_if3_clk";
 847 +                       resets = <&ispcrg JH7110_ISPRST_VIN_SYS>,
 848 +                                <&ispcrg JH7110_ISPRST_VIN_APB>,
 849 +                                <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>,
 850 +                                <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>,
 851 +                                <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>,
 852 +                                <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>;
 853 +                       reset-names = "sys", "reg_bank",
 854 +                                "pixel_if0", "pixel_if1",
 855 +                                "pixel_if2", "pixel_if3";
 856 +                       phys = <&csi_phy>;
 857 +                       phy-names = "dphy";
 858 +                       status = "disabled";
 859 +               };
 860 +
 861 +               ispcrg: clock-controller@19810000 {
 862 +                       compatible = "starfive,jh7110-ispcrg";
 863 +                       reg = <0x0 0x19810000 0x0 0x10000>;
 864 +                       clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
 865 +                                <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
 866 +                                <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
 867 +                                <&dvp_clk>;
 868 +                       clock-names = "isp_top_core", "isp_top_axi",
 869 +                                     "noc_bus_isp_axi", "dvp_clk";
 870 +                       resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
 871 +                                <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
 872 +                                <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
 873 +                       #clock-cells = <1>;
 874 +                       #reset-cells = <1>;
 875 +                       power-domains = <&pwrc JH7110_PD_ISP>;
 876 +               };
 877 +
 878 +               csi_phy: phy@19820000 {
 879 +                       compatible = "starfive,jh7110-dphy-rx";
 880 +                       reg = <0x0 0x19820000 0x0 0x10000>;
 881 +                       clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
 882 +                                <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
 883 +                                <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
 884 +                       clock-names = "cfg", "ref", "tx";
 885 +                       resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
 886 +                                <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
 887 +                       power-domains = <&aon_syscon JH7110_PD_DPHY_RX>;
 888 +                       #phy-cells = <0>;
 889 +               };
 890 +
 891 +               stfcamss: camss@19840000 {
 892 +                       compatible = "starfive,jh7110-camss";
 893 +                       reg = <0x0 0x19840000 0x0 0x10000>,
 894 +                               <0x0 0x19870000 0x0 0x30000>;
 895 +                       reg-names = "syscon", "isp";
 896 +                       clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
 897 +                                <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>,
 898 +                                <&ispcrg JH7110_ISPCLK_DVP_INV>,
 899 +                                <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>,
 900 +                                <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>,
 901 +                                <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
 902 +                                <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>;
 903 +                       clock-names = "clk_apb_func",
 904 +                               "clk_wrapper_clk_c",
 905 +                               "clk_dvp_inv",
 906 +                               "clk_axiwr",
 907 +                               "clk_mipi_rx0_pxl",
 908 +                               "clk_ispcore_2x",
 909 +                               "clk_isp_axi";
 910 +                       resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>,
 911 +                                <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>,
 912 +                                <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>,
 913 +                                <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>,
 914 +                                <&syscrg JH7110_SYSRST_ISP_TOP>,
 915 +                                <&syscrg JH7110_SYSRST_ISP_TOP_AXI>;
 916 +                       reset-names = "rst_wrapper_p",
 917 +                               "rst_wrapper_c",
 918 +                               "rst_axird",
 919 +                               "rst_axiwr",
 920 +                               "rst_isp_top_n",
 921 +                               "rst_isp_top_axi";
 922 +                       power-domains = <&pwrc JH7110_PD_ISP>;
 923 +                       /* irq nr: vin, isp, isp_csi, isp_csiline */
 924 +                       interrupts = <92>, <87>, <90>;
 925 +                       status = "disabled";
 926 +               };
 927 +
 928 +               voutcrg: clock-controller@295c0000 {
 929 +                       compatible = "starfive,jh7110-voutcrg";
 930 +                       reg = <0x0 0x295c0000 0x0 0x10000>;
 931 +                       clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
 932 +                                <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
 933 +                                <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
 934 +                                <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
 935 +                                <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
 936 +                                <&hdmitx0_pixelclk>;
 937 +                       clock-names = "vout_src", "vout_top_ahb",
 938 +                                     "vout_top_axi", "vout_top_hdmitx0_mclk",
 939 +                                     "i2stx0_bclk", "hdmitx0_pixelclk";
 940 +                       resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
 941 +                       #clock-cells = <1>;
 942 +                       #reset-cells = <1>;
 943 +                       power-domains = <&pwrc JH7110_PD_VOUT>;
 944 +               };
 945 +
 946 +               pcie0: pcie@2B000000 {
 947 +                       compatible = "starfive,jh7110-pcie";
 948 +                       #address-cells = <3>;
 949 +                       #size-cells = <2>;
 950 +                       #interrupt-cells = <1>;
 951 +                       reg = <0x0 0x2B000000 0x0 0x1000000
 952 +                              0x9 0x40000000 0x0 0x10000000>;
 953 +                       reg-names = "reg", "config";
 954 +                       device_type = "pci";
 955 +                       starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
 956 +                       bus-range = <0x0 0xff>;
 957 +                       ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
 958 +                                <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
 959 +                       interrupts = <56>;
 960 +                       interrupt-parent = <&plic>;
 961 +                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 962 +                       interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
 963 +                                       <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
 964 +                                       <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
 965 +                                       <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
 966 +                       msi-parent = <&pcie0>;
 967 +                       msi-controller;
 968 +                       clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
 969 +                                <&stgcrg JH7110_STGCLK_PCIE0_TL>,
 970 +                                <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
 971 +                                <&stgcrg JH7110_STGCLK_PCIE0_APB>;
 972 +                       clock-names = "noc", "tl", "axi_mst0", "apb";
 973 +                       resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
 974 +                                <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
 975 +                                <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
 976 +                                <&stgcrg JH7110_STGRST_PCIE0_BRG>,
 977 +                                <&stgcrg JH7110_STGRST_PCIE0_CORE>,
 978 +                                <&stgcrg JH7110_STGRST_PCIE0_APB>;
 979 +                       reset-names = "mst0", "slv0", "slv", "brg",
 980 +                                     "core", "apb";
 981 +                       status = "disabled";
 982 +
 983 +                       pcie_intc0: interrupt-controller {
 984 +                               #address-cells = <0>;
 985 +                               #interrupt-cells = <1>;
 986 +                               interrupt-controller;
 987 +                       };
 988 +               };
 989 +
 990 +               pcie1: pcie@2C000000 {
 991 +                       compatible = "starfive,jh7110-pcie";
 992 +                       #address-cells = <3>;
 993 +                       #size-cells = <2>;
 994 +                       #interrupt-cells = <1>;
 995 +                       reg = <0x0 0x2C000000 0x0 0x1000000
 996 +                              0x9 0xc0000000 0x0 0x10000000>;
 997 +                       reg-names = "reg", "config";
 998 +                       device_type = "pci";
 999 +                       starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
1000 +                       bus-range = <0x0 0xff>;
1001 +                       ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
1002 +                                <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
1003 +                       interrupts = <57>;
1004 +                       interrupt-parent = <&plic>;
1005 +                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1006 +                       interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
1007 +                                       <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
1008 +                                       <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
1009 +                                       <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
1010 +                       msi-parent = <&pcie1>;
1011 +                       msi-controller;
1012 +                       clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
1013 +                                <&stgcrg JH7110_STGCLK_PCIE1_TL>,
1014 +                                <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
1015 +                                <&stgcrg JH7110_STGCLK_PCIE1_APB>;
1016 +                       clock-names = "noc", "tl", "axi_mst0", "apb";
1017 +                       resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
1018 +                                <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
1019 +                                <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
1020 +                                <&stgcrg JH7110_STGRST_PCIE1_BRG>,
1021 +                                <&stgcrg JH7110_STGRST_PCIE1_CORE>,
1022 +                                <&stgcrg JH7110_STGRST_PCIE1_APB>;
1023 +                       reset-names = "mst0", "slv0", "slv", "brg",
1024 +                                     "core", "apb";
1025 +                       status = "disabled";
1026 +
1027 +                       pcie_intc1: interrupt-controller {
1028 +                               #address-cells = <0>;
1029 +                               #interrupt-cells = <1>;
1030 +                               interrupt-controller;
1031 +                       };
1032 +               };
1033         };
1034  };