1 From 0bc7aa28dcdee75a52b1874a02dfbf0107c2d448 Mon Sep 17 00:00:00 2001
2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
3 Date: Fri, 17 Feb 2023 17:30:09 +0800
4 Subject: [PATCH 032/122] clk: starfive: Add StarFive JH7110 PLL clock driver
6 Add driver for the StarFive JH7110 PLL clock controller
7 and they work by reading and setting syscon registers.
9 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
12 drivers/clk/starfive/Kconfig | 8 +
13 drivers/clk/starfive/Makefile | 1 +
14 .../clk/starfive/clk-starfive-jh7110-pll.c | 427 ++++++++++++++++++
15 .../clk/starfive/clk-starfive-jh7110-pll.h | 293 ++++++++++++
16 5 files changed, 735 insertions(+)
17 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c
18 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.h
22 @@ -19650,6 +19650,12 @@ M: Emil Renner Berthing <kernel@esmil.dk
24 F: arch/riscv/boot/dts/starfive/
26 +STARFIVE JH7110 PLL CLOCK DRIVER
27 +M: Xingyu Wu <xingyu.wu@starfivetech.com>
29 +F: Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
30 +F: drivers/clk/starfive/clk-starfive-jh7110-pll.*
32 STARFIVE JH71X0 CLOCK DRIVERS
33 M: Emil Renner Berthing <kernel@esmil.dk>
34 M: Hal Feng <hal.feng@starfivetech.com>
35 --- a/drivers/clk/starfive/Kconfig
36 +++ b/drivers/clk/starfive/Kconfig
37 @@ -21,6 +21,14 @@ config CLK_STARFIVE_JH7100_AUDIO
38 Say Y or M here to support the audio clocks on the StarFive JH7100
41 +config CLK_STARFIVE_JH7110_PLL
42 + bool "StarFive JH7110 PLL clock support"
43 + depends on ARCH_STARFIVE || COMPILE_TEST
44 + default ARCH_STARFIVE
46 + Say yes here to support the PLL clock controller on the
47 + StarFive JH7110 SoC.
49 config CLK_STARFIVE_JH7110_SYS
50 bool "StarFive JH7110 system clock support"
51 depends on ARCH_STARFIVE || COMPILE_TEST
52 --- a/drivers/clk/starfive/Makefile
53 +++ b/drivers/clk/starfive/Makefile
54 @@ -4,5 +4,6 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk
55 obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
56 obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
58 +obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o
59 obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
60 obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
62 +++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.c
64 +// SPDX-License-Identifier: GPL-2.0
66 + * StarFive JH7110 PLL Clock Generator Driver
68 + * Copyright (C) 2023 StarFive Technology Co., Ltd.
70 + * This driver is about to register JH7110 PLL clock generator and support ops.
71 + * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
72 + * Each PLL clocks work in integer mode or fraction mode by some dividers,
73 + * and the configuration registers and dividers are set in several syscon registers.
74 + * The formula for calculating frequency is:
75 + * Fvco = Fref * (NI + NF) / M / Q1
76 + * Fref: OSC source clock rate
77 + * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0].
78 + * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999.
79 + * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
80 + * Q1: frequency dividing ratio of post divider, set by postdiv1[1:0], Q1= 1,2,4,8.
83 +#include <linux/clk-provider.h>
84 +#include <linux/debugfs.h>
85 +#include <linux/device.h>
86 +#include <linux/kernel.h>
87 +#include <linux/mfd/syscon.h>
88 +#include <linux/platform_device.h>
89 +#include <linux/regmap.h>
91 +#include <dt-bindings/clock/starfive,jh7110-crg.h>
93 +#include "clk-starfive-jh7110-pll.h"
95 +static struct jh7110_clk_pll_data *jh7110_pll_data_from(struct clk_hw *hw)
97 + return container_of(hw, struct jh7110_clk_pll_data, hw);
100 +static struct jh7110_clk_pll_priv *jh7110_pll_priv_from(struct jh7110_clk_pll_data *data)
102 + return container_of(data, struct jh7110_clk_pll_priv, data[data->idx]);
105 +/* Read register value from syscon and calculate PLL(x) frequency */
106 +static unsigned long jh7110_pll_get_freq(struct jh7110_clk_pll_data *data,
107 + unsigned long parent_rate)
109 + struct jh7110_clk_pll_priv *priv = jh7110_pll_priv_from(data);
110 + struct jh7110_pll_syscon_offset *offset = &data->offset;
111 + struct jh7110_pll_syscon_mask *mask = &data->mask;
112 + struct jh7110_pll_syscon_shift *shift = &data->shift;
113 + unsigned long freq = 0;
114 + unsigned long frac_cal;
123 + if (regmap_read(priv->syscon_regmap, offset->dacpd, ®_val))
125 + dacpd = (reg_val & mask->dacpd) >> shift->dacpd;
127 + if (regmap_read(priv->syscon_regmap, offset->dsmpd, ®_val))
129 + dsmpd = (reg_val & mask->dsmpd) >> shift->dsmpd;
131 + if (regmap_read(priv->syscon_regmap, offset->fbdiv, ®_val))
133 + fbdiv = (reg_val & mask->fbdiv) >> shift->fbdiv;
134 + /* fbdiv value should be 8 to 4095 */
138 + if (regmap_read(priv->syscon_regmap, offset->prediv, ®_val))
140 + prediv = (reg_val & mask->prediv) >> shift->prediv;
142 + if (regmap_read(priv->syscon_regmap, offset->postdiv1, ®_val))
144 + /* postdiv1 = 2 ^ reg_val */
145 + postdiv1 = 1 << ((reg_val & mask->postdiv1) >> shift->postdiv1);
147 + if (regmap_read(priv->syscon_regmap, offset->frac, ®_val))
149 + frac = (reg_val & mask->frac) >> shift->frac;
152 + * Integer Mode (Both 1) or Fraction Mode (Both 0).
153 + * And the decimal places are counted by expanding them by
154 + * a factor of STARFIVE_PLL_FRAC_PATR_SIZE.
156 + if (dacpd == 1 && dsmpd == 1)
158 + else if (dacpd == 0 && dsmpd == 0)
159 + frac_cal = (unsigned long)frac * STARFIVE_PLL_FRAC_PATR_SIZE / (1 << 24);
163 + /* Fvco = Fref * (NI + NF) / M / Q1 */
164 + freq = parent_rate / STARFIVE_PLL_FRAC_PATR_SIZE *
165 + (fbdiv * STARFIVE_PLL_FRAC_PATR_SIZE + frac_cal) / prediv / postdiv1;
171 +static unsigned long jh7110_pll_rate_sub_fabs(unsigned long rate1, unsigned long rate2)
173 + return rate1 > rate2 ? (rate1 - rate2) : (rate2 - rate1);
176 +/* Select the appropriate frequency from the already configured registers value */
177 +static void jh7110_pll_select_near_freq_id(struct jh7110_clk_pll_data *data,
178 + unsigned long rate)
180 + const struct starfive_pll_syscon_value *syscon_val;
182 + unsigned int pll_arry_size;
183 + unsigned long rate_diff;
185 + if (data->idx == JH7110_CLK_PLL0_OUT)
186 + pll_arry_size = ARRAY_SIZE(jh7110_pll0_syscon_freq);
187 + else if (data->idx == JH7110_CLK_PLL1_OUT)
188 + pll_arry_size = ARRAY_SIZE(jh7110_pll1_syscon_freq);
190 + pll_arry_size = ARRAY_SIZE(jh7110_pll2_syscon_freq);
192 + /* compare the frequency one by one from small to large in order */
193 + for (id = 0; id < pll_arry_size; id++) {
194 + if (data->idx == JH7110_CLK_PLL0_OUT)
195 + syscon_val = &jh7110_pll0_syscon_freq[id];
196 + else if (data->idx == JH7110_CLK_PLL1_OUT)
197 + syscon_val = &jh7110_pll1_syscon_freq[id];
199 + syscon_val = &jh7110_pll2_syscon_freq[id];
201 + if (rate == syscon_val->freq)
204 + /* select near frequency */
205 + if (rate < syscon_val->freq) {
206 + /* The last frequency is closer to the target rate than this time. */
208 + if (rate_diff < jh7110_pll_rate_sub_fabs(rate, syscon_val->freq))
213 + rate_diff = jh7110_pll_rate_sub_fabs(rate, syscon_val->freq);
218 + data->freq_select_idx = id;
221 +static int jh7110_pll_set_freq_syscon(struct jh7110_clk_pll_data *data)
223 + struct jh7110_clk_pll_priv *priv = jh7110_pll_priv_from(data);
224 + struct jh7110_pll_syscon_offset *offset = &data->offset;
225 + struct jh7110_pll_syscon_mask *mask = &data->mask;
226 + struct jh7110_pll_syscon_shift *shift = &data->shift;
227 + unsigned int freq_idx = data->freq_select_idx;
228 + const struct starfive_pll_syscon_value *syscon_val;
231 + if (data->idx == JH7110_CLK_PLL0_OUT)
232 + syscon_val = &jh7110_pll0_syscon_freq[freq_idx];
233 + else if (data->idx == JH7110_CLK_PLL1_OUT)
234 + syscon_val = &jh7110_pll1_syscon_freq[freq_idx];
236 + syscon_val = &jh7110_pll2_syscon_freq[freq_idx];
238 + ret = regmap_update_bits(priv->syscon_regmap, offset->dacpd, mask->dacpd,
239 + (syscon_val->dacpd << shift->dacpd));
243 + ret = regmap_update_bits(priv->syscon_regmap, offset->dsmpd, mask->dsmpd,
244 + (syscon_val->dsmpd << shift->dsmpd));
248 + ret = regmap_update_bits(priv->syscon_regmap, offset->prediv, mask->prediv,
249 + (syscon_val->prediv << shift->prediv));
253 + ret = regmap_update_bits(priv->syscon_regmap, offset->fbdiv, mask->fbdiv,
254 + (syscon_val->fbdiv << shift->fbdiv));
258 + ret = regmap_update_bits(priv->syscon_regmap, offset->postdiv1, mask->postdiv1,
259 + ((syscon_val->postdiv1 >> 1) << shift->postdiv1));
263 + /* frac: Integer Mode (Both 1) or Fraction Mode (Both 0) */
264 + if (syscon_val->dacpd == 0 && syscon_val->dsmpd == 0)
265 + ret = regmap_update_bits(priv->syscon_regmap, offset->frac, mask->frac,
266 + (syscon_val->frac << shift->frac));
267 + else if (syscon_val->dacpd != syscon_val->dsmpd)
274 +static unsigned long jh7110_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
276 + struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
278 + return jh7110_pll_get_freq(data, parent_rate);
281 +static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
283 + struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
285 + jh7110_pll_select_near_freq_id(data, req->rate);
287 + if (data->idx == JH7110_CLK_PLL0_OUT)
288 + req->rate = jh7110_pll0_syscon_freq[data->freq_select_idx].freq;
289 + else if (data->idx == JH7110_CLK_PLL1_OUT)
290 + req->rate = jh7110_pll1_syscon_freq[data->freq_select_idx].freq;
292 + req->rate = jh7110_pll2_syscon_freq[data->freq_select_idx].freq;
297 +static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate,
298 + unsigned long parent_rate)
300 + struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
302 + return jh7110_pll_set_freq_syscon(data);
305 +#ifdef CONFIG_DEBUG_FS
306 +static void jh7110_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
308 + static const struct debugfs_reg32 jh7110_clk_pll_reg = {
312 + struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
313 + struct jh7110_clk_pll_priv *priv = jh7110_pll_priv_from(data);
314 + struct debugfs_regset32 *regset;
316 + regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
320 + regset->regs = &jh7110_clk_pll_reg;
323 + debugfs_create_regset32("registers", 0400, dentry, regset);
326 +#define jh7110_pll_debug_init NULL
329 +static const struct clk_ops jh7110_pll_ops = {
330 + .recalc_rate = jh7110_pll_recalc_rate,
331 + .determine_rate = jh7110_pll_determine_rate,
332 + .set_rate = jh7110_pll_set_rate,
333 + .debug_init = jh7110_pll_debug_init,
336 +/* get offset, mask and shift of PLL(x) syscon */
337 +static int jh7110_pll_data_get(struct jh7110_clk_pll_data *data, int index)
339 + struct jh7110_pll_syscon_offset *offset = &data->offset;
340 + struct jh7110_pll_syscon_mask *mask = &data->mask;
341 + struct jh7110_pll_syscon_shift *shift = &data->shift;
343 + if (index == JH7110_CLK_PLL0_OUT) {
344 + offset->dacpd = STARFIVE_JH7110_PLL0_DACPD_OFFSET;
345 + offset->dsmpd = STARFIVE_JH7110_PLL0_DSMPD_OFFSET;
346 + offset->fbdiv = STARFIVE_JH7110_PLL0_FBDIV_OFFSET;
347 + offset->frac = STARFIVE_JH7110_PLL0_FRAC_OFFSET;
348 + offset->prediv = STARFIVE_JH7110_PLL0_PREDIV_OFFSET;
349 + offset->postdiv1 = STARFIVE_JH7110_PLL0_POSTDIV1_OFFSET;
351 + mask->dacpd = STARFIVE_JH7110_PLL0_DACPD_MASK;
352 + mask->dsmpd = STARFIVE_JH7110_PLL0_DSMPD_MASK;
353 + mask->fbdiv = STARFIVE_JH7110_PLL0_FBDIV_MASK;
354 + mask->frac = STARFIVE_JH7110_PLL0_FRAC_MASK;
355 + mask->prediv = STARFIVE_JH7110_PLL0_PREDIV_MASK;
356 + mask->postdiv1 = STARFIVE_JH7110_PLL0_POSTDIV1_MASK;
358 + shift->dacpd = STARFIVE_JH7110_PLL0_DACPD_SHIFT;
359 + shift->dsmpd = STARFIVE_JH7110_PLL0_DSMPD_SHIFT;
360 + shift->fbdiv = STARFIVE_JH7110_PLL0_FBDIV_SHIFT;
361 + shift->frac = STARFIVE_JH7110_PLL0_FRAC_SHIFT;
362 + shift->prediv = STARFIVE_JH7110_PLL0_PREDIV_SHIFT;
363 + shift->postdiv1 = STARFIVE_JH7110_PLL0_POSTDIV1_SHIFT;
365 + } else if (index == JH7110_CLK_PLL1_OUT) {
366 + offset->dacpd = STARFIVE_JH7110_PLL1_DACPD_OFFSET;
367 + offset->dsmpd = STARFIVE_JH7110_PLL1_DSMPD_OFFSET;
368 + offset->fbdiv = STARFIVE_JH7110_PLL1_FBDIV_OFFSET;
369 + offset->frac = STARFIVE_JH7110_PLL1_FRAC_OFFSET;
370 + offset->prediv = STARFIVE_JH7110_PLL1_PREDIV_OFFSET;
371 + offset->postdiv1 = STARFIVE_JH7110_PLL1_POSTDIV1_OFFSET;
373 + mask->dacpd = STARFIVE_JH7110_PLL1_DACPD_MASK;
374 + mask->dsmpd = STARFIVE_JH7110_PLL1_DSMPD_MASK;
375 + mask->fbdiv = STARFIVE_JH7110_PLL1_FBDIV_MASK;
376 + mask->frac = STARFIVE_JH7110_PLL1_FRAC_MASK;
377 + mask->prediv = STARFIVE_JH7110_PLL1_PREDIV_MASK;
378 + mask->postdiv1 = STARFIVE_JH7110_PLL1_POSTDIV1_MASK;
380 + shift->dacpd = STARFIVE_JH7110_PLL1_DACPD_SHIFT;
381 + shift->dsmpd = STARFIVE_JH7110_PLL1_DSMPD_SHIFT;
382 + shift->fbdiv = STARFIVE_JH7110_PLL1_FBDIV_SHIFT;
383 + shift->frac = STARFIVE_JH7110_PLL1_FRAC_SHIFT;
384 + shift->prediv = STARFIVE_JH7110_PLL1_PREDIV_SHIFT;
385 + shift->postdiv1 = STARFIVE_JH7110_PLL1_POSTDIV1_SHIFT;
387 + } else if (index == JH7110_CLK_PLL2_OUT) {
388 + offset->dacpd = STARFIVE_JH7110_PLL2_DACPD_OFFSET;
389 + offset->dsmpd = STARFIVE_JH7110_PLL2_DSMPD_OFFSET;
390 + offset->fbdiv = STARFIVE_JH7110_PLL2_FBDIV_OFFSET;
391 + offset->frac = STARFIVE_JH7110_PLL2_FRAC_OFFSET;
392 + offset->prediv = STARFIVE_JH7110_PLL2_PREDIV_OFFSET;
393 + offset->postdiv1 = STARFIVE_JH7110_PLL2_POSTDIV1_OFFSET;
395 + mask->dacpd = STARFIVE_JH7110_PLL2_DACPD_MASK;
396 + mask->dsmpd = STARFIVE_JH7110_PLL2_DSMPD_MASK;
397 + mask->fbdiv = STARFIVE_JH7110_PLL2_FBDIV_MASK;
398 + mask->frac = STARFIVE_JH7110_PLL2_FRAC_MASK;
399 + mask->prediv = STARFIVE_JH7110_PLL2_PREDIV_MASK;
400 + mask->postdiv1 = STARFIVE_JH7110_PLL2_POSTDIV1_MASK;
402 + shift->dacpd = STARFIVE_JH7110_PLL2_DACPD_SHIFT;
403 + shift->dsmpd = STARFIVE_JH7110_PLL2_DSMPD_SHIFT;
404 + shift->fbdiv = STARFIVE_JH7110_PLL2_FBDIV_SHIFT;
405 + shift->frac = STARFIVE_JH7110_PLL2_FRAC_SHIFT;
406 + shift->prediv = STARFIVE_JH7110_PLL2_PREDIV_SHIFT;
407 + shift->postdiv1 = STARFIVE_JH7110_PLL2_POSTDIV1_SHIFT;
416 +static struct clk_hw *jh7110_pll_get(struct of_phandle_args *clkspec, void *data)
418 + struct jh7110_clk_pll_priv *priv = data;
419 + unsigned int idx = clkspec->args[0];
421 + if (idx < JH7110_PLLCLK_END)
422 + return &priv->data[idx].hw;
424 + return ERR_PTR(-EINVAL);
427 +static int jh7110_pll_probe(struct platform_device *pdev)
429 + const char *pll_name[JH7110_PLLCLK_END] = {
434 + struct jh7110_clk_pll_priv *priv;
435 + struct jh7110_clk_pll_data *data;
439 + priv = devm_kzalloc(&pdev->dev, struct_size(priv, data, JH7110_PLLCLK_END),
444 + priv->dev = &pdev->dev;
445 + priv->syscon_regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
446 + if (IS_ERR(priv->syscon_regmap))
447 + return PTR_ERR(priv->syscon_regmap);
449 + for (idx = 0; idx < JH7110_PLLCLK_END; idx++) {
450 + struct clk_parent_data parents = {
453 + struct clk_init_data init = {
454 + .name = pll_name[idx],
455 + .ops = &jh7110_pll_ops,
456 + .parent_data = &parents,
461 + data = &priv->data[idx];
463 + ret = jh7110_pll_data_get(data, idx);
467 + data->hw.init = &init;
470 + ret = devm_clk_hw_register(&pdev->dev, &data->hw);
475 + return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv);
478 +static const struct of_device_id jh7110_pll_match[] = {
479 + { .compatible = "starfive,jh7110-pll" },
482 +MODULE_DEVICE_TABLE(of, jh7110_pll_match);
484 +static struct platform_driver jh7110_pll_driver = {
486 + .name = "clk-starfive-jh7110-pll",
487 + .of_match_table = jh7110_pll_match,
490 +builtin_platform_driver_probe(jh7110_pll_driver, jh7110_pll_probe);
492 +++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.h
494 +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
496 + * StarFive JH7110 PLL Clock Generator Driver
498 + * Copyright (C) 2023 StarFive Technology Co., Ltd.
501 +#ifndef _CLK_STARFIVE_JH7110_PLL_H_
502 +#define _CLK_STARFIVE_JH7110_PLL_H_
504 +#include <linux/bits.h>
506 +/* The decimal places are counted by expanding them by a factor of STARFIVE_PLL_FRAC_PATR_SIZE */
507 +#define STARFIVE_PLL_FRAC_PATR_SIZE 1000
509 +#define STARFIVE_JH7110_PLL0_DACPD_OFFSET 0x18
510 +#define STARFIVE_JH7110_PLL0_DACPD_SHIFT 24
511 +#define STARFIVE_JH7110_PLL0_DACPD_MASK BIT(24)
512 +#define STARFIVE_JH7110_PLL0_DSMPD_OFFSET 0x18
513 +#define STARFIVE_JH7110_PLL0_DSMPD_SHIFT 25
514 +#define STARFIVE_JH7110_PLL0_DSMPD_MASK BIT(25)
515 +#define STARFIVE_JH7110_PLL0_FBDIV_OFFSET 0x1c
516 +#define STARFIVE_JH7110_PLL0_FBDIV_SHIFT 0
517 +#define STARFIVE_JH7110_PLL0_FBDIV_MASK GENMASK(11, 0)
518 +#define STARFIVE_JH7110_PLL0_FRAC_OFFSET 0x20
519 +#define STARFIVE_JH7110_PLL0_FRAC_SHIFT 0
520 +#define STARFIVE_JH7110_PLL0_FRAC_MASK GENMASK(23, 0)
521 +#define STARFIVE_JH7110_PLL0_POSTDIV1_OFFSET 0x20
522 +#define STARFIVE_JH7110_PLL0_POSTDIV1_SHIFT 28
523 +#define STARFIVE_JH7110_PLL0_POSTDIV1_MASK GENMASK(29, 28)
524 +#define STARFIVE_JH7110_PLL0_PREDIV_OFFSET 0x24
525 +#define STARFIVE_JH7110_PLL0_PREDIV_SHIFT 0
526 +#define STARFIVE_JH7110_PLL0_PREDIV_MASK GENMASK(5, 0)
528 +#define STARFIVE_JH7110_PLL1_DACPD_OFFSET 0x24
529 +#define STARFIVE_JH7110_PLL1_DACPD_SHIFT 15
530 +#define STARFIVE_JH7110_PLL1_DACPD_MASK BIT(15)
531 +#define STARFIVE_JH7110_PLL1_DSMPD_OFFSET 0x24
532 +#define STARFIVE_JH7110_PLL1_DSMPD_SHIFT 16
533 +#define STARFIVE_JH7110_PLL1_DSMPD_MASK BIT(16)
534 +#define STARFIVE_JH7110_PLL1_FBDIV_OFFSET 0x24
535 +#define STARFIVE_JH7110_PLL1_FBDIV_SHIFT 17
536 +#define STARFIVE_JH7110_PLL1_FBDIV_MASK GENMASK(28, 17)
537 +#define STARFIVE_JH7110_PLL1_FRAC_OFFSET 0x28
538 +#define STARFIVE_JH7110_PLL1_FRAC_SHIFT 0
539 +#define STARFIVE_JH7110_PLL1_FRAC_MASK GENMASK(23, 0)
540 +#define STARFIVE_JH7110_PLL1_POSTDIV1_OFFSET 0x28
541 +#define STARFIVE_JH7110_PLL1_POSTDIV1_SHIFT 28
542 +#define STARFIVE_JH7110_PLL1_POSTDIV1_MASK GENMASK(29, 28)
543 +#define STARFIVE_JH7110_PLL1_PREDIV_OFFSET 0x2c
544 +#define STARFIVE_JH7110_PLL1_PREDIV_SHIFT 0
545 +#define STARFIVE_JH7110_PLL1_PREDIV_MASK GENMASK(5, 0)
547 +#define STARFIVE_JH7110_PLL2_DACPD_OFFSET 0x2c
548 +#define STARFIVE_JH7110_PLL2_DACPD_SHIFT 15
549 +#define STARFIVE_JH7110_PLL2_DACPD_MASK BIT(15)
550 +#define STARFIVE_JH7110_PLL2_DSMPD_OFFSET 0x2c
551 +#define STARFIVE_JH7110_PLL2_DSMPD_SHIFT 16
552 +#define STARFIVE_JH7110_PLL2_DSMPD_MASK BIT(16)
553 +#define STARFIVE_JH7110_PLL2_FBDIV_OFFSET 0x2c
554 +#define STARFIVE_JH7110_PLL2_FBDIV_SHIFT 17
555 +#define STARFIVE_JH7110_PLL2_FBDIV_MASK GENMASK(28, 17)
556 +#define STARFIVE_JH7110_PLL2_FRAC_OFFSET 0x30
557 +#define STARFIVE_JH7110_PLL2_FRAC_SHIFT 0
558 +#define STARFIVE_JH7110_PLL2_FRAC_MASK GENMASK(23, 0)
559 +#define STARFIVE_JH7110_PLL2_POSTDIV1_OFFSET 0x30
560 +#define STARFIVE_JH7110_PLL2_POSTDIV1_SHIFT 28
561 +#define STARFIVE_JH7110_PLL2_POSTDIV1_MASK GENMASK(29, 28)
562 +#define STARFIVE_JH7110_PLL2_PREDIV_OFFSET 0x34
563 +#define STARFIVE_JH7110_PLL2_PREDIV_SHIFT 0
564 +#define STARFIVE_JH7110_PLL2_PREDIV_MASK GENMASK(5, 0)
566 +struct jh7110_pll_syscon_offset {
567 + unsigned int dacpd;
568 + unsigned int dsmpd;
569 + unsigned int fbdiv;
571 + unsigned int prediv;
572 + unsigned int postdiv1;
575 +struct jh7110_pll_syscon_mask {
584 +struct jh7110_pll_syscon_shift {
593 +struct jh7110_clk_pll_data {
596 + unsigned int freq_select_idx;
598 + struct jh7110_pll_syscon_offset offset;
599 + struct jh7110_pll_syscon_mask mask;
600 + struct jh7110_pll_syscon_shift shift;
603 +struct jh7110_clk_pll_priv {
604 + struct device *dev;
605 + struct regmap *syscon_regmap;
606 + struct jh7110_clk_pll_data data[];
609 +struct starfive_pll_syscon_value {
610 + unsigned long freq;
614 +/* Both daxpd and dsmpd set 1 while integer mode */
615 +/* Both daxpd and dsmpd set 0 while fraction mode */
618 +/* frac value should be decimals multiplied by 2^24 */
622 +enum starfive_pll0_freq_index {
635 +enum starfive_pll1_freq_index {
636 + PLL1_FREQ_1066 = 0,
643 +enum starfive_pll2_freq_index {
644 + PLL2_FREQ_1188 = 0,
650 + * Because the pll frequency is relatively fixed,
651 + * it cannot be set arbitrarily, so it needs a specific configuration.
652 + * PLL0 frequency should be multiple of 125MHz (USB frequency).
654 +static const struct starfive_pll_syscon_value
655 + jh7110_pll0_syscon_freq[PLL0_FREQ_MAX] = {
656 + [PLL0_FREQ_375] = {
664 + [PLL0_FREQ_500] = {
672 + [PLL0_FREQ_625] = {
680 + [PLL0_FREQ_750] = {
688 + [PLL0_FREQ_875] = {
696 + [PLL0_FREQ_1000] = {
697 + .freq = 1000000000,
704 + [PLL0_FREQ_1250] = {
705 + .freq = 1250000000,
712 + [PLL0_FREQ_1375] = {
713 + .freq = 1375000000,
720 + [PLL0_FREQ_1500] = {
721 + .freq = 1500000000,
730 +static const struct starfive_pll_syscon_value
731 + jh7110_pll1_syscon_freq[PLL1_FREQ_MAX] = {
732 + [PLL1_FREQ_1066] = {
733 + .freq = 1066000000,
740 + [PLL1_FREQ_1200] = {
741 + .freq = 1200000000,
748 + [PLL1_FREQ_1400] = {
749 + .freq = 1400000000,
756 + [PLL1_FREQ_1600] = {
757 + .freq = 1600000000,
766 +static const struct starfive_pll_syscon_value
767 + jh7110_pll2_syscon_freq[PLL2_FREQ_MAX] = {
768 + [PLL2_FREQ_1188] = {
769 + .freq = 1188000000,
776 + [PLL2_FREQ_12288] = {
777 + .freq = 1228800000,