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realtek: reduce excessive logging for FDB operations
[openwrt/staging/ansuel.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_info("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134 if (priv->family_id == RTL9310_FAMILY_ID) {
135 info.if_id = 0;
136 info.multicast_grp_mask = 0;
137 info.l2_tunnel_list_id = -1;
138 }
139
140 // Initialize all vlans 0-4095
141 for (i = 0; i < MAX_VLANS; i ++)
142 priv->r->vlan_set_tagged(i, &info);
143
144 // reset PVIDs; defaults to 1 on reset
145 for (i = 0; i <= priv->ds->num_ports; i++) {
146 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
147 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
148 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
149 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
150 }
151
152 // Set forwarding action based on inner VLAN tag
153 for (i = 0; i < priv->cpu_port; i++)
154 priv->r->vlan_fwd_on_inner(i, true);
155 }
156
157 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
158 {
159 int i;
160
161 for (i = 0; i < priv->cpu_port; i++)
162 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
163 }
164
165 static int rtl83xx_setup(struct dsa_switch *ds)
166 {
167 int i;
168 struct rtl838x_switch_priv *priv = ds->priv;
169 u64 port_bitmap = BIT_ULL(priv->cpu_port);
170
171 pr_debug("%s called\n", __func__);
172
173 /* Disable MAC polling the PHY so that we can start configuration */
174 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
175
176 for (i = 0; i < ds->num_ports; i++)
177 priv->ports[i].enable = false;
178 priv->ports[priv->cpu_port].enable = true;
179
180 /* Isolate ports from each other: traffic only CPU <-> port */
181 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
182 * traffic from source port i to destination port j
183 */
184 for (i = 0; i < priv->cpu_port; i++) {
185 if (priv->ports[i].phy) {
186 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
187 priv->r->port_iso_ctrl(i));
188 port_bitmap |= BIT_ULL(i);
189 }
190 }
191 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
192
193 if (priv->family_id == RTL8380_FAMILY_ID)
194 rtl838x_print_matrix();
195 else
196 rtl839x_print_matrix();
197
198 rtl83xx_init_stats(priv);
199
200 rtl83xx_vlan_setup(priv);
201
202 rtl83xx_setup_bpdu_traps(priv);
203
204 ds->configure_vlan_while_not_filtering = true;
205
206 priv->r->l2_learning_setup();
207
208 /*
209 * Make sure all frames sent to the switch's MAC are trapped to the CPU-port
210 * 0: FWD, 1: DROP, 2: TRAP2CPU
211 */
212 if (priv->family_id == RTL8380_FAMILY_ID)
213 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
214 else
215 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
216
217 /* Enable MAC Polling PHY again */
218 rtl83xx_enable_phy_polling(priv);
219 pr_debug("Please wait until PHY is settled\n");
220 msleep(1000);
221 priv->r->pie_init(priv);
222
223 return 0;
224 }
225
226 static int rtl93xx_setup(struct dsa_switch *ds)
227 {
228 int i;
229 struct rtl838x_switch_priv *priv = ds->priv;
230 u32 port_bitmap = BIT(priv->cpu_port);
231
232 pr_info("%s called\n", __func__);
233
234 /* Disable MAC polling the PHY so that we can start configuration */
235 if (priv->family_id == RTL9300_FAMILY_ID)
236 sw_w32(0, RTL930X_SMI_POLL_CTRL);
237
238 if (priv->family_id == RTL9310_FAMILY_ID) {
239 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
240 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
241 }
242
243 // Disable all ports except CPU port
244 for (i = 0; i < ds->num_ports; i++)
245 priv->ports[i].enable = false;
246 priv->ports[priv->cpu_port].enable = true;
247
248 for (i = 0; i < priv->cpu_port; i++) {
249 if (priv->ports[i].phy) {
250 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
251 port_bitmap |= BIT_ULL(i);
252 }
253 }
254 priv->r->traffic_set(priv->cpu_port, port_bitmap);
255
256 rtl930x_print_matrix();
257
258 // TODO: Initialize statistics
259
260 rtl83xx_vlan_setup(priv);
261
262 ds->configure_vlan_while_not_filtering = true;
263
264 priv->r->l2_learning_setup();
265
266 rtl83xx_enable_phy_polling(priv);
267
268 priv->r->pie_init(priv);
269
270 priv->r->led_init(priv);
271
272 return 0;
273 }
274
275 static int rtl93xx_get_sds(struct phy_device *phydev)
276 {
277 struct device *dev = &phydev->mdio.dev;
278 struct device_node *dn;
279 u32 sds_num;
280
281 if (!dev)
282 return -1;
283 if (dev->of_node) {
284 dn = dev->of_node;
285 if (of_property_read_u32(dn, "sds", &sds_num))
286 sds_num = -1;
287 } else {
288 dev_err(dev, "No DT node.\n");
289 return -1;
290 }
291
292 return sds_num;
293 }
294
295 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
296 unsigned long *supported,
297 struct phylink_link_state *state)
298 {
299 struct rtl838x_switch_priv *priv = ds->priv;
300 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
301
302 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
303
304 if (!phy_interface_mode_is_rgmii(state->interface) &&
305 state->interface != PHY_INTERFACE_MODE_NA &&
306 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
307 state->interface != PHY_INTERFACE_MODE_MII &&
308 state->interface != PHY_INTERFACE_MODE_REVMII &&
309 state->interface != PHY_INTERFACE_MODE_GMII &&
310 state->interface != PHY_INTERFACE_MODE_QSGMII &&
311 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
312 state->interface != PHY_INTERFACE_MODE_SGMII) {
313 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
314 dev_err(ds->dev,
315 "Unsupported interface: %d for port %d\n",
316 state->interface, port);
317 return;
318 }
319
320 /* Allow all the expected bits */
321 phylink_set(mask, Autoneg);
322 phylink_set_port_modes(mask);
323 phylink_set(mask, Pause);
324 phylink_set(mask, Asym_Pause);
325
326 /* With the exclusion of MII and Reverse MII, we support Gigabit,
327 * including Half duplex
328 */
329 if (state->interface != PHY_INTERFACE_MODE_MII &&
330 state->interface != PHY_INTERFACE_MODE_REVMII) {
331 phylink_set(mask, 1000baseT_Full);
332 phylink_set(mask, 1000baseT_Half);
333 }
334
335 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
336 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
337 phylink_set(mask, 1000baseX_Full);
338
339 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
340 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
341 phylink_set(mask, 1000baseX_Full);
342
343 phylink_set(mask, 10baseT_Half);
344 phylink_set(mask, 10baseT_Full);
345 phylink_set(mask, 100baseT_Half);
346 phylink_set(mask, 100baseT_Full);
347
348 bitmap_and(supported, supported, mask,
349 __ETHTOOL_LINK_MODE_MASK_NBITS);
350 bitmap_and(state->advertising, state->advertising, mask,
351 __ETHTOOL_LINK_MODE_MASK_NBITS);
352 }
353
354 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
355 unsigned long *supported,
356 struct phylink_link_state *state)
357 {
358 struct rtl838x_switch_priv *priv = ds->priv;
359 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
360
361 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
362 phy_modes(state->interface));
363
364 if (!phy_interface_mode_is_rgmii(state->interface) &&
365 state->interface != PHY_INTERFACE_MODE_NA &&
366 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
367 state->interface != PHY_INTERFACE_MODE_MII &&
368 state->interface != PHY_INTERFACE_MODE_REVMII &&
369 state->interface != PHY_INTERFACE_MODE_GMII &&
370 state->interface != PHY_INTERFACE_MODE_QSGMII &&
371 state->interface != PHY_INTERFACE_MODE_XGMII &&
372 state->interface != PHY_INTERFACE_MODE_HSGMII &&
373 state->interface != PHY_INTERFACE_MODE_10GBASER &&
374 state->interface != PHY_INTERFACE_MODE_10GKR &&
375 state->interface != PHY_INTERFACE_MODE_USXGMII &&
376 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
377 state->interface != PHY_INTERFACE_MODE_SGMII) {
378 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
379 dev_err(ds->dev,
380 "Unsupported interface: %d for port %d\n",
381 state->interface, port);
382 return;
383 }
384
385 /* Allow all the expected bits */
386 phylink_set(mask, Autoneg);
387 phylink_set_port_modes(mask);
388 phylink_set(mask, Pause);
389 phylink_set(mask, Asym_Pause);
390
391 /* With the exclusion of MII and Reverse MII, we support Gigabit,
392 * including Half duplex
393 */
394 if (state->interface != PHY_INTERFACE_MODE_MII &&
395 state->interface != PHY_INTERFACE_MODE_REVMII) {
396 phylink_set(mask, 1000baseT_Full);
397 phylink_set(mask, 1000baseT_Half);
398 }
399
400 // Internal phys of the RTL93xx family provide 10G
401 if (priv->ports[port].phy_is_integrated
402 && state->interface == PHY_INTERFACE_MODE_1000BASEX) {
403 phylink_set(mask, 1000baseX_Full);
404 } else if (priv->ports[port].phy_is_integrated) {
405 phylink_set(mask, 1000baseX_Full);
406 phylink_set(mask, 10000baseKR_Full);
407 phylink_set(mask, 10000baseSR_Full);
408 phylink_set(mask, 10000baseCR_Full);
409 }
410 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
411 phylink_set(mask, 1000baseX_Full);
412 phylink_set(mask, 1000baseT_Full);
413 phylink_set(mask, 10000baseKR_Full);
414 phylink_set(mask, 10000baseT_Full);
415 phylink_set(mask, 10000baseSR_Full);
416 phylink_set(mask, 10000baseCR_Full);
417 }
418
419 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
420 phylink_set(mask, 10000baseT_Full);
421
422 phylink_set(mask, 10baseT_Half);
423 phylink_set(mask, 10baseT_Full);
424 phylink_set(mask, 100baseT_Half);
425 phylink_set(mask, 100baseT_Full);
426
427 bitmap_and(supported, supported, mask,
428 __ETHTOOL_LINK_MODE_MASK_NBITS);
429 bitmap_and(state->advertising, state->advertising, mask,
430 __ETHTOOL_LINK_MODE_MASK_NBITS);
431 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
432 }
433
434 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
435 struct phylink_link_state *state)
436 {
437 struct rtl838x_switch_priv *priv = ds->priv;
438 u64 speed;
439 u64 link;
440
441 if (port < 0 || port > priv->cpu_port)
442 return -EINVAL;
443
444 state->link = 0;
445 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
446 if (link & BIT_ULL(port))
447 state->link = 1;
448 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
449
450 state->duplex = 0;
451 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
452 state->duplex = 1;
453
454 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
455 speed >>= (port % 16) << 1;
456 switch (speed & 0x3) {
457 case 0:
458 state->speed = SPEED_10;
459 break;
460 case 1:
461 state->speed = SPEED_100;
462 break;
463 case 2:
464 state->speed = SPEED_1000;
465 break;
466 case 3:
467 if (priv->family_id == RTL9300_FAMILY_ID
468 && (port == 24 || port == 26)) /* Internal serdes */
469 state->speed = SPEED_2500;
470 else
471 state->speed = SPEED_100; /* Is in fact 500Mbit */
472 }
473
474 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
475 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
476 state->pause |= MLO_PAUSE_RX;
477 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
478 state->pause |= MLO_PAUSE_TX;
479 return 1;
480 }
481
482 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
483 struct phylink_link_state *state)
484 {
485 struct rtl838x_switch_priv *priv = ds->priv;
486 u64 speed;
487 u64 link;
488 u64 media;
489
490 if (port < 0 || port > priv->cpu_port)
491 return -EINVAL;
492
493 /*
494 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
495 * state needs to be read twice in order to read a correct result.
496 * This would not be necessary for ports connected e.g. to RTL8218D
497 * PHYs.
498 */
499 state->link = 0;
500 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
501 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
502 if (link & BIT_ULL(port))
503 state->link = 1;
504
505 if (priv->family_id == RTL9310_FAMILY_ID)
506 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
507
508 if (priv->family_id == RTL9300_FAMILY_ID)
509 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
510
511 if (media & BIT_ULL(port))
512 state->link = 1;
513
514 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
515 link & BIT_ULL(port), media);
516
517 state->duplex = 0;
518 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
519 state->duplex = 1;
520
521 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
522 speed >>= (port % 8) << 2;
523 switch (speed & 0xf) {
524 case 0:
525 state->speed = SPEED_10;
526 break;
527 case 1:
528 state->speed = SPEED_100;
529 break;
530 case 2:
531 case 7:
532 state->speed = SPEED_1000;
533 break;
534 case 4:
535 state->speed = SPEED_10000;
536 break;
537 case 5:
538 case 8:
539 state->speed = SPEED_2500;
540 break;
541 case 6:
542 state->speed = SPEED_5000;
543 break;
544 default:
545 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
546 }
547
548 if (priv->family_id == RTL9310_FAMILY_ID
549 && (port >= 52 || port <= 55)) { /* Internal serdes */
550 state->speed = SPEED_10000;
551 state->link = 1;
552 state->duplex = 1;
553 }
554
555 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
556 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
557 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
558 state->pause |= MLO_PAUSE_RX;
559 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
560 state->pause |= MLO_PAUSE_TX;
561 return 1;
562 }
563
564 static void rtl83xx_config_interface(int port, phy_interface_t interface)
565 {
566 u32 old, int_shift, sds_shift;
567
568 switch (port) {
569 case 24:
570 int_shift = 0;
571 sds_shift = 5;
572 break;
573 case 26:
574 int_shift = 3;
575 sds_shift = 0;
576 break;
577 default:
578 return;
579 }
580
581 old = sw_r32(RTL838X_SDS_MODE_SEL);
582 switch (interface) {
583 case PHY_INTERFACE_MODE_1000BASEX:
584 if ((old >> sds_shift & 0x1f) == 4)
585 return;
586 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
587 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
588 break;
589 case PHY_INTERFACE_MODE_SGMII:
590 if ((old >> sds_shift & 0x1f) == 2)
591 return;
592 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
593 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
594 break;
595 default:
596 return;
597 }
598 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
599 }
600
601 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
602 unsigned int mode,
603 const struct phylink_link_state *state)
604 {
605 struct rtl838x_switch_priv *priv = ds->priv;
606 u32 reg;
607 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
608
609 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
610
611 if (port == priv->cpu_port) {
612 /* Set Speed, duplex, flow control
613 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
614 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
615 * | MEDIA_SEL
616 */
617 if (priv->family_id == RTL8380_FAMILY_ID) {
618 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
619 /* allow CRC errors on CPU-port */
620 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
621 } else {
622 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
623 }
624 return;
625 }
626
627 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
628 /* Auto-Negotiation does not work for MAC in RTL8390 */
629 if (priv->family_id == RTL8380_FAMILY_ID) {
630 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
631 pr_debug("PHY autonegotiates\n");
632 reg |= RTL838X_NWAY_EN;
633 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
634 rtl83xx_config_interface(port, state->interface);
635 return;
636 }
637 }
638
639 if (mode != MLO_AN_FIXED)
640 pr_debug("Fixed state.\n");
641
642 /* Clear id_mode_dis bit, and the existing port mode, let
643 * RGMII_MODE_EN bet set by mac_link_{up,down} */
644 if (priv->family_id == RTL8380_FAMILY_ID) {
645 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
646 if (state->pause & MLO_PAUSE_TXRX_MASK) {
647 if (state->pause & MLO_PAUSE_TX)
648 reg |= RTL838X_TX_PAUSE_EN;
649 reg |= RTL838X_RX_PAUSE_EN;
650 }
651 } else if (priv->family_id == RTL8390_FAMILY_ID) {
652 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
653 if (state->pause & MLO_PAUSE_TXRX_MASK) {
654 if (state->pause & MLO_PAUSE_TX)
655 reg |= RTL839X_TX_PAUSE_EN;
656 reg |= RTL839X_RX_PAUSE_EN;
657 }
658 }
659
660
661 reg &= ~(3 << speed_bit);
662 switch (state->speed) {
663 case SPEED_1000:
664 reg |= 2 << speed_bit;
665 break;
666 case SPEED_100:
667 reg |= 1 << speed_bit;
668 break;
669 default:
670 break; // Ignore, including 10MBit which has a speed value of 0
671 }
672
673 if (priv->family_id == RTL8380_FAMILY_ID) {
674 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
675 if (state->link)
676 reg |= RTL838X_FORCE_LINK_EN;
677 if (state->duplex == RTL838X_DUPLEX_MODE)
678 reg |= RTL838X_DUPLEX_MODE;
679 } else if (priv->family_id == RTL8390_FAMILY_ID) {
680 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
681 if (state->link)
682 reg |= RTL839X_FORCE_LINK_EN;
683 if (state->duplex == RTL839X_DUPLEX_MODE)
684 reg |= RTL839X_DUPLEX_MODE;
685 }
686
687 // LAG members must use DUPLEX and we need to enable the link
688 if (priv->lagmembers & BIT_ULL(port)) {
689 switch(priv->family_id) {
690 case RTL8380_FAMILY_ID:
691 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
692 break;
693 case RTL8390_FAMILY_ID:
694 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
695 break;
696 }
697 }
698
699 // Disable AN
700 if (priv->family_id == RTL8380_FAMILY_ID)
701 reg &= ~RTL838X_NWAY_EN;
702 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
703 }
704
705 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
706 unsigned int mode,
707 const struct phylink_link_state *state)
708 {
709 struct rtl838x_switch_priv *priv = ds->priv;
710 int sds_num;
711 u32 reg, band;
712
713 sds_num = priv->ports[port].sds_num;
714 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
715
716 switch (state->interface) {
717 case PHY_INTERFACE_MODE_HSGMII:
718 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
719 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
720 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
721 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
722 break;
723 case PHY_INTERFACE_MODE_1000BASEX:
724 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
725 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
726 break;
727 case PHY_INTERFACE_MODE_XGMII:
728 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
729 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
730 break;
731 case PHY_INTERFACE_MODE_10GBASER:
732 case PHY_INTERFACE_MODE_10GKR:
733 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
734 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
735 break;
736 case PHY_INTERFACE_MODE_USXGMII:
737 // Translates to MII_USXGMII_10GSXGMII
738 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
739 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
740 break;
741 case PHY_INTERFACE_MODE_SGMII:
742 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
743 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
744 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
745 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
746 break;
747 case PHY_INTERFACE_MODE_QSGMII:
748 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
749 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
750 break;
751 default:
752 pr_err("%s: unknown serdes mode: %s\n",
753 __func__, phy_modes(state->interface));
754 return;
755 }
756
757 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
758 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
759
760 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
761
762 reg &= ~(0xf << 12);
763 reg |= 0x2 << 12; // Set SMI speed to 0x2
764
765 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
766
767 if (priv->lagmembers & BIT_ULL(port))
768 reg |= RTL931X_DUPLEX_MODE;
769
770 if (state->duplex == DUPLEX_FULL)
771 reg |= RTL931X_DUPLEX_MODE;
772
773 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
774
775 }
776
777 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
778 unsigned int mode,
779 const struct phylink_link_state *state)
780 {
781 struct rtl838x_switch_priv *priv = ds->priv;
782 int sds_num, sds_mode;
783 u32 reg;
784
785 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
786 port, mode, phy_modes(state->interface), state->speed, state->link);
787
788 // Nothing to be done for the CPU-port
789 if (port == priv->cpu_port)
790 return;
791
792 if (priv->family_id == RTL9310_FAMILY_ID)
793 return rtl931x_phylink_mac_config(ds, port, mode, state);
794
795 sds_num = priv->ports[port].sds_num;
796 pr_info("%s SDS is %d\n", __func__, sds_num);
797 if (sds_num >= 0) {
798 switch (state->interface) {
799 case PHY_INTERFACE_MODE_HSGMII:
800 sds_mode = 0x12;
801 break;
802 case PHY_INTERFACE_MODE_1000BASEX:
803 sds_mode = 0x04;
804 break;
805 case PHY_INTERFACE_MODE_XGMII:
806 sds_mode = 0x10;
807 break;
808 case PHY_INTERFACE_MODE_10GBASER:
809 case PHY_INTERFACE_MODE_10GKR:
810 sds_mode = 0x1b; // 10G 1000X Auto
811 break;
812 case PHY_INTERFACE_MODE_USXGMII:
813 sds_mode = 0x0d;
814 break;
815 default:
816 pr_err("%s: unknown serdes mode: %s\n",
817 __func__, phy_modes(state->interface));
818 return;
819 }
820 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
821 rtl9300_serdes_setup(sds_num, state->interface);
822 }
823
824 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
825 reg &= ~(0xf << 3);
826
827 switch (state->speed) {
828 case SPEED_10000:
829 reg |= 4 << 3;
830 break;
831 case SPEED_5000:
832 reg |= 6 << 3;
833 break;
834 case SPEED_2500:
835 reg |= 5 << 3;
836 break;
837 case SPEED_1000:
838 reg |= 2 << 3;
839 break;
840 default:
841 reg |= 2 << 3;
842 break;
843 }
844
845 if (state->link)
846 reg |= RTL930X_FORCE_LINK_EN;
847
848 if (priv->lagmembers & BIT_ULL(port))
849 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
850
851 if (state->duplex == DUPLEX_FULL)
852 reg |= RTL930X_DUPLEX_MODE;
853
854 if (priv->ports[port].phy_is_integrated)
855 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
856 else
857 reg |= RTL930X_FORCE_EN;
858
859 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
860 }
861
862 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
863 unsigned int mode,
864 phy_interface_t interface)
865 {
866 struct rtl838x_switch_priv *priv = ds->priv;
867
868 /* Stop TX/RX to port */
869 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
870
871 // No longer force link
872 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
873 }
874
875 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
876 unsigned int mode,
877 phy_interface_t interface)
878 {
879 struct rtl838x_switch_priv *priv = ds->priv;
880 u32 v = 0;
881
882 /* Stop TX/RX to port */
883 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
884
885 // No longer force link
886 if (priv->family_id == RTL9300_FAMILY_ID)
887 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
888 else if (priv->family_id == RTL9310_FAMILY_ID)
889 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
890 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
891 }
892
893 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
894 unsigned int mode,
895 phy_interface_t interface,
896 struct phy_device *phydev,
897 int speed, int duplex,
898 bool tx_pause, bool rx_pause)
899 {
900 struct rtl838x_switch_priv *priv = ds->priv;
901 /* Restart TX/RX to port */
902 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
903 // TODO: Set speed/duplex/pauses
904 }
905
906 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
907 unsigned int mode,
908 phy_interface_t interface,
909 struct phy_device *phydev,
910 int speed, int duplex,
911 bool tx_pause, bool rx_pause)
912 {
913 struct rtl838x_switch_priv *priv = ds->priv;
914
915 /* Restart TX/RX to port */
916 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
917 // TODO: Set speed/duplex/pauses
918 }
919
920 static void rtl83xx_get_strings(struct dsa_switch *ds,
921 int port, u32 stringset, u8 *data)
922 {
923 int i;
924
925 if (stringset != ETH_SS_STATS)
926 return;
927
928 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
929 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
930 ETH_GSTRING_LEN);
931 }
932
933 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
934 uint64_t *data)
935 {
936 struct rtl838x_switch_priv *priv = ds->priv;
937 const struct rtl83xx_mib_desc *mib;
938 int i;
939 u64 h;
940
941 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
942 mib = &rtl83xx_mib[i];
943
944 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
945 if (mib->size == 2) {
946 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
947 data[i] |= h << 32;
948 }
949 }
950 }
951
952 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
953 {
954 if (sset != ETH_SS_STATS)
955 return 0;
956
957 return ARRAY_SIZE(rtl83xx_mib);
958 }
959
960 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
961 {
962 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
963 u64 portmask;
964
965 if (mc_group >= MAX_MC_GROUPS - 1)
966 return -1;
967
968 if (priv->is_lagmember[port]) {
969 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
970 return 0;
971 }
972
973 set_bit(mc_group, priv->mc_group_bm);
974 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
975 portmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port);
976 priv->r->write_mcast_pmask(mc_group, portmask);
977
978 return mc_group;
979 }
980
981 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
982 {
983 u64 portmask = priv->r->read_mcast_pmask(mc_group);
984
985 pr_debug("%s: %d\n", __func__, port);
986 if (priv->is_lagmember[port]) {
987 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
988 return portmask;
989 }
990 portmask |= BIT_ULL(port);
991 priv->r->write_mcast_pmask(mc_group, portmask);
992
993 return portmask;
994 }
995
996 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
997 {
998 u64 portmask = priv->r->read_mcast_pmask(mc_group);
999
1000 pr_debug("%s: %d\n", __func__, port);
1001 if (priv->is_lagmember[port]) {
1002 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1003 return portmask;
1004 }
1005 priv->r->write_mcast_pmask(mc_group, portmask);
1006 if (portmask == BIT_ULL(priv->cpu_port)) {
1007 portmask &= ~BIT_ULL(priv->cpu_port);
1008 priv->r->write_mcast_pmask(mc_group, portmask);
1009 clear_bit(mc_group, priv->mc_group_bm);
1010 }
1011
1012 return portmask;
1013 }
1014
1015 static void store_mcgroups(struct rtl838x_switch_priv *priv, int port)
1016 {
1017 int mc_group;
1018
1019 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1020 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1021 if (portmask & BIT_ULL(port)) {
1022 priv->mc_group_saves[mc_group] = port;
1023 rtl83xx_mc_group_del_port(priv, mc_group, port);
1024 }
1025 }
1026 }
1027
1028 static void load_mcgroups(struct rtl838x_switch_priv *priv, int port)
1029 {
1030 int mc_group;
1031
1032 for (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {
1033 if (priv->mc_group_saves[mc_group] == port) {
1034 rtl83xx_mc_group_add_port(priv, mc_group, port);
1035 priv->mc_group_saves[mc_group] = -1;
1036 }
1037 }
1038 }
1039
1040 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1041 struct phy_device *phydev)
1042 {
1043 struct rtl838x_switch_priv *priv = ds->priv;
1044 u64 v;
1045
1046 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1047 priv->ports[port].enable = true;
1048
1049 /* enable inner tagging on egress, do not keep any tags */
1050 if (priv->family_id == RTL9310_FAMILY_ID)
1051 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
1052 else
1053 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
1054
1055 if (dsa_is_cpu_port(ds, port))
1056 return 0;
1057
1058 /* add port to switch mask of CPU_PORT */
1059 priv->r->traffic_enable(priv->cpu_port, port);
1060
1061 load_mcgroups(priv, port);
1062
1063 if (priv->is_lagmember[port]) {
1064 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1065 return 0;
1066 }
1067
1068 /* add all other ports in the same bridge to switch mask of port */
1069 v = priv->r->traffic_get(port);
1070 v |= priv->ports[port].pm;
1071 priv->r->traffic_set(port, v);
1072
1073 // TODO: Figure out if this is necessary
1074 if (priv->family_id == RTL9300_FAMILY_ID) {
1075 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1076 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1077 }
1078
1079 if (priv->ports[port].sds_num < 0)
1080 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1081
1082 return 0;
1083 }
1084
1085 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1086 {
1087 struct rtl838x_switch_priv *priv = ds->priv;
1088 u64 v;
1089
1090 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1091 /* you can only disable user ports */
1092 if (!dsa_is_user_port(ds, port))
1093 return;
1094
1095 // BUG: This does not work on RTL931X
1096 /* remove port from switch mask of CPU_PORT */
1097 priv->r->traffic_disable(priv->cpu_port, port);
1098 store_mcgroups(priv, port);
1099
1100 /* remove all other ports in the same bridge from switch mask of port */
1101 v = priv->r->traffic_get(port);
1102 v &= ~priv->ports[port].pm;
1103 priv->r->traffic_set(port, v);
1104
1105 priv->ports[port].enable = false;
1106 }
1107
1108 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1109 struct ethtool_eee *e)
1110 {
1111 struct rtl838x_switch_priv *priv = ds->priv;
1112
1113 if (e->eee_enabled && !priv->eee_enabled) {
1114 pr_info("Globally enabling EEE\n");
1115 priv->r->init_eee(priv, true);
1116 }
1117
1118 priv->r->port_eee_set(priv, port, e->eee_enabled);
1119
1120 if (e->eee_enabled)
1121 pr_info("Enabled EEE for port %d\n", port);
1122 else
1123 pr_info("Disabled EEE for port %d\n", port);
1124 return 0;
1125 }
1126
1127 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1128 struct ethtool_eee *e)
1129 {
1130 struct rtl838x_switch_priv *priv = ds->priv;
1131
1132 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1133
1134 priv->r->eee_port_ability(priv, e, port);
1135
1136 e->eee_enabled = priv->ports[port].eee_enabled;
1137
1138 e->eee_active = !!(e->advertised & e->lp_advertised);
1139
1140 return 0;
1141 }
1142
1143 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1144 struct ethtool_eee *e)
1145 {
1146 struct rtl838x_switch_priv *priv = ds->priv;
1147
1148 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
1149 | SUPPORTED_2500baseX_Full;
1150
1151 priv->r->eee_port_ability(priv, e, port);
1152
1153 e->eee_enabled = priv->ports[port].eee_enabled;
1154
1155 e->eee_active = !!(e->advertised & e->lp_advertised);
1156
1157 return 0;
1158 }
1159
1160 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1161 {
1162 struct rtl838x_switch_priv *priv = ds->priv;
1163
1164 priv->r->set_ageing_time(msec);
1165 return 0;
1166 }
1167
1168 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1169 struct net_device *bridge)
1170 {
1171 struct rtl838x_switch_priv *priv = ds->priv;
1172 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1173 int i;
1174
1175 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1176
1177 if (priv->is_lagmember[port]) {
1178 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1179 return 0;
1180 }
1181
1182 mutex_lock(&priv->reg_mutex);
1183 for (i = 0; i < ds->num_ports; i++) {
1184 /* Add this port to the port matrix of the other ports in the
1185 * same bridge. If the port is disabled, port matrix is kept
1186 * and not being setup until the port becomes enabled.
1187 */
1188 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1189 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1190 continue;
1191 if (priv->ports[i].enable)
1192 priv->r->traffic_enable(i, port);
1193
1194 priv->ports[i].pm |= BIT_ULL(port);
1195 port_bitmap |= BIT_ULL(i);
1196 }
1197 }
1198 load_mcgroups(priv, port);
1199
1200 /* Add all other ports to this port matrix. */
1201 if (priv->ports[port].enable) {
1202 priv->r->traffic_enable(priv->cpu_port, port);
1203 v = priv->r->traffic_get(port);
1204 v |= port_bitmap;
1205 priv->r->traffic_set(port, v);
1206 }
1207 priv->ports[port].pm |= port_bitmap;
1208 mutex_unlock(&priv->reg_mutex);
1209
1210 return 0;
1211 }
1212
1213 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1214 struct net_device *bridge)
1215 {
1216 struct rtl838x_switch_priv *priv = ds->priv;
1217 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1218 int i;
1219
1220 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1221 mutex_lock(&priv->reg_mutex);
1222 for (i = 0; i < ds->num_ports; i++) {
1223 /* Remove this port from the port matrix of the other ports
1224 * in the same bridge. If the port is disabled, port matrix
1225 * is kept and not being setup until the port becomes enabled.
1226 * And the other port's port matrix cannot be broken when the
1227 * other port is still a VLAN-aware port.
1228 */
1229 if (dsa_is_user_port(ds, i) && i != port) {
1230 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1231 continue;
1232 if (priv->ports[i].enable)
1233 priv->r->traffic_disable(i, port);
1234
1235 priv->ports[i].pm |= BIT_ULL(port);
1236 port_bitmap &= ~BIT_ULL(i);
1237 }
1238 }
1239 store_mcgroups(priv, port);
1240
1241 /* Add all other ports to this port matrix. */
1242 if (priv->ports[port].enable) {
1243 v = priv->r->traffic_get(port);
1244 v |= port_bitmap;
1245 priv->r->traffic_set(port, v);
1246 }
1247 priv->ports[port].pm &= ~port_bitmap;
1248
1249 mutex_unlock(&priv->reg_mutex);
1250 }
1251
1252 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1253 {
1254 u32 msti = 0;
1255 u32 port_state[4];
1256 int index, bit;
1257 int pos = port;
1258 struct rtl838x_switch_priv *priv = ds->priv;
1259 int n = priv->port_width << 1;
1260
1261 /* Ports above or equal CPU port can never be configured */
1262 if (port >= priv->cpu_port)
1263 return;
1264
1265 mutex_lock(&priv->reg_mutex);
1266
1267 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1268 * have 64 bit fields, 839x and 931x have 128 bit fields
1269 */
1270 if (priv->family_id == RTL8390_FAMILY_ID)
1271 pos += 12;
1272 if (priv->family_id == RTL9300_FAMILY_ID)
1273 pos += 3;
1274 if (priv->family_id == RTL9310_FAMILY_ID)
1275 pos += 8;
1276
1277 index = n - (pos >> 4) - 1;
1278 bit = (pos << 1) % 32;
1279
1280 priv->r->stp_get(priv, msti, port_state);
1281
1282 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1283 port_state[index] &= ~(3 << bit);
1284
1285 switch (state) {
1286 case BR_STATE_DISABLED: /* 0 */
1287 port_state[index] |= (0 << bit);
1288 break;
1289 case BR_STATE_BLOCKING: /* 4 */
1290 case BR_STATE_LISTENING: /* 1 */
1291 port_state[index] |= (1 << bit);
1292 break;
1293 case BR_STATE_LEARNING: /* 2 */
1294 port_state[index] |= (2 << bit);
1295 break;
1296 case BR_STATE_FORWARDING: /* 3*/
1297 port_state[index] |= (3 << bit);
1298 default:
1299 break;
1300 }
1301
1302 priv->r->stp_set(priv, msti, port_state);
1303
1304 mutex_unlock(&priv->reg_mutex);
1305 }
1306
1307 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1308 {
1309 struct rtl838x_switch_priv *priv = ds->priv;
1310 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1311
1312 pr_debug("FAST AGE port %d\n", port);
1313 mutex_lock(&priv->reg_mutex);
1314 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1315 * port fields:
1316 * 0-4: Replacing port
1317 * 5-9: Flushed/replaced port
1318 * 10-21: FVID
1319 * 22: Entry types: 1: dynamic, 0: also static
1320 * 23: Match flush port
1321 * 24: Match FVID
1322 * 25: Flush (0) or replace (1) L2 entries
1323 * 26: Status of action (1: Start, 0: Done)
1324 */
1325 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1326
1327 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1328
1329 mutex_unlock(&priv->reg_mutex);
1330 }
1331
1332 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1333 {
1334 struct rtl838x_switch_priv *priv = ds->priv;
1335
1336 pr_info("%s port %d\n", __func__, port);
1337 mutex_lock(&priv->reg_mutex);
1338 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1339
1340 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1341
1342 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1343
1344 mutex_unlock(&priv->reg_mutex);
1345 }
1346
1347 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1348 {
1349 struct rtl838x_switch_priv *priv = ds->priv;
1350
1351 if (priv->family_id == RTL9310_FAMILY_ID)
1352 return rtl931x_fast_age(ds, port);
1353
1354 pr_debug("FAST AGE port %d\n", port);
1355 mutex_lock(&priv->reg_mutex);
1356 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1357
1358 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1359
1360 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1361
1362 mutex_unlock(&priv->reg_mutex);
1363 }
1364
1365 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1366 bool vlan_filtering,
1367 struct switchdev_trans *trans)
1368 {
1369 struct rtl838x_switch_priv *priv = ds->priv;
1370
1371 pr_debug("%s: port %d\n", __func__, port);
1372 mutex_lock(&priv->reg_mutex);
1373
1374 if (vlan_filtering) {
1375 /* Enable ingress and egress filtering
1376 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1377 * the filter action:
1378 * 0: Always Forward
1379 * 1: Drop packet
1380 * 2: Trap packet to CPU port
1381 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1382 */
1383 if (port != priv->cpu_port)
1384 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1385
1386 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1387 } else {
1388 /* Disable ingress and egress filtering */
1389 if (port != priv->cpu_port)
1390 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1391
1392 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1393 }
1394
1395 /* Do we need to do something to the CPU-Port, too? */
1396 mutex_unlock(&priv->reg_mutex);
1397
1398 return 0;
1399 }
1400
1401 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1402 const struct switchdev_obj_port_vlan *vlan)
1403 {
1404 struct rtl838x_vlan_info info;
1405 struct rtl838x_switch_priv *priv = ds->priv;
1406
1407 priv->r->vlan_tables_read(0, &info);
1408
1409 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1410 info.tagged_ports, info.untagged_ports, info.profile_id,
1411 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1412
1413 priv->r->vlan_tables_read(1, &info);
1414 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1415 info.tagged_ports, info.untagged_ports, info.profile_id,
1416 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1417 priv->r->vlan_set_untagged(1, info.untagged_ports);
1418 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1419
1420 priv->r->vlan_set_tagged(1, &info);
1421 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1422
1423 return 0;
1424 }
1425
1426 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1427 const struct switchdev_obj_port_vlan *vlan)
1428 {
1429 struct rtl838x_vlan_info info;
1430 struct rtl838x_switch_priv *priv = ds->priv;
1431 int v;
1432
1433 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1434 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1435
1436 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1437 dev_err(priv->dev, "VLAN out of range: %d - %d",
1438 vlan->vid_begin, vlan->vid_end);
1439 return;
1440 }
1441
1442 mutex_lock(&priv->reg_mutex);
1443
1444 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1445 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1446 if (!v)
1447 continue;
1448 /* Set both inner and outer PVID of the port */
1449 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, v);
1450 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, v);
1451 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1452 PBVLAN_MODE_UNTAG_AND_PRITAG);
1453 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1454 PBVLAN_MODE_UNTAG_AND_PRITAG);
1455
1456 priv->ports[port].pvid = vlan->vid_end;
1457 }
1458 }
1459
1460 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1461 /* Get port memberships of this vlan */
1462 priv->r->vlan_tables_read(v, &info);
1463
1464 /* new VLAN? */
1465 if (!info.tagged_ports) {
1466 info.fid = 0;
1467 info.hash_mc_fid = false;
1468 info.hash_uc_fid = false;
1469 info.profile_id = 0;
1470 }
1471
1472 /* sanitize untagged_ports - must be a subset */
1473 if (info.untagged_ports & ~info.tagged_ports)
1474 info.untagged_ports = 0;
1475
1476 info.tagged_ports |= BIT_ULL(port);
1477 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1478 info.untagged_ports |= BIT_ULL(port);
1479
1480 priv->r->vlan_set_untagged(v, info.untagged_ports);
1481 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1482
1483 priv->r->vlan_set_tagged(v, &info);
1484 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1485 }
1486
1487 mutex_unlock(&priv->reg_mutex);
1488 }
1489
1490 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1491 const struct switchdev_obj_port_vlan *vlan)
1492 {
1493 struct rtl838x_vlan_info info;
1494 struct rtl838x_switch_priv *priv = ds->priv;
1495 int v;
1496 u16 pvid;
1497
1498 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1499 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1500
1501 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1502 dev_err(priv->dev, "VLAN out of range: %d - %d",
1503 vlan->vid_begin, vlan->vid_end);
1504 return -ENOTSUPP;
1505 }
1506
1507 mutex_lock(&priv->reg_mutex);
1508 pvid = priv->ports[port].pvid;
1509
1510 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1511 /* Reset to default if removing the current PVID */
1512 if (v == pvid) {
1513 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);
1514 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);
1515 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1516 PBVLAN_MODE_UNTAG_AND_PRITAG);
1517 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1518 PBVLAN_MODE_UNTAG_AND_PRITAG);
1519 }
1520 /* Get port memberships of this vlan */
1521 priv->r->vlan_tables_read(v, &info);
1522
1523 /* remove port from both tables */
1524 info.untagged_ports &= (~BIT_ULL(port));
1525 info.tagged_ports &= (~BIT_ULL(port));
1526
1527 priv->r->vlan_set_untagged(v, info.untagged_ports);
1528 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1529
1530 priv->r->vlan_set_tagged(v, &info);
1531 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1532 }
1533 mutex_unlock(&priv->reg_mutex);
1534
1535 return 0;
1536 }
1537
1538 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1539 {
1540 e->is_ip_mc = e->is_ipv6_mc = false;
1541 e->valid = true;
1542 e->age = 3;
1543 e->port = port,
1544 e->vid = vid;
1545 u64_to_ether_addr(mac, e->mac);
1546 }
1547
1548 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1549 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1550 {
1551 e->is_ip_mc = e->is_ipv6_mc = false;
1552 e->valid = true;
1553 e->mc_portmask_index = mc_group;
1554 e->type = L2_MULTICAST;
1555 e->rvid = e->vid = vid;
1556 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1557 u64_to_ether_addr(mac, e->mac);
1558 }
1559
1560 /*
1561 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1562 * over the entries in the bucket until either a matching entry is found or an empty slot
1563 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1564 * when an empty slot was found and must exist is false, the index of the slot is returned
1565 * when no slots are available returns -1
1566 */
1567 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1568 bool must_exist, struct rtl838x_l2_entry *e)
1569 {
1570 int i, idx = -1;
1571 u32 key = priv->r->l2_hash_key(priv, seed);
1572 u64 entry;
1573
1574 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1575 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1576 for (i = 0; i < priv->l2_bucket_size; i++) {
1577 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1578 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1579 if (must_exist && !e->valid)
1580 continue;
1581 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1582 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1583 break;
1584 }
1585 }
1586
1587 return idx;
1588 }
1589
1590 /*
1591 * Uses the seed to identify an entry in the CAM by looping over all its entries
1592 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1593 * when an empty slot was found the index of the slot is returned
1594 * when no slots are available returns -1
1595 */
1596 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1597 bool must_exist, struct rtl838x_l2_entry *e)
1598 {
1599 int i, idx = -1;
1600 u64 entry;
1601
1602 for (i = 0; i < 64; i++) {
1603 entry = priv->r->read_cam(i, e);
1604 if (!must_exist && !e->valid) {
1605 if (idx < 0) /* First empty entry? */
1606 idx = i;
1607 break;
1608 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1609 pr_debug("Found entry in CAM\n");
1610 idx = i;
1611 break;
1612 }
1613 }
1614 return idx;
1615 }
1616
1617 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1618 const unsigned char *addr, u16 vid)
1619 {
1620 struct rtl838x_switch_priv *priv = ds->priv;
1621 u64 mac = ether_addr_to_u64(addr);
1622 struct rtl838x_l2_entry e;
1623 int err = 0, idx;
1624 u64 seed = priv->r->l2_hash_seed(mac, vid);
1625
1626 if (priv->is_lagmember[port]) {
1627 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1628 return 0;
1629 }
1630
1631 mutex_lock(&priv->reg_mutex);
1632
1633 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1634
1635 // Found an existing or empty entry
1636 if (idx >= 0) {
1637 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1638 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1639 goto out;
1640 }
1641
1642 // Hash buckets full, try CAM
1643 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1644
1645 if (idx >= 0) {
1646 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1647 priv->r->write_cam(idx, &e);
1648 goto out;
1649 }
1650
1651 err = -ENOTSUPP;
1652 out:
1653 mutex_unlock(&priv->reg_mutex);
1654 return err;
1655 }
1656
1657 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1658 const unsigned char *addr, u16 vid)
1659 {
1660 struct rtl838x_switch_priv *priv = ds->priv;
1661 u64 mac = ether_addr_to_u64(addr);
1662 struct rtl838x_l2_entry e;
1663 int err = 0, idx;
1664 u64 seed = priv->r->l2_hash_seed(mac, vid);
1665
1666 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1667 mutex_lock(&priv->reg_mutex);
1668
1669 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1670
1671 if (idx >= 0) {
1672 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1673 e.valid = false;
1674 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1675 goto out;
1676 }
1677
1678 /* Check CAM for spillover from hash buckets */
1679 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1680
1681 if (idx >= 0) {
1682 e.valid = false;
1683 priv->r->write_cam(idx, &e);
1684 goto out;
1685 }
1686 err = -ENOENT;
1687 out:
1688 mutex_unlock(&priv->reg_mutex);
1689 return err;
1690 }
1691
1692 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1693 dsa_fdb_dump_cb_t *cb, void *data)
1694 {
1695 struct rtl838x_l2_entry e;
1696 struct rtl838x_switch_priv *priv = ds->priv;
1697 int i;
1698
1699 mutex_lock(&priv->reg_mutex);
1700
1701 for (i = 0; i < priv->fib_entries; i++) {
1702 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1703
1704 if (!e.valid)
1705 continue;
1706
1707 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1708 cb(e.mac, e.vid, e.is_static, data);
1709 }
1710
1711 for (i = 0; i < 64; i++) {
1712 priv->r->read_cam(i, &e);
1713
1714 if (!e.valid)
1715 continue;
1716
1717 if (e.port == port)
1718 cb(e.mac, e.vid, e.is_static, data);
1719 }
1720
1721 mutex_unlock(&priv->reg_mutex);
1722 return 0;
1723 }
1724
1725 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1726 const struct switchdev_obj_port_mdb *mdb)
1727 {
1728 struct rtl838x_switch_priv *priv = ds->priv;
1729
1730 if (priv->id >= 0x9300)
1731 return -EOPNOTSUPP;
1732
1733 return 0;
1734 }
1735
1736 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1737 const struct switchdev_obj_port_mdb *mdb)
1738 {
1739 struct rtl838x_switch_priv *priv = ds->priv;
1740 u64 mac = ether_addr_to_u64(mdb->addr);
1741 struct rtl838x_l2_entry e;
1742 int err = 0, idx;
1743 int vid = mdb->vid;
1744 u64 seed = priv->r->l2_hash_seed(mac, vid);
1745 int mc_group;
1746
1747 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1748
1749 if (priv->is_lagmember[port]) {
1750 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1751 return;
1752 }
1753
1754 mutex_lock(&priv->reg_mutex);
1755
1756 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1757
1758 // Found an existing or empty entry
1759 if (idx >= 0) {
1760 if (e.valid) {
1761 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1762 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1763 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1764 } else {
1765 pr_debug("New entry for seed %016llx\n", seed);
1766 mc_group = rtl83xx_mc_group_alloc(priv, port);
1767 if (mc_group < 0) {
1768 err = -ENOTSUPP;
1769 goto out;
1770 }
1771 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1772 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1773 }
1774 goto out;
1775 }
1776
1777 // Hash buckets full, try CAM
1778 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1779
1780 if (idx >= 0) {
1781 if (e.valid) {
1782 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1783 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1784 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1785 } else {
1786 pr_debug("New entry\n");
1787 mc_group = rtl83xx_mc_group_alloc(priv, port);
1788 if (mc_group < 0) {
1789 err = -ENOTSUPP;
1790 goto out;
1791 }
1792 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1793 priv->r->write_cam(idx, &e);
1794 }
1795 goto out;
1796 }
1797
1798 err = -ENOTSUPP;
1799 out:
1800 mutex_unlock(&priv->reg_mutex);
1801 if (err)
1802 dev_err(ds->dev, "failed to add MDB entry\n");
1803 }
1804
1805 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1806 const struct switchdev_obj_port_mdb *mdb)
1807 {
1808 struct rtl838x_switch_priv *priv = ds->priv;
1809 u64 mac = ether_addr_to_u64(mdb->addr);
1810 struct rtl838x_l2_entry e;
1811 int err = 0, idx;
1812 int vid = mdb->vid;
1813 u64 seed = priv->r->l2_hash_seed(mac, vid);
1814 u64 portmask;
1815
1816 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1817
1818 if (priv->is_lagmember[port]) {
1819 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1820 return 0;
1821 }
1822
1823 mutex_lock(&priv->reg_mutex);
1824
1825 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1826
1827 if (idx >= 0) {
1828 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1829 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1830 if (!portmask) {
1831 e.valid = false;
1832 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1833 }
1834 goto out;
1835 }
1836
1837 /* Check CAM for spillover from hash buckets */
1838 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1839
1840 if (idx >= 0) {
1841 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1842 if (!portmask) {
1843 e.valid = false;
1844 priv->r->write_cam(idx, &e);
1845 }
1846 goto out;
1847 }
1848 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1849 out:
1850 mutex_unlock(&priv->reg_mutex);
1851 return err;
1852 }
1853
1854 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1855 struct dsa_mall_mirror_tc_entry *mirror,
1856 bool ingress)
1857 {
1858 /* We support 4 mirror groups, one destination port per group */
1859 int group;
1860 struct rtl838x_switch_priv *priv = ds->priv;
1861 int ctrl_reg, dpm_reg, spm_reg;
1862
1863 pr_debug("In %s\n", __func__);
1864
1865 for (group = 0; group < 4; group++) {
1866 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1867 break;
1868 }
1869 if (group >= 4) {
1870 for (group = 0; group < 4; group++) {
1871 if (priv->mirror_group_ports[group] < 0)
1872 break;
1873 }
1874 }
1875
1876 if (group >= 4)
1877 return -ENOSPC;
1878
1879 ctrl_reg = priv->r->mir_ctrl + group * 4;
1880 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1881 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1882
1883 pr_debug("Using group %d\n", group);
1884 mutex_lock(&priv->reg_mutex);
1885
1886 if (priv->family_id == RTL8380_FAMILY_ID) {
1887 /* Enable mirroring to port across VLANs (bit 11) */
1888 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1889 } else {
1890 /* Enable mirroring to destination port */
1891 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1892 }
1893
1894 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1895 mutex_unlock(&priv->reg_mutex);
1896 return -EEXIST;
1897 }
1898 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1899 mutex_unlock(&priv->reg_mutex);
1900 return -EEXIST;
1901 }
1902
1903 if (ingress)
1904 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1905 else
1906 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1907
1908 priv->mirror_group_ports[group] = mirror->to_local_port;
1909 mutex_unlock(&priv->reg_mutex);
1910 return 0;
1911 }
1912
1913 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1914 struct dsa_mall_mirror_tc_entry *mirror)
1915 {
1916 int group = 0;
1917 struct rtl838x_switch_priv *priv = ds->priv;
1918 int ctrl_reg, dpm_reg, spm_reg;
1919
1920 pr_debug("In %s\n", __func__);
1921 for (group = 0; group < 4; group++) {
1922 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1923 break;
1924 }
1925 if (group >= 4)
1926 return;
1927
1928 ctrl_reg = priv->r->mir_ctrl + group * 4;
1929 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1930 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1931
1932 mutex_lock(&priv->reg_mutex);
1933 if (mirror->ingress) {
1934 /* Ingress, clear source port matrix */
1935 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1936 } else {
1937 /* Egress, clear destination port matrix */
1938 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1939 }
1940
1941 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1942 priv->mirror_group_ports[group] = -1;
1943 sw_w32(0, ctrl_reg);
1944 }
1945
1946 mutex_unlock(&priv->reg_mutex);
1947 }
1948
1949 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1950 {
1951 struct rtl838x_switch_priv *priv = ds->priv;
1952 unsigned long features = 0;
1953 pr_debug("%s: %d %lX\n", __func__, port, flags);
1954 if (priv->r->enable_learning)
1955 features |= BR_LEARNING;
1956 if (priv->r->enable_flood)
1957 features |= BR_FLOOD;
1958 if (priv->r->enable_mcast_flood)
1959 features |= BR_MCAST_FLOOD;
1960 if (priv->r->enable_bcast_flood)
1961 features |= BR_BCAST_FLOOD;
1962 if (flags & ~(features))
1963 return -EINVAL;
1964
1965 return 0;
1966 }
1967
1968 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1969 {
1970 struct rtl838x_switch_priv *priv = ds->priv;
1971
1972 pr_debug("%s: %d %lX\n", __func__, port, flags);
1973 if (priv->r->enable_learning)
1974 priv->r->enable_learning(port, !!(flags & BR_LEARNING));
1975
1976 if (priv->r->enable_flood)
1977 priv->r->enable_flood(port, !!(flags & BR_FLOOD));
1978
1979 if (priv->r->enable_mcast_flood)
1980 priv->r->enable_mcast_flood(port, !!(flags & BR_MCAST_FLOOD));
1981
1982 if (priv->r->enable_bcast_flood)
1983 priv->r->enable_bcast_flood(port, !!(flags & BR_BCAST_FLOOD));
1984
1985 return 0;
1986 }
1987
1988 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1989 struct net_device *lag,
1990 struct netdev_lag_upper_info *info)
1991 {
1992 int id;
1993
1994 id = dsa_lag_id(ds->dst, lag);
1995 if (id < 0 || id >= ds->num_lag_ids)
1996 return false;
1997
1998 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1999 return false;
2000 }
2001 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
2002 return false;
2003
2004 return true;
2005 }
2006
2007 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2008 {
2009 struct rtl838x_switch_priv *priv = ds->priv;
2010
2011 pr_debug("%s: %d\n", __func__, port);
2012 // Nothing to be done...
2013
2014 return 0;
2015 }
2016
2017 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2018 struct net_device *lag,
2019 struct netdev_lag_upper_info *info)
2020 {
2021 struct rtl838x_switch_priv *priv = ds->priv;
2022 int i, err = 0;
2023
2024 if (!rtl83xx_lag_can_offload(ds, lag, info))
2025 return -EOPNOTSUPP;
2026
2027 mutex_lock(&priv->reg_mutex);
2028
2029 for (i = 0; i < priv->n_lags; i++) {
2030 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2031 break;
2032 }
2033 if (port >= priv->cpu_port) {
2034 err = -EINVAL;
2035 goto out;
2036 }
2037 pr_info("port_lag_join: group %d, port %d\n",i, port);
2038 if (!priv->lag_devs[i])
2039 priv->lag_devs[i] = lag;
2040
2041 if (priv->lag_primary[i]==-1) {
2042 priv->lag_primary[i]=port;
2043 } else
2044 priv->is_lagmember[port] = 1;
2045
2046 priv->lagmembers |= (1ULL << port);
2047
2048 pr_debug("lag_members = %llX\n", priv->lagmembers);
2049 err = rtl83xx_lag_add(priv->ds, i, port, info);
2050 if (err) {
2051 err = -EINVAL;
2052 goto out;
2053 }
2054
2055 out:
2056 mutex_unlock(&priv->reg_mutex);
2057 return err;
2058
2059 }
2060
2061 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2062 struct net_device *lag)
2063 {
2064 int i, group = -1, err;
2065 struct rtl838x_switch_priv *priv = ds->priv;
2066
2067 mutex_lock(&priv->reg_mutex);
2068 for (i=0;i<priv->n_lags;i++) {
2069 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2070 group = i;
2071 break;
2072 }
2073 }
2074
2075 if (group == -1) {
2076 pr_info("port_lag_leave: port %d is not a member\n", port);
2077 err = -EINVAL;
2078 goto out;
2079 }
2080
2081 if (port >= priv->cpu_port) {
2082 err = -EINVAL;
2083 goto out;
2084 }
2085 pr_info("port_lag_del: group %d, port %d\n",group, port);
2086 priv->lagmembers &=~ (1ULL << port);
2087 priv->lag_primary[i] = -1;
2088 priv->is_lagmember[port] = 0;
2089 pr_debug("lag_members = %llX\n", priv->lagmembers);
2090 err = rtl83xx_lag_del(priv->ds, group, port);
2091 if (err) {
2092 err = -EINVAL;
2093 goto out;
2094 }
2095 if (!priv->lags_port_members[i])
2096 priv->lag_devs[i] = NULL;
2097
2098 out:
2099 mutex_unlock(&priv->reg_mutex);
2100 return 0;
2101 }
2102
2103 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2104 {
2105 u32 val;
2106 u32 offset = 0;
2107 struct rtl838x_switch_priv *priv = ds->priv;
2108
2109 if (phy_addr >= 24 && phy_addr <= 27
2110 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2111 if (phy_addr == 26)
2112 offset = 0x100;
2113 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2114 return val;
2115 }
2116
2117 read_phy(phy_addr, 0, phy_reg, &val);
2118 return val;
2119 }
2120
2121 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2122 {
2123 u32 offset = 0;
2124 struct rtl838x_switch_priv *priv = ds->priv;
2125
2126 if (phy_addr >= 24 && phy_addr <= 27
2127 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2128 if (phy_addr == 26)
2129 offset = 0x100;
2130 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2131 return 0;
2132 }
2133 return write_phy(phy_addr, 0, phy_reg, val);
2134 }
2135
2136 const struct dsa_switch_ops rtl83xx_switch_ops = {
2137 .get_tag_protocol = rtl83xx_get_tag_protocol,
2138 .setup = rtl83xx_setup,
2139
2140 .phy_read = dsa_phy_read,
2141 .phy_write = dsa_phy_write,
2142
2143 .phylink_validate = rtl83xx_phylink_validate,
2144 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2145 .phylink_mac_config = rtl83xx_phylink_mac_config,
2146 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2147 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2148
2149 .get_strings = rtl83xx_get_strings,
2150 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2151 .get_sset_count = rtl83xx_get_sset_count,
2152
2153 .port_enable = rtl83xx_port_enable,
2154 .port_disable = rtl83xx_port_disable,
2155
2156 .get_mac_eee = rtl83xx_get_mac_eee,
2157 .set_mac_eee = rtl83xx_set_mac_eee,
2158
2159 .set_ageing_time = rtl83xx_set_ageing_time,
2160 .port_bridge_join = rtl83xx_port_bridge_join,
2161 .port_bridge_leave = rtl83xx_port_bridge_leave,
2162 .port_stp_state_set = rtl83xx_port_stp_state_set,
2163 .port_fast_age = rtl83xx_fast_age,
2164
2165 .port_vlan_filtering = rtl83xx_vlan_filtering,
2166 .port_vlan_prepare = rtl83xx_vlan_prepare,
2167 .port_vlan_add = rtl83xx_vlan_add,
2168 .port_vlan_del = rtl83xx_vlan_del,
2169
2170 .port_fdb_add = rtl83xx_port_fdb_add,
2171 .port_fdb_del = rtl83xx_port_fdb_del,
2172 .port_fdb_dump = rtl83xx_port_fdb_dump,
2173
2174 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2175 .port_mdb_add = rtl83xx_port_mdb_add,
2176 .port_mdb_del = rtl83xx_port_mdb_del,
2177
2178 .port_mirror_add = rtl83xx_port_mirror_add,
2179 .port_mirror_del = rtl83xx_port_mirror_del,
2180
2181 .port_lag_change = rtl83xx_port_lag_change,
2182 .port_lag_join = rtl83xx_port_lag_join,
2183 .port_lag_leave = rtl83xx_port_lag_leave,
2184
2185 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2186 .port_bridge_flags = rtl83xx_port_bridge_flags,
2187 };
2188
2189 const struct dsa_switch_ops rtl930x_switch_ops = {
2190 .get_tag_protocol = rtl83xx_get_tag_protocol,
2191 .setup = rtl93xx_setup,
2192
2193 .phy_read = dsa_phy_read,
2194 .phy_write = dsa_phy_write,
2195
2196 .phylink_validate = rtl93xx_phylink_validate,
2197 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2198 .phylink_mac_config = rtl93xx_phylink_mac_config,
2199 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2200 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2201
2202 .get_strings = rtl83xx_get_strings,
2203 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2204 .get_sset_count = rtl83xx_get_sset_count,
2205
2206 .port_enable = rtl83xx_port_enable,
2207 .port_disable = rtl83xx_port_disable,
2208
2209 .get_mac_eee = rtl93xx_get_mac_eee,
2210 .set_mac_eee = rtl83xx_set_mac_eee,
2211
2212 .set_ageing_time = rtl83xx_set_ageing_time,
2213 .port_bridge_join = rtl83xx_port_bridge_join,
2214 .port_bridge_leave = rtl83xx_port_bridge_leave,
2215 .port_stp_state_set = rtl83xx_port_stp_state_set,
2216 .port_fast_age = rtl930x_fast_age,
2217
2218 .port_vlan_filtering = rtl83xx_vlan_filtering,
2219 .port_vlan_prepare = rtl83xx_vlan_prepare,
2220 .port_vlan_add = rtl83xx_vlan_add,
2221 .port_vlan_del = rtl83xx_vlan_del,
2222
2223 .port_fdb_add = rtl83xx_port_fdb_add,
2224 .port_fdb_del = rtl83xx_port_fdb_del,
2225 .port_fdb_dump = rtl83xx_port_fdb_dump,
2226
2227 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2228 .port_mdb_add = rtl83xx_port_mdb_add,
2229 .port_mdb_del = rtl83xx_port_mdb_del,
2230
2231 .port_lag_change = rtl83xx_port_lag_change,
2232 .port_lag_join = rtl83xx_port_lag_join,
2233 .port_lag_leave = rtl83xx_port_lag_leave,
2234
2235 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2236 .port_bridge_flags = rtl83xx_port_bridge_flags,
2237 };
Staging tree of Christian Marangi