ramips: mt7620a: convert to nvmem-layout
[openwrt/staging/hauke.git] / target / linux / ramips / dts / mt7620a_wavlink_wl-wn530hg4.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 #include "mt7620a.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "wavlink,wl-wn530hg4", "ralink,mt7620a-soc";
10 model = "Wavlink WL-WN530HG4";
11
12 aliases {
13 led-boot = &led_status_blue;
14 led-failsafe = &led_status_blue;
15 led-running = &led_status_blue;
16 led-upgrade = &led_status_blue;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 led_status_blue: status_blue {
23 label = "blue:status";
24 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
25 };
26
27 status_yellow {
28 label = "yellow:status";
29 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
30 };
31
32 status_red {
33 label = "red:status";
34 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
35 };
36 };
37
38 keys {
39 compatible = "gpio-keys";
40
41 reset {
42 label = "reset";
43 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
44 linux,code = <KEY_RESTART>;
45 };
46 };
47 };
48
49 &spi0 {
50 status = "okay";
51
52 flash@0 {
53 compatible = "jedec,spi-nor";
54 reg = <0>;
55 spi-max-frequency = <24000000>;
56
57 partitions {
58 compatible = "fixed-partitions";
59 #address-cells = <1>;
60 #size-cells = <1>;
61
62 partition@0 {
63 label = "u-boot";
64 reg = <0x0 0x30000>;
65 read-only;
66 };
67
68 partition@30000 {
69 label = "config";
70 reg = <0x30000 0x10000>;
71 read-only;
72 };
73
74 factory: partition@40000 {
75 label = "factory";
76 reg = <0x40000 0x10000>;
77 read-only;
78
79 nvmem-layout {
80 compatible = "fixed-layout";
81 #address-cells = <1>;
82 #size-cells = <1>;
83
84 eeprom_factory_0: eeprom@0 {
85 reg = <0x0 0x200>;
86 };
87
88 eeprom_factory_8000: eeprom@8000 {
89 reg = <0x8000 0x200>;
90 };
91
92 macaddr_factory_28: macaddr@28 {
93 reg = <0x28 0x6>;
94 };
95 };
96 };
97
98 partition@50000 {
99 compatible = "denx,uimage";
100 label = "firmware";
101 reg = <0x50000 0x7b0000>;
102 };
103 };
104 };
105 };
106
107 &state_default {
108 gpio {
109 groups = "i2c", "uartf";
110 function = "gpio";
111 };
112 };
113
114 &ethernet {
115 pinctrl-names = "default";
116 pinctrl-0 = <&rgmii2_pins &mdio_pins>;
117
118 nvmem-cells = <&macaddr_factory_28>;
119 nvmem-cell-names = "mac-address";
120
121 mediatek,portmap = "llllw";
122
123 port@5 {
124 status = "okay";
125 phy-handle = <&phy5>;
126 phy-mode = "rgmii";
127 };
128
129 mdio-bus {
130 status = "okay";
131
132 phy5: ethernet-phy@5 {
133 reg = <5>;
134 phy-mode = "rgmii";
135 };
136 };
137 };
138
139 &pcie {
140 status = "okay";
141 };
142
143 &pcie0 {
144 mt76@0,0 {
145 reg = <0x0000 0 0 0 0>;
146 nvmem-cells = <&eeprom_factory_8000>;
147 nvmem-cell-names = "eeprom";
148 ieee80211-freq-limit = <5000000 6000000>;
149 };
150 };
151
152 &wmac {
153 pinctrl-names = "default", "pa_gpio";
154 pinctrl-0 = <&pa_pins>;
155 pinctrl-1 = <&pa_gpio_pins>;
156 nvmem-cells = <&eeprom_factory_0>;
157 nvmem-cell-names = "eeprom";
158 };