ramips: mt7620a: convert to nvmem-layout
[openwrt/staging/hauke.git] / target / linux / ramips / dts / mt7620a_linksys_e1700.dts
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
4 */
5
6 #include "mt7620a.dtsi"
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10
11 / {
12 compatible = "linksys,e1700", "ralink,mt7620a-soc";
13 model = "Linksys E1700";
14
15 aliases {
16 led-boot = &led_power;
17 led-failsafe = &led_power;
18 led-running = &led_power;
19 led-upgrade = &led_power;
20 };
21
22 keys {
23 compatible = "gpio-keys";
24
25 reset {
26 label = "reset";
27 gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
28 linux,code = <KEY_RESTART>;
29 };
30
31 wps {
32 label = "wps";
33 gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
34 linux,code = <KEY_WPS_BUTTON>;
35 };
36 };
37
38 leds {
39 compatible = "gpio-leds";
40
41 led_power: power {
42 label = "green:power";
43 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
44 };
45
46 wan {
47 label = "green:wps";
48 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
49 };
50 };
51 };
52
53 &spi0 {
54 status = "okay";
55
56 flash@0 {
57 compatible = "jedec,spi-nor";
58 reg = <0>;
59 spi-max-frequency = <10000000>;
60
61 partitions {
62 compatible = "fixed-partitions";
63 #address-cells = <1>;
64 #size-cells = <1>;
65
66 partition@0 {
67 label = "u-boot";
68 reg = <0x0 0x30000>;
69 read-only;
70 };
71
72 partition@30000 {
73 label = "config";
74 reg = <0x30000 0x10000>;
75 read-only;
76 };
77
78 factory: partition@40000 {
79 label = "factory";
80 reg = <0x40000 0x10000>;
81 read-only;
82
83 nvmem-layout {
84 compatible = "fixed-layout";
85 #address-cells = <1>;
86 #size-cells = <1>;
87
88 eeprom_factory_0: eeprom@0 {
89 reg = <0x0 0x200>;
90 };
91
92 macaddr_factory_28: macaddr@28 {
93 reg = <0x28 0x6>;
94 };
95 };
96 };
97
98 partition@50000 {
99 compatible = "denx,uimage";
100 label = "firmware";
101 reg = <0x50000 0x7b0000>;
102 };
103 };
104 };
105 };
106
107 &state_default {
108 gpio {
109 groups = "i2c", "uartf";
110 function = "gpio";
111 };
112 };
113
114 &ethernet {
115 pinctrl-names = "default";
116 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
117
118 nvmem-cells = <&macaddr_factory_28>;
119 nvmem-cell-names = "mac-address";
120
121 port@5 {
122 status = "okay";
123 mediatek,fixed-link = <1000 1 1 1>;
124 phy-mode = "rgmii";
125 };
126
127 mdio-bus {
128 status = "okay";
129
130 phy0: ethernet-phy@0 {
131 reg = <0>;
132 phy-mode = "rgmii";
133 };
134
135 phy1: ethernet-phy@1 {
136 reg = <1>;
137 phy-mode = "rgmii";
138 };
139
140 phy2: ethernet-phy@2 {
141 reg = <2>;
142 phy-mode = "rgmii";
143 };
144
145 phy3: ethernet-phy@3 {
146 reg = <3>;
147 phy-mode = "rgmii";
148 };
149
150 phy4: ethernet-phy@4 {
151 reg = <4>;
152 phy-mode = "rgmii";
153 };
154
155 phy1f: ethernet-phy@1f {
156 reg = <0x1f>;
157 phy-mode = "rgmii";
158 };
159 };
160 };
161
162 &gsw {
163 mediatek,ephy-base = /bits/ 8 <12>;
164 };
165
166 &wmac {
167 nvmem-cells = <&eeprom_factory_0>;
168 nvmem-cell-names = "eeprom";
169 };