target/linux/qualcommax/patches-6.6/0053-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch

   1 From 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Sat, 21 Oct 2023 13:55:18 +0200
   4 Subject: [PATCH] clk: qcom: gcc-ipq6018: add QUP6 I2C clock
   5
   6 QUP6 I2C clock is listed in the dt bindings but it was never included in
   7 the GCC driver.
   8 So lets add support for it, it is marked as criticial as it is used by RPM
   9 to communicate to the external PMIC over I2C so this clock must not be
  10 disabled.
  11
  12 Signed-off-by: Robert Marko <robimarko@gmail.com>
  13 Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
  14 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
  15 Link: https://lore.kernel.org/r/20231021115545.229060-1-robimarko@gmail.com
  16 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  17 ---
  18  drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++
  19  1 file changed, 21 insertions(+)
  20
  21 --- a/drivers/clk/qcom/gcc-ipq6018.c
  22 +++ b/drivers/clk/qcom/gcc-ipq6018.c
  23 @@ -2121,6 +2121,26 @@ static struct clk_branch gcc_blsp1_qup5_
  24         },
  25  };
  26
  27 +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
  28 +       .halt_reg = 0x07010,
  29 +       .clkr = {
  30 +               .enable_reg = 0x07010,
  31 +               .enable_mask = BIT(0),
  32 +               .hw.init = &(struct clk_init_data){
  33 +                       .name = "gcc_blsp1_qup6_i2c_apps_clk",
  34 +                       .parent_hws = (const struct clk_hw *[]){
  35 +                                       &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
  36 +                       .num_parents = 1,
  37 +                       /*
  38 +                        * RPM uses QUP6 I2C to communicate with the external
  39 +                        * PMIC so it must not be disabled.
  40 +                        */
  41 +                       .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
  42 +                       .ops = &clk_branch2_ops,
  43 +               },
  44 +       },
  45 +};
  46 +
  47  static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
  48         .halt_reg = 0x0700c,
  49         .clkr = {
  50 @@ -4277,6 +4297,7 @@ static struct clk_regmap *gcc_ipq6018_cl
  51         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
  52         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
  53         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
  54 +       [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
  55         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
  56         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
  57         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,