target/linux/mediatek/patches-6.6/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch

   1 From 6c83b2d94fcca735cf7d8aa7a55a4957eb404a9d Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Thu, 26 Jan 2023 00:34:56 +0000
   4 Subject: [PATCH] pinctrl: add mt7981 pinctrl driver
   5
   6 Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver
   7 which can also be found the SDK.
   8
   9 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  10 Reviewed-by: Rob Herring <robh@kernel.org>
  11 Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org
  12 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  13 ---
  14  drivers/pinctrl/mediatek/Kconfig          |    5 +
  15  drivers/pinctrl/mediatek/Makefile         |    1 +
  16  drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++++++++++++
  17  3 files changed, 1054 insertions(+)
  18  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c
  19
  20 --- a/drivers/pinctrl/mediatek/Kconfig
  21 +++ b/drivers/pinctrl/mediatek/Kconfig
  22 @@ -127,6 +127,11 @@ config PINCTRL_MT7622
  23         default ARM64 && ARCH_MEDIATEK
  24         select PINCTRL_MTK_MOORE
  25
  26 +config PINCTRL_MT7981
  27 +       bool "Mediatek MT7981 pin control"
  28 +       depends on OF
  29 +       select PINCTRL_MTK_MOORE
  30 +
  31  config PINCTRL_MT7986
  32         bool "Mediatek MT7986 pin control"
  33         depends on OF
  34 --- a/drivers/pinctrl/mediatek/Makefile
  35 +++ b/drivers/pinctrl/mediatek/Makefile
  36 @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797)  += pinctrl-
  37  obj-$(CONFIG_PINCTRL_MT7622)   += pinctrl-mt7622.o
  38  obj-$(CONFIG_PINCTRL_MT7623)   += pinctrl-mt7623.o
  39  obj-$(CONFIG_PINCTRL_MT7629)   += pinctrl-mt7629.o
  40 +obj-$(CONFIG_PINCTRL_MT7981)   += pinctrl-mt7981.o
  41  obj-$(CONFIG_PINCTRL_MT7986)   += pinctrl-mt7986.o
  42  obj-$(CONFIG_PINCTRL_MT8167)   += pinctrl-mt8167.o
  43  obj-$(CONFIG_PINCTRL_MT8173)   += pinctrl-mt8173.o
  44 --- /dev/null
  45 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
  46 @@ -0,0 +1,1048 @@
  47 +// SPDX-License-Identifier: GPL-2.0
  48 +/*
  49 + * The MT7981 driver based on Linux generic pinctrl binding.
  50 + *
  51 + * Copyright (C) 2020 MediaTek Inc.
  52 + * Author: Sam Shih <sam.shih@mediatek.com>
  53 + */
  54 +
  55 +#include "pinctrl-moore.h"
  56 +
  57 +#define MT7981_PIN(_number, _name)                             \
  58 +       MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
  59 +
  60 +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)    \
  61 +       PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,      \
  62 +                      _x_bits, 32, 0)
  63 +
  64 +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits)   \
  65 +       PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,      \
  66 +                     _x_bits, 32, 1)
  67 +
  68 +static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = {
  69 +       PIN_FIELD(0, 56, 0x300, 0x10, 0, 4),
  70 +};
  71 +
  72 +static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = {
  73 +       PIN_FIELD(0, 56, 0x0, 0x10, 0, 1),
  74 +};
  75 +
  76 +static const struct mtk_pin_field_calc mt7981_pin_di_range[] = {
  77 +       PIN_FIELD(0, 56, 0x200, 0x10, 0, 1),
  78 +};
  79 +
  80 +static const struct mtk_pin_field_calc mt7981_pin_do_range[] = {
  81 +       PIN_FIELD(0, 56, 0x100, 0x10, 0, 1),
  82 +};
  83 +
  84 +static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = {
  85 +       PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1),
  86 +       PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1),
  87 +       PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
  88 +       PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
  89 +       PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
  90 +       PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
  91 +       PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
  92 +       PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
  93 +       PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
  94 +
  95 +       PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
  96 +       PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
  97 +       PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
  98 +       PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1),
  99 +       PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1),
 100 +
 101 +       PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1),
 102 +
 103 +       PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1),
 104 +       PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1),
 105 +       PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1),
 106 +       PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1),
 107 +       PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1),
 108 +       PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1),
 109 +       PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1),
 110 +       PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1),
 111 +       PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1),
 112 +       PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1),
 113 +       PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1),
 114 +
 115 +       PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1),
 116 +       PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1),
 117 +       PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1),
 118 +       PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1),
 119 +       PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1),
 120 +       PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1),
 121 +
 122 +       PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1),
 123 +       PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1),
 124 +
 125 +       PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1),
 126 +       PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1),
 127 +
 128 +       PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1),
 129 +       PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1),
 130 +       PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1),
 131 +       PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1),
 132 +
 133 +       PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1),
 134 +       PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1),
 135 +       PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1),
 136 +       PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1),
 137 +       PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
 138 +       PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1),
 139 +       PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1),
 140 +       PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1),
 141 +       PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1),
 142 +       PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1),
 143 +
 144 +       PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1),
 145 +       PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1),
 146 +       PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1),
 147 +       PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1),
 148 +       PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1),
 149 +       PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1),
 150 +       PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1),
 151 +};
 152 +
 153 +static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = {
 154 +       PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1),
 155 +       PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1),
 156 +       PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1),
 157 +       PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1),
 158 +       PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1),
 159 +       PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1),
 160 +       PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1),
 161 +       PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1),
 162 +       PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1),
 163 +
 164 +       PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1),
 165 +       PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1),
 166 +       PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1),
 167 +       PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1),
 168 +       PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1),
 169 +
 170 +       PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1),
 171 +
 172 +       PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1),
 173 +       PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1),
 174 +       PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1),
 175 +       PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1),
 176 +       PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1),
 177 +       PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
 178 +       PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1),
 179 +       PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1),
 180 +       PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1),
 181 +       PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1),
 182 +       PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1),
 183 +
 184 +       PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1),
 185 +       PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1),
 186 +       PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1),
 187 +       PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1),
 188 +       PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1),
 189 +       PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1),
 190 +
 191 +       PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1),
 192 +       PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1),
 193 +
 194 +       PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1),
 195 +       PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1),
 196 +
 197 +       PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1),
 198 +       PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1),
 199 +       PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1),
 200 +       PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1),
 201 +
 202 +       PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1),
 203 +       PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1),
 204 +       PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1),
 205 +       PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1),
 206 +       PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1),
 207 +       PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1),
 208 +       PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1),
 209 +       PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1),
 210 +       PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1),
 211 +       PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1),
 212 +
 213 +       PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1),
 214 +       PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1),
 215 +       PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1),
 216 +       PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1),
 217 +       PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1),
 218 +       PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1),
 219 +       PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1),
 220 +};
 221 +
 222 +static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = {
 223 +       PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1),
 224 +       PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1),
 225 +       PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1),
 226 +       PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1),
 227 +       PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1),
 228 +       PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1),
 229 +       PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1),
 230 +       PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1),
 231 +       PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1),
 232 +       PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1),
 233 +
 234 +       PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1),
 235 +       PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1),
 236 +       PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1),
 237 +       PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1),
 238 +       PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1),
 239 +       PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1),
 240 +       PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1),
 241 +};
 242 +
 243 +static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = {
 244 +       PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1),
 245 +       PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1),
 246 +       PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1),
 247 +       PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1),
 248 +       PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1),
 249 +       PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1),
 250 +       PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1),
 251 +       PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1),
 252 +       PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1),
 253 +       PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1),
 254 +
 255 +       PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1),
 256 +       PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1),
 257 +       PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1),
 258 +       PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1),
 259 +       PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1),
 260 +       PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1),
 261 +       PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1),
 262 +};
 263 +
 264 +static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = {
 265 +       PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3),
 266 +       PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3),
 267 +
 268 +       PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3),
 269 +
 270 +       PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1),
 271 +       PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1),
 272 +       PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3),
 273 +       PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3),
 274 +       PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3),
 275 +       PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3),
 276 +
 277 +       PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3),
 278 +       PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3),
 279 +       PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3),
 280 +       PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3),
 281 +       PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3),
 282 +
 283 +       PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3),
 284 +
 285 +       PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3),
 286 +       PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3),
 287 +       PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3),
 288 +       PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3),
 289 +       PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3),
 290 +       PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3),
 291 +       PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3),
 292 +       PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3),
 293 +       PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3),
 294 +       PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3),
 295 +       PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3),
 296 +
 297 +       PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3),
 298 +       PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3),
 299 +       PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3),
 300 +       PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3),
 301 +       PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3),
 302 +       PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3),
 303 +
 304 +       PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3),
 305 +       PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3),
 306 +
 307 +       PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3),
 308 +       PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3),
 309 +
 310 +       PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3),
 311 +       PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3),
 312 +       PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3),
 313 +       PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3),
 314 +
 315 +       PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3),
 316 +       PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3),
 317 +       PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3),
 318 +       PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3),
 319 +       PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3),
 320 +       PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3),
 321 +       PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3),
 322 +       PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3),
 323 +       PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3),
 324 +       PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3),
 325 +
 326 +       PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3),
 327 +       PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3),
 328 +       PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3),
 329 +       PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3),
 330 +       PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3),
 331 +       PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3),
 332 +       PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3),
 333 +};
 334 +
 335 +static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = {
 336 +       PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1),
 337 +       PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1),
 338 +       PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1),
 339 +       PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1),
 340 +       PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1),
 341 +       PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1),
 342 +       PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1),
 343 +       PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1),
 344 +       PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1),
 345 +
 346 +       PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1),
 347 +       PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1),
 348 +       PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1),
 349 +       PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1),
 350 +       PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1),
 351 +
 352 +       PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1),
 353 +
 354 +       PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1),
 355 +       PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1),
 356 +       PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1),
 357 +       PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1),
 358 +       PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1),
 359 +       PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1),
 360 +       PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1),
 361 +       PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1),
 362 +       PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1),
 363 +       PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1),
 364 +       PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1),
 365 +
 366 +       PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1),
 367 +       PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1),
 368 +       PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1),
 369 +       PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1),
 370 +       PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1),
 371 +       PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1),
 372 +
 373 +       PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1),
 374 +       PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1),
 375 +
 376 +       PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1),
 377 +       PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1),
 378 +
 379 +       PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1),
 380 +       PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1),
 381 +       PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1),
 382 +       PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1),
 383 +};
 384 +
 385 +static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = {
 386 +       PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1),
 387 +       PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1),
 388 +       PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1),
 389 +       PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1),
 390 +       PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1),
 391 +       PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1),
 392 +       PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1),
 393 +       PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1),
 394 +       PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
 395 +
 396 +       PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1),
 397 +       PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1),
 398 +       PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1),
 399 +       PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1),
 400 +       PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1),
 401 +
 402 +       PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1),
 403 +
 404 +       PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1),
 405 +       PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1),
 406 +       PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1),
 407 +       PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1),
 408 +       PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1),
 409 +       PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1),
 410 +       PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1),
 411 +       PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1),
 412 +       PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1),
 413 +       PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1),
 414 +       PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1),
 415 +
 416 +       PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1),
 417 +       PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1),
 418 +       PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1),
 419 +       PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1),
 420 +       PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1),
 421 +       PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1),
 422 +
 423 +       PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1),
 424 +       PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1),
 425 +
 426 +       PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1),
 427 +       PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1),
 428 +
 429 +       PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1),
 430 +       PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1),
 431 +       PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1),
 432 +       PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1),
 433 +};
 434 +
 435 +static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
 436 +       PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1),
 437 +       PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1),
 438 +       PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1),
 439 +       PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1),
 440 +       PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1),
 441 +       PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1),
 442 +       PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1),
 443 +       PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1),
 444 +       PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1),
 445 +
 446 +       PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1),
 447 +       PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1),
 448 +       PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1),
 449 +       PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1),
 450 +       PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1),
 451 +
 452 +       PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1),
 453 +
 454 +       PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1),
 455 +       PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1),
 456 +       PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1),
 457 +       PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1),
 458 +       PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1),
 459 +       PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1),
 460 +       PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1),
 461 +       PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1),
 462 +       PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1),
 463 +       PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1),
 464 +       PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1),
 465 +
 466 +       PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1),
 467 +       PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1),
 468 +       PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1),
 469 +       PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1),
 470 +       PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1),
 471 +       PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1),
 472 +
 473 +       PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1),
 474 +       PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1),
 475 +
 476 +       PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1),
 477 +       PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1),
 478 +
 479 +       PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1),
 480 +       PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1),
 481 +       PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1),
 482 +       PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
 483 +};
 484 +
 485 +static const unsigned int mt7981_pull_type[] = {
 486 +       MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
 487 +       MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
 488 +       MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
 489 +       MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
 490 +       MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
 491 +       MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
 492 +       MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
 493 +       MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
 494 +       MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
 495 +       MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
 496 +       MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
 497 +       MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
 498 +       MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
 499 +       MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
 500 +       MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
 501 +       MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
 502 +       MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/
 503 +       MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/
 504 +       MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/
 505 +       MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
 506 +       MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
 507 +       MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
 508 +       MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
 509 +       MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
 510 +       MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
 511 +       MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/
 512 +       MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/
 513 +       MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/
 514 +       MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/
 515 +       MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/
 516 +       MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/
 517 +       MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/
 518 +       MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/
 519 +       MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/
 520 +       MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/
 521 +       MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/
 522 +       MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/
 523 +       MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/
 524 +       MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/
 525 +       MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/
 526 +       MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/
 527 +       MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/
 528 +       MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/
 529 +       MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/
 530 +       MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/
 531 +       MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/
 532 +       MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/
 533 +       MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/
 534 +       MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/
 535 +       MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/
 536 +       MTK_PULL_PU_PD_TYPE,/*100*/
 537 +};
 538 +
 539 +static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
 540 +       [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
 541 +       [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
 542 +       [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
 543 +       [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range),
 544 +       [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range),
 545 +       [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range),
 546 +       [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range),
 547 +       [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range),
 548 +       [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range),
 549 +       [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range),
 550 +       [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range),
 551 +       [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range),
 552 +};
 553 +
 554 +static const struct mtk_pin_desc mt7981_pins[] = {
 555 +       MT7981_PIN(0, "GPIO_WPS"),
 556 +       MT7981_PIN(1, "GPIO_RESET"),
 557 +       MT7981_PIN(2, "SYS_WATCHDOG"),
 558 +       MT7981_PIN(3, "PCIE_PERESET_N"),
 559 +       MT7981_PIN(4, "JTAG_JTDO"),
 560 +       MT7981_PIN(5, "JTAG_JTDI"),
 561 +       MT7981_PIN(6, "JTAG_JTMS"),
 562 +       MT7981_PIN(7, "JTAG_JTCLK"),
 563 +       MT7981_PIN(8, "JTAG_JTRST_N"),
 564 +       MT7981_PIN(9, "WO_JTAG_JTDO"),
 565 +       MT7981_PIN(10, "WO_JTAG_JTDI"),
 566 +       MT7981_PIN(11, "WO_JTAG_JTMS"),
 567 +       MT7981_PIN(12, "WO_JTAG_JTCLK"),
 568 +       MT7981_PIN(13, "WO_JTAG_JTRST_N"),
 569 +       MT7981_PIN(14, "USB_VBUS"),
 570 +       MT7981_PIN(15, "PWM0"),
 571 +       MT7981_PIN(16, "SPI0_CLK"),
 572 +       MT7981_PIN(17, "SPI0_MOSI"),
 573 +       MT7981_PIN(18, "SPI0_MISO"),
 574 +       MT7981_PIN(19, "SPI0_CS"),
 575 +       MT7981_PIN(20, "SPI0_HOLD"),
 576 +       MT7981_PIN(21, "SPI0_WP"),
 577 +       MT7981_PIN(22, "SPI1_CLK"),
 578 +       MT7981_PIN(23, "SPI1_MOSI"),
 579 +       MT7981_PIN(24, "SPI1_MISO"),
 580 +       MT7981_PIN(25, "SPI1_CS"),
 581 +       MT7981_PIN(26, "SPI2_CLK"),
 582 +       MT7981_PIN(27, "SPI2_MOSI"),
 583 +       MT7981_PIN(28, "SPI2_MISO"),
 584 +       MT7981_PIN(29, "SPI2_CS"),
 585 +       MT7981_PIN(30, "SPI2_HOLD"),
 586 +       MT7981_PIN(31, "SPI2_WP"),
 587 +       MT7981_PIN(32, "UART0_RXD"),
 588 +       MT7981_PIN(33, "UART0_TXD"),
 589 +       MT7981_PIN(34, "PCIE_CLK_REQ"),
 590 +       MT7981_PIN(35, "PCIE_WAKE_N"),
 591 +       MT7981_PIN(36, "SMI_MDC"),
 592 +       MT7981_PIN(37, "SMI_MDIO"),
 593 +       MT7981_PIN(38, "GBE_INT"),
 594 +       MT7981_PIN(39, "GBE_RESET"),
 595 +       MT7981_PIN(40, "WF_DIG_RESETB"),
 596 +       MT7981_PIN(41, "WF_CBA_RESETB"),
 597 +       MT7981_PIN(42, "WF_XO_REQ"),
 598 +       MT7981_PIN(43, "WF_TOP_CLK"),
 599 +       MT7981_PIN(44, "WF_TOP_DATA"),
 600 +       MT7981_PIN(45, "WF_HB1"),
 601 +       MT7981_PIN(46, "WF_HB2"),
 602 +       MT7981_PIN(47, "WF_HB3"),
 603 +       MT7981_PIN(48, "WF_HB4"),
 604 +       MT7981_PIN(49, "WF_HB0"),
 605 +       MT7981_PIN(50, "WF_HB0_B"),
 606 +       MT7981_PIN(51, "WF_HB5"),
 607 +       MT7981_PIN(52, "WF_HB6"),
 608 +       MT7981_PIN(53, "WF_HB7"),
 609 +       MT7981_PIN(54, "WF_HB8"),
 610 +       MT7981_PIN(55, "WF_HB9"),
 611 +       MT7981_PIN(56, "WF_HB10"),
 612 +};
 613 +
 614 +/* List all groups consisting of these pins dedicated to the enablement of
 615 + * certain hardware block and the corresponding mode for all of the pins.
 616 + * The hardware probably has multiple combinations of these pinouts.
 617 + */
 618 +
 619 +/* WA_AICE */
 620 +static int mt7981_wa_aice1_pins[] = { 0, 1, };
 621 +static int mt7981_wa_aice1_funcs[] = { 2, 2, };
 622 +
 623 +static int mt7981_wa_aice2_pins[] = { 0, 1, };
 624 +static int mt7981_wa_aice2_funcs[] = { 3, 3, };
 625 +
 626 +static int mt7981_wa_aice3_pins[] = { 28, 29, };
 627 +static int mt7981_wa_aice3_funcs[] = { 3, 3, };
 628 +
 629 +static int mt7981_wm_aice1_pins[] = { 9, 10, };
 630 +static int mt7981_wm_aice1_funcs[] = { 2, 2, };
 631 +
 632 +static int mt7981_wm_aice2_pins[] = { 30, 31, };
 633 +static int mt7981_wm_aice2_funcs[] = { 5, 5, };
 634 +
 635 +/* WM_UART */
 636 +static int mt7981_wm_uart_0_pins[] = { 0, 1, };
 637 +static int mt7981_wm_uart_0_funcs[] = { 5, 5, };
 638 +
 639 +static int mt7981_wm_uart_1_pins[] = { 20, 21, };
 640 +static int mt7981_wm_uart_1_funcs[] = { 4, 4, };
 641 +
 642 +static int mt7981_wm_uart_2_pins[] = { 30, 31, };
 643 +static int mt7981_wm_uart_2_funcs[] = { 3, 3, };
 644 +
 645 +/* DFD */
 646 +static int mt7981_dfd_pins[] = { 0, 1, 4, 5, };
 647 +static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, };
 648 +
 649 +/* SYS_WATCHDOG */
 650 +static int mt7981_watchdog_pins[] = { 2, };
 651 +static int mt7981_watchdog_funcs[] = { 1, };
 652 +
 653 +static int mt7981_watchdog1_pins[] = { 13, };
 654 +static int mt7981_watchdog1_funcs[] = { 5, };
 655 +
 656 +/* PCIE_PERESET_N */
 657 +static int mt7981_pcie_pereset_pins[] = { 3, };
 658 +static int mt7981_pcie_pereset_funcs[] = { 1, };
 659 +
 660 +/* JTAG */
 661 +static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, };
 662 +static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, };
 663 +
 664 +/* WM_JTAG */
 665 +static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, };
 666 +static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, };
 667 +
 668 +static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, };
 669 +static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
 670 +
 671 +/* WO0_JTAG */
 672 +static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, };
 673 +static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, };
 674 +
 675 +static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, };
 676 +static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, };
 677 +
 678 +/* UART2 */
 679 +static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
 680 +static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
 681 +
 682 +/* GBE_LED0 */
 683 +static int mt7981_gbe_led0_pins[] = { 8, };
 684 +static int mt7981_gbe_led0_funcs[] = { 3, };
 685 +
 686 +/* PTA_EXT */
 687 +static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, };
 688 +static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, };
 689 +
 690 +static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, };
 691 +static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, };
 692 +
 693 +/* PWM2 */
 694 +static int mt7981_pwm2_pins[] = { 7, };
 695 +static int mt7981_pwm2_funcs[] = { 4, };
 696 +
 697 +/* NET_WO0_UART_TXD */
 698 +static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, };
 699 +static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, };
 700 +
 701 +static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, };
 702 +static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, };
 703 +
 704 +static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, };
 705 +static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, };
 706 +
 707 +/* SPI1 */
 708 +static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, };
 709 +static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, };
 710 +
 711 +/* I2C */
 712 +static int mt7981_i2c0_0_pins[] = { 6, 7, };
 713 +static int mt7981_i2c0_0_funcs[] = { 6, 6, };
 714 +
 715 +static int mt7981_i2c0_1_pins[] = { 30, 31, };
 716 +static int mt7981_i2c0_1_funcs[] = { 4, 4, };
 717 +
 718 +static int mt7981_i2c0_2_pins[] = { 36, 37, };
 719 +static int mt7981_i2c0_2_funcs[] = { 2, 2, };
 720 +
 721 +static int mt7981_u2_phy_i2c_pins[] = { 30, 31, };
 722 +static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, };
 723 +
 724 +static int mt7981_u3_phy_i2c_pins[] = { 32, 33, };
 725 +static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, };
 726 +
 727 +static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, };
 728 +static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, };
 729 +
 730 +static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, };
 731 +static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, };
 732 +
 733 +/* DFD_NTRST */
 734 +static int mt7981_dfd_ntrst_pins[] = { 8, };
 735 +static int mt7981_dfd_ntrst_funcs[] = { 6, };
 736 +
 737 +/* PWM0 */
 738 +static int mt7981_pwm0_0_pins[] = { 13, };
 739 +static int mt7981_pwm0_0_funcs[] = { 2, };
 740 +
 741 +static int mt7981_pwm0_1_pins[] = { 15, };
 742 +static int mt7981_pwm0_1_funcs[] = { 1, };
 743 +
 744 +/* PWM1 */
 745 +static int mt7981_pwm1_0_pins[] = { 14, };
 746 +static int mt7981_pwm1_0_funcs[] = { 2, };
 747 +
 748 +static int mt7981_pwm1_1_pins[] = { 15, };
 749 +static int mt7981_pwm1_1_funcs[] = { 3, };
 750 +
 751 +/* GBE_LED1 */
 752 +static int mt7981_gbe_led1_pins[] = { 13, };
 753 +static int mt7981_gbe_led1_funcs[] = { 3, };
 754 +
 755 +/* PCM */
 756 +static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 };
 757 +static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, };
 758 +
 759 +/* UDI */
 760 +static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, };
 761 +static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, };
 762 +
 763 +/* DRV_VBUS */
 764 +static int mt7981_drv_vbus_pins[] = { 14, };
 765 +static int mt7981_drv_vbus_funcs[] = { 1, };
 766 +
 767 +/* EMMC */
 768 +static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
 769 +static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
 770 +
 771 +/* SNFI */
 772 +static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, };
 773 +static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, };
 774 +
 775 +/* SPI0 */
 776 +static int mt7981_spi0_pins[] = { 16, 17, 18, 19, };
 777 +static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, };
 778 +
 779 +/* SPI0 */
 780 +static int mt7981_spi0_wp_hold_pins[] = { 20, 21, };
 781 +static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, };
 782 +
 783 +/* SPI1 */
 784 +static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, };
 785 +static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, };
 786 +
 787 +/* SPI2 */
 788 +static int mt7981_spi2_pins[] = { 26, 27, 28, 29, };
 789 +static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, };
 790 +
 791 +/* SPI2 */
 792 +static int mt7981_spi2_wp_hold_pins[] = { 30, 31, };
 793 +static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, };
 794 +
 795 +/* UART1 */
 796 +static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, };
 797 +static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, };
 798 +
 799 +static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
 800 +static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
 801 +
 802 +/* UART2 */
 803 +static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
 804 +static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
 805 +
 806 +/* UART0 */
 807 +static int mt7981_uart0_pins[] = { 32, 33, };
 808 +static int mt7981_uart0_funcs[] = { 1, 1, };
 809 +
 810 +/* PCIE_CLK_REQ */
 811 +static int mt7981_pcie_clk_pins[] = { 34, };
 812 +static int mt7981_pcie_clk_funcs[] = { 2, };
 813 +
 814 +/* PCIE_WAKE_N */
 815 +static int mt7981_pcie_wake_pins[] = { 35, };
 816 +static int mt7981_pcie_wake_funcs[] = { 2, };
 817 +
 818 +/* MDC_MDIO */
 819 +static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, };
 820 +static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, };
 821 +
 822 +static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, };
 823 +static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, };
 824 +
 825 +/* WF0_MODE1 */
 826 +static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 };
 827 +static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 828 +
 829 +/* WF0_MODE3 */
 830 +static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 };
 831 +static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 };
 832 +
 833 +/* WF2G_LED */
 834 +static int mt7981_wf2g_led0_pins[] = { 30, };
 835 +static int mt7981_wf2g_led0_funcs[] = { 2, };
 836 +
 837 +static int mt7981_wf2g_led1_pins[] = { 34, };
 838 +static int mt7981_wf2g_led1_funcs[] = { 1, };
 839 +
 840 +/* WF5G_LED */
 841 +static int mt7981_wf5g_led0_pins[] = { 31, };
 842 +static int mt7981_wf5g_led0_funcs[] = { 2, };
 843 +
 844 +static int mt7981_wf5g_led1_pins[] = { 35, };
 845 +static int mt7981_wf5g_led1_funcs[] = { 1, };
 846 +
 847 +/* MT7531_INT */
 848 +static int mt7981_mt7531_int_pins[] = { 38, };
 849 +static int mt7981_mt7531_int_funcs[] = { 1, };
 850 +
 851 +/* ANT_SEL */
 852 +static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 };
 853 +static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 };
 854 +
 855 +static const struct group_desc mt7981_groups[] = {
 856 +       /* @GPIO(0,1): WA_AICE(2) */
 857 +       PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1),
 858 +       /* @GPIO(0,1): WA_AICE(3) */
 859 +       PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2),
 860 +       /* @GPIO(0,1): WM_UART(5) */
 861 +       PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0),
 862 +       /* @GPIO(0,1,4,5): DFD(6) */
 863 +       PINCTRL_PIN_GROUP("dfd", mt7981_dfd),
 864 +       /* @GPIO(2): SYS_WATCHDOG(1) */
 865 +       PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog),
 866 +       /* @GPIO(3): PCIE_PERESET_N(1) */
 867 +       PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset),
 868 +       /* @GPIO(4,8) JTAG(1) */
 869 +       PINCTRL_PIN_GROUP("jtag", mt7981_jtag),
 870 +       /* @GPIO(4,8) WM_JTAG(2) */
 871 +       PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0),
 872 +       /* @GPIO(9,13) WO0_JTAG(1) */
 873 +       PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
 874 +       /* @GPIO(4,7) WM_JTAG(3) */
 875 +       PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
 876 +       /* @GPIO(8) GBE_LED0(3) */
 877 +       PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
 878 +       /* @GPIO(4,6) PTA_EXT(4) */
 879 +       PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0),
 880 +       /* @GPIO(7) PWM2(4) */
 881 +       PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2),
 882 +       /* @GPIO(8) NET_WO0_UART_TXD(4) */
 883 +       PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0),
 884 +       /* @GPIO(4,7) SPI1(5) */
 885 +       PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0),
 886 +       /* @GPIO(6,7) I2C(5) */
 887 +       PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0),
 888 +       /* @GPIO(0,1,4,5): DFD_NTRST(6) */
 889 +       PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst),
 890 +       /* @GPIO(9,10): WM_AICE(2) */
 891 +       PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1),
 892 +       /* @GPIO(13): PWM0(2) */
 893 +       PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0),
 894 +       /* @GPIO(15): PWM0(1) */
 895 +       PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1),
 896 +       /* @GPIO(14): PWM1(2) */
 897 +       PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0),
 898 +       /* @GPIO(15): PWM1(3) */
 899 +       PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1),
 900 +       /* @GPIO(14) NET_WO0_UART_TXD(3) */
 901 +       PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1),
 902 +       /* @GPIO(15) NET_WO0_UART_TXD(4) */
 903 +       PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2),
 904 +       /* @GPIO(13) GBE_LED0(3) */
 905 +       PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1),
 906 +       /* @GPIO(9,13) PCM(4) */
 907 +       PINCTRL_PIN_GROUP("pcm", mt7981_pcm),
 908 +       /* @GPIO(13): SYS_WATCHDOG1(5) */
 909 +       PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1),
 910 +       /* @GPIO(9,13) UDI(4) */
 911 +       PINCTRL_PIN_GROUP("udi", mt7981_udi),
 912 +       /* @GPIO(14) DRV_VBUS(1) */
 913 +       PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
 914 +       /* @GPIO(15,25): EMMC(2) */
 915 +       PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
 916 +       /* @GPIO(16,21): SNFI(3) */
 917 +       PINCTRL_PIN_GROUP("snfi", mt7981_snfi),
 918 +       /* @GPIO(16,19): SPI0(1) */
 919 +       PINCTRL_PIN_GROUP("spi0", mt7981_spi0),
 920 +       /* @GPIO(20,21): SPI0(1) */
 921 +       PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold),
 922 +       /* @GPIO(22,25) SPI1(1) */
 923 +       PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1),
 924 +       /* @GPIO(26,29): SPI2(1) */
 925 +       PINCTRL_PIN_GROUP("spi2", mt7981_spi2),
 926 +       /* @GPIO(30,31): SPI0(1) */
 927 +       PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold),
 928 +       /* @GPIO(16,19): UART1(4) */
 929 +       PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
 930 +       /* @GPIO(26,29): UART1(2) */
 931 +       PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
 932 +       /* @GPIO(22,25): UART1(3) */
 933 +       PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
 934 +       /* @GPIO(22,24) PTA_EXT(4) */
 935 +       PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1),
 936 +       /* @GPIO(20,21): WM_UART(4) */
 937 +       PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1),
 938 +       /* @GPIO(30,31): WM_UART(3) */
 939 +       PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2),
 940 +       /* @GPIO(20,24) WM_JTAG(5) */
 941 +       PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1),
 942 +       /* @GPIO(25,29) WO0_JTAG(5) */
 943 +       PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1),
 944 +       /* @GPIO(28,29): WA_AICE(3) */
 945 +       PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3),
 946 +       /* @GPIO(30,31): WM_AICE(5) */
 947 +       PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2),
 948 +       /* @GPIO(30,31): I2C(4) */
 949 +       PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1),
 950 +       /* @GPIO(30,31): I2C(6) */
 951 +       PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c),
 952 +       /* @GPIO(32,33): I2C(1) */
 953 +       PINCTRL_PIN_GROUP("uart0", mt7981_uart0),
 954 +       /* @GPIO(32,33): I2C(2) */
 955 +       PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c),
 956 +       /* @GPIO(32,33): I2C(3) */
 957 +       PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c),
 958 +       /* @GPIO(32,33): I2C(5) */
 959 +       PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c),
 960 +       /* @GPIO(34): PCIE_CLK_REQ(2) */
 961 +       PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk),
 962 +       /* @GPIO(35): PCIE_WAKE_N(2) */
 963 +       PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake),
 964 +       /* @GPIO(36,37): I2C(2) */
 965 +       PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2),
 966 +       /* @GPIO(36,37): MDC_MDIO(1) */
 967 +       PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio),
 968 +       /* @GPIO(36,37): MDC_MDIO(3) */
 969 +       PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio),
 970 +       /* @GPIO(69,85): WF0_MODE1(1) */
 971 +       PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1),
 972 +       /* @GPIO(74,80): WF0_MODE3(3) */
 973 +       PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3),
 974 +       /* @GPIO(30): WF2G_LED(2) */
 975 +       PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0),
 976 +       /* @GPIO(34): WF2G_LED(1) */
 977 +       PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1),
 978 +       /* @GPIO(31): WF5G_LED(2) */
 979 +       PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0),
 980 +       /* @GPIO(35): WF5G_LED(1) */
 981 +       PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1),
 982 +       /* @GPIO(38): MT7531_INT(1) */
 983 +       PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int),
 984 +       /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */
 985 +       PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel),
 986 +};
 987 +
 988 +/* Joint those groups owning the same capability in user point of view which
 989 + * allows that people tend to use through the device tree.
 990 + */
 991 +static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
 992 +       "wa_aice3", "wm_aice1_2", };
 993 +static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
 994 +       "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
 995 +       "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
 996 +static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
 997 +static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
 998 +static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
 999 +static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0",
1000 +       "wo0_jtag_1", "wm_jtag_1", };
1001 +static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0",
1002 +       "wf2g_led1", "wf5g_led0", "wf5g_led1", };
1003 +static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", };
1004 +static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1",
1005 +       "pwm1_0", "pwm1_1", };
1006 +static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2",
1007 +       "spi2_wp_hold", };
1008 +static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c",
1009 +       "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", };
1010 +static const char *mt7981_pcm_groups[] = { "pcm", };
1011 +static const char *mt7981_udi_groups[] = { "udi", };
1012 +static const char *mt7981_usb_groups[] = { "drv_vbus", };
1013 +static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
1014 +static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
1015 +       "wf0_mode1", "wf0_mode3", "mt7531_int", };
1016 +static const char *mt7981_ant_groups[] = { "ant_sel", };
1017 +
1018 +static const struct function_desc mt7981_functions[] = {
1019 +       {"wa_aice",     mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)},
1020 +       {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)},
1021 +       {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)},
1022 +       {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)},
1023 +       {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)},
1024 +       {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)},
1025 +       {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)},
1026 +       {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)},
1027 +       {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)},
1028 +       {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)},
1029 +       {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)},
1030 +       {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)},
1031 +       {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)},
1032 +       {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)},
1033 +       {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)},
1034 +       {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)},
1035 +       {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)},
1036 +};
1037 +
1038 +static const struct mtk_eint_hw mt7981_eint_hw = {
1039 +       .port_mask = 7,
1040 +       .ports     = 7,
1041 +       .ap_num    = ARRAY_SIZE(mt7981_pins),
1042 +       .db_cnt    = 16,
1043 +};
1044 +
1045 +static const char * const mt7981_pinctrl_register_base_names[] = {
1046 +       "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb",
1047 +       "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl",
1048 +};
1049 +
1050 +static struct mtk_pin_soc mt7981_data = {
1051 +       .reg_cal = mt7981_reg_cals,
1052 +       .pins = mt7981_pins,
1053 +       .npins = ARRAY_SIZE(mt7981_pins),
1054 +       .grps = mt7981_groups,
1055 +       .ngrps = ARRAY_SIZE(mt7981_groups),
1056 +       .funcs = mt7981_functions,
1057 +       .nfuncs = ARRAY_SIZE(mt7981_functions),
1058 +       .eint_hw = &mt7981_eint_hw,
1059 +       .gpio_m = 0,
1060 +       .ies_present = false,
1061 +       .base_names = mt7981_pinctrl_register_base_names,
1062 +       .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names),
1063 +       .pull_type = mt7981_pull_type,
1064 +       .bias_set_combo = mtk_pinconf_bias_set_combo,
1065 +       .bias_get_combo = mtk_pinconf_bias_get_combo,
1066 +       .drive_set = mtk_pinconf_drive_set_rev1,
1067 +       .drive_get = mtk_pinconf_drive_get_rev1,
1068 +       .adv_pull_get = mtk_pinconf_adv_pull_get,
1069 +       .adv_pull_set = mtk_pinconf_adv_pull_set,
1070 +};
1071 +
1072 +static const struct of_device_id mt7981_pinctrl_of_match[] = {
1073 +       { .compatible = "mediatek,mt7981-pinctrl", },
1074 +       {}
1075 +};
1076 +
1077 +static int mt7981_pinctrl_probe(struct platform_device *pdev)
1078 +{
1079 +       return mtk_moore_pinctrl_probe(pdev, &mt7981_data);
1080 +}
1081 +
1082 +static struct platform_driver mt7981_pinctrl_driver = {
1083 +       .driver = {
1084 +               .name = "mt7981-pinctrl",
1085 +               .of_match_table = mt7981_pinctrl_of_match,
1086 +       },
1087 +       .probe = mt7981_pinctrl_probe,
1088 +};
1089 +
1090 +static int __init mt7981_pinctrl_init(void)
1091 +{
1092 +       return platform_driver_register(&mt7981_pinctrl_driver);
1093 +}
1094 +arch_initcall(mt7981_pinctrl_init);