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c96444db57077fa242ef7560af5153012f648d72
[openwrt/staging/jow.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7981.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 * Author: Jianhui Zhao <zhaojh329@gmail.com>
6 */
7
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
12 #include <dt-bindings/reset/mt7986-resets.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/input/linux-event-codes.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/mux/mux.h>
18
19 / {
20 compatible = "mediatek,mt7981";
21 interrupt-parent = <&gic>;
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a53";
32 enable-method = "psci";
33 reg = <0x0>;
34 };
35
36 cpu@1 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a53";
39 enable-method = "psci";
40 reg = <0x1>;
41 };
42 };
43
44 ice: ice_debug {
45 compatible = "mediatek,mt7981-ice_debug",
46 "mediatek,mt2701-ice_debug";
47 clocks = <&infracfg CLK_INFRA_DBG_CK>;
48 clock-names = "ice_dbg";
49 };
50
51 clk40m: oscillator@0 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <40000000>;
55 clock-output-names = "clkxtal";
56 };
57
58 psci {
59 compatible = "arm,psci-0.2";
60 method = "smc";
61 };
62
63 fan: pwm-fan {
64 compatible = "pwm-fan";
65 /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
66 cooling-levels = <0 63 95 127 159 191 223 255>;
67 #cooling-cells = <2>;
68 status = "disabled";
69 };
70
71 reg_3p3v: regulator-3p3v {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-3.3V";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
76 regulator-boot-on;
77 regulator-always-on;
78 };
79
80 reserved-memory {
81 #address-cells = <2>;
82 #size-cells = <2>;
83 ranges;
84
85 /* 64 KiB reserved for ramoops/pstore */
86 ramoops@42ff0000 {
87 compatible = "ramoops";
88 reg = <0 0x42ff0000 0 0x10000>;
89 record-size = <0x1000>;
90 };
91
92 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
93 secmon_reserved: secmon@43000000 {
94 reg = <0 0x43000000 0 0x30000>;
95 no-map;
96 };
97
98 wmcpu_emi: wmcpu-reserved@47c80000 {
99 reg = <0 0x47c80000 0 0x100000>;
100 no-map;
101 };
102
103 wo_emi0: wo-emi@47d80000 {
104 reg = <0 0x47d80000 0 0x40000>;
105 no-map;
106 };
107
108 wo_data: wo-data@47dc0000 {
109 reg = <0 0x47dc0000 0 0x240000>;
110 no-map;
111 };
112 };
113
114 soc {
115 compatible = "simple-bus";
116 ranges;
117 #address-cells = <2>;
118 #size-cells = <2>;
119
120 pwm: pwm@10048000 {
121 compatible = "mediatek,mt7981-pwm";
122 reg = <0 0x10048000 0 0x1000>;
123 #pwm-cells = <2>;
124 clocks = <&infracfg CLK_INFRA_PWM_STA>,
125 <&infracfg CLK_INFRA_PWM_HCK>,
126 <&infracfg CLK_INFRA_PWM1_CK>,
127 <&infracfg CLK_INFRA_PWM2_CK>,
128 <&infracfg CLK_INFRA_PWM3_CK>;
129 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
130 };
131
132 thermal: thermal@1100c800 {
133 #thermal-sensor-cells = <1>;
134 compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
135 reg = <0 0x1100c800 0 0x800>;
136 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&infracfg CLK_INFRA_THERM_CK>,
138 <&infracfg CLK_INFRA_ADC_26M_CK>;
139 clock-names = "therm", "auxadc";
140 mediatek,auxadc = <&auxadc>;
141 mediatek,apmixedsys = <&apmixedsys>;
142 nvmem-cells = <&thermal_calibration>;
143 nvmem-cell-names = "calibration-data";
144 };
145
146 auxadc: adc@1100d000 {
147 compatible = "mediatek,mt7981-auxadc",
148 "mediatek,mt7986-auxadc",
149 "mediatek,mt7622-auxadc";
150 reg = <0 0x1100d000 0 0x1000>;
151 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
152 <&infracfg CLK_INFRA_ADC_FRC_CK>;
153 clock-names = "main", "32k";
154 #io-channel-cells = <1>;
155 };
156
157 wdma: wdma@15104800 {
158 compatible = "mediatek,wed-wdma";
159 reg = <0 0x15104800 0 0x400>,
160 <0 0x15104c00 0 0x400>;
161 };
162
163 ap2woccif: ap2woccif@151a5000 {
164 compatible = "mediatek,ap2woccif";
165 reg = <0 0x151a5000 0 0x1000>,
166 <0 0x151ad000 0 0x1000>;
167 interrupt-parent = <&gic>;
168 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
170 };
171
172 infracfg: infracfg@10001000 {
173 compatible = "mediatek,mt7981-infracfg", "syscon";
174 reg = <0 0x10001000 0 0x1000>;
175 #clock-cells = <1>;
176 };
177
178 topckgen: topckgen@1001B000 {
179 compatible = "mediatek,mt7981-topckgen", "syscon";
180 reg = <0 0x1001B000 0 0x1000>;
181 #clock-cells = <1>;
182 };
183
184 apmixedsys: apmixedsys@1001E000 {
185 compatible = "mediatek,mt7981-apmixedsys", "syscon";
186 reg = <0 0x1001E000 0 0x1000>;
187 #clock-cells = <1>;
188 };
189
190 watchdog: watchdog@1001c000 {
191 compatible = "mediatek,mt7986-wdt",
192 "mediatek,mt6589-wdt";
193 reg = <0 0x1001c000 0 0x1000>;
194 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
195 #reset-cells = <1>;
196 status = "disabled";
197 };
198
199 gic: interrupt-controller@c000000 {
200 compatible = "arm,gic-v3";
201 #interrupt-cells = <3>;
202 interrupt-parent = <&gic>;
203 interrupt-controller;
204 reg = <0 0x0c000000 0 0x40000>, /* GICD */
205 <0 0x0c080000 0 0x200000>; /* GICR */
206
207 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
208 };
209
210 uart0: serial@11002000 {
211 compatible = "mediatek,mt6577-uart";
212 reg = <0 0x11002000 0 0x400>;
213 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
215 <&infracfg CLK_INFRA_UART0_CK>;
216 clock-names = "baud", "bus";
217 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
218 <&infracfg CLK_INFRA_UART0_SEL>;
219 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
220 <&topckgen CLK_TOP_UART_SEL>;
221 pinctrl-0 = <&uart0_pins>;
222 pinctrl-names = "default";
223 status = "disabled";
224 };
225
226 uart1: serial@11003000 {
227 compatible = "mediatek,mt6577-uart";
228 reg = <0 0x11003000 0 0x400>;
229 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
231 <&infracfg CLK_INFRA_UART1_CK>;
232 clock-names = "baud", "bus";
233 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
234 <&infracfg CLK_INFRA_UART1_SEL>;
235 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
236 <&topckgen CLK_TOP_UART_SEL>;
237 status = "disabled";
238 };
239
240 uart2: serial@11004000 {
241 compatible = "mediatek,mt6577-uart";
242 reg = <0 0x11004000 0 0x400>;
243 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
245 <&infracfg CLK_INFRA_UART2_CK>;
246 clock-names = "baud", "bus";
247 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
248 <&infracfg CLK_INFRA_UART2_SEL>;
249 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
250 <&topckgen CLK_TOP_UART_SEL>;
251 status = "disabled";
252 };
253
254 i2c0: i2c@11007000 {
255 compatible = "mediatek,mt7981-i2c";
256 reg = <0 0x11007000 0 0x1000>,
257 <0 0x10217080 0 0x80>;
258 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
259 clock-div = <1>;
260 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
261 <&infracfg CLK_INFRA_AP_DMA_CK>,
262 <&infracfg CLK_INFRA_I2C_MCK_CK>,
263 <&infracfg CLK_INFRA_I2C_PCK_CK>;
264 clock-names = "main", "dma", "arb", "pmic";
265 #address-cells = <1>;
266 #size-cells = <0>;
267 status = "disabled";
268 };
269
270 pcie: pcie@11280000 {
271 compatible = "mediatek,mt7981-pcie",
272 "mediatek,mt7986-pcie";
273 device_type = "pci";
274 reg = <0 0x11280000 0 0x4000>;
275 reg-names = "pcie-mac";
276 #address-cells = <3>;
277 #size-cells = <2>;
278 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
279 bus-range = <0x00 0xff>;
280 ranges = <0x82000000 0 0x20000000
281 0x0 0x20000000 0 0x10000000>;
282 status = "disabled";
283
284 clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
285 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
286 <&infracfg CLK_INFRA_IPCIER_CK>,
287 <&infracfg CLK_INFRA_IPCIEB_CK>;
288
289 phys = <&u3port0 PHY_TYPE_PCIE>;
290 phy-names = "pcie-phy";
291
292 #interrupt-cells = <1>;
293 interrupt-map-mask = <0 0 0 7>;
294 interrupt-map = <0 0 0 1 &pcie_intc 0>,
295 <0 0 0 2 &pcie_intc 1>,
296 <0 0 0 3 &pcie_intc 2>,
297 <0 0 0 4 &pcie_intc 3>;
298 pcie_intc: interrupt-controller {
299 interrupt-controller;
300 #address-cells = <0>;
301 #interrupt-cells = <1>;
302 };
303 };
304
305 crypto: crypto@10320000 {
306 compatible = "inside-secure,safexcel-eip97";
307 reg = <0 0x10320000 0 0x40000>;
308 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-names = "ring0", "ring1", "ring2", "ring3";
313 clocks = <&topckgen CLK_TOP_EIP97B>;
314 clock-names = "top_eip97_ck";
315 assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
316 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
317 };
318
319 pio: pinctrl@11d00000 {
320 compatible = "mediatek,mt7981-pinctrl";
321 reg = <0 0x11d00000 0 0x1000>,
322 <0 0x11c00000 0 0x1000>,
323 <0 0x11c10000 0 0x1000>,
324 <0 0x11d20000 0 0x1000>,
325 <0 0x11e00000 0 0x1000>,
326 <0 0x11e20000 0 0x1000>,
327 <0 0x11f00000 0 0x1000>,
328 <0 0x11f10000 0 0x1000>,
329 <0 0x1000b000 0 0x1000>;
330 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
331 "iocfg_rb", "iocfg_lb", "iocfg_bl",
332 "iocfg_tm", "iocfg_tl", "eint";
333 gpio-controller;
334 #gpio-cells = <2>;
335 gpio-ranges = <&pio 0 0 56>;
336 interrupt-controller;
337 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-parent = <&gic>;
339 #interrupt-cells = <2>;
340
341 mdio_pins: mdc-mdio-pins {
342 mux {
343 function = "eth";
344 groups = "smi_mdc_mdio";
345 };
346 };
347
348 uart0_pins: uart0-pins {
349 mux {
350 function = "uart";
351 groups = "uart0";
352 };
353 };
354
355 wifi_dbdc_pins: wifi-dbdc-pins {
356 mux {
357 function = "eth";
358 groups = "wf0_mode1";
359 };
360 conf {
361 pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
362 "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
363 "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
364 "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
365 "WF_CBA_RESETB", "WF_DIG_RESETB";
366 drive-strength = <4>;
367 };
368 };
369
370 gbe_led0_pins: gbe-led0-pins {
371 mux {
372 function = "led";
373 groups = "gbe_led0";
374 };
375 };
376
377 gbe_led1_pins: gbe-led1-pins {
378 mux {
379 function = "led";
380 groups = "gbe_led1";
381 };
382 };
383 };
384
385 ethsys: syscon@15000000 {
386 #address-cells = <1>;
387 #size-cells = <1>;
388 compatible = "mediatek,mt7981-ethsys",
389 "syscon";
390 reg = <0 0x15000000 0 0x1000>;
391 #clock-cells = <1>;
392 #reset-cells = <1>;
393 };
394
395 wed: wed@15010000 {
396 compatible = "mediatek,mt7981-wed",
397 "mediatek,mt7986-wed",
398 "syscon";
399 reg = <0 0x15010000 0 0x1000>;
400 interrupt-parent = <&gic>;
401 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
402 memory-region = <&wo_emi0>, <&wo_data>;
403 memory-region-names = "wo-emi", "wo-data";
404 mediatek,wo-ccif = <&wo_ccif0>;
405 mediatek,wo-ilm = <&wo_ilm0>;
406 mediatek,wo-dlm = <&wo_dlm0>;
407 mediatek,wo-cpuboot = <&wo_cpuboot>;
408 };
409
410 eth: ethernet@15100000 {
411 compatible = "mediatek,mt7981-eth";
412 reg = <0 0x15100000 0 0x80000>;
413 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&ethsys CLK_ETH_FE_EN>,
418 <&ethsys CLK_ETH_GP2_EN>,
419 <&ethsys CLK_ETH_GP1_EN>,
420 <&ethsys CLK_ETH_WOCPU0_EN>,
421 <&sgmiisys0 CLK_SGM0_TX_EN>,
422 <&sgmiisys0 CLK_SGM0_RX_EN>,
423 <&sgmiisys0 CLK_SGM0_CK0_EN>,
424 <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
425 <&sgmiisys1 CLK_SGM1_TX_EN>,
426 <&sgmiisys1 CLK_SGM1_RX_EN>,
427 <&sgmiisys1 CLK_SGM1_CK1_EN>,
428 <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
429 <&topckgen CLK_TOP_SGM_REG>,
430 <&topckgen CLK_TOP_NETSYS_SEL>,
431 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
432 clock-names = "fe", "gp2", "gp1", "wocpu0",
433 "sgmii_tx250m", "sgmii_rx250m",
434 "sgmii_cdr_ref", "sgmii_cdr_fb",
435 "sgmii2_tx250m", "sgmii2_rx250m",
436 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
437 "sgmii_ck", "netsys0", "netsys1";
438 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
439 <&topckgen CLK_TOP_SGM_325M_SEL>;
440 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
441 <&topckgen CLK_TOP_CB_SGM_325M>;
442 mediatek,ethsys = <&ethsys>;
443 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
444 mediatek,infracfg = <&topmisc>;
445 mediatek,wed = <&wed>;
446 #reset-cells = <1>;
447 #address-cells = <1>;
448 #size-cells = <0>;
449 status = "disabled";
450
451 mdio_bus: mdio-bus {
452 #address-cells = <1>;
453 #size-cells = <0>;
454
455 int_gbe_phy: ethernet-phy@0 {
456 reg = <0>;
457 compatible = "ethernet-phy-ieee802.3-c22";
458 phy-mode = "gmii";
459 phy-is-integrated;
460 nvmem-cells = <&phy_calibration>;
461 nvmem-cell-names = "phy-cal-data";
462
463 leds {
464 #address-cells = <1>;
465 #size-cells = <0>;
466
467 int_gbe_phy_led0: int-gbe-phy-led0@0 {
468 reg = <0>;
469 function = LED_FUNCTION_LAN;
470 status = "disabled";
471 };
472
473 int_gbe_phy_led1: int-gbe-phy-led1@1 {
474 reg = <1>;
475 function = LED_FUNCTION_LAN;
476 status = "disabled";
477 };
478 };
479 };
480 };
481 };
482
483 wo_dlm0: syscon@151e8000 {
484 compatible = "mediatek,mt7986-wo-dlm", "syscon";
485 reg = <0 0x151e8000 0 0x2000>;
486 };
487
488 wo_ilm0: syscon@151e0000 {
489 compatible = "mediatek,mt7986-wo-ilm", "syscon";
490 reg = <0 0x151e0000 0 0x8000>;
491 };
492
493 wo_cpuboot: syscon@15194000 {
494 compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
495 reg = <0 0x15194000 0 0x1000>;
496 };
497
498 wo_ccif0: syscon@151a5000 {
499 compatible = "mediatek,mt7986-wo-ccif", "syscon";
500 reg = <0 0x151a5000 0 0x1000>;
501 interrupt-parent = <&gic>;
502 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
503 };
504
505 sgmiisys0: syscon@10060000 {
506 compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
507 reg = <0 0x10060000 0 0x1000>;
508 mediatek,pnswap;
509 #clock-cells = <1>;
510 };
511
512 sgmiisys1: syscon@10070000 {
513 compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
514 reg = <0 0x10070000 0 0x1000>;
515 #clock-cells = <1>;
516 };
517
518 topmisc: topmisc@11d10000 {
519 compatible = "mediatek,mt7981-topmisc", "syscon";
520 reg = <0 0x11d10000 0 0x10000>;
521 #clock-cells = <1>;
522 };
523
524 snand: snfi@11005000 {
525 compatible = "mediatek,mt7986-snand";
526 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
527 reg-names = "nfi", "ecc";
528 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
530 <&infracfg CLK_INFRA_NFI1_CK>,
531 <&infracfg CLK_INFRA_NFI_HCK_CK>;
532 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
533 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
534 <&topckgen CLK_TOP_NFI1X_SEL>;
535 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
536 <&topckgen CLK_TOP_CB_M_D8>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 status = "disabled";
540 };
541
542 mmc0: mmc@11230000 {
543 compatible = "mediatek,mt7986-mmc",
544 "mediatek,mt7981-mmc";
545 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
546 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
548 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
549 <&infracfg CLK_INFRA_MSDC_66M_CK>,
550 <&infracfg CLK_INFRA_MSDC_133M_CK>;
551 assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
552 <&topckgen CLK_TOP_EMMC_400M_SEL>;
553 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
554 <&topckgen CLK_TOP_CB_NET2_D2>;
555 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
556 status = "disabled";
557 };
558
559 wed_pcie: wed_pcie@10003000 {
560 compatible = "mediatek,wed_pcie";
561 reg = <0 0x10003000 0 0x10>;
562 };
563
564 spi0: spi@1100a000 {
565 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
566 #address-cells = <1>;
567 #size-cells = <0>;
568 reg = <0 0x1100a000 0 0x100>;
569 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&topckgen CLK_TOP_CB_M_D2>,
571 <&topckgen CLK_TOP_SPI_SEL>,
572 <&infracfg CLK_INFRA_SPI0_CK>,
573 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
574
575 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
576 status = "disabled";
577 };
578
579 spi1: spi@1100b000 {
580 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
581 #address-cells = <1>;
582 #size-cells = <0>;
583 reg = <0 0x1100b000 0 0x100>;
584 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&topckgen CLK_TOP_CB_M_D2>,
586 <&topckgen CLK_TOP_SPIM_MST_SEL>,
587 <&infracfg CLK_INFRA_SPI1_CK>,
588 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
589 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
590 status = "disabled";
591 };
592
593 spi2: spi@11009000 {
594 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
595 #address-cells = <1>;
596 #size-cells = <0>;
597 reg = <0 0x11009000 0 0x100>;
598 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&topckgen CLK_TOP_CB_M_D2>,
600 <&topckgen CLK_TOP_SPI_SEL>,
601 <&infracfg CLK_INFRA_SPI2_CK>,
602 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
603 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
604 status = "disabled";
605 };
606
607 consys: consys@10000000 {
608 compatible = "mediatek,mt7981-consys";
609 reg = <0 0x10000000 0 0x8600000>;
610 memory-region = <&wmcpu_emi>;
611 };
612
613 xhci: usb@11200000 {
614 compatible = "mediatek,mt7986-xhci",
615 "mediatek,mtk-xhci";
616 reg = <0 0x11200000 0 0x2e00>,
617 <0 0x11203e00 0 0x0100>;
618 reg-names = "mac", "ippc";
619 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
621 <&infracfg CLK_INFRA_IUSB_CK>,
622 <&infracfg CLK_INFRA_IUSB_133_CK>,
623 <&infracfg CLK_INFRA_IUSB_66M_CK>,
624 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
625 clock-names = "sys_ck",
626 "ref_ck",
627 "mcu_ck",
628 "dma_ck",
629 "xhci_ck";
630 phys = <&u2port0 PHY_TYPE_USB2>,
631 <&u3port0 PHY_TYPE_USB3>;
632 vusb33-supply = <&reg_3p3v>;
633 status = "disabled";
634 };
635
636 usb_phy: usb-phy@11e10000 {
637 compatible = "mediatek,mt7981",
638 "mediatek,generic-tphy-v2";
639 #address-cells = <1>;
640 #size-cells = <1>;
641 ranges = <0 0 0x11e10000 0x1700>;
642 status = "disabled";
643
644 u2port0: usb-phy@0 {
645 reg = <0x0 0x700>;
646 clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
647 clock-names = "ref";
648 #phy-cells = <1>;
649 };
650
651 u3port0: usb-phy@700 {
652 reg = <0x700 0x900>;
653 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
654 clock-names = "ref";
655 #phy-cells = <1>;
656 mediatek,syscon-type = <&topmisc 0x218 0>;
657 status = "okay";
658 };
659 };
660
661 efuse: efuse@11f20000 {
662 compatible = "mediatek,mt7981-efuse",
663 "mediatek,efuse";
664 reg = <0 0x11f20000 0 0x1000>;
665 #address-cells = <1>;
666 #size-cells = <1>;
667 status = "okay";
668
669 thermal_calibration: thermal-calib@274 {
670 reg = <0x274 0xc>;
671 };
672
673 phy_calibration: phy-calib@8dc {
674 reg = <0x8dc 0x10>;
675 };
676
677 comb_rx_imp_p0: usb3-rx-imp@8c8 {
678 reg = <0x8c8 1>;
679 bits = <0 5>;
680 };
681
682 comb_tx_imp_p0: usb3-tx-imp@8c8 {
683 reg = <0x8c8 2>;
684 bits = <5 5>;
685 };
686
687 comb_intr_p0: usb3-intr@8c9 {
688 reg = <0x8c9 1>;
689 bits = <2 6>;
690 };
691 };
692
693 afe: audio-controller@11210000 {
694 compatible = "mediatek,mt79xx-audio";
695 reg = <0 0x11210000 0 0x9000>;
696 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
698 <&infracfg CLK_INFRA_AUD_26M_CK>,
699 <&infracfg CLK_INFRA_AUD_L_CK>,
700 <&infracfg CLK_INFRA_AUD_AUD_CK>,
701 <&infracfg CLK_INFRA_AUD_EG2_CK>,
702 <&topckgen CLK_TOP_AUD_SEL>;
703 clock-names = "aud_bus_ck",
704 "aud_26m_ck",
705 "aud_l_ck",
706 "aud_aud_ck",
707 "aud_eg2_ck",
708 "aud_sel";
709 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
710 <&topckgen CLK_TOP_A1SYS_SEL>,
711 <&topckgen CLK_TOP_AUD_L_SEL>,
712 <&topckgen CLK_TOP_A_TUNER_SEL>;
713 assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
714 <&topckgen CLK_TOP_APLL2_D4>,
715 <&topckgen CLK_TOP_CB_APLL2_196M>,
716 <&topckgen CLK_TOP_APLL2_D4>;
717 status = "disabled";
718 };
719
720 wifi: wifi@18000000 {
721 compatible = "mediatek,mt7981-wmac";
722 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
723 reset-names = "consys";
724 pinctrl-0 = <&wifi_dbdc_pins>;
725 pinctrl-names = "dbdc";
726 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
727 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
728 clock-names = "mcu", "ap2conn";
729 reg = <0 0x18000000 0 0x1000000>,
730 <0 0x10003000 0 0x1000>,
731 <0 0x11d10000 0 0x1000>;
732 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
736 memory-region = <&wmcpu_emi>;
737 status = "disabled";
738 };
739 };
740
741 thermal-zones {
742 cpu_thermal: cpu-thermal {
743 polling-delay-passive = <1000>;
744 polling-delay = <1000>;
745 thermal-sensors = <&thermal 0>;
746 trips {
747 cpu_trip_active_highest: active-highest {
748 temperature = <70000>;
749 hysteresis = <2000>;
750 type = "active";
751 };
752
753 cpu_trip_active_high: active-high {
754 temperature = <60000>;
755 hysteresis = <2000>;
756 type = "active";
757 };
758
759 cpu_trip_active_med: active-med {
760 temperature = <50000>;
761 hysteresis = <2000>;
762 type = "active";
763 };
764
765 cpu_trip_active_low: active-low {
766 temperature = <45000>;
767 hysteresis = <2000>;
768 type = "active";
769 };
770
771 cpu_trip_active_lowest: active-lowest {
772 temperature = <40000>;
773 hysteresis = <2000>;
774 type = "active";
775 };
776 };
777
778 cooling-maps {
779 cpu-active-highest {
780 /* active: set fan to cooling level 7 */
781 cooling-device = <&fan 7 7>;
782 trip = <&cpu_trip_active_highest>;
783 };
784
785 cpu-active-high {
786 /* active: set fan to cooling level 5 */
787 cooling-device = <&fan 5 5>;
788 trip = <&cpu_trip_active_high>;
789 };
790
791 cpu-active-med {
792 /* active: set fan to cooling level 3 */
793 cooling-device = <&fan 3 3>;
794 trip = <&cpu_trip_active_med>;
795 };
796
797 cpu-active-low {
798 /* active: set fan to cooling level 2 */
799 cooling-device = <&fan 2 2>;
800 trip = <&cpu_trip_active_low>;
801 };
802
803 cpu-active-lowest {
804 /* active: set fan to cooling level 1 */
805 cooling-device = <&fan 1 1>;
806 trip = <&cpu_trip_active_lowest>;
807 };
808 };
809 };
810 };
811
812 timer {
813 compatible = "arm,armv8-timer";
814 interrupt-parent = <&gic>;
815 clock-frequency = <13000000>;
816 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
817 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
818 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
819 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
820
821 };
822
823 trng {
824 compatible = "mediatek,mt7981-rng";
825 };
826 };
Staging tree of Jo-Philipp Wich