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mediatek: filogic: reorder mt7981 DT SoC reg-based nodes
[openwrt/staging/jow.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7981.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 * Author: Jianhui Zhao <zhaojh329@gmail.com>
6 */
7
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
12 #include <dt-bindings/reset/mt7986-resets.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/input/linux-event-codes.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/mux/mux.h>
18
19 / {
20 compatible = "mediatek,mt7981";
21 interrupt-parent = <&gic>;
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a53";
32 enable-method = "psci";
33 reg = <0x0>;
34 };
35
36 cpu@1 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a53";
39 enable-method = "psci";
40 reg = <0x1>;
41 };
42 };
43
44 ice: ice_debug {
45 compatible = "mediatek,mt7981-ice_debug",
46 "mediatek,mt2701-ice_debug";
47 clocks = <&infracfg CLK_INFRA_DBG_CK>;
48 clock-names = "ice_dbg";
49 };
50
51 clk40m: oscillator@0 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <40000000>;
55 clock-output-names = "clkxtal";
56 };
57
58 psci {
59 compatible = "arm,psci-0.2";
60 method = "smc";
61 };
62
63 fan: pwm-fan {
64 compatible = "pwm-fan";
65 /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
66 cooling-levels = <0 63 95 127 159 191 223 255>;
67 #cooling-cells = <2>;
68 status = "disabled";
69 };
70
71 reg_3p3v: regulator-3p3v {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-3.3V";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
76 regulator-boot-on;
77 regulator-always-on;
78 };
79
80 reserved-memory {
81 #address-cells = <2>;
82 #size-cells = <2>;
83 ranges;
84
85 /* 64 KiB reserved for ramoops/pstore */
86 ramoops@42ff0000 {
87 compatible = "ramoops";
88 reg = <0 0x42ff0000 0 0x10000>;
89 record-size = <0x1000>;
90 };
91
92 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
93 secmon_reserved: secmon@43000000 {
94 reg = <0 0x43000000 0 0x30000>;
95 no-map;
96 };
97
98 wmcpu_emi: wmcpu-reserved@47c80000 {
99 reg = <0 0x47c80000 0 0x100000>;
100 no-map;
101 };
102
103 wo_emi0: wo-emi@47d80000 {
104 reg = <0 0x47d80000 0 0x40000>;
105 no-map;
106 };
107
108 wo_data: wo-data@47dc0000 {
109 reg = <0 0x47dc0000 0 0x240000>;
110 no-map;
111 };
112 };
113
114 soc {
115 compatible = "simple-bus";
116 ranges;
117 #address-cells = <2>;
118 #size-cells = <2>;
119
120 gic: interrupt-controller@c000000 {
121 compatible = "arm,gic-v3";
122 #interrupt-cells = <3>;
123 interrupt-parent = <&gic>;
124 interrupt-controller;
125 reg = <0 0x0c000000 0 0x40000>, /* GICD */
126 <0 0x0c080000 0 0x200000>; /* GICR */
127
128 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
129 };
130
131 consys: consys@10000000 {
132 compatible = "mediatek,mt7981-consys";
133 reg = <0 0x10000000 0 0x8600000>;
134 memory-region = <&wmcpu_emi>;
135 };
136
137 infracfg: infracfg@10001000 {
138 compatible = "mediatek,mt7981-infracfg", "syscon";
139 reg = <0 0x10001000 0 0x1000>;
140 #clock-cells = <1>;
141 };
142
143 wed_pcie: wed_pcie@10003000 {
144 compatible = "mediatek,wed_pcie";
145 reg = <0 0x10003000 0 0x10>;
146 };
147
148 topckgen: topckgen@1001B000 {
149 compatible = "mediatek,mt7981-topckgen", "syscon";
150 reg = <0 0x1001B000 0 0x1000>;
151 #clock-cells = <1>;
152 };
153
154 watchdog: watchdog@1001c000 {
155 compatible = "mediatek,mt7986-wdt",
156 "mediatek,mt6589-wdt";
157 reg = <0 0x1001c000 0 0x1000>;
158 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
159 #reset-cells = <1>;
160 status = "disabled";
161 };
162
163 apmixedsys: apmixedsys@1001E000 {
164 compatible = "mediatek,mt7981-apmixedsys", "syscon";
165 reg = <0 0x1001E000 0 0x1000>;
166 #clock-cells = <1>;
167 };
168
169 pwm: pwm@10048000 {
170 compatible = "mediatek,mt7981-pwm";
171 reg = <0 0x10048000 0 0x1000>;
172 #pwm-cells = <2>;
173 clocks = <&infracfg CLK_INFRA_PWM_STA>,
174 <&infracfg CLK_INFRA_PWM_HCK>,
175 <&infracfg CLK_INFRA_PWM1_CK>,
176 <&infracfg CLK_INFRA_PWM2_CK>,
177 <&infracfg CLK_INFRA_PWM3_CK>;
178 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
179 };
180
181 sgmiisys0: syscon@10060000 {
182 compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
183 reg = <0 0x10060000 0 0x1000>;
184 mediatek,pnswap;
185 #clock-cells = <1>;
186 };
187
188 sgmiisys1: syscon@10070000 {
189 compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
190 reg = <0 0x10070000 0 0x1000>;
191 #clock-cells = <1>;
192 };
193
194 crypto: crypto@10320000 {
195 compatible = "inside-secure,safexcel-eip97";
196 reg = <0 0x10320000 0 0x40000>;
197 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-names = "ring0", "ring1", "ring2", "ring3";
202 clocks = <&topckgen CLK_TOP_EIP97B>;
203 clock-names = "top_eip97_ck";
204 assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
205 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
206 };
207
208 uart0: serial@11002000 {
209 compatible = "mediatek,mt6577-uart";
210 reg = <0 0x11002000 0 0x400>;
211 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
213 <&infracfg CLK_INFRA_UART0_CK>;
214 clock-names = "baud", "bus";
215 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
216 <&infracfg CLK_INFRA_UART0_SEL>;
217 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
218 <&topckgen CLK_TOP_UART_SEL>;
219 pinctrl-0 = <&uart0_pins>;
220 pinctrl-names = "default";
221 status = "disabled";
222 };
223
224 uart1: serial@11003000 {
225 compatible = "mediatek,mt6577-uart";
226 reg = <0 0x11003000 0 0x400>;
227 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
229 <&infracfg CLK_INFRA_UART1_CK>;
230 clock-names = "baud", "bus";
231 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
232 <&infracfg CLK_INFRA_UART1_SEL>;
233 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
234 <&topckgen CLK_TOP_UART_SEL>;
235 status = "disabled";
236 };
237
238 uart2: serial@11004000 {
239 compatible = "mediatek,mt6577-uart";
240 reg = <0 0x11004000 0 0x400>;
241 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
243 <&infracfg CLK_INFRA_UART2_CK>;
244 clock-names = "baud", "bus";
245 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
246 <&infracfg CLK_INFRA_UART2_SEL>;
247 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
248 <&topckgen CLK_TOP_UART_SEL>;
249 status = "disabled";
250 };
251
252 snand: snfi@11005000 {
253 compatible = "mediatek,mt7986-snand";
254 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
255 reg-names = "nfi", "ecc";
256 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
258 <&infracfg CLK_INFRA_NFI1_CK>,
259 <&infracfg CLK_INFRA_NFI_HCK_CK>;
260 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
261 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
262 <&topckgen CLK_TOP_NFI1X_SEL>;
263 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
264 <&topckgen CLK_TOP_CB_M_D8>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 status = "disabled";
268 };
269
270 i2c0: i2c@11007000 {
271 compatible = "mediatek,mt7981-i2c";
272 reg = <0 0x11007000 0 0x1000>,
273 <0 0x10217080 0 0x80>;
274 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
275 clock-div = <1>;
276 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
277 <&infracfg CLK_INFRA_AP_DMA_CK>,
278 <&infracfg CLK_INFRA_I2C_MCK_CK>,
279 <&infracfg CLK_INFRA_I2C_PCK_CK>;
280 clock-names = "main", "dma", "arb", "pmic";
281 #address-cells = <1>;
282 #size-cells = <0>;
283 status = "disabled";
284 };
285
286 spi2: spi@11009000 {
287 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
288 #address-cells = <1>;
289 #size-cells = <0>;
290 reg = <0 0x11009000 0 0x100>;
291 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&topckgen CLK_TOP_CB_M_D2>,
293 <&topckgen CLK_TOP_SPI_SEL>,
294 <&infracfg CLK_INFRA_SPI2_CK>,
295 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
296 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
297 status = "disabled";
298 };
299
300 spi0: spi@1100a000 {
301 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
302 #address-cells = <1>;
303 #size-cells = <0>;
304 reg = <0 0x1100a000 0 0x100>;
305 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&topckgen CLK_TOP_CB_M_D2>,
307 <&topckgen CLK_TOP_SPI_SEL>,
308 <&infracfg CLK_INFRA_SPI0_CK>,
309 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
310
311 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
312 status = "disabled";
313 };
314
315 spi1: spi@1100b000 {
316 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
317 #address-cells = <1>;
318 #size-cells = <0>;
319 reg = <0 0x1100b000 0 0x100>;
320 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&topckgen CLK_TOP_CB_M_D2>,
322 <&topckgen CLK_TOP_SPIM_MST_SEL>,
323 <&infracfg CLK_INFRA_SPI1_CK>,
324 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
325 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
326 status = "disabled";
327 };
328
329 thermal: thermal@1100c800 {
330 #thermal-sensor-cells = <1>;
331 compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
332 reg = <0 0x1100c800 0 0x800>;
333 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&infracfg CLK_INFRA_THERM_CK>,
335 <&infracfg CLK_INFRA_ADC_26M_CK>;
336 clock-names = "therm", "auxadc";
337 mediatek,auxadc = <&auxadc>;
338 mediatek,apmixedsys = <&apmixedsys>;
339 nvmem-cells = <&thermal_calibration>;
340 nvmem-cell-names = "calibration-data";
341 };
342
343 auxadc: adc@1100d000 {
344 compatible = "mediatek,mt7981-auxadc",
345 "mediatek,mt7986-auxadc",
346 "mediatek,mt7622-auxadc";
347 reg = <0 0x1100d000 0 0x1000>;
348 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
349 <&infracfg CLK_INFRA_ADC_FRC_CK>;
350 clock-names = "main", "32k";
351 #io-channel-cells = <1>;
352 };
353
354 xhci: usb@11200000 {
355 compatible = "mediatek,mt7986-xhci",
356 "mediatek,mtk-xhci";
357 reg = <0 0x11200000 0 0x2e00>,
358 <0 0x11203e00 0 0x0100>;
359 reg-names = "mac", "ippc";
360 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
362 <&infracfg CLK_INFRA_IUSB_CK>,
363 <&infracfg CLK_INFRA_IUSB_133_CK>,
364 <&infracfg CLK_INFRA_IUSB_66M_CK>,
365 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
366 clock-names = "sys_ck",
367 "ref_ck",
368 "mcu_ck",
369 "dma_ck",
370 "xhci_ck";
371 phys = <&u2port0 PHY_TYPE_USB2>,
372 <&u3port0 PHY_TYPE_USB3>;
373 vusb33-supply = <&reg_3p3v>;
374 status = "disabled";
375 };
376
377 afe: audio-controller@11210000 {
378 compatible = "mediatek,mt79xx-audio";
379 reg = <0 0x11210000 0 0x9000>;
380 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
382 <&infracfg CLK_INFRA_AUD_26M_CK>,
383 <&infracfg CLK_INFRA_AUD_L_CK>,
384 <&infracfg CLK_INFRA_AUD_AUD_CK>,
385 <&infracfg CLK_INFRA_AUD_EG2_CK>,
386 <&topckgen CLK_TOP_AUD_SEL>;
387 clock-names = "aud_bus_ck",
388 "aud_26m_ck",
389 "aud_l_ck",
390 "aud_aud_ck",
391 "aud_eg2_ck",
392 "aud_sel";
393 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
394 <&topckgen CLK_TOP_A1SYS_SEL>,
395 <&topckgen CLK_TOP_AUD_L_SEL>,
396 <&topckgen CLK_TOP_A_TUNER_SEL>;
397 assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
398 <&topckgen CLK_TOP_APLL2_D4>,
399 <&topckgen CLK_TOP_CB_APLL2_196M>,
400 <&topckgen CLK_TOP_APLL2_D4>;
401 status = "disabled";
402 };
403
404 mmc0: mmc@11230000 {
405 compatible = "mediatek,mt7986-mmc",
406 "mediatek,mt7981-mmc";
407 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
408 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
410 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
411 <&infracfg CLK_INFRA_MSDC_66M_CK>,
412 <&infracfg CLK_INFRA_MSDC_133M_CK>;
413 assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
414 <&topckgen CLK_TOP_EMMC_400M_SEL>;
415 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
416 <&topckgen CLK_TOP_CB_NET2_D2>;
417 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
418 status = "disabled";
419 };
420
421 pcie: pcie@11280000 {
422 compatible = "mediatek,mt7981-pcie",
423 "mediatek,mt7986-pcie";
424 device_type = "pci";
425 reg = <0 0x11280000 0 0x4000>;
426 reg-names = "pcie-mac";
427 #address-cells = <3>;
428 #size-cells = <2>;
429 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
430 bus-range = <0x00 0xff>;
431 ranges = <0x82000000 0 0x20000000
432 0x0 0x20000000 0 0x10000000>;
433 status = "disabled";
434
435 clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
436 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
437 <&infracfg CLK_INFRA_IPCIER_CK>,
438 <&infracfg CLK_INFRA_IPCIEB_CK>;
439
440 phys = <&u3port0 PHY_TYPE_PCIE>;
441 phy-names = "pcie-phy";
442
443 #interrupt-cells = <1>;
444 interrupt-map-mask = <0 0 0 7>;
445 interrupt-map = <0 0 0 1 &pcie_intc 0>,
446 <0 0 0 2 &pcie_intc 1>,
447 <0 0 0 3 &pcie_intc 2>,
448 <0 0 0 4 &pcie_intc 3>;
449 pcie_intc: interrupt-controller {
450 interrupt-controller;
451 #address-cells = <0>;
452 #interrupt-cells = <1>;
453 };
454 };
455
456 pio: pinctrl@11d00000 {
457 compatible = "mediatek,mt7981-pinctrl";
458 reg = <0 0x11d00000 0 0x1000>,
459 <0 0x11c00000 0 0x1000>,
460 <0 0x11c10000 0 0x1000>,
461 <0 0x11d20000 0 0x1000>,
462 <0 0x11e00000 0 0x1000>,
463 <0 0x11e20000 0 0x1000>,
464 <0 0x11f00000 0 0x1000>,
465 <0 0x11f10000 0 0x1000>,
466 <0 0x1000b000 0 0x1000>;
467 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
468 "iocfg_rb", "iocfg_lb", "iocfg_bl",
469 "iocfg_tm", "iocfg_tl", "eint";
470 gpio-controller;
471 #gpio-cells = <2>;
472 gpio-ranges = <&pio 0 0 56>;
473 interrupt-controller;
474 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
475 interrupt-parent = <&gic>;
476 #interrupt-cells = <2>;
477
478 mdio_pins: mdc-mdio-pins {
479 mux {
480 function = "eth";
481 groups = "smi_mdc_mdio";
482 };
483 };
484
485 uart0_pins: uart0-pins {
486 mux {
487 function = "uart";
488 groups = "uart0";
489 };
490 };
491
492 wifi_dbdc_pins: wifi-dbdc-pins {
493 mux {
494 function = "eth";
495 groups = "wf0_mode1";
496 };
497 conf {
498 pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
499 "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
500 "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
501 "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
502 "WF_CBA_RESETB", "WF_DIG_RESETB";
503 drive-strength = <4>;
504 };
505 };
506
507 gbe_led0_pins: gbe-led0-pins {
508 mux {
509 function = "led";
510 groups = "gbe_led0";
511 };
512 };
513
514 gbe_led1_pins: gbe-led1-pins {
515 mux {
516 function = "led";
517 groups = "gbe_led1";
518 };
519 };
520 };
521
522 topmisc: topmisc@11d10000 {
523 compatible = "mediatek,mt7981-topmisc", "syscon";
524 reg = <0 0x11d10000 0 0x10000>;
525 #clock-cells = <1>;
526 };
527
528 usb_phy: usb-phy@11e10000 {
529 compatible = "mediatek,mt7981",
530 "mediatek,generic-tphy-v2";
531 #address-cells = <1>;
532 #size-cells = <1>;
533 ranges = <0 0 0x11e10000 0x1700>;
534 status = "disabled";
535
536 u2port0: usb-phy@0 {
537 reg = <0x0 0x700>;
538 clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
539 clock-names = "ref";
540 #phy-cells = <1>;
541 };
542
543 u3port0: usb-phy@700 {
544 reg = <0x700 0x900>;
545 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
546 clock-names = "ref";
547 #phy-cells = <1>;
548 mediatek,syscon-type = <&topmisc 0x218 0>;
549 status = "okay";
550 };
551 };
552
553 efuse: efuse@11f20000 {
554 compatible = "mediatek,mt7981-efuse",
555 "mediatek,efuse";
556 reg = <0 0x11f20000 0 0x1000>;
557 #address-cells = <1>;
558 #size-cells = <1>;
559 status = "okay";
560
561 thermal_calibration: thermal-calib@274 {
562 reg = <0x274 0xc>;
563 };
564
565 phy_calibration: phy-calib@8dc {
566 reg = <0x8dc 0x10>;
567 };
568
569 comb_rx_imp_p0: usb3-rx-imp@8c8 {
570 reg = <0x8c8 1>;
571 bits = <0 5>;
572 };
573
574 comb_tx_imp_p0: usb3-tx-imp@8c8 {
575 reg = <0x8c8 2>;
576 bits = <5 5>;
577 };
578
579 comb_intr_p0: usb3-intr@8c9 {
580 reg = <0x8c9 1>;
581 bits = <2 6>;
582 };
583 };
584
585 ethsys: syscon@15000000 {
586 #address-cells = <1>;
587 #size-cells = <1>;
588 compatible = "mediatek,mt7981-ethsys",
589 "syscon";
590 reg = <0 0x15000000 0 0x1000>;
591 #clock-cells = <1>;
592 #reset-cells = <1>;
593 };
594
595 wed: wed@15010000 {
596 compatible = "mediatek,mt7981-wed",
597 "mediatek,mt7986-wed",
598 "syscon";
599 reg = <0 0x15010000 0 0x1000>;
600 interrupt-parent = <&gic>;
601 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
602 memory-region = <&wo_emi0>, <&wo_data>;
603 memory-region-names = "wo-emi", "wo-data";
604 mediatek,wo-ccif = <&wo_ccif0>;
605 mediatek,wo-ilm = <&wo_ilm0>;
606 mediatek,wo-dlm = <&wo_dlm0>;
607 mediatek,wo-cpuboot = <&wo_cpuboot>;
608 };
609
610 eth: ethernet@15100000 {
611 compatible = "mediatek,mt7981-eth";
612 reg = <0 0x15100000 0 0x80000>;
613 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&ethsys CLK_ETH_FE_EN>,
618 <&ethsys CLK_ETH_GP2_EN>,
619 <&ethsys CLK_ETH_GP1_EN>,
620 <&ethsys CLK_ETH_WOCPU0_EN>,
621 <&sgmiisys0 CLK_SGM0_TX_EN>,
622 <&sgmiisys0 CLK_SGM0_RX_EN>,
623 <&sgmiisys0 CLK_SGM0_CK0_EN>,
624 <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
625 <&sgmiisys1 CLK_SGM1_TX_EN>,
626 <&sgmiisys1 CLK_SGM1_RX_EN>,
627 <&sgmiisys1 CLK_SGM1_CK1_EN>,
628 <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
629 <&topckgen CLK_TOP_SGM_REG>,
630 <&topckgen CLK_TOP_NETSYS_SEL>,
631 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
632 clock-names = "fe", "gp2", "gp1", "wocpu0",
633 "sgmii_tx250m", "sgmii_rx250m",
634 "sgmii_cdr_ref", "sgmii_cdr_fb",
635 "sgmii2_tx250m", "sgmii2_rx250m",
636 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
637 "sgmii_ck", "netsys0", "netsys1";
638 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
639 <&topckgen CLK_TOP_SGM_325M_SEL>;
640 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
641 <&topckgen CLK_TOP_CB_SGM_325M>;
642 mediatek,ethsys = <&ethsys>;
643 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
644 mediatek,infracfg = <&topmisc>;
645 mediatek,wed = <&wed>;
646 #reset-cells = <1>;
647 #address-cells = <1>;
648 #size-cells = <0>;
649 status = "disabled";
650
651 mdio_bus: mdio-bus {
652 #address-cells = <1>;
653 #size-cells = <0>;
654
655 int_gbe_phy: ethernet-phy@0 {
656 reg = <0>;
657 compatible = "ethernet-phy-ieee802.3-c22";
658 phy-mode = "gmii";
659 phy-is-integrated;
660 nvmem-cells = <&phy_calibration>;
661 nvmem-cell-names = "phy-cal-data";
662
663 leds {
664 #address-cells = <1>;
665 #size-cells = <0>;
666
667 int_gbe_phy_led0: int-gbe-phy-led0@0 {
668 reg = <0>;
669 function = LED_FUNCTION_LAN;
670 status = "disabled";
671 };
672
673 int_gbe_phy_led1: int-gbe-phy-led1@1 {
674 reg = <1>;
675 function = LED_FUNCTION_LAN;
676 status = "disabled";
677 };
678 };
679 };
680 };
681 };
682
683 wdma: wdma@15104800 {
684 compatible = "mediatek,wed-wdma";
685 reg = <0 0x15104800 0 0x400>,
686 <0 0x15104c00 0 0x400>;
687 };
688
689 wo_cpuboot: syscon@15194000 {
690 compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
691 reg = <0 0x15194000 0 0x1000>;
692 };
693
694 ap2woccif: ap2woccif@151a5000 {
695 compatible = "mediatek,ap2woccif";
696 reg = <0 0x151a5000 0 0x1000>,
697 <0 0x151ad000 0 0x1000>;
698 interrupt-parent = <&gic>;
699 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
701 };
702
703 wo_ccif0: syscon@151a5000 {
704 compatible = "mediatek,mt7986-wo-ccif", "syscon";
705 reg = <0 0x151a5000 0 0x1000>;
706 interrupt-parent = <&gic>;
707 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
708 };
709
710 wo_ilm0: syscon@151e0000 {
711 compatible = "mediatek,mt7986-wo-ilm", "syscon";
712 reg = <0 0x151e0000 0 0x8000>;
713 };
714
715 wo_dlm0: syscon@151e8000 {
716 compatible = "mediatek,mt7986-wo-dlm", "syscon";
717 reg = <0 0x151e8000 0 0x2000>;
718 };
719
720 wifi: wifi@18000000 {
721 compatible = "mediatek,mt7981-wmac";
722 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
723 reset-names = "consys";
724 pinctrl-0 = <&wifi_dbdc_pins>;
725 pinctrl-names = "dbdc";
726 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
727 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
728 clock-names = "mcu", "ap2conn";
729 reg = <0 0x18000000 0 0x1000000>,
730 <0 0x10003000 0 0x1000>,
731 <0 0x11d10000 0 0x1000>;
732 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
736 memory-region = <&wmcpu_emi>;
737 status = "disabled";
738 };
739 };
740
741 thermal-zones {
742 cpu_thermal: cpu-thermal {
743 polling-delay-passive = <1000>;
744 polling-delay = <1000>;
745 thermal-sensors = <&thermal 0>;
746 trips {
747 cpu_trip_active_highest: active-highest {
748 temperature = <70000>;
749 hysteresis = <2000>;
750 type = "active";
751 };
752
753 cpu_trip_active_high: active-high {
754 temperature = <60000>;
755 hysteresis = <2000>;
756 type = "active";
757 };
758
759 cpu_trip_active_med: active-med {
760 temperature = <50000>;
761 hysteresis = <2000>;
762 type = "active";
763 };
764
765 cpu_trip_active_low: active-low {
766 temperature = <45000>;
767 hysteresis = <2000>;
768 type = "active";
769 };
770
771 cpu_trip_active_lowest: active-lowest {
772 temperature = <40000>;
773 hysteresis = <2000>;
774 type = "active";
775 };
776 };
777
778 cooling-maps {
779 cpu-active-highest {
780 /* active: set fan to cooling level 7 */
781 cooling-device = <&fan 7 7>;
782 trip = <&cpu_trip_active_highest>;
783 };
784
785 cpu-active-high {
786 /* active: set fan to cooling level 5 */
787 cooling-device = <&fan 5 5>;
788 trip = <&cpu_trip_active_high>;
789 };
790
791 cpu-active-med {
792 /* active: set fan to cooling level 3 */
793 cooling-device = <&fan 3 3>;
794 trip = <&cpu_trip_active_med>;
795 };
796
797 cpu-active-low {
798 /* active: set fan to cooling level 2 */
799 cooling-device = <&fan 2 2>;
800 trip = <&cpu_trip_active_low>;
801 };
802
803 cpu-active-lowest {
804 /* active: set fan to cooling level 1 */
805 cooling-device = <&fan 1 1>;
806 trip = <&cpu_trip_active_lowest>;
807 };
808 };
809 };
810 };
811
812 timer {
813 compatible = "arm,armv8-timer";
814 interrupt-parent = <&gic>;
815 clock-frequency = <13000000>;
816 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
817 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
818 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
819 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
820
821 };
822
823 trng {
824 compatible = "mediatek,mt7981-rng";
825 };
826 };
Staging tree of Jo-Philipp Wich