mediatek: convert to new LED color/function format where possible
[openwrt/staging/mans0n.git] / target / linux / mediatek / dts / mt7986a-zyxel-ex5700-telenor.dts
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/gpio/gpio.h>
7
8 #include "mt7986a.dtsi"
9
10 / {
11 model = "ZyXEL EX5700 (Telenor)";
12 compatible = "zyxel,ex5700-telenor", "mediatek,mt7986a";
13
14 aliases {
15 serial0 = &uart0;
16 ethernet0 = &gmac0;
17 led-boot = &led_status_green;
18 led-failsafe = &led_status_green;
19 led-running = &led_status_green;
20 led-upgrade = &led_status_amber;
21 };
22
23 chosen {
24 stdout-path = "serial0:115200n8";
25
26 // Stock U-Boot crashes unless /chosen/bootargs exists
27 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
28 };
29
30 memory {
31 reg = <0 0x40000000 0 0x40000000>;
32 };
33
34 reg_3p3v: regulator-3p3v {
35 compatible = "regulator-fixed";
36 regulator-name = "fixed-3.3V";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 regulator-boot-on;
40 regulator-always-on;
41 };
42
43 reg_5v: regulator-5v {
44 compatible = "regulator-fixed";
45 regulator-name = "fixed-5V";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
48 regulator-boot-on;
49 regulator-always-on;
50 };
51
52
53 keys {
54 compatible = "gpio-keys";
55 poll-interval = <20>;
56
57 reset-button {
58 label = "reset";
59 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
60 linux,code = <KEY_RESTART>;
61 };
62
63 wps-button {
64 label = "wps";
65 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
66 linux,code = <KEY_WPS_BUTTON>;
67 };
68 };
69
70 leds {
71 compatible = "gpio-leds";
72
73 red1 {
74 label = "red:net";
75 gpios = <&pio 23 GPIO_ACTIVE_HIGH>;
76 default-state = "off";
77 };
78
79 green1 {
80 label = "green:net";
81 gpios = <&pio 25 GPIO_ACTIVE_HIGH>;
82 default-state = "off";
83 };
84
85 amber1 {
86 label = "amber:net";
87 gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
88 default-state = "off";
89 };
90
91 white2 {
92 function = LED_FUNCTION_STATUS;
93 color = <LED_COLOR_ID_WHITE>;
94 gpios = <&pio 16 GPIO_ACTIVE_HIGH>;
95 default-state = "off";
96 };
97
98 red2 {
99 function = LED_FUNCTION_STATUS;
100 color = <LED_COLOR_ID_RED>;
101 gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
102 default-state = "off";
103 };
104
105 led_status_green: green2 {
106 function = LED_FUNCTION_STATUS;
107 color = <LED_COLOR_ID_GREEN>;
108 gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
109 default-state = "off";
110 };
111
112 led_status_amber: amber2 {
113 function = LED_FUNCTION_STATUS;
114 color = <LED_COLOR_ID_AMBER>;
115 gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
116 default-state = "off";
117 };
118 };
119
120 };
121
122 &eth {
123 status = "okay";
124 pinctrl-names = "default";
125 pinctrl-0 = <&eth_pins>;
126
127 gmac0: mac@0 {
128 compatible = "mediatek,eth-mac";
129 reg = <0>;
130 phy-mode = "2500base-x";
131
132 fixed-link {
133 speed = <2500>;
134 full-duplex;
135 pause;
136 };
137 };
138
139 mac@1 {
140 compatible = "mediatek,eth-mac";
141 reg = <1>;
142 label = "wan";
143 phy-mode = "2500base-x";
144 phy-handle = <&phy6>;
145 };
146
147 mdio: mdio-bus {
148 #address-cells = <1>;
149 #size-cells = <0>;
150 };
151 };
152
153 &mdio {
154 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
155 reset-delay-us = <50000>;
156 reset-post-delay-us = <20000>;
157
158 phy5: phy@5 {
159 compatible = "ethernet-phy-ieee802.3-c45";
160 reg = <5>;
161 };
162
163 phy6: phy@6 {
164 compatible = "ethernet-phy-ieee802.3-c45";
165 reg = <6>;
166 };
167
168 switch: switch@1f {
169 compatible = "mediatek,mt7531";
170 reg = <31>;
171 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
172 interrupt-controller;
173 #interrupt-cells = <1>;
174 interrupt-parent = <&pio>;
175 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
176 };
177 };
178
179 &switch {
180 ports {
181 #address-cells = <1>;
182 #size-cells = <0>;
183
184 port@0 {
185 reg = <0>;
186 label = "lan3";
187 };
188
189 port@1 {
190 reg = <1>;
191 label = "lan2";
192 };
193
194 port@2 {
195 reg = <2>;
196 label = "lan1";
197 };
198
199 port@5 {
200 reg = <5>;
201 label = "lan4";
202 phy-mode = "2500base-x";
203 phy-handle = <&phy5>;
204 };
205
206 port@6 {
207 reg = <6>;
208 ethernet = <&gmac0>;
209 phy-mode = "2500base-x";
210
211 fixed-link {
212 speed = <2500>;
213 full-duplex;
214 pause;
215 };
216 };
217 };
218 };
219
220 &crypto {
221 status = "okay";
222 };
223
224 &pcie {
225 pinctrl-names = "default";
226 pinctrl-0 = <&pcie_pins>;
227 status = "okay";
228
229 pcie@0,0 {
230 reg = <0x0000 0 0 0 0>;
231
232 wifi@0,0 {
233 compatible = "mediatek,mt76";
234 reg = <0x0000 0 0 0 0>;
235 mediatek,mtd-eeprom = <&factory 0xa0000>;
236 };
237 };
238 };
239
240 &pcie_phy {
241 status = "okay";
242 };
243
244 &watchdog {
245 status = "okay";
246 };
247
248 &wifi {
249 status = "okay";
250 pinctrl-names = "default";
251 pinctrl-0 = <&wf_5g_pins>;
252
253 mediatek,mtd-eeprom = <&factory 0x0>;
254 };
255
256 &pio {
257 eth_pins: eth-pins {
258 mux {
259 function = "eth";
260 groups = "switch_int", "mdc_mdio";
261 };
262 };
263
264 pcie_pins: pcie-pins {
265 mux {
266 function = "pcie";
267 groups = "pcie_pereset"; // "pcie_clk" and "pcie_wake" is unused?
268 };
269 };
270
271 spi_flash_pins: spi-flash-pins-33-to-38 {
272 mux {
273 function = "spi";
274 groups = "spi0", "spi0_wp_hold";
275 };
276 conf-pu {
277 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
278 drive-strength = <8>;
279 mediatek,pull-up-adv = <0>; /* bias-disable */
280 };
281 conf-pd {
282 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
283 drive-strength = <8>;
284 mediatek,pull-down-adv = <0>; /* bias-disable */
285 };
286 };
287
288 wf_5g_pins: wf_5g-pins {
289 mux {
290 function = "wifi";
291 groups = "wf_5g";
292 };
293 conf {
294 pins = "WF1_HB1", "WF1_HB2", "WF1_HB3", "WF1_HB4",
295 "WF1_HB0", "WF1_HB5", "WF1_HB6", "WF1_HB7",
296 "WF1_HB8", "WF1_TOP_CLK", "WF1_TOP_DATA";
297 drive-strength = <4>;
298 };
299 };
300
301 };
302
303 &spi0 {
304 pinctrl-names = "default";
305 pinctrl-0 = <&spi_flash_pins>;
306 cs-gpios = <0>, <0>;
307 status = "okay";
308
309 flash@0 {
310 compatible = "jedec,spi-nor";
311 reg = <0>;
312 spi-max-frequency = <20000000>;
313 };
314
315 flash@1 {
316 compatible = "spi-nand";
317 reg = <1>;
318
319 mediatek,nmbm;
320 mediatek,bmt-max-ratio = <1>;
321 mediatek,bmt-max-reserved-blocks = <64>;
322
323 spi-max-frequency = <20000000>;
324 spi-tx-bus-width = <4>;
325 spi-rx-bus-width = <4>;
326
327 partitions {
328 compatible = "fixed-partitions";
329 #address-cells = <1>;
330 #size-cells = <1>;
331
332 partition@0 {
333 label = "BL2";
334 reg = <0x000000 0x100000>;
335 read-only;
336 };
337 partition@100000 {
338 label = "u-boot-env";
339 reg = <0x100000 0x80000>;
340 };
341 factory: partition@180000 {
342 label = "Factory";
343 reg = <0x180000 0x200000>;
344 read-only;
345 };
346 partition@380000 {
347 label = "FIP";
348 reg = <0x380000 0x200000>;
349 read-only;
350 };
351 partition@580000 {
352 label = "ubi";
353 reg = <0x580000 0x1da80000>;
354 };
355 };
356 };
357 };
358
359 &ssusb {
360 vusb33-supply = <&reg_3p3v>;
361 vbus-supply = <&reg_5v>;
362 status = "okay";
363 };
364
365 &trng {
366 status = "okay";
367 };
368
369 &uart0 {
370 status = "okay";
371 };
372
373 &usb_phy {
374 status = "okay";
375 };