target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/leds/common.h>
   6
   7 #include "mt7986a.dtsi"
   8
   9 / {
  10         aliases {
  11                 serial0 = &uart0;
  12                 label-mac-device = &gmac0;
  13                 led-boot = &led_status_green;
  14                 led-failsafe = &led_status_red;
  15                 led-running = &led_status_green;
  16                 led-upgrade = &led_status_red;
  17         };
  18
  19         chosen {
  20                 stdout-path = "serial0:115200n8";
  21         };
  22
  23         memory {
  24                 reg = <0 0x40000000 0 0x20000000>;
  25         };
  26
  27         reg_3p3v: regulator-3p3v {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "fixed-3.3V";
  30                 regulator-min-microvolt = <3300000>;
  31                 regulator-max-microvolt = <3300000>;
  32                 regulator-boot-on;
  33                 regulator-always-on;
  34         };
  35
  36         reg_5v: regulator-5v {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "fixed-5V";
  39                 regulator-min-microvolt = <5000000>;
  40                 regulator-max-microvolt = <5000000>;
  41                 regulator-boot-on;
  42                 regulator-always-on;
  43         };
  44
  45         keys {
  46                 compatible = "gpio-keys";
  47
  48                 reset {
  49                         label = "reset";
  50                         linux,code = <KEY_RESTART>;
  51                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  52                 };
  53
  54                 wps {
  55                         label = "wps";
  56                         linux,code = <KEY_WPS_BUTTON>;
  57                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  58                 };
  59
  60                 turbo {
  61                         label = "turbo";
  62                         linux,code = <BTN_1>;
  63                         gpios = <&pio 11 GPIO_ACTIVE_LOW>;
  64                 };
  65         };
  66
  67         leds {
  68                 compatible = "gpio-leds";
  69
  70                 led_status_red: status_red {
  71                         function = LED_FUNCTION_STATUS;
  72                         color = <LED_COLOR_ID_RED>;
  73                         gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
  74                 };
  75
  76                 led_status_green: status_green {
  77                         function = LED_FUNCTION_STATUS;
  78                         color = <LED_COLOR_ID_GREEN>;
  79                         gpios = <&pio 8 GPIO_ACTIVE_HIGH>;
  80                 };
  81
  82                 turbo {
  83                         label = "green:turbo";
  84                         gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
  85                 };
  86         };
  87 };
  88
  89 &crypto {
  90         status = "okay";
  91 };
  92
  93 &eth {
  94         status = "okay";
  95
  96         gmac0: mac@0 {
  97                 compatible = "mediatek,eth-mac";
  98                 reg = <0>;
  99                 phy-mode = "2500base-x";
 100
 101                 nvmem-cells = <&macaddr_config_1c 0>;
 102                 nvmem-cell-names = "mac-address";
 103
 104                 fixed-link {
 105                         speed = <2500>;
 106                         full-duplex;
 107                         pause;
 108                 };
 109         };
 110
 111         gmac1: mac@1 {
 112                 compatible = "mediatek,eth-mac";
 113                 reg = <1>;
 114                 phy-handle = <&phy7>;
 115                 phy-mode = "2500base-x";
 116
 117                 nvmem-cells = <&macaddr_config_1c 1>;
 118                 nvmem-cell-names = "mac-address";
 119         };
 120
 121         mdio: mdio-bus {
 122                 #address-cells = <1>;
 123                 #size-cells = <0>;
 124         };
 125 };
 126
 127 &mdio {
 128         phy5: ethernet-phy@5 {
 129                 compatible = "ethernet-phy-ieee802.3-c45";
 130                 reg = <5>;
 131                 reset-assert-us = <100000>;
 132                 reset-deassert-us = <100000>;
 133                 reset-gpios = <&pio 13 GPIO_ACTIVE_LOW>;
 134                 realtek,aldps-enable;
 135         };
 136
 137         phy7: ethernet-phy@7 {
 138                 compatible = "ethernet-phy-ieee802.3-c45";
 139                 reg = <7>;
 140                 reset-assert-us = <100000>;
 141                 reset-deassert-us = <100000>;
 142                 reset-gpios = <&pio 17 GPIO_ACTIVE_LOW>;
 143                 realtek,aldps-enable;
 144         };
 145
 146         switch: switch@1f {
 147                 compatible = "mediatek,mt7531";
 148                 reg = <31>;
 149                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 150                 interrupt-controller;
 151                 #interrupt-cells = <1>;
 152                 interrupt-parent = <&pio>;
 153                 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
 154         };
 155 };
 156
 157 &spi0 {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&spi_flash_pins>;
 160         status = "okay";
 161
 162         flash@0 {
 163                 compatible = "spi-nand";
 164                 #address-cells = <1>;
 165                 #size-cells = <1>;
 166                 reg = <0>;
 167
 168                 spi-max-frequency = <20000000>;
 169                 spi-tx-bus-width = <4>;
 170                 spi-rx-bus-width = <4>;
 171
 172                 partitions {
 173                         compatible = "fixed-partitions";
 174                         #address-cells = <1>;
 175                         #size-cells = <1>;
 176
 177                         partition@0 {
 178                                 label = "bl2";
 179                                 reg = <0x000000 0x0100000>;
 180                                 read-only;
 181                         };
 182
 183                         config: partition@100000 {
 184                                 label = "config";
 185                                 reg = <0x100000 0x0060000>;
 186                                 read-only;
 187
 188                                 nvmem-layout {
 189                                         compatible = "fixed-layout";
 190                                         #address-cells = <1>;
 191                                         #size-cells = <1>;
 192
 193                                         macaddr_config_1c: macaddr@1c {
 194                                                 compatible = "mac-base";
 195                                                 reg = <0x1c 0x6>;
 196                                                 #nvmem-cell-cells = <1>;
 197                                         };
 198                                 };
 199                         };
 200
 201                         factory: partition@160000 {
 202                                 label = "factory";
 203                                 reg = <0x160000 0x0060000>;
 204                                 read-only;
 205                         };
 206
 207                         partition@1c0000 {
 208                                 label = "reserved";
 209                                 reg = <0x1c0000 0x01c0000>;
 210                                 read-only;
 211                         };
 212
 213                         partition@380000 {
 214                                 label = "fip";
 215                                 reg = <0x380000 0x0200000>;
 216                                 read-only;
 217                         };
 218
 219                         partition@580000 {
 220                                 label = "ubi";
 221                                 reg = <0x580000 0x7800000>;
 222                         };
 223                 };
 224         };
 225 };
 226
 227 &pio {
 228         spi_flash_pins: spi-flash-pins-33-to-38 {
 229                 mux {
 230                         function = "spi";
 231                         groups = "spi0", "spi0_wp_hold";
 232                 };
 233                 conf-pu {
 234                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 235                         drive-strength = <8>;
 236                         mediatek,pull-up-adv = <0>; /* bias-disable */
 237                 };
 238                 conf-pd {
 239                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 240                         drive-strength = <8>;
 241                         mediatek,pull-down-adv = <0>; /* bias-disable */
 242                 };
 243         };
 244 };
 245
 246 &ssusb {
 247         vusb33-supply = <&reg_3p3v>;
 248         vbus-supply = <&reg_5v>;
 249         status = "okay";
 250 };
 251
 252 &trng {
 253         status = "okay";
 254 };
 255
 256 &uart0 {
 257         status = "okay";
 258 };
 259
 260 &usb_phy {
 261         status = "okay";
 262 };
 263
 264 &watchdog {
 265         status = "okay";
 266 };
 267
 268 &wifi {
 269         mediatek,mtd-eeprom = <&factory 0x0>;
 270         nvmem-cells = <&macaddr_config_1c 2>;
 271         nvmem-cell-names = "mac-address";
 272         status = "okay";
 273 };