target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/leds/common.h>
   7
   8 #include "mt7986a.dtsi"
   9
  10 / {
  11         model = "ASUS TUF-AX6000";
  12         compatible = "asus,tuf-ax6000", "mediatek,mt7986a";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 led-boot = &led_system;
  17                 led-failsafe = &led_system;
  18                 led-running = &led_system;
  19                 led-upgrade = &led_system;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24                 bootargs-override = "ubi.mtd=UBI_DEV";
  25         };
  26
  27         memory {
  28                 reg = <0 0x40000000 0 0x20000000>;
  29         };
  30
  31         keys {
  32                 compatible = "gpio-keys";
  33
  34                 reset {
  35                         label = "reset";
  36                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  37                         linux,code = <KEY_RESTART>;
  38                 };
  39
  40                 mesh {
  41                         label = "wps";
  42                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  43                         linux,code = <KEY_WPS_BUTTON>;
  44                 };
  45         };
  46
  47         leds {
  48                 compatible = "gpio-leds";
  49
  50                 wlan {
  51                         function = LED_FUNCTION_WLAN;
  52                         color = <LED_COLOR_ID_WHITE>;
  53                         gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
  54                         linux,default-trigger = "phy1tpt";
  55                 };
  56
  57                 led_system: system {
  58                         label = "white:system";
  59                         gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
  60                 };
  61
  62                 wan-red {
  63                         function = LED_FUNCTION_WAN;
  64                         color = <LED_COLOR_ID_RED>;
  65                         gpios = <&pio 12 GPIO_ACTIVE_LOW>;
  66                 };
  67
  68                 cover-blue {
  69                         label = "blue:cover";
  70                         gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
  71                 };
  72         };
  73
  74         reg_3p3v: regulator-3p3v {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "fixed-3.3V";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 regulator-boot-on;
  80                 regulator-always-on;
  81         };
  82
  83         reg_5v: regulator-5v {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "fixed-5V";
  86                 regulator-min-microvolt = <5000000>;
  87                 regulator-max-microvolt = <5000000>;
  88                 regulator-boot-on;
  89                 regulator-always-on;
  90         };
  91 };
  92
  93 &crypto {
  94         status = "okay";
  95 };
  96
  97 &eth {
  98         status = "okay";
  99
 100         gmac0: mac@0 {
 101                 /* LAN */
 102                 compatible = "mediatek,eth-mac";
 103                 reg = <0>;
 104                 phy-mode = "2500base-x";
 105
 106                 fixed-link {
 107                         speed = <2500>;
 108                         full-duplex;
 109                         pause;
 110                 };
 111         };
 112
 113         gmac1: mac@1 {
 114                 /* WAN */
 115                 compatible = "mediatek,eth-mac";
 116                 reg = <1>;
 117                 phy-mode = "2500base-x";
 118                 phy-handle = <&phy6>;
 119         };
 120
 121         mdio: mdio-bus {
 122                 #address-cells = <1>;
 123                 #size-cells = <0>;
 124         };
 125 };
 126
 127 &mdio {
 128         reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 129         reset-delay-us = <50000>;
 130         reset-post-delay-us = <20000>;
 131
 132         phy5: phy@5 {
 133                 compatible = "ethernet-phy-ieee802.3-c45";
 134                 reg = <5>;
 135
 136                 mxl,led-drive-vdd;
 137                 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
 138         };
 139
 140         phy6: phy@6 {
 141                 compatible = "ethernet-phy-ieee802.3-c45";
 142                 reg = <6>;
 143
 144                 /* LED0: CONN (WAN white) */
 145                 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
 146         };
 147
 148         switch: switch@1f {
 149                 compatible = "mediatek,mt7531";
 150                 reg = <31>;
 151
 152                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 153                 reset-assert-us = <10000>;
 154                 reset-deassert-us = <10000>;
 155         };
 156 };
 157
 158 &pio {
 159         spi_flash_pins: spi-flash-pins-33-to-38 {
 160                 mux {
 161                         function = "spi";
 162                         groups = "spi0", "spi0_wp_hold";
 163                 };
 164                 conf-pu {
 165                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 166                         drive-strength = <8>;
 167                         mediatek,pull-up-adv = <0>; /* bias-disable */
 168                 };
 169                 conf-pd {
 170                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 171                         drive-strength = <8>;
 172                         mediatek,pull-down-adv = <0>; /* bias-disable */
 173                 };
 174         };
 175
 176         wf_2g_5g_pins: wf_2g_5g-pins {
 177                 mux {
 178                         function = "wifi";
 179                         groups = "wf_2g", "wf_5g";
 180                 };
 181                 conf {
 182                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 183                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 184                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 185                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 186                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 187                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 188                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 189                         drive-strength = <4>;
 190                 };
 191         };
 192
 193         wf_dbdc_pins: wf-dbdc-pins {
 194                 mux {
 195                         function = "wifi";
 196                         groups = "wf_dbdc";
 197                 };
 198                 conf {
 199                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 200                                 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 201                                 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 202                                 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 203                                 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 204                                 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 205                                 "WF1_TOP_CLK", "WF1_TOP_DATA";
 206                         drive-strength = <4>;
 207                 };
 208         };
 209 };
 210
 211 &pcie_phy {
 212         status = "okay";
 213 };
 214
 215 &spi0 {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&spi_flash_pins>;
 218         status = "okay";
 219
 220         spi_nand_flash: flash@0 {
 221                 compatible = "spi-nand";
 222                 #address-cells = <1>;
 223                 #size-cells = <1>;
 224                 reg = <0>;
 225
 226                 spi-max-frequency = <20000000>;
 227                 spi-tx-bus-width = <4>;
 228                 spi-rx-bus-width = <4>;
 229
 230                 partitions: partitions {
 231                         compatible = "fixed-partitions";
 232                         #address-cells = <1>;
 233                         #size-cells = <1>;
 234
 235                         partition@0 {
 236                                 label = "bootloader";
 237                                 reg = <0x0 0x400000>;
 238                                 read-only;
 239                         };
 240
 241                         partition@400000 {
 242                                 label = "UBI_DEV";
 243                                 reg = <0x400000 0xfc00000>;
 244                         };
 245                 };
 246         };
 247 };
 248
 249 &switch {
 250         ports {
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253
 254                 port@1 {
 255                         reg = <4>;
 256                         label = "lan1";
 257                 };
 258
 259                 port@2 {
 260                         reg = <3>;
 261                         label = "lan2";
 262                 };
 263
 264                 port@3 {
 265                         reg = <2>;
 266                         label = "lan3";
 267                 };
 268
 269                 port@4 {
 270                         reg = <1>;
 271                         label = "lan4";
 272                 };
 273
 274                 port@5 {
 275                         reg = <5>;
 276                         label = "lan5";
 277                         phy-mode = "2500base-x";
 278                         phy-handle = <&phy5>;
 279
 280                 };
 281
 282                 port@6 {
 283                         reg = <6>;
 284                         label = "cpu";
 285                         ethernet = <&gmac0>;
 286                         phy-mode = "2500base-x";
 287
 288                         fixed-link {
 289                                 speed = <2500>;
 290                                 full-duplex;
 291                                 pause;
 292                         };
 293                 };
 294         };
 295
 296         mdio {
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299
 300                 phy@1 {
 301                         reg = <1>;
 302
 303                         mediatek,led-config = <
 304                                 0x21 0x8009 /* BASIC_CTRL */
 305                                 0x22 0x0c00 /* ON_DURATION */
 306                                 0x23 0x1400 /* BLINK_DURATION */
 307                                 0x24 0x8000 /* LED0_ON_CTRL */
 308                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 309                                 0x26 0xc007 /* LED1_ON_CTRL */
 310                                 0x27 0x003f /* LED1_BLINK_CTRL */
 311                         >;
 312                 };
 313
 314                 phy@2 {
 315                         reg = <2>;
 316
 317                         mediatek,led-config = <
 318                                 0x21 0x8009 /* BASIC_CTRL */
 319                                 0x22 0x0c00 /* ON_DURATION */
 320                                 0x23 0x1400 /* BLINK_DURATION */
 321                                 0x24 0x8000 /* LED0_ON_CTRL */
 322                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 323                                 0x26 0xc007 /* LED1_ON_CTRL */
 324                                 0x27 0x003f /* LED1_BLINK_CTRL */
 325                         >;
 326                 };
 327
 328                 phy@3 {
 329                         reg = <3>;
 330
 331                         mediatek,led-config = <
 332                                 0x21 0x8009 /* BASIC_CTRL */
 333                                 0x22 0x0c00 /* ON_DURATION */
 334                                 0x23 0x1400 /* BLINK_DURATION */
 335                                 0x24 0x8000 /* LED0_ON_CTRL */
 336                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 337                                 0x26 0xc007 /* LED1_ON_CTRL */
 338                                 0x27 0x003f /* LED1_BLINK_CTRL */
 339                         >;
 340                 };
 341
 342                 phy@4 {
 343                         reg = <4>;
 344
 345                         mediatek,led-config = <
 346                                 0x21 0x8009 /* BASIC_CTRL */
 347                                 0x22 0x0c00 /* ON_DURATION */
 348                                 0x23 0x1400 /* BLINK_DURATION */
 349                                 0x24 0x8000 /* LED0_ON_CTRL */
 350                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 351                                 0x26 0xc007 /* LED1_ON_CTRL */
 352                                 0x27 0x003f /* LED1_BLINK_CTRL */
 353                         >;
 354                 };
 355         };
 356 };
 357
 358 &watchdog {
 359         status = "okay";
 360 };
 361
 362 &wifi {
 363         status = "okay";
 364         pinctrl-names = "default", "dbdc";
 365         pinctrl-0 = <&wf_2g_5g_pins>;
 366         pinctrl-1 = <&wf_dbdc_pins>;
 367 };
 368
 369 &trng {
 370         status = "okay";
 371 };
 372
 373 &uart0 {
 374         status = "okay";
 375 };
 376
 377 &ssusb {
 378         vusb33-supply = <&reg_3p3v>;
 379         vbus-supply = <&reg_5v>;
 380         status = "okay";
 381 };
 382
 383 &usb_phy {
 384         status = "okay";
 385 };