target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/leds/common.h>
   7
   8 #include "mt7986a.dtsi"
   9
  10 / {
  11         model = "ASUS TUF-AX4200";
  12         compatible = "asus,tuf-ax4200", "mediatek,mt7986a";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 led-boot = &led_system;
  17                 led-failsafe = &led_system;
  18                 led-running = &led_system;
  19                 led-upgrade = &led_system;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24                 bootargs-override = "ubi.mtd=UBI_DEV";
  25         };
  26
  27         memory {
  28                 reg = <0 0x40000000 0 0x20000000>;
  29         };
  30
  31         keys {
  32                 compatible = "gpio-keys";
  33
  34                 reset {
  35                         label = "reset";
  36                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  37                         linux,code = <KEY_RESTART>;
  38                 };
  39
  40                 mesh {
  41                         label = "wps";
  42                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  43                         linux,code = <KEY_WPS_BUTTON>;
  44                 };
  45         };
  46
  47         leds {
  48                 compatible = "gpio-leds";
  49
  50                 wlan24 {
  51                         label = "white:wlan24";
  52                         gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
  53                         linux,default-trigger = "phy0tpt";
  54                 };
  55
  56                 wlan5 {
  57                         label = "white:wlan5";
  58                         gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
  59                         linux,default-trigger = "phy1tpt";
  60                 };
  61
  62                 led_system: system {
  63                         label = "white:system";
  64                         gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
  65                 };
  66
  67                 wan-red {
  68                         function = LED_FUNCTION_WAN;
  69                         color = <LED_COLOR_ID_RED>;
  70                         gpios = <&pio 12 GPIO_ACTIVE_LOW>;
  71                 };
  72         };
  73
  74         reg_3p3v: regulator-3p3v {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "fixed-3.3V";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 regulator-boot-on;
  80                 regulator-always-on;
  81         };
  82
  83         reg_5v: regulator-5v {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "fixed-5V";
  86                 regulator-min-microvolt = <5000000>;
  87                 regulator-max-microvolt = <5000000>;
  88                 regulator-boot-on;
  89                 regulator-always-on;
  90         };
  91 };
  92
  93 &crypto {
  94         status = "okay";
  95 };
  96
  97 &eth {
  98         status = "okay";
  99
 100         gmac0: mac@0 {
 101                 /* LAN */
 102                 compatible = "mediatek,eth-mac";
 103                 reg = <0>;
 104                 phy-mode = "2500base-x";
 105
 106                 fixed-link {
 107                         speed = <2500>;
 108                         full-duplex;
 109                         pause;
 110                 };
 111         };
 112
 113         gmac1: mac@1 {
 114                 /* WAN */
 115                 compatible = "mediatek,eth-mac";
 116                 reg = <1>;
 117                 phy-mode = "2500base-x";
 118                 phy-handle = <&phy6>;
 119         };
 120
 121         mdio: mdio-bus {
 122                 #address-cells = <1>;
 123                 #size-cells = <0>;
 124         };
 125 };
 126
 127 &mdio {
 128         phy6: phy@6 {
 129                 compatible = "ethernet-phy-ieee802.3-c45";
 130                 reg = <6>;
 131
 132                 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 133                 reset-assert-us = <10000>;
 134                 reset-deassert-us = <10000>;
 135
 136                 /* LED0: CONN (WAN white) */
 137                 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
 138         };
 139
 140         switch: switch@1f {
 141                 compatible = "mediatek,mt7531";
 142                 reg = <31>;
 143
 144                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 145                 reset-assert-us = <10000>;
 146                 reset-deassert-us = <10000>;
 147         };
 148 };
 149
 150 &pio {
 151         spi_flash_pins: spi-flash-pins-33-to-38 {
 152                 mux {
 153                         function = "spi";
 154                         groups = "spi0", "spi0_wp_hold";
 155                 };
 156                 conf-pu {
 157                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 158                         drive-strength = <8>;
 159                         mediatek,pull-up-adv = <0>; /* bias-disable */
 160                 };
 161                 conf-pd {
 162                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 163                         drive-strength = <8>;
 164                         mediatek,pull-down-adv = <0>; /* bias-disable */
 165                 };
 166         };
 167
 168         wf_2g_5g_pins: wf_2g_5g-pins {
 169                 mux {
 170                         function = "wifi";
 171                         groups = "wf_2g", "wf_5g";
 172                 };
 173                 conf {
 174                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 175                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 176                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 177                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 178                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 179                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 180                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 181                         drive-strength = <4>;
 182                 };
 183         };
 184
 185         wf_dbdc_pins: wf-dbdc-pins {
 186                 mux {
 187                         function = "wifi";
 188                         groups = "wf_dbdc";
 189                 };
 190                 conf {
 191                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 192                                 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 193                                 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 194                                 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 195                                 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 196                                 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 197                                 "WF1_TOP_CLK", "WF1_TOP_DATA";
 198                         drive-strength = <4>;
 199                 };
 200         };
 201 };
 202
 203 &spi0 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&spi_flash_pins>;
 206         status = "okay";
 207
 208         spi_nand_flash: flash@0 {
 209                 compatible = "spi-nand";
 210                 #address-cells = <1>;
 211                 #size-cells = <1>;
 212                 reg = <0>;
 213
 214                 spi-max-frequency = <20000000>;
 215                 spi-tx-bus-width = <4>;
 216                 spi-rx-bus-width = <4>;
 217
 218                 partitions: partitions {
 219                         compatible = "fixed-partitions";
 220                         #address-cells = <1>;
 221                         #size-cells = <1>;
 222
 223                         partition@0 {
 224                                 label = "bootloader";
 225                                 reg = <0x0 0x400000>;
 226                                 read-only;
 227                         };
 228
 229                         partition@400000 {
 230                                 label = "UBI_DEV";
 231                                 reg = <0x400000 0xfc00000>;
 232                         };
 233                 };
 234         };
 235 };
 236
 237 &switch {
 238         ports {
 239                 #address-cells = <1>;
 240                 #size-cells = <0>;
 241
 242                 port@1 {
 243                         reg = <1>;
 244                         label = "lan1";
 245                 };
 246
 247                 port@2 {
 248                         reg = <2>;
 249                         label = "lan2";
 250                 };
 251
 252                 port@3 {
 253                         reg = <3>;
 254                         label = "lan3";
 255                 };
 256
 257                 port@4 {
 258                         reg = <4>;
 259                         label = "lan4";
 260                 };
 261
 262                 port@6 {
 263                         reg = <6>;
 264                         label = "cpu";
 265                         ethernet = <&gmac0>;
 266                         phy-mode = "2500base-x";
 267
 268                         fixed-link {
 269                                 speed = <2500>;
 270                                 full-duplex;
 271                                 pause;
 272                         };
 273                 };
 274         };
 275
 276         mdio {
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279
 280                 phy@1 {
 281                         reg = <1>;
 282
 283                         mediatek,led-config = <
 284                                 0x21 0x8009 /* BASIC_CTRL */
 285                                 0x22 0x0c00 /* ON_DURATION */
 286                                 0x23 0x1400 /* BLINK_DURATION */
 287                                 0x24 0x8000 /* LED0_ON_CTRL */
 288                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 289                                 0x26 0xc007 /* LED1_ON_CTRL */
 290                                 0x27 0x003f /* LED1_BLINK_CTRL */
 291                         >;
 292                 };
 293
 294                 phy@2 {
 295                         reg = <2>;
 296
 297                         mediatek,led-config = <
 298                                 0x21 0x8009 /* BASIC_CTRL */
 299                                 0x22 0x0c00 /* ON_DURATION */
 300                                 0x23 0x1400 /* BLINK_DURATION */
 301                                 0x24 0x8000 /* LED0_ON_CTRL */
 302                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 303                                 0x26 0xc007 /* LED1_ON_CTRL */
 304                                 0x27 0x003f /* LED1_BLINK_CTRL */
 305                         >;
 306                 };
 307
 308                 phy@3 {
 309                         reg = <3>;
 310
 311                         mediatek,led-config = <
 312                                 0x21 0x8009 /* BASIC_CTRL */
 313                                 0x22 0x0c00 /* ON_DURATION */
 314                                 0x23 0x1400 /* BLINK_DURATION */
 315                                 0x24 0x8000 /* LED0_ON_CTRL */
 316                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 317                                 0x26 0xc007 /* LED1_ON_CTRL */
 318                                 0x27 0x003f /* LED1_BLINK_CTRL */
 319                         >;
 320                 };
 321
 322                 phy@4 {
 323                         reg = <4>;
 324
 325                         mediatek,led-config = <
 326                                 0x21 0x8009 /* BASIC_CTRL */
 327                                 0x22 0x0c00 /* ON_DURATION */
 328                                 0x23 0x1400 /* BLINK_DURATION */
 329                                 0x24 0x8000 /* LED0_ON_CTRL */
 330                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 331                                 0x26 0xc007 /* LED1_ON_CTRL */
 332                                 0x27 0x003f /* LED1_BLINK_CTRL */
 333                         >;
 334                 };
 335         };
 336 };
 337
 338 &watchdog {
 339         status = "okay";
 340 };
 341
 342 &wifi {
 343         status = "okay";
 344         pinctrl-names = "default", "dbdc";
 345         pinctrl-0 = <&wf_2g_5g_pins>;
 346         pinctrl-1 = <&wf_dbdc_pins>;
 347 };
 348
 349 &trng {
 350         status = "okay";
 351 };
 352
 353 &uart0 {
 354         status = "okay";
 355 };
 356
 357 &ssusb {
 358         vusb33-supply = <&reg_3p3v>;
 359         vbus-supply = <&reg_5v>;
 360         status = "okay";
 361 };
 362
 363 &usb_phy {
 364         status = "okay";
 365 };