target/linux/generic/pending-5.15/728-net-mtk_sgmii-set-the-speed-according-to-the-phy-int.patch

   1 From 952b64575613d26163a5afa5ff8bfdb57840091b Mon Sep 17 00:00:00 2001
   2 From: Alexander Couzens <lynxis@fe80.eu>
   3 Date: Mon, 15 Aug 2022 15:00:14 +0200
   4 Subject: [PATCH 08/10] net: mtk_sgmii: set the speed according to the phy
   5  interface in AN
   6
   7 The non auto-negotioting code path is setting the correct speed for the
   8 interface. Ensure auto-negotiation code path is doing it as well.
   9
  10 Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
  11 ---
  12  drivers/net/ethernet/mediatek/mtk_sgmii.c | 11 +++++++++--
  13  1 file changed, 9 insertions(+), 2 deletions(-)
  14
  15 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  16 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  17 @@ -20,12 +20,14 @@ static struct mtk_pcs *pcs_to_mtk_pcs(st
  18  }
  19
  20  /* For SGMII interface mode */
  21 -static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
  22 +static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs, phy_interface_t interface)
  23  {
  24         unsigned int val;
  25
  26         regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
  27         val &= ~RG_PHY_SPEED_MASK;
  28 +       if (interface == PHY_INTERFACE_MODE_2500BASEX)
  29 +               val |= RG_PHY_SPEED_3_125G;
  30         regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
  31
  32         /* Setup the link timer and QPHY power up inside SGMIISYS */
  33 @@ -98,7 +100,7 @@ static int mtk_pcs_config(struct phylink
  34         if (interface != PHY_INTERFACE_MODE_SGMII)
  35                 err = mtk_pcs_setup_mode_force(mpcs, interface);
  36         else if (phylink_autoneg_inband(mode))
  37 -               err = mtk_pcs_setup_mode_an(mpcs);
  38 +               err = mtk_pcs_setup_mode_an(mpcs, interface);
  39
  40         /* Release PHYA power down state
  41          * Only removing bit SGMII_PHYA_PWD isn't enough.