target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch

   1 From 7f75f43fe2159123baa101fcc8c6faa0b0a4c598 Mon Sep 17 00:00:00 2001
   2 From: Alexander Couzens <lynxis@fe80.eu>
   3 Date: Sat, 13 Aug 2022 14:48:51 +0200
   4 Subject: [PATCH 05/10] net: mtk_sgmii: fix powering up the SGMII phy
   5
   6 There are certain race condition when the SGMII_PHYA_PWD register still
   7 contains 0x9 which prevents the SGMII from working properly.
   8
   9 The SGMII still shows link but no traffic can flow.
  10
  11 Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
  12 ---
  13  drivers/net/ethernet/mediatek/mtk_sgmii.c | 8 ++------
  14  1 file changed, 2 insertions(+), 6 deletions(-)
  15
  16 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  17 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  18 @@ -36,9 +36,7 @@ static int mtk_pcs_setup_mode_an(struct
  19         val |= SGMII_AN_RESTART;
  20         regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
  21
  22 -       regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
  23 -       val &= ~SGMII_PHYA_PWD;
  24 -       regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
  25 +       regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
  26
  27         return 0;
  28
  29 @@ -70,9 +68,7 @@ static int mtk_pcs_setup_mode_force(stru
  30         regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
  31
  32         /* Release PHYA power down state */
  33 -       regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
  34 -       val &= ~SGMII_PHYA_PWD;
  35 -       regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
  36 +       regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
  37
  38         return 0;
  39  }