target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6368-enetsw.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * BCM6368 Ethernet Switch Controller Driver
   4  *
   5  * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
   6  * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
   7  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/ethtool.h>
  15 #include <linux/if_vlan.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/of_clk.h>
  18 #include <linux/of_net.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_domain.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/reset.h>
  23
  24 /* MTU */
  25 #define ENETSW_TAG_SIZE                 6
  26 #define ENETSW_MTU_OVERHEAD             (VLAN_ETH_HLEN + VLAN_HLEN + \
  27                                          ENETSW_TAG_SIZE)
  28 #define ENETSW_FRAG_SIZE(x)             (SKB_DATA_ALIGN(NET_SKB_PAD + x + \
  29                                          SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
  30
  31 /* default number of descriptor */
  32 #define ENETSW_DEF_RX_DESC              64
  33 #define ENETSW_DEF_TX_DESC              32
  34 #define ENETSW_DEF_CPY_BREAK            128
  35
  36 /* maximum burst len for dma (4 bytes unit) */
  37 #define ENETSW_DMA_MAXBURST             8
  38
  39 /* DMA channels */
  40 #define DMA_CHAN_WIDTH                  0x10
  41
  42 /* Controller Configuration Register */
  43 #define DMA_CFG_REG                     0x0
  44 #define DMA_CFG_EN_SHIFT                0
  45 #define DMA_CFG_EN_MASK                 (1 << DMA_CFG_EN_SHIFT)
  46 #define DMA_CFG_FLOWCH_MASK(x)          (1 << ((x >> 1) + 1))
  47
  48 /* Flow Control Descriptor Low Threshold register */
  49 #define DMA_FLOWCL_REG(x)               (0x4 + (x) * 6)
  50
  51 /* Flow Control Descriptor High Threshold register */
  52 #define DMA_FLOWCH_REG(x)               (0x8 + (x) * 6)
  53
  54 /* Flow Control Descriptor Buffer Alloca Threshold register */
  55 #define DMA_BUFALLOC_REG(x)             (0xc + (x) * 6)
  56 #define DMA_BUFALLOC_FORCE_SHIFT        31
  57 #define DMA_BUFALLOC_FORCE_MASK         (1 << DMA_BUFALLOC_FORCE_SHIFT)
  58
  59 /* Channel Configuration register */
  60 #define DMAC_CHANCFG_REG                0x0
  61 #define DMAC_CHANCFG_EN_SHIFT           0
  62 #define DMAC_CHANCFG_EN_MASK            (1 << DMAC_CHANCFG_EN_SHIFT)
  63 #define DMAC_CHANCFG_PKTHALT_SHIFT      1
  64 #define DMAC_CHANCFG_PKTHALT_MASK       (1 << DMAC_CHANCFG_PKTHALT_SHIFT)
  65 #define DMAC_CHANCFG_BUFHALT_SHIFT      2
  66 #define DMAC_CHANCFG_BUFHALT_MASK       (1 << DMAC_CHANCFG_BUFHALT_SHIFT)
  67 #define DMAC_CHANCFG_CHAINING_SHIFT     2
  68 #define DMAC_CHANCFG_CHAINING_MASK      (1 << DMAC_CHANCFG_CHAINING_SHIFT)
  69 #define DMAC_CHANCFG_WRAP_EN_SHIFT      3
  70 #define DMAC_CHANCFG_WRAP_EN_MASK       (1 << DMAC_CHANCFG_WRAP_EN_SHIFT)
  71 #define DMAC_CHANCFG_FLOWC_EN_SHIFT     4
  72 #define DMAC_CHANCFG_FLOWC_EN_MASK      (1 << DMAC_CHANCFG_FLOWC_EN_SHIFT)
  73
  74 /* Interrupt Control/Status register */
  75 #define DMAC_IR_REG                     0x4
  76 #define DMAC_IR_BUFDONE_MASK            (1 << 0)
  77 #define DMAC_IR_PKTDONE_MASK            (1 << 1)
  78 #define DMAC_IR_NOTOWNER_MASK           (1 << 2)
  79
  80 /* Interrupt Mask register */
  81 #define DMAC_IRMASK_REG                 0x8
  82
  83 /* Maximum Burst Length */
  84 #define DMAC_MAXBURST_REG               0xc
  85
  86 /* Ring Start Address register */
  87 #define DMAS_RSTART_REG                 0x0
  88
  89 /* State Ram Word 2 */
  90 #define DMAS_SRAM2_REG                  0x4
  91
  92 /* State Ram Word 3 */
  93 #define DMAS_SRAM3_REG                  0x8
  94
  95 /* State Ram Word 4 */
  96 #define DMAS_SRAM4_REG                  0xc
  97
  98 struct bcm6368_enetsw_desc {
  99         u32 len_stat;
 100         u32 address;
 101 };
 102
 103 /* control */
 104 #define DMADESC_LENGTH_SHIFT            16
 105 #define DMADESC_LENGTH_MASK             (0xfff << DMADESC_LENGTH_SHIFT)
 106 #define DMADESC_OWNER_MASK              (1 << 15)
 107 #define DMADESC_EOP_MASK                (1 << 14)
 108 #define DMADESC_SOP_MASK                (1 << 13)
 109 #define DMADESC_ESOP_MASK               (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
 110 #define DMADESC_WRAP_MASK               (1 << 12)
 111 #define DMADESC_USB_NOZERO_MASK         (1 << 1)
 112 #define DMADESC_USB_ZERO_MASK           (1 << 0)
 113
 114 /* status */
 115 #define DMADESC_UNDER_MASK              (1 << 9)
 116 #define DMADESC_APPEND_CRC              (1 << 8)
 117 #define DMADESC_OVSIZE_MASK             (1 << 4)
 118 #define DMADESC_RXER_MASK               (1 << 2)
 119 #define DMADESC_CRC_MASK                (1 << 1)
 120 #define DMADESC_OV_MASK                 (1 << 0)
 121 #define DMADESC_ERR_MASK                (DMADESC_UNDER_MASK | \
 122                                          DMADESC_OVSIZE_MASK | \
 123                                          DMADESC_RXER_MASK | \
 124                                          DMADESC_CRC_MASK | \
 125                                          DMADESC_OV_MASK)
 126
 127 struct bcm6368_enetsw {
 128         void __iomem *dma_base;
 129         void __iomem *dma_chan;
 130         void __iomem *dma_sram;
 131
 132         struct device **pm;
 133         struct device_link **link_pm;
 134         int num_pms;
 135
 136         struct clk **clock;
 137         unsigned int num_clocks;
 138
 139         struct reset_control **reset;
 140         unsigned int num_resets;
 141
 142         int copybreak;
 143
 144         int irq_rx;
 145         int irq_tx;
 146
 147         /* hw view of rx & tx dma ring */
 148         dma_addr_t rx_desc_dma;
 149         dma_addr_t tx_desc_dma;
 150
 151         /* allocated size (in bytes) for rx & tx dma ring */
 152         unsigned int rx_desc_alloc_size;
 153         unsigned int tx_desc_alloc_size;
 154
 155         struct napi_struct napi;
 156
 157         /* dma channel id for rx */
 158         int rx_chan;
 159
 160         /* number of dma desc in rx ring */
 161         int rx_ring_size;
 162
 163         /* cpu view of rx dma ring */
 164         struct bcm6368_enetsw_desc *rx_desc_cpu;
 165
 166         /* current number of armed descriptor given to hardware for rx */
 167         int rx_desc_count;
 168
 169         /* next rx descriptor to fetch from hardware */
 170         int rx_curr_desc;
 171
 172         /* next dirty rx descriptor to refill */
 173         int rx_dirty_desc;
 174
 175         /* size of allocated rx buffer */
 176         unsigned int rx_buf_size;
 177
 178         /* size of allocated rx frag */
 179         unsigned int rx_frag_size;
 180
 181         /* list of buffer given to hw for rx */
 182         unsigned char **rx_buf;
 183
 184         /* used when rx buffer allocation failed, so we defer rx queue
 185          * refill */
 186         struct timer_list rx_timeout;
 187
 188         /* lock rx_timeout against rx normal operation */
 189         spinlock_t rx_lock;
 190
 191         /* dma channel id for tx */
 192         int tx_chan;
 193
 194         /* number of dma desc in tx ring */
 195         int tx_ring_size;
 196
 197         /* maximum dma burst size */
 198         int dma_maxburst;
 199
 200         /* cpu view of rx dma ring */
 201         struct bcm6368_enetsw_desc *tx_desc_cpu;
 202
 203         /* number of available descriptor for tx */
 204         int tx_desc_count;
 205
 206         /* next tx descriptor avaiable */
 207         int tx_curr_desc;
 208
 209         /* next dirty tx descriptor to reclaim */
 210         int tx_dirty_desc;
 211
 212         /* list of skb given to hw for tx */
 213         struct sk_buff **tx_skb;
 214
 215         /* lock used by tx reclaim and xmit */
 216         spinlock_t tx_lock;
 217
 218         /* network device reference */
 219         struct net_device *net_dev;
 220
 221         /* platform device reference */
 222         struct platform_device *pdev;
 223
 224         /* dma channel enable mask */
 225         u32 dma_chan_en_mask;
 226
 227         /* dma channel interrupt mask */
 228         u32 dma_chan_int_mask;
 229
 230         /* dma channel width */
 231         unsigned int dma_chan_width;
 232 };
 233
 234 static inline void dma_writel(struct bcm6368_enetsw *priv, u32 val, u32 off)
 235 {
 236         __raw_writel(val, priv->dma_base + off);
 237 }
 238
 239 static inline u32 dma_readl(struct bcm6368_enetsw *priv, u32 off, int chan)
 240 {
 241         return __raw_readl(priv->dma_chan + off + chan * priv->dma_chan_width);
 242 }
 243
 244 static inline void dmac_writel(struct bcm6368_enetsw *priv, u32 val,
 245                                     u32 off, int chan)
 246 {
 247         __raw_writel(val, priv->dma_chan + off + chan * priv->dma_chan_width);
 248 }
 249
 250 static inline void dmas_writel(struct bcm6368_enetsw *priv, u32 val,
 251                                     u32 off, int chan)
 252 {
 253         __raw_writel(val, priv->dma_sram + off + chan * priv->dma_chan_width);
 254 }
 255
 256 /*
 257  * refill rx queue
 258  */
 259 static int bcm6368_enetsw_refill_rx(struct net_device *dev, bool napi_mode)
 260 {
 261         struct bcm6368_enetsw *priv = netdev_priv(dev);
 262
 263         while (priv->rx_desc_count < priv->rx_ring_size) {
 264                 struct bcm6368_enetsw_desc *desc;
 265                 int desc_idx;
 266                 u32 len_stat;
 267
 268                 desc_idx = priv->rx_dirty_desc;
 269                 desc = &priv->rx_desc_cpu[desc_idx];
 270
 271                 if (!priv->rx_buf[desc_idx]) {
 272                         unsigned char *buf;
 273
 274                         if (likely(napi_mode))
 275                                 buf = napi_alloc_frag(priv->rx_frag_size);
 276                         else
 277                                 buf = netdev_alloc_frag(priv->rx_frag_size);
 278
 279                         if (unlikely(!buf))
 280                                 break;
 281
 282                         priv->rx_buf[desc_idx] = buf;
 283                         desc->address = dma_map_single(&priv->pdev->dev,
 284                                                        buf + NET_SKB_PAD,
 285                                                        priv->rx_buf_size,
 286                                                        DMA_FROM_DEVICE);
 287                 }
 288
 289                 len_stat = priv->rx_buf_size << DMADESC_LENGTH_SHIFT;
 290                 len_stat |= DMADESC_OWNER_MASK;
 291                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 292                         len_stat |= DMADESC_WRAP_MASK;
 293                         priv->rx_dirty_desc = 0;
 294                 } else {
 295                         priv->rx_dirty_desc++;
 296                 }
 297                 wmb();
 298                 desc->len_stat = len_stat;
 299
 300                 priv->rx_desc_count++;
 301
 302                 /* tell dma engine we allocated one buffer */
 303                 dma_writel(priv, 1, DMA_BUFALLOC_REG(priv->rx_chan));
 304         }
 305
 306         /* If rx ring is still empty, set a timer to try allocating
 307          * again at a later time. */
 308         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 309                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 310                 priv->rx_timeout.expires = jiffies + HZ;
 311                 add_timer(&priv->rx_timeout);
 312         }
 313
 314         return 0;
 315 }
 316
 317 /*
 318  * timer callback to defer refill rx queue in case we're OOM
 319  */
 320 static void bcm6368_enetsw_refill_rx_timer(struct timer_list *t)
 321 {
 322         struct bcm6368_enetsw *priv = from_timer(priv, t, rx_timeout);
 323         struct net_device *dev = priv->net_dev;
 324
 325         spin_lock(&priv->rx_lock);
 326         bcm6368_enetsw_refill_rx(dev, false);
 327         spin_unlock(&priv->rx_lock);
 328 }
 329
 330 /*
 331  * extract packet from rx queue
 332  */
 333 static int bcm6368_enetsw_receive_queue(struct net_device *dev, int budget)
 334 {
 335         struct bcm6368_enetsw *priv = netdev_priv(dev);
 336         struct device *kdev = &priv->pdev->dev;
 337         struct list_head rx_list;
 338         struct sk_buff *skb;
 339         int processed = 0;
 340
 341         INIT_LIST_HEAD(&rx_list);
 342
 343         /* don't scan ring further than number of refilled
 344          * descriptor */
 345         if (budget > priv->rx_desc_count)
 346                 budget = priv->rx_desc_count;
 347
 348         do {
 349                 struct bcm6368_enetsw_desc *desc;
 350                 unsigned int frag_size;
 351                 unsigned char *buf;
 352                 int desc_idx;
 353                 u32 len_stat;
 354                 unsigned int len;
 355
 356                 desc_idx = priv->rx_curr_desc;
 357                 desc = &priv->rx_desc_cpu[desc_idx];
 358
 359                 /* make sure we actually read the descriptor status at
 360                  * each loop */
 361                 rmb();
 362
 363                 len_stat = desc->len_stat;
 364
 365                 /* break if dma ownership belongs to hw */
 366                 if (len_stat & DMADESC_OWNER_MASK)
 367                         break;
 368
 369                 processed++;
 370                 priv->rx_curr_desc++;
 371                 if (priv->rx_curr_desc == priv->rx_ring_size)
 372                         priv->rx_curr_desc = 0;
 373
 374                 /* if the packet does not have start of packet _and_
 375                  * end of packet flag set, then just recycle it */
 376                 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
 377                         dev->stats.rx_dropped++;
 378                         continue;
 379                 }
 380
 381                 /* valid packet */
 382                 buf = priv->rx_buf[desc_idx];
 383                 len = (len_stat & DMADESC_LENGTH_MASK)
 384                       >> DMADESC_LENGTH_SHIFT;
 385                 /* don't include FCS */
 386                 len -= 4;
 387
 388                 if (len < priv->copybreak) {
 389                         unsigned int nfrag_size = ENETSW_FRAG_SIZE(len);
 390                         unsigned char *nbuf = napi_alloc_frag(nfrag_size);
 391
 392                         if (unlikely(!nbuf)) {
 393                                 /* forget packet, just rearm desc */
 394                                 dev->stats.rx_dropped++;
 395                                 continue;
 396                         }
 397
 398                         dma_sync_single_for_cpu(kdev, desc->address,
 399                                                 len, DMA_FROM_DEVICE);
 400                         memcpy(nbuf + NET_SKB_PAD, buf + NET_SKB_PAD, len);
 401                         dma_sync_single_for_device(kdev, desc->address,
 402                                                    len, DMA_FROM_DEVICE);
 403                         buf = nbuf;
 404                         frag_size = nfrag_size;
 405                 } else {
 406                         dma_unmap_single(kdev, desc->address,
 407                                          priv->rx_buf_size, DMA_FROM_DEVICE);
 408                         priv->rx_buf[desc_idx] = NULL;
 409                         frag_size = priv->rx_frag_size;
 410                 }
 411
 412                 skb = napi_build_skb(buf, frag_size);
 413                 if (unlikely(!skb)) {
 414                         skb_free_frag(buf);
 415                         dev->stats.rx_dropped++;
 416                         continue;
 417                 }
 418
 419                 skb_reserve(skb, NET_SKB_PAD);
 420                 skb_put(skb, len);
 421                 dev->stats.rx_packets++;
 422                 dev->stats.rx_bytes += len;
 423                 list_add_tail(&skb->list, &rx_list);
 424         } while (processed < budget);
 425
 426         list_for_each_entry(skb, &rx_list, list)
 427                 skb->protocol = eth_type_trans(skb, dev);
 428         netif_receive_skb_list(&rx_list);
 429         priv->rx_desc_count -= processed;
 430
 431         if (processed || !priv->rx_desc_count) {
 432                 bcm6368_enetsw_refill_rx(dev, true);
 433
 434                 /* kick rx dma */
 435                 dmac_writel(priv, priv->dma_chan_en_mask,
 436                             DMAC_CHANCFG_REG, priv->rx_chan);
 437         }
 438
 439         return processed;
 440 }
 441
 442 /*
 443  * try to or force reclaim of transmitted buffers
 444  */
 445 static int bcm6368_enetsw_tx_reclaim(struct net_device *dev, int force,
 446                                      int budget)
 447 {
 448         struct bcm6368_enetsw *priv = netdev_priv(dev);
 449         unsigned int bytes = 0;
 450         int released = 0;
 451
 452         while (priv->tx_desc_count < priv->tx_ring_size) {
 453                 struct bcm6368_enetsw_desc *desc;
 454                 struct sk_buff *skb;
 455
 456                 /* We run in a bh and fight against start_xmit, which
 457                  * is called with bh disabled */
 458                 spin_lock(&priv->tx_lock);
 459
 460                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 461
 462                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 463                         spin_unlock(&priv->tx_lock);
 464                         break;
 465                 }
 466
 467                 /* ensure other field of the descriptor were not read
 468                  * before we checked ownership */
 469                 rmb();
 470
 471                 skb = priv->tx_skb[priv->tx_dirty_desc];
 472                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 473                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 474                                  DMA_TO_DEVICE);
 475
 476                 priv->tx_dirty_desc++;
 477                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 478                         priv->tx_dirty_desc = 0;
 479                 priv->tx_desc_count++;
 480
 481                 spin_unlock(&priv->tx_lock);
 482
 483                 if (desc->len_stat & DMADESC_UNDER_MASK)
 484                         dev->stats.tx_errors++;
 485
 486                 bytes += skb->len;
 487                 napi_consume_skb(skb, budget);
 488                 released++;
 489         }
 490
 491         netdev_completed_queue(dev, released, bytes);
 492
 493         if (netif_queue_stopped(dev) && released)
 494                 netif_wake_queue(dev);
 495
 496         return released;
 497 }
 498
 499 /*
 500  * poll func, called by network core
 501  */
 502 static int bcm6368_enetsw_poll(struct napi_struct *napi, int budget)
 503 {
 504         struct bcm6368_enetsw *priv = container_of(napi, struct bcm6368_enetsw, napi);
 505         struct net_device *dev = priv->net_dev;
 506         int rx_work_done;
 507
 508         /* ack interrupts */
 509         dmac_writel(priv, priv->dma_chan_int_mask,
 510                          DMAC_IR_REG, priv->rx_chan);
 511         dmac_writel(priv, priv->dma_chan_int_mask,
 512                          DMAC_IR_REG, priv->tx_chan);
 513
 514         /* reclaim sent skb */
 515         bcm6368_enetsw_tx_reclaim(dev, 0, budget);
 516
 517         spin_lock(&priv->rx_lock);
 518         rx_work_done = bcm6368_enetsw_receive_queue(dev, budget);
 519         spin_unlock(&priv->rx_lock);
 520
 521         if (rx_work_done >= budget) {
 522                 /* rx queue is not yet empty/clean */
 523                 return rx_work_done;
 524         }
 525
 526         /* no more packet in rx/tx queue, remove device from poll
 527          * queue */
 528         napi_complete_done(napi, rx_work_done);
 529
 530         /* restore rx/tx interrupt */
 531         dmac_writel(priv, priv->dma_chan_int_mask,
 532                          DMAC_IRMASK_REG, priv->rx_chan);
 533         dmac_writel(priv, priv->dma_chan_int_mask,
 534                          DMAC_IRMASK_REG, priv->tx_chan);
 535
 536         return rx_work_done;
 537 }
 538
 539 /*
 540  * rx/tx dma interrupt handler
 541  */
 542 static irqreturn_t bcm6368_enetsw_isr_dma(int irq, void *dev_id)
 543 {
 544         struct net_device *dev = dev_id;
 545         struct bcm6368_enetsw *priv = netdev_priv(dev);
 546
 547         /* mask rx/tx interrupts */
 548         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 549         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 550
 551         napi_schedule(&priv->napi);
 552
 553         return IRQ_HANDLED;
 554 }
 555
 556 /*
 557  * tx request callback
 558  */
 559 static netdev_tx_t
 560 bcm6368_enetsw_start_xmit(struct sk_buff *skb, struct net_device *dev)
 561 {
 562         struct bcm6368_enetsw *priv = netdev_priv(dev);
 563         struct bcm6368_enetsw_desc *desc;
 564         u32 len_stat;
 565         netdev_tx_t ret;
 566
 567         /* lock against tx reclaim */
 568         spin_lock(&priv->tx_lock);
 569
 570         /* make sure the tx hw queue is not full, should not happen
 571          * since we stop queue before it's the case */
 572         if (unlikely(!priv->tx_desc_count)) {
 573                 netif_stop_queue(dev);
 574                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 575                         "available?\n");
 576                 ret = NETDEV_TX_BUSY;
 577                 goto out_unlock;
 578         }
 579
 580         /* pad small packets */
 581         if (skb->len < (ETH_ZLEN + ETH_FCS_LEN)) {
 582                 int needed = (ETH_ZLEN + ETH_FCS_LEN) - skb->len;
 583                 char *data;
 584
 585                 if (unlikely(skb_tailroom(skb) < needed)) {
 586                         struct sk_buff *nskb;
 587
 588                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 589                         if (!nskb) {
 590                                 ret = NETDEV_TX_BUSY;
 591                                 goto out_unlock;
 592                         }
 593
 594                         dev_kfree_skb(skb);
 595                         skb = nskb;
 596                 }
 597                 data = skb_put_zero(skb, needed);
 598         }
 599
 600         /* point to the next available desc */
 601         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 602         priv->tx_skb[priv->tx_curr_desc] = skb;
 603
 604         /* fill descriptor */
 605         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 606                                        DMA_TO_DEVICE);
 607
 608         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 609         len_stat |= DMADESC_ESOP_MASK | DMADESC_APPEND_CRC |
 610                     DMADESC_OWNER_MASK;
 611
 612         priv->tx_curr_desc++;
 613         if (priv->tx_curr_desc == priv->tx_ring_size) {
 614                 priv->tx_curr_desc = 0;
 615                 len_stat |= DMADESC_WRAP_MASK;
 616         }
 617         priv->tx_desc_count--;
 618
 619         /* dma might be already polling, make sure we update desc
 620          * fields in correct order */
 621         wmb();
 622         desc->len_stat = len_stat;
 623         wmb();
 624
 625         netdev_sent_queue(dev, skb->len);
 626
 627         /* kick tx dma */
 628         dmac_writel(priv, priv->dma_chan_en_mask, DMAC_CHANCFG_REG,
 629                     priv->tx_chan);
 630
 631         /* stop queue if no more desc available */
 632         if (!priv->tx_desc_count)
 633                 netif_stop_queue(dev);
 634
 635         dev->stats.tx_bytes += skb->len;
 636         dev->stats.tx_packets++;
 637         ret = NETDEV_TX_OK;
 638
 639 out_unlock:
 640         spin_unlock(&priv->tx_lock);
 641         return ret;
 642 }
 643
 644 /*
 645  * disable dma in given channel
 646  */
 647 static void bcm6368_enetsw_disable_dma(struct bcm6368_enetsw *priv, int chan)
 648 {
 649         int limit = 1000;
 650
 651         dmac_writel(priv, 0, DMAC_CHANCFG_REG, chan);
 652
 653         do {
 654                 u32 val;
 655
 656                 val = dma_readl(priv, DMAC_CHANCFG_REG, chan);
 657                 if (!(val & DMAC_CHANCFG_EN_MASK))
 658                         break;
 659
 660                 udelay(1);
 661         } while (limit--);
 662 }
 663
 664 static int bcm6368_enetsw_open(struct net_device *dev)
 665 {
 666         struct bcm6368_enetsw *priv = netdev_priv(dev);
 667         struct device *kdev = &priv->pdev->dev;
 668         int i, ret;
 669         unsigned int size;
 670         void *p;
 671         u32 val;
 672
 673         /* mask all interrupts and request them */
 674         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 675         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 676
 677         ret = request_irq(priv->irq_rx, bcm6368_enetsw_isr_dma,
 678                           0, dev->name, dev);
 679         if (ret)
 680                 goto out_freeirq;
 681
 682         if (priv->irq_tx != -1) {
 683                 ret = request_irq(priv->irq_tx, bcm6368_enetsw_isr_dma,
 684                                   0, dev->name, dev);
 685                 if (ret)
 686                         goto out_freeirq_rx;
 687         }
 688
 689         /* allocate rx dma ring */
 690         size = priv->rx_ring_size * sizeof(struct bcm6368_enetsw_desc);
 691         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 692         if (!p) {
 693                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
 694                 ret = -ENOMEM;
 695                 goto out_freeirq_tx;
 696         }
 697
 698         memset(p, 0, size);
 699         priv->rx_desc_alloc_size = size;
 700         priv->rx_desc_cpu = p;
 701
 702         /* allocate tx dma ring */
 703         size = priv->tx_ring_size * sizeof(struct bcm6368_enetsw_desc);
 704         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 705         if (!p) {
 706                 dev_err(kdev, "cannot allocate tx ring\n");
 707                 ret = -ENOMEM;
 708                 goto out_free_rx_ring;
 709         }
 710
 711         memset(p, 0, size);
 712         priv->tx_desc_alloc_size = size;
 713         priv->tx_desc_cpu = p;
 714
 715         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
 716                                GFP_KERNEL);
 717         if (!priv->tx_skb) {
 718                 dev_err(kdev, "cannot allocate tx skb queue\n");
 719                 ret = -ENOMEM;
 720                 goto out_free_tx_ring;
 721         }
 722
 723         priv->tx_desc_count = priv->tx_ring_size;
 724         priv->tx_dirty_desc = 0;
 725         priv->tx_curr_desc = 0;
 726         spin_lock_init(&priv->tx_lock);
 727
 728         /* init & fill rx ring with buffers */
 729         priv->rx_buf = kzalloc(sizeof(unsigned char *) * priv->rx_ring_size,
 730                                GFP_KERNEL);
 731         if (!priv->rx_buf) {
 732                 dev_err(kdev, "cannot allocate rx buffer queue\n");
 733                 ret = -ENOMEM;
 734                 goto out_free_tx_skb;
 735         }
 736
 737         priv->rx_desc_count = 0;
 738         priv->rx_dirty_desc = 0;
 739         priv->rx_curr_desc = 0;
 740
 741         /* initialize flow control buffer allocation */
 742         dma_writel(priv, DMA_BUFALLOC_FORCE_MASK | 0,
 743                    DMA_BUFALLOC_REG(priv->rx_chan));
 744
 745         if (bcm6368_enetsw_refill_rx(dev, false)) {
 746                 dev_err(kdev, "cannot allocate rx buffer queue\n");
 747                 ret = -ENOMEM;
 748                 goto out;
 749         }
 750
 751         /* write rx & tx ring addresses */
 752         dmas_writel(priv, priv->rx_desc_dma,
 753                     DMAS_RSTART_REG, priv->rx_chan);
 754         dmas_writel(priv, priv->tx_desc_dma,
 755                     DMAS_RSTART_REG, priv->tx_chan);
 756
 757         /* clear remaining state ram for rx & tx channel */
 758         dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->rx_chan);
 759         dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->tx_chan);
 760         dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->rx_chan);
 761         dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->tx_chan);
 762         dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->rx_chan);
 763         dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->tx_chan);
 764
 765         /* set dma maximum burst len */
 766         dmac_writel(priv, priv->dma_maxburst,
 767                     DMAC_MAXBURST_REG, priv->rx_chan);
 768         dmac_writel(priv, priv->dma_maxburst,
 769                     DMAC_MAXBURST_REG, priv->tx_chan);
 770
 771         /* set flow control low/high threshold to 1/3 / 2/3 */
 772         val = priv->rx_ring_size / 3;
 773         dma_writel(priv, val, DMA_FLOWCL_REG(priv->rx_chan));
 774         val = (priv->rx_ring_size * 2) / 3;
 775         dma_writel(priv, val, DMA_FLOWCH_REG(priv->rx_chan));
 776
 777         /* all set, enable mac and interrupts, start dma engine and
 778          * kick rx dma channel
 779          */
 780         wmb();
 781         dma_writel(priv, DMA_CFG_EN_MASK, DMA_CFG_REG);
 782         dmac_writel(priv, DMAC_CHANCFG_EN_MASK,
 783                     DMAC_CHANCFG_REG, priv->rx_chan);
 784
 785         /* watch "packet transferred" interrupt in rx and tx */
 786         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 787                     DMAC_IR_REG, priv->rx_chan);
 788         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 789                     DMAC_IR_REG, priv->tx_chan);
 790
 791         /* make sure we enable napi before rx interrupt  */
 792         napi_enable(&priv->napi);
 793
 794         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 795                     DMAC_IRMASK_REG, priv->rx_chan);
 796         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 797                     DMAC_IRMASK_REG, priv->tx_chan);
 798
 799         netif_carrier_on(dev);
 800         netif_start_queue(dev);
 801
 802         return 0;
 803
 804 out:
 805         for (i = 0; i < priv->rx_ring_size; i++) {
 806                 struct bcm6368_enetsw_desc *desc;
 807
 808                 if (!priv->rx_buf[i])
 809                         continue;
 810
 811                 desc = &priv->rx_desc_cpu[i];
 812                 dma_unmap_single(kdev, desc->address, priv->rx_buf_size,
 813                                  DMA_FROM_DEVICE);
 814                 skb_free_frag(priv->rx_buf[i]);
 815         }
 816         kfree(priv->rx_buf);
 817
 818 out_free_tx_skb:
 819         kfree(priv->tx_skb);
 820
 821 out_free_tx_ring:
 822         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
 823                           priv->tx_desc_cpu, priv->tx_desc_dma);
 824
 825 out_free_rx_ring:
 826         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
 827                           priv->rx_desc_cpu, priv->rx_desc_dma);
 828
 829 out_freeirq_tx:
 830         if (priv->irq_tx != -1)
 831                 free_irq(priv->irq_tx, dev);
 832
 833 out_freeirq_rx:
 834         free_irq(priv->irq_rx, dev);
 835
 836 out_freeirq:
 837         return ret;
 838 }
 839
 840 static int bcm6368_enetsw_stop(struct net_device *dev)
 841 {
 842         struct bcm6368_enetsw *priv = netdev_priv(dev);
 843         struct device *kdev = &priv->pdev->dev;
 844         int i;
 845
 846         netif_stop_queue(dev);
 847         napi_disable(&priv->napi);
 848         del_timer_sync(&priv->rx_timeout);
 849
 850         /* mask all interrupts */
 851         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 852         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 853
 854         /* disable dma & mac */
 855         bcm6368_enetsw_disable_dma(priv, priv->tx_chan);
 856         bcm6368_enetsw_disable_dma(priv, priv->rx_chan);
 857
 858         /* force reclaim of all tx buffers */
 859         bcm6368_enetsw_tx_reclaim(dev, 1, 0);
 860
 861         /* free the rx buffer ring */
 862         for (i = 0; i < priv->rx_ring_size; i++) {
 863                 struct bcm6368_enetsw_desc *desc;
 864
 865                 if (!priv->rx_buf[i])
 866                         continue;
 867
 868                 desc = &priv->rx_desc_cpu[i];
 869                 dma_unmap_single_attrs(kdev, desc->address, priv->rx_buf_size,
 870                                        DMA_FROM_DEVICE,
 871                                        DMA_ATTR_SKIP_CPU_SYNC);
 872                 skb_free_frag(priv->rx_buf[i]);
 873         }
 874
 875         /* free remaining allocated memory */
 876         kfree(priv->rx_buf);
 877         kfree(priv->tx_skb);
 878         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
 879                           priv->rx_desc_cpu, priv->rx_desc_dma);
 880         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
 881                           priv->tx_desc_cpu, priv->tx_desc_dma);
 882         if (priv->irq_tx != -1)
 883                 free_irq(priv->irq_tx, dev);
 884         free_irq(priv->irq_rx, dev);
 885
 886         netdev_reset_queue(dev);
 887
 888         return 0;
 889 }
 890
 891 static const struct net_device_ops bcm6368_enetsw_ops = {
 892         .ndo_open = bcm6368_enetsw_open,
 893         .ndo_stop = bcm6368_enetsw_stop,
 894         .ndo_start_xmit = bcm6368_enetsw_start_xmit,
 895 };
 896
 897 static int bcm6368_enetsw_probe(struct platform_device *pdev)
 898 {
 899         struct bcm6368_enetsw *priv;
 900         struct device *dev = &pdev->dev;
 901         struct device_node *node = dev->of_node;
 902         struct net_device *ndev;
 903         struct resource *res;
 904         unsigned i;
 905         int ret;
 906
 907         ndev = alloc_etherdev(sizeof(*priv));
 908         if (!ndev)
 909                 return -ENOMEM;
 910
 911         priv = netdev_priv(ndev);
 912
 913         priv->num_pms = of_count_phandle_with_args(node, "power-domains",
 914                                                    "#power-domain-cells");
 915         if (priv->num_pms > 1) {
 916                 priv->pm = devm_kcalloc(dev, priv->num_pms,
 917                                         sizeof(struct device *), GFP_KERNEL);
 918                 if (!priv->pm)
 919                         return -ENOMEM;
 920
 921                 priv->link_pm = devm_kcalloc(dev, priv->num_pms,
 922                                              sizeof(struct device_link *),
 923                                              GFP_KERNEL);
 924                 if (!priv->link_pm)
 925                         return -ENOMEM;
 926
 927                 for (i = 0; i < priv->num_pms; i++) {
 928                         priv->pm[i] = genpd_dev_pm_attach_by_id(dev, i);
 929                         if (IS_ERR(priv->pm[i])) {
 930                                 dev_err(dev, "error getting pm %d\n", i);
 931                                 return -EINVAL;
 932                         }
 933
 934                         priv->link_pm[i] = device_link_add(dev, priv->pm[i],
 935                                 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
 936                                 DL_FLAG_RPM_ACTIVE);
 937                 }
 938         }
 939
 940         pm_runtime_enable(dev);
 941         pm_runtime_no_callbacks(dev);
 942         ret = pm_runtime_get_sync(dev);
 943         if (ret < 0) {
 944                 pm_runtime_disable(dev);
 945                 dev_info(dev, "PM prober defer: ret=%d\n", ret);
 946                 return -EPROBE_DEFER;
 947         }
 948
 949         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
 950         priv->dma_base = devm_ioremap_resource(dev, res);
 951         if (IS_ERR(priv->dma_base))
 952                 return PTR_ERR(priv->dma_base);
 953
 954         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 955                                            "dma-channels");
 956         priv->dma_chan = devm_ioremap_resource(dev, res);
 957         if (IS_ERR(priv->dma_chan))
 958                 return PTR_ERR(priv->dma_chan);
 959
 960         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma-sram");
 961         priv->dma_sram = devm_ioremap_resource(dev, res);
 962         if (IS_ERR(priv->dma_sram))
 963                 return PTR_ERR(priv->dma_sram);
 964
 965         priv->irq_rx = platform_get_irq_byname(pdev, "rx");
 966         if (!priv->irq_rx)
 967                 return -ENODEV;
 968
 969         priv->irq_tx = platform_get_irq_byname(pdev, "tx");
 970         if (!priv->irq_tx)
 971                 return -ENODEV;
 972         else if (priv->irq_tx < 0)
 973                 priv->irq_tx = -1;
 974
 975         if (device_property_read_u32(dev, "dma-rx", &priv->rx_chan))
 976                 return -ENODEV;
 977
 978         if (device_property_read_u32(dev, "dma-tx", &priv->tx_chan))
 979                 return -ENODEV;
 980
 981         priv->rx_ring_size = ENETSW_DEF_RX_DESC;
 982         priv->tx_ring_size = ENETSW_DEF_TX_DESC;
 983
 984         priv->dma_maxburst = ENETSW_DMA_MAXBURST;
 985
 986         priv->copybreak = ENETSW_DEF_CPY_BREAK;
 987
 988         priv->dma_chan_en_mask = DMAC_CHANCFG_EN_MASK;
 989         priv->dma_chan_int_mask = DMAC_IR_PKTDONE_MASK;
 990         priv->dma_chan_width = DMA_CHAN_WIDTH;
 991
 992         of_get_mac_address(node, ndev->dev_addr);
 993         if (is_valid_ether_addr(ndev->dev_addr)) {
 994                 dev_info(dev, "mtd mac %pM\n", ndev->dev_addr);
 995         } else {
 996                 random_ether_addr(ndev->dev_addr);
 997                 dev_info(dev, "random mac %pM\n", ndev->dev_addr);
 998         }
 999
1000         priv->rx_buf_size = ALIGN(ndev->mtu + ENETSW_MTU_OVERHEAD,
1001                                   priv->dma_maxburst * 4);
1002
1003         priv->rx_frag_size = ENETSW_FRAG_SIZE(priv->rx_buf_size);
1004
1005         priv->num_clocks = of_clk_get_parent_count(node);
1006         if (priv->num_clocks) {
1007                 priv->clock = devm_kcalloc(dev, priv->num_clocks,
1008                                            sizeof(struct clk *), GFP_KERNEL);
1009                 if (!priv->clock)
1010                         return -ENOMEM;
1011         }
1012         for (i = 0; i < priv->num_clocks; i++) {
1013                 priv->clock[i] = of_clk_get(node, i);
1014                 if (IS_ERR(priv->clock[i])) {
1015                         dev_err(dev, "error getting clock %d\n", i);
1016                         return -EINVAL;
1017                 }
1018
1019                 ret = clk_prepare_enable(priv->clock[i]);
1020                 if (ret) {
1021                         dev_err(dev, "error enabling clock %d\n", i);
1022                         return ret;
1023                 }
1024         }
1025
1026         priv->num_resets = of_count_phandle_with_args(node, "resets",
1027                                                       "#reset-cells");
1028         if (priv->num_resets) {
1029                 priv->reset = devm_kcalloc(dev, priv->num_resets,
1030                                            sizeof(struct reset_control *),
1031                                            GFP_KERNEL);
1032                 if (!priv->reset)
1033                         return -ENOMEM;
1034         }
1035         for (i = 0; i < priv->num_resets; i++) {
1036                 priv->reset[i] = devm_reset_control_get_by_index(dev, i);
1037                 if (IS_ERR(priv->reset[i])) {
1038                         dev_err(dev, "error getting reset %d\n", i);
1039                         return -EINVAL;
1040                 }
1041
1042                 ret = reset_control_reset(priv->reset[i]);
1043                 if (ret) {
1044                         dev_err(dev, "error performing reset %d\n", i);
1045                         return ret;
1046                 }
1047         }
1048
1049         spin_lock_init(&priv->rx_lock);
1050
1051         timer_setup(&priv->rx_timeout, bcm6368_enetsw_refill_rx_timer, 0);
1052
1053         /* register netdevice */
1054         ndev->netdev_ops = &bcm6368_enetsw_ops;
1055         ndev->min_mtu = ETH_ZLEN;
1056         ndev->mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1057         ndev->max_mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1058         netif_napi_add(ndev, &priv->napi, bcm6368_enetsw_poll, 16);
1059         SET_NETDEV_DEV(ndev, dev);
1060
1061         ret = register_netdev(ndev);
1062         if (ret)
1063                 goto out_disable_clk;
1064
1065         netif_carrier_off(ndev);
1066         platform_set_drvdata(pdev, ndev);
1067         priv->pdev = pdev;
1068         priv->net_dev = ndev;
1069
1070         return 0;
1071
1072 out_disable_clk:
1073         for (i = 0; i < priv->num_resets; i++)
1074                 reset_control_assert(priv->reset[i]);
1075
1076         for (i = 0; i < priv->num_clocks; i++)
1077                 clk_disable_unprepare(priv->clock[i]);
1078
1079         return ret;
1080 }
1081
1082 static int bcm6368_enetsw_remove(struct platform_device *pdev)
1083 {
1084         struct device *dev = &pdev->dev;
1085         struct net_device *ndev = platform_get_drvdata(pdev);
1086         struct bcm6368_enetsw *priv = netdev_priv(ndev);
1087         unsigned int i;
1088
1089         unregister_netdev(ndev);
1090
1091         pm_runtime_put_sync(dev);
1092         for (i = 0; priv->pm && i < priv->num_pms; i++) {
1093                 dev_pm_domain_detach(priv->pm[i], true);
1094                 device_link_del(priv->link_pm[i]);
1095         }
1096
1097         for (i = 0; i < priv->num_resets; i++)
1098                 reset_control_assert(priv->reset[i]);
1099
1100         for (i = 0; i < priv->num_clocks; i++)
1101                 clk_disable_unprepare(priv->clock[i]);
1102
1103         free_netdev(ndev);
1104
1105         return 0;
1106 }
1107
1108 static const struct of_device_id bcm6368_enetsw_of_match[] = {
1109         { .compatible = "brcm,bcm6318-enetsw", },
1110         { .compatible = "brcm,bcm6328-enetsw", },
1111         { .compatible = "brcm,bcm6362-enetsw", },
1112         { .compatible = "brcm,bcm6368-enetsw", },
1113         { .compatible = "brcm,bcm63268-enetsw", },
1114         { /* sentinel */ }
1115 };
1116 MODULE_DEVICE_TABLE(of, bcm6368_enetsw_of_match);
1117
1118 static struct platform_driver bcm6368_enetsw_driver = {
1119         .driver = {
1120                 .name = "bcm6368-enetsw",
1121                 .of_match_table = of_match_ptr(bcm6368_enetsw_of_match),
1122         },
1123         .probe  = bcm6368_enetsw_probe,
1124         .remove = bcm6368_enetsw_remove,
1125 };
1126 module_platform_driver(bcm6368_enetsw_driver);