plat/st/stm32mp1/stm32mp1_pm.c

   1 /*
   2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8 #include <errno.h>
   9
  10 #include <platform_def.h>
  11
  12 #include <arch_helpers.h>
  13 #include <common/debug.h>
  14 #include <drivers/arm/gic_common.h>
  15 #include <drivers/arm/gicv2.h>
  16 #include <drivers/st/stm32mp1_clk.h>
  17 #include <dt-bindings/clock/stm32mp1-clks.h>
  18 #include <lib/mmio.h>
  19 #include <lib/psci/psci.h>
  20 #include <plat/common/platform.h>
  21
  22 static uintptr_t stm32_sec_entrypoint;
  23 static uint32_t cntfrq_core0;
  24
  25 /*******************************************************************************
  26  * STM32MP1 handler called when a CPU is about to enter standby.
  27  * call by core 1 to enter in wfi
  28  ******************************************************************************/
  29 static void stm32_cpu_standby(plat_local_state_t cpu_state)
  30 {
  31         uint32_t interrupt = GIC_SPURIOUS_INTERRUPT;
  32
  33         assert(cpu_state == ARM_LOCAL_STATE_RET);
  34
  35         /*
  36          * Enter standby state
  37          * dsb is good practice before using wfi to enter low power states
  38          */
  39         isb();
  40         dsb();
  41         while (interrupt == GIC_SPURIOUS_INTERRUPT) {
  42                 wfi();
  43
  44                 /* Acknoledge IT */
  45                 interrupt = gicv2_acknowledge_interrupt();
  46                 /* If Interrupt == 1022 it will be acknowledged by non secure */
  47                 if ((interrupt != PENDING_G1_INTID) &&
  48                     (interrupt != GIC_SPURIOUS_INTERRUPT)) {
  49                         gicv2_end_of_interrupt(interrupt);
  50                 }
  51         }
  52 }
  53
  54 /*******************************************************************************
  55  * STM32MP1 handler called when a power domain is about to be turned on. The
  56  * mpidr determines the CPU to be turned on.
  57  * call by core 0 to activate core 1
  58  ******************************************************************************/
  59 static int stm32_pwr_domain_on(u_register_t mpidr)
  60 {
  61         unsigned long current_cpu_mpidr = read_mpidr_el1();
  62         uint32_t tamp_clk_off = 0;
  63         uint32_t bkpr_core1_addr =
  64                 tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX);
  65         uint32_t bkpr_core1_magic =
  66                 tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX);
  67
  68         if (mpidr == current_cpu_mpidr) {
  69                 return PSCI_E_INVALID_PARAMS;
  70         }
  71
  72         if ((stm32_sec_entrypoint < STM32MP_SYSRAM_BASE) ||
  73             (stm32_sec_entrypoint > (STM32MP_SYSRAM_BASE +
  74                                      (STM32MP_SYSRAM_SIZE - 1)))) {
  75                 return PSCI_E_INVALID_ADDRESS;
  76         }
  77
  78         if (!stm32mp_clk_is_enabled(RTCAPB)) {
  79                 tamp_clk_off = 1;
  80                 if (stm32mp_clk_enable(RTCAPB) != 0) {
  81                         panic();
  82                 }
  83         }
  84
  85         cntfrq_core0 = read_cntfrq_el0();
  86
  87         /* Write entrypoint in backup RAM register */
  88         mmio_write_32(bkpr_core1_addr, stm32_sec_entrypoint);
  89
  90         /* Write magic number in backup register */
  91         mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER);
  92
  93         if (tamp_clk_off != 0U) {
  94                 if (stm32mp_clk_disable(RTCAPB) != 0) {
  95                         panic();
  96                 }
  97         }
  98
  99         /* Generate an IT to core 1 */
 100         gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP_SECONDARY_CPU);
 101
 102         return PSCI_E_SUCCESS;
 103 }
 104
 105 /*******************************************************************************
 106  * STM32MP1 handler called when a power domain is about to be turned off. The
 107  * target_state encodes the power state that each level should transition to.
 108  ******************************************************************************/
 109 static void stm32_pwr_domain_off(const psci_power_state_t *target_state)
 110 {
 111         /* Nothing to do */
 112 }
 113
 114 /*******************************************************************************
 115  * STM32MP1 handler called when a power domain is about to be suspended. The
 116  * target_state encodes the power state that each level should transition to.
 117  ******************************************************************************/
 118 static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state)
 119 {
 120         /* Nothing to do, power domain is not disabled */
 121 }
 122
 123 /*******************************************************************************
 124  * STM32MP1 handler called when a power domain has just been powered on after
 125  * being turned off earlier. The target_state encodes the low power state that
 126  * each level has woken up from.
 127  * call by core 1 just after wake up
 128  ******************************************************************************/
 129 static void stm32_pwr_domain_on_finish(const psci_power_state_t *target_state)
 130 {
 131         stm32mp1_gic_pcpu_init();
 132
 133         write_cntfrq_el0(cntfrq_core0);
 134 }
 135
 136 /*******************************************************************************
 137  * STM32MP1 handler called when a power domain has just been powered on after
 138  * having been suspended earlier. The target_state encodes the low power state
 139  * that each level has woken up from.
 140  ******************************************************************************/
 141 static void stm32_pwr_domain_suspend_finish(const psci_power_state_t
 142                                             *target_state)
 143 {
 144         /* Nothing to do, power domain is not disabled */
 145 }
 146
 147 static void __dead2 stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t
 148                                                   *target_state)
 149 {
 150         ERROR("stm32mpu1 Power Down WFI: operation not handled.\n");
 151         panic();
 152 }
 153
 154 static void __dead2 stm32_system_off(void)
 155 {
 156         ERROR("stm32mpu1 System Off: operation not handled.\n");
 157         panic();
 158 }
 159
 160 static void __dead2 stm32_system_reset(void)
 161 {
 162         mmio_setbits_32(RCC_BASE + RCC_MP_GRSTCSETR, RCC_MP_GRSTCSETR_MPSYSRST);
 163
 164         /* Loop in case system reset is not immediately caught */
 165         for ( ; ; ) {
 166                 ;
 167         }
 168 }
 169
 170 static int stm32_validate_power_state(unsigned int power_state,
 171                                       psci_power_state_t *req_state)
 172 {
 173         int pstate = psci_get_pstate_type(power_state);
 174
 175         if (pstate != 0) {
 176                 return PSCI_E_INVALID_PARAMS;
 177         }
 178
 179         if (psci_get_pstate_pwrlvl(power_state)) {
 180                 return PSCI_E_INVALID_PARAMS;
 181         }
 182
 183         if (psci_get_pstate_id(power_state)) {
 184                 return PSCI_E_INVALID_PARAMS;
 185         }
 186
 187         req_state->pwr_domain_state[0] = ARM_LOCAL_STATE_RET;
 188         req_state->pwr_domain_state[1] = ARM_LOCAL_STATE_RUN;
 189
 190         return PSCI_E_SUCCESS;
 191 }
 192
 193 static int stm32_validate_ns_entrypoint(uintptr_t entrypoint)
 194 {
 195         /* The non-secure entry point must be in DDR */
 196         if (entrypoint < STM32MP_DDR_BASE) {
 197                 return PSCI_E_INVALID_ADDRESS;
 198         }
 199
 200         return PSCI_E_SUCCESS;
 201 }
 202
 203 static int stm32_node_hw_state(u_register_t target_cpu,
 204                                unsigned int power_level)
 205 {
 206         /*
 207          * The format of 'power_level' is implementation-defined, but 0 must
 208          * mean a CPU. Only allow level 0.
 209          */
 210         if (power_level != MPIDR_AFFLVL0) {
 211                 return PSCI_E_INVALID_PARAMS;
 212         }
 213
 214         /*
 215          * From psci view the CPU 0 is always ON,
 216          * CPU 1 can be SUSPEND or RUNNING.
 217          * Therefore do not manage POWER OFF state and always return HW_ON.
 218          */
 219
 220         return (int)HW_ON;
 221 }
 222
 223 /*******************************************************************************
 224  * Export the platform handlers. The ARM Standard platform layer will take care
 225  * of registering the handlers with PSCI.
 226  ******************************************************************************/
 227 static const plat_psci_ops_t stm32_psci_ops = {
 228         .cpu_standby = stm32_cpu_standby,
 229         .pwr_domain_on = stm32_pwr_domain_on,
 230         .pwr_domain_off = stm32_pwr_domain_off,
 231         .pwr_domain_suspend = stm32_pwr_domain_suspend,
 232         .pwr_domain_on_finish = stm32_pwr_domain_on_finish,
 233         .pwr_domain_suspend_finish = stm32_pwr_domain_suspend_finish,
 234         .pwr_domain_pwr_down_wfi = stm32_pwr_domain_pwr_down_wfi,
 235         .system_off = stm32_system_off,
 236         .system_reset = stm32_system_reset,
 237         .validate_power_state = stm32_validate_power_state,
 238         .validate_ns_entrypoint = stm32_validate_ns_entrypoint,
 239         .get_node_hw_state = stm32_node_hw_state
 240 };
 241
 242 /*******************************************************************************
 243  * Export the platform specific power ops.
 244  ******************************************************************************/
 245 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
 246                         const plat_psci_ops_t **psci_ops)
 247 {
 248         stm32_sec_entrypoint = sec_entrypoint;
 249         *psci_ops = &stm32_psci_ops;
 250
 251         return 0;
 252 }