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GICv3 driver: Fix support for full SPI range
[project/bcm63xx/atf.git] / drivers / arm / gic / v3 / gicv3_main.c
1 /*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch.h>
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <common/interrupt_props.h>
13 #include <drivers/arm/gicv3.h>
14 #include <lib/spinlock.h>
15
16 #include "gicv3_private.h"
17
18 const gicv3_driver_data_t *gicv3_driver_data;
19 static unsigned int gicv2_compat;
20
21 /*
22 * Spinlock to guard registers needing read-modify-write. APIs protected by this
23 * spinlock are used either at boot time (when only a single CPU is active), or
24 * when the system is fully coherent.
25 */
26 static spinlock_t gic_lock;
27
28 /*
29 * Redistributor power operations are weakly bound so that they can be
30 * overridden
31 */
32 #pragma weak gicv3_rdistif_off
33 #pragma weak gicv3_rdistif_on
34
35
36 /* Helper macros to save and restore GICD registers to and from the context */
37 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \
38 do { \
39 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
40 int_id += (1U << REG##_SHIFT)) { \
41 gicd_write_##reg(base, int_id, \
42 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \
43 } \
44 } while (false)
45
46 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \
47 do { \
48 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
49 int_id += (1U << REG##_SHIFT)) { \
50 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\
51 gicd_read_##reg(base, int_id); \
52 } \
53 } while (false)
54
55
56 /*******************************************************************************
57 * This function initialises the ARM GICv3 driver in EL3 with provided platform
58 * inputs.
59 ******************************************************************************/
60 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
61 {
62 unsigned int gic_version;
63
64 assert(plat_driver_data != NULL);
65 assert(plat_driver_data->gicd_base != 0U);
66 assert(plat_driver_data->gicr_base != 0U);
67 assert(plat_driver_data->rdistif_num != 0U);
68 assert(plat_driver_data->rdistif_base_addrs != NULL);
69
70 assert(IS_IN_EL3());
71
72 assert(plat_driver_data->interrupt_props_num > 0 ?
73 plat_driver_data->interrupt_props != NULL : 1);
74
75 /* Check for system register support */
76 #ifdef __aarch64__
77 assert((read_id_aa64pfr0_el1() &
78 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
79 #else
80 assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
81 #endif /* __aarch64__ */
82
83 /* The GIC version should be 3.0 */
84 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
85 gic_version >>= PIDR2_ARCH_REV_SHIFT;
86 gic_version &= PIDR2_ARCH_REV_MASK;
87 assert(gic_version == ARCH_REV_GICV3);
88
89 /*
90 * Find out whether the GIC supports the GICv2 compatibility mode. The
91 * ARE_S bit resets to 0 if supported
92 */
93 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base);
94 gicv2_compat >>= CTLR_ARE_S_SHIFT;
95 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK);
96
97 /*
98 * Find the base address of each implemented Redistributor interface.
99 * The number of interfaces should be equal to the number of CPUs in the
100 * system. The memory for saving these addresses has to be allocated by
101 * the platform port
102 */
103 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs,
104 plat_driver_data->rdistif_num,
105 plat_driver_data->gicr_base,
106 plat_driver_data->mpidr_to_core_pos);
107
108 gicv3_driver_data = plat_driver_data;
109
110 /*
111 * The GIC driver data is initialized by the primary CPU with caches
112 * enabled. When the secondary CPU boots up, it initializes the
113 * GICC/GICR interface with the caches disabled. Hence flush the
114 * driver data to ensure coherency. This is not required if the
115 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
116 * enabled.
117 */
118 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
119 flush_dcache_range((uintptr_t) &gicv3_driver_data,
120 sizeof(gicv3_driver_data));
121 flush_dcache_range((uintptr_t) gicv3_driver_data,
122 sizeof(*gicv3_driver_data));
123 #endif
124
125 INFO("GICv3 %s legacy support detected."
126 " ARM GICV3 driver initialized in EL3\n",
127 gicv2_compat ? "with" : "without");
128 }
129
130 /*******************************************************************************
131 * This function initialises the GIC distributor interface based upon the data
132 * provided by the platform while initialising the driver.
133 ******************************************************************************/
134 void __init gicv3_distif_init(void)
135 {
136 unsigned int bitmap = 0;
137
138 assert(gicv3_driver_data != NULL);
139 assert(gicv3_driver_data->gicd_base != 0U);
140
141 assert(IS_IN_EL3());
142
143 /*
144 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
145 * the ARE_S bit. The Distributor might generate a system error
146 * otherwise.
147 */
148 gicd_clr_ctlr(gicv3_driver_data->gicd_base,
149 CTLR_ENABLE_G0_BIT |
150 CTLR_ENABLE_G1S_BIT |
151 CTLR_ENABLE_G1NS_BIT,
152 RWP_TRUE);
153
154 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
155 gicd_set_ctlr(gicv3_driver_data->gicd_base,
156 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
157
158 /* Set the default attribute of all SPIs */
159 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base);
160
161 bitmap = gicv3_secure_spis_config_props(
162 gicv3_driver_data->gicd_base,
163 gicv3_driver_data->interrupt_props,
164 gicv3_driver_data->interrupt_props_num);
165
166 /* Enable the secure SPIs now that they have been configured */
167 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
168 }
169
170 /*******************************************************************************
171 * This function initialises the GIC Redistributor interface of the calling CPU
172 * (identified by the 'proc_num' parameter) based upon the data provided by the
173 * platform while initialising the driver.
174 ******************************************************************************/
175 void gicv3_rdistif_init(unsigned int proc_num)
176 {
177 uintptr_t gicr_base;
178 unsigned int bitmap = 0U;
179 uint32_t ctlr;
180
181 assert(gicv3_driver_data != NULL);
182 assert(proc_num < gicv3_driver_data->rdistif_num);
183 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
184 assert(gicv3_driver_data->gicd_base != 0U);
185
186 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base);
187 assert((ctlr & CTLR_ARE_S_BIT) != 0U);
188
189 assert(IS_IN_EL3());
190
191 /* Power on redistributor */
192 gicv3_rdistif_on(proc_num);
193
194 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
195
196 /* Set the default attribute of all SGIs and PPIs */
197 gicv3_ppi_sgi_config_defaults(gicr_base);
198
199 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
200 gicv3_driver_data->interrupt_props,
201 gicv3_driver_data->interrupt_props_num);
202
203 /* Enable interrupt groups as required, if not already */
204 if ((ctlr & bitmap) != bitmap)
205 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
206 }
207
208 /*******************************************************************************
209 * Functions to perform power operations on GIC Redistributor
210 ******************************************************************************/
211 void gicv3_rdistif_off(unsigned int proc_num)
212 {
213 return;
214 }
215
216 void gicv3_rdistif_on(unsigned int proc_num)
217 {
218 return;
219 }
220
221 /*******************************************************************************
222 * This function enables the GIC CPU interface of the calling CPU using only
223 * system register accesses.
224 ******************************************************************************/
225 void gicv3_cpuif_enable(unsigned int proc_num)
226 {
227 uintptr_t gicr_base;
228 unsigned int scr_el3;
229 unsigned int icc_sre_el3;
230
231 assert(gicv3_driver_data != NULL);
232 assert(proc_num < gicv3_driver_data->rdistif_num);
233 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
234 assert(IS_IN_EL3());
235
236 /* Mark the connected core as awake */
237 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
238 gicv3_rdistif_mark_core_awake(gicr_base);
239
240 /* Disable the legacy interrupt bypass */
241 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT;
242
243 /*
244 * Enable system register access for EL3 and allow lower exception
245 * levels to configure the same for themselves. If the legacy mode is
246 * not supported, the SRE bit is RAO/WI
247 */
248 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
249 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
250
251 scr_el3 = (uint32_t) read_scr_el3();
252
253 /*
254 * Switch to NS state to write Non secure ICC_SRE_EL1 and
255 * ICC_SRE_EL2 registers.
256 */
257 write_scr_el3(scr_el3 | SCR_NS_BIT);
258 isb();
259
260 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3);
261 write_icc_sre_el1(ICC_SRE_SRE_BIT);
262 isb();
263
264 /* Switch to secure state. */
265 write_scr_el3(scr_el3 & (~SCR_NS_BIT));
266 isb();
267
268 /* Write the secure ICC_SRE_EL1 register */
269 write_icc_sre_el1(ICC_SRE_SRE_BIT);
270 isb();
271
272 /* Program the idle priority in the PMR */
273 write_icc_pmr_el1(GIC_PRI_MASK);
274
275 /* Enable Group0 interrupts */
276 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT);
277
278 /* Enable Group1 Secure interrupts */
279 write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
280 IGRPEN1_EL3_ENABLE_G1S_BIT);
281 isb();
282 }
283
284 /*******************************************************************************
285 * This function disables the GIC CPU interface of the calling CPU using
286 * only system register accesses.
287 ******************************************************************************/
288 void gicv3_cpuif_disable(unsigned int proc_num)
289 {
290 uintptr_t gicr_base;
291
292 assert(gicv3_driver_data != NULL);
293 assert(proc_num < gicv3_driver_data->rdistif_num);
294 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
295
296 assert(IS_IN_EL3());
297
298 /* Disable legacy interrupt bypass */
299 write_icc_sre_el3(read_icc_sre_el3() |
300 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT));
301
302 /* Disable Group0 interrupts */
303 write_icc_igrpen0_el1(read_icc_igrpen0_el1() &
304 ~IGRPEN1_EL1_ENABLE_G0_BIT);
305
306 /* Disable Group1 Secure and Non-Secure interrupts */
307 write_icc_igrpen1_el3(read_icc_igrpen1_el3() &
308 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT |
309 IGRPEN1_EL3_ENABLE_G1S_BIT));
310
311 /* Synchronise accesses to group enable registers */
312 isb();
313
314 /* Mark the connected core as asleep */
315 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
316 gicv3_rdistif_mark_core_asleep(gicr_base);
317 }
318
319 /*******************************************************************************
320 * This function returns the id of the highest priority pending interrupt at
321 * the GIC cpu interface.
322 ******************************************************************************/
323 unsigned int gicv3_get_pending_interrupt_id(void)
324 {
325 unsigned int id;
326
327 assert(IS_IN_EL3());
328 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
329
330 /*
331 * If the ID is special identifier corresponding to G1S or G1NS
332 * interrupt, then read the highest pending group 1 interrupt.
333 */
334 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID))
335 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
336
337 return id;
338 }
339
340 /*******************************************************************************
341 * This function returns the type of the highest priority pending interrupt at
342 * the GIC cpu interface. The return values can be one of the following :
343 * PENDING_G1S_INTID : The interrupt type is secure Group 1.
344 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1.
345 * 0 - 1019 : The interrupt type is secure Group 0.
346 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
347 * sufficient priority to be signaled
348 ******************************************************************************/
349 unsigned int gicv3_get_pending_interrupt_type(void)
350 {
351 assert(IS_IN_EL3());
352 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
353 }
354
355 /*******************************************************************************
356 * This function returns the type of the interrupt id depending upon the group
357 * this interrupt has been configured under by the interrupt controller i.e.
358 * group0 or group1 Secure / Non Secure. The return value can be one of the
359 * following :
360 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt
361 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt
362 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure
363 * interrupt.
364 ******************************************************************************/
365 unsigned int gicv3_get_interrupt_type(unsigned int id,
366 unsigned int proc_num)
367 {
368 unsigned int igroup, grpmodr;
369 uintptr_t gicr_base;
370
371 assert(IS_IN_EL3());
372 assert(gicv3_driver_data != NULL);
373
374 /* Ensure the parameters are valid */
375 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID));
376 assert(proc_num < gicv3_driver_data->rdistif_num);
377
378 /* All LPI interrupts are Group 1 non secure */
379 if (id >= MIN_LPI_ID)
380 return INTR_GROUP1NS;
381
382 if (id < MIN_SPI_ID) {
383 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
384 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
385 igroup = gicr_get_igroupr0(gicr_base, id);
386 grpmodr = gicr_get_igrpmodr0(gicr_base, id);
387 } else {
388 assert(gicv3_driver_data->gicd_base != 0U);
389 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id);
390 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id);
391 }
392
393 /*
394 * If the IGROUP bit is set, then it is a Group 1 Non secure
395 * interrupt
396 */
397 if (igroup != 0U)
398 return INTR_GROUP1NS;
399
400 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
401 if (grpmodr != 0U)
402 return INTR_GROUP1S;
403
404 /* Else it is a Group 0 Secure interrupt */
405 return INTR_GROUP0;
406 }
407
408 /*****************************************************************************
409 * Function to save and disable the GIC ITS register context. The power
410 * management of GIC ITS is implementation-defined and this function doesn't
411 * save any memory structures required to support ITS. As the sequence to save
412 * this state is implementation defined, it should be executed in platform
413 * specific code. Calling this function alone and then powering down the GIC and
414 * ITS without implementing the aforementioned platform specific code will
415 * corrupt the ITS state.
416 *
417 * This function must be invoked after the GIC CPU interface is disabled.
418 *****************************************************************************/
419 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx)
420 {
421 unsigned int i;
422
423 assert(gicv3_driver_data != NULL);
424 assert(IS_IN_EL3());
425 assert(its_ctx != NULL);
426 assert(gits_base != 0U);
427
428 its_ctx->gits_ctlr = gits_read_ctlr(gits_base);
429
430 /* Disable the ITS */
431 gits_write_ctlr(gits_base, its_ctx->gits_ctlr &
432 (~GITS_CTLR_ENABLED_BIT));
433
434 /* Wait for quiescent state */
435 gits_wait_for_quiescent_bit(gits_base);
436
437 its_ctx->gits_cbaser = gits_read_cbaser(gits_base);
438 its_ctx->gits_cwriter = gits_read_cwriter(gits_base);
439
440 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++)
441 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i);
442 }
443
444 /*****************************************************************************
445 * Function to restore the GIC ITS register context. The power
446 * management of GIC ITS is implementation defined and this function doesn't
447 * restore any memory structures required to support ITS. The assumption is
448 * that these structures are in memory and are retained during system suspend.
449 *
450 * This must be invoked before the GIC CPU interface is enabled.
451 *****************************************************************************/
452 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx)
453 {
454 unsigned int i;
455
456 assert(gicv3_driver_data != NULL);
457 assert(IS_IN_EL3());
458 assert(its_ctx != NULL);
459 assert(gits_base != 0U);
460
461 /* Assert that the GITS is disabled and quiescent */
462 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
463 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U);
464
465 gits_write_cbaser(gits_base, its_ctx->gits_cbaser);
466 gits_write_cwriter(gits_base, its_ctx->gits_cwriter);
467
468 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++)
469 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]);
470
471 /* Restore the ITS CTLR but leave the ITS disabled */
472 gits_write_ctlr(gits_base, its_ctx->gits_ctlr &
473 (~GITS_CTLR_ENABLED_BIT));
474 }
475
476 /*****************************************************************************
477 * Function to save the GIC Redistributor register context. This function
478 * must be invoked after CPU interface disable and prior to Distributor save.
479 *****************************************************************************/
480 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx)
481 {
482 uintptr_t gicr_base;
483 unsigned int int_id;
484
485 assert(gicv3_driver_data != NULL);
486 assert(proc_num < gicv3_driver_data->rdistif_num);
487 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
488 assert(IS_IN_EL3());
489 assert(rdist_ctx != NULL);
490
491 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
492
493 /*
494 * Wait for any write to GICR_CTLR to complete before trying to save any
495 * state.
496 */
497 gicr_wait_for_pending_write(gicr_base);
498
499 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base);
500
501 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base);
502 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base);
503
504 rdist_ctx->gicr_igroupr0 = gicr_read_igroupr0(gicr_base);
505 rdist_ctx->gicr_isenabler0 = gicr_read_isenabler0(gicr_base);
506 rdist_ctx->gicr_ispendr0 = gicr_read_ispendr0(gicr_base);
507 rdist_ctx->gicr_isactiver0 = gicr_read_isactiver0(gicr_base);
508 rdist_ctx->gicr_icfgr0 = gicr_read_icfgr0(gicr_base);
509 rdist_ctx->gicr_icfgr1 = gicr_read_icfgr1(gicr_base);
510 rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base);
511 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base);
512 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
513 int_id += (1U << IPRIORITYR_SHIFT)) {
514 rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] =
515 gicr_read_ipriorityr(gicr_base, int_id);
516 }
517
518
519 /*
520 * Call the pre-save hook that implements the IMP DEF sequence that may
521 * be required on some GIC implementations. As this may need to access
522 * the Redistributor registers, we pass it proc_num.
523 */
524 gicv3_distif_pre_save(proc_num);
525 }
526
527 /*****************************************************************************
528 * Function to restore the GIC Redistributor register context. We disable
529 * LPI and per-cpu interrupts before we start restore of the Redistributor.
530 * This function must be invoked after Distributor restore but prior to
531 * CPU interface enable. The pending and active interrupts are restored
532 * after the interrupts are fully configured and enabled.
533 *****************************************************************************/
534 void gicv3_rdistif_init_restore(unsigned int proc_num,
535 const gicv3_redist_ctx_t * const rdist_ctx)
536 {
537 uintptr_t gicr_base;
538 unsigned int int_id;
539
540 assert(gicv3_driver_data != NULL);
541 assert(proc_num < gicv3_driver_data->rdistif_num);
542 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
543 assert(IS_IN_EL3());
544 assert(rdist_ctx != NULL);
545
546 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
547
548 /* Power on redistributor */
549 gicv3_rdistif_on(proc_num);
550
551 /*
552 * Call the post-restore hook that implements the IMP DEF sequence that
553 * may be required on some GIC implementations. As this may need to
554 * access the Redistributor registers, we pass it proc_num.
555 */
556 gicv3_distif_post_restore(proc_num);
557
558 /*
559 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
560 * more scalable approach as it avoids clearing the enable bits in the
561 * GICD_CTLR
562 */
563 gicr_write_icenabler0(gicr_base, ~0U);
564 /* Wait for pending writes to GICR_ICENABLER */
565 gicr_wait_for_pending_write(gicr_base);
566
567 /*
568 * Disable the LPIs to avoid unpredictable behavior when writing to
569 * GICR_PROPBASER and GICR_PENDBASER.
570 */
571 gicr_write_ctlr(gicr_base,
572 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT));
573
574 /* Restore registers' content */
575 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser);
576 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser);
577
578 gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0);
579
580 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
581 int_id += (1U << IPRIORITYR_SHIFT)) {
582 gicr_write_ipriorityr(gicr_base, int_id,
583 rdist_ctx->gicr_ipriorityr[
584 (int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]);
585 }
586
587 gicr_write_icfgr0(gicr_base, rdist_ctx->gicr_icfgr0);
588 gicr_write_icfgr1(gicr_base, rdist_ctx->gicr_icfgr1);
589 gicr_write_igrpmodr0(gicr_base, rdist_ctx->gicr_igrpmodr0);
590 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr);
591
592 /* Restore after group and priorities are set */
593 gicr_write_ispendr0(gicr_base, rdist_ctx->gicr_ispendr0);
594 gicr_write_isactiver0(gicr_base, rdist_ctx->gicr_isactiver0);
595
596 /*
597 * Wait for all writes to the Distributor to complete before enabling
598 * the SGI and PPIs.
599 */
600 gicr_wait_for_upstream_pending_write(gicr_base);
601 gicr_write_isenabler0(gicr_base, rdist_ctx->gicr_isenabler0);
602
603 /*
604 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case
605 * the first write to GICR_CTLR was still in flight (this write only
606 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this
607 * bit).
608 */
609 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr);
610 gicr_wait_for_pending_write(gicr_base);
611 }
612
613 /*****************************************************************************
614 * Function to save the GIC Distributor register context. This function
615 * must be invoked after CPU interface disable and Redistributor save.
616 *****************************************************************************/
617 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
618 {
619 unsigned int num_ints;
620
621 assert(gicv3_driver_data != NULL);
622 assert(gicv3_driver_data->gicd_base != 0U);
623 assert(IS_IN_EL3());
624 assert(dist_ctx != NULL);
625
626 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
627
628 num_ints = gicd_read_typer(gicd_base);
629 num_ints &= TYPER_IT_LINES_NO_MASK;
630 num_ints = (num_ints + 1U) << 5;
631
632 /* Filter out special INTIDs 1020-1023 */
633 if (num_ints > (MAX_SPI_ID + 1U))
634 num_ints = MAX_SPI_ID + 1U;
635
636 /* Wait for pending write to complete */
637 gicd_wait_for_pending_write(gicd_base);
638
639 /* Save the GICD_CTLR */
640 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base);
641
642 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */
643 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
644
645 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */
646 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER);
647
648 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */
649 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR);
650
651 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */
652 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER);
653
654 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */
655 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR);
656
657 /* Save GICD_ICFGR for INTIDs 32 - 1019 */
658 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR);
659
660 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */
661 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR);
662
663 /* Save GICD_NSACR for INTIDs 32 - 1019 */
664 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR);
665
666 /* Save GICD_IROUTER for INTIDs 32 - 1019 */
667 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER);
668
669 /*
670 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when
671 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3
672 * driver.
673 */
674 }
675
676 /*****************************************************************************
677 * Function to restore the GIC Distributor register context. We disable G0, G1S
678 * and G1NS interrupt groups before we start restore of the Distributor. This
679 * function must be invoked prior to Redistributor restore and CPU interface
680 * enable. The pending and active interrupts are restored after the interrupts
681 * are fully configured and enabled.
682 *****************************************************************************/
683 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
684 {
685 unsigned int num_ints = 0U;
686
687 assert(gicv3_driver_data != NULL);
688 assert(gicv3_driver_data->gicd_base != 0U);
689 assert(IS_IN_EL3());
690 assert(dist_ctx != NULL);
691
692 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
693
694 /*
695 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
696 * the ARE_S bit. The Distributor might generate a system error
697 * otherwise.
698 */
699 gicd_clr_ctlr(gicd_base,
700 CTLR_ENABLE_G0_BIT |
701 CTLR_ENABLE_G1S_BIT |
702 CTLR_ENABLE_G1NS_BIT,
703 RWP_TRUE);
704
705 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
706 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
707
708 num_ints = gicd_read_typer(gicd_base);
709 num_ints &= TYPER_IT_LINES_NO_MASK;
710 num_ints = (num_ints + 1U) << 5;
711
712 /* Filter out special INTIDs 1020-1023 */
713 if (num_ints > (MAX_SPI_ID + 1U))
714 num_ints = MAX_SPI_ID + 1U;
715
716 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */
717 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
718
719 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */
720 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR);
721
722 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */
723 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR);
724
725 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */
726 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR);
727
728 /* Restore GICD_NSACR for INTIDs 32 - 1019 */
729 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR);
730
731 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */
732 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER);
733
734 /*
735 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are
736 * configured.
737 */
738
739 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */
740 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER);
741
742 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */
743 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR);
744
745 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */
746 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER);
747
748 /* Restore the GICD_CTLR */
749 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr);
750 gicd_wait_for_pending_write(gicd_base);
751
752 }
753
754 /*******************************************************************************
755 * This function gets the priority of the interrupt the processor is currently
756 * servicing.
757 ******************************************************************************/
758 unsigned int gicv3_get_running_priority(void)
759 {
760 return (unsigned int)read_icc_rpr_el1();
761 }
762
763 /*******************************************************************************
764 * This function checks if the interrupt identified by id is active (whether the
765 * state is either active, or active and pending). The proc_num is used if the
766 * interrupt is SGI or PPI and programs the corresponding Redistributor
767 * interface.
768 ******************************************************************************/
769 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num)
770 {
771 unsigned int value;
772
773 assert(gicv3_driver_data != NULL);
774 assert(gicv3_driver_data->gicd_base != 0U);
775 assert(proc_num < gicv3_driver_data->rdistif_num);
776 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
777 assert(id <= MAX_SPI_ID);
778
779 if (id < MIN_SPI_ID) {
780 /* For SGIs and PPIs */
781 value = gicr_get_isactiver0(
782 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
783 } else {
784 value = gicd_get_isactiver(gicv3_driver_data->gicd_base, id);
785 }
786
787 return value;
788 }
789
790 /*******************************************************************************
791 * This function enables the interrupt identified by id. The proc_num
792 * is used if the interrupt is SGI or PPI, and programs the corresponding
793 * Redistributor interface.
794 ******************************************************************************/
795 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num)
796 {
797 assert(gicv3_driver_data != NULL);
798 assert(gicv3_driver_data->gicd_base != 0U);
799 assert(proc_num < gicv3_driver_data->rdistif_num);
800 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
801 assert(id <= MAX_SPI_ID);
802
803 /*
804 * Ensure that any shared variable updates depending on out of band
805 * interrupt trigger are observed before enabling interrupt.
806 */
807 dsbishst();
808 if (id < MIN_SPI_ID) {
809 /* For SGIs and PPIs */
810 gicr_set_isenabler0(
811 gicv3_driver_data->rdistif_base_addrs[proc_num],
812 id);
813 } else {
814 gicd_set_isenabler(gicv3_driver_data->gicd_base, id);
815 }
816 }
817
818 /*******************************************************************************
819 * This function disables the interrupt identified by id. The proc_num
820 * is used if the interrupt is SGI or PPI, and programs the corresponding
821 * Redistributor interface.
822 ******************************************************************************/
823 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num)
824 {
825 assert(gicv3_driver_data != NULL);
826 assert(gicv3_driver_data->gicd_base != 0U);
827 assert(proc_num < gicv3_driver_data->rdistif_num);
828 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
829 assert(id <= MAX_SPI_ID);
830
831 /*
832 * Disable interrupt, and ensure that any shared variable updates
833 * depending on out of band interrupt trigger are observed afterwards.
834 */
835 if (id < MIN_SPI_ID) {
836 /* For SGIs and PPIs */
837 gicr_set_icenabler0(
838 gicv3_driver_data->rdistif_base_addrs[proc_num],
839 id);
840
841 /* Write to clear enable requires waiting for pending writes */
842 gicr_wait_for_pending_write(
843 gicv3_driver_data->rdistif_base_addrs[proc_num]);
844 } else {
845 gicd_set_icenabler(gicv3_driver_data->gicd_base, id);
846
847 /* Write to clear enable requires waiting for pending writes */
848 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base);
849 }
850
851 dsbishst();
852 }
853
854 /*******************************************************************************
855 * This function sets the interrupt priority as supplied for the given interrupt
856 * id.
857 ******************************************************************************/
858 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
859 unsigned int priority)
860 {
861 uintptr_t gicr_base;
862
863 assert(gicv3_driver_data != NULL);
864 assert(gicv3_driver_data->gicd_base != 0U);
865 assert(proc_num < gicv3_driver_data->rdistif_num);
866 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
867 assert(id <= MAX_SPI_ID);
868
869 if (id < MIN_SPI_ID) {
870 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
871 gicr_set_ipriorityr(gicr_base, id, priority);
872 } else {
873 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority);
874 }
875 }
876
877 /*******************************************************************************
878 * This function assigns group for the interrupt identified by id. The proc_num
879 * is used if the interrupt is SGI or PPI, and programs the corresponding
880 * Redistributor interface. The group can be any of GICV3_INTR_GROUP*
881 ******************************************************************************/
882 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
883 unsigned int type)
884 {
885 bool igroup = false, grpmod = false;
886 uintptr_t gicr_base;
887
888 assert(gicv3_driver_data != NULL);
889 assert(gicv3_driver_data->gicd_base != 0U);
890 assert(proc_num < gicv3_driver_data->rdistif_num);
891 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
892
893 switch (type) {
894 case INTR_GROUP1S:
895 igroup = false;
896 grpmod = true;
897 break;
898 case INTR_GROUP0:
899 igroup = false;
900 grpmod = false;
901 break;
902 case INTR_GROUP1NS:
903 igroup = true;
904 grpmod = false;
905 break;
906 default:
907 assert(false);
908 break;
909 }
910
911 if (id < MIN_SPI_ID) {
912 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
913 if (igroup)
914 gicr_set_igroupr0(gicr_base, id);
915 else
916 gicr_clr_igroupr0(gicr_base, id);
917
918 if (grpmod)
919 gicr_set_igrpmodr0(gicr_base, id);
920 else
921 gicr_clr_igrpmodr0(gicr_base, id);
922 } else {
923 /* Serialize read-modify-write to Distributor registers */
924 spin_lock(&gic_lock);
925 if (igroup)
926 gicd_set_igroupr(gicv3_driver_data->gicd_base, id);
927 else
928 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id);
929
930 if (grpmod)
931 gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id);
932 else
933 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id);
934 spin_unlock(&gic_lock);
935 }
936 }
937
938 /*******************************************************************************
939 * This function raises the specified Secure Group 0 SGI.
940 *
941 * The target parameter must be a valid MPIDR in the system.
942 ******************************************************************************/
943 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target)
944 {
945 unsigned int tgt, aff3, aff2, aff1, aff0;
946 uint64_t sgi_val;
947
948 /* Verify interrupt number is in the SGI range */
949 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID));
950
951 /* Extract affinity fields from target */
952 aff0 = MPIDR_AFFLVL0_VAL(target);
953 aff1 = MPIDR_AFFLVL1_VAL(target);
954 aff2 = MPIDR_AFFLVL2_VAL(target);
955 aff3 = MPIDR_AFFLVL3_VAL(target);
956
957 /*
958 * Make target list from affinity 0, and ensure GICv3 SGI can target
959 * this PE.
960 */
961 assert(aff0 < GICV3_MAX_SGI_TARGETS);
962 tgt = BIT_32(aff0);
963
964 /* Raise SGI to PE specified by its affinity */
965 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF,
966 tgt);
967
968 /*
969 * Ensure that any shared variable updates depending on out of band
970 * interrupt trigger are observed before raising SGI.
971 */
972 dsbishst();
973 write_icc_sgi0r_el1(sgi_val);
974 isb();
975 }
976
977 /*******************************************************************************
978 * This function sets the interrupt routing for the given SPI interrupt id.
979 * The interrupt routing is specified in routing mode and mpidr.
980 *
981 * The routing mode can be either of:
982 * - GICV3_IRM_ANY
983 * - GICV3_IRM_PE
984 *
985 * The mpidr is the affinity of the PE to which the interrupt will be routed,
986 * and is ignored for routing mode GICV3_IRM_ANY.
987 ******************************************************************************/
988 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr)
989 {
990 unsigned long long aff;
991 uint64_t router;
992
993 assert(gicv3_driver_data != NULL);
994 assert(gicv3_driver_data->gicd_base != 0U);
995
996 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE));
997 assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID));
998
999 aff = gicd_irouter_val_from_mpidr(mpidr, irm);
1000 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff);
1001
1002 /*
1003 * In implementations that do not require 1 of N distribution of SPIs,
1004 * IRM might be RAZ/WI. Read back and verify IRM bit.
1005 */
1006 if (irm == GICV3_IRM_ANY) {
1007 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id);
1008 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) {
1009 ERROR("GICv3 implementation doesn't support routing ANY\n");
1010 panic();
1011 }
1012 }
1013 }
1014
1015 /*******************************************************************************
1016 * This function clears the pending status of an interrupt identified by id.
1017 * The proc_num is used if the interrupt is SGI or PPI, and programs the
1018 * corresponding Redistributor interface.
1019 ******************************************************************************/
1020 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num)
1021 {
1022 assert(gicv3_driver_data != NULL);
1023 assert(gicv3_driver_data->gicd_base != 0U);
1024 assert(proc_num < gicv3_driver_data->rdistif_num);
1025 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
1026
1027 /*
1028 * Clear pending interrupt, and ensure that any shared variable updates
1029 * depending on out of band interrupt trigger are observed afterwards.
1030 */
1031 if (id < MIN_SPI_ID) {
1032 /* For SGIs and PPIs */
1033 gicr_set_icpendr0(gicv3_driver_data->rdistif_base_addrs[proc_num],
1034 id);
1035 } else {
1036 gicd_set_icpendr(gicv3_driver_data->gicd_base, id);
1037 }
1038 dsbishst();
1039 }
1040
1041 /*******************************************************************************
1042 * This function sets the pending status of an interrupt identified by id.
1043 * The proc_num is used if the interrupt is SGI or PPI and programs the
1044 * corresponding Redistributor interface.
1045 ******************************************************************************/
1046 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num)
1047 {
1048 assert(gicv3_driver_data != NULL);
1049 assert(gicv3_driver_data->gicd_base != 0U);
1050 assert(proc_num < gicv3_driver_data->rdistif_num);
1051 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
1052
1053 /*
1054 * Ensure that any shared variable updates depending on out of band
1055 * interrupt trigger are observed before setting interrupt pending.
1056 */
1057 dsbishst();
1058 if (id < MIN_SPI_ID) {
1059 /* For SGIs and PPIs */
1060 gicr_set_ispendr0(gicv3_driver_data->rdistif_base_addrs[proc_num],
1061 id);
1062 } else {
1063 gicd_set_ispendr(gicv3_driver_data->gicd_base, id);
1064 }
1065 }
1066
1067 /*******************************************************************************
1068 * This function sets the PMR register with the supplied value. Returns the
1069 * original PMR.
1070 ******************************************************************************/
1071 unsigned int gicv3_set_pmr(unsigned int mask)
1072 {
1073 unsigned int old_mask;
1074
1075 old_mask = (uint32_t) read_icc_pmr_el1();
1076
1077 /*
1078 * Order memory updates w.r.t. PMR write, and ensure they're visible
1079 * before potential out of band interrupt trigger because of PMR update.
1080 * PMR system register writes are self-synchronizing, so no ISB required
1081 * thereafter.
1082 */
1083 dsbishst();
1084 write_icc_pmr_el1(mask);
1085
1086 return old_mask;
1087 }
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