target/linux/rockchip/patches-6.1/301-arm64-dts-rockchip-add-DT-entry-for-RNG-to-RK356x.patch

   1 From patchwork Sat Nov 12 14:10:59 2022
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   5 X-Patchwork-Submitter: Aurelien Jarno <aurelien@aurel32.net>
   6 X-Patchwork-Id: 13041221
   7 From: Aurelien Jarno <aurelien@aurel32.net>
   8 To: Olivia Mackall <olivia@selenic.com>,
   9         Herbert Xu <herbert@gondor.apana.org.au>,
  10         Rob Herring <robh+dt@kernel.org>,
  11         Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
  12         Heiko Stuebner <heiko@sntech.de>,
  13         Philipp Zabel <p.zabel@pengutronix.de>,
  14         Lin Jinhan <troy.lin@rock-chips.com>
  15 Cc: linux-crypto@vger.kernel.org (open list:HARDWARE RANDOM NUMBER GENERATOR
  16  CORE),
  17         devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE
  18  BINDINGS),
  19         linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC
  20  support),
  21         linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support),
  22         linux-kernel@vger.kernel.org (open list),
  23         Aurelien Jarno <aurelien@aurel32.net>
  24 Subject: [PATCH v1 3/3] arm64: dts: rockchip: add DT entry for RNG to RK356x
  25 Date: Sat, 12 Nov 2022 15:10:59 +0100
  26 Message-Id: <20221112141059.3802506-4-aurelien@aurel32.net>
  27 In-Reply-To: <20221112141059.3802506-1-aurelien@aurel32.net>
  28 References: <20221112141059.3802506-1-aurelien@aurel32.net>
  29 MIME-Version: 1.0
  30 List-Id: <linux-arm-kernel.lists.infradead.org>
  31
  32 Enable the just added Rockchip RNG driver for RK356x SoCs.
  33
  34 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
  35 ---
  36  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 9 +++++++++
  37  1 file changed, 9 insertions(+)
  38
  39 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
  40 +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
  41 @@ -1773,6 +1773,15 @@
  42                 };
  43         };
  44
  45 +       rng: rng@fe388000 {
  46 +               compatible = "rockchip,rk3568-rng";
  47 +               reg = <0x0 0xfe388000 0x0 0x4000>;
  48 +               clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
  49 +               clock-names = "trng_clk", "trng_hclk";
  50 +               resets = <&cru SRST_TRNG_NS>;
  51 +               reset-names = "reset";
  52 +       };
  53 +
  54         pinctrl: pinctrl {
  55                 compatible = "rockchip,rk3568-pinctrl";
  56                 rockchip,grf = <&grf>;