include $(TOPDIR)/rules.mk
ARCH:=riscv64
-BOARD:=sifiveu
-BOARDNAME:=SiFive U-based RISC-V boards
+BOARD:=visionfive
+BOARDNAME:=Vision five
FEATURES:=ext4
KERNELNAME:=Image dtbs
MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
KERNEL_NAME := Image
endef
-define Device/sifive_unleashed
+define Device/visionfive
$(call Device/FitImage)
- DEVICE_VENDOR := SiFive
- DEVICE_MODEL := Unleashed (FU540)
- DEVICE_DTS := sifive/hifive-unleashed-a00
- UBOOT := sifive_unleashed
+ DEVICE_VENDOR := StarFive
+ DEVICE_MODEL := VisionFive
+ DEVICE_DTS := starfive/jh7100-starfive-visionfive-v1
endef
-TARGET_DEVICES += sifive_unleashed
+TARGET_DEVICES += visionfive
-define Device/sifive_unmatched
- $(call Device/FitImage)
- DEVICE_VENDOR := SiFive
- DEVICE_MODEL := Unmatched (FU740)
- DEVICE_DTS := sifive/hifive-unmatched-a00
- DEVICE_PACKAGES += kmod-eeprom-at24 kmod-hwmon-lm90
- UBOOT := sifive_unmatched
-endef
-TARGET_DEVICES += sifive_unmatched
$(eval $(call BuildImage))
--- /dev/null
+From 3d24568b01c5a7a9e88f73f917477b60edb35bfe Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 10 Oct 2021 16:10:32 +0200
+Subject: [PATCH 01/16] RISC-V: Add StarFive SoC Kconfig option
+
+Add StarFive Kconfig option to select SoC specific and common drivers
+required for these SoCs. Select subsystems required to boot so the
+required drivers gets enabled by default.
+
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/Kconfig.socs | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
+index 30676ebb16eb..6ec44a22278a 100644
+--- a/arch/riscv/Kconfig.socs
++++ b/arch/riscv/Kconfig.socs
+@@ -19,6 +19,14 @@ config SOC_SIFIVE
+ help
+ This enables support for SiFive SoC platform hardware.
+
++config SOC_STARFIVE
++ bool "StarFive SoCs"
++ select PINCTRL
++ select RESET_CONTROLLER
++ select SIFIVE_PLIC
++ help
++ This enables support for StarFive SoC platform hardware.
++
+ config SOC_VIRT
+ bool "QEMU Virt Machine"
+ select CLINT_TIMER if RISCV_M_MODE
+--
+2.30.2
+
+++ /dev/null
-From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Wed, 17 Feb 2021 06:06:14 -0800
-Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
- sifive,u74-mc
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
-index abbb960..3095d82 100644
---- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
-+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
-@@ -39,7 +39,7 @@
- };
- };
- cpu1: cpu@1 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
-@@ -63,7 +63,7 @@
- };
- };
- cpu2: cpu@2 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
-@@ -87,7 +87,7 @@
- };
- };
- cpu3: cpu@3 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
-@@ -111,7 +111,7 @@
- };
- };
- cpu4: cpu@4 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
---
-2.7.4
-
--- /dev/null
+From 3234d3a1374308615c0cde5e83e52f6b644eaf53 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 10 Oct 2021 16:48:27 +0200
+Subject: [PATCH 02/16] dt-bindings: timer: Add StarFive JH7100 clint
+
+Add compatible string for the StarFive JH7100 clint.
+
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+index a35952f48742..8d5f4687add9 100644
+--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
++++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+@@ -25,6 +25,7 @@ properties:
+ items:
+ - enum:
+ - sifive,fu540-c000-clint
++ - starfive,jh7100-clint
+ - canaan,k210-clint
+ - const: sifive,clint0
+
+--
+2.30.2
+
+++ /dev/null
-From 657819ff477dd73cd71075609698aa57ba098d8c Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Wed, 15 Sep 2021 07:10:02 -0700
-Subject: [PATCH 2/7] riscv: sifive: unmatched: update regulators values
-
-These are the regulators values from the schematics for Rev3{A,B} boards.
-
-Note this is not fully correct as bcore1/bcore2 and bmem/bio are merged, but
-it's only supported in v5.15 kernel. See:
-
-541ee8f640327f951e7039278057827322231ab0 ("regulator: da9063: Add support for
-full-current mode.")
-
-This will be changed for v5.15 kernel based on the patch above.
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 32 +++++++++++-----------
- 1 file changed, 16 insertions(+), 16 deletions(-)
-
-diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-index 2e4ea84..e026f60 100644
---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-@@ -72,16 +72,16 @@
-
- regulators {
- vdd_bcore1: bcore1 {
-- regulator-min-microvolt = <900000>;
-- regulator-max-microvolt = <900000>;
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1050000>;
- regulator-min-microamp = <5000000>;
- regulator-max-microamp = <5000000>;
- regulator-always-on;
- };
-
- vdd_bcore2: bcore2 {
-- regulator-min-microvolt = <900000>;
-- regulator-max-microvolt = <900000>;
-+ regulator-min-microvolt = <1050000>;
-+ regulator-max-microvolt = <1050000>;
- regulator-min-microamp = <5000000>;
- regulator-max-microamp = <5000000>;
- regulator-always-on;
-@@ -136,48 +136,48 @@
- };
-
- vdd_ldo3: ldo3 {
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
- regulator-always-on;
- };
-
- vdd_ldo4: ldo4 {
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-+ regulator-min-microvolt = <2500000>;
-+ regulator-max-microvolt = <2500000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
- regulator-always-on;
- };
-
- vdd_ldo5: ldo5 {
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
- regulator-min-microamp = <100000>;
- regulator-max-microamp = <100000>;
- regulator-always-on;
- };
-
- vdd_ldo6: ldo6 {
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
- regulator-always-on;
- };
-
- vdd_ldo7: ldo7 {
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
- regulator-always-on;
- };
-
- vdd_ldo8: ldo8 {
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
- regulator-min-microamp = <200000>;
- regulator-max-microamp = <200000>;
- regulator-always-on;
---
-2.7.4
-
--- /dev/null
+From 9ac16169b4d4359d3832669bf06aab9e51184828 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 10 Oct 2021 16:48:27 +0200
+Subject: [PATCH 03/16] dt-bindings: interrupt-controller: Add StarFive JH7100
+ plic
+
+Add compatible string for StarFive JH7100 plic.
+
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+index 08d5a57ce00f..28b6b17fe4b2 100644
+--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
++++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+@@ -45,6 +45,7 @@ properties:
+ items:
+ - enum:
+ - sifive,fu540-c000-plic
++ - starfive,jh7100-plic
+ - canaan,k210-plic
+ - const: sifive,plic-1.0.0
+
+--
+2.30.2
+
+++ /dev/null
-From 2c2d8ac8c124a2938c9326c14b2dffd46d76b4a8 Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Mon, 13 Sep 2021 02:15:37 -0700
-Subject: [PATCH 3/7] riscv: sifive: unmatched: define PWM LEDs
-
-Add D2 (RGB) and D12 (green) LEDs for SiFive Unmatched board.
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 41 ++++++++++++++++++++++
- 1 file changed, 41 insertions(+)
-
-diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-index e026f60..200d022 100644
---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-@@ -3,6 +3,8 @@
-
- #include "fu740-c000.dtsi"
- #include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pwm/pwm.h>
-
- /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
- #define RTCCLK_FREQ 1000000
-@@ -30,6 +32,45 @@
- soc {
- };
-
-+ pwmleds {
-+ compatible = "pwm-leds";
-+ green-d12 {
-+ label = "green:d12";
-+ color = <LED_COLOR_ID_GREEN>;
-+ pwms = <&pwm0 0 7812500 PWM_POLARITY_INVERTED>;
-+ active-low = <1>;
-+ max-brightness = <255>;
-+ linux,default-trigger = "none";
-+ };
-+
-+ green-d2 {
-+ label = "green:d2";
-+ color = <LED_COLOR_ID_GREEN>;
-+ pwms = <&pwm0 1 7812500 PWM_POLARITY_INVERTED>;
-+ active-low = <1>;
-+ max-brightness = <255>;
-+ linux,default-trigger = "none";
-+ };
-+
-+ red-d2 {
-+ label = "red:d2";
-+ color = <LED_COLOR_ID_RED>;
-+ pwms = <&pwm0 2 7812500 PWM_POLARITY_INVERTED>;
-+ active-low = <1>;
-+ max-brightness = <255>;
-+ linux,default-trigger = "none";
-+ };
-+
-+ blue-d2 {
-+ label = "blue:d2";
-+ color = <LED_COLOR_ID_BLUE>;
-+ pwms = <&pwm0 3 7812500 PWM_POLARITY_INVERTED>;
-+ active-low = <1>;
-+ max-brightness = <255>;
-+ linux,default-trigger = "none";
-+ };
-+ };
-+
- hfclk: hfclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
---
-2.7.4
-
--- /dev/null
+From 38bb8a7264daf0ff5bb3024ae94bc465de78203d Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Fri, 25 Jun 2021 11:29:51 +0200
+Subject: [PATCH 04/16] dt-bindings: clock: starfive: Add JH7100 clock
+ definitions
+
+Add all clock outputs for the StarFive JH7100 clock generator.
+
+Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added
+to all definitions.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ include/dt-bindings/clock/starfive-jh7100.h | 202 ++++++++++++++++++++
+ 1 file changed, 202 insertions(+)
+ create mode 100644 include/dt-bindings/clock/starfive-jh7100.h
+
+diff --git a/include/dt-bindings/clock/starfive-jh7100.h b/include/dt-bindings/clock/starfive-jh7100.h
+new file mode 100644
+index 000000000000..aa0863b9728d
+--- /dev/null
++++ b/include/dt-bindings/clock/starfive-jh7100.h
+@@ -0,0 +1,202 @@
++/* SPDX-License-Identifier: GPL-2.0 OR MIT */
++/*
++ * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
++ */
++
++#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
++#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
++
++#define JH7100_CLK_CPUNDBUS_ROOT 0
++#define JH7100_CLK_DLA_ROOT 1
++#define JH7100_CLK_DSP_ROOT 2
++#define JH7100_CLK_GMACUSB_ROOT 3
++#define JH7100_CLK_PERH0_ROOT 4
++#define JH7100_CLK_PERH1_ROOT 5
++#define JH7100_CLK_VIN_ROOT 6
++#define JH7100_CLK_VOUT_ROOT 7
++#define JH7100_CLK_AUDIO_ROOT 8
++#define JH7100_CLK_CDECHIFI4_ROOT 9
++#define JH7100_CLK_CDEC_ROOT 10
++#define JH7100_CLK_VOUTBUS_ROOT 11
++#define JH7100_CLK_CPUNBUS_ROOT_DIV 12
++#define JH7100_CLK_DSP_ROOT_DIV 13
++#define JH7100_CLK_PERH0_SRC 14
++#define JH7100_CLK_PERH1_SRC 15
++#define JH7100_CLK_PLL0_TESTOUT 16
++#define JH7100_CLK_PLL1_TESTOUT 17
++#define JH7100_CLK_PLL2_TESTOUT 18
++#define JH7100_CLK_PLL2_REF 19
++#define JH7100_CLK_CPU_CORE 20
++#define JH7100_CLK_CPU_AXI 21
++#define JH7100_CLK_AHB_BUS 22
++#define JH7100_CLK_APB1_BUS 23
++#define JH7100_CLK_APB2_BUS 24
++#define JH7100_CLK_DOM3AHB_BUS 25
++#define JH7100_CLK_DOM7AHB_BUS 26
++#define JH7100_CLK_U74_CORE0 27
++#define JH7100_CLK_U74_CORE1 28
++#define JH7100_CLK_U74_AXI 29
++#define JH7100_CLK_U74RTC_TOGGLE 30
++#define JH7100_CLK_SGDMA2P_AXI 31
++#define JH7100_CLK_DMA2PNOC_AXI 32
++#define JH7100_CLK_SGDMA2P_AHB 33
++#define JH7100_CLK_DLA_BUS 34
++#define JH7100_CLK_DLA_AXI 35
++#define JH7100_CLK_DLANOC_AXI 36
++#define JH7100_CLK_DLA_APB 37
++#define JH7100_CLK_VP6_CORE 38
++#define JH7100_CLK_VP6BUS_SRC 39
++#define JH7100_CLK_VP6_AXI 40
++#define JH7100_CLK_VCDECBUS_SRC 41
++#define JH7100_CLK_VDEC_BUS 42
++#define JH7100_CLK_VDEC_AXI 43
++#define JH7100_CLK_VDECBRG_MAIN 44
++#define JH7100_CLK_VDEC_BCLK 45
++#define JH7100_CLK_VDEC_CCLK 46
++#define JH7100_CLK_VDEC_APB 47
++#define JH7100_CLK_JPEG_AXI 48
++#define JH7100_CLK_JPEG_CCLK 49
++#define JH7100_CLK_JPEG_APB 50
++#define JH7100_CLK_GC300_2X 51
++#define JH7100_CLK_GC300_AHB 52
++#define JH7100_CLK_JPCGC300_AXIBUS 53
++#define JH7100_CLK_GC300_AXI 54
++#define JH7100_CLK_JPCGC300_MAIN 55
++#define JH7100_CLK_VENC_BUS 56
++#define JH7100_CLK_VENC_AXI 57
++#define JH7100_CLK_VENCBRG_MAIN 58
++#define JH7100_CLK_VENC_BCLK 59
++#define JH7100_CLK_VENC_CCLK 60
++#define JH7100_CLK_VENC_APB 61
++#define JH7100_CLK_DDRPLL_DIV2 62
++#define JH7100_CLK_DDRPLL_DIV4 63
++#define JH7100_CLK_DDRPLL_DIV8 64
++#define JH7100_CLK_DDROSC_DIV2 65
++#define JH7100_CLK_DDRC0 66
++#define JH7100_CLK_DDRC1 67
++#define JH7100_CLK_DDRPHY_APB 68
++#define JH7100_CLK_NOC_ROB 69
++#define JH7100_CLK_NOC_COG 70
++#define JH7100_CLK_NNE_AHB 71
++#define JH7100_CLK_NNEBUS_SRC1 72
++#define JH7100_CLK_NNE_BUS 73
++#define JH7100_CLK_NNE_AXI 74
++#define JH7100_CLK_NNENOC_AXI 75
++#define JH7100_CLK_DLASLV_AXI 76
++#define JH7100_CLK_DSPX2C_AXI 77
++#define JH7100_CLK_HIFI4_SRC 78
++#define JH7100_CLK_HIFI4_COREFREE 79
++#define JH7100_CLK_HIFI4_CORE 80
++#define JH7100_CLK_HIFI4_BUS 81
++#define JH7100_CLK_HIFI4_AXI 82
++#define JH7100_CLK_HIFI4NOC_AXI 83
++#define JH7100_CLK_SGDMA1P_BUS 84
++#define JH7100_CLK_SGDMA1P_AXI 85
++#define JH7100_CLK_DMA1P_AXI 86
++#define JH7100_CLK_X2C_AXI 87
++#define JH7100_CLK_USB_BUS 88
++#define JH7100_CLK_USB_AXI 89
++#define JH7100_CLK_USBNOC_AXI 90
++#define JH7100_CLK_USBPHY_ROOTDIV 91
++#define JH7100_CLK_USBPHY_125M 92
++#define JH7100_CLK_USBPHY_PLLDIV25M 93
++#define JH7100_CLK_USBPHY_25M 94
++#define JH7100_CLK_AUDIO_DIV 95
++#define JH7100_CLK_AUDIO_SRC 96
++#define JH7100_CLK_AUDIO_12288 97
++#define JH7100_CLK_VIN_SRC 98
++#define JH7100_CLK_ISP0_BUS 99
++#define JH7100_CLK_ISP0_AXI 100
++#define JH7100_CLK_ISP0NOC_AXI 101
++#define JH7100_CLK_ISPSLV_AXI 102
++#define JH7100_CLK_ISP1_BUS 103
++#define JH7100_CLK_ISP1_AXI 104
++#define JH7100_CLK_ISP1NOC_AXI 105
++#define JH7100_CLK_VIN_BUS 106
++#define JH7100_CLK_VIN_AXI 107
++#define JH7100_CLK_VINNOC_AXI 108
++#define JH7100_CLK_VOUT_SRC 109
++#define JH7100_CLK_DISPBUS_SRC 110
++#define JH7100_CLK_DISP_BUS 111
++#define JH7100_CLK_DISP_AXI 112
++#define JH7100_CLK_DISPNOC_AXI 113
++#define JH7100_CLK_SDIO0_AHB 114
++#define JH7100_CLK_SDIO0_CCLKINT 115
++#define JH7100_CLK_SDIO0_CCLKINT_INV 116
++#define JH7100_CLK_SDIO1_AHB 117
++#define JH7100_CLK_SDIO1_CCLKINT 118
++#define JH7100_CLK_SDIO1_CCLKINT_INV 119
++#define JH7100_CLK_GMAC_AHB 120
++#define JH7100_CLK_GMAC_ROOT_DIV 121
++#define JH7100_CLK_GMAC_PTP_REF 122
++#define JH7100_CLK_GMAC_GTX 123
++#define JH7100_CLK_GMAC_RMII_TX 124
++#define JH7100_CLK_GMAC_RMII_RX 125
++#define JH7100_CLK_GMAC_TX 126
++#define JH7100_CLK_GMAC_TX_INV 127
++#define JH7100_CLK_GMAC_RX_PRE 128
++#define JH7100_CLK_GMAC_RX_INV 129
++#define JH7100_CLK_GMAC_RMII 130
++#define JH7100_CLK_GMAC_TOPHYREF 131
++#define JH7100_CLK_SPI2AHB_AHB 132
++#define JH7100_CLK_SPI2AHB_CORE 133
++#define JH7100_CLK_EZMASTER_AHB 134
++#define JH7100_CLK_E24_AHB 135
++#define JH7100_CLK_E24RTC_TOGGLE 136
++#define JH7100_CLK_QSPI_AHB 137
++#define JH7100_CLK_QSPI_APB 138
++#define JH7100_CLK_QSPI_REF 139
++#define JH7100_CLK_SEC_AHB 140
++#define JH7100_CLK_AES 141
++#define JH7100_CLK_SHA 142
++#define JH7100_CLK_PKA 143
++#define JH7100_CLK_TRNG_APB 144
++#define JH7100_CLK_OTP_APB 145
++#define JH7100_CLK_UART0_APB 146
++#define JH7100_CLK_UART0_CORE 147
++#define JH7100_CLK_UART1_APB 148
++#define JH7100_CLK_UART1_CORE 149
++#define JH7100_CLK_SPI0_APB 150
++#define JH7100_CLK_SPI0_CORE 151
++#define JH7100_CLK_SPI1_APB 152
++#define JH7100_CLK_SPI1_CORE 153
++#define JH7100_CLK_I2C0_APB 154
++#define JH7100_CLK_I2C0_CORE 155
++#define JH7100_CLK_I2C1_APB 156
++#define JH7100_CLK_I2C1_CORE 157
++#define JH7100_CLK_GPIO_APB 158
++#define JH7100_CLK_UART2_APB 159
++#define JH7100_CLK_UART2_CORE 160
++#define JH7100_CLK_UART3_APB 161
++#define JH7100_CLK_UART3_CORE 162
++#define JH7100_CLK_SPI2_APB 163
++#define JH7100_CLK_SPI2_CORE 164
++#define JH7100_CLK_SPI3_APB 165
++#define JH7100_CLK_SPI3_CORE 166
++#define JH7100_CLK_I2C2_APB 167
++#define JH7100_CLK_I2C2_CORE 168
++#define JH7100_CLK_I2C3_APB 169
++#define JH7100_CLK_I2C3_CORE 170
++#define JH7100_CLK_WDTIMER_APB 171
++#define JH7100_CLK_WDT_CORE 172
++#define JH7100_CLK_TIMER0_CORE 173
++#define JH7100_CLK_TIMER1_CORE 174
++#define JH7100_CLK_TIMER2_CORE 175
++#define JH7100_CLK_TIMER3_CORE 176
++#define JH7100_CLK_TIMER4_CORE 177
++#define JH7100_CLK_TIMER5_CORE 178
++#define JH7100_CLK_TIMER6_CORE 179
++#define JH7100_CLK_VP6INTC_APB 180
++#define JH7100_CLK_PWM_APB 181
++#define JH7100_CLK_MSI_APB 182
++#define JH7100_CLK_TEMP_APB 183
++#define JH7100_CLK_TEMP_SENSE 184
++#define JH7100_CLK_SYSERR_APB 185
++
++#define JH7100_CLK_PLL0_OUT 186
++#define JH7100_CLK_PLL1_OUT 187
++#define JH7100_CLK_PLL2_OUT 188
++
++#define JH7100_CLK_END 189
++
++#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */
+--
+2.30.2
+
+++ /dev/null
-From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Mon, 13 Sep 2021 02:18:30 -0700
-Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node
-
-Add gpio-poweroff node to allow powering off the system.
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-index 200d022..4584676 100644
-@@ -84,6 +85,11 @@
- clock-frequency = <RTCCLK_FREQ>;
- clock-output-names = "rtcclk";
- };
-+
-+ gpio-poweroff {
-+ compatible = "gpio-poweroff";
-+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
-+ };
- };
-
- &uart0 {
---
-2.7.4
-
+++ /dev/null
-From 082e93a136eafb444e93e518115aac349304b77e Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Fri, 5 Jun 2020 07:02:10 +0000
-Subject: [PATCH 5/7] SiFive HiFive Unleashed: Add PWM LEDs (D1, D2, D3, D4)
-
-By default no functions are assigned to LEDs. It's up to user/distribution
-to provide udev rules to configure them.
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 32 ++++++++++++++++++++++
- 1 file changed, 32 insertions(+)
-
-diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-index 60846e8..a99aded 100644
---- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-@@ -3,6 +3,7 @@
-
- #include "fu540-c000.dtsi"
- #include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/pwm/pwm.h>
-
- /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
- #define RTCCLK_FREQ 1000000
-@@ -27,6 +28,37 @@
- };
-
- soc {
-+ pwmleds {
-+ compatible = "pwm-leds";
-+ d1 {
-+ label = "green:d1";
-+ pwms = <&pwm0 0 7812500 PWM_POLARITY_INVERTED>;
-+ active-low = <1>;
-+ max-brightness = <255>;
-+ linux,default-trigger = "none";
-+ };
-+ d2 {
-+ label = "green:d2";
-+ pwms = <&pwm0 1 7812500 PWM_POLARITY_INVERTED>;
-+ active-low = <1>;
-+ max-brightness = <255>;
-+ linux,default-trigger = "none";
-+ };
-+ d3 {
-+ label = "green:d3";
-+ pwms = <&pwm0 2 7812500 PWM_POLARITY_INVERTED>;
-+ active-low = <1>;
-+ max-brightness = <255>;
-+ linux,default-trigger = "none";
-+ };
-+ d4 {
-+ label = "green:d4";
-+ pwms = <&pwm0 3 7812500 PWM_POLARITY_INVERTED>;
-+ active-low = <1>;
-+ max-brightness = <255>;
-+ linux,default-trigger = "none";
-+ };
-+ };
- };
-
- hfclk: hfclk {
---
-2.7.4
-
--- /dev/null
+From af35098f4fcd1f9bfc58dc37479e0786a4d85e96 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Tue, 1 Jun 2021 16:02:23 +0200
+Subject: [PATCH 05/16] dt-bindings: clock: starfive: Add JH7100 bindings
+
+Add bindings for the clock generator on the JH7100 RISC-V SoC by
+StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../clock/starfive,jh7100-clkgen.yaml | 56 +++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
+
+diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
+new file mode 100644
+index 000000000000..12f17b60ecbe
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
+@@ -0,0 +1,56 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive JH7100 Clock Generator
++
++maintainers:
++ - Geert Uytterhoeven <geert@linux-m68k.org>
++ - Emil Renner Berthing <kernel@esmil.dk>
++
++properties:
++ compatible:
++ const: starfive,jh7100-clkgen
++
++ reg:
++ maxItems: 1
++
++ clocks:
++ items:
++ - description: Main clock source (25 MHz)
++ - description: Application-specific clock source (12-27 MHz)
++ - description: RMII reference clock (50 MHz)
++ - description: RGMII RX clock (125 MHz)
++
++ clock-names:
++ items:
++ - const: osc_sys
++ - const: osc_aud
++ - const: gmac_rmii_ref
++ - const: gmac_gr_mii_rxclk
++
++ '#clock-cells':
++ const: 1
++ description:
++ See <dt-bindings/clock/starfive-jh7100.h> for valid indices.
++
++required:
++ - compatible
++ - reg
++ - clocks
++ - clock-names
++ - '#clock-cells'
++
++additionalProperties: false
++
++examples:
++ - |
++ clock-controller@11800000 {
++ compatible = "starfive,jh7100-clkgen";
++ reg = <0x11800000 0x10000>;
++ clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
++ clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
++ #clock-cells = <1>;
++ };
+--
+2.30.2
+
--- /dev/null
+From 4210be668a09ee20e4e1c7adf61b47d33d05c480 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Tue, 1 Jun 2021 15:57:52 +0200
+Subject: [PATCH 06/16] clk: starfive: Add JH7100 clock generator driver
+
+Add a driver for the StarFive JH7100 clock generator.
+
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ MAINTAINERS | 7 +
+ drivers/clk/Kconfig | 1 +
+ drivers/clk/Makefile | 1 +
+ drivers/clk/starfive/Kconfig | 9 +
+ drivers/clk/starfive/Makefile | 3 +
+ drivers/clk/starfive/clk-starfive-jh7100.c | 689 +++++++++++++++++++++
+ 6 files changed, 710 insertions(+)
+ create mode 100644 drivers/clk/starfive/Kconfig
+ create mode 100644 drivers/clk/starfive/Makefile
+ create mode 100644 drivers/clk/starfive/clk-starfive-jh7100.c
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 7a2345ce8521..2548ef1f8246 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -18130,6 +18130,13 @@ M: Ion Badulescu <ionut@badula.org>
+ S: Odd Fixes
+ F: drivers/net/ethernet/adaptec/starfire*
+
++STARFIVE JH7100 CLOCK DRIVER
++M: Emil Renner Berthing <kernel@esmil.dk>
++S: Maintained
++F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
++F: drivers/clk/starfive/clk-starfive-jh7100.c
++F: include/dt-bindings/clock/starfive-jh7100.h
++
+ STATIC BRANCH/CALL
+ M: Peter Zijlstra <peterz@infradead.org>
+ M: Josh Poimboeuf <jpoimboe@redhat.com>
+diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
+index c5b3dc97396a..c91931c94888 100644
+--- a/drivers/clk/Kconfig
++++ b/drivers/clk/Kconfig
+@@ -412,6 +412,7 @@ source "drivers/clk/samsung/Kconfig"
+ source "drivers/clk/sifive/Kconfig"
+ source "drivers/clk/socfpga/Kconfig"
+ source "drivers/clk/sprd/Kconfig"
++source "drivers/clk/starfive/Kconfig"
+ source "drivers/clk/sunxi/Kconfig"
+ source "drivers/clk/sunxi-ng/Kconfig"
+ source "drivers/clk/tegra/Kconfig"
+diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
+index e42312121e51..a9bb2478fbdd 100644
+--- a/drivers/clk/Makefile
++++ b/drivers/clk/Makefile
+@@ -109,6 +109,7 @@ obj-y += socfpga/
+ obj-$(CONFIG_PLAT_SPEAR) += spear/
+ obj-y += sprd/
+ obj-$(CONFIG_ARCH_STI) += st/
++obj-$(CONFIG_SOC_STARFIVE) += starfive/
+ obj-$(CONFIG_ARCH_SUNXI) += sunxi/
+ obj-$(CONFIG_SUNXI_CCU) += sunxi-ng/
+ obj-$(CONFIG_ARCH_TEGRA) += tegra/
+diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
+new file mode 100644
+index 000000000000..c0fa9d5e641f
+--- /dev/null
++++ b/drivers/clk/starfive/Kconfig
+@@ -0,0 +1,9 @@
++# SPDX-License-Identifier: GPL-2.0
++
++config CLK_STARFIVE_JH7100
++ bool "StarFive JH7100 clock support"
++ depends on SOC_STARFIVE || COMPILE_TEST
++ default SOC_STARFIVE
++ help
++ Say yes here to support the clock controller on the StarFive JH7100
++ SoC.
+diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
+new file mode 100644
+index 000000000000..09759cc73530
+--- /dev/null
++++ b/drivers/clk/starfive/Makefile
+@@ -0,0 +1,3 @@
++# SPDX-License-Identifier: GPL-2.0
++# StarFive Clock
++obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
+diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
+new file mode 100644
+index 000000000000..25d31afa0f87
+--- /dev/null
++++ b/drivers/clk/starfive/clk-starfive-jh7100.c
+@@ -0,0 +1,689 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * StarFive JH7100 Clock Generator Driver
++ *
++ * Copyright 2021 Ahmad Fatoum, Pengutronix
++ * Copyright (C) 2021 Glider bv
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#include <linux/bits.h>
++#include <linux/clk-provider.h>
++#include <linux/debugfs.h>
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/mod_devicetable.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <dt-bindings/clock/starfive-jh7100.h>
++
++/* external clocks */
++#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
++#define JH7100_CLK_OSC_AUD (JH7100_CLK_END + 1)
++#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
++#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
++
++/* register fields */
++#define JH7100_CLK_ENABLE BIT(31)
++#define JH7100_CLK_INVERT BIT(30)
++#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
++#define JH7100_CLK_MUX_SHIFT 24
++#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
++
++/* clock data */
++#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
++ .name = _name, \
++ .flags = CLK_SET_RATE_PARENT | (_flags), \
++ .max = JH7100_CLK_ENABLE, \
++ .parents = { [0] = _parent }, \
++}
++
++#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
++ .name = _name, \
++ .flags = 0, \
++ .max = _max, \
++ .parents = { [0] = _parent }, \
++}
++
++#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
++ .name = _name, \
++ .flags = _flags, \
++ .max = JH7100_CLK_ENABLE | (_max), \
++ .parents = { [0] = _parent }, \
++}
++
++#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
++ .name = _name, \
++ .flags = 0, \
++ .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
++ .parents = { __VA_ARGS__ }, \
++}
++
++#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
++ .name = _name, \
++ .flags = _flags, \
++ .max = JH7100_CLK_ENABLE | \
++ (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
++ .parents = { __VA_ARGS__ }, \
++}
++
++#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
++ .name = _name, \
++ .flags = CLK_SET_RATE_PARENT, \
++ .max = JH7100_CLK_INVERT, \
++ .parents = { [0] = _parent }, \
++}
++
++static const struct {
++ const char *name;
++ unsigned long flags;
++ u32 max;
++ u8 parents[4];
++} jh7100_clk_data[] __initconst = {
++ JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
++ JH7100_CLK_OSC_SYS,
++ JH7100_CLK_PLL0_OUT,
++ JH7100_CLK_PLL1_OUT,
++ JH7100_CLK_PLL2_OUT),
++ JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
++ JH7100_CLK_OSC_SYS,
++ JH7100_CLK_PLL1_OUT,
++ JH7100_CLK_PLL2_OUT),
++ JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
++ JH7100_CLK_OSC_SYS,
++ JH7100_CLK_PLL0_OUT,
++ JH7100_CLK_PLL1_OUT,
++ JH7100_CLK_PLL2_OUT),
++ JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
++ JH7100_CLK_OSC_SYS,
++ JH7100_CLK_PLL0_OUT,
++ JH7100_CLK_PLL2_OUT),
++ JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
++ JH7100_CLK_OSC_SYS,
++ JH7100_CLK_PLL0_OUT),
++ JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
++ JH7100_CLK_OSC_SYS,
++ JH7100_CLK_PLL2_OUT),
++ JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
++ JH7100_CLK_OSC_SYS,
++ JH7100_CLK_PLL1_OUT,
++ JH7100_CLK_PLL2_OUT),
++ JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
++ JH7100_CLK_OSC_AUD,
++ JH7100_CLK_PLL0_OUT,
++ JH7100_CLK_PLL2_OUT),
++ JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
++ JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
++ JH7100_CLK_OSC_SYS,
++ JH7100_CLK_PLL1_OUT,
++ JH7100_CLK_PLL2_OUT),
++ JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
++ JH7100_CLK_OSC_SYS,
++ JH7100_CLK_PLL0_OUT,
++ JH7100_CLK_PLL1_OUT),
++ JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
++ JH7100_CLK_OSC_AUD,
++ JH7100_CLK_PLL0_OUT,
++ JH7100_CLK_PLL2_OUT),
++ JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
++ JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
++ JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
++ JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
++ JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
++ JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
++ JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
++ JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
++ JH7100_CLK_OSC_SYS,
++ JH7100_CLK_OSC_AUD),
++ JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++ JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
++ JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++ JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
++ JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
++ JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
++ JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
++ JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
++ JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
++ JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
++ JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
++ JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
++ JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
++ JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
++ JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
++ JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
++ JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
++ JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
++ JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
++ JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
++ JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
++ JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
++ JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
++ JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
++ JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
++ JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
++ JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++ JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++ JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
++ JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
++ JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
++ JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
++ JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
++ JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
++ JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
++ JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
++ JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
++ JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
++ JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
++ JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
++ JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
++ JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
++ JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
++ JH7100_CLK_DDROSC_DIV2,
++ JH7100_CLK_DDRPLL_DIV2,
++ JH7100_CLK_DDRPLL_DIV4,
++ JH7100_CLK_DDRPLL_DIV8),
++ JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
++ JH7100_CLK_DDROSC_DIV2,
++ JH7100_CLK_DDRPLL_DIV2,
++ JH7100_CLK_DDRPLL_DIV4,
++ JH7100_CLK_DDRPLL_DIV8),
++ JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++ JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
++ JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
++ JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
++ JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
++ JH7100_CLK_CPU_AXI,
++ JH7100_CLK_NNEBUS_SRC1),
++ JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
++ JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
++ JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
++ JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
++ JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
++ JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
++ JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
++ JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
++ JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
++ JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
++ JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++ JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
++ JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
++ JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++ JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
++ JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
++ JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
++ JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
++ JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
++ JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
++ JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
++ JH7100_CLK_OSC_SYS,
++ JH7100_CLK_USBPHY_PLLDIV25M),
++ JH7100__DIV(JH7100_CLK_AUDIO_DIV, "audio_div", 131072, JH7100_CLK_AUDIO_ROOT),
++ JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
++ JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
++ JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
++ JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
++ JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
++ JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
++ JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
++ JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
++ JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
++ JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
++ JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
++ JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
++ JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
++ JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
++ JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
++ JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
++ JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
++ JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
++ JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
++ JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
++ JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
++ JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
++ JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
++ JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
++ JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
++ JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
++ JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
++ JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
++ JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
++ JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
++ JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
++ JH7100_CLK_GMAC_GTX,
++ JH7100_CLK_GMAC_TX_INV,
++ JH7100_CLK_GMAC_RMII_TX),
++ JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
++ JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
++ JH7100_CLK_GMAC_GR_MII_RX,
++ JH7100_CLK_GMAC_RMII_RX),
++ JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
++ JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
++ JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
++ JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
++ JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
++ JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
++ JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
++ JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
++ JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
++ JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
++ JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
++ JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
++ JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
++ JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
++ JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
++ JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
++ JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
++ JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
++ JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
++ JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
++ JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
++ JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
++ JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
++ JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
++ JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
++ JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
++ JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
++ JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
++ JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
++ JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
++ JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
++ JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
++ JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
++ JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
++ JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
++};
++
++struct jh7100_clk {
++ struct clk_hw hw;
++ unsigned int idx;
++ unsigned int max_div;
++};
++
++struct jh7100_clk_priv {
++ /* protect clk enable and set rate/parent from happening at the same time */
++ spinlock_t rmw_lock;
++ struct device *dev;
++ void __iomem *base;
++ struct clk_hw *pll[3];
++ struct jh7100_clk reg[JH7100_CLK_PLL0_OUT];
++};
++
++static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
++{
++ return container_of(hw, struct jh7100_clk, hw);
++}
++
++static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
++{
++ return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
++}
++
++static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
++{
++ struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
++ void __iomem *reg = priv->base + 4 * clk->idx;
++
++ return readl_relaxed(reg);
++}
++
++static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
++{
++ struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
++ void __iomem *reg = priv->base + 4 * clk->idx;
++ unsigned long flags;
++
++ spin_lock_irqsave(&priv->rmw_lock, flags);
++ value |= readl_relaxed(reg) & ~mask;
++ writel_relaxed(value, reg);
++ spin_unlock_irqrestore(&priv->rmw_lock, flags);
++}
++
++static int jh7100_clk_enable(struct clk_hw *hw)
++{
++ struct jh7100_clk *clk = jh7100_clk_from(hw);
++
++ jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
++ return 0;
++}
++
++static void jh7100_clk_disable(struct clk_hw *hw)
++{
++ struct jh7100_clk *clk = jh7100_clk_from(hw);
++
++ jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
++}
++
++static int jh7100_clk_is_enabled(struct clk_hw *hw)
++{
++ struct jh7100_clk *clk = jh7100_clk_from(hw);
++
++ return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
++}
++
++static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct jh7100_clk *clk = jh7100_clk_from(hw);
++ u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
++
++ return div ? parent_rate / div : 0;
++}
++
++static unsigned long jh7100_clk_bestdiv(struct jh7100_clk *clk,
++ unsigned long rate, unsigned long parent)
++{
++ unsigned long max = clk->max_div;
++ unsigned long div = DIV_ROUND_UP(parent, rate);
++
++ return min(div, max);
++}
++
++static int jh7100_clk_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ struct jh7100_clk *clk = jh7100_clk_from(hw);
++ unsigned long parent = req->best_parent_rate;
++ unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
++ unsigned long div = jh7100_clk_bestdiv(clk, rate, parent);
++ unsigned long result = parent / div;
++
++ /*
++ * we want the result clamped by min_rate and max_rate if possible:
++ * case 1: div hits the max divider value, which means it's less than
++ * parent / rate, so the result is greater than rate and min_rate in
++ * particular. we can't do anything about result > max_rate because the
++ * divider doesn't go any further.
++ * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
++ * always lower or equal to rate and max_rate. however the result may
++ * turn out lower than min_rate, but then the next higher rate is fine:
++ * div - 1 = ceil(parent / rate) - 1 < parent / rate
++ * and thus
++ * min_rate <= rate < parent / (div - 1)
++ */
++ if (result < req->min_rate && div > 1)
++ result = parent / (div - 1);
++
++ req->rate = result;
++ return 0;
++}
++
++static int jh7100_clk_set_rate(struct clk_hw *hw,
++ unsigned long rate,
++ unsigned long parent_rate)
++{
++ struct jh7100_clk *clk = jh7100_clk_from(hw);
++ unsigned long div = jh7100_clk_bestdiv(clk, rate, parent_rate);
++
++ jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
++ return 0;
++}
++
++static u8 jh7100_clk_get_parent(struct clk_hw *hw)
++{
++ struct jh7100_clk *clk = jh7100_clk_from(hw);
++ u32 value = jh7100_clk_reg_get(clk);
++
++ return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
++}
++
++static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
++{
++ struct jh7100_clk *clk = jh7100_clk_from(hw);
++ u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
++
++ jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
++ return 0;
++}
++
++static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
++ struct clk_rate_request *req)
++{
++ return clk_mux_determine_rate_flags(hw, req, 0);
++}
++
++static int jh7100_clk_get_phase(struct clk_hw *hw)
++{
++ struct jh7100_clk *clk = jh7100_clk_from(hw);
++ u32 value = jh7100_clk_reg_get(clk);
++
++ return (value & JH7100_CLK_INVERT) ? 180 : 0;
++}
++
++static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
++{
++ struct jh7100_clk *clk = jh7100_clk_from(hw);
++ u32 value;
++
++ if (degrees == 0)
++ value = 0;
++ else if (degrees == 180)
++ value = JH7100_CLK_INVERT;
++ else
++ return -EINVAL;
++
++ jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
++ return 0;
++}
++
++#ifdef CONFIG_DEBUG_FS
++static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
++{
++ static const struct debugfs_reg32 jh7100_clk_reg = {
++ .name = "CTRL",
++ .offset = 0,
++ };
++ struct jh7100_clk *clk = jh7100_clk_from(hw);
++ struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
++ struct debugfs_regset32 *regset;
++
++ regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
++ if (!regset)
++ return;
++
++ regset->regs = &jh7100_clk_reg;
++ regset->nregs = 1;
++ regset->base = priv->base + 4 * clk->idx;
++
++ debugfs_create_regset32("registers", 0400, dentry, regset);
++}
++#else
++#define jh7100_clk_debug_init NULL
++#endif
++
++static const struct clk_ops jh7100_clk_gate_ops = {
++ .enable = jh7100_clk_enable,
++ .disable = jh7100_clk_disable,
++ .is_enabled = jh7100_clk_is_enabled,
++ .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops jh7100_clk_div_ops = {
++ .recalc_rate = jh7100_clk_recalc_rate,
++ .determine_rate = jh7100_clk_determine_rate,
++ .set_rate = jh7100_clk_set_rate,
++ .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops jh7100_clk_gdiv_ops = {
++ .enable = jh7100_clk_enable,
++ .disable = jh7100_clk_disable,
++ .is_enabled = jh7100_clk_is_enabled,
++ .recalc_rate = jh7100_clk_recalc_rate,
++ .determine_rate = jh7100_clk_determine_rate,
++ .set_rate = jh7100_clk_set_rate,
++ .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops jh7100_clk_mux_ops = {
++ .determine_rate = jh7100_clk_mux_determine_rate,
++ .set_parent = jh7100_clk_set_parent,
++ .get_parent = jh7100_clk_get_parent,
++ .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops jh7100_clk_gmux_ops = {
++ .enable = jh7100_clk_enable,
++ .disable = jh7100_clk_disable,
++ .is_enabled = jh7100_clk_is_enabled,
++ .determine_rate = jh7100_clk_mux_determine_rate,
++ .set_parent = jh7100_clk_set_parent,
++ .get_parent = jh7100_clk_get_parent,
++ .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops jh7100_clk_inv_ops = {
++ .get_phase = jh7100_clk_get_phase,
++ .set_phase = jh7100_clk_set_phase,
++ .debug_init = jh7100_clk_debug_init,
++};
++
++static const struct clk_ops *__init jh7100_clk_ops(u32 max)
++{
++ if (max & JH7100_CLK_DIV_MASK) {
++ if (max & JH7100_CLK_ENABLE)
++ return &jh7100_clk_gdiv_ops;
++ return &jh7100_clk_div_ops;
++ }
++
++ if (max & JH7100_CLK_MUX_MASK) {
++ if (max & JH7100_CLK_ENABLE)
++ return &jh7100_clk_gmux_ops;
++ return &jh7100_clk_mux_ops;
++ }
++
++ if (max & JH7100_CLK_ENABLE)
++ return &jh7100_clk_gate_ops;
++
++ return &jh7100_clk_inv_ops;
++}
++
++static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
++{
++ struct jh7100_clk_priv *priv = data;
++ unsigned int idx = clkspec->args[0];
++
++ if (idx < JH7100_CLK_PLL0_OUT)
++ return &priv->reg[idx].hw;
++
++ if (idx < JH7100_CLK_END)
++ return priv->pll[idx - JH7100_CLK_PLL0_OUT];
++
++ return ERR_PTR(-EINVAL);
++}
++
++static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
++{
++ struct jh7100_clk_priv *priv;
++ unsigned int idx;
++ int ret;
++
++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ spin_lock_init(&priv->rmw_lock);
++ priv->dev = &pdev->dev;
++ priv->base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(priv->base))
++ return PTR_ERR(priv->base);
++
++ priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
++ "osc_sys", 0, 40, 1);
++ if (IS_ERR(priv->pll[0]))
++ return PTR_ERR(priv->pll[0]);
++
++ priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
++ "osc_sys", 0, 64, 1);
++ if (IS_ERR(priv->pll[1]))
++ return PTR_ERR(priv->pll[1]);
++
++ priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
++ "pll2_refclk", 0, 55, 1);
++ if (IS_ERR(priv->pll[2]))
++ return PTR_ERR(priv->pll[2]);
++
++ for (idx = 0; idx < JH7100_CLK_PLL0_OUT; idx++) {
++ u32 max = jh7100_clk_data[idx].max;
++ struct clk_parent_data parents[4] = {};
++ struct clk_init_data init = {
++ .name = jh7100_clk_data[idx].name,
++ .ops = jh7100_clk_ops(max),
++ .parent_data = parents,
++ .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
++ .flags = jh7100_clk_data[idx].flags,
++ };
++ struct jh7100_clk *clk = &priv->reg[idx];
++ unsigned int i;
++
++ for (i = 0; i < init.num_parents; i++) {
++ unsigned int pidx = jh7100_clk_data[idx].parents[i];
++
++ if (pidx < JH7100_CLK_PLL0_OUT)
++ parents[i].hw = &priv->reg[pidx].hw;
++ else if (pidx < JH7100_CLK_END)
++ parents[i].hw = priv->pll[pidx - JH7100_CLK_PLL0_OUT];
++ else if (pidx == JH7100_CLK_OSC_SYS)
++ parents[i].fw_name = "osc_sys";
++ else if (pidx == JH7100_CLK_OSC_AUD)
++ parents[i].fw_name = "osc_aud";
++ else if (pidx == JH7100_CLK_GMAC_RMII_REF)
++ parents[i].fw_name = "gmac_rmii_ref";
++ else if (pidx == JH7100_CLK_GMAC_GR_MII_RX)
++ parents[i].fw_name = "gmac_gr_mii_rxclk";
++ }
++
++ clk->hw.init = &init;
++ clk->idx = idx;
++ clk->max_div = max & JH7100_CLK_DIV_MASK;
++
++ ret = devm_clk_hw_register(priv->dev, &clk->hw);
++ if (ret)
++ return ret;
++ }
++
++ return devm_of_clk_add_hw_provider(priv->dev, jh7100_clk_get, priv);
++}
++
++static const struct of_device_id clk_starfive_jh7100_match[] = {
++ { .compatible = "starfive,jh7100-clkgen" },
++ { /* sentinel */ }
++};
++
++static struct platform_driver clk_starfive_jh7100_driver = {
++ .driver = {
++ .name = "clk-starfive-jh7100",
++ .of_match_table = clk_starfive_jh7100_match,
++ .suppress_bind_attrs = true,
++ },
++};
++builtin_platform_driver_probe(clk_starfive_jh7100_driver, clk_starfive_jh7100_probe);
+--
+2.30.2
+
+++ /dev/null
-From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Fri, 14 May 2021 05:27:51 -0700
-Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
-
-Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/Kconfig | 8 +++++
- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++
- .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
- 3 files changed, 47 insertions(+)
-
-diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
-index 3c3647a..7ae47ca 100644
---- a/arch/riscv/Kconfig
-+++ b/arch/riscv/Kconfig
-@@ -550,6 +550,14 @@ config BUILTIN_DTB
- depends on OF
- default y if XIP_KERNEL
-
-+menu "CPU Power Management"
-+
-+source "drivers/cpuidle/Kconfig"
-+
-+source "drivers/cpufreq/Kconfig"
-+
-+endmenu
-+
- menu "Power management options"
-
- source "kernel/power/Kconfig"
-diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-index 7db8610..023a8fd 100644
---- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-@@ -30,6 +30,7 @@
- i-cache-size = <16384>;
- reg = <0>;
- riscv,isa = "rv64imac";
-+ clocks = <&prci PRCI_CLK_COREPLL>;
- status = "disabled";
- cpu0_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -54,6 +55,7 @@
- reg = <1>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu1_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -78,6 +80,7 @@
- reg = <2>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu2_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -102,6 +105,7 @@
- reg = <3>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu3_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -126,6 +130,7 @@
- reg = <4>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu4_intc: interrupt-controller {
- #interrupt-cells = <1>;
-diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-index a99aded..b1e7f85 100644
---- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-@@ -78,6 +78,40 @@
- compatible = "gpio-restart";
- gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
- };
-+
-+ fu540_c000_opp_table: opp-table {
-+ compatible = "operating-points-v2";
-+ opp-shared;
-+
-+ opp-350000000 {
-+ opp-hz = /bits/ 64 <350000000>;
-+ };
-+ opp-700000000 {
-+ opp-hz = /bits/ 64 <700000000>;
-+ };
-+ opp-999999999 {
-+ opp-hz = /bits/ 64 <999999999>;
-+ };
-+ opp-1400000000 {
-+ opp-hz = /bits/ 64 <1400000000>;
-+ };
-+ };
-+};
-+
-+&cpu0 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu1 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu2 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu3 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu4 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
- };
-
- &uart0 {
---
-2.7.4
-
--- /dev/null
+From 810e287e83b69ff8563bde15cae9120c802ac5d7 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Fri, 25 Jun 2021 11:30:00 +0200
+Subject: [PATCH 07/16] dt-bindings: reset: Add StarFive JH7100 reset
+ definitions
+
+Add all resets for the StarFive JH7100 reset controller.
+
+Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added
+to all definitions.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ include/dt-bindings/reset/starfive-jh7100.h | 126 ++++++++++++++++++++
+ 1 file changed, 126 insertions(+)
+ create mode 100644 include/dt-bindings/reset/starfive-jh7100.h
+
+diff --git a/include/dt-bindings/reset/starfive-jh7100.h b/include/dt-bindings/reset/starfive-jh7100.h
+new file mode 100644
+index 000000000000..540e19254f39
+--- /dev/null
++++ b/include/dt-bindings/reset/starfive-jh7100.h
+@@ -0,0 +1,126 @@
++/* SPDX-License-Identifier: GPL-2.0 OR MIT */
++/*
++ * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
++ */
++
++#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_H__
++#define __DT_BINDINGS_RESET_STARFIVE_JH7100_H__
++
++#define JH7100_RSTN_DOM3AHB_BUS 0
++#define JH7100_RSTN_DOM7AHB_BUS 1
++#define JH7100_RST_U74 2
++#define JH7100_RSTN_U74_AXI 3
++#define JH7100_RSTN_SGDMA2P_AHB 4
++#define JH7100_RSTN_SGDMA2P_AXI 5
++#define JH7100_RSTN_DMA2PNOC_AXI 6
++#define JH7100_RSTN_DLA_AXI 7
++#define JH7100_RSTN_DLANOC_AXI 8
++#define JH7100_RSTN_DLA_APB 9
++#define JH7100_RST_VP6_DRESET 10
++#define JH7100_RST_VP6_BRESET 11
++#define JH7100_RSTN_VP6_AXI 12
++#define JH7100_RSTN_VDECBRG_MAIN 13
++#define JH7100_RSTN_VDEC_AXI 14
++#define JH7100_RSTN_VDEC_BCLK 15
++#define JH7100_RSTN_VDEC_CCLK 16
++#define JH7100_RSTN_VDEC_APB 17
++#define JH7100_RSTN_JPEG_AXI 18
++#define JH7100_RSTN_JPEG_CCLK 19
++#define JH7100_RSTN_JPEG_APB 20
++#define JH7100_RSTN_JPCGC300_MAIN 21
++#define JH7100_RSTN_GC300_2X 22
++#define JH7100_RSTN_GC300_AXI 23
++#define JH7100_RSTN_GC300_AHB 24
++#define JH7100_RSTN_VENC_AXI 25
++#define JH7100_RSTN_VENCBRG_MAIN 26
++#define JH7100_RSTN_VENC_BCLK 27
++#define JH7100_RSTN_VENC_CCLK 28
++#define JH7100_RSTN_VENC_APB 29
++#define JH7100_RSTN_DDRPHY_APB 30
++#define JH7100_RSTN_NOC_ROB 31
++#define JH7100_RSTN_NOC_COG 32
++#define JH7100_RSTN_HIFI4_AXI 33
++#define JH7100_RSTN_HIFI4NOC_AXI 34
++#define JH7100_RST_HIFI4_DRESET 35
++#define JH7100_RST_HIFI4_BRESET 36
++#define JH7100_RSTN_USB_AXI 37
++#define JH7100_RSTN_USBNOC_AXI 38
++#define JH7100_RSTN_SGDMA1P_AXI 39
++#define JH7100_RSTN_DMA1P_AXI 40
++#define JH7100_RSTN_X2C_AXI 41
++#define JH7100_RSTN_NNE_AHB 42
++#define JH7100_RSTN_NNE_AXI 43
++#define JH7100_RSTN_NNENOC_AXI 44
++#define JH7100_RSTN_DLASLV_AXI 45
++#define JH7100_RSTN_DSPX2C_AXI 46
++#define JH7100_RSTN_VIN_SRC 47
++#define JH7100_RSTN_ISPSLV_AXI 48
++#define JH7100_RSTN_VIN_AXI 49
++#define JH7100_RSTN_VINNOC_AXI 50
++#define JH7100_RSTN_ISP0_AXI 51
++#define JH7100_RSTN_ISP0NOC_AXI 52
++#define JH7100_RSTN_ISP1_AXI 53
++#define JH7100_RSTN_ISP1NOC_AXI 54
++#define JH7100_RSTN_VOUT_SRC 55
++#define JH7100_RSTN_DISP_AXI 56
++#define JH7100_RSTN_DISPNOC_AXI 57
++#define JH7100_RSTN_SDIO0_AHB 58
++#define JH7100_RSTN_SDIO1_AHB 59
++#define JH7100_RSTN_GMAC_AHB 60
++#define JH7100_RSTN_SPI2AHB_AHB 61
++#define JH7100_RSTN_SPI2AHB_CORE 62
++#define JH7100_RSTN_EZMASTER_AHB 63
++#define JH7100_RST_E24 64
++#define JH7100_RSTN_QSPI_AHB 65
++#define JH7100_RSTN_QSPI_CORE 66
++#define JH7100_RSTN_QSPI_APB 67
++#define JH7100_RSTN_SEC_AHB 68
++#define JH7100_RSTN_AES 69
++#define JH7100_RSTN_PKA 70
++#define JH7100_RSTN_SHA 71
++#define JH7100_RSTN_TRNG_APB 72
++#define JH7100_RSTN_OTP_APB 73
++#define JH7100_RSTN_UART0_APB 74
++#define JH7100_RSTN_UART0_CORE 75
++#define JH7100_RSTN_UART1_APB 76
++#define JH7100_RSTN_UART1_CORE 77
++#define JH7100_RSTN_SPI0_APB 78
++#define JH7100_RSTN_SPI0_CORE 79
++#define JH7100_RSTN_SPI1_APB 80
++#define JH7100_RSTN_SPI1_CORE 81
++#define JH7100_RSTN_I2C0_APB 82
++#define JH7100_RSTN_I2C0_CORE 83
++#define JH7100_RSTN_I2C1_APB 84
++#define JH7100_RSTN_I2C1_CORE 85
++#define JH7100_RSTN_GPIO_APB 86
++#define JH7100_RSTN_UART2_APB 87
++#define JH7100_RSTN_UART2_CORE 88
++#define JH7100_RSTN_UART3_APB 89
++#define JH7100_RSTN_UART3_CORE 90
++#define JH7100_RSTN_SPI2_APB 91
++#define JH7100_RSTN_SPI2_CORE 92
++#define JH7100_RSTN_SPI3_APB 93
++#define JH7100_RSTN_SPI3_CORE 94
++#define JH7100_RSTN_I2C2_APB 95
++#define JH7100_RSTN_I2C2_CORE 96
++#define JH7100_RSTN_I2C3_APB 97
++#define JH7100_RSTN_I2C3_CORE 98
++#define JH7100_RSTN_WDTIMER_APB 99
++#define JH7100_RSTN_WDT 100
++#define JH7100_RSTN_TIMER0 101
++#define JH7100_RSTN_TIMER1 102
++#define JH7100_RSTN_TIMER2 103
++#define JH7100_RSTN_TIMER3 104
++#define JH7100_RSTN_TIMER4 105
++#define JH7100_RSTN_TIMER5 106
++#define JH7100_RSTN_TIMER6 107
++#define JH7100_RSTN_VP6INTC_APB 108
++#define JH7100_RSTN_PWM_APB 109
++#define JH7100_RSTN_MSI_APB 110
++#define JH7100_RSTN_TEMP_APB 111
++#define JH7100_RSTN_TEMP_SENSE 112
++#define JH7100_RSTN_SYSERR_APB 113
++
++#define JH7100_RSTN_END 114
++
++#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ */
+--
+2.30.2
+
+++ /dev/null
-From 512834e96c3dd8778278836e2d132d9381c1f129 Mon Sep 17 00:00:00 2001
-From: Stanislaw Kardach <kda@semihalf.com>
-Date: Mon, 12 Apr 2021 13:10:12 +0200
-Subject: [PATCH 7/7] riscv: enable generic PCI resource mapping
-
-Enable the PCI resource mapping on RISC-V using the generic framework.
-This allows userspace applications to mmap PCI resources using
-/sys/devices/pci*/*/resource* interface.
-The mmap has been tested with Intel x520-DA2 NIC card on a HiFive
-Unmatched board (SiFive FU740 SoC).
-
-Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
----
- arch/riscv/include/asm/pci.h | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/riscv/include/asm/pci.h b/arch/riscv/include/asm/pci.h
-index 658e112..7fd52a3 100644
---- a/arch/riscv/include/asm/pci.h
-+++ b/arch/riscv/include/asm/pci.h
-@@ -18,6 +18,8 @@
- /* RISC-V shim does not initialize PCI bus */
- #define pcibios_assign_all_busses() 1
-
-+#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
-+
- extern int isa_dma_bridge_buggy;
-
- #ifdef CONFIG_PCI
---
-2.7.4
-
--- /dev/null
+From d7d456a5201d2e707318bbdc4fb69a3407eed29e Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 19 Sep 2021 14:34:34 +0200
+Subject: [PATCH 08/16] dt-bindings: reset: Add Starfive JH7100 reset bindings
+
+Add bindings for the reset controller on the JH7100 RISC-V SoC by
+StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
+
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../bindings/reset/starfive,jh7100-reset.yaml | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
+
+diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
+new file mode 100644
+index 000000000000..300359a5e14b
+--- /dev/null
++++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
+@@ -0,0 +1,38 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive JH7100 SoC Reset Controller Device Tree Bindings
++
++maintainers:
++ - Emil Renner Berthing <kernel@esmil.dk>
++
++properties:
++ compatible:
++ enum:
++ - starfive,jh7100-reset
++
++ reg:
++ maxItems: 1
++
++ "#reset-cells":
++ const: 1
++
++required:
++ - compatible
++ - reg
++ - "#reset-cells"
++
++additionalProperties: false
++
++examples:
++ - |
++ reset-controller@11840000 {
++ compatible = "starfive,jh7100-reset";
++ reg = <0x11840000 0x10000>;
++ #reset-cells = <1>;
++ };
++
++...
+--
+2.30.2
+
+++ /dev/null
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-Subject: [PATCH v7 1/1] RISC-V: Use SBI SRST extension when available
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-
-The SBI SRST extension provides a standard way to poweroff and
-reboot the system irrespective to whether Linux RISC-V S-mode
-is running natively (HS-mode) or inside Guest/VM (VS-mode).
-
-The SBI SRST extension is available in the SBI v0.3 specification.
-(Refer, https://github.com/riscv/riscv-sbi-doc/releases/tag/v0.3.0-rc1)
-
-This patch extends Linux RISC-V SBI implementation to detect
-and use SBI SRST extension.
-
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
-Reviewed-by: Atish Patra <atish.patra@wdc.com>
----
- arch/riscv/include/asm/sbi.h | 24 ++++++++++++++++++++++++
- arch/riscv/kernel/sbi.c | 35 +++++++++++++++++++++++++++++++++++
- 2 files changed, 59 insertions(+)
-
-diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
-index 0d42693cb65e..289621da4a2a 100644
---- a/arch/riscv/include/asm/sbi.h
-+++ b/arch/riscv/include/asm/sbi.h
-@@ -27,6 +27,7 @@ enum sbi_ext_id {
- SBI_EXT_IPI = 0x735049,
- SBI_EXT_RFENCE = 0x52464E43,
- SBI_EXT_HSM = 0x48534D,
-+ SBI_EXT_SRST = 0x53525354,
- };
-
- enum sbi_ext_base_fid {
-@@ -70,6 +71,21 @@ enum sbi_hsm_hart_status {
- SBI_HSM_HART_STATUS_STOP_PENDING,
- };
-
-+enum sbi_ext_srst_fid {
-+ SBI_EXT_SRST_RESET = 0,
-+};
-+
-+enum sbi_srst_reset_type {
-+ SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
-+ SBI_SRST_RESET_TYPE_COLD_REBOOT,
-+ SBI_SRST_RESET_TYPE_WARM_REBOOT,
-+};
-+
-+enum sbi_srst_reset_reason {
-+ SBI_SRST_RESET_REASON_NONE = 0,
-+ SBI_SRST_RESET_REASON_SYS_FAILURE,
-+};
-+
- #define SBI_SPEC_VERSION_DEFAULT 0x1
- #define SBI_SPEC_VERSION_MAJOR_SHIFT 24
- #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
-@@ -148,6 +164,14 @@ static inline unsigned long sbi_minor_version(void)
- return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
- }
-
-+/* Make SBI version */
-+static inline unsigned long sbi_mk_version(unsigned long major,
-+ unsigned long minor)
-+{
-+ return ((major & SBI_SPEC_VERSION_MAJOR_MASK) <<
-+ SBI_SPEC_VERSION_MAJOR_SHIFT) | minor;
-+}
-+
- int sbi_err_map_linux_errno(int err);
- #else /* CONFIG_RISCV_SBI */
- static inline int sbi_remote_fence_i(const unsigned long *hart_mask) { return -1; }
-diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
-index 7402a417f38e..9a84f0cb5175 100644
---- a/arch/riscv/kernel/sbi.c
-+++ b/arch/riscv/kernel/sbi.c
-@@ -7,6 +7,7 @@
-
- #include <linux/init.h>
- #include <linux/pm.h>
-+#include <linux/reboot.h>
- #include <asm/sbi.h>
- #include <asm/smp.h>
-
-@@ -501,6 +502,32 @@ int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
- }
- EXPORT_SYMBOL(sbi_remote_hfence_vvma_asid);
-
-+static void sbi_srst_reset(unsigned long type, unsigned long reason)
-+{
-+ sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_RESET, type, reason,
-+ 0, 0, 0, 0);
-+ pr_warn("%s: type=0x%lx reason=0x%lx failed\n",
-+ __func__, type, reason);
-+}
-+
-+static int sbi_srst_reboot(struct notifier_block *this,
-+ unsigned long mode, void *cmd)
-+{
-+ sbi_srst_reset((mode == REBOOT_WARM || mode == REBOOT_SOFT) ?
-+ SBI_SRST_RESET_TYPE_WARM_REBOOT :
-+ SBI_SRST_RESET_TYPE_COLD_REBOOT,
-+ SBI_SRST_RESET_REASON_NONE);
-+ return NOTIFY_DONE;
-+}
-+
-+static struct notifier_block sbi_srst_reboot_nb;
-+
-+static void sbi_srst_power_off(void)
-+{
-+ sbi_srst_reset(SBI_SRST_RESET_TYPE_SHUTDOWN,
-+ SBI_SRST_RESET_REASON_NONE);
-+}
-+
- /**
- * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
- * @extid: The extension ID to be probed.
-@@ -608,6 +635,14 @@ void __init sbi_init(void)
- } else {
- __sbi_rfence = __sbi_rfence_v01;
- }
-+ if ((sbi_spec_version >= sbi_mk_version(0, 3)) &&
-+ (sbi_probe_extension(SBI_EXT_SRST) > 0)) {
-+ pr_info("SBI SRST extension detected\n");
-+ pm_power_off = sbi_srst_power_off;
-+ sbi_srst_reboot_nb.notifier_call = sbi_srst_reboot;
-+ sbi_srst_reboot_nb.priority = 192;
-+ register_restart_handler(&sbi_srst_reboot_nb);
-+ }
- } else {
- __sbi_set_timer = __sbi_set_timer_v01;
- __sbi_send_ipi = __sbi_send_ipi_v01;
---
-2.25.1
-
-
-_______________________________________________
-linux-riscv mailing list
-linux-riscv@lists.infradead.org
-http://lists.infradead.org/mailman/listinfo/linux-riscv
-
--- /dev/null
+From 0be3a1595bf8c7f39153be02c9aae61dd2108576 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 19 Sep 2021 14:21:05 +0200
+Subject: [PATCH 09/16] reset: starfive-jh7100: Add StarFive JH7100 reset
+ driver
+
+Add a driver for the StarFive JH7100 reset controller.
+
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ MAINTAINERS | 7 ++
+ drivers/reset/Kconfig | 7 ++
+ drivers/reset/Makefile | 1 +
+ drivers/reset/reset-starfive-jh7100.c | 172 ++++++++++++++++++++++++++
+ 4 files changed, 187 insertions(+)
+ create mode 100644 drivers/reset/reset-starfive-jh7100.c
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 2548ef1f8246..1152f5d94690 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -18137,6 +18137,13 @@ F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
+ F: drivers/clk/starfive/clk-starfive-jh7100.c
+ F: include/dt-bindings/clock/starfive-jh7100.h
+
++STARFIVE JH7100 RESET CONTROLLER DRIVER
++M: Emil Renner Berthing <kernel@esmil.dk>
++S: Maintained
++F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
++F: drivers/reset/reset-starfive-jh7100.c
++F: include/dt-bindings/reset/starfive-jh7100.h
++
+ STATIC BRANCH/CALL
+ M: Peter Zijlstra <peterz@infradead.org>
+ M: Josh Poimboeuf <jpoimboe@redhat.com>
+diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
+index 85024eb1d2ea..6f8ba0ddc05f 100644
+--- a/drivers/reset/Kconfig
++++ b/drivers/reset/Kconfig
+@@ -224,6 +224,13 @@ config RESET_SOCFPGA
+ This enables the reset driver for the SoCFPGA ARMv7 platforms. This
+ driver gets initialized early during platform init calls.
+
++config RESET_STARFIVE_JH7100
++ bool "StarFive JH7100 Reset Driver"
++ depends on SOC_STARFIVE || COMPILE_TEST
++ default SOC_STARFIVE
++ help
++ This enables the reset controller driver for the StarFive JH7100 SoC.
++
+ config RESET_SUNXI
+ bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
+ default ARCH_SUNXI
+diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
+index 21d46d8869ff..bd0a97be18b5 100644
+--- a/drivers/reset/Makefile
++++ b/drivers/reset/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
+ obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
+ obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+ obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
++obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
+ obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+ obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
+ obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
+diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/reset-starfive-jh7100.c
+new file mode 100644
+index 000000000000..e28a19d271cb
+--- /dev/null
++++ b/drivers/reset/reset-starfive-jh7100.c
+@@ -0,0 +1,172 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Reset driver for the StarFive JH7100 SoC
++ *
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#include <linux/bitmap.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/mod_devicetable.h>
++#include <linux/platform_device.h>
++#include <linux/reset-controller.h>
++#include <linux/spinlock.h>
++
++#include <dt-bindings/reset/starfive-jh7100.h>
++
++/* register offsets */
++#define JH7100_RESET_ASSERT0 0x00
++#define JH7100_RESET_ASSERT1 0x04
++#define JH7100_RESET_ASSERT2 0x08
++#define JH7100_RESET_ASSERT3 0x0c
++#define JH7100_RESET_STATUS0 0x10
++#define JH7100_RESET_STATUS1 0x14
++#define JH7100_RESET_STATUS2 0x18
++#define JH7100_RESET_STATUS3 0x1c
++
++/*
++ * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
++ * line 32m + n, and writing a 0 deasserts the same line.
++ * Most reset lines have their status inverted so a 0 bit in the STATUS
++ * register means the line is asserted and a 1 means it's deasserted. A few
++ * lines don't though, so store the expected value of the status registers when
++ * all lines are asserted.
++ */
++static const u64 jh7100_reset_asserted[2] = {
++ /* STATUS0 */
++ BIT_ULL_MASK(JH7100_RST_U74) |
++ BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
++ BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
++ /* STATUS1 */
++ BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
++ BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
++ /* STATUS2 */
++ BIT_ULL_MASK(JH7100_RST_E24) |
++ /* STATUS3 */
++ 0,
++};
++
++struct jh7100_reset {
++ struct reset_controller_dev rcdev;
++ /* protect registers against concurrent read-modify-write */
++ spinlock_t lock;
++ void __iomem *base;
++};
++
++static inline struct jh7100_reset *
++jh7100_reset_from(struct reset_controller_dev *rcdev)
++{
++ return container_of(rcdev, struct jh7100_reset, rcdev);
++}
++
++static int jh7100_reset_update(struct reset_controller_dev *rcdev,
++ unsigned long id, bool assert)
++{
++ struct jh7100_reset *data = jh7100_reset_from(rcdev);
++ unsigned long offset = BIT_ULL_WORD(id);
++ u64 mask = BIT_ULL_MASK(id);
++ void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
++ void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
++ u64 done = jh7100_reset_asserted[offset] & mask;
++ u64 value;
++ unsigned long flags;
++ int ret;
++
++ if (!assert)
++ done ^= mask;
++
++ spin_lock_irqsave(&data->lock, flags);
++
++ value = readq(reg_assert);
++ if (assert)
++ value |= mask;
++ else
++ value &= ~mask;
++ writeq(value, reg_assert);
++
++ /* if the associated clock is gated, deasserting might otherwise hang forever */
++ ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
++
++ spin_unlock_irqrestore(&data->lock, flags);
++ return ret;
++}
++
++static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ return jh7100_reset_update(rcdev, id, true);
++}
++
++static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ return jh7100_reset_update(rcdev, id, false);
++}
++
++static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ int ret;
++
++ ret = jh7100_reset_assert(rcdev, id);
++ if (ret)
++ return ret;
++
++ return jh7100_reset_deassert(rcdev, id);
++}
++
++static int jh7100_reset_status(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ struct jh7100_reset *data = jh7100_reset_from(rcdev);
++ unsigned long offset = BIT_ULL_WORD(id);
++ u64 mask = BIT_ULL_MASK(id);
++ void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
++ u64 value = readq(reg_status);
++
++ return !((value ^ jh7100_reset_asserted[offset]) & mask);
++}
++
++static const struct reset_control_ops jh7100_reset_ops = {
++ .assert = jh7100_reset_assert,
++ .deassert = jh7100_reset_deassert,
++ .reset = jh7100_reset_reset,
++ .status = jh7100_reset_status,
++};
++
++static int __init jh7100_reset_probe(struct platform_device *pdev)
++{
++ struct jh7100_reset *data;
++
++ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
++
++ data->base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(data->base))
++ return PTR_ERR(data->base);
++
++ data->rcdev.ops = &jh7100_reset_ops;
++ data->rcdev.owner = THIS_MODULE;
++ data->rcdev.nr_resets = JH7100_RSTN_END;
++ data->rcdev.dev = &pdev->dev;
++ data->rcdev.of_node = pdev->dev.of_node;
++ spin_lock_init(&data->lock);
++
++ return devm_reset_controller_register(&pdev->dev, &data->rcdev);
++}
++
++static const struct of_device_id jh7100_reset_dt_ids[] = {
++ { .compatible = "starfive,jh7100-reset" },
++ { /* sentinel */ }
++};
++
++static struct platform_driver jh7100_reset_driver = {
++ .driver = {
++ .name = "jh7100-reset",
++ .of_match_table = jh7100_reset_dt_ids,
++ .suppress_bind_attrs = true,
++ },
++};
++builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);
+--
+2.30.2
+
--- /dev/null
+From 3021114b3d172cf80c074c81425741f9e26c6679 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Tue, 6 Jul 2021 20:19:06 +0200
+Subject: [PATCH 10/16] dt-bindings: pinctrl: Add StarFive pinctrl definitions
+
+Add definitons for pins and GPIO input, output and output enable
+signals on the StarFive JH7100 SoC.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../dt-bindings/pinctrl/pinctrl-starfive.h | 275 ++++++++++++++++++
+ 1 file changed, 275 insertions(+)
+ create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive.h
+
+diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive.h b/include/dt-bindings/pinctrl/pinctrl-starfive.h
+new file mode 100644
+index 000000000000..de4f75c2c9e8
+--- /dev/null
++++ b/include/dt-bindings/pinctrl/pinctrl-starfive.h
+@@ -0,0 +1,275 @@
++/* SPDX-License-Identifier: GPL-2.0 OR MIT */
++/*
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_H__
++#define __DT_BINDINGS_PINCTRL_STARFIVE_H__
++
++#define PAD_GPIO_OFFSET 0
++#define PAD_FUNC_SHARE_OFFSET 64
++#define PAD_GPIO(x) (PAD_GPIO_OFFSET + (x))
++#define PAD_FUNC_SHARE(x) (PAD_FUNC_SHARE_OFFSET + (x))
++
++/*
++ * GPIOMUX bits:
++ * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 |
++ * | dout | doen | din | dout rev | doen rev | gpio nr |
++ *
++ * dout: output signal
++ * doen: output enable signal
++ * din: optional input signal, 0xff = none
++ * dout rev: output signal reverse bit
++ * doen rev: output enable signal reverse bit
++ * gpio nr: gpio number, 0 - 63
++ */
++#define GPIOMUX(n, dout, doen, din) ( \
++ (((dout) & 0x80000000) >> (31 - 7)) | (((dout) & 0xff) << 24) | \
++ (((doen) & 0x80000000) >> (31 - 6)) | (((doen) & 0xff) << 16) | \
++ (((din) & 0xff) << 8) | \
++ ((n) & 0x3f))
++
++#define GPO_REVERSE 0x80000000
++
++#define GPO_LOW 0
++#define GPO_HIGH 1
++#define GPO_ENABLE 0
++#define GPO_DISABLE 1
++#define GPO_CLK_GMAC_PAPHYREF 2
++#define GPO_JTAG_TDO 3
++#define GPO_JTAG_TDO_OEN 4
++#define GPO_DMIC_CLK_OUT 5
++#define GPO_DSP_JTDOEN_PAD 6
++#define GPO_DSP_JTDO_PAD 7
++#define GPO_I2C0_PAD_SCK_OE 8
++#define GPO_I2C0_PAD_SCK_OEN (GPO_I2C0_PAD_SCK_OE | GPO_REVERSE)
++#define GPO_I2C0_PAD_SDA_OE 9
++#define GPO_I2C0_PAD_SDA_OEN (GPO_I2C0_PAD_SDA_OE | GPO_REVERSE)
++#define GPO_I2C1_PAD_SCK_OE 10
++#define GPO_I2C1_PAD_SCK_OEN (GPO_I2C1_PAD_SCK_OE | GPO_REVERSE)
++#define GPO_I2C1_PAD_SDA_OE 11
++#define GPO_I2C1_PAD_SDA_OEN (GPO_I2C1_PAD_SDA_OE | GPO_REVERSE)
++#define GPO_I2C2_PAD_SCK_OE 12
++#define GPO_I2C2_PAD_SCK_OEN (GPO_I2C2_PAD_SCK_OE | GPO_REVERSE)
++#define GPO_I2C2_PAD_SDA_OE 13
++#define GPO_I2C2_PAD_SDA_OEN (GPO_I2C2_PAD_SDA_OE | GPO_REVERSE)
++#define GPO_I2C3_PAD_SCK_OE 14
++#define GPO_I2C3_PAD_SCK_OEN (GPO_I2C3_PAD_SCK_OE | GPO_REVERSE)
++#define GPO_I2C3_PAD_SDA_OE 15
++#define GPO_I2C3_PAD_SDA_OEN (GPO_I2C3_PAD_SDA_OE | GPO_REVERSE)
++#define GPO_I2SRX_BCLK_OUT 16
++#define GPO_I2SRX_BCLK_OUT_OEN 17
++#define GPO_I2SRX_LRCK_OUT 18
++#define GPO_I2SRX_LRCK_OUT_OEN 19
++#define GPO_I2SRX_MCLK_OUT 20
++#define GPO_I2STX_BCLK_OUT 21
++#define GPO_I2STX_BCLK_OUT_OEN 22
++#define GPO_I2STX_LRCK_OUT 23
++#define GPO_I2STX_LRCK_OUT_OEN 24
++#define GPO_I2STX_MCLK_OUT 25
++#define GPO_I2STX_SDOUT0 26
++#define GPO_I2STX_SDOUT1 27
++#define GPO_LCD_PAD_CSM_N 28
++#define GPO_PWM_PAD_OE_N_BIT0 29
++#define GPO_PWM_PAD_OE_N_BIT1 30
++#define GPO_PWM_PAD_OE_N_BIT2 31
++#define GPO_PWM_PAD_OE_N_BIT3 32
++#define GPO_PWM_PAD_OE_N_BIT4 33
++#define GPO_PWM_PAD_OE_N_BIT5 34
++#define GPO_PWM_PAD_OE_N_BIT6 35
++#define GPO_PWM_PAD_OE_N_BIT7 36
++#define GPO_PWM_PAD_OUT_BIT0 37
++#define GPO_PWM_PAD_OUT_BIT1 38
++#define GPO_PWM_PAD_OUT_BIT2 39
++#define GPO_PWM_PAD_OUT_BIT3 40
++#define GPO_PWM_PAD_OUT_BIT4 41
++#define GPO_PWM_PAD_OUT_BIT5 42
++#define GPO_PWM_PAD_OUT_BIT6 43
++#define GPO_PWM_PAD_OUT_BIT7 44
++#define GPO_PWMDAC_LEFT_OUT 45
++#define GPO_PWMDAC_RIGHT_OUT 46
++#define GPO_QSPI_CSN1_OUT 47
++#define GPO_QSPI_CSN2_OUT 48
++#define GPO_QSPI_CSN3_OUT 49
++#define GPO_REGISTER23_SCFG_CMSENSOR_RST0 50
++#define GPO_REGISTER23_SCFG_CMSENSOR_RST1 51
++#define GPO_REGISTER32_SCFG_GMAC_PHY_RSTN 52
++#define GPO_SDIO0_PAD_CARD_POWER_EN 53
++#define GPO_SDIO0_PAD_CCLK_OUT 54
++#define GPO_SDIO0_PAD_CCMD_OE 55
++#define GPO_SDIO0_PAD_CCMD_OEN (GPO_SDIO0_PAD_CCMD_OE | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CCMD_OUT 56
++#define GPO_SDIO0_PAD_CDATA_OE_BIT0 57
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT0 (GPO_SDIO0_PAD_CDATA_OE_BIT0 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT1 58
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT1 (GPO_SDIO0_PAD_CDATA_OE_BIT1 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT2 59
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT2 (GPO_SDIO0_PAD_CDATA_OE_BIT2 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT3 60
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT3 (GPO_SDIO0_PAD_CDATA_OE_BIT3 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT4 61
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT4 (GPO_SDIO0_PAD_CDATA_OE_BIT4 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT5 62
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT5 (GPO_SDIO0_PAD_CDATA_OE_BIT5 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT6 63
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT6 (GPO_SDIO0_PAD_CDATA_OE_BIT6 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OE_BIT7 64
++#define GPO_SDIO0_PAD_CDATA_OEN_BIT7 (GPO_SDIO0_PAD_CDATA_OE_BIT7 | GPO_REVERSE)
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT0 65
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT1 66
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT2 67
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT3 68
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT4 69
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT5 70
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT6 71
++#define GPO_SDIO0_PAD_CDATA_OUT_BIT7 72
++#define GPO_SDIO0_PAD_RST_N 73
++#define GPO_SDIO1_PAD_CARD_POWER_EN 74
++#define GPO_SDIO1_PAD_CCLK_OUT 75
++#define GPO_SDIO1_PAD_CCMD_OE 76
++#define GPO_SDIO1_PAD_CCMD_OEN (GPO_SDIO1_PAD_CCMD_OE | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CCMD_OUT 77
++#define GPO_SDIO1_PAD_CDATA_OE_BIT0 78
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT0 (GPO_SDIO1_PAD_CDATA_OE_BIT0 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT1 79
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT1 (GPO_SDIO1_PAD_CDATA_OE_BIT1 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT2 80
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT2 (GPO_SDIO1_PAD_CDATA_OE_BIT2 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT3 81
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT3 (GPO_SDIO1_PAD_CDATA_OE_BIT3 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT4 82
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT4 (GPO_SDIO1_PAD_CDATA_OE_BIT4 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT5 83
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT5 (GPO_SDIO1_PAD_CDATA_OE_BIT5 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT6 84
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT6 (GPO_SDIO1_PAD_CDATA_OE_BIT6 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OE_BIT7 85
++#define GPO_SDIO1_PAD_CDATA_OEN_BIT7 (GPO_SDIO1_PAD_CDATA_OE_BIT7 | GPO_REVERSE)
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT0 86
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT1 87
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT2 88
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT3 89
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT4 90
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT5 91
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT6 92
++#define GPO_SDIO1_PAD_CDATA_OUT_BIT7 93
++#define GPO_SDIO1_PAD_RST_N 94
++#define GPO_SPDIF_TX_SDOUT 95
++#define GPO_SPDIF_TX_SDOUT_OEN 96
++#define GPO_SPI0_PAD_OE_N 97
++#define GPO_SPI0_PAD_SCK_OUT 98
++#define GPO_SPI0_PAD_SS_0_N 99
++#define GPO_SPI0_PAD_SS_1_N 100
++#define GPO_SPI0_PAD_TXD 101
++#define GPO_SPI1_PAD_OE_N 102
++#define GPO_SPI1_PAD_SCK_OUT 103
++#define GPO_SPI1_PAD_SS_0_N 104
++#define GPO_SPI1_PAD_SS_1_N 105
++#define GPO_SPI1_PAD_TXD 106
++#define GPO_SPI2_PAD_OE_N 107
++#define GPO_SPI2_PAD_SCK_OUT 108
++#define GPO_SPI2_PAD_SS_0_N 109
++#define GPO_SPI2_PAD_SS_1_N 110
++#define GPO_SPI2_PAD_TXD 111
++#define GPO_SPI2AHB_PAD_OE_N_BIT0 112
++#define GPO_SPI2AHB_PAD_OE_N_BIT1 113
++#define GPO_SPI2AHB_PAD_OE_N_BIT2 114
++#define GPO_SPI2AHB_PAD_OE_N_BIT3 115
++#define GPO_SPI2AHB_PAD_TXD_BIT0 116
++#define GPO_SPI2AHB_PAD_TXD_BIT1 117
++#define GPO_SPI2AHB_PAD_TXD_BIT2 118
++#define GPO_SPI2AHB_PAD_TXD_BIT3 119
++#define GPO_SPI3_PAD_OE_N 120
++#define GPO_SPI3_PAD_SCK_OUT 121
++#define GPO_SPI3_PAD_SS_0_N 122
++#define GPO_SPI3_PAD_SS_1_N 123
++#define GPO_SPI3_PAD_TXD 124
++#define GPO_UART0_PAD_DTRN 125
++#define GPO_UART0_PAD_RTSN 126
++#define GPO_UART0_PAD_SOUT 127
++#define GPO_UART1_PAD_SOUT 128
++#define GPO_UART2_PAD_DTR_N 129
++#define GPO_UART2_PAD_RTS_N 130
++#define GPO_UART2_PAD_SOUT 131
++#define GPO_UART3_PAD_SOUT 132
++#define GPO_USB_DRV_BUS 133
++
++#define GPI_CPU_JTAG_TCK 0
++#define GPI_CPU_JTAG_TDI 1
++#define GPI_CPU_JTAG_TMS 2
++#define GPI_CPU_JTAG_TRST 3
++#define GPI_DMIC_SDIN_BIT0 4
++#define GPI_DMIC_SDIN_BIT1 5
++#define GPI_DSP_JTCK_PAD 6
++#define GPI_DSP_JTDI_PAD 7
++#define GPI_DSP_JTMS_PAD 8
++#define GPI_DSP_TRST_PAD 9
++#define GPI_I2C0_PAD_SCK_IN 10
++#define GPI_I2C0_PAD_SDA_IN 11
++#define GPI_I2C1_PAD_SCK_IN 12
++#define GPI_I2C1_PAD_SDA_IN 13
++#define GPI_I2C2_PAD_SCK_IN 14
++#define GPI_I2C2_PAD_SDA_IN 15
++#define GPI_I2C3_PAD_SCK_IN 16
++#define GPI_I2C3_PAD_SDA_IN 17
++#define GPI_I2SRX_BCLK_IN 18
++#define GPI_I2SRX_LRCK_IN 19
++#define GPI_I2SRX_SDIN_BIT0 20
++#define GPI_I2SRX_SDIN_BIT1 21
++#define GPI_I2SRX_SDIN_BIT2 22
++#define GPI_I2STX_BCLK_IN 23
++#define GPI_I2STX_LRCK_IN 24
++#define GPI_SDIO0_PAD_CARD_DETECT_N 25
++#define GPI_SDIO0_PAD_CARD_WRITE_PRT 26
++#define GPI_SDIO0_PAD_CCMD_IN 27
++#define GPI_SDIO0_PAD_CDATA_IN_BIT0 28
++#define GPI_SDIO0_PAD_CDATA_IN_BIT1 29
++#define GPI_SDIO0_PAD_CDATA_IN_BIT2 30
++#define GPI_SDIO0_PAD_CDATA_IN_BIT3 31
++#define GPI_SDIO0_PAD_CDATA_IN_BIT4 32
++#define GPI_SDIO0_PAD_CDATA_IN_BIT5 33
++#define GPI_SDIO0_PAD_CDATA_IN_BIT6 34
++#define GPI_SDIO0_PAD_CDATA_IN_BIT7 35
++#define GPI_SDIO1_PAD_CARD_DETECT_N 36
++#define GPI_SDIO1_PAD_CARD_WRITE_PRT 37
++#define GPI_SDIO1_PAD_CCMD_IN 38
++#define GPI_SDIO1_PAD_CDATA_IN_BIT0 39
++#define GPI_SDIO1_PAD_CDATA_IN_BIT1 40
++#define GPI_SDIO1_PAD_CDATA_IN_BIT2 41
++#define GPI_SDIO1_PAD_CDATA_IN_BIT3 42
++#define GPI_SDIO1_PAD_CDATA_IN_BIT4 43
++#define GPI_SDIO1_PAD_CDATA_IN_BIT5 44
++#define GPI_SDIO1_PAD_CDATA_IN_BIT6 45
++#define GPI_SDIO1_PAD_CDATA_IN_BIT7 46
++#define GPI_SPDIF_RX_SDIN 47
++#define GPI_SPI0_PAD_RXD 48
++#define GPI_SPI0_PAD_SS_IN_N 49
++#define GPI_SPI1_PAD_RXD 50
++#define GPI_SPI1_PAD_SS_IN_N 51
++#define GPI_SPI2_PAD_RXD 52
++#define GPI_SPI2_PAD_SS_IN_N 53
++#define GPI_SPI2AHB_PAD_RXD_BIT0 54
++#define GPI_SPI2AHB_PAD_RXD_BIT1 55
++#define GPI_SPI2AHB_PAD_RXD_BIT2 56
++#define GPI_SPI2AHB_PAD_RXD_BIT3 57
++#define GPI_SPI2AHB_PAD_SS_N 58
++#define GPI_SPI2AHB_SLV_SCLKIN 59
++#define GPI_SPI3_PAD_RXD 60
++#define GPI_SPI3_PAD_SS_IN_N 61
++#define GPI_UART0_PAD_CTSN 62
++#define GPI_UART0_PAD_DCDN 63
++#define GPI_UART0_PAD_DSRN 64
++#define GPI_UART0_PAD_RIN 65
++#define GPI_UART0_PAD_SIN 66
++#define GPI_UART1_PAD_SIN 67
++#define GPI_UART2_PAD_CTS_N 68
++#define GPI_UART2_PAD_DCD_N 69
++#define GPI_UART2_PAD_DSR_N 70
++#define GPI_UART2_PAD_RI_N 71
++#define GPI_UART2_PAD_SIN 72
++#define GPI_UART3_PAD_SIN 73
++#define GPI_USB_OVER_CURRENT 74
++
++#define GPI_NONE 0xff
++
++#endif /* __DT_BINDINGS_PINCTRL_STARFIVE_H__ */
+--
+2.30.2
+
--- /dev/null
+From 7431b391df95f5b8d08fd0f9fa1a75cc038ee290 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Tue, 27 Jul 2021 14:34:33 +0200
+Subject: [PATCH 11/16] dt-bindings: pinctrl: Add StarFive JH7100 bindings
+
+Add bindings for the GPIO/pin controller on the JH7100 RISC-V SoC by
+StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.
+
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../pinctrl/starfive,jh7100-pinctrl.yaml | 307 ++++++++++++++++++
+ 1 file changed, 307 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
+
+diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
+new file mode 100644
+index 000000000000..92963604422f
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
+@@ -0,0 +1,307 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: StarFive JH7100 Pin Controller Device Tree Bindings
++
++description: |
++ Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
++
++ Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
++ and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have
++ configurable bias, drive strength, schmitt trigger etc. The SoC has an
++ interesting 2-layered approach to pin muxing best illustrated by the diagram
++ below.
++
++ Signal group 0, 1, ... or 6
++ ___|___
++ | |
++ LCD output -----------------| |
++ CMOS Camera interface ------| |--- PAD_GPIO[0]
++ Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
++ ... | | ...
++ | |--- PAD_GPIO[63]
++ -------- GPIO0 ------------| |
++ | -------|-- GPIO1 --------| |--- PAD_FUNC_SHARE[0]
++ | | | | | |--- PAD_FUNC_SHARE[1]
++ | | | | ... | | ...
++ | | | | | |--- PAD_FUNC_SHARE[141]
++ | | -----|---|-- GPIO63 ---| |
++ | | | | | | -------
++ UART0 UART1 --
++
++
++ The big MUX in the diagram only has 7 different ways of mapping peripherals
++ on the left to pins on the right. StarFive calls the 7 configurations "signal
++ groups".
++ However some peripherals have their I/O go through the 64 "GPIOs". The
++ diagram only shows UART0 and UART1, but this also includes a number of other
++ UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64
++ GPIOs such that any GPIO can be set up to be controlled by any of the
++ peripherals.
++ Note that signal group 0 doesn't map any of the GPIOs to pins, and only
++ signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63].
++
++maintainers:
++ - Emil Renner Berthing <kernel@esmil.dk>
++ - Drew Fustini <drew@beagleboard.org>
++
++properties:
++ compatible:
++ const: starfive,jh7100-pinctrl
++
++ reg:
++ minItems: 2
++ maxItems: 2
++
++ reg-names:
++ items:
++ - const: gpio
++ - const: padctl
++
++ clocks:
++ maxItems: 1
++
++ resets:
++ maxItems: 1
++
++ gpio-controller: true
++
++ "#gpio-cells":
++ const: 2
++
++ interrupts:
++ maxItems: 1
++ description: The GPIO parent interrupt.
++
++ interrupt-controller: true
++
++ "#interrupt-cells":
++ const: 2
++
++ starfive,signal-group:
++ description: |
++ Select one of the 7 signal groups. If this property is not set it
++ defaults to the configuration already chosen by the earlier boot stages.
++ $ref: /schemas/types.yaml#/definitions/uint32
++ enum: [0, 1, 2, 3, 4, 5, 6]
++
++required:
++ - compatible
++ - reg
++ - reg-names
++ - clocks
++ - gpio-controller
++ - "#gpio-cells"
++ - interrupts
++ - interrupt-controller
++ - "#interrupt-cells"
++
++patternProperties:
++ '-[0-9]+$':
++ type: object
++ patternProperties:
++ '-pins$':
++ type: object
++ description: |
++ A pinctrl node should contain at least one subnode representing the
++ pinctrl groups available on the machine. Each subnode will list the
++ pins it needs, and how they should be configured, with regard to
++ muxer configuration, bias, input enable/disable, input schmitt
++ trigger enable/disable, slew-rate and drive strength.
++ $ref: "/schemas/pinctrl/pincfg-node.yaml"
++
++ properties:
++ pins:
++ description: |
++ The list of pin identifiers that properties in the node apply to.
++ This should be set using either the PAD_GPIO or PAD_FUNC_SHARE
++ macros.
++ Either this or "pinmux" has to be specified, but not both.
++ $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pins"
++
++ pinmux:
++ description: |
++ The list of GPIOs and their mux settings that properties in the
++ node apply to. This should be set using the GPIOMUX macro.
++ Either this or "pins" has to be specified, but not both.
++ $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux"
++
++ bias-disable: true
++
++ bias-pull-up:
++ type: boolean
++
++ bias-pull-down:
++ type: boolean
++
++ drive-strength:
++ enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ]
++
++ input-enable: true
++
++ input-disable: true
++
++ input-schmitt-enable: true
++
++ input-schmitt-disable: true
++
++ slew-rate:
++ maximum: 7
++
++ starfive,strong-pull-up:
++ description: enable strong pull-up.
++ type: boolean
++
++ additionalProperties: false
++
++ additionalProperties: false
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/clock/starfive-jh7100.h>
++ #include <dt-bindings/reset/starfive-jh7100.h>
++ #include <dt-bindings/pinctrl/pinctrl-starfive.h>
++
++ soc {
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ pinctrl@11910000 {
++ compatible = "starfive,jh7100-pinctrl";
++ reg = <0x0 0x11910000 0x0 0x10000>,
++ <0x0 0x11858000 0x0 0x1000>;
++ reg-names = "gpio", "padctl";
++ clocks = <&clkgen JH7100_CLK_GPIO_APB>;
++ resets = <&clkgen JH7100_RSTN_GPIO_APB>;
++ interrupts = <32>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ starfive,signal-group = <6>;
++
++ gmac_pins_default: gmac-0 {
++ gtxclk-pins {
++ pins = <PAD_FUNC_SHARE(115)>;
++ bias-pull-up;
++ drive-strength = <35>;
++ input-enable;
++ input-schmitt-enable;
++ slew-rate = <0>;
++ };
++ miitxclk-pins {
++ pins = <PAD_FUNC_SHARE(116)>;
++ bias-pull-up;
++ drive-strength = <14>;
++ input-enable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ tx-pins {
++ pins = <PAD_FUNC_SHARE(117)>,
++ <PAD_FUNC_SHARE(119)>,
++ <PAD_FUNC_SHARE(120)>,
++ <PAD_FUNC_SHARE(121)>,
++ <PAD_FUNC_SHARE(122)>,
++ <PAD_FUNC_SHARE(123)>,
++ <PAD_FUNC_SHARE(124)>,
++ <PAD_FUNC_SHARE(125)>,
++ <PAD_FUNC_SHARE(126)>;
++ bias-disable;
++ drive-strength = <35>;
++ input-disable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ rxclk-pins {
++ pins = <PAD_FUNC_SHARE(127)>;
++ bias-pull-up;
++ drive-strength = <14>;
++ input-enable;
++ input-schmitt-disable;
++ slew-rate = <6>;
++ };
++ rxer-pins {
++ pins = <PAD_FUNC_SHARE(129)>;
++ bias-pull-up;
++ drive-strength = <14>;
++ input-enable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ rx-pins {
++ pins = <PAD_FUNC_SHARE(128)>,
++ <PAD_FUNC_SHARE(130)>,
++ <PAD_FUNC_SHARE(131)>,
++ <PAD_FUNC_SHARE(132)>,
++ <PAD_FUNC_SHARE(133)>,
++ <PAD_FUNC_SHARE(134)>,
++ <PAD_FUNC_SHARE(135)>,
++ <PAD_FUNC_SHARE(136)>,
++ <PAD_FUNC_SHARE(137)>,
++ <PAD_FUNC_SHARE(138)>,
++ <PAD_FUNC_SHARE(139)>,
++ <PAD_FUNC_SHARE(140)>,
++ <PAD_FUNC_SHARE(141)>;
++ bias-pull-up;
++ drive-strength = <14>;
++ input-enable;
++ input-schmitt-enable;
++ slew-rate = <0>;
++ };
++ };
++
++ i2c0_pins_default: i2c0-0 {
++ i2c-pins {
++ pinmux = <GPIOMUX(62, GPO_LOW,
++ GPO_I2C0_PAD_SCK_OEN,
++ GPI_I2C0_PAD_SCK_IN)>,
++ <GPIOMUX(61, GPO_LOW,
++ GPO_I2C0_PAD_SDA_OEN,
++ GPI_I2C0_PAD_SDA_IN)>;
++ bias-disable; /* external pull-up */
++ input-enable;
++ input-schmitt-enable;
++ };
++ };
++
++ uart3_pins_default: uart3-0 {
++ rx-pins {
++ pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
++ GPI_UART3_PAD_SIN)>;
++ bias-pull-up;
++ input-enable;
++ input-schmitt-enable;
++ };
++ tx-pins {
++ pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
++ GPO_ENABLE, GPI_NONE)>;
++ bias-disable;
++ input-disable;
++ input-schmitt-disable;
++ };
++ };
++ };
++
++ gmac {
++ pinctrl-0 = <&gmac_pins_default>;
++ pinctrl-names = "default";
++ };
++
++ i2c0 {
++ pinctrl-0 = <&i2c0_pins_default>;
++ pinctrl-names = "default";
++ };
++
++ uart3 {
++ pinctrl-0 = <&uart3_pins_default>;
++ pinctrl-names = "default";
++ };
++ };
++
++...
+--
+2.30.2
+
--- /dev/null
+From ec648f6b7686b716424e8e73eebb4c11ae199187 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Tue, 6 Jul 2021 20:19:06 +0200
+Subject: [PATCH 12/16] pinctrl: starfive: Add pinctrl driver for StarFive SoCs
+
+Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by
+StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which
+is said to feature only minor changes to these pinctrl/GPIO parts.
+
+For each "GPIO" there are two registers for configuring the output and
+output enable signals which may come from other peripherals. Among these
+are two special signals that are constant 0 and constant 1 respectively.
+Controlling the GPIOs from software is done by choosing one of these
+signals. In other words the same registers are used for both pin muxing
+and controlling the GPIOs, which makes it easier to combine the pinctrl
+and GPIO driver in one.
+
+I wrote the pinconf and pinmux parts, but the GPIO part of the code is
+based on the GPIO driver in the vendor tree written by Huan Feng with
+cleanups and fixes by Drew and me.
+
+Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
+Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
+Co-developed-by: Drew Fustini <drew@beagleboard.org>
+Signed-off-by: Drew Fustini <drew@beagleboard.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ MAINTAINERS | 8 +
+ drivers/pinctrl/Kconfig | 17 +
+ drivers/pinctrl/Makefile | 1 +
+ drivers/pinctrl/pinctrl-starfive.c | 1354 ++++++++++++++++++++++++++++
+ 4 files changed, 1380 insertions(+)
+ create mode 100644 drivers/pinctrl/pinctrl-starfive.c
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 1152f5d94690..30d6842969e7 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -18137,6 +18137,14 @@ F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml
+ F: drivers/clk/starfive/clk-starfive-jh7100.c
+ F: include/dt-bindings/clock/starfive-jh7100.h
+
++STARFIVE JH7100 PINCTRL DRIVER
++M: Emil Renner Berthing <kernel@esmil.dk>
++L: linux-gpio@vger.kernel.org
++S: Maintained
++F: Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
++F: drivers/pinctrl/pinctrl-starfive.c
++F: include/dt-bindings/pinctrl/pinctrl-starfive.h
++
+ STARFIVE JH7100 RESET CONTROLLER DRIVER
+ M: Emil Renner Berthing <kernel@esmil.dk>
+ S: Maintained
+diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
+index 6a961d5f8726..0d5b61e4c21e 100644
+--- a/drivers/pinctrl/Kconfig
++++ b/drivers/pinctrl/Kconfig
+@@ -281,6 +281,23 @@ config PINCTRL_ST
+ select PINCONF
+ select GPIOLIB_IRQCHIP
+
++config PINCTRL_STARFIVE
++ tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
++ depends on SOC_STARFIVE || COMPILE_TEST
++ depends on OF
++ default SOC_STARFIVE
++ select GENERIC_PINCTRL_GROUPS
++ select GENERIC_PINMUX_FUNCTIONS
++ select GENERIC_PINCONF
++ select GPIOLIB
++ select GPIOLIB_IRQCHIP
++ select OF_GPIO
++ help
++ Say yes here to support pin control on the StarFive JH7100 SoC.
++ This also provides an interface to the GPIO pins not used by other
++ peripherals supporting inputs, outputs, configuring pull-up/pull-down
++ and interrupts on input changes.
++
+ config PINCTRL_STMFX
+ tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
+ depends on I2C
+diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
+index 5e63de2ffcf4..f5bdd6b209a6 100644
+--- a/drivers/pinctrl/Makefile
++++ b/drivers/pinctrl/Makefile
+@@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
+ obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
+ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
+ obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
++obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
+ obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
+ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
+ obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
+diff --git a/drivers/pinctrl/pinctrl-starfive.c b/drivers/pinctrl/pinctrl-starfive.c
+new file mode 100644
+index 000000000000..0b912152a405
+--- /dev/null
++++ b/drivers/pinctrl/pinctrl-starfive.c
+@@ -0,0 +1,1354 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Pinctrl / GPIO driver for StarFive JH7100 SoC
++ *
++ * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd.
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++#include <linux/bits.h>
++#include <linux/clk.h>
++#include <linux/gpio/driver.h>
++#include <linux/io.h>
++#include <linux/mod_devicetable.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/reset.h>
++#include <linux/spinlock.h>
++
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinmux.h>
++
++#include <dt-bindings/pinctrl/pinctrl-starfive.h>
++
++#include "core.h"
++#include "pinctrl-utils.h"
++#include "pinmux.h"
++#include "pinconf.h"
++
++#define DRIVER_NAME "pinctrl-starfive"
++
++/*
++ * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
++ * https://github.com/starfive-tech/JH7100_Docs
++ */
++#define NR_GPIOS 64
++
++/*
++ * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts
++ * are enabled. If set to 0 the GPIO interrupts are disabled.
++ */
++#define GPIOEN 0x000
++
++/*
++ * The following 32-bit registers come in pairs, but only the offset of the
++ * first register is defined. The first controls (interrupts for) GPIO 0-31 and
++ * the second GPIO 32-63.
++ */
++
++/*
++ * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
++ * interrupt is level-triggered.
++ */
++#define GPIOIS 0x010
++
++/*
++ * Edge-Trigger Interrupt Type. If set to 1 the interrupt gets triggered on
++ * both positive and negative edges. If set to 0 the interrupt is triggered by a
++ * single edge.
++ */
++#define GPIOIBE 0x018
++
++/*
++ * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a
++ * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
++ * interrupt is triggered on a falling edge (edge-triggered) or low level
++ * (level-triggered).
++ */
++#define GPIOIEV 0x020
++
++/*
++ * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 0
++ * the interrupt is disabled (masked). Note that the current documentation is
++ * wrong and says the exct opposite of this.
++ */
++#define GPIOIE 0x028
++
++/*
++ * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
++ * interrupt.
++ */
++#define GPIOIC 0x030
++
++/*
++ * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
++ */
++#define GPIORIS 0x038
++
++/*
++ * Interrupt Status after Masking. A 1 means the configured edge or level was
++ * detected and not masked.
++ */
++#define GPIOMIS 0x040
++
++/*
++ * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is
++ * a digital 1 and if 0 the pin is a digital 0.
++ */
++#define GPIODIN 0x048
++
++/*
++ * From the data sheet section 12.2, there are 64 32-bit output data registers
++ * and 64 output enable registers. Output data and output enable registers for
++ * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is
++ * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c. The stride
++ * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n
++ * and GPOn_DOEN_CFG is 0x54 + 8n.
++ */
++#define GPON_DOUT_CFG 0x050
++#define GPON_DOEN_CFG 0x054
++
++/*
++ * From Section 12.3, there are 75 input signal configuration registers which
++ * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with
++ * GPI_USB_OVER_CURRENT_CFG 0x378
++ */
++#define GPI_CFG_OFFSET 0x250
++
++/*
++ * Pad Control Bits. There are 16 pad control bits for each pin located in 103
++ * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
++ * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16
++ * bit of each register.
++ */
++#define PAD_SLEW_RATE_MASK GENMASK(11, 9)
++#define PAD_SLEW_RATE_POS 9
++#define PAD_BIAS_STRONG_PULL_UP BIT(8)
++#define PAD_INPUT_ENABLE BIT(7)
++#define PAD_INPUT_SCHMITT_ENABLE BIT(6)
++#define PAD_BIAS_DISABLE BIT(5)
++#define PAD_BIAS_PULL_DOWN BIT(4)
++#define PAD_BIAS_MASK \
++ (PAD_BIAS_STRONG_PULL_UP | \
++ PAD_BIAS_DISABLE | \
++ PAD_BIAS_PULL_DOWN)
++#define PAD_DRIVE_STRENGTH_MASK GENMASK(3, 0)
++#define PAD_DRIVE_STRENGTH_POS 0
++
++/*
++ * From Section 11, the IO_PADSHARE_SEL register can be programmed to select
++ * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
++ * PAD_GPIO pads. This is a global setting.
++ */
++#define IO_PADSHARE_SEL 0x1a0
++
++/*
++ * This just needs to be some number such that when
++ * sfp->gpio.pin_base = PAD_INVALID_GPIO then
++ * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.
++ * That is it should underflow and return something >= NR_GPIOS.
++ */
++#define PAD_INVALID_GPIO 0x10000
++
++/*
++ * The packed pinmux values from the device tree look like this:
++ *
++ * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 |
++ * | dout | doen | din | dout rev | doen rev | gpio nr |
++ *
++ * ..but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this:
++ *
++ * | 31 | 30 - 8 | 7 - 0 |
++ * | dout/doen rev | unused | dout/doen |
++ */
++static unsigned int starfive_pinmux_to_gpio(u32 v)
++{
++ return v & (NR_GPIOS - 1);
++}
++
++static u32 starfive_pinmux_to_dout(u32 v)
++{
++ return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));
++}
++
++static u32 starfive_pinmux_to_doen(u32 v)
++{
++ return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));
++}
++
++static u32 starfive_pinmux_to_din(u32 v)
++{
++ return (v >> 8) & GENMASK(7, 0);
++}
++
++/*
++ * The maximum GPIO output current depends on the chosen drive strength:
++ *
++ * DS: 0 1 2 3 4 5 6 7
++ * mA: 14.2 21.2 28.2 35.2 42.2 49.1 56.0 62.8
++ *
++ * After rounding that is 7*DS + 14 mA
++ */
++static u32 starfive_drive_strength_to_max_mA(u16 ds)
++{
++ return 7 * ds + 14;
++}
++
++static u16 starfive_drive_strength_from_max_mA(u32 i)
++{
++ return (clamp(i, 14U, 63U) - 14) / 7;
++}
++
++struct starfive_pinctrl {
++ struct gpio_chip gc;
++ struct pinctrl_gpio_range gpios;
++ raw_spinlock_t lock;
++ void __iomem *base;
++ void __iomem *padctl;
++ struct pinctrl_dev *pctl;
++};
++
++static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,
++ unsigned int pin)
++{
++ return pin - sfp->gpios.pin_base;
++}
++
++static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp,
++ unsigned int gpio)
++{
++ return sfp->gpios.pin_base + gpio;
++}
++
++static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
++{
++ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
++
++ return container_of(gc, struct starfive_pinctrl, gc);
++}
++
++static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
++{
++ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
++
++ return container_of(gc, struct starfive_pinctrl, gc);
++}
++
++static const struct pinctrl_pin_desc starfive_pins[] = {
++ PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"),
++ PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"),
++ PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"),
++ PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"),
++ PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"),
++ PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"),
++ PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"),
++ PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"),
++ PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"),
++ PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"),
++ PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"),
++ PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"),
++ PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"),
++ PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"),
++ PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"),
++ PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"),
++ PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"),
++ PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"),
++ PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"),
++ PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"),
++ PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"),
++ PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"),
++ PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"),
++ PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"),
++ PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"),
++ PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"),
++ PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"),
++ PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"),
++ PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"),
++ PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"),
++ PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"),
++ PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"),
++ PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"),
++ PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"),
++ PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"),
++ PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"),
++ PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"),
++ PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"),
++ PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"),
++ PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"),
++ PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"),
++ PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"),
++ PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"),
++ PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"),
++ PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"),
++ PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"),
++ PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"),
++ PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"),
++ PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"),
++ PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"),
++ PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"),
++ PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"),
++ PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"),
++ PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"),
++ PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"),
++ PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"),
++ PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"),
++ PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"),
++ PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"),
++ PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"),
++ PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"),
++ PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"),
++ PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"),
++ PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(0), "FUNC_SHARE[0]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(1), "FUNC_SHARE[1]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(2), "FUNC_SHARE[2]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(3), "FUNC_SHARE[3]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(4), "FUNC_SHARE[4]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(5), "FUNC_SHARE[5]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(6), "FUNC_SHARE[6]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(7), "FUNC_SHARE[7]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(8), "FUNC_SHARE[8]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(9), "FUNC_SHARE[9]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(10), "FUNC_SHARE[10]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(11), "FUNC_SHARE[11]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(12), "FUNC_SHARE[12]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(13), "FUNC_SHARE[13]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(14), "FUNC_SHARE[14]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(15), "FUNC_SHARE[15]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(16), "FUNC_SHARE[16]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(17), "FUNC_SHARE[17]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(18), "FUNC_SHARE[18]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(19), "FUNC_SHARE[19]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(20), "FUNC_SHARE[20]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(21), "FUNC_SHARE[21]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(22), "FUNC_SHARE[22]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(23), "FUNC_SHARE[23]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(24), "FUNC_SHARE[24]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(25), "FUNC_SHARE[25]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(26), "FUNC_SHARE[26]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(27), "FUNC_SHARE[27]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(28), "FUNC_SHARE[28]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(29), "FUNC_SHARE[29]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(30), "FUNC_SHARE[30]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(31), "FUNC_SHARE[31]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(32), "FUNC_SHARE[32]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(33), "FUNC_SHARE[33]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(34), "FUNC_SHARE[34]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(35), "FUNC_SHARE[35]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(36), "FUNC_SHARE[36]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(37), "FUNC_SHARE[37]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(38), "FUNC_SHARE[38]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(39), "FUNC_SHARE[39]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(40), "FUNC_SHARE[40]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(41), "FUNC_SHARE[41]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(42), "FUNC_SHARE[42]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(43), "FUNC_SHARE[43]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(44), "FUNC_SHARE[44]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(45), "FUNC_SHARE[45]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(46), "FUNC_SHARE[46]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(47), "FUNC_SHARE[47]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(48), "FUNC_SHARE[48]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(49), "FUNC_SHARE[49]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(50), "FUNC_SHARE[50]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(51), "FUNC_SHARE[51]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(52), "FUNC_SHARE[52]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(53), "FUNC_SHARE[53]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(54), "FUNC_SHARE[54]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(55), "FUNC_SHARE[55]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(56), "FUNC_SHARE[56]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(57), "FUNC_SHARE[57]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(58), "FUNC_SHARE[58]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(59), "FUNC_SHARE[59]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(60), "FUNC_SHARE[60]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(61), "FUNC_SHARE[61]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(62), "FUNC_SHARE[62]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(63), "FUNC_SHARE[63]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(64), "FUNC_SHARE[64]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(65), "FUNC_SHARE[65]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(66), "FUNC_SHARE[66]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(67), "FUNC_SHARE[67]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(68), "FUNC_SHARE[68]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(69), "FUNC_SHARE[69]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(70), "FUNC_SHARE[70]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(71), "FUNC_SHARE[71]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(72), "FUNC_SHARE[72]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(73), "FUNC_SHARE[73]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(74), "FUNC_SHARE[74]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(75), "FUNC_SHARE[75]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(76), "FUNC_SHARE[76]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(77), "FUNC_SHARE[77]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(78), "FUNC_SHARE[78]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(79), "FUNC_SHARE[79]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(80), "FUNC_SHARE[80]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(81), "FUNC_SHARE[81]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(82), "FUNC_SHARE[82]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(83), "FUNC_SHARE[83]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(84), "FUNC_SHARE[84]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(85), "FUNC_SHARE[85]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(86), "FUNC_SHARE[86]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(87), "FUNC_SHARE[87]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(88), "FUNC_SHARE[88]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(89), "FUNC_SHARE[89]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(90), "FUNC_SHARE[90]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(91), "FUNC_SHARE[91]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(92), "FUNC_SHARE[92]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(93), "FUNC_SHARE[93]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(94), "FUNC_SHARE[94]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(95), "FUNC_SHARE[95]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(96), "FUNC_SHARE[96]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(97), "FUNC_SHARE[97]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(98), "FUNC_SHARE[98]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(99), "FUNC_SHARE[99]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(100), "FUNC_SHARE[100]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(101), "FUNC_SHARE[101]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(102), "FUNC_SHARE[102]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(103), "FUNC_SHARE[103]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(104), "FUNC_SHARE[104]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(105), "FUNC_SHARE[105]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(106), "FUNC_SHARE[106]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(107), "FUNC_SHARE[107]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(108), "FUNC_SHARE[108]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(109), "FUNC_SHARE[109]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(110), "FUNC_SHARE[110]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(111), "FUNC_SHARE[111]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(112), "FUNC_SHARE[112]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(113), "FUNC_SHARE[113]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(114), "FUNC_SHARE[114]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(115), "FUNC_SHARE[115]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(116), "FUNC_SHARE[116]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(117), "FUNC_SHARE[117]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(118), "FUNC_SHARE[118]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(119), "FUNC_SHARE[119]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(120), "FUNC_SHARE[120]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(121), "FUNC_SHARE[121]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(122), "FUNC_SHARE[122]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(123), "FUNC_SHARE[123]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(124), "FUNC_SHARE[124]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(125), "FUNC_SHARE[125]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(126), "FUNC_SHARE[126]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(127), "FUNC_SHARE[127]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(128), "FUNC_SHARE[128]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(129), "FUNC_SHARE[129]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(130), "FUNC_SHARE[130]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(131), "FUNC_SHARE[131]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(132), "FUNC_SHARE[132]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(133), "FUNC_SHARE[133]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(134), "FUNC_SHARE[134]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(135), "FUNC_SHARE[135]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(136), "FUNC_SHARE[136]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(137), "FUNC_SHARE[137]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(138), "FUNC_SHARE[138]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(139), "FUNC_SHARE[139]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(140), "FUNC_SHARE[140]"),
++ PINCTRL_PIN(PAD_FUNC_SHARE(141), "FUNC_SHARE[141]"),
++};
++
++#ifdef CONFIG_DEBUG_FS
++static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,
++ struct seq_file *s,
++ unsigned int pin)
++{
++ struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++ unsigned int gpio = starfive_pin_to_gpio(sfp, pin);
++ void __iomem *reg;
++ u32 dout, doen;
++
++ if (gpio >= NR_GPIOS)
++ return;
++
++ reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;
++ dout = readl_relaxed(reg + 0x000);
++ doen = readl_relaxed(reg + 0x004);
++
++ seq_printf(s, "dout=%lu%s doen=%lu%s",
++ dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "",
++ doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : "");
++}
++#else
++#define starfive_pin_dbg_show NULL
++#endif
++
++static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
++ struct device_node *np,
++ struct pinctrl_map **maps,
++ unsigned int *num_maps)
++{
++ struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++ struct device *dev = sfp->gc.parent;
++ struct device_node *child;
++ struct pinctrl_map *map;
++ const char **pgnames;
++ const char *grpname;
++ u32 *pinmux;
++ int ngroups;
++ int *pins;
++ int nmaps;
++ int ret;
++
++ nmaps = 0;
++ ngroups = 0;
++ for_each_child_of_node(np, child) {
++ int npinmux = of_property_count_u32_elems(child, "pinmux");
++ int npins = of_property_count_u32_elems(child, "pins");
++
++ if (npinmux > 0 && npins > 0) {
++ dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n",
++ np, child);
++ of_node_put(child);
++ return -EINVAL;
++ }
++ if (npinmux == 0 && npins == 0) {
++ dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n",
++ np, child);
++ of_node_put(child);
++ return -EINVAL;
++ }
++
++ if (npinmux > 0)
++ nmaps += 2;
++ else
++ nmaps += 1;
++ ngroups += 1;
++ }
++
++ pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
++ if (!pgnames)
++ return -ENOMEM;
++
++ map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
++ if (!map)
++ return -ENOMEM;
++
++ nmaps = 0;
++ ngroups = 0;
++ for_each_child_of_node(np, child) {
++ int npins;
++ int i;
++
++ grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
++ if (!grpname) {
++ ret = -ENOMEM;
++ goto put_child;
++ }
++
++ pgnames[ngroups++] = grpname;
++
++ if ((npins = of_property_count_u32_elems(child, "pinmux")) > 0) {
++ pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
++ if (!pins) {
++ ret = -ENOMEM;
++ goto put_child;
++ }
++
++ pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
++ if (!pinmux) {
++ ret = -ENOMEM;
++ goto put_child;
++ }
++
++ ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
++ if (ret)
++ goto put_child;
++
++ for (i = 0; i < npins; i++) {
++ unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);
++
++ pins[i] = starfive_gpio_to_pin(sfp, gpio);
++ }
++
++ map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
++ map[nmaps].data.mux.function = np->name;
++ map[nmaps].data.mux.group = grpname;
++ nmaps += 1;
++ } else if ((npins = of_property_count_u32_elems(child, "pins")) > 0) {
++ pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
++ if (!pins) {
++ ret = -ENOMEM;
++ goto put_child;
++ }
++
++ pinmux = NULL;
++
++ for (i = 0; i < npins; i++) {
++ u32 v;
++
++ ret = of_property_read_u32_index(child, "pins", i, &v);
++ if (ret)
++ goto put_child;
++ pins[i] = v;
++ }
++ } else {
++ ret = -EINVAL;
++ goto put_child;
++ }
++
++ ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux);
++ if (ret < 0) {
++ dev_err(dev, "error adding group %s: %d\n", grpname, ret);
++ goto put_child;
++ }
++
++ ret = pinconf_generic_parse_dt_config(child, pctldev,
++ &map[nmaps].data.configs.configs,
++ &map[nmaps].data.configs.num_configs);
++ if (ret) {
++ dev_err(dev, "error parsing pin config of group %s: %d\n",
++ grpname, ret);
++ goto put_child;
++ }
++
++ /* don't create a map if there are no pinconf settings */
++ if (map[nmaps].data.configs.num_configs == 0)
++ continue;
++
++ map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
++ map[nmaps].data.configs.group_or_pin = grpname;
++ nmaps += 1;
++ }
++
++ ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);
++ if (ret < 0) {
++ dev_err(dev, "error adding function %s: %d\n", np->name, ret);
++ goto free_map;
++ }
++
++ *maps = map;
++ *num_maps = nmaps;
++ return 0;
++
++put_child:
++ of_node_put(child);
++free_map:
++ pinctrl_utils_free_map(pctldev, map, nmaps);
++ return ret;
++}
++
++static const struct pinctrl_ops starfive_pinctrl_ops = {
++ .get_groups_count = pinctrl_generic_get_group_count,
++ .get_group_name = pinctrl_generic_get_group_name,
++ .get_group_pins = pinctrl_generic_get_group_pins,
++ .pin_dbg_show = starfive_pin_dbg_show,
++ .dt_node_to_map = starfive_dt_node_to_map,
++ .dt_free_map = pinctrl_utils_free_map,
++};
++
++static int starfive_set_mux(struct pinctrl_dev *pctldev,
++ unsigned int fsel, unsigned int gsel)
++{
++ struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++ struct device *dev = sfp->gc.parent;
++ const struct group_desc *group;
++ const u32 *pinmux;
++ unsigned int i;
++
++ group = pinctrl_generic_get_group(pctldev, gsel);
++ if (!group)
++ return -EINVAL;
++
++ pinmux = group->data;
++ for (i = 0; i < group->num_pins; i++) {
++ u32 v = pinmux[i];
++ unsigned int gpio = starfive_pinmux_to_gpio(v);
++ u32 dout = starfive_pinmux_to_dout(v);
++ u32 doen = starfive_pinmux_to_doen(v);
++ u32 din = starfive_pinmux_to_din(v);
++ void __iomem *reg_dout;
++ void __iomem *reg_doen;
++ void __iomem *reg_din;
++ unsigned long flags;
++
++ dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n",
++ gpio, dout, doen, din);
++
++ reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
++ reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
++ if (din != GPI_NONE)
++ reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;
++ else
++ reg_din = NULL;
++
++ raw_spin_lock_irqsave(&sfp->lock, flags);
++ writel_relaxed(dout, reg_dout);
++ writel_relaxed(doen, reg_doen);
++ if (reg_din)
++ writel_relaxed(gpio + 2, reg_din);
++ raw_spin_unlock_irqrestore(&sfp->lock, flags);
++ }
++
++ return 0;
++}
++
++static const struct pinmux_ops starfive_pinmux_ops = {
++ .get_functions_count = pinmux_generic_get_function_count,
++ .get_function_name = pinmux_generic_get_function_name,
++ .get_function_groups = pinmux_generic_get_function_groups,
++ .set_mux = starfive_set_mux,
++ .strict = true,
++};
++
++static u16 starfive_padctl_get(struct starfive_pinctrl *sfp,
++ unsigned int pin)
++{
++ void __iomem *reg = sfp->padctl + 4 * (pin / 2);
++ int shift = 16 * (pin % 2);
++
++ return readl_relaxed(reg) >> shift;
++}
++
++static void starfive_padctl_rmw(struct starfive_pinctrl *sfp,
++ unsigned int pin,
++ u16 _mask, u16 _value)
++{
++ void __iomem *reg = sfp->padctl + 4 * (pin / 2);
++ int shift = 16 * (pin % 2);
++ u32 mask = (u32)_mask << shift;
++ u32 value = (u32)_value << shift;
++ unsigned long flags;
++
++ dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);
++
++ raw_spin_lock_irqsave(&sfp->lock, flags);
++ value |= readl_relaxed(reg) & ~mask;
++ writel_relaxed(value, reg);
++ raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++#define PIN_CONFIG_STARFIVE_STRONG_PULL_UP (PIN_CONFIG_END + 1)
++
++static const struct pinconf_generic_params starfive_pinconf_custom_params[] = {
++ { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
++};
++
++#ifdef CONFIG_DEBUG_FS
++static const struct pin_config_item starfive_pinconf_custom_conf_items[] = {
++ PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
++};
++
++static_assert(ARRAY_SIZE(starfive_pinconf_custom_conf_items) ==
++ ARRAY_SIZE(starfive_pinconf_custom_params));
++#else
++#define starfive_pinconf_custom_conf_items NULL
++#endif
++
++static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
++ unsigned int pin, unsigned long *config)
++{
++ struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++ int param = pinconf_to_config_param(*config);
++ u16 value = starfive_padctl_get(sfp, pin);
++ bool enabled;
++ u32 arg;
++
++ switch (param) {
++ case PIN_CONFIG_BIAS_DISABLE:
++ enabled = value & PAD_BIAS_DISABLE;
++ arg = 0;
++ break;
++ case PIN_CONFIG_BIAS_PULL_DOWN:
++ enabled = value & PAD_BIAS_PULL_DOWN;
++ arg = 1;
++ break;
++ case PIN_CONFIG_BIAS_PULL_UP:
++ enabled = !(value & PAD_BIAS_MASK);
++ arg = 1;
++ break;
++ case PIN_CONFIG_DRIVE_STRENGTH:
++ enabled = value & PAD_DRIVE_STRENGTH_MASK;
++ arg = starfive_drive_strength_to_max_mA(value & PAD_DRIVE_STRENGTH_MASK);
++ break;
++ case PIN_CONFIG_INPUT_ENABLE:
++ enabled = value & PAD_INPUT_ENABLE;
++ arg = enabled;
++ break;
++ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
++ enabled = value & PAD_INPUT_SCHMITT_ENABLE;
++ arg = enabled;
++ break;
++ case PIN_CONFIG_SLEW_RATE:
++ enabled = value & PAD_SLEW_RATE_MASK;
++ arg = (value & PAD_SLEW_RATE_MASK) >> PAD_SLEW_RATE_POS;
++ break;
++ case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
++ enabled = value & PAD_BIAS_STRONG_PULL_UP;
++ arg = enabled;
++ break;
++ default:
++ return -ENOTSUPP;
++ }
++
++ *config = pinconf_to_config_packed(param, arg);
++ return enabled ? 0 : -EINVAL;
++}
++
++static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,
++ unsigned int gsel, unsigned long *config)
++{
++ const struct group_desc *group;
++
++ group = pinctrl_generic_get_group(pctldev, gsel);
++ if (!group)
++ return -EINVAL;
++
++ return starfive_pinconf_get(pctldev, group->pins[0], config);
++}
++
++static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
++ unsigned int gsel,
++ unsigned long *configs,
++ unsigned int num_configs)
++{
++ struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++ const struct group_desc *group;
++ u16 mask, value;
++ int i;
++
++ group = pinctrl_generic_get_group(pctldev, gsel);
++ if (!group)
++ return -EINVAL;
++
++ mask = 0;
++ value = 0;
++ for (i = 0; i < num_configs; i++) {
++ int param = pinconf_to_config_param(configs[i]);
++ u32 arg = pinconf_to_config_argument(configs[i]);
++
++ switch (param) {
++ case PIN_CONFIG_BIAS_DISABLE:
++ mask |= PAD_BIAS_MASK;
++ value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_DISABLE;
++ break;
++ case PIN_CONFIG_BIAS_PULL_DOWN:
++ if (arg == 0)
++ return -ENOTSUPP;
++ mask |= PAD_BIAS_MASK;
++ value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_PULL_DOWN;
++ break;
++ case PIN_CONFIG_BIAS_PULL_UP:
++ if (arg == 0)
++ return -ENOTSUPP;
++ mask |= PAD_BIAS_MASK;
++ value = value & ~PAD_BIAS_MASK;
++ break;
++ case PIN_CONFIG_DRIVE_STRENGTH:
++ mask |= PAD_DRIVE_STRENGTH_MASK;
++ value = (value & ~PAD_DRIVE_STRENGTH_MASK) |
++ starfive_drive_strength_from_max_mA(arg);
++ break;
++ case PIN_CONFIG_INPUT_ENABLE:
++ mask |= PAD_INPUT_ENABLE;
++ if (arg)
++ value |= PAD_INPUT_ENABLE;
++ else
++ value &= ~PAD_INPUT_ENABLE;
++ break;
++ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
++ mask |= PAD_INPUT_SCHMITT_ENABLE;
++ if (arg)
++ value |= PAD_INPUT_SCHMITT_ENABLE;
++ else
++ value &= ~PAD_INPUT_SCHMITT_ENABLE;
++ break;
++ case PIN_CONFIG_SLEW_RATE:
++ mask |= PAD_SLEW_RATE_MASK;
++ value = (value & ~PAD_SLEW_RATE_MASK) |
++ ((arg << PAD_SLEW_RATE_POS) & PAD_SLEW_RATE_MASK);
++ break;
++ case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
++ if (arg) {
++ mask |= PAD_BIAS_MASK;
++ value = (value & ~PAD_BIAS_MASK) |
++ PAD_BIAS_STRONG_PULL_UP;
++ } else {
++ mask |= PAD_BIAS_STRONG_PULL_UP;
++ value = value & ~PAD_BIAS_STRONG_PULL_UP;
++ }
++ break;
++ default:
++ return -ENOTSUPP;
++ }
++ }
++
++ for (i = 0; i < group->num_pins; i++)
++ starfive_padctl_rmw(sfp, group->pins[i], mask, value);
++
++ return 0;
++}
++
++#ifdef CONFIG_DEBUG_FS
++static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
++ struct seq_file *s, unsigned int pin)
++{
++ struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
++ u16 value = starfive_padctl_get(sfp, pin);
++
++ seq_printf(s, " (0x%03x)", value);
++}
++#else
++#define starfive_pinconf_dbg_show NULL
++#endif
++
++static const struct pinconf_ops starfive_pinconf_ops = {
++ .pin_config_get = starfive_pinconf_get,
++ .pin_config_group_get = starfive_pinconf_group_get,
++ .pin_config_group_set = starfive_pinconf_group_set,
++ .pin_config_dbg_show = starfive_pinconf_dbg_show,
++ .is_generic = true,
++};
++
++static struct pinctrl_desc starfive_desc = {
++ .name = DRIVER_NAME,
++ .pins = starfive_pins,
++ .npins = ARRAY_SIZE(starfive_pins),
++ .pctlops = &starfive_pinctrl_ops,
++ .pmxops = &starfive_pinmux_ops,
++ .confops = &starfive_pinconf_ops,
++ .owner = THIS_MODULE,
++ .num_custom_params = ARRAY_SIZE(starfive_pinconf_custom_params),
++ .custom_params = starfive_pinconf_custom_params,
++ .custom_conf_items = starfive_pinconf_custom_conf_items,
++};
++
++static int starfive_gpio_request(struct gpio_chip *gc, unsigned int gpio)
++{
++ return pinctrl_gpio_request(gc->base + gpio);
++}
++
++static void starfive_gpio_free(struct gpio_chip *gc, unsigned int gpio)
++{
++ pinctrl_gpio_free(gc->base + gpio);
++}
++
++static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
++{
++ struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++ void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
++
++ if (readl_relaxed(doen) == GPO_ENABLE)
++ return GPIO_LINE_DIRECTION_OUT;
++
++ return GPIO_LINE_DIRECTION_IN;
++}
++
++static int starfive_gpio_direction_input(struct gpio_chip *gc,
++ unsigned int gpio)
++{
++ struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++ void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
++ unsigned long flags;
++
++ /* enable input and schmitt trigger */
++ starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
++ PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
++ PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE);
++
++ raw_spin_lock_irqsave(&sfp->lock, flags);
++ writel_relaxed(GPO_DISABLE, doen);
++ raw_spin_unlock_irqrestore(&sfp->lock, flags);
++ return 0;
++}
++
++static int starfive_gpio_direction_output(struct gpio_chip *gc,
++ unsigned int gpio, int value)
++{
++ struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++ void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
++ void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
++ unsigned long flags;
++
++ raw_spin_lock_irqsave(&sfp->lock, flags);
++ writel_relaxed(value, dout);
++ writel_relaxed(GPO_ENABLE, doen);
++ raw_spin_unlock_irqrestore(&sfp->lock, flags);
++
++ /* disable input, schmitt trigger and bias */
++ starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
++ PAD_BIAS_MASK | PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
++ PAD_BIAS_DISABLE);
++
++ return 0;
++}
++
++static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio)
++{
++ struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++ void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);
++
++ return !!(readl_relaxed(din) & BIT(gpio % 32));
++}
++
++static void starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,
++ int value)
++{
++ struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++ void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
++ unsigned long flags;
++
++ raw_spin_lock_irqsave(&sfp->lock, flags);
++ writel_relaxed(value, dout);
++ raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,
++ unsigned long config)
++{
++ struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++ u32 arg = pinconf_to_config_argument(config);
++ u16 value;
++ u16 mask;
++
++ switch (pinconf_to_config_param(config)) {
++ case PIN_CONFIG_BIAS_DISABLE:
++ mask = PAD_BIAS_MASK;
++ value = PAD_BIAS_DISABLE;
++ break;
++ case PIN_CONFIG_BIAS_PULL_DOWN:
++ if (arg == 0)
++ return -ENOTSUPP;
++ mask = PAD_BIAS_MASK;
++ value = PAD_BIAS_PULL_DOWN;
++ break;
++ case PIN_CONFIG_BIAS_PULL_UP:
++ if (arg == 0)
++ return -ENOTSUPP;
++ mask = PAD_BIAS_MASK;
++ value = 0;
++ break;
++ case PIN_CONFIG_DRIVE_PUSH_PULL:
++ return 0;
++ case PIN_CONFIG_INPUT_ENABLE:
++ mask = PAD_INPUT_ENABLE;
++ value = arg ? PAD_INPUT_ENABLE : 0;
++ break;
++ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
++ mask = PAD_INPUT_SCHMITT_ENABLE;
++ value = arg ? PAD_INPUT_SCHMITT_ENABLE : 0;
++ break;
++ default:
++ return -ENOTSUPP;
++ };
++
++ starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
++ return 0;
++}
++
++static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc)
++{
++ struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++
++ sfp->gpios.name = sfp->gc.label;
++ sfp->gpios.base = sfp->gc.base;
++ /*
++ * sfp->gpios.pin_base depends on the chosen signal group
++ * and is set in starfive_probe()
++ */
++ sfp->gpios.npins = NR_GPIOS;
++ sfp->gpios.gc = &sfp->gc;
++ pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
++ return 0;
++}
++
++static void starfive_irq_ack(struct irq_data *d)
++{
++ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
++ irq_hw_number_t gpio = irqd_to_hwirq(d);
++ void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
++ u32 mask = BIT(gpio % 32);
++ unsigned long flags;
++
++ raw_spin_lock_irqsave(&sfp->lock, flags);
++ writel_relaxed(mask, ic);
++ raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++static void starfive_irq_mask(struct irq_data *d)
++{
++ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
++ irq_hw_number_t gpio = irqd_to_hwirq(d);
++ void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
++ u32 mask = BIT(gpio % 32);
++ unsigned long flags;
++ u32 value;
++
++ raw_spin_lock_irqsave(&sfp->lock, flags);
++ value = readl_relaxed(ie) & ~mask;
++ writel_relaxed(value, ie);
++ raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++static void starfive_irq_mask_ack(struct irq_data *d)
++{
++ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
++ irq_hw_number_t gpio = irqd_to_hwirq(d);
++ void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
++ void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
++ u32 mask = BIT(gpio % 32);
++ unsigned long flags;
++ u32 value;
++
++ raw_spin_lock_irqsave(&sfp->lock, flags);
++ value = readl_relaxed(ie) & ~mask;
++ writel_relaxed(value, ie);
++ writel_relaxed(mask, ic);
++ raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++static void starfive_irq_unmask(struct irq_data *d)
++{
++ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
++ irq_hw_number_t gpio = irqd_to_hwirq(d);
++ void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
++ u32 mask = BIT(gpio % 32);
++ unsigned long flags;
++ u32 value;
++
++ raw_spin_lock_irqsave(&sfp->lock, flags);
++ value = readl_relaxed(ie) | mask;
++ writel_relaxed(value, ie);
++ raw_spin_unlock_irqrestore(&sfp->lock, flags);
++}
++
++static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)
++{
++ struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
++ irq_hw_number_t gpio = irqd_to_hwirq(d);
++ void __iomem *base = sfp->base + 4 * (gpio / 32);
++ u32 mask = BIT(gpio % 32);
++ u32 irq_type, edge_both, polarity;
++ unsigned long flags;
++
++ switch (trigger) {
++ case IRQ_TYPE_EDGE_RISING:
++ irq_type = mask; /* 1: edge triggered */
++ edge_both = 0; /* 0: single edge */
++ polarity = mask; /* 1: rising edge */
++ break;
++ case IRQ_TYPE_EDGE_FALLING:
++ irq_type = mask; /* 1: edge triggered */
++ edge_both = 0; /* 0: single edge */
++ polarity = 0; /* 0: falling edge */
++ break;
++ case IRQ_TYPE_EDGE_BOTH:
++ irq_type = mask; /* 1: edge triggered */
++ edge_both = mask; /* 1: both edges */
++ polarity = 0; /* 0: ignored */
++ break;
++ case IRQ_TYPE_LEVEL_HIGH:
++ irq_type = 0; /* 0: level triggered */
++ edge_both = 0; /* 0: ignored */
++ polarity = mask; /* 1: high level */
++ break;
++ case IRQ_TYPE_LEVEL_LOW:
++ irq_type = 0; /* 0: level triggered */
++ edge_both = 0; /* 0: ignored */
++ polarity = 0; /* 0: low level */
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ if (trigger & IRQ_TYPE_EDGE_BOTH)
++ irq_set_handler_locked(d, handle_edge_irq);
++ else
++ irq_set_handler_locked(d, handle_level_irq);
++
++ raw_spin_lock_irqsave(&sfp->lock, flags);
++ irq_type |= readl_relaxed(base + GPIOIS) & ~mask;
++ writel_relaxed(irq_type, base + GPIOIS);
++ edge_both |= readl_relaxed(base + GPIOIBE) & ~mask;
++ writel_relaxed(edge_both, base + GPIOIBE);
++ polarity |= readl_relaxed(base + GPIOIEV) & ~mask;
++ writel_relaxed(polarity, base + GPIOIEV);
++ raw_spin_unlock_irqrestore(&sfp->lock, flags);
++ return 0;
++}
++
++static struct irq_chip starfive_irq_chip = {
++ .irq_ack = starfive_irq_ack,
++ .irq_mask = starfive_irq_mask,
++ .irq_mask_ack = starfive_irq_mask_ack,
++ .irq_unmask = starfive_irq_unmask,
++ .irq_set_type = starfive_irq_set_type,
++ .flags = IRQCHIP_SET_TYPE_MASKED,
++};
++
++static void starfive_gpio_irq_handler(struct irq_desc *desc)
++{
++ struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
++ struct irq_chip *chip = irq_desc_get_chip(desc);
++ unsigned long mis;
++ unsigned int pin;
++
++ chained_irq_enter(chip, desc);
++
++ mis = readl_relaxed(sfp->base + GPIOMIS + 0);
++ for_each_set_bit(pin, &mis, 32)
++ generic_handle_domain_irq(sfp->gc.irq.domain, pin);
++
++ mis = readl_relaxed(sfp->base + GPIOMIS + 4);
++ for_each_set_bit(pin, &mis, 32)
++ generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
++
++ chained_irq_exit(chip, desc);
++}
++
++static int starfive_gpio_init_hw(struct gpio_chip *gc)
++{
++ struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
++
++ /* mask all GPIO interrupts */
++ writel(0, sfp->base + GPIOIE + 0);
++ writel(0, sfp->base + GPIOIE + 4);
++ /* clear edge interrupt flags */
++ writel(~0U, sfp->base + GPIOIC + 0);
++ writel(~0U, sfp->base + GPIOIC + 4);
++ /* enable GPIO interrupts */
++ writel(1, sfp->base + GPIOEN);
++ return 0;
++}
++
++static void starfive_disable_clock(void *data)
++{
++ clk_disable_unprepare(data);
++}
++
++static int starfive_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct starfive_pinctrl *sfp;
++ struct reset_control *rst;
++ struct clk *clk;
++ u32 value;
++ int ret;
++
++ sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
++ if (!sfp)
++ return -ENOMEM;
++
++ sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
++ if (IS_ERR(sfp->base))
++ return PTR_ERR(sfp->base);
++
++ sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");
++ if (IS_ERR(sfp->padctl))
++ return PTR_ERR(sfp->padctl);
++
++ clk = devm_clk_get(dev, NULL);
++ if (IS_ERR(clk))
++ return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
++
++ rst = devm_reset_control_get_exclusive(dev, NULL);
++ if (IS_ERR(rst))
++ return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
++
++ ret = clk_prepare_enable(clk);
++ if (ret)
++ return dev_err_probe(dev, ret, "could not enable clock\n");
++
++ ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
++ if (ret)
++ return ret;
++
++ /*
++ * We don't want to assert reset and risk undoing pin muxing for the
++ * early boot serial console, but let's make sure the reset line is
++ * deasserted in case someone runs a really minimal bootloader.
++ */
++ ret = reset_control_deassert(rst);
++ if (ret)
++ return dev_err_probe(dev, ret, "could not deassert reset\n");
++
++ platform_set_drvdata(pdev, sfp);
++ sfp->gc.parent = dev;
++ raw_spin_lock_init(&sfp->lock);
++
++ ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);
++ if (ret)
++ return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
++
++ if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {
++ if (value > 6)
++ return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
++ writel(value, sfp->padctl + IO_PADSHARE_SEL);
++ }
++
++ value = readl(sfp->padctl + IO_PADSHARE_SEL);
++ switch (value) {
++ case 0:
++ sfp->gpios.pin_base = PAD_INVALID_GPIO;
++ goto out_pinctrl_enable;
++ case 1:
++ sfp->gpios.pin_base = PAD_GPIO(0);
++ break;
++ case 2:
++ sfp->gpios.pin_base = PAD_FUNC_SHARE(72);
++ break;
++ case 3:
++ sfp->gpios.pin_base = PAD_FUNC_SHARE(70);
++ break;
++ case 4: case 5: case 6:
++ sfp->gpios.pin_base = PAD_FUNC_SHARE(0);
++ break;
++ default:
++ return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
++ }
++
++ sfp->gc.label = dev_name(dev);
++ sfp->gc.owner = THIS_MODULE;
++ sfp->gc.request = starfive_gpio_request;
++ sfp->gc.free = starfive_gpio_free;
++ sfp->gc.get_direction = starfive_gpio_get_direction;
++ sfp->gc.direction_input = starfive_gpio_direction_input;
++ sfp->gc.direction_output = starfive_gpio_direction_output;
++ sfp->gc.get = starfive_gpio_get;
++ sfp->gc.set = starfive_gpio_set;
++ sfp->gc.set_config = starfive_gpio_set_config;
++ sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
++ sfp->gc.base = -1;
++ sfp->gc.ngpio = NR_GPIOS;
++
++ starfive_irq_chip.parent_device = dev;
++ starfive_irq_chip.name = sfp->gc.label;
++
++ sfp->gc.irq.chip = &starfive_irq_chip;
++ sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
++ sfp->gc.irq.num_parents = 1;
++ sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
++ sizeof(*sfp->gc.irq.parents), GFP_KERNEL);
++ if (!sfp->gc.irq.parents)
++ return -ENOMEM;
++ sfp->gc.irq.default_type = IRQ_TYPE_NONE;
++ sfp->gc.irq.handler = handle_bad_irq;
++ sfp->gc.irq.init_hw = starfive_gpio_init_hw;
++
++ ret = platform_get_irq(pdev, 0);
++ if (ret < 0)
++ return ret;
++ sfp->gc.irq.parents[0] = ret;
++
++ ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
++ if (ret)
++ return dev_err_probe(dev, ret, "could not register gpiochip\n");
++
++out_pinctrl_enable:
++ return pinctrl_enable(sfp->pctl);
++}
++
++static const struct of_device_id starfive_of_match[] = {
++ { .compatible = "starfive,jh7100-pinctrl" },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, starfive_of_match);
++
++static struct platform_driver starfive_pinctrl_driver = {
++ .probe = starfive_probe,
++ .driver = {
++ .name = DRIVER_NAME,
++ .of_match_table = starfive_of_match,
++ },
++};
++module_platform_driver(starfive_pinctrl_driver);
++
++MODULE_DESCRIPTION("Pinctrl driver for StarFive SoCs");
++MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
++MODULE_LICENSE("GPL v2");
+--
+2.30.2
+
--- /dev/null
+From d0b65b1500973fef840dbc4bb9f9c237db2b761f Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Thu, 7 Oct 2021 14:24:29 +0200
+Subject: [PATCH 13/16] dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts
+
+Add compatibles for the StarFive JH7100 uarts.
+
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ .../devicetree/bindings/serial/snps-dw-apb-uart.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+index b49fda5e608f..12137fe80acf 100644
+--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
++++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+@@ -40,6 +40,11 @@ properties:
+ - brcm,bcm11351-dw-apb-uart
+ - brcm,bcm21664-dw-apb-uart
+ - const: snps,dw-apb-uart
++ - items:
++ - enum:
++ - starfive,jh7100-hsuart
++ - starfive,jh7100-uart
++ - const: snps,dw-apb-uart
+ - const: snps,dw-apb-uart
+
+ reg:
+--
+2.30.2
+
--- /dev/null
+From b0ad20a3b64bf653a717860819691b262c0b2a2b Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Mon, 4 Oct 2021 19:40:29 +0200
+Subject: [PATCH 14/16] serial: 8250_dw: Add StarFive JH7100 quirk
+
+On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
+exactly 16 * 115200Hz and many other common bitrates. Trying this will
+only result in a higher input clock, but low enough that the UART's
+internal divisor can't come close enough to the baud rate target.
+So rather than try to set the input clock it's better to skip the
+clk_set_rate call and rely solely on the UART's internal divisor.
+
+Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ drivers/tty/serial/8250/8250_dw.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
+index 53f57c3b9f42..1769808031c5 100644
+--- a/drivers/tty/serial/8250/8250_dw.c
++++ b/drivers/tty/serial/8250/8250_dw.c
+@@ -414,6 +414,8 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
+
+ if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
+ p->serial_out = dw8250_serial_out38x;
++ if (of_device_is_compatible(np, "starfive,jh7100-uart"))
++ p->set_termios = dw8250_do_set_termios;
+
+ } else if (acpi_dev_present("APMC0D08", NULL, -1)) {
+ p->iotype = UPIO_MEM32;
+@@ -696,6 +698,7 @@ static const struct of_device_id dw8250_of_match[] = {
+ { .compatible = "cavium,octeon-3860-uart" },
+ { .compatible = "marvell,armada-38x-uart" },
+ { .compatible = "renesas,rzn1-uart" },
++ { .compatible = "starfive,jh7100-uart" },
+ { /* Sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, dw8250_of_match);
+--
+2.30.2
+
--- /dev/null
+From ec85362fb121d0297b9f3bb56816ea6282c34fda Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 10 Oct 2021 16:48:27 +0200
+Subject: [PATCH 15/16] RISC-V: Add initial StarFive JH7100 device tree
+
+Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This
+is a test chip for their upcoming JH7110 SoC.
+
+The CPU and cache data is based on the device tree in the vendor u-boot
+port.
+
+Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/boot/dts/starfive/jh7100.dtsi | 230 +++++++++++++++++++++++
+ 1 file changed, 230 insertions(+)
+ create mode 100644 arch/riscv/boot/dts/starfive/jh7100.dtsi
+
+diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+new file mode 100644
+index 000000000000..69f22f9aad9d
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -0,0 +1,230 @@
++// SPDX-License-Identifier: GPL-2.0 OR MIT
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++/dts-v1/;
++#include <dt-bindings/clock/starfive-jh7100.h>
++#include <dt-bindings/reset/starfive-jh7100.h>
++
++/ {
++ compatible = "starfive,jh7100";
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ compatible = "sifive,u74-mc", "riscv";
++ reg = <0>;
++ d-cache-block-size = <64>;
++ d-cache-sets = <64>;
++ d-cache-size = <32768>;
++ d-tlb-sets = <1>;
++ d-tlb-size = <32>;
++ device_type = "cpu";
++ i-cache-block-size = <64>;
++ i-cache-sets = <64>;
++ i-cache-size = <32768>;
++ i-tlb-sets = <1>;
++ i-tlb-size = <32>;
++ mmu-type = "riscv,sv39";
++ riscv,isa = "rv64imafdc";
++ tlb-split;
++
++ cpu0_intc: interrupt-controller {
++ compatible = "riscv,cpu-intc";
++ interrupt-controller;
++ #interrupt-cells = <1>;
++ };
++ };
++
++ cpu@1 {
++ compatible = "sifive,u74-mc", "riscv";
++ reg = <1>;
++ d-cache-block-size = <64>;
++ d-cache-sets = <64>;
++ d-cache-size = <32768>;
++ d-tlb-sets = <1>;
++ d-tlb-size = <32>;
++ device_type = "cpu";
++ i-cache-block-size = <64>;
++ i-cache-sets = <64>;
++ i-cache-size = <32768>;
++ i-tlb-sets = <1>;
++ i-tlb-size = <32>;
++ mmu-type = "riscv,sv39";
++ riscv,isa = "rv64imafdc";
++ tlb-split;
++
++ cpu1_intc: interrupt-controller {
++ compatible = "riscv,cpu-intc";
++ interrupt-controller;
++ #interrupt-cells = <1>;
++ };
++ };
++ };
++
++ osc_sys: osc_sys {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ /* This value must be overridden by the board */
++ clock-frequency = <0>;
++ };
++
++ osc_aud: osc_aud {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ /* This value must be overridden by the board */
++ clock-frequency = <0>;
++ };
++
++ gmac_rmii_ref: gmac_rmii_ref {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ /* Should be overridden by the board when needed */
++ clock-frequency = <0>;
++ };
++
++ gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ /* Should be overridden by the board when needed */
++ clock-frequency = <0>;
++ };
++
++ soc {
++ compatible = "simple-bus";
++ interrupt-parent = <&plic>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ clint: clint@2000000 {
++ compatible = "starfive,jh7100-clint", "sifive,clint0";
++ reg = <0x0 0x2000000 0x0 0x10000>;
++ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
++ &cpu1_intc 3 &cpu1_intc 7>;
++ };
++
++ plic: interrupt-controller@c000000 {
++ compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
++ reg = <0x0 0xc000000 0x0 0x4000000>;
++ interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
++ &cpu1_intc 11 &cpu1_intc 9>;
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ riscv,ndev = <127>;
++ };
++
++ clkgen: clock-controller@11800000 {
++ compatible = "starfive,jh7100-clkgen";
++ reg = <0x0 0x11800000 0x0 0x10000>;
++ clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
++ clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
++ #clock-cells = <1>;
++ };
++
++ rstgen: reset-controller@11840000 {
++ compatible = "starfive,jh7100-reset";
++ reg = <0x0 0x11840000 0x0 0x10000>;
++ #reset-cells = <1>;
++ };
++
++ i2c0: i2c@118b0000 {
++ compatible = "snps,designware-i2c";
++ reg = <0x0 0x118b0000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
++ <&clkgen JH7100_CLK_I2C0_APB>;
++ clock-names = "ref", "pclk";
++ resets = <&rstgen JH7100_RSTN_I2C0_APB>;
++ interrupts = <96>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c1: i2c@118c0000 {
++ compatible = "snps,designware-i2c";
++ reg = <0x0 0x118c0000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
++ <&clkgen JH7100_CLK_I2C1_APB>;
++ clock-names = "ref", "pclk";
++ resets = <&rstgen JH7100_RSTN_I2C1_APB>;
++ interrupts = <97>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ gpio: pinctrl@11910000 {
++ compatible = "starfive,jh7100-pinctrl";
++ reg = <0x0 0x11910000 0x0 0x10000>,
++ <0x0 0x11858000 0x0 0x1000>;
++ reg-names = "gpio", "padctl";
++ clocks = <&clkgen JH7100_CLK_GPIO_APB>;
++ resets = <&rstgen JH7100_RSTN_GPIO_APB>;
++ interrupts = <32>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ uart2: serial@12430000 {
++ compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x12430000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_UART2_CORE>,
++ <&clkgen JH7100_CLK_UART2_APB>;
++ clock-names = "baudclk", "apb_pclk";
++ resets = <&rstgen JH7100_RSTN_UART2_APB>;
++ interrupts = <72>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
++ uart3: serial@12440000 {
++ compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x12440000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_UART3_CORE>,
++ <&clkgen JH7100_CLK_UART3_APB>;
++ clock-names = "baudclk", "apb_pclk";
++ resets = <&rstgen JH7100_RSTN_UART3_APB>;
++ interrupts = <73>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
++ i2c2: i2c@12450000 {
++ compatible = "snps,designware-i2c";
++ reg = <0x0 0x12450000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
++ <&clkgen JH7100_CLK_I2C2_APB>;
++ clock-names = "ref", "pclk";
++ resets = <&rstgen JH7100_RSTN_I2C2_APB>;
++ interrupts = <74>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c3: i2c@12460000 {
++ compatible = "snps,designware-i2c";
++ reg = <0x0 0x12460000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
++ <&clkgen JH7100_CLK_I2C3_APB>;
++ clock-names = "ref", "pclk";
++ resets = <&rstgen JH7100_RSTN_I2C3_APB>;
++ interrupts = <75>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ };
++};
+--
+2.30.2
+
--- /dev/null
+From a43676272a6e0b398781bc5337ca4cc187ba923d Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 10 Oct 2021 19:48:36 +0200
+Subject: [PATCH 16/16] RISC-V: Add BeagleV Starlight Beta device tree
+
+Add initial device tree for the BeagleV Starlight Beta board. About 300
+of these boards were sent out as part of a now cancelled BeagleBoard.org
+project.
+
+I2C timing data is based on the device tree in the vendor u-boot port.
+Heartbeat LED added by Geert.
+
+Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
+Co-developed-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/boot/dts/Makefile | 1 +
+ arch/riscv/boot/dts/starfive/Makefile | 2 +
+ .../dts/starfive/jh7100-beaglev-starlight.dts | 164 ++++++++++++++++++
+ 3 files changed, 167 insertions(+)
+ create mode 100644 arch/riscv/boot/dts/starfive/Makefile
+ create mode 100644 arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+
+diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
+index fe996b88319e..ff174996cdfd 100644
+--- a/arch/riscv/boot/dts/Makefile
++++ b/arch/riscv/boot/dts/Makefile
+@@ -1,5 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ subdir-y += sifive
++subdir-y += starfive
+ subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
+ subdir-y += microchip
+
+diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
+new file mode 100644
+index 000000000000..0ea1bc15ab30
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+new file mode 100644
+index 000000000000..c9af67f7a0d2
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+@@ -0,0 +1,164 @@
++// SPDX-License-Identifier: GPL-2.0 OR MIT
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++/dts-v1/;
++#include "jh7100.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/pinctrl-starfive.h>
++
++/ {
++ model = "BeagleV Starlight Beta";
++ compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
++
++ aliases {
++ serial0 = &uart3;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ cpus {
++ timebase-frequency = <6250000>;
++ };
++
++ memory@80000000 {
++ device_type = "memory";
++ reg = <0x0 0x80000000 0x2 0x0>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ led-ack {
++ gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_HEARTBEAT;
++ linux,default-trigger = "heartbeat";
++ label = "ack";
++ };
++ };
++};
++
++&gpio {
++ i2c0_pins: i2c0-0 {
++ i2c-pins {
++ pinmux = <GPIOMUX(62, GPO_LOW,
++ GPO_I2C0_PAD_SCK_OEN,
++ GPI_I2C0_PAD_SCK_IN)>,
++ <GPIOMUX(61, GPO_LOW,
++ GPO_I2C0_PAD_SDA_OEN,
++ GPI_I2C0_PAD_SDA_IN)>;
++ bias-disable; /* external pull-up */
++ input-enable;
++ input-schmitt-enable;
++ };
++ };
++
++ i2c1_pins: i2c1-0 {
++ i2c-pins {
++ pinmux = <GPIOMUX(47, GPO_LOW,
++ GPO_I2C1_PAD_SCK_OEN,
++ GPI_I2C1_PAD_SCK_IN)>,
++ <GPIOMUX(48, GPO_LOW,
++ GPO_I2C1_PAD_SDA_OEN,
++ GPI_I2C1_PAD_SDA_IN)>;
++ bias-pull-up;
++ input-enable;
++ input-schmitt-enable;
++ };
++ };
++
++ i2c2_pins: i2c2-0 {
++ i2c-pins {
++ pinmux = <GPIOMUX(60, GPO_LOW,
++ GPO_I2C2_PAD_SCK_OEN,
++ GPI_I2C2_PAD_SCK_IN)>,
++ <GPIOMUX(59, GPO_LOW,
++ GPO_I2C2_PAD_SDA_OEN,
++ GPI_I2C2_PAD_SDA_IN)>;
++ bias-disable; /* external pull-up */
++ input-enable;
++ input-schmitt-enable;
++ };
++ };
++
++ uart3_pins: uart3-0 {
++ rx-pins {
++ pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
++ GPI_UART3_PAD_SIN)>;
++ bias-pull-up;
++ drive-strength = <14>;
++ input-enable;
++ input-schmitt-enable;
++ slew-rate = <0>;
++ };
++ tx-pins {
++ pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
++ GPO_ENABLE, GPI_NONE)>;
++ bias-disable;
++ drive-strength = <35>;
++ input-disable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ };
++};
++
++&i2c0 {
++ clock-frequency = <100000>;
++ i2c-sda-hold-time-ns = <300>;
++ i2c-sda-falling-time-ns = <500>;
++ i2c-scl-falling-time-ns = <500>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0_pins>;
++ status = "okay";
++
++ pmic@5e {
++ compatible = "ti,tps65086";
++ reg = <0x5e>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ regulators {
++ };
++ };
++};
++
++&i2c1 {
++ clock-frequency = <400000>;
++ i2c-sda-hold-time-ns = <300>;
++ i2c-sda-falling-time-ns = <100>;
++ i2c-scl-falling-time-ns = <100>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1_pins>;
++ status = "okay";
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ i2c-sda-hold-time-ns = <300>;
++ i2c-sda-falling-time-ns = <500>;
++ i2c-scl-falling-time-ns = <500>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c2_pins>;
++ status = "okay";
++};
++
++&osc_sys {
++ clock-frequency = <25000000>;
++};
++
++&osc_aud {
++ clock-frequency = <27000000>;
++};
++
++&uart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart3_pins>;
++ status = "okay";
++};
+--
+2.30.2
+
--- /dev/null
+From 2a88bea858254873c675dcd1bbafefd5e17a387d Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Thu, 25 Nov 2021 14:21:18 +0100
+Subject: [PATCH 50/53] riscv: dts: starfive: Group tuples in interrupt
+ properties
+
+To improve human readability and enable automatic validation, the tuples
+in the various properties containing interrupt specifiers should be
+grouped.
+
+Fix this by grouping the tuples of "interrupts-extended" properties
+using angle brackets.
+
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+---
+ arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+index 69f22f9aad9d..d74fc29af642 100644
+--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -106,15 +106,15 @@ soc {
+ clint: clint@2000000 {
+ compatible = "starfive,jh7100-clint", "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0x10000>;
+- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+- &cpu1_intc 3 &cpu1_intc 7>;
++ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
++ <&cpu1_intc 3>, <&cpu1_intc 7>;
+ };
+
+ plic: interrupt-controller@c000000 {
+ compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+- interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
+- &cpu1_intc 11 &cpu1_intc 9>;
++ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
++ <&cpu1_intc 11>, <&cpu1_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+--
+2.30.2
+
--- /dev/null
+From ce4d791aa84319736eb4827b615f250f1be59274 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 20 Nov 2021 17:13:22 +0100
+Subject: [PATCH 51/53] RISC-V: Add StarFive JH7100 audio clock node
+
+Add device tree node for the audio clocks on the StarFive JH7100 RISC-V
+SoC.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+index d74fc29af642..31b4ccc282e0 100644
+--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -121,6 +121,16 @@ plic: interrupt-controller@c000000 {
+ riscv,ndev = <127>;
+ };
+
++ audclk: clock-controller@10480000 {
++ compatible = "starfive,jh7100-audclk";
++ reg = <0x0 0x10480000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
++ <&clkgen JH7100_CLK_AUDIO_12288>,
++ <&clkgen JH7100_CLK_DOM7AHB_BUS>;
++ clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
++ #clock-cells = <1>;
++ };
++
+ clkgen: clock-controller@11800000 {
+ compatible = "starfive,jh7100-clkgen";
+ reg = <0x0 0x11800000 0x0 0x10000>;
+--
+2.30.2
+
--- /dev/null
+From ecaf4b0c2e3fdd0f909f848ef2f252b021dd4d60 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sat, 20 Nov 2021 21:33:08 +0100
+Subject: [PATCH 52/53] RISC-V: Add StarFive JH7100 audio reset node
+
+Add device tree node for the audio resets on the StarFive JH7100 RISC-V
+SoC.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+---
+ arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+index 31b4ccc282e0..d76a67098620 100644
+--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -131,6 +131,12 @@ audclk: clock-controller@10480000 {
+ #clock-cells = <1>;
+ };
+
++ audrst: reset-controller@10490000 {
++ compatible = "starfive,jh7100-audrst";
++ reg = <0x0 0x10490000 0x0 0x10000>;
++ #reset-cells = <1>;
++ };
++
+ clkgen: clock-controller@11800000 {
+ compatible = "starfive,jh7100-clkgen";
+ reg = <0x0 0x11800000 0x0 0x10000>;
+--
+2.30.2
+
--- /dev/null
+From e712a44441571060b1b2ad011a1d76fe84fb1506 Mon Sep 17 00:00:00 2001
+From: Emil Renner Berthing <kernel@esmil.dk>
+Date: Sun, 31 Oct 2021 17:15:58 +0100
+Subject: [PATCH 53/53] riscv: dts: Add full JH7100, Starlight and VisionFive
+ support
+
+Based on the device tree in https://github.com/starfive-tech/u-boot/
+with contributions from:
+yanhong.wang <yanhong.wang@starfivetech.com>
+Huan.Feng <huan.feng@starfivetech.com>
+ke.zhu <ke.zhu@starfivetech.com>
+yiming.li <yiming.li@starfivetech.com>
+jack.zhu <jack.zhu@starfivetech.com>
+Samin Guo <samin.guo@starfivetech.com>
+Chenjieqin <Jessica.Chen@starfivetech.com>
+bo.li <bo.li@starfivetech.com>
+
+Rearranged, cleanups, fixes, pins and resets added by Emil.
+Cleanups, fixes, clocks added by Geert.
+Cleanups and GPIO fixes from Drew.
+Thermal zone added by Stephen.
+PWM pins added by Jianlong.
+
+Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Stephen L Arnold <nerdboy@gentoo.org>
+Signed-off-by: Drew Fustini <drew@beagleboard.org>
+Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
+---
+ arch/riscv/boot/dts/starfive/Makefile | 2 +-
+ .../starfive/jh7100-beaglev-starlight-a1.dts | 24 +
+ .../dts/starfive/jh7100-beaglev-starlight.dts | 154 +----
+ .../boot/dts/starfive/jh7100-common.dtsi | 586 ++++++++++++++++++
+ .../jh7100-starfive-visionfive-v1.dts | 32 +
+ arch/riscv/boot/dts/starfive/jh7100.dtsi | 559 +++++++++++++++++
+ 6 files changed, 1208 insertions(+), 149 deletions(-)
+ create mode 100644 arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
+ create mode 100644 arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+ create mode 100644 arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
+
+diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
+index 0ea1bc15ab30..058ea584aae4 100644
+--- a/arch/riscv/boot/dts/starfive/Makefile
++++ b/arch/riscv/boot/dts/starfive/Makefile
+@@ -1,2 +1,2 @@
+ # SPDX-License-Identifier: GPL-2.0
+-dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
++dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight-a1.dtb jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
+diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
+new file mode 100644
+index 000000000000..d307e44590f3
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
+@@ -0,0 +1,24 @@
++// SPDX-License-Identifier: GPL-2.0 OR MIT
++/*
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++/dts-v1/;
++#include "jh7100-common.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++ model = "BeagleV Starlight Beta A1";
++ compatible = "beagle,beaglev-starlight-jh7100-a1", "starfive,jh7100";
++
++ gpio-restart {
++ compatible = "gpio-restart";
++ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
++ priority = <224>;
++ };
++};
++
++&gpio {
++ /* don't reset gpio mux for serial console and reset gpio */
++ starfive,keep-gpiomux = <13 14 63>;
++};
+diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+index c9af67f7a0d2..ec42effa7a0e 100644
+--- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
++++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+@@ -1,164 +1,22 @@
+ // SPDX-License-Identifier: GPL-2.0 OR MIT
+ /*
+- * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+ /dts-v1/;
+-#include "jh7100.dtsi"
++#include "jh7100-common.dtsi"
+ #include <dt-bindings/gpio/gpio.h>
+-#include <dt-bindings/leds/common.h>
+-#include <dt-bindings/pinctrl/pinctrl-starfive.h>
+
+ / {
+ model = "BeagleV Starlight Beta";
+ compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
+-
+- aliases {
+- serial0 = &uart3;
+- };
+-
+- chosen {
+- stdout-path = "serial0:115200n8";
+- };
+-
+- cpus {
+- timebase-frequency = <6250000>;
+- };
+-
+- memory@80000000 {
+- device_type = "memory";
+- reg = <0x0 0x80000000 0x2 0x0>;
+- };
+-
+- leds {
+- compatible = "gpio-leds";
+-
+- led-ack {
+- gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
+- color = <LED_COLOR_ID_GREEN>;
+- function = LED_FUNCTION_HEARTBEAT;
+- linux,default-trigger = "heartbeat";
+- label = "ack";
+- };
+- };
+ };
+
+-&gpio {
+- i2c0_pins: i2c0-0 {
+- i2c-pins {
+- pinmux = <GPIOMUX(62, GPO_LOW,
+- GPO_I2C0_PAD_SCK_OEN,
+- GPI_I2C0_PAD_SCK_IN)>,
+- <GPIOMUX(61, GPO_LOW,
+- GPO_I2C0_PAD_SDA_OEN,
+- GPI_I2C0_PAD_SDA_IN)>;
+- bias-disable; /* external pull-up */
+- input-enable;
+- input-schmitt-enable;
+- };
+- };
+-
+- i2c1_pins: i2c1-0 {
+- i2c-pins {
+- pinmux = <GPIOMUX(47, GPO_LOW,
+- GPO_I2C1_PAD_SCK_OEN,
+- GPI_I2C1_PAD_SCK_IN)>,
+- <GPIOMUX(48, GPO_LOW,
+- GPO_I2C1_PAD_SDA_OEN,
+- GPI_I2C1_PAD_SDA_IN)>;
+- bias-pull-up;
+- input-enable;
+- input-schmitt-enable;
+- };
+- };
+-
+- i2c2_pins: i2c2-0 {
+- i2c-pins {
+- pinmux = <GPIOMUX(60, GPO_LOW,
+- GPO_I2C2_PAD_SCK_OEN,
+- GPI_I2C2_PAD_SCK_IN)>,
+- <GPIOMUX(59, GPO_LOW,
+- GPO_I2C2_PAD_SDA_OEN,
+- GPI_I2C2_PAD_SDA_IN)>;
+- bias-disable; /* external pull-up */
+- input-enable;
+- input-schmitt-enable;
+- };
+- };
+-
+- uart3_pins: uart3-0 {
+- rx-pins {
+- pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
+- GPI_UART3_PAD_SIN)>;
+- bias-pull-up;
+- drive-strength = <14>;
+- input-enable;
+- input-schmitt-enable;
+- slew-rate = <0>;
+- };
+- tx-pins {
+- pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
+- GPO_ENABLE, GPI_NONE)>;
+- bias-disable;
+- drive-strength = <35>;
+- input-disable;
+- input-schmitt-disable;
+- slew-rate = <0>;
+- };
+- };
++&gmac {
++ snps,reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
+ };
+
+-&i2c0 {
+- clock-frequency = <100000>;
+- i2c-sda-hold-time-ns = <300>;
+- i2c-sda-falling-time-ns = <500>;
+- i2c-scl-falling-time-ns = <500>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&i2c0_pins>;
+- status = "okay";
+-
+- pmic@5e {
+- compatible = "ti,tps65086";
+- reg = <0x5e>;
+- gpio-controller;
+- #gpio-cells = <2>;
+-
+- regulators {
+- };
+- };
+-};
+-
+-&i2c1 {
+- clock-frequency = <400000>;
+- i2c-sda-hold-time-ns = <300>;
+- i2c-sda-falling-time-ns = <100>;
+- i2c-scl-falling-time-ns = <100>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&i2c1_pins>;
+- status = "okay";
+-};
+-
+-&i2c2 {
+- clock-frequency = <100000>;
+- i2c-sda-hold-time-ns = <300>;
+- i2c-sda-falling-time-ns = <500>;
+- i2c-scl-falling-time-ns = <500>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&i2c2_pins>;
+- status = "okay";
+-};
+-
+-&osc_sys {
+- clock-frequency = <25000000>;
+-};
+-
+-&osc_aud {
+- clock-frequency = <27000000>;
+-};
+-
+-&uart3 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&uart3_pins>;
+- status = "okay";
++&gpio {
++ /* don't reset gpio mux for serial console on uart3 */
++ starfive,keep-gpiomux = <13 14>;
+ };
+diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+new file mode 100644
+index 000000000000..2a5c4a4c0810
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+@@ -0,0 +1,586 @@
++// SPDX-License-Identifier: GPL-2.0 OR MIT
++/*
++ * Copyright (C) 2021 StarFive Technology Co., Ltd.
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++/dts-v1/;
++#include "jh7100.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/pinctrl-starfive.h>
++
++/ {
++ aliases {
++ mshc0 = &sdio0;
++ mshc1 = &sdio1;
++ serial0 = &uart3;
++ serial1 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ cpus {
++ timebase-frequency = <6250000>;
++ };
++
++ memory@80000000 {
++ device_type = "memory";
++ reg = <0x0 0x80000000 0x2 0x0>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ led-ack {
++ gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_HEARTBEAT;
++ linux,default-trigger = "heartbeat";
++ label = "ack";
++ };
++ };
++
++ reserved-memory {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ linux,cma {
++ compatible = "shared-dma-pool";
++ reusable;
++ size = <0x0 0x28000000>;
++ alignment = <0x0 0x1000>;
++ alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
++ linux,cma-default;
++ };
++
++ jpu_reserved: framebuffer@c9000000 {
++ reg = <0x0 0xc9000000 0x0 0x4000000>;
++ };
++
++ nvdla_reserved: framebuffer@d0000000 {
++ no-map;
++ reg = <0x0 0xd0000000 0x0 0x28000000>;
++ };
++
++ vin_reserved: framebuffer@f9000000 {
++ compatible = "shared-dma-pool";
++ no-map;
++ reg = <0x0 0xf9000000 0x0 0x1000000>;
++ };
++
++ sffb_reserved: framebuffer@fb000000 {
++ compatible = "shared-dma-pool";
++ no-map;
++ reg = <0x0 0xfb000000 0x0 0x2000000>;
++ };
++ };
++
++ wifi_pwrseq: wifi-pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
++ };
++};
++
++&display {
++ memory-region = <&sffb_reserved>;
++ status = "okay";
++};
++
++&crtc {
++ ddr-format = <4>; //<WIN_FMT_RGB565>;
++ status = "okay";
++
++ port: port@0 {
++ reg = <0>;
++
++ crtc_0_out: endpoint {
++ remote-endpoint = <&hdmi_input0>;
++ };
++ };
++};
++
++&encoder {
++ encoder-type = <2>; // 2-TMDS, 3-LVDS, 6-DSI, 8-DPI
++ status = "okay";
++
++ ports {
++ port@0 {
++ hdmi_out: endpoint {
++ remote-endpoint = <&tda998x_0_input>;
++ };
++ };
++
++ port@1 {
++ hdmi_input0: endpoint {
++ remote-endpoint = <&crtc_0_out>;
++ };
++ };
++
++ };
++};
++
++&gmac {
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac_pins>;
++ status = "okay";
++};
++
++&gpio {
++ gmac_pins: gmac-0 {
++ gtxclk-pins {
++ pins = <PAD_FUNC_SHARE(115)>;
++ bias-pull-up;
++ drive-strength = <35>;
++ input-enable;
++ input-schmitt-enable;
++ slew-rate = <0>;
++ };
++ miitxclk-pins {
++ pins = <PAD_FUNC_SHARE(116)>;
++ bias-pull-up;
++ drive-strength = <14>;
++ input-enable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ tx-pins {
++ pins = <PAD_FUNC_SHARE(117)>,
++ <PAD_FUNC_SHARE(119)>,
++ <PAD_FUNC_SHARE(120)>,
++ <PAD_FUNC_SHARE(121)>,
++ <PAD_FUNC_SHARE(122)>,
++ <PAD_FUNC_SHARE(123)>,
++ <PAD_FUNC_SHARE(124)>,
++ <PAD_FUNC_SHARE(125)>,
++ <PAD_FUNC_SHARE(126)>;
++ bias-pull-up;
++ drive-strength = <35>;
++ input-disable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ rxclk-pins {
++ pins = <PAD_FUNC_SHARE(127)>;
++ bias-pull-up;
++ drive-strength = <14>;
++ input-enable;
++ input-schmitt-disable;
++ slew-rate = <6>;
++ };
++ rxer-pins {
++ pins = <PAD_FUNC_SHARE(129)>;
++ bias-pull-up;
++ drive-strength = <14>;
++ input-enable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ rx-pins {
++ pins = <PAD_FUNC_SHARE(128)>,
++ <PAD_FUNC_SHARE(130)>,
++ <PAD_FUNC_SHARE(131)>,
++ <PAD_FUNC_SHARE(132)>,
++ <PAD_FUNC_SHARE(133)>,
++ <PAD_FUNC_SHARE(134)>,
++ <PAD_FUNC_SHARE(135)>,
++ <PAD_FUNC_SHARE(136)>,
++ <PAD_FUNC_SHARE(137)>,
++ <PAD_FUNC_SHARE(138)>,
++ <PAD_FUNC_SHARE(139)>,
++ <PAD_FUNC_SHARE(140)>,
++ <PAD_FUNC_SHARE(141)>;
++ bias-pull-up;
++ drive-strength = <14>;
++ input-enable;
++ input-schmitt-enable;
++ slew-rate = <0>;
++ };
++ };
++
++ i2c0_pins: i2c0-0 {
++ i2c-pins {
++ pinmux = <GPIOMUX(62, GPO_LOW,
++ GPO_I2C0_PAD_SCK_OEN,
++ GPI_I2C0_PAD_SCK_IN)>,
++ <GPIOMUX(61, GPO_LOW,
++ GPO_I2C0_PAD_SDA_OEN,
++ GPI_I2C0_PAD_SDA_IN)>;
++ bias-disable; /* external pull-up */
++ input-enable;
++ input-schmitt-enable;
++ };
++ };
++
++ i2c1_pins: i2c1-0 {
++ i2c-pins {
++ pinmux = <GPIOMUX(47, GPO_LOW,
++ GPO_I2C1_PAD_SCK_OEN,
++ GPI_I2C1_PAD_SCK_IN)>,
++ <GPIOMUX(48, GPO_LOW,
++ GPO_I2C1_PAD_SDA_OEN,
++ GPI_I2C1_PAD_SDA_IN)>;
++ bias-pull-up;
++ input-enable;
++ input-schmitt-enable;
++ };
++ };
++
++ i2c2_pins: i2c2-0 {
++ i2c-pins {
++ pinmux = <GPIOMUX(60, GPO_LOW,
++ GPO_I2C2_PAD_SCK_OEN,
++ GPI_I2C2_PAD_SCK_IN)>,
++ <GPIOMUX(59, GPO_LOW,
++ GPO_I2C2_PAD_SDA_OEN,
++ GPI_I2C2_PAD_SDA_IN)>;
++ bias-disable; /* external pull-up */
++ input-enable;
++ input-schmitt-enable;
++ };
++ };
++
++ pwmdac_pins: pwmdac-0 {
++ pwmdac-pins {
++ pinmux = <GPIOMUX(23, GPO_PWMDAC_LEFT_OUT,
++ GPO_ENABLE, GPI_NONE)>,
++ <GPIOMUX(24, GPO_PWMDAC_RIGHT_OUT,
++ GPO_ENABLE, GPI_NONE)>;
++ bias-disable;
++ drive-strength = <35>;
++ input-disable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ };
++
++ pwm_pins: pwm-0 {
++ pwm-pins {
++ pinmux = <GPIOMUX(7,
++ GPO_PWM_PAD_OUT_BIT0,
++ GPO_PWM_PAD_OE_N_BIT0,
++ GPI_NONE)>,
++ <GPIOMUX(5,
++ GPO_PWM_PAD_OUT_BIT1,
++ GPO_PWM_PAD_OE_N_BIT1,
++ GPI_NONE)>;
++ bias-disable;
++ drive-strength = <35>;
++ input-disable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ };
++
++ sdio0_pins: sdio0-0 {
++ clk-pins {
++ pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
++ GPO_ENABLE, GPI_NONE)>;
++ bias-disable;
++ input-disable;
++ input-schmitt-disable;
++ };
++ sdio-pins {
++ pinmux = <GPIOMUX(55, GPO_LOW, GPO_DISABLE,
++ GPI_SDIO0_PAD_CARD_DETECT_N)>,
++ <GPIOMUX(53,
++ GPO_SDIO0_PAD_CCMD_OUT,
++ GPO_SDIO0_PAD_CCMD_OEN,
++ GPI_SDIO0_PAD_CCMD_IN)>,
++ <GPIOMUX(49,
++ GPO_SDIO0_PAD_CDATA_OUT_BIT0,
++ GPO_SDIO0_PAD_CDATA_OEN_BIT0,
++ GPI_SDIO0_PAD_CDATA_IN_BIT0)>,
++ <GPIOMUX(50,
++ GPO_SDIO0_PAD_CDATA_OUT_BIT1,
++ GPO_SDIO0_PAD_CDATA_OEN_BIT1,
++ GPI_SDIO0_PAD_CDATA_IN_BIT1)>,
++ <GPIOMUX(51,
++ GPO_SDIO0_PAD_CDATA_OUT_BIT2,
++ GPO_SDIO0_PAD_CDATA_OEN_BIT2,
++ GPI_SDIO0_PAD_CDATA_IN_BIT2)>,
++ <GPIOMUX(52,
++ GPO_SDIO0_PAD_CDATA_OUT_BIT3,
++ GPO_SDIO0_PAD_CDATA_OEN_BIT3,
++ GPI_SDIO0_PAD_CDATA_IN_BIT3)>;
++ bias-pull-up;
++ input-enable;
++ input-schmitt-enable;
++ };
++ };
++
++ sdio1_pins: sdio1-0 {
++ clk-pins {
++ pinmux = <GPIOMUX(33, GPO_SDIO1_PAD_CCLK_OUT,
++ GPO_ENABLE, GPI_NONE)>;
++ bias-disable;
++ input-disable;
++ input-schmitt-disable;
++ };
++ sdio-pins {
++ pinmux = <GPIOMUX(29,
++ GPO_SDIO1_PAD_CCMD_OUT,
++ GPO_SDIO1_PAD_CCMD_OEN,
++ GPI_SDIO1_PAD_CCMD_IN)>,
++ <GPIOMUX(36,
++ GPO_SDIO1_PAD_CDATA_OUT_BIT0,
++ GPO_SDIO1_PAD_CDATA_OEN_BIT0,
++ GPI_SDIO1_PAD_CDATA_IN_BIT0)>,
++ <GPIOMUX(30,
++ GPO_SDIO1_PAD_CDATA_OUT_BIT1,
++ GPO_SDIO1_PAD_CDATA_OEN_BIT1,
++ GPI_SDIO1_PAD_CDATA_IN_BIT1)>,
++ <GPIOMUX(34,
++ GPO_SDIO1_PAD_CDATA_OUT_BIT2,
++ GPO_SDIO1_PAD_CDATA_OEN_BIT2,
++ GPI_SDIO1_PAD_CDATA_IN_BIT2)>,
++ <GPIOMUX(31,
++ GPO_SDIO1_PAD_CDATA_OUT_BIT3,
++ GPO_SDIO1_PAD_CDATA_OEN_BIT3,
++ GPI_SDIO1_PAD_CDATA_IN_BIT3)>;
++ bias-pull-up;
++ input-enable;
++ input-schmitt-enable;
++ };
++ };
++
++ spi2_pins: spi2-0 {
++ mosi-pins {
++ pinmux = <GPIOMUX(18, GPO_SPI2_PAD_TXD,
++ GPO_ENABLE, GPI_NONE)>;
++ bias-disable;
++ input-disable;
++ input-schmitt-disable;
++ };
++ miso-pins {
++ pinmux = <GPIOMUX(16, GPO_LOW, GPO_DISABLE,
++ GPI_SPI2_PAD_RXD)>;
++ bias-pull-up;
++ input-enable;
++ input-schmitt-enable;
++ };
++ sck-pins {
++ pinmux = <GPIOMUX(12, GPO_SPI2_PAD_SCK_OUT,
++ GPO_ENABLE, GPI_NONE)>;
++ bias-disable;
++ input-disable;
++ input-schmitt-disable;
++ };
++ ss-pins {
++ pinmux = <GPIOMUX(15, GPO_SPI2_PAD_SS_0_N,
++ GPO_ENABLE, GPI_NONE)>,
++ <GPIOMUX(11, GPO_SPI2_PAD_SS_1_N,
++ GPO_ENABLE, GPI_NONE)>;
++ bias-disable;
++ input-disable;
++ input-schmitt-disable;
++ };
++ };
++
++ uart0_pins: uart0-0 {
++ rx-pins {
++ pinmux = <GPIOMUX(40, GPO_LOW, GPO_DISABLE,
++ GPI_UART0_PAD_SIN)>,
++ <GPIOMUX(39, GPO_LOW, GPO_DISABLE,
++ GPI_UART0_PAD_CTSN)>;
++ bias-pull-up;
++ drive-strength = <14>;
++ input-enable;
++ input-schmitt-enable;
++ };
++ tx-pins {
++ pinmux = <GPIOMUX(41, GPO_UART0_PAD_SOUT,
++ GPO_ENABLE, GPI_NONE)>,
++ <GPIOMUX(42, GPO_UART0_PAD_RTSN,
++ GPO_ENABLE, GPI_NONE)>;
++ bias-disable;
++ drive-strength = <35>;
++ input-disable;
++ input-schmitt-disable;
++ };
++ };
++
++ uart3_pins: uart3-0 {
++ rx-pins {
++ pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
++ GPI_UART3_PAD_SIN)>;
++ bias-pull-up;
++ drive-strength = <14>;
++ input-enable;
++ input-schmitt-enable;
++ slew-rate = <0>;
++ };
++ tx-pins {
++ pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
++ GPO_ENABLE, GPI_NONE)>;
++ bias-disable;
++ drive-strength = <35>;
++ input-disable;
++ input-schmitt-disable;
++ slew-rate = <0>;
++ };
++ };
++};
++
++&i2c0 {
++ clock-frequency = <100000>;
++ i2c-sda-hold-time-ns = <300>;
++ i2c-sda-falling-time-ns = <500>;
++ i2c-scl-falling-time-ns = <500>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0_pins>;
++ status = "okay";
++
++ pmic@5e {
++ compatible = "ti,tps65086";
++ reg = <0x5e>;
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ regulators {
++ };
++ };
++
++ tda998x@70 {
++ compatible = "nxp,tda998x";
++ reg = <0x70>;
++
++ port {
++ tda998x_0_input: endpoint {
++ remote-endpoint = <&hdmi_out>;
++ };
++ };
++ };
++};
++
++&i2c1 {
++ clock-frequency = <400000>;
++ i2c-sda-hold-time-ns = <300>;
++ i2c-sda-falling-time-ns = <100>;
++ i2c-scl-falling-time-ns = <100>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1_pins>;
++ status = "okay";
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ i2c-sda-hold-time-ns = <300>;
++ i2c-sda-falling-time-ns = <500>;
++ i2c-scl-falling-time-ns = <500>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c2_pins>;
++ status = "okay";
++};
++
++&osc_sys {
++ clock-frequency = <25000000>;
++};
++
++&osc_aud {
++ clock-frequency = <27000000>;
++};
++
++&ptc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm_pins>;
++ status = "okay";
++};
++
++&pwmdac {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwmdac_pins>;
++ status = "okay";
++};
++
++&qspi {
++ nor_flash: nor-flash@0 {
++ compatible = "spi-flash";
++ reg = <0>;
++ spi-max-frequency = <31250000>;
++ page-size = <256>;
++ block-size = <16>;
++ cdns,read-delay = <4>;
++ cdns,tshsl-ns = <1>;
++ cdns,tsd2d-ns = <1>;
++ cdns,tchsh-ns = <1>;
++ cdns,tslch-ns = <1>;
++ spi-tx-bus-width = <1>;
++ spi-rx-bus-width = <1>;
++ };
++
++ nand_flash: nand-flash@1 {
++ compatible = "spi-flash-nand";
++ reg = <1>;
++ spi-max-frequency = <31250000>;
++ page-size = <2048>;
++ block-size = <17>;
++ cdns,read-delay = <4>;
++ cdns,tshsl-ns = <1>;
++ cdns,tsd2d-ns = <1>;
++ cdns,tchsh-ns = <1>;
++ cdns,tslch-ns = <1>;
++ spi-tx-bus-width = <1>;
++ spi-rx-bus-width = <1>;
++ };
++};
++
++&sdio0 {
++ broken-cd;
++ bus-width = <4>;
++ cap-sd-highspeed;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdio0_pins>;
++ status = "okay";
++};
++
++&sdio1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ bus-width = <4>;
++ cap-sd-highspeed;
++ cap-sdio-irq;
++ cap-power-off-card;
++ mmc-pwrseq = <&wifi_pwrseq>;
++ non-removable;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdio1_pins>;
++ status = "okay";
++
++ wifi@1 {
++ compatible = "brcm,bcm4329-fmac";
++ reg = <1>;
++ };
++};
++
++&spi2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi2_pins>;
++ status = "okay";
++
++ spi_dev0: spi@0 {
++ compatible = "rohm,dh2228fv";
++ spi-max-frequency = <10000000>;
++ reg = <0>;
++ };
++};
++
++&uart0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0_pins>;
++ status = "okay";
++};
++
++&uart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart3_pins>;
++ status = "okay";
++};
++
++&usb3 {
++ dr_mode = "host";
++ status = "okay";
++};
+diff --git a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
+new file mode 100644
+index 000000000000..68616a1c9cf6
+--- /dev/null
++++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
+@@ -0,0 +1,32 @@
++// SPDX-License-Identifier: GPL-2.0 OR MIT
++/*
++ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
++ */
++
++/dts-v1/;
++#include "jh7100-common.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++ model = "StarFive VisionFive V1";
++ compatible = "starfive,visionfive-v1", "starfive,jh7100";
++
++ gpio-restart {
++ compatible = "gpio-restart";
++ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
++ priority = <224>;
++ };
++};
++
++&gpio {
++ /* don't reset gpio mux for serial console and reset gpio */
++ starfive,keep-gpiomux = <13 14 63>;
++};
++
++&i2c0 {
++ eeprom@50 {
++ compatible = "atmel,24c04";
++ reg = <0x50>;
++ pagesize = <16>;
++ };
++};
+diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+index d76a67098620..fab3611d135c 100644
+--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
+@@ -6,7 +6,9 @@
+
+ /dts-v1/;
+ #include <dt-bindings/clock/starfive-jh7100.h>
++#include <dt-bindings/clock/starfive-jh7100-audio.h>
+ #include <dt-bindings/reset/starfive-jh7100.h>
++#include <dt-bindings/reset/starfive-jh7100-audio.h>
+
+ / {
+ compatible = "starfive,jh7100";
+@@ -32,7 +34,9 @@ cpu@0 {
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
++ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
++ starfive,itim = <&itim0>;
+ tlb-split;
+
+ cpu0_intc: interrupt-controller {
+@@ -57,7 +61,9 @@ cpu@1 {
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
++ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc";
++ starfive,itim = <&itim1>;
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+@@ -103,6 +109,24 @@ soc {
+ #size-cells = <2>;
+ ranges;
+
++ dtim: dtim@1000000 {
++ compatible = "starfive,dtim0";
++ reg = <0x0 0x1000000 0x0 0x2000>;
++ reg-names = "mem";
++ };
++
++ itim0: itim@1808000 {
++ compatible = "starfive,itim0";
++ reg = <0x0 0x1808000 0x0 0x8000>;
++ reg-names = "mem";
++ };
++
++ itim1: itim@1820000 {
++ compatible = "starfive,itim0";
++ reg = <0x0 0x1820000 0x0 0x8000>;
++ reg-names = "mem";
++ };
++
+ clint: clint@2000000 {
+ compatible = "starfive,jh7100-clint", "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0x10000>;
+@@ -110,6 +134,20 @@ clint: clint@2000000 {
+ <&cpu1_intc 3>, <&cpu1_intc 7>;
+ };
+
++ ccache: cache-controller@2010000 {
++ compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
++ reg = <0x0 0x2010000 0x0 0x1000>,
++ <0x0 0x8000000 0x0 0x2000000>;
++ reg-names = "control", "sideband";
++ interrupts = <128>, <131>, <129>, <130>;
++ cache-block-size = <64>;
++ cache-level = <2>;
++ cache-sets = <2048>;
++ cache-size = <2097152>;
++ cache-unified;
++ /*next-level-cache = <&L40 &L36>;*/
++ };
++
+ plic: interrupt-controller@c000000 {
+ compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+@@ -121,6 +159,179 @@ plic: interrupt-controller@c000000 {
+ riscv,ndev = <127>;
+ };
+
++ sdio0: mmc@10000000 {
++ compatible = "snps,dw-mshc";
++ reg = <0x0 0x10000000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
++ <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
++ clock-names = "biu", "ciu";
++ interrupts = <4>;
++ data-addr = <0>;
++ fifo-depth = <32>;
++ fifo-watermark-aligned;
++ status = "disabled";
++ };
++
++ sdio1: mmc@10010000 {
++ compatible = "snps,dw-mshc";
++ reg = <0x0 0x10010000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
++ <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
++ clock-names = "biu", "ciu";
++ interrupts = <5>;
++ data-addr = <0>;
++ fifo-depth = <32>;
++ fifo-watermark-aligned;
++ status = "disabled";
++ };
++
++ /* gmac device configuration */
++ stmmac_axi_setup: stmmac-axi-config {
++ snps,wr_osr_lmt = <0xf>;
++ snps,rd_osr_lmt = <0xf>;
++ snps,blen = <256 128 64 32 0 0 0>;
++ };
++
++ gmac: ethernet@10020000 {
++ compatible = "snps,dwmac";
++ reg = <0x0 0x10020000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_GMAC_GTX>,
++ <&clkgen JH7100_CLK_GMAC_AHB>,
++ <&clkgen JH7100_CLK_GMAC_PTP_REF>;
++ clock-names = "stmmaceth", "pclk", "ptp_ref";
++ resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
++ reset-names = "ahb";
++ interrupts = <6>, <7>;
++ interrupt-names = "macirq", "eth_wake_irq";
++ max-frame-size = <9000>;
++ phy-mode = "rgmii-txid";
++ snps,multicast-filter-bins = <256>;
++ snps,perfect-filter-entries = <128>;
++ rx-fifo-depth = <32768>;
++ tx-fifo-depth = <16384>;
++ snps,axi-config = <&stmmac_axi_setup>;
++ snps,fixed-burst;
++ /*snps,force_sf_dma_mode;*/
++ snps,force_thresh_dma_mode;
++ snps,no-pbl-x8 = <1>;
++ status = "disabled";
++ };
++
++ dma2p: dma-controller@100b0000 {
++ compatible = "snps,axi-dma-1.01a";
++ reg = <0x0 0x100b0000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
++ <&clkgen JH7100_CLK_SGDMA2P_AHB>;
++ clock-names = "core-clk", "cfgr-clk";
++ interrupts = <2>;
++ #dma-cells = <1>;
++ dma-channels = <4>;
++ snps,dma-masters = <1>;
++ snps,data-width = <4>;
++ snps,block-size = <4096 4096 4096 4096>;
++ snps,priority = <0 1 2 3>;
++ snps,axi-max-burst-len = <128>;
++ dma-coherent;
++ };
++
++ crypto: crypto@100d0000 {
++ compatible = "starfive,vic-sec";
++ reg = <0x0 0x100d0000 0x0 0x20000>,
++ <0x0 0x11800234 0x0 0xc>;
++ reg-names = "secmem", "secclk";
++ clocks = <&clkgen JH7100_CLK_SEC_AHB>;
++ interrupts = <31>;
++ };
++
++ i2sadc0: i2sadc0@10400000 {
++ compatible = "snps,designware-i2sadc0";
++ reg = <0x0 0x10400000 0x0 0x1000>;
++ clocks = <&clkgen JH7100_CLK_APB1_BUS>;
++ clock-names = "i2sclk";
++ interrupt-parent = <&plic>;
++ #sound-dai-cells = <0>;
++ dmas = <&dma2p 28>;
++ dma-names = "rx";
++ };
++
++ i2svad: i2svad@10420000 {
++ compatible = "starfive,sf-i2svad";
++ reg = <0x0 0x10420000 0x0 0x1000> ;
++ clocks = <&audclk JH7100_AUDCLK_I2SVAD_APB>;
++ clock-names = "i2svad_apb";
++ resets = <&audrst JH7100_AUDRSTN_I2SVAD_APB>,
++ <&audrst JH7100_AUDRSTN_I2SVAD_SRST>;
++ reset-names = "apb_i2svad", "i2svad_srst";
++ interrupts = <60>, <61>;
++ interrupt-names = "spintr", "slintr";
++ #sound-dai-cells = <0>;
++ };
++
++ pwmdac: pwmdac@10440000 {
++ compatible = "starfive,pwmdac";
++ reg = <0x0 0x10440000 0x0 0x1000>;
++ clocks = <&clkgen JH7100_CLK_AUDIO_ROOT>,
++ <&clkgen JH7100_CLK_AUDIO_SRC>,
++ <&clkgen JH7100_CLK_AUDIO_12288>,
++ <&audclk JH7100_AUDCLK_DMA1P_AHB>,
++ <&audclk JH7100_AUDCLK_PWMDAC_APB>,
++ <&audclk JH7100_AUDCLK_DAC_MCLK>;
++ clock-names = "audio_root",
++ "audio_src",
++ "audio_12288",
++ "dma1p_ahb",
++ "pwmdac_apb",
++ "dac_mclk";
++ resets = <&audrst JH7100_AUDRSTN_APB_BUS>,
++ <&audrst JH7100_AUDRSTN_DMA1P_AHB>,
++ <&audrst JH7100_AUDRSTN_PWMDAC_APB>;
++ reset-names = "apb_bus", "dma1p_ahb", "apb_pwmdac";
++ dmas = <&dma2p 23>;
++ dma-names = "tx";
++ #sound-dai-cells = <0>;
++ };
++
++ i2sdac0: i2sdac0@10450000 {
++ compatible = "snps,designware-i2sdac0";
++ reg = <0x0 0x10450000 0x0 0x1000>;
++ clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
++ <&audclk JH7100_AUDCLK_I2SDAC_BCLK>,
++ <&audclk JH7100_AUDCLK_I2SDAC_LRCLK>,
++ <&audclk JH7100_AUDCLK_I2SDAC_APB>;
++ clock-names = "dac_mclk", "i2sdac0_bclk", "i2sdac0_lrclk", "i2sdac_apb";
++ resets = <&audrst JH7100_AUDRSTN_I2SDAC_APB>,
++ <&audrst JH7100_AUDRSTN_I2SDAC_SRST>;
++ reset-names = "apb_i2sdac", "i2sdac_srst";
++ #sound-dai-cells = <0>;
++ dmas = <&dma2p 30>;
++ dma-names = "tx";
++ };
++
++ i2sdac1: i2sdac1@10460000 {
++ compatible = "snps,designware-i2sdac1";
++ reg = <0x0 0x10460000 0x0 0x1000>;
++ clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
++ <&audclk JH7100_AUDCLK_I2S1_BCLK>,
++ <&audclk JH7100_AUDCLK_I2S1_LRCLK>,
++ <&audclk JH7100_AUDCLK_I2S1_APB>;
++ clock-names = "dac_mclk", "i2sdac1_bclk", "i2sdac1_lrclk", "i2s1_apb";
++ resets = <&audrst JH7100_AUDRSTN_I2S1_APB>,
++ <&audrst JH7100_AUDRSTN_I2S1_SRST>;
++ #sound-dai-cells = <0>;
++ dmas = <&dma2p 31>;
++ dma-names = "tx";
++ };
++
++ i2sdac16k: i2sdac16k@10470000 {
++ compatible = "snps,designware-i2sdac16k";
++ reg = <0x0 0x10470000 0x0 0x1000>;
++ clocks = <&clkgen JH7100_CLK_APB1_BUS>;
++ clock-names = "i2sclk";
++ #sound-dai-cells = <0>;
++ dmas = <&dma2p 29>;
++ dma-names = "tx";
++ };
++
+ audclk: clock-controller@10480000 {
+ compatible = "starfive,jh7100-audclk";
+ reg = <0x0 0x10480000 0x0 0x10000>;
+@@ -137,6 +348,79 @@ audrst: reset-controller@10490000 {
+ #reset-cells = <1>;
+ };
+
++ spdif_transmitter: spdif-transmitter {
++ compatible = "linux,spdif-dit";
++ #sound-dai-cells = <0>;
++ };
++
++ spdif_receiver: spdif-receiver {
++ compatible = "linux,spdif-dir";
++ #sound-dai-cells = <0>;
++ };
++
++ pwmdac_codec: pwmdac-transmitter {
++ compatible = "linux,pwmdac-dit";
++ #sound-dai-cells = <0>;
++ };
++
++ dmic_codec: dmic {
++ compatible = "dmic-codec";
++ #sound-dai-cells = <0>;
++ };
++
++ sound: snd-card {
++ compatible = "simple-audio-card";
++ simple-audio-card,name = "Starfive-Multi-Sound-Card";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ /* pwmdac */
++ simple-audio-card,dai-link@0 {
++ reg = <0>;
++ status = "okay";
++ format = "left_j";
++ bitclock-master = <&sndcpu0>;
++ frame-master = <&sndcpu0>;
++
++ sndcpu0: cpu {
++ sound-dai = <&pwmdac>;
++ };
++
++ codec {
++ sound-dai = <&pwmdac_codec>;
++ };
++ };
++ };
++
++ usb3: usb@104c0000 {
++ compatible = "cdns,usb3";
++ reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
++ <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
++ <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
++ reg-names = "otg", "xhci", "dev";
++ interrupts = <44>, <52>, <43>;
++ interrupt-names = "host", "peripheral", "otg";
++ phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
++ maximum-speed = "super-speed";
++ status = "disabled";
++ };
++
++ dma1p: dma-controller@10500000 {
++ compatible = "snps,axi-dma-1.01a";
++ reg = <0x0 0x10500000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
++ <&clkgen JH7100_CLK_SGDMA1P_BUS>;
++ clock-names = "core-clk", "cfgr-clk";
++ interrupts = <1>;
++ #dma-cells = <1>;
++ dma-channels = <16>;
++ snps,dma-masters = <1>;
++ snps,data-width = <3>;
++ snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
++ snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
++ snps,axi-max-burst-len = <64>;
++ };
++
+ clkgen: clock-controller@11800000 {
+ compatible = "starfive,jh7100-clkgen";
+ reg = <0x0 0x11800000 0x0 0x10000>;
+@@ -145,12 +429,88 @@ clkgen: clock-controller@11800000 {
+ #clock-cells = <1>;
+ };
+
++ otp: otp@11810000 {
++ compatible = "starfive,fu740-otp";
++ reg = <0x0 0x11810000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_OTP_APB>;
++ fuse-count = <0x200>;
++ };
++
+ rstgen: reset-controller@11840000 {
+ compatible = "starfive,jh7100-reset";
+ reg = <0x0 0x11840000 0x0 0x10000>;
+ #reset-cells = <1>;
+ };
+
++ qspi: spi@11860000 {
++ compatible = "cdns,qspi-nor";
++ reg = <0x0 0x11860000 0x0 0x10000>,
++ <0x0 0x20000000 0x0 0x20000000>;
++ clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
++ interrupts = <3>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ cdns,fifo-depth = <256>;
++ cdns,fifo-width = <4>;
++ cdns,trigger-address = <0x0>;
++ spi-max-frequency = <250000000>;
++ status = "disabled";
++ };
++
++ uart0: serial@11870000 {
++ compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
++ reg = <0x0 0x11870000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_UART0_CORE>,
++ <&clkgen JH7100_CLK_UART0_APB>;
++ clock-names = "baudclk", "apb_pclk";
++ resets = <&rstgen JH7100_RSTN_UART0_APB>;
++ interrupts = <92>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
++ uart1: serial@11880000 {
++ compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
++ reg = <0x0 0x11880000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_UART1_CORE>,
++ <&clkgen JH7100_CLK_UART1_APB>;
++ clock-names = "baudclk", "apb_pclk";
++ resets = <&rstgen JH7100_RSTN_UART1_APB>;
++ interrupts = <93>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
++ spi0: spi@11890000 {
++ compatible = "snps,dw-apb-ssi";
++ reg = <0x0 0x11890000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
++ <&clkgen JH7100_CLK_SPI0_APB>;
++ clock-names = "ssi_clk", "pclk";
++ resets = <&rstgen JH7100_RSTN_SPI0_APB>;
++ reset-names = "spi";
++ interrupts = <94>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ spi1: spi@118a0000 {
++ compatible = "snps,dw-apb-ssi";
++ reg = <0x0 0x118a0000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
++ <&clkgen JH7100_CLK_SPI1_APB>;
++ clock-names = "ssi_clk", "pclk";
++ resets = <&rstgen JH7100_RSTN_SPI1_APB>;
++ reset-names = "spi";
++ interrupts = <95>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
+ i2c0: i2c@118b0000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x118b0000 0x0 0x10000>;
+@@ -177,6 +537,41 @@ i2c1: i2c@118c0000 {
+ status = "disabled";
+ };
+
++ trng: trng@118d0000 {
++ compatible = "starfive,vic-rng";
++ reg = <0x0 0x118d0000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_TRNG_APB>;
++ interrupts = <98>;
++ };
++
++ vpu_enc: vpu_enc@118e0000 {
++ compatible = "cm,cm521-vpu";
++ reg = <0x0 0x118e0000 0x0 0x4000>;
++ reg-names = "control";
++ clocks = <&clkgen JH7100_CLK_VP6_CORE>;
++ clock-names = "vcodec";
++ interrupts = <26>;
++ };
++
++ vpu_dec: vpu_dec@118f0000 {
++ compatible = "c&m,cm511-vpu";
++ reg = <0 0x118f0000 0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_VP6_CORE>;
++ clock-names = "vcodec";
++ interrupts = <23>;
++ //memory-region = <&vpu_reserved>;
++ };
++
++ jpu: coadj12@11900000 {
++ compatible = "cm,codaj12-jpu-1";
++ reg = <0x0 0x11900000 0x0 0x300>;
++ reg-names = "control";
++ clocks = <&clkgen JH7100_CLK_JPEG_APB>;
++ clock-names = "jpege";
++ interrupts = <24>;
++ memory-region = <&jpu_reserved>;
++ };
++
+ gpio: pinctrl@11910000 {
+ compatible = "starfive,jh7100-pinctrl";
+ reg = <0x0 0x11910000 0x0 0x10000>,
+@@ -191,6 +586,86 @@ gpio: pinctrl@11910000 {
+ #interrupt-cells = <2>;
+ };
+
++ nvdla@11940000 {
++ compatible = "nvidia,nvdla_os_initial";
++ interrupts = <22>;
++ memory-region = <&nvdla_reserved>;
++ reg = <0x0 0x11940000 0x0 0x40000>;
++ status = "okay";
++ };
++
++ display: display-subsystem {
++ compatible = "starfive,display-subsystem";
++ dma-coherent;
++ status = "disabled";
++ };
++
++ encoder: display-encoder {
++ compatible = "starfive,display-encoder";
++ status = "disabled";
++ };
++
++ crtc: crtc@12000000 {
++ compatible = "starfive,jh7100-crtc";
++ reg = <0x0 0x12000000 0x0 0x10000>,
++ <0x0 0x12040000 0x0 0x10000>,
++ <0x0 0x12080000 0x0 0x10000>,
++ <0x0 0x120c0000 0x0 0x10000>,
++ <0x0 0x12240000 0x0 0x10000>,
++ <0x0 0x12250000 0x0 0x10000>,
++ <0x0 0x12260000 0x0 0x10000>;
++ reg-names = "lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
++ clocks = <&clkgen JH7100_CLK_DISP_AXI>, <&clkgen JH7100_CLK_VOUT_SRC>;
++ clock-names = "disp_axi", "vout_src";
++ resets = <&rstgen JH7100_RSTN_DISP_AXI>, <&rstgen JH7100_RSTN_VOUT_SRC>;
++ reset-names = "disp_axi", "vout_src";
++ interrupts = <101>, <103>;
++ interrupt-names = "lcdc_irq", "vpp1_irq";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ pp1 {
++ pp-id = <1>;
++ fifo-out;
++ //sys-bus-out;
++ src-format = <11>; //<COLOR_RGB565>;
++ src-width = <1920>;
++ src-height = <1080>;
++ dst-format = <7>; //<COLOR_RGB888_ARGB>;
++ dst-width = <1920>;
++ dst-height = <1080>;
++ };
++ };
++
++ spi2: spi@12410000 {
++ compatible = "snps,dw-apb-ssi";
++ reg = <0x0 0x12410000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
++ <&clkgen JH7100_CLK_SPI2_APB>;
++ clock-names = "ssi_clk", "pclk";
++ resets = <&rstgen JH7100_RSTN_SPI2_APB>;
++ reset-names = "spi";
++ interrupts = <70>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ spi3: spi@12420000 {
++ compatible = "snps,dw-apb-ssi";
++ reg = <0x0 0x12420000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
++ <&clkgen JH7100_CLK_SPI3_APB>;
++ clock-names = "ssi_clk", "pclk";
++ resets = <&rstgen JH7100_RSTN_SPI3_APB>;
++ reset-names = "spi";
++ interrupts = <71>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
+ uart2: serial@12430000 {
+ compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x12430000 0x0 0x10000>;
+@@ -242,5 +717,89 @@ i2c3: i2c@12460000 {
+ #size-cells = <0>;
+ status = "disabled";
+ };
++
++ watchdog@12480000 {
++ compatible = "starfive,si5-wdt";
++ reg = <0x0 0x12480000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_WDT_CORE>,
++ <&clkgen JH7100_CLK_WDTIMER_APB>;
++ clock-names = "wdt_coreclk", "wdtimer_apb";
++ resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
++ <&rstgen JH7100_RSTN_WDT>;
++ reset-names = "wdtimer_apb", "wdt";
++ interrupts = <80>;
++ };
++
++ ptc: pwm@12490000 {
++ compatible = "starfive,pwm0";
++ reg = <0x0 0x12490000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_PWM_APB>;
++ resets = <&rstgen JH7100_RSTN_PWM_APB>;
++ #pwm-cells = <3>;
++ sifive,npwm = <8>;
++ status = "disabled";
++ };
++
++ sfctemp: tmon@124a0000 {
++ compatible = "starfive,jh7100-temp";
++ reg = <0x0 0x124a0000 0x0 0x10000>;
++ clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
++ <&clkgen JH7100_CLK_TEMP_APB>;
++ clock-names = "sense", "bus";
++ resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
++ <&rstgen JH7100_RSTN_TEMP_APB>;
++ reset-names = "sense", "bus";
++ interrupts = <122>;
++ #thermal-sensor-cells = <0>;
++ };
++
++ thermal-zones {
++ cpu-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <15000>;
++
++ thermal-sensors = <&sfctemp>;
++
++ cooling-maps {
++ };
++
++ trips {
++ cpu_alert0: cpu_alert0 {
++ /* milliCelsius */
++ temperature = <75000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++
++ cpu_crit: cpu_crit {
++ /* milliCelsius */
++ temperature = <90000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++ };
++ };
++ };
++
++ xrp@f0000000 {
++ compatible = "cdns,xrp";
++ reg = <0x0 0xf0000000 0x0 0x01ffffff>,
++ <0x10 0x72000000 0x0 0x00001000>,
++ <0x10 0x72001000 0x0 0x00fff000>,
++ <0x0 0x124b0000 0x0 0x00010000>;
++ clocks = <&clkgen JH7100_CLK_VP6_CORE>;
++ interrupts = <27>, <28>;
++ firmware-name = "vp6_elf";
++ dsp-irq = <19 20>;
++ dsp-irq-src = <0x20 0x21>;
++ intc-irq-mode = <1>;
++ intc-irq = <0 1>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0x40000000 0x0 0x40000000 0x01000000>,
++ <0xb0000000 0x10 0x70000000 0x3000000>;
++ dsp@0 {
++ };
++ };
+ };
+ };
+--
+2.30.2
+
projects / openwrt / staging / hauke.git / commitdiff